use systemverilog 2012 for simulation

2022-11-19 18:41:25 -07:00
parent 8055444b99
commit 449efd3c3c
2 changed files with 5 additions and 5 deletions
--- a/tests/test_c/Makefile
+++ b/tests/test_c/Makefile
@@ -48,7 +48,7 @@ LDFLAGS = -melf32lriscv_ilp32
 	riscv64-linux-gnu-objcopy --target=verilog $< $@

 %.out: %.sv $(SOURCE_V)
-	iverilog -o $@ $^
+	iverilog -g2012 -o $@ $^

 %.vcd %.log: %.out %.hex
 	./$< | tee $(patsubst %.out, %.log, $<)