large restructure

This commit is contained in:
Brendan Haines 2021-08-11 00:18:46 -06:00
parent 6b0a72d516
commit 392e0a24ed
25 changed files with 158 additions and 281 deletions

2
.gitignore vendored
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@ -1 +1 @@
build *.~lock*

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@ -1,13 +1,16 @@
image: ubuntu image: ubuntu
stages: stages:
- install
- build - build
build-job: install-job:
stage: build stage: install
script: script:
- echo "Installing dependencies..." - echo "Installing dependencies..."
- apt update && apt install -y make iverilog gcc-8-riscv64-linux-gnu - apt update && apt install -y make iverilog gcc-8-riscv64-linux-gnu
- echo "Compiling the code..."
- make sim testbench:
- echo "Compile complete." stage: build
script:
- make -C testbench

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@ -1,63 +0,0 @@
BUILD_DIR = build
# ================
# Hardware options
# ================
# SOURCE_V = $(wildcard hdl/*.v)
# TESTBENCH_V = $(wildcard hdl/tb/*.v)
SOURCE_V = hdl/core.v
TESTBENCH_V = hdl/tb/core_tb.v
# ================
# Software options
# ================
# SOURCE_C = $(wildcard test/*.c)
SOURCE_C =
SOURCE_AS = $(wildcard test/*.S)
OBJ = $(addprefix $(BUILD_DIR)/, $(notdir $(SOURCE_AS:.S=.o)))
OBJ += $(addprefix $(BUILD_DIR)/, $(notdir $(SOURCE_C:.c=.o)))
CC = riscv64-linux-gnu-gcc-8
# CFLAGS = -march=rv32i -mabi=ilp32
CFLAGS = -march=rv64i -mabi=lp64
AS = riscv64-linux-gnu-as
ASFLAGS = $(CFLAGS)
LD = riscv64-linux-gnu-ld
LDFLAGS = -T
all: sim
## Hardware
$(BUILD_DIR)/tb.out: $(SOURCE_V) $(TESTBENCH_V) | $(BUILD_DIR)
iverilog $^ -o $@
## Software
$(BUILD_DIR)/%.o: test/%.S | $(BUILD_DIR)
$(AS) $(ASFLAGS) $^ -o $@
$(BUILD_DIR)/%.o: test/%.c | $(BUILD_DIR)
$(CC) $(CFLAGS) $^ -o $@
$(BUILD_DIR)/%.elf: test/%.ld $(OBJ) | $(BUILD_DIR)
$(LD) $(LDFLAGS) $^ -o $@
%.hex: %.elf
riscv64-linux-gnu-objcopy --target=verilog $< $@
$(BUILD_DIR)/core_tb.vcd: $(BUILD_DIR)/tb.out $(BUILD_DIR)/test.hex
cd $(BUILD_DIR) && ./tb.out | tee sim_log.txt
sim: $(BUILD_DIR)/core_tb.vcd
@grep -q "SUCCESS" $(BUILD_DIR)/sim_log.txt
## General
$(BUILD_DIR):
mkdir -p $(BUILD_DIR)
clean:
rm -rf $(BUILD_DIR)
.SECONDARY:
.PHONY: all clean sim

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hdl/.gitignore vendored
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*.out
*.vcd

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@ -1,203 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Sun Jul 4 02:57:58 2021
[*]
[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
[dumpfile_mtime] "Sun Jul 4 02:57:52 2021"
[dumpfile_size] 500611
[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
[timestart] 0
[size] 1920 1016
[pos] -1 -1
*-19.000000 3297000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] core_tb.
[treeopen] core_tb.dut.
[sst_width] 289
[signals_width] 277
[sst_expanded] 1
[sst_vpaned_height] 301
@200
-TB
@28
core_tb.clk
core_tb.reset
@200
-
@22
core_tb.mem_data_addr[31:0]
core_tb.mem_data_rdata[31:0]
@28
core_tb.mem_data_rvalid
@22
core_tb.mem_data_wdata[31:0]
@28
core_tb.mem_data_we
core_tb.mem_data_wready
@22
core_tb.mem_inst_addr[31:0]
core_tb.mem_inst_data[31:0]
@23
core_tb.\mem[2048][7:0]
@200
-
-DUT
@22
core_tb.dut.\regfile[0][31:0]
core_tb.dut.\regfile[1][31:0]
core_tb.dut.\regfile[2][31:0]
core_tb.dut.\regfile[3][31:0]
core_tb.dut.\regfile[4][31:0]
core_tb.dut.\regfile[5][31:0]
core_tb.dut.\regfile[6][31:0]
core_tb.dut.\regfile[7][31:0]
core_tb.dut.\regfile[8][31:0]
core_tb.dut.\regfile[9][31:0]
core_tb.dut.\regfile[10][31:0]
core_tb.dut.\regfile[11][31:0]
core_tb.dut.\regfile[12][31:0]
core_tb.dut.\regfile[13][31:0]
core_tb.dut.\regfile[14][31:0]
core_tb.dut.\regfile[15][31:0]
core_tb.dut.\regfile[16][31:0]
core_tb.dut.\regfile[17][31:0]
core_tb.dut.\regfile[18][31:0]
core_tb.dut.\regfile[19][31:0]
core_tb.dut.\regfile[20][31:0]
core_tb.dut.\regfile[21][31:0]
core_tb.dut.\regfile[22][31:0]
core_tb.dut.\regfile[23][31:0]
@c00022
core_tb.dut.\regfile[24][31:0]
@28
(0)core_tb.dut.\regfile[24][31:0]
(1)core_tb.dut.\regfile[24][31:0]
(2)core_tb.dut.\regfile[24][31:0]
(3)core_tb.dut.\regfile[24][31:0]
(4)core_tb.dut.\regfile[24][31:0]
(5)core_tb.dut.\regfile[24][31:0]
(6)core_tb.dut.\regfile[24][31:0]
(7)core_tb.dut.\regfile[24][31:0]
(8)core_tb.dut.\regfile[24][31:0]
(9)core_tb.dut.\regfile[24][31:0]
(10)core_tb.dut.\regfile[24][31:0]
(11)core_tb.dut.\regfile[24][31:0]
(12)core_tb.dut.\regfile[24][31:0]
(13)core_tb.dut.\regfile[24][31:0]
(14)core_tb.dut.\regfile[24][31:0]
(15)core_tb.dut.\regfile[24][31:0]
(16)core_tb.dut.\regfile[24][31:0]
(17)core_tb.dut.\regfile[24][31:0]
(18)core_tb.dut.\regfile[24][31:0]
(19)core_tb.dut.\regfile[24][31:0]
(20)core_tb.dut.\regfile[24][31:0]
(21)core_tb.dut.\regfile[24][31:0]
(22)core_tb.dut.\regfile[24][31:0]
(23)core_tb.dut.\regfile[24][31:0]
(24)core_tb.dut.\regfile[24][31:0]
(25)core_tb.dut.\regfile[24][31:0]
(26)core_tb.dut.\regfile[24][31:0]
(27)core_tb.dut.\regfile[24][31:0]
(28)core_tb.dut.\regfile[24][31:0]
(29)core_tb.dut.\regfile[24][31:0]
(30)core_tb.dut.\regfile[24][31:0]
(31)core_tb.dut.\regfile[24][31:0]
@1401200
-group_end
@22
core_tb.dut.\regfile[25][31:0]
core_tb.dut.\regfile[26][31:0]
core_tb.dut.\regfile[27][31:0]
core_tb.dut.\regfile[28][31:0]
core_tb.dut.\regfile[29][31:0]
core_tb.dut.\regfile[30][31:0]
core_tb.dut.\regfile[31][31:0]
@200
-
@c00022
core_tb.dut.r_if_pc[31:0]
@28
(0)core_tb.dut.r_if_pc[31:0]
(1)core_tb.dut.r_if_pc[31:0]
(2)core_tb.dut.r_if_pc[31:0]
(3)core_tb.dut.r_if_pc[31:0]
(4)core_tb.dut.r_if_pc[31:0]
(5)core_tb.dut.r_if_pc[31:0]
(6)core_tb.dut.r_if_pc[31:0]
(7)core_tb.dut.r_if_pc[31:0]
(8)core_tb.dut.r_if_pc[31:0]
(9)core_tb.dut.r_if_pc[31:0]
(10)core_tb.dut.r_if_pc[31:0]
(11)core_tb.dut.r_if_pc[31:0]
(12)core_tb.dut.r_if_pc[31:0]
(13)core_tb.dut.r_if_pc[31:0]
(14)core_tb.dut.r_if_pc[31:0]
(15)core_tb.dut.r_if_pc[31:0]
(16)core_tb.dut.r_if_pc[31:0]
(17)core_tb.dut.r_if_pc[31:0]
(18)core_tb.dut.r_if_pc[31:0]
(19)core_tb.dut.r_if_pc[31:0]
(20)core_tb.dut.r_if_pc[31:0]
(21)core_tb.dut.r_if_pc[31:0]
(22)core_tb.dut.r_if_pc[31:0]
(23)core_tb.dut.r_if_pc[31:0]
(24)core_tb.dut.r_if_pc[31:0]
(25)core_tb.dut.r_if_pc[31:0]
(26)core_tb.dut.r_if_pc[31:0]
(27)core_tb.dut.r_if_pc[31:0]
(28)core_tb.dut.r_if_pc[31:0]
(29)core_tb.dut.r_if_pc[31:0]
(30)core_tb.dut.r_if_pc[31:0]
(31)core_tb.dut.r_if_pc[31:0]
@1401200
-group_end
@200
-
@28
core_tb.dut.r_id_valid
@22
core_tb.dut.r_id_pc[31:0]
core_tb.dut.r_id_inst[31:0]
core_tb.dut.s_id_immed_btype[31:0]
core_tb.dut.s_id_immed_itype[31:0]
core_tb.dut.s_id_immed_jtype[31:0]
core_tb.dut.s_id_immed_stype[31:0]
core_tb.dut.s_id_immed_utype[31:0]
@200
-
@28
core_tb.dut.r_ex_valid
@22
core_tb.dut.r_ex_pc[31:0]
core_tb.dut.r_ex_inst[31:0]
@24
core_tb.dut.r_ex_rs1[4:0]
core_tb.dut.r_ex_rs2[4:0]
core_tb.dut.r_ex_rd[4:0]
@22
core_tb.dut.r_ex_s1[31:0]
core_tb.dut.r_ex_s2[31:0]
core_tb.dut.r_ex_aluop[3:0]
@28
core_tb.dut.r_ex_jump
core_tb.dut.r_ex_branch
core_tb.dut.r_ex_branch_pol
core_tb.dut.r_ex_load
core_tb.dut.r_ex_store
@200
-
@22
core_tb.dut.r_mem_pc[31:0]
core_tb.dut.r_mem_alu_out[31:0]
@28
core_tb.dut.r_mem_load
core_tb.dut.r_mem_store
@200
-
@22
core_tb.dut.r_wb_pc[31:0]
core_tb.dut.r_wb_alu_out[31:0]
core_tb.dut.r_wb_load_data[31:0]
@28
core_tb.dut.r_wb_load
[pattern_trace] 1
[pattern_trace] 0

1
test/.gitignore vendored
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@ -1 +0,0 @@
*.~lock*

3
testbench/.gitignore vendored Normal file
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@ -0,0 +1,3 @@
*.out
*.vcd
*.log

19
testbench/Makefile Normal file
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@ -0,0 +1,19 @@
all: verify
# BENCHES = $(filter-out common/, $(sort $(dir $(wildcard */))))
BENCHES = basic_test
$(info $$BENCHES is [${BENCHES}])
verify:
@for d in $(BENCHES); do \
make -C $d verify; \
done
clean:
@for d in $(BENCHES); do \
make -C $d clean; \
done
.SECONDARY:
.PHONY: all clean verify

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@ -0,0 +1,64 @@
all: verify
TESTBENCH_V = $(wildcard *tb.sv)
SOURCE_V = $(wildcard ../../src/*.v ../../src/*.sv)
SOURCE_V += $(wildcard ../common/*.v) $(wildcard ../common/*.sv)
LOGS = $(TESTBENCH_V:.sv=.log)
# SOURCE_C = $(wildcard *.c)
SOURCE_C =
SOURCE_AS = $(wildcard *.S)
OBJ = $(notdir $(SOURCE_AS:.S=.o))
OBJ += $(notdir $(SOURCE_C:.c=.o))
CC = riscv64-linux-gnu-gcc-8
# CFLAGS = -march=rv32i -mabi=ilp32
CFLAGS = -march=rv64i -mabi=lp64
CPPFLAGS =
AS = riscv64-linux-gnu-as
ASFLAGS = $(CFLAGS)
LD = riscv64-linux-gnu-ld
LDFLAGS = -T
# $(info $$TESTBENCH_V is [${TESTBENCH_V}])
# $(info $$SOURCE_V is [${SOURCE_V}])
# $(info $$LOGS is [${LOGS}])
# $(info $$SOURCE_C is [${SOURCE_C}])
# $(info $$SOURCE_AS is [${SOURCE_AS}])
# $(info $$OBJ is [${OBJ}])
%.o: %.S
$(AS) $(ASFLAGS) $^ -o $@
%.o: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) $^ -o $@
%.elf: %.ld $(OBJ)
$(LD) $(LDFLAGS) $^ -o $@
%.hex: %.elf
riscv64-linux-gnu-objcopy --target=verilog $< $@
%.out: %.sv $(SOURCE_V)
iverilog -o $@ $^
%.vcd %.log: %.out %.hex
./$< | tee $(patsubst %.out, %.log, $<)
verify: $(LOGS)
@echo "Checking log for \"ERROR:\"..."
@! grep "ERROR:" $^
@echo "Checking log for \"SUCCESS:\"..."
@grep "SUCCESS:" $^
clean:
rm -rf *.vcd *.log *.out *.hex
.SECONDARY: %.log %.vcd
.PHONY: all clean verify

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@ -1,14 +1,15 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module core_tb(); module tb();
localparam ADDR_FAILCODE = 32'h800; localparam ADDR_FAILCODE = 32'h800;
localparam WATCHDOG_MAX = 32'h00001000;
initial $timeformat(-9, 2, " ns", 20); initial $timeformat(-9, 2, " ns", 20);
initial begin: dump initial begin: dump
integer i; integer i;
$dumpfile("core_tb.vcd"); $dumpfile("tb.vcd");
$dumpvars(0, core_tb); $dumpvars(0, tb);
for (i=0; i<32; i=i+1) begin for (i=0; i<32; i=i+1) begin
$dumpvars(0, dut.regfile[i]); $dumpvars(0, dut.regfile[i]);
end end
@ -25,7 +26,7 @@ localparam DATA_INVALID = 32'hdeadbeef;
// Memory // Memory
reg [7:0] mem [0:MEM_LENGTH-1]; reg [7:0] mem [0:MEM_LENGTH-1];
initial $readmemh("test.hex", mem); initial $readmemh("tb.hex", mem);
// Instruction Memory // Instruction Memory
wire [31:0] mem_inst_addr; wire [31:0] mem_inst_addr;
@ -113,23 +114,34 @@ initial begin
$finish; $finish;
end end
integer watchdog = 0;
logic [31:0] returnval;
always @(posedge clk) begin always @(posedge clk) begin
#100 #100
case ({mem[ADDR_FAILCODE+3], mem[ADDR_FAILCODE+2], mem[ADDR_FAILCODE+1], mem[ADDR_FAILCODE+0]}) returnval = {mem[ADDR_FAILCODE+3], mem[ADDR_FAILCODE+2], mem[ADDR_FAILCODE+1], mem[ADDR_FAILCODE+0]};
case (returnval)
32'h00000000: begin 32'h00000000: begin
// Initial value // Initial value
end end
32'hffffffff: begin 32'hffffffff: begin
// Success // Success
#100
$display("%0t:\tSUCCESS: TEST PASSED", $time); $display("%0t:\tSUCCESS: TEST PASSED", $time);
$finish; $finish;
end end
default: begin default: begin
$display("%0t:\tERROR: FAILCODE = 0x%h", $time, {mem[ADDR_FAILCODE+3], mem[ADDR_FAILCODE+2], mem[ADDR_FAILCODE+1], mem[ADDR_FAILCODE+0]}); $display("%0t:\tERROR: FAILCODE = 0x%h", $time, returnval);
#200 #200
$finish; $finish;
end end
endcase endcase
watchdog = watchdog + 1;
if (watchdog > WATCHDOG_MAX) begin
$display("%0t:\tERROR: WATCHDOG", $time);
#200
$finish;
end
end end
always #2 clk = !clk; always #2 clk = !clk;

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@ -316,6 +316,7 @@ done:
addi x30, x30, 0xff # x31 = 0x00ffffff addi x30, x30, 0xff # x31 = 0x00ffffff
slli x30, x30, 8 # x31 = 0xffffff00 slli x30, x30, 8 # x31 = 0xffffff00
addi x30, x30, 0xff # x31 = 0xffffffff addi x30, x30, 0xff # x31 = 0xffffffff
# slli x30, x30, 1 # x31 = 0xfffffffe // this should cause a fail
nop nop
nop nop
nop nop
@ -338,6 +339,7 @@ done:
addi x5, x0, 1 # x5 = 1 addi x5, x0, 1 # x5 = 1
addi x6, x0, 1 # x6 = 1 addi x6, x0, 1 # x6 = 1
loop_init:
# counter and infinite loop # counter and infinite loop
addi x31, x0, 1 # x1 = 1 addi x31, x0, 1 # x1 = 1

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@ -0,0 +1,5 @@
module axi4_lite(
input wire aclk
);
endmodule

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@ -0,0 +1,38 @@
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Wed Aug 11 06:10:48 2021
[*]
[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/testbench/basic_test/tb.vcd"
[dumpfile_mtime] "Wed Aug 11 06:09:59 2021"
[dumpfile_size] 511500
[savefile] "/home/brendan/Documents/Projects/0039_cpu/testbench/testbench_tb.gtkw"
[timestart] 0
[size] 1920 1052
[pos] -1970 -28
*-20.000000 3402000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb.
[sst_width] 289
[signals_width] 277
[sst_expanded] 1
[sst_vpaned_height] 352
@28
tb.clk
tb.reset
@22
tb.mem_inst_addr[31:0]
tb.mem_inst_data[31:0]
tb.mem_data_addr[31:0]
tb.mem_data_rdata[31:0]
@28
tb.mem_data_rvalid
@22
tb.mem_data_wdata[31:0]
tb.mem_data_wmask[3:0]
@28
tb.mem_data_we
tb.mem_data_wready
@22
tb.returnval[31:0]
tb.dut.\regfile[31][31:0]
[pattern_trace] 1
[pattern_trace] 0