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https://gitlab.com/brendanhaines/cpu.git
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shift to iverilog + gtkwave for simulation
This commit is contained in:
parent
82283f01f4
commit
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187
Makefile
187
Makefile
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@ -1,187 +0,0 @@
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###########################################################################
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## Xilinx ISE Makefile
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##
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## To the extent possible under law, the author(s) have dedicated all copyright
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## and related and neighboring rights to this software to the public domain
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## worldwide. This software is distributed without any warranty.
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###########################################################################
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include project.cfg
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###########################################################################
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# Default values
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###########################################################################
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ifndef XILINX
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$(error XILINX must be defined)
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endif
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ifndef PROJECT
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$(error PROJECT must be defined)
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endif
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ifndef TARGET_PART
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$(error TARGET_PART must be defined)
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endif
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TOPLEVEL ?= $(PROJECT)
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CONSTRAINTS ?= $(PROJECT).ucf
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BITFILE ?= build/$(PROJECT).bit
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COMMON_OPTS ?= -intstyle xflow
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XST_OPTS ?=
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NGDBUILD_OPTS ?=
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MAP_OPTS ?=
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PAR_OPTS ?=
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BITGEN_OPTS ?=
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TRACE_OPTS ?=
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FUSE_OPTS ?= -incremental
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PROGRAMMER ?= none
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IMPACT_OPTS ?= -batch impact.cmd
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DJTG_EXE ?= djtgcfg
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DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
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DJTG_INDEX ?= 0
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XC3SPROG_EXE ?= xc3sprog
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XC3SPROG_CABLE ?= none
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XC3SPROG_OPTS ?=
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###########################################################################
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# Internal variables, platform-specific definitions, and macros
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###########################################################################
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ifeq ($(OS),Windows_NT)
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XILINX := $(shell cygpath -m $(XILINX))
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CYG_XILINX := $(shell cygpath $(XILINX))
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EXE := .exe
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XILINX_PLATFORM ?= nt64
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PATH := $(PATH):$(CYG_XILINX)/bin/$(XILINX_PLATFORM)
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else
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EXE :=
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XILINX_PLATFORM ?= lin64
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PATH := $(PATH):$(XILINX)/bin/$(XILINX_PLATFORM)
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endif
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TEST_NAMES = $(foreach file,$(VTEST) $(VHDTEST),$(basename $(file)))
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TEST_EXES = $(foreach test,$(TEST_NAMES),build/isim_$(test)$(EXE))
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RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
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cd build && $(XILINX)/bin/$(XILINX_PLATFORM)/$(1)
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# isim executables don't work without this
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export XILINX
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###########################################################################
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# Default build
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###########################################################################
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default: $(BITFILE)
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clean:
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rm -rf build
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build/$(PROJECT).prj: project.cfg
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@echo "Updating $@"
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@mkdir -p build
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@rm -f $@
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@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;)
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@$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;)
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build/$(PROJECT)_sim.prj: build/$(PROJECT).prj
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@cp build/$(PROJECT).prj $@
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@$(foreach file,$(VTEST),echo "verilog work \"../$(file)\"" >> $@;)
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@$(foreach file,$(VHDTEST),echo "vhdl work \"../$(file)\"" >> $@;)
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@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
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build/$(PROJECT).scr: project.cfg
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@echo "Updating $@"
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@mkdir -p build
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@rm -f $@
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@echo "run" \
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"-ifn $(PROJECT).prj" \
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"-ofn $(PROJECT).ngc" \
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"-ifmt mixed" \
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"$(XST_OPTS)" \
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"-top $(TOPLEVEL)" \
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"-ofmt NGC" \
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"-p $(TARGET_PART)" \
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> build/$(PROJECT).scr
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$(BITFILE): project.cfg $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
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@mkdir -p build
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$(call RUN,xst) $(COMMON_OPTS) \
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-ifn $(PROJECT).scr
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$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
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-p $(TARGET_PART) -uc ../$(CONSTRAINTS) \
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$(PROJECT).ngc $(PROJECT).ngd
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$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
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-p $(TARGET_PART) \
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-w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
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$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
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-w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
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$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
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-w $(PROJECT).ncd $(PROJECT).bit
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@echo -ne "\e[1;32m======== OK ========\e[m\n"
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###########################################################################
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# Testing (work in progress)
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###########################################################################
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trace: project.cfg $(BITFILE)
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$(call RUN,trce) $(COMMON_OPTS) $(TRACE_OPTS) \
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$(PROJECT).ncd $(PROJECT).pcf
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test: $(TEST_EXES)
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build/isim_%$(EXE): build/$(PROJECT)_sim.prj $(VSOURCE) $(VHDSOURCE) $(VTEST) $(VHDTEST)
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$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
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-prj $(PROJECT)_sim.prj \
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-o isim_$*$(EXE) \
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work.$* work.glbl
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isim: build/isim_$(TB)$(EXE)
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@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd
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@echo "run all" >> build/isim_$(TB).cmd
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cd build ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
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isimgui: build/isim_$(TB)$(EXE)
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@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd
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@echo "run all" >> build/isim_$(TB).cmd
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cd build ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
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###########################################################################
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# Programming
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###########################################################################
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ifeq ($(PROGRAMMER), impact)
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prog: $(BITFILE)
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$(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
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endif
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ifeq ($(PROGRAMMER), digilent)
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prog: $(BITFILE)
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$(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), xc3sprog)
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prog: $(BITFILE)
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$(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), none)
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prog:
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$(error PROGRAMMER must be set to use 'make prog')
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endif
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###########################################################################
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# vim: set filetype=make: #
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2
hdl/.gitignore
vendored
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2
hdl/.gitignore
vendored
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@ -0,0 +1,2 @@
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*.out
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*.vcd
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19
hdl/Makefile
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19
hdl/Makefile
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# SOURCE_V = $(wildcard *.v)
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# TESTBENCH_V = $(wildcard tb/*.v)
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SOURCE_V = core.v
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TESTBENCH_V = tb/core_tb.v
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all: sim
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tb.out: $(SOURCE_V) $(TESTBENCH_V)
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iverilog $^ -o $@
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sim: tb.out
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./tb.out
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clean:
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rm -rf tb.out tb.vcd
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.SECONDARY:
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.PHONY: all clean sim
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22
hdl/tb/core_tb.gtkw
Normal file
22
hdl/tb/core_tb.gtkw
Normal file
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@ -0,0 +1,22 @@
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Fri Jul 2 06:48:14 2021
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[*]
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[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/hdl/core_tb.vcd"
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[dumpfile_mtime] "Fri Jul 2 06:46:26 2021"
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[dumpfile_size] 667859
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[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
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[timestart] 0
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[size] 1871 1025
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[pos] -1900 -2
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*0.000000 2 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] core_tb.
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[sst_width] 289
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[signals_width] 199
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[sst_expanded] 1
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[sst_vpaned_height] 301
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@28
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core_tb.clk
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core_tb.reset
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[pattern_trace] 1
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[pattern_trace] 0
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`timescale 500 ps / 1 ps
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`timescale 1ns/1ps
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module core_tb();
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module core_tb();
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initial $timeformat(-9, 2, " ns", 20);
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initial $timeformat(-9, 2, " ns", 20);
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initial begin
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$dumpfile("core_tb.vcd");
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$dumpvars(0);
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end
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wire dummy_out;
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wire dummy_out;
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@ -57,7 +61,7 @@ initial begin
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#5000
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#5000
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reset = 1;
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reset = 1;
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$stop;
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$finish;
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end
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end
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always #2 clk = !clk;
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always #2 clk = !clk;
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