shift to iverilog + gtkwave for simulation

2021-07-02 00:49:13 -06:00
parent 82283f01f4
commit 180f05fb0a
5 changed files with 49 additions and 189 deletions
--- a/hdl/Makefile
+++ b/hdl/Makefile
@@ -0,0 +1,19 @@
+# SOURCE_V = $(wildcard *.v)
+# TESTBENCH_V = $(wildcard tb/*.v)
+
+SOURCE_V = core.v
+TESTBENCH_V = tb/core_tb.v
+
+all: sim
+
+tb.out: $(SOURCE_V) $(TESTBENCH_V)
+	iverilog $^ -o $@
+
+sim: tb.out
+	./tb.out
+
+clean:
+	rm -rf tb.out tb.vcd
+
+.SECONDARY:
+.PHONY: all clean sim