shift to iverilog + gtkwave for simulation

hdl/.gitignore

@@ -0,0 +1,2 @@
+*.out
+*.vcd

hdl/Makefile

@@ -0,0 +1,19 @@
+# SOURCE_V = $(wildcard *.v)
+# TESTBENCH_V = $(wildcard tb/*.v)
+
+SOURCE_V = core.v
+TESTBENCH_V = tb/core_tb.v
+
+all: sim
+
+tb.out: $(SOURCE_V) $(TESTBENCH_V)
+	iverilog $^ -o $@
+
+sim: tb.out
+	./tb.out
+
+clean:
+	rm -rf tb.out tb.vcd
+
+.SECONDARY:
+.PHONY: all clean sim

hdl/tb/core_tb.gtkw

@@ -0,0 +1,22 @@
+[*]
+[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
+[*] Fri Jul  2 06:48:14 2021
+[*]
+[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/hdl/core_tb.vcd"
+[dumpfile_mtime] "Fri Jul  2 06:46:26 2021"
+[dumpfile_size] 667859
+[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
+[timestart] 0
+[size] 1871 1025
+[pos] -1900 -2
+*0.000000 2 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] core_tb.
+[sst_width] 289
+[signals_width] 199
+[sst_expanded] 1
+[sst_vpaned_height] 301
+@28
+core_tb.clk
+core_tb.reset
+[pattern_trace] 1
+[pattern_trace] 0

hdl/tb/core_tb.v

@@ -1,8 +1,12 @@
-`timescale 500 ps / 1 ps 
+`timescale 1ns/1ps
 
 module core_tb();
 
 initial $timeformat(-9, 2, " ns", 20);
+initial begin
+    $dumpfile("core_tb.vcd");
+    $dumpvars(0);
+end
 
 wire dummy_out;
 
@@ -57,7 +61,7 @@ initial begin
     
     #5000
     reset = 1;
-    $stop;
+    $finish;
 end
 
 always #2 clk  = !clk;