cpu/README.md

![pipeline status](https://gitlab.com/brendanhaines/0039_cpu/badges/master/pipeline.svg)

# RISC-V CPU

Harvard architecture

Desired features:
* 1- or 5-stage pipeline selectable via parameter
* AXI-lite Master for both instruction and data memory
* 32, 64, or 128 bit word size
* floating point support
* multiplication
* division
* instruction and data caches
add pipeline status to README.md 2021-08-11 00:28:00 -06:00			`![pipeline status](https://gitlab.com/brendanhaines/0039_cpu/badges/master/pipeline.svg)`

Add README.md 2021-05-03 22:47:58 -06:00			`# RISC-V CPU`

			`Harvard architecture`

			`Desired features:`
			`* 1- or 5-stage pipeline selectable via parameter`
			`* AXI-lite Master for both instruction and data memory`
			`* 32, 64, or 128 bit word size`
			`* floating point support`
			`* multiplication`
			`* division`
			`* instruction and data caches`