cpu/other_projects/test.sv

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227 B
Systemverilog
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2021-05-03 22:13:26 -06:00
interface test_if();
parameter int DW = 32;
logic[DW-1:0] data;
modport consumer (
input data
);
endinterface
module test_mod(
test_if.consumer if_in,
output[31:0] dout
);
assign dout = if_in.data;
endmodule