246 lines
8.3 KiB
Python
Executable File
246 lines
8.3 KiB
Python
Executable File
import os
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import zipfile
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from datetime import datetime
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from pathlib import Path
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import pcbnew
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__all__ = ["FabOutputs"]
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class FabOutputs(pcbnew.ActionPlugin):
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def defaults(self):
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self.name = "Generate Outputs"
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self.category = "Output Generation"
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self.description = "Generate Gerbers, BOM, Drawings, etc and add to pdf/zip"
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self.show_toolbar_button = True
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self.icon_file_name = os.path.join(os.path.dirname(__file__), "icon.png")
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def Run(self):
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# ================
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# General Data
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# ================
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now = datetime.now()
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pcb = pcbnew.GetBoard()
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path_cwd = Path.cwd()
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path_pcb = Path(pcb.GetFileName())
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dir_pcb = path_pcb.parent
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dir_fab = dir_pcb / "FabricationOutputs"
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dir_asy = dir_pcb / "AssemblyOutputs"
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project_name = path_pcb.stem
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part_number = pcb.GetTitleBlock().GetTitle()
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rev = str.upper(pcb.GetTitleBlock().GetRevision())
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suffix = ""
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if rev != "":
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suffix += f"_REV{rev}"
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suffix += f"_{now.strftime('%Y%m%d_%H%M%S')}"
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layer_count = pcb.GetDesignSettings().GetCopperLayerCount()
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layer_info = [
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("Front Paste", "gtp", pcbnew.F_Paste),
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("Front Silkscreen", "gto", pcbnew.F_SilkS),
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("Front Mask", "gts", pcbnew.F_Mask),
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("Front Copper", "gtl", pcbnew.F_Cu),
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*[
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(f"Inner Layer {layer} Copper", f"g{layer}", layer)
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for layer in range(1, layer_count - 1)
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],
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("Back Copper", "gbl", pcbnew.B_Cu),
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("Back Mask", "gbs", pcbnew.B_Mask),
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("Back SilkScreen", "gbo", pcbnew.B_SilkS),
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("Back Paste", "gbp", pcbnew.B_Paste),
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("Edges Cuts", "gm1", pcbnew.Edge_Cuts),
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("Drill", "drl", None),
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]
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stackup = [
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# [pcbnew layer, file extension, thickness, comment]
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[pcbnew.F_Paste, "gtp", None, "SN63/PB37"],
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[pcbnew.F_SilkS, "gto", None, "White"],
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[pcbnew.F_Mask, "gts", 1, "Explicit mask material"],
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[None, None, None, "ENIG"],
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[pcbnew.F_Cu, "gtl", 2.1, "copper roughness"],
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[None, None, 10, "Dielectric stuff"],
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[1, "g1", 0.7, "Copper roughness"],
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[None, None, 24, "Dielectric stuff"],
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[None, None, 12, "Dielectric stuff"],
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[2, "g2", 0.7, "Copper roughness"],
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[None, None, 10, "Dielectric stuff"],
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[pcbnew.B_Cu, "gbl", 2.1, "copper roughness"],
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[None, None, None, "ENIG"],
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[pcbnew.B_Mask, "gbs", 1, "Explicit mask material"],
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[pcbnew.B_SilkS, "gbo", None, "White"],
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[pcbnew.B_Paste, "gbp", None, "SN63/PB37"],
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]
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board_features = {
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"core cap": True,
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"castellated": False,
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"plated board edge": False,
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"copper finish": "ENIG",
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"hard gold": False,
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"bevelled edge": False,
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"soldermask defined": None, # TODO: how do I want to determine this?
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}
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dir_fab.mkdir(parents=True, exist_ok=True)
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dir_asy.mkdir(parents=True, exist_ok=True)
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files_fab = []
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files_asy = []
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# ================
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# Gerbers
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# ================
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#### SETTINGS
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tent_vias = True
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trim_silkscreen = False
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plot_controller = pcbnew.PLOT_CONTROLLER(pcb)
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plot_options = plot_controller.GetPlotOptions()
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# Set General Options:
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# plot_options.Format()
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plot_options.SetOutputDirectory(dir_fab)
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plot_options.SetPlotFrameRef(False)
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plot_options.SetPlotValue(False)
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plot_options.SetPlotReference(True)
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plot_options.SetPlotInvisibleText(False)
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plot_options.SetPlotViaOnMaskLayer(not tent_vias)
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plot_options.SetExcludeEdgeLayer(True)
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plot_options.SetUseAuxOrigin(False)
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plot_options.SetMirror(False)
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plot_options.SetNegative(False)
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plot_options.SetScale(1)
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# plot_options.SetAutoScale(True)
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# plot_options.SetPlotMode(PLOT_MODE)
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# plot_options.SetLineWidth(pcbnew.FromMM(PLOT_LINE_WIDTH))
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plot_options.SetUseGerberAttributes(True)
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plot_options.SetUseGerberProtelExtensions(False)
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plot_options.SetCreateGerberJobFile(False)
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plot_options.SetIncludeGerberNetlistInfo(False)
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plot_options.SetUseGerberX2format(True)
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# plot_options.SetDrillMarksType()
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plot_options.SetSubtractMaskFromSilk(trim_silkscreen)
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plot_plan = [
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# ( layer ID, file extension, description)
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(pcbnew.F_Paste, "gtp", "Front Paste"),
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(pcbnew.F_SilkS, "gto", "Front SilkScreen"),
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(pcbnew.F_Mask, "gts", "Front Mask"),
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(pcbnew.F_Cu, "gtl", "Front Copper"),
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*[
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(layer, f"g{layer}", f"Inner Layer {layer} Copper")
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for layer in range(1, layer_count - 1)
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],
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(pcbnew.B_Cu, "gbl", "Back Copper"),
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(pcbnew.B_Mask, "gbs", "Back Mask"),
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(pcbnew.B_SilkS, "gbo", "Back SilkScreen"),
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(pcbnew.B_Paste, "gbp", "Back Paste"),
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(pcbnew.Edge_Cuts, "gm1", "Edges Cuts"),
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]
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for layer_info in plot_plan:
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plot_controller.SetLayer(layer_info[0])
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plot_controller.OpenPlotfile("", pcbnew.PLOT_FORMAT_GERBER, layer_info[2])
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plot_controller.PlotLayer()
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fname = f"{project_name}{suffix}.{layer_info[1]}"
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os.rename(dir_fab / f"{project_name}.gbr", dir_fab / fname)
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files_fab.append(fname)
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plot_controller.ClosePlot()
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# ================
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# Drill Files
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# ================
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METRIC = True
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ZERO_FORMAT = pcbnew.GENDRILL_WRITER_BASE.DECIMAL_FORMAT
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INTEGER_DIGITS = 3
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MANTISSA_DIGITS = 3
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MIRROR_Y_AXIS = False
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HEADER = True
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OFFSET = pcbnew.wxPoint(0, 0)
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MERGE_PTH_NPTH = True
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DRILL_FILE = True
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MAP_FILE = False
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REPORTER = None
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drill_writer = pcbnew.EXCELLON_WRITER(pcb)
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drill_writer.SetFormat(METRIC, ZERO_FORMAT, INTEGER_DIGITS, MANTISSA_DIGITS)
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drill_writer.SetOptions(MIRROR_Y_AXIS, HEADER, OFFSET, MERGE_PTH_NPTH)
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drill_writer.CreateDrillandMapFilesSet(
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str(dir_fab), DRILL_FILE, MAP_FILE, REPORTER
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)
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fname = f"{project_name}{suffix}.drl"
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os.rename(dir_fab / f"{project_name}.drl", dir_fab / fname)
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files_fab.append(fname)
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# ================
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# Drawing
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# ================
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# TODO
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# ================
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# BOM
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# ================
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# TODO
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# ================
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# Pick and Place
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# ================
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# TODO
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# ================
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# Fab Notes
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# ================
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# fname = f"README_FABRICATION{suffix}.TXT"
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# with open(dir_fab / fname, "w") as f:
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# f.write(f"{project_name}-REV{rev}\n")
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# f.write(f"Layer Order\n")
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# # for layer in plot_plan:
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# files_fab.append(fname)
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# ================
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# Assembly Notes
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# ================
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# fname = f"README_ASSEMBLY{suffix}.TXT"
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# with open(dir_asy / fname, "w") as f:
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# f.write(f"{project_name}-REV{rev}\n")
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# files_asy.append(fname)
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# ================
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# Zip
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# ================
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with zipfile.ZipFile(
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dir_fab / f"{project_name}{suffix}_fabrication.zip", "w"
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) as z:
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for fname in files_fab:
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z.write(dir_fab / fname, arcname=fname)
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with zipfile.ZipFile(
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dir_asy / f"{project_name}{suffix}_assembly.zip", "w"
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) as z:
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for fname in files_fab:
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z.write(dir_fab / fname, arcname=Path("fabrication") / fname)
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for fname in files_asy:
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z.write(dir_asy / fname, arcname=fname)
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# dir_archive = dir_pcb / "Archive"
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# with zipfile.ZipFile(dir_archive / f"{project_name}{suffix}_archive.zip", "w") as z:
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# for fname in files_fab:
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# z.write(dir_fab / fname, arcname=Path("fabrication") / fname)
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# for fname in files_asy:
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# z.write(dir_asy / fname, arcname=Path("assembly") / fname)
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# # TODO: archive project here
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