* Copyright (c) 1998-2019 Analog Devices, Inc.  All rights reserved.
*
.subckt AD8031 1 2 3 4 5
C1 N005 X {Cf}
A1 N006 0 M M M M X M OTA g={Ga} Iout={Islew} en=15n enk=200 Vhigh=1e308 Vlow=-1e308
B1 3 N005 I=if(V(m,x)>=0, V(m,x)*(Gb + Gbx*V(m,x)),0)
B2 N005 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0)
D21 X 3 ESD
D22 4 X ESD
D5 N005 3 X1
D6 4 N005 X2
G2 0 M 3 0 500µ
R4 M 0 1K noiseless
G3 0 M 4 0 500µ
S1 X M 4 3 SD
A2 2 1 0 0 0 0 0 0 OTA g=0 in=.4p ink=200k incm=.04p incmk=200k
C11 3 1 .8p Rpar=160Meg noiseless
C4 N004 0 1.2p Rpar=1K noiseless
L1 N004 N006 1.2µ
C6 N006 0 1.2p Rpar=1K noiseless
C2 3 N005 1p
C3 3 5 1p
C7 5 4 1p
C8 N005 4 1p
D3 3 4 IQ
C5 1 4 .8p Rpar=160Meg noiseless
C9 2 4 .8p Rpar=160Meg noiseless
C10 3 2 .8p Rpar=160Meg noiseless
R1 2 1 280.49K noiseless
D4 3 2 450nA
D7 3 1 450nA
B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)+.6,.1), V(4)-.6, .1)+100n*V(1)
B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)+.6,.1), V(4)-.6, .1)+100n*V(2)
D2 5 N005 BB
D1 5 N005 AA
.param Cf = 1p
.param Ro       =  5.2K
.param Avol     =  15k
.param RL       =  1K
.param AVmid =  80
.param FmidA = 1Meg
.param Zomid  = .6
.param FmidZ  = 1Meg
.param Vslew  = 32Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.param Gbx = Gb
.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-5m epsilon=10m noiseless)
.model X2 D(Ron=1m Roff={2*Ro} Vfwd=-5m epsilon=10m noiseless)
.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless)
.model IQ D(Ron=1K Roff=100Meg epsilon=1 Ilimit=800u noiseless)
.model AA D(Ron=38 Vrev=0 Ilimit=35m revIlimit=35m noiseless)
.model BB D(Ron=150 Roff=10Meg Ilimit=15m epsilon=.5 noiseless)
.model 450nA D(Ron=150K Ilimit=.45u revilimit=.45u Vfwd=1.1 Vrev=-1.1 noiseless)
.ends AD8031
*
.subckt AD8033 1 2 3 4 5
C1 N006 X {Cf}
A1 N005 0 M M M M X M OTA g={Ga} Iout={Islew} en=11n enk=8k Vhigh=1e308 Vlow=-1e308
D21 X 3 ESD
D22 4 X ESD
D5 N006 3 X1
D6 4 N006 X1
G2 0 M 3 0 500µ
R4 M 0 1K noiseless
G3 0 M 4 0 500µ
S1 X M 4 3 SD
A2 2 1 0 0 0 0 0 0 OTA g=0 in=7f ink=10 incm=.007f incmk=10
C4 N004 0 2.1p Rpar=1K noiseless
L1 N004 N005 2.1µ
C6 N005 0 2.1p Rpar=1K noiseless
C2 3 N006 1p
C3 3 5 1p
C7 5 4 1p
C8 N006 4 1p
D3 3 4 IQ
D4 3 2 2p
D7 3 1 2p
D1 5 N006 AA
D8 2 1 ED2
C5 3 1 .575p Rpar=4T noiseless
C9 1 4 .575p Rpar=4T noiseless
C10 2 4 .575p Rpar=4T noiseless
C11 3 2 .575p Rpar=4T noiseless
C18 2 1 1.125p
B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)-2.9,.1), V(4)-.1, .1)+100n*V(1)
B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)-2.9,.1), V(4)-.1, .1)+100n*V(2)
D2 5 3 X2
D9 4 5 X2
B1 3 N006 I=if(V(m,x)>=0, V(m,x)*Gb,0)
B2 N006 4 I=if(V(x,m)>0, V(x,m)*Gb,0)
.param Cf = .5p
.param Ro       =  5K
.param Avol     =  63K
.param RL       =  1K
.param AVmid =  30 ; 80
.param FmidA = 1Meg
.param Zomid  = .1
.param FmidZ  = 200K
.param Vslew  = 80Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.model ESD D(Ron=10 Roff=1T Vfwd=3 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff={4*Ro} Vfwd=.287 epsilon=10m noiseless)
.model X2 D(Ron=1m Roff={4*Ro} Vfwd=-20m epsilon=10m noiseless)
.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless)
.model IQ D(Ron=1K Roff=100Meg epsilon=1 Ilimit=1.8m noiseless)
.model AA D(Ron=30 Vrev=0 Ilimit=60m revIlimit=60m noiseless)
.model 2p D(Ron=1T epsilon=1 Ilimit=2p noiseless)
.model ED2 D(Ron=1 Roff=1.3T Vfwd=1 epsilon=1 Vrev=.75 revepsilon=1 noiseless)
.ends AD8033
*
.subckt AD8038 1 2 3 4 5
A1 2 1 0 0 0 0 0 0 OTA g=0 in=600f ink=1k incm=60f incmk=1k
M1 3 N004 5 5 N temp=27
M2 4 N004 5 5 P temp=27
C3 3 5 1p
C4 5 4 1p
A2 0 N005 M M M M N004 M OTA g=330u Isrc=43u en=8n enk=1k Vlow=-1e308 Vhigh=1e308 Cout= .1p asym
C10 N003 0 {.12p*x} Rpar=1K noiseless
D1 N004 5 Y
D6 5 N004 Y
G1 0 M 3 0 1m
G2 0 M 4 0 1m
R3 M 0 1K noiseless
S1 N004 M 4 3 UVLO
D3 N004 3 X
D4 4 N004 X
C2 3 2 1p Rpar=20Meg noiseless
C5 2 4 1p Rpar=20Meg noiseless
C6 3 1 1p Rpar=20Meg noiseless
C7 1 4 1p Rpar=20Meg noiseless
B1 N003 0 I=1m*dnlim(uplim(V(2),V(3)-.9,.1), V(4)+.9, .1)+100n*V(2)
B2 0 N003 I=1m*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+.9, .1)+100n*V(1)
C1 N005 0 {.12p*x} Rpar=1K noiseless
L1 N003 N005 {.12u*x}
.model X D(Ron=2K Roff=20Meg Vfwd=-1.1  epsilon=.1 noiseless)
.model Y D(Ron=500 Roff=1T Vfwd=1.2 epsilon=.1 noiseless)
.model N VDMOS(Vto=-100m Kp=.12 Ksubthres=.1 noiseless)
.model P VDMOS(Vto=100m Kp=.12 pchan Ksubthres=.1 noiseless)
.model UVLO SW(Ron=1K Roff=5G Vt=-3.75 Vh=.25 noiseless)
.param x =1.3
.ends AD8038
*
.subckt AD8029 1 2 3 4 5 6
C1 N005 X {Cf}
A1 N006 0 M M M M X M OTA g={Ga} Iout={Islew} en=16.5n enk=500 Vhigh=1e308 Vlow=-1e308
D21 X 3 ESD
D22 4 X ESD
D5 N005 3 X1
D6 4 N005 X1
G2 0 M 3 0 500µ
R4 M 0 1K noiseless
G3 0 M 4 0 500µ
S1 X M 4 3 SD
A2 2 1 0 0 0 0 0 0 OTA g=0 in=1.1p ink=4K incm=.1p incmk=4K
C11 3 1 1p Rpar=12Meg noiseless
C4 N004 0 {.5p*x} Rpar=1K noiseless
L1 N004 N006 {.5µ*x}
C6 N006 0 {.5p*x} Rpar=1K noiseless
C2 3 N005 {1p*y}
D4 3 2 bias
D1 5 N005 AA
D8 2 1 ED2
C5 1 4 1p Rpar=12Meg noiseless
C9 2 4 1p Rpar=12Meg noiseless
C10 3 2 1p Rpar=12Meg noiseless
D7 3 1 bias
B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)+.3,.1), V(4)-.3, .1)+100n*V(2)
B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+100n*V(1)
D2 5 N005 BB
C3 3 5 {1p*y}
C7 5 4 {1p*y}
C8 N005 4 {1p*y}
D9 3 6 6.5uA
C12 6 4 1p Rpar=10Meg
S2 X M 4 6 DIS
S3 4 3 6 4 IQ
D3 3 4 IQ
B1 3 N005 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0)
B2 N005 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0)
.param Cf = 1.8p
.param Ro       =  50K
.param Avol     =  5K
.param RL       =  1K
.param AVmid =  125
.param FmidA = 1Meg
.param Zomid  = 1.6
.param FmidZ  = 1Meg
.param Vslew  = 50Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.param Gbx = 2*Gb
.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-15m epsilon=10m noiseless)
.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless)
.model IQ D(Ron=10K Roff=1G epsilon=1 Ilimit=90u noiseless)
.model IQ SW(Ron=1K Roff=100Meg Ilimit=1.25m level=2 Vt=1 Vh=-.2  noiseless)
.model AA D(Ron=40 Vrev=0 Ilimit=50m revIlimit=50m noiseless)
.model BB D(Ron=5 Vrev=1 Vfwd=1 epsilon=1 revepsilon=1 Ilimit=115m revIlimit=115m noiseless)
.model ED2 D(Ron=1 Roff=1T Vfwd=1.2 epsilon=1 Vrev=1.2 revepsilon=1 noiseless)
.model bias D(Ron=50K  Ilimit=1.7u revilimit=.7u  Vfwd=.5 Vrev=-.5 noiseless)
.model 6.5uA D(Ron=30K Vfwd=1 epsilon=1 Ilimit=6.5u noiseless)
.model DIS SW(Ron=1m Roff=1T Vt=-1 Vh=.2)
.param X=.7 y=.5
.ends AD8029
*
.subckt AD8040 1 2 3 4 5
C1 N005 X {Cf}
A1 N006 0 M M M M X M OTA g={Ga} Iout={Islew} en=16.5n enk=500 Vhigh=1e308 Vlow=-1e308
D21 X 3 ESD
D22 4 X ESD
D5 N005 3 X1
D6 4 N005 X1
G2 0 M 3 0 500µ
R4 M 0 1K noiseless
G3 0 M 4 0 500µ
S1 X M 4 3 SD
A2 2 1 0 0 0 0 0 0 OTA g=0 in=1.1p ink=4K incm=.1p incmk=4K
C11 3 1 1p Rpar=12Meg noiseless
C4 N004 0 {.5p*x} Rpar=1K noiseless
L1 N004 N006 {.5µ*x}
C6 N006 0 {.5p*x} Rpar=1K noiseless
C2 3 N005 {1p*y}
D3 3 4 IQ
D4 3 2 bias
D1 5 N005 AA
D8 2 1 ED2
C5 1 4 1p Rpar=12Meg noiseless
C9 2 4 1p Rpar=12Meg noiseless
C10 3 2 1p Rpar=12Meg noiseless
D7 3 1 bias
B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)+.3,.1), V(4)-.3, .1)+100n*V(2)
B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+100n*V(1)
D2 5 N005 BB
C3 3 5 {1p*y}
C7 5 4 {1p*y}
C8 N005 4 {1p*y}
B1 3 N005 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0)
B2 N005 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0)
.param Cf = 1.8p
.param Ro       =  50K
.param Avol     =  5K
.param RL       =  1K
.param AVmid =  125
.param FmidA = 1Meg
.param Zomid  = 1.6
.param FmidZ  = 1Meg
.param Vslew  = 50Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.param Gbx = 2*Gb
.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-15m epsilon=10m noiseless)
.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless)
.model IQ D(Ron=1K Roff=100Meg epsilon=1 Ilimit=1.25m noiseless)
.model AA D(Ron=40 Vrev=0 Ilimit=50m revIlimit=50m noiseless)
.model BB D(Ron=5 Vrev=1 Vfwd=1 epsilon=1 revepsilon=1 Ilimit=115m revIlimit=115m noiseless)
.model ED2 D(Ron=1 Roff=1T Vfwd=1.2 epsilon=1 Vrev=1.2 revepsilon=1 noiseless)
.model bias D(Ron=50K  Ilimit=1.7u revilimit=.7u  Vfwd=.5 Vrev=-.5 noiseless)
.param X=.7 y=.5
.ends AD8040
*
.subckt AD8041 1 2 3 4 5 6
C1 N005 X {Cf} Rser=150
A1 N006 0 M M M M X M OTA g={Ga} Iout={Islew} en=16n enk=850 Vhigh=1e308 Vlow=-1e308
D21 X 3 ESD
D22 4 X ESD
D5 N005 3 X1
D6 4 N005 X1
G2 0 M 3 0 500µ
R4 M 0 1K noiseless
G3 0 M 4 0 500µ
S1 X M 4 3 SD
A2 2 1 0 0 0 0 0 0 OTA g=0 in=600f ink=2K incm=60f incmk=2K
C11 3 1 .9p Rpar=320K noiseless
C4 N004 0 {.5p*x} Rpar=1K noiseless
L1 N004 N006 {.5µ*x}
C6 N006 0 {.5p*x} Rpar=1K noiseless
C2 3 N005 1p
D1 5 N005 AA
C3 3 5 1p
C7 5 4 1p
C8 N005 4 1p
C12 3 6 1p Rpar=2Meg noiseless
S2 M X 3 6 DIS
S3 3 4 6 3 IQ
D3 3 4 IQ
I1 3 1 1.2µ load
I2 3 2 1.2µ load
C5 1 4 .9p Rpar=320K noiseless
C9 2 4 .9p Rpar=320K noiseless
C10 3 2 .9p Rpar=320K noiseless
B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)-.9,.1), V(4)-.3, .1)+100n*V(2)
B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)-.9,.1), V(4)-.3, .1)+100n*V(1)
D2 5 N005 BB
B1 3 N005 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0)
B2 N005 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0)
.param Cf = 1p
.param Ro       =  6.5K
.param Avol     =  70K
.param RL       =  2K
.param AVmid =  150
.param FmidA = 1Meg
.param Zomid  = 5.5
.param FmidZ  = 1Meg
.param Vslew  = 160Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.param Gbx = 20*Gb
.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless)
.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless)
.model IQ D(Ron=10K Roff=1G epsilon=1 Ilimit=1.6m noiseless)
.model IQ SW(Ron=200 Roff=100Meg Ilimit=4.2m level=2 Vt=-2 Vh=-.2  noiseless)
.model AA D(Ron=33 Vrev=0 Ilimit=50m revIlimit=50m noiseless)
.model BB D(Ron=3 Vrev=1 Vfwd=.1 epsilon=.1 revepsilon=.5 Ilimit=100m revIlimit=50m noiseless)
.model bias D(Ron=50K  Ilimit=1.7u revilimit=.7u  Vfwd=.5 Vrev=-.5 noiseless)
.model 6.5uA D(Ron=30K Vfwd=1 epsilon=1 Ilimit=6.5u noiseless)
.model DIS SW(Ron=1m Roff=1T Vt=2 Vh=.2)
.param X=.7
.ends AD8041
*
* AD8042a Spice Macro-model
* Description: Amplifier
* Generic Desc: Dual 160MHz Rail-to-rail amplifier
* Developed by:
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (09/1996)
* Copyright 1996, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*     Distortion and noise are not characterized
*
* Parameters modeled include:
*    open loop gain and phase vs frequency
*    output clamping voltage and current
*    input common mode range
*    CMRR vs freq
*    I bias vs Vcm in
*    Slew rate
*    Output currents are reflected to V supplies
*    Vos is static and will not vary with Vcm in
*    Step response is modeled at unity gain w/1k load
*
* END Notes
*
* Node assignments
*                non-inverting input
*                | inverting input
*                | | positive supply
*                | | |  negative supply
*                | | |  |  output
*                | | |  |  |
.SUBCKT AD8042a  1 2 99 50 61
*#ASSOC Category="Op-amps" symbol=opamp

***** Input bias current source

ecm 20 0 99 3 1
d1 20 21 dx
v3 21 22 0.2
r20 22 0 100
f1 0 25 v3 1
r22 25 0 1k
r23 26 28 8
d3 25 26 dx
v5 28 0 .3
g1 1 0 0 25 400e-9
g2 2 0 0 25 400e-9

***** Input Stage

R1 1 3 80k
R2 3 2 80k
C1 1 2 1.8pf
rcm1 1 0 5e6
rcm2 2 0 5e6
R3 1 98 40e6
R4 2 98 40e6
r9 15 7 764
r10 16 7 764
q1 5 1 15 qp1
q2 6 4 16 qp1
r5 50 5 1254
r6 50 6 1254
ib3 99 7 1e-4
eos 2 4 poly(1) (108,98) 2e-3 1

***** gain stage/pole at 3200hz/clamp circuitry

g3 99 31 6 5 7.97e-4
g4 31 50 5 6 7.97e-4
r7 99 31 63e6
r8 31 50 63e6
c3 99 31 0.635e-12
c4 31 50 0.635e-12

vc1 99 45 0.72
vc2 46 50 0.72
dc1 31 45 dx
dc2 46 31 dx

***** pole at 200mhz

e1 32 98 31 98 1
rflt 32 33 1k
cflt 33 98 0.796e-12

***** internal reference

rdiv1 99 97 100k
rdiv2 97 50 100k
Eref 98 0 97 0 1
rref 98 0 1e6

***** Common mode gain network

gacm1 99 100 3 98 2e-13
gacm2 100 50 98 3 2e-13
racm1 99 100 1e4
racm2 100 50 1e4

***** Common mode gain network/zero at 3200hz

ecm1  101 98 100 98 1e6
racm3 101 102 1e6
racm4 102 103 1
lacm1 103 98 40u

***** Common mode gain network/zero at 100khz/pole at 60mhz

ecm2  104 98 102 98 300
racm5 104 105 300
racm6 105 106 1
lacm2 106 98 .78u

***** Common mode gain network/pole at 60mhz

ecm3 107 98 105 98 1
racm7 107 108 10k
cacm1 108 98 0.265e-12

***** buffer to output stage

gbuf 98 34 33 98 1e-4
re1 34 98 10k

***** output stage

fo1 98 110 vcd 1
do1 110 111 dx
do2 112 110 dx
vi1 111 98 0
vi2 98 112 0

fsy 99 50 poly(2) vi1 vi2 4.73e-3 1 1

go3 60 99 99 34 0.1
go4 50 60 34 50 0.1
r03 60 99 10
r04 60 50 10
vcd 60 62 0
lo1 62 61 2n
ro2 61 98 1e9
do5 34 70 dx
do6 71 34 dx
vo1 70 60 -0.31
vo2 60 71 -0.05

.model dx d(is=1e-15)
.model qn1 npn(bf=500 vaf=100)
.model qp1 pnp(bf=500 vaf=60)
.ends AD8042a





* AD8044a Spice Macro-model
* Description: Amplifier
* Generic Desc: Quad 150MHz Rail-to-rail amplifier
* Developed by:
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (09/1996)
* Copyright 1996, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*     Distortion and noise are not characterized
*
* Parameters modeled include:
*    open loop gain and phase vs frequency
*    output clamping voltage and current
*    input common mode range
*    CMRR vs freq
*    I bias vs Vcm in
*    Slew rate
*    Output currents are reflected to V supplies
*    Vos is static and will not vary with Vcm in
*    Step response is modeled at unity gain w/1k load
*
* END Notes
*
* Node assignments
*                non-inverting input
*                | inverting input
*                | | positive supply
*                | | |  negative supply
*                | | |  |  output
*                | | |  |  |
.SUBCKT AD8044a  1 2 99 50 61
*#ASSOC Category="Op-amps" symbol=opamp

***** Input bias current source

ecm 20 0 99 3 1
d1 20 21 dx
v3 21 22 0.2
r20 22 0 100
f1 0 25 v3 1
r22 25 0 1k
r23 26 28 8
d3 25 26 dx
v5 28 0 .3
g1 1 0 0 25 400e-9
g2 2 0 0 25 400e-9

***** Input Stage

R1 1 3 80k
R2 3 2 80k
C1 1 2 1.8pf
rcm1 1 0 5e6
rcm2 2 0 5e6
R3 1 98 40e6
R4 2 98 40e6
r9 15 7 764
r10 16 7 764
q1 5 1 15 qp1
q2 6 4 16 qp1
r5 50 5 1254
r6 50 6 1254
ib3 99 7 1e-4
eos 2 4 poly(1) 108 98 2e-3 1

***** gain stage/pole at 3200hz/clamp circuitry

*g3 99 31 6 5 7.97e-4
*g4 31 50 5 6 7.97e-4
*r7 99 31 63e6
*r8 31 50 63e6
*c3 99 31 0.635e-12
*c4 31 50 0.635e-12
g3 99 31 6 5 6.37e-4
g4 31 50 5 6 6.37e-4
r7 99 31 82.9e6
r8 31 50 82.9e6
c3 99 31 0.6e-12
c4 31 50 0.6e-12

vc1 99 45 0.72
vc2 46 50 0.72
dc1 31 45 dx
dc2 46 31 dx

***** pole at 100mhz

e1 32 98 31 98 1
rflt 32 33 1k
cflt 33 98 1.6e-12

***** internal reference

rdiv1 99 97 100k
rdiv2 97 50 100k
Eref 98 0 97 0 1
rref 98 0 1e6

***** Common mode gain network

gacm1 99 100 3 98 2e-13
gacm2 100 50 98 3 2e-13
racm1 99 100 1e4
racm2 100 50 1e4

***** Common mode gain network/zero at 3200hz

ecm1  101 98 100 98 1e6
racm3 101 102 1e6
racm4 102 103 1
lacm1 103 98 40u

***** Common mode gain network/zero at 100khz/pole at 60mhz

ecm2  104 98 102 98 300
racm5 104 105 300
racm6 105 106 1
lacm2 106 98 .78u

***** Common mode gain network/pole at 60mhz

ecm3 107 98 105 98 1
racm7 107 108 10k
cacm1 108 98 0.265e-12

***** buffer to output stage

gbuf 98 34 33 98 1e-4
re1 34 98 10k

***** output stage

fo1 98 110 vcd 1
do1 110 111 dx
do2 112 110 dx
vi1 111 98 0
vi2 98 112 0

fsy 99 50 poly(2) vi1 vi2 4.73e-3 1 1

go3 60 99 99 34 0.1
go4 50 60 34 50 0.1
r03 60 99 10
r04 60 50 10
vcd 60 62 0
lo1 62 61 2n
ro2 61 98 1e9
do5 34 70 dx
do6 71 34 dx
vo1 70 60 -0.31
vo2 60 71 -0.05

.model dx d(is=1e-15)
.model qn1 npn(bf=500 vaf=100)
.model qp1 pnp(bf=500 vaf=60)
.ends AD8044a






* AD8047 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 250MHz (G=1) voltage feedback op amp
* Developed by: JCH / ADI
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (11/1997)
* Copyright 1997, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* CAUTION: NOISE PERFORMANCE IS NOT INCLUDED IN THIS MODEL.  NOISE
* MODELING WILL BE INCLUDED IN A LATER REVISION.
*
* Node assignments
*               non-inverting input
*               |  inverting input
*               |  |  positive supply
*               |  |  |  negative supply
*               |  |  |  |  output
*               |  |  |  |  |
.SUBCKT AD8047  3  1  99 50 44
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE AND POLE AT 800MHZ
*
I1   8    50   1E-3
Q1   4    1    6    QN
Q2   5    2    7    QN
R1   99   4    862
R2   99   5    862
C1   4    5    0.116p
R3   6    8    810.5
R4   7    8    810.5
RCM1 1    20   5G
RCM2 3    20   5G
IOS  1    3    3u
EOS  3    2    POLY(1) (16,98) 1E-3 1
CIN1 1   99    1.5PF
CIN2 2   99    1.5PF
*
* GAIN STAGE AND DOMINANT POLE AT 110KHZ
*
EREF 98   0    POLY(2) (99,0) (50,0) 0 0.5 0.5
G1   98   9    (4,5) 1.16E-3
R5   9    98   1.085E6
C2   9    98   1.333E-12
D1   9    10   DX
D2   11   9    DX
H1   99   10   POLY(1) Vout 1.87  37.9 -3.94E2  2.44E3
H2   11   50   POLY(1) Vout 1.93 -40.3 -4.51E2 -2.70E3
*
*POLE AT 1.1GHZ
*
GP1  98   12    (9,98) 1
RP1  98   12    1
CP1  98   12    0.14N
*
*POLE AT 1.1GHZ
*
GP2  98   13    (12,98) 1
RP2  98   13    1
CP2  98   13    0.14N
*
*POLE AT 1.1GHZ
*
GP3  98   14    (13,98) 1
RP3  98   14    1
CP3  98   14    0.14N
*
*POLE AT 1.3GHZ
*
GP4  98   17    (14,98) 1
RP4  98   17    1
CP4  98   17    0.12N
*
*COMMON-MODE ZERO AT 113KHZ
*
GCM1 98   15    20 98 1E-10
RCM3 15   16    1MEG
LCM1 16   98    1.4
*
* BUFFER TO OUTPUT STAGE
*
GB11  98   40   (14,98) 200m
RB11  98   40   5
*
* OUTPUT STAGE
*
RO1  99   45   0.4
RO2  45   50   0.4
G7   45   99   (99,40) 2.5
G8   50   45   (40,50) 2.5
G9   98   60   (45,40) 2.5
D7   60   61   DX
D8   62   60   DX
V7   61   98   DC 0
V8   98   62   DC 0
FSY  99   50   POLY(2) V7 V8 4E-3  1  1
D9   41   45   DX
D10  45   42   DX
V5   40   41   0.68
V6   42   40   0.68
Vout 45   46   0
LO   46   44   .06E-9
*
* MODELS USED
*
.MODEL DX D
.MODEL QN NPN(BF=500)
.ENDS AD8047






*AD8065 Macro-model
*Function:Amplifier
*
*Revision History:
*Rev.2.1 Jun 2015-ZZ
*Copyright 2015 by Analog Devices
*
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
*for License Statement. Use of this model indicates your acceptance
*of the terms and provisions in the License Staement.
*
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
*
*Not modeled: Distortion, PSRR, Overload Recovery,
*             Shutdown Turn On/Turn Off time
*
*Parameters modeled include:
*   Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
*   Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
*   Capacitive load drive, Quiescent and dynamic supply currents,
*   Shut Down pin functionality where applicable,
*   Single supply & offset supply functionality.
*
*Node Assignments
*               Non-Inverting Input
*               |   Inverting Input
*               |   |   Positive supply
*               |   |   |   Negative supply
*               |   |   |   |   Output
*               |   |   |   |   |
.Subckt AD8065 100 101 102 103 104
*#ASSOC Category="Op-Amps" symbol=opamp
***Power Supplies***
Rz1    102    1020    Rideal    1e-6
Rz2    103    1030    Rideal    1e-6
Ibias    1020    1030    dc    0.64e-3
DzPS    98    1020    diode
Iquies    1020    98    dc    5.76e-3
S1    98    1030    106    113    Switch
R1    1020    99    Rideal    1e7
R2    99    1030    Rideal    1e7
e1    111    110    1020    110    1
e2    110    112    110    1030    1
e3    110    0    99    0    1
*
*
***Inputs***
S2    1    100    106    113    Switch
S3    9    101    106    113    Switch
VOS    1    2    dc    400e-6
IbiasP    110    2    dc    2e-12
IbiasN    110    9    dc    2e-12
RinCMP    110    2    Rideal    10000e6
RinCMN    9    110    Rideal    10000e6
CinCMP    110    2    1.1e-12
CinCMN    9    110    1.1e-12
IOS    9    2    1e-12
RinDiff    9    2    Rideal    10000e3
CinDiff    9    2    4e-12
*
*
***Non-Inverting Input with Clamp***
g1    3    110    110    2    0.001
RInP    3    110    Rideal    1e3
RX1    40    3    Rideal    0.001
DInP    40    41    diode
DInN    42    40    diode
VinP    111    41    dc    3.06
VinN    42    112    dc    0.46
*
*
***Vnoise***
hVn    6    5    Vmeas1    707.10678
Vmeas1    20    110    DC    0
Vvn    21    110    dc    0.65
Dvn    21    20    DVnoisy
hVn1    6    7    Vmeas2    707.10678
Vmeas2    22    110    dc    0
Vvn1    23    110    dc    0.65
Dvn1    23    22    DVnoisy
*
*
***Inoise***
FnIN    9    110    Vmeas3    0.7071068
Vmeas3    51    110    dc    0
VnIN    50    110    dc    0.65
DnIN    50    51    DINnoisy
FnIN1    110    9    Vmeas4    0.7071068
Vmeas4    53    110    dc    0
VnIN1    52    110    dc    0.65
DnIN1    52    53    DINnoisy
*
FnIP    2    110    Vmeas5    0.7071068
Vmeas5    31    110    dc    0
VnIP    30    110    dc    0.65
DnIP    30    31    DIPnoisy
FnIP1    110    2    Vmeas6    0.7071068
Vmeas6    33    110    dc    0
VnIP1    32    110    dc    0.65
DnIP1    32    33    DIPnoisy
*
*
***CMRR***
RcmrrP    3    10    Rideal    1e12
RcmrrN    10    9    Rideal    1e12
g10    11    110    10    110    -1e-10
Lcmrr    11    12    1e-12
Rcmrr    12    110    Rideal    1e3
e4    5    3    11    110    1
*
*
***Power Down***
VPD    111    80    dc    2
VPD1    81    0    dc    1.5
RPD    111    106    Rideal    0.286e6
ePD    80    113    82    0    1
RDP1    82    0    Rideal    1e3
CPD    82    0    1e-10
S5    81    82    83    113    Switch
CDP1    83    0    1e-12
RPD2    106    83    1e6
*
*
***Feedback Pin***
*RF    105    104    Rideal    0.001
*
*
***VFB Stage***
g200    200    110    7    9    1
R200    200    110    Rideal    250
DzSlewP    201    200    DzSlewP
DzSlewN    201    110    DzSlewN
*
*
***Dominant Pole at 150 Hz***
g210    210    110    200    110    1.684e-6
R210    210    110    Rideal    1061.03e6
C210    210    110    1e-012
*
*
***Output Voltage Clamp-1***
RX2    60    210    Rideal    0.001
DzVoutP    61    60    DzVoutP
DzVoutN    60    62    DzVoutN
DVoutP    61    63    diode
DVoutN    64    62    diode
VoutP    65    63    dc    5.176
VoutN    64    66    dc    5.072
e60    65    110    111    110    1.038
e61    66    110    112    110    1.038
*
*
***Pole at 90MHz***
g220    220    110    210    110    0.001
R220    220    110    Rideal    1000
C220    220    110    1.7684e-12
*
***Pole at 1400MHz***
g230    230    110    220    110    0.001
R230    230    110    Rideal    1000
C230    230    110    0.1137e-12
*
***Pole at 1800MHz***
g240    240    110    230    110    0.001
R240    240    110    Rideal    1000
C240    240    110    0.0884e-12
*
***Zero at 1000MHz***
g245    245    110    240    110    0.001
R245    245    246    Rideal    1000
L245    246    110    0.1592e-6
*
***Buffer***
g250    250    110    245    110    0.001
R250    250    110    Rideal    1000
*
***Buffer***
g255    255    110    250    110    0.001
R255    255    110    Rideal    1000
*
***Buffer***
g260    260    110    255    110    0.001
R260    260    110    Rideal    1000
*
***Buffer***
g265    265    110    260    110    0.001
R265    265    110    Rideal    1000
*
***Buffer***
g270    270    110    265    110    0.001
R270    270    110    Rideal    1000
*
***Buffer***
e280    280    110    270    110    1
R280    280    285    Rideal    10
*
***Peak: f=210MHz, Zeta=0.999999999999999, Gain=2.3dB***
e290    290    110    285    110    1
R290    290    292    Rideal    10
L290    290    291    3.789e-9
C290    291    292    151.576e-12
R291    292    110    Rideal    32.985
e295    295    110    292    110    1.3032
*
*
***Output Stage***
g300    300    110    295    110    0.001
R300    300    110    Rideal    1000
e301    301    110    300    110    1
Rout    302    303    Rideal     4.9
Lout    303    310     7e-9
Cout    310    110     46e-12
*
*
***Output Current Limit***
H1    301    304    Vsense1    100
Vsense1    301    302    dc    0
VIoutP    305    304    dc    8.336
VIoutN    304    306    dc    8.336
DIoutP    307    305    diode
DIoutN    306    307    diode
Rx3    307    300    Rideal    0.001
*
*
***Output Clamp-2***
VoutP1    111    73    dc    0.735
VoutN1    74    112    dc    0.715
DVoutP1    75    73    diode
DVoutN1    74    75    diode
RX4    75    310    Rideal    0.001
*
*
***Supply Currents***
FIoVcc    314    110    Vmeas8    1
Vmeas8    310    311    dc    0
R314    110    314    Rideal    1e9
DzOVcc    110    314    diode
DOVcc    102    314    diode
RX5    311    312    Rideal    0.001
FIoVee    315    110    Vmeas9    1
Vmeas9    312    313    dc    0
R315    315    110    Rideal    1e9
DzOVee    315    110    diode
DOVee    315    103    diode
*
*
***Output Switch***
S4    104    313    106    113    Switch
*
*
*** Common Models ***
.model    diode    d(bv=100)
.model    Switch    vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6)
.model    DzVoutP    D(BV=4.3)
.model    DzVoutN    D(BV=4.3)
.model    DzSlewP    D(BV=107.367)
.model    DzSlewN    D(BV=107.367)
.model    DVnoisy    D(IS=1.41e-15 KF=1.05e-15)
.model    DINnoisy    D(IS=3.81e-23 KF=0.00e0)
.model    DIPnoisy    D(IS=3.81e-23 KF=0.00e0)
.model    Rideal    res(T_ABS=-273)
*
.ends AD8065

*AD8066 Macro-model
*Function:Amplifier
*
*Revision History:
*Rev.2.1 Jun 2015-ZZ
*Copyright 2015 by Analog Devices
*
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
*for License Statement. Use of this model indicates your acceptance
*of the terms and provisions in the License Staement.
*
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
*
*Not modeled: Distortion, PSRR, Overload Recovery,
*             Shutdown Turn On/Turn Off time
*
*Parameters modeled include:
*   Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
*   Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
*   Capacitive load drive, Quiescent and dynamic supply currents,
*   Shut Down pin functionality where applicable,
*   Single supply & offset supply functionality.
*
*Node Assignments
*               Non-Inverting Input
*               |   Inverting Input
*               |   |   Positive supply
*               |   |   |   Negative supply
*               |   |   |   |   Output
*               |   |   |   |   |
.Subckt AD8066 100 101 102 103 104
*#ASSOC Category="Op-Amps" symbol=opamp
***Power Supplies***
Rz1    102    1020    Rideal    1e-6
Rz2    103    1030    Rideal    1e-6
Ibias    1020    1030    dc    0.64e-3
DzPS    98    1020    diode
Iquies    1020    98    dc    5.76e-3
S1    98    1030    106    113    Switch
R1    1020    99    Rideal    1e7
R2    99    1030    Rideal    1e7
e1    111    110    1020    110    1
e2    110    112    110    1030    1
e3    110    0    99    0    1
*
*
***Inputs***
S2    1    100    106    113    Switch
S3    9    101    106    113    Switch
VOS    1    2    dc    400e-6
IbiasP    110    2    dc    2e-12
IbiasN    110    9    dc    2e-12
RinCMP    110    2    Rideal    10000e6
RinCMN    9    110    Rideal    10000e6
CinCMP    110    2    1.1e-12
CinCMN    9    110    1.1e-12
IOS    9    2    1e-12
RinDiff    9    2    Rideal    10000e3
CinDiff    9    2    4e-12
*
*
***Non-Inverting Input with Clamp***
g1    3    110    110    2    0.001
RInP    3    110    Rideal    1e3
RX1    40    3    Rideal    0.001
DInP    40    41    diode
DInN    42    40    diode
VinP    111    41    dc    3.06
VinN    42    112    dc    0.46
*
*
***Vnoise***
hVn    6    5    Vmeas1    707.10678
Vmeas1    20    110    DC    0
Vvn    21    110    dc    0.65
Dvn    21    20    DVnoisy
hVn1    6    7    Vmeas2    707.10678
Vmeas2    22    110    dc    0
Vvn1    23    110    dc    0.65
Dvn1    23    22    DVnoisy
*
*
***Inoise***
FnIN    9    110    Vmeas3    0.7071068
Vmeas3    51    110    dc    0
VnIN    50    110    dc    0.65
DnIN    50    51    DINnoisy
FnIN1    110    9    Vmeas4    0.7071068
Vmeas4    53    110    dc    0
VnIN1    52    110    dc    0.65
DnIN1    52    53    DINnoisy
*
FnIP    2    110    Vmeas5    0.7071068
Vmeas5    31    110    dc    0
VnIP    30    110    dc    0.65
DnIP    30    31    DIPnoisy
FnIP1    110    2    Vmeas6    0.7071068
Vmeas6    33    110    dc    0
VnIP1    32    110    dc    0.65
DnIP1    32    33    DIPnoisy
*
*
***CMRR***
RcmrrP    3    10    Rideal    1e12
RcmrrN    10    9    Rideal    1e12
g10    11    110    10    110    -1e-10
Lcmrr    11    12    1e-12
Rcmrr    12    110    Rideal    1e3
e4    5    3    11    110    1
*
*
***Power Down***
VPD    111    80    dc    2
VPD1    81    0    dc    1.5
RPD    111    106    Rideal    0.286e6
ePD    80    113    82    0    1
RDP1    82    0    Rideal    1e3
CPD    82    0    1e-10
S5    81    82    83    113    Switch
CDP1    83    0    1e-12
RPD2    106    83    1e6
*
*
***Feedback Pin***
*RF    105    104    Rideal    0.001
*
*
***VFB Stage***
g200    200    110    7    9    1
R200    200    110    Rideal    250
DzSlewP    201    200    DzSlewP
DzSlewN    201    110    DzSlewN
*
*
***Dominant Pole at 150 Hz***
g210    210    110    200    110    1.684e-6
R210    210    110    Rideal    1061.03e6
C210    210    110    1e-012
*
*
***Output Voltage Clamp-1***
RX2    60    210    Rideal    0.001
DzVoutP    61    60    DzVoutP
DzVoutN    60    62    DzVoutN
DVoutP    61    63    diode
DVoutN    64    62    diode
VoutP    65    63    dc    5.176
VoutN    64    66    dc    5.072
e60    65    110    111    110    1.038
e61    66    110    112    110    1.038
*
*
***Pole at 90MHz***
g220    220    110    210    110    0.001
R220    220    110    Rideal    1000
C220    220    110    1.7684e-12
*
***Pole at 1400MHz***
g230    230    110    220    110    0.001
R230    230    110    Rideal    1000
C230    230    110    0.1137e-12
*
***Pole at 1800MHz***
g240    240    110    230    110    0.001
R240    240    110    Rideal    1000
C240    240    110    0.0884e-12
*
***Zero at 1000MHz***
g245    245    110    240    110    0.001
R245    245    246    Rideal    1000
L245    246    110    0.1592e-6
*
***Buffer***
g250    250    110    245    110    0.001
R250    250    110    Rideal    1000
*
***Buffer***
g255    255    110    250    110    0.001
R255    255    110    Rideal    1000
*
***Buffer***
g260    260    110    255    110    0.001
R260    260    110    Rideal    1000
*
***Buffer***
g265    265    110    260    110    0.001
R265    265    110    Rideal    1000
*
***Buffer***
g270    270    110    265    110    0.001
R270    270    110    Rideal    1000
*
***Buffer***
e280    280    110    270    110    1
R280    280    285    Rideal    10
*
***Peak: f=210MHz, Zeta=0.999999999999999, Gain=2.3dB***
e290    290    110    285    110    1
R290    290    292    Rideal    10
L290    290    291    3.789e-9
C290    291    292    151.576e-12
R291    292    110    Rideal    32.985
e295    295    110    292    110    1.3032
*
*
***Output Stage***
g300    300    110    295    110    0.001
R300    300    110    Rideal    1000
e301    301    110    300    110    1
Rout    302    303    Rideal     4.9
Lout    303    310     7e-9
Cout    310    110     46e-12
*
*
***Output Current Limit***
H1    301    304    Vsense1    100
Vsense1    301    302    dc    0
VIoutP    305    304    dc    8.336
VIoutN    304    306    dc    8.336
DIoutP    307    305    diode
DIoutN    306    307    diode
Rx3    307    300    Rideal    0.001
*
*
***Output Clamp-2***
VoutP1    111    73    dc    0.735
VoutN1    74    112    dc    0.715
DVoutP1    75    73    diode
DVoutN1    74    75    diode
RX4    75    310    Rideal    0.001
*
*
***Supply Currents***
FIoVcc    314    110    Vmeas8    1
Vmeas8    310    311    dc    0
R314    110    314    Rideal    1e9
DzOVcc    110    314    diode
DOVcc    102    314    diode
RX5    311    312    Rideal    0.001
FIoVee    315    110    Vmeas9    1
Vmeas9    312    313    dc    0
R315    315    110    Rideal    1e9
DzOVee    315    110    diode
DOVee    315    103    diode
*
*
***Output Switch***
S4    104    313    106    113    Switch
*
*
*** Common Models ***
.model    diode    d(bv=100)
.model    Switch    vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6)
.model    DzVoutP    D(BV=4.3)
.model    DzVoutN    D(BV=4.3)
.model    DzSlewP    D(BV=107.367)
.model    DzSlewN    D(BV=107.367)
.model    DVnoisy    D(IS=1.41e-15 KF=1.05e-15)
.model    DINnoisy    D(IS=3.81e-23 KF=0.00e0)
.model    DIPnoisy    D(IS=3.81e-23 KF=0.00e0)
.model    Rideal    res(T_ABS=-273)
*
.ends AD8066

*AD8067 Macro-model
*Function:Amplifier
*
*Revision History:
*Rev.2.1 Jun 2015-ZZ
*Copyright 2015 by Analog Devices
*
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
*for License Statement. Use of this model indicates your acceptance
*of the terms and provisions in the License Staement.
*
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
*
*Not modeled: Distortion, PSRR, Overload Recovery,
*             Shutdown Turn On/Turn Off time
*
*Parameters modeled include:
*   Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
*   Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
*   Capacitive load drive, Quiescent and dynamic supply currents,
*   Shut Down pin functionality where applicable,
*   Single supply & offset supply functionality.
*
*Node Assignments
*               Non-Inverting Input
*               |   Inverting Input
*               |   |   Positive supply
*               |   |   |   Negative supply
*               |   |   |   |   Output
*               |   |   |   |   |
.Subckt AD8067 100 101 102 103 104
*#ASSOC Category="Op-Amps" symbol=opamp
*
***Power Supplies***
Rz1    102    1020    Rideal    1e-6
Rz2    103    1030    Rideal    1e-6
Ibias    1020    1030    dc    0.65e-3
DzPS    98    1020    diode
Iquies    1020    98    dc    5.85e-3
S1    98    1030    106    113    Switch
R1    1020    99    Rideal    1e7
R2    99    1030    Rideal    1e7
e1    111    110    1020    110    1
e2    110    112    110    1030    1
e3    110    0    99    0    1
*
*
***Inputs***
S2    1    100    106    113    Switch
S3    9    101    106    113    Switch
VOS    1    2    dc    200e-6
IbiasP    110    2    dc    0.6e-12
IbiasN    110    9    dc    0.6e-12
RinCMP    110    2    Rideal    10000e6
RinCMN    9    110    Rideal    10000e6
CinCMP    110    2    0.8e-12
CinCMN    9    110    0.8e-12
IOS    9    2    0.2e-12
RinDiff    9    2    Rideal    10000e3
CinDiff    9    2    4e-12
*
*
***Non-Inverting Input with Clamp***
g1    3    110    110    2    0.001
RInP    3    110    Rideal    1e3
RX1    40    3    Rideal    0.001
DInP    40    41    diode
DInN    42    40    diode
VinP    111    41    dc    3.46
VinN    42    112    dc    0.46
*
*
***Vnoise***
hVn    6    5    Vmeas1    707.10678
Vmeas1    20    110    DC    0
Vvn    21    110    dc    0.65
Dvn    21    20    DVnoisy
hVn1    6    7    Vmeas2    707.10678
Vmeas2    22    110    dc    0
Vvn1    23    110    dc    0.65
Dvn1    23    22    DVnoisy
*
*
***Inoise***
FnIN    9    110    Vmeas3    0.7071068
Vmeas3    51    110    dc    0
VnIN    50    110    dc    0.65
DnIN    50    51    DINnoisy
FnIN1    110    9    Vmeas4    0.7071068
Vmeas4    53    110    dc    0
VnIN1    52    110    dc    0.65
DnIN1    52    53    DINnoisy
*
FnIP    2    110    Vmeas5    0.7071068
Vmeas5    31    110    dc    0
VnIP    30    110    dc    0.65
DnIP    30    31    DIPnoisy
FnIP1    110    2    Vmeas6    0.7071068
Vmeas6    33    110    dc    0
VnIP1    32    110    dc    0.65
DnIP1    32    33    DIPnoisy
*
*
***CMRR***
RcmrrP    3    10    Rideal    1e12
RcmrrN    10    9    Rideal    1e12
g10    11    110    10    110    -1e-10
Lcmrr    11    12    1e-12
Rcmrr    12    110    Rideal    1e3
e4    5    3    11    110    1
*
*
***Power Down***
VPD    111    80    dc    2.6
VPD1    81    0    dc    0.1
RPD    111    106    Rideal    1e6
ePD    80    113    82    0    1
RDP1    82    0    Rideal    1e3
CPD    82    0    1e-10
S5    81    82    83    113    Switch
CDP1    83    0    1e-12
RPD2    106    83    1e6
*
*
***Feedback Pin***
*RF    105    104    Rideal    0.001
*
*
***VFB Stage***
g200    200    110    7    9    1
R200    200    110    Rideal    250
DzSlewP    201    200    DzSlewP
DzSlewN    201    110    DzSlewN
*
*
***Dominant Pole at 280 Hz***
g210    210    110    200    110    6.2719e-6
R210    210    110    Rideal    568.41e6
C210    210    110    1e-012
*
*
***Output Voltage Clamp-1***
RX2    60    210    Rideal    0.001
DzVoutP    61    60    DzVoutP
DzVoutN    60    62    DzVoutN
DVoutP    61    63    diode
DVoutN    64    62    diode
VoutP    65    63    dc    5.289
VoutN    64    66    dc    5.34
e60    65    110    111    110    1.038
e61    66    110    112    110    1.038
*
*
***Pole at 100MHz***
g220    220    110    210    110    0.001
R220    220    110    Rideal    1000
C220    220    110    1.5915e-12
*
***Pole at 550MHz***
g230    230    110    220    110    0.001
R230    230    110    Rideal    1000
C230    230    110    0.2894e-12
*
***Pole at 550MHz***
g240    240    110    230    110    0.001
R240    240    110    Rideal    1000
C240    240    110    0.2894e-12
*
***Pole at 550MHz***
g245    245    110    240    110    0.001
R245    245    110    Rideal    1000
C245    245    110    0.2894e-12
*
***Pole at 580MHz***
g250    250    110    245    110    0.001
R250    250    110    Rideal    1000
C250    250    110    0.2744e-12
*
***Pole at 600MHz***
g255    255    110    250    110    0.001
R255    255    110    Rideal    1000
C255    255    110    0.2653e-12
*
***Pole at 600MHz***
g260    260    110    255    110    0.001
R260    260    110    Rideal    1000
C260    260    110    0.2653e-12
*
***Pole at 1690MHz***
g265    265    110    260    110    0.001
R265    265    110    Rideal    1000
C265    265    110    0.0942e-12
*
***Buffer***
g270    270    110    265    110    0.001
R270    270    110    Rideal    1000
*
***Buffer***
e280    280    110    270    110    1
R280    280    285    Rideal    10
*
***Peak: f=80MHz, Zeta=1.1, Gain=0.2dB***
e290    290    110    285    110    1
R290    290    292    Rideal    10
L290    290    291    9.043e-9
C290    291    292    437.676e-12
R291    292    110    Rideal    429.314
e295    295    110    292    110    1.0233
*
*
***Output Stage***
g300    300    110    295    110    0.001
R300    300    110    Rideal    1000
e301    301    110    300    110    1
Rout    302    303    Rideal     5
Lout    303    310     29e-9
Cout    310    110     6e-12
*
*
***Output Current Limit***
H1    301    304    Vsense1    100
Vsense1    301    302    dc    0
VIoutP    305    304    dc    9.836
VIoutN    304    306    dc    9.836
DIoutP    307    305    diode
DIoutN    306    307    diode
Rx3    307    300    Rideal    0.001
*
*
***Output Clamp-2***
VoutP1    111    73    dc    0.765
VoutN1    74    112    dc    0.765
DVoutP1    75    73    diode
DVoutN1    74    75    diode
RX4    75    310    Rideal    0.001
*
*
***Supply Currents***
FIoVcc    314    110    Vmeas8    1
Vmeas8    310    311    dc    0
R314    110    314    Rideal    1e9
DzOVcc    110    314    diode
DOVcc    102    314    diode
RX5    311    312    Rideal    0.001
FIoVee    315    110    Vmeas9    1
Vmeas9    312    313    dc    0
R315    315    110    Rideal    1e9
DzOVee    315    110    diode
DOVee    315    103    diode
*
*
***Output Switch***
S4    104    313    106    113    Switch
*
*
*** Common Models ***
.model    diode    d(bv=100)
.model    Switch    vswitch(Von=0.105,Voff=0.095,ron=0.001,roff=1e6)
.model    DzVoutP    D(BV=4.3)
.model    DzVoutN    D(BV=4.3)
.model    DzSlewP    D(BV=102.518)
.model    DzSlewN    D(BV=102.518)
.model    DVnoisy    D(IS=1.49e-15 KF=3.61e-16)
.model    DINnoisy    D(IS=1.37e-23 KF=5.70e-19)
.model    DIPnoisy    D(IS=1.37e-23 KF=5.70e-19)
.model    Rideal    res(T_ABS=-273)
*
.ends AD8067

* AD8091 SPICE Macro-model
* Description: Amplifier
* Generic Desc: Single 110MHz rail-to-rail op amp 2.7V
* Developed by: TRW / ADI
* Revision History: 08/10/2012 - Updated to new header style
* 0.0 (02/2002)
* Copyright 1998, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
* CMRR IS NOT MODELED
*
* Parameters modeled include:
* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V)
*
* END Notes
*
* Node assignments
*                 noninverting input
*                 |       inverting input
*                 |       |       positive supply
*                 |       |       |       negative supply
*                 |       |       |       |       output
*                 |       |       |       |       |
*                 |       |       |       |       |
.SUBCKT AD8091    1       2       99      50      45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
Q1  4  3  5 QPI
Q2  6  2  7 QPI
RC1   50  4 20.5k
RC2   50  6 20.5k
RE1    5  8 5k
RE2    7  8 5k
EOS    3  1 POLY(1) 53 98 1.7E-3 1
IOS    1  2 0.1u
FNOI1  1  0 VMEAS2 1E-4
FNOI2  2  0 VMEAS2 1E-4

CPAR1  3 50 1.7p
CPAR2  2 50 1.7p
VCMH1 99  9 1
VCMH2 99 10 1
D1     5  9  DX
D2     7 10 DX
IBIAS 99  8 73u
*
* INTERNAL VOLTAGE REFERENCE
*
EREF1 98  0 POLY(2) 99 0 50 0 0 0.5 0.5
EREF2 97  0 POLY(2)  1 0 2 0 0 0.5 0.5
GREF2 97 0 97 0 1E-6
*
*VOLTAGE NOISE STAGE
*
DN1 51 52 DNOI1
VN1 51 98 0.61
VMEAS 52 98 0
RNOI1 52 98 6.5E-3

H1 53 98 VMEAS 1
RNOI2 53 98 1
*
*CURRENT NOISE STAGE
*
DN2 61 62 DNOI2
VN2 61 98 0.545
VMEAS2 62 98 0
RNOI3  62 98 2E-4
*
* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz
*
G1   98 20 4 6 1E-3
RP1  98 20 550
CP1  98 20 3p
*
* GAIN STAGE WITH DOMINANT POLE
*
G4   98 30 20 98 2.6E-3
RG1 30 98 155k
CF1  30 45 13.5p
D5 31 99 DX
D6 50 32 DX
V1 31 30 0.6
V2 30 32 0.6
*
* OUTPUT STAGE
*
Q3  45 42 99 QPOX
Q4  45 44 50 QNOX
EO3 99 42 POLY(1) 98 30 0.7175 0.5
EO4 44 50 POLY(1) 30 98 0.7355 0.5
*
* MODELS
*
.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6)
.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3)
.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6)
.MODEL DX D(IS=1E-16)
.MODEL DZ D(IS=1E-14,BV=6.6)
.MODEL DNOI1 D(KF=9E-10)
.MODEL DNOI2 D(KF=1E-8)
.ENDS AD8091






* AD8092 SPICE Macro-model
* Description: Amplifier
* Generic Desc: Dual 110MHz rail-to-rail op amp 2.7V
* Developed by: TRW / ADI
* Revision History: 08/10/2012 - Updated to new header style
* 0.0 (02/2002)
* Copyright 1998, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
* CMRR IS NOT MODELED
*
* Parameters modeled include:
* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V)
*
* END Notes
*
* Node assignments
*                 noninverting input
*                 |       inverting input
*                 |       |       positive supply
*                 |       |       |       negative supply
*                 |       |       |       |       output
*                 |       |       |       |       |
*                 |       |       |       |       |
.SUBCKT AD8092    1       2       99      50      45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
Q1  4  3  5 QPI
Q2  6  2  7 QPI
RC1   50  4 20.5k
RC2   50  6 20.5k
RE1    5  8 5k
RE2    7  8 5k
EOS    3  1 POLY(1) 53 98 1.7E-3 1
IOS    1  2 0.1u
FNOI1  1  0 VMEAS2 1E-4
FNOI2  2  0 VMEAS2 1E-4

CPAR1  3 50 1.7p
CPAR2  2 50 1.7p
VCMH1 99  9 1
VCMH2 99 10 1
D1     5  9  DX
D2     7 10 DX
IBIAS 99  8 73u
*
* INTERNAL VOLTAGE REFERENCE
*
EREF1 98  0 POLY(2) 99 0 50 0 0 0.5 0.5
EREF2 97  0 POLY(2)  1 0 2 0 0 0.5 0.5
GREF2 97 0 97 0 1E-6
*
*VOLTAGE NOISE STAGE
*
DN1 51 52 DNOI1
VN1 51 98 0.61
VMEAS 52 98 0
RNOI1 52 98 6.5E-3

H1 53 98 VMEAS 1
RNOI2 53 98 1
*
*CURRENT NOISE STAGE
*
DN2 61 62 DNOI2
VN2 61 98 0.545
VMEAS2 62 98 0
RNOI3  62 98 2E-4
*
* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz
*
G1   98 20 4 6 1E-3
RP1  98 20 550
CP1  98 20 3p
*
* GAIN STAGE WITH DOMINANT POLE
*
G4   98 30 20 98 2.6E-3
RG1 30 98 155k
CF1  30 45 13.5p
D5 31 99 DX
D6 50 32 DX
V1 31 30 0.6
V2 30 32 0.6
*
* OUTPUT STAGE
*
Q3  45 42 99 QPOX
Q4  45 44 50 QNOX
EO3 99 42 POLY(1) 98 30 0.7175 0.5
EO4 44 50 POLY(1) 30 98 0.7355 0.5
*
* MODELS
*
.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6)
.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3)
.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6)
.MODEL DX D(IS=1E-16)
.MODEL DZ D(IS=1E-14,BV=6.6)
.MODEL DNOI1 D(KF=9E-10)
.MODEL DNOI2 D(KF=1E-8)
.ENDS AD8092






* AD811 SPICE Macro-model
* Description: Amplifier
* Generic Desc: High Performance Video Op Amp
* Developed by: JCB / PMI
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/1991)
* Copyright 1991, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*              non-inverting input
*              | inverting input
*              | | positive supply
*              | | |  negative supply
*              | | |  |  output
*              | | |  |  |
.SUBCKT AD811  1 2 99 50 28
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
R1   99  8     1E3
R2   10 50     1E3
V1   99  9     11
D1   9   8     DX
V2   11 50     11
D2   10 11     DX
I1   99  5     920E-6
I2   4  50     920E-6
Q1   5   5  3  QN
Q2   4   4  3  QP
Q3   8   5 30  QN
Q4   10  4 30  QP
*
* INPUT ERROR SOURCES
*
GB1  99  1     POLY(1)  1  22  2E-6  1E-6
GB2  99 30     POLY(1)  1  22  2E-6  1E-6
VOS  3   1     500E-6
LS1  30  2     4E-8
CS1  99  2     0.5E-12
CS2  50  2     0.5E-12
CIN  1  50     2E-12
*
EREF 97  0     22  0  1
*
* GAIN STAGE & DOMINANT POLE
*
R5   12 97     1.5E6
C3   12 97     3.9E-12
G1   97 12     99  8  1E-3
G2   12 97     10 50  1E-3
V3   99 13     2.9
V4   14 50     2.9
D3   12 13     DX
D4   14 12     DX
*
* POLE AT 400 MHZ
*
R8  17 97     1E6
C4  17 97     0.530E-15
G4  97 17     12 22  1E-6
*
* ZERO AT 150 MHZ
*
R20 18 19     1E6
R21 19 97     1
C20 18 19     -.530E-15
E20 18 97     17 22  1E6
*
* POLE AT 200 MHZ
*
R12 21 97     1E6
C8  21 97     0.395E-15
G8  97 21     19 22  1E-6
*
* OUTPUT STAGE
*
ISY 99 50     14.7E-3
R13 22 99     16.7E3
R14 22 50     16.7E3
R15 27 99     22
R16 27 50     22
L2  27 28     1E-8
G9  25 50     21 27  45.45E-3
G10 26 50     27 21  45.45E-3
G11 27 99     99 21  45.45E-3
G12 50 27     21 50  45.45E-3
V5  23 27     1.3
V6  27 24     1.3
D5  21 23     DX
D6  24 21     DX
D7  99 25     DX
D8  99 26     DX
D9  50 25     DY
D10 50 26     DY
*
* MODELS USED
*
.MODEL QN   NPN(BF=1E9 IS=1E-15)
.MODEL QP   PNP(BF=1E9 IS=1E-15)
.MODEL DX   D(IS=1E-15)
.MODEL DY   D(IS=1E-15 BV=50)
.ENDS AD811






* AD815 Spice Macro-model
* Description: Amplifier
* Generic Desc: High output differential driver amp
* Developed by:
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (09/1996)
* Copyright 1996, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.
* Use of this model indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*     distortion is not characterized
*
* Parameters modeled include:
*     closed loop gain and phase vs bandwidth
*     output current and voltage limiting
*     offset voltage (is static, will not vary with vcm)
*     ibias (again, is static, will not vary with vcm)
*     slew rate and step response performance
*     (slew rate is based on 10-90% of step response)
*     current on output will be reflected to the supplies
*     vnoise, referred to the input
*     inoise, referred to the input
*
* END Notes
*
* Node assignments
*                non-inverting input
*                | inverting input
*                | | positive supply
*                | | |  negative supply
*                | | |  |  output
*                | | |  |  |
.SUBCKT AD815    1 2 99 50 61
*#ASSOC Category="Op-amps" symbol=opamp


***** Input Stage

q1 50 41 4 qp1
q2 99 41 3 qn1
i1 99 4 1e-4
i2 3 50 1e-4

fni 99 2 vn2 1
fnn 99 1 vn2 0.1

*ibneg 2 99 10e-6
*ibpos 1 99 2e-6

cin1 4 88 1.4pf
cin2 2 88 1.4pf

q3 9 4 2 qn2
q4 10 3 2 qp2

rxxa 99 4 28k
rxxb 3 50 28k


VT1 99 9 0   ;ammeters for monitoring
VT2 50 10 0  ;current thru Q3, Q4
eos 41 1 poly(1) 43 88 5e-3 1

***** internal vnoise source

dn1 42 88 dnv
rn1 42 88 5e-3
vn1 42 88 0

hn1 43 88 vn1 1
rn2 43 88 1

***** internal inoise source

dn2 72 88 dniinv
rn3 72 88 50
vn2 72 88 0

hn2 73 88 vn2 1
rn4 73 88 1

***** internal reference

Eref 88 0 poly(2) 99 0 50 0 0 0.5 0.5

***** gain stage/dominant pole/clamp circuitry

f3 88 31 vt1 0.7e-4
f4 88 31 vt2 0.7e-4
dgain1 88 31 dy
dgain2 31 88 dy

egain1 28 88 31 88 143000
r3 28 29 5
c1 29 88 4500nf

vc1 99 45 3.65
vc2 46 50 3.65
dc1 29 45 dx
dc2 46 29 dx

***** pole at 100MHz

egain2 32 88 88 29 1
r4 32 44 0.001
c3 44 88 1500000p

***** buffer to output stage

gbuf 34 88 44 88 1e-2
re1 34 88 100

***** output stage

fo1 88 110 vcd 1
do1 110 111 dx
do2 112 110 dx
vi1 111 88 0
vi2 88 112 0

fsy 99 50 poly(2) vi1 vi2 5.61e-4 1 1

go3 60 99 99 34 0.385
go4 50 60 34 50 0.385
r03 60 99 2.6
r04 60 50 2.6
vcd 60 62 0
lo1 62 61 1e-10
ro2 61 88 1e9
do5 34 70 dx
do6 71 34 dx
vo1 70 60 0.45
vo2 60 71 0.45

.model dx d(is=1e-13 kf=1e-30 af=0)
.model dy d(is=26e-9 kf=1e-30 af=0)
.model dnv d(is=1e-15 kf=2e-15 af=0)
.model dniinv d(is=1e-15 kf=1e-19 af=0)
.model qn1 npn(bf=200 kf=1e-30 af=0)
.model qn2 npn(bf=200 kf=1e-30 af=0)
.model qp1 pnp(bf=200 kf=1e-30 af=0)
.model qp2 pnp(bf=200 kf=1e-30 af=0)
.ends ad815
*
.subckt AD823 1 2 3 4 5
C1 N006 X {Cf}
A1 N005 0 M M M M X M OTA g={Ga} Iout={Islew} en=16n enk=250 Vhigh=1e308 Vlow=-1e308
B1 3 N006 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0)
B2 N006 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0)
D21 X 3 ESD
D22 4 X ESD
D5 N006 3 X1
D6 4 N006 X2
G2 0 M 3 0 500µ
R4 M 0 1K noiseless
G3 0 M 4 0 500µ
S1 X M 4 3 SD
A2 2 1 0 0 0 0 0 0 OTA g=0 in=1f ink=100 incm=.08f incmk=100
C11 3 1 .9p Rpar=2e13 noiseless
C4 N004 0 5p Rpar=1K noiseless
L1 N004 N005 5µ
C6 N005 0 5p Rpar=1K noiseless
I3 3 4 50µ load
C2 3 N006 1p
C3 3 5 1p
C7 5 4 1p
C8 N006 4 1p
C5 1 4 .9p Rpar=2e13 noiseless
C10 2 4 .9p Rpar=2e13 noiseless
C12 3 2 .9p Rpar=2e13 noiseless
B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)+-.3, .1)+100n*V(1)
B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)-1.1,.1), V(4)+-.3, .1)+100n*V(2)
D3 3 4 IQ
I1 3 2 5p load
I2 3 1 5p load
D1 5 N006 A
.param Cf = 1p
.param Ro       =  11K
.param Avol    =  149K
.param RL       =  2K
.param AVmid =  16
.param FmidA = 1Meg
.param Zomid  =  .2
.param FmidZ  = 100K
.param Vslew  = 25Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.param Gbx = Gb
.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless)
.model X2 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless)
.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless)
.model IQ D(Ron=1K Roff=10Meg epsilon=1 Ilimit=2.6m noiseless)
.model 1uA D(Ron=1Meg Vfwd=2 epsilon=1 Ilimit=1u noiseless)
.model A D(Ron=20 Roff=20 epsilon=10m Ilimit=80m revIlimit=60m Vrev=0 noiseless)
.ends AD823
*
*
*
.subckt AD823A 1 2 3 4 5
C1 N006 X {Cf}
A1 N005 0 M M M M X M OTA g={Ga} Iout={Islew} en=16n enk=250 Vhigh=1e308 Vlow=-1e308
B1 3 N006 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0)
B2 N006 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0)
D21 X 3 ESD
D22 4 X ESD
D5 N006 3 X1
D6 4 N006 X2
G2 0 M 3 0 500µ
R4 M 0 1K noiseless
G3 0 M 4 0 500µ
S1 X M 4 3 SD
A2 2 1 0 0 0 0 0 0 OTA g=0 in=1f ink=100 incm=.08f incmk=100
C11 3 1 .9p Rpar=2e13 noiseless
C4 N004 0 5p Rpar=1K noiseless
L1 N004 N005 5µ
C6 N005 0 5p Rpar=1K noiseless
I3 3 4 50µ load
C2 3 N006 1p
C3 3 5 1p
C7 5 4 1p
C8 N006 4 1p
C5 1 4 .9p Rpar=2e13 noiseless
C10 2 4 .9p Rpar=2e13 noiseless
C12 3 2 .9p Rpar=2e13 noiseless
B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)+-.3, .1)+100n*V(1)
B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)-1.1,.1), V(4)+-.3, .1)+100n*V(2)
D3 3 4 IQ
I1 3 2 5p load
I2 3 1 5p load
D1 5 N006 A
.param Cf = 1p
.param Ro       =  11K
.param Avol    =  149K
.param RL       =  2K
.param AVmid =  16
.param FmidA = 1Meg
.param Zomid  =  .2
.param FmidZ  = 100K
.param Vslew  = 25Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.param Gbx = Gb
.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless)
.model X2 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless)
.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless)
.model IQ D(Ron=1K Roff=10Meg epsilon=1 Ilimit=2.6m noiseless)
.model 1uA D(Ron=1Meg Vfwd=2 epsilon=1 Ilimit=1u noiseless)
.model A D(Ron=20 Roff=20 epsilon=10m Ilimit=80m revIlimit=60m Vrev=0 noiseless)
.ends AD823A
*
*
.subckt AD8510 1 2 3 4 5
A1 2 1 0 0 0 0 0 0 OTA g=0 in=.01p ink=10 incm=.001p incmk=10
C6 3 1 2.875p Rpar=62.5G noiseless
C1 2 1 6.25p noiseless
G1 0 M 3 0 1m
G2 0 M 4 0 1m
R3 M 0 1K noiseless
S1 N005 M 4 3 UVLO
D3 N005 3 X1
D4 4 N005 X2
D2 3 4 IQ
C7 1 4 2.875p Rpar=62.5G noiseless
C8 3 2 2.875p Rpar=62.5G noiseless
C9 2 4 2.875p Rpar=62.5G noiseless
I1 3 2 21p load
I2 3 1 21p load
A2 0 N006 M M M M N005 M OTA g=82u Iout=18u Isink=-28u en=7.55n enk=174.5 Vlow=-1e308 Vhigh=1e308 Cout= 1.3p asym
C10 N006 0 10p Rpar=1K noiseless
L1 N003 N006 10p
B1 N003 0 I=2m*dnlim(uplim(V(2),V(3)-(2.64-25m*V(3,4)),.1), V(4)+3.65-75m*V(3,4)-.01, .1)+100n*V(2)
B2 0 N003 I=2m*dnlim(uplim(V(1),V(3)-(2.65-25m*V(3,4)),.1), V(4)+3.65-75m*V(3,4), .1)+100n*V(1)
C5 N003 0 10p Rpar=1K noiseless
M1 3 N004 5 5 N temp=27
M2 4 N004 5 5 P temp=27
C3 3 5 2p
C4 5 4 2p
C13 5 N004 5p Rser=1Meg noiseless
R5 N004 N005 1Meg
D1 5 N004 Y2A
D6 5 N004 Y2B
D9 N004 5 Y1
.model X1 D(Ron=1K Roff=100G Vfwd=-0.8 epsilon=.1 noiseless)
.model X2 D(Ron=10 Roff=100G Vfwd=-0.12 epsilon=.1 noiseless)
.model Y1 D(Ron=18k Roff=100G Vfwd=650m epsilon=500m noiseless)
.model Y2A D(Ron=25k Roff=100G Vfwd=250m epsilon=500m noiseless)
.model Y2B D(Ron=5k Roff=100G Vfwd=450m epsilon=500m noiseless)
.model N VDMOS(Vto=-40m Kp=100m Ksubthres=100m noiseless)
.model P VDMOS(Vto=40m Kp=300m pchan Ksubthres=100m noiseless)
.model UVLO SW(Ron=1K Roff=3G Vt=-3.75 Vh=.25 noiseless)
.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=0.08m noiseless)
.ends AD8510
*

* AD8515 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 1.8/5V, CMOS, OP, Low Pwr, RRIO, 1X
* Developed by: RM / ADSiv
* Revision History: 08/10/2012 - Updated to new header style
* 0.0 (07/2003)
* Copyright 2002, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8515      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=81.24E-6
M2   6  2  8  8 PIX L=1E-6 W=81.24E-6
M3  11  7 10 10 NIX L=1E-6 W=81.24E-6
M4  12  2 10 10 NIX L=1E-6 W=81.24E-6
RC1  4 14 0.001E+3
RC2  6 16 0.001E+3
RC3 17 11 0.001E+3
RC4 18 12 0.001E+3
RC5 14 50 10E+3
RC6 16 50 10E+3
RC7 99 17 10E+3
RC8 99 18 10E+3
*Set the secondary pole at 17MHz using c1,c2 and RC5..
C1  14 16 0.70E-12
C2  17 18 0.70E-12
I1  99  8 60E-6
I2  10 50 60E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-3 1 1 1
IOS  1  2 1E-12
*
* CMRR 75dB, ZERO AT 20kHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 281.170E+3
CCM1 21 22 2.83E-11
RCM2 22 98 50
*
* PSRR=85dB, ZERO AT 200Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 795.774E+3
CPS3 72 73 10.0E-9
RPS4 73 98 44.74
*
* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 22
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 4E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 17MHz, POLE AT 83.9MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .6270 .6270
R2 32 33 2.378E+3
R3 33 98 9.362E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 6.3E-5
R1 30 98 1.48E+8
CF 45 30 13.2E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=3.23E-3
M6  45 47 50 50 NOX L=1E-6 W=3.58E-3
EG1 99 46 POLY(1) (98,30) 0.4394 1
EG2 47 50 POLY(1) (30,98) 0.4336 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8515
*
*$





* AD8538 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 1X
* Developed by: ADISJ  HH
* Revision History: 08/10/2012 - Updated to new header style
* 1.1 (10/2007)
* Copyright 2007, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*                  noninverting input
*                  |   inverting input
*                  |   |    positive supply
*                  |   |    |    negative supply
*                  |   |    |    |    output
*                  |   |    |    |    |
*                  |   |    |    |    |
.SUBCKT AD8538     1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=2.844E-05
M2  16  2  8  8 PIX L=1E-6 W=2.844E-05
M3  17  7 10 10 NIX L=1E-6 W=2.844E-05
M4  18  2 10 10 NIX L=1E-6 W=2.844E-05
RD1 14 50 2.667E+04
RD2 16 50 2.667E+04
RD3 99 17 2.667E+04
RD4 99 18 2.667E+04
C1  14 16 6.700E-12
C2  17 18 6.700E-12
I1  99  8 1.500E-05
I2  10 50 1.500E-05
V1  99  9 0.997E+00
V2  13 50 0.997E+00
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(4) (22,98) (73,98) (83,98) (70,98) 5.00E-06 1 1 1.2 1
IOS 1 2 1.00E-11
*
*CMRR=135dB, POLE AT 9 Hz ZERO AT 2.5 MHz
*
E1  21 98 POLY(2) (1,98) (2,98) 0 7.113E-02 7.113E-02
R10 21 22 1.592E+04
R20 22 98 1.989E-02
C10 21 22 1.000E-06
*
* PSRR=95dB, POLE AT 100 Hz
*
EPSY 72 98 POLY(1) (99,50) -8.89E-01 1.78E-00
CPS3 72 73 1.00E-06
RPS3 72 73 3.98E+04
RPS4 73 98 3.98E-02
*
* VOLTAGE NOISE REFERENCE OF 60nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98  16.45E-05
*
HN  81 98 VN1 60E+00
RNHH1 81 183 5.3
CHH1 183 98 1uF
*
CHH2 183 184 2.7E-07
RNHH2 184 98 10
*
RNHH3 184 83 100k
CHH3 83 98 2.41E-10
*
* FLICKER NOISE CORNER = 0.000001 Hz
D5  69 98 DNOISE
VSN 69 98 DC 0.6551
H1  70 98 POLY(1) VSN 1.00E-03 1.00E+00
RN  70 98 1
*
* INTERNAL VOLTAGE REFERENCE
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) -242.5E-6 2.5E-06
EVP  97 98 POLY(1) (99,50) 0 0.5
EVN  51 98 POLY(1) (50,99) 0 0.5
*
* GAIN STAGE
G1 98 30 POLY(2) (14,16) (17,18) 0 2.678E-02 2.678E-02
R1 30 98 1.00E+06
V3 32 30 -3.603E-00
V4 30 33 -3.733E-00
EZ (145 0) (45 0) 1
CF 145 31 4.400E-08
RZ  30 31 3.800E+00
D3 32 97 DX
D4 51 33 DX
*
* OUTPUT STAGE
M5  45 46 99 99 POX L=1E-6 W=2.238E-05
M6  45 47 50 50 NOX L=1E-6 W=2.152E-05
EG1 99 46 POLY(1) (98,30) 1.299E+00 1
EG2 47 50 POLY(1) (30,98) 1.217E+00 1
*
* MODELS
.MODEL POX PMOS (LEVEL=2,KP=6.00E-05,VTO=-0.6,LAMBDA=0.02,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=8.00E-05,VTO=+0.6,LAMBDA=0.02,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-0.5,LAMBDA=0.02)
.MODEL NIX NMOS (LEVEL=2,KP=5.00E-05,VTO=0.5, LAMBDA=0.02)
.MODEL DX D(IS=1E-14,RS=5)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=2.50E-18)
*
.ENDS AD8538
*
*$





* AD8539 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 2X
* Developed by: ADISJ  HH
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/2010)
* Copyright 2007, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*                  noninverting input
*                  |   inverting input
*                  |   |    positive supply
*                  |   |    |    negative supply
*                  |   |    |    |    output
*                  |   |    |    |    |
*                  |   |    |    |    |
.SUBCKT AD8539     1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=2.844E-05
M2  16  2  8  8 PIX L=1E-6 W=2.844E-05
M3  17  7 10 10 NIX L=1E-6 W=2.844E-05
M4  18  2 10 10 NIX L=1E-6 W=2.844E-05
RD1 14 50 2.667E+04
RD2 16 50 2.667E+04
RD3 99 17 2.667E+04
RD4 99 18 2.667E+04
C1  14 16 6.700E-12
C2  17 18 6.700E-12
I1  99  8 1.500E-05
I2  10 50 1.500E-05
V1  99  9 0.997E+00
V2  13 50 0.997E+00
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(4) (22,98) (73,98) (83,98) (70,98) 5.00E-06 1 1 1.2 1
IOS 1 2 1.00E-11
*
*CMRR=135dB, POLE AT 9 Hz ZERO AT 2.5 MHz
*
E1  21 98 POLY(2) (1,98) (2,98) 0 7.113E-02 7.113E-02
R10 21 22 1.592E+04
R20 22 98 1.989E-02
C10 21 22 1.000E-06
*
* PSRR=95dB, POLE AT 100 Hz
*
EPSY 72 98 POLY(1) (99,50) -8.89E-01 1.78E-00
CPS3 72 73 1.00E-06
RPS3 72 73 3.98E+04
RPS4 73 98 3.98E-02
*
* VOLTAGE NOISE REFERENCE OF 60nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98  16.45E-05
*
HN  81 98 VN1 60E+00
RNHH1 81 183 5.3
CHH1 183 98 1uF
*
CHH2 183 184 2.7E-07
RNHH2 184 98 10
*
RNHH3 184 83 100k
CHH3 83 98 2.41E-10
*
* FLICKER NOISE CORNER = 0.000001 Hz
D5  69 98 DNOISE
VSN 69 98 DC 0.6551
H1  70 98 POLY(1) VSN 1.00E-03 1.00E+00
RN  70 98 1
*
* INTERNAL VOLTAGE REFERENCE
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) -242.5E-6 2.5E-06
EVP  97 98 POLY(1) (99,50) 0 0.5
EVN  51 98 POLY(1) (50,99) 0 0.5
*
* GAIN STAGE
G1 98 30 POLY(2) (14,16) (17,18) 0 2.678E-02 2.678E-02
R1 30 98 1.00E+06
V3 32 30 -3.603E-00
V4 30 33 -3.733E-00
EZ (145 0) (45 0) 1
CF 145 31 4.400E-08
RZ  30 31 3.800E+00
D3 32 97 DX
D4 51 33 DX
*
* OUTPUT STAGE
M5  45 46 99 99 POX L=1E-6 W=2.238E-05
M6  45 47 50 50 NOX L=1E-6 W=2.152E-05
EG1 99 46 POLY(1) (98,30) 1.299E+00 1
EG2 47 50 POLY(1) (30,98) 1.217E+00 1
*
* MODELS
.MODEL POX PMOS (LEVEL=2,KP=6.00E-05,VTO=-0.6,LAMBDA=0.02,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=8.00E-05,VTO=+0.6,LAMBDA=0.02,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-0.5,LAMBDA=0.02)
.MODEL NIX NMOS (LEVEL=2,KP=5.00E-05,VTO=0.5, LAMBDA=0.02)
.MODEL DX D(IS=1E-14,RS=5)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=2.50E-18)
*
.ENDS AD8539
*
*$





* AD8541 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Pwr, RRIO, 1X
* Developed by: TAM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (06/1998)
* Copyright 1998, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*      noninverting input
*      |   inverting input
*      |   |    positive supply
*      |   |    |    negative supply
*      |   |    |    |    output
*      |   |    |    |    |
*      |   |    |    |    |
.SUBCKT AD8541   1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  1 8 8 PIX L=0.6E-6 W=16E-6
M2   6  7 8 8 PIX L=0.6E-6 W=16E-6
M3  11  1 10 10 NIX L=0.6E-6 W=16E-6
M4  12  7 10 10 NIX L=0.6E-6 W=16E-6
RC1  4 50 20E3
RC2  6 50 20E3
RC3 99 11 20E3
RC4 99 12 20E3
C1   4  6 1.5E-12
C2  11 12 1.5E-12
I1  99  8 1E-5
I2  10 50 1E-5
V1  99  9 0.2
V2  13 50 0.2
D1   8  9 DX
D2  13 10 DX
EOS  7  2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 64dB, ZERO AT 20kHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 79.6E3
CCM1 21 22 100E-12
RCM2 22 98 50
*
* PSRR=90dB, ZERO AT 200Hz
*
RPS1 70  0 1E6
RPS2 71  0 1E6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1.59E6
CPS3 72 73 500E-12
RPS4 73 98 25
*
* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz)
*
VN1 80 0 0
RN1 80 0 16.45E-3
HN  81 0 VN1 35
RN2 81 0 1
*
* INTERNAL VOLTAGE REFERENCE
*
VFIX 90 98 DC 1
S1   90 91 (50,99) VSY_SWITCH
VSN1 91 92 DC 0
RSY  92 98 1E3
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 POLY(1) (99,50) 0 3.7E-6
*
* ADAPTIVE GAIN STAGE
* AT Vsy>+4.2, AVol=45  V/mv
* AT Vsy<+3.8, AVol=450 V/mv
*
G1  98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5
VR1 30 31 DC 0
H1  31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9
CF  45 30 10E-12
D3  30 99 DX
D4  50 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=0.6E-6 W=375E-6
M6  45 47 50 50 NOX L=0.6E-6 W=500E-6
EG1 99 46 POLY(1) (98,30) 1.05 1
EG2 47 50 POLY(1) (30,98) 1.04 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067)
.MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067)
.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31)
.MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31)
.MODEL DX D(IS=1E-14)
.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5)
.ENDS AD8541





* AD8542 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Pwr, RRIO, 2X
* Developed by: TAM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (06/1998)
* Copyright 1998, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*      noninverting input
*      |   inverting input
*      |   |    positive supply
*      |   |    |    negative supply
*      |   |    |    |    output
*      |   |    |    |    |
*      |   |    |    |    |
.SUBCKT AD8542   1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  1 8 8 PIX L=0.6E-6 W=16E-6
M2   6  7 8 8 PIX L=0.6E-6 W=16E-6
M3  11  1 10 10 NIX L=0.6E-6 W=16E-6
M4  12  7 10 10 NIX L=0.6E-6 W=16E-6
RC1  4 50 20E3
RC2  6 50 20E3
RC3 99 11 20E3
RC4 99 12 20E3
C1   4  6 1.5E-12
C2  11 12 1.5E-12
I1  99  8 1E-5
I2  10 50 1E-5
V1  99  9 0.2
V2  13 50 0.2
D1   8  9 DX
D2  13 10 DX
EOS  7  2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 64dB, ZERO AT 20kHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 79.6E3
CCM1 21 22 100E-12
RCM2 22 98 50
*
* PSRR=90dB, ZERO AT 200Hz
*
RPS1 70  0 1E6
RPS2 71  0 1E6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1.59E6
CPS3 72 73 500E-12
RPS4 73 98 25
*
* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz)
*
VN1 80 0 0
RN1 80 0 16.45E-3
HN  81 0 VN1 35
RN2 81 0 1
*
* INTERNAL VOLTAGE REFERENCE
*
VFIX 90 98 DC 1
S1   90 91 (50,99) VSY_SWITCH
VSN1 91 92 DC 0
RSY  92 98 1E3
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 POLY(1) (99,50) 0 3.7E-6
*
* ADAPTIVE GAIN STAGE
* AT Vsy>+4.2, AVol=45  V/mv
* AT Vsy<+3.8, AVol=450 V/mv
*
G1  98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5
VR1 30 31 DC 0
H1  31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9
CF  45 30 10E-12
D3  30 99 DX
D4  50 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=0.6E-6 W=375E-6
M6  45 47 50 50 NOX L=0.6E-6 W=500E-6
EG1 99 46 POLY(1) (98,30) 1.05 1
EG2 47 50 POLY(1) (30,98) 1.04 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067)
.MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067)
.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31)
.MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31)
.MODEL DX D(IS=1E-14)
.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5)
.ENDS AD8542





* AD8544 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Pwr, RRIO, 4X
* Developed by: TAM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (06/1998)
* Copyright 1998, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*      noninverting input
*      |   inverting input
*      |   |    positive supply
*      |   |    |    negative supply
*      |   |    |    |    output
*      |   |    |    |    |
*      |   |    |    |    |
.SUBCKT AD8544   1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  1 8 8 PIX L=0.6E-6 W=16E-6
M2   6  7 8 8 PIX L=0.6E-6 W=16E-6
M3  11  1 10 10 NIX L=0.6E-6 W=16E-6
M4  12  7 10 10 NIX L=0.6E-6 W=16E-6
RC1  4 50 20E3
RC2  6 50 20E3
RC3 99 11 20E3
RC4 99 12 20E3
C1   4  6 1.5E-12
C2  11 12 1.5E-12
I1  99  8 1E-5
I2  10 50 1E-5
V1  99  9 0.2
V2  13 50 0.2
D1   8  9 DX
D2  13 10 DX
EOS  7  2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 64dB, ZERO AT 20kHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 79.6E3
CCM1 21 22 100E-12
RCM2 22 98 50
*
* PSRR=90dB, ZERO AT 200Hz
*
RPS1 70  0 1E6
RPS2 71  0 1E6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1.59E6
CPS3 72 73 500E-12
RPS4 73 98 25
*
* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz)
*
VN1 80 0 0
RN1 80 0 16.45E-3
HN  81 0 VN1 35
RN2 81 0 1
*
* INTERNAL VOLTAGE REFERENCE
*
VFIX 90 98 DC 1
S1   90 91 (50,99) VSY_SWITCH
VSN1 91 92 DC 0
RSY  92 98 1E3
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 POLY(1) (99,50) 0 3.7E-6
*
* ADAPTIVE GAIN STAGE
* AT Vsy>+4.2, AVol=45  V/mv
* AT Vsy<+3.8, AVol=450 V/mv
*
G1  98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5
VR1 30 31 DC 0
H1  31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9
CF  45 30 10E-12
D3  30 99 DX
D4  50 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=0.6E-6 W=375E-6
M6  45 47 50 50 NOX L=0.6E-6 W=500E-6
EG1 99 46 POLY(1) (98,30) 1.05 1
EG2 47 50 POLY(1) (30,98) 1.04 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067)
.MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067)
.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31)
.MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31)
.MODEL DX D(IS=1E-14)
.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5)
.ENDS AD8544





* AD8546 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 3/18V, CMOS, OP, Low Pwr, RRIO, 2X
* Developed by: VW ADSJ
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (01/2011)
* Copyright 2010, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*                       noninverting input
*                       |   inverting input
*                       |   |    positive supply
*                       |   |    |   negative supply
*                       |   |    |   |   output
*                       |   |    |   |   |
*                       |   |    |   |   |
.SUBCKT AD8546          1   2   99  50  45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L= 1.000E-06 W= 1.532E-04
M2   6  2  8  8 PIX L= 1.000E-06 W=1.532E-04
M3  14  7 18 18 NIX L=1.000E-06 W=4.085E-04
M4  16  2 18 18 NIX L=1.000E-06 W=4.085E-04
RD1  4 50 2.0E+04
RD2  6 50 2.0E+04
RD3 99 14 2.0E+04
RD4 99 16 2.0E+04
C1   4  6 9.4750E-12
C2  14 16 9.4750E-12
I1  99  8 1.722E-05
I2  18 50 1.722E-05
V1  99  9 1.429E-01
V2  19 50 1.429E-01
D1   8  9 DX
D2  19 18 DX
EOS  7  1 POLY(4) (73,98) (22,98) (81,98) (83,98) 3E-03 1 1 1 1
IOS  1  2 2.000E-11
CDiff  1 2 3.5E-12
Cin1   1 50 10.5E-12
Cin2   2 50 10.5E-12
*
*
* CMRR
*
E1  72 98 POLY(2) (1,98) (2,98) 0 6.817E-02 6.817E-02
R10 72 73 2.894E+02
R20 73 98 1.592E-02
C10 72 73 1.000E-06
*
* PSRR
*
EPSY 21 98 POLY(1) (99,50) -1.757E+02 9.762E+00
RPS1 21 22 3.183E+03
RPS2 22 98 7.958E-01
CPS1 21 22 1.000E-06
*
* VOLTAGE NOISE
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 4.5165E+01
RN2 81 98 1
*
* FLICKER NOISE
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1.000E-03 1.000E+00
RFN 83 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) -1.74975E-05 5.031E-08
EVP  97 98 POLY(1) (99,50) -1.05 0.25
EVN  51 98 POLY(1) (50,99) 1.45 0.3

*
* GAIN STAGE
*
G1 98 30 POLY(2) (4,6) (14,16) 0 5.693E-05 5.693E-05
R1 30 98 1.000E+06
RZ 30 31 8.2720E+03
CF 45 31 5.605E-10
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L= 2.000E-06 W=2.450E-04
M6  45 47 50 50 NOX L= 2.000E-06 W=1.591E-04
EG1 99 46 POLY(1) (98,30) 3.347E-01 1
EG2 47 50 POLY(1) (30,98) 3.216E-01 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=1.000E-05,VTO=-0.3,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=4.000E-05,VTO=+0.3,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=4.000E-05,VTO=-0.5,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=1.500E-05,VTO=0.5,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=0.1)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.5E-10)
*
*
.ENDS AD8546
*
*$






* AD8548 SPICE Macro-model Typical values at Vsy=18V
* Description: Amplifier
* Generic Desc: 2.7/18V, CMOS, RRIO
* Developed by: VW
* Revision History:
* 1.0 (8/2012) - VW - initial release
* Copyright 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html
* for License Statement. Use of this model indicates your acceptance
* of the terms and provisions in the License Statement.
*
*
* BEGIN Notes:
*
* Not Modeled:
* Temperature effects
*
* END Notes
*
* Node Assignments
*                  noninverting input
*                  |   inverting input
*                  |   |    positive supply
*                  |   |    |    negative supply
*                  |   |    |    |    output
*                  |   |    |    |    |
*                  |   |    |    |    |
.SUBCKT AD8548     1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L= 1.000E-06 W= 1.532E-04
M2   6  2  8  8 PIX L= 1.000E-06 W=1.532E-04
M3  14  7 18 18 NIX L=1.000E-06 W=4.085E-04
M4  16  2 18 18 NIX L=1.000E-06 W=4.085E-04
RD1  4 50 2.0E+04
RD2  6 50 2.0E+04
RD3 99 14 2.0E+04
RD4 99 16 2.0E+04
C1   4  6 9.4750E-12
C2  14 16 9.4750E-12
I1  99  8 1.722E-05
I2  18 50 1.722E-05
V1  99  9 1.429E-01
V2  19 50 1.429E-01
D1   8  9 DX
D2  19 18 DX
EOS  7  1 POLY(4) (73,98) (22,98) (81,98) (83,98) 3E-03 1 1 1 1
IOS  1  2 2.000E-11
CDiff  1 2 3.5E-12
Cin1   1 50 10.5E-12
Cin2   2 50 10.5E-12
*
*
* CMRR
*
E1  72 98 POLY(2) (1,98) (2,98) 0 6.817E-02 6.817E-02
R10 72 73 2.894E+02
R20 73 98 1.592E-02
C10 72 73 1.000E-06
*
* PSRR
*
EPSY 21 98 POLY(1) (99,50) -1.757E+02 9.762E+00
RPS1 21 22 3.183E+03
RPS2 22 98 7.958E-01
CPS1 21 22 1.000E-06
*
* VOLTAGE NOISE
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 4.5165E+01
RN2 81 98 1
*
* FLICKER NOISE
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1.000E-03 1.000E+00
RFN 83 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) -1.74975E-05 5.031E-08
EVP  97 98 POLY(1) (99,50) -1.05 0.25
EVN  51 98 POLY(1) (50,99) 1.45 0.3

*
* GAIN STAGE
*
G1 98 30 POLY(2) (4,6) (14,16) 0 5.693E-05 5.693E-05
R1 30 98 1.000E+06
RZ 30 31 8.2720E+03
CF 45 31 5.605E-10
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L= 2.000E-06 W=2.450E-04
M6  45 47 50 50 NOX L= 2.000E-06 W=1.591E-04
EG1 99 46 POLY(1) (98,30) 3.347E-01 1
EG2 47 50 POLY(1) (30,98) 3.216E-01 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=1.000E-05,VTO=-0.3,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=4.000E-05,VTO=+0.3,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=4.000E-05,VTO=-0.5,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=1.500E-05,VTO=0.5,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=0.1)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.5E-10)
*
*
.ENDS AD8548
*
*$


* AD8551 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 1X
* Developed by: TAM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/1999)
* Copyright 1999, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8551      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=355.3E-6
M2   6  2  8  8 PIX L=1E-6 W=355.3E-6
M3  11  7 10 10 NIX L=1E-6 W=355.3E-6
M4  12  2 10 10 NIX L=1E-6 W=355.3E-6
RC1  4 14 9E+3
RC2  6 16 9E+3
RC3 17 11 9E+3
RC4 18 12 9E+3
RC5 14 50 1E+3
RC6 16 50 1E+3
RC7 99 17 1E+3
RC8 99 18 1E+3
C1  14 16 30E-12
C2  17 18 30E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16
*
* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 45
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 7MHz, POLE AT 50MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
R2 32 33 3.7E+3
R3 33 98 22.74E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 22.7E-6
R1 30 98 259.1E+6
CF 45 30 45.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.111E-3
M6  45 47 50 50 NOX L=1E-6 W=1.6E-3
EG1 99 46 POLY(1) (98,30) 1.1936 1
EG2 47 50 POLY(1) (30,98) 1.2324 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8551






* AD8552 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 2X
* Developed by: TAM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/1999)
* Copyright 1999, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8552      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=355.3E-6
M2   6  2  8  8 PIX L=1E-6 W=355.3E-6
M3  11  7 10 10 NIX L=1E-6 W=355.3E-6
M4  12  2 10 10 NIX L=1E-6 W=355.3E-6
RC1  4 14 9E+3
RC2  6 16 9E+3
RC3 17 11 9E+3
RC4 18 12 9E+3
RC5 14 50 1E+3
RC6 16 50 1E+3
RC7 99 17 1E+3
RC8 99 18 1E+3
C1  14 16 30E-12
C2  17 18 30E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16
*
* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 45
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 7MHz, POLE AT 50MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
R2 32 33 3.7E+3
R3 33 98 22.74E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 22.7E-6
R1 30 98 259.1E+6
CF 45 30 45.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.111E-3
M6  45 47 50 50 NOX L=1E-6 W=1.6E-3
EG1 99 46 POLY(1) (98,30) 1.1936 1
EG2 47 50 POLY(1) (30,98) 1.2324 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8552






* AD8554 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 4X
* Developed by: TAM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/1999)
* Copyright 1999, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8554      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=355.3E-6
M2   6  2  8  8 PIX L=1E-6 W=355.3E-6
M3  11  7 10 10 NIX L=1E-6 W=355.3E-6
M4  12  2 10 10 NIX L=1E-6 W=355.3E-6
RC1  4 14 9E+3
RC2  6 16 9E+3
RC3 17 11 9E+3
RC4 18 12 9E+3
RC5 14 50 1E+3
RC6 16 50 1E+3
RC7 99 17 1E+3
RC8 99 18 1E+3
C1  14 16 30E-12
C2  17 18 30E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16
*
* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 45
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 7MHz, POLE AT 50MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
R2 32 33 3.7E+3
R3 33 98 22.74E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 22.7E-6
R1 30 98 259.1E+6
CF 45 30 45.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.111E-3
M6  45 47 50 50 NOX L=1E-6 W=1.6E-3
EG1 99 46 POLY(1) (98,30) 1.1936 1
EG2 47 50 POLY(1) (30,98) 1.2324 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8554






* AD8571 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 1X
* Developed by: TAM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (10/1999)
* Copyright 1999, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8571      1       2       99       50      45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=355.3E-6
M2   6  2  8  8 PIX L=1E-6 W=355.3E-6
M3  11  7 10 10 NIX L=1E-6 W=355.3E-6
M4  12  2 10 10 NIX L=1E-6 W=355.3E-6
RC1  4 14 9E+3
RC2  6 16 9E+3
RC3 17 11 9E+3
RC4 18 12 9E+3
RC5 14 50 1E+3
RC6 16 50 1E+3
RC7 99 17 1E+3
RC8 99 18 1E+3
C1  14 16 30E-12
C2  17 18 30E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16
*
* VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 51
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 7MHz, POLE AT 50MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
R2 32 33 3.7E+3
R3 33 98 22.74E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 22.7E-6
R1 30 98 259.1E+6
CF 45 30 45.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.111E-3
M6  45 47 50 50 NOX L=1E-6 W=1.6E-3
EG1 99 46 POLY(1) (98,30) 1.1936 1
EG2 47 50 POLY(1) (30,98) 1.2324 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8571






* AD8572 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 2X
* Developed by: TAM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (10/1999)
* Copyright 1999, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8572      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=355.3E-6
M2   6  2  8  8 PIX L=1E-6 W=355.3E-6
M3  11  7 10 10 NIX L=1E-6 W=355.3E-6
M4  12  2 10 10 NIX L=1E-6 W=355.3E-6
RC1  4 14 9E+3
RC2  6 16 9E+3
RC3 17 11 9E+3
RC4 18 12 9E+3
RC5 14 50 1E+3
RC6 16 50 1E+3
RC7 99 17 1E+3
RC8 99 18 1E+3
C1  14 16 30E-12
C2  17 18 30E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16
*
* VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 51
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 7MHz, POLE AT 50MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
R2 32 33 3.7E+3
R3 33 98 22.74E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 22.7E-6
R1 30 98 259.1E+6
CF 45 30 45.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.111E-3
M6  45 47 50 50 NOX L=1E-6 W=1.6E-3
EG1 99 46 POLY(1) (98,30) 1.1936 1
EG2 47 50 POLY(1) (30,98) 1.2324 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8572






* AD8574 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 4X
* Developed by: TAM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (10/1999)
* Copyright 1999, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8574       1       2       99      50      45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=355.3E-6
M2   6  2  8  8 PIX L=1E-6 W=355.3E-6
M3  11  7 10 10 NIX L=1E-6 W=355.3E-6
M4  12  2 10 10 NIX L=1E-6 W=355.3E-6
RC1  4 14 9E+3
RC2  6 16 9E+3
RC3 17 11 9E+3
RC4 18 12 9E+3
RC5 14 50 1E+3
RC6 16 50 1E+3
RC7 99 17 1E+3
RC8 99 18 1E+3
C1  14 16 30E-12
C2  17 18 30E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16
*
* VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 51
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 7MHz, POLE AT 50MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
R2 32 33 3.7E+3
R3 33 98 22.74E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 22.7E-6
R1 30 98 259.1E+6
CF 45 30 45.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.111E-3
M6  45 47 50 50 NOX L=1E-6 W=1.6E-3
EG1 99 46 POLY(1) (98,30) 1.1936 1
EG2 47 50 POLY(1) (30,98) 1.2324 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8574





* AD8601 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Vos, RRIO, 1X
* Developed by: OEB / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (03/2000)
* Copyright 1999, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8601      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=982E-6
M2  16  2  8  8 PIX L=1E-6 W=982E-6
M3  17  7 10 10 NIX L=1E-6 W=982E-6
M4  18  2 10 10 NIX L=1E-6 W=982E-6
RC5 14 50 4E+3
RC6 16 50 4E+3
RC7 99 17 4E+3
RC8 99 18 4E+3
C1  14 16 0.6E-12
C2  17 18 0.6E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 300E-6 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 90dB, ZERO AT 15kHz, POLE AT 2MHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
CCM1 21 22 3.54E-10
RCM1 21 22 30000
RCM2 22 98 1
*
* PSRR=100dB, ZERO AT 300Hz
*
EPSY 98 72 POLY(1) (99,50) 0 1
CPS3 72 73 5.30E-9
RPS3 72 73 100E+3
RPS4 73 98 1
*
*
* VOLTAGE NOISE REFERENCE OF 33nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 33
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 POLY(1) (99,50) -0.6 0.5
EVN  51 98 POLY(1) (50,99) 0.6 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (14,16) (17,18) 0 375E-6 375E-6
R1 30 98 2.53E+6
CF 45 30 50E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.6E-3
M6  45 47 50 50 NOX L=1E-6 W=3.33E-3
EG1 99 46 POLY(1) (98,30) 0.5216 1
EG2 47 50 POLY(1) (30,98) 0.4622 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3)
.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8601
*
*$





* AD8602 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Vos, RRIO, 2X
* Developed by: OEB / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (03/2000)
* Copyright 1999, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8602       1       2       99      50      45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=982E-6
M2  16  2  8  8 PIX L=1E-6 W=982E-6
M3  17  7 10 10 NIX L=1E-6 W=982E-6
M4  18  2 10 10 NIX L=1E-6 W=982E-6
RC5 14 50 4E+3
RC6 16 50 4E+3
RC7 99 17 4E+3
RC8 99 18 4E+3
C1  14 16 0.6E-12
C2  17 18 0.6E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 300E-6 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 90dB, ZERO AT 15kHz, POLE AT 2MHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
CCM1 21 22 3.54E-10
RCM1 21 22 30000
RCM2 22 98 1
*
* PSRR=100dB, ZERO AT 300Hz
*
EPSY 98 72 POLY(1) (99,50) 0 1
CPS3 72 73 5.30E-9
RPS3 72 73 100E+3
RPS4 73 98 1
*
*
* VOLTAGE NOISE REFERENCE OF 33nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 33
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 POLY(1) (99,50) -0.6 0.5
EVN  51 98 POLY(1) (50,99) 0.6 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (14,16) (17,18) 0 375E-6 375E-6
R1 30 98 2.53E+6
CF 45 30 50E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.6E-3
M6  45 47 50 50 NOX L=1E-6 W=3.33E-3
EG1 99 46 POLY(1) (98,30) 0.5216 1
EG2 47 50 POLY(1) (30,98) 0.4622 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3)
.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8602
*
*$





* AD8604 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Vos, RRIO, 4X
* Developed by: OEB / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/2010) - from AD8601-3/00v1
* Copyright 1999, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8604      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=982E-6
M2  16  2  8  8 PIX L=1E-6 W=982E-6
M3  17  7 10 10 NIX L=1E-6 W=982E-6
M4  18  2 10 10 NIX L=1E-6 W=982E-6
RC5 14 50 4E+3
RC6 16 50 4E+3
RC7 99 17 4E+3
RC8 99 18 4E+3
C1  14 16 0.6E-12
C2  17 18 0.6E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 300E-6 1 1 1
IOS  1  2 2.5E-12
*
* CMRR 90dB, ZERO AT 15kHz, POLE AT 2MHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
CCM1 21 22 3.54E-10
RCM1 21 22 30000
RCM2 22 98 1
*
* PSRR=100dB, ZERO AT 300Hz
*
EPSY 98 72 POLY(1) (99,50) 0 1
CPS3 72 73 5.30E-9
RPS3 72 73 100E+3
RPS4 73 98 1
*
*
* VOLTAGE NOISE REFERENCE OF 33nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 33
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 POLY(1) (99,50) -0.6 0.5
EVN  51 98 POLY(1) (50,99) 0.6 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (14,16) (17,18) 0 375E-6 375E-6
R1 30 98 2.53E+6
CF 45 30 50E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.6E-3
M6  45 47 50 50 NOX L=1E-6 W=3.33E-3
EG1 99 46 POLY(1) (98,30) 0.5216 1
EG2 47 50 POLY(1) (30,98) 0.4622 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3)
.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8604
*
*






* AD8605 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Noise, RRIO, 1X
* Developed by: SB, ADSiV apps
* Revision History:
* 2.0  (05/2016) - Fixed flicker noise model - Emman.A (ADGT)
* 08/10/2012 - Updated to new header style
* 1.0 (05/2002) - from AD8601-3/00v1
* Copyright 2002, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8605      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=1600E-6
M2  16  2  8  8 PIX L=1E-6 W=1600E-6
M3  17  7 10 10 NIX L=1E-6 W=1600E-6
M4  18  2 10 10 NIX L=1E-6 W=1600E-6
RC5 14 50 4E+3
RC6 16 50 4E+3
RC7 99 17 4E+3
RC8 99 18 4E+3
C1  14 16 0.6E-12
C2  17 18 0.6E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 10E-6 1 1 1
IOS  1  2 0.05E-12
*
* CMRR 100dB,  POLE AT 4.5KHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
CCM1 21 22 3.54E-10
RCM1 21 22 100E3
RCM2 22 98 1
*
* PSRR=95dB, ZERO AT 534Hz
*
EPSY 98 72 POLY(1) (99,50) 0 1
CPS3 72 73 5.30E-9
RPS3 72 73 56234
RPS4 73 98 1
*
*
* VOLTAGE NOISE REFERENCE OF 8nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 5.8
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 POLY(1) (99,50) -0.6 0.5
EVN  51 98 POLY(1) (50,99) 0.6 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (14,16) (17,18) 0 56.3E-6 56.3E-6
R1 30 98 5.43E8
CF 45 30 9E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.08E-3
M6  45 47 50 50 NOX L=1E-6 W=1.61E-3
EG1 99 46 POLY(1) (98,30) 0.4644 1
EG2 47 50 POLY(1) (30,98) 0.4394 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3)
.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8605
*
*$





* AD8606 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Noise, RRIO, 2X
* Developed by: ADSJ-HH
* Revision History:
* 2.0  (05/2016) - Fixed flicker noise model - Emman.A (ADGT)
* 08/10/2012 - Updated to new header style
* 1.0 (05/2002) - from AD8601-3/00v1
* Copyright 2010, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8606          1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=1600E-6
M2  16  2  8  8 PIX L=1E-6 W=1600E-6
M3  17  7 10 10 NIX L=1E-6 W=1600E-6
M4  18  2 10 10 NIX L=1E-6 W=1600E-6
RC5 14 50 4E+3
RC6 16 50 4E+3
RC7 99 17 4E+3
RC8 99 18 4E+3
C1  14 16 0.6E-12
C2  17 18 0.6E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 10E-6 1 1 1
IOS  1  2 0.05E-12
*
* CMRR 100dB,  POLE AT 4.5KHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
CCM1 21 22 3.54E-10
RCM1 21 22 100E3
RCM2 22 98 1
*
* PSRR=95dB, ZERO AT 534Hz
*
EPSY 98 72 POLY(1) (99,50) 0 1
CPS3 72 73 5.30E-9
RPS3 72 73 56234
RPS4 73 98 1
*
*
* VOLTAGE NOISE REFERENCE OF 8nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 5.8
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 POLY(1) (99,50) -0.6 0.5
EVN  51 98 POLY(1) (50,99) 0.6 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (14,16) (17,18) 0 56.3E-6 56.3E-6
R1 30 98 5.43E8
CF 45 30 9E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.08E-3
M6  45 47 50 50 NOX L=1E-6 W=1.61E-3
EG1 99 46 POLY(1) (98,30) 0.4644 1
EG2 47 50 POLY(1) (30,98) 0.4394 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3)
.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8606
*
*




* AD8608 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Low Noise, RRIO, 4X
* Developed by: ADSJ HH
* Revision History:
* 2.0  (05/2016) - Fixed flicker noise model - Emman.A (ADGT)
* 08/10/2012 - Updated to new header style
* 0.0 (05/2002) - from AD8601-3/00v1
* Copyright 2010, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8608          1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=1600E-6
M2  16  2  8  8 PIX L=1E-6 W=1600E-6
M3  17  7 10 10 NIX L=1E-6 W=1600E-6
M4  18  2 10 10 NIX L=1E-6 W=1600E-6
RC5 14 50 4E+3
RC6 16 50 4E+3
RC7 99 17 4E+3
RC8 99 18 4E+3
C1  14 16 0.6E-12
C2  17 18 0.6E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 10E-6 1 1 1
IOS  1  2 0.05E-12
*
* CMRR 100dB,  POLE AT 4.5KHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
CCM1 21 22 3.54E-10
RCM1 21 22 100E3
RCM2 22 98 1
*
* PSRR=95dB, ZERO AT 534Hz
*
EPSY 98 72 POLY(1) (99,50) 0 1
CPS3 72 73 5.30E-9
RPS3 72 73 56234
RPS4 73 98 1
*
*
* VOLTAGE NOISE REFERENCE OF 8nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 5.8
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 48E-6
EVP  97 98 POLY(1) (99,50) -0.6 0.5
EVN  51 98 POLY(1) (50,99) 0.6 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (14,16) (17,18) 0 56.3E-6 56.3E-6
R1 30 98 5.43E8
CF 45 30 9E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.08E-3
M6  45 47 50 50 NOX L=1E-6 W=1.61E-3
EG1 99 46 POLY(1) (98,30) 0.4644 1
EG2 47 50 POLY(1) (30,98) 0.4394 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3)
.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8608
*
*




* AD8614/AD8644 SPICE Macro-model
* Description: Amplifier
* Generic Desc: Single high-voltage LCD driver
* Developed by: Troy Murphy / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 0.0 (11/1999)
* Copyright 1996, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*                      noninverting input
*                      |       inverting input
*                      |       |       positive supply
*                      |       |       |       negative supply
*                      |       |       |       |       output
*                      |       |       |       |       |
*                      |       |       |       |       |
.SUBCKT AD8614         1       2       99      50      45
*#ASSOC Category="Op-amps" symbol=opamp
*
* RAIL-TO-RAIL INPUT STAGE
*
Q1    5  7  3 PIX
Q2    6  2  4 PIX
Q3   11  7 13 NIX
Q4   12  2 14 NIX
RC1   5 50 2310
RC2   6 50 2310
RC3  99 11 2310
RC4  99 12 2310
RE1   3 10 620
RE2   4 10 620
RE3  13 15 620
RE4  14 15 620
I1   99 10 300E-6
I2   15 50 300E-6
RCM1 10 99 5.58E+5
RCM2 15 50 5.58E+5
CCM1 10 99 1.43E-11
CCM2 15 50 1.43E-11
C1    5  6 1.19E-12
C2   11 12 1.19E-12
D1    3  8 DX
D2    4  9 DX
D3   16 13 DX
D4   17 14 DX
V1   99  8 DC 0.7
V2   99  9 DC 0.7
V3   16 50 DC 0.7
V4   17 50 DC 0.7
EOS   7  1 POLY(2) (73,98) (81,98) 1E-3 1 1
IOS   1  2 10E-9
*
* PSRR=100dB, ZERO AT 100Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 50E-12
RPS4 73 98 159
*
* VOLTAGE NOISE REFERENCE OF 10nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 10
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 POLY(1) (99,50) 41.121E-6 5E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* GAIN STAGE
*
G1   98 30 POLY(2) (5,6) (11,12) 0 3.125E-4 3.125E-4
R1   30 98 2.25E+6
CF   30 45 49E-12
D5   30 97 DX
D6   51 30 DX
*
* RAIL-TO-RAIL OUTPUT STAGE
*
Q5   45 41 99 POUT
Q6   45 43 50 NOUT
EB1  99 40 POLY(1) (98,30) 0.7129 1
EB2  42 50 POLY(1) (30,98) 0.7129 1
RB1  40 41 500
RB2  42 43 500
D7   46 99 DX
D8   47 43 DX
V5   46 41 0.5
V6   47 50 0.5
*
.MODEL NIX NPN (BF=220,IS=1E-16,VAF=130,KF=2.5E-14)
.MODEL PIX PNP (BF=220,IS=1E-16,VAF=130,KF=2.5E-14)
.MODEL POUT PNP (BF=100,IS=1E-16,VAF=200,RC=4)
.MODEL NOUT NPN (BF=100,IS=1E-16,VAF=200,RC=4)
.MODEL DX D(IS=1E-16,RS=5)
.ENDS AD8614








* AD8618 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Fast, RRIO, 4X
* Developed by: Soufiane Bendaoud, ADSiV apps, TRW
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (05/2004)
* Copyright 2004, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes: Typical Values at Vs=+/-2.5V
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8618      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=1580E-6
M2  16  2  8  8 PIX L=1E-6 W=1580E-6
M3  17  7 10 10 NIX L=1E-6 W=1580E-6
M4  18  2 10 10 NIX L=1E-6 W=1580E-6
RC5 14 50 4E+3
RC6 16 50 4E+3
RC7 99 17 4E+3
RC8 99 18 4E+3
C1  14 16 0.08E-12
C2  17 18 0.08E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.2
V2  13 50 0.2
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(4) (22,98) (73,98) (81,98) (70,98) 27.326e-3 1 1 1 1
IOS  1  2  0.05E-12

*
*CMRR=100dB, ZERO AT 1MHz
*
 E1 21 98 POLY(2) (1,98) (2,98) 0 0.001255943   0.001255943
 R10 21 22 1.59E1
 R20 22 98 1.59E-1
 C10 21 22 1E-6

*
* PSRR=95dB, ZERO AT 534Hz
*
EPSY 98 72 POLY(1) (99,50) 0 0.5
CPS3 72 73 1E-6
RPS3 72 73 3.98E1
RPS4 73 98 7.96E-3
*
*
* VOLTAGE NOISE REFERENCE OF 8nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 7
RN2 81 98 1

*flicker noise

D5 69 98 DNOISE
VSN 69 98 DC .6551
H1 70 98 VSN 25.3
RN 70 98 1

*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 240E-6
EVP  97 98 POLY(1) (99,50) -0.6 0.5
EVN  51 98 POLY(1) (50,99) 0.6 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (14,16) (17,18) 0 2.1E-4 2.1E-4
R1 30 98 3.634E7
CF 45 30 14E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=4.03E-3
M6  45 47 50 50 NOX L=1E-6 W=4.03E-3
EG1 99 46 POLY(1) (98,30) 0.45 1
EG2 47 50 POLY(1) (30,98) 0.45 1


*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,TOX=100E-3)
.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,TOX=100E-3)
.MODEL DX D(IS=1E-14,RS=5,KF=1E-15)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=1E-15)

.ENDS AD8618
*








* AD8622/AD8624 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 5/30V, BIP, OP, Low Noise, RRO, 4X
* Developed by: VW ADSJ
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (01/2010)
* Copyright 2009, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes: VSY=5V, T=25degC
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*              noninverting input
*                  |   inverting input
*              |   |   positive supply
*              |   |   |   negative supply
*              |   |   |   |   output
*              |   |   |   |   |
*              |   |   |   |   |
.SUBCKT AD8624      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
*INPUT STAGE
*
Q1   15 7 60 NIX
Q2   6 2 61 NIX
IOS  1 2 1.75E-11
I1  5 50 50e-6
EOS  7  1 POLY(4) (14,98) (73,98) (81,98) (70,98)  10E-6 1 1 1 1
RC1  11 15 2.6E4
RC2  11 6 2.6E4
RE1 60 5 0.896E2
RE2 61 5 0.896E2
C1   15 6 6.25E-13
D1  50 9 DX
V1  5  9 DC 0.3
D10 99 10 DX
V6 10 11 0.3
*
* CMRR
*
ECM   13 98 POLY(2) (1,98) (2,98) 0 7.192E-4 7.192E-4
RCM1  13 14 2.15E2
RCM2  14 98 5.31E-1
CCM1  13 14 1E-6
*
* PSRR
*
EPSY 72 98 POLY(1) (99,50) -1.683 0.056
CPS3 72 73 1E-6
RPS3 72 73 7.9577E+0
RPS4 73 98 1.5915E-3
*
* EXTRA POLE AND ZERO
*
G1 21 98 (6,15) 1E-6
R1 21 98 1E6
R2 21 22 7E5
C2 22 98 1.7614E-12
D3 21 99 DX
D4 50 21 DX
*
* VOLTAGE NOISE
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 7.98
RN2 81 98 1
*
* FLICKER NOISE
*
D5 69 98 DNOISE
VSN 69 98 DC .6551
H1 70 98 VSN 40.85
RN 70 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 POLY(1) (99,50) -25E-6 1.7495E-8
*
* GAIN STAGE
*
G2  98 25 (21,98) 1E-6
R5  25 98 9.9E7
CF  45 25 2.69E-12
V4 25 33 5.3
D7 51 33 DX
EVN 51 98 (50,99) 0.5
V3 32 25 5.3
D6 32 97 DX
EVP 97 98 (99,50) 0.5
*
* OUTPUT STAGE
*
Q3   45 41 99 POUT
Q4   45 43 50 NOUT
RB1  40 41 7.25E4
RB2  42 43 7.25E4
EB1  99 40 POLY(1) (98,25) 0.7153  1
EB2  42 50 POLY(1) (25,98) 0.7153  1
*
* MODELS
*
.MODEL NIX NPN (BF=71429,IS=1E-16)
.MODEL POUT PNP (BF=200,VAF=50,BR=70,IS=1E-15,RC=71.25)
.MODEL NOUT NPN (BF=200,VAF=50,BR=22,IS=1E-15,RC=29.2)
.MODEL DX D(IS=1E-16, RS=5, KF=1E-15)
.MODEL DNOISE D(IS=1E-16,RS=0,KF=1.095E-14)

.ENDS AD8624






* AD8628 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 1X
* Developed by: RM / ADSiv
* Revision History: 08/10/2012 - Updated to new header style
* 0.0 (03/2002)
* Copyright 2002, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8628      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=174.1E-6
M2   6  2  8  8 PIX L=1E-6 W=174.1E-6
M3  11  7 10 10 NIX L=1E-6 W=174.1E-6
M4  12  2 10 10 NIX L=1E-6 W=174.1E-6
RC1  4 14 0.001E+3
RC2  6 16 0.001E+3
RC3 17 11 0.001E+3
RC4 18 12 0.001E+3
RC5 14 50 6E+3
RC6 16 50 6E+3
RC7 99 17 6E+3
RC8 99 18 6E+3
*Set teh secondary pole at 17MHz using c1,c2 and RC5..
C1  14 16 5.40E-12
C2  17 18 5.40E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
IOS  1  2 25E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=115dB, ZERO AT 20Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 28.9E+6
CPS3 72 73 .25E-9
RPS4 73 98 40
*
* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 20
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 44E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 17MHz, POLE AT 50.3MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .6689 .6689
R2 32 33 3.164E+3
R3 33 98 9.362E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 25E-6
R1 30 98 2.46E+9
CF 45 30 12.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.47E-3
M6  45 47 50 50 NOX L=1E-6 W=1.90E-3
EG1 99 46 POLY(1) (98,30) 0.5303 1
EG2 47 50 POLY(1) (30,98) 0.5058 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8628
*
*$





* AD8629 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 2X
* Developed by: RM / ADSiv
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/2010)
* Copyright 2010, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8629      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=174.1E-6
M2   6  2  8  8 PIX L=1E-6 W=174.1E-6
M3  11  7 10 10 NIX L=1E-6 W=174.1E-6
M4  12  2 10 10 NIX L=1E-6 W=174.1E-6
RC1  4 14 0.001E+3
RC2  6 16 0.001E+3
RC3 17 11 0.001E+3
RC4 18 12 0.001E+3
RC5 14 50 6E+3
RC6 16 50 6E+3
RC7 99 17 6E+3
RC8 99 18 6E+3
*Set teh secondary pole at 17MHz using c1,c2 and RC5..
C1  14 16 5.40E-12
C2  17 18 5.40E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
IOS  1  2 25E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=115dB, ZERO AT 20Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 28.9E+6
CPS3 72 73 .25E-9
RPS4 73 98 40
*
* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 20
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 44E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 17MHz, POLE AT 50.3MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .6689 .6689
R2 32 33 3.164E+3
R3 33 98 9.362E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 25E-6
R1 30 98 2.46E+9
CF 45 30 12.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.47E-3
M6  45 47 50 50 NOX L=1E-6 W=1.90E-3
EG1 99 46 POLY(1) (98,30) 0.5303 1
EG2 47 50 POLY(1) (30,98) 0.5058 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8629
*







* AD8630 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 4X
* Developed by: RM / ADSiv
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/2010)
* Copyright 2010, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT AD8630      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=1E-6 W=174.1E-6
M2   6  2  8  8 PIX L=1E-6 W=174.1E-6
M3  11  7 10 10 NIX L=1E-6 W=174.1E-6
M4  12  2 10 10 NIX L=1E-6 W=174.1E-6
RC1  4 14 0.001E+3
RC2  6 16 0.001E+3
RC3 17 11 0.001E+3
RC4 18 12 0.001E+3
RC5 14 50 6E+3
RC6 16 50 6E+3
RC7 99 17 6E+3
RC8 99 18 6E+3
*Set teh secondary pole at 17MHz using c1,c2 and RC5..
C1  14 16 5.40E-12
C2  17 18 5.40E-12
I1  99  8 100E-6
I2  10 50 100E-6
V1  99  9 0.3
V2  13 50 0.3
D1   8  9 DX
D2  13 10 DX
EOS  7  1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1
IOS  1  2 25E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=115dB, ZERO AT 20Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 28.9E+6
CPS3 72 73 .25E-9
RPS4 73 98 40
*
* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 20
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 (99,50) 44E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* LHP ZERO AT 17MHz, POLE AT 50.3MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .6689 .6689
R2 32 33 3.164E+3
R3 33 98 9.362E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 25E-6
R1 30 98 2.46E+9
CF 45 30 12.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.47E-3
M6  45 47 50 50 NOX L=1E-6 W=1.90E-3
EG1 99 46 POLY(1) (98,30) 0.5303 1
EG2 47 50 POLY(1) (30,98) 0.5058 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8630
*







* AD8641 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 5/26V, JFET, OP, RRO, S SPLY, 1X
* Developed by: ADSJ-HH, Soufiane Bendaoud, ADSiV
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (12/2010) - Switched to NFETs, Corrected Zout, Vdo, GBW, Ibias
* 1.0 (12/2004) - Soufiane Bendaoud, ADSiV apps
* Copyright 2004, 2008, 2010, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*  CAUTION!!  To aid in convergence, most Spice simulators add a
*  conductance on every node to insure that no node is floating.
*  This is GMIN, and the default value is usually 1E-12.  To properly
*  simulate the low input bias current and low current noise, the
*  Spice simulator options have to be set to the following:
*  .OPTIONS GMIN=0.01p
*  .OPTIONS ABSTOL=0.01pA
*
* Not Modeled:
*
* Parameters modeled include:
* This model simulates typical values at Vs=+/-13V
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |   inverting input
*                |   | positive supply
*                |   |    |  negative supply
*                |   |    |    |  output
*                |   |    |    |    |
.SUBCKT AD8641   1   2   99   50   30
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
CIN  1   2    4.5E-12
CCM1  1 50    3E-12
CCM2  2 50    3E-12
J1   5   7   4  JX;  DGS
J2   6   2   4  JX;
R3   99  5    1.500E+04
R4   99  6    1.500E+04
CCOMP 5 6     6.35E-13
I1   4  50    4.000E-05
Vclamp 99 101 3.8
Dclamp 4 101 DY
IOS  1   2     0.25E-12
EOS  7  1    POLY(3) (142,0) (73,98) (22,98) 70E-6  1  1  1
GB1  2  50    POLY(3) (4,2) (5,2) (50,2) -0.2E-12 2E-14 2E-14 2E-14
GB2  7  50    POLY(3) (4,7) (6,7) (50,7) -0.3E-12 1E-14 1E-14 -0.2E-14
*
EREF 98 0 24 0   1
R14  24 99     500E3
R15  24 50     500E3
*
* SECOND STAGE
G1   9  98    (6,5)  5.022E-04
R105 9  98     1.0E+06
D1   9   8    DX
V2   8  98    0.085;
D2   10  9    DX
V3   10 98    -0.065;
RZ  451 453  1.95E+02
CZ  453   9  1.33E-10
*
* POLE AT 15 MHZ
*
R13  18 98   1E3
C9   18 98   1.75E-16; -11
G105   (18,98) (98,9)  1E-3
*
* COMMON-MODE GAIN NETWORK
*
E1   72 98     POLY(2) (1 98) (2 98)  0  3.132E-03 3.132E-03
R10  72 73     7.958E+01
R20  73 98     6.366E-02
C10  72 73     1.000E-06
*
* PSRR
*
EPSY 98 21 POLY(1) (99,50) 3.646  1.402E-01
RPS1 21 22 4.421E+05
RPS2 22 98 1.989E+01
CPS1 21 22 1.000E-09
*
* VOLTAGE NOISE GENERATOR
*
VN1  141 0    DC 2
DN1  141 142  DEN
DN2  142 143  DEN
VN2  0 143    DC 2
*
* OUTPUT STAGE
*
Q3   451 41 99 POUT
RB1  40 41 1.5E+3
EB1  99 40 POLY(1) (98, 18) 6.173E-01  1E-0;
Q4   451 43 50 NOUT
RB2  42 43 2.0E+3
EB2  42 50 POLY(1) (18, 98) 6.08E-01  1E-0;
Lout 30 451  10E-14
*
GSY  99 50 POLY(1) (99 50) 81.13E-6 1.632E-06
*
* MODELS
*
.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130)
.MODEL POUT PNP (BF=70,IS=2.8E-15,VA=130);
.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=200);
.MODEL JX NJF(BETA=1.400E-03  VTO=-1.00  IS=2E-18 RD=1
+ RS=1 CGD=3E-12 CGS=3E-12 lambda=7.0E-03)
.MODEL DX   D(IS=1E-15 RS=0 CJO=1E-12)
.MODEL DY   D(IS=1E-15 BV=50 RS=10 CJO=1E-12)
.MODEL DEN  D(IS=1E-12 RS=7.63E4, KF=9.665E-15 AF=1)
.MODEL DIN  D(IS=1E-12 RS=12090 KF=0 AF=1)
*
.ENDS AD8641
*
$





* AD8642 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 5/26V, JFET, OP, RRO, S SPLY, 2X
* Developed by: ADSJ-HH, Soufiane Bendaoud, ADSiV
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (12/2010) - Switched to NFETs, Corrected Zout, Vdo, GBW, Ibias
* 1.0 (12/2004) - Soufiane Bendaoud, ADSiV apps
* Copyright 2004, 2008, 2010, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*  CAUTION!!  To aid in convergence, most Spice simulators add a
*  conductance on every node to insure that no node is floating.
*  This is GMIN, and the default value is usually 1E-12.  To properly
*  simulate the low input bias current and low current noise, the
*  Spice simulator options have to be set to the following:
*  .OPTIONS GMIN=0.01p
*  .OPTIONS ABSTOL=0.01pA
*
* Not Modeled:
*
* Parameters modeled include:
* This model simulates typical values at Vs=+/-13V
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |   inverting input
*                |   | positive supply
*                |   |    |  negative supply
*                |   |    |    |  output
*                |   |    |    |    |
.SUBCKT AD8642   1   2   99   50   30
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
CIN  1   2    4.5E-12
CCM1  1 50    3E-12
CCM2  2 50    3E-12
J1   5   7   4  JX;  DGS
J2   6   2   4  JX;
R3   99  5    1.500E+04
R4   99  6    1.500E+04
CCOMP 5 6     6.35E-13
I1   4  50    4.000E-05
Vclamp 99 101 3.8
Dclamp 4 101 DY
IOS  1   2     0.25E-12
EOS  7  1    POLY(3) (142,0) (73,98) (22,98) 70E-6  1  1  1
GB1  2  50    POLY(3) (4,2) (5,2) (50,2) -0.2E-12 2E-14 2E-14 2E-14
GB2  7  50    POLY(3) (4,7) (6,7) (50,7) -0.3E-12 1E-14 1E-14 -0.2E-14
*
EREF 98 0 24 0   1
R14  24 99     500E3
R15  24 50     500E3
*
* SECOND STAGE
G1   9  98    (6,5)  5.022E-04
R105 9  98     1.0E+06
D1   9   8    DX
V2   8  98    0.085;
D2   10  9    DX
V3   10 98    -0.065;
RZ  451 453  1.95E+02
CZ  453   9  1.33E-10
*
* POLE AT 15 MHZ
*
R13  18 98   1E3
C9   18 98   1.75E-16; -11
G105   (18,98) (98,9)  1E-3
*
* COMMON-MODE GAIN NETWORK
*
E1   72 98     POLY(2) (1 98) (2 98)  0  3.132E-03 3.132E-03
R10  72 73     7.958E+01
R20  73 98     6.366E-02
C10  72 73     1.000E-06
*
* PSRR
*
EPSY 98 21 POLY(1) (99,50) 3.646  1.402E-01
RPS1 21 22 4.421E+05
RPS2 22 98 1.989E+01
CPS1 21 22 1.000E-09
*
* VOLTAGE NOISE GENERATOR
*
VN1  141 0    DC 2
DN1  141 142  DEN
DN2  142 143  DEN
VN2  0 143    DC 2
*
* OUTPUT STAGE
*
Q3   451 41 99 POUT
RB1  40 41 1.5E+3
EB1  99 40 POLY(1) (98, 18) 6.173E-01  1E-0;
Q4   451 43 50 NOUT
RB2  42 43 2.0E+3
EB2  42 50 POLY(1) (18, 98) 6.08E-01  1E-0;
Lout 30 451  10E-14
*
GSY  99 50 POLY(1) (99 50) 81.13E-6 1.632E-06
*
* MODELS
*
.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130)
.MODEL POUT PNP (BF=70,IS=2.8E-15,VA=130);
.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=200);
.MODEL JX NJF(BETA=1.400E-03  VTO=-1.00  IS=2E-18 RD=1
+ RS=1 CGD=3E-12 CGS=3E-12 lambda=7.0E-03)
.MODEL DX   D(IS=1E-15 RS=0 CJO=1E-12)
.MODEL DY   D(IS=1E-15 BV=50 RS=10 CJO=1E-12)
.MODEL DEN  D(IS=1E-12 RS=7.63E4, KF=9.665E-15 AF=1)
.MODEL DIN  D(IS=1E-12 RS=12090 KF=0 AF=1)
*
.ENDS AD8642
*
$





* AD8643 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 5/26V, JFET, OP, RRO, S SPLY, 4X
* Developed by: ADSJ-HH, Soufiane Bendaoud, ADSiV
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (12/2010) - Switched to NFETs, Corrected Zout, Vdo, GBW, Ibias
* 1.0 (12/2004) - Soufiane Bendaoud, ADSiV apps
* Copyright 2004, 2008, 2010, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*  CAUTION!!  To aid in convergence, most Spice simulators add a
*  conductance on every node to insure that no node is floating.
*  This is GMIN, and the default value is usually 1E-12.  To properly
*  simulate the low input bias current and low current noise, the
*  Spice simulator options have to be set to the following:
*  .OPTIONS GMIN=0.01p
*  .OPTIONS ABSTOL=0.01pA
*
* Not Modeled:
*
* Parameters modeled include:
* This model simulates typical values at Vs=+/-13V
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |   inverting input
*                |   | positive supply
*                |   |    |  negative supply
*                |   |    |    |  output
*                |   |    |    |    |
.SUBCKT AD8643   1   2   99   50   30
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
CIN  1   2    4.5E-12
CCM1  1 50    3E-12
CCM2  2 50    3E-12
J1   5   7   4  JX;  DGS
J2   6   2   4  JX;
R3   99  5    1.500E+04
R4   99  6    1.500E+04
CCOMP 5 6     6.35E-13
I1   4  50    4.000E-05
Vclamp 99 101 3.8
Dclamp 4 101 DY
IOS  1   2     0.25E-12
EOS  7  1    POLY(3) (142,0) (73,98) (22,98) 70E-6  1  1  1
GB1  2  50    POLY(3) (4,2) (5,2) (50,2) -0.2E-12 2E-14 2E-14 2E-14
GB2  7  50    POLY(3) (4,7) (6,7) (50,7) -0.3E-12 1E-14 1E-14 -0.2E-14
*
EREF 98 0 24 0   1
R14  24 99     500E3
R15  24 50     500E3
*
* SECOND STAGE
G1   9  98    (6,5)  5.022E-04
R105 9  98     1.0E+06
D1   9   8    DX
V2   8  98    0.085;
D2   10  9    DX
V3   10 98    -0.065;
RZ  451 453  1.95E+02
CZ  453   9  1.33E-10
*
* POLE AT 15 MHZ
*
R13  18 98   1E3
C9   18 98   1.75E-16; -11
G105   (18,98) (98,9)  1E-3
*
* COMMON-MODE GAIN NETWORK
*
E1   72 98     POLY(2) (1 98) (2 98)  0  3.132E-03 3.132E-03
R10  72 73     7.958E+01
R20  73 98     6.366E-02
C10  72 73     1.000E-06
*
* PSRR
*
EPSY 98 21 POLY(1) (99,50) 3.646  1.402E-01
RPS1 21 22 4.421E+05
RPS2 22 98 1.989E+01
CPS1 21 22 1.000E-09
*
* VOLTAGE NOISE GENERATOR
*
VN1  141 0    DC 2
DN1  141 142  DEN
DN2  142 143  DEN
VN2  0 143    DC 2
*
* OUTPUT STAGE
*
Q3   451 41 99 POUT
RB1  40 41 1.5E+3
EB1  99 40 POLY(1) (98, 18) 6.173E-01  1E-0;
Q4   451 43 50 NOUT
RB2  42 43 2.0E+3
EB2  42 50 POLY(1) (18, 98) 6.08E-01  1E-0;
Lout 30 451  10E-14
*
GSY  99 50 POLY(1) (99 50) 81.13E-6 1.632E-06
*
* MODELS
*
.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130)
.MODEL POUT PNP (BF=70,IS=2.8E-15,VA=130);
.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=200);
.MODEL JX NJF(BETA=1.400E-03  VTO=-1.00  IS=2E-18 RD=1
+ RS=1 CGD=3E-12 CGS=3E-12 lambda=7.0E-03)
.MODEL DX   D(IS=1E-15 RS=0 CJO=1E-12)
.MODEL DY   D(IS=1E-15 BV=50 RS=10 CJO=1E-12)
.MODEL DEN  D(IS=1E-12 RS=7.63E4, KF=9.665E-15 AF=1)
.MODEL DIN  D(IS=1E-12 RS=12090 KF=0 AF=1)
*
.ENDS AD8643
*
$





* AD8648 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/5V, CMOS, OP, Fast, RRIO, 4X
* Developed by: HH-SJ
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 ( 07/2010) - Modify 1/f circuit
* 1.0 (04/2008)
* Copyright 2010, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*                       noninverting input
*                       |   inverting input
*                       |   |    positive supply
*                       |   |    |   negative supply
*                       |   |    |   |   output
*                       |   |    |   |   |
*                       |   |    |   |   |
.SUBCKT AD8648          1   2   99  50  45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=2E-6 W=6.443E-03
M2   6  2  8  8 PIX L=2E-6 W=6.443E-03
M3  14  7 18 18 NIX L=2E-6 W=6.443E-03
M4  16  2 18 18 NIX L=2E-6 W=6.443E-03
RD1  4 50 1.818E+03
RD2  6 50 1.818E+03
RD3 99 14 1.818E+03
RD4 99 16 1.818E+03
C1   4  611 2.900E-13
rcx1 611 6 3.8m
C2  14 1611 2.900E-13
rcx2 1611 16 3.8m
I1  99  8 2.20E-04
I2  18 50 2.20E-04
V1  99  9 1.117E+00
V2  19 50 1.117E+00
D1   8  9 DX
D2  19 18 DX
EOS  7  1 POLY(4) (73,98) (22,98) (81,98) (83,98) 6.00E-04 1 1 1 1
IOS  1  2 2.50E-11
*
*CMRR=90dB, POLE AT 12000 Hz
*
E1  72 98 POLY(2) (1,98) (2,98) 0 9.438E-02 9.438E-02
R10 72 73 1.326E+01
R20 73 98 2.274E-03
C10 72 73 1.000E-06
*
* PSRR=80dB, POLE AT 7000 Hz
*
EPSY 21 98 POLY(1) (99,50) -14.865E+00 2.973E-00
RPS1 21 22 4.301E+01
RPS2 22 98 1.447E-03
CPS1 21 22 1.000E-06
*
* VOLTAGE NOISE REFERENCE OF 6nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 20.70E-3
HN  81 98 VN1 6.20E+00
RN2 81 98 1
*
* FLICKER NOISE CORNER = 900 Hz
*
DFN 82 98 DNOISE 1000
IFN 98 82 DC 1E-03
DFN2 182 98 DY
IFN2 98 182 DC 1E-06
GFN 83 98 POLY(1) (182,82) 1.00E-13 1.00E-01
RFN 83 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) -308.0E-06 78.0E-06
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (4,6) (14,16) 0 4.574E-04 4.574E-04
R1 30 98 1.00E+06
CF 30 31 2.400E-11
RZ 45 31 3.221E+01
V3 32 30 1.108E+00
V4 30 33 1.193E-00
D3 32 97 DX
D4 51 33 DX
*
* OUTPUT STAGE
*
M5  455 46 99 99 POX L=1E-6 W=6.079E-03
M6  455 47 50 50 NOX L=1E-6 W=5.983E-03
EG1 99 46 POLY(1) (98,30) 5.115E-01 1
EG2 47 50 POLY(1) (30,98) 5.130E-01 1
Lout 45 455 1nH
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.5,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=1.00E-05,VTO=0.5,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=0.1)
.MODEL DY D(IS=1E-16,RS=0.1)
.MODEL DNOISE D(IS=1E-16,RS=0,KF=3.85E-12)
*
.ENDS AD8648
*
*$





* AD8663 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 1X
* Developed by: HH - ADSJ
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (04/2008)
* Copyright 2008, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include: VSY=16V, T=25degC
*
* END Notes
*
* Node Assignments
*                       noninverting input
*                       |   inverting input
*                       |   |    positive supply
*                       |   |    |   negative supply
*                       |   |    |   |   output
*                       |   |    |   |   |
*                       |   |    |   |   |
.SUBCKT AD8663          1   2   99  50  45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=2E-6 W=2.894E-04
M2   6  2  8  8 PIX L=2E-6 W=2.894E-04
RD1  4 50 5.333E+03
RD2  6 50 5.333E+03
C1   4  6 1.300E-11;
I1  99  8 75.00E-06
V1   9  8 1.602E+00
D1   9 99 DX
EOS  7  1 POLY(4) (73,98) (22,98) (81,98) (83,98) 1.10E-014 1 1 1 1
IOS  1  2 5.00E-11
*
* CMRR=87dB, POLE AT 14 kHz
*
E1  72 98 POLY(2) (1,98) (2,98) 0 4.786E-03 4.786E-03
R10 72 73 1.137E+01
R20 73 98 5.305E-02
C10 72 73 1.00E-06
*
* PSRR=95dB, POLE AT 200 Hz
*
EPSY 21 98 POLY(1) (99,50) -2.128+00 0.133E+00
RPS1 21 22 1.061E+03
RPS2 22 98 1.592E-01
CPS1 21 22 1.000E-06
*
* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 1.910E+01
RN2 81 98 1
*
* FLICKER NOISE CORNER = 200 Hz
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) -18.60E-06 1.110E-06
*
* GAIN STAGE
*
G1 98 30 (4,6) 1.427E-03
R1 30 98 1.000E+06
CF 30 31 1.544E-09;  1.595E-9
RZ 455 31 5.639E-00
EZ 455 98  (45 98) 1
EVP  32 98 POLY(1) (99,50) -1.10 +0.38E-00;
EVN  33 98 POLY(1) (50,99) +0.00 +0.45E-00;
D3a 30 32 DX
D4a 33 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=5.008E-05
M6  45 47 50 50 NOX L=1E-6 W=1.099E-04
EG1 99 46 POLY(1) (98,30) 7.607E-01 1
EG2 47 50 POLY(1) (30,98) 6.201E-01 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=3.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=3.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-5.00E-01,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=0.1)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.449E-11)
*
*
.ENDS AD8663
*
*$





* AD8667 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 2X
* Developed by: VW ADSJ
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (04/2008)
* Copyright 2008, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include: VSY=16V, T=25degC
*
* END Notes
*
* Node Assignments
*                       noninverting input
*                       |   inverting input
*                       |   |    positive supply
*                       |   |    |   negative supply
*                       |   |    |   |   output
*                       |   |    |   |   |
*                       |   |    |   |   |
.SUBCKT AD8667          1   2   99  50  45
*#ASSOC Category="Op-amps" symbol=opamp
*
*
M1   4  7  8  8 PIX L=2E-6 W=5.371e-04
M2   6  2  8  8 PIX L=2E-6 W=5.371E-04
RD1  4 50 2.000E+04
RD2  6 50 2.000E+04
C1   4  6 2.84E-12
I1  99  8 2.000E-05
V1   9  8 1.614E+00
D1   9 99 DX
EOS  7  1 POLY(4) (73,98) (22,98) (81,98) (83,98) 4.00E-05 1 1 1 1
IOS  1  2 1.00E-13
*
*
E1  72 98 POLY(2) (1,98) (2,98) 0 1.976E-02 1.976E-02
R10 72 73 3.979E+01
R20 73 98 3.183E-02
C10 72 73 2.8E-7
*
*
EPSY 21 98 POLY(1) (99,50) -14.226e+00 8.891E-01
RPS1 21 22 7.96E+03
RPS2 22 98 1.59E-01
CPS1 21 22 1.00E-06
*
*
VN1 80 98 0
RN1 80 98 21.50E-3
HN  81 98 VN1 1.924E+01
RN2 81 98 1
*
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) 5.8E-05 1.70E-7
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
*
G1 98 30 (4,6) 3.641E-04
R1 30 98 1.00E+07
CF 30 31 3.86E-10
Ez  31 98 45 98 1
V3 32 30 3.104E+00
V4 30 33 0.544E+00
D3 32 97 DX
D4 51 33 DX
*
*
M5  45 46 99 99 POX L=2E-6 W=2.860E-04
M6  45 47 50 50 NOX L=2E-6 W=6.473E-04
EG1 99 46 POLY(1) (98,30) 7.386E-01 1
EG2 47 50 POLY(1) (30,98) 6.010E-01 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=0.1)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.100E-11)
*
*
.ENDS AD8667
*
*$





* AD8669 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 4X
* Developed by: HH/ADI-SJ
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (10/2007)
* Copyright 2007, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*                       noninverting input
*                       |   inverting input
*                       |   |    positive supply
*                       |   |    |   negative supply
*                       |   |    |   |   output
*                       |   |    |   |   |
*                       |   |    |   |   |
.SUBCKT AD8669          1   2   99  50  45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  14  7  8  8 PIX L=1E-6 W=2.525E-03
M2  16  2  8  8 PIX L=1E-6 W=2.525E-03
RC5 14 50 2.00E+03
RC6 16 50 2.00E+03
C1  14 16 3.220E-11
I1  99  8 2.000E-04
V1  99  9 2.097E+00
D1   8  9 DX
EOS  7  1 POLY(4) (22,98) (73,98) (81,98) (70,98) 3.00E-05 1 1 1 1
IOS  1  2 1.00E-13
*
* CMRR=114B, POLE AT 800 Hz
*
E1  21 98 POLY(2) (1,98) (2,98) 8.199E-03 8.199E-03
R10 21 22 1.326E+02
R20 22 98 3.183E-02
C10 21 22 1.000E-06
*
* PSRR=100dB, POLE AT 10 Hz
*
EPSY 72 98 POLY(1) (99,50) -111.596E+00 6.975E+00
RPS3 72 73 2.468E+04
RPS4 73 98 1.989E-02
CPS3 72 73 1.000E-06
*
* VOLTAGE NOISE REFERENCE OF 20.7nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 17.04E-3
HN  81 98 VN1 2.07E+01
RN2 81 98 1
*
* FLICKER NOISE CORNER = 90 Hz
*
D5  69 98 DNOISE
VSN 69 98 DC 0.6551
H1  70 98 POLY(1) VSN 1.00E-03 1.00E+00
RN  70 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) -0.1298E-03 9.0E-07
EVP  97 98 POLY(1) (99,50) 0 0.5E-09
EVN  51 98 POLY(1) (50,99) 0 0.5E-09
*
* GAIN STAGE
*
G1 98 30 POLY(1) (14,16)  0 1.286E-02
R1 30 98 1.00E+06
V3 32 30 -4.108E+00
V4 30 33 -6.421E+00
EZ (145 0) (45 0) 1
CF 145 31 1.270E-08
RZ  30 31 0.100E+00
D3 32 97 DX
D4 51 33 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.673E-04
M6  45 47 50 50 NOX L=1E-6 W=3.762E-04
EG1 99 46 POLY(1) (98,30) 7.233E-01 1
EG2 47 50 POLY(1) (30,98) 5.916E-01 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0.1)
.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0.1)
.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.53E-11)
*
*
.ENDS AD8669
*
*$





* AD8671 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 10/30V, BIP, OP, Low Noise, Low Ib, 1X
* Developed by: HH/ADI-SJ, Soufiane Bendaoud ADI Silicon valley
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (12/2009) - Corrected unpowered Ibais, PM, PSRR, IVR.  Changed noise gen,
*              Added input C.
* 1.0 ( 07/2003)
* Copyright 2003, 2009, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
* This model simulates typical values at Vs=+/-15V
*
* END Notes
*
* Node assignments
*                      non-inverting input
*                  |    inverting input
*                 |    |    positive supply
*                      |    |     |     negative supply
*                      |    |     |     |   output
*                      |    |     |     |      |
.SUBCKT AD8671         1    2     99    50     39
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
R3   5  99    2.033E+04
R4   6  99    2.033E+04
CIN  1   2    7.45E-12
CCM1 1  50    6.25E-12
CCM2 2  50    6.25E-12
RC   5  56    5.3E+03
CC   56  6    2.14E-13
I1   4  50    300E-06
VI1  450 50   2.7
DI1  450  4   DX
IOS  1   2    3E-9
EOS  9  1    POLY(4)  (31 98) (81 98) (83 98) (73 98)  20E-6  1 1  1 1
Q1   5  2  4  QINN
Q2   6  9  4  QINN
D1   2   1    DX
D2   1   2    DX
GN1  50  2    (60 61)  1.453E-05
GN2  50  1    (62 63)  1.453E-05
*
* GAIN STAGE
*
R7   20 98     1.652E+05
C3   20 98     5.61E-07
G1   98 20     (5 6) 3.603E-01
EV1   98 21 POLY(1) (99 98)  -2.0E0 10E-1
EV2   22 98 POLY(1) (98 50)  -2.3E0 10E-1
D5   21 20     DX
D6   20 22     DX
EPLUS 97 0    99  0  1
ENEG  51 0    50  0  1
Rtemp1 97 51 1meg
*
* COMMON-MODE GAIN NETWORK
*
E5   30 98     POLY(2) (2 50) (1 50)  0  4.196E-03  4.196E-03
RCM1 30 31     1.061E+03
RCM2 31 98     1.592E-01
CCM  30 31     1.000E-06
*
* PSRR NETWORK
*
EPSY 98 72 POLY(1) (99,50) 3.350E-03  9.375E-01
CPS3 72 73 1.000E-06
RPS3 72 73 9.947E+02
RPS4 73 98 1.061E-02
*
* VOLTAGE NOISE REFERENCE OF 2.8nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 26.34E-3
HN  81 98 VN1 2.80E+00
RN2 81 98 1
*
* FLICKER NOISE CORNER
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.65520
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
D60 60 0 DIN1 1000
I60 0 60 1m
D61 61 0 DIN1
I61 0 61 1u
*
* SECOND CURRENT NOISE SOURCE
*
D62 62 0 DIN1
I62 0 62 1u
D63 63 0 DIN1
I63 0 63 1u
*
R17  33 99     1meg
R18  33 50     1meg
C178 33 50    1E-06
C188 33 99    1E-06
EREF  98 0    33  0  1
*
GSY  99 50     POLY(1) 99 50 2.24E-3 15E-6
*
* OUTPUT STAGE
*
R19  34 99     100
R20  34 50     100
G9   34 99     99 20  1.000E-02
G10  50 34     20 50  1.000E-02
*
V3   35 34     0.65
D9   20 35     DX
V4   34 36     0.52;
D10  36 20     DX
*
G7   37 50     20 34  1.0E-2
G8   38 50     34 20  1.0E-2
D11  99 37     DX
D12  99 38     DX
D13  50 37     DY
D14  50 38     DY
*
F1   34  0     V3  1
F2   0  34     V4  1
*
L3   34 39     1E-8;  39 is output pin
*
* MODELS USED
*
.MODEL QINN NPN(BF=3.0E4, VA=130)
.MODEL DX   D(IS=1E-15, RS=1m)
.MODEL DY   D(IS=1E-15 BV=50)
.MODEL DEN  D(IS=1E-12, RS=4.0E+2, KF=1.08E-16, AF=1)
.MODEL DNOISE D(IS=1E-14,RS=1E-1,KF=3.14E-14)
.MODEL DIN  D(IS=1E-18, RS=1.0E-6, KF=1.82E-14, AF=1)
.MODEL DIN1 D(IS=1E-16, RS=1.0E-0, KF=3.7E-16, AF=1)
.ENDS AD8671
*$





* AD8672 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 10/30V, BIP, OP, Low Noise, Low Ib, 2X
* Developed by: HH/ADI-SJ, Soufiane Bendaoud ADI Silicon valley
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (12/2009) - Corrected unpowered Ibais, PM, PSRR, IVR.  Changed noise gen,
*              Added input C.
* 1.0 ( 07/2003)
* Copyright 2003, 2009, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
* This model simulates typical values at Vs=+/-15V
*
* END Notes
*
* Node assignments
*                      non-inverting input
*                  |    inverting input
*                    |    |    positive supply
*                    |    |     |     negative supply
*                         |    |     |     |   output
*                         |    |     |     |      |
.SUBCKT AD8672            1    2     99    50     39
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
R3   5  99    2.033E+04
R4   6  99    2.033E+04
CIN  1   2    7.45E-12
CCM1 1  50    6.25E-12
CCM2 2  50    6.25E-12
RC   5  56    5.3E+03
CC   56  6    2.14E-13
I1   4  50    300E-06
VI1  450 50   2.7
DI1  450  4   DX
IOS  1   2    3E-9
EOS  9  1    POLY(4)  (31 98) (81 98) (83 98) (73 98)  20E-6  1 1  1 1
Q1   5  2  4  QINN
Q2   6  9  4  QINN
D1   2   1    DX
D2   1   2    DX
GN1  50  2    (60 61)  1.453E-05
GN2  50  1    (62 63)  1.453E-05
*
* GAIN STAGE
*
R7   20 98     1.652E+05
C3   20 98     5.61E-07
G1   98 20     (5 6) 3.603E-01
EV1   98 21 POLY(1) (99 98)  -2.0E0 10E-1
EV2   22 98 POLY(1) (98 50)  -2.3E0 10E-1
D5   21 20     DX
D6   20 22     DX
EPLUS 97 0    99  0  1
ENEG  51 0    50  0  1
Rtemp1 97 51 1meg
*
* COMMON-MODE GAIN NETWORK
*
E5   30 98     POLY(2) (2 50) (1 50)  0  4.196E-03  4.196E-03
RCM1 30 31     1.061E+03
RCM2 31 98     1.592E-01
CCM  30 31     1.000E-06
*
* PSRR NETWORK
*
EPSY 98 72 POLY(1) (99,50) 3.350E-03  9.375E-01
CPS3 72 73 1.000E-06
RPS3 72 73 9.947E+02
RPS4 73 98 1.061E-02
*
* VOLTAGE NOISE REFERENCE OF 2.8nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 26.34E-3
HN  81 98 VN1 2.80E+00
RN2 81 98 1
*
* FLICKER NOISE CORNER
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.65520
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
D60 60 0 DIN1 1000
I60 0 60 1m
D61 61 0 DIN1
I61 0 61 1u
*
* SECOND CURRENT NOISE SOURCE
*
D62 62 0 DIN1
I62 0 62 1u
D63 63 0 DIN1
I63 0 63 1u
*
R17  33 99     1meg
R18  33 50     1meg
C178 33 50    1E-06
C188 33 99    1E-06
EREF  98 0    33  0  1
*
GSY  99 50     POLY(1) 99 50 2.24E-3 15E-6
*
* OUTPUT STAGE
*
R19  34 99     100
R20  34 50     100
G9   34 99     99 20  1.000E-02
G10  50 34     20 50  1.000E-02
*
V3   35 34     0.65
D9   20 35     DX
V4   34 36     0.52;
D10  36 20     DX
*
G7   37 50     20 34  1.0E-2
G8   38 50     34 20  1.0E-2
D11  99 37     DX
D12  99 38     DX
D13  50 37     DY
D14  50 38     DY
*
F1   34  0     V3  1
F2   0  34     V4  1
*
L3   34 39     1E-8;  39 is output pin
*
* MODELS USED
*
.MODEL QINN NPN(BF=3.0E4, VA=130)
.MODEL DX   D(IS=1E-15, RS=1m Cjo=10f)
.MODEL DY   D(IS=1E-15 BV=50 Cjo=10f)
.MODEL DEN  D(IS=1E-12, RS=4.0E+2, KF=1.08E-16, AF=1 Cjo=10f)
.MODEL DNOISE D(IS=1E-14,RS=1E-1,KF=3.14E-14)
.MODEL DIN  D(IS=1E-18, RS=1.0E-6, KF=1.82E-14, AF=1)
.MODEL DIN1 D(IS=1E-16, RS=1.0E-0, KF=3.7E-16, AF=1)
.ENDS AD8672
*$





* AD8674 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 10/30V, BIP, OP, Low Noise, Low Ib, 4X
* Developed by: HH/ADI-SJ, Soufiane Bendaoud ADI Silicon valley
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (12/2009) - Corrected unpowered Ibais, PM, PSRR, IVR.  Changed noise gen,
*              Added input C.
* 1.0 ( 07/2003)
* Copyright 2003, 2009, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
* This model simulates typical values at Vs=+/-15V
*
* END Notes
*
* Node assignments
*                      non-inverting input
*                     |    inverting input
*                    |    |    positive supply
*                    |    |     |     negative supply
*                         |    |     |     |   output
*                         |    |     |     |      |
.SUBCKT AD8674            1    2     99    50     39
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
R3   5  99    2.033E+04
R4   6  99    2.033E+04
CIN  1   2    7.45E-12
CCM1 1  50    6.25E-12
CCM2 2  50    6.25E-12
RC   5  56    5.3E+03
CC   56  6    2.14E-13
I1   4  50    300E-06
VI1  450 50   2.7
DI1  450  4   DX
IOS  1   2    3E-9
EOS  9  1    POLY(4)  (31 98) (81 98) (83 98) (73 98)  20E-6  1 1  1 1
Q1   5  2  4  QINN
Q2   6  9  4  QINN
D1   2   1    DX
D2   1   2    DX
GN1  50  2    (60 61)  1.453E-05
GN2  50  1    (62 63)  1.453E-05
*
* GAIN STAGE
*
R7   20 98     1.652E+05
C3   20 98     5.61E-07
G1   98 20     (5 6) 3.603E-01
EV1   98 21 POLY(1) (99 98)  -2.0E0 10E-1
EV2   22 98 POLY(1) (98 50)  -2.3E0 10E-1
D5   21 20     DX
D6   20 22     DX
EPLUS 97 0    99  0  1
ENEG  51 0    50  0  1
Rtemp1 97 51 1meg
*
* COMMON-MODE GAIN NETWORK
*
E5   30 98     POLY(2) (2 50) (1 50)  0  4.196E-03  4.196E-03
RCM1 30 31     1.061E+03
RCM2 31 98     1.592E-01
CCM  30 31     1.000E-06
*
* PSRR NETWORK
*
EPSY 98 72 POLY(1) (99,50) 3.350E-03  9.375E-01
CPS3 72 73 1.000E-06
RPS3 72 73 9.947E+02
RPS4 73 98 1.061E-02
*
* VOLTAGE NOISE REFERENCE OF 2.8nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 26.34E-3
HN  81 98 VN1 2.80E+00
RN2 81 98 1
*
* FLICKER NOISE CORNER
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.65520
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
D60 60 0 DIN1 1000
I60 0 60 1m
D61 61 0 DIN1
I61 0 61 1u
*
* SECOND CURRENT NOISE SOURCE
*
D62 62 0 DIN1
I62 0 62 1u
D63 63 0 DIN1
I63 0 63 1u
*
R17  33 99     1meg
R18  33 50     1meg
C178 33 50    1E-06
C188 33 99    1E-06
EREF  98 0    33  0  1
*
GSY  99 50     POLY(1) 99 50 2.24E-3 15E-6
*
* OUTPUT STAGE
*
R19  34 99     100
R20  34 50     100
G9   34 99     99 20  1.000E-02
G10  50 34     20 50  1.000E-02
*
V3   35 34     0.65
D9   20 35     DX
V4   34 36     0.52;
D10  36 20     DX
*
G7   37 50     20 34  1.0E-2
G8   38 50     34 20  1.0E-2
D11  99 37     DX
D12  99 38     DX
D13  50 37     DY
D14  50 38     DY
*
F1   34  0     V3  1
F2   0  34     V4  1
*
L3   34 39     1E-8;  39 is output pin
*
* MODELS USED
*
.MODEL QINN NPN(BF=3.0E4, VA=130)
.MODEL DX   D(IS=1E-15, RS=1m)
.MODEL DY   D(IS=1E-15 BV=50)
.MODEL DEN  D(IS=1E-12, RS=4.0E+2, KF=1.08E-16, AF=1)
.MODEL DNOISE D(IS=1E-14,RS=1E-1,KF=3.14E-14)
.MODEL DIN  D(IS=1E-18, RS=1.0E-6, KF=1.82E-14, AF=1)
.MODEL DIN1 D(IS=1E-16, RS=1.0E-0, KF=3.7E-16, AF=1)
.ENDS AD8674
*
.subckt AD8675 1 2 3 4 5
C1 N006 N005 {Cf}
A1 N009 0 N010 N010 N010 N010 N005 N010 OTA g={Ga} Iout={Islew} en=2.8n enk=4.5 Vhigh=1e308 Vlow=-1e308
D5 N006 3 X1
D6 4 N006 X2
G2 0 N010 3 0 500µ
R4 N010 0 1K noiseless
G3 0 N010 4 0 500µ
S1 N005 N010 4 3 SD
C4 N004 0 {5p*x} Rpar=1K noiseless
C11 3 2 .95p Rpar=1T noiseless
C18 2 1 8.65p Rpar=1T noiseless
D8 3 1 1nA m=.5
C3 3 5 .25p
C7 5 4 .25p
A2 2 1 0 0 0 0 0 0 OTA g=0 in=.1p ink=1.5K incm=.1p incmk=1.5k
Ö1 N006 3 4 N005 N010 Gm1={Gb} Ibias=2.3m
C2 2 4 .95p Rpar=1T noiseless
C5 3 1 .95p Rpar=1T noiseless
C6 1 4 .95p Rpar=1T noiseless
D1 3 2 1nA m=.5
B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)-2,.1), V(4)+2, .1)+100n*V(2)
B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)-2,.1), V(4)+2, .1)+100n*V(1)
D3 N005 N010 IO
R5 5 N006 22
L1 N004 N007 {5µ*x}
L2 N008 N009 {5µ*x}
C10 N009 0 {5p*x} Rpar=1K noiseless
C8 N007 0 {10p*x}
L3 N007 N008 {5µ*x}
C12 N008 0 {10p*x}
.param Cf = 6p
.param Ro       =  5K
.param Avol     =  4Meg
.param RL       =  2K
.param AVmid =  10
.param FmidA = 1Meg
.param Zomid  = 5
.param FmidZ  = 1Meg
.param Vslew  = 2.5Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.model X1 D(Ron=1m Roff=1G Vfwd=0 epsilon=10m noiseless)
.model X2 D(Ron=1m Roff=1G Vfwd=20m epsilon=10m noiseless)
.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless)
.model 1nA D(Ron=500Meg epsilon=.5 Ilimit=1n noiseless)
.model IO  D(Ron=2K Roff=1T Vfwd={32m/Gb} Vrev={32m/Gb} revepsilon=.1 epsilon=.1 noiseless)
.param X=.6
.ends AD8675
*
* Robert Ritchie
.subckt AD8691 1 2 3 4 5
M1 14A 7A 8A 8A PIXN temp=27
RC5 14A 4 8.00E+02 noiseless
C1 14A 16A 6.29E-12
IOS 1 2 5.00E-14
R1 30A 0 1.00E+06 noiseless
CF N004 30A 1.34E-09 Rser=3.5 noiseless
M5 5 46A 3 3 POXN temp=27
M6 5 47A 4 4 NOXN temp=27
E2 N004 0 5 Mid 1
R4 22A 0 15.9 noiseless
C2 N008 22A 10n Rpar=2.59K noiseless
R5 N008 0 1 noiseless
B1 N008 0 V=1.58m*(V(1)+V(2)-V(3)-V(4))
R6 73A 0 15.9 noiseless
C3 N007 73A 10n Rpar=3.98K noiseless
B2 N007 0 V=-70.3m+14.1m*V(3,4)
RC1 16A 4 8.00E+02 noiseless
A1 0 0 1 1 1 1 7A 1 OTA g=.1 linear Rout=10 en=8.3n enk=280 vlow=-1e308 vhigh=1e308
I2 1 7A 40µ
G2 1 7A 22A 0 100m
G3 1 7A 73A 0 100m
R7 N007 0 1 noiseless
G4 46A 3 0 30A 1
R8 3 46A 1 noiseless
I3 46A 3 602.3m
R9 47A 4 1 noiseless
I4 4 47A 533.7m
G5 4 47A 30A 0 1
R10 3 Mid 20K noiseless
R11 Mid 4 20K noiseless
D1 3 8A Dptail
M2 16A 2 8A 8A PIXN temp=27
B3 0 30A I=16.7m*V(14A,16A)*(.5+.5*tanh(V(30A,Limlow)/100m))*(.5+.5*tanh(V(Limhigh,30A)/100m))
G1 0 Limhigh 3 4 .5m
I1 Limhigh 0 729µ
G6 0 Limhigh 14A 16A 90µ
R12 Limhigh 0 1K noiseless
G7 0 Limlow 4 3 .5m
R13 Limlow 0 1K noiseless
I5 Limlow 0 7µ
G8 0 Limlow 14A 16A 90µ
B4 4 3 I=332u*(.5+.5*tanh((V(3,4)-300m)/120m))
.model PIXN VDMOS(Vto=-.5 Kp=112m lambda=10m Cgs=100f pchan noiseless)
.model NOXN VDMOS(Vto=.328 Kp=27.8m lambda=10m)
.model POXN VDMOS(Vto=-.328 Kp=15.6m Lambda=10m pchan)
.model Dptail D(Ron=100 Roff=1G vfwd=.52 epsilon=100m ilimit=500u noiseless)
.ends AD8691
*
.subckt ADA4000 1 2 3 4 5
A1 2 1 0 0 0 0 0 0 OTA g=0 in=.01p ink=10 incm=.001p incmk=10
M1 3 N005 5 5 N temp=27
M2 4 N005 5 5 P temp=27
C3 3 5 2p
C4 5 4 2p
A2 0 N004 M M M M N005 M OTA g=118u Isrc=90u Isink=-110u en=16n enk=100 Vlow=-1e308 Vhigh=1e308 Cout= 3.15p asym
C10 N004 0 16.45p Rpar=1K noiseless
D1 N005 5 Y
D6 5 N005 Y
C1 2 1 2.625p Rpar=10.1G noiseless
G1 0 M 3 0 1m
G2 0 M 4 0 1m
R3 M 0 1K noiseless
S1 N005 M 4 3 UVLO
D3 N005 3 X1
D4 4 N005 X2
D2 3 4 IQ
I1 1 4 5p load
I2 2 4 5p load
B1 N004 0 I=1m*dnlim(uplim(V(2),V(3)-0,.1), V(4)+4, .1)+100n*V(2)
B2 0 N004 I=1m*dnlim(uplim(V(1),V(3)-1,.1), V(4)+3.5, .1)+100n*V(1)
C6 3 2 1.375p Rpar=4T noiseless
C2 2 4 1.375p Rpar=4T noiseless
C5 3 1 1.375p Rpar=4T noiseless
C7 1 4 1.375p Rpar=4T noiseless
.model X1 D(Ron=2K Roff=100G Vfwd=-.82   epsilon=.1 noiseless)
.model X2 D(Ron=2K Roff=100G Vfwd=-1.27 epsilon=.1 noiseless)
.model Y D(Ron=500 Roff=1T Vfwd=1.2 epsilon=.1 noiseless)
.model N VDMOS(Vto=-250m Kp=24m Ksubthres=.2 noiseless)
.model P VDMOS(Vto=250m Kp=24m pchan Ksubthres=.2 noiseless)
.model UVLO SW(Ron=1K Roff=5G Vt=-3.75 Vh=.25 noiseless)
.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=.35m noiseless)
.ends ADA4000
*
* ADA4051 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 1.8/5V, CMOS, OP, Zero Drift, RRIO, 2X
* Developed by: HH/ADSJ, GEC/ADSJ
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (07/2010) - Modified for 1.8 to 5V Vsy
* 1.0 (11/2009)
* Copyright 2009, 2010, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include: Typical Values at Vsy=5V, Ta=25degC
*
* END Notes
*
* Node Assignments
*                       noninverting input
*                       |   inverting input
*                       |   |    positive supply
*                       |   |    |   negative supply
*                       |   |    |   |   output
*                       |   |    |   |   |
*                       |   |    |   |   |
.SUBCKT ADA4051         1   2   99  50  45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1   4  7  8  8 PIX L=2E-6 W=2.321E-04;  ** D G S
M2   6  2  8  8 PIX L=2E-6 W=2.321E-04
M3  14  7 18 18 NIX L=2E-6 W=8.911E-05
M4  16  2 18 18 NIX L=2E-6 W=8.911E-05
Cincmp 1 50 5E-12
Cincmn 2 50 5E-12
Cindm 1 2 2E-12
RD1  4 50 2E+05
RD2  6 50 2E+05
RD3 99 14 2E+05
RD4 99 16 2E+05
C1   4  6 3.361E-12
C2  14 16 3.361E-12
I1  99  8 2E-06
I2  18 50 2E-06
V1  99  9 0.166E+00
D1   8  9 DX
V2  19 50 0.157E+00
D2  19 18 DX
EOS  7  1 POLY(4) (73,98) (22,98) (81,98) (83,98) 2.00E-06 1 1 1 1
IOS  1  2 2.00E-11
*
*CMRR
*
E1  72 98 POLY(2) (1,98) (2,98) 0 4.708E-04 4.708E-04
R10 72 73 1.061E+01
R20 73 98 1.592E-01
C10 72 73 1.00E-06
*
* PSRR
*
EPSY 21 98 POLY(1) (99, 50) -8.000E-03 1.600E-03
RPS1 21 22 3.183E+01
RPS2 22 98 1.989E-01
CPS1 21 22 1.00E-06
*
* VOLTAGE NOISE REFERENCE OF 95nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 9.3564E+01
RN2 81 98 1
*
* FLICKER NOISE CORNER
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
EVP  97 98 (99,50) 0.36
EVN  51 98 (50,99) 0.36
GSY  99 50 POLY(1) (99,50) 7.6E-06 8.00E-08
*
* GAIN STAGE
*
G1 98 30 POLY(2) (4,6) (14,16) 0 2.608E-04 2.608E-04
R1 30 98 1.00E+06
RZ 45 31 1.855E+3
CF 30 31 5.57E-09
EV3 32 98 Poly(1) (99,50) 0.18125 0.03375;
EV4 98 33 Poly(1) (99,50) -0.13125 0.06625;
D3 30 32 DX
D4 33 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=3E-6 W=2.041E-03
M6  45 47 50 50 NOX L=3E-6 W=8.333E-03
EG1 99 46 POLY(1) (98,30) 7.091E-01 1
EG2 47 50 POLY(1) (30,98) 6.090E-01 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.7,LAMBDA=0.047,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.6,LAMBDA=0.022,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=1.50E-05,VTO=-0.5,LAMBDA=0.03)
.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5,LAMBDA=0.02)
.MODEL DX D(IS=1E-14,RS=0.1)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=0E+00)
*
.ENDS ADA4051
*
*$
* ADA4077 SPICE DMod model Typical values
* Description: Amplifier
* Generic Desc: 30V, BIP, OP, Low Noise, Low THD, 2X
* Developed by: RM ADSJ
* Revision History: 1.0 03/31/2015 - Updated to new header style
* 0.0 (11/2012)
* Copyright 2008, 2012,2015 by Analog Devices
*
* Refer to "README.DOC" file for License Statement.  Use of this
* model indicates your acceptance of the terms and provisions in
* the License Statement.
*
* Node Assignments
*		        noninverting input
*	            	|	inverting input
*		        |	|	positive supply
*		        |	|	|	negative supply
*		        |	|	|	|	output
*		        |	|	|	|	|
*		        |	|	|	|	|
.SUBCKT ADA4077-2 1	2	99	50	45
*
*INPUT STAGE
**4input sacled poly
Q1   15 7 60 NIX
Q2   6 2 61 NIX
IOS  1 2 1.75E-10
I1  5 50 77e-6
EOS  7  1 POLY(4) (14,98) (73,98) (81,98) (70,98)  10E-6 1 1 1 1
RC1  11 15 2.6E4
RC2  11 6 2.6E4
RE1 60 5 0.896E2
RE2 61 5 0.896E2
C1   15 6 4.25E-13
D1  50 9 DX
V1  5  9 DC 1.8
D10 99 10 DX
V6 10 11 1.3
*
* CMRR
*
ECM   13 98 POLY(2) (1,98) (2,98) 0 7.192E-4 7.192E-4
RCM1  13 14 2.15E2
RCM2  14 98 5.31E-3
CCM1  13 14 1E-6
*
* PSRR
*
EPSY 72 98 POLY(1) (99,50) -1.683 0.056
CPS3 72 73 1E-6
RPS3 72 73 7.9577E+1
RPS4 73 98 6.5915E-4
*
* EXTRA POLE AND ZERO
*
G1 21 98 (6,15) 26E-6
R1 21 98 9.8E4
R2 21 22 9E6
C2 22 98 1.7614E-12
D3 21 99 DX
D4 50 21 DX
*
* VOLTAGE NOISE
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 6
RN2 81 98 1
*
* FLICKER NOISE
*
D5 69 98 DNOISE
VSN 69 98 DC .60551
H1 70 98 VSN 30.85
RN 70 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 POLY(1) (99,50) 130E-6 1.7495E-10
*
* GAIN STAGE
*
G2  98 25 (21,98) 1E-6
R5  25 98 9.9E7
CF  45 25 2.69E-12
V4 25 33 5.3
D7 51 33 DX
EVN 51 98 (50,99) 0.5
V3 32 25 5.3
D6 32 97 DX
EVP 97 98 (99,50) 0.5
*
* OUTPUT STAGE
*
Q3   45 41 99 POUT
Q4   45 43 50 NOUT
RB1  40 41 9.25E-4
RB2  42 43 9.25E-4
EB1  99 40 POLY(1) (98,25) 0.7153  1
EB2  42 50 POLY(1) (25,98) 0.7153  1
*
* MODELS
*
.MODEL NIX NPN (BF=71429,IS=1E-16)
.MODEL POUT PNP (BF=200,VAF=50,BR=70,IS=1E-15,RC=71.25)
.MODEL NOUT NPN (BF=200,VAF=50,BR=22,IS=1E-15,RC=29.2)
.MODEL DX D(IS=1E-16, RS=5, KF=1E-15)
.MODEL DNOISE D(IS=1E-16,RS=0,KF=1.095E-14)
.ENDS ADA4077-2
*$


*$

* ADA4091 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/30V, BIP, OP, Low Pwr, RRIO, 2X
* Developed by: HH / AD-SJ
* Revision History: 08/10/2012 - Updated to new header style
* 05/14/2014 - ported to Simplis (JSW)
* 0.0 (04/2009)
* Copyright 2008, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |  inverting input
*                |  |  positive supply
*                |  |  |  negative supply
*                |  |  |  |  output
*                |  |  |  |  |
.SUBCKT ADA4091  1  2  99 50 45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
I1   99   7    8.00E-06
Q1   6    4    7A    QP
Q2   5    3    7B    QP
RE1  7A   7   7.774E+02
RE2  7B   7   7.774E+02
D1   3    99   DX
D2   4    99   DX
D3   50   3    DX
D4   50   4    DX
D5   3    4    DX
D6   4    3    DX
R1   3    8    5E+03
R2   4    2    5E+03
R3   5    50   7.500E4;
R4   6    50   7.500E4;
Cph  5    5A   0.235E-12
Rph  5A   6    300
EOS  8    1    POLY(4) (73,98) (22,98) (81,98) (83,98) -400E-9   1 1 1 1
IOS  3    4     -50E-12
CDiff  1    2    2.5E-12
Cin1   1   50    2E-12
Cin2   2   50    2E-12
*
* INPUT PROTECTION NETWORK
*
X_in1 1 50 Diac1
X_in2 2 50 Diac1
X_in3 1 99 Diac1
X_in4 2 99 Diac1
*
*
RS1  99   39   400.0E3
RS2  39   50   400.0E3
EREF 98   0    (39,0) 1
*
* 1ST GAIN STAGE
*
G1   9  98    (6,5) 1.0E-06
R7   9   98   1E6
*
* 2ND GAIN STAGE AND DOMINANT POLE
*
R8    12   98   1.094E+08
G2    12   98  (98,9) 3.881E-06
D7   12   13   DX
D8   14   12   DX
V1   13   98   +0.2; source
V2   14   98   -0.2; sink
*
* Provision for second pole
*
G3   18   98   (98,12) 1E-05
R11  18   98   1E5
*
* CMRR=90dB, Pole at 1100 Hz
*
ECM  21   98   POLY(2) (1,98) (2,98) 0 1.318E-01 1.318E-01
R10  21   22   1.326E+05
R20  22   98   1.592E+01
C10  21   22   1E-9
*
* PSRR=85dB, POLE AT 300 Hz
*
EPSY 72 98 POLY(1) (99,50) +0.1E-1 1.770E+01
RPS1 72 73 7.958E+02
RPS2 73 98 3.183E-03
CPS1 72 73 1.00E-06
*
* VOLTAGE NOISE REFERENCE OF 24nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 96.300E-3
HN  81 98 VN1 2.397E+01
RN2 81 98 1
*
* FLICKER NOISE CORNER = 300 Hz
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* OUTPUT STAGE
*
Q3   451 41 99 POUT
RB1  40 41 1.5E+03
EB1  99 40 POLY(1) (98,18) 6.190E-01  1E-0;
Q4   451 43 50 NOUT
RB2  42 43 2.0E+03
EB2  42 50 POLY(1) (18,98) 6.155E-01  1E-0;
Lout 45 451  10E-10
RZ  45 453  100
CZ  453  12  4.67E-12
*
GSY  99 50 POLY(1) (99 50) 106.2E-6 -0.89E-06
*
* MODELS
*
.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130)
.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130,IK=6E+00,BR=15,VAR=14.4, RC=30)
.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250,IK=11E+00,BR=30, VAR=20.0, RC=7)
.MODEL DW D(IS=1E-18)
.MODEL DX D()
.MODEL DY D(IS=1E-9)
.MODEL DZ D(IS=1E-6)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=8.640E-12)
*
.SUBCKT Diac1 1 2
Done 1 3 DZ42hh
Dtwo 2 3 DZ42hh
.MODEL DZ42hh D(IS=3.3179E-6, N=2.0, RS=1.0000E-3, CJO=10.00E-12, M=.31349, VJ=.3905, ISR=2.9061E-9, BV=42.0, IBV=5.0E-03, TT=300.0E-9)
.ENDS Diac1
*
*
.ENDS  ADA4091
*

* ADA4092 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/30V, BIP, OP, Low Pwr, RRIO, 4X
* Developed by: HH / AD-SJ
* Revision History: 08/10/2012 - Updated to new header style
* 05/14/2014 - Ported to Simplis (JSW)
* 0.0 (12/2010)
* Copyright 2010, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |  inverting input
*                |  |  positive supply
*                |  |  |  negative supply
*                |  |  |  |  output
*                |  |  |  |  |
.SUBCKT ADA4092  1  2  99 50 45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
Q1   6    4    7A    QP
Q2   5    3    7B    QP
RE1  7A   7   5.656E+02
RE2  7B   7   5.656E+02
I1   99   7    8.00E-06
D1   3    99   DX
D2   4    99   DX
D3   50   3    DX
D4   50   4    DX
D5   3    4    DX
D6   4    3    DX
R1   3    8    5E+03
R2   4    2    5E+03
R3   5    50   7.500E4;
R4   6    50   7.500E4;
Cph  5    5A   0.23E-12
Rph  5A   6    300
EOS  8    1    POLY(4) (73,98) (22,98) (81,98) (83,98) -1.4E-03 1 1 1 1
IOS  3    4     -2.0E-09
CDiff  1    2    2.5E-12
Cin1   1   50    2E-12
Cin2   2   50    2E-12
*
* INPUT PROTECTION NETWORK
*
X_in1 1 50 Diac1
X_in2 2 50 Diac1
X_in3 1 99 Diac1
X_in4 2 99 Diac1
*
*
RS1  99   39   400.0E3
RS2  39   50   400.0E3
EREF 98   0    (39,0) 1
*
* 1ST GAIN STAGE
*
R7    9  98    3.266E+08
G1    9  98  (6,5) 4.303E-06
D7    9  13   DX
D8   14   9   DX
V1   13  98   0.37; sink
V2   14  98   +0.017; source
*
* 2ND GAIN STAGE AND DOMINANT POLE
*
R8   12   98   1.0E+06
G2   12   98  (98,9) 1.0E-06
*
* Provision for second pole
*
G3   18   98   (98,12) 1E-05
R11  18   98   1E5
*
* CMRR
*
ECM  21   98   POLY(2) (1,98) (2,98) 0 7.813E-02 7.813E-02
R10  21   22   2.487E+04
R20  22   98   1.592E+01
C10  21   22   1E-9
*
* PSRR
*
EPSY 72 98 POLY(1) (99,50) +0.1E-6 1.485E+01
RPS1 72 73 5.305E+02
RPS2 73 98 3.183E-03
CPS1 72 73 1.00E-06
*
* VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 25.5E-3
HN  81 98 VN1 3.0E+01
RN2 81 98 1
*
* FLICKER NOISE CORNER
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* OUTPUT STAGE
*
Q3   451 41 99 POUT
RB1  40 41 1.5E+03
EB1  99 40 POLY(1) (98,18) 6.190E-01  1E-0;
Q4   451 43 50 NOUT
RB2  42 43 2.0E+03
EB2  42 50 POLY(1) (18,98) 6.155E-01  1E-0;
Lout 45 451  6.2E-12
RZ  451 453  100
CZ  453  9  4.6E-12
*
GSY  99 50 POLY(1) (99 50) 79.9E-6 -1.04E-06
*
* MODELS
*
.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130)
.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130, BR=3,VAR=15, RC=38);
.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250, BR=7, VAR=20, RC=8);
.MODEL DW D(IS=1E-18)
.MODEL DX D()
.MODEL DY D(IS=1E-9)
.MODEL DZ D(IS=1E-6)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.15E-12)
*
.SUBCKT Diac1 1 2
Done 1 3 DZ42hh
Dtwo 2 3 DZ42hh
.MODEL DZ42hh D(IS=3.3179E-6, N=2.0, RS=1.0000E-3, CJO=10.00E-12, M=.31349, VJ=.3905, ISR=2.9061E-9, BV=42.0, IBV=5.0E-03, TT=300.0E-9)
.ENDS Diac1
.ENDS  ADA4092
*
*





* ADA4096 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 3/30V, BIP, OP, OVP, RRIO, 2X
* Developed by: HH / AD-SJ
* Revision History: 08/10/2012 - Updated to new header style
* 0.0 (07/2011)
* Copyright 2011, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |  inverting input
*                |  |  positive supply
*                |  |  |  negative supply
*                |  |  |  |  output
*                |  |  |  |  |
.SUBCKT ADA4096  1  2  99 50 45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
I1   99   7    8.00E-06
RE1  7   7A    3.714E+03
RE2  7   7B    3.714E+03
Q1   6    4    7A    QP
Q2   5    3    7B    QP
D1   3    99   DX
D2   4    99   DX
D3   50   3    DX
D4   50   4    DX
D5   3    4    DX
D6   4    3    DX
R1   202    8    5E-03
R2   204    4    5E-03
R3   5    50   7.500E4;
R4   6    50   7.500E4;
Cph  5    5A   6.3E-13
Rph  5A   6    400
EOS  8   3    POLY(4) (73,98) (22,98) (81,98) (83,98) -250E-06 1 1 1 1
IOS  3    4     -1.0E-09
CDiff  1    2    6.35E-12
Cin1   1   50    0.67E-12
Cin2   2   50    0.67E-12
*
* INPUT PROTECTION NETWORK
*
J1    1  201  202  JXB ;
J2  201  201  202  JXL ;
J3    2  203  204  JXB ;
J4  203  203  204  JXL
*
* 1ST GAIN STAGE
*
G1   9  98    (6,5) 1.0E-06
R7   9  98   1E6
*
* 2ND GAIN STAGE AND DOMINANT POLE
*
G2    12   98  (98,9) 3.375E-06
R8    12   98  3.4E+08
D7   12   13   DX
D8   14   12   DX
V1   13   98   +0.5;
V2   14   98   -0.2;
*
* Provision for second pole
*
G3   18   98   (98,12) 1E-05
R11  18   98   1E5
C11x 18   98  1E-14
*
* CMRR
*
ECM  21   98   POLY(2) (1,98) (2,98) 0 2.635E-01 2.635E-01
R10  21   22   1.326E+05
R20  22   98   7.958E+00
C10  21   22   1E-9
*
* PSRR
*
EPSY 72 98 POLY(1) (99,50) -1.514E+3 5.048E+01
RPS1 72 73 1.592E+03
RPS2 73 98 1.989E-03
CPS1 72 73 1.00E-06
*
* VOLTAGE NOISE REFERENCE
*
VN1 80 98 0
RN1 80 98 96.300E-3
HN  81 98 VN1 2.397E+01
RN2 81 98 1
*
* FLICKER NOISE CORNER
*
DFN 82 98 DNOISE 1000
IFN 98 82 DC 1E-03
DFN2 182 98 DY
IFN2 98 182 DC 1E-06
GFN 83 98 POLY(1) (182,82) 1.00E-13 1.00E-01
RFN 83 98 1
*
* Current Noise
D60 60 98 DN1 1000
I60 98 60 1E-03
D61 61 98 DN4
I61 98 61 1E-06
G60 1 50 61 60 1.23E-05
G61 2 50 61 60 1.33E-05
*
RS1  99   39   400.0E3
RS2  39   50   400.0E3
EREF 98   0    (39,0) 1
*
GSY  99 50 POLY(1) (99 50) -23.8E-6 -1.109E-06
*
* OUTPUT STAGE
*
Q3   451 41 99 POUT
RB1  40 41 4.37E+03
EB1  99 40 POLY(1) (98,18) 6.218E-01  1E-0;
Q4   451 43 50 NOUT
RB2  42 43 10E+03
EB2  42 50 POLY(1) (18,98) 6.170E-01  1E-0;
Lout 45 451  10E-10
EZ 453 98 (45 98) 1
CZ  453  12  4.94E-12
R99T 201 202 450k
*
* MODELS
*
.MODEL QP PNP(BF=300, IS=1.00E-16, VA=130)
.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130,BR=4.3,VAR=20, RC=75);
.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250,BR=9.5, VAR=18, RC=42);
.MODEL DN1 D IS=1E-16
.MODEL DN4 D IS=1E-16 AF=1 KF=4.35E-17
.MODEL DW D(IS=1E-18)
.MODEL DX D(IS=1E-16)
.MODEL DY D(IS=1E-16,RS=0.1)
.MODEL DZ D(IS=1E-6)
.MODEL DNOISE D(IS=1E-16,RS=0,KF=2.6E-13)
.MODEL JXL PJF(BETA=4E-05 VTO=-2.0 IS=1E-18 LAMBDA=0.008 RD=1E-1
+ RS=5E1 CGD=1E-12 CGS=1E-12)
.MODEL JXB PJF(BETA=10E-05 VTO=-1.6 IS=1E-19 LAMBDA=0.005 RD=1E-1 RS=1.41E3)
.ENDS  ADA4096
*
* ADA4500 SPICE Macro-model
* Function: Amplifier
* Revision History:
* 1.0 (3/2013) - PH/DB - initial release

* Copyright 2013 by Analog Devices
*
*Refer to
*http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html
*for License Statement. Use of this model indicates your acceptance
*of the terms and provisions in the License Statement.
*
*
* Notes:
*
* Node Assignments
*                  noninverting input
*                  |   inverting input
*                  |   |    positive supply
*                  |   |    |    negative supply
*                  |   |    |    |    output
*                  |   |    |    |    |
.SUBCKT ADA4500    1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* input stage
G_TAIL 99 8 40 98 120e-6
mp1 11  7  8  8  pix
mp2 12  2  8  8  pix
RD1 11 50  2.0k
RD2 12 50  2.0k
C1  11 50  5.0pf
C2  12 50  5.0pf
C11  1 50  2.5pf
C12  2 50  2.5pf
C13  1  2  2.0pf
*
* gain stage
* basic gain stage
EXP1 13 98 11 12  10
EXP2 16 98 14 98   1
EXP3 18 98 17 98   1
G1   98 30  19 98 60E-6
R1   30 98  1E6
R13  13 14  1.0K
R15  16 17  2.0K
R16  18 19  1.0K
C15  14 98  1.0PF
C16  17 98  1.0PF
C17  19 98  1.0PF
*
* slew rate enhance
D1  13 15  dx
D2  15 13  dx
G2  98 30  15 98  200E-6
* GR1 is a noiseless 10K resistor
GR1 15 98  15 98  1.0E-4
*
* overload clamp
EVN  98 29  40 98 2.8
EVp  28 98  40 98 2.4
D3   30 28  dx
D4   29 30  dx
*
* output stage
EG1  42 44  98 30  1
EG2  43 41  30 98  1
EG3  47 42  47 33  1
EG4  41 46  32 46  1
EVH  99 47  40 98  0.006
EVL  46 50  40 98  0.006
GG5  33 32  40 98 600E-6
mn6  45 43 46 50  nox
mn8  32 32 46 50  nox
mp5  45 44 47 47  pox
mp7  33 33 47 47  pox
RZ   31 45  560
CC1  30 31  30pf
CC2  30 45  2.0pf
*
* gnd bias
EREF  98 50  99 50  0.50
*
* start up and bias generator
EB1  38 98  36 50  0.755
EB2  40 38  36 37  9.65
GB1  99 37  99 35   5e-6
GB2  99 36  99 35  50e-6
D39  34 52  dx
D40  35 34  dx
D41  99 35  dx
D42  37 50  dx
D43  36 50  dx
R39  52 50  20K
R40  99 34  20K
R41  99 35  40K
R42  37 50  20e6
R43  36 50   2e6
CB1  99 34  40pf
*
* input Vos adjust
* CMRR  (set E23 K = 0.00 to remove CMRR adj)
*E23  23  1  72 98  0.0
E23  23  1  72 98  0.50
*
* This gnd is the only system ground used in this macromodel
* Different versions of SPICE may need gnd, gnd!, GND, GND!, or node 0
* Note gnd is not a pin on the amp macromodel schematic, but gnd is in
* both the amp subckt call pin list and in the subckt header pin list
E71  71 98   8 0 1.0 ;orig = E71  71 98   8 gnd 1.0
*
R71  71 72  500K
R72  72 98  1.0
R73  71 73  100
C72  73 72  200PF
*
* SHOT and FLICKER NOISE (set E25 & E26 K = 0.00 to remove shot noise)
*E25  25 23  81 98 0.00
*E26  25 26  98 82 0.00
E25  25 23  81 98 9.0E-3
E26  25 26  98 82 9.0E-3
G81  82 81  40 98 50E-6
D81  81 98  dnoise
D82  98 82  dnoise
R81  81 98  1.0e6
R82  98 82  1.0e6
*
* WHITE NOISE (set E27 K = 0.00 to remove white noise)
*E27  27 26  98 83  0.00
E27  27 26  98 83  0.690
R83  83 98  20K
R84  83 98  20K
*
* VOS ADJUST (set E28 K = 0.00 to remove VOS adj)
*E28  7 27  40 98  0.00
E28  7 27  40 98  -0.8e-6
*
*
* ESD DIODES
D11  50  1  dx
D12  50  2  dx
D13   1 99  dx
D14   2 99  dx
D15  50 45  dx
D16  45 99  dx
D17  50 99  dz8p50
*
**************************************************************************************
*
.model pix pmos (kp=1.00e-05, vto=-0.700, lambda=0.001, rd=0, w=2000u, l=1.0u)
.model pox pmos (kp=1.00e-05, vto=-0.700, lambda=0.020, rd=0, w=1400u, l=1.0u)
.model nox nmos (kp=2.00e-05, vto=+0.650, lambda=0.020, rd=0, w=700u,  l=1.0u)
.model dx     d (is=1e-14, rs=1.0)
.model dz8p50 d (is=1e-13, rs=1.0, bv=8.50, ibv=5e-4)
.model dnoise d (is=1e-14, rs=1.0, kf=4.78e-11)
*
**************************************************************************************
*
.ENDS ADA4500
*
**************************************************************************************

**************************************************************************************
* ADA4505 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 1.8/5V, CMOS, OP, ZCO, RRIO, 2X
* Developed by: GEC/ADSJ
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (07/2009)
* Copyright 2009, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*    
* Parameters modeled include: VSY=5V, T=25°C
*
* END Notes
*
* Node Assignments
*                       noninverting input
*                       |   inverting input
*                       |   |    positive supply
*                       |   |    |   negative supply
*                       |   |    |   |   output
*                       |   |    |   |   |
*                       |   |    |   |   |
.SUBCKT ADA4505         1   2   99x  50x  45
*
* INPUT STAGE
*
M1   4  7x  8  8 PIX L=1E-6 W=7.80E-02
M2   6  2x  8  8 PIX L=1E-6 W=7.80E-02
* Cinp 1 98 4.7pF
* Cinn 2 98 4.7pF
* Cdiff 7 2 2.5pF
RD1  4 50 800
RD2  6 50 800
C1   4  6 1.26E-09
I1  99  8 5.00E-04
V1   9  8 0.015E-00
D1   9 99 DX
EOS  7  1 POLY(4) (73,98) (22,98) (81,98) (83,98) 5.00E-04 1 1 1 1
IOS  1  2 1.30E-14

RCM1 1 98 223E9 noiseless
RCM2 2 98 223E9 noiseless
Rdiff 7 2 1E6 noiseless

Ibias1 1 98 0.5p
Ibias2 2 98 0.5p

Cinp 1 98 1.3pF
Cinn 2 98 1.3pF
Cdiff 1 2 2.5pF

Einn 2x 98 2 98 1
Einp 7x 98 7 98 1 

*Supply Current

Esupply_plus 99 0 99x 0 1
Esupply_minus 50 0 50x 0 1
Isupply 99x 50x 9.24u

*
* CMRR=107dB, POLE AT 350 Hz
*
*E1  72 98 POLY(2) (1,98) (2,98) 0 0.06381194E-00 0.06381194E-00
E1  72 98 POLY(2) (1,98) (2,98) 0 0.02381194E-00 0.02381194E-00
R10 72 73 454.728E+00
R20 73 98 3.18E-02
C10 72 73 1.00E-06
*
* PSRR=105dB, POLE AT 0.5 Hz
*
*EPSY 21 98 POLY(1) (99,50) -1.374048E-00 .9898096E-00
EPSY 21 98 POLY(1) (99,50) -3.374048E-00 .0988096E-00
RPS1 21 22 3.18E+04
RPS2 22 98 2.65E+00
CPS1 21 22 1.00E-06
*
**Inoise***
FnIN	2	98	Vmeas3	0.7071068
Vmeas3	510	98	dc	0
VnIN	500	98	dc	0.535
DnIN	500	510	DINnoisy
FnIN1	98	2	Vmeas4	0.7071068
Vmeas4	53	98	dc	0
VnIN1	52	98	dc	0.535
DnIN1	52	53	DINnoisy
*
FnIP	1	98	Vmeas5	0.7071068
Vmeas5	310	98	dc	0
VnIP	300	98	dc	0.535
DnIP	300	310	DIPnoisy
FnIP1	98	1	Vmeas6	0.7071068
Vmeas6	330	98	dc	0
VnIP1	320	98	dc	0.535
DnIP1	320	330	DIPnoisy
*
* VOLTAGE NOISE REFERENCE OF 53nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
*HN  81 98 VN1 5.30E+01
HN  81 98 VN1 6.50E+01
RN2 81 98 1
*
* FLICKER NOISE CORNER = 25 Hz
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.647
HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00
RFN 83 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) -4.9999E-04 0.1E-10
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* Extra Poles

*G2 98 999 4 6 26E-6
G2 98 999 4 6 3.6E-6
R2 999 98 3.19E5
R3 999 N027 1e3
C2 N027 98 9.947e-12
D2 999 99 DX
D5 50 999 DX


* GAIN STAGE
*
*G1 98 30 (4,6) 7.809E-05
G1 98 30 (999,98) 4.809E-05
R1 30 98 1E+06
*CF 30 31 3.124E-09
CF 30 31 2.624E-09
RZ 45 31 1.697E+03
V3 32 30 5.43E-01
V4 30 33 5.42E-01
D3 32 97 DX
D4 51 33 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=1.10E-03
M6  45 47 50 50 NOX L=1E-6 W=1.38E-03
EG1 99 46 POLY(1) (98,30) 3.649E-01 1
EG2 47 50 POLY(1) (30,98) 3.610E-01 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=0.1)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=4.78E-11)
.model DINnoisy	D(IS=1.38e-18 KF=0.00e0)
.model DIPnoisy	D(IS=1.38e-18 KF=0.00e0)
*
*
.ENDS ADA4505
*
**************************************************************************************
*

* Copyright (c) 1998-2021 Analog Devices, Inc.  All rights reserved.
*
.subckt ADA4522-1 1 2 3 4 5
D6 4 1 DX
Ccm1 1 4 35p Rser=100 noiseless
Cdm 1 2 7p Rser=200 noiseless
CF N007 N009 7.1p Rser=15k noiseless
M5 5 N006 3 3 POXN temp=27
M6 5 N012 4 4 NOXN temp=27
R4 N010 0 48 noiseless
C3 N011 N010 10n Rpar=18.9K noiseless
R5 N011 0 1 noiseless
G1 0 N011 1 0 5.25m
G8 0 N011 2 0 5.25m
G9 0 N011 0 3 5.25m
G10 0 N011 0 4 5.25m
D9 3 4 Dburn
R10 3 Mid 100Meg noiseless
D10 2 1 Din
G12 0 N009 5 Mid 100m
R12 N009 0 1K noiseless
B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-.2, .1)+1n*V(1) + 2.93p
B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-.21, .1)+1n*V(2)
C1 N004 0 .01f Rpar=100K noiseless
C2 3 N006 15f Rser=3 Rpar=100Meg noiseless
A1 0 N007 3 3 3 3 N006 3 OTA g=10u linear ref=-33.8m vlow=-2.2 vhigh=0
C5 N012 4 15f Rser=3 Rpar=100Meg noiseless
A3 0 N007 4 4 4 4 N012 4 OTA g=10u linear ref=33.8m vlow=0 vhigh=1.7
D1 N007 0 DANTISAT
A5 N005 0 0 0 0 0 N007 0 OTA g=120u asym isource=6.43u isink=-12.7u vlow=-1e308 vhigh=1e308
L1 N009 0 500n Rser=10 noiseless
G7 3 N006 5 3 10m vto=-10m dir=1
G6 N012 4 4 5 10m vto=-8m dir=1
C8 3 5 1p Rpar=100Meg noiseless
C9 5 4 1p Rpar=100Meg noiseless
C10 Mid 4 50p Rser=1Meg Rpar=100Meg noiseless
A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear Rout=1Meg Cout=90f en=sqrt( ( (7.3n*(1+(freq/600K)**2)*(1+freq/10Meg))/((1+(freq/920K)**3.2)))**2+((17p*((freq/350k)**4.6))/(((1+freq/2.4Meg)**1.4)*((1+freq/10Meg)**4)*((1+freq/6.8Meg)**2)*((1+freq/9Meg)**2)))**2) + (.1n*(1+freq/9Meg)**3.5)/(1+freq/70Meg) vlow=-1e308 vhigh=1e308
G2 0 N004 0 N010 1µ
Ccm2 2 4 35p Rser=100 noiseless
D2 1 3 DX
D3 2 3 DX
D4 4 2 DX
D5 3 1 DBIAS
D7 3 2 DBIAS
A2 0 2 0 0 0 0 0 0 OTA g=0 in=.66p*((1+MIN(freq,4k)/15k)**3)/((MAX(freq,5k)/5k)**1.5)
A6 0 1 0 0 0 0 0 0 OTA g=0 in=.66p*((1+MIN(freq,4k)/15k)**3)/((MAX(freq,5k)/5k)**1.5)
.model DX D(IS=1E-14,RS=0.1 noiseless)
.model NOXN VDMOS(Vto=.83  Mtriode=.7 Kp=53.33m RD=38 noiseless)
.model POXN VDMOS(Vto=-.83 Mtriode=.55 Kp=26.67m Theta=10m Rd=7  pchan noiseless)
.model Din D(Ron=150 Roff=30K Rrev=600 vfwd=5.1 epsilon=600m vrev=5.5 revepsilon=600m noiseless)
.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=600m ilimit=211.8u noiseless)
.model DANTISAT D(Ron=1k Roff=30Meg vfwd=1 epsilon=100m vrev=600m revepsilon=100m noiseless)
.model DBIAS D(Ron=100Meg Roff=1T vfwd=600m epsilon=500m ilimit=100p noiseless)
.ends ADA4522-1
*
*
.subckt ADA4522 1 2 3 4 5
D6 4 1 DX
Ccm1 1 4 35p Rser=100 noiseless
Cdm 1 2 7p Rser=200 noiseless
CF N007 N009 7.1p Rser=25k noiseless
M5 5 N006 3 3 POXN temp=27
M6 5 N012 4 4 NOXN temp=27
R4 N010 0 48 noiseless
C3 N011 N010 10n Rpar=18.9K noiseless
R5 N011 0 1 noiseless
G1 0 N011 1 0 5.25m
G8 0 N011 2 0 5.25m
G9 0 N011 0 3 5.25m
G10 0 N011 0 4 5.25m
D9 3 4 Dburn
R10 3 Mid 100Meg noiseless
D10 2 1 Din
G12 0 N009 5 Mid 100m
R12 N009 0 1K noiseless
B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-.2, .1)+1n*V(1) + 2.93p
B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-.21, .1)+1n*V(2)
C1 N004 0 .01f Rpar=100K noiseless
C2 3 N006 15f Rser=3 Rpar=100Meg noiseless
A1 0 N007 3 3 3 3 N006 3 OTA g=300n linear ref=-33.8m vlow=-2.2 vhigh=0
C5 N012 4 15f Rser=3 Rpar=100Meg noiseless
A3 0 N007 4 4 4 4 N012 4 OTA g=300n linear ref=33.8m vlow=0 vhigh=1.7
D1 N007 0 DANTISAT
A5 N005 0 0 0 0 0 N007 0 OTA g=120u asym isource=6.43u isink=-12.7u vlow=-1e308 vhigh=1e308
L1 N009 0 500n Rser=10 noiseless
G7 3 N006 5 3 10m vto=-10m dir=1
G6 N012 4 4 5 10m vto=-8m dir=1
C8 3 5 1p Rpar=100Meg noiseless
C9 5 4 1p Rpar=100Meg noiseless
C10 Mid 4 50p Rser=1Meg Rpar=100Meg noiseless
A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear Rout=1Meg Cout=90f en=sqrt( ( (7.3n*(1+(freq/600K)**2)*(1+freq/10Meg))/((1+(freq/920K)**3.2)))**2+((17p*((freq/350k)**4.6))/(((1+freq/2.4Meg)**1.4)*((1+freq/10Meg)**4)*((1+freq/6.8Meg)**2)*((1+freq/9Meg)**2)))**2) + (.1n*(1+freq/9Meg)**3.5)/(1+freq/70Meg) vlow=-1e308 vhigh=1e308
G2 0 N004 0 N010 1µ
Ccm2 2 4 35p Rser=100 noiseless
D2 1 3 DX
D3 2 3 DX
D4 4 2 DX
D5 3 1 DBIAS
D7 3 2 DBIAS
A2 0 2 0 0 0 0 0 0 OTA g=0 in=.66p*((1+MIN(freq,4k)/15k)**3)/((MAX(freq,5k)/5k)**1.5)
A6 0 1 0 0 0 0 0 0 OTA g=0 in=.66p*((1+MIN(freq,4k)/15k)**3)/((MAX(freq,5k)/5k)**1.5)
.model DX D(IS=1E-14,RS=0.1 noiseless)
.model NOXN VDMOS(Vto=.83  Mtriode=.7 Kp=53.33m RD=38 noiseless)
.model POXN VDMOS(Vto=-.83 Mtriode=.55 Kp=26.67m Theta=10m Rd=7  pchan noiseless)
.model Din D(Ron=150 Roff=30K Rrev=600 vfwd=5.1 epsilon=600m vrev=5.5 revepsilon=600m noiseless)
.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=600m ilimit=211.8u noiseless)
.model DANTISAT D(Ron=1k Roff=30Meg vfwd=1 epsilon=100m vrev=600m revepsilon=100m noiseless)
.model DBIAS D(Ron=100Meg Roff=1T vfwd=600m epsilon=500m ilimit=100p noiseless)
.ends ADA4522
*
*
*
.subckt ADA4528 1 2 3 4 5
Ccm1 1 4 15.75p Rser=100 noiseless
Cdm 1 2 15.7p Rser=200 noiseless
CF N006 N008 3.8p
M5 5 N005 3 3 POXN temp=27
M6 5 N010 4 4 NOXN temp=27
D9 3 4 Dburn
R10 3 Mid 100Meg noiseless
G12 0 N008 5 Mid 100m
R12 N008 0 10 noiseless
B1 0 N007 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1) + 2.93p
B2 N007 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.2, .1)+1n*V(2)
C1 N007 0 .01f Rpar=100K noiseless
C2 3 N005 400f Rser=300k Rpar=10Meg noiseless
A1 0 N006 3 3 3 3 N005 3 OTA g=3u linear ref=-33.5m vlow=-2 vhigh=0
A3 0 N006 4 4 4 4 N010 4 OTA g=3u linear ref=33.5m vlow=0 vhigh=2
D1 N006 0 Dantisat
A5 N004 0 0 0 0 0 N006 0 OTA g=95u iout=1.91u Cout=1p vlow=-1e308 vhigh=1e308
G7 3 N005 5 3 100m vto=-4.8m dir=1
G6 N010 4 4 5 100m vto=-4.3m dir=1
C8 3 5 1p Rpar=100Meg noiseless
C9 5 4 1p Rpar=100Meg noiseless
C10 Mid 4 50p Rser=1Meg Rpar=100Meg noiseless
A4 0 N007 0 0 0 0 N004 0 OTA g=1u linear en=6n*((1+(uplim(freq,170k,10K)/150k)**18)/(1+(uplim(freq,280k,10k)/250k)**18))*(((1+freq/10.2k)/(1+freq/9.8k))**4)*(1+(uplim(freq,1.15Meg,200k)/1Meg)**5)/((1+freq/5Meg)**2) Rout=1Meg Cout=22f vlow=-1e308 vhigh=1e308
D2 1 3 DX temp=27
A2 0 2 0 0 0 0 0 0 OTA g=0 in=.6p
A6 0 1 0 0 0 0 0 0 OTA g=0 in=.6p
C4 N010 4 400f Rser=300k Rpar=10Meg noiseless
D3 2 3 DX temp=27
D4 4 2 DX temp=27
D5 4 1 DX temp=27
Ccm3 3 1 15.75p Rser=100 noiseless
Ccm2 2 4 15.75p Rser=100 noiseless
Ccm4 3 2 15.75p Rser=100 noiseless
D6 1 4 Dbias1
S1 1 3 3 4 Sbias1
D7 3 2 Dbias1
S2 4 2 3 4 Sbias1
D8 2 1 Din
D10 1 2 Din
C5 3 4 20p Rpar=25k noiseless
.model DX D(IS=1E-16,RS=100 noiseless)
.model NOXN VDMOS(Vto=.8  Mtriode=1.8 Kp=30m noiseless)
.model POXN VDMOS(Vto=-.8 Mtriode=1.2 Kp=40m pchan noiseless)
.model Din D(Ron=400k Roff=400k ilimit=5u noiseless)
.model Dburn D(Ron=100 Roff=1G vfwd=600m epsilon=600m ilimit=576.5u noiseless)
.model Dantisat D(Ron=1k Roff=30Meg vfwd=300m epsilon=100m vrev=300m revepsilon=100m noiseless)
.model DBIAS1 D(Ron=1Meg Roff=1Meg ilimit=220p noiseless)
.model SBIAS1 SW(level=2 Ron=1Meg Roff=1e40 vt=.5 vh=-1.5 ilimit= 130p noiseless)
.param RL=10K
.ends ADA4528
*
* ADA4665 SPICE Macro-model Typical Values at Vsy=+/-8V
* Description: Amplifier
* Generic Desc: 5/16V, CMOS, OP, Low Pwr, RRIO, 2X
* Developed by: VW ADSJ
* Revision History: 08/10/2012 - Updated to new header style
* 0.2 (05/2009)
* Copyright 2009, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
* Not Modeled:
*
* Parameters modeled include: Vsy = 16V, Ta = 25C
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |    positive supply
*         |   |    |    negative supply
*         |   |    |    |    output
*         |   |    |    |    |
*         |   |    |    |    |
.SUBCKT ADA4665    1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
M1  4  7  8  8 PIX L=2E-6 W=2.72e-4
M2  6  2  8  8 PIX L=2E-6 W=2.72e-4
M3  14  7 18 18 NIX L=2E-6 W=2.72e-4
M4  16  2 18 18 NIX L=2E-6 W=2.72e-4
Rd1 4 50 1.6E+4
Rd2 6 50 1.6E+4
Rd3 99 14 1.6E+4
Rd4 99 16 1.6E+4
C1  4 6 2.58E-12
C2  14 16 2.58E-12
I1  99  8 2.5E-5
I2  18 50 2.5E-5
V1  99  9 0.940
V2  19 50 0.940
D1   8  9 DX
D2  19 18 DX
EOS  7  1 POLY(4) (22,98) (73,98) (81,98) (83,98) 1e-3 1 1 1 1
IOS  1  2  0.05E-12

*
* CMRR
*
E1 72 98 POLY(2) (1,98) (2,98) 0 2.24e-3 2.24e-3
R10 72 73 3.98E1
R20 73 98 3.18e-1
C10 72 73 1E-6

*
* PSRR
*
EPSY 21 98 POLY(1) (99,50) -18.083 1.1302
CPS3 21 22 1E-6
RPS1 21 22 3.18e3
RPS2 22 98 5.31E-2

*
* VOLTAGE NOISE REFERENCE
*
VN1 80 98 0
RN1 80 98 16.45E-3
*HN  81 98 VN1 24.5
HN  81 98 VN1 25.5
RN2 81 98 1

*
* FLICKER NOISE
*
DFN 82 98 DNOISE
VFN 82 98 DC 0.6551
HFN 83 98 POLY(1) VFN 1e-3 1
RFN 83 98 1

*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 0.5 0.5
GSY  99 50 POLY(1) (99,50) 8.615e-5 4.95e-7
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5


*
* GAIN STAGE
*
G1 98 30 POLY(2) (4,6) (14,16) 0 3.54e-3 3.54e-3
R1 30 98 1e6
CF 31 30 1.99e-9
RZ 31 100 9
EZ 100 98 (45,98) 1
V3 32 30 3.35
V4 30 33 0.85
D3 32 97 DX
D4 51 33 DX

*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=3E-6 W=5.43E-4
M6  45 47 50 50 NOX L=3E-6 W=1.197E-3
EG1 99 46 POLY(1) (98,30) 7e-1 1
EG2 47 50 POLY(1) (30,98) 6e-1 1

*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.02,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.02,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.02,TOX=100E-3)
.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.02,TOX=100E-3)
.MODEL DX D(IS=1E-14,RS=5,KF=1E-15)
.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.94E-10)

.ENDS ADA4665
*
*$





.Subckt ADA4805 100 101 102 103 104 106
* ADA4805 SPICE Macro-model
* Function: Amplifier
*
* Revision History:
* Rev. 2.0 Jul 2014 -BP
* Copyright 2014 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
* for License Statement. Use of this model indicates your acceptance
* of the terms and provisions in the License Staement.
*
* Tested on MultiSim, SiMetrix(NGSpice), PSICE
*
* Not modeled: Distortion, PSRR, Overload recovery, Slew Rate Enhancment,
*                       ShutDown Turn On/Turn Off time
*
* Parameters modeled include:
*   Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, CMRR,
*   Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
*   Capacitive load drive, Quiescent and dynamic supply currents,
*   Shut Down pin functionality, Single supply & offset supply functionality.
*
* Node Assignments
*                             Non-Inverting Input
*                              |     Inverting Input
*                              |      |      Positive supply
*                              |      |      |      Negative supply
*                              |      |      |      |      Output
*                              |      |      |      |      |      ShutDown BAR
*                              |      |      |      |      |      |
*Subckt ADA4805 100 101 102 103 104 106
*#ASSOC Category="Op-Amps" symbol=opamp_6_pd_bar
*
***Power Supplies***
Ibias    102    103    dc    7.4e-6
DzPS    98    102    diode
Iquies    102    98    dc    562.6e-6
S1    98    103    106    113    Switch
R1    102    99    Rideal    1e7
R2    99    103    Rideal    1e7
e1    111    110    102    110    1
e2    110    112    110    103    1
e3    110    0    99    0    1
*
*
***Inputs***
S2    1    100    106    113    Switch
S3    9    101    106    113    Switch
VOS    1    2    dc    9e-6
IbiasP    110    2    dc    470e-9
IbiasN    110    9    dc    470e-9
RinCMP    110    2    Rideal    5e7
RinCMN    9    110    Rideal    5e7
CinCMP    110    2    1e-15
CinCMN    9    110    1e-15
IOS    9    2    dc    4e-10
RinDiff    9    2    Rideal    260e3
CinDiff    9    2    1e-012
*
*
***Non-Inverting Input with Clamp***
g1    3    110    110    2    0.001
RInP    3    110    Rideal    1e3
RX1    40    3    Rideal    0.001
DInP    40    41    diode
DInN    42    40    diode
VinP    111    41    dc    1.55
VinN    42    112    dc    0.45
*
*
***Vnoise***
hVn    6    5    Vmeas1    707.1067812
Vmeas1    20    110    DC    0
Vvn    21    110    dc    0.65
Dvn    21    20    DVnoisy
hVn1    6    7    Vmeas2    707.1067812
Vmeas2    22    110    DC    0
Vvn1    23    110    dc    0.65
Dvn1    23    22    DVnoisy
*
*
***Inoise***
FnIN    9    110    Vmeas3    0.70710678
Vmeas3    51    110    dc    0
VnIN    50    110    dc    0.65
DnIN    50    51    DINnoisy
FnIN1    110    9    Vmeas4    0.70710678
Vmeas4    53    110    dc    0
VnIN1    52    110    dc    0.65
DnIN1    52    53    DINnoisy
*
FnIP    2    110    Vmeas5    0.70710678
Vmeas5    31    110    dc    0
VnIP    30    110    dc    0.65
DnIP    30    31    DIPnoisy
FnIP1    110    2    Vmeas6    0.70710678
Vmeas6    33    110    dc    0
VnIP1    32    110    dc    0.65
DnIP1    32    33    DIPnoisy
*
*
***CMRR***
RcmrrP    3    10    Rideal    1e7
RcmrrN    10    9    Rideal    1e7
g10    11    110    10    110    6e-11
Lcmrr    11    12    5e-3
Rcmrr    12    110    Rideal    1E3
e4    5    3    11    110    1
*
*
***Power Down***
VPD    110    80    dc    0.8
VPD1    81    0    dc    0.4
RPD    110    106    Rideal    5.4e6
ePD    80    113    82    0    1
RDP1    82    0    Rideal    1e3
CPD    82    0    1e-10
S5    81    82    106    113    Switch
*
*
***Feedback Pin***
*RF    105    104    Rideal    0.001
*
*
***VFB Stage***
g200    200    110    7    9    1
R200    200    110    Rideal    250
DzSlewP    201    200    DzSlewP
DzSlewN    201    110    DzSlewN
*
*
***1st Pole***
g210    210    110    200    110    928.1e-9
R210    210    110    Rideal    1.0827e9
C210    210    110    1e-012
*
*
***Output Voltage Clamp-1***
RX2    60    210    Rideal    0.001
DzVoutP    61    60    DzVoutP
DzVoutN    60    62    DzVoutN
DVoutP    61    63    diode
DVoutN    64    62    diode
VoutP    65    63    dc    5.1
VoutN    64    66    dc    5.1
e60    65    110    111    110    1.05
e61    66    110    112    110    1.05
*
*
*** 11 frequency stages ***
g220    220    110    210    110    0.001
R220    220    110    Rideal    1000
C220    220    110    0.9947e-12
*
g230    230    110    220    110    0.001
R230    230    110    Rideal    1000
C230    230    110    0.7579e-12
*
g240    240    110    230    110    0.001
R240    240    110    Rideal    1000
C240    240    110    0.6366e-12
*
g245    245    110    240    110    0.001
R245    245    110    Rideal    1000
C245    245    110    0.6121e-12
*
g250    250    110    245    110    0.001
R250    250    110    Rideal    1000
C250    250    110    0.6121e-12
*
g255    255    110    250    110    0.001
R255    255    110    Rideal    1000
C255    255    110    1e-15
*
g260    260    110    255    110    0.001
R260    260    110    Rideal    1000
C260    260    110    1e-15
*
g265    265    110    260    110    0.001
R265    265    110    Rideal    1000
C265    265    110    1e-15
*
g270    270    110    265    110    0.001
R270    270    110    Rideal    1000
C270    270    110    1e-15
*
e280    280    110    270    110    1
R280    280    285    Rideal    1
L280    285    281    1e-12
C280    281    282    1e-15
R281    282    110    Rideal    1e3
*
e290    290    110    285    110    1
R290    290    292    Rideal    10
L290    290    291    3.36e-9
C290    291    292    227.4e-12
R291    292    110    Rideal    3.3545
e295    295    110    292    110    3.9811
*
*
***Output Stage***
g300    300    110    295    110    0.001
R300    300    110    Rideal    1000
e301    301    110    300    110    1
Rout    301    302    Rideal    50
Lout    302    310    1e-009
Cout    310    110    6e-012
*
*
***Output Current Limit***
VIoutP    71    310    dc    3.65
VIoutN    310    72    dc    2.97
DIoutP    70    71    diode
DIoutN    72    70    diode
Rx3    70    300    Rideal    0.001
*
*
***Output Clamp-2***
VoutP1    111    73    dc    0.71
VoutN1    74    112    dc    0.71
DVoutP1    75    73    diode
DVoutN1    74    75    diode
RX4    75    310    Rideal    0.001
*
*
***Supply Currents***
FIoVcc    314    110    Vmeas8    1
Vmeas8    310    311    DC    0
R314    110    314    Rideal    1e9
DzOVcc    110    314    diode
DOVcc    102    314    diode
RX5    311    312    Rideal    0.001
FIoVee    315    110    Vmeas9    1
Vmeas9    312    313    DC    0
R315    315    110    Rideal    1e9
DzOVee    315    110    diode
DOVee    315    103    diode
*
*
***Output Switch***
S4    104    313    106    113    Switch
*
*
*** Common models***
.model    diode    d(bv=100)
.model    Switch    vswitch(Von=0.401,Voff=0.399,ron=0.001,roff=1e6)
.model    DzVoutP    D(BV=4.3)
.model    DzVoutN    D(BV=4.3)
.model    DzSlewP    D(BV=181.24)
.model    DzSlewN D(BV=181.24)
.model    DVnoisy    D(IS=1.03e-015 KF=8.94e-018)
.model    DINnoisy    D(IS=1.86e-017 KF=9.41e-017)
.model    DIPnoisy    D(IS=1.86e-017 KF=9.41e-017)
.model    Rideal    res(T_ABS=-273)
.ends ADA4805
^
*
* Copyright (c) 1998-2020 Analog Devices, Inc.  All rights reserved.
*
.subckt ADA4807-1 1 2 3 4 5 6
A1 0 X0 0 0 0 0 X1 0 OTA g=1m linear en=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? 3n*(1+4/freq) : 6n*(1+15/freq)) Vlow= -1e308 Vhigh=1e308
C4 X0 0 1e-20 Rpar=1K noiseless
D4 N004 2 bias1
B3 0 X0 I=1m*dnlim(uplim(V(1),V(3)+.6,.1), V(4)-.6, .1)+100n*V(1) - 2.53264n
B4 X0 0 I=1m*dnlim(uplim(V(2),V(3)+.6,.1), V(4)-.6, .1)+100n*V(2)
C5 1 4 .5p Rpar=180Meg noiseless
C9 3 1 .5p Rpar=180Meg noiseless
C10 2 4 .5p Rpar=180Meg noiseless
C11 3 2 .5p Rpar=180Meg noiseless
C18 2 1 .5p Rpar=35K noiseless
D7 N004 1 bias1
D8 3 2 bias2
D9 3 1 bias2
D2 1 3 ED1
D10 4 1 ED1
D11 2 3 ED1
D12 4 2 ED1
A2 0 2 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K
R10 N005 0 {RH*2} noiseless
C1 N005 N007 {Cf}
C2 X2 0 {C1_PZ1} Rser={R1_PZ1} Rpar={R2_PZ1} noiseless
G4 0 XX N005 0 {alpha_PZ2}
C3 XX 0 {C1_PZ2} Rser={R1_PZ2} Rpar={R2_PZ2} noiseless
G5 0 X2 X1 0 {alpha_PZ1}
C6 X1 0 200f Rpar=1K noiseless
M1 5 PG 3 3 PI temp=27
M2 5 NG 4 4 NI temp=27
D1 3 PG DLIMP
D5 NG 4 DLIMN
C7 3 PG {CX} Rser={RX} Lser={LX} RLshunt={RLS} noiseless
B1 4 NG I=(.5+.5*tanh((V(ON)-.5)/100m))*dnlim(vminn/1e6+1.3u*(V(XX)+voffn),vminn/1e6,100n)
B2 PG 3 I=(.5+.5*tanh((V(ON)-.5)/100m))*dnlim(vminp/1e6-1.3u*(V(XX)-voffp),vminp/1e6,100n)
C8 NG 4 {CX} Rser={RX} Lser={LX} RLshunt={RLS} noiseless
C12 3 5 1p Rpar=100Meg Rser=100 noiseless
G1 0 N007 5 Mid 100m
L1 N007 0 1.5n Rser=10 noiseless
A5 X2 0 0 0 0 0 XSMIN 0 OTA g=1.8m asym isource=130u isink=-120u Rout=10k Vhigh=1e308 Vlow=-1e308
D6 2 1 ED2
R11 3 Mid 5Meg noiseless
C13 5 4 1p Rpar=100Meg Rser=100 noiseless
C14 3 N006 6p Rpar=100Meg Rser=100 noiseless
C15 N006 4 6p Rpar=100Meg Rser=100 noiseless
S1 N006 5 0 ON SDIS
C16 N006 5 100f
D13 N005 0 DLIMOD
R12 Mid 4 5Meg noiseless
A6 0 1 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K
S2 3 4 ON 0 Iq
B5 0 N005 I=200u*uplim(dnlim(-V(X2)-600m,0,100m),1,100m)-250u*uplim(dnlim(V(X2)-600m,0,100m),1,100m)
D14 X2 X1 DLS
S3 N004 3 ON 0 SBIAS
C17 3 N004 10f
D15 N004 3 bias3
D16 3 4 DBURN
R4 N011 ON 10Meg noiseless
A4 0 XSMIN ON 0 0 0 N005 0 OTA g=100u linear vlow=-1e308 vhigh=1e308
R6 ON 0 100Meg noiseless
G2 4 N010 3 4 1µ
R5 N010 4 1Meg noiseless
D3 3 6 470nA
A3 N010 6 0 0 0 N011 0 0 SCHMITT Vt=0 Vh=150m Trise=3.5u Tfall=425n vlow=0 vhigh=1.1
I1 N010 4 3.5µ
G3 4 N010 4 N010 100µ vto=-1.335 dir=1
.param Cf = 1p
.param Ro       =  5K
.param Avol     =  3.16Meg
.param RL       =  1K
.param AVmid =  260
.param FmidA = 1Meg
.param Zomid  = 2.1
.param FmidZ  = 10Meg
.param Vslew  = 225Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff=1G Vfwd=-17m epsilon=10m noiseless)
.model X2 D(Ron=1m Roff=1G Vfwd=-47m epsilon=10m noiseless)
.model X SW(Ron={2*Ro} Roff=1T Vt=.5 Vh=-.4 noiseless)
.model IQ SW(Ron=1K Roff=1G Vt=.5 Vh=-.4 Ilimit=151.5u noiseless)
.model bias1 D(Ron=50K Vfwd=1.1 Vrev=-1.1 noiseless)
.model bias2 D(Ron=19Meg  Vfwd=1.1 epsilon=.5 noiseless)
.model bias3 D(Ron=100k vfwd=-500m epsilon=500m ilimit=950n noiseless)
.model ED1 D(Ron=1 Roff=1T Vfwd=.5 epsilon=1 noiseless)
.model ED2 D(Ron=100 Roff=1T Vfwd=1.2 epsilon=1 Vrev=1 revepsilon=1 noiseless)
.model 470nA D(Ron=1Meg Roff=1G Ilimit=470n epsilon=1 Vfwd=1 noiseless)
.param alpha_PZ1=1.0e-6 pole_PZ1=8.8e6 zero_PZ1=22e6
+ R2_PZ1=1.0/alpha_PZ1 R1_PZ1=1.0/(alpha_PZ1*(zero_PZ1/pole_PZ1 - 1.0))
+C1_PZ1=1.0/(2.0*pi*zero_PZ1*R1_PZ1)
.param alpha_PZ2=1.0e-3 pole_PZ2=70e6 zero_PZ2=90e6
+ R2_PZ2=1.0/alpha_PZ2 R1_PZ2=1.0/(alpha_PZ2*(zero_PZ2/pole_PZ2 - 1.0))
+C1_PZ2=1.0/(2.0*pi*zero_PZ2*R1_PZ2)
.param vminp = 400m
.param voffp = 105.8m
.param vminn=400m
.param voffn = 100m
.model PI VDMOS(VTO=-300m mtriode=3 KP=30m pchan noiseless)
.model NI VDMOS(VTO=300m mtriode=4.4 KP=32m noiseless)
.model SDIS SW(Ron=1 Roff=100Meg vt=-.5 vh=-200m noiseless)
.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2.45  epsilon=100m  noiseless)
.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2.45  epsilon=100m noiseless)
.model DLIMOD D(Ron=10 Roff={RH*2} vfwd=1.5 epsilon=200m vrev=2 revepsilon=200m noiseless)
.model DLS D(Ron=10 Roff=10G vfwd=300m epsilon=100m vrev=300m revepsilon=100m noiseless)
.model SBIAS SW(level=2 Ron=1k Roff=10G vt=500m vh=-200m ilimit=1.8u epsilon=100m oneway noiseless)
.model DBURN D(Ron=100k Roff=1G vfwd=1 epsilon=1 ilimit=200n noiseless)
.param CX=4f
.param RX = 400k
.param LX=1.8m
.param RLS = 1Meg
.param vs = 5
.ends ADA4807-1
*
*
*
*
* Copyright (c) 1998-2020 Analog Devices, Inc.  All rights reserved.
*
.subckt ADA4807 1 2 3 4 5 6
A1 0 X0 0 0 0 0 X1 0 OTA g=1m linear en=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? 3n*(1+4/freq) : 6n*(1+15/freq)) Vlow= -1e308 Vhigh=1e308
C4 X0 0 1e-20 Rpar=1K noiseless
D4 N004 2 bias1
B3 0 X0 I=1m*dnlim(uplim(V(1),V(3)+.6,.1), V(4)-.6, .1)+100n*V(1) - 2.53264n
B4 X0 0 I=1m*dnlim(uplim(V(2),V(3)+.6,.1), V(4)-.6, .1)+100n*V(2)
C5 1 4 .5p Rpar=180Meg noiseless
C9 3 1 .5p Rpar=180Meg noiseless
C10 2 4 .5p Rpar=180Meg noiseless
C11 3 2 .5p Rpar=180Meg noiseless
C18 2 1 .5p Rpar=35K noiseless
D7 N004 1 bias1
D8 3 2 bias2
D9 3 1 bias2
D2 1 3 ED1
D10 4 1 ED1
D11 2 3 ED1
D12 4 2 ED1
A2 0 2 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K
R10 N005 0 {RH*2} noiseless
C1 N005 N007 {Cf}
C2 X2 0 {C1_PZ1} Rser={R1_PZ1} Rpar={R2_PZ1} noiseless
G4 0 XX N005 0 {alpha_PZ2}
C3 XX 0 {C1_PZ2} Rser={R1_PZ2} Rpar={R2_PZ2} noiseless
G5 0 X2 X1 0 {alpha_PZ1}
C6 X1 0 200f Rpar=1K noiseless
M1 5 PG 3 3 PI temp=27
M2 5 NG 4 4 NI temp=27
D1 3 PG DLIMP
D5 NG 4 DLIMN
C7 3 PG {CX} Rser={RX} Lser={LX} RLshunt={RLS} noiseless
B1 4 NG I=(.5+.5*tanh((V(ON)-.5)/100m))*dnlim(vminn/1e6+1.3u*(V(XX)+voffn),vminn/1e6,100n)
B2 PG 3 I=(.5+.5*tanh((V(ON)-.5)/100m))*dnlim(vminp/1e6-1.3u*(V(XX)-voffp),vminp/1e6,100n)
C8 NG 4 {CX} Rser={RX} Lser={LX} RLshunt={RLS} noiseless
C12 3 5 1p Rpar=100Meg Rser=100 noiseless
G1 0 N007 5 Mid 100m
L1 N007 0 1.5n Rser=10 noiseless
A5 X2 0 0 0 0 0 XSMIN 0 OTA g=1.8m asym isource=130u isink=-120u Rout=10k Vhigh=1e308 Vlow=-1e308
D6 2 1 ED2
R11 3 Mid 5Meg noiseless
C13 5 4 1p Rpar=100Meg Rser=100 noiseless
C14 3 N006 6p Rpar=100Meg Rser=100 noiseless
C15 N006 4 6p Rpar=100Meg Rser=100 noiseless
S1 N006 5 0 ON SDIS
C16 N006 5 100f
D13 N005 0 DLIMOD
R12 Mid 4 5Meg noiseless
A6 0 1 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K
S2 3 4 ON 0 Iq
B5 0 N005 I=200u*uplim(dnlim(-V(X2)-600m,0,100m),1,100m)-250u*uplim(dnlim(V(X2)-600m,0,100m),1,100m)
D14 X2 X1 DLS
S3 N004 3 ON 0 SBIAS
C17 3 N004 10f
D15 N004 3 bias3
D16 3 4 DBURN
R4 N011 ON 10Meg noiseless
A4 0 XSMIN ON 0 0 0 N005 0 OTA g=100u linear vlow=-1e308 vhigh=1e308
R6 ON 0 100Meg noiseless
G2 4 N010 3 4 1µ
R5 N010 4 1Meg noiseless
D3 3 6 470nA
A3 N010 6 0 0 0 N011 0 0 SCHMITT Vt=0 Vh=150m Trise=3.5u Tfall=425n vlow=0 vhigh=1.1
I1 N010 4 3.5µ
G3 4 N010 4 N010 100µ vto=-1.335 dir=1
.param Cf = 1p
.param Ro       =  5K
.param Avol     =  3.16Meg
.param RL       =  1K
.param AVmid =  260
.param FmidA = 1Meg
.param Zomid  = 2.1
.param FmidZ  = 10Meg
.param Vslew  = 225Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff=1G Vfwd=-17m epsilon=10m noiseless)
.model X2 D(Ron=1m Roff=1G Vfwd=-47m epsilon=10m noiseless)
.model X SW(Ron={2*Ro} Roff=1T Vt=.5 Vh=-.4 noiseless)
.model IQ SW(Ron=1K Roff=1G Vt=.5 Vh=-.4 Ilimit=151.5u noiseless)
.model bias1 D(Ron=50K Vfwd=1.1 Vrev=-1.1 noiseless)
.model bias2 D(Ron=19Meg  Vfwd=1.1 epsilon=.5 noiseless)
.model bias3 D(Ron=100k vfwd=-500m epsilon=500m ilimit=950n noiseless)
.model ED1 D(Ron=1 Roff=1T Vfwd=.5 epsilon=1 noiseless)
.model ED2 D(Ron=100 Roff=1T Vfwd=1.2 epsilon=1 Vrev=1 revepsilon=1 noiseless)
.model 470nA D(Ron=1Meg Roff=1G Ilimit=470n epsilon=1 Vfwd=1 noiseless)
.param alpha_PZ1=1.0e-6 pole_PZ1=8.8e6 zero_PZ1=22e6
+ R2_PZ1=1.0/alpha_PZ1 R1_PZ1=1.0/(alpha_PZ1*(zero_PZ1/pole_PZ1 - 1.0))
+C1_PZ1=1.0/(2.0*pi*zero_PZ1*R1_PZ1)
.param alpha_PZ2=1.0e-3 pole_PZ2=70e6 zero_PZ2=90e6
+ R2_PZ2=1.0/alpha_PZ2 R1_PZ2=1.0/(alpha_PZ2*(zero_PZ2/pole_PZ2 - 1.0))
+C1_PZ2=1.0/(2.0*pi*zero_PZ2*R1_PZ2)
.param vminp = 400m
.param voffp = 105.8m
.param vminn=400m
.param voffn = 100m
.model PI VDMOS(VTO=-300m mtriode=3 KP=30m pchan noiseless)
.model NI VDMOS(VTO=300m mtriode=4.4 KP=32m noiseless)
.model SDIS SW(Ron=1 Roff=100Meg vt=-.5 vh=-200m noiseless)
.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2.45  epsilon=100m  noiseless)
.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2.45  epsilon=100m noiseless)
.model DLIMOD D(Ron=10 Roff={RH*2} vfwd=1.5 epsilon=200m vrev=2 revepsilon=200m noiseless)
.model DLS D(Ron=10 Roff=10G vfwd=300m epsilon=100m vrev=300m revepsilon=100m noiseless)
.model SBIAS SW(level=2 Ron=1k Roff=10G vt=500m vh=-200m ilimit=1.8u epsilon=100m oneway noiseless)
.model DBURN D(Ron=100k Roff=1G vfwd=1 epsilon=1 ilimit=200n noiseless)
.param CX=4f
.param RX = 400k
.param LX=1.8m
.param RLS = 1Meg
.param vs = 5
.ends ADA4807
*
*
.subckt ADA4807-4 1 2 3 4 5
C1 N006 X {Cf}
A1 N005 0 M M M M X M OTA g={Ga} Iout={Islew} en=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? 3n*(1+4/freq) : 6n*(1+15/freq)) Vhigh=1e308 Vlow=-1e308
D21 X 3 ESD
D22 4 X ESD
D5 N006 3 X1
D6 4 N006 X2
G2 0 M 3 0 500µ
R4 M 0 1K noiseless
G3 0 M 4 0 500µ
S1 X M 4 3 SD
C4 N004 0 20p Rpar=1K Rser=10 noiseless
C2 3 N006 .25p
D3 3 4 IQ
D4 3 2 bias1
B3 0 N004 I=1m*dnlim(uplim(V(1),V(3)+.6,.1), V(4)-.6, .1)+100n*V(1)
B4 N004 0 I=1m*dnlim(uplim(V(2),V(3)+.6,.1), V(4)-.6, .1)+100n*V(2)
D1 N007 N006 AA
C5 1 4 .25p Rpar=180Meg noiseless
C9 3 1 .25p Rpar=180Meg noiseless
C10 2 4 .25p Rpar=180Meg noiseless
C11 3 2 .25p Rpar=180Meg noiseless
C18 2 1 .75p Rpar=35K noiseless
D7 3 1 bias1
D8 3 2 bias2
D9 3 1 bias2
D2 1 3 ED1
D10 4 1 ED1
D11 2 3 ED1
D12 4 2 ED1
D13 2 1 ED2
D14 5 3 ED1
D15 4 5 ED1
G4 0 N005 N004 0 1m
L1 N005 0 20µ Cpar=.7p Rser=2k Rpar=2K noiseless
C3 3 5 .25p
C7 5 4 .25p
C8 N006 4 .25p
L2 N007 5 100n Rpar=10 noiseless
A2 2 1 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K incm=.1p incmk=1.5k
B1 3 N006 I=if(V(m,x)>=0, V(m,x)*Gb,0)
B2 N006 4 I=if(V(x,m)>0, V(x,m)*Gb,0)
.param Cf = 6p
.param Ro       =  5K
.param Avol     =  3.16Meg
.param RL       =  1K
.param AVmid =  10
.param FmidA = 18Meg
.param Zomid  = 2.1
.param FmidZ  = 10Meg
.param Vslew  = 225Meg
.param Vmin = 2
.param Roe = 1/(1/RL+1/Ro)
.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe
.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb)
.param RH = Avol/(Ga*Gb*Roe)
.param Islew = Vslew*Cf*(1+1/(Roe*Gb))
.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless)
.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-17m epsilon=10m noiseless)
.model X2 D(Ron=1m Roff={2*Ro} Vfwd=-47m epsilon=10m noiseless)
.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless)
.model IQ D(Ron=1K Roff=100Meg epsilon=1 Ilimit=500u noiseless)
.model AA D(Ron=5 Vrev=0 Ilimit=80m revIlimit=80m noiseless)
.model bias1 D(Ron=50K Ilimit=.9u revilimit=.45u Vfwd=1.1 Vrev=-1.1 noiseless)
.model bias2 D(Ron=19Meg  Vfwd=1.1 epsilon=.5 noiseless)
.model ED1 D(Ron=1 Roff=1T Vfwd=.5 epsilon=1 noiseless)
.model ED2 D(Ron=1 Roff=1T Vfwd=1 epsilon=1 Vrev=1 revepsilon=1 noiseless)
.ends ADA4807-4
*
*ADA4841 Macro-model
*Function:Amplifier
*
*Revision History:
*Rev.x Oct 2015-ZZ
*Copyright 2015 by Analog Devices
*
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
*for License Statement. Use of this model indicates your acceptance
*of the terms and provisions in the License Staement.
*
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
*
*Not modeled: Distortion, PSRR, Overload Recovery,
*             Shutdown Turn On/Turn Off time
*
*Parameters modeled include:
*   Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
*   Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
*   Capacitive load drive, Quiescent and dynamic supply currents,
*   Shut Down pin functionality where applicable,
*   Single supply & offset supply functionality.
*
*Node Assignments
*                Non-Inverting Input
*                |   Inverting Input
*                |   |   Positive supply
*                |   |   |   Negative supply
*                |   |   |   |   Output
*                |   |   |   |   |   PD
*                |   |   |   |   |   |
.Subckt ADA4841 100 101 102 103 104 106
*#ASSOC Category="Op-Amps" symbol=opamp_6_pd
***Power Supplies***
Rz1    102    1020    Rideal    1e-6
Rz2    103    1030    Rideal    1e-6
Ibias    1020    1030    dc    0.04e-3
DzPS    98    1020    diode
Iquies    1020    98    dc    1.16e-3
S1    98    1030    106    113    Switch
R1    1020    99    Rideal    1e7
R2    99    1030    Rideal    1e7
e1    111    110    1020    110    1
e2    110    112    110    1030    1
e3    110    0    99    0    1
*
*
***Inputs***
S2    1    100    106    113    Switch
S3    9    101    106    113    Switch
VOS    1    2    dc    40e-6
IbiasP    110    2    dc    3e-6
IbiasN    110    9    dc    3e-6
RinCMP    110    2    Rideal    180e6
RinCMN    9    110    Rideal    180e6
CinCMP    110    2    1.5e-12
CinCMN    9    110    1.5e-12
IOS    9    2    0.1e-6
RinDiff    9    2    Rideal    25e3
CinDiff    9    2    3e-12
*
*
***Non-Inverting Input with Clamp***
g1    3    110    110    2    0.001
RInP    3    110    Rideal    1e3
RX1    40    3    Rideal    0.001
DInP    40    41    diode
DInN    42    40    diode
VinP    111    41    dc    1.46
VinN    42    112    dc    0.36
*
*
***Vnoise***
hVn    6    5    Vmeas1    707.10678
Vmeas1    20    110    DC    0
Vvn    21    110    dc    0.65
Dvn    21    20    DVnoisy
hVn1    6    7    Vmeas2    707.10678
Vmeas2    22    110    dc    0
Vvn1    23    110    dc    0.65
Dvn1    23    22    DVnoisy
*
*
***Inoise***
FnIN    9    110    Vmeas3    0.7071068
Vmeas3    51    110    dc    0
VnIN    50    110    dc    0.65
DnIN    50    51    DINnoisy
FnIN1    110    9    Vmeas4    0.7071068
Vmeas4    53    110    dc    0
VnIN1    52    110    dc    0.65
DnIN1    52    53    DINnoisy
*
FnIP    2    110    Vmeas5    0.7071068
Vmeas5    31    110    dc    0
VnIP    30    110    dc    0.65
DnIP    30    31    DIPnoisy
FnIP1    110    2    Vmeas6    0.7071068
Vmeas6    33    110    dc    0
VnIP1    32    110    dc    0.65
DnIP1    32    33    DIPnoisy
*
*
***CMRR***
RcmrrP    3    10    Rideal    1e12
RcmrrN    10    9    Rideal    1e12
g10    11    110    10    110    -1e-10
Lcmrr    11    12    1e-12
Rcmrr    12    110    Rideal    1e3
e4    5    3    11    110    1
*
*
***Power Down***
VPD    111    80    dc    1.89
VPD1    81    0    dc    0.42
RPD    111    106    Rideal    0.769e6
ePD    80    113    82    0    1
RDP1    82    0    Rideal    1e3
CPD    82    0    1e-10
S5    81    82    83    113    Switch
CDP1    83    0    1e-12
RPD2    106    83    1e6
*
*
***Feedback Pin***
*RF    105    104    Rideal    0.001
*
*
***VFB Stage***
g200    200    110    7    9    1
R200    200    110    Rideal    250
DzSlewP    201    200    DzSlewP
DzSlewN    201    110    DzSlewN
*
*
***Dominant Pole at 50 Hz***
g210    210    110    200    110    1.2566e-6
R210    210    110    Rideal    3183.1e6
C210    210    110    1e-012
*
*
***Output Voltage Clamp-1***
RX2    60    210    Rideal    0.001
DzVoutP    61    60    DzVoutP
DzVoutN    60    62    DzVoutN
DVoutP    61    63    diode
DVoutN    64    62    diode
VoutP    65    63    dc    5.109
VoutN    64    66    dc    5.109
e60    65    110    111    110    1.086
e61    66    110    112    110    1.086
*
*
***Pole at 128MHz***
g220    220    110    210    110    0.001
R220    220    110    Rideal    1000
C220    220    110    1.2434e-12
*
***Buffer***
g230    230    110    220    110    0.001
R230    230    110    Rideal    1000
*
***Buffer***
g240    240    110    230    110    0.001
R240    240    110    Rideal    1000
*
***Buffer***
g245    245    110    240    110    0.001
R245    245    110    Rideal    1000
*
***Buffer***
g250    250    110    245    110    0.001
R250    250    110    Rideal    1000
*
***Buffer***
g255    255    110    250    110    0.001
R255    255    110    Rideal    1000
*
***Buffer***
g260    260    110    255    110    0.001
R260    260    110    Rideal    1000
*
***Buffer***
g265    265    110    260    110    0.001
R265    265    110    Rideal    1000
*
***Buffer***
g270    270    110    265    110    0.001
R270    270    110    Rideal    1000
*
***Notch: f=110MHz, Zeta=2, Gain=2.6dB***
e280    280    110    270    110    1
R280    280    285    Rideal    10
L280    285    281    13.983e-9
C280    281    282    149.715e-12
R281    282    110    Rideal    28.656
*
***Buffer***
e290    290    110    285    110    1
R290    290    292    Rideal    10
e295    295    110    292    110    1
*
*
***Output Stage***
g300    300    110    295    110    0.001
R300    300    110    Rideal    1000
e301    301    110    300    110    1
Rout    302    303    Rideal     43
Lout    303    310     80e-9
Cout    310    110     8e-12
*
*
***Output Current Limit***
H1    301    304    Vsense1    100
Vsense1    301    302    dc    0
VIoutP    305    304    dc    2.336
VIoutN    304    306    dc    5.336
DIoutP    307    305    diode
DIoutN    306    307    diode
Rx3    307    300    Rideal    0.001
*
*
***Output Clamp-2***
VoutP1    111    73    dc    0.69
VoutN1    74    112    dc    0.69
DVoutP1    75    73    diode
DVoutN1    74    75    diode
RX4    75    310    Rideal    0.001
*
*
***Supply Currents***
FIoVcc    314    110    Vmeas8    1
Vmeas8    310    311    dc    0
R314    110    314    Rideal    1e9
DzOVcc    110    314    diode
DOVcc    102    314    diode
RX5    311    312    Rideal    0.001
FIoVee    315    110    Vmeas9    1
Vmeas9    312    313    dc    0
R315    315    110    Rideal    1e9
DzOVee    315    110    diode
DOVee    315    103    diode
*
*
***Output Switch***
S4    104    313    106    113    Switch
*
*
*** Common Models ***
.model    diode    d(bv=100)
.model    Switch    vswitch(Von=0.425,Voff=0.415,ron=0.001,roff=1e6)
.model    DzVoutP    D(BV=4.3)
.model    DzVoutN    D(BV=4.3)
.model    DzSlewP    D(BV=9.273)
.model    DzSlewN    D(BV=9.273)
.model    DVnoisy    D(IS=1.67e-16 KF=3.26e-17)
.model    DINnoisy    D(IS=7.39e-17 KF=3.69e-16)
.model    DIPnoisy    D(IS=7.39e-17 KF=3.69e-16)
.model    Rideal    res(T_ABS=-273)
*
.ends ADA4841

* ADA4851 SPICE Macro-model
* Description: Amplifier
* Generic Desc: Low Cost Voltage Feedback RR Dual
* Developed by:
* Revision History: 08/10/2012 - Updated to new header style
*
* Copyright 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
* END Notes
*
* Node assignments
.SUBCKT ADA4851 INV NINV OUT VCC VEE
*#ASSOC Category="Op-amps" symbol=opamp
***************************************
* Analog Devices ADA4851
* 2005.03.20 v1.1
* OP AMP modeling services provided by:
* Interface Technologies
* www.i-t.com
***************************************
*  Features included in model
* 1. Open loop gain and phase
* 2. Output voltage and current
* 3. Input Common mode range
* 4. Input Bias current
* 5. Input voltage noise
* 6. Slew rate
* 7. Output current reflected in Vs supplies
* 8. Transient Response
* 9. Frequency Response
***************************************
Q_Q1         V5 92 7 NPN
D_DN5         96 97 DIN
V_V1         VCC_INT N129837 2.7
I_I1         4 VEE_INT DC .05
V_VN2         37 0 2Vdc
R_R3         ISUPP1 0 RCOLD 10meg
C_C1         100 81  4p
E_E5         VEE_INT 0 VEE 0 1
G_G7         100 CMRRP2 CMRRP1 100 .01
G_G2         100 N10305 10 100 1e-2
R_RP1         10 100 RCOLD 100
C_CP3         100 100  1.0610e-12
G_G1         100 10 N06761 100 7.1
D_DN6         97 98 DIN
D_D8         VCC ISUPP1 DNOM
Q_Q2         V6 INV 8 NPN
G_GV         100 N06761 V6 V5 .001
V_VP         VCC_INT VCCVPBAT .499
R_RCM2a         CMRRP1 100 RCOLD 100
G_G3a         100 MAINP2 N10305 100 1e-2
V_VN3         0 93 2
D_D9         ISUPP2 VEE DNOM
C_CP1         100 10  8.07e-6
E_E4         VCC_INT 0 VCC 0 1
R_RCM3         CMRRP2 100 RCOLD 100
R_RC1         VCC_INT V5 RCOLD 101.034
V_VN4         95 0 2
G_GN1         0 NINV 94 0 2.15e-9
R_R4         0 ISUPP2 RCOLD 10meg
D_D5         INV N129837 DP
V_VN         VEEVNBAT VEE_INT .505
G_G5         100 30 VINMID 100 3.162e-8
R_RCM         31 100 RCOLD 1E2
V_VN5         0 96 2
C_CCM2a         100 CMRRP1  2.6526e-11
R_RC2         VCC_INT V6 RCOLD 101.034
D_DZ2         100 16 DLIM
R_RCM1         NINV VINMID RCOLD 1000MEG
E_EBUF         80 100 MAINP2 100 1
V_VN6         98 0 2
G_G10         0 INV 97 0 2.15e-9
C_CCM3         100 CMRRP2  1.9894e-11
L_LCM         31 30  2.274e-3
E_ENIN         92 9 36 0 2.5e-7
R_RE1         7 4 RCOLD 100
D_DN1         35 36 DEN
G_G3         ISUPP1 0 80 81 .02
R_RCM4         CMRR_V 100 RCOLD 100
D_DZ1         N06761 16 DLIM
D_DN2         36 37 DEN
D_D_VCCclamp         10 VCCVPBAT DP
E_EOS         NINV 9 POLY(1) CMRR_V 100 0.0 1
R_RE2         8 4 RCOLD 100
R_RCM2         VINMID INV RCOLD 1000MEG
G_G4         0 ISUPP2 80 81 -.02
L_Lout         OUT 81  60n
R_RP2         N10305 100 RCOLD 100
I_IQP         ISUPP1 0 DC 2.5m
E_E1         100 0 103 0 1
D_D6         0 ISUPP1 DZ
G_G8         100 CMRR_V CMRRP2 100 .01
D_DN3         93 94 DIN
E_E6         103 VEE_INT VALUE { (V(VCC_INT)-V(VEE_INT))/2 }
G_G6         100 CMRRP1 30 100 .01
D_D_VEEclamp         VEEVNBAT 10 DN
D_D7         ISUPP2 0 DZ
R_RP3         MAINP2 100 RCOLD 100
I_IQM         0 ISUPP2 DC 2.5m
R_Rout         80 81 RCOLD 50
D_DN4         94 95 DIN
C_CCM4         100 CMRR_V  1.9894e-12
R_RV         N06761 100 RCOLD 500k
V_VN1         0 35 2Vdc
C_CP2         100 N10305  1.326e-11
.MODEL DLIM D(IS=1E-15 BV=1010)
.MODEL DEN  D(IS=1E-8 RS=1 KF=1E-15 AF=1)
.MODEL DIN  D(IS=.75E-12 RS=100 KF=3e-15 AF=1)
.MODEL   DNOM   D(IS=1E-15 T_ABS=-100)
.MODEL   DZ   D(IS=1E-15 BV=50 T_ABS=-100)
.MODEL  RCOLD   RES T_ABS=-273
.MODEL    DILIM   D(IS=1E-15)
.MODEL NPN  NPN(BF=1.47e4)
.MODEL   DP   D(IS=5E-10 BV=700 )
.MODEL   DN   D(IS=5E-10 BV=700 )
.ENDS ADA4851



*ADA4891 Macro-model
*Function:Amplifier
*
*Revision History:
*Rev.2.1 Oct 2016-JL
*Copyright 2016 by Analog Devices
*
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
*for License Statement. Use of this model indicates your acceptance
*of the terms and provisions in the License Staement.
*
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
*
*Not modeled: Distortion, PSRR, Overload Recovery,
*             Shutdown Turn On/Turn Off time
*
*Parameters modeled include:
*   Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
*   Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
*   Capacitive load drive, Quiescent and dynamic supply currents.
*
*
*
*Node Assignments
*                Non-Inverting Input
*                |   Inverting Input
*                |   |   Positive supply
*                |   |   |   Negative supply
*                |   |   |   |   Output
*                |   |   |   |   |
*                |   |   |   |   |
.Subckt ADA4891 100 101 102 103 104
*
***Power Supplies***
Rz1	102	1020	Rideal	1e-6
Rz2	103	1030	Rideal	1e-6
Ibias	1020	1030	dc	0.01e-3
DzPS	98	1020	diode
Iquies	1020	98	dc	4.39e-3
S1	98	1030	106	113	Switch
R1	1020	99	Rideal	1e7
R2	99	1030	Rideal	1e7
e1	111	110	1020	110	1
e2	110	112	110	1030	1
e3	110	0	99	0	1
*
*
***Inputs***
S2	1	100	106	113	Switch
S3	9	101	106	113	Switch
VOS	1	2	dc	2.5e-3
IbiasP	110	2	dc	2e-12
IbiasN	110	9	dc	2e-12
RinCMP	110	2	Rideal	5000e6
RinCMN	9	110	Rideal	5000e6
CinCMP	110	2	2.2e-12
CinCMN	9	110	2.2e-12
IOS	9	2	1e-15
RinDiff	9	2	Rideal	10000e3
CinDiff	9	2	0.8e-12
*
*
***Non-Inverting Input with Clamp***
g1	3	110	110	2	0.001
RInP	3	110	Rideal	1e3
RX1	40	3	Rideal	0.001
DInP	40	41	diode
DInN	42	40	diode
VinP	111	41	dc	1.26
VinN	42	112	dc	0.16
*
*
***Vnoise***
hVn	6	5	Vmeas1	707.10678
Vmeas1	20	110	DC	0
Vvn	21	110	dc	0.65
Dvn	21	20	DVnoisy
hVn1	6	7	Vmeas2	707.10678
Vmeas2	22	110	dc	0
Vvn1	23	110	dc	0.65
Dvn1	23	22	DVnoisy
*
*
***Inoise***
FnIN	9	110	Vmeas3	0.7071068
Vmeas3	51	110	dc	0
VnIN	50	110	dc	0.65
DnIN	50	51	DINnoisy
FnIN1	110	9	Vmeas4	0.7071068
Vmeas4	53	110	dc	0
VnIN1	52	110	dc	0.65
DnIN1	52	53	DINnoisy
*
FnIP	2	110	Vmeas5	0.7071068
Vmeas5	31	110	dc	0
VnIP	30	110	dc	0.65
DnIP	30	31	DIPnoisy
FnIP1	110	2	Vmeas6	0.7071068
Vmeas6	33	110	dc	0
VnIP1	32	110	dc	0.65
DnIP1	32	33	DIPnoisy
*
*
***CMRR***
RcmrrP	3	10	Rideal	1e12
RcmrrN	10	9	Rideal	1e12
g10	11	110	10	110	-8.437e-9
Lcmrr	11	12	8e-3
Rcmrr	12	110	Rideal	1e3
e4	5	3	11	110	1
*
*
***Power Down***
VPD	111	80	dc	2
VPD1	81	0	dc	1.5
RPD	111	106	Rideal	1e6
ePD	80	113	82	0	1
RDP1	82	0	Rideal	1e3
CPD	82	0	1e-10
S5	81	82	83	113	Switch
CDP1	83	0	1e-12
RPD2	106	83	1e6
*
*
***Feedback Pin***
*RF	105	104	Rideal	0.001
*
*
***VFB Stage***
g200	200	110	7	9	1
R200	200	110	Rideal	250
DzSlewP	201	200	DzSlewP
DzSlewN	201	110	DzSlewN
*
*
***Dominant Pole at 8.88 Hz***
g210	210	110	200	110	3.378e-6
R210	210	110	Rideal	17.92e6
C210	210	110	1e-012
*
*
***Output Voltage Clamp-1***
RX2	60	210	Rideal	0.001
DzVoutP	61	60	DzVoutP
DzVoutN	60	62	DzVoutN
DVoutP	61	63	diode
DVoutN	64	62	diode
VoutP	65	63	dc	5.121
VoutN	64	66	dc	5.095
e60	65	110	111	110	1.27
e61	66	110	112	110	1.27
*
*
***Pole at 500MHz***
g220	220	110	210	110	0.001
R220	220	110	Rideal	1000
C220	220	110	0.3183e-12
*
***Pole at 800MHz***
g230	230	110	220	110	0.001
R230	230	110	Rideal	1000
C230	230	110	0.1989e-12
*
***Pole at 1200MHz***
g240	240	110	230	110	0.001
R240	240	110	Rideal	1000
C240	240	110	0.1326e-12
*
***Pole at 1500MHz***
g245	245	110	240	110	0.001
R245	245	110	Rideal	1000
C245	245	110	0.1061e-12
*
***Pole at 1700MHz***
g250	250	110	245	110	0.001
R250	250	110	Rideal	1000
C250	250	110	0.0936e-12
*
***Buffer***
g255	255	110	250	110	0.001
R255	255	110	Rideal	1000
*
***Buffer***
g260	260	110	255	110	0.001
R260	260	110	Rideal	1000
*
***Buffer***
g265	265	110	260	110	0.001
R265	265	110	Rideal	1000
*
***Buffer***
g270	270	110	265	110	0.001
R270	270	110	Rideal	1000
*
***Buffer***
e280	280	110	270	110	1
R280	280	285	Rideal	10
*
***Peak: f=210MHz, Zeta=0.7, Gain=0.2dB***
e290	290	110	285	110	1
R290	290	292	Rideal	10
L290	290	291	5.413e-9
C290	291	292	106.103e-12
R291	292	110	Rideal	429.314
e295	295	110	292	110	1.0233
*
*
***Output Stage***
g300	300	110	295	110	0.001
R300	300	110	Rideal	1000
e301	301	110	300	110	1
Rout	302	303	Rideal	 36
Lout	303	310	 7e-9
Cout	310	110	 1.3e-12
*
*
***Output Current Limit***
H1	301	304	Vsense1	100
Vsense1	301	302	dc	0
VIoutP	305	304	dc	19.836
VIoutN	304	306	dc	30.036
DIoutP	307	305	diode
DIoutN	306	307	diode
Rx3	307	300	Rideal	0.001
*
*
***Output Clamp-2***
VoutP1	111	73	dc	0.705
VoutN1	74	112	dc	0.695
DVoutP1	75	73	diode
DVoutN1	74	75	diode
RX4	75	310	Rideal	0.001
*
*
***Supply Currents***
FIoVcc	314	110	Vmeas8	1
Vmeas8	310	311	dc	0
R314	110	314	Rideal	1e9
DzOVcc	110	314	diode
DOVcc	102	314	diode
RX5	311	312	Rideal	0.001
FIoVee	315	110	Vmeas9	1
Vmeas9	312	313	dc	0
R315	315	110	Rideal	1e9
DzOVee	315	110	diode
DOVee	315	103	diode
*
*
***Output Switch***
S4	104	313	106	113	Switch
*
*
*** Common Models ***
.model	diode	d(bv=100)
.model	Switch	vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6)
.model	DzVoutP	D(BV=4.3)
.model	DzVoutN	D(BV=4.3)
.model	DzSlewP	D(BV=50.802)
.model	DzSlewN	D(BV=62.643)
.model	DVnoisy	D(IS=2.99e-15 KF=1.02e-14)
.model	DINnoisy	D(IS=3.81e-19 KF=0.00e0)
.model	DIPnoisy	D(IS=3.81e-19 KF=0.00e0)
.model	Rideal	res(T_ABS=-273)
*
.ends ADA4891

*ADA4895 Macro-model
*Function:Amplifier
*
*Revision History:
*Rev.2.1 Jul 2016-JL
*Copyright 2016 by Analog Devices
*
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
*for License Statement. Use of this model indicates your acceptance
*of the terms and provisions in the License Staement.
*
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
*
*Not modeled: Distortion, PSRR, Overload Recovery,
*             Shutdown Turn On/Turn Off time
*
*Parameters modeled include:
*   Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
*   Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
*   Capacitive load drive, Quiescent and dynamic supply currents,
*   Shut Down pin functionality where applicable,
*   Single supply & offset supply functionality.
*
*Node Assignments
*                Non-Inverting Input
*                |   Inverting Input
*                |   |   Positive supply
*                |   |   |   Negative supply
*                |   |   |   |   Output
*                |   |   |   |   |   PD
*                |   |   |   |   |   |
.Subckt ADA4895 100 101 102 103 104 106
*#ASSOC Category="Op-Amps" symbol=opamp_6_pd_bar
***Power Supplies***
Rz1	102	1020	Rideal	1e-6
Rz2	103	1030	Rideal	1e-6
Ibias	1020	1030	dc	0.1e-3
DzPS	98	1020	diode
Iquies	1020	98	dc	2.8e-3
S1	98	1030	106	113	Switch
R1	1020	99	Rideal	1e7
R2	99	1030	Rideal	1e7
e1	111	110	1020	110	1
e2	110	112	110	1030	1
e3	110	0	99	0	1
*
*
***Inputs***
S2	1	100	106	113	Switch
S3	9	101	106	113	Switch
VOS	1	2	dc	53e-6
IbiasP	110	2	dc	11e-6
IbiasN	110	9	dc	11e-6
RinCMP	110	2	Rideal	10e6
RinCMN	9	110	Rideal	10e6
CinCMP	110	2	3e-12
CinCMN	9	110	3e-12
IOS	9	2	-0.02e-6
RinDiff	9	2	Rideal	10e3
CinDiff	9	2	11e-12
*
*
***Non-Inverting Input with Clamp***
g1	3	110	110	2	0.001
RInP	3	110	Rideal	1e3
RX1	40	3	Rideal	0.001
DInP	40	41	diode
DInN	42	40	diode
VinP	111	41	dc	1.36
VinN	42	112	dc	0.56
*
*
***Vnoise***
hVn	6	5	Vmeas1	707.10678
Vmeas1	20	110	DC	0
Vvn	21	110	dc	0.65
Dvn	21	20	DVnoisy
hVn1	6	7	Vmeas2	707.10678
Vmeas2	22	110	dc	0
Vvn1	23	110	dc	0.65
Dvn1	23	22	DVnoisy
*
*
***Inoise***
FnIN	9	110	Vmeas3	0.7071068
Vmeas3	51	110	dc	0
VnIN	50	110	dc	0.65
DnIN	50	51	DINnoisy
FnIN1	110	9	Vmeas4	0.7071068
Vmeas4	53	110	dc	0
VnIN1	52	110	dc	0.65
DnIN1	52	53	DINnoisy
*
FnIP	2	110	Vmeas5	0.7071068
Vmeas5	31	110	dc	0
VnIP	30	110	dc	0.65
DnIP	30	31	DIPnoisy
FnIP1	110	2	Vmeas6	0.7071068
Vmeas6	33	110	dc	0
VnIP1	32	110	dc	0.65
DnIP1	32	33	DIPnoisy
*
*
***CMRR***
RcmrrP	3	10	Rideal	1e12
RcmrrN	10	9	Rideal	1e12
g10	11	110	10	110	-0.746e-9
Lcmrr	11	12	22.7e-3
Rcmrr	12	110	Rideal	1e3
e4	5	3	11	110	1
*
*
***Power Down***
VPD	111	80	dc	2
VPD1	81	0	dc	1.5
RPD	111	106	Rideal	1e6
ePD	80	113	82	0	1
RDP1	82	0	Rideal	1e3
CPD	82	0	1e-10
S5	81	82	83	113	Switch
CDP1	83	0	1e-12
RPD2	106	83	1e6
*
*
***Feedback Pin***
*RF	105	104	Rideal	0.001
*
*
***VFB Stage***
g200	200	110	7	9	1
R200	200	110	Rideal	250
DzSlewP	201	200	DzSlewP
DzSlewN	201	110	DzSlewN
*
*
***Dominant Pole at 9.5 Hz***
g210	210	110	200	110	75.503e-6
R210	210	110	Rideal	16.75e6
C210	210	110	1e-012
*
*
***Output Voltage Clamp-1***
RX2	60	210	Rideal	0.001
DzVoutP	61	60	DzVoutP
DzVoutN	60	62	DzVoutN
DVoutP	61	63	diode
DVoutN	64	62	diode
VoutP	65	63	dc	5.386
VoutN	64	66	dc	5.251
e60	65	110	111	110	1.681
e61	66	110	112	110	1.681
*
*
***Pole at 110MHz***
g220	220	110	210	110	0.001
R220	220	110	Rideal	1000
C220	220	110	1.4469e-12
*
***Pole at 3500MHz***
g230	230	110	220	110	0.001
R230	230	110	Rideal	1000
C230	230	110	0.0455e-12
*
***Zero at 2500MHz***
g240	240	110	230	110	0.001
R240	240	241	Rideal	1000
L240	241	110	0.0637e-6
*
***Pole at 4500MHz***
g245	245	110	240	110	0.001
R245	245	110	Rideal	1000
C245	245	110	0.0354e-12
*
***Buffer***
g250	250	110	245	110	0.001
R250	250	110	Rideal	1000
*
***Buffer***
g255	255	110	250	110	0.001
R255	255	110	Rideal	1000
*
***Buffer***
g260	260	110	255	110	0.001
R260	260	110	Rideal	1000
*
***Buffer***
g265	265	110	260	110	0.001
R265	265	110	Rideal	1000
*
***Buffer***
g270	270	110	265	110	0.001
R270	270	110	Rideal	1000
*
***Notch: f=66MHz, Zeta=1.7, Gain=4.4dB***
e280	280	110	270	110	1
R280	280	285	Rideal	10
L280	285	281	17.845e-9
C280	281	282	325.857e-12
R281	282	110	Rideal	15.161
*
***Peak: f=660MHz, Zeta=1.3, Gain=6.2dB***
e290	290	110	285	110	1
R290	290	292	Rideal	10
L290	290	291	0.927e-9
C290	291	292	62.697e-12
R291	292	110	Rideal	9.599
e295	295	110	292	110	2.0417
*
*
***Output Stage***
g300	300	110	295	110	0.001
R300	300	110	Rideal	1000
e301	301	110	300	110	1
Rout	302	303	Rideal	 50
Lout	303	310	 1.1e-9
Cout	310	110	 2.6e-12
*
*
***Output Current Limit***
H1	301	304	Vsense1	100
Vsense1	301	302	dc	0
VIoutP	305	304	dc	10.936
VIoutN	304	306	dc	10.436
DIoutP	307	305	diode
DIoutN	306	307	diode
Rx3	307	300	Rideal	0.001
*
*
***Output Clamp-2***
VoutP1	111	73	dc	0.725
VoutN1	74	112	dc	0.715
DVoutP1	75	73	diode
DVoutN1	74	75	diode
RX4	75	310	Rideal	0.001
*
*
***Supply Currents***
FIoVcc	314	110	Vmeas8	1
Vmeas8	310	311	dc	0
R314	110	314	Rideal	1e9
DzOVcc	110	314	diode
DOVcc	102	314	diode
RX5	311	312	Rideal	0.001
FIoVee	315	110	Vmeas9	1
Vmeas9	312	313	dc	0
R315	315	110	Rideal	1e9
DzOVee	315	110	diode
DOVee	315	103	diode
*
*
***Output Switch***
S4	104	313	106	113	Switch
*
*
*** Common Models ***
.model	diode	d(bv=100)
.model	Switch	vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6)
.model	DzVoutP	D(BV=4.3)
.model	DzVoutN	D(BV=4.3)
.model	DzSlewP	D(BV=12.965)
.model	DzSlewN	D(BV=12.965)
.model	DVnoisy	D(IS=3.75e-17 KF=9.78e-18)
.model	DINnoisy	D(IS=9.69e-17 KF=2.44e-16)
.model	DIPnoisy	D(IS=9.69e-17 KF=2.44e-16)
.model	Rideal	res(T_ABS=-273)
*
.ends ADA4895

*ADA4896 Macro-model
*Function:Amplifier
*
*Revision History:
*Rev.3.1 Jul 2016-rv
*Copyright 2016 by Analog Devices
*
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
*for License Statement. Use of this model indicates your acceptance
*of the terms and provisions in the License Staement.
*
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
*
*Not modeled: Distortion, PSRR, Overload Recovery,
*             Shutdown Turn On/Turn Off time
*
*Parameters modeled include:
*   Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
*   Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
*   Capacitive load drive, Quiescent and dynamic supply currents,
*   Shut Down pin functionality where applicable,
*   Single supply & offset supply functionality.
*
*Node Assignments
*                Non-Inverting Input
*                |   Inverting Input
*                |   |   Positive supply
*                |   |   |   Negative supply
*                |   |   |   |   Output
*                |   |   |   |   |
.Subckt ADA4896 100 101 102 103 104
*
***Power Supplies***
Rz1	102	1020	Rideal	1e-6
Rz2	103	1030	Rideal	1e-6
R3	96	0	Rideal	1e3
S6	97	96	1020	1030	Sswitch
V2	97	0	dc	2
gBias	1020	1030	96	0	0.3e-3
DzPS	98	1020	diode
gQuies	1020	98	96	0	2.7e-3
S1	98	1030	106	113	Switch
R1	1020	99	Rideal	1e7
R2	99	1030	Rideal	1e7
e1	111	110	1020	110	1
e2	110	112	110	1030	1
e3	110	0	99	0	1
*
*
***Inputs***
S2	1	100	106	113	Switch
S3	9	101	106	113	Switch
VOS	1	2	dc	-28e-6
IbiasP	110	2	dc	-11e-6
IbiasN	110	9	dc	-11e-6
RinCMP	110	2	Rideal	1e7
RinCMN	9	110	Rideal	1e7
CinCMP	110	2	2.6e-12
CinCMN	9	110	2.6e-12
IOS	9	2	-0.02e-6
RinDiff	9	2	Rideal	1e4
CinDiff	9	2	3.4e-12
*
*
***Non-Inverting Input with Clamp***
g1	3	110	110	2	0.001
RInP	3	110	Rideal	1e3
RX1	40	3	Rideal	0.001
DInP	40	41	diode
DInN	42	40	diode
VinP	111	41	dc	0.56
VinN	42	112	dc	0.56
*
*
***Vnoise***
hVn	6	5	Vmeas1	707.10678
Vmeas1	20	110	DC	0
Vvn	21	110	dc	0.65
Dvn	21	20	DVnoisy
hVn1	6	7	Vmeas2	707.10678
Vmeas2	22	110	dc	0
Vvn1	23	110	dc	0.65
Dvn1	23	22	DVnoisy
*
*
***Inoise***
FnIN	9	110	Vmeas3	0.7071068
Vmeas3	51	110	dc	0
VnIN	50	110	dc	0.65
DnIN	50	51	DINnoisy
FnIN1	110	9	Vmeas4	0.7071068
Vmeas4	53	110	dc	0
VnIN1	52	110	dc	0.65
DnIN1	52	53	DINnoisy
*
FnIP	2	110	Vmeas5	0.7071068
Vmeas5	31	110	dc	0
VnIP	30	110	dc	0.65
DnIP	30	31	DIPnoisy
FnIP1	110	2	Vmeas6	0.7071068
Vmeas6	33	110	dc	0
VnIP1	32	110	dc	0.65
DnIP1	32	33	DIPnoisy
*
*
***CMRR***
RcmrrP	3	10	Rideal	1e12
RcmrrN	10	9	Rideal	1e12
g10	11	110	10	110	-1e-10
Lcmrr	11	12	1e-12
Rcmrr	12	110	Rideal	1e3
e4	5	3	11	110	1
*
*
***Power Down***
VPD	111	80	dc	3.4
VPD1	81	0	dc	1.5
RPD	111	106	Rideal	0.286e6
ePD	80	113	82	0	1
RDP1	82	0	Rideal	1e3
CPD	82	0	1e-10
S5	81	82	83	113	Switch
CDP1	83	0	1e-12
RPD2	106	83	1e6
*
*
***Feedback Pin***
*RF	105	104	Rideal	0.001
*
*
***Gain Split***
g200	200	110	7	9	1
R200	200	110	Rideal	1e4
*
*
***Dominant Pole at 452 Hz***
g210	210	110	Value={limit(V(200,110)*8.976e-4,1.459,-1.459)}
R210	210	110	Rideal	3.523e4
C210	210	110	1e-8
*
*
***Output Voltage Clamp-1***
RX2	60	210	Rideal	0.001
DzVoutP	61	60	DzVoutP
DzVoutN	60	62	DzVoutN
DVoutP	61	63	diode
DVoutN	64	62	diode
VoutP	65	63	dc	5.328
VoutN	64	66	dc	5.195
e60	65	110	111	110	1.216
e61	66	110	112	110	1.216
*
*
***Pole at 360MHz***
g220	220	110	210	110	0.001
R220	220	110	Rideal	1000
C220	220	110	0.4421e-12
*
***Pole at 460MHz***
g230	230	110	220	110	0.001
R230	230	110	Rideal	1000
C230	230	110	0.346e-12
*
***Buffer***
g240	240	110	230	110	0.001
R240	240	110	Rideal	1000
*
***Buffer***
g245	245	110	240	110	0.001
R245	245	110	Rideal	1000
*
***Buffer***
g250	250	110	245	110	0.001
R250	250	110	Rideal	1000
*
***Buffer***
g255	255	110	250	110	0.001
R255	255	110	Rideal	1000
*
***Buffer***
g260	260	110	255	110	0.001
R260	260	110	Rideal	1000
*
***Buffer***
g265	265	110	260	110	0.001
R265	265	110	Rideal	1000
*
***Buffer***
g270	270	110	265	110	0.001
R270	270	110	Rideal	1000
*
***Notch: f=94MHz, Zeta=1.9, Gain=3.8dB***
e280	280	110	270	110	1
L280	285	281	12.574e-9
C280	281	282	227.983e-12
R281	282	110	Rideal	18.221
R280	280	285	Rideal	10
*
***Peak: f=90MHz, Zeta=1.7, Gain=0.4dB***
e290	290	110	285	110	1
L290	290	291	5.201e-9
C290	291	292	601.251e-12
R291	292	110	Rideal	212.186
e295	295	110	292	110	1.0471
R290	290	292	Rideal	10
*
*
***Output Stage***
g300	300	110	295	110	0.001
R300	300	110	Rideal	1000
e301	301	110	300	110	1
Rout	302	303	Rideal	 18
Lout	303	310	 6e-9
Cout	310	110	 13e-12
*
*
***Output Current Limit***
H1	301	304	Vsense1	100
Vsense1	301	302	dc	0
VIoutP	305	304	dc	12.836
VIoutN	304	306	dc	12.836
DIoutP	307	305	diode
DIoutN	306	307	diode
Rx3	307	300	Rideal	0.001
*
*
***Output Clamp-2***
VoutP1	111	73	dc	0.795
VoutN1	74	112	dc	0.785
DVoutP1	75	73	diode
DVoutN1	74	75	diode
RX4	75	310	Rideal	0.001
*
*
***Supply Currents***
FIoVcc	314	110	Vmeas8	1
Vmeas8	310	311	dc	0
R314	110	314	Rideal	1e9
DzOVcc	110	314	diode
DOVcc	102	314	diode
RX5	311	312	Rideal	0.001
FIoVee	315	110	Vmeas9	1
Vmeas9	312	313	dc	0
R315	315	110	Rideal	1e9
DzOVee	315	110	diode
DOVee	315	103	diode
*
*
***Output Switch***
S4	104	313	106	113	Switch
*
*
*** Common Models ***
.model	diode	d(bv=100)
.model	Switch	vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6)
.model	Sswitch	vswitch(Von=3,Voff=0.1,ron=1000,roff=1e6)
.model	DzVoutP	D(BV=4.3)
.model	DzVoutN	D(BV=4.3)
.model	DVnoisy	D(IS=3.8e-17 KF=1.33e-17)
.model	DINnoisy	D(IS=2.99e-16 KF=4.63e-17)
.model	DIPnoisy	D(IS=2.99e-16 KF=4.63e-17)
.model	Rideal	res(T_ABS=-273)
*
.ends
*
.subckt ADTL082 1 2 3 4 5
A1 2 1 0 0 0 0 0 0 OTA g=0 in=.01p ink=10 incm=.001p incmk=10
M1 3 N004 5 5 N temp=27
M2 4 N004 5 5 P temp=27
C3 3 5 2p
C4 5 4 2p
C6 3 1 1.375p Rpar=250G noiseless
A2 0 N003 M M M M N004 M OTA g=150u Isrc=90u Isink=-120u en=16n enk=100 Vlow=-1e308 Vhigh=1e308 Cout= 4p asym
C10 N003 0 2p Rpar=1K noiseless
D1 N004 5 Y
D6 5 N004 Y
C1 2 1 4.125p noiseless
G1 0 M 3 0 1m
G2 0 M 4 0 1m
R3 M 0 1K noiseless
S1 N004 M 4 3 UVLO
D3 N004 3 X
D4 4 N004 X
D2 3 4 IQ
C7 1 4 1.375p Rpar=250G noiseless
C8 3 2 1.375p Rpar=250G noiseless
C9 2 4 1.375p Rpar=250G noiseless
I1 1 4 2p load
I2 2 4 2p load
B1 N003 0 I=1m*dnlim(uplim(V(2),V(3)-1,.1), V(4)+3.5, .1)+100n*V(2)
B2 0 N003 I=1m*dnlim(uplim(V(1),V(3)-1,.1), V(4)+3.5, .1)+100n*V(1)
.model X D(Ron=10K Roff=100G Vfwd=-1.25 epsilon=.1 noiseless)
.model Y D(Ron=500 Roff=1T Vfwd=2 epsilon=.1 noiseless)
.model N VDMOS(Vto=-250m Kp=10m Ksubthres=.2 noiseless)
.model P VDMOS(Vto=250m Kp=10m pchan Ksubthres=.2 noiseless)
.model UVLO SW(Ron=1K Roff=5G Vt=-3.75 Vh=.25 noiseless)
.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=4.7m noiseless)
.ends ADTL082
*
.SUBCKT OP113       3  2  7  4  6
*
*  INPUT STAGE
*
R3   4   19   1.5E3
R4   4   20   1.5E3
C1   19  20   5.31E-12
I1   7   18   106E-6
IOS  2    3   25E-09
EOS  12   5   POLY(1) 51 4 25E-06 1
Q1   19   3   18 PNP1
Q2   20  12   18 PNP1
CIN  3    2   3E-12
D1   3    1   DY
D2   2    1   DY
EN   5    2   22  0  1
GN1  0    2   25  0  1E-5
GN2  0    3   28  0  1E-5
*
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
*
DN1  21  22   DEN
DN2  22  23   DEN
VN1  21   0   DC 2
VN2  0   23   DC 2
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
DN3  24  25   DIN
DN4  25  26   DIN
VN3  24   0   DC 2
VN4  0   26   DC 2
*
* SECOND CURRENT NOISE SOURCE
*
DN5  27  28   DIN
DN6  28  29   DIN
VN5  27   0   DC 2
VN6  0   29   DC 2
*
* GAIN STAGE & DOMINANT POLE AT 2HZ
*
G2   34  36   19 20 2.65E-04
R7   34  36   39E6
V3   35   4   DC  6
D4   36  35   DX
VB2  34   4   1.6
*
* SUPPLY/2 GENERATOR
*
ISY  7    4   0.2E-3
R10  7   60   40E3
R11  60   4   40E3
C3   60   0   1E-9
*
* CMRR STAGE & POLE AT 6kHZ
*
ECM  50   4   POLY(2) 3 60 2 60 0 0.8 0.8
CCM  50  51   26.5E-12
RCM1 50  51   1E6
RCM2 51   4   1
*
* OUTPUT STAGE
*
R12  37  36  1E3
R13  38  36  500
C4   37   6  20E-12
C5   38  39  20E-12
M1   39  36  4   4   MN  L=9E-6  W=1000E-6  AD=15E-9 AS=15E-9
M2   45  36  4   4   MN  L=9E-6  W=1000E-6  AD=15E-9 AS=15E-9
D5   39  47  DX
D6   47  45  DX
Q3   39  40  41  QPA  8
VB   7   40  DC  0.861
R14  7   41  375
Q4   41   7  43  QNA  1
R17  7   43  15
Q5   43  39  6   QNA  20
Q6   46  45  6   QPA  20
R18  46   4  15
Q7   36  46  4   QNA  1
M3   6   36  4   4   MN  L=9E-6  W=2000E-6  AD=30E-9 AS=30E-9
*
* NONLINEAR MODELS USED
*
.MODEL DX D (IS=1E-15)
.MODEL DY D (IS=1E-15  BV=7)
.MODEL PNP1 PNP (BF=220)
.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1)
.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1)
.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3
+ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573
+ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12
+ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30)
.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3
+ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13
+ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4
+ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30)
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8
+ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4
+ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33)
.ENDS OP113

* OP177A SPICE Macro-model
* Description: Amplifier
* Generic Desc: 6/30V, BIP, OP, Low Vos, Low TcVos, 1X
* Developed by: JCB / PMI
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (12/1990) - Re-ordered subcircuit call out nodes to put the output node last.
*           - Changed Ios from 1E-9 to 0.5E-9
*             - Added F1 and F2 to fix short circuit current limit.
* Copyright 1990, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
* This version of the OP-177 model simulates the worst case
* parameters of the 'A' grade.  The worst case parameters
* used correspond to those in the data book.
*
* END Notes
*
* Node assignments
*                non-inverting input
*                | inverting input
*                | | positive supply
*                | | |  negative supply
*                | | |  |  output
*                | | |  |  |
.SUBCKT OP177A   1 2 99 50 39
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE & POLE AT 6 MHZ
*
R1   2   3    5E11
R2   1   3    5E11
R3   5  97    0.0606
R4   6  97    0.0606
CIN  1   2    4E-12
C2   5   6    218.9E-9
I1   4  51    1
IOS  1   2    0.5E-9
EOS  9  10    POLY(1)  30 33  10E-6  1
Q1   5  2  7  QX
Q2   6  9  8  QX
R5   7   4    0.009
R6   8   4    0.009
D1   2   1    DX
D2   1   2    DX
EN   10  1    12  0  1
GN1  0   2    15  0  1
GN2  0   1    18  0  1
*
EREF  98 0    33  0  1
EPLUS 97 0    99  0  1
ENEG  51 0    50  0  1
*
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
*
DN1  11  12   DEN
DN2  12  13   DEN
VN1  11   0   DC 2
VN2  0   13   DC 2
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
DN3  14  15   DIN
DN4  15  16   DIN
VN3  14   0   DC 2
VN4  0   16   DC 2
*
* SECOND CURRENT NOISE SOURCE
*
DN5  17  18   DIN
DN6  18  19   DIN
VN5  17   0   DC 2
VN6  0   19   DC 2
*
* FIRST GAIN STAGE
*
R7   20 98     1
G1   98 20     5  6  119.8
D3   20 21     DX
D4   22 20     DX
E1   97 21     POLY(1) 97 33 -2.4 1
E2   22 51     POLY(1) 33 51 -2.4 1
*
* GAIN STAGE & DOMINANT POLE AT 0.127 HZ
*
R8   23 98     1.253E9
C3   23 98     1E-9
G2   98 23     20 33  33.3E-6
V1   97 24     1.8
V2   25 51     1.8
D5   23 24     DX
D6   25 23     DX
*
* NEGATIVE ZERO AT -4MHZ
*
R9   26 27     1
C4   26 27     -39.75E-9
R10  27 98     1E-6
E3   26 98     23 33  1E6
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ
*
R13  30 31     1
L2   31 98     2.52E-3
G4   98 30     3  33  0.316E-6
D7   30 97     DX
D8   51 30     DX
*
* POLE AT 2 MHZ
*
R14  32 98     1
C5   32 98     79.5E-9
G5   98 32     27 33  1
*
* OUTPUT STAGE
*
R15  33 97     1
R16  33 51     1
GSY  99 50     POLY(1) 99 50 0.725E-3 0.0425E-3
F1   34  0     V3  1
F2   0  34     V4  1
R17  34 99     400
R18  34 50     400
L3   34 39     2E-7
G6   37 50     32 34  2.5E-3
G7   38 50     34 32  2.5E-3
G8   34 99     99 32  2.5E-3
G9   50 34     32 50  2.5E-3
V3   35 34     6.8
V4   34 36     4.4
D9   32 35     DX
D10  36 32     DX
D11  99 37     DX
D12  99 38     DX
D13  50 37     DY
D14  50 38     DY
*
* MODELS USED
*
.MODEL QX NPN(BF=333.3E6)
.MODEL DX   D(IS=1E-15)
.MODEL DY   D(IS=1E-15 BV=50)
.MODEL DEN  D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1)
.MODEL DIN  D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1)
.ENDS OP177A



* OP191 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/12V, BIP, OP, RRIO, OVP, 1X
* Developed by: ARG / PMI. TRW / ADI
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (11/1994)
* Copyright 1994, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |  inverting input
*                |  |  positive supply
*                |  |  |  negative supply
*                |  |  |  |  output
*                |  |  |  |  |
.SUBCKT OP191    1  2  99 50 45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
I1   99   7    8.06E-6
Q1   6    4    7    QP
Q2   5    3    7    QP
D1   3    99   DX
D2   4    99   DX
D3   3    4    DX
D4   4    3    DX
R1   3    8    5E3
R2   4    2    5E3
R3   5    50   6.4654E3
R4   6    50   6.4654E3
EOS  8    1    POLY(1) 16 39 -80E-6 1
IOS  3    4    50E-12
GB1  3    98   21 98 50E-9
GB2  4    98   21 98 50E-9
CIN  1    2    1E-12
*
* 1ST GAIN STAGE
*
EREF 98   0    39 0 1
G1   98   9    6 5 31.667E-6
R7   9    98   1E6
EC1  99   10   POLY(1) 99 39  -0.52 1
EC2  11   50   POLY(1) 39 50 -0.52 1
D5   9    10   DX
D6   11   9    DX
*
* 2ND GAIN STAGE AND DOMINANT POLE AT 36HZ
*
G2   98   12   9 39 8E-6
R8   12   98   276.311E6
C2   12   98   16E-12
D7   12   13   DX
D8   14   12   DX
V1   99   13   0.58
V2   14   50   0.58
*
* COMMON MODE STAGE
*
ECM  15   98   POLY(2) 1 39 2 39 0 0.5 0.5
R9   15   16   1E6
R10  16   98   10
*
* POLE AT 2.5MHZ
*
G3   98   18   12 39 1E-6
R11  18   98   1E6
C4   18   98   63.662E-15
*
* BIAS CURRENT-VS-COMMON MODE VOLTAGE
*
EP   97   0    99 0 1
VB   99   17   1.3
RB   17   50   1E9
E3   19   0    15 17 16
D13  19   20   DX
R12  20   0    1E6
G4   98   21   20 0 1E-3
R13  21   98   5E3
D14  21   22   DY
E4   97   22   POLY(1) 99 98 -0.765 1
*
* POLE AT 100MHZ
*
G6   98   40   18 39 1E-6
R20  40   98   1E6
C10  40   98   1.592E-15
*
* OUTPUT STAGE
*
RS1  99   39   109.375E3
RS2  39   50   109.375E3
RO1  99   45   41.667
RO2  45   50   41.667
G7   45   99   99 40 24E-3
G8   50   45   40 50 24E-3
G9   98   60   45 40 24E-3
D9   60   61   DX
D10  62   60   DX
V7   61   98   DC 0
V8   98   62   DC 0
FSY  99   50   POLY(2) V7 V8 0.207E-3  1  1
D11  41   45   DZ
D12  45   42   DZ
V5   40   41   0.131
V6   42   40   0.131
.MODEL DX D()
.MODEL DY D(IS=1E-9)
.MODEL DZ D(IS=1E-6)
.MODEL QP PNP(BF=133.333)
.ENDS OP191






* OP213 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 4/30V, BIP, OP, Low Noise, Low Drift, 2X
* Developed by: JCB / PMI
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (09/1992)
* Copyright 1992, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*
*                   non-inverting input
*                   |  inverting input
*                   |  |  positive supply
*                   |  |  |  negative supply
*                   |  |  |  |  output
*                   |  |  |  |  |
.SUBCKT OP213       3  2  7  4  6
*#ASSOC Category="Op-amps" symbol=opamp
*
*  INPUT STAGE
*
R3   4   19   1.5E3
R4   4   20   1.5E3
C1   19  20   5.31E-12
I1   7   18   106E-6
IOS  2    3   25E-09
EOS  12   5   POLY(1) 51 4 25E-06 1
Q1   19   3   18 PNP1
Q2   20  12   18 PNP1
CIN  3    2   3E-12
D1   3    1   DY
D2   2    1   DY
EN   5    2   22  0  1
GN1  0    2   25  0  1E-5
GN2  0    3   28  0  1E-5
*
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
*
DN1  21  22   DEN
DN2  22  23   DEN
VN1  21   0   DC 2
VN2  0   23   DC 2
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
DN3  24  25   DIN
DN4  25  26   DIN
VN3  24   0   DC 2
VN4  0   26   DC 2
*
* SECOND CURRENT NOISE SOURCE
*
DN5  27  28   DIN
DN6  28  29   DIN
VN5  27   0   DC 2
VN6  0   29   DC 2
*
* GAIN STAGE & DOMINANT POLE AT   .2000E+01 HZ
*
G2   34  36   19 20 2.65E-04
R7   34  36   39E+06
V3   35   4   DC  6
D4   36  35   DX
VB2  34   4   1.6
*
* SUPPLY/2 GENERATOR
*
ISY  7    4   0.2E-3
R10  7   60   40E+3
R11  60   4   40E+3
C3   60   0   1E-9
*
* CMRR STAGE & POLE AT   6 kHZ
*
ECM  50   4   POLY(2) 3 60 2 60 0 0.8 0.8
CCM  50  51   26.5E-12
RCM1 50  51   1E6
RCM2 51   4   1
*
* OUTPUT STAGE
*
R12  37  36  1E3
R13  38  36  500
C4   37   6  20E-12
C5   38  39  20E-12
M1   39  36  4   4   MN  L=9E-6  W=1000E-6  AD=15E-9 AS=15E-9
M2   45  36  4   4   MN  L=9E-6  W=1000E-6  AD=15E-9 AS=15E-9
D5   39  47  DX
D6   47  45  DX
Q3   39  40  41  QPA  8
VB   7   40  DC  0.861
R14  7   41  375
Q4   41   7  43  QNA  1
R17  7   43  15
Q5   43  39  6   QNA  20
Q6   46  45  6   QPA  20
R18  46   4  15
Q7   36  46  4   QNA  1
M3   6   36  4   4   MN  L=9E-6  W=2000E-6  AD=30E-9 AS=30E-9
*
* NONLINEAR MODELS USED
*
.MODEL DX D (IS=1E-15)
.MODEL DY D (IS=1E-15  BV=7)
.MODEL PNP1 PNP (BF=220)
.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1)
.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1)
.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3
+ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573
+ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12
+ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30)
.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3
+ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13
+ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4
+ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30)
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8
+ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4
+ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33)
*
.ENDS OP213






* OP291 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/12V, BIP, OP, RRIO, OVP, 2X
* Developed by: ARG / PMI
* Revision History: 08/10/2012 - Updated to new header style
* 1.1 (02/2011) - Remove extraneous "(" in E4 line
* 1.0 (05/1994)
* Copyright 1994, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*                    non-inverting input
*                    |  inverting input
*                    |  |  positive supply
*                    |  |  |  negative supply
*                    |  |  |  |  output
*                    |  |  |  |  |
.SUBCKT OP291       1  2  99 50 45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
I1   99   7    8.06E-6
Q1   6    4    7    QP
Q2   5    3    7    QP
D1   3    99   DX
D2   4    99   DX
D3   3    4    DX
D4   4    3    DX
R1   3    8    5E3
R2   4    2    5E3
R3   5    50   6.4654E3
R4   6    50   6.4654E3
EOS  8    1    POLY(1) (16,39) -80E-6 1
IOS  3    4    50E-12
GB1  3    98   (21,98) 50E-9
GB2  4    98   (21,98) 50E-9
CIN  1    2    1E-12
*
* 1ST GAIN STAGE
*
EREF 98   0    (39,0) 1
G1   98   9    (6,5) 31.667E-6
R7   9    98   1E6
EC1  99   10   POLY(1) (99,39) -0.52 1
EC2  11   50   POLY(1) (39,50) -0.52 1
D5   9    10   DX
D6   11   9    DX
*
* 2ND GAIN STAGE AND DOMINANT POLE AT 36HZ
*
G2   98   12   (9,39) 8E-6
R8   12   98   276.311E6
C2   12   98   16E-12
D7   12   13   DX
D8   14   12   DX
V1   99   13   0.58
V2   14   50   0.58
*
* COMMON MODE STAGE
*
ECM  15   98   POLY(2) (1,39) (2,39) 0 0.5 0.5
R9   15   16   1E6
R10  16   98   10
*
* POLE AT 2.5MHZ
*
G3   98   18   (12,39) 1E-6
R11  18   98   1E6
C4   18   98   63.662E-15
*
* BIAS CURRENT-VS-COMMON MODE VOLTAGE
*
EP   97   0    (99,0) 1
VB   99   17   1.3
RB   17   50   1E9
E3   19   0    (15,17) 16
D13  19   20   DX
R12  20   0    1E6
G4   98   21   (20,0) 1E-3
R13  21   98   5E3
D14  21   22   DY
E4   97   22   POLY(1) (99,98) -0.765 1
*
* POLE AT 100MHZ
*
G6   98   40   (18,39) 1E-6
R20  40   98   1E6
C10  40   98   1.592E-15
*
* OUTPUT STAGE
*
RS1  99   39   109.375E3
RS2  39   50   109.375E3
RO1  99   45   41.667
RO2  45   50   41.667
G7   45   99   (99,40) 24E-3
G8   50   45   (40,50) 24E-3
G9   98   60   (45,40) 24E-3
D9   60   61   DX
D10  62   60   DX
V7   61   98   DC 0
V8   98   62   DC 0
FSY  99   50   POLY(2) V7 V8 0.207E-3  1  1
D11  41   45   DZ
D12  45   42   DZ
V5   40   41   0.131
V6   42   40   0.131
.MODEL DX D()
.MODEL DY D(IS=1E-9)
.MODEL DZ D(IS=1E-6)
.MODEL QP PNP(BF=133.333)
.ENDS OP291
*$








* OP296 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 3/15V, BIP, OP, Low Pwr, RRIO, 2X
* Developed by: ARG / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (05/1995)
* Copyright 1995, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |  inverting input
*                |  |  positive supply
*                |  |  |  negative supply
*                |  |  |  |  output
*                |  |  |  |  |
.SUBCKT OP296    1  2  99 50 49
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
IREF 21 50 1U
QB1 21 21 99 99 QP 1
QB2 22 21 99 99 QP 1
QB3 4 21 99 99 QP 1.5
QB4 22 22 50 50 QN 2
QB5 11 22 50 50 QN 3
Q1 5 4 7 50 QN 2
Q2 6 4 8 50 QN 2
Q3 4 4 7 50 QN 1
Q4 4 4 8 50 QN 1
Q5 50 1 7 99 QP 2
Q6 50 3 8 99 QP 2
EOS 3 2 POLY(1) (17,98) 35U 1
Q7 99 1 9 50 QN 2
Q8 99 3 10 50 QN 2
Q9 12 11 9 99 QP 2
Q10 13 11 10 99 QP 2
Q11 11 11 9 99 QP 1
Q12 11 11 10 99 QP 1
R1 99 5 50K
R2 99 6 50K
R3 12 50 50K
R4 13 50 50K
IOS 1 2 0.75N
C10 5 6 3.183P
C11 12 13 3.183P
CIN 1 2 1P
*
* GAIN STAGE
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U
R10 15 98 251.641MEG
CC 15 49 8P
D1 15 99 DX
D2 50 15 DX
*
* COMMON MODE STAGE
*
ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
R11 16 17 1E6
R12 17 98 10
*
* OUTPUT STAGE
*
ISY 99 50 20E-6
EIN 35 50 POLY(1) (15,98) 1.42735 1
Q24 37 35 36 50 QN 1
QD4 37 37 38 99 QP 1
Q27 40 37 38 99 QP 1
R5 36 39 150K
R6 99 38 45K
Q26 39 42 50 50 QN 3
QD5 40 40 39 50 QN 1
Q28 41 40 44 50 QN 1
QL1 37 41 99 99 QP 1
R7 99 41 10.7K
I4 99 43 2U
QD7 42 42 50 50 QN 2
QD6 43 43 42 50 QN 2
Q29 47 43 44 50 QN 1
Q30 44 45 50 50 QN 1.5
QD10 45 46 50 50 QN 1
R9 45 46 175
Q31 46 47 48 99 QP 1
QD8 47 47 48 99 QP 1
QD9 48 48 51 99 QP 5
R8 99 51 2.9K
I5 99 46 1U
Q32 49 48 99 99 QP 10
Q33 49 44 50 50 QN 4
.MODEL DX D()
.MODEL QN NPN(BF=120 VAF=100)
.MODEL QP PNP(BF=80 VAF=60)
.ENDS OP296
*
.subckt OP27 1 2 3 4 5
A1 2 1 0 0 0 0 0 0 OTA g=0 in=.4p ink=140 incm=.001p incmk=10
M1 3 N005 5 5 N temp=27
M2 4 N005 5 5 P temp=27
C3 3 5 2p Rpar=20K noiseless
C6 3 1 1.375p Rpar=12G noiseless
A2 0 N006 M M M M N005 M OTA g=130u Iout=8u en=3n enk=2.7 Vlow=-1e308 Vhigh=1e308 Cout=2.5p
C10 N004 0 100p Rpar=1K noiseless
D1 N005 5 Y
D6 5 N005 Y
G1 0 M 3 0 1m
G2 0 M 4 0 1m
R3 M 0 1K noiseless
S1 N005 M 4 3 UVLO
D3 N005 3 X
D4 4 N005 X
D2 3 4 IQ
C7 1 4 1.375p Rpar=12G noiseless
C8 3 2 1.375p Rpar=12G noiseless
C9 2 4 1.375p Rpar=12G noiseless
B1 N004 0 I=1m*dnlim(uplim(V(2),V(3)-2.7,.1), V(4)+2.7, .1)+100n*V(2)
B2 0 N004 I=1m*dnlim(uplim(V(1),V(3)-2.7,.1), V(4)+2.7, .1)+100n*V(1)
C1 2 1 1.375p noiseless
D7 2 1 IN
G3 0 N006 N004 0 1.1m
L1 N006 0 30µ Rser=1K Cpar=1p Rpar=10K noiseless
C2 5 4 2p Rpar=20K noiseless
.model IN D(Ron=.2 Roff=6Meg Vfwd=.65 epsilon=.5 Vrev=.65 revepsilon=.5 noiseless)
.model X D(Ron=200K Roff=100G Vfwd=-2.5 epsilon=.1 noiseless)
.model Y D(Ron=10K Roff=1T Vfwd=.28 epsilon=.1 noiseless)
.model N VDMOS(Vto=-65m Kp=.3 Ksubthres=.1 mtriode=2 noiseless)
.model P VDMOS(Vto=65m Kp=.3 pchan Ksubthres=.1 mtriode=2 noiseless)
.model UVLO SW(Ron=1K Roff=30G Vt=-3.75 Vh=.25 noiseless)
.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=.5m noiseless)
.ends OP27
*
.subckt OP37 1 2 3 4 5
A1 2 1 0 0 0 0 0 0 OTA g=0 in=.4p ink=140 incm=.001p incmk=10
M1 3 N005 5 5 N temp=27
M2 4 N005 5 5 P temp=27
C3 3 5 2p Rpar=20K noiseless
C6 3 1 1.375p Rpar=12G noiseless
A2 0 N006 M M M M N005 M OTA g=130u Iout=8u en=3n enk=2.7 Vlow=-1e308 Vhigh=1e308 Cout=.3p
C10 N004 0 100p Rpar=1K noiseless
D1 N005 5 Y
D6 5 N005 Y
G1 0 M 3 0 1m
G2 0 M 4 0 1m
R3 M 0 1K noiseless
S1 N005 M 4 3 UVLO
D3 N005 3 X
D4 4 N005 X
D2 3 4 IQ
C7 1 4 1.375p Rpar=12G noiseless
C8 3 2 1.375p Rpar=12G noiseless
C9 2 4 1.375p Rpar=12G noiseless
B1 N004 0 I=1m*dnlim(uplim(V(2),V(3)-2.7,.1), V(4)+2.7, .1)+100n*V(2)
B2 0 N004 I=1m*dnlim(uplim(V(1),V(3)-2.7,.1), V(4)+2.7, .1)+100n*V(1)
C1 2 1 1.375p noiseless
D7 2 1 IN
G3 0 N006 N004 0 1.1m
L1 N006 0 30µ Rser=1K Cpar=1p Rpar=10K noiseless
C2 5 4 2p Rpar=20K noiseless
.model IN D(Ron=.2 Roff=6Meg Vfwd=.65 epsilon=.5 Vrev=.65 revepsilon=.5 noiseless)
.model X D(Ron=200K Roff=100G Vfwd=-2.5 epsilon=.1 noiseless)
.model Y D(Ron=10K Roff=1T Vfwd=.28 epsilon=.1 noiseless)
.model N VDMOS(Vto=-65m Kp=.3 Ksubthres=.1 mtriode=2 noiseless)
.model P VDMOS(Vto=65m Kp=.3 pchan Ksubthres=.1 mtriode=2 noiseless)
.model UVLO SW(Ron=1K Roff=30G Vt=-3.75 Vh=.25 noiseless)
.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=.5m noiseless)
.ends OP37
*
* OP413 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 4/30V, BIP, OP, Low Noise, Low Drift, 4X
* Developed by: ARG / PMI
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (03/1994)
* Copyright 1992, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*
*                   non-inverting input
*                   |  inverting input
*                   |  |  positive supply
*                   |  |  |  negative supply
*                   |  |  |  |  output
*                   |  |  |  |  |
.SUBCKT OP413       3  2  7  4  6
*#ASSOC Category="Op-amps" symbol=opamp
*
*  INPUT STAGE
*
R3   4   19   1.5E3
R4   4   20   1.5E3
C1   19  20   5.31E-12
I1   7   18   106E-6
IOS  2    3   25E-09
EOS  12   5   POLY(1) 51 4 25E-06 1
Q1   19   3   18 PNP1
Q2   20  12   18 PNP1
CIN  3    2   3E-12
D1   3    1   DY
D2   2    1   DY
EN   5    2   22  0  1
GN1  0    2   25  0  1E-5
GN2  0    3   28  0  1E-5
*
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
*
DN1  21  22   DEN
DN2  22  23   DEN
VN1  21   0   DC 2
VN2  0   23   DC 2
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
DN3  24  25   DIN
DN4  25  26   DIN
VN3  24   0   DC 2
VN4  0   26   DC 2
*
* SECOND CURRENT NOISE SOURCE
*
DN5  27  28   DIN
DN6  28  29   DIN
VN5  27   0   DC 2
VN6  0   29   DC 2
*
* GAIN STAGE & DOMINANT POLE AT 2HZ
*
G2   34  36   19 20 2.65E-04
R7   34  36   39E6
V3   35   4   DC  6
D4   36  35   DX
VB2  34   4   1.6
*
* SUPPLY/2 GENERATOR
*
ISY  7    4   0.2E-3
R10  7   60   40E3
R11  60   4   40E3
C3   60   0   1E-9
*
* CMRR STAGE & POLE AT 6kHZ
*
ECM  50   4   POLY(2) 3 60 2 60 0 0.8 0.8
CCM  50  51   26.5E-12
RCM1 50  51   1E6
RCM2 51   4   1
*
* OUTPUT STAGE
*
R12  37  36  1E3
R13  38  36  500
C4   37   6  20E-12
C5   38  39  20E-12
M1   39  36  4   4   MN  L=9E-6  W=1000E-6  AD=15E-9 AS=15E-9
M2   45  36  4   4   MN  L=9E-6  W=1000E-6  AD=15E-9 AS=15E-9
D5   39  47  DX
D6   47  45  DX
Q3   39  40  41  QPA  8
VB   7   40  DC  0.861
R14  7   41  375
Q4   41   7  43  QNA  1
R17  7   43  15
Q5   43  39  6   QNA  20
Q6   46  45  6   QPA  20
R18  46   4  15
Q7   36  46  4   QNA  1
M3   6   36  4   4   MN  L=9E-6  W=2000E-6  AD=30E-9 AS=30E-9
*
* NONLINEAR MODELS USED
*
.MODEL DX D (IS=1E-15)
.MODEL DY D (IS=1E-15  BV=7)
.MODEL PNP1 PNP (BF=220)
.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1)
.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1)
.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3
+ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573
+ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12
+ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30)
.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3
+ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13
+ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4
+ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30)
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8
+ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4
+ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33)
.ENDS OP413






* OP491 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 2.7/12V, BIP, OP, RRIO, OVP, 4X
* Developed by: ARG / PMI
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (05/1994)
* Copyright 1994, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |  inverting input
*                |  |  positive supply
*                |  |  |  negative supply
*                |  |  |  |  output
*                |  |  |  |  |
.SUBCKT OP491    1  2  99 50 45
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
I1   99   7    8.06E-6
Q1   6    4    7    QP
Q2   5    3    7    QP
D1   3    99   DX
D2   4    99   DX
D3   3    4    DX
D4   4    3    DX
R1   3    8    5E3
R2   4    2    5E3
R3   5    50   6.4654E3
R4   6    50   6.4654E3
EOS  8    1    POLY(1) (16,39) -80E-6 1
IOS  3    4    50E-12
GB1  3    98   (21,98) 50E-9
GB2  4    98   (21,98) 50E-9
CIN  1    2    1E-12
*
* 1ST GAIN STAGE
*
EREF 98   0    (39,0) 1
G1   98   9    (6,5) 31.667E-6
R7   9    98   1E6
EC1  99   10   POLY(1) (99,39) -0.52 1
EC2  11   50   POLY(1) (39,50) -0.52 1
D5   9    10   DX
D6   11   9    DX
*
* 2ND GAIN STAGE AND DOMINANT POLE AT 36HZ
*
G2   98   12   (9,39) 8E-6
R8   12   98   276.311E6
C2   12   98   16E-12
D7   12   13   DX
D8   14   12   DX
V1   99   13   0.58
V2   14   50   0.58
*
* COMMON MODE STAGE
*
ECM  15   98   POLY(2) (1,39) (2,39) 0 0.5 0.5
R9   15   16   1E6
R10  16   98   10
*
* POLE AT 2.5MHZ
*
G3   98   18   (12,39) 1E-6
R11  18   98   1E6
C4   18   98   63.662E-15
*
* BIAS CURRENT-VS-COMMON MODE VOLTAGE
*
EP   97   0    (99,0) 1
VB   99   17   1.3
RB   17   50   1E9
E3   19   0    (15,17) 16
D13  19   20   DX
R12  20   0    1E6
G4   98   21   (20,0) 1E-3
R13  21   98   5E3
D14  21   22   DY
E4   97   22   POLY(1) (99,98) -0.765 1
*
* POLE AT 100MHZ
*
G6   98   40   (18,39) 1E-6
R20  40   98   1E6
C10  40   98   1.592E-15
*
* OUTPUT STAGE
*
RS1  99   39   109.375E3
RS2  39   50   109.375E3
RO1  99   45   41.667
RO2  45   50   41.667
G7   45   99   (99,40) 24E-3
G8   50   45   (40,50) 24E-3
G9   98   60   (45,40) 24E-3
D9   60   61   DX
D10  62   60   DX
V7   61   98   DC 0
V8   98   62   DC 0
FSY  99   50   POLY(2) V7 V8 0.207E-3  1  1
D11  41   45   DZ
D12  45   42   DZ
V5   40   41   0.131
V6   42   40   0.131
.MODEL DX D()
.MODEL DY D(IS=1E-9)
.MODEL DZ D(IS=1E-6)
.MODEL QP PNP(BF=133.333)
.ENDS OP491






* OP492 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 4.5/33V, BIP, OP, Low Cost, S SPLY, 4X
* Developed by: ARG / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (03/1995)
* Copyright 1993, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |  inverting input
*                |  |  positive supply
*                |  |  |  negative supply
*                |  |  |  |  output
*                |  |  |  |  |
.SUBCKT OP492    2  1  99 50 34
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE AND POLE AT 40MHZ
*
I1   99   4    50E-6
IOS  2    1    10E-9
EOS  2    3    POLY(1) (21,30) 1.5E-3 75
CIN  1    2    3E-12
Q1   5    1    7    QP
Q2   6    3    8    QP
R3   5    50   2E3
R4   6    50   2E3
R5   4    7    966
R6   4    8    966
C1   5    6    .995E-12
*
* GAIN STAGE
*
EREF 98   0    (30,0) 1
G1   98   9    (5,6) 500E-6
R7   9    98   210.819E3
D1   9    10   DX
D2   11   9    DX
V1   99   10   .6
V2   11   50   .6
*
* ZERO/POLE AT 6MHZ/12MHZ
*
E1   12   98   (9,30) 2
R8   12   13   1
R9   13   98   1
C3   12   13   26.526E-9
*
* ZERO AT 15MHZ
*
E2   14   98   (13,30) 1E6
R10  14   15   1E6
R11  15   98   1
C4   14   15   10.610E-15
*
* COMMON MODE STAGE WITH ZERO AT 40KHZ
*
ECM  20   98   POLY(2) (1,30) (2,30) 0 0.5 0.5
R20  20   21   1E6
R21  21   98   1
C5   20   21   3.979E-12
*
* POLE AT 100MHZ
*
G2   98   16   (15,30) 1
R12  16   98   1
C6   16   98   1.592E-9
*
* OUTPUT STAGE
*
RS1  99   30   1E6
RS2  30   50   1E6
ISY  99   50   .44E-3
G3   31   50   POLY(1) (16,30) -1.635E-6 4E-6
R16  31   50   1E6
DCL  50   31   DZ
I2   99   32   250E-6
RCL  33   50   56
M1   32   31   50   50   MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
M2   34   31   50   50   MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9
CC   31   32   14E-12
Q3   99   32   34   QNA
Q4   33   32   34   QPA
Q5   31   33   50   QNA
.MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3
+ ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4
+ ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209
+ CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5
+ CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30)
.MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4
+ ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5
+ ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4
+ CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4
+ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30)
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3
+ TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837
+ MJ=0.407 CJSW=0.5E-9 MJSW=0.33)
.MODEL QP PNP(BF=61.5)
.MODEL DX D
.MODEL DZ D(BV=3.6)
.ENDS OP492






* OP495 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 3/30V, BIP, OP, RRO, S SPLY, 4X
* Developed by: ARG / ADI
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (02/1995)
* Copyright 1995, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*                non-inverting input
*                |  inverting input
*                |  |  positive supply
*                |  |  |  negative supply
*                |  |  |  |  output
*                |  |  |  |  |
.SUBCKT OP495    1  2  99 50 20
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE
*
I1   99   4    2.016E-6
R1   1    6    5E3
R2   2    5    5E3
CIN  1    2    2E-12
IOS  1    2    0.5E-9
D1   5    3    DZ
D2   6    3    DZ
EOS  7    6    POLY(1) (31,39) 30E-6 0.024
Q1   8    5    4   QP
Q2   9    7    4   QP
R3   8    50   25.861E3
R4   9    50   25.861E3
*
* GAIN STAGE
*
R7   10   98   270E6
G1   98   10   POLY(1) (9,8) -4.26712E-9 27.8E-6
EREF 98   0    (39,0) 1
R5   99   39   417E3
R6   39   50   417E3
*
* COMMON MODE STAGE
*
ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5
R12 30 31 1E6
R13 31 98 100
*
* OUTPUT STAGE
*
ISY  99   50   49E-6
I2   18   50   1.59E-6
V2   99   12   DC 2.2763
Q4   10   14   50   QNA  1.0
R11  14   50   33
M3   15   10   13   13   MN  L=9E-6 W=102E-6 AD=15E-10 AS=15E-10
M4   13   10   50   50   MN  L=9E-6 W=50E-6 AD=75E-11 AS=75E-11
D8   10   22   DX
V3   22   50   DC 6
M2   20   10   14   14   MN  L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9
Q5   17   17   99   QPA  1.0
Q6   18   17   99   QPA  4.0
R8   18   99   2.2E6
Q7   18   19   99   QPA  1.0
R9   99   19   8
C2   18   99   20E-12
M6   15   12   17   99   MP  L=9E-6 W=27E-6 AD=405E-12 AS=405E-12
M1   20   18   19   99   MP  L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9
D4   21   18   DX
V4   99   21   DC 6
R10  10   11   6E3
C3   11   20   54E-12
.MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3
+ ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4
+ ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209
+ CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5
+ CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30)
.MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4
+ ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5
+ ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4
+ CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4
+ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30)
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3
+ TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
+ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837
+ MJ=0.407 CJSW=0.5E-9 MJSW=0.33)
.MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7
+ TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5
+ XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56
+ MJ=0.442 CJSW=0.4E-9 MJSW=0.33)
.MODEL DX D(IS=1E-15)
.MODEL DZ D(IS=1E-15, BV=7)
.MODEL QP PNP(BF=125)
.ENDS OP495






* OP727 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/30V, BIP, OP, S SPLY, RRO, 2X
* Developed by: RM / ADSC, HH / ADSJ
* Revision History: 08/10/2012 - Updated to new header style
* 1.2 (04/2009) - Corrected EVP, EVN
* 1.1 (08/2000)
* Copyright 2000, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |   positive supply
*         |   |   |   negative supply
*         |   |   |   |   output
*         |   |   |   |   |
*         |   |   |   |   |
.SUBCKT OP727      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* PNP INPUT STAGE
*
Q1    5  7 3 PIX
Q2    6  2 3 PIX
RC1   5 50 8000
RC2   6 50 8000
C1    5  6 0.5E-12
D1    3  8 DX
V1   99  8 DC 1.0
I1   99  3 50E-6
EOS   7  1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1
IOS   2  1 1E-9
*
* PSRR=120dB, ZERO AT 150Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1E+6
CPS3 72 73 1.06E-9
RPS4 73 98 1
*
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 15
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 POLY(1) (99,50) 0 2.6E-6
*
*
* CMRR 110dB, ZERO AT 400Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 1E+6
CCM1 21 22 0.397E-9
RCM2 22 98 1
*
* GAIN STAGE
*
G1 98 30 POLY(1) (5,6) 0 28.8E-6
R1 30 98 2.02E+8
CF 45 30 50E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=0.329E-3
M6  45 47 50 50 NOX L=1E-6 W=0.496E-3
EG1 99 46 POLY(1) (98,30) 0.6299 1
EG2 47 50 POLY(1) (30,98) 0.5739 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS OP727






* OP747 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/30V, BIP, OP, S SPLY, RRO, 4X
* Developed by: RM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.2 (04/2009) - Corrected EVP, EVN
* 1.1 (08/2000)
* Copyright 2000, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |   positive supply
*         |   |   |   negative supply
*         |   |   |   |   output
*         |   |   |   |   |
*         |   |   |   |   |
.SUBCKT OP747      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* PNP INPUT STAGE
*
Q1    5  7 3 PIX
Q2    6  2 3 PIX
RC1   5 50 8000
RC2   6 50 8000
C1    5  6 0.5E-12
D1    3  8 DX
V1   99  8 DC 1.0
I1   99  3 50E-6
EOS   7  1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1
IOS   2  1 1E-9
*
* PSRR=120dB, ZERO AT 150Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1E+6
CPS3 72 73 1.06E-9
RPS4 73 98 1
*
* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 15
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 POLY(1) (99,50) 0 2.6E-6
EVP  97 98 POLY(1) (99,50) 0 0.5
EVN  51 98 POLY(1) (50,99) 0 0.5
*
*
* CMRR 110dB, ZERO AT 400Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 1E+6
CCM1 21 22 0.397E-9
RCM2 22 98 1
*
* GAIN STAGE
*
G1 98 30 POLY(1) (5,6) 0 28.8E-6
R1 30 98 2.02E+8
CF 45 30 50E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=0.329E-3
M6  45 47 50 50 NOX L=1E-6 W=0.496E-3
EG1 99 46 POLY(1) (98,30) 0.6299 1
EG2 47 50 POLY(1) (30,98) 0.5739 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS OP747






* OP77 SPICE Macro-model
* Description: Amplifier
* Generic Desc: 6/30V, BIP, OP, Low Vos, Precision, 1X
* Developed by: JCB / PMI
* Revision History: 08/10/2012 - Updated to new header style
* 2.0 (12/1990) - Re-ordered subcircuit call out nodes to put the output node last.
*          - Changed Ios from 0.3E-9 to 0.15E-9
*      - Added F1 and F2 to fix short circuit current limit.
* Copyright 1990, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
*              non-inverting input
*              | inverting input
*              | | positive supply
*              | | |  negative supply
*              | | |  |  output
*              | | |  |  |
.SUBCKT OP77   1 2 99 50 39
*#ASSOC Category="Op-amps" symbol=opamp
*
* INPUT STAGE & POLE AT 6 MHZ
*
R1   2   3    5E11
R2   1   3    5E11
R3   5  97    0.0606
R4   6  97    0.0606
CIN  1   2    4E-12
C2   5   6    218.9E-9
I1   4  51    1
IOS  1   2    0.15E-9
EOS  9  10    POLY(1)  30 33  10E-6  1
Q1   5  2  7  QX
Q2   6  9  8  QX
R5   7   4    0.009
R6   8   4    0.009
D1   2   1    DX
D2   1   2    DX
EN   10  1    12  0  1
GN1  0   2    15  0  1
GN2  0   1    18  0  1
*
EREF  98 0    33  0  1
EPLUS 97 0    99  0  1
ENEG  51 0    50  0  1
*
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
*
DN1  11  12   DEN
DN2  12  13   DEN
VN1  11   0   DC 2
VN2  0   13   DC 2
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
DN3  14  15   DIN
DN4  15  16   DIN
VN3  14   0   DC 2
VN4  0   16   DC 2
*
* SECOND CURRENT NOISE SOURCE
*
DN5  17  18   DIN
DN6  18  19   DIN
VN5  17   0   DC 2
VN6  0   19   DC 2
*
* FIRST GAIN STAGE
*
R7   20 98     1
G1   98 20     5  6  59.91
D3   20 21     DX
D4   22 20     DX
E1   97 21     POLY(1) 97 33 -2.4 1
E2   22 51     POLY(1) 33 51 -2.4 1
*
* GAIN STAGE & DOMINANT POLE AT 0.053 HZ
*
R8   23 98     6.01E9
C3   23 98     500E-12
G2   98 23     20 33  33.3E-6
V1   97 24     1.3
V2   25 51     1.3
D5   23 24     DX
D6   25 23     DX
*
* NEGATIVE ZERO AT -4MHZ
*
R9   26 27     1
C4   26 27     -39.75E-9
R10  27 98     1E-6
E3   26 98     23 33  1E6
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 20 HZ
*
R13  30 31     1
L2   31 98     7.96E-3
G4   98 30     3  33  1.0E-7
D7   30 97     DX
D8   51 30     DX
*
* POLE AT 2 MHZ
*
R14  32 98     1
C5   32 98     79.5E-9
G5   98 32     27 33  1
*
* OUTPUT STAGE
*
R15  33 97     1
R16  33 51     1
GSY  99 50     POLY(1) 99 50 0.325E-3 0.0425E-3
F1   34  0     V3  1
F2   0  34     V4  1
R17  34 99     400
R18  34 50     400
L3   34 39     2E-7
G6   37 50     32 34  2.5E-3
G7   38 50     34 32  2.5E-3
G8   34 99     99 32  2.5E-3
G9   50 34     32 50  2.5E-3
V3   35 34     6.8
V4   34 36     4.4
D9   32 35     DX
D10  36 32     DX
D11  99 37     DX
D12  99 38     DX
D13  50 37     DY
D14  50 38     DY
*
* MODELS USED
*
.MODEL QX NPN(BF=417E6)
.MODEL DX   D(IS=1E-15)
.MODEL DY   D(IS=1E-15 BV=50)
.MODEL DEN  D(IS=1E-12, RS=12.08K, KF=1E-17, AF=1)
.MODEL DIN  D(IS=1E-12, RS=7.55E-6, KF=1.55E-15, AF=1)
.ENDS OP77



* OP777 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 2.7/30V, BIP, OP, S SPLY, RRO, 1X
* Developed by: RM / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.2 (04/2009) - Corrected EVP, EVN
* 1.1 (08/2000)
* Copyright 2000, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement.  Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
*         noninverting input
*         |   inverting input
*         |   |   positive supply
*         |   |   |   negative supply
*         |   |   |   |   output
*         |   |   |   |   |
*         |   |   |   |   |
.SUBCKT OP777      1   2   99   50   45
*#ASSOC Category="Op-amps" symbol=opamp
*
* PNP INPUT STAGE
*
Q1    5  7 3 PIX
Q2    6  2 3 PIX
RC1   5 50 8000
RC2   6 50 8000
C1    5  6 0.5E-12
D1    3  8 DX
V1   99  8 DC 1.0
I1   99  3 50E-6
EOS   7  1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1
IOS   2  1 1E-9
*
* PSRR=120dB, ZERO AT 150Hz
*
RPS1 70  0 1E+6
RPS2 71  0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1E+6
CPS3 72 73 1.06E-9
RPS4 73 98 1
*
* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN  81 98 VN1 15
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98  0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY  99 50 POLY(1) (99,50) 0 2.6E-6
EVP  97 98 (99,50) 0.5
EVN  51 98 (50,99) 0.5
*
*
* CMRR 110dB, ZERO AT 400Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 1E+6
CCM1 21 22 0.397E-9
RCM2 22 98 1
*
* GAIN STAGE
*
G1 98 30 POLY(1) (5,6) 0 28.8E-6
R1 30 98 2.02E+8
CF 45 30 50E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5  45 46 99 99 POX L=1E-6 W=0.329E-3
M6  45 47 50 50 NOX L=1E-6 W=0.496E-3
EG1 99 46 POLY(1) (98,30) 0.6299 1
EG2 47 50 POLY(1) (30,98) 0.5739 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1)
.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS OP777
*
.subckt ADHV4702-1 1 2 3 4 5 6 7
C10 N005 0 .1f Rpar=100K noiseless
C16 N004 N006 24p
C7 4 1 3.95p Rser=1k noiseless
C4 2 1 12.9p Rser=1k noiseless
C13 4 5 10p
D1 3 4 DESD
D2 5 3 DESD
C20 N004 0 1p
D3 N004 0 DANTISAT
G4 0 N008 N007 0 1m
D5 2 4 DESD
D8 5 2 DESD
D11 1 4 DESD
D12 5 1 DESD
D13 2 1 DINCLP N=4
C21 N008 0 7p Rpar=1k noiseless
R5 N006 0 1 noiseless
G3 0 N006 N009 Mid 1
A6 N005 0 _SHDN 0 0 0 N007 0 OTA g=1m linear en=8n*(1+freq/10Meg)**1.9 enk=15 vlow=-1e309 vhigh=1e309
C12 4 3 5p
C14 3 5 5p
G5 0 XX N004 0 1m
C9 XX 0 151.2p noiseless Rser=52.6 Rpar=1k
C1 1 5 3.95p Rser=1k noiseless
C3 4 2 3.95p Rser=1k noiseless
C5 2 5 3.95p Rser=1k noiseless
M1 N009 PG 4 4 PI temp=27
D6 4 PG DLIMP
C6 4 PG 200f Rser=600k noiseless
B3 PG 4 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(100n-1.2u*(23.6*V(XX)-750m),100n,100n)
M2 N009 NG 5 5 NI temp=27
D7 NG 5 DLIMN
C11 NG 5 200f Rser=600k noiseless
B4 5 NG I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(100n+1.2u*(23.6*V(XX)+650m),100n,100n)
C2 N007 0 7p Rpar=1k noiseless
C8 X3 0 7p Rpar=1k noiseless
C15 PG N009 3f
C17 N009 NG 3f
A2 0 N008 0 0 0 0 X3 0 OTA g=1m linear vlow=-1e308 vhigh=1e308
C18 N012 0 100p Rpar=1k noiseless
C19 SLWFAC2 0 100p Rpar=100Meg noiseless
D9 N012 SLWFAC2 DRISE
D10 SLWFAC2 N012 DFALL
B5 0 N004 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*uplim(dnlim(703u*V(X3),-1.8m*uplim(V(SLWFAC2),1,50m),100u),1.8m*uplim(V(SLWFAC2),1,50m),100u)
B6 0 N012 I=uplim(dnlim(300u*ABS(V(X3))-200u,0,100u)+100u,2m,200u)
S1 N014 4 6 N014 SREG
R7 N014 7 400K noiseless
C22 6 7 1p
D14 N014 5 DBSD
C23 5 N014 1p
A3 7 6 0 0 0 0 _SHDN 0 SCHMITT vt=1.2 vh=400m trise=300u
S2 4 5 _SHDN 0 SPOW
B1 N005 0 I=10u*dnlim(uplim(V(2),V(4)-2.89,.1), V(5)+2.89, .1)+1n*V(2)
B2 0 N005 I=10u*dnlim(uplim(V(1),V(4)-2.9,.1), V(5)+2.9, .1)+1n*V(1)
R10 4 Mid 10Meg noiseless
R11 Mid 5 500Meg noiseless
A1 3 N009 N009 N009 N009 N009 3 N009 OTA g=1 iout=25m vlow=-1e308 vhigh=1e308
.param vs=220
.model PI VDMOS(Vto=-300m kp=8m  mtriode=430m  ksubthres=10m  pchan noiseless)
.model NI VDMOS(Vto=300m kp=12m mtriode=430m  ksubthres=10m noiseless)
.model DLIMN D(Ron=1k Roff=1Meg Vfwd=3.4  epsilon=100m  noiseless)
.model DLIMP D(Ron=1k Roff=1Meg Vfwd=4.8  epsilon=100m noiseless)
.model DRISE D(Ron=1 Roff=10Meg vfwd= 0 epsilon=10m noiseless)
.model DFALL D(Ron=1 Roff=10Meg vfwd= 0  epsilon=10m ilimit=80u noiseless)
.model DINCLP D(Ron=250  Roff=100T  vfwd=720m epsilon=800m vrev=720m revepsilon=800m noiseless)
.model DANTISAT D(Ron=100 Roff=127.3Meg vfwd=3 epsilon=100m vrev=3 revepsilon=100m noiseless)
.model SREG SW(level=2 Ron=10k Roff=1G vt=-5.2 vh=-100m noiseless)
.model DBSD D(Ron=10k Roff=1G vfwd=2 epsilon=300m ilimit=155.8u noiseless)
.model SPOW SW(Ron=100 Roff=10G vt=.5 vh=-.3 ilimit=890u noiseless)
.model DESD D(Ron=100 Roff=1g Vfwd=700m epsilon=500m noiseless)
.ends ADHV4702-1
*
.subckt SSM2141 1 2 3 4 5 6 7
M1 7 N004 6 6 N temp=27
M2 4 N004 6 6 P temp=27
C3 7 6 2p
C4 6 4 2p
A2 0 N007 M M M M N004 M OTA g=41u Isrc=10u en=10n enk=150 Vlow=-1e308 Vhigh=1e308 Cout= 1p
C10 N003 0 20p Rpar=1K noiseless
D1 N004 6 Y
D6 6 N004 Y N=.525
G1 0 M 7 0 1m
G2 0 M 4 0 1m
R3 M 0 1K noiseless
S1 N004 M 4 7 UVLO
D3 N004 7 X
D4 4 N004 X
L2 N003 N007 20µ
C2 N007 0 20p Rpar=1K noiseless
D2 7 4 IQ
B1 N003 0 I=2m*dnlim(uplim(V(A),V(7)-4,.1), V(4)+4, .1)+100n*V(A)
B2 0 N003 I=2m*dnlim(uplim(V(B),V(7)-4,.1), V(4)+4, .1)+100n*V(1)
R2 A 2 25K
R1 B 3 25K
R4 5 A 25K
R5 1 B 25K
.model X D(Ron=1K Roff=100G Vfwd=-2.57 epsilon=.1 noiseless)
.model Y D(Ron=500 Roff=1T Vfwd=2.2 epsilon=.1 noiseless)
.model N VDMOS(Vto=-250m Kp=15m Ksubthres=.2 noiseless)
.model P VDMOS(Vto=250m Kp=15m pchan Ksubthres=.2 noiseless)
.model UVLO SW(Ron=1K Roff=100G Vt=-3.75 Vh=.25 noiseless)
.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=1.8m noiseless)
.ends SSM2141
*
* Copyright (c) 1998-2020 Analog Devices, Inc.  All rights reserved.
*
.subckt AD820 1 2 3 4 5
A1 N009 0 0 0 0 0 N005 0 OTA g=66u Iout=40u Vhigh=1e308 Vlow=-1e308
C12 3 2 .25p Rser=2k noiseless
B3 0 N006 I=1m*dnlim(uplim(V(1),V(3)-.9,.1), V(4)-.2, .1)+100n*V(1)-941.26p
B4 N006 0 I=1m*dnlim(uplim(V(2),V(3)-.91,.1), V(4)-.21, .1)+100n*V(2)
C4 N006 0 1f Rpar=1K noiseless
D1 3 4 IQ
R5 2 1 10T noiseless
C2 N005 N008 10p
C3 N005 0 100f
D2 N005 0 DANTISAT1
G2 0 N008 5 Mid 1
R4 N008 0 1 noiseless
R6 3 Mid 312.5k noiseless
R7 Mid 4 312.5k noiseless
C6 N004 0 {C1_P1} Rpar={1/alpha_P1} noiseless
G5 0 N009 N004 0 {alpha_P1}
M1 5 PG 3 3 PI temp=27
M2 5 NG 4 4 NI temp=27
D3 3 PG DLIMP
D4 NG 4 DLIMN
C8 3 PG 10f Rser=400k noiseless
C9 NG 4 10f Rser=400k noiseless
B2 4 NG I=dnlim(vminn/1e6+1.8u*(V(XX)+voffn),vminn/1e6,100n)
B5 PG 3 I=dnlim(vminp/1e6-1.8u*(V(XX)-voffp),vminp/1e6,100n)
C13 3 5 1p
C15 5 4 1p
D5 N005 0 DANTISAT2
G1 2 3 2 3 10m vto=300m dir=1
G6 1 3 1 3 10m vto=300m dir=1
G7 4 2 4 2 10m vto=21 dir=1
G8 4 1 4 1 10m vto=21 dir=1
C16 2 1 2.8p Rser=1k noiseless
C17 N007 4 1p Rpar=1k noiseless
G9 4 N007 3 4 .5m
I1 4 N007 5m
D10 N007 2 DBIAS2
D11 N007 1 DBIAS2
D6 3 2 DBIAS1
D7 3 1 DBIAS1
G10 0 VBD1 3 0 50µ
C18 VBD1 0 1p Rpar=1k noiseless
G11 VBD1 0 2 0 25µ
G12 VBD1 0 1 0 25µ
I2 VBD1 0 400µ
D12 VBD2 0 DBIAS3 temp=27
R8 VBD2 VBD1 1k noiseless
G13 3 2 VBD1 VBD2 1.6n
G14 3 1 VBD1 VBD2 1.6n
C19 XX 0 {C1_PZ1} Rpar={R2_PZ1} Rser={R1_PZ1} noiseless
G15 0 XX N005 0 {alpha_PZ1*1.3}
A3 0 N006 0 0 0 0 N004 0 OTA g=20u linear en=13n enk=45 vlow=-1e308 vhigh=1e308
C1 N009 0 {C1_P1} Rpar={1/alpha_P1} noiseless
A4 0 2 0 0 0 0 0 0 OTA g=0 in=.8f ink=.5
A2 0 1 0 0 0 0 0 0 OTA g=0 in=.8f ink=.5
C5 2 4 .25p Rser=2k noiseless
C7 3 1 .25p Rser=2k noiseless
C10 1 4 .25p Rser=2k noiseless
G3 2 3 2 3 10µ vto=-800m dir=1
G4 1 3 1 3 10µ vto=-800m dir=1
.model DANTISAT1 D(Ron=10Meg Roff=95.6Meg vfwd=100m epsilon=100m vrev=100m revepsilon=100m noiseless)
.model DANTISAT2 D(Ron=1k Roff=95.6Meg vfwd=4 epsilon=100m vrev=4 revepsilon=100m noiseless)
.param alpha_PZ1=1.0e-3 pole_PZ1=150k zero_PZ1=700k
+ R2_PZ1=1.0/alpha_PZ1 R1_PZ1=1.0/(alpha_PZ1*(zero_PZ1/pole_PZ1 - 1.0))
+C1_PZ1=1.0/(2.0*pi*zero_PZ1*R1_PZ1)
.param alpha_P1=1.0e-5 pole_P1=11.0e6
+ C1_P1 = alpha_P1/(2*pi*pole_P1)
.param vadj = -12m
.param vminp = 418m
.param voffp = {45m+vadj}
.param vminn=400m
.param voffn ={5m-vadj}
.model NI VDMOS(VTO=300m mtriode=1.1 KP=45m ksubthres=10m lambda=.001 noiseless)
.model PI VDMOS(VTO=-300m mtriode=.65 KP=36m ksubthres=10m lambda=.001 pchan noiseless)
.model DLIMN D(Ron=1k Roff=1Meg Vfwd=1.5  epsilon=100m  noiseless)
.model DLIMP D(Ron=1k Roff=1Meg Vfwd=1.4  epsilon=100m noiseless)
.model DBIAS1 D(Ron=1k Roff=10T vfwd=0 epsilon=100m  ilimit=1p noiseless)
.model DBIAS2 D(Ron=5T Roff=30T vfwd=500m epsilon=100m noiseless)
.model DBIAS3 D(IS=1e-18 noiseless)
.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=53.13u noiseless)
.ends AD820

*
.subckt AD8205 1 2 3 4 5 6 7 8
R4 1 N003 150K
R5 N003 N009 38K
R6 N009 2 12K
R7 8 N006 150K
R8 N006 N011 38K
R9 N011 2 12K
R13 7 N011 {2*REF}
R14 N011 3 {2*REF}
R1 5 N009 {REF}
D1 2 N006 X
D2 2 N003 X
Q1 5 N005 6 0 P temp=27
D3 5 2 301uA
A2 N006 N003 6 6 6 6 N004 6 OTA Vhigh=0 Vlow=-1 G=1.35m Cout=200n en=.25u Iout=6000u epsilon=.1
S1 6 N004 2 6 UV
R3 N005 N004 500K noiseless
C2 7 2 3p
C1 8 2 3p
C3 5 2 3p
C4 6 2 3p
C5 1 2 3p
C6 3 2 3p
I1 6 5 1µ load
D4 6 2 IQ
.param Ref = 1.791Meg
.model X D(Ron=10 Vfwd=.5 epsilon=.1 Vrev=16.23 revepsilon=1 noiseless)
.model 301uA D(Ron=25 Vfwd=48m epsilon=50m Ilimit=301u noiseless)
.model P PNP(BF=100K noiseless)
.model UV SW(Ron=100 Roff=1T Vt=.3 Vh=-.5 noiseless)
.model IQ D(Ron=1K epsilon=1 Ilimit=1.25m noiseless)
.ends AD8205
*
* Copyright (c) 1998-2020 Analog Devices, Inc.  All rights reserved.
*
.subckt AD8479 1 2 3 4 5 6 7
M1 7 N004 6 6 N temp=27
M2 4 N004 6 6 P temp=27
C3 7 6 2p
C4 6 4 2p
A2 0 N007 M M M M N004 M OTA g=100u Isrc=10.1u en=10n enk=2.3 Vlow=-1e308 Vhigh=1e308 Cout=1.1p
C10 N003 0 2p Rpar=1K noiseless
D1 N004 6 Y
D6 6 N004 Y
G1 0 M 7 0 1m
G2 0 M 4 0 1m
R3 M 0 1K noiseless
S1 N004 M 4 7 UVLO
D3 N004 7 X
D4 4 N004 X
D2 7 4 IQ
B1 N003 0 I=2m*dnlim(uplim(V(A),V(7)-4,.1), V(4)+4, .1)+100000n*V(A)
B2 0 N003 I=2m*dnlim(uplim(V(B),V(7)-4,.1), V(4)+4, .1)+100000n*V(B)
R2 A 2 1060310.61
R1 B N009 530155.305
R4 6 N001 118694
R5 5 B 17671.43509
R7 N009 3 530155.305
R8 N001 A 15693.6
R9 N001 1 2011.7645
L1 N003 N007 2µ
C2 N007 0 2p Rpar=1K noiseless
C1 N009 0 35e-16
C5 A B 5.2p
I1 A 2 4.7156e-10
.model X D(Ron=100 Roff=100G Vfwd=-0.1 epsilon=.1 noiseless)
.model Y D(Ron=100 Roff=1T Vfwd=2.36 epsilon=.1 noiseless)
.model N VDMOS(Vto=-250m Kp=16m Ksubthres=.1 noiseless)
.model P VDMOS(Vto=250m Kp=16m pchan Ksubthres=.1 noiseless)
.model UVLO SW(Ron=1K Roff=100G Vt=-3.75 Vh=.25 noiseless)
.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=18u noiseless)
.ends AD8479