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288befd8f5 |
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.vscode/extensions.json
vendored
Normal file
5
.vscode/extensions.json
vendored
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{
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|
2523
bh.kicad_sym
2523
bh.kicad_sym
File diff suppressed because it is too large
Load Diff
222
common.pretty/2466267-1.kicad_mod
Normal file
222
common.pretty/2466267-1.kicad_mod
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Normal file
291
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Normal file
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192
common.pretty/Bourns_PVG3A.kicad_mod
Normal file
192
common.pretty/Bourns_PVG3A.kicad_mod
Normal file
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244
common.pretty/MSOP8.kicad_mod
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244
common.pretty/MSOP8.kicad_mod
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122
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common.pretty/SOD-882.kicad_mod
Normal file
135
common.pretty/SOD-882.kicad_mod
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169
common.pretty/SOT-89-5.kicad_mod
Normal file
169
common.pretty/SOT-89-5.kicad_mod
Normal file
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135
common.pretty/TEMD5110X01.kicad_mod
Normal file
135
common.pretty/TEMD5110X01.kicad_mod
Normal file
|
@ -0,0 +1,135 @@
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140
common.pretty/TO-252-3.kicad_mod
Normal file
140
common.pretty/TO-252-3.kicad_mod
Normal file
|
@ -0,0 +1,140 @@
|
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(footprint "TO-252-3"
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|
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|
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|
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|
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|
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|
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|
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|
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(model "${KIPRJMOD}/common_libraries/common.pretty/step/TO-252-3_TI_KVU0003A.step"
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)
|
|
@ -2,8 +2,7 @@ ISO-10303-21;
|
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HEADER;
|
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FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
|
||||
FILE_NAME(
|
||||
'/home/brendan/Documents/tempsync/projects/0000_
|
||||
KiCad/libraries/common.3dshapes/Amphenol_12401832E402A.step',
|
||||
'Amphenol_12401832E402A.step',
|
||||
'2021-08-07T19:22:33',('Author'),(''),
|
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'Open CASCADE STEP processor 7.3','FreeCAD','Unknown');
|
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FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));
|
||||
|
|
3727
common.pretty/step/Bourns_PVG3A.STEP
Normal file
3727
common.pretty/step/Bourns_PVG3A.STEP
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -2,8 +2,7 @@ ISO-10303-21;
|
|||
HEADER;
|
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FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
|
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FILE_NAME(
|
||||
'/home/brendan/Documents/tempsync/projects/0000_
|
||||
KiCad/libraries/common.3dshapes/CK_export.step','2021-06-26T02:57:55',(
|
||||
'CK_export.step','2021-06-26T02:57:55',(
|
||||
'Author'),(''),'Open CASCADE STEP processor 7.3','FreeCAD','Unknown'
|
||||
);
|
||||
FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));
|
||||
|
|
15257
common.pretty/step/CK_1201M2S3CQE2.step
Normal file
15257
common.pretty/step/CK_1201M2S3CQE2.step
Normal file
File diff suppressed because it is too large
Load Diff
6759
common.pretty/step/Keystone_967.step
Normal file
6759
common.pretty/step/Keystone_967.step
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -2,8 +2,7 @@ ISO-10303-21;
|
|||
HEADER;
|
||||
FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
|
||||
FILE_NAME(
|
||||
'/home/brendan/Documents/tempsync/projects/0000_
|
||||
KiCad/3dshapecad/MiniCircuits_JC0603-1.step','2021-06-26T04:56:55',(
|
||||
'MiniCircuits_JC0603-1.step','2021-06-26T04:56:55',(
|
||||
'Author'),(''),'Open CASCADE STEP processor 7.3','FreeCAD','Unknown'
|
||||
);
|
||||
FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));
|
||||
|
|
|
@ -2,8 +2,7 @@ ISO-10303-21;
|
|||
HEADER;
|
||||
FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
|
||||
FILE_NAME(
|
||||
'/home/brendan/Documents/tempsync/projects/0000_
|
||||
KiCad/libraries/common.3dshapes/Panasonic_EVP-AEBB2A.step',
|
||||
'Panasonic_EVP-AEBB2A.step',
|
||||
'2021-06-26T03:57:27',('Author'),(''),
|
||||
'Open CASCADE STEP processor 7.3','FreeCAD','Unknown');
|
||||
FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));
|
||||
|
|
|
@ -2,8 +2,7 @@ ISO-10303-21;
|
|||
HEADER;
|
||||
FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
|
||||
FILE_NAME(
|
||||
'/home/brendan/Documents/tempsync/projects/0000_
|
||||
KiCad/libraries/common.3dshapes/TE_2337857-1.step','2021-06-26T03:46:57'
|
||||
'TE_2337857-1.step','2021-06-26T03:46:57'
|
||||
,('Author'),(''),'Open CASCADE STEP processor 7.3','FreeCAD','Unknown'
|
||||
);
|
||||
FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));
|
||||
|
|
2745
common.pretty/step/TE_2466267-1.step
Normal file
2745
common.pretty/step/TE_2466267-1.step
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -2,8 +2,7 @@ ISO-10303-21;
|
|||
HEADER;
|
||||
FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
|
||||
FILE_NAME(
|
||||
'/home/brendan/Documents/tempsync/projects/0000_
|
||||
KiCad/libraries/common.3dshapes/TE_6116075-1.step','2021-06-26T03:23:56'
|
||||
'TE_6116075-1.step','2021-06-26T03:23:56'
|
||||
,('Author'),(''),'Open CASCADE STEP processor 7.3','FreeCAD','Unknown'
|
||||
);
|
||||
FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));
|
||||
|
|
|
@ -104,7 +104,7 @@
|
|||
(property "Spice_Netlist_Enabled" "Y" (id 6) (at 0 2.54 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/onsemi/S115FA.LIB" (id 7) (at 0 2.54 0)
|
||||
(property "Spice_Lib_File" "./spice/onsemi/S115FA.LIB" (id 7) (at 0 2.54 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_description" "Diode, Schottky, 1A, 150V, SOD-123FL" (id 8) (at 0 0 0)
|
||||
|
@ -136,7 +136,7 @@
|
|||
(property "Spice_Netlist_Enabled" "Y" (id 6) (at 0 2.54 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/onsemi/S310FA.LIB" (id 7) (at 0 2.54 0)
|
||||
(property "Spice_Lib_File" "./spice/onsemi/S310FA.LIB" (id 7) (at 0 2.54 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_description" "Diode, Schottky, 3A, 100V, SOD-123FL" (id 8) (at 0 0 0)
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
(property "Spice_Node_Sequence" "Y A B VCC GND" (id 12) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/ti/SN74LVC1G00.cir" (id 13) (at 0 0 0)
|
||||
(property "Spice_Lib_File" "./spice/ti/SN74LVC1G00.cir" (id 13) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_description" "IC, Logic, NAND, Single, SOT-353" (id 14) (at 0 0 0)
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
(pad "0" thru_hole circle (at -8.001 -3.048) (size 2.921 2.921) (drill 1.6) (layers *.Cu *.Mask))
|
||||
(pad "" np_thru_hole circle (at 5.715 0) (size 3.250001 3.250001) (drill 3.250001) (layers *.Cu *.Mask))
|
||||
(pad "" np_thru_hole circle (at -5.715 0) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask))
|
||||
(model "/home/brendan/Documents/Projects/0002_WaveGen/Hardware/Libraries/WaveGen.pretty/3dmodels/CONN_RJ45_TE_1-2301994-5.step"
|
||||
(model "./step/CONN_RJ45_TE_1-2301994-5.step"
|
||||
(offset (xyz 0 -10.795 7.112000000000001))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz -90 0 0))
|
||||
|
|
|
@ -18,7 +18,7 @@
|
|||
(pad 0 smd rect (at 0.825 0.65) (size 0.95 0.8) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 2 smd rect (at 0.825 -0.65) (size 0.95 0.8) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 1 smd rect (at -0.825 0.65) (size 0.95 0.8) (layers F.Cu F.Paste F.Mask))
|
||||
(model "/home/brendan/Documents/Projects/libraries/common.3dshapes/User Library-Crystal NDK NX2520SA series.step"
|
||||
(model "./step/User Library-Crystal NDK NX2520SA series.step"
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
|
|
|
@ -24,7 +24,7 @@
|
|||
(pad 1 smd rect (at 2.5 -0.8) (size 0.8 1.6) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 0 smd rect (at -5.05 2.1) (size 2.1 3) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 0 smd rect (at 5.05 2.1) (size 2.1 3) (layers F.Cu F.Paste F.Mask))
|
||||
(model /home/brendan/Documents/Projects/libraries/Connector_Molex.3dshapes/532610571.stp
|
||||
(model "./step/Connector_Molex.3dshapes/532610571.stp"
|
||||
(offset (xyz 0 -3.301999950408935 1.777999973297119))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 180))
|
||||
|
|
|
@ -26,7 +26,7 @@
|
|||
(pad 10 smd rect (at -3.81 -3.8608) (size 1.4224 1.7272) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 11 smd rect (at -6.35 0) (size 1.4224 1.7272) (layers F.Cu F.Paste F.Mask))
|
||||
(pad 12 smd rect (at -6.35 -3.8608) (size 1.4224 1.7272) (layers F.Cu F.Paste F.Mask))
|
||||
(model /home/brendan/Documents/Projects/libraries/Connector_Samtec.3dshapes/SMH-106-02-G-D.stp
|
||||
(model "./step/SMH-106-02-G-D.stp"
|
||||
(offset (xyz 0 -3 2.54))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz -90 0 0))
|
||||
|
|
|
@ -1,16 +1,128 @@
|
|||
(footprint "PinHeader_1x01_0.1in_TSW-101-07-L-S"
|
||||
(version 20221029)
|
||||
(generator pcbnew)
|
||||
(version 20240108)
|
||||
(generator "pcbnew")
|
||||
(generator_version "8.0")
|
||||
(layer "F.Cu")
|
||||
(attr smd)
|
||||
(descr "Header, Male, 1x01, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
|
||||
(tags "header pin")
|
||||
(fp_text reference "REF**" (at 0.0 -2.032 0) (layer "F.SilkS") (effects (font (size 0.7619999999999999 0.7619999999999999) (thickness 0.17779999999999999))) )
|
||||
(fp_text value "VAL**" (at -0.635 0.0 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
|
||||
(fp_text user "${REFERENCE}**" (at 0.635 0.0 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
|
||||
(fp_rect (start -1.27 -1.27) (end 1.27 1.27) (stroke (width 0.17779999999999999) (type default)) (fill none) (layer "F.SilkS") )
|
||||
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
|
||||
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
|
||||
(pad "1" thru_hole rect (at 0.0 0.0) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
|
||||
(model "step/TSW-101-07-L-S.stp" (offset (xyz 0.0 0.0 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
|
||||
(property "Reference" "REF**"
|
||||
(at 0 -2.032 0)
|
||||
(layer "F.SilkS")
|
||||
(uuid "268fd539-fa62-448f-ba39-0d0a34159c58")
|
||||
(effects
|
||||
(font
|
||||
(size 0.762 0.762)
|
||||
(thickness 0.1778)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Value" "VAL**"
|
||||
(at -0.635 0 90)
|
||||
(layer "F.Fab")
|
||||
(uuid "fd9e82e7-4097-4aba-bdc6-6ba33ca2a8d5")
|
||||
(effects
|
||||
(font
|
||||
(size 0.635 0.635)
|
||||
(thickness 0.127)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Footprint" ""
|
||||
(at 0 0 0)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "97652ea8-be16-440f-87d6-045f4e84e8ff")
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 0 0 0)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "1e796d57-f407-4272-9917-a4453790e269")
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Description" ""
|
||||
(at 0 0 0)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "f9a4ba14-1d79-47db-a907-d4bd24c675bf")
|
||||
(effects
|
||||
(font
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||||
(size 1.27 1.27)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(attr through_hole)
|
||||
(fp_line
|
||||
(start -1.27 1.27)
|
||||
(end 1.27 1.27)
|
||||
(stroke
|
||||
(width 0.1778)
|
||||
(type solid)
|
||||
)
|
||||
(layer "F.SilkS")
|
||||
(uuid "0f9698d2-c188-49d9-a59c-66b3d8e79763")
|
||||
)
|
||||
(fp_line
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||||
(start 1.27 -1.27)
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||||
(end 1.27 1.27)
|
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(stroke
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||||
(width 0.1778)
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||||
(type solid)
|
||||
)
|
||||
(layer "F.SilkS")
|
||||
(uuid "a00e8d2a-30e3-49be-9e41-363bcc000469")
|
||||
)
|
||||
(fp_rect
|
||||
(start -1.27 -1.27)
|
||||
(end 1.27 1.27)
|
||||
(stroke
|
||||
(width 0.1778)
|
||||
(type default)
|
||||
)
|
||||
(fill none)
|
||||
(layer "F.SilkS")
|
||||
(uuid "e628e852-d71e-4b6b-9d9a-d7418c3343eb")
|
||||
)
|
||||
(fp_text user "${REFERENCE}**"
|
||||
(at 0.635 0 90)
|
||||
(layer "F.Fab")
|
||||
(uuid "176420af-86da-46c8-8361-c2ff9e1a8f75")
|
||||
(effects
|
||||
(font
|
||||
(size 0.635 0.635)
|
||||
(thickness 0.127)
|
||||
)
|
||||
)
|
||||
)
|
||||
(pad "1" thru_hole rect
|
||||
(at 0 0)
|
||||
(size 1.905 1.905)
|
||||
(drill 1.016)
|
||||
(layers "*.Cu" "*.Mask")
|
||||
(remove_unused_layers no)
|
||||
(uuid "d9b557cd-e5a9-4b58-95fc-fedb0e8ab99a")
|
||||
)
|
||||
(model "step/TSW-101-07-L-S.stp"
|
||||
(offset
|
||||
(xyz 0 0 0)
|
||||
)
|
||||
(scale
|
||||
(xyz 1 1 1)
|
||||
)
|
||||
(rotate
|
||||
(xyz -90 0 90)
|
||||
)
|
||||
)
|
||||
)
|
|
@ -1,18 +1,147 @@
|
|||
(footprint "PinHeader_1x02_0.1in_TSW-102-07-L-S"
|
||||
(version 20221029)
|
||||
(generator pcbnew)
|
||||
(version 20240108)
|
||||
(generator "pcbnew")
|
||||
(generator_version "8.0")
|
||||
(layer "F.Cu")
|
||||
(attr smd)
|
||||
(descr "Header, Male, 1x02, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
|
||||
(tags "header pin")
|
||||
(fp_text reference "REF**" (at 0.0 -2.032 0) (layer "F.SilkS") (effects (font (size 0.7619999999999999 0.7619999999999999) (thickness 0.17779999999999999))) )
|
||||
(fp_text value "VAL**" (at -0.635 1.27 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
|
||||
(fp_text user "${REFERENCE}**" (at 0.635 1.27 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
|
||||
(fp_rect (start -1.27 -1.27) (end 1.27 3.81) (stroke (width 0.17779999999999999) (type default)) (fill none) (layer "F.SilkS") )
|
||||
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
|
||||
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
|
||||
(pad "1" thru_hole rect (at 0.0 0.0) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
|
||||
(model "step/TSW-102-07-L-S.stp" (offset (xyz 0.0 1.27 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
|
||||
(pad "2" thru_hole circle (at 0.0 2.54) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
|
||||
(model "step/TSW-102-07-L-S.stp" (offset (xyz 0.0 1.27 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
|
||||
(property "Reference" "REF**"
|
||||
(at 0 -2.032 0)
|
||||
(layer "F.SilkS")
|
||||
(uuid "9ec3ba1e-dd85-4edc-b2ba-53e2bee2a7fb")
|
||||
(effects
|
||||
(font
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(thickness 0.1778)
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||||
)
|
||||
)
|
||||
)
|
||||
(property "Value" "VAL**"
|
||||
(at -0.635 1.27 90)
|
||||
(layer "F.Fab")
|
||||
(uuid "5db18a84-0e10-442d-b4a0-e6cbb0675b87")
|
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(effects
|
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(font
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||||
)
|
||||
)
|
||||
)
|
||||
(property "Footprint" ""
|
||||
(at 0 0 0)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "c771cfb0-cea5-49ec-a268-09277cf8c5a0")
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(effects
|
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(font
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(thickness 0.15)
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||||
)
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
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||||
(at 0 0 0)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "57e4a6d4-46de-444a-be3d-7a35d18f458c")
|
||||
(effects
|
||||
(font
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(size 1.27 1.27)
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(thickness 0.15)
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||||
)
|
||||
)
|
||||
)
|
||||
(property "Description" ""
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||||
(at 0 0 0)
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||||
(layer "F.Fab")
|
||||
(hide yes)
|
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(uuid "bcbbc288-9ac4-4fd4-acbe-33b5f401beef")
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(effects
|
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||||
)
|
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)
|
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)
|
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(attr through_hole)
|
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(fp_line
|
||||
(start -1.27 1.27)
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(end 1.27 1.27)
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(stroke
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(width 0.1778)
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(type solid)
|
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)
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(layer "F.SilkS")
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(uuid "85700b88-428e-4a83-b86f-428f89dbff84")
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)
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(stroke
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)
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|
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(uuid "b56f842a-6b80-4193-ab1b-6132ac989d2f")
|
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)
|
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||||
(xyz 0 3.81 0)
|
||||
)
|
||||
(scale
|
||||
(xyz 1 1 1)
|
||||
)
|
||||
(rotate
|
||||
(xyz -90 0 90)
|
||||
)
|
||||
)
|
||||
)
|
|
@ -36,7 +36,7 @@
|
|||
(property "Spice_Netlist_Enabled" "Y" (id 11) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Spice_Lib_File" "/home/brendan/Documents/tempsync/projects/0000_KiCad/libraries/spice/Ad8038.cir" (id 12) (at 0 0 0)
|
||||
(property "Spice_Lib_File" "./spice/Ad8038.cir" (id 12) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_description" "Spice, OpAmp" (id 13) (at 0 0 0)
|
||||
|
|
9
spice/generic/varistor.lib
Normal file
9
spice/generic/varistor.lib
Normal file
|
@ -0,0 +1,9 @@
|
|||
*BEGIN MODEL VARISTOR
|
||||
*//////////////////////////////////////////////////////////////////////
|
||||
* (C) Brendan Haines
|
||||
*/////////////////////////////////////////////////////////////////////
|
||||
.SUBCKT VARISTOR IN_P IN_N R_P R_N PARAMS: gain=1
|
||||
*/////////////////////////////////////////////////////
|
||||
R R_P R_N {(V(IN_P) - V(IN_N)) * gain + 1n}
|
||||
.ENDS
|
||||
* END MODEL VARISTOR
|
207
spice/ti/LMH6611.lib
Normal file
207
spice/ti/LMH6611.lib
Normal file
|
@ -0,0 +1,207 @@
|
|||
*Rev.a July,2008
|
||||
*BEGIN MODEL LMH6611
|
||||
*//////////////////////////////////////////////////////////////////////
|
||||
* (C) National Semiconductor, Corporation.
|
||||
* Models developed and under copyright by:
|
||||
* National Semiconductor, Corporation.
|
||||
*/////////////////////////////////////////////////////////////////////
|
||||
* Legal Notice:
|
||||
* The model may be copied, and distributed without any modifications;
|
||||
* however, reselling or licensing the material is illegal.
|
||||
* We reserve the right to make changes to the model without prior notice.
|
||||
* Pspice Models are provided "AS IS, WITH NO WARRANTY OF ANY KIND"
|
||||
*////////////////////////////////////////////////////////////////////
|
||||
*
|
||||
* PINOUT ORDER +IN -IN +V -V OUT
|
||||
* PINOUT ORDER 3 2 8 4 1
|
||||
.SUBCKT LMH6611 3 2 8 4 1
|
||||
*/////////////////////////////////////////////////////
|
||||
* USE V139 BELOW TO ADJUST OFFSET IF DESIRED
|
||||
* PRESENT VALUE OF -77 UV GIVES TYPICAL OFFSET
|
||||
* NOTE THAT VOS CHANGES VIA CMRR,PSRR, AND TCVOS
|
||||
* FOR BOTH THE REAL PART AND THE MODEL
|
||||
* ADJUST UP OR DOWN FROM -77 UV
|
||||
V139 14 29 -77U
|
||||
*//////////////////////////////////////////////////////////////
|
||||
* MODEL FEATURES INCLUDE OUTPUT SWING, OUTPUT CURRENT THRU
|
||||
* THE SUPPLY RAILS, OUTPUT CURRENT LIMIT, OPEN LOOP GAIN
|
||||
* AND PHASE WITH RL AND CL EFFECTS, SLEW RATE, COMMON MODE
|
||||
* REJECTION WITH FREQ EFFECTS, POWER SUPPLY REJECTION WITH
|
||||
* FREQ EFFECTS, INPUT VOLTAGE NOISE WITH 1/F, INPUT CURRENT
|
||||
* NOISE WITH 1/F, INPUT BIAS CURRENT, INPUT COMMON MODE
|
||||
* RANGE, INPUT OFFSET VOLTAGE WITH TEMPERATURE EFFECTS, AND
|
||||
* QUIESCENT CURRENT VS VOLTAGE AND TEMPERATURE.
|
||||
*//////////////////////////////////////////////////////
|
||||
D17 9 0 DIN
|
||||
D18 10 0 DIN
|
||||
I14 0 9 0.1E-3
|
||||
I15 0 10 0.1E-3
|
||||
D19 11 0 DVN
|
||||
D20 12 0 DVN
|
||||
I16 0 11 0.1E-3
|
||||
I17 0 12 0.1E-3
|
||||
E15 13 2 11 12 2.6
|
||||
G5 14 13 9 10 3E-4
|
||||
E16 15 0 16 0 1
|
||||
E17 17 0 18 0 1
|
||||
E18 19 0 20 0 1
|
||||
R56 15 21 1E6
|
||||
R57 17 22 1E6
|
||||
R58 19 23 1E6
|
||||
R59 0 21 10
|
||||
R60 0 22 10
|
||||
R61 0 23 10
|
||||
E19 24 25 23 0 1E-4
|
||||
R62 26 20 1E3
|
||||
R63 20 27 1E3
|
||||
C15 15 21 1E-12
|
||||
C16 17 22 1E-12
|
||||
C17 19 23 1E-12
|
||||
E20 28 24 22 0 -1
|
||||
E21 29 28 21 0 2
|
||||
R64 0 30 1E12
|
||||
V52 30 0 1
|
||||
G12 14 13 31 0 1.45E-14
|
||||
R136 0 31 10E3
|
||||
R137 0 31 10E3
|
||||
R138 25 24 1E9
|
||||
R139 24 28 1E9
|
||||
R140 28 29 1E9
|
||||
E54 27 0 14 0 1
|
||||
E55 26 0 13 0 1
|
||||
C23 14 13 0.25E-12
|
||||
E57 25 3 32 0 2.25E-4
|
||||
R146 25 3 1E9
|
||||
R147 0 30 1E12
|
||||
Q41 33 34 18 QLN
|
||||
R148 34 35 1E3
|
||||
R149 36 37 1E3
|
||||
R150 38 16 1
|
||||
R151 18 39 1
|
||||
R153 40 41 5
|
||||
R154 42 16 1
|
||||
R155 18 43 1
|
||||
D22 44 8 DD
|
||||
D23 4 44 DD
|
||||
E58 18 0 4 0 1
|
||||
E59 16 0 8 0 1
|
||||
R156 4 8 30E3
|
||||
E60 45 18 16 18 0.5
|
||||
D24 40 16 DD
|
||||
D25 18 40 DD
|
||||
R157 46 47 100
|
||||
R158 48 49 100
|
||||
G14 40 45 50 45 1E-3
|
||||
R159 45 40 2E6
|
||||
C24 41 51 3E-12
|
||||
C25 44 0 1E-12
|
||||
D26 49 33 DD
|
||||
D27 52 47 DD
|
||||
Q42 52 37 16 QLP
|
||||
R160 44 53 1
|
||||
R161 54 44 1
|
||||
E61 55 45 56 57 1
|
||||
R162 55 50 1E4
|
||||
C26 50 45 0.025P
|
||||
G15 58 45 40 45 -1E-3
|
||||
G16 45 59 40 45 1E-3
|
||||
G17 45 60 61 18 1E-3
|
||||
G18 62 45 16 63 1E-3
|
||||
D28 62 58 DD
|
||||
D29 59 60 DD
|
||||
R163 58 62 100E6
|
||||
R164 60 59 100E6
|
||||
R165 62 16 1E3
|
||||
R166 18 60 1E3
|
||||
R167 59 45 1E6
|
||||
R168 60 45 1E6
|
||||
R169 45 62 1E6
|
||||
R170 45 58 1E6
|
||||
G19 8 4 30 0 2.72E-3
|
||||
R171 45 50 1E9
|
||||
R172 46 16 1E9
|
||||
R173 18 48 1E9
|
||||
G20 63 61 30 0 0.25E-3
|
||||
I22 8 4 0.5E-16
|
||||
L2 44 1 3E-9
|
||||
R175 44 1 1E3
|
||||
R176 63 16 1E8
|
||||
R177 18 61 1E8
|
||||
R178 39 49 1E8
|
||||
R179 38 47 1E8
|
||||
R180 0 30 1E9
|
||||
E99 16 36 8 38 4.8
|
||||
E100 35 18 39 4 4.8
|
||||
E124 51 0 44 0 1
|
||||
R719 40 51 2E8
|
||||
I30 0 64 1E-3
|
||||
D46 64 0 DD
|
||||
R778 0 64 10E6
|
||||
V127 64 32 0.65
|
||||
R779 0 32 10E6
|
||||
Q52 53 47 38 QLP
|
||||
Q53 54 49 39 QLN
|
||||
Q54 61 61 43 QLN
|
||||
Q55 63 63 42 QLP
|
||||
E144 16 46 16 62 1
|
||||
E145 48 18 60 18 1
|
||||
Q56 65 14 66 QIN
|
||||
Q57 67 13 68 QIN
|
||||
Q58 57 69 65 QIN
|
||||
Q59 56 70 67 QIN
|
||||
Q60 69 69 16 QIP
|
||||
Q61 14 69 16 QIP
|
||||
Q62 70 70 16 QIP
|
||||
Q63 13 70 16 QIP
|
||||
R780 57 71 1200
|
||||
R781 56 71 1200
|
||||
R782 72 66 350
|
||||
R783 72 68 350
|
||||
Q64 72 73 74 QTN
|
||||
I33 0 75 1E-3
|
||||
D49 75 0 DD
|
||||
R787 0 75 10E6
|
||||
V130 75 76 1.2301
|
||||
R788 0 76 10E6
|
||||
E150 77 0 76 0 -1.75
|
||||
R789 0 77 10E6
|
||||
R790 78 77 10E6
|
||||
M3 78 79 0 0 NEN L=2U W=1000U
|
||||
G22 74 73 78 0 12E-6
|
||||
V132 80 0 1
|
||||
R791 80 79 1E6
|
||||
M4 79 81 0 0 NEN L=2U W=100U
|
||||
V133 81 0 1
|
||||
C109 57 56 70F
|
||||
V134 71 16 0.4
|
||||
C110 0 14 2E-12
|
||||
C111 13 0 2E-12
|
||||
G23 8 0 53 44 1
|
||||
G24 4 0 44 54 -1
|
||||
G25 8 4 32 0 -2.4E-3
|
||||
Q65 82 82 14 QIP
|
||||
Q66 83 82 82 QIP
|
||||
Q67 84 84 83 QIP
|
||||
Q68 14 14 84 QIP
|
||||
R792 13 83 50
|
||||
V136 74 18 -0.9
|
||||
J1 85 14 85 JNC
|
||||
J2 85 13 85 JNC
|
||||
J3 14 86 14 JNC
|
||||
J4 13 86 13 JNC
|
||||
V137 16 85 1.65
|
||||
V138 86 18 0
|
||||
I34 14 0 5.7E-6
|
||||
I35 13 0 5.7E-6
|
||||
.MODEL DD D
|
||||
.MODEL QIN NPN BF=235 RB=900
|
||||
.MODEL QIP PNP BF=235
|
||||
.MODEL QTN NPN
|
||||
.MODEL DVN D KF=2.5E-15
|
||||
.MODEL DIN D KF=8E-15
|
||||
.MODEL QLN NPN
|
||||
.MODEL QLP PNP
|
||||
.MODEL JNC NJF IS=1E-18
|
||||
.MODEL NEN NMOS KP=200U VTO=0.5 IS=1E-18
|
||||
.ENDS
|
||||
* END MODEL LMH6611
|
279
spice/ti/LMR70503_TRANS.lib
Normal file
279
spice/ti/LMR70503_TRANS.lib
Normal file
|
@ -0,0 +1,279 @@
|
|||
*$
|
||||
* LMR70503
|
||||
*****************************************************************************
|
||||
* (C) Copyright 2013 Texas Instruments Incorporated. All rights reserved.
|
||||
*****************************************************************************
|
||||
** This model is designed as an aid for customers of Texas Instruments.
|
||||
** TI and its licensors and suppliers make no warranties, either expressed
|
||||
** or implied, with respect to this model, including the warranties of
|
||||
** merchantability or fitness for a particular purpose. The model is
|
||||
** provided solely on an "as is" basis. The entire risk as to its quality
|
||||
** and performance is with the customer
|
||||
*****************************************************************************
|
||||
*
|
||||
* This model is subject to change without notice. Texas Instruments
|
||||
* Incorporated is not responsible for updating this model.
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
** Released by: WEBENCH Design Center, Texas Instruments Inc.
|
||||
* Part: LMR70503
|
||||
* Date: 20JUNE2013
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* Simulator Version: 16.2.0.p001
|
||||
* EVM Order Number: AN-2264 LMR70503
|
||||
* EVM Users Guide: SNVU155A – Revised April 2013
|
||||
* Datasheet: SNVS850A – REVISED APRIL 2013
|
||||
*
|
||||
* Model Version: Final 1.00
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*****************************************************************************
|
||||
.SUBCKT LMR70503_TRANS VIN EN GND VREF FB VOUT SW
|
||||
X_A6_minon S1tt S1tin ONE_SHOT Params: t=70
|
||||
ES1t S1t 0 value={if((V(S1tin))>0.5,5,0)}
|
||||
X13 S1 36 S1tt AND2_BASIC_GEN
|
||||
C1 FB GND 1p IC=0
|
||||
X17 S2 45 S2tt AND2_BASIC_GEN
|
||||
X18 R1t 45 INV_DELAY_BASIC_GEN
|
||||
X_A6_minon19x S2tt S2tin ONE_SHOT Params: t=70
|
||||
ES2t S2t 0 value={if(V(S2tin)>0.5,5,0)}
|
||||
X15 24 GND FBHYS COMPHYS_BASIC_GEN PARAMS:VDD=1 VTHRESH=100u
|
||||
+hyst=0.0001 VSS=-1
|
||||
E3 24 0 FB GND 1
|
||||
E_BDriver 9 GND value = { IF((V(PWMen)>1.5) ,0 ,V(VIN))}
|
||||
M1 SW 8 PS PS POWERMOS L=1u W=16670u
|
||||
.MODEL POWERMOS PMOS AF=1 KP=20u IS=1E-14 CJ=0 RD=0 RS=0 VTO=0
|
||||
Rgate 9 8 3
|
||||
Rsense PS VIN 50m
|
||||
X5 41 57 UTD PARAMS: K=1 TD=150u
|
||||
X7 52 32 49 R1tt AND3_BASIC_GEN
|
||||
X1 S2tt S1tt 12 10 NOR3_BASIC_GEN
|
||||
X2 10 R1tt R2 R3 12 NOR4_BASIC_GEN
|
||||
V2_Vref VREF GND DC=1.19
|
||||
E_B4_FBcomp S1 0 value ={IF((V(FBHYS)>0)&(V(SDbar) >1.5 ),3.3 ,0)}
|
||||
E_B5_ilimit ilimit 0 value = { IF((V(FB,GND) >0 ),320e-3 ,
|
||||
+IF(( V(FB, GND) > -7.75e-3),320e-3 + V(FB,GND)*41.2 , 0.7e-3))}
|
||||
E2_cs 35 0 VIN PS 20
|
||||
E1 Qt 0 12 0 1
|
||||
E_B2 Qt1 0 value = { IF((V(Qt)>1.5) ,1 ,0)}
|
||||
E_B3 PWM 0 value = { IF((V(Qdelayt) > 0.5 ), 5 , 0)}
|
||||
E_B6_ilimitcomp R1 0 value = { IF( V(isense) > V(ilimit), 5 , 0)}
|
||||
V3 R2 0 DC=0
|
||||
X_A3 50 28in ONE_SHOT Params: t=100
|
||||
E28 28 0 value={if(V(28in)>0.5,5,0)}
|
||||
I1 0 vramp DC=100u
|
||||
C3 vramp 0 100p IC=0
|
||||
E_B7 30 0 value = { IF((V(vramp)>1.9 ) ,5 ,0)}
|
||||
X_A4 30 S2in ONE_SHOT Params: t=100
|
||||
ES2 S2 0 value={if(V(S2in)>0.5,5,0)}
|
||||
S1 vramp 0 28 0 _S1_mod
|
||||
.MODEL _S1_mod vswitch VT=0.5 VH=0.1 RON=100 ROFF=10Meg
|
||||
V4 R3 0 DC=0
|
||||
X20 S2t 49 INV_DELAY_BASIC_GEN
|
||||
C5 12 0 10p IC=3.3
|
||||
C4 10 0 10p IC=0
|
||||
X4 Qt1 Qdelayt UTD PARAMS: K=1 TD=140n
|
||||
X21 Qt SDbar 50 AND2_BASIC_GEN
|
||||
R2 35 isense 1k
|
||||
D2 0 vramp _DLIMIT
|
||||
.MODEL _DLIMIT D
|
||||
D3 vramp 16 _DLIMIT
|
||||
X_A5_minoff R1in Tminoff R1tin Ctrl_one_shot
|
||||
ER1 R1in 0 VALUE= {if(V(R1) >2.5,1,0)}
|
||||
ER1t R1t 0 value={if((V(R1tin))>0.5,5,0)}
|
||||
V7 16 0 DC=2.5
|
||||
S2 GND VOUT SDbar 0 _S2_mod
|
||||
.MODEL _S2_mod vswitch VT=1.5 VH=0.2 RON=100k ROFF=30
|
||||
X8 S1t 32 INV_DELAY_BASIC_GEN
|
||||
X9 EN GND 41 COMPHYS_BASIC_GEN PARAMS:VDD=5 VTHRESH=0.93
|
||||
+hyst=0.16 VSS=0
|
||||
X10 VIN GND 39 COMPHYS_BASIC_GEN PARAMS:VDD=5 VTHRESH=2.55
|
||||
+hyst=0.1 VSS=0
|
||||
X11 46 39 SDbar AND2_BASIC_GEN
|
||||
X12 SDbar PWM PWMen AND2_BASIC_GEN
|
||||
X16 57 41 46 AND2_BASIC_GEN
|
||||
C6 PWMen 0 10p
|
||||
X14 R1t 36 INV_DELAY_BASIC_GEN
|
||||
C7 SDbar 0 10p IC=0
|
||||
C8 isense 0 10p IC=0
|
||||
E_E37 Toffvout 0 TABLE { V(VOUT) }
|
||||
+((-5,250) (-3.3,330) (-2.5,400)(-1.5,540) (-0.9,720)
|
||||
+ (-0.45,1000) (0,1200))
|
||||
E_B10 Tminoff 0 value = {V(Toffvout) + (V(VIN) - 2.8)*60}
|
||||
X24 R1 55 52 OR2_BASIC_GEN
|
||||
E_E17 VGSDummy 0 TABLE { V(VIN) }
|
||||
+ ( (0,2.5) (2.5,2.5) (2.8,2.8) (5.5,3.6) (6,3.6) )
|
||||
E_E27 VDSDummy 0 TABLE { V(FB) }
|
||||
+( (-1,4) (-40e-3,4) (-30e-3,3.2) (-20e-3,2) (-12e-3,0.65)
|
||||
+(-5e-3,0) (0,0))
|
||||
M2 58 VGSDummy 0 0 _DUMMYLOAD L=1u W=50u
|
||||
.MODEL _DUMMYLOAD NMOS ( VTO=0 KP=2E-5 GAMMA=0 PHI=600M LAMBDA=0
|
||||
+ RD=0 RS=0 RG=0 RB=0 RDS=0
|
||||
+ CBD=0 CBS=0 IS=1E-14 N=1 PB=800M
|
||||
+ CGSO=0 CGDO=0 CGBO=0 RSH=0 CJ=0
|
||||
+ MJ=500M CJSW=0 MJSW=500M JS=0 TOX=1e-7
|
||||
+ LD=0 UO=600 FC=500M TPG=1
|
||||
+ NSS=0 TNOM=27 KF=0 AF=1 L=1U
|
||||
+ W=50U )
|
||||
E_B8 55 0 value = { IF(V(ilimit) < 1e-3, 5 , 0)}
|
||||
G1 GND VOUT 58 VDSDummy -1
|
||||
R1 VDSDummy 58 1
|
||||
.ends LMR70503_TRANS
|
||||
*$
|
||||
.SUBCKT UTD 1 2 PARAMS: K=1 TD=1
|
||||
RIN 1 0 1E15
|
||||
E1 3 0 1 0 {K}
|
||||
T1 3 0 2 0 Z0=1 TD={TD}
|
||||
R1 2 0 1
|
||||
.ENDS UTD
|
||||
*$
|
||||
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5
|
||||
E_ABMGATE YINT 0 VALUE ={IF(V(A) > {VTHRESH} &
|
||||
+ V(B) > {VTHRESH},{VDD},{VSS})}
|
||||
RINT YINT Y 1
|
||||
CINT Y 0 1n
|
||||
.ENDS AND2_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5
|
||||
+DELAY = 1n
|
||||
E_ABMGATE1 YINT1 0 VALUE ={IF(V(A) > {VTHRESH} ,
|
||||
+ {VSS},{VDD})}
|
||||
RINT2 YINT1 Y 1
|
||||
CINT2 Y 0 1n
|
||||
.ENDS INV_DELAY_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5
|
||||
E_ABMGATE YINT 0 VALUE ={IF(V(A) > {VTHRESH} |
|
||||
+ V(B) > {VTHRESH},{VDD},{VSS})}
|
||||
RINT YINT Y 1
|
||||
CINT Y 0 1n
|
||||
.ENDS OR2_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5
|
||||
E_ABMGATE YINT 0 VALUE ={IF(V(A) > {VTHRESH} &
|
||||
+ V(B) > {VTHRESH} &
|
||||
+ V(C) > {VTHRESH},{VDD},{VSS})}
|
||||
RINT YINT Y 1
|
||||
CINT Y 0 1n
|
||||
.ENDS AND3_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5
|
||||
E_ABMGATE YINT 0 VALUE ={IF(V(A) > {VTHRESH} |
|
||||
+ V(B) > {VTHRESH} |
|
||||
+ V(C) > {VTHRESH},{VSS},{VDD})}
|
||||
RINT YINT Y 1
|
||||
CINT Y 0 1n
|
||||
.ENDS NOR3_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5
|
||||
E_ABMGATE YINT 0 VALUE ={IF(V(A) > {VTHRESH} |
|
||||
+ V(B) > {VTHRESH} |
|
||||
+ V(C) > {VTHRESH} |
|
||||
+ V(D) > {VTHRESH},{VSS},{VDD})}
|
||||
RINT YINT Y 1
|
||||
CINT Y 0 1n
|
||||
.ENDS NOR4_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT COMPHYS_BASIC_GEN INP INM OUT PARAMS: VDD=1 VSS=-1
|
||||
+VTHRESH=100u HYST=100u
|
||||
EIN INP1 INM1 INP INM 1
|
||||
EHYS INP1 INP2 VALUE ={ IF( V(1) > 0.1,{VTHRESH-HYST},{VTHRESH})}
|
||||
EOUT OUT 0 VALUE ={ IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
|
||||
R1 OUT 1 1
|
||||
C1 1 0 5n
|
||||
RINP1 INP1 0 1K
|
||||
.ENDS COMPHYS_BASIC_GEN
|
||||
*$
|
||||
.subckt one_shot in out params: t=100
|
||||
s_s1 meas 0 reset2 0 s1
|
||||
e_abm1 ch 0 value={ if( v(in)>0.5 | v(out)>0.5,1,0)}
|
||||
r_r2 reset2 reset 0.1
|
||||
e_abm3 out 0 value={ if( v(meas)<0.5 & v(ch)>0.5,1,0)}
|
||||
r_r1 meas ch {t}
|
||||
c_c2 0 reset2 1.4427n
|
||||
c_c1 0 meas 1.4427n
|
||||
e_abm2 reset 0 value={ if(v(ch)<0.5,1,0)}
|
||||
.model s1 vswitch roff=1e+009 ron=1 voff=0.25 von=0.75
|
||||
.ends one_shot
|
||||
*$
|
||||
.SUBCKT Ctrl_one_shot IN Ctrl_input OUT
|
||||
X_U586 IN VIN_ONE ONE_SHOT PARAMS: t=200
|
||||
X_U584 VIN_ONE RESET OUT RESET_OUT SRLATCHRHP_BASIC_GEN
|
||||
+PARAMS: VDD=5 VSS=0 VTHRESH=0.5
|
||||
E_ABM21 RESET 0 VALUE = { if(V(T_RAMP)>V(CTRL_INPUT_N) ,5,0)}
|
||||
X_S1 RESET_OUT 0 T_RAMP 0 Ctrl_one_shot_S1
|
||||
R_R5 0 OUT 1G TC=0,0
|
||||
E_ABM23 CTRL_INPUT_N 0 VALUE ={(V(CTRL_INPUT1)*1E06)}
|
||||
C_C2 0 T_RAMP 1n TC=0,0
|
||||
I_I1 0 T_RAMP DC 1m
|
||||
E_A22 Ctrl_input1 0 TABLE { V(Ctrl_input)} = ((-100,250n) (0,250n)
|
||||
+(250,250n) (330,330n) (400,400n) (540,540n) (720,720n) (850,850n)
|
||||
+(1000,1000n ) (1500,1500n) (2000,1500n) )
|
||||
.ENDS Ctrl_one_shot
|
||||
*$
|
||||
.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}
|
||||
CQint Qint 0 1n
|
||||
RQint Qint 0 1000MEG
|
||||
D_D10 Qint MY5 D_D1
|
||||
V1 MY5 0 {VDD}
|
||||
D_D11 MYVSS Qint D_D1
|
||||
V2 MYVSS 0 {VSS}
|
||||
EQ Qqq 0 Qint 0 1
|
||||
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS:VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
|
||||
RQq Qqqd1 Q 1
|
||||
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
|
||||
RQb Qbr QB 1
|
||||
Cdummy1 Q 0 1n
|
||||
Cdummy2 QB 0 1n
|
||||
.IC V(Qint) {VSS}
|
||||
.ENDS SRLATCHRHP_BASIC_GEN
|
||||
*$
|
||||
.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
|
||||
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
|
||||
+ {VDD},{VSS})}}
|
||||
RINT YINT Y 1
|
||||
CINT Y 0 1n
|
||||
.ENDS BUF_BASIC_GEN
|
||||
*$
|
||||
.MODEL D_D1 D( IS=1e-15 Rs=0.005 N=.1 )
|
||||
*$
|
||||
.subckt Ctrl_one_shot_S1 1 2 3 4
|
||||
S_S1 3 4 1 2 _S1
|
||||
RS_S1 1 2 1G
|
||||
.MODEL _S1 VSWITCH Roff=1e9 Ron=1.0m Voff=0.5V Von=1.5V
|
||||
.ends Ctrl_one_shot_S1
|
||||
*$
|
||||
.SUBCKT CESR IN OUT
|
||||
+ PARAMs: C=100u ESR=0.01 IC=0
|
||||
C IN 1 {C} IC={IC}
|
||||
RESR 1 OUT {ESR}
|
||||
.ENDS CESR
|
||||
*$
|
||||
.SUBCKT LDCR IN OUT
|
||||
+ PARAMs: L=1u DCR=0.01 IC=0
|
||||
L IN 1 {L} IC={IC}
|
||||
RDCR 1 OUT {DCR}
|
||||
.ENDS LDCR
|
||||
*$
|
||||
.MODEL D1N6650 D BV=22 CJO=3.874e-11 EG=0.69 IS=1.028e-5
|
||||
+ M=.4641 N=0.9172 RS=0.3489 VJ=0.3188 XTI=2
|
||||
*$
|
||||
.END
|
||||
*$
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
356
spice/ti/OPA810.lib
Normal file
356
spice/ti/OPA810.lib
Normal file
|
@ -0,0 +1,356 @@
|
|||
* OPA810 - Rev. A
|
||||
* Created by Sean Cashin; 2020-06-11
|
||||
* Created with Green-Williams-Lis Current Sense Amp Macro-model Architecture
|
||||
* Copyright 2020 by Texas Instruments Corporation
|
||||
******************************************************
|
||||
* MACRO-MODEL SIMULATED PARAMETERS:
|
||||
******************************************************
|
||||
* AC PARAMETERS
|
||||
**********************
|
||||
* CLOSED-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zout vs. Freq.)
|
||||
* CLOSED-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Acl vs. Freq.)
|
||||
* COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR vs. Freq.)
|
||||
* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR vs. Freq.)
|
||||
* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en vs. Freq.)
|
||||
**********************
|
||||
* DC PARAMETERS
|
||||
**********************
|
||||
* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
|
||||
* GAIN ERROR (Eg)
|
||||
* INPUT BIAS CURRENT VS. INPUT COMMON-MODE VOLTAGE (Ib vs. Vcm)
|
||||
* INPUT OFFSET VOLTAGE VS. TEMPERATURE (Vos vs. Temp)
|
||||
* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vout vs. Iout)
|
||||
* SHORT-CIRCUIT OUTPUT CURRENT (Isc)
|
||||
* QUIESCENT CURRENT (Iq)
|
||||
**********************
|
||||
* TRANSIENT PARAMETERS
|
||||
**********************
|
||||
* SLEW RATE (SR)
|
||||
* SETTLING TIME VS. CAPACITIVE LOAD (ts)
|
||||
* OVERLOAD RECOVERY TIME (tor)
|
||||
******************************************************
|
||||
.subckt OPA810 IN+ IN- OUT VCC VEE
|
||||
******************************************************
|
||||
.MODEL R_NOISE RES (T_ABS=0)
|
||||
.MODEL R_NOISELESS RES (T_ABS=-273.15)
|
||||
C_C12 MID N45892 1E-15
|
||||
C_C13 N45974 MID 1E-15
|
||||
C_C17 MID N68747 1E-12
|
||||
C_C18 MID N68594 1E-12
|
||||
C_C19 MID SW_OL_OPA810 1E-12
|
||||
C_C1A N725398 N725428 15.92E-6
|
||||
C_C1A1 N701935 N701965 3.537P
|
||||
C_C1A10 N789898 N789912 342.3F
|
||||
C_C1A4 N709083 N709113 63.66N
|
||||
C_C1A9 N704975 N705005 83.77N
|
||||
C_C1C1 N821901 N725762 159.2E-9
|
||||
C_C1C3 N725214 N725836 26.53E-15
|
||||
C_C1D MID N725708 93.62E-15
|
||||
C_C1_0 MID N79181 23.5E-9
|
||||
C_C2 MID N694641 740E-12
|
||||
C_C3 MID N694487 740E-12
|
||||
C_C33 N406634 0 1E-15
|
||||
C_C34 N317950 0 1
|
||||
C_C35 N406794 0 1E-15
|
||||
C_C36 N894736 N892256 227.4E-12
|
||||
C_C7 N31014 MID 1E-15
|
||||
C_C8 MID N35813 1E-15
|
||||
C_C9 MID N38096 1E-15
|
||||
C_C_CMN MID ESDN 2.5E-12
|
||||
C_C_CMP ESDP MID 2.5E-12
|
||||
C_C_DIFF ESDN ESDP 0.5E-12
|
||||
C_C_VCLP VCLP MID 1E-12
|
||||
C_C_VIMON MID VIMON 1E-9
|
||||
C_C_VOUT_S MID VOUT_S 1E-9
|
||||
E_E2 N91498 MID CL_CLAMP MID 1
|
||||
E_E3 N112292 MID OUT MID 1
|
||||
E_E6 MID 0 N317950 0 1
|
||||
G_G1 N725398 MID CL_CLAMP N516723 -90.91
|
||||
G_G10 N73852 MID N55875 MID -1
|
||||
G_G11 N55050 MID N56119 MID -1
|
||||
G_G16 CL_CLAMP MID N894736 MID -1E-3
|
||||
G_G2 N10570 N10561 N701965 MID -1E-3
|
||||
G_G36 VCC_B 0 VCC 0 -1
|
||||
G_G37 VEE_B 0 VEE 0 -1
|
||||
G_G54 N694641 MID N79181 MID -1
|
||||
G_G55 N701935 MID N789912 MID -222.22
|
||||
G_G56 N709083 MID VCC_B MID -1.265
|
||||
G_G58 N704975 MID VEE_B MID -1.664
|
||||
G_G59 N789898 MID ESDP MID -29.75M
|
||||
G_G6 N25816 N11984 N709113 N705005 -1E-3
|
||||
G_G60 N06456 MID N799160 MID -10E-6
|
||||
G_G61 ESDN MID N804105 MID -10E-6
|
||||
G_G62 N821901 MID N725428 MID -100
|
||||
G_G63 N892256 MID N694487 MID -1.3
|
||||
G_G7 N694487 MID N694641 MID -1
|
||||
G_G8 VCC_CLP MID N35813 MID -1E-3
|
||||
G_G9 VEE_CLP MID N38096 MID -1E-3
|
||||
G_GB N725346 MID N725762 MID -25
|
||||
G_GD4 N725214 MID N725574 MID -0.3
|
||||
G_GD5 N725936 MID N725836 MID -166.7
|
||||
I_I_B N06456 MID DC 2E-12
|
||||
I_I_OS ESDN MID DC 1E-12
|
||||
I_I_Q VCC VEE DC 1.9E-3
|
||||
R_R1 ESDP IN+ R_NOISELESS 10E-3
|
||||
R_R10 ESDN N11991 R_NOISELESS 1E-3
|
||||
R_R107 VCC_B 0 R_NOISELESS 1
|
||||
R_R108 N317950 0 R_NOISELESS 1E12
|
||||
R_R109 VEE_B 0 R_NOISELESS 1
|
||||
R_R11 MID N725346 R_NOISELESS 1
|
||||
R_R110 VCC_B N406634 R_NOISELESS 1E-3
|
||||
R_R111 N406634 N317950 R_NOISELESS 1E6
|
||||
R_R112 N317950 N406794 R_NOISELESS 1E6
|
||||
R_R113 N406794 VEE_B R_NOISELESS 1E-3
|
||||
R_R133 N694487 MID R_NOISELESS 1
|
||||
R_R134 N694641 MID R_NOISELESS 1
|
||||
R_R135 N701935 MID R_NOISELESS 1
|
||||
R_R136 N704975 MID R_NOISELESS 1
|
||||
R_R137 MID N725398 R_NOISELESS 1
|
||||
R_R139 MID N725214 R_NOISELESS 1
|
||||
R_R140 MID N725936 R_NOISELESS 1
|
||||
R_R141 N789898 MID R_NOISELESS 1
|
||||
R_R145 MID N821901 R_NOISELESS 1
|
||||
R_R149 N892256 MID R_NOISELESS 1
|
||||
R_R150 N894736 MID R_NOISELESS 33.3
|
||||
R_R151 N892256 N894736 R_NOISELESS 10
|
||||
R_R1A N725428 N725398 R_NOISELESS 10E3
|
||||
R_R1A1 N701935 N701965 R_NOISELESS 1E4
|
||||
R_R1A10 N789898 N789912 R_NOISELESS 1E8
|
||||
R_R1A11 MID N799160 R_NOISE 15
|
||||
R_R1A12 MID N804105 R_NOISE 15
|
||||
R_R1A3 N704975 N705005 R_NOISELESS 1E8
|
||||
R_R1A4 N709083 N709113 R_NOISELESS 1E8
|
||||
R_R1C1 N725762 N821901 R_NOISELESS 10E3
|
||||
R_R1C2 N725836 N725214 R_NOISELESS 1E4
|
||||
R_R1D1 N725708 N725574 R_NOISELESS 10E3
|
||||
R_R2 ESDN IN- R_NOISELESS 10E-3
|
||||
R_R21 N11984 N25816 R_NOISELESS 1E3
|
||||
R_R25 MID N28602 R_NOISELESS 1E9
|
||||
R_R26 N30136 MID R_NOISELESS 1E9
|
||||
R_R27 MID N30913 R_NOISELESS 1
|
||||
R_R28 N31014 N30913 R_NOISELESS 1E-3
|
||||
R_R29 N35669 VCC_B R_NOISELESS 1E3
|
||||
R_R2A1 N701965 MID R_NOISELESS 45.2
|
||||
R_R2A10 N705005 MID R_NOISELESS 19M
|
||||
R_R2A11 N789912 MID R_NOISELESS 465
|
||||
R_R2A13 MID N725428 R_NOISELESS 101
|
||||
R_R2A4 N709113 MID R_NOISELESS 25M
|
||||
R_R2C1 MID N725762 R_NOISELESS 416.7
|
||||
R_R2C3 MID N725836 R_NOISELESS 60.36
|
||||
R_R2D N725574 N725346 R_NOISELESS 367.8E3
|
||||
R_R3 MID ESDP R_NOISELESS 1E12
|
||||
R_R30 N35813 N35669 R_NOISELESS 1E-3
|
||||
R_R31 VCC_CLP MID R_NOISELESS 1E3
|
||||
R_R32 N38050 VEE_B R_NOISELESS 1E3
|
||||
R_R33 N38096 N38050 R_NOISELESS 1E-3
|
||||
R_R34 VEE_CLP MID R_NOISELESS 1E3
|
||||
R_R4 ESDN MID R_NOISELESS 1E12
|
||||
R_R41 MID N50645 R_NOISELESS 1E9
|
||||
R_R42 N45856 MID R_NOISELESS 1
|
||||
R_R43 N45892 N45856 R_NOISELESS 1E-3
|
||||
R_R44 N45974 N45986 R_NOISELESS 1E-3
|
||||
R_R45 MID N45986 R_NOISELESS 1
|
||||
R_R46 MID N48550 R_NOISELESS 1E9
|
||||
R_R47 MID N73852 R_NOISELESS 1
|
||||
R_R48 MID N55050 R_NOISELESS 1
|
||||
R_R5 N709083 MID R_NOISELESS 1
|
||||
R_R56 N68747 OLN R_NOISELESS 100
|
||||
R_R57 N68594 OLP R_NOISELESS 100
|
||||
R_R58 N69264 MID R_NOISELESS 1
|
||||
R_R59 N69264 SW_OL_OPA810 R_NOISELESS 100
|
||||
R_R60 MID AOLNET R_NOISELESS 1E6
|
||||
R_R66 MID CL_CLAMP R_NOISELESS 1E3
|
||||
R_R8 N10561 N10570 R_NOISELESS 1E3
|
||||
R_R81 MID N110431 R_NOISELESS 1E9
|
||||
R_R83 MID N112292 R_NOISELESS 1E9
|
||||
R_R9 N10570 N11984 R_NOISELESS 1E-3
|
||||
R_RDUMMY1 MID N516723 R_NOISELESS 10E3
|
||||
R_RX1 N516723 N725936 R_NOISELESS 100E3
|
||||
R_R_VCLP N91498 VCLP R_NOISELESS 100
|
||||
R_R_VIMON VIMON N110431 R_NOISELESS 100
|
||||
R_R_VOUT_S VOUT_S N112292 R_NOISELESS 100
|
||||
V_VCM_MAX N30136 VCC_B 0.15
|
||||
V_VCM_MIN N28602 VEE_B -0.2
|
||||
V_V_ISCN N48550 MID -120
|
||||
V_V_ISCP N50645 MID 120
|
||||
V_V_ORN N55875 VCLP -68.5
|
||||
V_V_ORP N56119 VCLP 37.13
|
||||
X_AOL_1 N31014 N11991 MID AOLNET AOL_1_OPA810
|
||||
X_AOL_2 AOLNET MID MID N79181 AOL_2_OPA810
|
||||
X_CLAWN MID VIMON VEE_B N38050 CLAWN_OPA810
|
||||
X_CLAWP VIMON MID N35669 VCC_B CLAWP_OPA810
|
||||
X_CL_AMP N50645 N48550 VIMON MID N45856 N45986 CLAMP_AMP_LO_OPA810
|
||||
X_CL_SRC N45892 N45974 CL_CLAMP MID CL_SRC_OPA810
|
||||
X_ESD_OUT OUT VCC VEE ESD_OUT_OPA810
|
||||
X_E_N ESDP N06456 VNSE_OPA810
|
||||
X_H1 N73852 N166377 OLN MID 08_OP_AMP_COMPLETE_H1_OPA810
|
||||
X_H2 N55050 N166817 OLP MID 08_OP_AMP_COMPLETE_H2_OPA810
|
||||
X_H3 OUT N516723 N110431 MID 08_OP_AMP_COMPLETE_H3_OPA810
|
||||
X_IQ_N MID VIMON MID VEE IQ_SRC_OPA810
|
||||
X_IQ_P VIMON MID VCC MID IQ_SRC_OPA810
|
||||
X_OL_SENSE MID N69264 N68747 N68594 OL_SENSE_OPA810
|
||||
X_S1 OUT VCC_CLP N79181 MID 08_OP_AMP_COMPLETE_S1_OPA810
|
||||
X_S2 VEE_CLP OUT N79181 MID 08_OP_AMP_COMPLETE_S2_OPA810
|
||||
X_SW_OL SW_OL_OPA810 MID N725398 N725428 SW_OL_OPA810
|
||||
X_SW_OR CLAMP N166377 N166817 SW_OR_OPA810
|
||||
X_VCM_CLAMP N25816 MID N30913 MID N30136 N28602 VCM_CLAMP_OPA810
|
||||
X_VOS_DRIFT N749288 N06456 VOS_DRIFT_OPA810
|
||||
X_VOS_VS_VCM N10561 N749288 VCC VEE VOS_VS_VCM_OPA810
|
||||
.ENDS OPA810
|
||||
*
|
||||
.SUBCKT 08_OP_AMP_COMPLETE_H1_OPA810 1 2 3 4
|
||||
H_H1 3 4 VH_H1 1
|
||||
VH_H1 1 2 0V
|
||||
.ENDS 08_OP_AMP_COMPLETE_H1_OPA810
|
||||
*
|
||||
.SUBCKT 08_OP_AMP_COMPLETE_H2_OPA810 1 2 3 4
|
||||
H_H2 3 4 VH_H2 -1
|
||||
VH_H2 1 2 0V
|
||||
.ENDS 08_OP_AMP_COMPLETE_H2_OPA810
|
||||
*
|
||||
.SUBCKT 08_OP_AMP_COMPLETE_H3_OPA810 1 2 3 4
|
||||
H_H3 3 4 VH_H3 -1E3
|
||||
VH_H3 1 2 0V
|
||||
.ENDS 08_OP_AMP_COMPLETE_H3_OPA810
|
||||
*
|
||||
.SUBCKT 08_OP_AMP_COMPLETE_S1_OPA810 1 2 3 4
|
||||
S_S1 3 4 1 2 _S1
|
||||
RS_S1 1 2 1G
|
||||
.MODEL _S1 VSWITCH ROFF=200E3 RON=0.5 VOFF=-1 VON=0.4
|
||||
.ENDS 08_OP_AMP_COMPLETE_S1_OPA810
|
||||
*
|
||||
.SUBCKT 08_OP_AMP_COMPLETE_S2_OPA810 1 2 3 4
|
||||
S_S2 3 4 1 2 _S2
|
||||
RS_S2 1 2 1G
|
||||
.MODEL _S2 VSWITCH ROFF=200E3 RON=0.5 VOFF=-1 VON=0.4
|
||||
.ENDS 08_OP_AMP_COMPLETE_S2_OPA810
|
||||
*
|
||||
.SUBCKT AOL_1_OPA810 VC+ VC- IOUT+ IOUT-
|
||||
.PARAM GAIN = 1E-2
|
||||
.PARAM IPOS = .5
|
||||
.PARAM INEG = -.5
|
||||
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
|
||||
.ENDS AOL_1_OPA810
|
||||
*
|
||||
.SUBCKT AOL_2_OPA810 VC+ VC- IOUT+ IOUT-
|
||||
.PARAM GAIN = 1E-3
|
||||
.PARAM IPOS = 5.6
|
||||
.PARAM INEG = -5.6
|
||||
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
|
||||
.ENDS AOL_2_OPA810
|
||||
*
|
||||
.SUBCKT CLAMP_AMP_LO_OPA810 VC+ VC- VIN COM VO+ VO-
|
||||
.PARAM G=1
|
||||
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
|
||||
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
|
||||
.ENDS CLAMP_AMP_LO_OPA810
|
||||
*
|
||||
.SUBCKT CLAWN_OPA810 VC+ VC- IOUT+ IOUT-
|
||||
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
|
||||
+(0, 10E-5)
|
||||
+(30, 10E-5)
|
||||
+(40, 10E-5)
|
||||
+(60, 10E-5)
|
||||
+(70, 10E-5)
|
||||
+(80, 20E-5)
|
||||
+(90, 30E-5)
|
||||
+(100, 40E-5)
|
||||
+(110, 500E-5)
|
||||
+(120, 1000E-5)
|
||||
.ENDS CLAWN_OPA810
|
||||
*
|
||||
.SUBCKT CLAWP_OPA810 VC+ VC- IOUT+ IOUT-
|
||||
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
|
||||
+(0, 8E-5)
|
||||
+(30, 10E-5)
|
||||
+(40, 28E-5)
|
||||
+(50, 36E-5)
|
||||
+(60, 50E-5)
|
||||
+(70, 100E-5)
|
||||
+(80, 200E-5)
|
||||
+(90, 400E-5)
|
||||
+(100, 800E-5)
|
||||
+(110, 1600E-5)
|
||||
+(120, 3200E-5)
|
||||
.ENDS CLAWP_OPA810
|
||||
*
|
||||
.SUBCKT CL_SRC_OPA810 VC+ VC- IOUT+ IOUT-
|
||||
.PARAM GAIN = 1
|
||||
.PARAM IPOS = 16.8
|
||||
.PARAM INEG = -16.8
|
||||
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
|
||||
.ENDS CL_SRC_OPA810
|
||||
*
|
||||
.SUBCKT ESD_OUT_OPA810 OUT VCC VEE
|
||||
.MODEL ESD_SW VSWITCH(RON=50 ROFF=1E12 VON=500E-3 VOFF=450E-3)
|
||||
S1 VCC OUT OUT VCC ESD_SW
|
||||
S2 OUT VEE VEE OUT ESD_SW
|
||||
.ENDS ESD_OUT_OPA810
|
||||
*
|
||||
.SUBCKT IQ_SRC_OPA810 VC+ VC- IOUT+ IOUT-
|
||||
.PARAM GAIN = 1E-3
|
||||
G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )}
|
||||
.ENDS IQ_SRC_OPA810
|
||||
*
|
||||
.SUBCKT OL_SENSE_OPA810 1 2 3 4
|
||||
GSW+ 1 2 VALUE = {IF((V(3,1)>10E-3 | V(4,1)>10E-3),1,0)}
|
||||
.ENDS OL_SENSE_OPA810
|
||||
*
|
||||
.SUBCKT SW_OL_OPA810 SW_OL_OPA810 MID CAP_L CAP_R
|
||||
.MODEL OL_SW VSWITCH(RON=1E-3 ROFF=1E9 VON=900E-3 VOFF=800E-3)
|
||||
S1 CAP_L CAP_R SW_OL_OPA810 MID OL_SW
|
||||
.ENDS SW_OL_OPA810
|
||||
*
|
||||
.SUBCKT SW_OR_OPA810 CLAMP OLN OLP
|
||||
.MODEL OR_SW VSWITCH(RON=10E-3 ROFF=1E9 VON=10E-3 VOFF=0)
|
||||
S1 OLP CLAMP CLAMP OLP OR_SW
|
||||
S2 CLAMP OLN OLN CLAMP OR_SW
|
||||
.ENDS SW_OR_OPA810
|
||||
*
|
||||
.SUBCKT VCM_CLAMP_OPA810 VIN+ VIN- IOUT- IOUT+ VP+ VP-
|
||||
.PARAM GAIN = 1
|
||||
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
|
||||
.ENDS VCM_CLAMP_OPA810
|
||||
*
|
||||
.SUBCKT VNSE_OPA810 1 2
|
||||
.PARAM FLW=0.1
|
||||
.PARAM NLF=1190
|
||||
.PARAM NVR=5.7
|
||||
.PARAM GLF={PWR(FLW,0.25)*NLF/1164}
|
||||
.PARAM RNV={1.184*PWR(NVR,2)}
|
||||
.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
|
||||
I1 0 7 10E-3
|
||||
I2 0 8 10E-3
|
||||
D1 7 0 DVN
|
||||
D2 8 0 DVN
|
||||
E1 3 6 7 8 {GLF}
|
||||
R1 3 0 1E9
|
||||
R2 3 0 1E9
|
||||
R3 3 6 1E9
|
||||
E2 6 4 5 0 10
|
||||
R4 5 0 {RNV}
|
||||
R5 5 0 {RNV}
|
||||
R6 3 4 1E9
|
||||
R7 4 0 1E9
|
||||
E3 1 2 3 4 1
|
||||
.ENDS VNSE_OPA810
|
||||
*
|
||||
.SUBCKT VOS_DRIFT_OPA810 VOS+ VOS-
|
||||
.PARAM DC = 76.1E-6
|
||||
.PARAM POL = 1
|
||||
.PARAM DRIFT = 0.3E-6
|
||||
E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}
|
||||
.ENDS VOS_DRIFT_OPA810
|
||||
*
|
||||
.SUBCKT VOS_VS_VCM_OPA810 V+ V- REF+ REF-
|
||||
E1 V+ 1 TABLE {(V(REF+, V-))} =
|
||||
+(0.35, 450E-6)
|
||||
+(0.4, 435E-6)
|
||||
+(0.55, 275E-6)
|
||||
+(0.65, 150E-6)
|
||||
+(0.75, 75E-6)
|
||||
+(0.85, 25E-6)
|
||||
+(1, 0)
|
||||
V1 1 V- 0
|
||||
.ENDS VOS_VS_VCM_OPA810
|
||||
*
|
|
@ -0,0 +1,137 @@
|
|||
@OrCAD Simulation Server Version: 1.0
|
||||
|
||||
@Settings: 0 1
|
||||
@General:
|
||||
ProfileName= "trans"
|
||||
ProfileFile= "trans.sim"
|
||||
Connectivity= "SCHEMATIC1.net"
|
||||
NetlistFile= "trans.cir"
|
||||
DataFile= "trans.dat"
|
||||
OutFile= "trans.out"
|
||||
Notes=
|
||||
@#$BEGINNOTES
|
||||
@#$ENDNOTES
|
||||
@End General
|
||||
@Analysis: 0 1
|
||||
+0 0 0 0
|
||||
+0 "1m"
|
||||
+1 ""
|
||||
+2 "0"
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
@End Analysis
|
||||
@Analysis: 1 0
|
||||
+2 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 2 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 3 0
|
||||
+0 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
@End Analysis
|
||||
@Analysis: 4 0
|
||||
+0 0 1 0 0 0 0 0 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
LoadFile 0 ""
|
||||
SaveFile 0 ""
|
||||
@End Analysis
|
||||
@Analysis: 5 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 6 0
|
||||
+1
|
||||
+0 ""
|
||||
@End Analysis
|
||||
@Analysis: 7 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 8 0
|
||||
+0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 9 0
|
||||
+0 ""
|
||||
@End Analysis
|
||||
@Analysis: 10 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 11 1
|
||||
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
+ 0 0 0 0 0 0 0 0 0
|
||||
@End Analysis
|
||||
@Analysis: 12 0
|
||||
+2236960 0
|
||||
@End Analysis
|
||||
@Analysis: 13 1
|
||||
+0 1 1 1
|
||||
@End Analysis
|
||||
@Analysis: 14 1
|
||||
+1 1 1 "*"
|
||||
@End Analysis
|
||||
@Analysis: 15 0
|
||||
@End Analysis
|
||||
@Analysis: 16 0
|
||||
+0 "0"
|
||||
+1 "0"
|
||||
+2 "chkpt_default, , ,"
|
||||
@End Analysis
|
||||
@Analysis: 17 0
|
||||
+0 "-1"
|
||||
+1 ""
|
||||
+2 "-1"
|
||||
+3 "-1"
|
||||
+4 "1"
|
||||
@End Analysis
|
Binary file not shown.
|
@ -0,0 +1,76 @@
|
|||
[DISPLAYS]
|
||||
BEGIN DISPLAY LAST SESSION
|
||||
ANALYSIS TRANSIENT_ANALYSIS
|
||||
SYMBOL ALWAYS
|
||||
TRACECOLORSCHEME NORMAL
|
||||
BEGIN ANAPLOT 1
|
||||
XBASE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT s
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
END XAXIS
|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
ACTIVE
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT V
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
BEGIN TRACE V(Vout)
|
||||
MARKERID 1
|
||||
END TRACE V(Vout)
|
||||
END YAXIS 1
|
||||
END ANAPLOT 1
|
||||
BEGIN ANAPLOT 2
|
||||
ACTIVE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT s
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
END XAXIS
|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
ACTIVE
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT V
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
BEGIN TRACE V(Vin)
|
||||
MARKERID 2
|
||||
END TRACE V(Vin)
|
||||
END YAXIS 1
|
||||
END ANAPLOT 2
|
||||
END DISPLAY LAST SESSION
|
BIN
spice/ti/TLV70012_PSPICE_TRANS/TLV70012.DSN
Normal file
BIN
spice/ti/TLV70012_PSPICE_TRANS/TLV70012.DSN
Normal file
Binary file not shown.
BIN
spice/ti/TLV70012_PSPICE_TRANS/TLV70012.OLB
Normal file
BIN
spice/ti/TLV70012_PSPICE_TRANS/TLV70012.OLB
Normal file
Binary file not shown.
70
spice/ti/TLV70012_PSPICE_TRANS/TLV70012.lib
Normal file
70
spice/ti/TLV70012_PSPICE_TRANS/TLV70012.lib
Normal file
|
@ -0,0 +1,70 @@
|
|||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70012 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2011 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
|
||||
* Part: TLV70012
|
||||
* Date: 04/05/2011
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number:
|
||||
* EVM Users Guide:
|
||||
* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70012
|
||||
*$
|
||||
.SUBCKT TLV70012 IN GND EN OUT
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dce2e9103f51d0de79
|
||||
259e22a51c65bc4dee29b1af577e67324e552c8ab90b219a64615adc73efa63218909a58bd8b76904fcdb80814ad954a373688de6049867ad38aff4e12555a5d
|
||||
af1dff2e8151d1b3ad961377e023ab654e552c8ab90b219a64615adc73efa632ade02a6c3e64e287c90ba24b54740a7a2a931f55ee8d47b0d3b55e518a88efc0
|
||||
259e22a51c65bc4da1b65c0354cbc4412531ce9df5eb0603c921153da52548beb6f9c085d8eda78df34d311b7ac26f46c1f60d7ea22f9ce9e07acc9f85f01ad6
|
||||
259e22a51c65bc4d51a924006509d8924e552c8ab90b219a64615adc73efa632d9ae151f53d140dbc88e473ce12bfd9706ea93996f83a7bddf7a8af3bf3808c1
|
||||
259e22a51c65bc4d183fce15e18b18aa239bdbe658d21d004e837baae6a4ac8864615adc73efa6327ef5870a5e3da03d727a1739f56464652ba2c1c1728c017b
|
||||
af1dff2e8151d1b3ed846c24bda46d9644f91394b9d9e84610977954546a053d822ef85746450e5043e100eee5b305a94c49b18e65b20125cd81523dba430406
|
||||
3fc4c23aa5b659665a17e7431216915f504ad14f2fb29f6c71cf3cb4f0f12316644126c9831a96bd58f95f397589bbe7e854495f016ffd76d22b26a7b6cfc473
|
||||
5d078000650a8fa5f720513110d464d784228f9fa61e3ec38675a01b2db95be71bddfb574903d61a725ed083df9a515d637d1b072f0e2ebe507e5c82eb9edef9
|
||||
af1dff2e8151d1b3ed846c24bda46d96f5687491f31f292410977954546a053dca2f8c83eb5775a39c064bf94d8ce6078492e52ca990713779eccb7eaf03f4e4
|
||||
97273dca314e0f137158f7066bb1acc8e884561dc52031d166f9df056a16ed558b31c7db94f482141bddfb574903d61a725ed083df9a515d654bea6dfaccad75
|
||||
427c310c1c1f6b42fcdff44f046d00717e012483319edfad3d1a96345bca769f156308c046a85546e73070a45f1d549c8ae9764513fec3e270ea434bac481a10
|
||||
af1dff2e8151d1b3ed846c24bda46d9605f06f9213ce83ba10977954546a053dca2f8c83eb5775a3ecbee74170ca80188492e52ca990713779eccb7eaf03f4e4
|
||||
a96c53d84a6e3a2c777909964b84d5bf2b81e10e996e19ac294ff995b8f67f658ae9764513fec3e28e779e2db5abbf64f4f2ab4e4c8c394ffa8db939ff1224c4
|
||||
cd080d6014ef79b45b21fcbb5127d82b1bddfb574903d61a725ed083df9a515d637d1b072f0e2ebed3bdfb0233d3746a97fd1405997c9bbe211952a674e6752c
|
||||
ce1e320d9877b21bc90ba24b54740a7aa7d24ab7ae54f3c7cb82e1066e82af78e73070a45f1d549c8ae9764513fec3e28e779e2db5abbf646871dc705148aaae
|
||||
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|
||||
259e22a51c65bc4d695c770f0bec7fcc4e552c8ab90b219a605c5accbc975768c76c6f59598c925ec90ba24b54740a7ab286dd1121d2a6d23c33417d989f4d2c
|
||||
79b347c5b85360ef9dd0e5cec1514afc4e552c8ab90b219a64615adc73efa632d9ae151f53d140db68bc7b4cd898b01306ea93996f83a7bddf7a8af3bf3808c1
|
||||
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|
||||
259e22a51c65bc4d1db1e7e640c0f26a4e552c8ab90b219a64615adc73efa63218909a58bd8b76908c0e8091394b985661a0613e3a41a223d38aff4e12555a5d
|
||||
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|
||||
c90ba24b54740a7accefcc2bf8692e3b8ae9764513fec3e28e779e2db5abbf64f4f2ab4e4c8c394f02f29020cc6bed9a5594c975cd36d3d3456e122046cc1edb
|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70012
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70012_F1 1 2 3 4
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dce2e9103f51d0de79
|
||||
4f9bfd860debeaf29a2f4988e6fd138446b92e86e8aaa0ba6346aa19326e7599631ebabd5b20ecbf57e2c5aa80851370dcb2222a3ac73375375bc7f7c20b6cb9
|
||||
476007b7708ce3cdb942d935367989681852d2bae2562872b9ef19aa8805d3198e3bef92b0a3919088b82ad28ee6d41b53c9f4b6d37454d87b866626a673e230
|
||||
$CDNENCFINISH
|
||||
.ends SCHEMATIC1_TLV70012_F1
|
||||
*$
|
||||
|
49
spice/ti/TLV70012_PSPICE_TRANS/TLV70012.opj
Normal file
49
spice/ti/TLV70012_PSPICE_TRANS/TLV70012.opj
Normal file
|
@ -0,0 +1,49 @@
|
|||
(ExpressProject "TLV70012"
|
||||
(ProjectVersion "19981106")
|
||||
(ProjectType "Analog or A/D Mixed Mode")
|
||||
(Folder "Design Resources"
|
||||
(Folder "Library")
|
||||
(NoModify)
|
||||
(File ".\tlv70012.dsn"
|
||||
(Type "Schematic Design"))
|
||||
(BuildFileAddedOrDeleted "x")
|
||||
(CompileFileAddedOrDeleted "x")
|
||||
(PSPICE_Regenerate_Netlist_Flag "FALSE"))
|
||||
(Folder "Outputs"
|
||||
(File ".\tlv70012-pspicefiles\schematic1\schematic1.net"
|
||||
(Type "Report")))
|
||||
(Folder "PSpice Resources"
|
||||
(Folder "Simulation Profiles"
|
||||
(ActiveProfile ".\tlv70012-pspicefiles\schematic1\trans.sim")
|
||||
(File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
|
||||
".\tlv70012-pspicefiles\schematic1\trans.sim"
|
||||
(DisplayName "SCHEMATIC1-trans")
|
||||
(Type "PSpice Profile")))
|
||||
(Folder "Model Libraries"
|
||||
(Sort User)
|
||||
(File ".\tlv70012.lib"
|
||||
(Type "PSpiceLibrary")
|
||||
(DisplayName ".\tlv70012.lib")))
|
||||
(Folder "Stimulus Files"
|
||||
(Sort User))
|
||||
(Folder "Include Files"
|
||||
(Sort User)))
|
||||
(DefaultLibraryBrowseDirectory "library\PSpice")
|
||||
(PartMRUSelector
|
||||
(TLV70012
|
||||
(FullPartName "TLV70012.Normal")
|
||||
(LibraryName
|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70012\RELEASE_TI\PSPICE\TLV70012_PSPICE_TRANS\TLV70012.OLB")
|
||||
(DeviceIndex "0")))
|
||||
(LastUsedLibraryBrowseDirectory
|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70012\Release_TI\PSPICE\TLV70012_PSPICE_TRANS")
|
||||
(GlobalState
|
||||
(FileView
|
||||
(Path "Design Resources")
|
||||
(Path "Outputs"))
|
||||
(HierarchyView)
|
||||
(Doc
|
||||
(Type "COrCapturePMDoc")
|
||||
(Frame
|
||||
(Placement "44 0 1 -1 -1 -1 -1 0 200 0 367"))
|
||||
(Tab 0))))
|
|
@ -0,0 +1,137 @@
|
|||
@OrCAD Simulation Server Version: 1.0
|
||||
|
||||
@Settings: 0 1
|
||||
@General:
|
||||
ProfileName= "trans"
|
||||
ProfileFile= "trans.sim"
|
||||
Connectivity= "SCHEMATIC1.net"
|
||||
NetlistFile= "trans.cir"
|
||||
DataFile= "trans.dat"
|
||||
OutFile= "trans.out"
|
||||
Notes=
|
||||
@#$BEGINNOTES
|
||||
@#$ENDNOTES
|
||||
@End General
|
||||
@Analysis: 0 1
|
||||
+0 0 0 0
|
||||
+0 "1m"
|
||||
+1 ""
|
||||
+2 "0"
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
@End Analysis
|
||||
@Analysis: 1 0
|
||||
+2 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 2 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 3 0
|
||||
+0 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
@End Analysis
|
||||
@Analysis: 4 0
|
||||
+0 0 1 0 0 0 0 0 0 0
|
||||
+0 ""
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
LoadFile 0 ""
|
||||
SaveFile 0 ""
|
||||
@End Analysis
|
||||
@Analysis: 5 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
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|
||||
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|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 6 0
|
||||
+1
|
||||
+0 ""
|
||||
@End Analysis
|
||||
@Analysis: 7 0
|
||||
+0 0
|
||||
+0 ""
|
||||
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|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 8 0
|
||||
+0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 9 0
|
||||
+0 ""
|
||||
@End Analysis
|
||||
@Analysis: 10 0
|
||||
+0 0
|
||||
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|
||||
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|
||||
+2 ""
|
||||
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|
||||
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|
||||
+5 ""
|
||||
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|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 11 1
|
||||
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
+ 0 0 0 0 0 0 0 0 0
|
||||
@End Analysis
|
||||
@Analysis: 12 0
|
||||
+8946208 0
|
||||
@End Analysis
|
||||
@Analysis: 13 1
|
||||
+0 1 0 1
|
||||
@End Analysis
|
||||
@Analysis: 14 1
|
||||
+1 1 1 "*"
|
||||
@End Analysis
|
||||
@Analysis: 15 0
|
||||
@End Analysis
|
||||
@Analysis: 16 0
|
||||
+0 "0"
|
||||
+1 "0"
|
||||
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|
||||
@End Analysis
|
||||
@Analysis: 17 0
|
||||
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|
||||
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|
||||
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|
||||
+3 "-1"
|
||||
+4 "1"
|
||||
@End Analysis
|
Binary file not shown.
|
@ -0,0 +1,106 @@
|
|||
[DISPLAYS]
|
||||
BEGIN DISPLAY LAST SESSION
|
||||
ANALYSIS TRANSIENT_ANALYSIS
|
||||
SYMBOL ALWAYS
|
||||
TRACECOLORSCHEME NORMAL
|
||||
BEGIN ANAPLOT 1
|
||||
XBASE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT s
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
END XAXIS
|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
ACTIVE
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT V
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
BEGIN TRACE V(Vout)
|
||||
MARKERID 1
|
||||
END TRACE V(Vout)
|
||||
END YAXIS 1
|
||||
END ANAPLOT 1
|
||||
BEGIN ANAPLOT 2
|
||||
ACTIVE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT s
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
END XAXIS
|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
ACTIVE
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT V
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
BEGIN TRACE V(Vin)
|
||||
MARKERID 2
|
||||
END TRACE V(Vin)
|
||||
END YAXIS 1
|
||||
END ANAPLOT 2
|
||||
END DISPLAY LAST SESSION
|
||||
BEGIN DISPLAY LAST DISPLAY
|
||||
ANALYSIS TRANSIENT_ANALYSIS
|
||||
SYMBOL ALWAYS
|
||||
TRACECOLORSCHEME NORMAL
|
||||
BEGIN ANAPLOT 1
|
||||
ACTIVE
|
||||
XBASE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT s
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
END XAXIS
|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
ACTIVE
|
||||
RANGEFLAG NORANGE
|
||||
TYPE LINEAR
|
||||
UNIT
|
||||
END YAXIS 1
|
||||
END ANAPLOT 1
|
||||
END DISPLAY LAST DISPLAY
|
BIN
spice/ti/TLV70013_PSPICE_TRANS/TLV70013.DSN
Normal file
BIN
spice/ti/TLV70013_PSPICE_TRANS/TLV70013.DSN
Normal file
Binary file not shown.
BIN
spice/ti/TLV70013_PSPICE_TRANS/TLV70013.OLB
Normal file
BIN
spice/ti/TLV70013_PSPICE_TRANS/TLV70013.OLB
Normal file
Binary file not shown.
70
spice/ti/TLV70013_PSPICE_TRANS/TLV70013.lib
Normal file
70
spice/ti/TLV70013_PSPICE_TRANS/TLV70013.lib
Normal file
|
@ -0,0 +1,70 @@
|
|||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70013 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2011 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
|
||||
* Part: TLV70013
|
||||
* Date: 09/15/2011
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number:
|
||||
* EVM Users Guide:
|
||||
* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70013
|
||||
*$
|
||||
.SUBCKT TLV70013 IN GND EN OUT
|
||||
$CDNENCSTART
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70013
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70013_F1 1 2 3 4
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dc3ae7f242d93c2a62
|
||||
4f9bfd860debeaf27ecf225e6569dd2346b92e86e8aaa0ba6346aa19326e7599d5b99113bc2971da57e2c5aa808513703a70ec6c4fe6f448a1898c3447a6961c
|
||||
476007b7708ce3cd07bac0453cd873c21852d2bae2562872b9ef19aa8805d319125bb4087fc558681a9d982fdbafc20005489506b147170f4401399d6e036424
|
||||
$CDNENCFINISH
|
||||
.ends SCHEMATIC1_TLV70013_F1
|
||||
*$
|
||||
|
60
spice/ti/TLV70013_PSPICE_TRANS/TLV70013.opj
Normal file
60
spice/ti/TLV70013_PSPICE_TRANS/TLV70013.opj
Normal file
|
@ -0,0 +1,60 @@
|
|||
(ExpressProject "TLV70013"
|
||||
(ProjectVersion "19981106")
|
||||
(ProjectType "Analog or A/D Mixed Mode")
|
||||
(Folder "Design Resources"
|
||||
(Folder "Library")
|
||||
(NoModify)
|
||||
(File ".\tlv70013.dsn"
|
||||
(Type "Schematic Design"))
|
||||
(BuildFileAddedOrDeleted "x")
|
||||
(CompileFileAddedOrDeleted "x")
|
||||
(PSPICE_Regenerate_Netlist_Flag "FALSE"))
|
||||
(Folder "Outputs"
|
||||
(File ".\tlv70013-pspicefiles\schematic1\schematic1.net"
|
||||
(Type "Report")))
|
||||
(Folder "PSpice Resources"
|
||||
(Folder "Simulation Profiles"
|
||||
(ActiveProfile ".\tlv70013-pspicefiles\schematic1\trans.sim")
|
||||
(File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
|
||||
".\tlv70013-pspicefiles\schematic1\trans.sim"
|
||||
(DisplayName "SCHEMATIC1-trans")
|
||||
(Type "PSpice Profile")))
|
||||
(Folder "Model Libraries"
|
||||
(Sort User)
|
||||
(File ".\tlv70013.lib"
|
||||
(Type "PSpiceLibrary")
|
||||
(DisplayName ".\tlv70013.lib")))
|
||||
(Folder "Stimulus Files"
|
||||
(Sort User))
|
||||
(Folder "Include Files"
|
||||
(Sort User)))
|
||||
(DefaultLibraryBrowseDirectory "library\PSpice")
|
||||
(PartMRUSelector
|
||||
(TLV70013
|
||||
(FullPartName "TLV70013.Normal")
|
||||
(LibraryName
|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70013\RELEASE_TI\PSPICE\TLV70013_PSPICE_TRANS\TLV70013.OLB")
|
||||
(DeviceIndex "0")))
|
||||
(GlobalState
|
||||
(FileView
|
||||
(Path "Design Resources")
|
||||
(Path "Outputs"))
|
||||
(HierarchyView)
|
||||
(Doc
|
||||
(Type "COrCapturePMDoc")
|
||||
(Frame
|
||||
(Placement "44 0 1 -1 -1 -1 -1 0 200 0 432"))
|
||||
(Tab 0))
|
||||
(Doc
|
||||
(Type "COrSchematicDoc")
|
||||
(Frame
|
||||
(Placement "44 0 1 -1 -1 -1 -1 101 1246 29 638")
|
||||
(Scroll "-63 171")
|
||||
(Zoom "100")
|
||||
(Occurrence "/"))
|
||||
(Path
|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70013\RELEASE_TI\PSPICE\TLV70013_PSPICE_TRANS\TLV70013.DSN")
|
||||
(Schematic "SCHEMATIC1")
|
||||
(Page "PAGE1")))
|
||||
(LastUsedLibraryBrowseDirectory
|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70013\Release_TI\PSPICE\TLV70013_PSPICE_TRANS"))
|
|
@ -0,0 +1,137 @@
|
|||
@OrCAD Simulation Server Version: 1.0
|
||||
|
||||
@Settings: 0 1
|
||||
@General:
|
||||
ProfileName= "trans"
|
||||
ProfileFile= "trans.sim"
|
||||
Connectivity= "SCHEMATIC1.net"
|
||||
NetlistFile= "trans.cir"
|
||||
DataFile= "trans.dat"
|
||||
OutFile= "trans.out"
|
||||
Notes=
|
||||
@#$BEGINNOTES
|
||||
@#$ENDNOTES
|
||||
@End General
|
||||
@Analysis: 0 1
|
||||
+0 0 0 0
|
||||
+0 "1m"
|
||||
+1 ""
|
||||
+2 "0"
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
@End Analysis
|
||||
@Analysis: 1 0
|
||||
+2 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 2 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 3 0
|
||||
+0 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
@End Analysis
|
||||
@Analysis: 4 0
|
||||
+0 0 1 0 0 0 0 0 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
LoadFile 0 ""
|
||||
SaveFile 0 ""
|
||||
@End Analysis
|
||||
@Analysis: 5 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 6 0
|
||||
+1
|
||||
+0 ""
|
||||
@End Analysis
|
||||
@Analysis: 7 0
|
||||
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|
||||
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|
||||
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|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 8 0
|
||||
+0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
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|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 9 0
|
||||
+0 ""
|
||||
@End Analysis
|
||||
@Analysis: 10 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
@End Analysis
|
||||
@Analysis: 11 1
|
||||
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
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|
||||
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|
||||
@Analysis: 12 0
|
||||
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|
||||
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|
||||
@Analysis: 13 1
|
||||
+0 1 1 1
|
||||
@End Analysis
|
||||
@Analysis: 14 1
|
||||
+1 1 1 "*"
|
||||
@End Analysis
|
||||
@Analysis: 15 0
|
||||
@End Analysis
|
||||
@Analysis: 16 0
|
||||
+0 "0"
|
||||
+1 "0"
|
||||
+2 "chkpt_default, , ,"
|
||||
@End Analysis
|
||||
@Analysis: 17 0
|
||||
+0 "-1"
|
||||
+1 ""
|
||||
+2 "-1"
|
||||
+3 "-1"
|
||||
+4 "1"
|
||||
@End Analysis
|
Binary file not shown.
|
@ -0,0 +1,76 @@
|
|||
[DISPLAYS]
|
||||
BEGIN DISPLAY LAST SESSION
|
||||
ANALYSIS TRANSIENT_ANALYSIS
|
||||
SYMBOL ALWAYS
|
||||
TRACECOLORSCHEME NORMAL
|
||||
BEGIN ANAPLOT 1
|
||||
XBASE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT s
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
END XAXIS
|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
ACTIVE
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT V
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
BEGIN TRACE V(Vout)
|
||||
MARKERID 1
|
||||
END TRACE V(Vout)
|
||||
END YAXIS 1
|
||||
END ANAPLOT 1
|
||||
BEGIN ANAPLOT 2
|
||||
ACTIVE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT s
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
END XAXIS
|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
ACTIVE
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT V
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
BEGIN TRACE V(Vin)
|
||||
MARKERID 2
|
||||
END TRACE V(Vin)
|
||||
END YAXIS 1
|
||||
END ANAPLOT 2
|
||||
END DISPLAY LAST SESSION
|
BIN
spice/ti/TLV70015_PSPICE_TRANS/TLV70015.DSN
Normal file
BIN
spice/ti/TLV70015_PSPICE_TRANS/TLV70015.DSN
Normal file
Binary file not shown.
BIN
spice/ti/TLV70015_PSPICE_TRANS/TLV70015.OLB
Normal file
BIN
spice/ti/TLV70015_PSPICE_TRANS/TLV70015.OLB
Normal file
Binary file not shown.
70
spice/ti/TLV70015_PSPICE_TRANS/TLV70015.lib
Normal file
70
spice/ti/TLV70015_PSPICE_TRANS/TLV70015.lib
Normal file
|
@ -0,0 +1,70 @@
|
|||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70015 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2011 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
|
||||
* Part: TLV70015
|
||||
* Date: 04/05/2011
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number:
|
||||
* EVM Users Guide:
|
||||
* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70015
|
||||
*$
|
||||
.SUBCKT TLV70015 IN GND EN OUT
|
||||
$CDNENCSTART
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70015
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70015_F1 1 2 3 4
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dc5c60773b1239b886
|
||||
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|
||||
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|
||||
$CDNENCFINISH
|
||||
.ends SCHEMATIC1_TLV70015_F1
|
||||
*$
|
||||
|
60
spice/ti/TLV70015_PSPICE_TRANS/TLV70015.opj
Normal file
60
spice/ti/TLV70015_PSPICE_TRANS/TLV70015.opj
Normal file
|
@ -0,0 +1,60 @@
|
|||
(ExpressProject "TLV70015"
|
||||
(ProjectVersion "19981106")
|
||||
(ProjectType "Analog or A/D Mixed Mode")
|
||||
(Folder "Design Resources"
|
||||
(Folder "Library")
|
||||
(NoModify)
|
||||
(File ".\tlv70015.dsn"
|
||||
(Type "Schematic Design"))
|
||||
(BuildFileAddedOrDeleted "x")
|
||||
(CompileFileAddedOrDeleted "x")
|
||||
(PSPICE_Regenerate_Netlist_Flag "FALSE"))
|
||||
(Folder "Outputs"
|
||||
(File ".\tlv70015-pspicefiles\schematic1\schematic1.net"
|
||||
(Type "Report")))
|
||||
(Folder "PSpice Resources"
|
||||
(Folder "Simulation Profiles"
|
||||
(ActiveProfile ".\tlv70015-pspicefiles\schematic1\trans.sim")
|
||||
(File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
|
||||
".\tlv70015-pspicefiles\schematic1\trans.sim"
|
||||
(DisplayName "SCHEMATIC1-trans")
|
||||
(Type "PSpice Profile")))
|
||||
(Folder "Model Libraries"
|
||||
(Sort User)
|
||||
(File ".\tlv70015.lib"
|
||||
(Type "PSpiceLibrary")
|
||||
(DisplayName ".\tlv70015.lib")))
|
||||
(Folder "Stimulus Files"
|
||||
(Sort User))
|
||||
(Folder "Include Files"
|
||||
(Sort User)))
|
||||
(DefaultLibraryBrowseDirectory "library\PSpice")
|
||||
(PartMRUSelector
|
||||
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|
||||
(FullPartName "TLV70015.Normal")
|
||||
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|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70015\RELEASE_TI\PSPICE\TLV70015_PSPICE_TRANS\TLV70015.OLB")
|
||||
(DeviceIndex "0")))
|
||||
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|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70015\Release_TI\PSPICE\TLV70015_PSPICE_TRANS")
|
||||
(GlobalState
|
||||
(FileView
|
||||
(Path "Design Resources")
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||||
(Path "Outputs"))
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||||
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|
||||
(Doc
|
||||
(Type "COrCapturePMDoc")
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||||
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|
||||
(Placement "44 0 1 -1 -1 -1 -1 0 200 0 367"))
|
||||
(Tab 0))
|
||||
(Doc
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||||
(Type "COrSchematicDoc")
|
||||
(Frame
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||||
(Placement "44 0 1 -1 -1 -1 -1 60 1239 70 571")
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||||
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||||
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||||
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(Page "PAGE1"))))
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@OrCAD Simulation Server Version: 1.0
|
||||
|
||||
@Settings: 0 1
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||||
@General:
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||||
ProfileName= "trans"
|
||||
ProfileFile= "trans.sim"
|
||||
Connectivity= "SCHEMATIC1.net"
|
||||
NetlistFile= "trans.cir"
|
||||
DataFile= "trans.dat"
|
||||
OutFile= "trans.out"
|
||||
Notes=
|
||||
@#$BEGINNOTES
|
||||
@#$ENDNOTES
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
Binary file not shown.
|
@ -0,0 +1,76 @@
|
|||
[DISPLAYS]
|
||||
BEGIN DISPLAY LAST SESSION
|
||||
ANALYSIS TRANSIENT_ANALYSIS
|
||||
SYMBOL ALWAYS
|
||||
TRACECOLORSCHEME NORMAL
|
||||
BEGIN ANAPLOT 1
|
||||
XBASE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
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|
||||
UNIT s
|
||||
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|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
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|
||||
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|
||||
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|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
ACTIVE
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT V
|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
MARKERID 1
|
||||
END TRACE V(Vout)
|
||||
END YAXIS 1
|
||||
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|
||||
BEGIN ANAPLOT 2
|
||||
ACTIVE
|
||||
BEGIN XAXIS
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
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||||
MAJORSTYLE LINES
|
||||
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|
||||
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|
||||
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|
||||
END GRIDS
|
||||
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|
||||
BEGIN YAXIS 1
|
||||
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|
||||
ACTIVE
|
||||
RANGEFLAG AUTO
|
||||
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|
||||
UNIT V
|
||||
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|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
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|
||||
MINORSTYLE LINES
|
||||
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|
||||
END GRIDS
|
||||
BEGIN TRACE V(Vin)
|
||||
MARKERID 2
|
||||
END TRACE V(Vin)
|
||||
END YAXIS 1
|
||||
END ANAPLOT 2
|
||||
END DISPLAY LAST SESSION
|
BIN
spice/ti/TLV70018_PSPICE_TRANS/TLV70018.DSN
Normal file
BIN
spice/ti/TLV70018_PSPICE_TRANS/TLV70018.DSN
Normal file
Binary file not shown.
BIN
spice/ti/TLV70018_PSPICE_TRANS/TLV70018.OLB
Normal file
BIN
spice/ti/TLV70018_PSPICE_TRANS/TLV70018.OLB
Normal file
Binary file not shown.
70
spice/ti/TLV70018_PSPICE_TRANS/TLV70018.lib
Normal file
70
spice/ti/TLV70018_PSPICE_TRANS/TLV70018.lib
Normal file
|
@ -0,0 +1,70 @@
|
|||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70018 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2011 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
|
||||
* Part: TLV70018
|
||||
* Date: 04/05/2011
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number: TLV70018EVM-503
|
||||
* EVM Users Guide: SLUU391 - DECEMBER 2009
|
||||
* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70018
|
||||
*$
|
||||
.SUBCKT TLV70018 IN GND EN OUT
|
||||
$CDNENCSTART
|
||||
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||||
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||||
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|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70018
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70018_F1 1 2 3 4
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dca4d30e3523d8c2f5
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||||
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|
||||
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|
||||
$CDNENCFINISH
|
||||
.ends SCHEMATIC1_TLV70018_F1
|
||||
*$
|
||||
|
60
spice/ti/TLV70018_PSPICE_TRANS/TLV70018.opj
Normal file
60
spice/ti/TLV70018_PSPICE_TRANS/TLV70018.opj
Normal file
|
@ -0,0 +1,60 @@
|
|||
(ExpressProject "TLV70018"
|
||||
(ProjectVersion "19981106")
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(Folder "Simulation Profiles"
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(Folder "Model Libraries"
|
||||
(Sort User)
|
||||
(File ".\tlv70018.lib"
|
||||
(Type "PSpiceLibrary")
|
||||
(DisplayName ".\tlv70018.lib")))
|
||||
(Folder "Stimulus Files"
|
||||
(Sort User))
|
||||
(Folder "Include Files"
|
||||
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|
||||
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|
||||
(PartMRUSelector
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|||
[DISPLAYS]
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||||
BEGIN DISPLAY LAST SESSION
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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BIN
spice/ti/TLV70019_PSPICE_TRANS/TLV70019.DSN
Normal file
BIN
spice/ti/TLV70019_PSPICE_TRANS/TLV70019.DSN
Normal file
Binary file not shown.
BIN
spice/ti/TLV70019_PSPICE_TRANS/TLV70019.OLB
Normal file
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spice/ti/TLV70019_PSPICE_TRANS/TLV70019.OLB
Normal file
Binary file not shown.
70
spice/ti/TLV70019_PSPICE_TRANS/TLV70019.lib
Normal file
70
spice/ti/TLV70019_PSPICE_TRANS/TLV70019.lib
Normal file
|
@ -0,0 +1,70 @@
|
|||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70019 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2012 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
|
||||
* Part: TLV70019
|
||||
* Date: 01/17/2012
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number:
|
||||
* EVM Users Guide:
|
||||
* Datasheet: SLVSA00C - SEPTEMBER 2009 - REVISED JULY 2011
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70019
|
||||
*$
|
||||
.SUBCKT TLV70019 IN GND EN OUT
|
||||
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||||
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|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70019
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70019_F1 1 2 3 4
|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
*$
|
||||
|
60
spice/ti/TLV70019_PSPICE_TRANS/TLV70019.opj
Normal file
60
spice/ti/TLV70019_PSPICE_TRANS/TLV70019.opj
Normal file
|
@ -0,0 +1,60 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
|
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|
|||
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||||
|
||||
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||||
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|
||||
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|
||||
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|
||||
Connectivity= "SCHEMATIC1.net"
|
||||
NetlistFile= "trans.cir"
|
||||
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|
||||
OutFile= "trans.out"
|
||||
Notes=
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
SaveFile 0 ""
|
||||
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|
||||
@Analysis: 5 0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
@Analysis: 8 0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
Binary file not shown.
|
@ -0,0 +1,76 @@
|
|||
[DISPLAYS]
|
||||
BEGIN DISPLAY LAST SESSION
|
||||
ANALYSIS TRANSIENT_ANALYSIS
|
||||
SYMBOL ALWAYS
|
||||
TRACECOLORSCHEME NORMAL
|
||||
BEGIN ANAPLOT 1
|
||||
XBASE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
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||||
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|
||||
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|
||||
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|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
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|
||||
RANGEFLAG AUTO
|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
MARKERID 1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
ACTIVE
|
||||
BEGIN XAXIS
|
||||
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|
||||
RANGEFLAG AUTO
|
||||
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|
||||
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|
||||
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|
||||
AUTOMATIC
|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
END TRACE V(Vin)
|
||||
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|
||||
END ANAPLOT 2
|
||||
END DISPLAY LAST SESSION
|
BIN
spice/ti/TLV70022_PSPICE_TRANS/TLV70022.DSN
Normal file
BIN
spice/ti/TLV70022_PSPICE_TRANS/TLV70022.DSN
Normal file
Binary file not shown.
BIN
spice/ti/TLV70022_PSPICE_TRANS/TLV70022.OLB
Normal file
BIN
spice/ti/TLV70022_PSPICE_TRANS/TLV70022.OLB
Normal file
Binary file not shown.
70
spice/ti/TLV70022_PSPICE_TRANS/TLV70022.lib
Normal file
70
spice/ti/TLV70022_PSPICE_TRANS/TLV70022.lib
Normal file
|
@ -0,0 +1,70 @@
|
|||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70022 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2012 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
|
||||
* Part: TLV70022
|
||||
* Date: 01/17/2012
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number:
|
||||
* EVM Users Guide:
|
||||
* Datasheet: SLVSA00C - SEPTEMBER 2009 - REVISED JULY 2011
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70022
|
||||
*$
|
||||
.SUBCKT TLV70022 IN GND EN OUT
|
||||
$CDNENCSTART
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70022
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70022_F1 1 2 3 4
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dcd39171259953cbf3
|
||||
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|
||||
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|
||||
$CDNENCFINISH
|
||||
.ends SCHEMATIC1_TLV70022_F1
|
||||
*$
|
||||
|
60
spice/ti/TLV70022_PSPICE_TRANS/TLV70022.opj
Normal file
60
spice/ti/TLV70022_PSPICE_TRANS/TLV70022.opj
Normal file
|
@ -0,0 +1,60 @@
|
|||
(ExpressProject "TLV70022"
|
||||
(ProjectVersion "19981106")
|
||||
(ProjectType "Analog or A/D Mixed Mode")
|
||||
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|
||||
(Folder "Library")
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(File ".\tlv70022-pspicefiles\schematic1\schematic1.net"
|
||||
(Type "Report")))
|
||||
(Folder "PSpice Resources"
|
||||
(Folder "Simulation Profiles"
|
||||
(ActiveProfile ".\tlv70022-pspicefiles\schematic1\trans.sim")
|
||||
(File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
|
||||
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|
||||
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|
||||
(Type "PSpice Profile")))
|
||||
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|
||||
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|
||||
(File ".\tlv70022.lib"
|
||||
(Type "PSpiceLibrary")
|
||||
(DisplayName ".\tlv70022.lib")))
|
||||
(Folder "Stimulus Files"
|
||||
(Sort User))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(DeviceIndex "0")))
|
||||
(LastUsedLibraryBrowseDirectory
|
||||
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|
||||
(GlobalState
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
|
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|
|||
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|
||||
|
||||
@Settings: 0 1
|
||||
@General:
|
||||
ProfileName= "trans"
|
||||
ProfileFile= "trans.sim"
|
||||
Connectivity= "SCHEMATIC1.net"
|
||||
NetlistFile= "trans.cir"
|
||||
DataFile= "trans.dat"
|
||||
OutFile= "trans.out"
|
||||
Notes=
|
||||
@#$BEGINNOTES
|
||||
@#$ENDNOTES
|
||||
@End General
|
||||
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|
||||
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||||
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|
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
@Analysis: 13 1
|
||||
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|
||||
@End Analysis
|
||||
@Analysis: 14 1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
+0 "0"
|
||||
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|
||||
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|
||||
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|
||||
@Analysis: 17 0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
Binary file not shown.
|
@ -0,0 +1,76 @@
|
|||
[DISPLAYS]
|
||||
BEGIN DISPLAY LAST SESSION
|
||||
ANALYSIS TRANSIENT_ANALYSIS
|
||||
SYMBOL ALWAYS
|
||||
TRACECOLORSCHEME NORMAL
|
||||
BEGIN ANAPLOT 1
|
||||
XBASE
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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BIN
spice/ti/TLV70025_PSPICE_TRANS/TLV70025.DSN
Normal file
BIN
spice/ti/TLV70025_PSPICE_TRANS/TLV70025.DSN
Normal file
Binary file not shown.
BIN
spice/ti/TLV70025_PSPICE_TRANS/TLV70025.OLB
Normal file
BIN
spice/ti/TLV70025_PSPICE_TRANS/TLV70025.OLB
Normal file
Binary file not shown.
70
spice/ti/TLV70025_PSPICE_TRANS/TLV70025.lib
Normal file
70
spice/ti/TLV70025_PSPICE_TRANS/TLV70025.lib
Normal file
|
@ -0,0 +1,70 @@
|
|||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70025 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2011 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
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|
||||
* Part: TLV70025
|
||||
* Date: 04/05/2011
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number:
|
||||
* EVM Users Guide:
|
||||
* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70025
|
||||
*$
|
||||
.SUBCKT TLV70025 IN GND EN OUT
|
||||
$CDNENCSTART
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70025
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70025_F1 1 2 3 4
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dcce703e6b176617a3
|
||||
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|
||||
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|
||||
$CDNENCFINISH
|
||||
.ends SCHEMATIC1_TLV70025_F1
|
||||
*$
|
||||
|
60
spice/ti/TLV70025_PSPICE_TRANS/TLV70025.opj
Normal file
60
spice/ti/TLV70025_PSPICE_TRANS/TLV70025.opj
Normal file
|
@ -0,0 +1,60 @@
|
|||
(ExpressProject "TLV70025"
|
||||
(ProjectVersion "19981106")
|
||||
(ProjectType "Analog or A/D Mixed Mode")
|
||||
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|
||||
(Folder "Library")
|
||||
(NoModify)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(Type "Report")))
|
||||
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|
||||
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|
||||
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|
||||
(File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
|
||||
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|
||||
(DisplayName "SCHEMATIC1-trans")
|
||||
(Type "PSpice Profile")))
|
||||
(Folder "Model Libraries"
|
||||
(Sort User)
|
||||
(File ".\tlv70025.lib"
|
||||
(Type "PSpiceLibrary")
|
||||
(DisplayName ".\tlv70025.lib")))
|
||||
(Folder "Stimulus Files"
|
||||
(Sort User))
|
||||
(Folder "Include Files"
|
||||
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|
||||
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|
||||
(PartMRUSelector
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(DeviceIndex "0")))
|
||||
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|
||||
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|
||||
(GlobalState
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
|
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|
|||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
Connectivity= "SCHEMATIC1.net"
|
||||
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|
||||
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|
||||
OutFile= "trans.out"
|
||||
Notes=
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
Binary file not shown.
|
@ -0,0 +1,76 @@
|
|||
[DISPLAYS]
|
||||
BEGIN DISPLAY LAST SESSION
|
||||
ANALYSIS TRANSIENT_ANALYSIS
|
||||
SYMBOL ALWAYS
|
||||
TRACECOLORSCHEME NORMAL
|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
ACTIVE
|
||||
BEGIN XAXIS
|
||||
XAXISUSERNAME 0 (null)
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT s
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
END XAXIS
|
||||
BEGIN YAXIS 1
|
||||
YAXISSIDE LEFT
|
||||
ACTIVE
|
||||
RANGEFLAG AUTO
|
||||
TYPE LINEAR
|
||||
UNIT V
|
||||
BEGIN GRIDS
|
||||
AUTOMATIC
|
||||
MAJORNUMBERS
|
||||
MAJORSTYLE LINES
|
||||
MAJORPATTERN SOLID
|
||||
MINORSTYLE LINES
|
||||
MINORPATTERN DOT
|
||||
END GRIDS
|
||||
BEGIN TRACE V(Vin)
|
||||
MARKERID 2
|
||||
END TRACE V(Vin)
|
||||
END YAXIS 1
|
||||
END ANAPLOT 2
|
||||
END DISPLAY LAST SESSION
|
BIN
spice/ti/TLV70028_PSPICE_TRANS/TLV70028.DSN
Normal file
BIN
spice/ti/TLV70028_PSPICE_TRANS/TLV70028.DSN
Normal file
Binary file not shown.
BIN
spice/ti/TLV70028_PSPICE_TRANS/TLV70028.OLB
Normal file
BIN
spice/ti/TLV70028_PSPICE_TRANS/TLV70028.OLB
Normal file
Binary file not shown.
70
spice/ti/TLV70028_PSPICE_TRANS/TLV70028.lib
Normal file
70
spice/ti/TLV70028_PSPICE_TRANS/TLV70028.lib
Normal file
|
@ -0,0 +1,70 @@
|
|||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70028 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2011 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
|
||||
* Part: TLV70028
|
||||
* Date: 04/05/2011
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number: TLV70028EVM-463
|
||||
* EVM Users Guide: SLUU390 - DECEMBER 2009
|
||||
* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70028
|
||||
*$
|
||||
.SUBCKT TLV70028 IN GND EN OUT
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dc3b4270786a99dc40
|
||||
259e22a51c65bc4de0b26eee9119947a4e552c8ab90b219aec966d86a5abd21118909a58bd8b769021fde3e7c93c43a3373688de6049867ad38aff4e12555a5d
|
||||
af1dff2e8151d1b37a313a02b15a43f34e552c8ab90b219aec966d86a5abd211ade02a6c3e64e287d183594cbc7391122a931f55ee8d47b0d3b55e518a88efc0
|
||||
259e22a51c65bc4d1d2a01a58a1857da2531ce9df5eb0603c921153da52548bea81c0471b1ec8a76f34d311b7ac26f46c1f60d7ea22f9ce9e17b303aa268cbf3
|
||||
259e22a51c65bc4de3775edbdc4c44224e552c8ab90b219aec966d86a5abd211d9ae151f53d140dbc88e473ce12bfd976adb81ead9e83b514efc3e7368246b8d
|
||||
259e22a51c65bc4daa68cb129fcd7905239bdbe658d21d004e837baae6a4ac88ec966d86a5abd2117ef5870a5e3da03d727a1739f564646574fb7cf2e7c9f235
|
||||
af1dff2e8151d1b39ea14394c5d6640944f91394b9d9e84610977954546a053daa7d9df51dd4bff343e100eee5b305a94c49b18e65b20125934de75109b863ae
|
||||
3fc4c23aa5b6596685f1f86d3ff0fc2c006c3fb97196ad7671cf3cb4f0f12316644126c9831a96bd6dff3c5fd9103c1ff4021ececac8e1dea4b27f5dcb67880d
|
||||
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|
||||
af1dff2e8151d1b39ea14394c5d66409f5687491f31f292410977954546a053d5e5994701915d9f59c064bf94d8ce6078492e52ca990713779eccb7eaf03f4e4
|
||||
97273dca314e0f137158f7066bb1acc8e884561dc52031d166f9df056a16ed558b31c7db94f482141568e093b3e225349b997d4d4d35525a490dd8178ed72c4f
|
||||
427c310c1c1f6b42fcdff44f046d00717e012483319edfad3d1a96345bca769f156308c046a85546e73070a45f1d549c2536e4b177c8ae7af95da0c89d6e7148
|
||||
af1dff2e8151d1b39ea14394c5d6640905f06f9213ce83ba10977954546a053d5e5994701915d9f5ecbee74170ca80188492e52ca990713779eccb7eaf03f4e4
|
||||
a96c53d84a6e3a2c0ca0a1434385d0e92b81e10e996e19ac294ff995b8f67f652536e4b177c8ae7a512e8302d066867f0bbea32fb03732f08d1aa0cd2f3d6541
|
||||
cd080d6014ef79b45b21fcbb5127d82b1568e093b3e225349b997d4d4d35525a5d4f30377f1ec477cc9eec11790f4cf73d0fd73bc55bad0757b2d319b8193193
|
||||
ce1e320d9877b21bd183594cbc739112a7d24ab7ae54f3c7cb82e1066e82af78e73070a45f1d549c2536e4b177c8ae7a512e8302d066867fb0b04c37ba291cd7
|
||||
259e22a51c65bc4daa68cb129fcd7905cd9f9b0fe66d8ad14e837baae6a4ac88ec966d86a5abd2115ff6f42c959550fbd48c1d14d1b0c61c74fb7cf2e7c9f235
|
||||
259e22a51c65bc4dc224f6af4154f6094e552c8ab90b219a4def2f1d34b72f6bc76c6f59598c925ed183594cbc739112b286dd1121d2a6d23c33417d989f4d2c
|
||||
79b347c5b85360ef2fb6bff03cdb9f494e552c8ab90b219aec966d86a5abd211d9ae151f53d140db68bc7b4cd898b0136adb81ead9e83b514efc3e7368246b8d
|
||||
79b347c5b85360ef9447b0f3b458d2ed4e552c8ab90b219aec966d86a5abd21103713b4f43695ba7b36ef5dda9de6f52ac0bbcb25a375ea3a3326a35d52f6cdd
|
||||
259e22a51c65bc4db64af790a1852beb4e552c8ab90b219aec966d86a5abd21118909a58bd8b7690b36ef5dda9de6f52aab152db1ef0a24cb22655deab6bd6ae
|
||||
d153893f36515c502605855cbd77464f0e687f9469beafda61dfeef3e3017a78fc8a520169f0e78fa2c46dfbe29d75678e95fdd389b2972f9e301436d16375b1
|
||||
d183594cbc739112ccefcc2bf8692e3b2536e4b177c8ae7a512e8302d066867f0bbea32fb03732f063ba1dd3fd2a6454f0308a077022a541a4b423ad239e09e5
|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70028
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70028_F1 1 2 3 4
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dc3b4270786a99dc40
|
||||
4f9bfd860debeaf22605855cbd77464f46b92e86e8aaa0ba6346aa19326e759928b95d58561b011157e2c5aa808513703cd6545aefc0c88a9482a2dde2ad285f
|
||||
476007b7708ce3cdd34f2cf8cf965ad61852d2bae2562872b9ef19aa8805d3194c17cf64cc24cbc427c8b8df024c46f1257f46957cca70cf36be422afcebe4ac
|
||||
$CDNENCFINISH
|
||||
.ends SCHEMATIC1_TLV70028_F1
|
||||
*$
|
||||
|
60
spice/ti/TLV70028_PSPICE_TRANS/TLV70028.opj
Normal file
60
spice/ti/TLV70028_PSPICE_TRANS/TLV70028.opj
Normal file
|
@ -0,0 +1,60 @@
|
|||
(ExpressProject "TLV70028"
|
||||
(ProjectVersion "19981106")
|
||||
(ProjectType "Analog or A/D Mixed Mode")
|
||||
(Folder "Design Resources"
|
||||
(Folder "Library")
|
||||
(NoModify)
|
||||
(File ".\tlv70028.dsn"
|
||||
(Type "Schematic Design"))
|
||||
(BuildFileAddedOrDeleted "x")
|
||||
(CompileFileAddedOrDeleted "x")
|
||||
(PSPICE_Regenerate_Netlist_Flag "FALSE"))
|
||||
(Folder "Outputs"
|
||||
(File ".\tlv70028-pspicefiles\schematic1\schematic1.net"
|
||||
(Type "Report")))
|
||||
(Folder "PSpice Resources"
|
||||
(Folder "Simulation Profiles"
|
||||
(ActiveProfile ".\tlv70028-pspicefiles\schematic1\trans.sim")
|
||||
(File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
|
||||
".\tlv70028-pspicefiles\schematic1\trans.sim"
|
||||
(DisplayName "SCHEMATIC1-trans")
|
||||
(Type "PSpice Profile")))
|
||||
(Folder "Model Libraries"
|
||||
(Sort User)
|
||||
(File ".\tlv70028.lib"
|
||||
(Type "PSpiceLibrary")
|
||||
(DisplayName ".\tlv70028.lib")))
|
||||
(Folder "Stimulus Files"
|
||||
(Sort User))
|
||||
(Folder "Include Files"
|
||||
(Sort User)))
|
||||
(DefaultLibraryBrowseDirectory "library\PSpice")
|
||||
(PartMRUSelector
|
||||
(TLV70028
|
||||
(FullPartName "TLV70028.Normal")
|
||||
(LibraryName
|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70028\RELEASE_TI\PSPICE\TLV70028_PSPICE_TRANS\TLV70028.OLB")
|
||||
(DeviceIndex "0")))
|
||||
(LastUsedLibraryBrowseDirectory
|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70028\Release_TI\PSPICE\TLV70028_PSPICE_TRANS")
|
||||
(GlobalState
|
||||
(FileView
|
||||
(Path "Design Resources")
|
||||
(Path "Outputs"))
|
||||
(HierarchyView)
|
||||
(Doc
|
||||
(Type "COrCapturePMDoc")
|
||||
(Frame
|
||||
(Placement "44 0 1 -1 -1 -1 -1 0 200 0 367"))
|
||||
(Tab 0))
|
||||
(Doc
|
||||
(Type "COrSchematicDoc")
|
||||
(Frame
|
||||
(Placement "44 0 1 -1 -1 -1 -1 127 1264 42 507")
|
||||
(Scroll "-59 0")
|
||||
(Zoom "100")
|
||||
(Occurrence "/"))
|
||||
(Path
|
||||
"C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70028\RELEASE_TI\PSPICE\TLV70028_PSPICE_TRANS\TLV70028.DSN")
|
||||
(Schematic "SCHEMATIC1")
|
||||
(Page "PAGE1"))))
|
|
@ -0,0 +1,137 @@
|
|||
@OrCAD Simulation Server Version: 1.0
|
||||
|
||||
@Settings: 0 1
|
||||
@General:
|
||||
ProfileName= "trans"
|
||||
ProfileFile= "trans.sim"
|
||||
Connectivity= "SCHEMATIC1.net"
|
||||
NetlistFile= "trans.cir"
|
||||
DataFile= "trans.dat"
|
||||
OutFile= "trans.out"
|
||||
Notes=
|
||||
@#$BEGINNOTES
|
||||
@#$ENDNOTES
|
||||
@End General
|
||||
@Analysis: 0 1
|
||||
+0 0 0 0
|
||||
+0 "1m"
|
||||
+1 ""
|
||||
+2 "0"
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
@End Analysis
|
||||
@Analysis: 1 0
|
||||
+2 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 2 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
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|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 3 0
|
||||
+0 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
@End Analysis
|
||||
@Analysis: 4 0
|
||||
+0 0 1 0 0 0 0 0 0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
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|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
LoadFile 0 ""
|
||||
SaveFile 0 ""
|
||||
@End Analysis
|
||||
@Analysis: 5 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 6 0
|
||||
+1
|
||||
+0 ""
|
||||
@End Analysis
|
||||
@Analysis: 7 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 8 0
|
||||
+0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
@End Analysis
|
||||
@Analysis: 9 0
|
||||
+0 ""
|
||||
@End Analysis
|
||||
@Analysis: 10 0
|
||||
+0 0
|
||||
+0 ""
|
||||
+1 ""
|
||||
+2 ""
|
||||
+3 ""
|
||||
+4 ""
|
||||
+5 ""
|
||||
+6 ""
|
||||
+7 ""
|
||||
@End Analysis
|
||||
@Analysis: 11 1
|
||||
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
+ 0 0 0 0 0 0 0 0 0
|
||||
@End Analysis
|
||||
@Analysis: 12 0
|
||||
+2236960 0
|
||||
@End Analysis
|
||||
@Analysis: 13 1
|
||||
+0 1 1 1
|
||||
@End Analysis
|
||||
@Analysis: 14 1
|
||||
+1 1 1 "*"
|
||||
@End Analysis
|
||||
@Analysis: 15 0
|
||||
@End Analysis
|
||||
@Analysis: 16 0
|
||||
+0 "0"
|
||||
+1 "0"
|
||||
+2 "chkpt_default, , ,"
|
||||
@End Analysis
|
||||
@Analysis: 17 0
|
||||
+0 "-1"
|
||||
+1 ""
|
||||
+2 "-1"
|
||||
+3 "-1"
|
||||
+4 "1"
|
||||
@End Analysis
|
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user