add footprint for Bourns PVG3A series trim pot

.vscode/extensions.json

@@ -0,0 +1,5 @@
+{
+    "recommendations": [
+        "xuanli.spice"
+    ]
+}

common.pretty/2466267-1.kicad_mod

@@ -0,0 +1,222 @@
+(footprint "2466267-1"
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(descr "Connector, Coax, BNC, Right Angle")
+	(property "Reference" "REF**"
+		(at 0 -6.35 0)
+		(unlocked yes)
+		(layer "F.SilkS")
+		(uuid "22b1b89c-729a-4453-a910-e62ebbc1d2d7")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Value" "2466267-1"
+		(at 0 1.27 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "12141e7d-84d0-4113-a369-6f106107aabb")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "8ff17f48-5d19-4ece-bc7a-a4bc598cf65e")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "9560e7cb-ebf9-4a56-b9c4-d28f299dc327")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "2229a43b-9428-4e76-9822-ece452ef15e0")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr through_hole)
+	(fp_arc
+		(start -5.079999 2.54)
+		(mid -5.679612 0)
+		(end -5.079999 -2.54)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "a0aecd3d-42cd-47b7-bcaf-94906c439fc0")
+	)
+	(fp_arc
+		(start -2.54 -5.079999)
+		(mid 0 -5.679612)
+		(end 2.54 -5.079999)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "b28cb087-0d7a-49b9-b277-22539b7330a1")
+	)
+	(fp_arc
+		(start 2.54 5.079999)
+		(mid 0 5.679612)
+		(end -2.54 5.079999)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "7c866bff-d084-473c-bf50-aad3bd8c7d6a")
+	)
+	(fp_arc
+		(start 5.079999 -2.54)
+		(mid 5.679612 0)
+		(end 5.079999 2.54)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "36bc17ba-61fb-4e2f-a147-1079b7e57e0e")
+	)
+	(fp_line
+		(start -22.5 -5)
+		(end -22.5 5)
+		(stroke
+			(width 0.127)
+			(type default)
+		)
+		(layer "F.Fab")
+		(uuid "8982185a-e2f2-4cc1-97b6-7e663e6c003f")
+	)
+	(fp_line
+		(start -22.5 -5)
+		(end -1.651 -5)
+		(stroke
+			(width 0.127)
+			(type default)
+		)
+		(layer "F.Fab")
+		(uuid "ff060678-a997-4515-ad4e-10977b387f44")
+	)
+	(fp_line
+		(start -22.5 5)
+		(end -1.651 5)
+		(stroke
+			(width 0.127)
+			(type default)
+		)
+		(layer "F.Fab")
+		(uuid "26c92594-184a-4372-a44d-1737fd5f6a9f")
+	)
+	(fp_circle
+		(center 0 0)
+		(end 5.25 0)
+		(stroke
+			(width 0.127)
+			(type default)
+		)
+		(fill none)
+		(layer "F.Fab")
+		(uuid "8be8be71-c19e-4ee4-80f5-87da9e7f45a0")
+	)
+	(fp_text user "${REFERENCE}"
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "4f4e5a85-ce6f-42ab-a612-cd5667d624d4")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(pad "0" thru_hole circle
+		(at -3.3 -3.3)
+		(size 3.302 3.302)
+		(drill 2.11)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "4f7cb7e9-7c97-41f2-adfb-d9be05f5b568")
+	)
+	(pad "0" thru_hole circle
+		(at -3.3 3.3)
+		(size 3.302 3.302)
+		(drill 2.11)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "0af765cf-0828-462b-9d65-8b35998515e2")
+	)
+	(pad "0" thru_hole circle
+		(at 3.3 -3.3)
+		(size 3.302 3.302)
+		(drill 2.11)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "1e7dd8b3-7bab-4f2c-bf0e-9d91c4c25e8f")
+	)
+	(pad "0" thru_hole circle
+		(at 3.3 3.3)
+		(size 3.302 3.302)
+		(drill 2.11)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "73d6f4db-dff6-4ec7-a5f1-ae9262249f39")
+	)
+	(pad "1" thru_hole circle
+		(at 0 0)
+		(size 2.032 2.032)
+		(drill 1.17)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "ccd825d3-9427-4518-9039-89986996588f")
+	)
+	(model "${KIPRJMOD}/common_libraries/common.pretty/step/TE_2466267-1.step"
+		(offset
+			(xyz -22.9 0 6.096)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+)

common.pretty/BGA40P160X80X68-8-TI_YFX.kicad_mod

@@ -0,0 +1,291 @@
+(footprint "BGA40P160X80X68-8-TI_YFX"
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(property "Reference" "REF**"
+		(at 0 -1.778 0)
+		(unlocked yes)
+		(layer "F.SilkS")
+		(uuid "0954aee3-da56-4c12-a6b3-4d49ddb4ed38")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Value" "BGA40P160X80X68-8-TI_YFX"
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "5593f0e2-97a5-465a-bf10-ee17f3479bf7")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "6cbb546a-dde0-40cb-8566-d7250e758313")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "efb2b894-ebc4-4044-8731-8e7c72f810fc")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "697f1580-7465-47d3-a0bb-89593769a805")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr smd)
+	(fp_rect
+		(start -0.275 -0.675)
+		(end -0.125 -0.525)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.Paste")
+		(uuid "9016cfd0-1bfb-4e61-9545-f7de110f06d4")
+	)
+	(fp_rect
+		(start -0.275 -0.275)
+		(end -0.125 -0.125)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.Paste")
+		(uuid "2314e3a5-73b1-40dc-ae8d-bed674fcdb30")
+	)
+	(fp_rect
+		(start -0.275 0.125)
+		(end -0.125 0.275)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.Paste")
+		(uuid "1d8d9a3d-c3fe-4d1b-b7ba-75370c303332")
+	)
+	(fp_rect
+		(start -0.275 0.525)
+		(end -0.125 0.675)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.Paste")
+		(uuid "e582cea4-bb65-49f8-bc53-c5f1a1af0ec1")
+	)
+	(fp_rect
+		(start 0.125 -0.675)
+		(end 0.275 -0.525)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.Paste")
+		(uuid "84772325-f0e4-47b8-a00c-30af54574402")
+	)
+	(fp_rect
+		(start 0.125 -0.275)
+		(end 0.275 -0.125)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.Paste")
+		(uuid "206f142a-30bb-4f65-9c6a-c83113083d49")
+	)
+	(fp_rect
+		(start 0.125 0.125)
+		(end 0.275 0.275)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.Paste")
+		(uuid "9d9ee2d1-24ff-4c8d-922f-7e76bd2de469")
+	)
+	(fp_rect
+		(start 0.125 0.525)
+		(end 0.275 0.675)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.Paste")
+		(uuid "67f307c4-5f7e-42b4-a1f9-c7a9f253990a")
+	)
+	(fp_line
+		(start -0.762 -0.761998)
+		(end -0.762 1.143)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "77b11429-c3fc-4cea-b024-64ba9ab58906")
+	)
+	(fp_line
+		(start -0.762 1.143)
+		(end 0.762 1.143)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "107789c7-a2cc-4702-95c6-68a202dc59c3")
+	)
+	(fp_line
+		(start -0.380997 -1.143)
+		(end 0.762 -1.143)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "b0049f0b-903d-44d0-8a64-9058b60161a0")
+	)
+	(fp_line
+		(start 0.762 -1.143)
+		(end 0.762 1.143)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "d0e5338a-53b7-4e6c-8dc6-d61fa426cc85")
+	)
+	(fp_arc
+		(start -0.762 -0.761998)
+		(mid -0.650407 -1.031408)
+		(end -0.380997 -1.143)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "a12bed02-3bbc-4545-abf8-408440b4bfcf")
+	)
+	(fp_rect
+		(start -0.4275 -0.82)
+		(end 0.4275 0.82)
+		(stroke
+			(width 0.127)
+			(type default)
+		)
+		(fill none)
+		(layer "F.Fab")
+		(uuid "493e159c-c98c-4800-af52-56fd5afe44b9")
+	)
+	(fp_text user "${REFERENCE}"
+		(at 0 0 90)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "f8588c82-38b8-441e-88f0-0631316d1b67")
+		(effects
+			(font
+				(size 0.254 0.254)
+				(thickness 0.0508)
+				(bold yes)
+			)
+		)
+	)
+	(pad "A1" smd circle
+		(at -0.2 -0.6)
+		(size 0.225 0.225)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(uuid "fc36f205-7f85-4f7a-b31e-799056aa58e3")
+	)
+	(pad "A2" smd circle
+		(at 0.2 -0.6)
+		(size 0.225 0.225)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(uuid "16ac10cb-6933-4454-ae55-4a65c86293d0")
+	)
+	(pad "B1" smd circle
+		(at -0.2 -0.2)
+		(size 0.225 0.225)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(uuid "8d1025bc-30e3-492e-9a8a-22327c1e658d")
+	)
+	(pad "B2" smd circle
+		(at 0.2 -0.2)
+		(size 0.225 0.225)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(uuid "ba192741-8850-4f0b-b2c7-f57f15410708")
+	)
+	(pad "C1" smd circle
+		(at -0.2 0.2)
+		(size 0.225 0.225)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(uuid "685c3660-5601-4065-a2e0-531c63a9229f")
+	)
+	(pad "C2" smd circle
+		(at 0.2 0.2)
+		(size 0.225 0.225)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(uuid "dd238a5f-903e-4cbc-b3a3-2fb66d032034")
+	)
+	(pad "D1" smd circle
+		(at -0.2 0.6)
+		(size 0.225 0.225)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(uuid "713ada56-6685-453e-ab93-58988087df66")
+	)
+	(pad "D2" smd circle
+		(at 0.2 0.6)
+		(size 0.225 0.225)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(uuid "cf82cc3c-bce0-4839-96cb-991bc802e2e4")
+	)
+)

common.pretty/BGA40P165X139X63-12-TI_YFF.kicad_mod

@@ -1,45 +1,223 @@
-(footprint "BGA40P165X139X63-12-TI_YFF" (version 20221018) (generator pcbnew)
-  (layer "F.Cu")
-  (attr smd)
-  (fp_text reference "REF**" (at 0 -1.651) (layer "F.SilkS")
-      (effects (font (size 0.635 0.635) (thickness 0.127)))
-    (tstamp 96f7c673-f5fb-46e3-a5ba-2d24500b11cc)
-  )
-  (fp_text value "BGA40P165X139X63-12-TI_YFF" (at 0 0.635 unlocked) (layer "F.Fab") hide
-      (effects (font (size 0.635 0.635) (thickness 0.127)))
-    (tstamp 7877e857-2b89-43e7-a378-1e54942a85f8)
-  )
-  (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
-      (effects (font (size 0.254 0.254) (thickness 0.0508) bold))
-    (tstamp eca73822-c623-451b-9d4a-460e8a4910a1)
-  )
-  (fp_line (start -1.016 -0.762) (end -1.016 1.143)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp 00c9f252-2d16-4a09-855a-ad06516ad070))
-  (fp_line (start -1.016 1.143) (end 1.016 1.143)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp 93f6e6a0-a2e5-4c0e-aafa-3b4b31ca5b0a))
-  (fp_line (start 1.016 -1.143) (end -0.635 -1.143)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp 0faa53dd-30b2-43e6-860b-35e2e5b91e1b))
-  (fp_line (start 1.016 1.143) (end 1.016 -1.143)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp a855930c-db55-47be-aed7-139dc59d3101))
-  (fp_arc (start -1.016 -0.762) (mid -0.904408 -1.031408) (end -0.635 -1.143)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp 7e038b28-8bde-4bdc-b31c-c8cb3a278b5d))
-  (fp_rect (start -0.709 -0.8375) (end 0.709 0.8375)
-    (stroke (width 0.127) (type default)) (fill none) (layer "F.Fab") (tstamp 2796bfc7-3c4b-4b32-9820-e9ef68dda78e))
-  (pad "A1" smd circle (at -0.4 -0.6) (size 0.23 0.23) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 40f9c759-8962-482d-aa98-894802fa3492))
-  (pad "A2" smd circle (at 0 -0.6) (size 0.23 0.23) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp de16e2e5-d084-462a-806a-0e0d4a680031))
-  (pad "A3" smd circle (at 0.4 -0.6) (size 0.23 0.23) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d2850cdc-498a-4762-99b0-6495b2334d47))
-  (pad "B1" smd circle (at -0.4 -0.2) (size 0.23 0.23) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 752550e6-5bfd-4d79-be0b-73cb3f75bfbe))
-  (pad "B2" smd circle (at 0 -0.2) (size 0.23 0.23) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 894b5198-2173-4611-8d79-7f858393b225))
-  (pad "B3" smd circle (at 0.4 -0.2) (size 0.23 0.23) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ba280fc5-a3e4-4552-8726-315a752336e4))
-  (pad "C1" smd circle (at -0.4 0.2) (size 0.23 0.23) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e77fb54d-554c-4610-91e3-dbbef82abc19))
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-  (pad "C3" smd circle (at 0.4 0.2) (size 0.23 0.23) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9f295b62-19db-4182-b883-1a956c8b4164))
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-    (scale (xyz 1.39 1.65 0.63))
-    (rotate (xyz 0 0 0))
-  )
-)
+(footprint "BGA40P165X139X63-12-TI_YFF"
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(property "Reference" "REF**"
+		(at 0 -1.651 0)
+		(layer "F.SilkS")
+		(uuid "96f7c673-f5fb-46e3-a5ba-2d24500b11cc")
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+	(property "Value" "BGA40P165X139X63-12-TI_YFF"
+		(at 0 0.635 0)
+		(unlocked yes)
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+		(unlocked yes)
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+		(end -1.016 1.143)
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+			(type default)
+		)
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+		(uuid "00c9f252-2d16-4a09-855a-ad06516ad070")
+	)
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+		(end 1.016 1.143)
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+	)
+	(fp_line
+		(start 1.016 1.143)
+		(end 1.016 -1.143)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "a855930c-db55-47be-aed7-139dc59d3101")
+	)
+	(fp_arc
+		(start -1.016 -0.762)
+		(mid -0.904408 -1.031408)
+		(end -0.635 -1.143)
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+			(type default)
+		)
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+		(uuid "7e038b28-8bde-4bdc-b31c-c8cb3a278b5d")
+	)
+	(fp_rect
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+		(end 0.709 0.8375)
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+			(type default)
+		)
+		(fill none)
+		(layer "F.Fab")
+		(uuid "2796bfc7-3c4b-4b32-9820-e9ef68dda78e")
+	)
+	(fp_text user "${REFERENCE}"
+		(at 0 0 90)
+		(layer "F.Fab")
+		(uuid "eca73822-c623-451b-9d4a-460e8a4910a1")
+		(effects
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+		(size 0.23 0.23)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(uuid "40f9c759-8962-482d-aa98-894802fa3492")
+	)
+	(pad "A2" smd circle
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+		(layers "F.Cu" "F.Paste" "F.Mask")
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+	)
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+		(at 0.4 -0.6)
+		(size 0.23 0.23)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(uuid "d2850cdc-498a-4762-99b0-6495b2334d47")
+	)
+	(pad "B1" smd circle
+		(at -0.4 -0.2)
+		(size 0.23 0.23)
+		(layers "F.Cu" "F.Paste" "F.Mask")
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+	)
+	(pad "B2" smd circle
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+		(layers "F.Cu" "F.Paste" "F.Mask")
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+		(layers "F.Cu" "F.Paste" "F.Mask")
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+	)
+	(pad "C1" smd circle
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+		(size 0.23 0.23)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(uuid "e77fb54d-554c-4610-91e3-dbbef82abc19")
+	)
+	(pad "C2" smd circle
+		(at 0 0.2)
+		(size 0.23 0.23)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(uuid "49c20f33-a999-4cb0-87f7-01ab4c8f9bd0")
+	)
+	(pad "C3" smd circle
+		(at 0.4 0.2)
+		(size 0.23 0.23)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(uuid "9f295b62-19db-4182-b883-1a956c8b4164")
+	)
+	(pad "D1" smd circle
+		(at -0.4 0.6)
+		(size 0.23 0.23)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(uuid "be36231d-fe8e-4518-8958-6b12185ffb52")
+	)
+	(pad "D2" smd circle
+		(at 0 0.6)
+		(size 0.23 0.23)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(uuid "9eebbdf5-d659-45ed-9e6d-320c8e284e75")
+	)
+	(pad "D3" smd circle
+		(at 0.4 0.6)
+		(size 0.23 0.23)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(uuid "48e8a92d-398a-4d0b-be72-1ea14201445e")
+	)
+	(model "step/cube_1mm.step"
+		(offset
+			(xyz 0 0 0)
+		)
+		(scale
+			(xyz 1.39 1.65 0.63)
+		)
+		(rotate
+			(xyz 0 0 0)
+		)
+	)
+)

common.pretty/Bourns_PVG3A.kicad_mod

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+(footprint "Bourns_PVG3A"
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(property "Reference" "REF**"
+		(at 0 -2.667 0)
+		(unlocked yes)
+		(layer "F.SilkS")
+		(uuid "f05ec80e-f3a0-43e6-9dd7-100be86115bb")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Value" "Bourns_PVG3A"
+		(at 0 -1.143 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "0cdc6ff4-865d-465e-ae99-0990465d43b5")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "f988fd19-4df2-46f0-b0e7-aa3254ca6f43")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "3349ae57-15cb-4664-8d8e-cac6504ded55")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "66aa109a-c2b2-41a4-b3c8-95c95972d41c")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr smd)
+	(fp_line
+		(start -2.159 -2.032)
+		(end -2.159 2.032)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "bea2b35b-c96d-41e5-816a-39637e637091")
+	)
+	(fp_line
+		(start -2.159 -2.032)
+		(end -0.889 -2.032)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "bb779f98-6b82-4124-b32a-f8de56d1c27d")
+	)
+	(fp_line
+		(start -1.905 2.032)
+		(end -2.159 2.032)
+		(stroke
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+			(type default)
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+		(uuid "d9809586-0dff-4c84-bc82-f2ac3d05947d")
+	)
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+		(end 2.159 2.032)
+		(stroke
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+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "5af9fea6-6caf-4637-8ee6-e490476f64b4")
+	)
+	(fp_line
+		(start 2.159 -2.032)
+		(end 0.889 -2.032)
+		(stroke
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+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "7fe1a0d7-f0f9-4f4f-8a24-99d4c210197e")
+	)
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+		(end 2.159 2.032)
+		(stroke
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+		(layer "F.SilkS")
+		(uuid "e2d6b935-6ccd-4be4-91b9-1e69c77bfa04")
+	)
+	(fp_rect
+		(start -1.8 -1.7)
+		(end 1.8 1.7)
+		(stroke
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+			(type default)
+		)
+		(fill none)
+		(layer "F.Fab")
+		(uuid "4c3eb217-8aad-403c-a88e-88499f9cd99a")
+	)
+	(fp_text user "${REFERENCE}"
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "70a0fbf5-0958-42f4-a9a9-605c94fcb21f")
+		(effects
+			(font
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+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(pad "1" smd roundrect
+		(at 1.15 1.65)
+		(size 1.1 0.9)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.15)
+		(thermal_bridge_angle 45)
+		(uuid "130bb016-66a9-441e-9ed1-db3d37052fa8")
+	)
+	(pad "2" smd roundrect
+		(at -1.15 1.65)
+		(size 1.1 0.9)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.15)
+		(thermal_bridge_angle 45)
+		(uuid "e7deafbe-e7db-480c-add2-2eab2d208a89")
+	)
+	(pad "3" smd roundrect
+		(at 0 -1.65)
+		(size 1.4 0.9)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.15)
+		(thermal_bridge_angle 45)
+		(uuid "9f0ee0ac-7a43-45cb-883a-35202d490f77")
+	)
+	(model "${KIPRJMOD}/common_libraries/common.pretty/step/Bourns_PVG3A.STEP"
+		(offset
+			(xyz 0 -1.7 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz 0 0 0)
+		)
+	)
+)

common.pretty/DFN50P180X200X60-6P_TOREX_USP-6C.kicad_mod

@@ -0,0 +1,228 @@
+(footprint "DFN50P180X200X60-6P_TOREX_USP-6C"
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(property "Reference" "REF**"
+		(at 0 -1.778 0)
+		(unlocked yes)
+		(layer "F.SilkS")
+		(uuid "feaf9a61-7c9b-431e-ae6b-14ae3498e156")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Value" "DFN50P180X200X60-6P_TOREX_USP-6C"
+		(at 0 0.508 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "a92bfc62-e60d-4156-aa10-985307550b7f")
+		(effects
+			(font
+				(size 0.1016 0.1016)
+				(thickness 0.02032)
+				(bold yes)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "f2021718-5277-4ccc-a81b-98bc44a45693")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "b3272119-9a7b-4958-88ad-b694436b3e65")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
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+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "e02f9360-6465-4581-8ba8-b00fd0ae1fbf")
+		(effects
+			(font
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+				(thickness 0.15)
+			)
+		)
+	)
+	(attr smd)
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+		(start -1.27 0.762)
+		(end -1.27 1.143)
+		(stroke
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+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "8fd36617-5353-45e2-bef2-619f19c49e67")
+	)
+	(fp_line
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+		(end 1.27 1.143)
+		(stroke
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+			(type default)
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+		(uuid "b63b02aa-df5d-4391-a149-675dd58e55d0")
+	)
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+		(end 1.27 -1.143)
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+		(layer "F.SilkS")
+		(uuid "ddd3bd08-9fe0-458c-8c80-ea47511f8f3d")
+	)
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+		(end 1.27 -0.762)
+		(stroke
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+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "83694973-b257-42df-a04c-930295a21002")
+	)
+	(fp_line
+		(start 1.27 0.762)
+		(end 1.27 1.143)
+		(stroke
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+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "028b3470-cdbe-4721-a4fe-ff0a62242061")
+	)
+	(fp_arc
+		(start -1.27 -0.889)
+		(mid -1.195605 -1.068605)
+		(end -1.016 -1.143)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "d87716c4-f439-4b9f-b463-e191b44c504c")
+	)
+	(fp_rect
+		(start -1 -0.9)
+		(end 1 0.9)
+		(stroke
+			(width 0.1)
+			(type default)
+		)
+		(fill none)
+		(layer "F.Fab")
+		(uuid "37da6d53-6d4e-46bc-b7c6-4230505ff74b")
+	)
+	(fp_poly
+		(pts
+			(xy -1 -0.9) (xy -0.381 -0.889) (xy -1.016 -0.254)
+		)
+		(stroke
+			(width 0)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.Fab")
+		(uuid "6a8b005b-48c9-49e7-afba-b1964879f3a4")
+	)
+	(fp_text user "${REFERENCE}"
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "27a19d21-934b-463c-a65e-4b264fcc1157")
+		(effects
+			(font
+				(size 0.254 0.254)
+				(thickness 0.0508)
+				(bold yes)
+			)
+		)
+	)
+	(pad "0" smd roundrect
+		(at 0 0)
+		(size 1 1.8)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(roundrect_rratio 0.1)
+		(uuid "51a76b31-2bd6-4bfe-a2d0-69d70f569fe4")
+	)
+	(pad "1" smd roundrect
+		(at -0.975 -0.5)
+		(size 0.45 0.35)
+		(drill
+			(offset 0 -0.05)
+		)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(roundrect_rratio 0.1088571429)
+		(uuid "be2ce185-2c8f-41b6-8230-e6e71e0cdca7")
+	)
+	(pad "2" smd roundrect
+		(at -0.975 0)
+		(size 0.45 0.25)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(roundrect_rratio 0.1524)
+		(uuid "6d88453d-fb09-41e4-b32e-9444bf503aab")
+	)
+	(pad "3" smd roundrect
+		(at -0.975 0.5)
+		(size 0.45 0.25)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(roundrect_rratio 0.1524)
+		(uuid "44630884-dd8c-436d-b245-8e2c43671301")
+	)
+	(pad "4" smd roundrect
+		(at 0.975 0.5)
+		(size 0.45 0.25)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(roundrect_rratio 0.1524)
+		(uuid "8a1559c9-b069-4190-abfb-9ef8b2646f50")
+	)
+	(pad "5" smd roundrect
+		(at 0.975 0)
+		(size 0.45 0.25)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(roundrect_rratio 0.1524)
+		(uuid "6e1fe678-3c18-418d-929d-f2160016df04")
+	)
+	(pad "6" smd roundrect
+		(at 0.975 -0.5)
+		(size 0.45 0.25)
+		(property pad_prop_bga)
+		(layers "F.Cu" "F.Mask")
+		(roundrect_rratio 0.1524)
+		(uuid "c9af7b62-3cb2-4a67-907b-160a0200c367")
+	)
+)

common.pretty/JS202011JCQN.kicad_mod

@@ -52,7 +52,7 @@
     (thermal_bridge_angle 45) (tstamp b357b393-f1d7-40d7-b417-4438a29d23d0))
   (pad "6" smd roundrect (at 2.5 1.2) (size 1 1.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
     (thermal_bridge_angle 45) (tstamp 127ecd3d-5495-4ee0-8e59-82d352ff7dcf))
-  (model "/home/brendan/Documents/projects/mellifera/hardware/mellifera_hardware/common_libraries/common.pretty/step/CK_JS202011JCQN.stp"
+  (model "./step/CK_JS202011JCQN.stp"
     (offset (xyz 0 0 0))
     (scale (xyz 1 1 1))
     (rotate (xyz -90 0 0))

common.pretty/MC-311D.kicad_mod

@@ -1,54 +1,298 @@
-(footprint "MC-311D" (version 20221018) (generator pcbnew)
-  (layer "F.Cu")
-  (descr "Connector, USB C, 16 pin")
-  (attr smd)
-  (fp_text reference "REF**" (at 0 -5.842) (layer "F.SilkS")
-      (effects (font (size 0.635 0.635) (thickness 0.127) bold))
-    (tstamp 1218ce80-e7fa-44f9-b4a7-3921e33245ff)
-  )
-  (fp_text value "MC-311D" (at 0 1.016 unlocked) (layer "F.Fab") hide
-      (effects (font (size 0.635 0.635) (thickness 0.127) bold))
-    (tstamp 6af2527b-d46d-4d84-8913-9aab61bd4780)
-  )
-  (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
-      (effects (font (size 1.016 1.016) (thickness 0.2032) bold))
-    (tstamp 62adbbab-c027-4be2-abc5-41f9e33ece44)
-  )
-  (fp_line (start -4.699 -3.175) (end -4.699 -1.016)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp 06f5d7db-5728-453b-8aff-f4e6dca73f6e))
-  (fp_line (start -4.699 1.016) (end -4.699 1.778)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp 03cfd9b9-048f-45f9-9c31-6e3a1f00b142))
-  (fp_line (start -3.81 -5.08) (end -3.683 -5.08)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp 04a346ca-09ca-4cfb-80b7-d54832d1e2e5))
-  (fp_line (start 3.683 -5.08) (end 3.81 -5.08)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp 615df629-49d6-44a3-b23d-54b880c0cbd9))
-  (fp_line (start 4.699 -3.175) (end 4.699 -1.016)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp b5dbcaa5-7bcb-4994-8db2-90ccb4de2363))
-  (fp_line (start 4.699 1.016) (end 4.699 1.778)
-    (stroke (width 0.1778) (type default)) (layer "F.SilkS") (tstamp 5dee34b0-2165-485b-a791-b0ba6e09daf6))
-  (fp_rect (start -4.47 -4.75) (end 4.47 2.6)
-    (stroke (width 0.127) (type default)) (fill none) (layer "F.Fab") (tstamp 333d9c90-2e96-4787-bdca-5e45918b796c))
-  (pad "" np_thru_hole circle (at -2.89 -3.68) (size 0.65 0.65) (drill 0.65) (layers "F&B.Cu" "*.Mask") (tstamp fc9e8193-c075-44f0-863c-d1ef57e3c228))
-  (pad "" np_thru_hole circle (at 2.935 -3.68) (size 0.65 0.65) (drill 0.65) (layers "F&B.Cu" "*.Mask") (tstamp 3864ced7-3de7-49fd-8004-52be6e6ecaa2))
-  (pad "0" thru_hole roundrect (at -4.32 -4.18) (size 1 1.8) (drill oval 0.6 1.4) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.5) (tstamp a397bfe2-42b9-469f-9773-3dee5882a02f))
-  (pad "0" thru_hole roundrect (at -4.32 0) (size 1 1.8) (drill oval 0.6 1.4) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.5) (tstamp df408c0b-0e9d-4cef-a706-59bebbec8e65))
-  (pad "0" thru_hole roundrect (at 4.32 -4.18) (size 1 1.8) (drill oval 0.6 1.4) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.5) (tstamp 010c3d32-24ab-41ed-9895-575ac4d01f9f))
-  (pad "0" thru_hole roundrect (at 4.32 0) (size 1 1.8) (drill oval 0.6 1.4) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.5) (tstamp 7656ab45-f1bf-4c4a-837a-c695310f88d8))
-  (pad "A1B12" smd roundrect (at -3.2 -4.745) (size 0.6 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15) (tstamp 599451e1-8d8e-4549-9f89-c9ab5e6819fb))
-  (pad "A4B9" smd roundrect (at -2.4 -4.745) (size 0.6 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15) (tstamp 478a10c7-cc21-4bd6-b64b-e1e6124ab5f7))
-  (pad "A5" smd roundrect (at -1.25 -4.745) (size 0.3 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 79ffb550-c1f9-425f-ad59-03f551f1515e))
-  (pad "A6" smd roundrect (at -0.25 -4.745) (size 0.3 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 6c184e21-df3a-4100-8e6d-097602817995))
-  (pad "A7" smd roundrect (at 0.25 -4.745) (size 0.3 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp e8dd61a1-d244-47d6-a964-b64dc0c6030e))
-  (pad "A8" smd roundrect (at 1.25 -4.745) (size 0.3 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 105b474c-2e9c-49e2-af64-d8c7f2466540))
-  (pad "B1A12" smd roundrect (at 3.2 -4.745) (size 0.6 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15) (tstamp 153436a7-4ba8-43f2-898b-30411e4ce5fb))
-  (pad "B4A9" smd roundrect (at 2.4 -4.745) (size 0.6 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15) (tstamp 4e97f3e2-ae9f-4311-9dfa-9e45ed8e8e0f))
-  (pad "B5" smd roundrect (at 1.75 -4.745) (size 0.3 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp c6d24975-d5ce-4e1f-b5bd-dadc3f797614))
-  (pad "B6" smd roundrect (at 0.75 -4.745) (size 0.3 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp ac9681d3-b1e3-414d-bbc2-5824edf8fe4d))
-  (pad "B7" smd roundrect (at -0.75 -4.745) (size 0.3 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp dd8a327b-4131-429c-9a33-2862589d3d9d))
-  (pad "B8" smd roundrect (at -1.75 -4.745) (size 0.3 1.15) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 6ef2a963-c5d9-4531-9781-3af3c3756cd5))
-  (model "step/DX07S016JA1R1500.step"
-    (offset (xyz 0 1.6002 0))
-    (scale (xyz 1 1 1))
-    (rotate (xyz -90 0 0))
-  )
+(footprint "MC-311D"
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(descr "Connector, USB C, 16 pin")
+	(property "Reference" "REF**"
+		(at 0 -5.842 0)
+		(layer "F.SilkS")
+		(uuid "1218ce80-e7fa-44f9-b4a7-3921e33245ff")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Value" "MC-311D"
+		(at 0 1.016 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "6af2527b-d46d-4d84-8913-9aab61bd4780")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "585228c6-5451-4383-9c3a-ac929c9a21aa")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "53943f8c-031f-4c3c-b950-9993f463c774")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "34bd7c15-69e9-4ac4-a77e-19aab703b71d")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr through_hole)
+	(fp_line
+		(start -4.699 -3.175)
+		(end -4.699 -1.016)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "06f5d7db-5728-453b-8aff-f4e6dca73f6e")
+	)
+	(fp_line
+		(start -4.699 1.016)
+		(end -4.699 1.778)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "03cfd9b9-048f-45f9-9c31-6e3a1f00b142")
+	)
+	(fp_line
+		(start -3.81 -5.08)
+		(end -3.683 -5.08)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "04a346ca-09ca-4cfb-80b7-d54832d1e2e5")
+	)
+	(fp_line
+		(start 3.683 -5.08)
+		(end 3.81 -5.08)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "615df629-49d6-44a3-b23d-54b880c0cbd9")
+	)
+	(fp_line
+		(start 4.699 -3.175)
+		(end 4.699 -1.016)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "b5dbcaa5-7bcb-4994-8db2-90ccb4de2363")
+	)
+	(fp_line
+		(start 4.699 1.016)
+		(end 4.699 1.778)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "5dee34b0-2165-485b-a791-b0ba6e09daf6")
+	)
+	(fp_rect
+		(start -4.47 -4.75)
+		(end 4.47 2.6)
+		(stroke
+			(width 0.127)
+			(type default)
+		)
+		(fill none)
+		(layer "F.Fab")
+		(uuid "333d9c90-2e96-4787-bdca-5e45918b796c")
+	)
+	(fp_text user "${REFERENCE}"
+		(at 0 0 0)
+		(layer "F.Fab")
+		(uuid "62adbbab-c027-4be2-abc5-41f9e33ece44")
+		(effects
+			(font
+				(size 1.016 1.016)
+				(thickness 0.2032)
+				(bold yes)
+			)
+		)
+	)
+	(pad "" np_thru_hole circle
+		(at -2.89 -3.68)
+		(size 0.65 0.65)
+		(drill 0.65)
+		(layers "F&B.Cu" "*.Mask")
+		(uuid "fc9e8193-c075-44f0-863c-d1ef57e3c228")
+	)
+	(pad "" np_thru_hole circle
+		(at 2.935 -3.68)
+		(size 0.65 0.65)
+		(drill 0.65)
+		(layers "F&B.Cu" "*.Mask")
+		(uuid "3864ced7-3de7-49fd-8004-52be6e6ecaa2")
+	)
+	(pad "0" thru_hole roundrect
+		(at -4.32 -4.18)
+		(size 1 1.8)
+		(drill oval 0.6 1.4)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(roundrect_rratio 0.5)
+		(uuid "a397bfe2-42b9-469f-9773-3dee5882a02f")
+	)
+	(pad "0" thru_hole roundrect
+		(at -4.32 0)
+		(size 1 1.8)
+		(drill oval 0.6 1.4)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(roundrect_rratio 0.5)
+		(uuid "df408c0b-0e9d-4cef-a706-59bebbec8e65")
+	)
+	(pad "0" thru_hole roundrect
+		(at 4.32 -4.18)
+		(size 1 1.8)
+		(drill oval 0.6 1.4)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(roundrect_rratio 0.5)
+		(uuid "010c3d32-24ab-41ed-9895-575ac4d01f9f")
+	)
+	(pad "0" thru_hole roundrect
+		(at 4.32 0)
+		(size 1 1.8)
+		(drill oval 0.6 1.4)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(roundrect_rratio 0.5)
+		(uuid "7656ab45-f1bf-4c4a-837a-c695310f88d8")
+	)
+	(pad "A1B12" smd roundrect
+		(at -3.2 -4.745)
+		(size 0.6 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.15)
+		(uuid "599451e1-8d8e-4549-9f89-c9ab5e6819fb")
+	)
+	(pad "A4B9" smd roundrect
+		(at -2.4 -4.745)
+		(size 0.6 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.15)
+		(uuid "478a10c7-cc21-4bd6-b64b-e1e6124ab5f7")
+	)
+	(pad "A5" smd roundrect
+		(at -1.25 -4.745)
+		(size 0.3 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.25)
+		(uuid "79ffb550-c1f9-425f-ad59-03f551f1515e")
+	)
+	(pad "A6" smd roundrect
+		(at -0.25 -4.745)
+		(size 0.3 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.25)
+		(uuid "6c184e21-df3a-4100-8e6d-097602817995")
+	)
+	(pad "A7" smd roundrect
+		(at 0.25 -4.745)
+		(size 0.3 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.25)
+		(uuid "e8dd61a1-d244-47d6-a964-b64dc0c6030e")
+	)
+	(pad "A8" smd roundrect
+		(at 1.25 -4.745)
+		(size 0.3 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.25)
+		(uuid "105b474c-2e9c-49e2-af64-d8c7f2466540")
+	)
+	(pad "B1A12" smd roundrect
+		(at 3.2 -4.745)
+		(size 0.6 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.15)
+		(uuid "153436a7-4ba8-43f2-898b-30411e4ce5fb")
+	)
+	(pad "B4A9" smd roundrect
+		(at 2.4 -4.745)
+		(size 0.6 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.15)
+		(uuid "4e97f3e2-ae9f-4311-9dfa-9e45ed8e8e0f")
+	)
+	(pad "B5" smd roundrect
+		(at 1.75 -4.745)
+		(size 0.3 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.25)
+		(uuid "c6d24975-d5ce-4e1f-b5bd-dadc3f797614")
+	)
+	(pad "B6" smd roundrect
+		(at 0.75 -4.745)
+		(size 0.3 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.25)
+		(uuid "ac9681d3-b1e3-414d-bbc2-5824edf8fe4d")
+	)
+	(pad "B7" smd roundrect
+		(at -0.75 -4.745)
+		(size 0.3 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.25)
+		(uuid "dd8a327b-4131-429c-9a33-2862589d3d9d")
+	)
+	(pad "B8" smd roundrect
+		(at -1.75 -4.745)
+		(size 0.3 1.15)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.25)
+		(uuid "6ef2a963-c5d9-4531-9781-3af3c3756cd5")
+	)
+	(model "step/DX07S016JA1R1500.step"
+		(offset
+			(xyz 0 1.6002 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 0)
+		)
+	)
 )

common.pretty/R0201.kicad_mod

@@ -0,0 +1,122 @@
+(footprint "R0201"
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(property "Reference" "REF**"
+		(at 0 -0.889 0)
+		(unlocked yes)
+		(layer "F.SilkS")
+		(uuid "3a1fd817-daa0-427c-82eb-f7319b1027ae")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Value" "R0201"
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "dcf65ffe-b0b5-46eb-a72b-7374a01348aa")
+		(effects
+			(font
+				(size 0.127 0.127)
+				(thickness 0.0254)
+				(bold yes)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "f821e7a6-3b38-4b15-826b-c2e2eac20f2a")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "051c5b23-f68a-48db-ad33-abc6f17b4a9f")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "1dc412fb-efde-4999-a872-a47ed9743e00")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr smd)
+	(fp_rect
+		(start -0.635 -0.381)
+		(end 0.635 0.381)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(fill none)
+		(layer "F.SilkS")
+		(uuid "90dc834c-32b5-44e8-b5a7-d7e225f44865")
+	)
+	(fp_rect
+		(start -0.254 -0.127)
+		(end 0.254 0.127)
+		(stroke
+			(width 0.0762)
+			(type default)
+		)
+		(fill none)
+		(layer "F.Fab")
+		(uuid "ed421f81-4bec-4558-8698-8da0a0656b0f")
+	)
+	(fp_text user "${REFERENCE}"
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "67f0e018-2381-43aa-86f3-f714c2bf880b")
+		(effects
+			(font
+				(size 0.0762 0.0762)
+				(thickness 0.01524)
+				(bold yes)
+			)
+		)
+	)
+	(pad "1" smd roundrect
+		(at -0.275 0)
+		(size 0.25 0.35)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.1)
+		(uuid "b15d4046-851d-4dfe-83e1-00dba3458bfe")
+	)
+	(pad "2" smd roundrect
+		(at 0.275 0)
+		(size 0.25 0.35)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.1)
+		(uuid "144e8f9e-135e-408f-82b9-85e27a90c4ca")
+	)
+)

common.pretty/SOD-882.kicad_mod

@@ -0,0 +1,135 @@
+(footprint "SOD-882"
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(property "Reference" "REF**"
+		(at 0 -1.143 0)
+		(unlocked yes)
+		(layer "F.SilkS")
+		(uuid "56cb4925-fd1a-4cad-9648-fe903873f5d3")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+				(bold yes)
+			)
+		)
+	)
+	(property "Value" "SOD-882"
+		(at 0 0.254 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "8df07534-dc63-4d07-b8e3-d73f890e8e78")
+		(effects
+			(font
+				(size 0.127 0.127)
+				(thickness 0.0254)
+				(bold yes)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "1e8470d1-eca0-46ca-aabc-f7226238bf0b")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "d8debe72-bc53-4492-9758-3f391b2424a7")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "1324792a-4e1d-4fca-a7bb-e09df386a50f")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr smd)
+	(fp_rect
+		(start -1.016 -0.635)
+		(end -0.762 0.635)
+		(stroke
+			(width 0.1778)
+			(type solid)
+		)
+		(fill solid)
+		(layer "F.SilkS")
+		(uuid "c8dba288-9758-4e4e-80b4-c632001dde5a")
+	)
+	(fp_rect
+		(start -1.016 -0.635)
+		(end 0.762 0.635)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(fill none)
+		(layer "F.SilkS")
+		(uuid "1fadae7e-6af2-40b4-99a2-d9473311cadb")
+	)
+	(fp_rect
+		(start -0.65 -0.45)
+		(end 0.65 0.45)
+		(stroke
+			(width 0.127)
+			(type default)
+		)
+		(fill none)
+		(layer "F.Fab")
+		(uuid "337a2577-b0cd-46a4-9ac1-e482f60d7787")
+	)
+	(fp_text user "${REFERENCE}"
+		(at 0 0 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "411e7583-7a53-4428-a5ff-e9f76f3098ff")
+		(effects
+			(font
+				(size 0.127 0.127)
+				(thickness 0.0254)
+				(bold yes)
+			)
+		)
+	)
+	(pad "A" smd roundrect
+		(at 0.35 0)
+		(size 0.4 0.7)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.125)
+		(thermal_bridge_angle 45)
+		(uuid "5c50b2e5-5ea9-41e8-b4e0-bd720a8496bb")
+	)
+	(pad "K" smd roundrect
+		(at -0.35 0)
+		(size 0.4 0.7)
+		(layers "F.Cu" "F.Paste" "F.Mask")
+		(roundrect_rratio 0.125)
+		(thermal_bridge_angle 45)
+		(uuid "e6423183-7e06-4df8-b82a-d989410bbc2d")
+	)
+)

common.pretty/step/Amphenol_12401832E402A.step

@@ -2,8 +2,7 @@ ISO-10303-21;
 HEADER;
 FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
 FILE_NAME(
-'/home/brendan/Documents/tempsync/projects/0000_
-KiCad/libraries/common.3dshapes/Amphenol_12401832E402A.step',
+'Amphenol_12401832E402A.step',
   '2021-08-07T19:22:33',('Author'),(''),
   'Open CASCADE STEP processor 7.3','FreeCAD','Unknown');
 FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));

common.pretty/step/CK_1101M2S3CQE2.step

@@ -2,8 +2,7 @@ ISO-10303-21;
 HEADER;
 FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
 FILE_NAME(
-'/home/brendan/Documents/tempsync/projects/0000_
-KiCad/libraries/common.3dshapes/CK_export.step','2021-06-26T02:57:55',(
+'CK_export.step','2021-06-26T02:57:55',(
     'Author'),(''),'Open CASCADE STEP processor 7.3','FreeCAD','Unknown'
   );
 FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));

common.pretty/step/MiniCircuits_JC0603-1.step

@@ -2,8 +2,7 @@ ISO-10303-21;
 HEADER;
 FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
 FILE_NAME(
-'/home/brendan/Documents/tempsync/projects/0000_
-KiCad/3dshapecad/MiniCircuits_JC0603-1.step','2021-06-26T04:56:55',(
+'MiniCircuits_JC0603-1.step','2021-06-26T04:56:55',(
     'Author'),(''),'Open CASCADE STEP processor 7.3','FreeCAD','Unknown'
   );
 FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));

common.pretty/step/Panasonic_EVP-AEBB2A.step

@@ -2,8 +2,7 @@ ISO-10303-21;
 HEADER;
 FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
 FILE_NAME(
-'/home/brendan/Documents/tempsync/projects/0000_
-KiCad/libraries/common.3dshapes/Panasonic_EVP-AEBB2A.step',
+'Panasonic_EVP-AEBB2A.step',
   '2021-06-26T03:57:27',('Author'),(''),
   'Open CASCADE STEP processor 7.3','FreeCAD','Unknown');
 FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));

common.pretty/step/TE_2337857-1.step

@@ -2,8 +2,7 @@ ISO-10303-21;
 HEADER;
 FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
 FILE_NAME(
-'/home/brendan/Documents/tempsync/projects/0000_
-KiCad/libraries/common.3dshapes/TE_2337857-1.step','2021-06-26T03:46:57'
+'TE_2337857-1.step','2021-06-26T03:46:57'
   ,('Author'),(''),'Open CASCADE STEP processor 7.3','FreeCAD','Unknown'
   );
 FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));

common.pretty/step/TE_6116075-1.step

@@ -2,8 +2,7 @@ ISO-10303-21;
 HEADER;
 FILE_DESCRIPTION(('FreeCAD Model'),'2;1');
 FILE_NAME(
-'/home/brendan/Documents/tempsync/projects/0000_
-KiCad/libraries/common.3dshapes/TE_6116075-1.step','2021-06-26T03:23:56'
+'TE_6116075-1.step','2021-06-26T03:23:56'
   ,('Author'),(''),'Open CASCADE STEP processor 7.3','FreeCAD','Unknown'
   );
 FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));

diode.kicad_sym

@@ -104,7 +104,7 @@
     (property "Spice_Netlist_Enabled" "Y" (id 6) (at 0 2.54 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/onsemi/S115FA.LIB" (id 7) (at 0 2.54 0)
+    (property "Spice_Lib_File" "./spice/onsemi/S115FA.LIB" (id 7) (at 0 2.54 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "ki_description" "Diode, Schottky, 1A, 150V, SOD-123FL" (id 8) (at 0 0 0)
@@ -136,7 +136,7 @@
     (property "Spice_Netlist_Enabled" "Y" (id 6) (at 0 2.54 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/onsemi/S310FA.LIB" (id 7) (at 0 2.54 0)
+    (property "Spice_Lib_File" "./spice/onsemi/S310FA.LIB" (id 7) (at 0 2.54 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "ki_description" "Diode, Schottky, 3A, 100V, SOD-123FL" (id 8) (at 0 0 0)

logic.kicad_sym

@@ -39,7 +39,7 @@
     (property "Spice_Node_Sequence" "Y A B VCC GND" (id 12) (at 0 0 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/ti/SN74LVC1G00.cir" (id 13) (at 0 0 0)
+    (property "Spice_Lib_File" "./spice/ti/SN74LVC1G00.cir" (id 13) (at 0 0 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "ki_description" "IC, Logic, NAND, Single,  SOT-353" (id 14) (at 0 0 0)

old/footprints/common.pretty/CONN_RJ45_TE_1-2301994-5.kicad_mod

@@ -30,7 +30,7 @@
   (pad "0" thru_hole circle (at -8.001 -3.048) (size 2.921 2.921) (drill 1.6) (layers *.Cu *.Mask))
   (pad "" np_thru_hole circle (at 5.715 0) (size 3.250001 3.250001) (drill 3.250001) (layers *.Cu *.Mask))
   (pad "" np_thru_hole circle (at -5.715 0) (size 3.25 3.25) (drill 3.25) (layers *.Cu *.Mask))
-  (model "/home/brendan/Documents/Projects/0002_WaveGen/Hardware/Libraries/WaveGen.pretty/3dmodels/CONN_RJ45_TE_1-2301994-5.step"
+  (model "./step/CONN_RJ45_TE_1-2301994-5.step"
     (offset (xyz 0 -10.795 7.112000000000001))
     (scale (xyz 1 1 1))
     (rotate (xyz -90 0 0))

old/footprints/common.pretty/CRYSTAL_Abracon_ABM10AIG.kicad_mod

@@ -18,7 +18,7 @@
   (pad 0 smd rect (at 0.825 0.65) (size 0.95 0.8) (layers F.Cu F.Paste F.Mask))
   (pad 2 smd rect (at 0.825 -0.65) (size 0.95 0.8) (layers F.Cu F.Paste F.Mask))
   (pad 1 smd rect (at -0.825 0.65) (size 0.95 0.8) (layers F.Cu F.Paste F.Mask))
-  (model "/home/brendan/Documents/Projects/libraries/common.3dshapes/User Library-Crystal NDK NX2520SA series.step"
+  (model "./step/User Library-Crystal NDK NX2520SA series.step"
     (at (xyz 0 0 0))
     (scale (xyz 1 1 1))
     (rotate (xyz 0 0 0))

old/footprints/connector.pretty/Molex_532610571.kicad_mod

@@ -24,7 +24,7 @@
   (pad 1 smd rect (at 2.5 -0.8) (size 0.8 1.6) (layers F.Cu F.Paste F.Mask))
   (pad 0 smd rect (at -5.05 2.1) (size 2.1 3) (layers F.Cu F.Paste F.Mask))
   (pad 0 smd rect (at 5.05 2.1) (size 2.1 3) (layers F.Cu F.Paste F.Mask))
-  (model /home/brendan/Documents/Projects/libraries/Connector_Molex.3dshapes/532610571.stp
+  (model "./step/Connector_Molex.3dshapes/532610571.stp"
     (offset (xyz 0 -3.301999950408935 1.777999973297119))
     (scale (xyz 1 1 1))
     (rotate (xyz 0 0 180))

old/footprints/connector.pretty/Samtec_SMH-106-02-D.kicad_mod

@@ -26,7 +26,7 @@
   (pad 10 smd rect (at -3.81 -3.8608) (size 1.4224 1.7272) (layers F.Cu F.Paste F.Mask))
   (pad 11 smd rect (at -6.35 0) (size 1.4224 1.7272) (layers F.Cu F.Paste F.Mask))
   (pad 12 smd rect (at -6.35 -3.8608) (size 1.4224 1.7272) (layers F.Cu F.Paste F.Mask))
-  (model /home/brendan/Documents/Projects/libraries/Connector_Samtec.3dshapes/SMH-106-02-G-D.stp
+  (model "./step/SMH-106-02-G-D.stp"
     (offset (xyz 0 -3 2.54))
     (scale (xyz 1 1 1))
     (rotate (xyz -90 0 0))

samtec.pretty/PinHeader_1x01_0.1in_TSW-101-07-L-S.kicad_mod

@@ -1,16 +1,128 @@
 (footprint "PinHeader_1x01_0.1in_TSW-101-07-L-S"
-  (version 20221029)
-  (generator pcbnew)
-  (layer "F.Cu")
-  (attr smd)
-  (descr "Header, Male, 1x01, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
-  (tags "header pin")
-  (fp_text reference "REF**" (at 0.0 -2.032 0) (layer "F.SilkS") (effects (font (size 0.7619999999999999 0.7619999999999999) (thickness 0.17779999999999999))) )
-  (fp_text value "VAL**" (at -0.635 0.0 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
-  (fp_text user "${REFERENCE}**" (at 0.635 0.0 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
-  (fp_rect (start -1.27 -1.27) (end 1.27 1.27) (stroke (width 0.17779999999999999) (type default)) (fill none) (layer "F.SilkS") )
-  (fp_line (start -1.27 1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
-  (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
-  (pad "1" thru_hole rect (at 0.0 0.0) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-101-07-L-S.stp" (offset (xyz 0.0 0.0 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-)
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(descr "Header, Male, 1x01, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
+	(tags "header pin")
+	(property "Reference" "REF**"
+		(at 0 -2.032 0)
+		(layer "F.SilkS")
+		(uuid "268fd539-fa62-448f-ba39-0d0a34159c58")
+		(effects
+			(font
+				(size 0.762 0.762)
+				(thickness 0.1778)
+			)
+		)
+	)
+	(property "Value" "VAL**"
+		(at -0.635 0 90)
+		(layer "F.Fab")
+		(uuid "fd9e82e7-4097-4aba-bdc6-6ba33ca2a8d5")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "97652ea8-be16-440f-87d6-045f4e84e8ff")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "1e796d57-f407-4272-9917-a4453790e269")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "f9a4ba14-1d79-47db-a907-d4bd24c675bf")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr through_hole)
+	(fp_line
+		(start -1.27 1.27)
+		(end 1.27 1.27)
+		(stroke
+			(width 0.1778)
+			(type solid)
+		)
+		(layer "F.SilkS")
+		(uuid "0f9698d2-c188-49d9-a59c-66b3d8e79763")
+	)
+	(fp_line
+		(start 1.27 -1.27)
+		(end 1.27 1.27)
+		(stroke
+			(width 0.1778)
+			(type solid)
+		)
+		(layer "F.SilkS")
+		(uuid "a00e8d2a-30e3-49be-9e41-363bcc000469")
+	)
+	(fp_rect
+		(start -1.27 -1.27)
+		(end 1.27 1.27)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(fill none)
+		(layer "F.SilkS")
+		(uuid "e628e852-d71e-4b6b-9d9a-d7418c3343eb")
+	)
+	(fp_text user "${REFERENCE}**"
+		(at 0.635 0 90)
+		(layer "F.Fab")
+		(uuid "176420af-86da-46c8-8361-c2ff9e1a8f75")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+			)
+		)
+	)
+	(pad "1" thru_hole rect
+		(at 0 0)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "d9b557cd-e5a9-4b58-95fc-fedb0e8ab99a")
+	)
+	(model "step/TSW-101-07-L-S.stp"
+		(offset
+			(xyz 0 0 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+)

samtec.pretty/PinHeader_1x02_0.1in_TSW-102-07-L-S.kicad_mod

@@ -1,18 +1,147 @@
 (footprint "PinHeader_1x02_0.1in_TSW-102-07-L-S"
-  (version 20221029)
-  (generator pcbnew)
-  (layer "F.Cu")
-  (attr smd)
-  (descr "Header, Male, 1x02, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
-  (tags "header pin")
-  (fp_text reference "REF**" (at 0.0 -2.032 0) (layer "F.SilkS") (effects (font (size 0.7619999999999999 0.7619999999999999) (thickness 0.17779999999999999))) )
-  (fp_text value "VAL**" (at -0.635 1.27 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
-  (fp_text user "${REFERENCE}**" (at 0.635 1.27 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
-  (fp_rect (start -1.27 -1.27) (end 1.27 3.81) (stroke (width 0.17779999999999999) (type default)) (fill none) (layer "F.SilkS") )
-  (fp_line (start -1.27 1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
-  (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
-  (pad "1" thru_hole rect (at 0.0 0.0) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-102-07-L-S.stp" (offset (xyz 0.0 1.27 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-  (pad "2" thru_hole circle (at 0.0 2.54) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-102-07-L-S.stp" (offset (xyz 0.0 1.27 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-)
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(descr "Header, Male, 1x02, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
+	(tags "header pin")
+	(property "Reference" "REF**"
+		(at 0 -2.032 0)
+		(layer "F.SilkS")
+		(uuid "9ec3ba1e-dd85-4edc-b2ba-53e2bee2a7fb")
+		(effects
+			(font
+				(size 0.762 0.762)
+				(thickness 0.1778)
+			)
+		)
+	)
+	(property "Value" "VAL**"
+		(at -0.635 1.27 90)
+		(layer "F.Fab")
+		(uuid "5db18a84-0e10-442d-b4a0-e6cbb0675b87")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "c771cfb0-cea5-49ec-a268-09277cf8c5a0")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "57e4a6d4-46de-444a-be3d-7a35d18f458c")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "bcbbc288-9ac4-4fd4-acbe-33b5f401beef")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr through_hole)
+	(fp_line
+		(start -1.27 1.27)
+		(end 1.27 1.27)
+		(stroke
+			(width 0.1778)
+			(type solid)
+		)
+		(layer "F.SilkS")
+		(uuid "85700b88-428e-4a83-b86f-428f89dbff84")
+	)
+	(fp_line
+		(start 1.27 -1.27)
+		(end 1.27 1.27)
+		(stroke
+			(width 0.1778)
+			(type solid)
+		)
+		(layer "F.SilkS")
+		(uuid "b56f842a-6b80-4193-ab1b-6132ac989d2f")
+	)
+	(fp_rect
+		(start -1.27 -1.27)
+		(end 1.27 3.81)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(fill none)
+		(layer "F.SilkS")
+		(uuid "cf9a0146-1bf5-40fa-a482-0dcc9c53143e")
+	)
+	(fp_text user "${REFERENCE}**"
+		(at 0.635 1.27 90)
+		(layer "F.Fab")
+		(uuid "035cd0af-f8fa-4530-b766-03dca5fc1346")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+			)
+		)
+	)
+	(pad "1" thru_hole rect
+		(at 0 0)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "ca650439-912b-4a51-ab06-3d5aca29113d")
+	)
+	(pad "2" thru_hole circle
+		(at 0 2.54)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "dca9a986-385b-4436-9c97-1b41885da474")
+	)
+	(model "step/TSW-102-07-L-S.stp"
+		(offset
+			(xyz 0 1.27 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+	(model "step/TSW-102-07-L-S.stp"
+		(offset
+			(xyz 0 1.27 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+)

samtec.pretty/PinHeader_1x03_0.1in_TSW-103-07-L-S.kicad_mod

@@ -1,20 +1,166 @@
 (footprint "PinHeader_1x03_0.1in_TSW-103-07-L-S"
-  (version 20221029)
-  (generator pcbnew)
-  (layer "F.Cu")
-  (attr smd)
-  (descr "Header, Male, 1x03, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
-  (tags "header pin")
-  (fp_text reference "REF**" (at 0.0 -2.032 0) (layer "F.SilkS") (effects (font (size 0.7619999999999999 0.7619999999999999) (thickness 0.17779999999999999))) )
-  (fp_text value "VAL**" (at -0.635 2.54 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
-  (fp_text user "${REFERENCE}**" (at 0.635 2.54 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
-  (fp_rect (start -1.27 -1.27) (end 1.27 6.35) (stroke (width 0.17779999999999999) (type default)) (fill none) (layer "F.SilkS") )
-  (fp_line (start -1.27 1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
-  (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
-  (pad "1" thru_hole rect (at 0.0 0.0) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-103-07-L-S.stp" (offset (xyz 0.0 2.54 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-  (pad "2" thru_hole circle (at 0.0 2.54) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-103-07-L-S.stp" (offset (xyz 0.0 2.54 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-  (pad "3" thru_hole circle (at 0.0 5.08) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-103-07-L-S.stp" (offset (xyz 0.0 2.54 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-)
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(descr "Header, Male, 1x03, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
+	(tags "header pin")
+	(property "Reference" "REF**"
+		(at 0 -2.032 0)
+		(layer "F.SilkS")
+		(uuid "7b31a04b-fd07-4b86-9b9f-c38b4c255910")
+		(effects
+			(font
+				(size 0.762 0.762)
+				(thickness 0.1778)
+			)
+		)
+	)
+	(property "Value" "VAL**"
+		(at -0.635 2.54 90)
+		(layer "F.Fab")
+		(uuid "bcde9e6f-8482-447a-9dd8-250b2c1cf4cc")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "be109a80-11aa-403e-8a44-5ffbebc34e23")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "1428af0b-ba9c-4113-9299-7da076b602a1")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "3bd6a467-7d33-48cd-a23d-8e3bfa5bbac3")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr through_hole)
+	(fp_line
+		(start -1.27 1.27)
+		(end 1.27 1.27)
+		(stroke
+			(width 0.1778)
+			(type solid)
+		)
+		(layer "F.SilkS")
+		(uuid "c6ee5585-dd25-4e84-8aa9-7cdbeeda34c9")
+	)
+	(fp_line
+		(start 1.27 -1.27)
+		(end 1.27 1.27)
+		(stroke
+			(width 0.1778)
+			(type solid)
+		)
+		(layer "F.SilkS")
+		(uuid "7b4dbd97-4c05-49fc-8979-4c54e7d677dc")
+	)
+	(fp_rect
+		(start -1.27 -1.27)
+		(end 1.27 6.35)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(fill none)
+		(layer "F.SilkS")
+		(uuid "f19dece1-f1c8-48fd-a3bc-862d0b77d6e4")
+	)
+	(fp_text user "${REFERENCE}**"
+		(at 0.635 2.54 90)
+		(layer "F.Fab")
+		(uuid "38866a3d-f732-4e29-9c31-915930758988")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+			)
+		)
+	)
+	(pad "1" thru_hole rect
+		(at 0 0)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "dd5c5083-2a65-4d5c-af7d-ddc4ead2f8df")
+	)
+	(pad "2" thru_hole circle
+		(at 0 2.54)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "f01b11ed-065c-4f19-b253-1eeb689fe314")
+	)
+	(pad "3" thru_hole circle
+		(at 0 5.08)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "bf320981-cf1f-4cc1-8efc-84ec115ba870")
+	)
+	(model "step/TSW-103-07-L-S.stp"
+		(offset
+			(xyz 0 2.54 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+	(model "step/TSW-103-07-L-S.stp"
+		(offset
+			(xyz 0 2.54 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+	(model "step/TSW-103-07-L-S.stp"
+		(offset
+			(xyz 0 2.54 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+)

samtec.pretty/PinHeader_1x04_0.1in_TSW-104-07-L-S.kicad_mod

@@ -1,22 +1,185 @@
 (footprint "PinHeader_1x04_0.1in_TSW-104-07-L-S"
-  (version 20221029)
-  (generator pcbnew)
-  (layer "F.Cu")
-  (attr smd)
-  (descr "Header, Male, 1x04, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
-  (tags "header pin")
-  (fp_text reference "REF**" (at 0.0 -2.032 0) (layer "F.SilkS") (effects (font (size 0.7619999999999999 0.7619999999999999) (thickness 0.17779999999999999))) )
-  (fp_text value "VAL**" (at -0.635 3.81 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
-  (fp_text user "${REFERENCE}**" (at 0.635 3.81 90) (layer "F.Fab") (effects (font (size 0.635 0.635) (thickness 0.127))) )
-  (fp_rect (start -1.27 -1.27) (end 1.27 8.89) (stroke (width 0.17779999999999999) (type default)) (fill none) (layer "F.SilkS") )
-  (fp_line (start -1.27 1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
-  (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.17779999999999999))
-  (pad "1" thru_hole rect (at 0.0 0.0) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-104-07-L-S.stp" (offset (xyz 0.0 3.81 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-  (pad "2" thru_hole circle (at 0.0 2.54) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-104-07-L-S.stp" (offset (xyz 0.0 3.81 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-  (pad "3" thru_hole circle (at 0.0 5.08) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-104-07-L-S.stp" (offset (xyz 0.0 3.81 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-  (pad "4" thru_hole circle (at 0.0 7.62) (size 1.9049999999999998 1.9049999999999998) (drill 1.016) (layers *.Cu *.Mask))
-  (model "step/TSW-104-07-L-S.stp" (offset (xyz 0.0 3.81 0)) (scale (xyz 1 1 1)) (rotate (xyz -90 0 90)) )
-)
+	(version 20240108)
+	(generator "pcbnew")
+	(generator_version "8.0")
+	(layer "F.Cu")
+	(descr "Header, Male, 1x04, vertical, 10 µin (0.25 µm) Gold on post, Matte Tin on tail")
+	(tags "header pin")
+	(property "Reference" "REF**"
+		(at 0 -2.032 0)
+		(layer "F.SilkS")
+		(uuid "50b9221e-0ec4-4a2a-bb79-4b8278797fa7")
+		(effects
+			(font
+				(size 0.762 0.762)
+				(thickness 0.1778)
+			)
+		)
+	)
+	(property "Value" "VAL**"
+		(at -0.635 3.81 90)
+		(layer "F.Fab")
+		(uuid "cfdb3fd3-24b5-46c9-ac85-3b46c6bbcb14")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+			)
+		)
+	)
+	(property "Footprint" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "aad7dcf3-c7a3-404f-96f2-9bf36aed07b6")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "ef91f347-ce84-409b-85a2-1a827f2f116a")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 0 0)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "349fc74a-fdd8-4dc3-89e8-a2192cb58eaa")
+		(effects
+			(font
+				(size 1.27 1.27)
+				(thickness 0.15)
+			)
+		)
+	)
+	(attr through_hole)
+	(fp_line
+		(start -1.27 1.27)
+		(end 1.27 1.27)
+		(stroke
+			(width 0.1778)
+			(type solid)
+		)
+		(layer "F.SilkS")
+		(uuid "d184bb3d-4681-4da1-89f6-1f94255e8f56")
+	)
+	(fp_line
+		(start 1.27 -1.27)
+		(end 1.27 1.27)
+		(stroke
+			(width 0.1778)
+			(type solid)
+		)
+		(layer "F.SilkS")
+		(uuid "e019dc81-76fe-4c02-9e70-fb6459619bd9")
+	)
+	(fp_rect
+		(start -1.27 -1.27)
+		(end 1.27 8.89)
+		(stroke
+			(width 0.1778)
+			(type default)
+		)
+		(fill none)
+		(layer "F.SilkS")
+		(uuid "d33370fe-2368-4138-8a32-54b35e90e4e6")
+	)
+	(fp_text user "${REFERENCE}**"
+		(at 0.635 3.81 90)
+		(layer "F.Fab")
+		(uuid "8a4f0730-f66a-42c4-ab0a-63c122277a82")
+		(effects
+			(font
+				(size 0.635 0.635)
+				(thickness 0.127)
+			)
+		)
+	)
+	(pad "1" thru_hole rect
+		(at 0 0)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "86a0a6d8-b24b-48a6-9b25-cb3af4f0b94d")
+	)
+	(pad "2" thru_hole circle
+		(at 0 2.54)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "c5cd5c32-075a-40d1-80a5-84d8d43665f0")
+	)
+	(pad "3" thru_hole circle
+		(at 0 5.08)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "e1a56a2d-51a6-40a2-8d76-1f604efe5bbe")
+	)
+	(pad "4" thru_hole circle
+		(at 0 7.62)
+		(size 1.905 1.905)
+		(drill 1.016)
+		(layers "*.Cu" "*.Mask")
+		(remove_unused_layers no)
+		(uuid "e2884e14-ec91-4a75-9ec1-0682245d873b")
+	)
+	(model "step/TSW-104-07-L-S.stp"
+		(offset
+			(xyz 0 3.81 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+	(model "step/TSW-104-07-L-S.stp"
+		(offset
+			(xyz 0 3.81 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+	(model "step/TSW-104-07-L-S.stp"
+		(offset
+			(xyz 0 3.81 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+	(model "step/TSW-104-07-L-S.stp"
+		(offset
+			(xyz 0 3.81 0)
+		)
+		(scale
+			(xyz 1 1 1)
+		)
+		(rotate
+			(xyz -90 0 90)
+		)
+	)
+)

spice.kicad_sym

@@ -36,7 +36,7 @@
     (property "Spice_Netlist_Enabled" "Y" (id 11) (at 0 0 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Spice_Lib_File" "/home/brendan/Documents/tempsync/projects/0000_KiCad/libraries/spice/Ad8038.cir" (id 12) (at 0 0 0)
+    (property "Spice_Lib_File" "./spice/Ad8038.cir" (id 12) (at 0 0 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (property "ki_description" "Spice, OpAmp" (id 13) (at 0 0 0)

spice/generic/varistor.lib

@@ -0,0 +1,9 @@
+*BEGIN MODEL VARISTOR
+*//////////////////////////////////////////////////////////////////////
+* (C) Brendan Haines
+*/////////////////////////////////////////////////////////////////////
+.SUBCKT VARISTOR IN_P IN_N R_P R_N PARAMS: gain=1
+*/////////////////////////////////////////////////////
+R R_P R_N {(V(IN_P) - V(IN_N)) * gain + 1n}
+.ENDS
+* END MODEL VARISTOR

spice/ti/LMH6611.lib

@@ -0,0 +1,207 @@
+*Rev.a July,2008
+*BEGIN MODEL LMH6611
+*//////////////////////////////////////////////////////////////////////
+* (C) National Semiconductor, Corporation.
+* Models developed and under copyright by:
+* National Semiconductor, Corporation.  
+*/////////////////////////////////////////////////////////////////////
+* Legal Notice:  
+* The model may be copied, and distributed without any modifications;
+* however, reselling or licensing the material is illegal.
+* We reserve the right to make changes to the model without prior notice. 
+* Pspice Models are provided "AS IS, WITH NO WARRANTY OF ANY KIND" 
+*////////////////////////////////////////////////////////////////////
+*
+* PINOUT ORDER +IN -IN +V -V OUT
+* PINOUT ORDER  3   2   8  4  1
+.SUBCKT LMH6611 3 2 8 4 1
+*/////////////////////////////////////////////////////
+* USE V139 BELOW TO ADJUST OFFSET IF DESIRED
+* PRESENT VALUE OF -77 UV GIVES TYPICAL OFFSET
+* NOTE THAT VOS CHANGES VIA CMRR,PSRR, AND TCVOS
+* FOR BOTH THE REAL PART AND THE MODEL
+* ADJUST UP OR DOWN FROM -77 UV
+V139 14 29 -77U
+*//////////////////////////////////////////////////////////////
+* MODEL FEATURES INCLUDE OUTPUT SWING, OUTPUT CURRENT THRU
+* THE SUPPLY RAILS, OUTPUT CURRENT LIMIT, OPEN LOOP GAIN
+* AND PHASE WITH RL AND CL EFFECTS, SLEW RATE, COMMON MODE
+* REJECTION WITH FREQ EFFECTS, POWER SUPPLY REJECTION WITH
+* FREQ EFFECTS, INPUT VOLTAGE NOISE WITH 1/F, INPUT CURRENT
+* NOISE WITH 1/F, INPUT BIAS CURRENT, INPUT COMMON MODE
+* RANGE, INPUT OFFSET VOLTAGE WITH TEMPERATURE EFFECTS, AND
+* QUIESCENT CURRENT VS VOLTAGE AND TEMPERATURE.
+*//////////////////////////////////////////////////////
+D17 9 0 DIN
+D18 10 0 DIN
+I14 0 9 0.1E-3
+I15 0 10 0.1E-3
+D19 11 0 DVN
+D20 12 0 DVN
+I16 0 11 0.1E-3
+I17 0 12 0.1E-3
+E15 13 2 11 12 2.6
+G5 14 13 9 10 3E-4
+E16 15 0 16 0 1
+E17 17 0 18 0 1
+E18 19 0 20 0 1
+R56 15 21 1E6
+R57 17 22 1E6
+R58 19 23 1E6
+R59 0 21 10
+R60 0 22 10
+R61 0 23 10
+E19 24 25 23 0 1E-4
+R62 26 20 1E3
+R63 20 27 1E3
+C15 15 21 1E-12
+C16 17 22 1E-12
+C17 19 23 1E-12
+E20 28 24 22 0 -1
+E21 29 28 21 0 2
+R64 0 30 1E12
+V52 30 0 1
+G12 14 13 31 0 1.45E-14
+R136 0 31 10E3
+R137 0 31 10E3
+R138 25 24 1E9
+R139 24 28 1E9
+R140 28 29 1E9
+E54 27 0 14 0 1
+E55 26 0 13 0 1
+C23 14 13 0.25E-12
+E57 25 3 32 0 2.25E-4
+R146 25 3 1E9
+R147 0 30 1E12
+Q41 33 34 18 QLN
+R148 34 35 1E3
+R149 36 37 1E3
+R150 38 16 1
+R151 18 39 1
+R153 40 41 5
+R154 42 16 1
+R155 18 43 1
+D22 44 8 DD
+D23 4 44 DD
+E58 18 0 4 0 1
+E59 16 0 8 0 1
+R156 4 8 30E3
+E60 45 18 16 18 0.5
+D24 40 16 DD
+D25 18 40 DD
+R157 46 47 100
+R158 48 49 100
+G14 40 45 50 45 1E-3
+R159 45 40 2E6
+C24 41 51 3E-12
+C25 44 0 1E-12
+D26 49 33 DD
+D27 52 47 DD
+Q42 52 37 16 QLP
+R160 44 53 1
+R161 54 44 1
+E61 55 45 56 57 1
+R162 55 50 1E4
+C26 50 45 0.025P
+G15 58 45 40 45 -1E-3
+G16 45 59 40 45 1E-3
+G17 45 60 61 18 1E-3
+G18 62 45 16 63 1E-3
+D28 62 58 DD
+D29 59 60 DD
+R163 58 62 100E6
+R164 60 59 100E6
+R165 62 16 1E3
+R166 18 60 1E3
+R167 59 45 1E6
+R168 60 45 1E6
+R169 45 62 1E6
+R170 45 58 1E6
+G19 8 4 30 0 2.72E-3
+R171 45 50 1E9
+R172 46 16 1E9
+R173 18 48 1E9
+G20 63 61 30 0 0.25E-3
+I22 8 4 0.5E-16
+L2 44 1 3E-9
+R175 44 1 1E3
+R176 63 16 1E8
+R177 18 61 1E8
+R178 39 49 1E8
+R179 38 47 1E8
+R180 0 30 1E9
+E99 16 36 8 38 4.8
+E100 35 18 39 4 4.8
+E124 51 0 44 0 1
+R719 40 51 2E8
+I30 0 64 1E-3
+D46 64 0 DD
+R778 0 64 10E6
+V127 64 32 0.65
+R779 0 32 10E6
+Q52 53 47 38 QLP
+Q53 54 49 39 QLN
+Q54 61 61 43 QLN
+Q55 63 63 42 QLP
+E144 16 46 16 62 1
+E145 48 18 60 18 1
+Q56 65 14 66 QIN
+Q57 67 13 68 QIN
+Q58 57 69 65 QIN
+Q59 56 70 67 QIN
+Q60 69 69 16 QIP
+Q61 14 69 16 QIP
+Q62 70 70 16 QIP
+Q63 13 70 16 QIP
+R780 57 71 1200
+R781 56 71 1200
+R782 72 66 350
+R783 72 68 350
+Q64 72 73 74 QTN
+I33 0 75 1E-3
+D49 75 0 DD
+R787 0 75 10E6
+V130 75 76 1.2301
+R788 0 76 10E6
+E150 77 0 76 0 -1.75
+R789 0 77 10E6
+R790 78 77 10E6
+M3 78 79 0 0 NEN L=2U W=1000U
+G22 74 73 78 0 12E-6
+V132 80 0 1
+R791 80 79 1E6
+M4 79 81 0 0 NEN L=2U W=100U
+V133 81 0 1
+C109 57 56 70F
+V134 71 16 0.4
+C110 0 14 2E-12
+C111 13 0 2E-12
+G23 8 0 53 44 1
+G24 4 0 44 54 -1
+G25 8 4 32 0 -2.4E-3
+Q65 82 82 14 QIP
+Q66 83 82 82 QIP
+Q67 84 84 83 QIP
+Q68 14 14 84 QIP
+R792 13 83 50
+V136 74 18 -0.9
+J1 85 14 85 JNC
+J2 85 13 85 JNC
+J3 14 86 14 JNC
+J4 13 86 13 JNC
+V137 16 85 1.65
+V138 86 18 0
+I34 14 0 5.7E-6
+I35 13 0 5.7E-6
+.MODEL DD D
+.MODEL QIN NPN BF=235 RB=900
+.MODEL QIP PNP BF=235
+.MODEL QTN NPN
+.MODEL DVN D KF=2.5E-15
+.MODEL DIN D KF=8E-15
+.MODEL QLN NPN
+.MODEL QLP PNP
+.MODEL JNC NJF IS=1E-18
+.MODEL NEN NMOS KP=200U VTO=0.5 IS=1E-18
+.ENDS
+* END MODEL LMH6611

spice/ti/LMR70503_TRANS.lib

@@ -0,0 +1,279 @@
+*$
+* LMR70503
+*****************************************************************************
+* (C) Copyright 2013 Texas Instruments Incorporated. All rights reserved.
+*****************************************************************************
+** This model is designed as an aid for customers of Texas Instruments.
+** TI and its licensors and suppliers make no warranties, either expressed
+** or implied, with respect to this model, including the warranties of
+** merchantability or fitness for a particular purpose.  The model is
+** provided solely on an "as is" basis.  The entire risk as to its quality
+** and performance is with the customer
+*****************************************************************************
+*
+* This model is subject to change without notice. Texas Instruments
+* Incorporated is not responsible for updating this model.
+*
+*****************************************************************************
+*
+** Released by: WEBENCH Design Center, Texas Instruments Inc.
+* Part: LMR70503
+* Date: 20JUNE2013
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* Simulator Version: 16.2.0.p001
+* EVM Order Number: AN-2264 LMR70503
+* EVM Users Guide: SNVU155A – Revised April 2013
+* Datasheet: SNVS850A – REVISED APRIL 2013
+*
+* Model Version: Final 1.00
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*****************************************************************************
+.SUBCKT LMR70503_TRANS VIN EN GND VREF FB VOUT SW
+X_A6_minon S1tt S1tin ONE_SHOT Params: t=70 
+ES1t S1t 0 value={if((V(S1tin))>0.5,5,0)}
+X13  S1 36  S1tt AND2_BASIC_GEN	 
+C1 FB GND 1p IC=0
+X17  S2 45  S2tt AND2_BASIC_GEN 
+X18 R1t 45 INV_DELAY_BASIC_GEN 
+X_A6_minon19x S2tt S2tin ONE_SHOT Params: t=70 
+ES2t S2t 0 value={if(V(S2tin)>0.5,5,0)}
+X15 24 GND FBHYS COMPHYS_BASIC_GEN PARAMS:VDD=1 VTHRESH=100u 
++hyst=0.0001 VSS=-1
+E3 24 0 FB GND 1
+E_BDriver 9 GND value = { IF((V(PWMen)>1.5) ,0 ,V(VIN))}
+M1 SW 8 PS PS POWERMOS L=1u W=16670u 
+.MODEL POWERMOS PMOS AF=1 KP=20u IS=1E-14 CJ=0 RD=0 RS=0 VTO=0
+Rgate 9 8 3
+Rsense PS VIN 50m
+X5 41 57 UTD  PARAMS:  K=1 TD=150u 
+X7 52 32 49 R1tt AND3_BASIC_GEN
+X1 S2tt S1tt 12 10 NOR3_BASIC_GEN
+X2 10 R1tt R2 R3 12 NOR4_BASIC_GEN
+V2_Vref VREF GND DC=1.19
+E_B4_FBcomp S1 0 value ={IF((V(FBHYS)>0)&(V(SDbar) >1.5 ),3.3 ,0)}
+E_B5_ilimit ilimit 0 value = { IF((V(FB,GND) >0 ),320e-3 , 
++IF(( V(FB, GND) > -7.75e-3),320e-3 + V(FB,GND)*41.2 , 0.7e-3))}
+E2_cs 35 0 VIN PS 20
+E1 Qt 0 12 0 1
+E_B2 Qt1 0 value = { IF((V(Qt)>1.5) ,1 ,0)}
+E_B3 PWM 0 value = { IF((V(Qdelayt) > 0.5 ), 5  ,  0)}
+E_B6_ilimitcomp R1 0 value = { IF( V(isense) > V(ilimit), 5 , 0)}
+V3 R2 0 DC=0
+X_A3 50 28in ONE_SHOT Params: t=100 
+E28 28 0 value={if(V(28in)>0.5,5,0)}
+I1 0 vramp DC=100u
+C3 vramp 0 100p IC=0
+E_B7 30 0 value = { IF((V(vramp)>1.9 ) ,5 ,0)}
+X_A4 30 S2in ONE_SHOT Params: t=100 
+ES2 S2 0 value={if(V(S2in)>0.5,5,0)}
+S1 vramp 0 28 0 _S1_mod  
+.MODEL _S1_mod vswitch VT=0.5 VH=0.1 RON=100 ROFF=10Meg
+V4 R3 0 DC=0
+X20 S2t 49 INV_DELAY_BASIC_GEN 
+C5 12 0 10p IC=3.3
+C4 10 0 10p IC=0
+X4 Qt1 Qdelayt UTD  PARAMS:  K=1 TD=140n 
+X21 Qt SDbar 50 AND2_BASIC_GEN 
+R2 35 isense 1k
+D2 0 vramp _DLIMIT 
+.MODEL _DLIMIT D
+D3 vramp 16 _DLIMIT 
+X_A5_minoff R1in Tminoff R1tin Ctrl_one_shot
+ER1 R1in 0 VALUE= {if(V(R1) >2.5,1,0)}
+ER1t R1t 0 value={if((V(R1tin))>0.5,5,0)}
+V7 16 0 DC=2.5
+S2 GND VOUT SDbar 0 _S2_mod  
+.MODEL _S2_mod vswitch VT=1.5 VH=0.2 RON=100k ROFF=30
+X8 S1t 32 INV_DELAY_BASIC_GEN 
+X9 EN GND 41 COMPHYS_BASIC_GEN PARAMS:VDD=5 VTHRESH=0.93 
++hyst=0.16 VSS=0
+X10 VIN GND 39 COMPHYS_BASIC_GEN PARAMS:VDD=5 VTHRESH=2.55 
++hyst=0.1 VSS=0
+X11 46 39  SDbar AND2_BASIC_GEN 
+X12 SDbar PWM PWMen AND2_BASIC_GEN 
+X16 57 41 46 AND2_BASIC_GEN 
+C6 PWMen 0 10p
+X14 R1t 36 INV_DELAY_BASIC_GEN 
+C7 SDbar 0 10p IC=0
+C8 isense 0 10p IC=0
+E_E37 Toffvout 0 TABLE { V(VOUT) }
++((-5,250) (-3.3,330) (-2.5,400)(-1.5,540) (-0.9,720)
++ (-0.45,1000) (0,1200))
+E_B10 Tminoff 0 value = {V(Toffvout) +  (V(VIN) - 2.8)*60}
+X24 R1 55 52 OR2_BASIC_GEN
+E_E17 VGSDummy 0 TABLE { V(VIN) } 
++ ( (0,2.5) (2.5,2.5) (2.8,2.8) (5.5,3.6) (6,3.6) )
+E_E27 VDSDummy 0 TABLE { V(FB) } 
++( (-1,4) (-40e-3,4) (-30e-3,3.2)  (-20e-3,2) (-12e-3,0.65) 
++(-5e-3,0) (0,0))
+M2 58 VGSDummy 0 0 _DUMMYLOAD L=1u W=50u 
+.MODEL _DUMMYLOAD NMOS (  VTO=0 KP=2E-5 GAMMA=0 PHI=600M LAMBDA=0 
++      RD=0 RS=0 RG=0 RB=0 RDS=0 
++      CBD=0 CBS=0 IS=1E-14 N=1 PB=800M 
++      CGSO=0 CGDO=0 CGBO=0 RSH=0 CJ=0 
++      MJ=500M CJSW=0 MJSW=500M JS=0 TOX=1e-7 
++      LD=0 UO=600 FC=500M TPG=1 
++      NSS=0 TNOM=27 KF=0 AF=1 L=1U 
++      W=50U )
+E_B8 55 0 value = { IF(V(ilimit) < 1e-3, 5 , 0)}
+G1 GND VOUT 58 VDSDummy -1
+R1 VDSDummy 58 1
+.ends LMR70503_TRANS
+*$
+.SUBCKT UTD 1 2  PARAMS: K=1 TD=1
+RIN 1 0 1E15
+E1 3 0 1 0 {K}
+T1 3 0 2 0 Z0=1 TD={TD}
+R1 2 0 1
+.ENDS UTD
+*$
+.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5 
+E_ABMGATE    YINT 0 VALUE ={IF(V(A) > {VTHRESH}  &  
++ V(B) > {VTHRESH},{VDD},{VSS})}
+RINT YINT Y 1
+CINT Y 0 1n
+.ENDS AND2_BASIC_GEN
+*$
+.SUBCKT INV_DELAY_BASIC_GEN A  Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5 
++DELAY = 1n 
+E_ABMGATE1    YINT1 0 VALUE ={IF(V(A) > {VTHRESH} , 
++ {VSS},{VDD})}
+RINT2 YINT1 Y 1
+CINT2 Y 0 1n
+.ENDS INV_DELAY_BASIC_GEN
+*$
+.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5 
+E_ABMGATE    YINT 0 VALUE ={IF(V(A) > {VTHRESH}  |  
++ V(B) > {VTHRESH},{VDD},{VSS})}
+RINT YINT Y 1
+CINT Y 0 1n
+.ENDS OR2_BASIC_GEN
+*$
+.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5 
+E_ABMGATE    YINT 0 VALUE ={IF(V(A) > {VTHRESH}  &  
++ V(B) > {VTHRESH} &
++ V(C) > {VTHRESH},{VDD},{VSS})}
+RINT YINT Y 1
+CINT Y 0 1n
+.ENDS AND3_BASIC_GEN
+*$
+.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5 
+E_ABMGATE    YINT 0 VALUE ={IF(V(A) > {VTHRESH}  |  
++ V(B) > {VTHRESH} |
++ V(C) > {VTHRESH},{VSS},{VDD})}
+RINT YINT Y 1
+CINT Y 0 1n
+.ENDS NOR3_BASIC_GEN
+*$
+.SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=5 VSS=0.3 VTHRESH=1.5 
+E_ABMGATE    YINT 0 VALUE ={IF(V(A) > {VTHRESH}  |  
++ V(B) > {VTHRESH} |
++ V(C) > {VTHRESH} |
++ V(D) > {VTHRESH},{VSS},{VDD})}
+RINT YINT Y 1
+CINT Y 0 1n
+.ENDS NOR4_BASIC_GEN
+*$
+.SUBCKT COMPHYS_BASIC_GEN INP INM OUT PARAMS: VDD=1 VSS=-1 
++VTHRESH=100u HYST=100u
+EIN INP1 INM1 INP INM 1 
+EHYS INP1 INP2 VALUE ={ IF( V(1) > 0.1,{VTHRESH-HYST},{VTHRESH})}
+EOUT OUT 0 VALUE ={ IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
+R1 OUT 1 1
+C1 1 0 5n
+RINP1 INP1 0 1K
+.ENDS COMPHYS_BASIC_GEN
+*$
+.subckt one_shot in out params:  t=100
+s_s1    meas 0 reset2 0 s1
+e_abm1  ch 0 value={ if( v(in)>0.5 | v(out)>0.5,1,0)}
+r_r2    reset2 reset  0.1  
+e_abm3  out 0 value={ if( v(meas)<0.5 & v(ch)>0.5,1,0)}
+r_r1    meas ch  {t} 
+c_c2    0 reset2  1.4427n  
+c_c1    0 meas  1.4427n  
+e_abm2  reset 0 value={ if(v(ch)<0.5,1,0)}
+.model s1 vswitch roff=1e+009 ron=1 voff=0.25 von=0.75
+.ends one_shot
+*$
+.SUBCKT Ctrl_one_shot IN Ctrl_input  OUT  
+X_U586  IN VIN_ONE ONE_SHOT PARAMS:  t=200
+X_U584  VIN_ONE RESET OUT RESET_OUT SRLATCHRHP_BASIC_GEN 
++PARAMS: VDD=5 VSS=0 VTHRESH=0.5
+E_ABM21 RESET 0 VALUE = { if(V(T_RAMP)>V(CTRL_INPUT_N) ,5,0)}
+X_S1   RESET_OUT 0 T_RAMP 0 Ctrl_one_shot_S1 
+R_R5   0 OUT  1G TC=0,0 
+E_ABM23 CTRL_INPUT_N 0 VALUE ={(V(CTRL_INPUT1)*1E06)}
+C_C2   0 T_RAMP  1n  TC=0,0 
+I_I1   0 T_RAMP DC 1m     
+E_A22 Ctrl_input1 0 TABLE { V(Ctrl_input)} = ((-100,250n) (0,250n) 
++(250,250n) (330,330n) (400,400n) (540,540n) (720,720n) (850,850n) 
++(1000,1000n ) (1500,1500n) (2000,1500n) )
+.ENDS Ctrl_one_shot
+*$
+.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
+GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}
+CQint Qint 0 1n
+RQint Qint 0 1000MEG
+D_D10 Qint MY5 D_D1
+V1 MY5 0 {VDD}
+D_D11 MYVSS Qint D_D1
+V2 MYVSS 0 {VSS} 
+EQ Qqq 0 Qint 0 1
+X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS:VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
+RQq Qqqd1 Q 1
+EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
+RQb Qbr QB 1 
+Cdummy1 Q 0 1n 
+Cdummy2 QB 0 1n
+.IC V(Qint) {VSS}
+.ENDS SRLATCHRHP_BASIC_GEN
+*$
+.SUBCKT BUF_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
+E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , 
++ {VDD},{VSS})}}
+RINT YINT Y 1
+CINT Y 0 1n
+.ENDS BUF_BASIC_GEN
+*$
+.MODEL D_D1 D( IS=1e-15 Rs=0.005 N=.1  )
+*$
+.subckt Ctrl_one_shot_S1 1 2 3 4  
+S_S1   3 4 1 2 _S1
+RS_S1  1 2 1G
+.MODEL _S1 VSWITCH Roff=1e9 Ron=1.0m Voff=0.5V Von=1.5V
+.ends Ctrl_one_shot_S1
+*$
+.SUBCKT CESR IN OUT
++ PARAMs:  C=100u ESR=0.01 IC=0
+C	IN 1  {C} IC={IC}
+RESR	1 OUT {ESR}
+.ENDS CESR
+*$
+.SUBCKT LDCR IN OUT
++ PARAMs:  L=1u DCR=0.01 IC=0
+L	IN 1  {L} IC={IC}
+RDCR	1 OUT {DCR}
+.ENDS LDCR
+*$
+.MODEL D1N6650 D BV=22 CJO=3.874e-11 EG=0.69 IS=1.028e-5
++ M=.4641 N=0.9172 RS=0.3489 VJ=0.3188 XTI=2
+*$
+.END
+*$
+
+
+
+
+
+
+
+

spice/ti/OPA810.lib

@@ -0,0 +1,356 @@
+* OPA810 - Rev. A
+* Created by Sean Cashin; 2020-06-11
+* Created with Green-Williams-Lis Current Sense Amp Macro-model Architecture
+* Copyright 2020 by Texas Instruments Corporation
+******************************************************
+* MACRO-MODEL SIMULATED PARAMETERS:
+******************************************************
+* AC PARAMETERS
+**********************
+* CLOSED-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zout vs. Freq.)
+* CLOSED-LOOP GAIN AND PHASE VS. FREQUENCY  WITH RL, CL EFFECTS (Acl vs. Freq.)
+* COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR vs. Freq.)
+* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR vs. Freq.)
+* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en vs. Freq.)
+**********************
+* DC PARAMETERS
+**********************
+* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
+* GAIN ERROR (Eg)
+* INPUT BIAS CURRENT VS. INPUT COMMON-MODE VOLTAGE (Ib vs. Vcm)
+* INPUT OFFSET VOLTAGE VS. TEMPERATURE (Vos vs. Temp)
+* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vout vs. Iout)
+* SHORT-CIRCUIT OUTPUT CURRENT (Isc)
+* QUIESCENT CURRENT (Iq)
+**********************
+* TRANSIENT PARAMETERS
+**********************
+* SLEW RATE (SR)
+* SETTLING TIME VS. CAPACITIVE LOAD (ts)
+* OVERLOAD RECOVERY TIME (tor)
+******************************************************
+.subckt OPA810 IN+ IN- OUT VCC VEE
+******************************************************
+.MODEL R_NOISE RES (T_ABS=0)
+.MODEL R_NOISELESS RES (T_ABS=-273.15)
+C_C12         MID N45892  1E-15   
+C_C13         N45974 MID  1E-15   
+C_C17         MID N68747  1E-12   
+C_C18         MID N68594  1E-12   
+C_C19         MID SW_OL_OPA810  1E-12   
+C_C1A         N725398 N725428  15.92E-6   
+C_C1A1         N701935 N701965  3.537P   
+C_C1A10         N789898 N789912  342.3F   
+C_C1A4         N709083 N709113  63.66N   
+C_C1A9         N704975 N705005  83.77N   
+C_C1C1         N821901 N725762  159.2E-9   
+C_C1C3         N725214 N725836  26.53E-15   
+C_C1D         MID N725708  93.62E-15   
+C_C1_0         MID N79181  23.5E-9   
+C_C2         MID N694641  740E-12   
+C_C3         MID N694487  740E-12   
+C_C33         N406634 0  1E-15   
+C_C34         N317950 0  1   
+C_C35         N406794 0  1E-15   
+C_C36         N894736 N892256  227.4E-12   
+C_C7         N31014 MID  1E-15   
+C_C8         MID N35813  1E-15   
+C_C9         MID N38096  1E-15   
+C_C_CMN         MID ESDN  2.5E-12   
+C_C_CMP         ESDP MID  2.5E-12   
+C_C_DIFF         ESDN ESDP  0.5E-12   
+C_C_VCLP         VCLP MID  1E-12   
+C_C_VIMON         MID VIMON  1E-9   
+C_C_VOUT_S         MID VOUT_S  1E-9   
+E_E2         N91498 MID CL_CLAMP MID 1
+E_E3         N112292 MID OUT MID 1
+E_E6         MID 0 N317950 0 1
+G_G1         N725398 MID CL_CLAMP N516723 -90.91
+G_G10         N73852 MID N55875 MID -1
+G_G11         N55050 MID N56119 MID -1
+G_G16         CL_CLAMP MID N894736 MID -1E-3
+G_G2         N10570 N10561 N701965 MID -1E-3
+G_G36         VCC_B 0 VCC 0 -1
+G_G37         VEE_B 0 VEE 0 -1
+G_G54         N694641 MID N79181 MID -1
+G_G55         N701935 MID N789912 MID -222.22
+G_G56         N709083 MID VCC_B MID -1.265
+G_G58         N704975 MID VEE_B MID -1.664
+G_G59         N789898 MID ESDP MID -29.75M
+G_G6         N25816 N11984 N709113 N705005 -1E-3
+G_G60         N06456 MID N799160 MID -10E-6
+G_G61         ESDN MID N804105 MID -10E-6
+G_G62         N821901 MID N725428 MID -100
+G_G63         N892256 MID N694487 MID -1.3
+G_G7         N694487 MID N694641 MID -1
+G_G8         VCC_CLP MID N35813 MID -1E-3
+G_G9         VEE_CLP MID N38096 MID -1E-3
+G_GB         N725346 MID N725762 MID -25
+G_GD4         N725214 MID N725574 MID -0.3
+G_GD5         N725936 MID N725836 MID -166.7
+I_I_B         N06456 MID DC 2E-12  
+I_I_OS         ESDN MID DC 1E-12  
+I_I_Q         VCC VEE DC 1.9E-3  
+R_R1         ESDP IN+ R_NOISELESS 10E-3
+R_R10         ESDN N11991 R_NOISELESS 1E-3
+R_R107         VCC_B 0 R_NOISELESS 1
+R_R108         N317950 0 R_NOISELESS 1E12
+R_R109         VEE_B 0 R_NOISELESS 1
+R_R11         MID N725346 R_NOISELESS 1
+R_R110         VCC_B N406634 R_NOISELESS 1E-3
+R_R111         N406634 N317950 R_NOISELESS 1E6
+R_R112         N317950 N406794 R_NOISELESS 1E6
+R_R113         N406794 VEE_B R_NOISELESS 1E-3
+R_R133         N694487 MID R_NOISELESS 1
+R_R134         N694641 MID R_NOISELESS 1
+R_R135         N701935 MID R_NOISELESS 1
+R_R136         N704975 MID R_NOISELESS 1
+R_R137         MID N725398 R_NOISELESS 1
+R_R139         MID N725214 R_NOISELESS 1
+R_R140         MID N725936 R_NOISELESS 1
+R_R141         N789898 MID R_NOISELESS 1
+R_R145         MID N821901 R_NOISELESS 1
+R_R149         N892256 MID R_NOISELESS 1
+R_R150         N894736 MID R_NOISELESS 33.3
+R_R151         N892256 N894736 R_NOISELESS 10
+R_R1A         N725428 N725398 R_NOISELESS 10E3
+R_R1A1         N701935 N701965 R_NOISELESS 1E4
+R_R1A10         N789898 N789912 R_NOISELESS 1E8
+R_R1A11         MID N799160 R_NOISE 15
+R_R1A12         MID N804105 R_NOISE 15
+R_R1A3         N704975 N705005 R_NOISELESS 1E8
+R_R1A4         N709083 N709113 R_NOISELESS 1E8
+R_R1C1         N725762 N821901 R_NOISELESS 10E3
+R_R1C2         N725836 N725214 R_NOISELESS 1E4
+R_R1D1         N725708 N725574 R_NOISELESS 10E3
+R_R2         ESDN IN- R_NOISELESS 10E-3
+R_R21         N11984 N25816 R_NOISELESS 1E3
+R_R25         MID N28602 R_NOISELESS 1E9
+R_R26         N30136 MID R_NOISELESS 1E9
+R_R27         MID N30913 R_NOISELESS 1
+R_R28         N31014 N30913 R_NOISELESS 1E-3
+R_R29         N35669 VCC_B R_NOISELESS 1E3
+R_R2A1         N701965 MID R_NOISELESS 45.2
+R_R2A10         N705005 MID R_NOISELESS 19M
+R_R2A11         N789912 MID R_NOISELESS 465
+R_R2A13         MID N725428 R_NOISELESS 101
+R_R2A4         N709113 MID R_NOISELESS 25M
+R_R2C1         MID N725762 R_NOISELESS 416.7
+R_R2C3         MID N725836 R_NOISELESS 60.36
+R_R2D         N725574 N725346 R_NOISELESS 367.8E3
+R_R3         MID ESDP R_NOISELESS 1E12
+R_R30         N35813 N35669 R_NOISELESS 1E-3
+R_R31         VCC_CLP MID R_NOISELESS 1E3
+R_R32         N38050 VEE_B R_NOISELESS 1E3
+R_R33         N38096 N38050 R_NOISELESS 1E-3
+R_R34         VEE_CLP MID R_NOISELESS 1E3
+R_R4         ESDN MID R_NOISELESS 1E12
+R_R41         MID N50645 R_NOISELESS 1E9
+R_R42         N45856 MID R_NOISELESS 1
+R_R43         N45892 N45856 R_NOISELESS 1E-3
+R_R44         N45974 N45986 R_NOISELESS 1E-3
+R_R45         MID N45986 R_NOISELESS 1
+R_R46         MID N48550 R_NOISELESS 1E9
+R_R47         MID N73852 R_NOISELESS 1
+R_R48         MID N55050 R_NOISELESS 1
+R_R5         N709083 MID R_NOISELESS 1
+R_R56         N68747 OLN R_NOISELESS 100
+R_R57         N68594 OLP R_NOISELESS 100
+R_R58         N69264 MID R_NOISELESS 1
+R_R59         N69264 SW_OL_OPA810 R_NOISELESS 100
+R_R60         MID AOLNET R_NOISELESS 1E6
+R_R66         MID CL_CLAMP R_NOISELESS 1E3
+R_R8         N10561 N10570 R_NOISELESS 1E3
+R_R81         MID N110431 R_NOISELESS 1E9
+R_R83         MID N112292 R_NOISELESS 1E9
+R_R9         N10570 N11984 R_NOISELESS 1E-3
+R_RDUMMY1         MID N516723 R_NOISELESS 10E3
+R_RX1         N516723 N725936 R_NOISELESS 100E3
+R_R_VCLP         N91498 VCLP R_NOISELESS 100
+R_R_VIMON         VIMON N110431 R_NOISELESS 100
+R_R_VOUT_S         VOUT_S N112292 R_NOISELESS 100
+V_VCM_MAX         N30136 VCC_B 0.15
+V_VCM_MIN         N28602 VEE_B -0.2
+V_V_ISCN         N48550 MID -120
+V_V_ISCP         N50645 MID 120
+V_V_ORN         N55875 VCLP -68.5
+V_V_ORP         N56119 VCLP 37.13
+X_AOL_1         N31014 N11991 MID AOLNET AOL_1_OPA810 
+X_AOL_2         AOLNET MID MID N79181 AOL_2_OPA810 
+X_CLAWN         MID VIMON VEE_B N38050 CLAWN_OPA810 
+X_CLAWP         VIMON MID N35669 VCC_B CLAWP_OPA810 
+X_CL_AMP         N50645 N48550 VIMON MID N45856 N45986 CLAMP_AMP_LO_OPA810 
+X_CL_SRC         N45892 N45974 CL_CLAMP MID CL_SRC_OPA810 
+X_ESD_OUT         OUT VCC VEE ESD_OUT_OPA810 
+X_E_N         ESDP N06456 VNSE_OPA810 
+X_H1    N73852 N166377 OLN MID 08_OP_AMP_COMPLETE_H1_OPA810 
+X_H2    N55050 N166817 OLP MID 08_OP_AMP_COMPLETE_H2_OPA810 
+X_H3    OUT N516723 N110431 MID 08_OP_AMP_COMPLETE_H3_OPA810 
+X_IQ_N         MID VIMON MID VEE IQ_SRC_OPA810 
+X_IQ_P         VIMON MID VCC MID IQ_SRC_OPA810 
+X_OL_SENSE         MID N69264 N68747 N68594 OL_SENSE_OPA810 
+X_S1    OUT VCC_CLP N79181 MID 08_OP_AMP_COMPLETE_S1_OPA810 
+X_S2    VEE_CLP OUT N79181 MID 08_OP_AMP_COMPLETE_S2_OPA810 
+X_SW_OL         SW_OL_OPA810 MID N725398 N725428 SW_OL_OPA810 
+X_SW_OR         CLAMP N166377 N166817 SW_OR_OPA810 
+X_VCM_CLAMP         N25816 MID N30913 MID N30136 N28602 VCM_CLAMP_OPA810 
+X_VOS_DRIFT         N749288 N06456 VOS_DRIFT_OPA810 
+X_VOS_VS_VCM         N10561 N749288 VCC VEE VOS_VS_VCM_OPA810 
+.ENDS  OPA810
+*
+.SUBCKT 08_OP_AMP_COMPLETE_H1_OPA810 1 2 3 4  
+H_H1         3 4 VH_H1 1
+VH_H1         1 2 0V
+.ENDS  08_OP_AMP_COMPLETE_H1_OPA810
+*
+.SUBCKT 08_OP_AMP_COMPLETE_H2_OPA810 1 2 3 4  
+H_H2         3 4 VH_H2 -1
+VH_H2         1 2 0V
+.ENDS  08_OP_AMP_COMPLETE_H2_OPA810
+*
+.SUBCKT 08_OP_AMP_COMPLETE_H3_OPA810 1 2 3 4  
+H_H3         3 4 VH_H3 -1E3
+VH_H3         1 2 0V
+.ENDS  08_OP_AMP_COMPLETE_H3_OPA810
+*
+.SUBCKT 08_OP_AMP_COMPLETE_S1_OPA810 1 2 3 4  
+S_S1         3 4 1 2 _S1
+RS_S1         1 2 1G
+.MODEL         _S1 VSWITCH ROFF=200E3 RON=0.5 VOFF=-1 VON=0.4
+.ENDS  08_OP_AMP_COMPLETE_S1_OPA810
+*
+.SUBCKT 08_OP_AMP_COMPLETE_S2_OPA810 1 2 3 4  
+S_S2         3 4 1 2 _S2
+RS_S2         1 2 1G
+.MODEL         _S2 VSWITCH ROFF=200E3 RON=0.5 VOFF=-1 VON=0.4
+.ENDS  08_OP_AMP_COMPLETE_S2_OPA810
+*
+.SUBCKT AOL_1_OPA810 VC+ VC- IOUT+ IOUT-
+.PARAM GAIN = 1E-2
+.PARAM IPOS = .5
+.PARAM INEG = -.5
+G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
+.ENDS  AOL_1_OPA810
+*
+.SUBCKT AOL_2_OPA810 VC+ VC- IOUT+ IOUT-
+.PARAM GAIN = 1E-3
+.PARAM IPOS = 5.6
+.PARAM INEG = -5.6
+G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
+.ENDS  AOL_2_OPA810
+*
+.SUBCKT CLAMP_AMP_LO_OPA810 VC+ VC- VIN COM VO+ VO-
+.PARAM G=1
+GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
+GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
+.ENDS  CLAMP_AMP_LO_OPA810
+*
+.SUBCKT CLAWN_OPA810 VC+ VC- IOUT+ IOUT-
+G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
++(0, 10E-5)
++(30, 10E-5)
++(40, 10E-5)
++(60, 10E-5)
++(70, 10E-5)
++(80, 20E-5)
++(90, 30E-5)
++(100, 40E-5)
++(110, 500E-5)
++(120, 1000E-5)
+.ENDS  CLAWN_OPA810
+*
+.SUBCKT CLAWP_OPA810 VC+ VC- IOUT+ IOUT-
+G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
++(0, 8E-5)
++(30, 10E-5)
++(40, 28E-5)
++(50, 36E-5)
++(60, 50E-5)
++(70, 100E-5)
++(80, 200E-5)
++(90, 400E-5)
++(100, 800E-5)
++(110, 1600E-5)
++(120, 3200E-5)
+.ENDS  CLAWP_OPA810
+*
+.SUBCKT CL_SRC_OPA810 VC+ VC- IOUT+ IOUT-
+.PARAM GAIN = 1
+.PARAM IPOS = 16.8
+.PARAM INEG = -16.8
+G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
+.ENDS  CL_SRC_OPA810
+*
+.SUBCKT ESD_OUT_OPA810 OUT VCC VEE
+.MODEL ESD_SW VSWITCH(RON=50 ROFF=1E12 VON=500E-3 VOFF=450E-3)
+S1 VCC OUT OUT VCC ESD_SW
+S2 OUT VEE VEE OUT ESD_SW
+.ENDS  ESD_OUT_OPA810
+*
+.SUBCKT IQ_SRC_OPA810 VC+ VC- IOUT+ IOUT-
+.PARAM GAIN = 1E-3
+G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )}
+.ENDS  IQ_SRC_OPA810
+*
+.SUBCKT OL_SENSE_OPA810 1   2  3  4
+GSW+ 1 2 VALUE = {IF((V(3,1)>10E-3 | V(4,1)>10E-3),1,0)}
+.ENDS  OL_SENSE_OPA810
+*
+.SUBCKT SW_OL_OPA810 SW_OL_OPA810 MID CAP_L CAP_R
+.MODEL OL_SW VSWITCH(RON=1E-3 ROFF=1E9 VON=900E-3 VOFF=800E-3)
+S1 CAP_L CAP_R SW_OL_OPA810 MID OL_SW
+.ENDS  SW_OL_OPA810
+*
+.SUBCKT SW_OR_OPA810 CLAMP OLN OLP
+.MODEL OR_SW VSWITCH(RON=10E-3 ROFF=1E9 VON=10E-3 VOFF=0)
+S1 OLP CLAMP CLAMP OLP OR_SW
+S2 CLAMP OLN OLN CLAMP OR_SW
+.ENDS  SW_OR_OPA810
+*
+.SUBCKT VCM_CLAMP_OPA810 VIN+ VIN- IOUT- IOUT+ VP+ VP-
+.PARAM GAIN = 1
+G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
+.ENDS  VCM_CLAMP_OPA810
+*
+.SUBCKT VNSE_OPA810 1 2
+.PARAM FLW=0.1
+.PARAM NLF=1190
+.PARAM NVR=5.7
+.PARAM GLF={PWR(FLW,0.25)*NLF/1164}
+.PARAM RNV={1.184*PWR(NVR,2)}
+.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
+I1 0 7 10E-3
+I2 0 8 10E-3
+D1 7 0 DVN
+D2 8 0 DVN
+E1 3 6 7 8 {GLF}
+R1 3 0 1E9
+R2 3 0 1E9
+R3 3 6 1E9
+E2 6 4 5 0 10
+R4 5 0 {RNV}
+R5 5 0 {RNV}
+R6 3 4 1E9
+R7 4 0 1E9
+E3 1 2 3 4 1
+.ENDS  VNSE_OPA810
+*
+.SUBCKT VOS_DRIFT_OPA810 VOS+ VOS-
+.PARAM DC = 76.1E-6
+.PARAM POL = 1
+.PARAM DRIFT = 0.3E-6
+E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}
+.ENDS  VOS_DRIFT_OPA810
+*
+.SUBCKT VOS_VS_VCM_OPA810 V+ V- REF+ REF-
+E1 V+ 1 TABLE {(V(REF+, V-))} =
++(0.35, 450E-6)
++(0.4, 435E-6)
++(0.55, 275E-6)
++(0.65, 150E-6)
++(0.75, 75E-6)
++(0.85, 25E-6)
++(1, 0)
+V1 1 V- 0
+.ENDS  VOS_VS_VCM_OPA810
+*

spice/ti/TLV70012_PSPICE_TRANS/TLV70012-PSpiceFiles/SCHEMATIC1/trans.sim

@@ -0,0 +1,137 @@
+@OrCAD Simulation Server Version: 1.0
+
+@Settings: 0 1
+@General:
+ProfileName= "trans" 
+ProfileFile= "trans.sim" 
+Connectivity= "SCHEMATIC1.net" 
+NetlistFile= "trans.cir" 
+DataFile= "trans.dat" 
+OutFile= "trans.out" 
+Notes=
+@#$BEGINNOTES
+@#$ENDNOTES
+@End General
+@Analysis: 0 1
++0 0 0 0 
++0 "1m" 
++1 "" 
++2 "0" 
++3 "" 
++4 "" 
++5 "" 
++6 "" 
+@End Analysis
+@Analysis: 1 0
++2 0 0
++0 "" 
++1 "" 
++2 "" 
++3 "" 
++4 "" 
++5 "" 
+@End Analysis
+@Analysis: 2 0
++0 0
++0 "" 
++1 "" 
++2 "" 
++3 "" 
++4 "" 
++5 "" 
++6 "" 
++7 "" 
+@End Analysis
+@Analysis: 3 0
++0 0 0
++0 "" 
++1 "" 
++2 "" 
+@End Analysis
+@Analysis: 4 0
++0 0 1 0 0 0 0 0 0 0
++0 "" 
++1 "" 
++2 "" 
++3 "" 
++4 "" 
++5 "" 
++6 "" 
++7 "" 
+LoadFile 0 "" 
+SaveFile 0 "" 
+@End Analysis
+@Analysis: 5 0
++0 0
++0 "" 
++1 "" 
++2 "" 
++3 "" 
++4 "" 
++5 "" 
++6 "" 
++7 "" 
+@End Analysis
+@Analysis: 6 0
++1 
++0 "" 
+@End Analysis
+@Analysis: 7 0
++0 0
++0 "" 
++1 "" 
++2 "" 
++3 "" 
++4 "" 
++5 "" 
+@End Analysis
+@Analysis: 8 0
++0 
++0 "" 
++1 "" 
++2 "" 
++3 "" 
++4 "" 
++5 "" 
+@End Analysis
+@Analysis: 9 0
++0 "" 
+@End Analysis
+@Analysis: 10 0
++0 0
++0 "" 
++1 "" 
++2 "" 
++3 "" 
++4 "" 
++5 "" 
++6 "" 
++7 "" 
+@End Analysis
+@Analysis: 11 1
++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
++ 0 0 0 0 0 0 0 0 0
+@End Analysis
+@Analysis: 12 0
++2236960 0
+@End Analysis
+@Analysis: 13 1
++0 1 1 1
+@End Analysis
+@Analysis: 14 1
++1 1 1 "*" 
+@End Analysis
+@Analysis: 15 0
+@End Analysis
+@Analysis: 16 0
++0 "0" 
++1 "0" 
++2 "chkpt_default, , ," 
+@End Analysis
+@Analysis: 17 0
++0 "-1" 
++1 "" 
++2 "-1" 
++3 "-1" 
++4 "1" 
+@End Analysis

spice/ti/TLV70012_PSPICE_TRANS/TLV70012-PSpiceFiles/SCHEMATIC1/trans/trans.prb

@@ -0,0 +1,76 @@
+[DISPLAYS]
+BEGIN DISPLAY LAST SESSION
+ANALYSIS TRANSIENT_ANALYSIS
+SYMBOL ALWAYS
+TRACECOLORSCHEME NORMAL
+BEGIN ANAPLOT 1
+XBASE
+BEGIN XAXIS
+XAXISUSERNAME 0 (null)
+RANGEFLAG AUTO
+TYPE LINEAR
+UNIT s
+BEGIN GRIDS
+AUTOMATIC
+MAJORNUMBERS
+MAJORSTYLE LINES
+MAJORPATTERN SOLID
+MINORSTYLE LINES
+MINORPATTERN DOT
+END GRIDS
+END XAXIS
+BEGIN YAXIS 1
+YAXISSIDE LEFT
+ACTIVE
+RANGEFLAG AUTO
+TYPE LINEAR
+UNIT V
+BEGIN GRIDS
+AUTOMATIC
+MAJORNUMBERS
+MAJORSTYLE LINES
+MAJORPATTERN SOLID
+MINORSTYLE LINES
+MINORPATTERN DOT
+END GRIDS
+BEGIN TRACE V(Vout)
+MARKERID 1
+END TRACE V(Vout)
+END YAXIS 1
+END ANAPLOT 1
+BEGIN ANAPLOT 2
+ACTIVE
+BEGIN XAXIS
+XAXISUSERNAME 0 (null)
+RANGEFLAG AUTO
+TYPE LINEAR
+UNIT s
+BEGIN GRIDS
+AUTOMATIC
+MAJORNUMBERS
+MAJORSTYLE LINES
+MAJORPATTERN SOLID
+MINORSTYLE LINES
+MINORPATTERN DOT
+END GRIDS
+END XAXIS
+BEGIN YAXIS 1
+YAXISSIDE LEFT
+ACTIVE
+RANGEFLAG AUTO
+TYPE LINEAR
+UNIT V
+BEGIN GRIDS
+AUTOMATIC
+MAJORNUMBERS
+MAJORSTYLE LINES
+MAJORPATTERN SOLID
+MINORSTYLE LINES
+MINORPATTERN DOT
+END GRIDS
+BEGIN TRACE V(Vin)
+MARKERID 2
+END TRACE V(Vin)
+END YAXIS 1
+END ANAPLOT 2
+END DISPLAY LAST SESSION

spice/ti/TLV70012_PSPICE_TRANS/TLV70012.lib

@@ -0,0 +1,70 @@
+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70012 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2011 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70012
+* Date: 04/05/2011
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: 
+* EVM Users Guide: 
+* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70012
+*$
+.SUBCKT TLV70012 IN GND EN OUT
+$CDNENCSTART
+eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dce2e9103f51d0de79
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+$CDNENCFINISH
+.ENDS TLV70012
+*$
+.subckt SCHEMATIC1_TLV70012_F1 1 2 3 4  
+$CDNENCSTART
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70012_F1
+*$
+

spice/ti/TLV70012_PSPICE_TRANS/TLV70012.opj

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+(ExpressProject "TLV70012"
+  (ProjectVersion "19981106")
+  (ProjectType "Analog or A/D Mixed Mode")
+  (Folder "Design Resources"
+    (Folder "Library")
+    (NoModify)
+    (File ".\tlv70012.dsn"
+      (Type "Schematic Design"))
+    (BuildFileAddedOrDeleted "x")
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+  (Folder "Outputs"
+    (File ".\tlv70012-pspicefiles\schematic1\schematic1.net"
+      (Type "Report")))
+  (Folder "PSpice Resources"
+    (Folder "Simulation Profiles"
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+      (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
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+        (DisplayName "SCHEMATIC1-trans")
+        (Type "PSpice Profile")))
+    (Folder "Model Libraries"
+      (Sort User)
+      (File ".\tlv70012.lib"
+        (Type "PSpiceLibrary")
+        (DisplayName ".\tlv70012.lib")))
+    (Folder "Stimulus Files"
+      (Sort User))
+    (Folder "Include Files"
+      (Sort User)))
+  (DefaultLibraryBrowseDirectory "library\PSpice")
+  (PartMRUSelector
+    (TLV70012
+      (FullPartName "TLV70012.Normal")
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+      (DeviceIndex "0")))
+  (LastUsedLibraryBrowseDirectory
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+      (Tab 0))))

spice/ti/TLV70013_PSPICE_TRANS/TLV70013-PSpiceFiles/SCHEMATIC1/trans.sim

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+@OrCAD Simulation Server Version: 1.0
+
+@Settings: 0 1
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spice/ti/TLV70013_PSPICE_TRANS/TLV70013-PSpiceFiles/SCHEMATIC1/trans/trans.prb

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+[DISPLAYS]
+BEGIN DISPLAY LAST SESSION
+ANALYSIS TRANSIENT_ANALYSIS
+SYMBOL ALWAYS
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+BEGIN DISPLAY LAST DISPLAY
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spice/ti/TLV70013_PSPICE_TRANS/TLV70013.lib

@@ -0,0 +1,70 @@
+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70013 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2011 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70013
+* Date: 09/15/2011
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: 
+* EVM Users Guide: 
+* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70013
+*$
+.SUBCKT TLV70013 IN GND EN OUT
+$CDNENCSTART
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+$CDNENCFINISH
+.ENDS TLV70013
+*$
+.subckt SCHEMATIC1_TLV70013_F1 1 2 3 4  
+$CDNENCSTART
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70013_F1
+*$
+

spice/ti/TLV70013_PSPICE_TRANS/TLV70013.opj

@@ -0,0 +1,60 @@
+(ExpressProject "TLV70013"
+  (ProjectVersion "19981106")
+  (ProjectType "Analog or A/D Mixed Mode")
+  (Folder "Design Resources"
+    (Folder "Library")
+    (NoModify)
+    (File ".\tlv70013.dsn"
+      (Type "Schematic Design"))
+    (BuildFileAddedOrDeleted "x")
+    (CompileFileAddedOrDeleted "x")
+    (PSPICE_Regenerate_Netlist_Flag "FALSE"))
+  (Folder "Outputs"
+    (File ".\tlv70013-pspicefiles\schematic1\schematic1.net"
+      (Type "Report")))
+  (Folder "PSpice Resources"
+    (Folder "Simulation Profiles"
+      (ActiveProfile ".\tlv70013-pspicefiles\schematic1\trans.sim")
+      (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
+         ".\tlv70013-pspicefiles\schematic1\trans.sim"
+        (DisplayName "SCHEMATIC1-trans")
+        (Type "PSpice Profile")))
+    (Folder "Model Libraries"
+      (Sort User)
+      (File ".\tlv70013.lib"
+        (Type "PSpiceLibrary")
+        (DisplayName ".\tlv70013.lib")))
+    (Folder "Stimulus Files"
+      (Sort User))
+    (Folder "Include Files"
+      (Sort User)))
+  (DefaultLibraryBrowseDirectory "library\PSpice")
+  (PartMRUSelector
+    (TLV70013
+      (FullPartName "TLV70013.Normal")
+      (LibraryName
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70013\RELEASE_TI\PSPICE\TLV70013_PSPICE_TRANS\TLV70013.OLB")
+      (DeviceIndex "0")))
+  (GlobalState
+    (FileView
+      (Path "Design Resources")
+      (Path "Outputs"))
+    (HierarchyView)
+    (Doc
+      (Type "COrCapturePMDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 0 200 0 432"))
+      (Tab 0))
+    (Doc
+      (Type "COrSchematicDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 101 1246 29 638")
+        (Scroll "-63 171")
+        (Zoom "100")
+        (Occurrence "/"))
+      (Path
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70013\RELEASE_TI\PSPICE\TLV70013_PSPICE_TRANS\TLV70013.DSN")
+      (Schematic "SCHEMATIC1")
+      (Page "PAGE1")))
+  (LastUsedLibraryBrowseDirectory
+     "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70013\Release_TI\PSPICE\TLV70013_PSPICE_TRANS"))

spice/ti/TLV70015_PSPICE_TRANS/TLV70015-PSpiceFiles/SCHEMATIC1/trans.sim

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spice/ti/TLV70015_PSPICE_TRANS/TLV70015-PSpiceFiles/SCHEMATIC1/trans/trans.prb

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+[DISPLAYS]
+BEGIN DISPLAY LAST SESSION
+ANALYSIS TRANSIENT_ANALYSIS
+SYMBOL ALWAYS
+TRACECOLORSCHEME NORMAL
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+BEGIN XAXIS
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spice/ti/TLV70015_PSPICE_TRANS/TLV70015.lib

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+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70015 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2011 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70015
+* Date: 04/05/2011
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: 
+* EVM Users Guide: 
+* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70015
+*$
+.SUBCKT TLV70015 IN GND EN OUT
+$CDNENCSTART
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+$CDNENCFINISH
+.ENDS TLV70015
+*$
+.subckt SCHEMATIC1_TLV70015_F1 1 2 3 4  
+$CDNENCSTART
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70015_F1
+*$
+

spice/ti/TLV70015_PSPICE_TRANS/TLV70015.opj

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+(ExpressProject "TLV70015"
+  (ProjectVersion "19981106")
+  (ProjectType "Analog or A/D Mixed Mode")
+  (Folder "Design Resources"
+    (Folder "Library")
+    (NoModify)
+    (File ".\tlv70015.dsn"
+      (Type "Schematic Design"))
+    (BuildFileAddedOrDeleted "x")
+    (CompileFileAddedOrDeleted "x")
+    (PSPICE_Regenerate_Netlist_Flag "FALSE"))
+  (Folder "Outputs"
+    (File ".\tlv70015-pspicefiles\schematic1\schematic1.net"
+      (Type "Report")))
+  (Folder "PSpice Resources"
+    (Folder "Simulation Profiles"
+      (ActiveProfile ".\tlv70015-pspicefiles\schematic1\trans.sim")
+      (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
+         ".\tlv70015-pspicefiles\schematic1\trans.sim"
+        (DisplayName "SCHEMATIC1-trans")
+        (Type "PSpice Profile")))
+    (Folder "Model Libraries"
+      (Sort User)
+      (File ".\tlv70015.lib"
+        (Type "PSpiceLibrary")
+        (DisplayName ".\tlv70015.lib")))
+    (Folder "Stimulus Files"
+      (Sort User))
+    (Folder "Include Files"
+      (Sort User)))
+  (DefaultLibraryBrowseDirectory "library\PSpice")
+  (PartMRUSelector
+    (TLV70015
+      (FullPartName "TLV70015.Normal")
+      (LibraryName
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70015\RELEASE_TI\PSPICE\TLV70015_PSPICE_TRANS\TLV70015.OLB")
+      (DeviceIndex "0")))
+  (LastUsedLibraryBrowseDirectory
+     "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70015\Release_TI\PSPICE\TLV70015_PSPICE_TRANS")
+  (GlobalState
+    (FileView
+      (Path "Design Resources")
+      (Path "Outputs"))
+    (HierarchyView)
+    (Doc
+      (Type "COrCapturePMDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 0 200 0 367"))
+      (Tab 0))
+    (Doc
+      (Type "COrSchematicDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 60 1239 70 571")
+        (Scroll "-80 0")
+        (Zoom "100")
+        (Occurrence "/"))
+      (Path
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70015\RELEASE_TI\PSPICE\TLV70015_PSPICE_TRANS\TLV70015.DSN")
+      (Schematic "SCHEMATIC1")
+      (Page "PAGE1"))))

spice/ti/TLV70018_PSPICE_TRANS/TLV70018-PSpiceFiles/SCHEMATIC1/trans.sim

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+@OrCAD Simulation Server Version: 1.0
+
+@Settings: 0 1
+@General:
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+ProfileFile= "trans.sim" 
+Connectivity= "SCHEMATIC1.net" 
+NetlistFile= "trans.cir" 
+DataFile= "trans.dat" 
+OutFile= "trans.out" 
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spice/ti/TLV70018_PSPICE_TRANS/TLV70018-PSpiceFiles/SCHEMATIC1/trans/trans.prb

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+[DISPLAYS]
+BEGIN DISPLAY LAST SESSION
+ANALYSIS TRANSIENT_ANALYSIS
+SYMBOL ALWAYS
+TRACECOLORSCHEME NORMAL
+BEGIN ANAPLOT 1
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spice/ti/TLV70018_PSPICE_TRANS/TLV70018.lib

@@ -0,0 +1,70 @@
+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70018 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2011 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70018
+* Date: 04/05/2011
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: TLV70018EVM-503
+* EVM Users Guide: SLUU391 - DECEMBER 2009
+* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70018
+*$
+.SUBCKT TLV70018 IN GND EN OUT
+$CDNENCSTART
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+$CDNENCFINISH
+.ENDS TLV70018
+*$
+.subckt SCHEMATIC1_TLV70018_F1 1 2 3 4  
+$CDNENCSTART
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70018_F1
+*$
+

spice/ti/TLV70018_PSPICE_TRANS/TLV70018.opj

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+(ExpressProject "TLV70018"
+  (ProjectVersion "19981106")
+  (ProjectType "Analog or A/D Mixed Mode")
+  (Folder "Design Resources"
+    (Folder "Library")
+    (NoModify)
+    (File ".\tlv70018.dsn"
+      (Type "Schematic Design"))
+    (BuildFileAddedOrDeleted "x")
+    (CompileFileAddedOrDeleted "x")
+    (PSPICE_Regenerate_Netlist_Flag "FALSE"))
+  (Folder "Outputs"
+    (File ".\tlv70018-pspicefiles\schematic1\schematic1.net"
+      (Type "Report")))
+  (Folder "PSpice Resources"
+    (Folder "Simulation Profiles"
+      (ActiveProfile ".\tlv70018-pspicefiles\schematic1\trans.sim")
+      (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
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+        (DisplayName "SCHEMATIC1-trans")
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+    (Folder "Model Libraries"
+      (Sort User)
+      (File ".\tlv70018.lib"
+        (Type "PSpiceLibrary")
+        (DisplayName ".\tlv70018.lib")))
+    (Folder "Stimulus Files"
+      (Sort User))
+    (Folder "Include Files"
+      (Sort User)))
+  (DefaultLibraryBrowseDirectory "library\PSpice")
+  (PartMRUSelector
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+      (FullPartName "TLV70018.Normal")
+      (LibraryName
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+      (DeviceIndex "0")))
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+        (Placement "44 0 1 -1 -1 -1 -1 25 1251 25 556")
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+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70018\RELEASE_TI\PSPICE\TLV70018_PSPICE_TRANS\TLV70018.DSN")
+      (Schematic "SCHEMATIC1")
+      (Page "PAGE1")))
+  (LastUsedLibraryBrowseDirectory
+     "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70018\Release_TI\PSPICE\TLV70018_PSPICE_TRANS"))

spice/ti/TLV70019_PSPICE_TRANS/TLV70019-PSpiceFiles/SCHEMATIC1/trans.sim

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spice/ti/TLV70019_PSPICE_TRANS/TLV70019-PSpiceFiles/SCHEMATIC1/trans/trans.prb

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+[DISPLAYS]
+BEGIN DISPLAY LAST SESSION
+ANALYSIS TRANSIENT_ANALYSIS
+SYMBOL ALWAYS
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spice/ti/TLV70019_PSPICE_TRANS/TLV70019.lib

@@ -0,0 +1,70 @@
+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70019 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2012 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70019
+* Date: 01/17/2012
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: 
+* EVM Users Guide: 
+* Datasheet: SLVSA00C - SEPTEMBER 2009 - REVISED JULY 2011
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70019
+*$
+.SUBCKT TLV70019 IN GND EN OUT
+$CDNENCSTART
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+$CDNENCFINISH
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+*$
+.subckt SCHEMATIC1_TLV70019_F1 1 2 3 4  
+$CDNENCSTART
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70019_F1
+*$
+

spice/ti/TLV70019_PSPICE_TRANS/TLV70019.opj

@@ -0,0 +1,60 @@
+(ExpressProject "TLV70019"
+  (ProjectVersion "19981106")
+  (ProjectType "Analog or A/D Mixed Mode")
+  (Folder "Design Resources"
+    (Folder "Library")
+    (NoModify)
+    (File ".\tlv70019.dsn"
+      (Type "Schematic Design"))
+    (BuildFileAddedOrDeleted "x")
+    (CompileFileAddedOrDeleted "x")
+    (PSPICE_Regenerate_Netlist_Flag "FALSE"))
+  (Folder "Outputs"
+    (File ".\tlv70019-pspicefiles\schematic1\schematic1.net"
+      (Type "Report")))
+  (Folder "PSpice Resources"
+    (Folder "Simulation Profiles"
+      (ActiveProfile ".\tlv70019-pspicefiles\schematic1\trans.sim")
+      (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
+         ".\tlv70019-pspicefiles\schematic1\trans.sim"
+        (DisplayName "SCHEMATIC1-trans")
+        (Type "PSpice Profile")))
+    (Folder "Model Libraries"
+      (Sort User)
+      (File ".\tlv70019.lib"
+        (Type "PSpiceLibrary")
+        (DisplayName ".\tlv70019.lib")))
+    (Folder "Stimulus Files"
+      (Sort User))
+    (Folder "Include Files"
+      (Sort User)))
+  (DefaultLibraryBrowseDirectory "library\PSpice")
+  (PartMRUSelector
+    (TLV70019
+      (FullPartName "TLV70019.Normal")
+      (LibraryName
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70019\RELEASE_TI\PSPICE\TLV70019_PSPICE_TRANS\TLV70019.OLB")
+      (DeviceIndex "0")))
+  (LastUsedLibraryBrowseDirectory
+     "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70019\Release_TI\PSPICE\TLV70019_PSPICE_TRANS")
+  (GlobalState
+    (FileView
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+      (Path "Outputs"))
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+        (Placement "44 0 1 -1 -1 -1 -1 0 200 0 432"))
+      (Tab 0))
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+      (Path
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+      (Schematic "SCHEMATIC1")
+      (Page "PAGE1"))))

spice/ti/TLV70022_PSPICE_TRANS/TLV70022-PSpiceFiles/SCHEMATIC1/trans.sim

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spice/ti/TLV70022_PSPICE_TRANS/TLV70022-PSpiceFiles/SCHEMATIC1/trans/trans.prb

@@ -0,0 +1,76 @@
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+BEGIN DISPLAY LAST SESSION
+ANALYSIS TRANSIENT_ANALYSIS
+SYMBOL ALWAYS
+TRACECOLORSCHEME NORMAL
+BEGIN ANAPLOT 1
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+BEGIN TRACE V(Vin)
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spice/ti/TLV70022_PSPICE_TRANS/TLV70022.lib

@@ -0,0 +1,70 @@
+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70022 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2012 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70022
+* Date: 01/17/2012
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: 
+* EVM Users Guide: 
+* Datasheet: SLVSA00C - SEPTEMBER 2009 - REVISED JULY 2011
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70022
+*$
+.SUBCKT TLV70022 IN GND EN OUT
+$CDNENCSTART
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+$CDNENCFINISH
+.ENDS TLV70022
+*$
+.subckt SCHEMATIC1_TLV70022_F1 1 2 3 4  
+$CDNENCSTART
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70022_F1
+*$
+

spice/ti/TLV70022_PSPICE_TRANS/TLV70022.opj

@@ -0,0 +1,60 @@
+(ExpressProject "TLV70022"
+  (ProjectVersion "19981106")
+  (ProjectType "Analog or A/D Mixed Mode")
+  (Folder "Design Resources"
+    (Folder "Library")
+    (NoModify)
+    (File ".\tlv70022.dsn"
+      (Type "Schematic Design"))
+    (BuildFileAddedOrDeleted "x")
+    (CompileFileAddedOrDeleted "x")
+    (PSPICE_Regenerate_Netlist_Flag "FALSE"))
+  (Folder "Outputs"
+    (File ".\tlv70022-pspicefiles\schematic1\schematic1.net"
+      (Type "Report")))
+  (Folder "PSpice Resources"
+    (Folder "Simulation Profiles"
+      (ActiveProfile ".\tlv70022-pspicefiles\schematic1\trans.sim")
+      (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
+         ".\tlv70022-pspicefiles\schematic1\trans.sim"
+        (DisplayName "SCHEMATIC1-trans")
+        (Type "PSpice Profile")))
+    (Folder "Model Libraries"
+      (Sort User)
+      (File ".\tlv70022.lib"
+        (Type "PSpiceLibrary")
+        (DisplayName ".\tlv70022.lib")))
+    (Folder "Stimulus Files"
+      (Sort User))
+    (Folder "Include Files"
+      (Sort User)))
+  (DefaultLibraryBrowseDirectory "library\PSpice")
+  (PartMRUSelector
+    (TLV70022
+      (FullPartName "TLV70022.Normal")
+      (LibraryName
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70022\RELEASE_TI\PSPICE\TLV70022_PSPICE_TRANS\TLV70022.OLB")
+      (DeviceIndex "0")))
+  (LastUsedLibraryBrowseDirectory
+     "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70022\Release_TI\PSPICE\TLV70022_PSPICE_TRANS")
+  (GlobalState
+    (FileView
+      (Path "Design Resources")
+      (Path "Outputs"))
+    (HierarchyView)
+    (Doc
+      (Type "COrCapturePMDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 0 200 0 432"))
+      (Tab 0))
+    (Doc
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+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 24 1298 8 645")
+        (Scroll "-128 153")
+        (Zoom "100")
+        (Occurrence "/"))
+      (Path
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70022\RELEASE_TI\PSPICE\TLV70022_PSPICE_TRANS\TLV70022.DSN")
+      (Schematic "SCHEMATIC1")
+      (Page "PAGE1"))))

spice/ti/TLV70025_PSPICE_TRANS/TLV70025-PSpiceFiles/SCHEMATIC1/trans.sim

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+
+@Settings: 0 1
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+ProfileFile= "trans.sim" 
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spice/ti/TLV70025_PSPICE_TRANS/TLV70025-PSpiceFiles/SCHEMATIC1/trans/trans.prb

@@ -0,0 +1,76 @@
+[DISPLAYS]
+BEGIN DISPLAY LAST SESSION
+ANALYSIS TRANSIENT_ANALYSIS
+SYMBOL ALWAYS
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spice/ti/TLV70025_PSPICE_TRANS/TLV70025.lib

@@ -0,0 +1,70 @@
+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70025 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2011 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70025
+* Date: 04/05/2011
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: 
+* EVM Users Guide: 
+* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70025
+*$
+.SUBCKT TLV70025 IN GND EN OUT
+$CDNENCSTART
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+.subckt SCHEMATIC1_TLV70025_F1 1 2 3 4  
+$CDNENCSTART
+eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dcce703e6b176617a3
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70025_F1
+*$
+

spice/ti/TLV70025_PSPICE_TRANS/TLV70025.opj

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+(ExpressProject "TLV70025"
+  (ProjectVersion "19981106")
+  (ProjectType "Analog or A/D Mixed Mode")
+  (Folder "Design Resources"
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+      (Type "Report")))
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+    (Folder "Stimulus Files"
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spice/ti/TLV70028_PSPICE_TRANS/TLV70028-PSpiceFiles/SCHEMATIC1/trans.sim

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spice/ti/TLV70028_PSPICE_TRANS/TLV70028-PSpiceFiles/SCHEMATIC1/trans/trans.prb

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spice/ti/TLV70028_PSPICE_TRANS/TLV70028.lib

@@ -0,0 +1,70 @@
+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70028 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2011 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70028
+* Date: 04/05/2011
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: TLV70028EVM-463
+* EVM Users Guide: SLUU390 - DECEMBER 2009
+* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70028
+*$
+.SUBCKT TLV70028 IN GND EN OUT
+$CDNENCSTART
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+$CDNENCFINISH
+.ENDS TLV70028
+*$
+.subckt SCHEMATIC1_TLV70028_F1 1 2 3 4  
+$CDNENCSTART
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70028_F1
+*$
+

spice/ti/TLV70028_PSPICE_TRANS/TLV70028.opj

@@ -0,0 +1,60 @@
+(ExpressProject "TLV70028"
+  (ProjectVersion "19981106")
+  (ProjectType "Analog or A/D Mixed Mode")
+  (Folder "Design Resources"
+    (Folder "Library")
+    (NoModify)
+    (File ".\tlv70028.dsn"
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+  (Folder "Outputs"
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+      (Type "Report")))
+  (Folder "PSpice Resources"
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+      (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
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+    (Folder "Model Libraries"
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+        (DisplayName ".\tlv70028.lib")))
+    (Folder "Stimulus Files"
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+    (Folder "Include Files"
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+  (DefaultLibraryBrowseDirectory "library\PSpice")
+  (PartMRUSelector
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+      (LibraryName
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70028\RELEASE_TI\PSPICE\TLV70028_PSPICE_TRANS\TLV70028.OLB")
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+  (LastUsedLibraryBrowseDirectory
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+      (Schematic "SCHEMATIC1")
+      (Page "PAGE1"))))

spice/ti/TLV70029_PSPICE_TRANS/TLV0029-PSpiceFiles/SCHEMATIC1/trans.sim

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spice/ti/TLV70029_PSPICE_TRANS/TLV0029-PSpiceFiles/SCHEMATIC1/trans/trans.prb

@@ -0,0 +1,76 @@
+[DISPLAYS]
+BEGIN DISPLAY LAST SESSION
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spice/ti/TLV70029_PSPICE_TRANS/TLV0029.opj

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+    (File ".\tlv0029-pspicefiles\schematic1\schematic1.net"
+      (Type "Report")))
+  (Folder "PSpice Resources"
+    (Folder "Simulation Profiles"
+      (ActiveProfile ".\tlv0029-pspicefiles\schematic1\trans.sim")
+      (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
+         ".\tlv0029-pspicefiles\schematic1\trans.sim"
+        (DisplayName "SCHEMATIC1-trans")
+        (Type "PSpice Profile")))
+    (Folder "Model Libraries"
+      (Sort User)
+      (File ".\tlv70029.lib"
+        (Type "PSpiceLibrary")
+        (DisplayName ".\tlv70029.lib")))
+    (Folder "Stimulus Files"
+      (Sort User))
+    (Folder "Include Files"
+      (Sort User)))
+  (DefaultLibraryBrowseDirectory "library\PSpice")
+  (PartMRUSelector
+    (TLV70029
+      (FullPartName "TLV70029.Normal")
+      (LibraryName
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70029\RELEASE_TI\PSPICE\TLV70029_PSPICE_TRANS\TLV70029.OLB")
+      (DeviceIndex "0")))
+  (GlobalState
+    (FileView
+      (Path "Design Resources")
+      (Path "Outputs"))
+    (HierarchyView)
+    (Doc
+      (Type "COrCapturePMDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 0 200 0 367"))
+      (Tab 0))
+    (Doc
+      (Type "COrSchematicDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 37 1190 23 557")
+        (Scroll "-67 0")
+        (Zoom "100")
+        (Occurrence "/"))
+      (Path
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70029\RELEASE_TI\PSPICE\TLV70029_PSPICE_TRANS\TLV0029.DSN")
+      (Schematic "SCHEMATIC1")
+      (Page "PAGE1")))
+  (LastUsedLibraryBrowseDirectory
+     "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70029\Release_TI\PSPICE\TLV70029_PSPICE_TRANS"))

spice/ti/TLV70029_PSPICE_TRANS/TLV70029.lib

@@ -0,0 +1,70 @@
+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70029 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2011 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70029
+* Date: 04/05/2011
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: 
+* EVM Users Guide: 
+* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70029
+*$
+.SUBCKT TLV70029 IN GND EN OUT
+$CDNENCSTART
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+$CDNENCFINISH
+.ENDS TLV70029
+*$
+.subckt SCHEMATIC1_TLV70029_F1 1 2 3 4  
+$CDNENCSTART
+eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dc012ebc0b3df5b352
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70029_F1
+*$
+

spice/ti/TLV70030_PSPICE_TRANS/TLV70030-PSpiceFiles/SCHEMATIC1/trans.sim

@@ -0,0 +1,137 @@
+@OrCAD Simulation Server Version: 1.0
+
+@Settings: 0 1
+@General:
+ProfileName= "trans" 
+ProfileFile= "trans.sim" 
+Connectivity= "SCHEMATIC1.net" 
+NetlistFile= "trans.cir" 
+DataFile= "trans.dat" 
+OutFile= "trans.out" 
+Notes=
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spice/ti/TLV70030_PSPICE_TRANS/TLV70030-PSpiceFiles/SCHEMATIC1/trans/trans.prb

@@ -0,0 +1,76 @@
+[DISPLAYS]
+BEGIN DISPLAY LAST SESSION
+ANALYSIS TRANSIENT_ANALYSIS
+SYMBOL ALWAYS
+TRACECOLORSCHEME NORMAL
+BEGIN ANAPLOT 1
+XBASE
+BEGIN XAXIS
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+RANGEFLAG AUTO
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+BEGIN TRACE V(Vout)
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+END TRACE V(Vout)
+END YAXIS 1
+END ANAPLOT 1
+BEGIN ANAPLOT 2
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+RANGEFLAG AUTO
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+UNIT s
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+BEGIN YAXIS 1
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+TYPE LINEAR
+UNIT V
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+BEGIN TRACE V(Vin)
+MARKERID 2
+END TRACE V(Vin)
+END YAXIS 1
+END ANAPLOT 2
+END DISPLAY LAST SESSION