diff --git a/.gitignore b/.gitignore old mode 100644 new mode 100755 diff --git a/.gitmodules b/.gitmodules old mode 100644 new mode 100755 diff --git a/README.md b/README.md old mode 100644 new mode 100755 diff --git a/bh.kicad_sym b/bh.kicad_sym old mode 100644 new mode 100755 index a99dc70..8912c33 --- a/bh.kicad_sym +++ b/bh.kicad_sym @@ -1,4 +1,4 @@ -(kicad_symbol_lib (version 20210619) (generator kicad_symbol_editor) +(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor) (symbol "bh:ADM6710QARJZ-REEL7" (in_bom yes) (on_board yes) (property "Reference" "U" (id 0) (at 0 0 0) (effects (font (size 1.27 1.27))) @@ -35,7 +35,8 @@ ) (symbol "ADM6710QARJZ-REEL7_0_1" (rectangle (start 0 0) (end 12.7 -20.32) - (stroke (width 0)) (fill (type background)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type background)) ) ) (symbol "ADM6710QARJZ-REEL7_1_1" @@ -72,7 +73,7 @@ (property "Value" "ADUM1281BRZ" (id 1) (at 0 0 0) (effects (font (size 1.27 1.27))) ) - (property "Footprint" "" (id 2) (at 0 0 0) + (property "Footprint" "common:SOIC127P600X175-8" (id 2) (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) (property "Datasheet" "https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM1280_1281_1285_1286.pdf" (id 3) (at 0 0 0) @@ -97,134 +98,149 @@ (effects (font (size 1.27 1.27)) hide) ) (symbol "ADUM1281BRZ_0_1" - (rectangle (start 0 0) (end 12.7 -12.7) - (stroke (width 0.1524)) (fill (type background)) - ) (polyline (pts (xy 5.715 -7.62) (xy 3.81 -7.62) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 5.715 -5.08) (xy 4.445 -5.08) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.223 -11.43) (xy 6.223 -12.065) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.223 -10.16) (xy 6.223 -10.795) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.223 -8.89) (xy 6.223 -9.525) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.223 -5.969) (xy 6.223 -6.604) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.223 -3.175) (xy 6.223 -3.81) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.223 -1.905) (xy 6.223 -2.54) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.223 -1.27) (xy 6.223 -0.635) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.477 -11.43) (xy 6.477 -12.065) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.477 -10.16) (xy 6.477 -10.795) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.477 -8.89) (xy 6.477 -9.525) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.477 -5.969) (xy 6.477 -6.604) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.477 -3.175) (xy 6.477 -3.81) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.477 -1.905) (xy 6.477 -2.54) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.477 -1.27) (xy 6.477 -0.635) ) - (stroke (width 0.1524)) (fill (type none)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.985 -7.62) (xy 8.255 -7.62) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 6.985 -5.08) (xy 8.89 -5.08) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts @@ -234,7 +250,8 @@ (xy 5.715 -8.509) (xy 5.715 -7.62) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts @@ -244,7 +261,12 @@ (xy 6.985 -5.969) (xy 6.985 -5.08) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (rectangle (start 0 0) (end 12.7 -12.7) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type background)) ) ) (symbol "ADUM1281BRZ_1_1" @@ -282,6 +304,126 @@ ) ) ) + (symbol "bh:AR1100-I{slash}SS" (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "AR1100-I{slash}SS" (id 1) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "https://ww1.microchip.com/downloads/en/DeviceDoc/41606B.pdf" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Manufacturer" "Microchip Technology" (id 4) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ManufacturerPartNumber" "AR1100-I/SS" (id 5) (at 0 0 0) + (effects (font (size 1.27 1.27))) + ) + (property "Supplier" "" (id 6) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "SupplierPartNumber" "" (id 7) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Populate" "" (id 8) (at 0 0 0) + (effects (font (size 1.27 1.27))) + ) + (property "ki_description" "IC, USB HID, Touch Screen Controller, Resistive, 12bit, 20-SSOP" (id 9) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "AR1100-I{slash}SS_0_1" + (rectangle (start 0 0) (end 25.4 -43.18) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type background)) + ) + ) + (symbol "AR1100-I{slash}SS_1_1" + (pin power_in line (at -2.54 -2.54 0) (length 2.54) + (name "VDD" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -33.02 180) (length 2.54) + (name "UART-TX" (effects (font (size 1.27 1.27)))) + (number "10" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -27.94 180) (length 2.54) + (name "WAKE" (effects (font (size 1.27 1.27)))) + (number "11" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -35.56 180) (length 2.54) + (name "UART-RX" (effects (font (size 1.27 1.27)))) + (number "12" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -20.32 180) (length 2.54) + (name "SX-" (effects (font (size 1.27 1.27)))) + (number "13" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -17.78 180) (length 2.54) + (name "X-" (effects (font (size 1.27 1.27)))) + (number "14" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -5.08 180) (length 2.54) + (name "Y+(SY+)" (effects (font (size 1.27 1.27)))) + (number "15" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -7.62 180) (length 2.54) + (name "Y-" (effects (font (size 1.27 1.27)))) + (number "16" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -2.54 -33.02 0) (length 2.54) + (name "VUSB" (effects (font (size 1.27 1.27)))) + (number "17" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -2.54 -15.24 0) (length 2.54) + (name "USB-D-" (effects (font (size 1.27 1.27)))) + (number "18" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -2.54 -12.7 0) (length 2.54) + (name "USB-D+" (effects (font (size 1.27 1.27)))) + (number "19" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -2.54 -20.32 0) (length 2.54) + (name "OSC1" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -2.54 -40.64 0) (length 2.54) + (name "VSS" (effects (font (size 1.27 1.27)))) + (number "20" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -2.54 -27.94 0) (length 2.54) + (name "OSC2" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -2.54 -5.08 0) (length 2.54) + (name "MODE" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -40.64 180) (length 2.54) + (name "LED" (effects (font (size 1.27 1.27)))) + (number "5" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -2.54 180) (length 2.54) + (name "(Y+)" (effects (font (size 1.27 1.27)))) + (number "6" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -12.7 180) (length 2.54) + (name "X+" (effects (font (size 1.27 1.27)))) + (number "7" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -10.16 180) (length 2.54) + (name "SY-" (effects (font (size 1.27 1.27)))) + (number "8" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 27.94 -15.24 180) (length 2.54) + (name "SX+" (effects (font (size 1.27 1.27)))) + (number "9" (effects (font (size 1.27 1.27)))) + ) + ) + ) (symbol "bh:BOM_ITEM" (pin_names (offset 1.016)) (in_bom yes) (on_board no) (property "Reference" "BOM" (id 0) (at 0 1.27 0) (effects (font (size 1.27 1.27)) hide) @@ -320,7 +462,8 @@ ) (symbol "BOM_ITEM_0_1" (rectangle (start 0 0) (end 5.08 -2.54) - (stroke (width 0)) (fill (type background)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type background)) ) ) ) @@ -357,7 +500,8 @@ ) (symbol "BQ25730RSNR_0_1" (rectangle (start 0 0) (end 25.4 -76.2) - (stroke (width 0.1524)) (fill (type background)) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type background)) ) ) (symbol "BQ25730RSNR_1_1" @@ -528,38 +672,44 @@ ) (symbol "Battery_0_1" (rectangle (start -2.286 0.508) (end 2.286 0.254) - (stroke (width 0)) (fill (type outline)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type outline)) ) (rectangle (start -1.5748 -0.0762) (end 1.4732 -0.5842) - (stroke (width 0)) (fill (type outline)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type outline)) ) (polyline (pts (xy 0 -0.508) (xy 0 -1.27) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 0 0.508) (xy 0 1.27) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 0.508 2.159) (xy 1.524 2.159) ) - (stroke (width 0.254)) (fill (type none)) + (stroke (width 0.254) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 1.016 2.667) (xy 1.016 1.651) ) - (stroke (width 0.254)) (fill (type none)) + (stroke (width 0.254) (type default) (color 0 0 0 0)) + (fill (type none)) ) ) (symbol "Battery_1_1" @@ -616,14 +766,16 @@ (xy -2.032 -0.762) (xy 2.032 -0.762) ) - (stroke (width 0.508)) (fill (type none)) + (stroke (width 0.508) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy -2.032 0.762) (xy 2.032 0.762) ) - (stroke (width 0.508)) (fill (type none)) + (stroke (width 0.508) (type default) (color 0 0 0 0)) + (fill (type none)) ) ) (symbol "C_1_1" @@ -675,29 +827,33 @@ (effects (font (size 1.27 1.27)) hide) ) (symbol "CP_0_1" - (arc (start -2.032 -1.27) (end 2.032 -1.27) (radius (at 0 -3.81) (length 3.2512) (angles 128.7 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0.2311 -1.8066) (end 1.778 0) + (stroke (width 0.254) (type default) (color 0 0 0 0)) + (fill (type none)) ) - (arc (start 1.778 0) (end -1.778 -0.508) (radius (at -0.0254 0) (length 1.8034) (angles 0 -163.8)) - (stroke (width 0.254)) (fill (type none)) - ) - (circle (center 0 0) (radius 0.508) (stroke (width 0.2032)) (fill (type none))) (polyline (pts (xy -1.27 0) (xy -0.508 0) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) ) (polyline (pts (xy 0 -2.54) (xy 0 -1.778) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (circle (center 0 0) (radius 0.508) (stroke (width 0.2032) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (arc (start 1.778 0) (mid 0.2233 1.8169) (end -1.778 0.508) + (stroke (width 0.254) (type default) (color 0 0 0 0)) + (fill (type none)) ) ) (symbol "Conn_Coax_1_1" @@ -811,26 +973,25 @@ (effects (font (size 1.27 1.27)) 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(stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (circle (center 0 0) (radius 0.508) (stroke (width 0.2032) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (arc (start 1.778 0) (mid 0.2223 1.8103) (end -1.778 0.508) + (stroke (width 0.254) (type default) (color 0 0 0 0)) + (fill (type none)) ) ) (symbol "Conn_Coaxial_Switching_1_1" @@ -855,7 +1024,8 @@ (xy 2.54 0) (xy 1.778 0) ) - (stroke (width 0)) (fill (type none)) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) ) (pin passive line (at 0 -3.81 90) (length 1.27) (name "Ext" (effects (font (size 1.27 1.27)))) @@ -903,12 +1073,6 @@ (effects (font (size 1.27 1.27)) hide) ) (symbol "Conn_DisplayPort_0_1" - (text "SOURCE" (at 10.16 -53.34 0) - (effects (font (size 1.27 1.27))) - ) - (rectangle (start 0 0) (end 15.24 -55.88) - (stroke (width 0)) (fill (type background)) - ) (polyline (pts (xy 12.7 -2.54) @@ -918,7 +1082,8 @@ (xy 10.795 -3.175) (xy 10.795 -2.54) ) - (stroke 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"XT60_1_1" diff --git a/cap.kicad_sym b/cap.kicad_sym new file mode 100755 index 0000000..14168c9 --- /dev/null +++ b/cap.kicad_sym @@ -0,0 +1,172 @@ +(kicad_symbol_lib (version 20210619) (generator kicad_symbol_editor) + (symbol "cap:C" (pin_numbers hide) (pin_names (offset 0.254)) (in_bom yes) (on_board yes) + (property "Reference" "C" (id 0) (at 0.635 2.54 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Value" "C" (id 1) (at 0.635 -2.54 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Footprint" "common:C0402" (id 2) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0.635 2.54 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Manufacturer" "" (id 4) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ManufacturerPartNumber" "" (id 5) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Supplier" "" (id 6) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "SupplierPartNumber" "" (id 7) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Populate" "" (id 8) (at 0 0 0) + (effects (font (size 1.27 1.27))) + ) + (property "FieldName" "Value" (id 9) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Voltage" "" (id 10) (at 0 0 0) + (effects (font (size 1.27 1.27))) + ) + (property "Type" "" (id 11) (at 0 0 0) + (effects (font (size 1.27 1.27))) + ) + (property "ESR" "" (id 12) (at 0 0 0) + (effects (font (size 1.27 1.27))) + ) + (property "ESL" "" (id 13) (at 0 0 0) + (effects (font (size 1.27 1.27))) + ) + (property "ki_description" "Capacitor" (id 14) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_fp_filters" "*:C_*" (id 15) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "C_0_1" + (polyline + (pts + (xy -2.032 -0.762) + (xy 2.032 -0.762) + ) + (stroke (width 0.508)) (fill (type none)) + ) + (polyline + (pts + (xy -2.032 0.762) + (xy 2.032 0.762) + ) + (stroke (width 0.508)) (fill (type none)) + ) + ) + (symbol "C_1_1" + (pin passive line (at 0 3.81 270) (length 2.794) + (name "~" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -3.81 90) (length 2.794) + (name "~" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + ) + ) + (symbol "cap:thisisampn" (extends "C") + (property "Reference" "C" (id 0) (at 0.635 2.54 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Value" "thisisampn" (id 1) (at 0.635 -2.54 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0.635 2.54 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_description" "Capacitor" (id 4) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_fp_filters" "*:C_*" (id 5) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + ) + (symbol "cap:CP" (pin_numbers hide) (pin_names (offset 0.254) hide) (in_bom yes) (on_board yes) + (property "Reference" "C" (id 0) (at 0.635 2.54 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Value" "CP" (id 1) (at 0.635 -2.54 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Manufacturer" "" (id 4) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ManufacturerPartNumber" "" (id 5) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Supplier" "" (id 6) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "SupplierPartNumber" "" (id 7) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Populate" "" (id 8) (at 0 0 0) + (effects (font (size 1.27 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STYLED_ITEM( '', ( #1095 ), #1096 ); +#330 = STYLED_ITEM( '', ( #1097 ), #1098 ); +#331 = STYLED_ITEM( '', ( #1099 ), #1100 ); +#332 = STYLED_ITEM( '', ( #1101 ), #1102 ); +#333 = STYLED_ITEM( '', ( #1103 ), #1104 ); +#334 = STYLED_ITEM( '', ( #1105 ), #1106 ); +#335 = STYLED_ITEM( '', ( #1107 ), #1108 ); +#336 = STYLED_ITEM( '', ( #1109 ), #1110 ); +#337 = STYLED_ITEM( '', ( #1111 ), #1112 ); +#338 = STYLED_ITEM( '', ( #1113 ), #1114 ); +#339 = STYLED_ITEM( '', ( #1115 ), #1116 ); +#340 = STYLED_ITEM( '', ( #1117 ), #1118 ); +#341 = STYLED_ITEM( '', ( #1119 ), #1120 ); +#342 = STYLED_ITEM( '', ( #1121 ), #1122 ); +#343 = STYLED_ITEM( '', ( #1123 ), #1124 ); +#344 = STYLED_ITEM( '', ( #1125 ), #1126 ); +#345 = STYLED_ITEM( '', ( #1127 ), #1128 ); +#346 = STYLED_ITEM( '', ( #1129 ), #1130 ); +#347 = STYLED_ITEM( '', ( #1131 ), #1132 ); +#348 = STYLED_ITEM( '', ( #1133 ), #1134 ); +#349 = STYLED_ITEM( '', ( #1135 ), #1136 ); +#350 = STYLED_ITEM( '', ( #1137 ), #1138 ); +#351 = STYLED_ITEM( '', ( #1139 ), #1140 ); +#352 = STYLED_ITEM( '', ( #1141 ), #1142 ); +#353 = STYLED_ITEM( '', ( #1143 ), #1144 ); +#354 = STYLED_ITEM( '', ( #1145 ), #1146 ); +#355 = STYLED_ITEM( '', ( #1147 ), #1148 ); +#356 = STYLED_ITEM( '', ( #1149 ), #1150 ); +#357 = STYLED_ITEM( '', ( #1151 ), #1152 ); +#358 = STYLED_ITEM( '', ( #1153 ), #1154 ); +#359 = STYLED_ITEM( '', ( #1155 ), #1156 ); +#360 = STYLED_ITEM( '', ( #1157 ), #1158 ); +#361 = STYLED_ITEM( '', ( #1159 ), #1160 ); +#362 = STYLED_ITEM( '', ( #1161 ), #1162 ); +#363 = STYLED_ITEM( '', ( #1163 ), #1164 ); +#364 = STYLED_ITEM( '', ( #1165 ), #1166 ); +#365 = STYLED_ITEM( '', ( #1167 ), #1168 ); +#366 = STYLED_ITEM( '', ( #1169 ), #1170 ); +#367 = STYLED_ITEM( '', ( #1171 ), #1172 ); +#368 = STYLED_ITEM( '', ( #1173 ), #1174 ); +#369 = STYLED_ITEM( '', ( #1175 ), #1176 ); +#370 = STYLED_ITEM( '', ( #1177 ), #1178 ); +#371 = STYLED_ITEM( '', ( #1179 ), #1180 ); +#372 = STYLED_ITEM( '', ( #1181 ), #1182 ); +#373 = STYLED_ITEM( '', ( #1183 ), #1184 ); +#374 = STYLED_ITEM( '', ( #1185 ), #1186 ); +#375 = STYLED_ITEM( '', ( #1187 ), #1188 ); +#376 = STYLED_ITEM( '', ( #1189 ), #1190 ); +#377 = STYLED_ITEM( '', ( #1191 ), #1192 ); +#378 = STYLED_ITEM( '', ( #1193 ), #1194 ); +#379 = STYLED_ITEM( '', ( #1195 ), #1196 ); +#380 = STYLED_ITEM( '', ( #1197 ), #1198 ); +#381 = STYLED_ITEM( '', ( #1199 ), #1200 ); +#382 = STYLED_ITEM( '', ( #1201 ), #1202 ); +#383 = STYLED_ITEM( '', ( #1203 ), #1204 ); +#384 = STYLED_ITEM( '', ( #1205 ), #1206 ); +#385 = STYLED_ITEM( '', ( #1207 ), #1208 ); +#386 = STYLED_ITEM( '', ( #1209 ), #1210 ); +#387 = STYLED_ITEM( '', ( #1211 ), #1212 ); +#388 = STYLED_ITEM( '', ( #1213 ), #1214 ); +#389 = STYLED_ITEM( '', ( #1215 ), #1216 ); +#390 = STYLED_ITEM( '', ( #1217 ), #1218 ); +#391 = STYLED_ITEM( '', ( #1219 ), #1220 ); +#392 = STYLED_ITEM( '', ( #1221 ), #1222 ); +#393 = STYLED_ITEM( '', ( #1223 ), #1224 ); +#394 = STYLED_ITEM( '', ( #1225 ), #1226 ); +#395 = STYLED_ITEM( '', ( #1227 ), #1228 ); +#396 = STYLED_ITEM( '', ( #1229 ), #1230 ); +#397 = STYLED_ITEM( '', ( #1231 ), #1232 ); +#398 = STYLED_ITEM( '', ( #1233 ), #1234 ); +#399 = STYLED_ITEM( '', ( #1235 ), #1236 ); +#400 = STYLED_ITEM( '', ( #1237 ), #1238 ); +#401 = STYLED_ITEM( '', ( #1239 ), #1240 ); +#402 = STYLED_ITEM( '', ( #1241 ), #1242 ); +#403 = STYLED_ITEM( '', ( #1243 ), #1244 ); +#404 = STYLED_ITEM( '', ( #1245 ), #1246 ); +#405 = STYLED_ITEM( '', ( #1247 ), #1248 ); +#406 = STYLED_ITEM( '', ( #1249 ), #1250 ); +#407 = STYLED_ITEM( '', ( #1251 ), #1252 ); +#408 = STYLED_ITEM( '', ( #1253 ), #1254 ); +#409 = STYLED_ITEM( '', ( #1255 ), #1256 ); +#410 = STYLED_ITEM( '', ( #1257 ), #1258 ); +#411 = STYLED_ITEM( '', ( #1259 ), #1260 ); +#412 = STYLED_ITEM( '', ( #1261 ), #1262 ); +#413 = STYLED_ITEM( '', ( #1263 ), #1264 ); +#414 = STYLED_ITEM( '', ( #1265 ), #1266 ); +#415 = STYLED_ITEM( '', ( #1267 ), #1268 ); +#416 = STYLED_ITEM( '', ( #1269 ), #1270 ); +#417 = STYLED_ITEM( '', ( #1271 ), #1272 ); +#418 = STYLED_ITEM( '', ( #1273 ), #1274 ); +#419 = STYLED_ITEM( '', ( #1275 ), #1276 ); +#420 = STYLED_ITEM( '', ( #1277 ), #1278 ); +#421 = STYLED_ITEM( '', ( #1279 ), #1280 ); +#422 = STYLED_ITEM( '', ( #1281 ), #1282 ); +#423 = STYLED_ITEM( '', ( #1283 ), #1284 ); +#424 = STYLED_ITEM( '', ( #1285 ), #1286 ); +#425 = STYLED_ITEM( '', ( #1287 ), #1288 ); +#426 = STYLED_ITEM( '', ( #1289 ), #1290 ); +#427 = STYLED_ITEM( '', ( #1291 ), #1292 ); +#428 = STYLED_ITEM( '', ( #1293 ), #1294 ); +#429 = STYLED_ITEM( '', ( #1295 ), #1296 ); +#430 = STYLED_ITEM( '', ( #1297 ), #1298 ); +#431 = STYLED_ITEM( '', ( #1299 ), #1300 ); +#432 = STYLED_ITEM( '', ( #1301 ), #1302 ); +#433 = STYLED_ITEM( '', ( #1303 ), #1304 ); +#434 = STYLED_ITEM( '', ( #1305 ), #1306 ); +#435 = STYLED_ITEM( '', ( #1307 ), #1308 ); +#436 = STYLED_ITEM( '', ( #1309 ), #1310 ); +#437 = STYLED_ITEM( '', ( #1311 ), #1312 ); +#438 = STYLED_ITEM( '', ( #1313 ), #1314 ); +#439 = STYLED_ITEM( '', ( #1315 ), #1316 ); +#440 = STYLED_ITEM( '', ( #1317 ), #1318 ); +#441 = STYLED_ITEM( '', ( #1319 ), #1320 ); +#442 = STYLED_ITEM( '', ( #1321 ), #1322 ); +#443 = STYLED_ITEM( '', ( #1323 ), #1324 ); +#444 = STYLED_ITEM( '', ( #1325 ), #1326 ); +#445 = STYLED_ITEM( '', ( #1327 ), #1328 ); +#446 = STYLED_ITEM( '', ( #1329 ), #1330 ); +#447 = STYLED_ITEM( '', ( #1331 ), #1332 ); +#448 = STYLED_ITEM( '', ( #1333 ), #1334 ); +#449 = STYLED_ITEM( '', ( #1335 ), #1336 ); +#450 = STYLED_ITEM( '', ( #1337 ), #1338 ); +#451 = STYLED_ITEM( '', ( #1339 ), #1340 ); +#452 = STYLED_ITEM( '', ( #1341 ), #1342 ); +#453 = STYLED_ITEM( '', ( #1343 ), #1344 ); +#454 = STYLED_ITEM( '', ( #1345 ), #1346 ); +#455 = STYLED_ITEM( '', ( #1347 ), #1348 ); +#456 = STYLED_ITEM( '', ( #1349 ), #1350 ); +#457 = STYLED_ITEM( '', ( #1351 ), #1352 ); +#458 = STYLED_ITEM( '', ( #1353 ), #1354 ); +#459 = STYLED_ITEM( '', ( #1355 ), #1356 ); +#460 = STYLED_ITEM( '', ( #1357 ), #1358 ); +#461 = STYLED_ITEM( '', ( #1359 ), #1360 ); +#462 = STYLED_ITEM( '', ( #1361 ), #1362 ); +#463 = STYLED_ITEM( '', ( #1363 ), #1364 ); +#464 = STYLED_ITEM( '', ( #1365 ), #1366 ); +#465 = STYLED_ITEM( '', ( #1367 ), #1368 ); +#466 = STYLED_ITEM( '', ( #1369 ), #1370 ); +#467 = STYLED_ITEM( '', ( #1371 ), #1372 ); +#468 = STYLED_ITEM( '', ( #1373 ), #1374 ); +#469 = STYLED_ITEM( '', ( #1375 ), #1376 ); +#470 = STYLED_ITEM( '', ( #1377 ), #1378 ); +#471 = STYLED_ITEM( '', ( #1379 ), #1380 ); +#472 = STYLED_ITEM( '', ( #1381 ), #1382 ); +#473 = STYLED_ITEM( '', ( #1383 ), #1384 ); +#474 = STYLED_ITEM( '', ( #1385 ), #1386 ); +#475 = STYLED_ITEM( '', ( #1387 ), #1388 ); +#476 = STYLED_ITEM( '', ( #1389 ), #1390 ); +#479 = UNCERTAINTY_MEASURE_WITH_UNIT( LENGTH_MEASURE( 3.93701000000000E-05 ), #481, '', '' ); +#481 = ( CONVERSION_BASED_UNIT( 'INCH', #1393 )LENGTH_UNIT( )NAMED_UNIT( #1396 ) ); +#482 = ( NAMED_UNIT( #1398 )PLANE_ANGLE_UNIT( )SI_UNIT( $, .RADIAN. ) ); +#483 = ( NAMED_UNIT( #1398 )SI_UNIT( $, .STERADIAN. )SOLID_ANGLE_UNIT( ) ); +#485 = PRODUCT( 'TSW-104-05-G-T', 'TSW-104-05-G-T', 'PART-TSW-104-05-G-T-DESC', ( #1404 ) ); +#486 = PRODUCT_DEFINITION( 'NONE', 'NONE', #1405, #1 ); +#487 = AXIS2_PLACEMENT_3D( '', #1406, #1407, #1408 ); +#488 = AXIS2_PLACEMENT_3D( '', #1409, #1410, #1411 ); +#489 = AXIS2_PLACEMENT_3D( '', #1412, #1413, #1414 ); +#490 = ( GEOMETRIC_REPRESENTATION_CONTEXT( 3 )GLOBAL_UNCERTAINTY_ASSIGNED_CONTEXT( ( #1417 ) )GLOBAL_UNIT_ASSIGNED_CONTEXT( ( #1419, #1420, #1421 ) )REPRESENTATION_CONTEXT( 'NONE', 'WORKSPACE' ) ); +#491 = PRODUCT( '_TSW-104-05-G-T_body', '_TSW-104-05-G-T_body', 'PART-_TSW-104-05-G-T_body-DESC', ( #1404 ) ); +#494 = ITEM_DEFINED_TRANSFORMATION( '', '', #487, #488 ); +#496 = NEXT_ASSEMBLY_USAGE_OCCURRENCE( 'NAUO1', '_TSW-104-05-G-T_body', '_TSW-104-05-G-T_body', #486, #497, $ ); +#497 = PRODUCT_DEFINITION( '_TSW-104-05-G-T_body', '_TSW-104-05-G-T_body', #1423, #1 ); +#498 = MANIFOLD_SOLID_BREP( '_TSW-104-05-G-T_body', #1424 ); +#499 = PRODUCT( '_T-1S6-21-TSW-1-05-4-T', '_T-1S6-21-TSW-1-05-4-T', 'PART-_T-1S6-21-TSW-1-05-4-T-DESC', ( #1404 ) ); +#502 = ITEM_DEFINED_TRANSFORMATION( '', '', #487, #489 ); +#504 = NEXT_ASSEMBLY_USAGE_OCCURRENCE( 'NAUO2', '_T-1S6-21-TSW-1-05-4-T', '_T-1S6-21-TSW-1-05-4-T', #486, #505, $ ); +#505 = PRODUCT_DEFINITION( '_T-1S6-21-TSW-1-05-4-T', '_T-1S6-21-TSW-1-05-4-T', #1425, #1 ); +#506 = MANIFOLD_SOLID_BREP( '_T-1S6-21-TSW-1-05-4-T', #1426 ); +#507 = PRESENTATION_STYLE_ASSIGNMENT( ( #1427 ) ); +#508 = ADVANCED_FACE( '', ( #1428 ), #1429, .T. ); +#509 = PRESENTATION_STYLE_ASSIGNMENT( ( #1430 ) ); +#510 = ADVANCED_FACE( '', ( #1431 ), #1432, .T. ); +#511 = PRESENTATION_STYLE_ASSIGNMENT( ( #1433 ) ); +#512 = ADVANCED_FACE( '', ( #1434 ), #1435, .T. ); +#513 = PRESENTATION_STYLE_ASSIGNMENT( ( #1436 ) ); +#514 = ADVANCED_FACE( '', ( #1437 ), #1438, .T. ); +#515 = PRESENTATION_STYLE_ASSIGNMENT( ( #1439 ) ); +#516 = ADVANCED_FACE( '', ( #1440 ), #1441, .T. ); +#517 = PRESENTATION_STYLE_ASSIGNMENT( ( #1442 ) ); +#518 = ADVANCED_FACE( '', ( #1443 ), #1444, .F. ); +#519 = PRESENTATION_STYLE_ASSIGNMENT( ( #1445 ) ); +#520 = ADVANCED_FACE( '', ( #1446, #1447, #1448, #1449 ), #1450, .T. ); +#521 = PRESENTATION_STYLE_ASSIGNMENT( ( #1451 ) ); +#522 = ADVANCED_FACE( '', ( #1452 ), #1453, .T. ); +#523 = PRESENTATION_STYLE_ASSIGNMENT( ( #1454 ) ); +#524 = ADVANCED_FACE( '', ( #1455 ), #1456, .T. ); +#525 = PRESENTATION_STYLE_ASSIGNMENT( ( #1457 ) ); +#526 = ADVANCED_FACE( '', ( #1458 ), #1459, .T. ); +#527 = PRESENTATION_STYLE_ASSIGNMENT( ( #1460 ) ); +#528 = ADVANCED_FACE( '', ( #1461 ), #1462, .F. ); +#529 = PRESENTATION_STYLE_ASSIGNMENT( ( #1463 ) ); +#530 = ADVANCED_FACE( '', ( #1464 ), #1465, .T. ); +#531 = PRESENTATION_STYLE_ASSIGNMENT( ( #1466 ) ); +#532 = ADVANCED_FACE( '', ( #1467 ), #1468, .F. ); +#533 = PRESENTATION_STYLE_ASSIGNMENT( ( #1469 ) ); +#534 = ADVANCED_FACE( '', ( #1470 ), #1471, .T. ); +#535 = PRESENTATION_STYLE_ASSIGNMENT( ( #1472 ) ); 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PRESENTATION_STYLE_ASSIGNMENT( ( #1502 ) ); +#556 = ADVANCED_FACE( '', ( #1503 ), #1504, .T. ); +#557 = PRESENTATION_STYLE_ASSIGNMENT( ( #1505 ) ); +#558 = ADVANCED_FACE( '', ( #1506 ), #1507, .T. ); +#559 = PRESENTATION_STYLE_ASSIGNMENT( ( #1508 ) ); +#560 = ADVANCED_FACE( '', ( #1509 ), #1510, .T. ); +#561 = PRESENTATION_STYLE_ASSIGNMENT( ( #1511 ) ); +#562 = ADVANCED_FACE( '', ( #1512 ), #1513, .T. ); +#563 = PRESENTATION_STYLE_ASSIGNMENT( ( #1514 ) ); +#564 = ADVANCED_FACE( '', ( #1515 ), #1516, .T. ); +#565 = PRESENTATION_STYLE_ASSIGNMENT( ( #1517 ) ); +#566 = ADVANCED_FACE( '', ( #1518 ), #1519, .F. ); +#567 = PRESENTATION_STYLE_ASSIGNMENT( ( #1520 ) ); +#568 = ADVANCED_FACE( '', ( #1521 ), #1522, .T. ); +#569 = PRESENTATION_STYLE_ASSIGNMENT( ( #1523 ) ); +#570 = ADVANCED_FACE( '', ( #1524 ), #1525, .T. ); +#571 = PRESENTATION_STYLE_ASSIGNMENT( ( #1526 ) ); +#572 = ADVANCED_FACE( '', ( #1527 ), #1528, .T. ); +#573 = PRESENTATION_STYLE_ASSIGNMENT( ( #1529 ) ); +#574 = ADVANCED_FACE( '', ( #1530 ), #1531, .T. ); +#575 = PRESENTATION_STYLE_ASSIGNMENT( ( #1532 ) ); +#576 = ADVANCED_FACE( '', ( #1533 ), #1534, .F. ); +#577 = PRESENTATION_STYLE_ASSIGNMENT( ( #1535 ) ); +#578 = ADVANCED_FACE( '', ( #1536 ), #1537, .T. ); +#579 = PRESENTATION_STYLE_ASSIGNMENT( ( #1538 ) ); +#580 = ADVANCED_FACE( '', ( #1539 ), #1540, .T. ); +#581 = PRESENTATION_STYLE_ASSIGNMENT( ( #1541 ) ); +#582 = ADVANCED_FACE( '', ( #1542 ), #1543, .T. ); +#583 = PRESENTATION_STYLE_ASSIGNMENT( ( #1544 ) ); +#584 = ADVANCED_FACE( '', ( #1545 ), #1546, .T. ); +#585 = PRESENTATION_STYLE_ASSIGNMENT( ( #1547 ) ); +#586 = ADVANCED_FACE( '', ( #1548 ), #1549, .T. ); +#587 = PRESENTATION_STYLE_ASSIGNMENT( ( #1550 ) ); +#588 = ADVANCED_FACE( '', ( #1551 ), #1552, .T. ); +#589 = PRESENTATION_STYLE_ASSIGNMENT( ( #1553 ) ); +#590 = ADVANCED_FACE( '', ( #1554 ), #1555, .T. ); +#591 = PRESENTATION_STYLE_ASSIGNMENT( ( #1556 ) ); +#592 = ADVANCED_FACE( '', ( #1557 ), #1558, .F. ); +#593 = PRESENTATION_STYLE_ASSIGNMENT( ( #1559 ) ); +#594 = ADVANCED_FACE( '', ( #1560 ), #1561, .T. ); +#595 = PRESENTATION_STYLE_ASSIGNMENT( ( #1562 ) ); +#596 = ADVANCED_FACE( '', ( #1563 ), #1564, .T. ); +#597 = PRESENTATION_STYLE_ASSIGNMENT( ( #1565 ) ); +#598 = ADVANCED_FACE( '', ( #1566 ), #1567, .T. ); +#599 = PRESENTATION_STYLE_ASSIGNMENT( ( #1568 ) ); +#600 = ADVANCED_FACE( '', ( #1569 ), #1570, .T. ); +#601 = PRESENTATION_STYLE_ASSIGNMENT( ( #1571 ) ); +#602 = ADVANCED_FACE( '', ( #1572 ), #1573, .T. ); +#603 = PRESENTATION_STYLE_ASSIGNMENT( ( #1574 ) ); +#604 = ADVANCED_FACE( '', ( #1575 ), #1576, .T. ); +#605 = PRESENTATION_STYLE_ASSIGNMENT( ( #1577 ) ); +#606 = ADVANCED_FACE( '', ( #1578 ), #1579, .T. ); +#607 = PRESENTATION_STYLE_ASSIGNMENT( ( #1580 ) ); +#608 = ADVANCED_FACE( '', ( #1581 ), #1582, .T. ); +#609 = PRESENTATION_STYLE_ASSIGNMENT( ( #1583 ) ); +#610 = ADVANCED_FACE( '', ( #1584 ), #1585, .F. ); +#611 = PRESENTATION_STYLE_ASSIGNMENT( ( #1586 ) ); +#612 = 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diff --git a/common.3dshapes/Synqor_PI31xx.step b/common.3dshapes/Synqor_PI31xx.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/TE_2-1445088-2.step b/common.3dshapes/TE_2-1445088-2.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/TE_2337857-1.step b/common.3dshapes/TE_2337857-1.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/TE_3-794679-2.step b/common.3dshapes/TE_3-794679-2.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/TE_6116075-1.step b/common.3dshapes/TE_6116075-1.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/TO-252-3_TI_KVU0003A.step b/common.3dshapes/TO-252-3_TI_KVU0003A.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/TO-252-5_TI_KVU0005A.step b/common.3dshapes/TO-252-5_TI_KVU0005A.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/TO-263-3_TI_KTT0003B.step b/common.3dshapes/TO-263-3_TI_KTT0003B.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/TO-263-5_TI_KTT0005A.step b/common.3dshapes/TO-263-5_TI_KTT0005A.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/XT60_Female.step b/common.3dshapes/XT60_Female.step old mode 100644 new mode 100755 diff --git a/common.3dshapes/XT60_Male.step b/common.3dshapes/XT60_Male.step old mode 100644 new mode 100755 diff --git a/common.pretty/Amphenol_12401832E402A.kicad_mod b/common.pretty/Amphenol_12401832E402A.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/C0402.kicad_mod b/common.pretty/C0402.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/C0402_NOSILK.kicad_mod b/common.pretty/C0402_NOSILK.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/C0603.kicad_mod b/common.pretty/C0603.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/C0805.kicad_mod b/common.pretty/C0805.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/C1206.kicad_mod b/common.pretty/C1206.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/C1210.kicad_mod b/common.pretty/C1210.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/CFT-125-01-L-D-RA-01-SL.kicad_mod b/common.pretty/CFT-125-01-L-D-RA-01-SL.kicad_mod new file mode 100755 index 0000000..5fab0fc --- /dev/null +++ b/common.pretty/CFT-125-01-L-D-RA-01-SL.kicad_mod @@ -0,0 +1,99 @@ +(footprint "CFT-125-01-L-D-RA-01-SL" (version 20210824) (generator pcbnew) (layer "F.Cu") + (tedit 6189F1D1) + (descr "Connector, Compact Flash") + (attr through_hole) + (fp_text reference "REF**" (at 0 -8.255 unlocked) (layer "F.SilkS") + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp 739e7edc-5b4f-43e0-8625-84d2479f17d4) + ) + (fp_text value "CFT-125-01-L-D-RA-01-SL" (at 0 0.635 unlocked) (layer "F.Fab") hide + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp 47ecfd74-2f82-47cd-934c-6220fd812f22) + ) + (fp_text user "${REFERENCE}" (at 0 1.5875 unlocked) (layer "F.Fab") + (effects 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(layers *.Cu *.Mask) (tstamp 65819532-758a-4ca6-8287-fc2535b33c85)) + (pad "25" thru_hole oval (at 15.24 -5.715) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp f31a44e3-ccb4-4f80-a1b9-b20ae9069845)) + (pad "26" thru_hole oval (at -15.24 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp a31cc0c1-25c2-481e-a750-ab8df68ec3ae)) + (pad "27" thru_hole oval (at -13.97 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 9908e761-badc-4975-aba7-cf6972019dbd)) + (pad "28" thru_hole oval (at -12.7 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp ee39309b-f024-4bb9-862c-b4a0d7c07936)) + (pad "29" thru_hole oval (at -11.43 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp cc310845-d993-4ae8-80b1-9c01516f1ac6)) + (pad "30" thru_hole oval (at -10.16 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 9c302b51-a97a-48c7-8fb7-9bf0e594bf18)) + (pad "31" thru_hole oval (at -8.89 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 0e04eac7-0453-4fd9-b32f-b9013de00609)) + (pad "32" thru_hole oval (at -7.62 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 7c0baf57-398b-41e6-b52e-6b57adc469e9)) + (pad "33" thru_hole oval (at -6.35 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 27f7e820-c4dc-4772-b3aa-f72051f5e55f)) + (pad "34" thru_hole oval (at -5.08 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 03d01f84-fc37-446b-a163-f072878735cf)) + (pad "35" thru_hole oval (at -3.81 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 99a43b98-b26f-40c6-820f-f2a728582f77)) + (pad "36" thru_hole oval (at -2.54 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 3677bb5d-9a26-44f7-a2c0-9d774c495cbd)) + (pad "37" thru_hole oval (at -1.27 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 283a02a4-525e-40a5-a120-a037b8ce7d09)) + (pad "38" thru_hole oval (at 0 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 1bd2eed2-d312-43fe-abf9-917785408c38)) + (pad "39" thru_hole oval (at 1.27 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 637696b5-a8b4-457e-9121-1f428592831b)) + (pad "40" thru_hole oval (at 2.54 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 15b37bc4-ba4b-433c-9e9b-03508a23bfbf)) + (pad "41" thru_hole oval (at 3.81 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 0f97a862-aea9-4545-89e8-3ae28c6a785f)) + (pad "42" thru_hole oval (at 5.08 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp f7a88d07-d2e1-45c8-b5f7-897770cbde69)) + (pad "43" thru_hole oval (at 6.35 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 02f528fe-927e-4ec5-960d-10db7615056d)) + (pad "44" thru_hole oval (at 7.62 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp c1c21b12-c367-4528-8abe-205ac53ec94c)) + (pad "45" thru_hole oval (at 8.89 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp e89d4d06-9253-4819-96b2-7cade51ff0c9)) + (pad "46" thru_hole oval (at 10.16 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 05f020a6-1795-42f8-9af5-566d29aa806e)) + (pad "47" thru_hole oval (at 11.43 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 07e00d0c-1b4a-43c0-a0db-ab0bfac24806)) + (pad "48" thru_hole oval (at 12.7 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 1959aca6-4e35-460b-b17c-5ea27b92ed3a)) + (pad "49" thru_hole oval (at 13.97 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp 1b6994fe-c6fa-4482-98c9-2f55994193f1)) + (pad "50" thru_hole oval (at 15.24 -2.54) (size 1.016 1.524) (drill 0.7112) (layers *.Cu *.Mask) (tstamp fc4ad78c-79de-4b03-b002-fade3f50d67f)) + (zone (net 0) (net_name "") (layer "F.Cu") (tstamp dea4f87b-f7f9-413c-9b75-631e10086f9e) (hatch edge 0.508) + (connect_pads (clearance 0)) + (min_thickness 0.254) + (keepout (tracks allowed) (vias allowed) (pads allowed ) (copperpour allowed) (footprints not_allowed)) + (fill (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 19.177 25.4) + (xy -19.177 25.4) + (xy -19.177 3.81) + (xy 19.177 3.81) + ) + ) + ) +) diff --git a/common.pretty/CK_1101M2S3CQE2.kicad_mod b/common.pretty/CK_1101M2S3CQE2.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/CK_T101MH9AQE.kicad_mod b/common.pretty/CK_T101MH9AQE.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/CONN_SuperSMA_Amphenol_901-10510-2.kicad_mod b/common.pretty/CONN_SuperSMA_Amphenol_901-10510-2.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/CRYSTAL_Abracon_ABM10AIG.kicad_mod b/common.pretty/CRYSTAL_Abracon_ABM10AIG.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_0402HP.kicad_mod b/common.pretty/Coilcraft_0402HP.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_ETH1-460L.kicad_mod b/common.pretty/Coilcraft_ETH1-460L.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_LPD5030.kicad_mod b/common.pretty/Coilcraft_LPD5030.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_LPS3015.kicad_mod b/common.pretty/Coilcraft_LPS3015.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_LPS5030.kicad_mod b/common.pretty/Coilcraft_LPS5030.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_LPS8045.kicad_mod b/common.pretty/Coilcraft_LPS8045.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_PFD2015.kicad_mod b/common.pretty/Coilcraft_PFD2015.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_XEL3515.kicad_mod b/common.pretty/Coilcraft_XEL3515.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_XEL3520.kicad_mod b/common.pretty/Coilcraft_XEL3520.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_XEL3530.kicad_mod b/common.pretty/Coilcraft_XEL3530.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_XEL5050_510.kicad_mod b/common.pretty/Coilcraft_XEL5050_510.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_XEL5050_520.kicad_mod b/common.pretty/Coilcraft_XEL5050_520.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_XEL5050_530.kicad_mod b/common.pretty/Coilcraft_XEL5050_530.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Coilcraft_XEL6060.kicad_mod b/common.pretty/Coilcraft_XEL6060.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Conn_FFC_Molex_5051102291-Adafruit_4421.kicad_mod b/common.pretty/Conn_FFC_Molex_5051102291-Adafruit_4421.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Conn_FFC_Molex_5051102291.kicad_mod b/common.pretty/Conn_FFC_Molex_5051102291.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Conn_MicroMateNLok_2-1445088-2.kicad_mod b/common.pretty/Conn_MicroMateNLok_2-1445088-2.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Conn_MicroMateNLok_3-794679-2.kicad_mod b/common.pretty/Conn_MicroMateNLok_3-794679-2.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/D0402.kicad_mod b/common.pretty/D0402.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/D0603.kicad_mod b/common.pretty/D0603.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/DF40HC(3.0)-100DS-0.4V(58).kicad_mod b/common.pretty/DF40HC(3.0)-100DS-0.4V(58).kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/DFN50P300X300X80-10P.kicad_mod b/common.pretty/DFN50P300X300X80-10P.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/DFN600X800_8P-W9.kicad_mod b/common.pretty/DFN600X800_8P-W9.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/DFN65P200X200X100-6P2_IRL100HS121.kicad_mod b/common.pretty/DFN65P200X200X100-6P2_IRL100HS121.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/DFN65P200X200X100-6P2_STL3N10F7.kicad_mod b/common.pretty/DFN65P200X200X100-6P2_STL3N10F7.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/DO-214AB.kicad_mod b/common.pretty/DO-214AB.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/DO-214AC.kicad_mod b/common.pretty/DO-214AC.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Deltron_571-0100_Black.kicad_mod b/common.pretty/Deltron_571-0100_Black.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Deltron_571-0200_Blue.kicad_mod b/common.pretty/Deltron_571-0200_Blue.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Deltron_571-0300_Brown.kicad_mod b/common.pretty/Deltron_571-0300_Brown.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Deltron_571-0400_Green.kicad_mod b/common.pretty/Deltron_571-0400_Green.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Deltron_571-0500_Red.kicad_mod b/common.pretty/Deltron_571-0500_Red.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Deltron_571-0600_White.kicad_mod b/common.pretty/Deltron_571-0600_White.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Deltron_571-0700_Yellow.kicad_mod b/common.pretty/Deltron_571-0700_Yellow.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/EVP-AEDB2A.kicad_mod b/common.pretty/EVP-AEDB2A.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/G6K-2F-Y.kicad_mod b/common.pretty/G6K-2F-Y.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/HSEC8-120-01-L-DV-A-WT-TR.kicad_mod b/common.pretty/HSEC8-120-01-L-DV-A-WT-TR.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/HSEC8-120-01-L-RA.kicad_mod b/common.pretty/HSEC8-120-01-L-RA.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/HSEC8-120.kicad_mod b/common.pretty/HSEC8-120.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Header_1_1.kicad_mod b/common.pretty/Header_1_1.kicad_mod old mode 100644 new mode 100755 index 5dbf9a0..0b9c932 --- a/common.pretty/Header_1_1.kicad_mod +++ b/common.pretty/Header_1_1.kicad_mod @@ -1,6 +1,6 @@ -(footprint "Header_1_1" (version 20210606) (generator pcbnew) (layer "F.Cu") - (tedit 60DAB1F8) - (descr "Header, 0.100\", 1x1, PTH") +(footprint "Header_1_1" (version 20211014) (generator pcbnew) (layer "F.Cu") + (tedit 61882CA1) + (descr "Header, 0.1\", 1x01, PTH") (attr through_hole) (fp_text reference "REF**" (at 0 -1.905) (layer "F.SilkS") (effects (font (size 0.762 0.762) (thickness 0.127))) diff --git a/common.pretty/Header_1_2.kicad_mod b/common.pretty/Header_1_2.kicad_mod old mode 100644 new mode 100755 index ce95178..d783b4f --- a/common.pretty/Header_1_2.kicad_mod +++ b/common.pretty/Header_1_2.kicad_mod @@ -1,6 +1,6 @@ -(footprint "Header_1_2" (version 20210606) (generator pcbnew) (layer "F.Cu") - (tedit 60DAB1FF) - (descr "Header, 0.100\", 1x2, PTH") +(footprint "Header_1_2" (version 20211014) (generator pcbnew) (layer "F.Cu") + (tedit 61882CA5) + (descr "Header, 0.1\", 1x02, PTH") (attr through_hole) (fp_text reference "REF**" (at 0 -1.905) (layer "F.SilkS") (effects (font (size 0.762 0.762) (thickness 0.127))) diff --git a/common.pretty/JST_S4B-XH-SM4-TB.kicad_mod b/common.pretty/JST_S4B-XH-SM4-TB.kicad_mod old mode 100644 new mode 100755 index 9f0e306..ff6eeed --- a/common.pretty/JST_S4B-XH-SM4-TB.kicad_mod +++ b/common.pretty/JST_S4B-XH-SM4-TB.kicad_mod @@ -1,6 +1,6 @@ -(footprint "JST_S4B-XH-SM4-TB" (version 20210606) (generator pcbnew) (layer "F.Cu") - (tedit 60DAC511) - (descr "Connector, 2.5mm, Right Angle, SMD") +(footprint "JST_S4B-XH-SM4-TB" (version 20211014) (generator pcbnew) (layer "F.Cu") + (tedit 61882C74) + (descr "Connector, 2.5mm, 1x04, Right Angle, SMD") (attr smd) (fp_text reference "REF**" (at 0 -11.684 unlocked) (layer "F.SilkS") (effects (font (size 0.635 0.635) (thickness 0.127))) diff --git a/common.pretty/Keystone_1043.kicad_mod b/common.pretty/Keystone_1043.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Keystone_5005_Red.kicad_mod b/common.pretty/Keystone_5005_Red.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Keystone_5006_Black.kicad_mod b/common.pretty/Keystone_5006_Black.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Keystone_5007_White.kicad_mod b/common.pretty/Keystone_5007_White.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Keystone_5008_Orange.kicad_mod b/common.pretty/Keystone_5008_Orange.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Keystone_5009_Yellow.kicad_mod b/common.pretty/Keystone_5009_Yellow.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Keystone_5010_Red.kicad_mod b/common.pretty/Keystone_5010_Red.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Keystone_5011_Black.kicad_mod b/common.pretty/Keystone_5011_Black.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Keystone_5019.kicad_mod b/common.pretty/Keystone_5019.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/LED0402.kicad_mod b/common.pretty/LED0402.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/LED0603.kicad_mod b/common.pretty/LED0603.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/LSHM-150-03.0-L-DV-A-S-TR.kicad_mod b/common.pretty/LSHM-150-03.0-L-DV-A-S-TR.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/LSHM-150-03.0-L-DV-A-S-TR_DUAL.kicad_mod b/common.pretty/LSHM-150-03.0-L-DV-A-S-TR_DUAL.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/MH120X230_#4.kicad_mod b/common.pretty/MH120X230_#4.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/MH120X230_#4_NOSILK.kicad_mod b/common.pretty/MH120X230_#4_NOSILK.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/MH90X180_#2.kicad_mod b/common.pretty/MH90X180_#2.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/MH90X180_#2_NOSILK.kicad_mod b/common.pretty/MH90X180_#2_NOSILK.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/MPD_BK-335-SM.kicad_mod b/common.pretty/MPD_BK-335-SM.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/MYBSP01201ABF.kicad_mod b/common.pretty/MYBSP01201ABF.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/MiniCircuits_JC0603-1_Filter.kicad_mod b/common.pretty/MiniCircuits_JC0603-1_Filter.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Molex_430450207.kicad_mod b/common.pretty/Molex_430450207.kicad_mod new file mode 100755 index 0000000..aee8de6 --- /dev/null +++ b/common.pretty/Molex_430450207.kicad_mod @@ -0,0 +1,62 @@ +(footprint "Molex_430450207" (version 20211014) (generator pcbnew) (layer "F.Cu") + (tedit 6188361D) + (descr "Connector, Micro-Fit 3.0, 2x01, Right Angle, SMD, Retention Clip") + (attr smd) + (fp_text reference "REF**" (at 2.667 -6.35 unlocked) (layer "F.SilkS") + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp f4de5818-e3a7-4263-b513-ce13b3eed8f6) + ) + (fp_text value "Molex_430450207" (at 0 0.635 unlocked) (layer "F.Fab") hide + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp 3741f39f-c505-4147-a887-a8c7299eeefb) + ) + (fp_text user "${REFERENCE}" (at 0 0 270 unlocked) (layer "F.Fab") + (effects (font (size 1.27 1.27) (thickness 0.254))) + (tstamp 20ed00fc-3e59-44ca-ba3f-64bcd7f8ef16) + ) + (fp_line (start -0.889 -5.723907) (end -3.937 -5.723907) (layer "F.SilkS") (width 0.1778) (tstamp 01e4a581-d808-4b5c-ba40-ce73a7e561bf)) + (fp_line (start 3.937 2.54) (end 3.937 -5.715) (layer "F.SilkS") (width 0.1778) (tstamp 2450d54d-2a23-4226-9975-b6550502e0fe)) + (fp_line (start -3.937 2.54) (end -3.937 -5.723907) (layer "F.SilkS") (width 0.1778) (tstamp 75937a1c-77e1-4643-b71e-f35aa28bbcec)) + (fp_line (start 3.937 -5.715) (end 0.889 -5.715) (layer "F.SilkS") (width 0.1778) (tstamp faf96c63-250a-4ffb-96af-a07844226df7)) + (fp_line (start 3.5814 -5.3086) (end 3.5814 4.5974) (layer "F.Fab") (width 0.127) (tstamp 015ace04-664d-42ba-8952-06d59ce26d4d)) + (fp_line (start 3.5814 -5.3086) (end -3.5814 -5.3086) (layer "F.Fab") (width 0.127) (tstamp 39cf6ebe-0f3b-4192-ad7f-de75fed2b077)) + (fp_line (start -3.5814 -5.3086) (end -3.5814 4.5974) (layer "F.Fab") (width 0.127) (tstamp 6bd841d2-8e8b-41c0-a11c-f5b160aaab07)) + (fp_line (start -3.5814 4.5974) (end 3.5814 4.5974) (layer "F.Fab") (width 0.127) (tstamp 8e5125f2-17ee-4efb-9c96-6f50c389c607)) + (pad "0" thru_hole circle (at -2.1463 0) (size 2.794 2.794) (drill 2.413) (layers *.Cu *.Mask) (tstamp 5f624558-4483-4fbd-9262-24be50ede081)) + (pad "0" thru_hole circle (at 2.1463 0) (size 2.794 2.794) (drill 2.413) (layers *.Cu *.Mask) (tstamp 7d736238-5368-4bad-af80-2437aa6c268f)) + (pad "1" smd roundrect (at 0 -5.4737) (size 1.27 2.921) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 7e2ba626-60bc-4a8e-a16b-38ff5399f890)) + (pad "2" smd roundrect (at 0 -10.0965) (size 1.27 2.921) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp a1d4f6a0-2dc2-403b-b5ec-5ba4fda0d713)) + (zone (net 0) (net_name "") (layer "F.Cu") (tstamp 5e49452f-1626-45df-8d53-17416206cd51) (hatch edge 0.508) + (connect_pads (clearance 0)) + (min_thickness 0.254) + (keepout (tracks not_allowed) (vias not_allowed) (pads not_allowed ) (copperpour not_allowed) (footprints allowed)) + (fill (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 4.0894 -2.2225) + (xy 1.651 -2.2225) + (xy 1.651 -3.8227) + (xy 4.0894 -3.8227) + ) + ) + ) + (zone (net 0) (net_name "") (layer "F.Cu") (tstamp a972c0da-4c2e-4de1-9678-11fdf61c4854) (hatch edge 0.508) + (connect_pads (clearance 0)) + (min_thickness 0.254) + (keepout (tracks not_allowed) (vias not_allowed) (pads not_allowed ) (copperpour not_allowed) (footprints allowed)) + (fill (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy -1.651 -2.2225) + (xy -4.0894 -2.2225) + (xy -4.0894 -3.8227) + (xy -1.651 -3.8227) + ) + ) + ) + (model "${KICAD_BHLIB_DIR}/common.3dshapes/Molex_430450207.stp" + (offset (xyz 0 0.3556 3.9624)) + (scale (xyz 1 1 1)) + (rotate (xyz -90 0 0)) + ) +) diff --git a/common.pretty/Molex_5022505191.kicad_mod b/common.pretty/Molex_5022505191.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Molex_532610571.kicad_mod b/common.pretty/Molex_532610571.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_1x02_P5.08mm_Vertical.kicad_mod b/common.pretty/PinHeader_1x02_P5.08mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_1x03_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_1x03_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_1x05_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_1x05_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_1x06_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_1x06_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_1x08_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_1x08_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_1x18_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_1x18_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_1x20_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_1x20_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_2x02_P1.27mm_Vertical-Samtec_FTSH-102-01-F-D.kicad_mod b/common.pretty/PinHeader_2x02_P1.27mm_Vertical-Samtec_FTSH-102-01-F-D.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_2x02_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_2x02_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_2x03_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_2x03_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_2x05_P1.27mm_Vertical-Samtec_FTSH-105-01-F-DV-K-A.kicad_mod b/common.pretty/PinHeader_2x05_P1.27mm_Vertical-Samtec_FTSH-105-01-F-DV-K-A.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_2x05_P1.27mm_Vertical-Samtec_FTSH-105-01-L-D-K.kicad_mod b/common.pretty/PinHeader_2x05_P1.27mm_Vertical-Samtec_FTSH-105-01-L-D-K.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_2x05_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_2x05_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_2x20_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_2x20_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_2x40_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_2x40_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_3x30_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_3x30_P2.54mm_Vertical.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/PinHeader_3x4_P2.54mm_Vertical.kicad_mod b/common.pretty/PinHeader_3x4_P2.54mm_Vertical.kicad_mod new file mode 100755 index 0000000..f4c3f39 --- /dev/null +++ b/common.pretty/PinHeader_3x4_P2.54mm_Vertical.kicad_mod @@ -0,0 +1,35 @@ +(footprint "PinHeader_3x4_P2.54mm_Vertical" (version 20210824) (generator pcbnew) (layer "F.Cu") + (tedit 614F9060) + (attr through_hole) + (fp_text reference "REF**" (at 0 -1.905) (layer "F.SilkS") + (effects (font (size 0.762 0.762) (thickness 0.127))) + (tstamp 9362e76e-978e-4f84-8caa-57ac3855ebad) + ) + (fp_text value "PinHeader_3x4_P2.54mm_Vertical" (at 0 -3.048) (layer "F.Fab") + (effects (font (size 0.762 0.762) (thickness 0.127))) + (tstamp f5781722-3330-441f-9f48-cae8ec29fe76) + ) + (fp_line (start -1.27 -1.27) (end 8.838425 -1.27) (layer "F.SilkS") (width 0.1778) (tstamp 3d678caa-0f38-4b78-b8de-0faf7daaf758)) + (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.1778) (tstamp 84ad56b8-5351-492c-83ae-64e7f595a656)) + (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer "F.SilkS") (width 0.1778) (tstamp 9f337ed0-79bf-4424-9e38-d9a33ddf13b0)) + (fp_line (start -1.27 6.35) (end -1.27 -1.27) (layer "F.SilkS") (width 0.1778) (tstamp b53083a9-4a2b-40f5-b421-d4d9fb95a8cf)) + (fp_line (start 8.838425 -1.27) (end 8.838425 6.35) (layer "F.SilkS") (width 0.1778) (tstamp c4e05bec-eb8d-4848-9d07-0b3211234749)) + (fp_line (start 8.838425 6.35) (end -1.27 6.35) (layer "F.SilkS") (width 0.1778) (tstamp e7145cf1-d1ce-4d8c-ad9d-521c2fc7183c)) + (pad "1" thru_hole rect (at 0 0) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp 1c3750d5-d8a9-4122-aa3f-672ff81c79bc)) + (pad "2" thru_hole circle (at 0 2.54) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp 2737ee6e-0c09-4b27-8777-e5ab638785ac)) + (pad "3" thru_hole circle (at 0 5.08) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp 6535b425-ecdd-41c8-941d-de3e93c6744d)) + (pad "4" thru_hole circle (at 2.54 0) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp ecbef67f-cd0c-417e-8b8d-26a4bb1b9cdc)) + (pad "5" thru_hole circle (at 2.54 2.54) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp acac5cc8-1d36-4724-b964-5c3f47544d9e)) + (pad "6" thru_hole circle (at 2.54 5.08) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp fe197f1e-622f-4771-9564-b5af8ecc3551)) + (pad "7" thru_hole circle (at 5.08 0) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp 01f236c9-cc9a-4056-8c3e-17813d31f830)) + (pad "8" thru_hole circle (at 5.08 2.54) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp fa5ec43b-b5ed-4669-a89a-9c45e586f29f)) + (pad "9" thru_hole circle (at 5.08 5.08) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp 598306fe-3773-4d25-a603-f70e02751d5f)) + (pad "10" thru_hole circle (at 7.62 0) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp 7be3c60b-c12e-472b-9539-cbc9061f6041)) + (pad "11" thru_hole circle (at 7.62 2.54) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp e352245f-2b5c-492d-ba57-2f32a6974986)) + (pad "12" thru_hole circle (at 7.62 5.08) (size 1.778 1.778) (drill 0.9906) (layers *.Cu *.Mask) (tstamp 2a77345b-8ada-4941-9161-d24b54f8cd6b)) + (model "${KICAD_BHLIB_DIR}/common.3dshapes/Samtec_TSW-104-05-G-T.step" + (offset (xyz 3.81 -2.54 2.54)) + (scale (xyz 1 1 1)) + (rotate (xyz 90 0 0)) + ) +) diff --git a/common.pretty/QFN40P400X400X80-32P.kicad_mod b/common.pretty/QFN40P400X400X80-32P.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/QFN40P800X800X90-64P.kicad_mod b/common.pretty/QFN40P800X800X90-64P.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/QFN50P500X500X90-32P.kicad_mod b/common.pretty/QFN50P500X500X90-32P.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/QFN50P500X700X90-38P.kicad_mod b/common.pretty/QFN50P500X700X90-38P.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/QFN65P400X400X75-16P.kicad_mod b/common.pretty/QFN65P400X400X75-16P.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/QFN65P400X400X80-16P_FT230XQ.kicad_mod b/common.pretty/QFN65P400X400X80-16P_FT230XQ.kicad_mod new file mode 100755 index 0000000..201d859 --- /dev/null +++ b/common.pretty/QFN65P400X400X80-16P_FT230XQ.kicad_mod @@ -0,0 +1,56 @@ +(footprint "QFN65P400X400X80-16P_FT230XQ" (version 20211014) (generator pcbnew) (layer "F.Cu") + (tedit 61884065) + (descr "Matches FT230XQ pads") + (attr through_hole) + (fp_text reference "REF**" (at 0 -3.048) (layer "F.SilkS") + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp 54d238d6-d9a5-477a-abe7-3ec55fc80421) + ) + (fp_text value "QFN65P400X400X80-16P_FT230XQ" (at 0 3.5) (layer "F.Fab") hide + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp 0a3c18eb-e6f9-4622-8e53-63137ee96250) + ) + (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab") + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp 4c19ca2e-7a48-4da1-b131-cb973e19fcd5) + ) + (fp_line (start -1.397 -2.413) (end -1.651 -2.413) (layer "F.SilkS") (width 0.1778) (tstamp 0411f564-3f4d-4b70-b118-d1946830f423)) + (fp_line (start -2.413 -1.651) (end -2.413 -1.397) (layer "F.SilkS") (width 0.1778) (tstamp 1176268d-e96d-4d77-8032-4a3052122830)) + (fp_line (start 2.413 1.524) (end 2.413 2.413) (layer "F.SilkS") (width 0.1778) (tstamp 4320227c-cfdd-49ea-8ddc-b7b95aa9dfb5)) + (fp_line (start -1.524 2.413) (end -2.413 2.413) (layer "F.SilkS") (width 0.1778) (tstamp 4fcc72ce-a356-4154-8428-c6b24183adc8)) + (fp_line (start 1.524 -2.413) (end 2.413 -2.413) (layer "F.SilkS") (width 0.1778) (tstamp 5298aac6-a6f2-416d-8897-4d1e8fa9b23d)) + (fp_line (start 2.413 -2.413) (end 2.413 -1.524) (layer "F.SilkS") (width 0.1778) (tstamp 572b32b9-7b7d-4e4f-a4ef-f1b43503d1b3)) + (fp_line (start 2.413 2.413) (end 1.524 2.413) (layer "F.SilkS") (width 0.1778) (tstamp 7ba5cf82-b32c-49d5-9ff9-ea9ee58f9622)) + (fp_line (start -2.413 2.413) (end -2.413 1.524) (layer "F.SilkS") (width 0.1778) (tstamp e2cde14d-3abf-4848-9f14-7b922302803e)) + (fp_arc (start -2.413 -1.651) (mid -2.189815 -2.189815) (end -1.651 -2.413) (layer "F.SilkS") (width 0.1778) (tstamp 53f642e9-78e3-4239-94df-16fb4ac138d8)) + (fp_rect (start -2 -2) (end 2 2) (layer "F.Fab") (width 0.127) (fill none) (tstamp acf6c997-336a-4e7e-b11f-b047b0484568)) + (fp_poly (pts + (xy -1 -2) + (xy -2 -1) + (xy -2 -2) + ) (layer "F.Fab") (width 0.127) (fill solid) (tstamp 57a925a9-75dc-4ec5-b7b1-e54c41dbf9ed)) + (pad "0" smd rect (at -0.525 -0.525) (size 1.05 1.05) (layers "F.Cu" "F.Paste" "F.Mask") + (solder_paste_margin -0.75) (tstamp cc16a017-4f33-4590-a7fd-a78a040dc3fc)) + (pad "0" smd rect (at 0.525 -0.525) (size 1.05 1.05) (layers "F.Cu" "F.Paste" "F.Mask") + (solder_paste_margin -0.75) (tstamp cc16a017-4f33-4590-a7fd-a78a040dc3fc)) + (pad "0" smd rect (at -0.525 0.525) (size 1.05 1.05) (layers "F.Cu" "F.Paste" "F.Mask") + (solder_paste_margin -0.75) (tstamp cc16a017-4f33-4590-a7fd-a78a040dc3fc)) + (pad "0" smd rect (at 0.525 0.525) (size 1.05 1.05) (layers "F.Cu" "F.Paste" "F.Mask") + (solder_paste_margin -0.75) (tstamp cc16a017-4f33-4590-a7fd-a78a040dc3fc)) + (pad "1" smd rect (at -1.825 -0.975 90) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 36e01a95-8569-438f-b984-f242d9696343)) + (pad "2" smd rect (at -1.825 -0.325 90) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 36e01a95-8569-438f-b984-f242d9696343)) + (pad "3" smd rect (at -1.825 0.325 90) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 36e01a95-8569-438f-b984-f242d9696343)) + (pad "4" smd rect (at -1.825 0.975 90) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 36e01a95-8569-438f-b984-f242d9696343)) + (pad "5" smd rect (at -0.975 1.825) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 708a0997-1865-4c2f-b4a3-b50b4d6144d6)) + (pad "6" smd rect (at -0.325 1.825) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 708a0997-1865-4c2f-b4a3-b50b4d6144d6)) + (pad "7" smd rect (at 0.325 1.825) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 708a0997-1865-4c2f-b4a3-b50b4d6144d6)) + (pad "8" smd rect (at 0.975 1.825) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 708a0997-1865-4c2f-b4a3-b50b4d6144d6)) + (pad "9" smd rect (at 1.825 0.975 90) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 36e01a95-8569-438f-b984-f242d9696343)) + (pad "10" smd rect (at 1.825 0.325 90) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 36e01a95-8569-438f-b984-f242d9696343)) + (pad "11" smd rect (at 1.825 -0.325 90) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 36e01a95-8569-438f-b984-f242d9696343)) + (pad "12" smd rect (at 1.825 -0.975 90) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 36e01a95-8569-438f-b984-f242d9696343)) + (pad "13" smd rect (at 0.975 -1.825) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 708a0997-1865-4c2f-b4a3-b50b4d6144d6)) + (pad "14" smd rect (at 0.325 -1.825) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 708a0997-1865-4c2f-b4a3-b50b4d6144d6)) + (pad "15" smd rect (at -0.325 -1.825) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 708a0997-1865-4c2f-b4a3-b50b4d6144d6)) + (pad "16" smd rect (at -0.975 -1.825) (size 0.37 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 708a0997-1865-4c2f-b4a3-b50b4d6144d6)) +) diff --git a/common.pretty/QFP50P1400X1400X120-128P.kicad_mod b/common.pretty/QFP50P1400X1400X120-128P.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/QFP50P2000X2000X160-144N.kicad_mod b/common.pretty/QFP50P2000X2000X160-144N.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/R0402.kicad_mod b/common.pretty/R0402.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/R0402_NOSILK.kicad_mod b/common.pretty/R0402_NOSILK.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/R0603.kicad_mod b/common.pretty/R0603.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/R0805.kicad_mod b/common.pretty/R0805.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/R1206.kicad_mod b/common.pretty/R1206.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/R1210.kicad_mod b/common.pretty/R1210.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/RaspberryPi-CM4.kicad_mod b/common.pretty/RaspberryPi-CM4.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOD-123.kicad_mod b/common.pretty/SOD-123.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOD-323.kicad_mod b/common.pretty/SOD-323.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOIC127P440X200-4.kicad_mod b/common.pretty/SOIC127P440X200-4.kicad_mod old mode 100644 new mode 100755 index 536ddde..9006485 --- a/common.pretty/SOIC127P440X200-4.kicad_mod +++ b/common.pretty/SOIC127P440X200-4.kicad_mod @@ -1,6 +1,6 @@ -(footprint "SOIC127P440X200-4" (version 20210606) (generator pcbnew) (layer "F.Cu") - (tedit 60CEFDC5) - (descr "TCMT1110") +(footprint "SOIC127P440X200-4" (version 20211014) (generator pcbnew) (layer "F.Cu") + (tedit 61883423) + (descr "WRONG_NAME, TCMT1110") (attr smd) (fp_text reference "REF**" (at 0 -2.413 unlocked) (layer "F.SilkS") (effects (font (size 0.635 0.635) (thickness 0.127))) @@ -20,15 +20,19 @@ (fp_line (start -2.54 1.778) (end 2.54 1.778) (layer "F.SilkS") (width 0.1778) (tstamp a76790e4-590f-46c7-b775-5532799a7df3)) (fp_line (start 2.54 -1.397) (end 2.54 -1.778) (layer "F.SilkS") (width 0.1778) (tstamp c207c93f-12d6-420f-b292-09de807189e4)) (fp_line (start 2.54 -1.778) (end -2.54 -1.778) (layer "F.SilkS") (width 0.1778) (tstamp ebb30184-85ec-48b9-a3b5-0549ff2489ba)) - (fp_poly (pts (xy -1.651 -1.397) - (xy -2.286 -1.397) - (xy -2.54 -1.397) - (xy -2.54 -1.778) - (xy -1.27 -1.778)) (layer "F.SilkS") (width 0.1778) (fill solid) (tstamp b3c5e892-9f45-4bcd-b5e7-90bd1c4357d6)) + (fp_poly (pts + (xy -1.651 -1.397) + (xy -2.286 -1.397) + (xy -2.54 -1.397) + (xy -2.54 -1.778) + (xy -1.27 -1.778) + ) (layer "F.SilkS") (width 0.1778) (fill solid) (tstamp b3c5e892-9f45-4bcd-b5e7-90bd1c4357d6)) (fp_rect (start -2.2 -1.425) (end 2.2 1.425) (layer "F.Fab") (width 0.127) (fill none) (tstamp 5a84df44-6643-449b-8d30-96af4385f533)) - (fp_poly (pts (xy -2.2 -0.79) - (xy -2.2 -1.425) - (xy -1.565 -1.425)) (layer "F.Fab") (width 0.127) (fill solid) (tstamp adc6418e-1ea4-45b8-895a-c4366637ae55)) + (fp_poly (pts + (xy -2.2 -0.79) + (xy -2.2 -1.425) + (xy -1.565 -1.425) + ) (layer "F.Fab") (width 0.127) (fill solid) (tstamp adc6418e-1ea4-45b8-895a-c4366637ae55)) (pad "1" smd rect (at -3.15 -0.635) (size 1.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6b4b8dc2-adba-4941-9fd4-7078a2d95c8e)) (pad "2" smd rect (at -3.15 0.635) (size 1.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b8d1533c-53fb-4ada-b03f-b192a501a916)) (pad "3" smd rect (at 3.15 0.635) (size 1.3 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp cfe7904d-e753-4c2e-bf22-da0014be2b0d)) diff --git a/common.pretty/SOIC127P600X175-8.kicad_mod b/common.pretty/SOIC127P600X175-8.kicad_mod new file mode 100755 index 0000000..93e5fe1 --- /dev/null +++ b/common.pretty/SOIC127P600X175-8.kicad_mod @@ -0,0 +1,51 @@ +(footprint "SOIC127P600X175-8" (version 20211014) (generator pcbnew) (layer "F.Cu") + (tedit 61883996) + (attr smd) + (fp_text reference "REF**" (at 0 -3.429 unlocked) (layer "F.SilkS") + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp efba3fd5-b849-4090-99c3-f14204c633d4) + ) + (fp_text value "SOIC127P600X175-8" (at 0 0.635 unlocked) (layer "F.Fab") hide + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp 56e96f7c-6de5-4b3b-88e4-775d54dd6afc) + ) + (fp_text user "${REFERENCE}" (at 0 0 270 unlocked) (layer "F.Fab") + (effects (font (size 0.635 0.635) (thickness 0.127))) + (tstamp 7ac3aaf9-5dc9-4d12-b75e-85f241657c1c) + ) + (fp_line (start -2.286 -2.794) (end 2.286 -2.794) (layer "F.SilkS") (width 0.1778) (tstamp 2069b501-9210-489c-82e6-969c3bacc7fc)) + (fp_line (start -2.286 -2.54) (end -1.778 -2.54) (layer "F.SilkS") (width 0.1778) (tstamp 3690e47a-3a3c-443a-940b-3601e63a8352)) + (fp_line (start 2.286 -2.794) (end 2.286 -2.54) (layer "F.SilkS") (width 0.1778) (tstamp 8583c524-e65a-47cb-b13d-e8401d8b44e4)) + (fp_line (start -1.778 -2.54) (end -1.778 -1.524) (layer "F.SilkS") (width 0.1778) (tstamp 890e0b08-0cfb-4444-9eb9-df62140bf95e)) + (fp_line (start -2.286 -2.794) (end -2.286 -2.54) (layer "F.SilkS") (width 0.1778) (tstamp 962a9744-4c94-42aa-9d0b-a16d05e853e0)) + (fp_line (start -2.286 2.54) (end -2.286 2.794) (layer "F.SilkS") (width 0.1778) (tstamp a66f0076-1e98-4b81-9b17-510d6cef1b90)) + (fp_line (start 2.286 2.794) (end 2.286 2.54) (layer "F.SilkS") (width 0.1778) (tstamp bc77a2d4-3f8d-4d12-befa-e965f66e99a4)) + (fp_line (start -1.778 -1.524) (end -0.508 -2.794) (layer "F.SilkS") (width 0.1778) (tstamp c19ee080-5dd2-42b0-9489-2f321abc75df)) + (fp_line (start -2.286 2.794) (end 2.286 2.794) (layer "F.SilkS") (width 0.1778) (tstamp d0251841-4e2c-40f3-85e7-12d368d2a157)) + (fp_poly (pts + (xy -1.778 -1.524) + (xy -1.778 -2.54) + (xy -2.286 -2.54) + (xy -2.286 -2.794) + (xy -0.508 -2.794) + ) (layer "F.SilkS") (width 0.1778) (fill solid) (tstamp 4ffccc78-6870-4f08-b380-34f05102ae9b)) + (fp_rect (start -2 -2.5) (end 2 2.5) (layer "F.Fab") (width 0.127) (fill none) (tstamp 4bb38588-6e47-499d-8671-96576ce15049)) + (fp_poly (pts + (xy -2 -1.27) + (xy -2 -2.5) + (xy -0.762 -2.5) + ) (layer "F.Fab") (width 0.127) (fill solid) (tstamp c0a6e2f6-2487-48f3-bc91-0bf63497bcd6)) + (pad "1" smd roundrect (at -2.75 -1.905) (size 1.4 0.762) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp b7a656c8-57af-4a27-80b2-31c912e5e635)) + (pad "2" smd roundrect (at -2.75 -0.635) (size 1.4 0.762) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 9c2cd576-db4b-4c5e-a3d2-07ecd111b9f7)) + (pad "3" smd roundrect (at -2.75 0.635) (size 1.4 0.762) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 571158aa-6386-4ce9-819c-5ef797d46e88)) + (pad "4" smd roundrect (at -2.75 1.905) (size 1.4 0.762) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp d51a2cef-dca4-4799-acae-955d855591f3)) + (pad "5" smd roundrect (at 2.75 1.905) (size 1.4 0.762) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp abeb9710-678b-4000-9e72-bb4a9e05d45d)) + (pad "6" smd roundrect (at 2.75 0.635) (size 1.4 0.762) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 04cc1ee4-5746-43a3-aff1-79ec1954bdcb)) + (pad "7" smd roundrect (at 2.75 -0.635) (size 1.4 0.762) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp 9bfcf6b7-cb8f-4117-bab8-757094e3ceb0)) + (pad "8" smd roundrect (at 2.75 -1.905) (size 1.4 0.762) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (tstamp f6b2746c-0439-4711-99db-255aaf99387a)) + (model "${KICAD_BHLIB_DIR}/common.3dshapes/SOIC127P600X175-8.step" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz -90 0 90)) + ) +) diff --git a/common.pretty/SOP50P300X110-10N.kicad_mod b/common.pretty/SOP50P300X110-10N.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOP50P490X110-10N.kicad_mod b/common.pretty/SOP50P490X110-10N.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOP80P1016X120-54N.kicad_mod b/common.pretty/SOP80P1016X120-54N.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOT-223.kicad_mod b/common.pretty/SOT-223.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOT-23-5.kicad_mod b/common.pretty/SOT-23-5.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOT-23-6.kicad_mod b/common.pretty/SOT-23-6.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOT-323.kicad_mod b/common.pretty/SOT-323.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOT-353.kicad_mod b/common.pretty/SOT-353.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOT-363.kicad_mod b/common.pretty/SOT-363.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOT-553.kicad_mod b/common.pretty/SOT-553.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SOT-563.kicad_mod b/common.pretty/SOT-563.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/SPST_SKQG.kicad_mod b/common.pretty/SPST_SKQG.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Samtec_MUSB-05-F-B-SM-A.kicad_mod b/common.pretty/Samtec_MUSB-05-F-B-SM-A.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Samtec_SMH-105-02-G-D.kicad_mod b/common.pretty/Samtec_SMH-105-02-G-D.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Samtec_SMH-106-02-G-D.kicad_mod b/common.pretty/Samtec_SMH-106-02-G-D.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TDA01H0SB1.kicad_mod b/common.pretty/TDA01H0SB1.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TDA02H0SB1.kicad_mod b/common.pretty/TDA02H0SB1.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TDA04H0SB1.kicad_mod b/common.pretty/TDA04H0SB1.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TDA06H0SB1.kicad_mod b/common.pretty/TDA06H0SB1.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TDA08H0SB1.kicad_mod b/common.pretty/TDA08H0SB1.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TDA10H0SB1.kicad_mod b/common.pretty/TDA10H0SB1.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TE_1-2301994-5.kicad_mod b/common.pretty/TE_1-2301994-5.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TE_2337857-1.kicad_mod b/common.pretty/TE_2337857-1.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TE_6116075-1.kicad_mod b/common.pretty/TE_6116075-1.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TIE_10X10.kicad_mod b/common.pretty/TIE_10X10.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TIE_20X20.kicad_mod b/common.pretty/TIE_20X20.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TIE_5X5.kicad_mod b/common.pretty/TIE_5X5.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TP-035.kicad_mod b/common.pretty/TP-035.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/TRANSITION_GENERIC.kicad_mod b/common.pretty/TRANSITION_GENERIC.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/Vicor_PI31xx-0x-HVIZ.kicad_mod b/common.pretty/Vicor_PI31xx-0x-HVIZ.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/XT60PW-F.kicad_mod b/common.pretty/XT60PW-F.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/XT60PW-M.kicad_mod b/common.pretty/XT60PW-M.kicad_mod old mode 100644 new mode 100755 diff --git a/common.pretty/XT60_Male.kicad_mod b/common.pretty/XT60_Male.kicad_mod old mode 100644 new mode 100755 diff --git a/scripting/plugins/BomGeneration/.gitignore b/scripting/plugins/BomGeneration/.gitignore old mode 100644 new mode 100755 diff --git a/scripting/plugins/BomGeneration/.vscode/settings.json b/scripting/plugins/BomGeneration/.vscode/settings.json old mode 100644 new mode 100755 diff --git a/scripting/plugins/BomGeneration/BomGeneration.py b/scripting/plugins/BomGeneration/BomGeneration.py old mode 100644 new mode 100755 diff --git a/scripting/plugins/BomGeneration/Pipfile b/scripting/plugins/BomGeneration/Pipfile old mode 100644 new mode 100755 index 6ce7190..6ce3196 --- a/scripting/plugins/BomGeneration/Pipfile +++ b/scripting/plugins/BomGeneration/Pipfile @@ -4,9 +4,9 @@ url = "https://pypi.org/simple" verify_ssl = true [dev-packages] -ipykernel = "*" black = "*" ipython = "*" +jupyter = "*" flake8 = "*" [packages] diff --git a/scripting/plugins/BomGeneration/Pipfile.lock b/scripting/plugins/BomGeneration/Pipfile.lock old mode 100644 new mode 100755 index d8af987..240a565 --- a/scripting/plugins/BomGeneration/Pipfile.lock +++ b/scripting/plugins/BomGeneration/Pipfile.lock @@ -1,7 +1,7 @@ { "_meta": { "hash": { - "sha256": "39582fc55c61462e40925de792f972373f2ca2988710293e5747ad8c059270cc" + "sha256": "b8965ebe41f7851843c81504793354eadac4050605c100670930684f9ea59155" }, "pipfile-spec": 6, "requires": { @@ -18,66 +18,72 @@ "default": { "numpy": { "hashes": [ - "sha256:09858463db6dd9f78b2a1a05c93f3b33d4f65975771e90d2cf7aadb7c2f66edf", - "sha256:209666ce9d4a817e8a4597cd475b71b4878a85fa4b8db41d79fdb4fdee01dde2", - "sha256:298156f4d3d46815eaf0fcf0a03f9625fc7631692bd1ad851517ab93c3168fc6", - "sha256:30fc68307c0155d2a75ad19844224be0f2c6f06572d958db4e2053f816b859ad", - "sha256:423216d8afc5923b15df86037c6053bf030d15cc9e3224206ef868c2d63dd6dc", - "sha256:426a00b68b0d21f2deb2ace3c6d677e611ad5a612d2c76494e24a562a930c254", - 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a/scripting/plugins/BomGeneration/optimize.py b/scripting/plugins/BomGeneration/optimize.py new file mode 100755 index 0000000..1a0c8ca --- /dev/null +++ b/scripting/plugins/BomGeneration/optimize.py @@ -0,0 +1,73 @@ +import pandas as pd +import numpy as np + +score_method = "qty" +columns = [ + "mpn", + "value", + "voltage_min", + "voltage_max", + "tolerance-", + "tolerance+", +] +parts = { + "C1": (None, 100e-9, 10, np.inf, None, None), + "C1a": (None, 100e-9, 10, 10, None, None), + "C2": (None, 100e-9, 16, np.inf, 0.20, 0.30), + "C2a": (None, 100e-9, 16, np.inf, None, None), + "C2b": (None, 100e-9, 12, np.inf, None, None), + "C3": (None, 100e-9, 0, np.inf, None, None), + "C4": (None, 10e-9, 10, np.inf, None, None), + "C5": (None, 10e-9, 12, np.inf, None, None), +} + +nominal = pd.DataFrame( + [v for _, v in parts.items()], + index=parts.keys(), + columns=columns, +) +actual = nominal.copy(deep=True) +remaining = nominal.copy(deep=True) + +# add temporary columns +remaining.insert(1, "matches", None, True) +remaining.insert(2, "score", -np.inf, True) +remaining.insert(3, "match_mpn", None, True) + +# determine matches +for idx, row in remaining.iterrows(): + matches = [] + for ii, rr in remaining.iterrows(): + if (ii == idx) or ( + (rr["value"] == row["value"]) + and (rr["voltage_min"] <= row["voltage_min"]) + and (rr["voltage_max"] >= row["voltage_max"]) + ): + matches.append(ii) + remaining["matches"][idx] = matches + +n = 0 +while len(remaining.index) > 0: + for idx, row in remaining.iterrows(): + if score_method == "qty": + # score by qty + remaining["score"][idx] = len(remaining["matches"][idx]) + else: + # score by price reduction + pass + + best_idx = remaining["score"].idxmax() + best_score = remaining["score"].max() + + print(f"Step {n}: {best_idx} matched {len(remaining['matches'][best_idx]):d} parts (score: {best_score})") + + for cmp in remaining["matches"][best_idx]: + if cmp in remaining.index: + actual.loc[cmp] = nominal.loc[best_idx] + + # remove matched parts + remaining.drop(remaining["matches"][best_idx], inplace=True) + for idx in remaining.index: + remaining["matches"].loc[idx] = set(remaining["matches"][idx]).intersection(remaining.index) + + n += 1 diff --git a/scripting/plugins/OutputGeneration/FabOutputs.py b/scripting/plugins/OutputGeneration/FabOutputs.py old mode 100644 new mode 100755 diff --git a/scripting/plugins/OutputGeneration/__init__.py b/scripting/plugins/OutputGeneration/__init__.py old mode 100644 new mode 100755 diff --git a/scripting/plugins/OutputGeneration/__pycache__/AsyOutputs.cpython-36.pyc b/scripting/plugins/OutputGeneration/__pycache__/AsyOutputs.cpython-36.pyc old mode 100644 new mode 100755 diff --git a/scripting/plugins/OutputGeneration/__pycache__/AsyOutputs.cpython-38.pyc b/scripting/plugins/OutputGeneration/__pycache__/AsyOutputs.cpython-38.pyc old mode 100644 new mode 100755 diff --git a/scripting/plugins/OutputGeneration/__pycache__/FabOutputs.cpython-36.pyc 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b/scripting/plugins/OutputGeneration/__pycache__/__init__.cpython-38.pyc differ diff --git a/scripting/plugins/OutputGeneration/icon.jpeg b/scripting/plugins/OutputGeneration/icon.jpeg old mode 100644 new mode 100755 diff --git a/scripting/plugins/OutputGeneration/icon.png b/scripting/plugins/OutputGeneration/icon.png old mode 100644 new mode 100755 diff --git a/spice.kicad_sym b/spice.kicad_sym old mode 100644 new mode 100755 diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/Application Note Introduction to Infineons Simulation Models for Power MOSFETs.pdf b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/Application Note Introduction to Infineons Simulation Models for Power MOSFETs.pdf new file mode 100755 index 0000000..fa13ded Binary files /dev/null and b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/Application Note Introduction to Infineons Simulation Models for Power MOSFETs.pdf differ diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/Intusoft/OptiMOS2_100_Intusoft.lib b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/Intusoft/OptiMOS2_100_Intusoft.lib new file mode 100755 index 0000000..b4e6a42 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/Intusoft/OptiMOS2_100_Intusoft.lib @@ -0,0 +1,1620 @@ +***************************************************************** +* INFINEON Power Transistors * +* Simplified Intusoft SPICE Model Library for OptiMOS n-Channel * +* Transistors * +* Version 101208 * +* * +***************************************************************** +* * +* The Simulation Model is subject to change without notice. In * +* addition, models can be a useful tool in evaluating device * +* performance, they cannot reflect the accurate device * +* performance under all conditions, nor are they intended to * +* replace bread boarding for final verification. Infineon * +* therefore does not assume any warranty or liability * +* whatsoever arising from their use. Infineon does not assume * +* any warranty or liability for the values and functions of the * +* Simulation Model. * +* The methods and results of the Simulation Model are to the * +* best of our knowledge * +* correct. However, the user is fully responsible to verify and * +* validate these results under the operating conditions and in * +* the environment of its application. Infineon will not bear * +* the responsibility arising out of or in connection with any * +* malfunction of the Simulation Models. * +* Models provided by Infineon are not warranted by Infineon as * +* completely and comprehensively representing all the * +* specifications and operating characteristics of the * +* semiconductor products to which these models relate. The * +* models describe the characteristics of typical devices. In * +* all cases, the current data sheet information for a given * +* device is the conclusive design guideline and the only actual * +* performance specification. * +* * +* This library contains models of the following INFINEON * +* OptiMOS2 transistors: * +* * +* 100V NL * +* IPB04CN10N IPD12CN10N * +* IPB05CN10N IPD16CN10N * +* IPB06CN10N IPD25CN10N * +* IPB08CN10N IPD33CN10N * +* IPB12CN10N IPD49CN10N * +* IPB16CN10N IPD78CN10N * +* IPP04CN10N IPD64CN10N * +* IPP05CN10N BSC079N10NS * +* IPP06CN10N BSC118N10NS * +* IPP08CN10N BSC196N10NS * +* IPP12CN10N BSC100N10NSF * +* IPP16CN10N BSC152N10NSF * +* IPP26CN10N BSC252N10NSF * +* IPP35CN10N BSC750N10ND * +* IPP50CN10N * +* IPP80CN10N * +* * +* 100 V LL * +* IPP05CN10L IPS12CN10L BSC159N10LSF * +* IPP06CN10L BSC082N10LS BSC265N10LSF * +* IPP08CN10L BSC123N10LS * +* IPP12CN10L BSC205N10LS * +* IPP16CN10L BSC105N10LSF * +***************************************************************** + + +*SRC=IPB04CN10N_L0;IPB04CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 4.1mOhm +*SYM=POWMOSN +.SUBCKT IPB04CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 623u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 372.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 2.3m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=7.7n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=51.5p N=1.11 RS=0.74u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 0.53m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.39n +.MODEL DGD D(M=2.4 CJO=3.39n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 10.36n + +.ENDS IPB04CN10N_L0 +****** + +*SRC=IPP04CN10N_L0;IPP04CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 4.4mOhm +*SYM=POWMOSN +.SUBCKT IPP04CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 623u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 372.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 2.6m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=7.7n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=51.5p N=1.11 RS=0.74u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 0.53m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.39n +.MODEL DGD D(M=2.4 CJO=3.39n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 10.36n + +.ENDS IPP04CN10N_L0 +****** + +*SRC=IPB05CN10N_L0;IPB05CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 5.1mOhm +*SYM=POWMOSN +.SUBCKT IPB05CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 805u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 322.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 2.65m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=6.67n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=44.6p N=1.11 RS=0.85u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 0.61m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.94n +.MODEL DGD D(M=2.4 CJO=2.94n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.98n + +.ENDS IPB05CN10N_L0 +****** + +*SRC=IPP05CN10N_L0;IPP05CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 5.4mOhm +*SYM=POWMOSN +.SUBCKT IPP05CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 805u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 322.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 2.95m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=6.67n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=44.6p N=1.11 RS=0.85u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 0.61m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.94n +.MODEL DGD D(M=2.4 CJO=2.94n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.98n + +.ENDS IPP05CN10N_L0 +****** + +*SRC=IPB06CN10N_L0;IPB06CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 6.2mOhm +*SYM=POWMOSN +.SUBCKT IPB06CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 745u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 246.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 3.46m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=5.08n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=34p N=1.11 RS=1.12u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 0.8m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.24n +.MODEL DGD D(M=2.4 CJO=2.24n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.86n + +.ENDS IPB06CN10N_L0 +****** + +*SRC=IPP06CN10N_L0;IPP06CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 6.5mOhm +*SYM=POWMOSN +.SUBCKT IPP06CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 745u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 246.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 3.76m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=5.08n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=34p N=1.11 RS=1.12u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 0.8m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.24n +.MODEL DGD D(M=2.4 CJO=2.24n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.86n + +.ENDS IPP06CN10N_L0 +****** + +*SRC=IPB08CN10N_L0;IPB08CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 95A 8.2mOhm +*SYM=POWMOSN +.SUBCKT IPB08CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 705u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 177.4 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 4.78m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.66n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=24.5p N=1.11 RS=1.55u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.12m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.62n +.MODEL DGD D(M=2.4 CJO=1.62n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.96n + +.ENDS IPB08CN10N_L0 +****** + +*SRC=IPP08CN10N_L0;IPP08CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 95A 8.5mOhm +*SYM=POWMOSN +.SUBCKT IPP08CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 705u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 177.4 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 5.08m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.66n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=24.5p N=1.11 RS=1.55u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.12m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.62n +.MODEL DGD D(M=2.4 CJO=1.62n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.96n + +.ENDS IPP08CN10N_L0 +****** + +*SRC=IPB12CN10N_L0;IPB12CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 67A 12.6mOhm +*SYM=POWMOSN +.SUBCKT IPB12CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 4n +Rs s1 s2 958u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 114.3 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 7.39m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.11 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.73m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.22n + +.ENDS IPB12CN10N_L0 +****** + +*SRC=IPP12CN10N_L0;IPP12CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 67A 12.9mOhm +*SYM=POWMOSN +.SUBCKT IPP12CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 958u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 114.3 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 7.69m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.11 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.73m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.22n + +.ENDS IPP12CN10N_L0 +****** + +*SRC=IPD12CN10N_L0;IPD12CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 67A 12.4mOhm +*SYM=POWMOSN +.SUBCKT IPD12CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 791u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 114.3 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 7.39m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.11 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.73m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.22n + +.ENDS IPD12CN10N_L0 +****** + +*SRC=IPB16CN10N_L0;IPB16CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 53A 16.2mOhm +*SYM=POWMOSN +.SUBCKT IPB16CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 4n +Rs s1 s2 908u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 84.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 9.95m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.11 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 2.34m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.4n + +.ENDS IPB16CN10N_L0 +****** + +*SRC=IPP16CN10N_L0;IPP16CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 53A 16.5mOhm +*SYM=POWMOSN +.SUBCKT IPP16CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 908u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 84.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 10.25m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.11 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 2.34m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.4n + +.ENDS IPP16CN10N_L0 +****** + +*SRC=IPD16CN10N_L0;IPD16CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 53A 16mOhm +*SYM=POWMOSN +.SUBCKT IPD16CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 741u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 84.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 9.95m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.11 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 2.34m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.4n + +.ENDS IPD16CN10N_L0 +****** + +*SRC=IPP26CN10N_L0;IPP26CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 35A 26mOhm +*SYM=POWMOSN +.SUBCKT IPP26CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 1.72m + +Rg g1 g2 1.1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 53.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 15.99m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.11n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=7.4p N=1.11 RS=5.13u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 3.69m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=2.4 CJO=0.49n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS IPP26CN10N_L0 +****** + +*SRC=IPD25CN10N_L0;IPD25CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 35A 25mOhm +*SYM=POWMOSN +.SUBCKT IPD25CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 1.41m + +Rg g1 g2 1.1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 53.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 15.69m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.11n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=7.4p N=1.11 RS=5.13u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 3.69m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=2.4 CJO=0.49n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS IPD25CN10N_L0 +****** + +*SRC=IPP35CN10N_L0;IPP35CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 27A 35mOhm +*SYM=POWMOSN +.SUBCKT IPP35CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 1.53m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 40.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 21.24m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.83n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=5.5p N=1.11 RS=6.85u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 4.93m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.37n +.MODEL DGD D(M=2.4 CJO=0.37n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.17n + +.ENDS IPP35CN10N_L0 +****** + +*SRC=IPD33CN10N_L0;IPD33CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 27A 33mOhm +*SYM=POWMOSN +.SUBCKT IPD33CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 1.22m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 40.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 20.94m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.83n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=5.5p N=1.11 RS=6.85u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 4.93m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.37n +.MODEL DGD D(M=2.4 CJO=0.37n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.17n + +.ENDS IPD33CN10N_L0 +****** + +*SRC=IPP50CN10N_L0;IPP50CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 20A 50mOhm +*SYM=POWMOSN +.SUBCKT IPP50CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 2.62m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 27.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 31.16m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.56n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.11 RS=10.1u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 7.27m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.25n +.MODEL DGD D(M=2.4 CJO=0.25n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.81n + +.ENDS IPP50CN10N_L0 +****** + +*SRC=IPD49CN10N_L0;IPD49CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 20A 49mOhm +*SYM=POWMOSN +.SUBCKT IPD49CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 2.01m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 27.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 30.86m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.56n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.11 RS=10.1u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 7.27m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.25n +.MODEL DGD D(M=2.4 CJO=0.25n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.81n + +.ENDS IPD49CN10N_L0 +****** + +*SRC=IPP80CN10N_L0;IPP80CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 13A 80mOhm +*SYM=POWMOSN +.SUBCKT IPP80CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 4.3m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 49.62m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.35n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=2.4p N=1.11 RS=16.16u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 11.63m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.16n +.MODEL DGD D(M=2.4 CJO=0.16n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.53n + +.ENDS IPP80CN10N_L0 +****** + +*SRC=IPD78CN10N_L0;IPD78CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 13A 78mOhm +*SYM=POWMOSN +.SUBCKT IPD78CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 3.14m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 49.32m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.35n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=2.4p N=1.11 RS=16.16u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 11.63m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.16n +.MODEL DGD D(M=2.4 CJO=0.16n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.53n + +.ENDS IPD78CN10N_L0 +****** + +*SRC=IPD64CN10N_L0;IPD64CN10N_L0;MOSFETs N;Infineon;OptiMOS2 100V 18A 64mOhm +*SYM=POWMOSN +.SUBCKT IPD64CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 3.14m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 16.7 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 30.05m +.model Rdmod R TC1=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.4n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.11 RS=10.1u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 4.04m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.127n +.MODEL DGD D(M=2.1 CJO=0.127n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.43n + +.ENDS IPD64CN10N_L0 +****** + +*SRC=IPP05CN10L_L0;IPP05CN10L_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 5.4mOhm +*SYM=POWMOSN +.SUBCKT IPP05CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 805u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 535.1 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 3.09m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=6.67n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=44.6p N=1.07 RS=0.85u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 0.7m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.94n +.MODEL DGD D(M=2.4 CJO=2.94n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.56n + +.ENDS IPP05CN10L_L0 +****** + +*SRC=IPP06CN10L_L0;IPP06CN10L_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 6.5mOhm +*SYM=POWMOSN +.SUBCKT IPP06CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 745u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 408.1 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 3.95m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=5.08n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=34p N=1.07 RS=1.12u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 0.92m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.24n +.MODEL DGD D(M=2.4 CJO=2.24n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.83n + +.ENDS IPP06CN10L_L0 +****** + +*SRC=IPP08CN10L_L0;IPP08CN10L_L0;MOSFETs N;Infineon;OptiMOS2 100V 95A 8.5mOhm +*SYM=POWMOSN +.SUBCKT IPP08CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 705u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 294.1 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 5.34m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.66n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=24.5p N=1.07 RS=1.55u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.28m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.62n +.MODEL DGD D(M=2.4 CJO=1.62n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.38n + +.ENDS IPP08CN10L_L0 +****** + +*SRC=IPP12CN10L_L0;IPP12CN10L_L0;MOSFETs N;Infineon;OptiMOS2 100V 67A 12.9mOhm +*SYM=POWMOSN +.SUBCKT IPP12CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 958u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 189.5 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 8.1m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.07 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.99m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.13n + +.ENDS IPP12CN10L_L0 +****** + +*SRC=IPS12CN10L_L0;IPS12CN10L_L0;MOSFETs N;Infineon;OptiMOS2 100V 67A 12.4mOhm +*SYM=POWMOSN +.SUBCKT IPS12CN10L_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 2n +Ls source s1 2n +Rs s1 s2 791u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 189.5 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 8m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.07 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.99m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.13n + +.ENDS IPS12CN10L_L0 +****** + +*SRC=IPP16CN10L_L0;IPP16CN10L_L0;MOSFETs N;Infineon;OptiMOS2 100V 53A 16mOhm +*SYM=POWMOSN +.SUBCKT IPP16CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 908u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 140.4 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 10.8m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.07 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 2.68m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.08n + +.ENDS IPP16CN10L_L0 +****** + + +*SRC=BSC079N10NS_L0;BSC079N10NS_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 7.9mOhm +*SYM=POWMOSN +.SUBCKT BSC079N10NS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 154.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 5.45m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.18n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.11 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.28m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.405n +.MODEL DGD D(M=2.4 CJO=1.405n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.32n + +.ENDS BSC079N10NS_L0 +****** + +*SRC=BSC118N10NS_L0;BSC118N10NS_L0;MOSFETs N;Infineon;OptiMOS2 100V 71A 11.8mOhm +*SYM=POWMOSN +.SUBCKT BSC118N10NS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 99.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 8.47m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.05n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.11 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 2m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.905n +.MODEL DGD D(M=2.4 CJO=0.905n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.8n + +.ENDS BSC118N10NS_L0 +****** + +*SRC=BSC196N10NS_L0;BSC196N10NS_L0;MOSFETs N;Infineon;OptiMOS2 100V 45A 19.6mOhm +*SYM=POWMOSN +.SUBCKT BSC196N10NS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 58.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 14.3m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.21n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.11 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 3.37m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.538n +.MODEL DGD D(M=2.4 CJO=0.538n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.68n + +.ENDS BSC196N10NS_L0 +****** + + +*SRC=BSC100N10NSF_L0;BSC100N10NSF_L0;MOSFETs N;Infineon;OptiMOS2 100V 89A 10mOhm +*SYM=POWMOSN +.SUBCKT BSC100N10NSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 94.7 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 5.31m +.model Rdmod R TC1=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.24n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.11 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 0.71m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.699n +.MODEL DGD D(M=2.1 CJO=0.699n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.18n + +.ENDS BSC100N10NSF_L0 +****** + +*SRC=BSC152N10NSF_L0;BSC152N10NSF_L0;MOSFETs N;Infineon;OptiMOS2 100V 61A 15.2mOhm +*SYM=POWMOSN +.SUBCKT BSC152N10NSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 60.9 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 8.25m +.model Rdmod R TC1=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.44n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.11 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.11m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.451n +.MODEL DGD D(M=2.1 CJO=0.451n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.42n + +.ENDS BSC152N10NSF_L0 +****** + +*SRC=BSC252N10NSF_L0;BSC252N10NSF_L0;MOSFETs N;Infineon;OptiMOS2 100V 39A 25.2mOhm +*SYM=POWMOSN +.SUBCKT BSC252N10NSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 36.1 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 13.92m +.model Rdmod R TC1=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.85n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.11 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.87m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.269n +.MODEL DGD D(M=2.1 CJO=0.269n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.87n + +.ENDS BSC252N10NSF_L0 +****** + +*SRC=BSC750N10ND_L0;BSC750N10ND_L0;MOSFETs N;Infineon;OptiMOS2 100V 13A 75mOhm +*SYM=POWMOSN +.SUBCKT BSC750N10ND_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 5.06m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 49.28m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.35n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=2.4p N=1.11 RS=16.16u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 11.63m +.model Rdiod R TC1=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.16n +.MODEL DGD D(M=2.4 CJO=0.16n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.53n + +.ENDS BSC750N10ND_L0 +****** + + +*SRC=BSC082N10LS_L0;BSC082N10LS_L0;MOSFETs N;Infineon;OptiMOS2 100V 100A 8.2mOhm +*SYM=POWMOSN +.SUBCKT BSC082N10LS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 255.6 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 5.75m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.18n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.07 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.47m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.405n +.MODEL DGD D(M=2.4 CJO=1.405n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 5.55n + +.ENDS BSC082N10LS_L0 +****** + +*SRC=BSC123N10LS_L0;BSC123N10LS_L0;MOSFETs N;Infineon;OptiMOS2 100V 72A 12.3mOhm +*SYM=POWMOSN +.SUBCKT BSC123N10LS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 164.3 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 8.95m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.05n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.07 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 2.29m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.905n +.MODEL DGD D(M=2.4 CJO=0.905n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.59n + +.ENDS BSC123N10LS_L0 +****** + +*SRC=BSC205N10LS_L0;BSC205N10LS_L0;MOSFETs N;Infineon;OptiMOS2 100V 45A 20.5mOhm +*SYM=POWMOSN +.SUBCKT BSC205N10LS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 97.3 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 15.1m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.21n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.07 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 3.87m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.538n +.MODEL DGD D(M=2.4 CJO=0.538n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.15n + +.ENDS BSC205N10LS_L0 +****** +****** + +*SRC=BSC105N10LSF_L0;BSC105N10LSF_L0;MOSFETs N;Infineon;OptiMOS2 100V 50A 10.5mOhm +*SYM=POWMOSN +.SUBCKT BSC105N10LSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 125.6 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 5.54m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.25n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.07 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 1.47m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.699n +.MODEL DGD D(M=2.4 CJO=0.699n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.85n + +.ENDS BSC105N10LSF_L0 +****** + +*SRC=BSC159N10LSF_L0;BSC159N10LSF_L0;MOSFETs N;Infineon;OptiMOS2 100V 50A 15.9mOhm +*SYM=POWMOSN +.SUBCKT BSC159N10LSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 1.0 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 80.7 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 8.61m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.09n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.07 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 2.29m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.451n +.MODEL DGD D(M=2.4 CJO=0.451n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.87n + +.ENDS BSC159N10LSF_L0 +****** + +*SRC=BSC265N10LSF_L0;BSC265N10LSF_L0;MOSFETs N;Infineon;OptiMOS2 100V 50A 26.5mOhm +*SYM=POWMOSN +.SUBCKT BSC265N10LSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 47.8 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 Rdmod 14.53m +.model Rdmod R TC1=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.24n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.07 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 Rdiod 3.87m +.model Rdiod R TC1=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.269n +.MODEL DGD D(M=2.4 CJO=0.269n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.15n + +.ENDS BSC265N10LSF_L0 +****** diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2 ReadMe.pdf b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2 ReadMe.pdf new file mode 100755 index 0000000..46a47c7 Binary files /dev/null and b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2 ReadMe.pdf differ diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V.lib b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V.lib new file mode 100755 index 0000000..80fa374 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V.lib @@ -0,0 +1,4546 @@ +***************************************************************** +* INFINEON Power Transistors * +* Level1/3 PSPICE Library for OptiMOS2 n-Channel Transistors * +* * +* This file also contains simplified models that are compatible * +* to standard Spice. * +* * +* Version 10122008 * +* * +***************************************************************** +* * +* The Simulation Model is subject to change without notice. In * +* addition, models can be a useful tool in evaluating device * +* performance, they cannot reflect the accurate device * +* performance under all conditions, nor are they intended to * +* replace bread boarding for final verification. Infineon * +* therefore does not assume any warranty or liability * +* whatsoever arising from their use. Infineon does not assume * +* any warranty or liability for the values and functions of the * +* Simulation Model. * +* The methods and results of the Simulation Model are to the * +* best of our knowledge * +* correct. However, the user is fully responsible to verify and * +* validate these results under the operating conditions and in * +* the environment of its application. Infineon will not bear * +* the responsibility arising out of or in connection with any * +* malfunction of the Simulation Models. * +* Models provided by Infineon are not warranted by Infineon as * +* completely and comprehensively representing all the * +* specifications and operating characteristics of the * +* semiconductor products to which these models relate. The * +* models describe the characteristics of typical devices. In * +* all cases, the current data sheet information for a given * +* device is the conclusive design guideline and the only actual * +* performance specification. * +* * +* This library contains models of the following INFINEON * +* OptiMOS2 transistors: * +* * +* 100V NL * +* IPB04CN10N IPD12CN10N * +* IPB05CN10N IPD16CN10N * +* IPB06CN10N IPD25CN10N * +* IPB08CN10N IPD33CN10N * +* IPB12CN10N IPD49CN10N * +* IPB16CN10N IPD78CN10N * +* IPP04CN10N IPD64CN10N * +* IPP05CN10N BSC079N10NS * +* IPP06CN10N BSC118N10NS * +* IPP08CN10N BSC196N10NS * +* IPP12CN10N BSC100N10NSF * +* IPP16CN10N BSC152N10NSF * +* IPP26CN10N BSC252N10NSF * +* IPP35CN10N BSC750N10ND * +* IPP50CN10N * +* IPP80CN10N * +* * +* 100 V LL * +* IPP05CN10L IPS12CN10L * +* IPP06CN10L BSC082N10LS BSC159N10LSF * +* IPP08CN10L BSC123N10LS BSC265N10LSF * +* IPP12CN10L BSC205N10LS * +* IPP16CN10L BSC105N10LSF * +***************************************************************** +* thermal nodes of level 3 models: * +* * +* .SUBCKT IPB05CN10N drain gate source Tj Tcase * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Tcase : node where the boundary contition - external heat * +* sinks etc - have to be connected (ideal heat sink * +* can be modeled by using a voltage source stating the * +* ambient temperature in °C between Tcase and ground. * +* * +***************************************************************** + + +.SUBCKT S3_100_a_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.065 Fn=0.5 kbq=85.8u +.PARAM c=1.55 muc=0.0 Vth0=4.073 auth=5.5m al=0.001 +.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132 + +.PARAM b0=22.55 p0=6.62 p1=-20.6m p2=39.2u + +.PARAM Rd=60m nmu=2.75 Tref=298 T0=273 lnIsj=-25.7 +.PARAM ndi=1.17 Rdi=12m nmu2=0.3 ta=30n td=100n +.PARAM Rf=0.34 nmu3=1.8 rpa=150u + +.PARAM f3=380p f3a=60p +.PARAM ps1=45p ps2=-62.5m ps3=80p ps4=-2 ps5=1.06p ps6=4p +.PARAM qs1=26p qs2=50p qs3=-2 qs4=175p qs5=-0.0357 + +.PARAM Vmin=3.073 Vmax=5.073 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT S3_100_b_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.065 Fn=0.5 kbq=85.8u +.PARAM c=1.312 muc=5m Vth0=4.073 auth=4.856m al=0.5 +.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132 + +.PARAM b0=10.91 p0=4.562 p1=-12.6m p2=32u + +.PARAM Rd=63m nmu=2.64 Tref=298 T0=273 lnIsj=-25.3 +.PARAM ndi=1.2 Rdi=5.7m nmu2=0.3 ta=30n td=100n +.PARAM Rf=0.28 nmu3=1.8 rpa=0u + +.PARAM f3=185p f3a=55p +.PARAM ps1=25p ps2=-62.5m ps3=40p ps4=-2 ps5=0.6p ps6=3p +.PARAM qs1=30p qs2=50p qs3=-2 qs4=200p qs5=-0.0357 + +.PARAM Vmin=3.073 Vmax=5.073 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT S3_100_c_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.085 Fn=0.5 kbq=85.8u +.PARAM c=1.08 muc=0.0 Vth0=2.69 auth=3.3m al=0.5 +.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132 + +.PARAM b0=35 p0=5.022 p1=-14.6m p2=25u + +.PARAM Rd=66m nmu=2.75 Tref=298 T0=273 lnIsj=-25.7 +.PARAM ndi=1.14 Rdi=12m nmu2=0.7 ta=30n td=100n +.PARAM Rf=0.34 nmu3=1.65 rpa=150u + +.PARAM f3=490p f3a=110p +.PARAM ps1=45p ps2=-62.5m ps3=80p ps4=-2 ps5=1.06p ps6=4p +.PARAM qs1=26p qs2=50p qs3=-2 qs4=180p qs5=-0.0333 + +.PARAM Vmin=2.04 Vmax=2.84 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT S3_100_d_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.085 Fn=0.5 kbq=85.8u +.PARAM c=1.4 muc=0.0 Vth0=2.69 auth=3.3m al=0.5 +.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132 + +.PARAM b0=16 p0=6.445 p1=-22.5m p2=39u + +.PARAM Rd=66m nmu=2.75 Tref=298 T0=273 lnIsj=-25.7 +.PARAM ndi=1.14 Rdi=12m nmu2=0.7 ta=30n td=100n +.PARAM Rf=0.34 nmu3=1.65 rpa=300u + +.PARAM f3=245p f3a=100p +.PARAM ps1=25p ps2=-77m ps3=43p ps4=-2 ps5=0.4p ps6=4p +.PARAM qs1=30p qs2=50p qs3=-2 qs4=180p qs5=-0.0333 + +.PARAM Vmin=2.04 Vmax=2.84 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT IPB04CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=623u Rg=1.9 Rd=50u Rm=156u +.PARAM Inn=100 Unn=10 Rmax=4.1m gmin=87 +.PARAM RRf=181m Rrbond=10m Rtb=5 g2=572m +.PARAM act=27.1 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.61m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.21m+limit(Zthtype,0,1)*449.24u} +Rth2 t1 t2 {13.31m+limit(Zthtype,0,1)*4.92m} +Rth3 t2 t3 {75.74m+limit(Zthtype,0,1)*25.08m} +Rth4 t3 t4 {65.33m+limit(Zthtype,0,1)*38.48m} +Rth5 t4 Tcase {173.36m+limit(Zthtype,0,1)*102.12m} +Cth1 Tj 0 377.292u +Cth2 t1 0 856.511u +Cth3 t2 0 9.103m +Cth4 t3 0 4.607m +Cth5 t4 0 136.409m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPB05CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=50u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.1m gmin=81 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=23.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.4m+limit(Zthtype,0,1)*515.4u} +Rth2 t1 t2 {15.33m+limit(Zthtype,0,1)*5.68m} +Rth3 t2 t3 {87.39m+limit(Zthtype,0,1)*28.98m} +Rth4 t3 t4 {75.43m+limit(Zthtype,0,1)*29.02m} +Rth5 t4 Tcase {185.07m+limit(Zthtype,0,1)*71.19m} +Cth1 Tj 0 326.755u +Cth2 t1 0 743.512u +Cth3 t2 0 7.891m +Cth4 t3 0 3.99m +Cth5 t4 0 121.993m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPB06CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=50u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.2m gmin=77 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=17.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.83m+limit(Zthtype,0,1)*681.8u} +Rth2 t1 t2 {20m+limit(Zthtype,0,1)*7.41m} +Rth3 t2 t3 {113.28m+limit(Zthtype,0,1)*38.04m} +Rth4 t3 t4 {98.91m+limit(Zthtype,0,1)*67.42m} +Rth5 t4 Tcase {209.58m+limit(Zthtype,0,1)*142.85m} +Cth1 Tj 0 249.208u +Cth2 t1 0 569.82u +Cth3 t2 0 6.105m +Cth4 t3 0 3.043m +Cth5 t4 0 100.531m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPB08CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=50u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.2m gmin=57 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=12.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.54m+limit(Zthtype,0,1)*945.06u} +Rth2 t1 t2 {27.57m+limit(Zthtype,0,1)*10.21m} +Rth3 t2 t3 {154.04m+limit(Zthtype,0,1)*52.84m} +Rth4 t3 t4 {137.24m+limit(Zthtype,0,1)*97.36m} +Rth5 t4 Tcase {244.09m+limit(Zthtype,0,1)*173.16m} +Cth1 Tj 0 179.597u +Cth2 t1 0 413.456u +Cth3 t2 0 4.512m +Cth4 t3 0 2.193m +Cth5 t4 0 81.53m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPB12CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=1n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=50u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.6m gmin=38 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {213.05m+limit(Zthtype,0,1)*127.18m} +Rth5 t4 Tcase {300.49m+limit(Zthtype,0,1)*179.38m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.413m +Cth5 t4 0 63.737m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPB16CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=1n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=50u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16.2m gmin=30 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=6.16 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {5.33m+limit(Zthtype,0,1)*1.97m} +Rth2 t1 t2 {56.59m+limit(Zthtype,0,1)*20.95m} +Rth3 t2 t3 {306.84m+limit(Zthtype,0,1)*111.08m} +Rth4 t3 t4 {287.41m+limit(Zthtype,0,1)*164.5m} +Rth5 t4 Tcase {346.82m+limit(Zthtype,0,1)*198.51m} +Cth1 Tj 0 85.761u +Cth2 t1 0 201.422u +Cth3 t2 0 2.296m +Cth4 t3 0 1.047m +Cth5 t4 0 55.041m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP04CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=623u Rg=1.9 Rd=350u Rm=156u +.PARAM Inn=100 Unn=10 Rmax=4.4m gmin=87 +.PARAM RRf=181m Rrbond=10m Rtb=5 g2=572m +.PARAM act=27.1 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.61m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.21m+limit(Zthtype,0,1)*449.24u} +Rth2 t1 t2 {13.31m+limit(Zthtype,0,1)*4.92m} +Rth3 t2 t3 {75.74m+limit(Zthtype,0,1)*25.08m} +Rth4 t3 t4 {65.33m+limit(Zthtype,0,1)*38.48m} +Rth5 t4 Tcase {173.36m+limit(Zthtype,0,1)*102.12m} +Cth1 Tj 0 377.292u +Cth2 t1 0 856.511u +Cth3 t2 0 9.103m +Cth4 t3 0 4.607m +Cth5 t4 0 136.409m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP05CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=350u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.4m gmin=81 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=23.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.4m+limit(Zthtype,0,1)*515.4u} +Rth2 t1 t2 {15.33m+limit(Zthtype,0,1)*5.68m} +Rth3 t2 t3 {87.39m+limit(Zthtype,0,1)*28.98m} +Rth4 t3 t4 {75.43m+limit(Zthtype,0,1)*29.02m} +Rth5 t4 Tcase {185.07m+limit(Zthtype,0,1)*71.19m} +Cth1 Tj 0 326.755u +Cth2 t1 0 743.512u +Cth3 t2 0 7.891m +Cth4 t3 0 3.99m +Cth5 t4 0 121.993m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP06CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=350u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.5m gmin=77 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=17.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.83m+limit(Zthtype,0,1)*681.8u} +Rth2 t1 t2 {20m+limit(Zthtype,0,1)*7.41m} +Rth3 t2 t3 {113.28m+limit(Zthtype,0,1)*38.04m} +Rth4 t3 t4 {98.91m+limit(Zthtype,0,1)*67.42m} +Rth5 t4 Tcase {209.58m+limit(Zthtype,0,1)*142.85m} +Cth1 Tj 0 249.208u +Cth2 t1 0 569.82u +Cth3 t2 0 6.105m +Cth4 t3 0 3.043m +Cth5 t4 0 100.531m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP08CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=350u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.5m gmin=57 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=12.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.54m+limit(Zthtype,0,1)*945.06u} +Rth2 t1 t2 {27.57m+limit(Zthtype,0,1)*10.21m} +Rth3 t2 t3 {154.04m+limit(Zthtype,0,1)*52.84m} +Rth4 t3 t4 {137.24m+limit(Zthtype,0,1)*97.36m} +Rth5 t4 Tcase {244.09m+limit(Zthtype,0,1)*173.16m} +Cth1 Tj 0 179.597u +Cth2 t1 0 413.456u +Cth3 t2 0 4.512m +Cth4 t3 0 2.193m +Cth5 t4 0 81.53m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP12CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=350u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.9m gmin=38 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {213.05m+limit(Zthtype,0,1)*127.18m} +Rth5 t4 Tcase {300.49m+limit(Zthtype,0,1)*179.38m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.413m +Cth5 t4 0 63.737m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP16CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=350u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16.5m gmin=30 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=6.16 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {5.33m+limit(Zthtype,0,1)*1.97m} +Rth2 t1 t2 {56.59m+limit(Zthtype,0,1)*20.95m} +Rth3 t2 t3 {306.84m+limit(Zthtype,0,1)*111.08m} +Rth4 t3 t4 {287.41m+limit(Zthtype,0,1)*164.5m} +Rth5 t4 Tcase {346.82m+limit(Zthtype,0,1)*198.51m} +Cth1 Tj 0 85.761u +Cth2 t1 0 201.422u +Cth3 t2 0 2.296m +Cth4 t3 0 1.047m +Cth5 t4 0 55.041m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP26CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=1.72m Rg=1.1 Rd=350u Rm=640u +.PARAM Inn=35 Unn=10 Rmax=26m gmin=19 +.PARAM RRf=473m Rrbond=124m Rtb=17.4 g2=822m +.PARAM act=3.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 2.93m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {8.42m+limit(Zthtype,0,1)*3.11m} +Rth2 t1 t2 {87.93m+limit(Zthtype,0,1)*32.54m} +Rth3 t2 t3 {463.44m+limit(Zthtype,0,1)*175.99m} +Rth4 t3 t4 {457.12m+limit(Zthtype,0,1)*225.29m} +Rth5 t4 Tcase {432.84m+limit(Zthtype,0,1)*213.32m} +Cth1 Tj 0 54.297u +Cth2 t1 0 129.642u +Cth3 t2 0 1.539m +Cth4 t3 0 662.942u +Cth5 t4 0 45.488m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP35CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=1.53m Rg=1 Rd=350u Rm=450u +.PARAM Inn=27 Unn=10 Rmax=35m gmin=15 +.PARAM RRf=473m Rrbond=124m Rtb=17.4 g2=822m +.PARAM act=2.92 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 2.93m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {11.24m+limit(Zthtype,0,1)*4.16m} +Rth2 t1 t2 {115.99m+limit(Zthtype,0,1)*42.92m} +Rth3 t2 t3 {603.94m+limit(Zthtype,0,1)*235.6m} +Rth4 t3 t4 {614.86m+limit(Zthtype,0,1)*260.87m} +Rth5 t4 Tcase {498.79m+limit(Zthtype,0,1)*211.63m} +Cth1 Tj 0 40.653u +Cth2 t1 0 98.282u +Cth3 t2 0 1.19m +Cth4 t3 0 496.356u +Cth5 t4 0 41.277m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP50CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=2.62m Rg=0.9 Rd=350u Rm=650u +.PARAM Inn=20 Unn=10 Rmax=50m gmin=10.5 +.PARAM RRf=494m Rrbond=518m Rtb=35.4 g2=904m +.PARAM act=1.98 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.43m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {16.58m+limit(Zthtype,0,1)*6.13m} +Rth2 t1 t2 {167.72m+limit(Zthtype,0,1)*62.07m} +Rth3 t2 t3 {841.93m+limit(Zthtype,0,1)*348.69m} +Rth4 t3 t4 {920.39m+limit(Zthtype,0,1)*260.77m} +Rth5 t4 Tcase {604.46m+limit(Zthtype,0,1)*171.26m} +Cth1 Tj 0 27.566u +Cth2 t1 0 67.968u +Cth3 t2 0 868.439u +Cth4 t3 0 336.57u +Cth5 t4 0 37.577m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP80CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=4.3m Rg=0.8 Rd=350u Rm=660u +.PARAM Inn=13 Unn=10 Rmax=80m gmin=6.5 +.PARAM RRf=498m Rrbond=2 Rtb=69.4 g2=949m +.PARAM act=1.238 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 731.6u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {26.51m+limit(Zthtype,0,1)*9.81m} +Rth2 t1 t2 {260.54m+limit(Zthtype,0,1)*96.42m} +Rth3 t2 t3 {1.23+limit(Zthtype,0,1)*565.19m} +Rth4 t3 t4 {1.5+limit(Zthtype,0,1)*296.12m} +Rth5 t4 Tcase {764.49m+limit(Zthtype,0,1)*150.92m} +Cth1 Tj 0 17.236u +Cth2 t1 0 43.753u +Cth3 t2 0 609.936u +Cth4 t3 0 210.441u +Cth5 t4 0 36.415m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPD12CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=791u Rg=1.5 Rd=50u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.4m gmin=38 +.PARAM RRf=301m Rrbond=14m Rtb=5.8 g2=623m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.9m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {172m+limit(Zthtype,0,1)*138.86m} +Rth5 t4 Tcase {281.76m+limit(Zthtype,0,1)*227.48m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.464m +Cth5 t4 0 34.87m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPD16CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=741u Rg=1.2 Rd=50u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16m gmin=30 +.PARAM RRf=301m Rrbond=14m Rtb=5.8 g2=623m +.PARAM act=6.16 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.9m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {5.33m+limit(Zthtype,0,1)*1.97m} +Rth2 t1 t2 {56.59m+limit(Zthtype,0,1)*20.95m} +Rth3 t2 t3 {306.84m+limit(Zthtype,0,1)*111.08m} +Rth4 t3 t4 {232.04m+limit(Zthtype,0,1)*180.69m} +Rth5 t4 Tcase {328.61m+limit(Zthtype,0,1)*255.9m} +Cth1 Tj 0 85.761u +Cth2 t1 0 201.422u +Cth3 t2 0 2.296m +Cth4 t3 0 1.086m +Cth5 t4 0 29.486m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPD25CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=1.41m Rg=1.1 Rd=50u Rm=640u +.PARAM Inn=35 Unn=10 Rmax=25m gmin=19 +.PARAM RRf=450m Rrbond=55m Rtb=11.6 g2=767m +.PARAM act=3.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.95m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {8.42m+limit(Zthtype,0,1)*3.11m} +Rth2 t1 t2 {87.93m+limit(Zthtype,0,1)*32.54m} +Rth3 t2 t3 {463.44m+limit(Zthtype,0,1)*175.99m} +Rth4 t3 t4 {369.67m+limit(Zthtype,0,1)*266.53m} +Rth5 t4 Tcase {402.31m+limit(Zthtype,0,1)*290.06m} +Cth1 Tj 0 54.297u +Cth2 t1 0 129.642u +Cth3 t2 0 1.539m +Cth4 t3 0 687.254u +Cth5 t4 0 25.436m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD33CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=1.22m Rg=1 Rd=50u Rm=450u +.PARAM Inn=27 Unn=10 Rmax=33m gmin=15 +.PARAM RRf=450m Rrbond=55m Rtb=11.6 g2=767m +.PARAM act=2.92 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.95m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {11.24m+limit(Zthtype,0,1)*4.16m} +Rth2 t1 t2 {115.99m+limit(Zthtype,0,1)*42.92m} +Rth3 t2 t3 {603.94m+limit(Zthtype,0,1)*235.6m} +Rth4 t3 t4 {498.05m+limit(Zthtype,0,1)*337.62m} +Rth5 t4 Tcase {447.28m+limit(Zthtype,0,1)*303.2m} +Cth1 Tj 0 40.653u +Cth2 t1 0 98.282u +Cth3 t2 0 1.19m +Cth4 t3 0 514.559u +Cth5 t4 0 25.184m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD49CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=2.01m Rg=0.9 Rd=50u Rm=650u +.PARAM Inn=20 Unn=10 Rmax=49m gmin=10.5 +.PARAM RRf=488m Rrbond=230m Rtb=23.6 g2=871m +.PARAM act=1.98 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 955.96u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {16.58m+limit(Zthtype,0,1)*6.13m} +Rth2 t1 t2 {167.72m+limit(Zthtype,0,1)*62.07m} +Rth3 t2 t3 {841.93m+limit(Zthtype,0,1)*348.69m} +Rth4 t3 t4 {748.13m+limit(Zthtype,0,1)*425.86m} +Rth5 t4 Tcase {498.9m+limit(Zthtype,0,1)*283.99m} +Cth1 Tj 0 27.566u +Cth2 t1 0 67.968u +Cth3 t2 0 868.439u +Cth4 t3 0 348.914u +Cth5 t4 0 29.676m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPD78CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=3.14m Rg=0.8 Rd=50u Rm=660u +.PARAM Inn=13 Unn=10 Rmax=78m gmin=6.5 +.PARAM RRf=497m Rrbond=884m Rtb=46.3 g2=930m +.PARAM act=1.238 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 487.73u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {26.51m+limit(Zthtype,0,1)*9.81m} +Rth2 t1 t2 {260.54m+limit(Zthtype,0,1)*96.42m} +Rth3 t2 t3 {1.23+limit(Zthtype,0,1)*565.19m} +Rth4 t3 t4 {1.23+limit(Zthtype,0,1)*664.58m} +Rth5 t4 Tcase {530.38m+limit(Zthtype,0,1)*286.57m} +Cth1 Tj 0 17.236u +Cth2 t1 0 43.753u +Cth3 t2 0 609.936u +Cth4 t3 0 218.159u +Cth5 t4 0 106.171m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD64CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=3.14m Rg=0.9 Rd=50u Rm=660u +.PARAM Inn=17 Unn=10 Rmax=64m gmin=4.86 +.PARAM RRf=497m Rrbond=884m Rtb=46.3 g2=930m +.PARAM act=1.98 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 487.73u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {16.58m+limit(Zthtype,0,1)*6.13m} +Rth2 t1 t2 {167.72m+limit(Zthtype,0,1)*62.07m} +Rth3 t2 t3 {841.93m+limit(Zthtype,0,1)*348.69m} +Rth4 t3 t4 {748.13m+limit(Zthtype,0,1)*425.86m} +Rth5 t4 Tcase {498.9m+limit(Zthtype,0,1)*283.99m} +Cth1 Tj 0 27.566u +Cth2 t1 0 67.968u +Cth3 t2 0 868.439u +Cth4 t3 0 348.914u +Cth5 t4 0 29.676m +Cth6 Tcase 0 70m + +.ENDS + +********** + + +.SUBCKT BSC079N10NS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=7.9m gmin=40 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=11.21 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.93m+limit(Zthtype,0,1)*1.08m} +Rth2 t1 t2 {31.62m+limit(Zthtype,0,1)*11.71m} +Rth3 t2 t3 {174.06m+limit(Zthtype,0,1)*60.85m} +Rth4 t3 t4 {127.51m+limit(Zthtype,0,1)*53.35m} +Rth5 t4 Tcase {237.51m+limit(Zthtype,0,1)*99.38m} +Cth1 Tj 0 156.068u +Cth2 t1 0 360.466u +Cth3 t2 0 4.012m +Cth4 t3 0 1.975m +Cth5 t4 0 43.728m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC118N10NS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=11.8m gmin=33 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=7.207 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.55m+limit(Zthtype,0,1)*1.69m} +Rth2 t1 t2 {48.61m+limit(Zthtype,0,1)*17.99m} +Rth3 t2 t3 {259.98m+limit(Zthtype,0,1)*94.86m} +Rth4 t3 t4 {198.33m+limit(Zthtype,0,1)*67.23m} +Rth5 t4 Tcase {303.78m+limit(Zthtype,0,1)*102.98m} +Cth1 Tj 0 100.337u +Cth2 t1 0 234.513u +Cth3 t2 0 2.715m +Cth4 t3 0 1.27m +Cth5 t4 0 31.977m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC196N10NS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=45 Unn=10 Rmax=19.6m gmin=24 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=4.269 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.69m+limit(Zthtype,0,1)*2.84m} +Rth2 t1 t2 {80.62m+limit(Zthtype,0,1)*29.83m} +Rth3 t2 t3 {427.48m+limit(Zthtype,0,1)*160.67m} +Rth4 t3 t4 {336.57m+limit(Zthtype,0,1)*77.37m} +Rth5 t4 Tcase {387.78m+limit(Zthtype,0,1)*89.15m} +Cth1 Tj 0 59.434u +Cth2 t1 0 141.405u +Cth3 t2 0 1.664m +Cth4 t3 0 752.279u +Cth5 t4 0 25.896m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC100N10NSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=10m gmin=20 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=11.21 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.93m+limit(Zthtype,0,1)*1.08m} +Rth2 t1 t2 {31.62m+limit(Zthtype,0,1)*11.71m} +Rth3 t2 t3 {174.06m+limit(Zthtype,0,1)*60.85m} +Rth4 t3 t4 {127.51m+limit(Zthtype,0,1)*53.35m} +Rth5 t4 Tcase {237.51m+limit(Zthtype,0,1)*99.38m} +Cth1 Tj 0 156.068u +Cth2 t1 0 360.466u +Cth3 t2 0 4.012m +Cth4 t3 0 1.975m +Cth5 t4 0 43.728m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC152N10NSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=15.2m gmin=16 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=7.207 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.55m+limit(Zthtype,0,1)*1.69m} +Rth2 t1 t2 {48.61m+limit(Zthtype,0,1)*17.99m} +Rth3 t2 t3 {259.98m+limit(Zthtype,0,1)*94.86m} +Rth4 t3 t4 {198.33m+limit(Zthtype,0,1)*67.23m} +Rth5 t4 Tcase {303.78m+limit(Zthtype,0,1)*102.98m} +Cth1 Tj 0 100.337u +Cth2 t1 0 234.513u +Cth3 t2 0 2.715m +Cth4 t3 0 1.27m +Cth5 t4 0 31.977m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC252N10NSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=39 Unn=10 Rmax=25.2m gmin=17 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=4.269 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.69m+limit(Zthtype,0,1)*2.84m} +Rth2 t1 t2 {80.62m+limit(Zthtype,0,1)*29.83m} +Rth3 t2 t3 {427.48m+limit(Zthtype,0,1)*160.67m} +Rth4 t3 t4 {336.57m+limit(Zthtype,0,1)*77.37m} +Rth5 t4 Tcase {387.78m+limit(Zthtype,0,1)*89.15m} +Cth1 Tj 0 59.434u +Cth2 t1 0 141.405u +Cth3 t2 0 1.664m +Cth4 t3 0 752.279u +Cth5 t4 0 25.896m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC750N10ND drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=5.06m Rg=0.8 Rd=10u Rm=2m +.PARAM Inn=12 Unn=10 Rmax=75m gmin=7.1 +.PARAM RRf=500m Rrbond=2 Rtb=67.5 g2=995m +.PARAM act=1.238 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 92.18u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {26.51m+limit(Zthtype,0,1)*9.81m} +Rth2 t1 t2 {260.54m+limit(Zthtype,0,1)*96.42m} +Rth3 t2 t3 {1.23+limit(Zthtype,0,1)*565.19m} +Rth4 t3 t4 {1.23+limit(Zthtype,0,1)*664.58m} +Rth5 t4 Tcase {530.38m+limit(Zthtype,0,1)*286.57m} +Cth1 Tj 0 17.236u +Cth2 t1 0 43.753u +Cth3 t2 0 609.936u +Cth4 t3 0 218.159u +Cth5 t4 0 106.171m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPP05CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=350u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.4m gmin=81 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=23.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.4m+limit(Zthtype,0,1)*515.4u} +Rth2 t1 t2 {15.33m+limit(Zthtype,0,1)*5.68m} +Rth3 t2 t3 {87.39m+limit(Zthtype,0,1)*28.98m} +Rth4 t3 t4 {75.43m+limit(Zthtype,0,1)*29.02m} +Rth5 t4 Tcase {185.07m+limit(Zthtype,0,1)*71.19m} +Cth1 Tj 0 326.755u +Cth2 t1 0 743.512u +Cth3 t2 0 7.891m +Cth4 t3 0 3.99m +Cth5 t4 0 121.993m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP06CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=350u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.5m gmin=77 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=17.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.83m+limit(Zthtype,0,1)*681.8u} +Rth2 t1 t2 {20m+limit(Zthtype,0,1)*7.41m} +Rth3 t2 t3 {113.28m+limit(Zthtype,0,1)*38.04m} +Rth4 t3 t4 {98.91m+limit(Zthtype,0,1)*67.42m} +Rth5 t4 Tcase {209.58m+limit(Zthtype,0,1)*142.85m} +Cth1 Tj 0 249.208u +Cth2 t1 0 569.82u +Cth3 t2 0 6.105m +Cth4 t3 0 3.043m +Cth5 t4 0 100.531m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP08CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=350u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.5m gmin=57 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=12.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.54m+limit(Zthtype,0,1)*945.06u} +Rth2 t1 t2 {27.57m+limit(Zthtype,0,1)*10.21m} +Rth3 t2 t3 {154.04m+limit(Zthtype,0,1)*52.84m} +Rth4 t3 t4 {137.24m+limit(Zthtype,0,1)*97.36m} +Rth5 t4 Tcase {244.09m+limit(Zthtype,0,1)*173.16m} +Cth1 Tj 0 179.597u +Cth2 t1 0 413.456u +Cth3 t2 0 4.512m +Cth4 t3 0 2.193m +Cth5 t4 0 81.53m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP12CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=350u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.9m gmin=38 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {213.05m+limit(Zthtype,0,1)*127.18m} +Rth5 t4 Tcase {300.49m+limit(Zthtype,0,1)*179.38m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.413m +Cth5 t4 0 63.737m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP16CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=350u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16m gmin=30 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=6.16 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {5.33m+limit(Zthtype,0,1)*1.97m} +Rth2 t1 t2 {56.59m+limit(Zthtype,0,1)*20.95m} +Rth3 t2 t3 {306.84m+limit(Zthtype,0,1)*111.08m} +Rth4 t3 t4 {287.41m+limit(Zthtype,0,1)*164.5m} +Rth5 t4 Tcase {346.82m+limit(Zthtype,0,1)*198.51m} +Cth1 Tj 0 85.761u +Cth2 t1 0 201.422u +Cth3 t2 0 2.296m +Cth4 t3 0 1.047m +Cth5 t4 0 55.041m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPS12CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2n Lg=3n + +.PARAM Rs=791u Rg=1.5 Rd=250u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.4m gmin=38 +.PARAM RRf=301m Rrbond=14m Rtb=5.8 g2=623m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.9m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {0p+limit(Zthtype,0,1)*0p} +Rth5 t4 Tcase {140.17m+limit(Zthtype,0,1)*679.93m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.413m +Cth5 t4 0 63.737m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT BSC082N10LS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=8.2m gmin=60 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=11.21 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.93m+limit(Zthtype,0,1)*1.08m} +Rth2 t1 t2 {31.62m+limit(Zthtype,0,1)*11.71m} +Rth3 t2 t3 {174.06m+limit(Zthtype,0,1)*60.85m} +Rth4 t3 t4 {127.51m+limit(Zthtype,0,1)*53.35m} +Rth5 t4 Tcase {237.51m+limit(Zthtype,0,1)*99.38m} +Cth1 Tj 0 156.068u +Cth2 t1 0 360.466u +Cth3 t2 0 4.012m +Cth4 t3 0 1.975m +Cth5 t4 0 43.728m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC123N10LS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=12.3m gmin=49 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=7.207 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.55m+limit(Zthtype,0,1)*1.69m} +Rth2 t1 t2 {48.61m+limit(Zthtype,0,1)*17.99m} +Rth3 t2 t3 {259.98m+limit(Zthtype,0,1)*94.86m} +Rth4 t3 t4 {198.33m+limit(Zthtype,0,1)*67.23m} +Rth5 t4 Tcase {303.78m+limit(Zthtype,0,1)*102.98m} +Cth1 Tj 0 100.337u +Cth2 t1 0 234.513u +Cth3 t2 0 2.715m +Cth4 t3 0 1.27m +Cth5 t4 0 31.977m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC205N10LS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=45 Unn=10 Rmax=20.5m gmin=36 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=4.269 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.69m+limit(Zthtype,0,1)*2.84m} +Rth2 t1 t2 {80.62m+limit(Zthtype,0,1)*29.83m} +Rth3 t2 t3 {427.48m+limit(Zthtype,0,1)*160.67m} +Rth4 t3 t4 {336.57m+limit(Zthtype,0,1)*77.37m} +Rth5 t4 Tcase {387.78m+limit(Zthtype,0,1)*89.15m} +Cth1 Tj 0 59.434u +Cth2 t1 0 141.405u +Cth3 t2 0 1.664m +Cth4 t3 0 752.279u +Cth5 t4 0 25.896m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC105N10LSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1.3 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=10.5m gmin=40 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=11.21 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.93m+limit(Zthtype,0,1)*1.08m} +Rth2 t1 t2 {31.62m+limit(Zthtype,0,1)*11.71m} +Rth3 t2 t3 {174.06m+limit(Zthtype,0,1)*60.85m} +Rth4 t3 t4 {127.51m+limit(Zthtype,0,1)*53.35m} +Rth5 t4 Tcase {237.51m+limit(Zthtype,0,1)*99.38m} +Cth1 Tj 0 156.068u +Cth2 t1 0 360.466u +Cth3 t2 0 4.012m +Cth4 t3 0 1.975m +Cth5 t4 0 43.728m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC159N10LSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=1.0 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=15.9m gmin=32 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=7.207 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.55m+limit(Zthtype,0,1)*1.69m} +Rth2 t1 t2 {48.61m+limit(Zthtype,0,1)*17.99m} +Rth3 t2 t3 {259.98m+limit(Zthtype,0,1)*94.86m} +Rth4 t3 t4 {198.33m+limit(Zthtype,0,1)*67.23m} +Rth5 t4 Tcase {303.78m+limit(Zthtype,0,1)*102.98m} +Cth1 Tj 0 100.337u +Cth2 t1 0 234.513u +Cth3 t2 0 2.715m +Cth4 t3 0 1.27m +Cth5 t4 0 31.977m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC265N10LSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1.5 Rd=10u Rm=106u +.PARAM Inn=50 Unn=10 Rmax=26.5m gmin=24 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=4.269 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.69m+limit(Zthtype,0,1)*2.84m} +Rth2 t1 t2 {80.62m+limit(Zthtype,0,1)*29.83m} +Rth3 t2 t3 {427.48m+limit(Zthtype,0,1)*160.67m} +Rth4 t3 t4 {336.57m+limit(Zthtype,0,1)*77.37m} +Rth5 t4 Tcase {387.78m+limit(Zthtype,0,1)*89.15m} +Cth1 Tj 0 59.434u +Cth2 t1 0 141.405u +Cth3 t2 0 1.664m +Cth4 t3 0 752.279u +Cth5 t4 0 25.896m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPB04CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=623u Rg=1.9 Rd=50u Rm=156u +.PARAM Inn=100 Unn=10 Rmax=4.1m gmin=87 +.PARAM act=27.1 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB05CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=50u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.1m gmin=81 +.PARAM act=23.47 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB06CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=50u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.2m gmin=77 +.PARAM act=17.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB08CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=50u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.2m gmin=57 +.PARAM act=12.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB12CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=1n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=50u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.6m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB16CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=1n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=50u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16.2m gmin=30 +.PARAM act=6.16 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP04CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=623u Rg=1.9 Rd=350u Rm=156u +.PARAM Inn=100 Unn=10 Rmax=4.4m gmin=87 +.PARAM act=27.1 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP05CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=350u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.4m gmin=81 +.PARAM act=23.47 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP06CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=350u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.5m gmin=77 +.PARAM act=17.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP08CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=350u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.5m gmin=57 +.PARAM act=12.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP12CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=350u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.9m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP16CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=350u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16.5m gmin=30 +.PARAM act=6.16 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP26CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=1.72m Rg=1.1 Rd=350u Rm=640u +.PARAM Inn=35 Unn=10 Rmax=26m gmin=19 +.PARAM act=3.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP35CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=1.53m Rg=1 Rd=350u Rm=450u +.PARAM Inn=27 Unn=10 Rmax=35m gmin=15 +.PARAM act=2.92 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP50CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=2.62m Rg=0.9 Rd=350u Rm=650u +.PARAM Inn=20 Unn=10 Rmax=50m gmin=10.5 +.PARAM act=1.98 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP80CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=4.3m Rg=0.8 Rd=350u Rm=660u +.PARAM Inn=13 Unn=10 Rmax=80m gmin=6.5 +.PARAM act=1.238 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD12CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=791u Rg=1.5 Rd=50u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.4m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD16CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=741u Rg=1.2 Rd=50u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16m gmin=30 +.PARAM act=6.16 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD25CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=1.41m Rg=1.1 Rd=50u Rm=640u +.PARAM Inn=35 Unn=10 Rmax=25m gmin=19 +.PARAM act=3.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD33CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=1.22m Rg=1 Rd=50u Rm=450u +.PARAM Inn=27 Unn=10 Rmax=33m gmin=15 +.PARAM act=2.92 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD49CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=2.01m Rg=0.9 Rd=50u Rm=650u +.PARAM Inn=20 Unn=10 Rmax=49m gmin=10.5 +.PARAM act=1.98 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD78CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=3.14m Rg=0.8 Rd=50u Rm=660u +.PARAM Inn=13 Unn=10 Rmax=78m gmin=6.5 +.PARAM act=1.238 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC079N10NS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=7.9m gmin=40 +.PARAM act=11.21 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC118N10NS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=11.8m gmin=33 +.PARAM act=7.207 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC196N10NS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=45 Unn=10 Rmax=19.6m gmin=24 +.PARAM act=4.269 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD64CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=3.14m Rg=0.9 Rd=50u Rm=660u +.PARAM Inn=17 Unn=10 Rmax=64m gmin=4.86 +.PARAM act=1.98 + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC100N10NSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=10m gmin=20 +.PARAM act=11.21 + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC152N10NSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=15.2m gmin=16 +.PARAM act=7.207 + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC252N10NSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=39 Unn=10 Rmax=25.2m gmin=17 +.PARAM act=4.269 + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC750N10ND_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=5.06m Rg=0.8 Rd=10u Rm=2m +.PARAM Inn=12 Unn=10 Rmax=75m gmin=7.1 +.PARAM act=1.238 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP05CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=350u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.4m gmin=81 +.PARAM act=23.47 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP06CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=350u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.5m gmin=77 +.PARAM act=17.9 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP08CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=350u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.5m gmin=57 +.PARAM act=12.9 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP12CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=350u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.9m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP16CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=350u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16m gmin=30 +.PARAM act=6.16 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPS12CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2n Lg=3n + +.PARAM Rs=791u Rg=1.5 Rd=250u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.4m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC082N10LS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=8.2m gmin=60 +.PARAM act=11.21 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC123N10LS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=12.3m gmin=49 +.PARAM act=7.207 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC205N10LS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=45 Unn=10 Rmax=20.5m gmin=36 +.PARAM act=4.269 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC105N10LSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1.3 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=10.5m gmin=40 +.PARAM act=11.21 + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC159N10LSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=1.0 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=15.9m gmin=32 +.PARAM act=7.207 + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC265N10LSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1.5 Rd=10u Rm=106u +.PARAM Inn=50 Unn=10 Rmax=26.5m gmin=24 +.PARAM act=4.269 + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB04CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 623u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 372.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 2.3m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=7.7n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=51.5p N=1.11 RS=0.74u EG=1.12 TT=90n) +Rdiode d1 21 0.53m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.39n +.MODEL DGD D(M=2.4 CJO=3.39n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 10.36n + +.ENDS IPB04CN10N_L0 + +****** + +.SUBCKT IPP04CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 623u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 372.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 2.6m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=7.7n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=51.5p N=1.11 RS=0.74u EG=1.12 TT=90n) +Rdiode d1 21 0.53m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.39n +.MODEL DGD D(M=2.4 CJO=3.39n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 10.36n + +.ENDS IPP04CN10N_L0 + +****** + +.SUBCKT IPB05CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 805u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 322.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 2.65m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=6.67n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=44.6p N=1.11 RS=0.85u EG=1.12 TT=90n) +Rdiode d1 21 0.61m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.94n +.MODEL DGD D(M=2.4 CJO=2.94n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.98n + +.ENDS IPB05CN10N_L0 + +****** + +.SUBCKT IPP05CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 805u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 322.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 2.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=6.67n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=44.6p N=1.11 RS=0.85u EG=1.12 TT=90n) +Rdiode d1 21 0.61m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.94n +.MODEL DGD D(M=2.4 CJO=2.94n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.98n + +.ENDS IPP05CN10N_L0 + +****** + +.SUBCKT IPB06CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 745u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 246.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 3.46m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=5.08n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=34p N=1.11 RS=1.12u EG=1.12 TT=90n) +Rdiode d1 21 0.8m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.24n +.MODEL DGD D(M=2.4 CJO=2.24n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.86n + +.ENDS IPB06CN10N_L0 + +****** + +.SUBCKT IPP06CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 745u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 246.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 3.76m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=5.08n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=34p N=1.11 RS=1.12u EG=1.12 TT=90n) +Rdiode d1 21 0.8m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.24n +.MODEL DGD D(M=2.4 CJO=2.24n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.86n + +.ENDS IPP06CN10N_L0 + +****** + +.SUBCKT IPB08CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 705u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 177.4 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 4.78m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.66n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=24.5p N=1.11 RS=1.55u EG=1.12 TT=90n) +Rdiode d1 21 1.12m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.62n +.MODEL DGD D(M=2.4 CJO=1.62n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.96n + +.ENDS IPB08CN10N_L0 + +****** + +.SUBCKT IPP08CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 705u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 177.4 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.08m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.66n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=24.5p N=1.11 RS=1.55u EG=1.12 TT=90n) +Rdiode d1 21 1.12m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.62n +.MODEL DGD D(M=2.4 CJO=1.62n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.96n + +.ENDS IPP08CN10N_L0 + +****** + +.SUBCKT IPB12CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 4n +Rs s1 s2 958u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 114.3 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 7.39m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.11 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.73m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.22n + +.ENDS IPB12CN10N_L0 + +****** + +.SUBCKT IPP12CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 958u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 114.3 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 7.69m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.11 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.73m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.22n + +.ENDS IPP12CN10N_L0 + +****** + +.SUBCKT IPD12CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 791u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 114.3 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 7.39m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.11 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.73m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.22n + +.ENDS IPD12CN10N_L0 + +****** + +.SUBCKT IPB16CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 4n +Rs s1 s2 908u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 84.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 9.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.11 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 2.34m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.4n + +.ENDS IPB16CN10N_L0 + +****** + +.SUBCKT IPP16CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 908u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 84.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 10.25m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.11 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 2.34m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.4n + +.ENDS IPP16CN10N_L0 + +****** + +.SUBCKT IPD16CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 741u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 84.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 9.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.11 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 2.34m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.4n + +.ENDS IPD16CN10N_L0 + +****** + +.SUBCKT IPP26CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 1.72m + +Rg g1 g2 1.1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 53.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 15.99m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.11n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=7.4p N=1.11 RS=5.13u EG=1.12 TT=90n) +Rdiode d1 21 3.69m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=2.4 CJO=0.49n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS IPP26CN10N_L0 + +****** + +.SUBCKT IPD25CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 1.41m + +Rg g1 g2 1.1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 53.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 15.69m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.11n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=7.4p N=1.11 RS=5.13u EG=1.12 TT=90n) +Rdiode d1 21 3.69m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=2.4 CJO=0.49n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS IPD25CN10N_L0 + +****** + +.SUBCKT IPP35CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 1.53m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 40.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 21.24m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.83n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=5.5p N=1.11 RS=6.85u EG=1.12 TT=90n) +Rdiode d1 21 4.93m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.37n +.MODEL DGD D(M=2.4 CJO=0.37n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.17n + +.ENDS IPP35CN10N_L0 + +****** + +.SUBCKT IPD33CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 1.22m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 40.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 20.94m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.83n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=5.5p N=1.11 RS=6.85u EG=1.12 TT=90n) +Rdiode d1 21 4.93m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.37n +.MODEL DGD D(M=2.4 CJO=0.37n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.17n + +.ENDS IPD33CN10N_L0 + +****** + +.SUBCKT IPP50CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 2.62m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 27.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 31.16m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.56n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.11 RS=10.1u EG=1.12 TT=90n) +Rdiode d1 21 7.27m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.25n +.MODEL DGD D(M=2.4 CJO=0.25n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.81n + +.ENDS IPP50CN10N_L0 + +****** + +.SUBCKT IPD49CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 2.01m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 27.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 30.86m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.56n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.11 RS=10.1u EG=1.12 TT=90n) +Rdiode d1 21 7.27m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.25n +.MODEL DGD D(M=2.4 CJO=0.25n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.81n + +.ENDS IPD49CN10N_L0 + +****** + +.SUBCKT IPP80CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 4.3m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 49.62m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.35n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=2.4p N=1.11 RS=16.16u EG=1.12 TT=90n) +Rdiode d1 21 11.63m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.16n +.MODEL DGD D(M=2.4 CJO=0.16n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.53n + +.ENDS IPP80CN10N_L0 + +****** + +.SUBCKT IPD78CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 3.14m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 49.32m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.35n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=2.4p N=1.11 RS=16.16u EG=1.12 TT=90n) +Rdiode d1 21 11.63m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.16n +.MODEL DGD D(M=2.4 CJO=0.16n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.53n + +.ENDS IPD78CN10N_L0 + +****** + +.SUBCKT BSC079N10NS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 154.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.45m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.18n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.11 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 1.28m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.405n +.MODEL DGD D(M=2.4 CJO=1.405n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.32n + +.ENDS BSC079N10NS_L0 + +****** + +.SUBCKT BSC118N10NS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 99.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.47m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.05n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.11 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 2m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.905n +.MODEL DGD D(M=2.4 CJO=0.905n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.8n + +.ENDS BSC118N10NS_L0 + +****** + +.SUBCKT BSC196N10NS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 58.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 14.3m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.21n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.11 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 3.37m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.538n +.MODEL DGD D(M=2.4 CJO=0.538n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.68n + +.ENDS BSC196N10NS_L0 + +****** + +.SUBCKT IPD64CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 3.14m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 16.7 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 30.05m TC=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.4n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.11 RS=10.1u EG=1.12 TT=90n) +Rdiode d1 21 4.04m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.127n +.MODEL DGD D(M=2.1 CJO=0.127n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.43n + +.ENDS IPD64CN10N_L0 + +****** + +.SUBCKT BSC100N10NSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 94.7 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.31m TC=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.24n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.11 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 0.71m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.699n +.MODEL DGD D(M=2.1 CJO=0.699n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.18n + +.ENDS BSC100N10NSF_L0 + +****** + +.SUBCKT BSC152N10NSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 60.9 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.25m TC=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.44n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.11 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 1.11m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.451n +.MODEL DGD D(M=2.1 CJO=0.451n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.42n + +.ENDS BSC152N10NSF_L0 + +****** + +.SUBCKT BSC252N10NSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 36.1 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 13.92m TC=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.85n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.11 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 1.87m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.269n +.MODEL DGD D(M=2.1 CJO=0.269n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.87n + +.ENDS BSC252N10NSF_L0 + +****** + +.SUBCKT BSC750N10ND_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 5.06m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 49.28m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.35n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=2.4p N=1.11 RS=16.16u EG=1.12 TT=90n) +Rdiode d1 21 11.63m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.16n +.MODEL DGD D(M=2.4 CJO=0.16n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.53n + +.ENDS BSC750N10ND_L0 + +****** + +.SUBCKT IPP05CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 805u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 535.1 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 3.09m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=6.67n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=44.6p N=1.07 RS=0.85u EG=1.12 TT=90n) +Rdiode d1 21 0.7m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.94n +.MODEL DGD D(M=2.4 CJO=2.94n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.56n + +.ENDS IPP05CN10L_L0 + +****** + +.SUBCKT IPP06CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 745u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 408.1 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 3.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=5.08n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=34p N=1.07 RS=1.12u EG=1.12 TT=90n) +Rdiode d1 21 0.92m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.24n +.MODEL DGD D(M=2.4 CJO=2.24n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.83n + +.ENDS IPP06CN10L_L0 + +****** + +.SUBCKT IPP08CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 705u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 294.1 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.34m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.66n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=24.5p N=1.07 RS=1.55u EG=1.12 TT=90n) +Rdiode d1 21 1.28m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.62n +.MODEL DGD D(M=2.4 CJO=1.62n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.38n + +.ENDS IPP08CN10L_L0 + +****** + +.SUBCKT IPP12CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 958u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 189.5 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.1m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.07 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.99m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.13n + +.ENDS IPP12CN10L_L0 + +****** + +.SUBCKT IPS12CN10L_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 2n +Ls source s1 2n +Rs s1 s2 791u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 189.5 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.07 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.99m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.13n + +.ENDS IPS12CN10L_L0 + +****** + +.SUBCKT IPP16CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 908u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 140.4 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 10.8m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.07 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 2.68m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.08n + +.ENDS IPP16CN10L_L0 + +****** + +.SUBCKT BSC082N10LS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 255.6 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.75m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.18n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.07 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 1.47m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.405n +.MODEL DGD D(M=2.4 CJO=1.405n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 5.55n + +.ENDS BSC082N10LS_L0 + +****** + +.SUBCKT BSC123N10LS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 164.3 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.05n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.07 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 2.29m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.905n +.MODEL DGD D(M=2.4 CJO=0.905n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.59n + +.ENDS BSC123N10LS_L0 + +****** + +.SUBCKT BSC205N10LS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 97.3 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 15.1m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.21n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.07 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 3.87m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.538n +.MODEL DGD D(M=2.4 CJO=0.538n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.15n + +.ENDS BSC205N10LS_L0 + +****** + + +.SUBCKT BSC105N10LSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 125.6 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.54m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.25n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.07 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 1.47m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.699n +.MODEL DGD D(M=2.4 CJO=0.699n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.85n + +.ENDS BSC105N10LSF_L0 + +****** + +.SUBCKT BSC159N10LSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 1.0 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 80.7 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.61m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.09n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.07 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 2.29m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.451n +.MODEL DGD D(M=2.4 CJO=0.451n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.87n + +.ENDS BSC159N10LSF_L0 + +****** + +.SUBCKT BSC265N10LSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 47.8 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 14.53m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.24n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.07 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 3.87m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.269n +.MODEL DGD D(M=2.4 CJO=0.269n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.15n + +.ENDS BSC265N10LSF_L0 + +****** diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_IPD_BSC_L0.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_IPD_BSC_L0.slb new file mode 100755 index 0000000..1396eb9 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_IPD_BSC_L0.slb @@ -0,0 +1,197 @@ +*version 8.0 355263187 +@index +symloc DMOS 0 1038 b +symloc IPD12CN10N_L0:DMOS 1038 289 +symloc IPD16CN10N_L0:DMOS 1327 289 +symloc IPD25CN10N_L0:DMOS 1616 289 +symloc IPD33CN10N_L0:DMOS 1905 289 +symloc IPD49CN10N_L0:DMOS 2194 289 +symloc IPD78CN10N_L0:DMOS 2483 289 +symloc BSC079N10NS_L0:DMOS 2772 292 +symloc BSC118N10NS_L0:DMOS 3064 292 +symloc BSC196N10NS_L0:DMOS 3356 292 +symloc IPD64CN10N_L0:DMOS 3648 289 +symloc BSC100N10NSF_L0:DMOS 3937 295 +symloc BSC152N10NSF_L0:DMOS 4232 295 +symloc BSC252N10NSF_L0:DMOS 4527 295 +symloc BSC750N10ND_L0:DMOS 4822 292 +*symbol DMOS b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPD12CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD12CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD12CN10N_L0 +*symbol IPD16CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD16CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD16CN10N_L0 +*symbol IPD25CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD25CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD25CN10N_L0 +*symbol IPD33CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD33CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD33CN10N_L0 +*symbol IPD49CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD49CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD49CN10N_L0 +*symbol IPD78CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD78CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD78CN10N_L0 +*symbol BSC079N10NS_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC079N10NS_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC079N10NS_L0 +*symbol BSC118N10NS_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC118N10NS_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC118N10NS_L0 +*symbol BSC196N10NS_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC196N10NS_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC196N10NS_L0 +*symbol IPD64CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD64CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD64CN10N_L0 +*symbol BSC100N10NSF_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC100N10NSF_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC100N10NSF_L0 +*symbol BSC152N10NSF_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC152N10NSF_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC152N10NSF_L0 +*symbol BSC252N10NSF_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC252N10NSF_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC252N10NSF_L0 +*symbol BSC750N10ND_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC750N10ND_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC750N10ND_L0 diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_IPD_BSC_L1.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_IPD_BSC_L1.slb new file mode 100755 index 0000000..2d2064e --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_IPD_BSC_L1.slb @@ -0,0 +1,302 @@ +*version 8.0 3518319357 +@index +symloc DMOS_S2_L1_n 0 1402 b +symloc IPD12CN10N_L1:DMOS_S2_L1_n 1402 626 +symloc IPD16CN10N_L1:DMOS_S2_L1_n 2028 626 +symloc IPD25CN10N_L1:DMOS_S2_L1_n 2654 628 +symloc IPD33CN10N_L1:DMOS_S2_L1_n 3282 628 +symloc IPD49CN10N_L1:DMOS_S2_L1_n 3910 628 +symloc IPD78CN10N_L1:DMOS_S2_L1_n 4538 628 +symloc BSC079N10NS_L1:DMOS_S2_L1_n 5166 631 +symloc BSC118N10NS_L1:DMOS_S2_L1_n 5797 631 +symloc BSC196N10NS_L1:DMOS_S2_L1_n 6428 631 +symloc IPD64CN10N_L1:DMOS_S2_L1_n 7059 628 +symloc BSC100N10NSF_L1:DMOS_S2_L1_n 7687 634 +symloc BSC152N10NSF_L1:DMOS_S2_L1_n 8321 634 +symloc BSC252N10NSF_L1:DMOS_S2_L1_n 8955 634 +symloc BSC750N10ND_L1:DMOS_S2_L1_n 9589 631 +*symbol DMOS_S2_L1_n b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1_n +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS_S2_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hcn 100 Ls=1n +a 0 u 0:13 0 0 20 hcn 100 Ld=0.5n +a 0 u 0:13 0 0 30 hcn 100 Lg=2n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPD12CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD12CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD12CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD16CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD16CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD16CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD25CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD25CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD25CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD33CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD33CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD33CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD49CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD49CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD49CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD78CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD78CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD78CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC079N10NS_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC079N10NS_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC079N10NS_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC118N10NS_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC118N10NS_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC118N10NS_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC196N10NS_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC196N10NS_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC196N10NS_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol IPD64CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD64CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD64CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC100N10NSF_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC100N10NSF_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC100N10NSF_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC152N10NSF_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC152N10NSF_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC152N10NSF_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC252N10NSF_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC252N10NSF_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC252N10NSF_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC750N10ND_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC750N10ND_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC750N10ND_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_IPD_BSC_L3.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_IPD_BSC_L3.slb new file mode 100755 index 0000000..5ffb567 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_IPD_BSC_L3.slb @@ -0,0 +1,328 @@ +*version 8.0 3518319357 +@index +symloc DMOS_S2_L3_n 0 1796 b +symloc IPD12CN10N:DMOS_S2_L3_n 1796 691 +symloc IPD16CN10N:DMOS_S2_L3_n 2487 691 +symloc IPD25CN10N:DMOS_S2_L3_n 3178 693 +symloc IPD33CN10N:DMOS_S2_L3_n 3871 693 +symloc IPD49CN10N:DMOS_S2_L3_n 4564 693 +symloc IPD78CN10N:DMOS_S2_L3_n 5257 693 +symloc BSC079N10NS:DMOS_S2_L3_n 5950 696 +symloc BSC118N10NS:DMOS_S2_L3_n 6646 696 +symloc BSC196N10NS:DMOS_S2_L3_n 7342 696 +symloc IPD64CN10N:DMOS_S2_L3_n 8038 693 +symloc BSC100N10NSF:DMOS_S2_L3_n 8731 699 +symloc BSC152N10NSF:DMOS_S2_L3_n 9430 699 +symloc BSC252N10NSF:DMOS_S2_L3_n 10129 699 +symloc BSC750N10ND:DMOS_S2_L3_n 10828 696 +*symbol DMOS_S2_L3_n b +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tcase n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 30 20 +20 20 +; +v 0 10 20 +15 20 +; +v 0 15 10 +15 30 +; +v 0 30 20 +30 30 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +v 0 20 23 +20 17 +; +v 0 38 10 +30 10 +; +v 0 30 30 +38 30 +38 10 +; +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 5 d_info:,,,,,,,,,,,,,5, +Tcase +*symbol IPD12CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD12CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD12CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD16CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD16CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD16CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD25CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD25CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD25CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD33CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD33CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD33CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD49CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD49CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD49CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPD78CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD78CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD78CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC079N10NS ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC079N10NS +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC079N10NS +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC118N10NS ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC118N10NS +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC118N10NS +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC196N10NS ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC196N10NS +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC196N10NS +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol IPD64CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD64CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD64CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC100N10NSF ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC100N10NSF +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC100N10NSF +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC152N10NSF ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC152N10NSF +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC152N10NSF +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC252N10NSF ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC252N10NSF +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC252N10NSF +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC750N10ND ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC750N10ND +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC750N10ND +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_LL_L0.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_LL_L0.slb new file mode 100755 index 0000000..44b013d --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_LL_L0.slb @@ -0,0 +1,179 @@ +*version 9.1 2625222009 +@index +symloc DMOS 0 1038 b +symloc IPP05CN10L_L0:DMOS 1038 289 +symloc IPP06CN10L_L0:DMOS 1327 289 +symloc IPP08CN10L_L0:DMOS 1616 289 +symloc IPP12CN10L_L0:DMOS 1905 289 +symloc IPS12CN10L_L0:DMOS 2194 289 +symloc IPP16CN10L_L0:DMOS 2483 289 +symloc BSC082N10LS_L0:DMOS 2772 292 +symloc BSC123N10LS_L0:DMOS 3064 292 +symloc BSC205N10LS_L0:DMOS 3356 292 +symloc BSC105N10LSF_L0:DMOS 3648 295 +symloc BSC159N10LSF_L0:DMOS 3943 295 +symloc BSC265N10LSF_L0:DMOS 4238 295 +*symbol DMOS b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPP05CN10L_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP05CN10L_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP05CN10L_L0 +*symbol IPP06CN10L_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP06CN10L_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP06CN10L_L0 +*symbol IPP08CN10L_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP08CN10L_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP08CN10L_L0 +*symbol IPP12CN10L_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP12CN10L_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP12CN10L_L0 +*symbol IPS12CN10L_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPS12CN10L_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPS12CN10L_L0 +*symbol IPP16CN10L_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP16CN10L_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP16CN10L_L0 +*symbol BSC082N10LS_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC082N10LS_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC082N10LS_L0 +*symbol BSC123N10LS_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC123N10LS_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC123N10LS_L0 +*symbol BSC205N10LS_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC205N10LS_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC205N10LS_L0 +*symbol BSC105N10LSF_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC105N10LSF_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC105N10LSF_L0 +*symbol BSC159N10LSF_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC159N10LSF_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC159N10LSF_L0 +*symbol BSC265N10LSF_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC265N10LSF_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC265N10LSF_L0 diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_LL_L1.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_LL_L1.slb new file mode 100755 index 0000000..f8eb607 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_LL_L1.slb @@ -0,0 +1,270 @@ +*version 9.1 870567026 +@index +symloc DMOS_S2_L1_n 0 1402 b +symloc IPP05CN10L_L1:DMOS_S2_L1_n 1402 626 +symloc IPP06CN10L_L1:DMOS_S2_L1_n 2028 626 +symloc IPP08CN10L_L1:DMOS_S2_L1_n 2654 626 +symloc IPP12CN10L_L1:DMOS_S2_L1_n 3280 626 +symloc IPS12CN10L_L1:DMOS_S2_L1_n 3906 626 +symloc IPP16CN10L_L1:DMOS_S2_L1_n 4532 626 +symloc BSC082N10LS_L1:DMOS_S2_L1_n 5158 631 +symloc BSC123N10LS_L1:DMOS_S2_L1_n 5789 631 +symloc BSC205N10LS_L1:DMOS_S2_L1_n 6420 631 +symloc BSC105N10LSF_L1:DMOS_S2_L1_n 7051 634 +symloc BSC159N10LSF_L1:DMOS_S2_L1_n 7685 634 +symloc BSC265N10LSF_L1:DMOS_S2_L1_n 8319 634 +*symbol DMOS_S2_L1_n b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1_n +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS_S2_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hcn 100 Ls=1n +a 0 u 0:13 0 0 20 hcn 100 Ld=0.5n +a 0 u 0:13 0 0 30 hcn 100 Lg=2n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPP05CN10L_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP05CN10L_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP05CN10L_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP06CN10L_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP06CN10L_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP06CN10L_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP08CN10L_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP08CN10L_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP08CN10L_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP12CN10L_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP12CN10L_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP12CN10L_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPS12CN10L_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPS12CN10L_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPS12CN10L_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPP16CN10L_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP16CN10L_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP16CN10L_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol BSC082N10LS_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC082N10LS_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC082N10LS_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC123N10LS_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC123N10LS_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC123N10LS_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC205N10LS_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC205N10LS_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC205N10LS_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC105N10LSF_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC105N10LSF_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC105N10LSF_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC159N10LSF_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC159N10LSF_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC159N10LSF_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC265N10LSF_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC265N10LSF_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC265N10LSF_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_LL_L3.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_LL_L3.slb new file mode 100755 index 0000000..ebced16 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_LL_L3.slb @@ -0,0 +1,294 @@ +*version 9.1 162033701 +@index +symloc DMOS_S2_L3_n 0 1796 b +symloc IPP05CN10L:DMOS_S2_L3_n 1796 691 +symloc IPP06CN10L:DMOS_S2_L3_n 2487 691 +symloc IPP08CN10L:DMOS_S2_L3_n 3178 691 +symloc IPP12CN10L:DMOS_S2_L3_n 3869 691 +symloc IPS12CN10L:DMOS_S2_L3_n 4560 691 +symloc IPP16CN10L:DMOS_S2_L3_n 5251 691 +symloc BSC082N10LS:DMOS_S2_L3_n 5942 696 +symloc BSC123N10LS:DMOS_S2_L3_n 6638 696 +symloc BSC205N10LS:DMOS_S2_L3_n 7334 696 +symloc BSC105N10LSF:DMOS_S2_L3_n 8030 699 +symloc BSC159N10LSF:DMOS_S2_L3_n 8729 699 +symloc BSC265N10LSF:DMOS_S2_L3_n 9428 699 +*symbol DMOS_S2_L3_n b +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tcase n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 30 20 +20 20 +; +v 0 10 20 +15 20 +; +v 0 15 10 +15 30 +; +v 0 30 20 +30 30 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +v 0 20 23 +20 17 +; +v 0 38 10 +30 10 +; +v 0 30 30 +38 30 +38 10 +; +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 5 d_info:,,,,,,,,,,,,,5, +Tcase +*symbol IPP05CN10L ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP05CN10L +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP05CN10L +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP06CN10L ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP06CN10L +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP06CN10L +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP08CN10L ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP08CN10L +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP08CN10L +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP12CN10L ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP12CN10L +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP12CN10L +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPS12CN10L ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPS12CN10L +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPS12CN10L +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPP16CN10L ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP16CN10L +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP16CN10L +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol BSC082N10LS ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC082N10LS +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC082N10LS +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC123N10LS ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC123N10LS +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC123N10LS +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC205N10LS ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC205N10LS +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC205N10LS +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC105N10LSF ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC105N10LSF +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC105N10LSF +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC159N10LSF ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC159N10LSF +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC159N10LSF +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n +*symbol BSC265N10LSF ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC265N10LSF +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC265N10LSF +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=2n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_NL_IPB_IPP_L0.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_NL_IPB_IPP_L0.slb new file mode 100755 index 0000000..924e0d1 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_NL_IPB_IPP_L0.slb @@ -0,0 +1,215 @@ +*version 8.0 856205713 +@index +symloc DMOS 0 1038 b +symloc IPB04CN10N_L0:DMOS 1038 289 +symloc IPB05CN10N_L0:DMOS 1327 289 +symloc IPB06CN10N_L0:DMOS 1616 289 +symloc IPB08CN10N_L0:DMOS 1905 289 +symloc IPB12CN10N_L0:DMOS 2194 289 +symloc IPB16CN10N_L0:DMOS 2483 289 +symloc IPP04CN10N_L0:DMOS 2772 289 +symloc IPP05CN10N_L0:DMOS 3061 289 +symloc IPP06CN10N_L0:DMOS 3350 289 +symloc IPP08CN10N_L0:DMOS 3639 289 +symloc IPP12CN10N_L0:DMOS 3928 289 +symloc IPP16CN10N_L0:DMOS 4217 289 +symloc IPP26CN10N_L0:DMOS 4506 289 +symloc IPP35CN10N_L0:DMOS 4795 289 +symloc IPP50CN10N_L0:DMOS 5084 289 +symloc IPP80CN10N_L0:DMOS 5373 289 +*symbol DMOS b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPB04CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB04CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB04CN10N_L0 +*symbol IPB05CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB05CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB05CN10N_L0 +*symbol IPB06CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB06CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB06CN10N_L0 +*symbol IPB08CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB08CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB08CN10N_L0 +*symbol IPB12CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB12CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB12CN10N_L0 +*symbol IPB16CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB16CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB16CN10N_L0 +*symbol IPP04CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP04CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP04CN10N_L0 +*symbol IPP05CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP05CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP05CN10N_L0 +*symbol IPP06CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP06CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP06CN10N_L0 +*symbol IPP08CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP08CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP08CN10N_L0 +*symbol IPP12CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP12CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP12CN10N_L0 +*symbol IPP16CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP16CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP16CN10N_L0 +*symbol IPP26CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP26CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP26CN10N_L0 +*symbol IPP35CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP35CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP35CN10N_L0 +*symbol IPP50CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP50CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP50CN10N_L0 +*symbol IPP80CN10N_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP80CN10N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP80CN10N_L0 diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_NL_IPB_IPP_L1.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_NL_IPB_IPP_L1.slb new file mode 100755 index 0000000..af6cf00 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_NL_IPB_IPP_L1.slb @@ -0,0 +1,334 @@ +*version 8.0 99324507 +@index +symloc DMOS_S2_L1_n 0 1402 b +symloc IPB04CN10N_L1:DMOS_S2_L1_n 1402 626 +symloc IPB05CN10N_L1:DMOS_S2_L1_n 2028 626 +symloc IPB06CN10N_L1:DMOS_S2_L1_n 2654 626 +symloc IPB08CN10N_L1:DMOS_S2_L1_n 3280 626 +symloc IPB12CN10N_L1:DMOS_S2_L1_n 3906 626 +symloc IPB16CN10N_L1:DMOS_S2_L1_n 4532 626 +symloc IPP04CN10N_L1:DMOS_S2_L1_n 5158 626 +symloc IPP05CN10N_L1:DMOS_S2_L1_n 5784 626 +symloc IPP06CN10N_L1:DMOS_S2_L1_n 6410 626 +symloc IPP08CN10N_L1:DMOS_S2_L1_n 7036 626 +symloc IPP12CN10N_L1:DMOS_S2_L1_n 7662 626 +symloc IPP16CN10N_L1:DMOS_S2_L1_n 8288 626 +symloc IPP26CN10N_L1:DMOS_S2_L1_n 8914 626 +symloc IPP35CN10N_L1:DMOS_S2_L1_n 9540 626 +symloc IPP50CN10N_L1:DMOS_S2_L1_n 10166 626 +symloc IPP80CN10N_L1:DMOS_S2_L1_n 10792 626 +*symbol DMOS_S2_L1_n b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1_n +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS_S2_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hcn 100 Ls=1n +a 0 u 0:13 0 0 20 hcn 100 Ld=0.5n +a 0 u 0:13 0 0 30 hcn 100 Lg=2n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPB04CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB04CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB04CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB05CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB05CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB05CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB06CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB06CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB06CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB08CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB08CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB08CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB12CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB12CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB12CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB16CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB16CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB16CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP04CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP04CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP04CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP05CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP05CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP05CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP06CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP06CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP06CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP08CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP08CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP08CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP12CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP12CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP12CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP16CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP16CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP16CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP26CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP26CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP26CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP35CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP35CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP35CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP50CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP50CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP50CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP80CN10N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP80CN10N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP80CN10N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_NL_IPB_IPP_L3.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_NL_IPB_IPP_L3.slb new file mode 100755 index 0000000..87bfca6 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS2/OptiMOS2_100V_NL_IPB_IPP_L3.slb @@ -0,0 +1,362 @@ +*version 8.0 292739952 +@index +symloc DMOS_S2_L3_n 0 1796 b +symloc IPB04CN10N:DMOS_S2_L3_n 1796 691 +symloc IPB05CN10N:DMOS_S2_L3_n 2487 691 +symloc IPB06CN10N:DMOS_S2_L3_n 3178 691 +symloc IPB08CN10N:DMOS_S2_L3_n 3869 691 +symloc IPB12CN10N:DMOS_S2_L3_n 4560 691 +symloc IPB16CN10N:DMOS_S2_L3_n 5251 691 +symloc IPP04CN10N:DMOS_S2_L3_n 5942 691 +symloc IPP05CN10N:DMOS_S2_L3_n 6633 691 +symloc IPP06CN10N:DMOS_S2_L3_n 7324 691 +symloc IPP08CN10N:DMOS_S2_L3_n 8015 691 +symloc IPP12CN10N:DMOS_S2_L3_n 8706 691 +symloc IPP16CN10N:DMOS_S2_L3_n 9397 691 +symloc IPP26CN10N:DMOS_S2_L3_n 10088 691 +symloc IPP35CN10N:DMOS_S2_L3_n 10779 691 +symloc IPP50CN10N:DMOS_S2_L3_n 11470 691 +symloc IPP80CN10N:DMOS_S2_L3_n 12161 691 +*symbol DMOS_S2_L3_n b +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tcase n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 30 20 +20 20 +; +v 0 10 20 +15 20 +; +v 0 15 10 +15 30 +; +v 0 30 20 +30 30 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +v 0 20 23 +20 17 +; +v 0 38 10 +30 10 +; +v 0 30 30 +38 30 +38 10 +; +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 5 d_info:,,,,,,,,,,,,,5, +Tcase +*symbol IPB04CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB04CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB04CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB05CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB05CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB05CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB06CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB06CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB06CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB08CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB08CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB08CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB12CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB12CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB12CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB16CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB16CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB16CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP04CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP04CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP04CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP05CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP05CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP05CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP06CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP06CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP06CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP08CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP08CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP08CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=3n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP12CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP12CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP12CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP16CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP16CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP16CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=4n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP26CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP26CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP26CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP35CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP35CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP35CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP50CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP50CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP50CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP80CN10N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP80CN10N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP80CN10N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3 ReadMe.pdf b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3 ReadMe.pdf new file mode 100755 index 0000000..7205444 Binary files /dev/null and b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3 ReadMe.pdf differ diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V.lib b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V.lib new file mode 100755 index 0000000..7580efd --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V.lib @@ -0,0 +1,4548 @@ +***************************************************************** +* INFINEON Power Transistors * +* Level1/3 PSPICE Library for OptiMOS3 n-Channel Transistors * +* * +* This file also contains simplified models that are compatible * +* to standard Spice (Level 0) * +* * +* Version 150520 * +* * +***************************************************************** +***************************************************************** +* * +* The Simulation Model is subject to change without notice. In * +* addition, models can be a useful tool in evaluating device * +* performance, they cannot reflect the accurate device * +* performance under all conditions, nor are they intended to * +* replace bread boarding for final verification. Infineon * +* therefore does not assume any warranty or liability * +* whatsoever arising from their use. Infineon does not assume * +* any warranty or liability for the values and functions of the * +* Simulation Model. * +* The methods and results of the Simulation Model are to the * +* best of our knowledge * +* correct. However, the user is fully responsible to verify and * +* validate these results under the operating conditions and in * +* the environment of its application. Infineon will not bear * +* the responsibility arising out of or in connection with any * +* malfunction of the Simulation Models. * +* Models provided by Infineon are not warranted by Infineon as * +* completely and comprehensively representing all the * +* specifications and operating characteristics of the * +* semiconductor products to which these models relate. The * +* models describe the characteristics of typical devices. In * +* all cases, the current data sheet information for a given * +* device is the conclusive design guideline and the only actual * +* performance specification. * +* * +* This library contains models of the following INFINEON * +* OptiMOS3 transistors: * +* * +* 100V NL * +* IPB025N10N3 IPB027N10N3 IPB039N10N3 * +* IPB042N10N3 IPB083N10N3 IPB123N10N3 * +* IPP030N10N3 IPP045N10N3 IPP072N10N3 * +* IPP086N10N3 IPP881N10N3 IPP126N10N3 * +* IPP180N10N3 IPP882N10N3 IPA030N10N3 * +* IPA045N10N3 IPA086N10N3 IPA126N10NM3S * +* IPA180N10N3 IPI030N10N3 IPI045N10N3 * +* IPI072N10N3 IPI086N10N3 IPI126N10N3 * +* IPI180N10N3 IPD068N10N3 IPD082N10N3 * +* IPD122N10N3 IPD180N10N3 BSC046N10NS3 * +* BSC060N10NS3 BSC070N10NS3 BSC109N10NS3 * +* BSC160N10NS3 BSC440N10NS3 BSZ160N10NS3 * +* BSZ440N10NS3 BSB056N10NN3 BSF134N10NJ3 * +* IPT020N10N3 IPB065N10N3 * +* * +* 100V LL * +* BSZ150N10LS3 * +* * +***************************************************************** +* thermal nodes of level 3 models: * +* * +* .SUBCKT IPB042N10N3 drain gate source Tj Tcase * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Tcase : node where the boundary contition - external heat * +* sinks etc - have to be connected (ideal heat sink * +* can be modeled by using a voltage source stating the * +* ambient temperature in °C between Tcase and ground. * +* * +***************************************************************** + + +.SUBCKT S3_100_s_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.15 Fn=0.5 kbq=85.8u +.PARAM c=1.402 muc=0.0 Vth0=3.63 auth=4.244m al=0.5 +.PARAM UT=100m ab=56m ab2=0 lB=-23 UB=110 + +.PARAM b0=27.6 p0=5.816 p1=-15.2m p2=27u + +.PARAM Rd=37.52m nmu=3 Tref=298 T0=273 lnIsj=-24.877 +.PARAM ndi=1.188 Rdi=6.3m nmu2=0 ta=40n td=100n +.PARAM Rf=0.48 nmu3=1.55 rpa=0 + +.PARAM f3=405p f3a=0p +.PARAM ps1=35p ps2=-66.7m ps3=70p ps4=-2 ps5=1.18p ps6=3.14p +.PARAM qs1=35p qs2=54p qs3=-1 qs4=230p qs5=-0.0385 + +.PARAM Vmin=2.93 Vmax=4.43 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**1)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + + +.SUBCKT S3_100_s1_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.15 Fn=0.5 kbq=85.8u +.PARAM c=1.402 muc=0.0 Vth0=3.63 auth=4.244m al=0.5 +.PARAM UT=100m ab=56m ab2=0 lB=-23 UB=110 + +.PARAM b0=27.6 p0=5.816 p1=-15.2m p2=27u + +.PARAM Rd=37.52m nmu=3 Tref=298 T0=273 lnIsj=-24.877 +.PARAM ndi=1.188 Rdi=6.3m nmu2=0 ta=40n td=100n +.PARAM Rf=0.48 nmu3=1.55 rpa=0 + +.PARAM f3=405p f3a=125p +.PARAM ps1=35p ps2=-66.7m ps3=70p ps4=-2 ps5=1.18p ps6=3.14p + +.PARAM qs1=35p qs2=160p qs3=-0.0333 qs4=54p qs5=-1 f2r=1 + +.PARAM Vmin=2.93 Vmax=4.43 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*(1+f2r/SQRT(a))*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**1)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT S3_100_s2_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.15 Fn=0.5 kbq=85.8u +.PARAM c=1.402 muc=0.0 Vth0=3.63 auth=4.244m al=0.5 +.PARAM UT=100m ab=56m ab2=0 lB=-23 UB=110 + +.PARAM b0=27.6 p0=5.816 p1=-15.2m p2=27u + +.PARAM Rd=34.22m nmu=3 Tref=298 T0=273 lnIsj=-24.877 +.PARAM ndi=1.188 Rdi=6.3m nmu2=0 ta=40n td=100n +.PARAM Rf=0.48 nmu3=1.55 rpa=0 + +.PARAM f3=405p f3a=125p +.PARAM ps1=35p ps2=-66.7m ps3=70p ps4=-2 ps5=1.18p ps6=3.14p + +.PARAM qs1=35p qs2=160p qs3=-0.0333 qs4=54p qs5=-1 f2r=1 + +.PARAM Vmin=2.93 Vmax=4.43 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*(1+f2r/SQRT(a))*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**1)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + + +.SUBCKT S3_100_t_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.15 Fn=0.5 kbq=85.8u +.PARAM c=1.2 muc=0.0 Vth0=2.31 auth=3.265m al=0.5 +.PARAM UT=100m ab=56m ab2=0 lB=-23 UB=110 + +.PARAM b0=37.674 p0=4.474 p1=-11.7m p2=20.8u + +.PARAM Rd=35m nmu=3 Tref=298 T0=273 lnIsj=-24.877 +.PARAM ndi=1.188 Rdi=6.3m nmu2=0 ta=40n td=100n +.PARAM Rf=0.48 nmu3=1.55 rpa=0 + +.PARAM f3=526.5p f3a=162.5p +.PARAM ps1=45.5p ps2=-66.7m ps3=91p ps4=-2 ps5=1.18p ps6=3.14p + +.PARAM qs1=35p qs2=152p qs3=-0.0333 qs4=48.6p qs5=-1 f2r=1 + +.PARAM Vmin=1.91 Vmax=2.71 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*(1+f2r/SQRT(a))*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**1)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT IPB025N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=4n + +.PARAM Rs=393u Rg=1.9 Rd=20u Rm=126u +.PARAM Inn=100 Unn=10 Rmax=2.5m gmin=104 +.PARAM RRf=382m Rrbond=5m Rtb=3.6 g2=647m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.75m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {64.9m+limit(Zthtype,0,1)*42.31m} +Rth5 t4 Tcase {172.84m+limit(Zthtype,0,1)*112.68m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 4.637m +Cth5 t4 0 137.136m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPA030N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=657u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=79 Unn=10 Rmax=3m gmin=89 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {616.39m+limit(Zthtype,0,1)*471.09m} +Rth5 t4 Tcase {1.42+limit(Zthtype,0,1)*1.09} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 30.936m +Cth5 t4 0 789.515m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPB027N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=657u Rg=1.9 Rd=50u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=2.7m gmin=99 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {64.9m+limit(Zthtype,0,1)*42.31m} +Rth5 t4 Tcase {172.84m+limit(Zthtype,0,1)*112.68m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 4.637m +Cth5 t4 0 137.136m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPI030N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=697u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=98 +.PARAM RRf=386m Rrbond=15m Rtb=6.1 g2=755m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.22m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {64.9m+limit(Zthtype,0,1)*42.31m} +Rth5 t4 Tcase {172.84m+limit(Zthtype,0,1)*112.68m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 4.637m +Cth5 t4 0 137.136m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP030N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=697u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=98 +.PARAM RRf=386m Rrbond=15m Rtb=6.1 g2=755m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.22m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {64.9m+limit(Zthtype,0,1)*42.31m} +Rth5 t4 Tcase {172.84m+limit(Zthtype,0,1)*112.68m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 4.637m +Cth5 t4 0 137.136m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPB039N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=4n + +.PARAM Rs=445u Rg=1.4 Rd=20u Rm=141u +.PARAM Inn=100 Unn=10 Rmax=3.9m gmin=80 +.PARAM RRf=418m Rrbond=8m Rtb=4.3 g2=687m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 11.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {114.22m+limit(Zthtype,0,1)*58.76m} +Rth5 t4 Tcase {224.04m+limit(Zthtype,0,1)*115.25m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 2.635m +Cth5 t4 0 91.413m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPA045N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=64 Unn=10 Rmax=4.5m gmin=62 +.PARAM RRf=389m Rrbond=16m Rtb=6.2 g2=758m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.36m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {742.26m+limit(Zthtype,0,1)*503.52m} +Rth5 t4 Tcase {1.41+limit(Zthtype,0,1)*956.49m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 15.917m +Cth5 t4 0 797.929m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPB042N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=50u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.2m gmin=76 +.PARAM RRf=389m Rrbond=16m Rtb=6.2 g2=758m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.36m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {114.22m+limit(Zthtype,0,1)*58.76m} +Rth5 t4 Tcase {224.04m+limit(Zthtype,0,1)*115.25m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 2.635m +Cth5 t4 0 91.413m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPI045N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.5m gmin=76 +.PARAM RRf=389m Rrbond=16m Rtb=6.2 g2=758m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.36m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {114.22m+limit(Zthtype,0,1)*58.76m} +Rth5 t4 Tcase {224.04m+limit(Zthtype,0,1)*115.25m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 2.635m +Cth5 t4 0 91.413m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP045N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.5m gmin=76 +.PARAM RRf=389m Rrbond=16m Rtb=6.2 g2=758m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.36m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {114.22m+limit(Zthtype,0,1)*58.76m} +Rth5 t4 Tcase {224.04m+limit(Zthtype,0,1)*115.25m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 2.635m +Cth5 t4 0 91.413m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPB065N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=50u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=6.5m gmin=52 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=9.06 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {186.89m+limit(Zthtype,0,1)*64.43m} +Rth4 t3 t4 {195.41m+limit(Zthtype,0,1)*83.45m} +Rth5 t4 Tcase {288.39m+limit(Zthtype,0,1)*123.15m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.884m +Cth4 t3 0 1.54m +Cth5 t4 0 66.7m +Cth6 Tcase 0 190m + +.ENDS + +********** + + +.SUBCKT IPD068N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=824u Rg=1.6 Rd=50u Rm=345u +.PARAM Inn=90 Unn=10 Rmax=6.8m gmin=56 +.PARAM RRf=390m Rrbond=12m Rtb=5.5 g2=758m +.PARAM act=9.06 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {186.89m+limit(Zthtype,0,1)*64.43m} +Rth4 t3 t4 {157.76m+limit(Zthtype,0,1)*97.65m} +Rth5 t4 Tcase {268.68m+limit(Zthtype,0,1)*166.31m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.884m +Cth4 t3 0 1.597m +Cth5 t4 0 36.984m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPI072N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=350u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=7.2m gmin=52 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=9.06 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {186.89m+limit(Zthtype,0,1)*64.43m} +Rth4 t3 t4 {195.41m+limit(Zthtype,0,1)*83.45m} +Rth5 t4 Tcase {288.39m+limit(Zthtype,0,1)*123.15m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.884m +Cth4 t3 0 1.54m +Cth5 t4 0 66.7m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP072N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=350u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=7.2m gmin=52 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=9.06 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {186.89m+limit(Zthtype,0,1)*64.43m} +Rth4 t3 t4 {195.41m+limit(Zthtype,0,1)*83.45m} +Rth5 t4 Tcase {288.39m+limit(Zthtype,0,1)*123.15m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.884m +Cth4 t3 0 1.54m +Cth5 t4 0 66.7m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT BSC046N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=172u Rg=1.9 Rd=1u Rm=1u +.PARAM Inn=50 Unn=10 Rmax=4.6m gmin=51 + +.PARAM act=11.15 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {2.94m+limit(Zthtype,0,1)*1.09m} +Rth2 t1 t2 {31.79m+limit(Zthtype,0,1)*11.76m} +Rth3 t2 t3 {40.18m+limit(Zthtype,0,1)*4.91m} +Rth4 t3 t4 {128.19m+limit(Zthtype,0,1)*119.23m} +Rth5 t4 Tcase {238.28m+limit(Zthtype,0,1)*221.63m} +Cth1 Tj 0 155.233u +Cth2 t1 0 358.583u +Cth3 t2 0 864.139u +Cth4 t3 0 1.965m +Cth5 t4 0 43.525m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC060N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=404u Rg=1.6 Rd=50u Rm=233u +.PARAM Inn=50 Unn=10 Rmax=6m gmin=45 + +.PARAM act=9.06 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {146.86m+limit(Zthtype,0,1)*48.03m} +Rth4 t3 t4 {157.76m+limit(Zthtype,0,1)*118.53m} +Rth5 t4 Tcase {268.68m+limit(Zthtype,0,1)*201.86m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.294m +Cth4 t3 0 1.597m +Cth5 t4 0 36.984m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC070N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=334u Rg=1.9 Rd=50u Rm=163u +.PARAM Inn=50 Unn=10 Rmax=7m gmin=41 + +.PARAM act=7.33 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {178.11m+limit(Zthtype,0,1)*59.47m} +Rth4 t3 t4 {195m+limit(Zthtype,0,1)*115.8m} +Rth5 t4 Tcase {301.14m+limit(Zthtype,0,1)*178.83m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 1.9m +Cth4 t3 0 1.292m +Cth5 t4 0 32.286m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC109N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=254u Rg=1.1 Rd=50u Rm=83u +.PARAM Inn=46 Unn=10 Rmax=10.9m gmin=31 + +.PARAM act=4.6 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {269.05m+limit(Zthtype,0,1)*95.2m} +Rth4 t3 t4 {310.73m+limit(Zthtype,0,1)*152.43m} +Rth5 t4 Tcase {375.71m+limit(Zthtype,0,1)*184.31m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.275m +Cth4 t3 0 810.607u +Cth5 t4 0 26.401m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPA086N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=45 Unn=10 Rmax=8.6m gmin=36 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {1.02+limit(Zthtype,0,1)*500.31m} +Rth5 t4 Tcase {1.41+limit(Zthtype,0,1)*691.6m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 9.834m +Cth5 t4 0 1.052 +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPB083N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=50u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.3m gmin=45 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {241.53m+limit(Zthtype,0,1)*112.6m} +Rth5 t4 Tcase {319.05m+limit(Zthtype,0,1)*148.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.246m +Cth5 t4 0 59.815m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD082N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=932u Rg=1.9 Rd=50u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.2m gmin=46 +.PARAM RRf=390m Rrbond=12m Rtb=5.5 g2=758m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {195m+limit(Zthtype,0,1)*128.04m} +Rth5 t4 Tcase {301.14m+limit(Zthtype,0,1)*197.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.292m +Cth5 t4 0 32.286m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPI086N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {241.53m+limit(Zthtype,0,1)*112.6m} +Rth5 t4 Tcase {319.05m+limit(Zthtype,0,1)*148.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.246m +Cth5 t4 0 59.815m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP086N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {241.53m+limit(Zthtype,0,1)*112.6m} +Rth5 t4 Tcase {319.05m+limit(Zthtype,0,1)*148.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.246m +Cth5 t4 0 59.815m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPP881N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {241.53m+limit(Zthtype,0,1)*112.6m} +Rth5 t4 Tcase {319.05m+limit(Zthtype,0,1)*148.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.246m +Cth5 t4 0 59.815m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPA126N10NM3S drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=35 Unn=10 Rmax=12.6m gmin=26 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {1.2+limit(Zthtype,0,1)*601.06m} +Rth5 t4 Tcase {1.41+limit(Zthtype,0,1)*706.25m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 5.75m +Cth5 t4 0 1.041 +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPB123N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=50u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.3m gmin=30 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {328.76m+limit(Zthtype,0,1)*130.54m} +Rth5 t4 Tcase {399.42m+limit(Zthtype,0,1)*158.59m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 781.931u +Cth5 t4 0 48.493m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD122N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=729u Rg=2 Rd=50u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.2m gmin=30 +.PARAM RRf=390m Rrbond=12m Rtb=5.5 g2=758m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {311.23m+limit(Zthtype,0,1)*149.68m} +Rth5 t4 Tcase {375.71m+limit(Zthtype,0,1)*180.69m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 810.607u +Cth5 t4 0 26.401m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPI126N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.6m gmin=30 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {328.76m+limit(Zthtype,0,1)*130.54m} +Rth5 t4 Tcase {399.42m+limit(Zthtype,0,1)*158.59m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 781.931u +Cth5 t4 0 48.493m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP126N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.6m gmin=30 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {328.76m+limit(Zthtype,0,1)*130.54m} +Rth5 t4 Tcase {399.42m+limit(Zthtype,0,1)*158.59m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 781.931u +Cth5 t4 0 48.493m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPA180N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=28 Unn=10 Rmax=18m gmin=20 +.PARAM RRf=488m Rrbond=141m Rtb=18.5 g2=904m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.12m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {1.2+limit(Zthtype,0,1)*732.5m} +Rth5 t4 Tcase {1.41+limit(Zthtype,0,1)*860.68m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 5.75m +Cth5 t4 0 1.041 +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPD180N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=1.24m Rg=2 Rd=50u Rm=481u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=22 +.PARAM RRf=472m Rrbond=50m Rtb=11 g2=862m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {437.86m+limit(Zthtype,0,1)*170.12m} +Rth5 t4 Tcase {428.66m+limit(Zthtype,0,1)*166.54m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 581.523u +Cth5 t4 0 25.044m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPI180N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM RRf=488m Rrbond=141m Rtb=18.5 g2=904m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.12m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {422.91m+limit(Zthtype,0,1)*147.15m} +Rth5 t4 Tcase {469.7m+limit(Zthtype,0,1)*163.42m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 560.95u +Cth5 t4 0 42.901m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP180N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM RRf=488m Rrbond=141m Rtb=18.5 g2=904m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.12m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {422.91m+limit(Zthtype,0,1)*147.15m} +Rth5 t4 Tcase {469.7m+limit(Zthtype,0,1)*163.42m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 560.95u +Cth5 t4 0 42.901m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPP882N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM RRf=488m Rrbond=141m Rtb=18.5 g2=904m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.12m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {422.91m+limit(Zthtype,0,1)*147.15m} +Rth5 t4 Tcase {469.7m+limit(Zthtype,0,1)*163.42m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 560.95u +Cth5 t4 0 42.901m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT BSC160N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=603u Rg=2 Rd=50u Rm=411u +.PARAM Inn=33 Unn=10 Rmax=16m gmin=22 + +.PARAM act=3.3 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {363.94m+limit(Zthtype,0,1)*133.22m} +Rth4 t3 t4 {433.13m+limit(Zthtype,0,1)*244.28m} +Rth5 t4 Tcase {428.66m+limit(Zthtype,0,1)*241.75m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 951.044u +Cth4 t3 0 581.523u +Cth5 t4 0 25.044m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ160N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=577u Rg=2 Rd=50u Rm=281u +.PARAM Inn=20 Unn=10 Rmax=16m gmin=17 +.PARAM RRf=497m Rrbond=11m Rtb=5.1 g2=948m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 2.47m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {363.94m+limit(Zthtype,0,1)*133.22m} +Rth4 t3 t4 {433.13m+limit(Zthtype,0,1)*244.28m} +Rth5 t4 Tcase {428.66m+limit(Zthtype,0,1)*241.75m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 951.044u +Cth4 t3 0 581.523u +Cth5 t4 0 25.044m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT BSC440N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=364u Rg=0.8 Rd=50u Rm=193u +.PARAM Inn=12 Unn=10 Rmax=44m gmin=8 + +.PARAM act=1.18 + + + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {27.81m+limit(Zthtype,0,1)*10.3m} +Rth2 t1 t2 {272.43m+limit(Zthtype,0,1)*100.82m} +Rth3 t2 t3 {851.77m+limit(Zthtype,0,1)*378.56m} +Rth4 t3 t4 {1.26+limit(Zthtype,0,1)*540.35m} +Rth5 t4 Tcase {530.47m+limit(Zthtype,0,1)*227.49m} +Cth1 Tj 0 16.428u +Cth2 t1 0 41.844u +Cth3 t2 0 430.125u +Cth4 t3 0 207.938u +Cth5 t4 0 184.647m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ440N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=1.06m Rg=0.8 Rd=50u Rm=641u +.PARAM Inn=12 Unn=10 Rmax=44m gmin=8 +.PARAM RRf=498m Rrbond=23m Rtb=7.4 g2=964m +.PARAM act=1.18 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {27.81m+limit(Zthtype,0,1)*10.3m} +Rth2 t1 t2 {272.43m+limit(Zthtype,0,1)*100.82m} +Rth3 t2 t3 {851.77m+limit(Zthtype,0,1)*378.56m} +Rth4 t3 t4 {1.26+limit(Zthtype,0,1)*540.35m} +Rth5 t4 Tcase {530.47m+limit(Zthtype,0,1)*227.49m} +Cth1 Tj 0 16.428u +Cth2 t1 0 41.844u +Cth3 t2 0 430.125u +Cth4 t3 0 207.938u +Cth5 t4 0 184.647m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT BSB056N10NN3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.05n Ld=0.7n Lg=0.1n + +.PARAM Rs=403u Rg=0.45 Rd=50u Rm=180u +.PARAM Inn=12 Unn=10 Rmax=5.6m gmin=23 +.PARAM RRf=-1k Rrbond=1u Rtb=58.7m g2=29m +.PARAM act=9.64 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 240.37u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.4m+limit(Zthtype,0,1)*1.26m} +Rth2 t1 t2 {36.64m+limit(Zthtype,0,1)*13.55m} +Rth3 t2 t3 {151.6m+limit(Zthtype,0,1)*53.68m} +Rth4 t3 t4 {183.65m+limit(Zthtype,0,1)*347.04m} +Rth5 t4 Tcase {280.02m+limit(Zthtype,0,1)*529.16m} +Cth1 Tj 0 134.21u +Cth2 t1 0 311.152u +Cth3 t2 0 2.957m +Cth4 t3 0 1.639m +Cth5 t4 0 68.973m +Cth6 Tcase 0 1m + +.ENDS + +********** + +.SUBCKT BSF134N10NJ3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.05n Ld=0.7n Lg=0.1n + +.PARAM Rs=300u Rg=0.55 Rd=250u Rm=102u +.PARAM Inn=12 Unn=10 Rmax=13.4m gmin=15 +.PARAM RRf=-966 Rrbond=1u Rtb=58.7m g2=32m +.PARAM act=3.8 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 240.37u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {8.64m+limit(Zthtype,0,1)*3.19m} +Rth2 t1 t2 {90.15m+limit(Zthtype,0,1)*33.36m} +Rth3 t2 t3 {347.78m+limit(Zthtype,0,1)*137.21m} +Rth4 t3 t4 {382.16m+limit(Zthtype,0,1)*722.55m} +Rth5 t4 Tcase {406.46m+limit(Zthtype,0,1)*768.5m} +Cth1 Tj 0 52.904u +Cth2 t1 0 126.45u +Cth3 t2 0 1.327m +Cth4 t3 0 669.632u +Cth5 t4 0 25.335m +Cth6 Tcase 0 1m + +.ENDS + +********** + +.SUBCKT IPT020N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=226u Rg=1.9 Rd=20u Rm=88u +.PARAM Inn=150 Unn=10 Rmax=2m gmin=108 +.PARAM RRf=500m Rrbond=3m Rtb=2.6 g2=999m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s2_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {32.15m+limit(Zthtype,0,1)*7.97m} +Rth4 t3 t4 {52.4m+limit(Zthtype,0,1)*47.4m} +Rth5 t4 Tcase {126.17m+limit(Zthtype,0,1)*114.14m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 3.927m +Cth4 t3 0 4.807m +Cth5 t4 0 177.355m +Cth6 Tcase 0 30m + +.ENDS + +********** + + +.SUBCKT BSZ150N10LS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=577u Rg=1.3 Rd=50u Rm=281u +.PARAM Inn=20 Unn=10 Rmax=15m gmin=17 +.PARAM RRf=497m Rrbond=11m Rtb=5.1 g2=948m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_t_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 2.47m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {363.94m+limit(Zthtype,0,1)*133.22m} +Rth4 t3 t4 {433.13m+limit(Zthtype,0,1)*244.28m} +Rth5 t4 Tcase {428.66m+limit(Zthtype,0,1)*241.75m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 951.044u +Cth4 t3 0 581.523u +Cth5 t4 0 25.044m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT IPB025N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=4n + +.PARAM Rs=393u Rg=1.9 Rd=20u Rm=126u +.PARAM Inn=100 Unn=10 Rmax=2.5m gmin=104 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA030N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=657u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=79 Unn=10 Rmax=3m gmin=89 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB027N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=657u Rg=1.9 Rd=50u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=2.7m gmin=99 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI030N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=697u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=98 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP030N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=697u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=98 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB039N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=4n + +.PARAM Rs=445u Rg=1.4 Rd=20u Rm=141u +.PARAM Inn=100 Unn=10 Rmax=3.9m gmin=80 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA045N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=64 Unn=10 Rmax=4.5m gmin=62 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB042N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=50u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.2m gmin=76 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI045N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.5m gmin=76 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP045N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.5m gmin=76 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB065N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=50u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=6.5m gmin=52 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD068N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=824u Rg=1.6 Rd=50u Rm=345u +.PARAM Inn=90 Unn=10 Rmax=6.8m gmin=56 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI072N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=350u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=7.2m gmin=52 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP072N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=350u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=7.2m gmin=52 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC046N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=172u Rg=1.9 Rd=1u Rm=1u +.PARAM Inn=50 Unn=10 Rmax=4.6m gmin=51 +.PARAM act=11.15 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC060N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=404u Rg=1.6 Rd=50u Rm=233u +.PARAM Inn=50 Unn=10 Rmax=6m gmin=45 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC070N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=334u Rg=1.9 Rd=50u Rm=163u +.PARAM Inn=50 Unn=10 Rmax=7m gmin=41 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC109N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=254u Rg=1.1 Rd=50u Rm=83u +.PARAM Inn=46 Unn=10 Rmax=10.9m gmin=31 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA086N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=45 Unn=10 Rmax=8.6m gmin=36 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB083N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=50u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.3m gmin=45 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD082N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=932u Rg=1.9 Rd=50u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.2m gmin=46 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI086N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP086N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP881N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA126N10NM3S_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=35 Unn=10 Rmax=12.6m gmin=26 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB123N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=50u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.3m gmin=30 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD122N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=729u Rg=2 Rd=50u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.2m gmin=30 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI126N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.6m gmin=30 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP126N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.6m gmin=30 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA180N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=28 Unn=10 Rmax=18m gmin=20 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD180N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=1.24m Rg=2 Rd=50u Rm=481u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=22 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI180N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP180N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP882N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC160N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=603u Rg=2 Rd=50u Rm=411u +.PARAM Inn=33 Unn=10 Rmax=16m gmin=22 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ160N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=577u Rg=2 Rd=50u Rm=281u +.PARAM Inn=20 Unn=10 Rmax=16m gmin=17 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC440N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=364u Rg=0.8 Rd=50u Rm=193u +.PARAM Inn=12 Unn=10 Rmax=44m gmin=8 +.PARAM act=1.18 + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ440N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=1.06m Rg=0.8 Rd=50u Rm=641u +.PARAM Inn=12 Unn=10 Rmax=44m gmin=8 +.PARAM act=1.18 + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSB056N10NN3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.05n Ld=0.7n Lg=0.1n + +.PARAM Rs=403u Rg=0.45 Rd=50u Rm=180u +.PARAM Inn=12 Unn=10 Rmax=5.6m gmin=23 +.PARAM act=9.64 + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSF134N10NJ3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.05n Ld=0.7n Lg=0.1n + +.PARAM Rs=300u Rg=0.55 Rd=250u Rm=102u +.PARAM Inn=12 Unn=10 Rmax=13.4m gmin=15 +.PARAM act=3.8 + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPT020N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=226u Rg=1.9 Rd=20u Rm=88u +.PARAM Inn=150 Unn=10 Rmax=2m gmin=108 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s2_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ150N10LS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=577u Rg=1.3 Rd=50u Rm=281u +.PARAM Inn=20 Unn=10 Rmax=15m gmin=17 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_t_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB025N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 393u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.3m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPB025N10N3_L0 + +****** + +.SUBCKT IPA030N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 657u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.63m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPA030N10N3_L0 + +****** + +.SUBCKT IPB027N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 657u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.33m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPB027N10N3_L0 + +****** + +.SUBCKT IPI030N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 697u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.63m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPI030N10N3_L0 + +****** + +.SUBCKT IPP030N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 697u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.63m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPP030N10N3_L0 + +****** + +.SUBCKT IPB039N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 445u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.28m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPB039N10N3_L0 + +****** + +.SUBCKT IPA045N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 748u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.61m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPA045N10N3_L0 + +****** + +.SUBCKT IPB042N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 748u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.31m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPB042N10N3_L0 + +****** + +.SUBCKT IPI045N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 748u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.61m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPI045N10N3_L0 + +****** + +.SUBCKT IPP045N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 748u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.61m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPP045N10N3_L0 + +****** + +.SUBCKT IPB065N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 1.04m + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.91m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS IPB065N10N3_L0 + +****** + +.SUBCKT IPD068N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 824u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.91m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS IPD068N10N3_L0 + +****** + +.SUBCKT IPI072N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.04m + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.21m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS IPI072N10N3_L0 + +****** + +.SUBCKT IPP072N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.04m + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.21m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS IPP072N10N3_L0 + +****** + +.SUBCKT BSC046N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 172u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 191.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.14m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=3.57n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=211.9p N=1.19 RS=0.04u EG=1.12 TT=60n) +Rdiode d1 21 0.57m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.18n +.MODEL DGD D(M=0.7 CJO=1.18n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.52n + +.ENDS BSC046N10NS3_L0 + +****** + +.SUBCKT BSC060N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 404u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.91m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS BSC060N10NS3_L0 + +****** + +.SUBCKT BSC070N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 334u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.82m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS BSC070N10NS3_L0 + +****** + +.SUBCKT BSC109N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 254u + +Rg g1 g2 1.1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS BSC109N10NS3_L0 + +****** + +.SUBCKT IPA086N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 5.12m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPA086N10N3_L0 + +****** + +.SUBCKT IPB083N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.82m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPB083N10N3_L0 + +****** + +.SUBCKT IPD082N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 932u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.82m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPD082N10N3_L0 + +****** + +.SUBCKT IPI086N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 5.12m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPI086N10N3_L0 + +****** + +.SUBCKT IPP086N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 5.12m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPP086N10N3_L0 + +****** + +.SUBCKT IPP881N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 5.12m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPP881N10N3_L0 + +****** + +.SUBCKT IPA126N10NM3S_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 947u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPA126N10NM3S_L0 + +****** + +.SUBCKT IPB123N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 947u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPB123N10N3_L0 + +****** + +.SUBCKT IPD122N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 729u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPD122N10N3_L0 + +****** + +.SUBCKT IPI126N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 947u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPI126N10N3_L0 + +****** + +.SUBCKT IPP126N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 947u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPP126N10N3_L0 + +****** + +.SUBCKT IPA180N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2.5n +Rs s1 s2 1.74m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPA180N10N3_L0 + +****** + +.SUBCKT IPD180N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 1.24m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPD180N10N3_L0 + +****** + +.SUBCKT IPI180N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2.5n +Rs s1 s2 1.74m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPI180N10N3_L0 + +****** + +.SUBCKT IPP180N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2.5n +Rs s1 s2 1.74m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPP180N10N3_L0 + +****** + +.SUBCKT IPP882N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2.5n +Rs s1 s2 1.74m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPP882N10N3_L0 + +****** + +.SUBCKT BSC160N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 603u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS BSC160N10NS3_L0 + +****** + +.SUBCKT BSZ160N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 577u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS BSZ160N10NS3_L0 + +****** + + +.SUBCKT BSC440N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 364u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 20.3 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 29.71m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=0.49n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=22.4p N=1.19 RS=0.42u EG=1.12 TT=60n) +Rdiode d1 21 5.34m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.13n +.MODEL DGD D(M=0.7 CJO=0.13n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.6n + +.ENDS BSC440N10NS3_L0 + +****** + +.SUBCKT BSZ440N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 1.06m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 20.3 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 29.71m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=0.49n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=22.4p N=1.19 RS=0.42u EG=1.12 TT=60n) +Rdiode d1 21 5.34m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.13n +.MODEL DGD D(M=0.7 CJO=0.13n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.6n + +.ENDS BSZ440N10NS3_L0 + +****** + +.SUBCKT BSB056N10NN3_L0 drain gate source + +Lg gate g1 0.1n +Ld drain d1 0.7n +Ls source s1 0.05n +Rs s1 s2 403u + +Rg g1 g2 0.45 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 165.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.68m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=3.4n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=183.2p N=1.19 RS=0.05u EG=1.12 TT=60n) +Rdiode d1 21 0.65m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.02n +.MODEL DGD D(M=0.7 CJO=1.02n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.03n + +.ENDS BSB056N10NN3_L0 + +****** + +.SUBCKT BSF134N10NJ3_L0 drain gate source + +Lg gate g1 0.1n +Ld drain d1 0.7n +Ls source s1 0.05n +Rs s1 s2 300u + +Rg g1 g2 0.55 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 65.4 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 9.46m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.41n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=72.2p N=1.19 RS=0.13u EG=1.12 TT=60n) +Rdiode d1 21 1.66m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.7 CJO=0.4n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.66n + +.ENDS BSF134N10NJ3_L0 + +****** + +.SUBCKT IPT020N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 2n +Ls source s1 1.5n +Rs s1 s2 226u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.18m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=9.25n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.17n + +.ENDS IPT020N10N3_L0 + +****** + +.SUBCKT BSZ150N10LS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 577u + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 77.6 VTO=2.31 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.5m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.24n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.45n +.MODEL DGD D(M=0.7 CJO=0.45n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.9n + +.ENDS BSZ150N10LS3_L0 + +****** diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_BSC_BSZ_BSB_BSF_L0.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_BSC_BSZ_BSB_BSF_L0.slb new file mode 100755 index 0000000..f1ddeb7 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_BSC_BSZ_BSB_BSF_L0.slb @@ -0,0 +1,170 @@ +*version 9.1 201173875 +@index +symloc DMOS 0 1038 b +symloc BSC060N10NS3_L0:DMOS 1038 295 +symloc BSC160N10NS3_L0:DMOS 1333 295 +symloc BSZ160N10NS3_L0:DMOS 1628 295 +symloc BSC440N10NS3_L0:DMOS 1923 295 +symloc BSZ440N10NS3_L0:DMOS 2218 295 +symloc BSC046N10NS3_L0:DMOS 2513 295 +symloc BSC070N10NS3_L0:DMOS 2808 295 +symloc BSC109N10NS3_L0:DMOS 3103 295 +symloc BSB056N10NN3_L0:DMOS 3398 295 +symloc BSF134N10NJ3_L0:DMOS 3693 295 +symloc BSZ150N10LS3_L0:DMOS 3988 295 +*symbol DMOS b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol BSC060N10NS3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC060N10NS3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC060N10NS3_L0 +*symbol BSC160N10NS3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC160N10NS3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC160N10NS3_L0 +*symbol BSZ160N10NS3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSZ160N10NS3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSZ160N10NS3_L0 +*symbol BSC440N10NS3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC440N10NS3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC440N10NS3_L0 +*symbol BSZ440N10NS3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSZ440N10NS3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSZ440N10NS3_L0 +*symbol BSC046N10NS3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC046N10NS3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC046N10NS3_L0 +*symbol BSC070N10NS3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC070N10NS3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC070N10NS3_L0 +*symbol BSC109N10NS3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC109N10NS3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC109N10NS3_L0 +*symbol BSB056N10NN3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSB056N10NN3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSB056N10NN3_L0 +*symbol BSF134N10NJ3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSF134N10NJ3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSF134N10NJ3_L0 +*symbol BSZ150N10LS3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSZ150N10LS3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSZ150N10LS3_L0 diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_BSC_BSZ_BSB_BSF_L1.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_BSC_BSZ_BSB_BSF_L1.slb new file mode 100755 index 0000000..17dba9e --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_BSC_BSZ_BSB_BSF_L1.slb @@ -0,0 +1,254 @@ +*version 9.1 1224434252 +@index +symloc DMOS_S2_L1_n 0 1402 b +symloc BSC060N10NS3_L1:DMOS_S2_L1_n 1402 632 +symloc BSC160N10NS3_L1:DMOS_S2_L1_n 2034 632 +symloc BSZ160N10NS3_L1:DMOS_S2_L1_n 2666 632 +symloc BSC440N10NS3_L1:DMOS_S2_L1_n 3298 632 +symloc BSZ440N10NS3_L1:DMOS_S2_L1_n 3930 632 +symloc BSC046N10NS3_L1:DMOS_S2_L1_n 4562 632 +symloc BSC070N10NS3_L1:DMOS_S2_L1_n 5194 632 +symloc BSC109N10NS3_L1:DMOS_S2_L1_n 5826 632 +symloc BSB056N10NN3_L1:DMOS_S2_L1_n 6458 639 +symloc BSF134N10NJ3_L1:DMOS_S2_L1_n 7097 639 +symloc BSZ150N10LS3_L1:DMOS_S2_L1_n 7736 632 +*symbol DMOS_S2_L1_n b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1_n +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS_S2_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hcn 100 Ls=1n +a 0 u 0:13 0 0 20 hcn 100 Ld=0.5n +a 0 u 0:13 0 0 30 hcn 100 Lg=2n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol BSC060N10NS3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC060N10NS3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC060N10NS3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC160N10NS3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC160N10NS3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC160N10NS3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSZ160N10NS3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSZ160N10NS3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSZ160N10NS3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC440N10NS3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC440N10NS3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC440N10NS3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSZ440N10NS3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSZ440N10NS3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSZ440N10NS3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC046N10NS3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC046N10NS3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC046N10NS3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC070N10NS3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC070N10NS3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC070N10NS3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC109N10NS3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC109N10NS3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC109N10NS3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSB056N10NN3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSB056N10NN3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSB056N10NN3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.05n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.7n +a 0 u 0:13 0 0 30 hlb 100 Lg=0.1n +*symbol BSF134N10NJ3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSF134N10NJ3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSF134N10NJ3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.05n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.7n +a 0 u 0:13 0 0 30 hlb 100 Lg=0.1n +*symbol BSZ150N10LS3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSZ150N10LS3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSZ150N10LS3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_BSC_BSZ_BSB_BSF_L3.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_BSC_BSZ_BSB_BSF_L3.slb new file mode 100755 index 0000000..89d049e --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_BSC_BSZ_BSB_BSF_L3.slb @@ -0,0 +1,277 @@ +*version 9.1 69128771 +@index +symloc DMOS_S2_L3_n 0 1796 b +symloc BSC060N10NS3:DMOS_S2_L3_n 1796 697 +symloc BSC160N10NS3:DMOS_S2_L3_n 2493 697 +symloc BSZ160N10NS3:DMOS_S2_L3_n 3190 697 +symloc BSC440N10NS3:DMOS_S2_L3_n 3887 697 +symloc BSZ440N10NS3:DMOS_S2_L3_n 4584 697 +symloc BSC046N10NS3:DMOS_S2_L3_n 5281 697 +symloc BSC070N10NS3:DMOS_S2_L3_n 5978 697 +symloc BSC109N10NS3:DMOS_S2_L3_n 6675 697 +symloc BSB056N10NN3:DMOS_S2_L3_n 7372 704 +symloc BSF134N10NJ3:DMOS_S2_L3_n 8076 704 +symloc BSZ150N10LS3:DMOS_S2_L3_n 8780 697 +*symbol DMOS_S2_L3_n b +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tcase n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 30 20 +20 20 +; +v 0 10 20 +15 20 +; +v 0 15 10 +15 30 +; +v 0 30 20 +30 30 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +v 0 20 23 +20 17 +; +v 0 38 10 +30 10 +; +v 0 30 30 +38 30 +38 10 +; +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 5 d_info:,,,,,,,,,,,,,5, +Tcase +*symbol BSC060N10NS3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC060N10NS3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC060N10NS3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC160N10NS3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC160N10NS3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC160N10NS3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSZ160N10NS3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSZ160N10NS3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSZ160N10NS3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC440N10NS3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC440N10NS3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC440N10NS3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSZ440N10NS3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSZ440N10NS3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSZ440N10NS3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC046N10NS3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC046N10NS3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC046N10NS3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC070N10NS3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC070N10NS3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC070N10NS3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC109N10NS3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC109N10NS3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC109N10NS3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSB056N10NN3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSB056N10NN3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSB056N10NN3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.05n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.7n +a 0 u 0:13 0 0 30 hlb 100 Lg=0.1n +*symbol BSF134N10NJ3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSF134N10NJ3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSF134N10NJ3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.05n +a 0 u 0:13 0 0 20 hlb 100 Ld=0.7n +a 0 u 0:13 0 0 30 hlb 100 Lg=0.1n +*symbol BSZ150N10LS3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSZ150N10LS3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSZ150N10LS3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPA_IPD_IPI_L0.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPA_IPD_IPI_L0.slb new file mode 100755 index 0000000..a06ccc5 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPA_IPD_IPI_L0.slb @@ -0,0 +1,206 @@ +*version 9.1 936856936 +@index +symloc DMOS 0 1038 b +symloc IPA030N10N3_L0:DMOS 1038 292 +symloc IPI030N10N3_L0:DMOS 1330 292 +symloc IPA045N10N3_L0:DMOS 1622 292 +symloc IPI045N10N3_L0:DMOS 1914 292 +symloc IPD068N10N3_L0:DMOS 2206 292 +symloc IPI072N10N3_L0:DMOS 2498 292 +symloc IPA086N10N3_L0:DMOS 2790 292 +symloc IPD082N10N3_L0:DMOS 3082 292 +symloc IPI086N10N3_L0:DMOS 3374 292 +symloc IPA126N10N3_L0:DMOS 3666 292 +symloc IPD122N10N3_L0:DMOS 3958 292 +symloc IPI126N10N3_L0:DMOS 4250 292 +symloc IPA180N10N3_L0:DMOS 4542 292 +symloc IPD180N10N3_L0:DMOS 4834 292 +symloc IPI180N10N3_L0:DMOS 5126 292 +*symbol DMOS b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPA030N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPA030N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA030N10N3_L0 +*symbol IPI030N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPI030N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI030N10N3_L0 +*symbol IPA045N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPA045N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA045N10N3_L0 +*symbol IPI045N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPI045N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI045N10N3_L0 +*symbol IPD068N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD068N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD068N10N3_L0 +*symbol IPI072N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPI072N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI072N10N3_L0 +*symbol IPA086N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPA086N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA086N10N3_L0 +*symbol IPD082N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD082N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD082N10N3_L0 +*symbol IPI086N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPI086N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI086N10N3_L0 +*symbol IPA126N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPA126N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA126N10N3_L0 +*symbol IPD122N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD122N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD122N10N3_L0 +*symbol IPI126N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPI126N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI126N10N3_L0 +*symbol IPA180N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPA180N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA180N10N3_L0 +*symbol IPD180N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPD180N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD180N10N3_L0 +*symbol IPI180N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPI180N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI180N10N3_L0 diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPA_IPD_IPI_L1.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPA_IPD_IPI_L1.slb new file mode 100755 index 0000000..5fe47ab --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPA_IPD_IPI_L1.slb @@ -0,0 +1,318 @@ +*version 9.1 203997478 +@index +symloc DMOS_S2_L1_n 0 1402 b +symloc IPA030N10N3_L1:DMOS_S2_L1_n 1402 633 +symloc IPI030N10N3_L1:DMOS_S2_L1_n 2035 633 +symloc IPA045N10N3_L1:DMOS_S2_L1_n 2668 633 +symloc IPI045N10N3_L1:DMOS_S2_L1_n 3301 633 +symloc IPD068N10N3_L1:DMOS_S2_L1_n 3934 631 +symloc IPI072N10N3_L1:DMOS_S2_L1_n 4565 631 +symloc IPA086N10N3_L1:DMOS_S2_L1_n 5196 631 +symloc IPD082N10N3_L1:DMOS_S2_L1_n 5827 631 +symloc IPI086N10N3_L1:DMOS_S2_L1_n 6458 631 +symloc IPA126N10N3_L1:DMOS_S2_L1_n 7089 631 +symloc IPD122N10N3_L1:DMOS_S2_L1_n 7720 631 +symloc IPI126N10N3_L1:DMOS_S2_L1_n 8351 631 +symloc IPA180N10N3_L1:DMOS_S2_L1_n 8982 633 +symloc IPD180N10N3_L1:DMOS_S2_L1_n 9615 629 +symloc IPI180N10N3_L1:DMOS_S2_L1_n 10244 633 +*symbol DMOS_S2_L1_n b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1_n +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS_S2_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hcn 100 Ls=1n +a 0 u 0:13 0 0 20 hcn 100 Ld=0.5n +a 0 u 0:13 0 0 30 hcn 100 Lg=2n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPA030N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPA030N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA030N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPI030N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPI030N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI030N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA045N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPA045N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA045N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPI045N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPI045N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI045N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPD068N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD068N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD068N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPI072N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPI072N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI072N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA086N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPA086N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA086N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPD082N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD082N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD082N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPI086N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPI086N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI086N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA126N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPA126N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA126N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPD122N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD122N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD122N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPI126N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPI126N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI126N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA180N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPA180N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA180N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPD180N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPD180N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPD180N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPI180N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPI180N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPI180N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPA_IPD_IPI_L3.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPA_IPD_IPI_L3.slb new file mode 100755 index 0000000..6f19726 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPA_IPD_IPI_L3.slb @@ -0,0 +1,345 @@ +*version 9.1 1960152540 +@index +symloc DMOS_S2_L3_n 0 1796 b +symloc IPA030N10N3:DMOS_S2_L3_n 1796 698 +symloc IPI030N10N3:DMOS_S2_L3_n 2494 698 +symloc IPA045N10N3:DMOS_S2_L3_n 3192 698 +symloc IPI045N10N3:DMOS_S2_L3_n 3890 698 +symloc IPD068N10N3:DMOS_S2_L3_n 4588 696 +symloc IPI072N10N3:DMOS_S2_L3_n 5284 696 +symloc IPA086N10N3:DMOS_S2_L3_n 5980 696 +symloc IPD082N10N3:DMOS_S2_L3_n 6676 696 +symloc IPI086N10N3:DMOS_S2_L3_n 7372 696 +symloc IPA126N10N3:DMOS_S2_L3_n 8068 696 +symloc IPD122N10N3:DMOS_S2_L3_n 8764 696 +symloc IPI126N10N3:DMOS_S2_L3_n 9460 696 +symloc IPA180N10N3:DMOS_S2_L3_n 10156 698 +symloc IPD180N10N3:DMOS_S2_L3_n 10854 694 +symloc IPI180N10N3:DMOS_S2_L3_n 11548 698 +*symbol DMOS_S2_L3_n b +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tcase n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 30 20 +20 20 +; +v 0 10 20 +15 20 +; +v 0 15 10 +15 30 +; +v 0 30 20 +30 30 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +v 0 20 23 +20 17 +; +v 0 38 10 +30 10 +; +v 0 30 30 +38 30 +38 10 +; +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 5 d_info:,,,,,,,,,,,,,5, +Tcase +*symbol IPA030N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPA030N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPA030N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPI030N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPI030N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPI030N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA045N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPA045N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPA045N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPI045N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPI045N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPI045N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPD068N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD068N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD068N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPI072N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPI072N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPI072N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA086N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPA086N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPA086N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPD082N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD082N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD082N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPI086N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPI086N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPI086N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA126N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPA126N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPA126N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPD122N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD122N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD122N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPI126N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPI126N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPI126N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA180N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPA180N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPA180N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPD180N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPD180N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPD180N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPI180N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPI180N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPI180N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPB_IPP_IPT_L0.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPB_IPP_IPT_L0.slb new file mode 100755 index 0000000..658afce --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPB_IPP_IPT_L0.slb @@ -0,0 +1,215 @@ +*version 9.1 239145096 +@index +symloc DMOS 0 1038 b +symloc IPB025N10N3_L0:DMOS 1038 292 +symloc IPB027N10N3_L0:DMOS 1330 292 +symloc IPP030N10N3_L0:DMOS 1622 292 +symloc IPB039N10N3_L0:DMOS 1914 292 +symloc IPB042N10N3_L0:DMOS 2206 292 +symloc IPP045N10N3_L0:DMOS 2498 292 +symloc IPP072N10N3_L0:DMOS 2790 292 +symloc IPB083N10N3_L0:DMOS 3082 292 +symloc IPP086N10N3_L0:DMOS 3374 292 +symloc IPP881N10N3_L0:DMOS 3666 292 +symloc IPB123N10N3_L0:DMOS 3958 292 +symloc IPP126N10N3_L0:DMOS 4250 292 +symloc IPP180N10N3_L0:DMOS 4542 292 +symloc IPP882N10N3_L0:DMOS 4834 292 +symloc IPT020N10N3_L0:DMOS 5126 292 +symloc IPB065N10N3_L0:DMOS 5418 292 +*symbol DMOS b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPB025N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB025N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB025N10N3_L0 +*symbol IPB027N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB027N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB027N10N3_L0 +*symbol IPP030N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP030N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP030N10N3_L0 +*symbol IPB039N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB039N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB039N10N3_L0 +*symbol IPB042N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB042N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB042N10N3_L0 +*symbol IPP045N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP045N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP045N10N3_L0 +*symbol IPP072N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP072N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP072N10N3_L0 +*symbol IPB083N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB083N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB083N10N3_L0 +*symbol IPP086N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP086N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP086N10N3_L0 +*symbol IPP881N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP881N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP881N10N3_L0 +*symbol IPB123N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB123N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB123N10N3_L0 +*symbol IPP126N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP126N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP126N10N3_L0 +*symbol IPP180N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP180N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP180N10N3_L0 +*symbol IPP882N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP882N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP882N10N3_L0 +*symbol IPT020N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPT020N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPT020N10N3_L0 +*symbol IPB065N10N3_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB065N10N3_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB065N10N3_L0 diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPB_IPP_IPT_L1.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPB_IPP_IPT_L1.slb new file mode 100755 index 0000000..a1cdd53 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPB_IPP_IPT_L1.slb @@ -0,0 +1,334 @@ +*version 9.1 6397678 +@index +symloc DMOS_S2_L1_n 0 1402 b +symloc IPB025N10N3_L1:DMOS_S2_L1_n 1402 631 +symloc IPB027N10N3_L1:DMOS_S2_L1_n 2033 631 +symloc IPP030N10N3_L1:DMOS_S2_L1_n 2664 633 +symloc IPB039N10N3_L1:DMOS_S2_L1_n 3297 631 +symloc IPB042N10N3_L1:DMOS_S2_L1_n 3928 631 +symloc IPP045N10N3_L1:DMOS_S2_L1_n 4559 633 +symloc IPP072N10N3_L1:DMOS_S2_L1_n 5192 631 +symloc IPB083N10N3_L1:DMOS_S2_L1_n 5823 629 +symloc IPP086N10N3_L1:DMOS_S2_L1_n 6452 631 +symloc IPP881N10N3_L1:DMOS_S2_L1_n 7083 631 +symloc IPB123N10N3_L1:DMOS_S2_L1_n 7714 629 +symloc IPP126N10N3_L1:DMOS_S2_L1_n 8343 631 +symloc IPP180N10N3_L1:DMOS_S2_L1_n 8974 633 +symloc IPP882N10N3_L1:DMOS_S2_L1_n 9607 633 +symloc IPT020N10N3_L1:DMOS_S2_L1_n 10240 631 +symloc IPB065N10N3_L1:DMOS_S2_L1_n 10871 629 +*symbol DMOS_S2_L1_n b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1_n +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS_S2_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hcn 100 Ls=1n +a 0 u 0:13 0 0 20 hcn 100 Ld=0.5n +a 0 u 0:13 0 0 30 hcn 100 Lg=2n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol IPB025N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB025N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB025N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB027N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB027N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB027N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP030N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP030N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP030N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB039N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB039N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB039N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB042N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB042N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB042N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP045N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP045N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP045N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP072N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP072N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP072N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB083N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB083N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB083N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP086N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP086N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP086N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP881N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP881N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP881N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB123N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB123N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB123N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP126N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP126N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP126N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP180N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP180N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP180N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP882N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP882N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP882N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPT020N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPT020N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPT020N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB065N10N3_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB065N10N3_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB065N10N3_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPB_IPP_IPT_L3.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPB_IPP_IPT_L3.slb new file mode 100755 index 0000000..f06ac36 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_IPB_IPP_IPT_L3.slb @@ -0,0 +1,362 @@ +*version 9.1 733104234 +@index +symloc DMOS_S2_L3_n 0 1796 b +symloc IPB025N10N3:DMOS_S2_L3_n 1796 696 +symloc IPB027N10N3:DMOS_S2_L3_n 2492 696 +symloc IPP030N10N3:DMOS_S2_L3_n 3188 698 +symloc IPB039N10N3:DMOS_S2_L3_n 3886 696 +symloc IPB042N10N3:DMOS_S2_L3_n 4582 696 +symloc IPP045N10N3:DMOS_S2_L3_n 5278 698 +symloc IPP072N10N3:DMOS_S2_L3_n 5976 696 +symloc IPB083N10N3:DMOS_S2_L3_n 6672 694 +symloc IPP086N10N3:DMOS_S2_L3_n 7366 696 +symloc IPP881N10N3:DMOS_S2_L3_n 8062 696 +symloc IPB123N10N3:DMOS_S2_L3_n 8758 694 +symloc IPP126N10N3:DMOS_S2_L3_n 9452 696 +symloc IPP180N10N3:DMOS_S2_L3_n 10148 698 +symloc IPP882N10N3:DMOS_S2_L3_n 10846 698 +symloc IPT020N10N3:DMOS_S2_L3_n 11544 696 +symloc IPB065N10N3:DMOS_S2_L3_n 12240 694 +*symbol DMOS_S2_L3_n b +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tcase n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 30 20 +20 20 +; +v 0 10 20 +15 20 +; +v 0 15 10 +15 30 +; +v 0 30 20 +30 30 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +v 0 20 23 +20 17 +; +v 0 38 10 +30 10 +; +v 0 30 30 +38 30 +38 10 +; +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 5 d_info:,,,,,,,,,,,,,5, +Tcase +*symbol IPB025N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB025N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB025N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB027N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB027N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB027N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP030N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP030N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP030N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB039N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB039N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB039N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB042N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB042N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB042N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP045N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP045N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP045N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP072N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP072N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP072N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB083N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB083N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB083N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP086N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP086N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP086N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP881N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP881N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP881N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB123N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB123N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB123N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP126N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP126N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP126N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP180N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP180N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP180N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP882N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP882N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP882N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPT020N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPT020N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPT020N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB065N10N3 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB065N10N3 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB065N10N3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_LTSpice.lib b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_LTSpice.lib new file mode 100755 index 0000000..70a76d4 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS3/OptiMOS3_100V_LTSpice.lib @@ -0,0 +1,4549 @@ +***************************************************************** +* INFINEON Power Transistors * +* Level1/3 LTSPICE Library for OptiMOS3 n-Channel Transistors * +* * +* This file also contains simplified models that are compatible * +* to standard Spice (Level 0) * +* * +* Version 150520 * +* * +***************************************************************** +***************************************************************** +* * +* The Simulation Model is subject to change without notice. In * +* addition, models can be a useful tool in evaluating device * +* performance, they cannot reflect the accurate device * +* performance under all conditions, nor are they intended to * +* replace bread boarding for final verification. Infineon * +* therefore does not assume any warranty or liability * +* whatsoever arising from their use. Infineon does not assume * +* any warranty or liability for the values and functions of the * +* Simulation Model. * +* The methods and results of the Simulation Model are to the * +* best of our knowledge * +* correct. However, the user is fully responsible to verify and * +* validate these results under the operating conditions and in * +* the environment of its application. Infineon will not bear * +* the responsibility arising out of or in connection with any * +* malfunction of the Simulation Models. * +* Models provided by Infineon are not warranted by Infineon as * +* completely and comprehensively representing all the * +* specifications and operating characteristics of the * +* semiconductor products to which these models relate. The * +* models describe the characteristics of typical devices. In * +* all cases, the current data sheet information for a given * +* device is the conclusive design guideline and the only actual * +* performance specification. * +* * +* This library contains models of the following INFINEON * +* OptiMOS3 transistors: * +* * +* 100V NL * +* IPB025N10N3 IPB027N10N3 IPB039N10N3 * +* IPB042N10N3 IPB083N10N3 IPB123N10N3 * +* IPP030N10N3 IPP045N10N3 IPP072N10N3 * +* IPP086N10N3 IPP881N10N3 IPP126N10N3 * +* IPP180N10N3 IPP882N10N3 IPA030N10N3 * +* IPA045N10N3 IPA086N10N3 IPA126N10NM3S * +* IPA180N10N3 IPI030N10N3 IPI045N10N3 * +* IPI072N10N3 IPI086N10N3 IPI126N10N3 * +* IPI180N10N3 IPD068N10N3 IPD082N10N3 * +* IPD122N10N3 IPD180N10N3 BSC046N10NS3 * +* BSC060N10NS3 BSC070N10NS3 BSC109N10NS3 * +* BSC160N10NS3 BSC440N10NS3 BSZ160N10NS3 * +* BSZ440N10NS3 BSB056N10NN3 BSF134N10NJ3 * +* IPT020N10N3 IPB065N10N3 * +* * +* 100V LL * +* BSZ150N10LS3 * +* * +***************************************************************** +* thermal nodes of level 3 models: * +* * +* .SUBCKT IPB042N10N3 drain gate source Tj Tcase * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Tcase : node where the boundary contition - external heat * +* sinks etc - have to be connected (ideal heat sink * +* can be modeled by using a voltage source stating the * +* ambient temperature in °C between Tcase and ground. * +* * +***************************************************************** + +.options Thev_Induc=1 + +.SUBCKT S3_100_s_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.15 Fn=0.5 kbq=85.8u +.PARAM c=1.402 muc=0.0 Vth0=3.63 auth=4.244m al=0.5 +.PARAM UT=100m ab=56m ab2=0 lB=-23 UB=110 + +.PARAM b0=27.6 p0=5.816 p1=-15.2m p2=27u + +.PARAM Rd=37.52m nmu=3 Tref=298 T0=273 lnIsj=-24.877 +.PARAM ndi=1.188 Rdi=6.3m nmu2=0 ta=40n td=100n +.PARAM Rf=0.48 nmu3=1.55 rpa=0 + +.PARAM f3=405p f3a=0p +.PARAM ps1=35p ps2=-66.7m ps3=70p ps4=-2 ps5=1.18p ps6=3.14p +.PARAM qs1=35p qs2=54p qs3=-1 qs4=230p qs5=-0.0385 + +.PARAM Vmin=2.93 Vmax=4.43 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**1)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + + +.SUBCKT S3_100_s1_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.15 Fn=0.5 kbq=85.8u +.PARAM c=1.402 muc=0.0 Vth0=3.63 auth=4.244m al=0.5 +.PARAM UT=100m ab=56m ab2=0 lB=-23 UB=110 + +.PARAM b0=27.6 p0=5.816 p1=-15.2m p2=27u + +.PARAM Rd=37.52m nmu=3 Tref=298 T0=273 lnIsj=-24.877 +.PARAM ndi=1.188 Rdi=6.3m nmu2=0 ta=40n td=100n +.PARAM Rf=0.48 nmu3=1.55 rpa=0 + +.PARAM f3=405p f3a=125p +.PARAM ps1=35p ps2=-66.7m ps3=70p ps4=-2 ps5=1.18p ps6=3.14p + +.PARAM qs1=35p qs2=160p qs3=-0.0333 qs4=54p qs5=-1 f2r=1 + +.PARAM Vmin=2.93 Vmax=4.43 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*(1+f2r/SQRT(a))*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**1)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT S3_100_s2_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.15 Fn=0.5 kbq=85.8u +.PARAM c=1.402 muc=0.0 Vth0=3.63 auth=4.244m al=0.5 +.PARAM UT=100m ab=56m ab2=0 lB=-23 UB=110 + +.PARAM b0=27.6 p0=5.816 p1=-15.2m p2=27u + +.PARAM Rd=34.22m nmu=3 Tref=298 T0=273 lnIsj=-24.877 +.PARAM ndi=1.188 Rdi=6.3m nmu2=0 ta=40n td=100n +.PARAM Rf=0.48 nmu3=1.55 rpa=0 + +.PARAM f3=405p f3a=125p +.PARAM ps1=35p ps2=-66.7m ps3=70p ps4=-2 ps5=1.18p ps6=3.14p + +.PARAM qs1=35p qs2=160p qs3=-0.0333 qs4=54p qs5=-1 f2r=1 + +.PARAM Vmin=2.93 Vmax=4.43 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*(1+f2r/SQRT(a))*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**1)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + + +.SUBCKT S3_100_t_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.15 Fn=0.5 kbq=85.8u +.PARAM c=1.2 muc=0.0 Vth0=2.31 auth=3.265m al=0.5 +.PARAM UT=100m ab=56m ab2=0 lB=-23 UB=110 + +.PARAM b0=37.674 p0=4.474 p1=-11.7m p2=20.8u + +.PARAM Rd=35m nmu=3 Tref=298 T0=273 lnIsj=-24.877 +.PARAM ndi=1.188 Rdi=6.3m nmu2=0 ta=40n td=100n +.PARAM Rf=0.48 nmu3=1.55 rpa=0 + +.PARAM f3=526.5p f3a=162.5p +.PARAM ps1=45.5p ps2=-66.7m ps3=91p ps4=-2 ps5=1.18p ps6=3.14p + +.PARAM qs1=35p qs2=152p qs3=-0.0333 qs4=48.6p qs5=-1 f2r=1 + +.PARAM Vmin=1.91 Vmax=2.71 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*(1+f2r/SQRT(a))*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**1)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT IPB025N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=4n + +.PARAM Rs=393u Rg=1.9 Rd=20u Rm=126u +.PARAM Inn=100 Unn=10 Rmax=2.5m gmin=104 +.PARAM RRf=382m Rrbond=5m Rtb=3.6 g2=647m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.75m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {64.9m+limit(Zthtype,0,1)*42.31m} +Rth5 t4 Tcase {172.84m+limit(Zthtype,0,1)*112.68m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 4.637m +Cth5 t4 0 137.136m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPA030N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=657u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=79 Unn=10 Rmax=3m gmin=89 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {616.39m+limit(Zthtype,0,1)*471.09m} +Rth5 t4 Tcase {1.42+limit(Zthtype,0,1)*1.09} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 30.936m +Cth5 t4 0 789.515m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPB027N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=657u Rg=1.9 Rd=50u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=2.7m gmin=99 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {64.9m+limit(Zthtype,0,1)*42.31m} +Rth5 t4 Tcase {172.84m+limit(Zthtype,0,1)*112.68m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 4.637m +Cth5 t4 0 137.136m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPI030N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=697u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=98 +.PARAM RRf=386m Rrbond=15m Rtb=6.1 g2=755m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.22m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {64.9m+limit(Zthtype,0,1)*42.31m} +Rth5 t4 Tcase {172.84m+limit(Zthtype,0,1)*112.68m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 4.637m +Cth5 t4 0 137.136m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP030N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=697u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=98 +.PARAM RRf=386m Rrbond=15m Rtb=6.1 g2=755m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.22m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {66.21m+limit(Zthtype,0,1)*21.29m} +Rth4 t3 t4 {64.9m+limit(Zthtype,0,1)*42.31m} +Rth5 t4 Tcase {172.84m+limit(Zthtype,0,1)*112.68m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 8.011m +Cth4 t3 0 4.637m +Cth5 t4 0 137.136m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPB039N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=4n + +.PARAM Rs=445u Rg=1.4 Rd=20u Rm=141u +.PARAM Inn=100 Unn=10 Rmax=3.9m gmin=80 +.PARAM RRf=418m Rrbond=8m Rtb=4.3 g2=687m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 11.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {114.22m+limit(Zthtype,0,1)*58.76m} +Rth5 t4 Tcase {224.04m+limit(Zthtype,0,1)*115.25m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 2.635m +Cth5 t4 0 91.413m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPA045N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=64 Unn=10 Rmax=4.5m gmin=62 +.PARAM RRf=389m Rrbond=16m Rtb=6.2 g2=758m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.36m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {742.26m+limit(Zthtype,0,1)*503.52m} +Rth5 t4 Tcase {1.41+limit(Zthtype,0,1)*956.49m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 15.917m +Cth5 t4 0 797.929m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPB042N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=50u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.2m gmin=76 +.PARAM RRf=389m Rrbond=16m Rtb=6.2 g2=758m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.36m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {114.22m+limit(Zthtype,0,1)*58.76m} +Rth5 t4 Tcase {224.04m+limit(Zthtype,0,1)*115.25m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 2.635m +Cth5 t4 0 91.413m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPI045N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.5m gmin=76 +.PARAM RRf=389m Rrbond=16m Rtb=6.2 g2=758m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.36m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {114.22m+limit(Zthtype,0,1)*58.76m} +Rth5 t4 Tcase {224.04m+limit(Zthtype,0,1)*115.25m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 2.635m +Cth5 t4 0 91.413m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP045N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.5m gmin=76 +.PARAM RRf=389m Rrbond=16m Rtb=6.2 g2=758m +.PARAM act=15.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.36m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.12m+limit(Zthtype,0,1)*780.76u} +Rth2 t1 t2 {23.04m+limit(Zthtype,0,1)*8.52m} +Rth3 t2 t3 {115.72m+limit(Zthtype,0,1)*37.55m} +Rth4 t3 t4 {114.22m+limit(Zthtype,0,1)*58.76m} +Rth5 t4 Tcase {224.04m+limit(Zthtype,0,1)*115.25m} +Cth1 Tj 0 215.794u +Cth2 t1 0 494.831u +Cth3 t2 0 4.593m +Cth4 t3 0 2.635m +Cth5 t4 0 91.413m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPB065N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=50u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=6.5m gmin=52 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=9.06 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {186.89m+limit(Zthtype,0,1)*64.43m} +Rth4 t3 t4 {195.41m+limit(Zthtype,0,1)*83.45m} +Rth5 t4 Tcase {288.39m+limit(Zthtype,0,1)*123.15m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.884m +Cth4 t3 0 1.54m +Cth5 t4 0 66.7m +Cth6 Tcase 0 190m + +.ENDS + +********** + + +.SUBCKT IPD068N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=824u Rg=1.6 Rd=50u Rm=345u +.PARAM Inn=90 Unn=10 Rmax=6.8m gmin=56 +.PARAM RRf=390m Rrbond=12m Rtb=5.5 g2=758m +.PARAM act=9.06 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {186.89m+limit(Zthtype,0,1)*64.43m} +Rth4 t3 t4 {157.76m+limit(Zthtype,0,1)*97.65m} +Rth5 t4 Tcase {268.68m+limit(Zthtype,0,1)*166.31m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.884m +Cth4 t3 0 1.597m +Cth5 t4 0 36.984m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPI072N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=350u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=7.2m gmin=52 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=9.06 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {186.89m+limit(Zthtype,0,1)*64.43m} +Rth4 t3 t4 {195.41m+limit(Zthtype,0,1)*83.45m} +Rth5 t4 Tcase {288.39m+limit(Zthtype,0,1)*123.15m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.884m +Cth4 t3 0 1.54m +Cth5 t4 0 66.7m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP072N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=350u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=7.2m gmin=52 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=9.06 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {186.89m+limit(Zthtype,0,1)*64.43m} +Rth4 t3 t4 {195.41m+limit(Zthtype,0,1)*83.45m} +Rth5 t4 Tcase {288.39m+limit(Zthtype,0,1)*123.15m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.884m +Cth4 t3 0 1.54m +Cth5 t4 0 66.7m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT BSC046N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=172u Rg=1.9 Rd=1u Rm=1u +.PARAM Inn=50 Unn=10 Rmax=4.6m gmin=51 + +.PARAM act=11.15 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {2.94m+limit(Zthtype,0,1)*1.09m} +Rth2 t1 t2 {31.79m+limit(Zthtype,0,1)*11.76m} +Rth3 t2 t3 {40.18m+limit(Zthtype,0,1)*4.91m} +Rth4 t3 t4 {128.19m+limit(Zthtype,0,1)*119.23m} +Rth5 t4 Tcase {238.28m+limit(Zthtype,0,1)*221.63m} +Cth1 Tj 0 155.233u +Cth2 t1 0 358.583u +Cth3 t2 0 864.139u +Cth4 t3 0 1.965m +Cth5 t4 0 43.525m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC060N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=404u Rg=1.6 Rd=50u Rm=233u +.PARAM Inn=50 Unn=10 Rmax=6m gmin=45 + +.PARAM act=9.06 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {3.62m+limit(Zthtype,0,1)*1.34m} +Rth2 t1 t2 {38.92m+limit(Zthtype,0,1)*14.4m} +Rth3 t2 t3 {146.86m+limit(Zthtype,0,1)*48.03m} +Rth4 t3 t4 {157.76m+limit(Zthtype,0,1)*118.53m} +Rth5 t4 Tcase {268.68m+limit(Zthtype,0,1)*201.86m} +Cth1 Tj 0 126.135u +Cth2 t1 0 292.909u +Cth3 t2 0 2.294m +Cth4 t3 0 1.597m +Cth5 t4 0 36.984m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC070N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=334u Rg=1.9 Rd=50u Rm=163u +.PARAM Inn=50 Unn=10 Rmax=7m gmin=41 + +.PARAM act=7.33 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {178.11m+limit(Zthtype,0,1)*59.47m} +Rth4 t3 t4 {195m+limit(Zthtype,0,1)*115.8m} +Rth5 t4 Tcase {301.14m+limit(Zthtype,0,1)*178.83m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 1.9m +Cth4 t3 0 1.292m +Cth5 t4 0 32.286m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC109N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=254u Rg=1.1 Rd=50u Rm=83u +.PARAM Inn=46 Unn=10 Rmax=10.9m gmin=31 + +.PARAM act=4.6 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {269.05m+limit(Zthtype,0,1)*95.2m} +Rth4 t3 t4 {310.73m+limit(Zthtype,0,1)*152.43m} +Rth5 t4 Tcase {375.71m+limit(Zthtype,0,1)*184.31m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.275m +Cth4 t3 0 810.607u +Cth5 t4 0 26.401m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPA086N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=45 Unn=10 Rmax=8.6m gmin=36 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {1.02+limit(Zthtype,0,1)*500.31m} +Rth5 t4 Tcase {1.41+limit(Zthtype,0,1)*691.6m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 9.834m +Cth5 t4 0 1.052 +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPB083N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=50u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.3m gmin=45 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {241.53m+limit(Zthtype,0,1)*112.6m} +Rth5 t4 Tcase {319.05m+limit(Zthtype,0,1)*148.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.246m +Cth5 t4 0 59.815m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD082N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=932u Rg=1.9 Rd=50u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.2m gmin=46 +.PARAM RRf=390m Rrbond=12m Rtb=5.5 g2=758m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {195m+limit(Zthtype,0,1)*128.04m} +Rth5 t4 Tcase {301.14m+limit(Zthtype,0,1)*197.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.292m +Cth5 t4 0 32.286m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPI086N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {241.53m+limit(Zthtype,0,1)*112.6m} +Rth5 t4 Tcase {319.05m+limit(Zthtype,0,1)*148.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.246m +Cth5 t4 0 59.815m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP086N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {241.53m+limit(Zthtype,0,1)*112.6m} +Rth5 t4 Tcase {319.05m+limit(Zthtype,0,1)*148.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.246m +Cth5 t4 0 59.815m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPP881N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=7.33 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.48m+limit(Zthtype,0,1)*1.66m} +Rth2 t1 t2 {47.82m+limit(Zthtype,0,1)*17.69m} +Rth3 t2 t3 {226.69m+limit(Zthtype,0,1)*79.75m} +Rth4 t3 t4 {241.53m+limit(Zthtype,0,1)*112.6m} +Rth5 t4 Tcase {319.05m+limit(Zthtype,0,1)*148.73m} +Cth1 Tj 0 102.05u +Cth2 t1 0 238.395u +Cth3 t2 0 2.389m +Cth4 t3 0 1.246m +Cth5 t4 0 59.815m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPA126N10NM3S drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=35 Unn=10 Rmax=12.6m gmin=26 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {1.2+limit(Zthtype,0,1)*601.06m} +Rth5 t4 Tcase {1.41+limit(Zthtype,0,1)*706.25m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 5.75m +Cth5 t4 0 1.041 +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPB123N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=50u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.3m gmin=30 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {328.76m+limit(Zthtype,0,1)*130.54m} +Rth5 t4 Tcase {399.42m+limit(Zthtype,0,1)*158.59m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 781.931u +Cth5 t4 0 48.493m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD122N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=729u Rg=2 Rd=50u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.2m gmin=30 +.PARAM RRf=390m Rrbond=12m Rtb=5.5 g2=758m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {311.23m+limit(Zthtype,0,1)*149.68m} +Rth5 t4 Tcase {375.71m+limit(Zthtype,0,1)*180.69m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 810.607u +Cth5 t4 0 26.401m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPI126N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.6m gmin=30 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {328.76m+limit(Zthtype,0,1)*130.54m} +Rth5 t4 Tcase {399.42m+limit(Zthtype,0,1)*158.59m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 781.931u +Cth5 t4 0 48.493m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP126N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.6m gmin=30 +.PARAM RRf=451m Rrbond=35m Rtb=9.3 g2=824m +.PARAM act=4.6 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.24m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.14m+limit(Zthtype,0,1)*2.64m} +Rth2 t1 t2 {75.03m+limit(Zthtype,0,1)*27.76m} +Rth3 t2 t3 {342.61m+limit(Zthtype,0,1)*127.51m} +Rth4 t3 t4 {328.76m+limit(Zthtype,0,1)*130.54m} +Rth5 t4 Tcase {399.42m+limit(Zthtype,0,1)*158.59m} +Cth1 Tj 0 64.042u +Cth2 t1 0 151.94u +Cth3 t2 0 1.603m +Cth4 t3 0 781.931u +Cth5 t4 0 48.493m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPA180N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=28 Unn=10 Rmax=18m gmin=20 +.PARAM RRf=488m Rrbond=141m Rtb=18.5 g2=904m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.12m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {1.2+limit(Zthtype,0,1)*732.5m} +Rth5 t4 Tcase {1.41+limit(Zthtype,0,1)*860.68m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 5.75m +Cth5 t4 0 1.041 +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPD180N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=1.24m Rg=2 Rd=50u Rm=481u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=22 +.PARAM RRf=472m Rrbond=50m Rtb=11 g2=862m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {437.86m+limit(Zthtype,0,1)*170.12m} +Rth5 t4 Tcase {428.66m+limit(Zthtype,0,1)*166.54m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 581.523u +Cth5 t4 0 25.044m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPI180N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM RRf=488m Rrbond=141m Rtb=18.5 g2=904m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.12m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {422.91m+limit(Zthtype,0,1)*147.15m} +Rth5 t4 Tcase {469.7m+limit(Zthtype,0,1)*163.42m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 560.95u +Cth5 t4 0 42.901m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP180N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM RRf=488m Rrbond=141m Rtb=18.5 g2=904m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.12m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {422.91m+limit(Zthtype,0,1)*147.15m} +Rth5 t4 Tcase {469.7m+limit(Zthtype,0,1)*163.42m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 560.95u +Cth5 t4 0 42.901m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPP882N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM RRf=488m Rrbond=141m Rtb=18.5 g2=904m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.12m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {463.56m+limit(Zthtype,0,1)*178.24m} +Rth4 t3 t4 {422.91m+limit(Zthtype,0,1)*147.15m} +Rth5 t4 Tcase {469.7m+limit(Zthtype,0,1)*163.42m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 1.196m +Cth4 t3 0 560.95u +Cth5 t4 0 42.901m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT BSC160N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=603u Rg=2 Rd=50u Rm=411u +.PARAM Inn=33 Unn=10 Rmax=16m gmin=22 + +.PARAM act=3.3 + + + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {363.94m+limit(Zthtype,0,1)*133.22m} +Rth4 t3 t4 {433.13m+limit(Zthtype,0,1)*244.28m} +Rth5 t4 Tcase {428.66m+limit(Zthtype,0,1)*241.75m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 951.044u +Cth4 t3 0 581.523u +Cth5 t4 0 25.044m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ160N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=577u Rg=2 Rd=50u Rm=281u +.PARAM Inn=20 Unn=10 Rmax=16m gmin=17 +.PARAM RRf=497m Rrbond=11m Rtb=5.1 g2=948m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 2.47m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {363.94m+limit(Zthtype,0,1)*133.22m} +Rth4 t3 t4 {433.13m+limit(Zthtype,0,1)*244.28m} +Rth5 t4 Tcase {428.66m+limit(Zthtype,0,1)*241.75m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 951.044u +Cth4 t3 0 581.523u +Cth5 t4 0 25.044m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT BSC440N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=364u Rg=0.8 Rd=50u Rm=193u +.PARAM Inn=12 Unn=10 Rmax=44m gmin=8 + +.PARAM act=1.18 + + + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {27.81m+limit(Zthtype,0,1)*10.3m} +Rth2 t1 t2 {272.43m+limit(Zthtype,0,1)*100.82m} +Rth3 t2 t3 {851.77m+limit(Zthtype,0,1)*378.56m} +Rth4 t3 t4 {1.26+limit(Zthtype,0,1)*540.35m} +Rth5 t4 Tcase {530.47m+limit(Zthtype,0,1)*227.49m} +Cth1 Tj 0 16.428u +Cth2 t1 0 41.844u +Cth3 t2 0 430.125u +Cth4 t3 0 207.938u +Cth5 t4 0 184.647m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ440N10NS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=1.06m Rg=0.8 Rd=50u Rm=641u +.PARAM Inn=12 Unn=10 Rmax=44m gmin=8 +.PARAM RRf=498m Rrbond=23m Rtb=7.4 g2=964m +.PARAM act=1.18 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {27.81m+limit(Zthtype,0,1)*10.3m} +Rth2 t1 t2 {272.43m+limit(Zthtype,0,1)*100.82m} +Rth3 t2 t3 {851.77m+limit(Zthtype,0,1)*378.56m} +Rth4 t3 t4 {1.26+limit(Zthtype,0,1)*540.35m} +Rth5 t4 Tcase {530.47m+limit(Zthtype,0,1)*227.49m} +Cth1 Tj 0 16.428u +Cth2 t1 0 41.844u +Cth3 t2 0 430.125u +Cth4 t3 0 207.938u +Cth5 t4 0 184.647m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT BSB056N10NN3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.05n Ld=0.7n Lg=0.1n + +.PARAM Rs=403u Rg=0.45 Rd=50u Rm=180u +.PARAM Inn=12 Unn=10 Rmax=5.6m gmin=23 +.PARAM RRf=-1k Rrbond=1u Rtb=58.7m g2=29m +.PARAM act=9.64 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 240.37u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.4m+limit(Zthtype,0,1)*1.26m} +Rth2 t1 t2 {36.64m+limit(Zthtype,0,1)*13.55m} +Rth3 t2 t3 {151.6m+limit(Zthtype,0,1)*53.68m} +Rth4 t3 t4 {183.65m+limit(Zthtype,0,1)*347.04m} +Rth5 t4 Tcase {280.02m+limit(Zthtype,0,1)*529.16m} +Cth1 Tj 0 134.21u +Cth2 t1 0 311.152u +Cth3 t2 0 2.957m +Cth4 t3 0 1.639m +Cth5 t4 0 68.973m +Cth6 Tcase 0 1m + +.ENDS + +********** + +.SUBCKT BSF134N10NJ3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.05n Ld=0.7n Lg=0.1n + +.PARAM Rs=300u Rg=0.55 Rd=250u Rm=102u +.PARAM Inn=12 Unn=10 Rmax=13.4m gmin=15 +.PARAM RRf=-966 Rrbond=1u Rtb=58.7m g2=32m +.PARAM act=3.8 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 240.37u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {8.64m+limit(Zthtype,0,1)*3.19m} +Rth2 t1 t2 {90.15m+limit(Zthtype,0,1)*33.36m} +Rth3 t2 t3 {347.78m+limit(Zthtype,0,1)*137.21m} +Rth4 t3 t4 {382.16m+limit(Zthtype,0,1)*722.55m} +Rth5 t4 Tcase {406.46m+limit(Zthtype,0,1)*768.5m} +Cth1 Tj 0 52.904u +Cth2 t1 0 126.45u +Cth3 t2 0 1.327m +Cth4 t3 0 669.632u +Cth5 t4 0 25.335m +Cth6 Tcase 0 1m + +.ENDS + +********** + +.SUBCKT IPT020N10N3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=226u Rg=1.9 Rd=20u Rm=88u +.PARAM Inn=150 Unn=10 Rmax=2m gmin=108 +.PARAM RRf=500m Rrbond=3m Rtb=2.6 g2=999m +.PARAM act=27.28 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_s2_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.2m+limit(Zthtype,0,1)*448.29u} +Rth2 t1 t2 {13.22m+limit(Zthtype,0,1)*4.9m} +Rth3 t2 t3 {32.15m+limit(Zthtype,0,1)*7.97m} +Rth4 t3 t4 {52.4m+limit(Zthtype,0,1)*47.4m} +Rth5 t4 Tcase {126.17m+limit(Zthtype,0,1)*114.14m} +Cth1 Tj 0 379.798u +Cth2 t1 0 862.111u +Cth3 t2 0 3.927m +Cth4 t3 0 4.807m +Cth5 t4 0 177.355m +Cth6 Tcase 0 30m + +.ENDS + +********** + + +.SUBCKT BSZ150N10LS3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=577u Rg=1.3 Rd=50u Rm=281u +.PARAM Inn=20 Unn=10 Rmax=15m gmin=17 +.PARAM RRf=497m Rrbond=11m Rtb=5.1 g2=948m +.PARAM act=3.3 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_t_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 2.47m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.95m+limit(Zthtype,0,1)*3.68m} +Rth2 t1 t2 {103.19m+limit(Zthtype,0,1)*38.2m} +Rth3 t2 t3 {363.94m+limit(Zthtype,0,1)*133.22m} +Rth4 t3 t4 {433.13m+limit(Zthtype,0,1)*244.28m} +Rth5 t4 Tcase {428.66m+limit(Zthtype,0,1)*241.75m} +Cth1 Tj 0 45.943u +Cth2 t1 0 110.466u +Cth3 t2 0 951.044u +Cth4 t3 0 581.523u +Cth5 t4 0 25.044m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT IPB025N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=4n + +.PARAM Rs=393u Rg=1.9 Rd=20u Rm=126u +.PARAM Inn=100 Unn=10 Rmax=2.5m gmin=104 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA030N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=657u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=79 Unn=10 Rmax=3m gmin=89 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB027N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=657u Rg=1.9 Rd=50u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=2.7m gmin=99 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI030N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=697u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=98 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP030N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=697u Rg=1.9 Rd=350u Rm=164u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=98 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB039N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=4n + +.PARAM Rs=445u Rg=1.4 Rd=20u Rm=141u +.PARAM Inn=100 Unn=10 Rmax=3.9m gmin=80 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA045N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=64 Unn=10 Rmax=4.5m gmin=62 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB042N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=50u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.2m gmin=76 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI045N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.5m gmin=76 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP045N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=748u Rg=1.4 Rd=350u Rm=210u +.PARAM Inn=100 Unn=10 Rmax=4.5m gmin=76 +.PARAM act=15.5 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB065N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=50u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=6.5m gmin=52 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD068N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=824u Rg=1.6 Rd=50u Rm=345u +.PARAM Inn=90 Unn=10 Rmax=6.8m gmin=56 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI072N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=350u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=7.2m gmin=52 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP072N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.04m Rg=1.6 Rd=350u Rm=345u +.PARAM Inn=80 Unn=10 Rmax=7.2m gmin=52 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC046N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=172u Rg=1.9 Rd=1u Rm=1u +.PARAM Inn=50 Unn=10 Rmax=4.6m gmin=51 +.PARAM act=11.15 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC060N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=404u Rg=1.6 Rd=50u Rm=233u +.PARAM Inn=50 Unn=10 Rmax=6m gmin=45 +.PARAM act=9.06 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC070N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=334u Rg=1.9 Rd=50u Rm=163u +.PARAM Inn=50 Unn=10 Rmax=7m gmin=41 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC109N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=254u Rg=1.1 Rd=50u Rm=83u +.PARAM Inn=46 Unn=10 Rmax=10.9m gmin=31 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA086N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=45 Unn=10 Rmax=8.6m gmin=36 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB083N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=50u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.3m gmin=45 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD082N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=932u Rg=1.9 Rd=50u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.2m gmin=46 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI086N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP086N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP881N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=1.15m Rg=1.9 Rd=350u Rm=453u +.PARAM Inn=73 Unn=10 Rmax=8.6m gmin=45 +.PARAM act=7.33 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA126N10NM3S_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=35 Unn=10 Rmax=12.6m gmin=26 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB123N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=50u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.3m gmin=30 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD122N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=729u Rg=2 Rd=50u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.2m gmin=30 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI126N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.6m gmin=30 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP126N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=947u Rg=2 Rd=350u Rm=250u +.PARAM Inn=46 Unn=10 Rmax=12.6m gmin=30 +.PARAM act=4.6 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA180N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=28 Unn=10 Rmax=18m gmin=20 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD180N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=1.24m Rg=2 Rd=50u Rm=481u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=22 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPI180N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP180N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP882N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=2.5n Lg=4n + +.PARAM Rs=1.74m Rg=2 Rd=350u Rm=562u +.PARAM Inn=33 Unn=10 Rmax=18m gmin=21 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC160N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=603u Rg=2 Rd=50u Rm=411u +.PARAM Inn=33 Unn=10 Rmax=16m gmin=22 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ160N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=577u Rg=2 Rd=50u Rm=281u +.PARAM Inn=20 Unn=10 Rmax=16m gmin=17 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_s_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC440N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=364u Rg=0.8 Rd=50u Rm=193u +.PARAM Inn=12 Unn=10 Rmax=44m gmin=8 +.PARAM act=1.18 + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ440N10NS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=1.06m Rg=0.8 Rd=50u Rm=641u +.PARAM Inn=12 Unn=10 Rmax=44m gmin=8 +.PARAM act=1.18 + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSB056N10NN3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.05n Ld=0.7n Lg=0.1n + +.PARAM Rs=403u Rg=0.45 Rd=50u Rm=180u +.PARAM Inn=12 Unn=10 Rmax=5.6m gmin=23 +.PARAM act=9.64 + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSF134N10NJ3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.05n Ld=0.7n Lg=0.1n + +.PARAM Rs=300u Rg=0.55 Rd=250u Rm=102u +.PARAM Inn=12 Unn=10 Rmax=13.4m gmin=15 +.PARAM act=3.8 + +X1 d1 g s Tj S3_100_s1_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPT020N10N3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=226u Rg=1.9 Rd=20u Rm=88u +.PARAM Inn=150 Unn=10 Rmax=2m gmin=108 +.PARAM act=27.28 + +X1 d1 g s Tj S3_100_s2_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ150N10LS3_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=1n Lg=3n + +.PARAM Rs=577u Rg=1.3 Rd=50u Rm=281u +.PARAM Inn=20 Unn=10 Rmax=15m gmin=17 +.PARAM act=3.3 + +X1 d1 g s Tj S3_100_t_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB025N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 393u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.3m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPB025N10N3_L0 + +****** + +.SUBCKT IPA030N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 657u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.63m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPA030N10N3_L0 + +****** + +.SUBCKT IPB027N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 657u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.33m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPB027N10N3_L0 + +****** + +.SUBCKT IPI030N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 697u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.63m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPI030N10N3_L0 + +****** + +.SUBCKT IPP030N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 697u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.63m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=8.73n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.05n + +.ENDS IPP030N10N3_L0 + +****** + +.SUBCKT IPB039N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 445u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.28m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPB039N10N3_L0 + +****** + +.SUBCKT IPA045N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 748u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.61m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPA045N10N3_L0 + +****** + +.SUBCKT IPB042N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 748u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.31m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPB042N10N3_L0 + +****** + +.SUBCKT IPI045N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 748u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.61m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPI045N10N3_L0 + +****** + +.SUBCKT IPP045N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 748u + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 266.6 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 2.61m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=4.96n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=294.5p N=1.19 RS=0.03u EG=1.12 TT=60n) +Rdiode d1 21 0.41m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.64n +.MODEL DGD D(M=0.7 CJO=1.64n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.28n + +.ENDS IPP045N10N3_L0 + +****** + +.SUBCKT IPB065N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 1.04m + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.91m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS IPB065N10N3_L0 + +****** + +.SUBCKT IPD068N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 824u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.91m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS IPD068N10N3_L0 + +****** + +.SUBCKT IPI072N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.04m + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.21m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS IPI072N10N3_L0 + +****** + +.SUBCKT IPP072N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.04m + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.21m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS IPP072N10N3_L0 + +****** + +.SUBCKT BSC046N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 172u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 191.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.14m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=3.57n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=211.9p N=1.19 RS=0.04u EG=1.12 TT=60n) +Rdiode d1 21 0.57m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.18n +.MODEL DGD D(M=0.7 CJO=1.18n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.52n + +.ENDS BSC046N10NS3_L0 + +****** + +.SUBCKT BSC060N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 404u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 155.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.91m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.9n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=172.1p N=1.19 RS=0.06u EG=1.12 TT=60n) +Rdiode d1 21 0.7m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.96n +.MODEL DGD D(M=0.7 CJO=0.96n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.67n + +.ENDS BSC060N10NS3_L0 + +****** + +.SUBCKT BSC070N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 334u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.82m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS BSC070N10NS3_L0 + +****** + +.SUBCKT BSC109N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 254u + +Rg g1 g2 1.1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS BSC109N10NS3_L0 + +****** + +.SUBCKT IPA086N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 5.12m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPA086N10N3_L0 + +****** + +.SUBCKT IPB083N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.82m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPB083N10N3_L0 + +****** + +.SUBCKT IPD082N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 932u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 4.82m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPD082N10N3_L0 + +****** + +.SUBCKT IPI086N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 5.12m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPI086N10N3_L0 + +****** + +.SUBCKT IPP086N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 5.12m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPP086N10N3_L0 + +****** + +.SUBCKT IPP881N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 1.15m + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 126.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 5.12m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=2.35n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=139.3p N=1.19 RS=0.07u EG=1.12 TT=60n) +Rdiode d1 21 0.86m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.78n +.MODEL DGD D(M=0.7 CJO=0.78n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.97n + +.ENDS IPP881N10N3_L0 + +****** + +.SUBCKT IPA126N10NM3S_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 947u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPA126N10NM3S_L0 + +****** + +.SUBCKT IPB123N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 947u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPB123N10N3_L0 + +****** + +.SUBCKT IPD122N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 729u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPD122N10N3_L0 + +****** + +.SUBCKT IPI126N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 947u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPI126N10N3_L0 + +****** + +.SUBCKT IPP126N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 947u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 79.1 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 7.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.47n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=87.4p N=1.19 RS=0.11u EG=1.12 TT=60n) +Rdiode d1 21 1.37m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=0.7 CJO=0.49n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.86n + +.ENDS IPP126N10N3_L0 + +****** + +.SUBCKT IPA180N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2.5n +Rs s1 s2 1.74m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPA180N10N3_L0 + +****** + +.SUBCKT IPD180N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 1.24m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPD180N10N3_L0 + +****** + +.SUBCKT IPI180N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2.5n +Rs s1 s2 1.74m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPI180N10N3_L0 + +****** + +.SUBCKT IPP180N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2.5n +Rs s1 s2 1.74m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPP180N10N3_L0 + +****** + +.SUBCKT IPP882N10N3_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2.5n +Rs s1 s2 1.74m + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.96m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS IPP882N10N3_L0 + +****** + +.SUBCKT BSC160N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 603u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS BSC160N10NS3_L0 + +****** + +.SUBCKT BSZ160N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 577u + +Rg g1 g2 2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 56.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.66m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.06n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.35n +.MODEL DGD D(M=0.7 CJO=0.35n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.34n + +.ENDS BSZ160N10NS3_L0 + +****** + + +.SUBCKT BSC440N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 364u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 20.3 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 29.71m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=0.49n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=22.4p N=1.19 RS=0.42u EG=1.12 TT=60n) +Rdiode d1 21 5.34m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.13n +.MODEL DGD D(M=0.7 CJO=0.13n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.6n + +.ENDS BSC440N10NS3_L0 + +****** + +.SUBCKT BSZ440N10NS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 1.06m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 20.3 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 29.71m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=0.49n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=22.4p N=1.19 RS=0.42u EG=1.12 TT=60n) +Rdiode d1 21 5.34m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.13n +.MODEL DGD D(M=0.7 CJO=0.13n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.6n + +.ENDS BSZ440N10NS3_L0 + +****** + +.SUBCKT BSB056N10NN3_L0 drain gate source + +Lg gate g1 0.1n +Ld drain d1 0.7n +Ls source s1 0.05n +Rs s1 s2 403u + +Rg g1 g2 0.45 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 165.8 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 3.68m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=3.4n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=183.2p N=1.19 RS=0.05u EG=1.12 TT=60n) +Rdiode d1 21 0.65m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.02n +.MODEL DGD D(M=0.7 CJO=1.02n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.03n + +.ENDS BSB056N10NN3_L0 + +****** + +.SUBCKT BSF134N10NJ3_L0 drain gate source + +Lg gate g1 0.1n +Ld drain d1 0.7n +Ls source s1 0.05n +Rs s1 s2 300u + +Rg g1 g2 0.55 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 65.4 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 9.46m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.41n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=72.2p N=1.19 RS=0.13u EG=1.12 TT=60n) +Rdiode d1 21 1.66m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.7 CJO=0.4n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.66n + +.ENDS BSF134N10NJ3_L0 + +****** + +.SUBCKT IPT020N10N3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 2n +Ls source s1 1.5n +Rs s1 s2 226u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 469.2 VTO=3.63 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 1.18m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=9.25n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=518.3p N=1.19 RS=0.02u EG=1.12 TT=60n) +Rdiode d1 21 0.23m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.89n +.MODEL DGD D(M=0.7 CJO=2.89n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.17n + +.ENDS IPT020N10N3_L0 + +****** + +.SUBCKT BSZ150N10LS3_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1n +Rs s1 s2 577u + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 77.6 VTO=2.31 THETA=0 VMAX=1.5e5 ETA=0.006 LEVEL=3) +Rd d1 d2 10.5m TC=8m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.3 CJO=1.24n VJ=0.9V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.19 RS=0.15u EG=1.12 TT=60n) +Rdiode d1 21 1.91m TC=10m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.45n +.MODEL DGD D(M=0.7 CJO=0.45n VJ=0.7) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.9n + +.ENDS BSZ150N10LS3_L0 + +****** diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS ReadMe.pdf b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS ReadMe.pdf new file mode 100755 index 0000000..3783a1f Binary files /dev/null and b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS ReadMe.pdf differ diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_L0.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_L0.slb new file mode 100755 index 0000000..bf23e1f --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_L0.slb @@ -0,0 +1,188 @@ +*version 9.1 231760093 +@index +symloc DMOS 0 1038 b +symloc BSZ097N10NS5_L0:DMOS 1038 295 +symloc IPB020N10N5_L0:DMOS 1333 292 +symloc IPP023N10N5_L0:DMOS 1625 292 +symloc BSC040N10NS5_L0:DMOS 1917 295 +symloc BSC070N10NS5_L0:DMOS 2212 295 +symloc IPT015N10N5_L0:DMOS 2507 292 +symloc IPB017N10N5_L0:DMOS 2799 292 +symloc IPB027N10N5_L0:DMOS 3091 292 +symloc IPP030N10N5_L0:DMOS 3383 292 +symloc IPA083N10N5_L0:DMOS 3675 292 +symloc IPP083N10N5_L0:DMOS 3967 292 +symloc BSC035N10NS5_L0:DMOS 4259 295 +symloc BSC098N10NS5_L0:DMOS 4554 295 +*symbol DMOS b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol BSZ097N10NS5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSZ097N10NS5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSZ097N10NS5_L0 +*symbol IPB020N10N5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB020N10N5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB020N10N5_L0 +*symbol IPP023N10N5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP023N10N5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP023N10N5_L0 +*symbol BSC040N10NS5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC040N10NS5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC040N10NS5_L0 +*symbol BSC070N10NS5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC070N10NS5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC070N10NS5_L0 +*symbol IPT015N10N5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPT015N10N5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPT015N10N5_L0 +*symbol IPB017N10N5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB017N10N5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB017N10N5_L0 +*symbol IPB027N10N5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPB027N10N5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB027N10N5_L0 +*symbol IPP030N10N5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP030N10N5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP030N10N5_L0 +*symbol IPA083N10N5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPA083N10N5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA083N10N5_L0 +*symbol IPP083N10N5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=IPP083N10N5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP083N10N5_L0 +*symbol BSC035N10NS5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC035N10NS5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC035N10NS5_L0 +*symbol BSC098N10NS5_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 89 38 hcn 100 PART=BSC098N10NS5_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC098N10NS5_L0 diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_L1.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_L1.slb new file mode 100755 index 0000000..e89e319 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_L1.slb @@ -0,0 +1,286 @@ +*version 9.1 4240037219 +@index +symloc DMOS_S2_L1_n 0 1402 b +symloc BSZ097N10NS5_L1:DMOS_S2_L1_n 1402 634 +symloc IPB020N10N5_L1:DMOS_S2_L1_n 2036 631 +symloc IPP023N10N5_L1:DMOS_S2_L1_n 2667 633 +symloc BSC040N10NS5_L1:DMOS_S2_L1_n 3300 634 +symloc BSC070N10NS5_L1:DMOS_S2_L1_n 3934 634 +symloc IPT015N10N5_L1:DMOS_S2_L1_n 4568 631 +symloc IPB017N10N5_L1:DMOS_S2_L1_n 5199 631 +symloc IPB027N10N5_L1:DMOS_S2_L1_n 5830 631 +symloc IPP030N10N5_L1:DMOS_S2_L1_n 6461 633 +symloc IPA083N10N5_L1:DMOS_S2_L1_n 7094 633 +symloc IPP083N10N5_L1:DMOS_S2_L1_n 7727 633 +symloc BSC035N10NS5_L1:DMOS_S2_L1_n 8360 634 +symloc BSC098N10NS5_L1:DMOS_S2_L1_n 8994 634 +*symbol DMOS_S2_L1_n b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1_n +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS_S2_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hcn 100 Ls=1n +a 0 u 0:13 0 0 20 hcn 100 Ld=0.5n +a 0 u 0:13 0 0 30 hcn 100 Lg=2n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol BSZ097N10NS5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSZ097N10NS5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSZ097N10NS5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPB020N10N5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB020N10N5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB020N10N5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP023N10N5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP023N10N5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP023N10N5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol BSC040N10NS5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC040N10NS5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC040N10NS5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC070N10NS5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC070N10NS5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC070N10NS5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPT015N10N5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPT015N10N5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPT015N10N5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPB017N10N5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB017N10N5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB017N10N5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB027N10N5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPB027N10N5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPB027N10N5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP030N10N5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP030N10N5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP030N10N5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA083N10N5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPA083N10N5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPA083N10N5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP083N10N5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=IPP083N10N5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=IPP083N10N5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol BSC035N10NS5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC035N10NS5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC035N10NS5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC098N10NS5_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSC098N10NS5_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSC098N10NS5_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_L3.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_L3.slb new file mode 100755 index 0000000..af6306f --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_L3.slb @@ -0,0 +1,311 @@ +*version 9.1 709970480 +@index +symloc BSZ097N10NS5:DMOS_S2_L3_n 0 699 +symloc DMOS_S2_L3_n 699 1796 b +symloc IPB020N10N5:DMOS_S2_L3_n 2495 696 +symloc IPP023N10N5:DMOS_S2_L3_n 3191 698 +symloc BSC040N10NS5:DMOS_S2_L3_n 3889 699 +symloc BSC070N10NS5:DMOS_S2_L3_n 4588 699 +symloc IPT015N10N5:DMOS_S2_L3_n 5287 696 +symloc IPB017N10N5:DMOS_S2_L3_n 5983 696 +symloc IPB027N10N5:DMOS_S2_L3_n 6679 696 +symloc IPP030N10N5:DMOS_S2_L3_n 7375 698 +symloc IPA083N10N5:DMOS_S2_L3_n 8073 698 +symloc IPP083N10N5:DMOS_S2_L3_n 8771 698 +symloc BSC035N10NS5:DMOS_S2_L3_n 9469 699 +symloc BSC098N10NS5:DMOS_S2_L3_n 10168 699 +*symbol BSZ097N10NS5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSZ097N10NS5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSZ097N10NS5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol DMOS_S2_L3_n b +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=2n +a 0 u 0:13 0 0 20 hlb 100 Ld=2n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tcase n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 30 30 +38 30 +38 10 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 20 13 +20 7 +; +v 0 30 20 +20 20 +; +v 0 15 10 +15 30 +; +v 0 20 30 +30 30 +; +v 0 10 20 +15 20 +; +v 0 30 20 +30 30 +; +v 0 38 10 +30 10 +; +v 0 20 10 +30 10 +; +v 0 20 33 +20 27 +; +v 0 20 23 +20 17 +; +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 5 d_info:,,,,,,,,,,,,,5, +Tcase +*symbol IPB020N10N5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB020N10N5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB020N10N5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP023N10N5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP023N10N5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP023N10N5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol BSC040N10NS5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC040N10NS5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC040N10NS5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC070N10NS5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC070N10NS5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC070N10NS5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPT015N10N5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPT015N10N5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPT015N10N5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.5n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol IPB017N10N5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB017N10N5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB017N10N5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPB027N10N5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPB027N10N5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPB027N10N5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP030N10N5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP030N10N5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP030N10N5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPA083N10N5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPA083N10N5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPA083N10N5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol IPP083N10N5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=IPP083N10N5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=IPP083N10N5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=1.8n +a 0 u 0:13 0 0 20 hlb 100 Ld=2.5n +a 0 u 0:13 0 0 30 hlb 100 Lg=4n +*symbol BSC035N10NS5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC035N10NS5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC035N10NS5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n +*symbol BSC098N10NS5 ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSC098N10NS5 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| ?Ls|Ls=@Ls| ?Ld|Ld=@Ld| ?Lg|Lg=@Lg| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSC098N10NS5 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +a 0 u 0:13 0 0 10 hlb 100 Ls=0.3n +a 0 u 0:13 0 0 20 hlb 100 Ld=1n +a 0 u 0:13 0 0 30 hlb 100 Lg=3n diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_LTSpice.lib b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_LTSpice.lib new file mode 100755 index 0000000..b2ddc11 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_LTSpice.lib @@ -0,0 +1,4030 @@ +***************************************************************** +* INFINEON Power Transistors * +* LTSPICE Library for * +* OptiMOS5 100V * +* n-channel Transistors * +* Version 150520 * +* * +***************************************************************** +* * +* The Simulation Model is subject to change without notice. In * +* addition, models can be a useful tool in evaluating device * +* performance, they cannot reflect the accurate device * +* performance under all conditions, nor are they intended to * +* replace bread boarding for final verification. Infineon * +* therefore does not assume any warranty or liability * +* whatsoever arising from their use. Infineon does not assume * +* any warranty or liability for the values and functions of the * +* Simulation Model. * +* The methods and results of the Simulation Model are to the * +* best of our knowledge * +* correct. However, the user is fully responsible to verify and * +* validate these results under the operating conditions and in * +* the environment of its application. Infineon will not bear * +* the responsibility arising out of or in connection with any * +* malfunction of the Simulation Models. * +* Models provided by Infineon are not warranted by Infineon as * +* completely and comprehensively representing all the * +* specifications and operating characteristics of the * +* semiconductor products to which these models relate. The * +* models describe the characteristics of typical devices. In * +* all cases, the current data sheet information for a given * +* device is the conclusive design guideline and the only actual * +* performance specification. * +* * +* * +* This library contains models of the following INFINEON * +* transistors: * +* * +* OptiMOS5 100V * +* * +* BSC027N10NS5 * +* BSC035N10NS5 * +* BSC040N10NS5 * +* BSC040N10NS5SC * +* BSC050N10NS5 * +* BSC070N10NS5 * +* BSC070N10NS5SC * +* BSC098N10NS5 * +* BSZ097N10NS5 * +* IPT015N10N5 * +* IPT020N10N5 * +* IPT026N10N5 * +* IPB017N10N5 * +* IPB020N10N5 * +* IPP023N10N5 * +* IPB024N10N5 * +* IPB027N10N5 * +* IPB032N10N5 * +* IPP030N10N5 * +* IPP039N10N5 * +* IPA050N10NM5S * +* IPD050N10N5 * +* IPA083N10N5 * +* IPP083N10N5 * +* IPA083N10NM5S * +* BSC034N10LS5 * +* BSC070N10LS5 * +* BSC096N10LS5 * +* BSZ096N10LS5 * +* BSC146N10LS5 * +* BSZ146N10LS5 * +* IRL100HS121 * +* * +***************************************************************** +* thermal nodes of level 3 models: * +* * +* .SUBCKT BSZ097N10NS5 drain gate source Tj Tcase * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Tcase : node where the boundary contition - external heat * +* sinks etc - have to be connected (ideal heat sink * +* can be modeled by using a voltage source stating the * +* ambient temperature in °C between Tcase and ground. * +* * +***************************************************************** +* thermal nodes of level 3 models with top side cooling: * +* * +* .SUBCKT BSC040N10NS5SC drain gate source Tj Ttop Tbottom * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Ttop, Tbottom : nodes where the boundary condition - * +* external heat sinks etc - have to be connected * +* (ideal heat sink can be modeled by using a voltage * +* source stating the ambient temperature in °C between * +* the surface node and ground. * +* * +***************************************************************** + +.options Thev_Induc=1 + +.SUBCKT S5_100_e_var dd g s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM b0=52 p0=7.92 p1=-29.8m p2=53u mubet=1.3 fbet=0 +.PARAM Vth0=3.99 c=1.5 Fm=150m Fn=500m al=500m auth=3.5m +.PARAM dvx=550m dvgs=0 auth_sub=3.5m + +.PARAM Rd=24.4m rpara=30u nmu=3.22 Rf=540m + +.PARAM lnIsj=-27.7 ndi=1.07 Rdi=5m nmu2=0 n_Isj=0 UB=107 +.PARAM ab=50m ab2=0 UT=100m lB=-23 td=30n ta=30n + +.PARAM kbq=85.8u Tref=298 T0=273 + +.PARAM f3=357p f3a=70p + +.PARAM f4=7.73p f5=4.49p sl=0.19p ps1=40p ps2=-1 ps3=45.57p +.PARAM ps4=-76.6m ps5=1.8p ps6=2p ps7=0 pc0=25p + +.PARAM q83=63p q84=-763m qs6=5p qs7=50p qs8=-38.2m + +.PARAM q80=96p q81=33.7p q82=1.92p qs1=35.2p qs2=80p qs3=-38.2m +.PARAM f2r=1.21 + +.PARAM x1={(q80-q81)/q82} x2={q80/q82} +.PARAM y1={(f4-f5)/sl} y2={f4/sl} +.PARAM Vmin=2.99 Vmax=4.99 dCmax=330m +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((1-fbet)*(T0/Tref)**mubet+fbet)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={((q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2))/(1+rpara*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*((1-fbet)*(T0/Tref)**mubet+fbet))} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+dCmax*limit(dC,0,1)} + +.PARAM Cgs0={f3*a*dC1} +.PARAM Cgs1={f3a*a*dC1} + +.PARAM Cds1={qs6*a*dC1} +.PARAM Cds2={qs7*a*dC1} +.PARAM Cds3={q83*a*dC1} +.PARAM Cds5={qs1*a*dC1} +.PARAM Cds6={(a*qs2*(1+f2r/sqrt(a)))*dC1} +.PARAM Cds8={q80*a*dC1} + +.PARAM Cdg1={(a*ps1+pc0*sqrt(a))*dC2} +.PARAM Cdg2={ps3*a*dC2} +.PARAM Cdg3={(ps5*a+ps6)*dC2} +.PARAM Cdg4={f4*a*dC2} +.PARAM dRdi={Rdi/a} + +.FUNC Ue(g,y,w) {(g-Vth+auth*(w-Tref)+Fm*y**Fn)} +.FUNC Ue1(g,y,w) {Ue(g,y,w)+(1+limit(Ue(g,y,w)+dvx,0,1)**2*(2*limit(Ue(g,y,w)+dvx,0,1)-3))*(dvgs+(auth_sub-auth)*(w-Tref))} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ih(Uds,T,p,Uee) {bet*((1-fbet)*(T0/T)**mubet+fbet)*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jh(d,g,w,y,s,x) {a*((Ih(s*y+min(d,0),w,(p0+(p1+p2*w)*w)*kbq*w,Ue1(g,y,w))+exp(min(lB+(d-UB-ab*(w-Tref))/UT,24))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**n_Isj)} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} +.FUNC Q01(Uds) {a*(limit(Uds,x1,x2)*(q80-q82/2*limit(Uds,x1,x2))+min(Uds-x1,0)*q81-max(x1,0)*(q80-q81)/2)} +.FUNC Q02(Udg) {a*(limit(Udg,y1,y2)*(f4-sl/2*limit(Udg,y1,y2))+min(Udg-y1,0)*f5-max(y1,0)*(f4-f5)/2)} + +C_Cgs g s {Cgs0} +C_Cgs1 g sp {Cgs1} + +C_Cds1 d s {Cds1} +E_Eds3 d edep3 VALUE {V(d,s)-I(V_sense3)/Cds3} +C_Cds3 edep3 s {Cds3} +E_Eds2 d edep2 VALUE {if(qs8==0,0,V(d,s)-(exp(qs8*max(V(d,s),-1))-1)/min(qs8,-1u)-min(V(d,s)+1,0)*exp(-qs8))} +C_Cds2 edep2 s {Cds2} + +C_Cds5 d sp {Cds5} +E_Eds6 d edep6 VALUE {if(qs3==0,0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/min(qs3,-1u)-min(V(d,sp),0))} +C_Cds6 edep6 sp {Cds6} +E_Eds8 d edep8 VALUE {V(d,sp)-Q01(V(d,sp))/Cds8} +C_Cds8 edep8 sp {Cds8} + +E_Edg1 d ox1 VALUE {if(ps2==0,0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/min(ps2,-1u)-min(V(d,g),0))} +C_Cdg1 ox1 g {Cdg1} +E_Edg2 d ox2 VALUE = ++{if(ps4==0,0,V(d,g)-((exp(ps4*(max(V(d,g)+ps7,0)))-exp(ps4*max(ps7,0)))/min(ps4,-1u)+min(V(d,g)+max(ps7,0),max(0,-ps7))))} +C_Cdg2 ox2 g {Cdg2} +C_Cdg3 d g {Cdg3} +E_Edg4 d ox4 VALUE {V(d,g)-Q02(V(d,g))/Cdg4} +C_Cdg4 ox4 g {Cdg4} + +Rfp s sp {Rsp} + +G_chan d5a s VALUE={Jh(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*max(V(d5a,s),0))-1)/2/al,sgn(V(d5a,s)),0)} +Rd06 d5a d5 1u +V_sm d d5 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds3*((exp(q84*max(V(d,s),-1))-1)/min(q84,-1u)-min(V(d,s)+1,0)*exp(-q84))} +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+Pr(V(s,s0),V(s,sp))} + + +.ENDS + +********** + +.SUBCKT S5_100_e1_var dd g s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM b0=52 p0=7.92 p1=-29.8m p2=53u mubet=1.3 fbet=0 +.PARAM Vth0=3.99 c=1.5 Fm=150m Fn=500m al=500m auth=3.5m +.PARAM dvx=550m dvgs=0 auth_sub=3.5m + +.PARAM Rd=24.4m rpara=30u nmu=3.22 Rf=540m + +.PARAM lnIsj=-27.7 ndi=1.07 Rdi=5m nmu2=0 n_Isj=0 UB=107 +.PARAM ab=50m ab2=0 UT=100m lB=-23 td=30n ta=30n + +.PARAM kbq=85.8u Tref=298 T0=273 + +.PARAM f3=380p f3b=30p f3a=70p + +.PARAM f4=7.73p f5=4.49p sl=0.19p ps1=45p ps2=-1 ps3=60p +.PARAM ps4=-90m ps5=1.5p ps6=4p ps7=0 pc0=50p + +.PARAM q83=63p q84=-763m qs6=5p qs7=50p qs8=-38.2m + +.PARAM q80=96p q81=33.7p q82=1.92p qs1=35.2p qs2=80p qs3=-38.2m +.PARAM f2r=1.21 + +.PARAM x1={(q80-q81)/q82} x2={q80/q82} +.PARAM y1={(f4-f5)/sl} y2={f4/sl} +.PARAM Vmin=2.99 Vmax=4.99 dCmax=330m +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((1-fbet)*(T0/Tref)**mubet+fbet)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={((q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2))/(1+rpara*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*((1-fbet)*(T0/Tref)**mubet+fbet))} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+dCmax*limit(dC,0,1)} + +.PARAM Cgs0={(f3*a+sqrt(a)*f3b)*dC1} +.PARAM Cgs1={f3a*a*dC1} + +.PARAM Cds1={qs6*a*dC1} +.PARAM Cds2={qs7*a*dC1} +.PARAM Cds3={q83*a*dC1} +.PARAM Cds5={qs1*a*dC1} +.PARAM Cds6={(a*qs2*(1+f2r/sqrt(a)))*dC1} +.PARAM Cds8={q80*a*dC1} + +.PARAM Cdg1={(a*ps1+pc0*sqrt(a))*dC2} +.PARAM Cdg2={ps3*a*dC2} +.PARAM Cdg3={(ps5*a+ps6)*dC2} +.PARAM Cdg4={f4*a*dC2} +.PARAM dRdi={Rdi/a} + +.FUNC Ue(g,y,w) {(g-Vth+auth*(w-Tref)+Fm*y**Fn)} +.FUNC Ue1(g,y,w) {Ue(g,y,w)+(1+limit(Ue(g,y,w)+dvx,0,1)**2*(2*limit(Ue(g,y,w)+dvx,0,1)-3))*(dvgs+(auth_sub-auth)*(w-Tref))} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ih(Uds,T,p,Uee) {bet*((1-fbet)*(T0/T)**mubet+fbet)*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jh(d,g,w,y,s,x) {a*((Ih(s*y+min(d,0),w,(p0+(p1+p2*w)*w)*kbq*w,Ue1(g,y,w))+exp(min(lB+(d-UB-ab*(w-Tref))/UT,24))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**n_Isj)} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} +.FUNC Q01(Uds) {a*(limit(Uds,x1,x2)*(q80-q82/2*limit(Uds,x1,x2))+min(Uds-x1,0)*q81-max(x1,0)*(q80-q81)/2)} +.FUNC Q02(Udg) {a*(limit(Udg,y1,y2)*(f4-sl/2*limit(Udg,y1,y2))+min(Udg-y1,0)*f5-max(y1,0)*(f4-f5)/2)} + +C_Cgs g s {Cgs0} +C_Cgs1 g sp {Cgs1} + +C_Cds1 d s {Cds1} +E_Eds3 d edep3 VALUE {V(d,s)-I(V_sense3)/Cds3} +C_Cds3 edep3 s {Cds3} +E_Eds2 d edep2 VALUE {if(qs8==0,0,V(d,s)-(exp(qs8*max(V(d,s),-1))-1)/min(qs8,-1u)-min(V(d,s)+1,0)*exp(-qs8))} +C_Cds2 edep2 s {Cds2} + +C_Cds5 d sp {Cds5} +E_Eds6 d edep6 VALUE {if(qs3==0,0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/min(qs3,-1u)-min(V(d,sp),0))} +C_Cds6 edep6 sp {Cds6} +E_Eds8 d edep8 VALUE {V(d,sp)-Q01(V(d,sp))/Cds8} +C_Cds8 edep8 sp {Cds8} + +E_Edg1 d ox1 VALUE {if(ps2==0,0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/min(ps2,-1u)-min(V(d,g),0))} +C_Cdg1 ox1 g {Cdg1} +E_Edg2 d ox2 VALUE = ++{if(ps4==0,0,V(d,g)-((exp(ps4*(max(V(d,g)+ps7,0)))-exp(ps4*max(ps7,0)))/min(ps4,-1u)+min(V(d,g)+max(ps7,0),max(0,-ps7))))} +C_Cdg2 ox2 g {Cdg2} +C_Cdg3 d g {Cdg3} +E_Edg4 d ox4 VALUE {V(d,g)-Q02(V(d,g))/Cdg4} +C_Cdg4 ox4 g {Cdg4} + +Rfp s sp {Rsp} + +G_chan d5a s VALUE={Jh(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*max(V(d5a,s),0))-1)/2/al,sgn(V(d5a,s)),0)} +Rd06 d5a d5 1u +V_sm d d5 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds3*((exp(q84*max(V(d,s),-1))-1)/min(q84,-1u)-min(V(d,s)+1,0)*exp(-q84))} +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+Pr(V(s,s0),V(s,sp))} + + +.ENDS + + + + +.SUBCKT S5_100_f_var dd g s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM b0=52 p0=7.92 p1=-29.8m p2=53u mubet=1.3 fbet=0 +.PARAM Vth0=3.99 c=1.5 Fm=150m Fn=500m al=500m auth=3.5m +.PARAM dvx=550m dvgs=0 auth_sub=3.5m + +.PARAM Rd=25.2m rpara=30u nmu=3.12 Rf=540m + +.PARAM lnIsj=-27.7 ndi=1.07 Rdi=5m nmu2=0 n_Isj=0 UB=107 +.PARAM ab=50m ab2=0 UT=100m lB=-23 td=30n ta=30n + +.PARAM kbq=85.8u Tref=298 T0=273 + +.PARAM f3=357p f3a=70p + +.PARAM f4=7.73p f5=4.49p sl=0.19p ps1=40p ps2=-1 ps3=45.57p +.PARAM ps4=-76.6m ps5=1.8p ps6=2p ps7=0 pc0=25p + +.PARAM q83=63p q84=-763m qs6=5p qs7=50p qs8=-38.2m + +.PARAM q80=96p q81=33.7p q82=1.92p qs1=35.2p qs2=80p qs3=-38.2m +.PARAM f2r=1.21 + +.PARAM x1={(q80-q81)/q82} x2={q80/q82} +.PARAM y1={(f4-f5)/sl} y2={f4/sl} +.PARAM Vmin=2.99 Vmax=4.99 dCmax=330m +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((1-fbet)*(T0/Tref)**mubet+fbet)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={((q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2))/(1+rpara*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*((1-fbet)*(T0/Tref)**mubet+fbet))} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+dCmax*limit(dC,0,1)} + +.PARAM Cgs0={f3*a*dC1} +.PARAM Cgs1={f3a*a*dC1} + +.PARAM Cds1={qs6*a*dC1} +.PARAM Cds2={qs7*a*dC1} +.PARAM Cds3={q83*a*dC1} +.PARAM Cds5={qs1*a*dC1} +.PARAM Cds6={(a*qs2*(1+f2r/sqrt(a)))*dC1} +.PARAM Cds8={q80*a*dC1} + +.PARAM Cdg1={(a*ps1+pc0*sqrt(a))*dC2} +.PARAM Cdg2={ps3*a*dC2} +.PARAM Cdg3={(ps5*a+ps6)*dC2} +.PARAM Cdg4={f4*a*dC2} +.PARAM dRdi={Rdi/a} + +.FUNC Ue(g,y,w) {(g-Vth+auth*(w-Tref)+Fm*y**Fn)} +.FUNC Ue1(g,y,w) {Ue(g,y,w)+(1+limit(Ue(g,y,w)+dvx,0,1)**2*(2*limit(Ue(g,y,w)+dvx,0,1)-3))*(dvgs+(auth_sub-auth)*(w-Tref))} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ih(Uds,T,p,Uee) {bet*((1-fbet)*(T0/T)**mubet+fbet)*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jh(d,g,w,y,s,x) {a*((Ih(s*y+min(d,0),w,(p0+(p1+p2*w)*w)*kbq*w,Ue1(g,y,w))+exp(min(lB+(d-UB-ab*(w-Tref))/UT,24))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**n_Isj)} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} +.FUNC Q01(Uds) {a*(limit(Uds,x1,x2)*(q80-q82/2*limit(Uds,x1,x2))+min(Uds-x1,0)*q81-max(x1,0)*(q80-q81)/2)} +.FUNC Q02(Udg) {a*(limit(Udg,y1,y2)*(f4-sl/2*limit(Udg,y1,y2))+min(Udg-y1,0)*f5-max(y1,0)*(f4-f5)/2)} + +C_Cgs g s {Cgs0} +C_Cgs1 g sp {Cgs1} + +C_Cds1 d s {Cds1} +E_Eds3 d edep3 VALUE {V(d,s)-I(V_sense3)/Cds3} +C_Cds3 edep3 s {Cds3} +E_Eds2 d edep2 VALUE {if(qs8==0,0,V(d,s)-(exp(qs8*max(V(d,s),-1))-1)/min(qs8,-1u)-min(V(d,s)+1,0)*exp(-qs8))} +C_Cds2 edep2 s {Cds2} + +C_Cds5 d sp {Cds5} +E_Eds6 d edep6 VALUE {if(qs3==0,0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/min(qs3,-1u)-min(V(d,sp),0))} +C_Cds6 edep6 sp {Cds6} +E_Eds8 d edep8 VALUE {V(d,sp)-Q01(V(d,sp))/Cds8} +C_Cds8 edep8 sp {Cds8} + +E_Edg1 d ox1 VALUE {if(ps2==0,0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/min(ps2,-1u)-min(V(d,g),0))} +C_Cdg1 ox1 g {Cdg1} +E_Edg2 d ox2 VALUE = ++{if(ps4==0,0,V(d,g)-((exp(ps4*(max(V(d,g)+ps7,0)))-exp(ps4*max(ps7,0)))/min(ps4,-1u)+min(V(d,g)+max(ps7,0),max(0,-ps7))))} +C_Cdg2 ox2 g {Cdg2} +C_Cdg3 d g {Cdg3} +E_Edg4 d ox4 VALUE {V(d,g)-Q02(V(d,g))/Cdg4} +C_Cdg4 ox4 g {Cdg4} + +Rfp s sp {Rsp} + +G_chan d5a s VALUE={Jh(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*max(V(d5a,s),0))-1)/2/al,sgn(V(d5a,s)),0)} +Rd06 d5a d5 1u +V_sm d d5 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds3*((exp(q84*max(V(d,s),-1))-1)/min(q84,-1u)-min(V(d,s)+1,0)*exp(-q84))} +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+Pr(V(s,s0),V(s,sp))} + + +.ENDS + +******************* + +.SUBCKT S5_100_g_var dd g s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM b0=47 p0=5.13 p1=-15.4m p2=25u mubet=1.3 fbet=0 +.PARAM Vth0=2.35 c=1.5 Fm=150m Fn=500m al=500m auth=2.3m +.PARAM dvx=550m dvgs=0 auth_sub=3.5m + +.PARAM Rd=24.4m rpara=30u nmu=3.22 Rf=540m + +.PARAM lnIsj=-27.7 ndi=1.07 Rdi=5m nmu2=0 n_Isj=0 UB=107 +.PARAM ab=50m ab2=0 UT=100m lB=-23 td=30n ta=30n + +.PARAM kbq=85.8u Tref=298 T0=273 + +.PARAM f3=357p f3a=70p + +.PARAM f4=7.73p f5=4.49p sl=0.19p ps1=40p ps2=-1 ps3=45.57p +.PARAM ps4=-76.6m ps5=1.8p ps6=2p ps7=0 pc0=25p + +.PARAM q83=63p q84=-763m qs6=5p qs7=50p qs8=-38.2m + +.PARAM q80=96p q81=33.7p q82=1.92p qs1=35.2p qs2=80p qs3=-38.2m +.PARAM f2r=1.21 + +.PARAM x1={(q80-q81)/q82} x2={q80/q82} +.PARAM y1={(f4-f5)/sl} y2={f4/sl} +.PARAM Vmin=1.95 Vmax=2.75 dCmax=330m +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((1-fbet)*(T0/Tref)**mubet+fbet)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={((q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2))/(1+rpara*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*((1-fbet)*(T0/Tref)**mubet+fbet))} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+dCmax*limit(dC,0,1)} + +.PARAM Cgs0={f3*a*dC1} +.PARAM Cgs1={f3a*a*dC1} + +.PARAM Cds1={qs6*a*dC1} +.PARAM Cds2={qs7*a*dC1} +.PARAM Cds3={q83*a*dC1} +.PARAM Cds5={qs1*a*dC1} +.PARAM Cds6={(a*qs2*(1+f2r/sqrt(a)))*dC1} +.PARAM Cds8={q80*a*dC1} + +.PARAM Cdg1={(a*ps1+pc0*sqrt(a))*dC2} +.PARAM Cdg2={ps3*a*dC2} +.PARAM Cdg3={(ps5*a+ps6)*dC2} +.PARAM Cdg4={f4*a*dC2} +.PARAM dRdi={Rdi/a} + +.FUNC Ue(g,y,w) {(g-Vth+auth*(w-Tref)+Fm*y**Fn)} +.FUNC Ue1(g,y,w) {Ue(g,y,w)+(1+limit(Ue(g,y,w)+dvx,0,1)**2*(2*limit(Ue(g,y,w)+dvx,0,1)-3))*(dvgs+(auth_sub-auth)*(w-Tref))} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ih(Uds,T,p,Uee) {bet*((1-fbet)*(T0/T)**mubet+fbet)*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jh(d,g,w,y,s,x) {a*((Ih(s*y+min(d,0),w,(p0+(p1+p2*w)*w)*kbq*w,Ue1(g,y,w))+exp(min(lB+(d-UB-ab*(w-Tref))/UT,24))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**n_Isj)} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} +.FUNC Q01(Uds) {a*(limit(Uds,x1,x2)*(q80-q82/2*limit(Uds,x1,x2))+min(Uds-x1,0)*q81-max(x1,0)*(q80-q81)/2)} +.FUNC Q02(Udg) {a*(limit(Udg,y1,y2)*(f4-sl/2*limit(Udg,y1,y2))+min(Udg-y1,0)*f5-max(y1,0)*(f4-f5)/2)} + +C_Cgs g s {Cgs0} +C_Cgs1 g sp {Cgs1} + +C_Cds1 d s {Cds1} +E_Eds3 d edep3 VALUE {V(d,s)-I(V_sense3)/Cds3} +C_Cds3 edep3 s {Cds3} +E_Eds2 d edep2 VALUE {if(qs8==0,0,V(d,s)-(exp(qs8*max(V(d,s),-1))-1)/min(qs8,-1u)-min(V(d,s)+1,0)*exp(-qs8))} +C_Cds2 edep2 s {Cds2} + +C_Cds5 d sp {Cds5} +E_Eds6 d edep6 VALUE {if(qs3==0,0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/min(qs3,-1u)-min(V(d,sp),0))} +C_Cds6 edep6 sp {Cds6} +E_Eds8 d edep8 VALUE {V(d,sp)-Q01(V(d,sp))/Cds8} +C_Cds8 edep8 sp {Cds8} + +E_Edg1 d ox1 VALUE {if(ps2==0,0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/min(ps2,-1u)-min(V(d,g),0))} +C_Cdg1 ox1 g {Cdg1} +E_Edg2 d ox2 VALUE = ++{if(ps4==0,0,V(d,g)-((exp(ps4*(max(V(d,g)+ps7,0)))-exp(ps4*max(ps7,0)))/min(ps4,-1u)+min(V(d,g)+max(ps7,0),max(0,-ps7))))} +C_Cdg2 ox2 g {Cdg2} +C_Cdg3 d g {Cdg3} +E_Edg4 d ox4 VALUE {V(d,g)-Q02(V(d,g))/Cdg4} +C_Cdg4 ox4 g {Cdg4} + +Rfp s sp {Rsp} + +G_chan d5a s VALUE={Jh(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*max(V(d5a,s),0))-1)/2/al,sgn(V(d5a,s)),0)} +Rd06 d5a d5 1u +V_sm d d5 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds3*((exp(q84*max(V(d,s),-1))-1)/min(q84,-1u)-min(V(d,s)+1,0)*exp(-q84))} +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+Pr(V(s,s0),V(s,sp))} + + +.ENDS + +******************* + +.SUBCKT IPT015N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=241u Rg=1.5 Rd=20u Rm=103u +.PARAM Inn=150 Unn=10 Rmax=1.5m gmin=170.17 +.PARAM RRf=500m Rrbond=3m Rtb=2.6 g2=999m +.PARAM act=27.96 Rsp=0.54 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.17m+limit(Zthtype,0,1)*438.21u} +Rth2 t1 t2 {12.91m+limit(Zthtype,0,1)*4.77m} +Rth3 t2 t3 {28.45m+limit(Zthtype,0,1)*6.6m} +Rth4 t3 t4 {51.12m+limit(Zthtype,0,1)*50.06m} +Rth5 t4 Tcase {123.53m+limit(Zthtype,0,1)*120.96m} +Cth1 Tj 0 389.265u +Cth2 t1 0 883.264u +Cth3 t2 0 3.629m +Cth4 t3 0 4.927m +Cth5 t4 0 115m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPB017N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=414u Rg=1.3 Rd=20u Rm=140u +.PARAM Inn=100 Unn=10 Rmax=1.7m gmin=133 +.PARAM RRf=391m Rrbond=6m Rtb=3.8 g2=656m +.PARAM act=27.88 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.14m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.18m+limit(Zthtype,0,1)*432.82u} +Rth2 t1 t2 {12.94m+limit(Zthtype,0,1)*4.79m} +Rth3 t2 t3 {28.53m+limit(Zthtype,0,1)*6.62m} +Rth4 t3 t4 {63.5m+limit(Zthtype,0,1)*30m} +Rth5 t4 Tcase {171.15m+limit(Zthtype,0,1)*80.86m} +Cth1 Tj 0 388.151u +Cth2 t1 0 880.776u +Cth3 t2 0 3.619m +Cth4 t3 0 4.739m +Cth5 t4 0 139.566m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPB020N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=656u Rg=1.3 Rd=50u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2m gmin=125 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.88 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.18m+limit(Zthtype,0,1)*432.82u} +Rth2 t1 t2 {12.94m+limit(Zthtype,0,1)*4.79m} +Rth3 t2 t3 {28.53m+limit(Zthtype,0,1)*6.62m} +Rth4 t3 t4 {63.5m+limit(Zthtype,0,1)*30m} +Rth5 t4 Tcase {171.15m+limit(Zthtype,0,1)*80.86m} +Cth1 Tj 0 388.151u +Cth2 t1 0 880.776u +Cth3 t2 0 3.619m +Cth4 t3 0 4.739m +Cth5 t4 0 139.566m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP023N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=656u Rg=1.3 Rd=350u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2.3m gmin=125 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.88 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.18m+limit(Zthtype,0,1)*432.82u} +Rth2 t1 t2 {12.94m+limit(Zthtype,0,1)*4.79m} +Rth3 t2 t3 {28.53m+limit(Zthtype,0,1)*6.62m} +Rth4 t3 t4 {63.5m+limit(Zthtype,0,1)*30m} +Rth5 t4 Tcase {171.15m+limit(Zthtype,0,1)*80.86m} +Cth1 Tj 0 388.151u +Cth2 t1 0 880.776u +Cth3 t2 0 3.619m +Cth4 t3 0 4.739m +Cth5 t4 0 139.566m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPT020N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=194u Rg=1.2 Rd=20u Rm=56u + +.PARAM Inn=150 Unn=10 Rmax=2m gmin=234 +.PARAM RRf=500m Rrbond=3m Rtb=2.6 g2=999m +.PARAM act=20.15 Rsp=0.43 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.63m+limit(Zthtype,0,1)*601.76u} +Rth2 t1 t2 {17.81m+limit(Zthtype,0,1)*6.59m} +Rth3 t2 t3 {39.07m+limit(Zthtype,0,1)*9.19m} +Rth4 t3 t4 {70.94m+limit(Zthtype,0,1)*74.66m} +Rth5 t4 Tcase {160.54m+limit(Zthtype,0,1)*168.97m} +Cth1 Tj 0 280.533u +Cth2 t1 0 640.034u +Cth3 t2 0 2.649m +Cth4 t3 0 3.551m +Cth5 t4 0 88.605m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPB024N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=359u Rg=1.2 Rd=20u Rm=85u +.PARAM Inn=100 Unn=10 Rmax=2.4m gmin=111 +.PARAM RRf=391m Rrbond=6m Rtb=3.8 g2=656m +.PARAM act=18.3 Rsp=0.46 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.14m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.79m+limit(Zthtype,0,1)*666.49u} +Rth2 t1 t2 {19.58m+limit(Zthtype,0,1)*7.24m} +Rth3 t2 t3 {42.87m+limit(Zthtype,0,1)*10.14m} +Rth4 t3 t4 {96.75m+limit(Zthtype,0,1)*67.91m} +Rth5 t4 Tcase {207.45m+limit(Zthtype,0,1)*145.61m} +Cth1 Tj 0 254.777u +Cth2 t1 0 582.308u +Cth3 t2 0 2.415m +Cth4 t3 0 3.111m +Cth5 t4 0 102.055m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPB027N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=735u Rg=1.2 Rd=50u Rm=242u +.PARAM Inn=100 Unn=10 Rmax=2.7m gmin=103 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=18.3 Rsp=0.46 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.79m+limit(Zthtype,0,1)*666.49u} +Rth2 t1 t2 {19.58m+limit(Zthtype,0,1)*7.24m} +Rth3 t2 t3 {42.87m+limit(Zthtype,0,1)*10.14m} +Rth4 t3 t4 {96.75m+limit(Zthtype,0,1)*67.91m} +Rth5 t4 Tcase {207.45m+limit(Zthtype,0,1)*145.61m} +Cth1 Tj 0 254.777u +Cth2 t1 0 582.308u +Cth3 t2 0 2.415m +Cth4 t3 0 3.111m +Cth5 t4 0 102.055m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPT026N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=350u Rg=1.3 Rd=20u Rm=160u + +.PARAM Inn=150 Unn=10 Rmax=2.6m gmin=197 +.PARAM RRf=500m Rrbond=5m Rtb=3.6 g2=999m +.PARAM act=15.83 Rsp=0.54 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.75m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.07m+limit(Zthtype,0,1)*770.26u} +Rth2 t1 t2 {22.57m+limit(Zthtype,0,1)*8.35m} +Rth3 t2 t3 {49.3m+limit(Zthtype,0,1)*11.73m} +Rth4 t3 t4 {90.29m+limit(Zthtype,0,1)*104.28m} +Rth5 t4 Tcase {190.56m+limit(Zthtype,0,1)*220.08m} +Cth1 Tj 0 220.389u +Cth2 t1 0 505.148u +Cth3 t2 0 2.103m +Cth4 t3 0 2.79m +Cth5 t4 0 62.518m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPB032N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=411u Rg=1.3 Rd=50u Rm=87u + +.PARAM Inn=83 Unn=10 Rmax=3.2m gmin=84 +.PARAM RRf=431m Rrbond=9m Rtb=4.7 g2=705m +.PARAM act=12.47 Rsp=0.44 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.17m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.63m+limit(Zthtype,0,1)*976.07u} +Rth2 t1 t2 {28.5m+limit(Zthtype,0,1)*10.55m} +Rth3 t2 t3 {61.98m+limit(Zthtype,0,1)*14.95m} +Rth4 t3 t4 {141.98m+limit(Zthtype,0,1)*105.74m} +Rth5 t4 Tcase {248m+limit(Zthtype,0,1)*184.7m} +Cth1 Tj 0 173.61u +Cth2 t1 0 399.981u +Cth3 t2 0 1.676m +Cth4 t3 0 2.12m +Cth5 t4 0 79.888m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP030N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=735u Rg=1.2 Rd=350u Rm=242u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=103 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=18.3 Rsp=0.46 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.79m+limit(Zthtype,0,1)*666.49u} +Rth2 t1 t2 {19.58m+limit(Zthtype,0,1)*7.24m} +Rth3 t2 t3 {42.87m+limit(Zthtype,0,1)*10.14m} +Rth4 t3 t4 {96.75m+limit(Zthtype,0,1)*67.91m} +Rth5 t4 Tcase {207.45m+limit(Zthtype,0,1)*145.61m} +Cth1 Tj 0 254.777u +Cth2 t1 0 582.308u +Cth3 t2 0 2.415m +Cth4 t3 0 3.111m +Cth5 t4 0 102.055m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPP039N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=565u Rg=1.4 Rd=350u Rm=87u +.PARAM Inn=50 Unn=10 Rmax=3.9m gmin=64.6 +.PARAM RRf=332m Rrbond=10m Rtb=5 g2=718m +.PARAM act=12.47 Rsp=0.44 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.61m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.63m+limit(Zthtype,0,1)*976.07u} +Rth2 t1 t2 {28.5m+limit(Zthtype,0,1)*10.55m} +Rth3 t2 t3 {61.98m+limit(Zthtype,0,1)*14.95m} +Rth4 t3 t4 {141.98m+limit(Zthtype,0,1)*105.74m} +Rth5 t4 Tcase {248m+limit(Zthtype,0,1)*184.7m} +Cth1 Tj 0 173.61u +Cth2 t1 0 399.981u +Cth3 t2 0 1.676m +Cth4 t3 0 2.12m +Cth5 t4 0 79.888m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPA050N10NM5S drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1.2 Rd=350u Rm=249u + +.PARAM Inn=80 Unn=10 Rmax=5.2m gmin=63.95 +.PARAM RRf=449m Rrbond=34m Rtb=9.1 g2=822m +.PARAM act=8.35 Rsp=0.7 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.15m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.93m+limit(Zthtype,0,1)*1.45m} +Rth2 t1 t2 {42.13m+limit(Zthtype,0,1)*15.6m} +Rth3 t2 t3 {90.82m+limit(Zthtype,0,1)*22.5m} +Rth4 t3 t4 {933.57m+limit(Zthtype,0,1)*543.43m} +Rth5 t4 Tcase {1.42+limit(Zthtype,0,1)*826.57m} +Cth1 Tj 0 116.251u +Cth2 t1 0 270.556u +Cth3 t2 0 1.148m +Cth4 t3 0 8.663m +Cth5 t4 0 754.984m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPD050N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=785u Rg=1.2 Rd=20u Rm=306u +.PARAM Inn=40 Unn=10 Rmax=5m gmin=46.5 +.PARAM RRf=390m Rrbond=12m Rtb=5.5 g2=758m +.PARAM act=8.35 Rsp=0.7 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.93m+limit(Zthtype,0,1)*1.45m} +Rth2 t1 t2 {42.13m+limit(Zthtype,0,1)*15.6m} +Rth3 t2 t3 {90.82m+limit(Zthtype,0,1)*22.5m} +Rth4 t3 t4 {171.18m+limit(Zthtype,0,1)*140.57m} +Rth5 t4 Tcase {281.03m+limit(Zthtype,0,1)*230.79m} +Cth1 Tj 0 116.251u +Cth2 t1 0 270.556u +Cth3 t2 0 1.148m +Cth4 t3 0 1.471m +Cth5 t4 0 34.98m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP083N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=75 Unn=10 Rmax=8.3m gmin=48.84 +.PARAM RRf=449m Rrbond=34m Rtb=9.1 g2=822m +.PARAM act=4.936 Rsp=0.43 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.15m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {149.01m+limit(Zthtype,0,1)*38.49m} +Rth4 t3 t4 {312.72m+limit(Zthtype,0,1)*227.66m} +Rth5 t4 Tcase {385.98m+limit(Zthtype,0,1)*280.99m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 704.871u +Cth4 t3 0 839.046u +Cth5 t4 0 49.922m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPA083N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=44 Unn=10 Rmax=8.3m gmin=37.82 +.PARAM RRf=449m Rrbond=34m Rtb=9.1 g2=822m +.PARAM act=4.936 Rsp=0.43 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.15m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {149.01m+limit(Zthtype,0,1)*38.49m} +Rth4 t3 t4 {1.1+limit(Zthtype,0,1)*585.52m} +Rth5 t4 Tcase {1.45+limit(Zthtype,0,1)*771.83m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 704.871u +Cth4 t3 0 3.059m +Cth5 t4 0 584.338m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPA083N10NM5S drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u + +.PARAM Inn=44 Unn=10 Rmax=8.3m gmin=37.82 +.PARAM RRf=449m Rrbond=34m Rtb=9.1 g2=822m +.PARAM act=4.936 Rsp=0.43 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.15m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {149.01m+limit(Zthtype,0,1)*38.49m} +Rth4 t3 t4 {1.1+limit(Zthtype,0,1)*585.52m} +Rth5 t4 Tcase {1.45+limit(Zthtype,0,1)*771.83m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 704.871u +Cth4 t3 0 3.059m +Cth5 t4 0 584.338m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT BSC027N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=159u Rg=1.7 Rd=20u Rm=36u +.PARAM Inn=50 Unn=10 Rmax=2.7m gmin=75 + +.PARAM act=14.62 Rsp=0.78 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {2.24m+limit(Zthtype,0,1)*835.36u} +Rth2 t1 t2 {24.39m+limit(Zthtype,0,1)*9.03m} +Rth3 t2 t3 {40.53m+limit(Zthtype,0,1)*7.53m} +Rth4 t3 t4 {97.77m+limit(Zthtype,0,1)*103.65m} +Rth5 t4 Tcase {200.97m+limit(Zthtype,0,1)*213.06m} +Cth1 Tj 0 203.543u +Cth2 t1 0 467.306u +Cth3 t2 0 1.467m +Cth4 t3 0 2.576m +Cth5 t4 0 56.903m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC035N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=412u Rg=1.5 Rd=20u Rm=241u +.PARAM Inn=50 Unn=10 Rmax=3.5m gmin=64 + +.PARAM act=11.52 Rsp=0.65 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {2.85m+limit(Zthtype,0,1)*1.05m} +Rth2 t1 t2 {30.79m+limit(Zthtype,0,1)*11.4m} +Rth3 t2 t3 {38.92m+limit(Zthtype,0,1)*4.75m} +Rth4 t3 t4 {124.08m+limit(Zthtype,0,1)*122.28m} +Rth5 t4 Tcase {233.64m+limit(Zthtype,0,1)*230.24m} +Cth1 Tj 0 160.384u +Cth2 t1 0 370.193u +Cth3 t2 0 891.859u +Cth4 t3 0 2.03m +Cth5 t4 0 44.789m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC040N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=373u Rg=1.3 Rd=20u Rm=202u +.PARAM Inn=50 Unn=10 Rmax=4m gmin=59 + +.PARAM act=9.46 Rsp=0.57 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {3.47m+limit(Zthtype,0,1)*1.28m} +Rth2 t1 t2 {37.31m+limit(Zthtype,0,1)*13.81m} +Rth3 t2 t3 {47.14m+limit(Zthtype,0,1)*5.84m} +Rth4 t3 t4 {151.09m+limit(Zthtype,0,1)*138.11m} +Rth5 t4 Tcase {262.24m+limit(Zthtype,0,1)*239.71m} +Cth1 Tj 0 131.704u +Cth2 t1 0 305.492u +Cth3 t2 0 737.321u +Cth4 t3 0 1.667m +Cth5 t4 0 38.161m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC040N10NS5SC drain gate source Tj Ttop Tbottom PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=122u Rg=1.3 Rd=10u Rm=14u + +.PARAM Inn=50 Unn=10 Rmax=4m gmin=59 +.PARAM act=9.46 Rsp=0.57 + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +Rth1 Tj t1 {3.47m+limit(Zthtype,0,1)*1.28m} +Rth2 t1 t2 {37.31m+limit(Zthtype,0,1)*13.81m} +Rth3 t2 t3 {47.14m+limit(Zthtype,0,1)*5.84m} +Rth4 t3 t4 {151.09m+limit(Zthtype,0,1)*138.11m} +Rth5 t4 Tbottom {262.23m+limit(Zthtype,0,1)*239.71m} +Cth1 Tj 0 131.7u +Cth2 t1 0 305.49u +Cth3 t2 0 737.32u +Cth4 t3 0 1.67m +Cth5 t4 0 38.16m +Cth6 Tbottom 0 30m +Rth1t Tj tt1 {233.64m+limit(Zthtype,0,1)*154.95m} +Rth2t tt1 tt2 {87.8m+limit(Zthtype,0,1)*154.95m} +Rth3t tt2 Ttop {69.01m+limit(Zthtype,0,1)*159.65m} +Cth1t tt1 0 1.18m +Cth2t tt2 0 2.63m +Cth3t Ttop 0 3.87m + +.ENDS + +********** + +.SUBCKT BSC050N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=342u Rg=1.2 Rd=20u Rm=171u + +.PARAM Inn=50 Unn=10 Rmax=5m gmin=52 +.PARAM RRf=-23m Rrbond=1m Rtb=1.8 g2=459m +.PARAM act=7.204 Rsp=0.52 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_e1_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.21m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.56m+limit(Zthtype,0,1)*1.68m} +Rth2 t1 t2 {48.63m+limit(Zthtype,0,1)*18m} +Rth3 t2 t3 {61.38m+limit(Zthtype,0,1)*7.81m} +Rth4 t3 t4 {198.41m+limit(Zthtype,0,1)*180.01m} +Rth5 t4 Tcase {303.85m+limit(Zthtype,0,1)*275.67m} +Cth1 Tj 0 100.296u +Cth2 t1 0 234.418u +Cth3 t2 0 567.368u +Cth4 t3 0 1.269m +Cth5 t4 0 31.969m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC070N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1 Rd=20u Rm=200u +.PARAM Inn=40 Unn=10 Rmax=7m gmin=39 + +.PARAM act=4.936 Rsp=0.43 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {88.37m+limit(Zthtype,0,1)*11.73m} +Rth4 t3 t4 {289.58m+limit(Zthtype,0,1)*283.82m} +Rth5 t4 Tcase {364.3m+limit(Zthtype,0,1)*357.05m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 395.377u +Cth4 t3 0 869.817u +Cth5 t4 0 26.98m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC098N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1.2 Rd=20u Rm=200u +.PARAM Inn=50 Unn=10 Rmax=9.8m gmin=37 + +.PARAM act=3.613 Rsp=0.57 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {9.08m+limit(Zthtype,0,1)*3.36m} +Rth2 t1 t2 {94.62m+limit(Zthtype,0,1)*35.02m} +Rth3 t2 t3 {119.14m+limit(Zthtype,0,1)*16.46m} +Rth4 t3 t4 {395.61m+limit(Zthtype,0,1)*347.83m} +Rth5 t4 Tcase {414.47m+limit(Zthtype,0,1)*364.41m} +Cth1 Tj 0 50.301u +Cth2 t1 0 120.478u +Cth3 t2 0 294.201u +Cth4 t3 0 636.679u +Cth5 t4 0 25.18m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ097N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=534u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=20 Unn=10 Rmax=9.7m gmin=23 +.PARAM RRf=498m Rrbond=17m Rtb=6.5 g2=958m +.PARAM act=3.613 Rsp=0.57 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.08m+limit(Zthtype,0,1)*3.36m} +Rth2 t1 t2 {94.62m+limit(Zthtype,0,1)*35.02m} +Rth3 t2 t3 {119.14m+limit(Zthtype,0,1)*16.46m} +Rth4 t3 t4 {395.61m+limit(Zthtype,0,1)*347.83m} +Rth5 t4 Tcase {414.47m+limit(Zthtype,0,1)*364.41m} +Cth1 Tj 0 50.301u +Cth2 t1 0 120.478u +Cth3 t2 0 294.201u +Cth4 t3 0 636.679u +Cth5 t4 0 25.18m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT BSC034N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=412u Rg=1.5 Rd=20u Rm=241u +.PARAM Inn=50 Unn=10 Rmax=3.4m gmin=61.09 + +.PARAM act=11.52 Rsp=0.65 + + + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {2.85m+limit(Zthtype,0,1)*1.05m} +Rth2 t1 t2 {30.79m+limit(Zthtype,0,1)*11.4m} +Rth3 t2 t3 {38.92m+limit(Zthtype,0,1)*4.75m} +Rth4 t3 t4 {124.08m+limit(Zthtype,0,1)*122.28m} +Rth5 t4 Tcase {233.64m+limit(Zthtype,0,1)*230.24m} +Cth1 Tj 0 160.384u +Cth2 t1 0 370.193u +Cth3 t2 0 891.859u +Cth4 t3 0 2.03m +Cth5 t4 0 44.789m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC070N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=367u Rg=1 Rd=10u Rm=200u + +.PARAM Inn=40 Unn=10 Rmax=7m gmin=36 +.PARAM act=4.936 Rsp=0.43 + + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {88.37m+limit(Zthtype,0,1)*11.73m} +Rth4 t3 t4 {289.58m+limit(Zthtype,0,1)*283.82m} +Rth5 t4 Tcase {364.3m+limit(Zthtype,0,1)*357.05m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 395.377u +Cth4 t3 0 869.817u +Cth5 t4 0 26.98m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC070N10NS5SC drain gate source Tj Ttop Tbottom PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=140u Rg=1 Rd=10u Rm=32u + +.PARAM Inn=40 Unn=10 Rmax=7m gmin=39 +.PARAM act=4.936 Rsp=0.43 + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {88.37m+limit(Zthtype,0,1)*11.73m} +Rth4 t3 t4 {289.58m+limit(Zthtype,0,1)*283.82m} +Rth5 t4 Tbottom {364.3m+limit(Zthtype,0,1)*357.05m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.62u +Cth3 t2 0 395.38u +Cth4 t3 0 869.82u +Cth5 t4 0 26.98m +Cth6 Tbottom 0 30m +Rth1t Tj tt1 {462.96m+limit(Zthtype,0,1)*216.41m} +Rth2t tt1 tt2 {169.4m+limit(Zthtype,0,1)*216.41m} +Rth3t tt2 Ttop {111.84m+limit(Zthtype,0,1)*222.97m} +Cth1t tt1 0 596.7u +Cth2t tt2 0 1.42m +Cth3t Ttop 0 2.83m + +.ENDS + +********** + +.SUBCKT BSC096N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=375u Rg=1.2 Rd=10u Rm=173u + +.PARAM Inn=50 Unn=10 Rmax=9.6m gmin=35 +.PARAM act=3.613 Rsp=0.57 + + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +Rth1 Tj t1 {9.08m+limit(Zthtype,0,1)*3.36m} +Rth2 t1 t2 {94.62m+limit(Zthtype,0,1)*35.02m} +Rth3 t2 t3 {119.14m+limit(Zthtype,0,1)*16.46m} +Rth4 t3 t4 {395.61m+limit(Zthtype,0,1)*347.83m} +Rth5 t4 Tcase {414.47m+limit(Zthtype,0,1)*364.41m} +Cth1 Tj 0 50.301u +Cth2 t1 0 120.478u +Cth3 t2 0 294.201u +Cth4 t3 0 636.679u +Cth5 t4 0 25.18m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ096N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=534u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=20 Unn=10 Rmax=9.6m gmin=22 +.PARAM RRf=498m Rrbond=17m Rtb=6.5 g2=958m +.PARAM act=3.613 Rsp=0.57 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.08m+limit(Zthtype,0,1)*3.36m} +Rth2 t1 t2 {94.62m+limit(Zthtype,0,1)*35.02m} +Rth3 t2 t3 {119.14m+limit(Zthtype,0,1)*16.46m} +Rth4 t3 t4 {395.61m+limit(Zthtype,0,1)*347.83m} +Rth5 t4 Tcase {414.47m+limit(Zthtype,0,1)*364.41m} +Cth1 Tj 0 50.301u +Cth2 t1 0 120.478u +Cth3 t2 0 294.201u +Cth4 t3 0 636.679u +Cth5 t4 0 25.18m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT BSC146N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1 Rd=20u Rm=200u +.PARAM Inn=20 Unn=10 Rmax=14.6m gmin=17.99 + +.PARAM act=2.345 Rsp=0.57 + + + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {14m+limit(Zthtype,0,1)*5.17m} +Rth2 t1 t2 {142.9m+limit(Zthtype,0,1)*52.88m} +Rth3 t2 t3 {179.63m+limit(Zthtype,0,1)*26.41m} +Rth4 t3 t4 {609.53m+limit(Zthtype,0,1)*499.43m} +Rth5 t4 Tcase {478.22m+limit(Zthtype,0,1)*391.83m} +Cth1 Tj 0 32.648u +Cth2 t1 0 79.775u +Cth3 t2 0 196.207u +Cth4 t3 0 413.234u +Cth5 t4 0 26.687m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ146N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=608u Rg=1 Rd=20u Rm=245u +.PARAM Inn=20 Unn=10 Rmax=14.6m gmin=18 +.PARAM RRf=498m Rrbond=17m Rtb=6.5 g2=958m +.PARAM act=2.345 Rsp=0.57 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {14m+limit(Zthtype,0,1)*5.17m} +Rth2 t1 t2 {142.9m+limit(Zthtype,0,1)*52.88m} +Rth3 t2 t3 {179.63m+limit(Zthtype,0,1)*26.41m} +Rth4 t3 t4 {609.53m+limit(Zthtype,0,1)*499.43m} +Rth5 t4 Tcase {478.22m+limit(Zthtype,0,1)*391.83m} +Cth1 Tj 0 32.648u +Cth2 t1 0 79.775u +Cth3 t2 0 196.207u +Cth4 t3 0 413.234u +Cth5 t4 0 26.687m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT IRL100HS121 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=2.25m Rg=0.9 Rd=20u Rm=257u +.PARAM Inn=6.7 Unn=10 Rmax=42m gmin=6.43 +.PARAM RRf=500m Rrbond=985m Rtb=62.7 g2=996m +.PARAM act=0.882 Rsp=1.1 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 38.04u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {37.21m+limit(Zthtype,0,1)*13.77m} +Rth2 t1 t2 {356.54m+limit(Zthtype,0,1)*131.95m} +Rth3 t2 t3 {446.45m+limit(Zthtype,0,1)*78.89m} +Rth4 t3 t4 {1.62+limit(Zthtype,0,1)*7.45} +Rth5 t4 Tcase {512.41m+limit(Zthtype,0,1)*2.36} +Cth1 Tj 0 12.279u +Cth2 t1 0 31.973u +Cth3 t2 0 80.397u +Cth4 t3 0 155.425u +Cth5 t4 0 3m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT IPT015N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=241u Rg=1.5 Rd=20u Rm=103u +.PARAM Inn=150 Unn=10 Rmax=1.5m gmin=170.17 +.PARAM act=27.96 Rsp=0.54 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB017N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=414u Rg=1.3 Rd=20u Rm=140u +.PARAM Inn=100 Unn=10 Rmax=1.7m gmin=133 +.PARAM act=27.88 Rsp=0.47 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB020N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=656u Rg=1.3 Rd=50u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2m gmin=125 +.PARAM act=27.88 Rsp=0.47 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP023N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=656u Rg=1.3 Rd=350u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2.3m gmin=125 +.PARAM act=27.88 Rsp=0.47 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPT020N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=194u Rg=1.2 Rd=20u Rm=56u +.PARAM Inn=150 Unn=10 Rmax=2m gmin=234 +.PARAM act=20.15 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB024N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=359u Rg=1.2 Rd=20u Rm=85u +.PARAM Inn=100 Unn=10 Rmax=2.4m gmin=111 +.PARAM act=18.3 Rsp=0.46 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB027N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=735u Rg=1.2 Rd=50u Rm=242u +.PARAM Inn=100 Unn=10 Rmax=2.7m gmin=103 +.PARAM act=18.3 Rsp=0.46 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPT026N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=350u Rg=1.3 Rd=20u Rm=160u +.PARAM Inn=150 Unn=10 Rmax=2.6m gmin=197 +.PARAM act=15.83 Rsp=0.54 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB032N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=411u Rg=1.3 Rd=50u Rm=87u +.PARAM Inn=83 Unn=10 Rmax=3.2m gmin=84 +.PARAM act=12.47 Rsp=0.44 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP030N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=735u Rg=1.2 Rd=350u Rm=242u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=103 +.PARAM act=18.3 Rsp=0.46 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP039N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=565u Rg=1.4 Rd=350u Rm=87u +.PARAM Inn=50 Unn=10 Rmax=3.9m gmin=64.6 +.PARAM act=12.47 Rsp=0.44 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA050N10NM5S_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1.2 Rd=350u Rm=249u +.PARAM Inn=80 Unn=10 Rmax=5.2m gmin=63.95 +.PARAM act=8.35 Rsp=0.7 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD050N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=785u Rg=1.2 Rd=20u Rm=306u +.PARAM Inn=40 Unn=10 Rmax=5m gmin=46.5 +.PARAM act=8.35 Rsp=0.7 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP083N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=75 Unn=10 Rmax=8.3m gmin=48.84 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA083N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=44 Unn=10 Rmax=8.3m gmin=37.82 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA083N10NM5S_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=44 Unn=10 Rmax=8.3m gmin=37.82 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC027N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=159u Rg=1.7 Rd=20u Rm=36u +.PARAM Inn=50 Unn=10 Rmax=2.7m gmin=75 +.PARAM act=14.62 Rsp=0.78 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC035N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=412u Rg=1.5 Rd=20u Rm=241u +.PARAM Inn=50 Unn=10 Rmax=3.5m gmin=64 +.PARAM act=11.52 Rsp=0.65 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC040N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=373u Rg=1.3 Rd=20u Rm=202u +.PARAM Inn=50 Unn=10 Rmax=4m gmin=59 +.PARAM act=9.46 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC040N10NS5SC_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=122u Rg=1.3 Rd=10u Rm=14u +.PARAM Inn=50 Unn=10 Rmax=4m gmin=59 +.PARAM act=9.46 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC050N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=342u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=50 Unn=10 Rmax=5m gmin=52 +.PARAM act=7.204 Rsp=0.52 + +X1 d1 g s sp Tj1 S5_100_e1_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC070N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1 Rd=20u Rm=200u +.PARAM Inn=40 Unn=10 Rmax=7m gmin=39 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC098N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1.2 Rd=20u Rm=200u +.PARAM Inn=50 Unn=10 Rmax=9.8m gmin=37 +.PARAM act=3.613 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ097N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=534u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=20 Unn=10 Rmax=9.7m gmin=23 +.PARAM act=3.613 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC034N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=412u Rg=1.5 Rd=20u Rm=241u +.PARAM Inn=50 Unn=10 Rmax=3.4m gmin=61.09 +.PARAM act=11.52 Rsp=0.65 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC070N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=367u Rg=1 Rd=10u Rm=200u +.PARAM Inn=40 Unn=10 Rmax=7m gmin=36 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC070N10NS5SC_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=140u Rg=1 Rd=10u Rm=32u +.PARAM Inn=40 Unn=10 Rmax=7m gmin=39 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC096N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=375u Rg=1.2 Rd=10u Rm=173u +.PARAM Inn=50 Unn=10 Rmax=9.6m gmin=35 +.PARAM act=3.613 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ096N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=534u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=20 Unn=10 Rmax=9.6m gmin=22 +.PARAM act=3.613 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC146N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1 Rd=20u Rm=200u +.PARAM Inn=20 Unn=10 Rmax=14.6m gmin=17.99 +.PARAM act=2.345 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ146N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=608u Rg=1 Rd=20u Rm=245u +.PARAM Inn=20 Unn=10 Rmax=14.6m gmin=18 +.PARAM act=2.345 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IRL100HS121_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=2.25m Rg=0.9 Rd=20u Rm=257u +.PARAM Inn=6.7 Unn=10 Rmax=42m gmin=6.43 +.PARAM act=0.882 Rsp=1.1 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPT015N10N5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 241u TC=3m + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1034.5 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 0.94m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=3.36n VJ=2.5V) +Rsp s2 s3 0.54 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=12.8n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=119.9p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.22m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.08n +.MODEL DGD D(M=0.55 CJO=3.08n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.94n + +.ENDS IPT015N10N5_L0 + +****** + +.SUBCKT IPB017N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 414u TC=3m + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1031.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 0.95m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=3.35n VJ=2.5V) +Rsp s2 s3 0.47 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=12.77n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=119.6p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.22m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.07n +.MODEL DGD D(M=0.55 CJO=3.07n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.9n + +.ENDS IPB017N10N5_L0 + +****** + +.SUBCKT IPB020N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 656u TC=3m + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1031.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 0.98m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=3.35n VJ=2.5V) +Rsp s2 s3 0.47 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=12.77n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=119.6p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.22m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.07n +.MODEL DGD D(M=0.55 CJO=3.07n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.9n + +.ENDS IPB020N10N5_L0 + +***************** + +.SUBCKT IPT020N10N5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 2n +Ls source s1 1.5n +Rs s1 s2 194u TC=3m + +Rg g1 g2 1.2 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=745.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.3m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=2.42n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=9.36n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=86.4p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.3m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.22n +.MODEL DGD D(M=0.55 CJO=2.22n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.6n + +.ENDS IPT020N10N5_L0 + +***************** + +.SUBCKT IPP023N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 656u TC=3m + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1031.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.28m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=3.35n VJ=2.5V) +Rsp s2 s3 0.47 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=12.77n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=119.6p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.22m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.07n +.MODEL DGD D(M=0.55 CJO=3.07n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.9n + +.ENDS IPP023N10N5_L0 + +****** + +.SUBCKT IPB024N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 359u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 677.1 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.43m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=2.2n VJ=2.5V) +Rsp s2 s3 0.46 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=8.54n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=78.5p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.33m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.01n +.MODEL DGD D(M=0.55 CJO=2.01n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 7.81n + +.ENDS IPB024N10N5_L0 + + +***************** + +.SUBCKT IPT026N10N5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 2n +Ls source s1 1.5n +Rs s1 s2 350u TC=3m + +Rg g1 g2 1.3 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=585.7 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.65m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.9n VJ=2.5V) +Rsp s2 s3 0.54 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=7.44n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=67.9p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.39m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.74n +.MODEL DGD D(M=0.55 CJO=1.74n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.76n + +.ENDS IPT026N10N5_L0 + +***************** + +.SUBCKT IPB027N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 735u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 677.1 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.46m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=2.2n VJ=2.5V) +Rsp s2 s3 0.46 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=8.54n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=78.5p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.33m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.01n +.MODEL DGD D(M=0.55 CJO=2.01n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 7.81n + +.ENDS IPB027N10N5_L0 + +****** + +.SUBCKT IPB032N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 411u TC=3m + +Rg g1 g2 1.3 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=461.4 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.12m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.5n VJ=2.5V) +Rsp s2 s3 0.44 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=5.94n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=53.5p N=1.12 RS=0.04u EG=1.12 TT=20n) +Rdiode d1 21 0.49m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.37n +.MODEL DGD D(M=0.55 CJO=1.37n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 5.32n + +.ENDS IPB032N10N5_L0 + +***************** + +.SUBCKT IPP030N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 735u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 677.1 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.76m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=2.2n VJ=2.5V) +Rsp s2 s3 0.46 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=8.54n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=78.5p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.33m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.01n +.MODEL DGD D(M=0.55 CJO=2.01n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 7.81n + +.ENDS IPP030N10N5_L0 + +****** + +.SUBCKT IPP039N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 565u TC=3m + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 461.4 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.42m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.5n VJ=2.5V) +Rsp s2 s3 0.44 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=5.94n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=53.5p N=1.12 RS=0.04u EG=1.12 TT=20n) +Rdiode d1 21 0.49m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.37n +.MODEL DGD D(M=0.55 CJO=1.37n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 5.32n + +.ENDS IPP039N10N5_L0 + +****** + +.SUBCKT IPA050N10NM5S_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 939u TC=3m + +Rg g1 g2 1.2 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=309 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 3.44m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1n VJ=2.5V) +Rsp s2 s3 0.7 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=4.08n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=35.8p N=1.12 RS=0.06u EG=1.12 TT=20n) +Rdiode d1 21 0.73m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.92n +.MODEL DGD D(M=0.55 CJO=0.92n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.57n + +.ENDS IPA050N10NM5S_L0 + +***************** + +.SUBCKT IPD050N10N5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 785u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 309 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 3.11m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1n VJ=2.5V) +Rsp s2 s3 0.7 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=4.08n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=35.8p N=1.12 RS=0.06u EG=1.12 TT=20n) +Rdiode d1 21 0.73m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.92n +.MODEL DGD D(M=0.55 CJO=0.92n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.57n + +.ENDS IPD050N10N5_L0 + +****** + +.SUBCKT IPP083N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 939u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.58m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS IPP083N10N5_L0 + +****** + +.SUBCKT IPA083N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 939u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.58m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS IPA083N10N5_L0 + +****** + +.SUBCKT IPA083N10NM5S_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 939u TC=3m + +Rg g1 g2 1 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.58m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS IPA083N10NM5S_L0 + +***************** + +.SUBCKT BSC027N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 159u TC=3m + +Rg g1 g2 1.7 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 540.9 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.73m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.75n VJ=2.5V) +Rsp s2 s3 0.78 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=6.91n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.42m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.61n +.MODEL DGD D(M=0.55 CJO=1.61n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.24n + +.ENDS BSC027N10NS5_L0 + +****** + +.SUBCKT BSC035N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 412u TC=3m + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 426.2 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.19m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.38n VJ=2.5V) +Rsp s2 s3 0.65 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=5.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=49.4p N=1.12 RS=0.04u EG=1.12 TT=20n) +Rdiode d1 21 0.53m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.27n +.MODEL DGD D(M=0.55 CJO=1.27n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.92n + +.ENDS BSC035N10NS5_L0 + +****** + +.SUBCKT BSC040N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 373u TC=3m + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 350 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.66m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.14n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=4.59n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=40.6p N=1.12 RS=0.05u EG=1.12 TT=20n) +Rdiode d1 21 0.64m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=0.55 CJO=1.04n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.04n + +.ENDS BSC040N10NS5_L0 + +********** + +.SUBCKT BSC040N10NS5SC_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 300p +Rs s1 s2 122u TC=3m + +Rg g1 g2 1.3 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=350 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.65m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.14n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=4.59n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=40.6p N=1.12 RS=0.05u EG=1.12 TT=20n) +Rdiode d1 21 0.64m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=0.55 CJO=1.04n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.04n + +.ENDS BSC040N10NS5SC_L0 + +***************** + +.SUBCKT BSC050N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 342u TC=3m + +Rg g1 g2 1.2 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=266.5 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 3.49m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.86n VJ=2.5V) +Rsp s2 s3 0.52 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=3.56n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=30.9p N=1.12 RS=0.07u EG=1.12 TT=20n) +Rdiode d1 21 0.85m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.9n +.MODEL DGD D(M=0.58 CJO=0.9n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.24n + +.ENDS BSC050N10NS5_L0 + +***************** + +.SUBCKT BSC070N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 371u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.08m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS BSC070N10NS5_L0 + +***************** + +.SUBCKT BSC070N10NS5SC_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 300p +Rs s1 s2 140u TC=3m + +Rg g1 g2 1 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.07m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS BSC070N10NS5SC_L0 + +***************** + +.SUBCKT BSC098N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 371u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 133.7 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 6.94m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.43n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.9n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.5p N=1.12 RS=0.14u EG=1.12 TT=20n) +Rdiode d1 21 1.69m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.55 CJO=0.4n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS BSC098N10NS5_L0 + +****** + +.SUBCKT BSZ097N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 534u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 133.7 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 6.94m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.43n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.9n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.5p N=1.12 RS=0.14u EG=1.12 TT=20n) +Rdiode d1 21 1.69m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.55 CJO=0.4n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS BSZ097N10NS5_L0 + +****** + +.SUBCKT BSC034N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 412u TC=3m + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 383.6 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.26m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.38n VJ=2.5V) +Rsp s2 s3 0.65 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=5.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=49.4p N=1.12 RS=0.04u EG=1.12 TT=20n) +Rdiode d1 21 0.53m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.27n +.MODEL DGD D(M=0.55 CJO=1.27n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.92n + +.ENDS BSC034N10LS5_L0 + +****** + +.SUBCKT BSC070N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 300p +Rs s1 s2 367u TC=3m + +Rg g1 g2 1 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=164.4 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.24m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS BSC070N10LS5_L0 + +***************** + +.SUBCKT BSC096N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 375u TC=3m + +Rg g1 g2 1.2 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=120.3 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 7.15m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.43n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.9n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.5p N=1.12 RS=0.14u EG=1.12 TT=20n) +Rdiode d1 21 1.69m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.55 CJO=0.4n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS BSC096N10LS5_L0 + +***************** + +.SUBCKT BSZ096N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 534u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 120.3 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 7.16m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.43n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.9n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.5p N=1.12 RS=0.14u EG=1.12 TT=20n) +Rdiode d1 21 1.69m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.55 CJO=0.4n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS BSZ096N10LS5_L0 + +****** + +.SUBCKT BSC146N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 371u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 78.1 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 11.02m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.28n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.29n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=10.1p N=1.12 RS=0.21u EG=1.12 TT=20n) +Rdiode d1 21 2.6m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.26n +.MODEL DGD D(M=0.55 CJO=0.26n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1n + +.ENDS BSC146N10LS5_L0 + +****** + +.SUBCKT BSZ146N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 608u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 78.1 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 11.02m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.28n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.29n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=10.1p N=1.12 RS=0.21u EG=1.12 TT=20n) +Rdiode d1 21 2.6m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.26n +.MODEL DGD D(M=0.55 CJO=0.26n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1n + +.ENDS BSZ146N10LS5_L0 + +****** + +.SUBCKT IRL100HS121_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 2.25m TC=3m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 29.4 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 29.27m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.11n VJ=2.5V) +Rsp s2 s3 1.1 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=0.56n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.12 RS=0.57u EG=1.12 TT=20n) +Rdiode d1 21 6.92m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.1n +.MODEL DGD D(M=0.55 CJO=0.1n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.38n + +.ENDS IRL100HS121_L0 + +****** + diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_PSpice.lib b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_PSpice.lib new file mode 100755 index 0000000..87134e6 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_100V_PSpice.lib @@ -0,0 +1,4028 @@ +***************************************************************** +* INFINEON Power Transistors * +* PSPICE Library for * +* OptiMOS5 100V * +* n-channel Transistors * +* Version 150520 * +* * +***************************************************************** +* * +* The Simulation Model is subject to change without notice. In * +* addition, models can be a useful tool in evaluating device * +* performance, they cannot reflect the accurate device * +* performance under all conditions, nor are they intended to * +* replace bread boarding for final verification. Infineon * +* therefore does not assume any warranty or liability * +* whatsoever arising from their use. Infineon does not assume * +* any warranty or liability for the values and functions of the * +* Simulation Model. * +* The methods and results of the Simulation Model are to the * +* best of our knowledge * +* correct. However, the user is fully responsible to verify and * +* validate these results under the operating conditions and in * +* the environment of its application. Infineon will not bear * +* the responsibility arising out of or in connection with any * +* malfunction of the Simulation Models. * +* Models provided by Infineon are not warranted by Infineon as * +* completely and comprehensively representing all the * +* specifications and operating characteristics of the * +* semiconductor products to which these models relate. The * +* models describe the characteristics of typical devices. In * +* all cases, the current data sheet information for a given * +* device is the conclusive design guideline and the only actual * +* performance specification. * +* * +* * +* This library contains models of the following INFINEON * +* transistors: * +* * +* OptiMOS5 100V * +* * +* BSC027N10NS5 * +* BSC035N10NS5 * +* BSC040N10NS5 * +* BSC040N10NS5SC * +* BSC050N10NS5 * +* BSC070N10NS5 * +* BSC070N10NS5SC * +* BSC098N10NS5 * +* BSZ097N10NS5 * +* IPT015N10N5 * +* IPT020N10N5 * +* IPT026N10N5 * +* IPB017N10N5 * +* IPB020N10N5 * +* IPP023N10N5 * +* IPB024N10N5 * +* IPB027N10N5 * +* IPB032N10N5 * +* IPP030N10N5 * +* IPP039N10N5 * +* IPA050N10NM5S * +* IPD050N10N5 * +* IPA083N10N5 * +* IPP083N10N5 * +* IPA083N10NM5S * +* BSC034N10LS5 * +* BSC070N10LS5 * +* BSC096N10LS5 * +* BSZ096N10LS5 * +* BSC146N10LS5 * +* BSZ146N10LS5 * +* IRL100HS121 * +* * +***************************************************************** +* thermal nodes of level 3 models: * +* * +* .SUBCKT BSZ097N10NS5 drain gate source Tj Tcase * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Tcase : node where the boundary contition - external heat * +* sinks etc - have to be connected (ideal heat sink * +* can be modeled by using a voltage source stating the * +* ambient temperature in °C between Tcase and ground. * +* * +***************************************************************** +* thermal nodes of level 3 models with top side cooling: * +* * +* .SUBCKT BSC040N10NS5SC drain gate source Tj Ttop Tbottom * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Ttop, Tbottom : nodes where the boundary condition - * +* external heat sinks etc - have to be connected * +* (ideal heat sink can be modeled by using a voltage * +* source stating the ambient temperature in °C between * +* the surface node and ground. * +* * +***************************************************************** + +.SUBCKT S5_100_e_var dd g s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM b0=52 p0=7.92 p1=-29.8m p2=53u mubet=1.3 fbet=0 +.PARAM Vth0=3.99 c=1.5 Fm=150m Fn=500m al=500m auth=3.5m +.PARAM dvx=550m dvgs=0 auth_sub=3.5m + +.PARAM Rd=24.4m rpara=30u nmu=3.22 Rf=540m + +.PARAM lnIsj=-27.7 ndi=1.07 Rdi=5m nmu2=0 n_Isj=0 UB=107 +.PARAM ab=50m ab2=0 UT=100m lB=-23 td=30n ta=30n + +.PARAM kbq=85.8u Tref=298 T0=273 + +.PARAM f3=357p f3a=70p + +.PARAM f4=7.73p f5=4.49p sl=0.19p ps1=40p ps2=-1 ps3=45.57p +.PARAM ps4=-76.6m ps5=1.8p ps6=2p ps7=0 pc0=25p + +.PARAM q83=63p q84=-763m qs6=5p qs7=50p qs8=-38.2m + +.PARAM q80=96p q81=33.7p q82=1.92p qs1=35.2p qs2=80p qs3=-38.2m +.PARAM f2r=1.21 + +.PARAM x1={(q80-q81)/q82} x2={q80/q82} +.PARAM y1={(f4-f5)/sl} y2={f4/sl} +.PARAM Vmin=2.99 Vmax=4.99 dCmax=330m +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((1-fbet)*(T0/Tref)**mubet+fbet)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={((q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2))/(1+rpara*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*((1-fbet)*(T0/Tref)**mubet+fbet))} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+dCmax*limit(dC,0,1)} + +.PARAM Cgs0={f3*a*dC1} +.PARAM Cgs1={f3a*a*dC1} + +.PARAM Cds1={qs6*a*dC1} +.PARAM Cds2={qs7*a*dC1} +.PARAM Cds3={q83*a*dC1} +.PARAM Cds5={qs1*a*dC1} +.PARAM Cds6={(a*qs2*(1+f2r/sqrt(a)))*dC1} +.PARAM Cds8={q80*a*dC1} + +.PARAM Cdg1={(a*ps1+pc0*sqrt(a))*dC2} +.PARAM Cdg2={ps3*a*dC2} +.PARAM Cdg3={(ps5*a+ps6)*dC2} +.PARAM Cdg4={f4*a*dC2} +.PARAM dRdi={Rdi/a} + +.FUNC Ue(g,y,w) {(g-Vth+auth*(w-Tref)+Fm*y**Fn)} +.FUNC Ue1(g,y,w) {Ue(g,y,w)+(1+limit(Ue(g,y,w)+dvx,0,1)**2*(2*limit(Ue(g,y,w)+dvx,0,1)-3))*(dvgs+(auth_sub-auth)*(w-Tref))} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ih(Uds,T,p,Uee) {bet*((1-fbet)*(T0/T)**mubet+fbet)*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jh(d,g,w,y,s,x) {a*((Ih(s*y+min(d,0),w,(p0+(p1+p2*w)*w)*kbq*w,Ue1(g,y,w))+exp(min(lB+(d-UB-ab*(w-Tref))/UT,24))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**n_Isj)} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} +.FUNC Q01(Uds) {a*(limit(Uds,x1,x2)*(q80-q82/2*limit(Uds,x1,x2))+min(Uds-x1,0)*q81-max(x1,0)*(q80-q81)/2)} +.FUNC Q02(Udg) {a*(limit(Udg,y1,y2)*(f4-sl/2*limit(Udg,y1,y2))+min(Udg-y1,0)*f5-max(y1,0)*(f4-f5)/2)} + +C_Cgs g s {Cgs0} +C_Cgs1 g sp {Cgs1} + +C_Cds1 d s {Cds1} +E_Eds3 d edep3 VALUE {V(d,s)-I(V_sense3)/Cds3} +C_Cds3 edep3 s {Cds3} +E_Eds2 d edep2 VALUE {if(qs8==0,0,V(d,s)-(exp(qs8*max(V(d,s),-1))-1)/min(qs8,-1u)-min(V(d,s)+1,0)*exp(-qs8))} +C_Cds2 edep2 s {Cds2} + +C_Cds5 d sp {Cds5} +E_Eds6 d edep6 VALUE {if(qs3==0,0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/min(qs3,-1u)-min(V(d,sp),0))} +C_Cds6 edep6 sp {Cds6} +E_Eds8 d edep8 VALUE {V(d,sp)-Q01(V(d,sp))/Cds8} +C_Cds8 edep8 sp {Cds8} + +E_Edg1 d ox1 VALUE {if(ps2==0,0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/min(ps2,-1u)-min(V(d,g),0))} +C_Cdg1 ox1 g {Cdg1} +E_Edg2 d ox2 VALUE = ++{if(ps4==0,0,V(d,g)-((exp(ps4*(max(V(d,g)+ps7,0)))-exp(ps4*max(ps7,0)))/min(ps4,-1u)+min(V(d,g)+max(ps7,0),max(0,-ps7))))} +C_Cdg2 ox2 g {Cdg2} +C_Cdg3 d g {Cdg3} +E_Edg4 d ox4 VALUE {V(d,g)-Q02(V(d,g))/Cdg4} +C_Cdg4 ox4 g {Cdg4} + +Rfp s sp {Rsp} + +G_chan d5a s VALUE={Jh(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*max(V(d5a,s),0))-1)/2/al,sgn(V(d5a,s)),0)} +Rd06 d5a d5 1u +V_sm d d5 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds3*((exp(q84*max(V(d,s),-1))-1)/min(q84,-1u)-min(V(d,s)+1,0)*exp(-q84))} +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+Pr(V(s,s0),V(s,sp))} + + +.ENDS + +********** + +.SUBCKT S5_100_e1_var dd g s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM b0=52 p0=7.92 p1=-29.8m p2=53u mubet=1.3 fbet=0 +.PARAM Vth0=3.99 c=1.5 Fm=150m Fn=500m al=500m auth=3.5m +.PARAM dvx=550m dvgs=0 auth_sub=3.5m + +.PARAM Rd=24.4m rpara=30u nmu=3.22 Rf=540m + +.PARAM lnIsj=-27.7 ndi=1.07 Rdi=5m nmu2=0 n_Isj=0 UB=107 +.PARAM ab=50m ab2=0 UT=100m lB=-23 td=30n ta=30n + +.PARAM kbq=85.8u Tref=298 T0=273 + +.PARAM f3=380p f3b=30p f3a=70p + +.PARAM f4=7.73p f5=4.49p sl=0.19p ps1=45p ps2=-1 ps3=60p +.PARAM ps4=-90m ps5=1.5p ps6=4p ps7=0 pc0=50p + +.PARAM q83=63p q84=-763m qs6=5p qs7=50p qs8=-38.2m + +.PARAM q80=96p q81=33.7p q82=1.92p qs1=35.2p qs2=80p qs3=-38.2m +.PARAM f2r=1.21 + +.PARAM x1={(q80-q81)/q82} x2={q80/q82} +.PARAM y1={(f4-f5)/sl} y2={f4/sl} +.PARAM Vmin=2.99 Vmax=4.99 dCmax=330m +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((1-fbet)*(T0/Tref)**mubet+fbet)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={((q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2))/(1+rpara*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*((1-fbet)*(T0/Tref)**mubet+fbet))} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+dCmax*limit(dC,0,1)} + +.PARAM Cgs0={(f3*a+sqrt(a)*f3b)*dC1} +.PARAM Cgs1={f3a*a*dC1} + +.PARAM Cds1={qs6*a*dC1} +.PARAM Cds2={qs7*a*dC1} +.PARAM Cds3={q83*a*dC1} +.PARAM Cds5={qs1*a*dC1} +.PARAM Cds6={(a*qs2*(1+f2r/sqrt(a)))*dC1} +.PARAM Cds8={q80*a*dC1} + +.PARAM Cdg1={(a*ps1+pc0*sqrt(a))*dC2} +.PARAM Cdg2={ps3*a*dC2} +.PARAM Cdg3={(ps5*a+ps6)*dC2} +.PARAM Cdg4={f4*a*dC2} +.PARAM dRdi={Rdi/a} + +.FUNC Ue(g,y,w) {(g-Vth+auth*(w-Tref)+Fm*y**Fn)} +.FUNC Ue1(g,y,w) {Ue(g,y,w)+(1+limit(Ue(g,y,w)+dvx,0,1)**2*(2*limit(Ue(g,y,w)+dvx,0,1)-3))*(dvgs+(auth_sub-auth)*(w-Tref))} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ih(Uds,T,p,Uee) {bet*((1-fbet)*(T0/T)**mubet+fbet)*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jh(d,g,w,y,s,x) {a*((Ih(s*y+min(d,0),w,(p0+(p1+p2*w)*w)*kbq*w,Ue1(g,y,w))+exp(min(lB+(d-UB-ab*(w-Tref))/UT,24))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**n_Isj)} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} +.FUNC Q01(Uds) {a*(limit(Uds,x1,x2)*(q80-q82/2*limit(Uds,x1,x2))+min(Uds-x1,0)*q81-max(x1,0)*(q80-q81)/2)} +.FUNC Q02(Udg) {a*(limit(Udg,y1,y2)*(f4-sl/2*limit(Udg,y1,y2))+min(Udg-y1,0)*f5-max(y1,0)*(f4-f5)/2)} + +C_Cgs g s {Cgs0} +C_Cgs1 g sp {Cgs1} + +C_Cds1 d s {Cds1} +E_Eds3 d edep3 VALUE {V(d,s)-I(V_sense3)/Cds3} +C_Cds3 edep3 s {Cds3} +E_Eds2 d edep2 VALUE {if(qs8==0,0,V(d,s)-(exp(qs8*max(V(d,s),-1))-1)/min(qs8,-1u)-min(V(d,s)+1,0)*exp(-qs8))} +C_Cds2 edep2 s {Cds2} + +C_Cds5 d sp {Cds5} +E_Eds6 d edep6 VALUE {if(qs3==0,0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/min(qs3,-1u)-min(V(d,sp),0))} +C_Cds6 edep6 sp {Cds6} +E_Eds8 d edep8 VALUE {V(d,sp)-Q01(V(d,sp))/Cds8} +C_Cds8 edep8 sp {Cds8} + +E_Edg1 d ox1 VALUE {if(ps2==0,0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/min(ps2,-1u)-min(V(d,g),0))} +C_Cdg1 ox1 g {Cdg1} +E_Edg2 d ox2 VALUE = ++{if(ps4==0,0,V(d,g)-((exp(ps4*(max(V(d,g)+ps7,0)))-exp(ps4*max(ps7,0)))/min(ps4,-1u)+min(V(d,g)+max(ps7,0),max(0,-ps7))))} +C_Cdg2 ox2 g {Cdg2} +C_Cdg3 d g {Cdg3} +E_Edg4 d ox4 VALUE {V(d,g)-Q02(V(d,g))/Cdg4} +C_Cdg4 ox4 g {Cdg4} + +Rfp s sp {Rsp} + +G_chan d5a s VALUE={Jh(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*max(V(d5a,s),0))-1)/2/al,sgn(V(d5a,s)),0)} +Rd06 d5a d5 1u +V_sm d d5 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds3*((exp(q84*max(V(d,s),-1))-1)/min(q84,-1u)-min(V(d,s)+1,0)*exp(-q84))} +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+Pr(V(s,s0),V(s,sp))} + + +.ENDS + + + + +.SUBCKT S5_100_f_var dd g s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM b0=52 p0=7.92 p1=-29.8m p2=53u mubet=1.3 fbet=0 +.PARAM Vth0=3.99 c=1.5 Fm=150m Fn=500m al=500m auth=3.5m +.PARAM dvx=550m dvgs=0 auth_sub=3.5m + +.PARAM Rd=25.2m rpara=30u nmu=3.12 Rf=540m + +.PARAM lnIsj=-27.7 ndi=1.07 Rdi=5m nmu2=0 n_Isj=0 UB=107 +.PARAM ab=50m ab2=0 UT=100m lB=-23 td=30n ta=30n + +.PARAM kbq=85.8u Tref=298 T0=273 + +.PARAM f3=357p f3a=70p + +.PARAM f4=7.73p f5=4.49p sl=0.19p ps1=40p ps2=-1 ps3=45.57p +.PARAM ps4=-76.6m ps5=1.8p ps6=2p ps7=0 pc0=25p + +.PARAM q83=63p q84=-763m qs6=5p qs7=50p qs8=-38.2m + +.PARAM q80=96p q81=33.7p q82=1.92p qs1=35.2p qs2=80p qs3=-38.2m +.PARAM f2r=1.21 + +.PARAM x1={(q80-q81)/q82} x2={q80/q82} +.PARAM y1={(f4-f5)/sl} y2={f4/sl} +.PARAM Vmin=2.99 Vmax=4.99 dCmax=330m +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((1-fbet)*(T0/Tref)**mubet+fbet)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={((q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2))/(1+rpara*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*((1-fbet)*(T0/Tref)**mubet+fbet))} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+dCmax*limit(dC,0,1)} + +.PARAM Cgs0={f3*a*dC1} +.PARAM Cgs1={f3a*a*dC1} + +.PARAM Cds1={qs6*a*dC1} +.PARAM Cds2={qs7*a*dC1} +.PARAM Cds3={q83*a*dC1} +.PARAM Cds5={qs1*a*dC1} +.PARAM Cds6={(a*qs2*(1+f2r/sqrt(a)))*dC1} +.PARAM Cds8={q80*a*dC1} + +.PARAM Cdg1={(a*ps1+pc0*sqrt(a))*dC2} +.PARAM Cdg2={ps3*a*dC2} +.PARAM Cdg3={(ps5*a+ps6)*dC2} +.PARAM Cdg4={f4*a*dC2} +.PARAM dRdi={Rdi/a} + +.FUNC Ue(g,y,w) {(g-Vth+auth*(w-Tref)+Fm*y**Fn)} +.FUNC Ue1(g,y,w) {Ue(g,y,w)+(1+limit(Ue(g,y,w)+dvx,0,1)**2*(2*limit(Ue(g,y,w)+dvx,0,1)-3))*(dvgs+(auth_sub-auth)*(w-Tref))} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ih(Uds,T,p,Uee) {bet*((1-fbet)*(T0/T)**mubet+fbet)*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jh(d,g,w,y,s,x) {a*((Ih(s*y+min(d,0),w,(p0+(p1+p2*w)*w)*kbq*w,Ue1(g,y,w))+exp(min(lB+(d-UB-ab*(w-Tref))/UT,24))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**n_Isj)} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} +.FUNC Q01(Uds) {a*(limit(Uds,x1,x2)*(q80-q82/2*limit(Uds,x1,x2))+min(Uds-x1,0)*q81-max(x1,0)*(q80-q81)/2)} +.FUNC Q02(Udg) {a*(limit(Udg,y1,y2)*(f4-sl/2*limit(Udg,y1,y2))+min(Udg-y1,0)*f5-max(y1,0)*(f4-f5)/2)} + +C_Cgs g s {Cgs0} +C_Cgs1 g sp {Cgs1} + +C_Cds1 d s {Cds1} +E_Eds3 d edep3 VALUE {V(d,s)-I(V_sense3)/Cds3} +C_Cds3 edep3 s {Cds3} +E_Eds2 d edep2 VALUE {if(qs8==0,0,V(d,s)-(exp(qs8*max(V(d,s),-1))-1)/min(qs8,-1u)-min(V(d,s)+1,0)*exp(-qs8))} +C_Cds2 edep2 s {Cds2} + +C_Cds5 d sp {Cds5} +E_Eds6 d edep6 VALUE {if(qs3==0,0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/min(qs3,-1u)-min(V(d,sp),0))} +C_Cds6 edep6 sp {Cds6} +E_Eds8 d edep8 VALUE {V(d,sp)-Q01(V(d,sp))/Cds8} +C_Cds8 edep8 sp {Cds8} + +E_Edg1 d ox1 VALUE {if(ps2==0,0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/min(ps2,-1u)-min(V(d,g),0))} +C_Cdg1 ox1 g {Cdg1} +E_Edg2 d ox2 VALUE = ++{if(ps4==0,0,V(d,g)-((exp(ps4*(max(V(d,g)+ps7,0)))-exp(ps4*max(ps7,0)))/min(ps4,-1u)+min(V(d,g)+max(ps7,0),max(0,-ps7))))} +C_Cdg2 ox2 g {Cdg2} +C_Cdg3 d g {Cdg3} +E_Edg4 d ox4 VALUE {V(d,g)-Q02(V(d,g))/Cdg4} +C_Cdg4 ox4 g {Cdg4} + +Rfp s sp {Rsp} + +G_chan d5a s VALUE={Jh(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*max(V(d5a,s),0))-1)/2/al,sgn(V(d5a,s)),0)} +Rd06 d5a d5 1u +V_sm d d5 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds3*((exp(q84*max(V(d,s),-1))-1)/min(q84,-1u)-min(V(d,s)+1,0)*exp(-q84))} +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+Pr(V(s,s0),V(s,sp))} + + +.ENDS + +******************* + +.SUBCKT S5_100_g_var dd g s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM b0=47 p0=5.13 p1=-15.4m p2=25u mubet=1.3 fbet=0 +.PARAM Vth0=2.35 c=1.5 Fm=150m Fn=500m al=500m auth=2.3m +.PARAM dvx=550m dvgs=0 auth_sub=3.5m + +.PARAM Rd=24.4m rpara=30u nmu=3.22 Rf=540m + +.PARAM lnIsj=-27.7 ndi=1.07 Rdi=5m nmu2=0 n_Isj=0 UB=107 +.PARAM ab=50m ab2=0 UT=100m lB=-23 td=30n ta=30n + +.PARAM kbq=85.8u Tref=298 T0=273 + +.PARAM f3=357p f3a=70p + +.PARAM f4=7.73p f5=4.49p sl=0.19p ps1=40p ps2=-1 ps3=45.57p +.PARAM ps4=-76.6m ps5=1.8p ps6=2p ps7=0 pc0=25p + +.PARAM q83=63p q84=-763m qs6=5p qs7=50p qs8=-38.2m + +.PARAM q80=96p q81=33.7p q82=1.92p qs1=35.2p qs2=80p qs3=-38.2m +.PARAM f2r=1.21 + +.PARAM x1={(q80-q81)/q82} x2={q80/q82} +.PARAM y1={(f4-f5)/sl} y2={f4/sl} +.PARAM Vmin=1.95 Vmax=2.75 dCmax=330m +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((1-fbet)*(T0/Tref)**mubet+fbet)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={((q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2))/(1+rpara*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*((1-fbet)*(T0/Tref)**mubet+fbet))} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+dCmax*limit(dC,0,1)} + +.PARAM Cgs0={f3*a*dC1} +.PARAM Cgs1={f3a*a*dC1} + +.PARAM Cds1={qs6*a*dC1} +.PARAM Cds2={qs7*a*dC1} +.PARAM Cds3={q83*a*dC1} +.PARAM Cds5={qs1*a*dC1} +.PARAM Cds6={(a*qs2*(1+f2r/sqrt(a)))*dC1} +.PARAM Cds8={q80*a*dC1} + +.PARAM Cdg1={(a*ps1+pc0*sqrt(a))*dC2} +.PARAM Cdg2={ps3*a*dC2} +.PARAM Cdg3={(ps5*a+ps6)*dC2} +.PARAM Cdg4={f4*a*dC2} +.PARAM dRdi={Rdi/a} + +.FUNC Ue(g,y,w) {(g-Vth+auth*(w-Tref)+Fm*y**Fn)} +.FUNC Ue1(g,y,w) {Ue(g,y,w)+(1+limit(Ue(g,y,w)+dvx,0,1)**2*(2*limit(Ue(g,y,w)+dvx,0,1)-3))*(dvgs+(auth_sub-auth)*(w-Tref))} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ih(Uds,T,p,Uee) {bet*((1-fbet)*(T0/T)**mubet+fbet)*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jh(d,g,w,y,s,x) {a*((Ih(s*y+min(d,0),w,(p0+(p1+p2*w)*w)*kbq*w,Ue1(g,y,w))+exp(min(lB+(d-UB-ab*(w-Tref))/UT,24))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**n_Isj)} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} +.FUNC Q01(Uds) {a*(limit(Uds,x1,x2)*(q80-q82/2*limit(Uds,x1,x2))+min(Uds-x1,0)*q81-max(x1,0)*(q80-q81)/2)} +.FUNC Q02(Udg) {a*(limit(Udg,y1,y2)*(f4-sl/2*limit(Udg,y1,y2))+min(Udg-y1,0)*f5-max(y1,0)*(f4-f5)/2)} + +C_Cgs g s {Cgs0} +C_Cgs1 g sp {Cgs1} + +C_Cds1 d s {Cds1} +E_Eds3 d edep3 VALUE {V(d,s)-I(V_sense3)/Cds3} +C_Cds3 edep3 s {Cds3} +E_Eds2 d edep2 VALUE {if(qs8==0,0,V(d,s)-(exp(qs8*max(V(d,s),-1))-1)/min(qs8,-1u)-min(V(d,s)+1,0)*exp(-qs8))} +C_Cds2 edep2 s {Cds2} + +C_Cds5 d sp {Cds5} +E_Eds6 d edep6 VALUE {if(qs3==0,0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/min(qs3,-1u)-min(V(d,sp),0))} +C_Cds6 edep6 sp {Cds6} +E_Eds8 d edep8 VALUE {V(d,sp)-Q01(V(d,sp))/Cds8} +C_Cds8 edep8 sp {Cds8} + +E_Edg1 d ox1 VALUE {if(ps2==0,0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/min(ps2,-1u)-min(V(d,g),0))} +C_Cdg1 ox1 g {Cdg1} +E_Edg2 d ox2 VALUE = ++{if(ps4==0,0,V(d,g)-((exp(ps4*(max(V(d,g)+ps7,0)))-exp(ps4*max(ps7,0)))/min(ps4,-1u)+min(V(d,g)+max(ps7,0),max(0,-ps7))))} +C_Cdg2 ox2 g {Cdg2} +C_Cdg3 d g {Cdg3} +E_Edg4 d ox4 VALUE {V(d,g)-Q02(V(d,g))/Cdg4} +C_Cdg4 ox4 g {Cdg4} + +Rfp s sp {Rsp} + +G_chan d5a s VALUE={Jh(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*max(V(d5a,s),0))-1)/2/al,sgn(V(d5a,s)),0)} +Rd06 d5a d5 1u +V_sm d d5 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds3*((exp(q84*max(V(d,s),-1))-1)/min(q84,-1u)-min(V(d,s)+1,0)*exp(-q84))} +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+Pr(V(s,s0),V(s,sp))} + + +.ENDS + +******************* + +.SUBCKT IPT015N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=241u Rg=1.5 Rd=20u Rm=103u +.PARAM Inn=150 Unn=10 Rmax=1.5m gmin=170.17 +.PARAM RRf=500m Rrbond=3m Rtb=2.6 g2=999m +.PARAM act=27.96 Rsp=0.54 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.17m+limit(Zthtype,0,1)*438.21u} +Rth2 t1 t2 {12.91m+limit(Zthtype,0,1)*4.77m} +Rth3 t2 t3 {28.45m+limit(Zthtype,0,1)*6.6m} +Rth4 t3 t4 {51.12m+limit(Zthtype,0,1)*50.06m} +Rth5 t4 Tcase {123.53m+limit(Zthtype,0,1)*120.96m} +Cth1 Tj 0 389.265u +Cth2 t1 0 883.264u +Cth3 t2 0 3.629m +Cth4 t3 0 4.927m +Cth5 t4 0 115m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPB017N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=414u Rg=1.3 Rd=20u Rm=140u +.PARAM Inn=100 Unn=10 Rmax=1.7m gmin=133 +.PARAM RRf=391m Rrbond=6m Rtb=3.8 g2=656m +.PARAM act=27.88 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.14m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.18m+limit(Zthtype,0,1)*432.82u} +Rth2 t1 t2 {12.94m+limit(Zthtype,0,1)*4.79m} +Rth3 t2 t3 {28.53m+limit(Zthtype,0,1)*6.62m} +Rth4 t3 t4 {63.5m+limit(Zthtype,0,1)*30m} +Rth5 t4 Tcase {171.15m+limit(Zthtype,0,1)*80.86m} +Cth1 Tj 0 388.151u +Cth2 t1 0 880.776u +Cth3 t2 0 3.619m +Cth4 t3 0 4.739m +Cth5 t4 0 139.566m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPB020N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=656u Rg=1.3 Rd=50u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2m gmin=125 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.88 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.18m+limit(Zthtype,0,1)*432.82u} +Rth2 t1 t2 {12.94m+limit(Zthtype,0,1)*4.79m} +Rth3 t2 t3 {28.53m+limit(Zthtype,0,1)*6.62m} +Rth4 t3 t4 {63.5m+limit(Zthtype,0,1)*30m} +Rth5 t4 Tcase {171.15m+limit(Zthtype,0,1)*80.86m} +Cth1 Tj 0 388.151u +Cth2 t1 0 880.776u +Cth3 t2 0 3.619m +Cth4 t3 0 4.739m +Cth5 t4 0 139.566m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP023N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=656u Rg=1.3 Rd=350u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2.3m gmin=125 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.88 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.18m+limit(Zthtype,0,1)*432.82u} +Rth2 t1 t2 {12.94m+limit(Zthtype,0,1)*4.79m} +Rth3 t2 t3 {28.53m+limit(Zthtype,0,1)*6.62m} +Rth4 t3 t4 {63.5m+limit(Zthtype,0,1)*30m} +Rth5 t4 Tcase {171.15m+limit(Zthtype,0,1)*80.86m} +Cth1 Tj 0 388.151u +Cth2 t1 0 880.776u +Cth3 t2 0 3.619m +Cth4 t3 0 4.739m +Cth5 t4 0 139.566m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPT020N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=194u Rg=1.2 Rd=20u Rm=56u + +.PARAM Inn=150 Unn=10 Rmax=2m gmin=234 +.PARAM RRf=500m Rrbond=3m Rtb=2.6 g2=999m +.PARAM act=20.15 Rsp=0.43 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.63m+limit(Zthtype,0,1)*601.76u} +Rth2 t1 t2 {17.81m+limit(Zthtype,0,1)*6.59m} +Rth3 t2 t3 {39.07m+limit(Zthtype,0,1)*9.19m} +Rth4 t3 t4 {70.94m+limit(Zthtype,0,1)*74.66m} +Rth5 t4 Tcase {160.54m+limit(Zthtype,0,1)*168.97m} +Cth1 Tj 0 280.533u +Cth2 t1 0 640.034u +Cth3 t2 0 2.649m +Cth4 t3 0 3.551m +Cth5 t4 0 88.605m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPB024N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=359u Rg=1.2 Rd=20u Rm=85u +.PARAM Inn=100 Unn=10 Rmax=2.4m gmin=111 +.PARAM RRf=391m Rrbond=6m Rtb=3.8 g2=656m +.PARAM act=18.3 Rsp=0.46 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.14m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.79m+limit(Zthtype,0,1)*666.49u} +Rth2 t1 t2 {19.58m+limit(Zthtype,0,1)*7.24m} +Rth3 t2 t3 {42.87m+limit(Zthtype,0,1)*10.14m} +Rth4 t3 t4 {96.75m+limit(Zthtype,0,1)*67.91m} +Rth5 t4 Tcase {207.45m+limit(Zthtype,0,1)*145.61m} +Cth1 Tj 0 254.777u +Cth2 t1 0 582.308u +Cth3 t2 0 2.415m +Cth4 t3 0 3.111m +Cth5 t4 0 102.055m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPB027N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=735u Rg=1.2 Rd=50u Rm=242u +.PARAM Inn=100 Unn=10 Rmax=2.7m gmin=103 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=18.3 Rsp=0.46 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.79m+limit(Zthtype,0,1)*666.49u} +Rth2 t1 t2 {19.58m+limit(Zthtype,0,1)*7.24m} +Rth3 t2 t3 {42.87m+limit(Zthtype,0,1)*10.14m} +Rth4 t3 t4 {96.75m+limit(Zthtype,0,1)*67.91m} +Rth5 t4 Tcase {207.45m+limit(Zthtype,0,1)*145.61m} +Cth1 Tj 0 254.777u +Cth2 t1 0 582.308u +Cth3 t2 0 2.415m +Cth4 t3 0 3.111m +Cth5 t4 0 102.055m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPT026N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=350u Rg=1.3 Rd=20u Rm=160u + +.PARAM Inn=150 Unn=10 Rmax=2.6m gmin=197 +.PARAM RRf=500m Rrbond=5m Rtb=3.6 g2=999m +.PARAM act=15.83 Rsp=0.54 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 9.75m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.07m+limit(Zthtype,0,1)*770.26u} +Rth2 t1 t2 {22.57m+limit(Zthtype,0,1)*8.35m} +Rth3 t2 t3 {49.3m+limit(Zthtype,0,1)*11.73m} +Rth4 t3 t4 {90.29m+limit(Zthtype,0,1)*104.28m} +Rth5 t4 Tcase {190.56m+limit(Zthtype,0,1)*220.08m} +Cth1 Tj 0 220.389u +Cth2 t1 0 505.148u +Cth3 t2 0 2.103m +Cth4 t3 0 2.79m +Cth5 t4 0 62.518m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPB032N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=411u Rg=1.3 Rd=50u Rm=87u + +.PARAM Inn=83 Unn=10 Rmax=3.2m gmin=84 +.PARAM RRf=431m Rrbond=9m Rtb=4.7 g2=705m +.PARAM act=12.47 Rsp=0.44 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.17m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.63m+limit(Zthtype,0,1)*976.07u} +Rth2 t1 t2 {28.5m+limit(Zthtype,0,1)*10.55m} +Rth3 t2 t3 {61.98m+limit(Zthtype,0,1)*14.95m} +Rth4 t3 t4 {141.98m+limit(Zthtype,0,1)*105.74m} +Rth5 t4 Tcase {248m+limit(Zthtype,0,1)*184.7m} +Cth1 Tj 0 173.61u +Cth2 t1 0 399.981u +Cth3 t2 0 1.676m +Cth4 t3 0 2.12m +Cth5 t4 0 79.888m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP030N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=735u Rg=1.2 Rd=350u Rm=242u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=103 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=18.3 Rsp=0.46 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.79m+limit(Zthtype,0,1)*666.49u} +Rth2 t1 t2 {19.58m+limit(Zthtype,0,1)*7.24m} +Rth3 t2 t3 {42.87m+limit(Zthtype,0,1)*10.14m} +Rth4 t3 t4 {96.75m+limit(Zthtype,0,1)*67.91m} +Rth5 t4 Tcase {207.45m+limit(Zthtype,0,1)*145.61m} +Cth1 Tj 0 254.777u +Cth2 t1 0 582.308u +Cth3 t2 0 2.415m +Cth4 t3 0 3.111m +Cth5 t4 0 102.055m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPP039N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=565u Rg=1.4 Rd=350u Rm=87u +.PARAM Inn=50 Unn=10 Rmax=3.9m gmin=64.6 +.PARAM RRf=332m Rrbond=10m Rtb=5 g2=718m +.PARAM act=12.47 Rsp=0.44 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.61m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.63m+limit(Zthtype,0,1)*976.07u} +Rth2 t1 t2 {28.5m+limit(Zthtype,0,1)*10.55m} +Rth3 t2 t3 {61.98m+limit(Zthtype,0,1)*14.95m} +Rth4 t3 t4 {141.98m+limit(Zthtype,0,1)*105.74m} +Rth5 t4 Tcase {248m+limit(Zthtype,0,1)*184.7m} +Cth1 Tj 0 173.61u +Cth2 t1 0 399.981u +Cth3 t2 0 1.676m +Cth4 t3 0 2.12m +Cth5 t4 0 79.888m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPA050N10NM5S drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1.2 Rd=350u Rm=249u + +.PARAM Inn=80 Unn=10 Rmax=5.2m gmin=63.95 +.PARAM RRf=449m Rrbond=34m Rtb=9.1 g2=822m +.PARAM act=8.35 Rsp=0.7 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.15m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.93m+limit(Zthtype,0,1)*1.45m} +Rth2 t1 t2 {42.13m+limit(Zthtype,0,1)*15.6m} +Rth3 t2 t3 {90.82m+limit(Zthtype,0,1)*22.5m} +Rth4 t3 t4 {933.57m+limit(Zthtype,0,1)*543.43m} +Rth5 t4 Tcase {1.42+limit(Zthtype,0,1)*826.57m} +Cth1 Tj 0 116.251u +Cth2 t1 0 270.556u +Cth3 t2 0 1.148m +Cth4 t3 0 8.663m +Cth5 t4 0 754.984m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPD050N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=785u Rg=1.2 Rd=20u Rm=306u +.PARAM Inn=40 Unn=10 Rmax=5m gmin=46.5 +.PARAM RRf=390m Rrbond=12m Rtb=5.5 g2=758m +.PARAM act=8.35 Rsp=0.7 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.71m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.93m+limit(Zthtype,0,1)*1.45m} +Rth2 t1 t2 {42.13m+limit(Zthtype,0,1)*15.6m} +Rth3 t2 t3 {90.82m+limit(Zthtype,0,1)*22.5m} +Rth4 t3 t4 {171.18m+limit(Zthtype,0,1)*140.57m} +Rth5 t4 Tcase {281.03m+limit(Zthtype,0,1)*230.79m} +Cth1 Tj 0 116.251u +Cth2 t1 0 270.556u +Cth3 t2 0 1.148m +Cth4 t3 0 1.471m +Cth5 t4 0 34.98m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP083N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=75 Unn=10 Rmax=8.3m gmin=48.84 +.PARAM RRf=449m Rrbond=34m Rtb=9.1 g2=822m +.PARAM act=4.936 Rsp=0.43 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.15m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {149.01m+limit(Zthtype,0,1)*38.49m} +Rth4 t3 t4 {312.72m+limit(Zthtype,0,1)*227.66m} +Rth5 t4 Tcase {385.98m+limit(Zthtype,0,1)*280.99m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 704.871u +Cth4 t3 0 839.046u +Cth5 t4 0 49.922m +Cth6 Tcase 0 220m + +.ENDS + +********** + +.SUBCKT IPA083N10N5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=44 Unn=10 Rmax=8.3m gmin=37.82 +.PARAM RRf=449m Rrbond=34m Rtb=9.1 g2=822m +.PARAM act=4.936 Rsp=0.43 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.15m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {149.01m+limit(Zthtype,0,1)*38.49m} +Rth4 t3 t4 {1.1+limit(Zthtype,0,1)*585.52m} +Rth5 t4 Tcase {1.45+limit(Zthtype,0,1)*771.83m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 704.871u +Cth4 t3 0 3.059m +Cth5 t4 0 584.338m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT IPA083N10NM5S drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u + +.PARAM Inn=44 Unn=10 Rmax=8.3m gmin=37.82 +.PARAM RRf=449m Rrbond=34m Rtb=9.1 g2=822m +.PARAM act=4.936 Rsp=0.43 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 6.15m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {149.01m+limit(Zthtype,0,1)*38.49m} +Rth4 t3 t4 {1.1+limit(Zthtype,0,1)*585.52m} +Rth5 t4 Tcase {1.45+limit(Zthtype,0,1)*771.83m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 704.871u +Cth4 t3 0 3.059m +Cth5 t4 0 584.338m +Cth6 Tcase 0 100m + +.ENDS + +********** + +.SUBCKT BSC027N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=159u Rg=1.7 Rd=20u Rm=36u +.PARAM Inn=50 Unn=10 Rmax=2.7m gmin=75 + +.PARAM act=14.62 Rsp=0.78 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {2.24m+limit(Zthtype,0,1)*835.36u} +Rth2 t1 t2 {24.39m+limit(Zthtype,0,1)*9.03m} +Rth3 t2 t3 {40.53m+limit(Zthtype,0,1)*7.53m} +Rth4 t3 t4 {97.77m+limit(Zthtype,0,1)*103.65m} +Rth5 t4 Tcase {200.97m+limit(Zthtype,0,1)*213.06m} +Cth1 Tj 0 203.543u +Cth2 t1 0 467.306u +Cth3 t2 0 1.467m +Cth4 t3 0 2.576m +Cth5 t4 0 56.903m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC035N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=412u Rg=1.5 Rd=20u Rm=241u +.PARAM Inn=50 Unn=10 Rmax=3.5m gmin=64 + +.PARAM act=11.52 Rsp=0.65 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {2.85m+limit(Zthtype,0,1)*1.05m} +Rth2 t1 t2 {30.79m+limit(Zthtype,0,1)*11.4m} +Rth3 t2 t3 {38.92m+limit(Zthtype,0,1)*4.75m} +Rth4 t3 t4 {124.08m+limit(Zthtype,0,1)*122.28m} +Rth5 t4 Tcase {233.64m+limit(Zthtype,0,1)*230.24m} +Cth1 Tj 0 160.384u +Cth2 t1 0 370.193u +Cth3 t2 0 891.859u +Cth4 t3 0 2.03m +Cth5 t4 0 44.789m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC040N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=373u Rg=1.3 Rd=20u Rm=202u +.PARAM Inn=50 Unn=10 Rmax=4m gmin=59 + +.PARAM act=9.46 Rsp=0.57 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {3.47m+limit(Zthtype,0,1)*1.28m} +Rth2 t1 t2 {37.31m+limit(Zthtype,0,1)*13.81m} +Rth3 t2 t3 {47.14m+limit(Zthtype,0,1)*5.84m} +Rth4 t3 t4 {151.09m+limit(Zthtype,0,1)*138.11m} +Rth5 t4 Tcase {262.24m+limit(Zthtype,0,1)*239.71m} +Cth1 Tj 0 131.704u +Cth2 t1 0 305.492u +Cth3 t2 0 737.321u +Cth4 t3 0 1.667m +Cth5 t4 0 38.161m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC040N10NS5SC drain gate source Tj Ttop Tbottom PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=122u Rg=1.3 Rd=10u Rm=14u + +.PARAM Inn=50 Unn=10 Rmax=4m gmin=59 +.PARAM act=9.46 Rsp=0.57 + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +Rth1 Tj t1 {3.47m+limit(Zthtype,0,1)*1.28m} +Rth2 t1 t2 {37.31m+limit(Zthtype,0,1)*13.81m} +Rth3 t2 t3 {47.14m+limit(Zthtype,0,1)*5.84m} +Rth4 t3 t4 {151.09m+limit(Zthtype,0,1)*138.11m} +Rth5 t4 Tbottom {262.23m+limit(Zthtype,0,1)*239.71m} +Cth1 Tj 0 131.7u +Cth2 t1 0 305.49u +Cth3 t2 0 737.32u +Cth4 t3 0 1.67m +Cth5 t4 0 38.16m +Cth6 Tbottom 0 30m +Rth1t Tj tt1 {233.64m+limit(Zthtype,0,1)*154.95m} +Rth2t tt1 tt2 {87.8m+limit(Zthtype,0,1)*154.95m} +Rth3t tt2 Ttop {69.01m+limit(Zthtype,0,1)*159.65m} +Cth1t tt1 0 1.18m +Cth2t tt2 0 2.63m +Cth3t Ttop 0 3.87m + +.ENDS + +********** + +.SUBCKT BSC050N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=342u Rg=1.2 Rd=20u Rm=171u + +.PARAM Inn=50 Unn=10 Rmax=5m gmin=52 +.PARAM RRf=-23m Rrbond=1m Rtb=1.8 g2=459m +.PARAM act=7.204 Rsp=0.52 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_e1_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.21m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.56m+limit(Zthtype,0,1)*1.68m} +Rth2 t1 t2 {48.63m+limit(Zthtype,0,1)*18m} +Rth3 t2 t3 {61.38m+limit(Zthtype,0,1)*7.81m} +Rth4 t3 t4 {198.41m+limit(Zthtype,0,1)*180.01m} +Rth5 t4 Tcase {303.85m+limit(Zthtype,0,1)*275.67m} +Cth1 Tj 0 100.296u +Cth2 t1 0 234.418u +Cth3 t2 0 567.368u +Cth4 t3 0 1.269m +Cth5 t4 0 31.969m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC070N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1 Rd=20u Rm=200u +.PARAM Inn=40 Unn=10 Rmax=7m gmin=39 + +.PARAM act=4.936 Rsp=0.43 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {88.37m+limit(Zthtype,0,1)*11.73m} +Rth4 t3 t4 {289.58m+limit(Zthtype,0,1)*283.82m} +Rth5 t4 Tcase {364.3m+limit(Zthtype,0,1)*357.05m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 395.377u +Cth4 t3 0 869.817u +Cth5 t4 0 26.98m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC098N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1.2 Rd=20u Rm=200u +.PARAM Inn=50 Unn=10 Rmax=9.8m gmin=37 + +.PARAM act=3.613 Rsp=0.57 + + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {9.08m+limit(Zthtype,0,1)*3.36m} +Rth2 t1 t2 {94.62m+limit(Zthtype,0,1)*35.02m} +Rth3 t2 t3 {119.14m+limit(Zthtype,0,1)*16.46m} +Rth4 t3 t4 {395.61m+limit(Zthtype,0,1)*347.83m} +Rth5 t4 Tcase {414.47m+limit(Zthtype,0,1)*364.41m} +Cth1 Tj 0 50.301u +Cth2 t1 0 120.478u +Cth3 t2 0 294.201u +Cth4 t3 0 636.679u +Cth5 t4 0 25.18m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ097N10NS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=534u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=20 Unn=10 Rmax=9.7m gmin=23 +.PARAM RRf=498m Rrbond=17m Rtb=6.5 g2=958m +.PARAM act=3.613 Rsp=0.57 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.08m+limit(Zthtype,0,1)*3.36m} +Rth2 t1 t2 {94.62m+limit(Zthtype,0,1)*35.02m} +Rth3 t2 t3 {119.14m+limit(Zthtype,0,1)*16.46m} +Rth4 t3 t4 {395.61m+limit(Zthtype,0,1)*347.83m} +Rth5 t4 Tcase {414.47m+limit(Zthtype,0,1)*364.41m} +Cth1 Tj 0 50.301u +Cth2 t1 0 120.478u +Cth3 t2 0 294.201u +Cth4 t3 0 636.679u +Cth5 t4 0 25.18m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT BSC034N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=412u Rg=1.5 Rd=20u Rm=241u +.PARAM Inn=50 Unn=10 Rmax=3.4m gmin=61.09 + +.PARAM act=11.52 Rsp=0.65 + + + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {2.85m+limit(Zthtype,0,1)*1.05m} +Rth2 t1 t2 {30.79m+limit(Zthtype,0,1)*11.4m} +Rth3 t2 t3 {38.92m+limit(Zthtype,0,1)*4.75m} +Rth4 t3 t4 {124.08m+limit(Zthtype,0,1)*122.28m} +Rth5 t4 Tcase {233.64m+limit(Zthtype,0,1)*230.24m} +Cth1 Tj 0 160.384u +Cth2 t1 0 370.193u +Cth3 t2 0 891.859u +Cth4 t3 0 2.03m +Cth5 t4 0 44.789m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC070N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=367u Rg=1 Rd=10u Rm=200u + +.PARAM Inn=40 Unn=10 Rmax=7m gmin=36 +.PARAM act=4.936 Rsp=0.43 + + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {88.37m+limit(Zthtype,0,1)*11.73m} +Rth4 t3 t4 {289.58m+limit(Zthtype,0,1)*283.82m} +Rth5 t4 Tcase {364.3m+limit(Zthtype,0,1)*357.05m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.619u +Cth3 t2 0 395.377u +Cth4 t3 0 869.817u +Cth5 t4 0 26.98m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC070N10NS5SC drain gate source Tj Ttop Tbottom PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=140u Rg=1 Rd=10u Rm=32u + +.PARAM Inn=40 Unn=10 Rmax=7m gmin=39 +.PARAM act=4.936 Rsp=0.43 + + +X1 d1 g s sp Tj S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +Rth1 Tj t1 {6.65m+limit(Zthtype,0,1)*2.46m} +Rth2 t1 t2 {70.1m+limit(Zthtype,0,1)*25.94m} +Rth3 t2 t3 {88.37m+limit(Zthtype,0,1)*11.73m} +Rth4 t3 t4 {289.58m+limit(Zthtype,0,1)*283.82m} +Rth5 t4 Tbottom {364.3m+limit(Zthtype,0,1)*357.05m} +Cth1 Tj 0 68.72u +Cth2 t1 0 162.62u +Cth3 t2 0 395.38u +Cth4 t3 0 869.82u +Cth5 t4 0 26.98m +Cth6 Tbottom 0 30m +Rth1t Tj tt1 {462.96m+limit(Zthtype,0,1)*216.41m} +Rth2t tt1 tt2 {169.4m+limit(Zthtype,0,1)*216.41m} +Rth3t tt2 Ttop {111.84m+limit(Zthtype,0,1)*222.97m} +Cth1t tt1 0 596.7u +Cth2t tt2 0 1.42m +Cth3t Ttop 0 2.83m + +.ENDS + +********** + +.SUBCKT BSC096N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=375u Rg=1.2 Rd=10u Rm=173u + +.PARAM Inn=50 Unn=10 Rmax=9.6m gmin=35 +.PARAM act=3.613 Rsp=0.57 + + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +Rth1 Tj t1 {9.08m+limit(Zthtype,0,1)*3.36m} +Rth2 t1 t2 {94.62m+limit(Zthtype,0,1)*35.02m} +Rth3 t2 t3 {119.14m+limit(Zthtype,0,1)*16.46m} +Rth4 t3 t4 {395.61m+limit(Zthtype,0,1)*347.83m} +Rth5 t4 Tcase {414.47m+limit(Zthtype,0,1)*364.41m} +Cth1 Tj 0 50.301u +Cth2 t1 0 120.478u +Cth3 t2 0 294.201u +Cth4 t3 0 636.679u +Cth5 t4 0 25.18m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ096N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=534u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=20 Unn=10 Rmax=9.6m gmin=22 +.PARAM RRf=498m Rrbond=17m Rtb=6.5 g2=958m +.PARAM act=3.613 Rsp=0.57 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {9.08m+limit(Zthtype,0,1)*3.36m} +Rth2 t1 t2 {94.62m+limit(Zthtype,0,1)*35.02m} +Rth3 t2 t3 {119.14m+limit(Zthtype,0,1)*16.46m} +Rth4 t3 t4 {395.61m+limit(Zthtype,0,1)*347.83m} +Rth5 t4 Tcase {414.47m+limit(Zthtype,0,1)*364.41m} +Cth1 Tj 0 50.301u +Cth2 t1 0 120.478u +Cth3 t2 0 294.201u +Cth4 t3 0 636.679u +Cth5 t4 0 25.18m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT BSC146N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1 Rd=20u Rm=200u +.PARAM Inn=20 Unn=10 Rmax=14.6m gmin=17.99 + +.PARAM act=2.345 Rsp=0.57 + + + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + + + + +Rth1 Tj t1 {14m+limit(Zthtype,0,1)*5.17m} +Rth2 t1 t2 {142.9m+limit(Zthtype,0,1)*52.88m} +Rth3 t2 t3 {179.63m+limit(Zthtype,0,1)*26.41m} +Rth4 t3 t4 {609.53m+limit(Zthtype,0,1)*499.43m} +Rth5 t4 Tcase {478.22m+limit(Zthtype,0,1)*391.83m} +Cth1 Tj 0 32.648u +Cth2 t1 0 79.775u +Cth3 t2 0 196.207u +Cth4 t3 0 413.234u +Cth5 t4 0 26.687m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSZ146N10LS5 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=608u Rg=1 Rd=20u Rm=245u +.PARAM Inn=20 Unn=10 Rmax=14.6m gmin=18 +.PARAM RRf=498m Rrbond=17m Rtb=6.5 g2=958m +.PARAM act=2.345 Rsp=0.57 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.97m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {14m+limit(Zthtype,0,1)*5.17m} +Rth2 t1 t2 {142.9m+limit(Zthtype,0,1)*52.88m} +Rth3 t2 t3 {179.63m+limit(Zthtype,0,1)*26.41m} +Rth4 t3 t4 {609.53m+limit(Zthtype,0,1)*499.43m} +Rth5 t4 Tcase {478.22m+limit(Zthtype,0,1)*391.83m} +Cth1 Tj 0 32.648u +Cth2 t1 0 79.775u +Cth3 t2 0 196.207u +Cth4 t3 0 413.234u +Cth5 t4 0 26.687m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT IRL100HS121 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=2.25m Rg=0.9 Rd=20u Rm=257u +.PARAM Inn=6.7 Unn=10 Rmax=42m gmin=6.43 +.PARAM RRf=500m Rrbond=985m Rtb=62.7 g2=996m +.PARAM act=0.882 Rsp=1.1 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s sp Tj S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 38.04u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {37.21m+limit(Zthtype,0,1)*13.77m} +Rth2 t1 t2 {356.54m+limit(Zthtype,0,1)*131.95m} +Rth3 t2 t3 {446.45m+limit(Zthtype,0,1)*78.89m} +Rth4 t3 t4 {1.62+limit(Zthtype,0,1)*7.45} +Rth5 t4 Tcase {512.41m+limit(Zthtype,0,1)*2.36} +Cth1 Tj 0 12.279u +Cth2 t1 0 31.973u +Cth3 t2 0 80.397u +Cth4 t3 0 155.425u +Cth5 t4 0 3m +Cth6 Tcase 0 10m + +.ENDS + +********** + +.SUBCKT IPT015N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=241u Rg=1.5 Rd=20u Rm=103u +.PARAM Inn=150 Unn=10 Rmax=1.5m gmin=170.17 +.PARAM act=27.96 Rsp=0.54 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB017N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=414u Rg=1.3 Rd=20u Rm=140u +.PARAM Inn=100 Unn=10 Rmax=1.7m gmin=133 +.PARAM act=27.88 Rsp=0.47 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB020N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=656u Rg=1.3 Rd=50u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2m gmin=125 +.PARAM act=27.88 Rsp=0.47 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP023N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=656u Rg=1.3 Rd=350u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2.3m gmin=125 +.PARAM act=27.88 Rsp=0.47 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPT020N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=194u Rg=1.2 Rd=20u Rm=56u +.PARAM Inn=150 Unn=10 Rmax=2m gmin=234 +.PARAM act=20.15 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB024N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=359u Rg=1.2 Rd=20u Rm=85u +.PARAM Inn=100 Unn=10 Rmax=2.4m gmin=111 +.PARAM act=18.3 Rsp=0.46 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB027N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=735u Rg=1.2 Rd=50u Rm=242u +.PARAM Inn=100 Unn=10 Rmax=2.7m gmin=103 +.PARAM act=18.3 Rsp=0.46 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPT026N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=2n Lg=3n + +.PARAM Rs=350u Rg=1.3 Rd=20u Rm=160u +.PARAM Inn=150 Unn=10 Rmax=2.6m gmin=197 +.PARAM act=15.83 Rsp=0.54 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB032N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=411u Rg=1.3 Rd=50u Rm=87u +.PARAM Inn=83 Unn=10 Rmax=3.2m gmin=84 +.PARAM act=12.47 Rsp=0.44 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP030N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=735u Rg=1.2 Rd=350u Rm=242u +.PARAM Inn=100 Unn=10 Rmax=3m gmin=103 +.PARAM act=18.3 Rsp=0.46 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP039N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=2.5n Lg=4n + +.PARAM Rs=565u Rg=1.4 Rd=350u Rm=87u +.PARAM Inn=50 Unn=10 Rmax=3.9m gmin=64.6 +.PARAM act=12.47 Rsp=0.44 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA050N10NM5S_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1.2 Rd=350u Rm=249u +.PARAM Inn=80 Unn=10 Rmax=5.2m gmin=63.95 +.PARAM act=8.35 Rsp=0.7 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD050N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=1n Lg=3n + +.PARAM Rs=785u Rg=1.2 Rd=20u Rm=306u +.PARAM Inn=40 Unn=10 Rmax=5m gmin=46.5 +.PARAM act=8.35 Rsp=0.7 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP083N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=75 Unn=10 Rmax=8.3m gmin=48.84 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA083N10N5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=44 Unn=10 Rmax=8.3m gmin=37.82 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPA083N10NM5S_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=939u Rg=1 Rd=350u Rm=249u +.PARAM Inn=44 Unn=10 Rmax=8.3m gmin=37.82 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_f_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC027N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=159u Rg=1.7 Rd=20u Rm=36u +.PARAM Inn=50 Unn=10 Rmax=2.7m gmin=75 +.PARAM act=14.62 Rsp=0.78 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC035N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=412u Rg=1.5 Rd=20u Rm=241u +.PARAM Inn=50 Unn=10 Rmax=3.5m gmin=64 +.PARAM act=11.52 Rsp=0.65 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC040N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=373u Rg=1.3 Rd=20u Rm=202u +.PARAM Inn=50 Unn=10 Rmax=4m gmin=59 +.PARAM act=9.46 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC040N10NS5SC_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=122u Rg=1.3 Rd=10u Rm=14u +.PARAM Inn=50 Unn=10 Rmax=4m gmin=59 +.PARAM act=9.46 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC050N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=342u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=50 Unn=10 Rmax=5m gmin=52 +.PARAM act=7.204 Rsp=0.52 + +X1 d1 g s sp Tj1 S5_100_e1_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC070N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1 Rd=20u Rm=200u +.PARAM Inn=40 Unn=10 Rmax=7m gmin=39 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC098N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1.2 Rd=20u Rm=200u +.PARAM Inn=50 Unn=10 Rmax=9.8m gmin=37 +.PARAM act=3.613 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ097N10NS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=534u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=20 Unn=10 Rmax=9.7m gmin=23 +.PARAM act=3.613 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC034N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=412u Rg=1.5 Rd=20u Rm=241u +.PARAM Inn=50 Unn=10 Rmax=3.4m gmin=61.09 +.PARAM act=11.52 Rsp=0.65 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC070N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=367u Rg=1 Rd=10u Rm=200u +.PARAM Inn=40 Unn=10 Rmax=7m gmin=36 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC070N10NS5SC_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=300p Ld=1n Lg=3n + +.PARAM Rs=140u Rg=1 Rd=10u Rm=32u +.PARAM Inn=40 Unn=10 Rmax=7m gmin=39 +.PARAM act=4.936 Rsp=0.43 + +X1 d1 g s sp Tj1 S5_100_e_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC096N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=375u Rg=1.2 Rd=10u Rm=173u +.PARAM Inn=50 Unn=10 Rmax=9.6m gmin=35 +.PARAM act=3.613 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} ++Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ096N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=534u Rg=1.2 Rd=20u Rm=171u +.PARAM Inn=20 Unn=10 Rmax=9.6m gmin=22 +.PARAM act=3.613 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC146N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=371u Rg=1 Rd=20u Rm=200u +.PARAM Inn=20 Unn=10 Rmax=14.6m gmin=17.99 +.PARAM act=2.345 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT BSZ146N10LS5_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=608u Rg=1 Rd=20u Rm=245u +.PARAM Inn=20 Unn=10 Rmax=14.6m gmin=18 +.PARAM act=2.345 Rsp=0.57 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IRL100HS121_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=0.3n Ld=1n Lg=3n + +.PARAM Rs=2.25m Rg=0.9 Rd=20u Rm=257u +.PARAM Inn=6.7 Unn=10 Rmax=42m gmin=6.43 +.PARAM act=0.882 Rsp=1.1 + +X1 d1 g s sp Tj1 S5_100_g_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE ={V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(g,g1)*V(g,g1)/Rg+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R2 w 0 1u + +.ENDS + +********** + +.SUBCKT IPT015N10N5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 241u TC=3m + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1034.5 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 0.94m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=3.36n VJ=2.5V) +Rsp s2 s3 0.54 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=12.8n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=119.9p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.22m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.08n +.MODEL DGD D(M=0.55 CJO=3.08n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.94n + +.ENDS IPT015N10N5_L0 + +****** + +.SUBCKT IPB017N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 414u TC=3m + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1031.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 0.95m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=3.35n VJ=2.5V) +Rsp s2 s3 0.47 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=12.77n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=119.6p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.22m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.07n +.MODEL DGD D(M=0.55 CJO=3.07n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.9n + +.ENDS IPB017N10N5_L0 + +****** + +.SUBCKT IPB020N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 656u TC=3m + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1031.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 0.98m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=3.35n VJ=2.5V) +Rsp s2 s3 0.47 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=12.77n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=119.6p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.22m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.07n +.MODEL DGD D(M=0.55 CJO=3.07n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.9n + +.ENDS IPB020N10N5_L0 + +***************** + +.SUBCKT IPT020N10N5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 2n +Ls source s1 1.5n +Rs s1 s2 194u TC=3m + +Rg g1 g2 1.2 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=745.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.3m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=2.42n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=9.36n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=86.4p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.3m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.22n +.MODEL DGD D(M=0.55 CJO=2.22n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.6n + +.ENDS IPT020N10N5_L0 + +***************** + +.SUBCKT IPP023N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 656u TC=3m + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1031.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.28m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=3.35n VJ=2.5V) +Rsp s2 s3 0.47 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=12.77n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=119.6p N=1.12 RS=0.02u EG=1.12 TT=20n) +Rdiode d1 21 0.22m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.07n +.MODEL DGD D(M=0.55 CJO=3.07n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.9n + +.ENDS IPP023N10N5_L0 + +****** + +.SUBCKT IPB024N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 359u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 677.1 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.43m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=2.2n VJ=2.5V) +Rsp s2 s3 0.46 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=8.54n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=78.5p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.33m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.01n +.MODEL DGD D(M=0.55 CJO=2.01n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 7.81n + +.ENDS IPB024N10N5_L0 + + +***************** + +.SUBCKT IPT026N10N5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 2n +Ls source s1 1.5n +Rs s1 s2 350u TC=3m + +Rg g1 g2 1.3 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=585.7 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.65m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.9n VJ=2.5V) +Rsp s2 s3 0.54 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=7.44n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=67.9p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.39m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.74n +.MODEL DGD D(M=0.55 CJO=1.74n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.76n + +.ENDS IPT026N10N5_L0 + +***************** + +.SUBCKT IPB027N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 735u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 677.1 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.46m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=2.2n VJ=2.5V) +Rsp s2 s3 0.46 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=8.54n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=78.5p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.33m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.01n +.MODEL DGD D(M=0.55 CJO=2.01n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 7.81n + +.ENDS IPB027N10N5_L0 + +****** + +.SUBCKT IPB032N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 1.8n +Rs s1 s2 411u TC=3m + +Rg g1 g2 1.3 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=461.4 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.12m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.5n VJ=2.5V) +Rsp s2 s3 0.44 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=5.94n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=53.5p N=1.12 RS=0.04u EG=1.12 TT=20n) +Rdiode d1 21 0.49m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.37n +.MODEL DGD D(M=0.55 CJO=1.37n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 5.32n + +.ENDS IPB032N10N5_L0 + +***************** + +.SUBCKT IPP030N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 735u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 677.1 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.76m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=2.2n VJ=2.5V) +Rsp s2 s3 0.46 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=8.54n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=78.5p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.33m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.01n +.MODEL DGD D(M=0.55 CJO=2.01n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 7.81n + +.ENDS IPP030N10N5_L0 + +****** + +.SUBCKT IPP039N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 1.8n +Rs s1 s2 565u TC=3m + +Rg g1 g2 1.4 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 461.4 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.42m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.5n VJ=2.5V) +Rsp s2 s3 0.44 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=5.94n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=53.5p N=1.12 RS=0.04u EG=1.12 TT=20n) +Rdiode d1 21 0.49m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.37n +.MODEL DGD D(M=0.55 CJO=1.37n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 5.32n + +.ENDS IPP039N10N5_L0 + +****** + +.SUBCKT IPA050N10NM5S_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 939u TC=3m + +Rg g1 g2 1.2 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=309 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 3.44m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1n VJ=2.5V) +Rsp s2 s3 0.7 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=4.08n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=35.8p N=1.12 RS=0.06u EG=1.12 TT=20n) +Rdiode d1 21 0.73m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.92n +.MODEL DGD D(M=0.55 CJO=0.92n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.57n + +.ENDS IPA050N10NM5S_L0 + +***************** + +.SUBCKT IPD050N10N5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 1.5n +Rs s1 s2 785u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 309 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 3.11m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1n VJ=2.5V) +Rsp s2 s3 0.7 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=4.08n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=35.8p N=1.12 RS=0.06u EG=1.12 TT=20n) +Rdiode d1 21 0.73m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.92n +.MODEL DGD D(M=0.55 CJO=0.92n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.57n + +.ENDS IPD050N10N5_L0 + +****** + +.SUBCKT IPP083N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 939u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.58m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS IPP083N10N5_L0 + +****** + +.SUBCKT IPA083N10N5_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 939u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.58m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS IPA083N10N5_L0 + +****** + +.SUBCKT IPA083N10NM5S_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2.5n +Ls source s1 2n +Rs s1 s2 939u TC=3m + +Rg g1 g2 1 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.58m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS IPA083N10NM5S_L0 + +***************** + +.SUBCKT BSC027N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 159u TC=3m + +Rg g1 g2 1.7 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 540.9 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 1.73m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.75n VJ=2.5V) +Rsp s2 s3 0.78 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=6.91n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=62.7p N=1.12 RS=0.03u EG=1.12 TT=20n) +Rdiode d1 21 0.42m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.61n +.MODEL DGD D(M=0.55 CJO=1.61n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.24n + +.ENDS BSC027N10NS5_L0 + +****** + +.SUBCKT BSC035N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 412u TC=3m + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 426.2 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.19m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.38n VJ=2.5V) +Rsp s2 s3 0.65 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=5.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=49.4p N=1.12 RS=0.04u EG=1.12 TT=20n) +Rdiode d1 21 0.53m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.27n +.MODEL DGD D(M=0.55 CJO=1.27n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.92n + +.ENDS BSC035N10NS5_L0 + +****** + +.SUBCKT BSC040N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 373u TC=3m + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 350 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.66m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.14n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=4.59n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=40.6p N=1.12 RS=0.05u EG=1.12 TT=20n) +Rdiode d1 21 0.64m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=0.55 CJO=1.04n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.04n + +.ENDS BSC040N10NS5_L0 + +********** + +.SUBCKT BSC040N10NS5SC_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 300p +Rs s1 s2 122u TC=3m + +Rg g1 g2 1.3 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=350 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.65m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.14n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=4.59n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=40.6p N=1.12 RS=0.05u EG=1.12 TT=20n) +Rdiode d1 21 0.64m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=0.55 CJO=1.04n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.04n + +.ENDS BSC040N10NS5SC_L0 + +***************** + +.SUBCKT BSC050N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 342u TC=3m + +Rg g1 g2 1.2 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=266.5 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 3.49m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.86n VJ=2.5V) +Rsp s2 s3 0.52 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=3.56n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=30.9p N=1.12 RS=0.07u EG=1.12 TT=20n) +Rdiode d1 21 0.85m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.9n +.MODEL DGD D(M=0.58 CJO=0.9n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.24n + +.ENDS BSC050N10NS5_L0 + +***************** + +.SUBCKT BSC070N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 371u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.08m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS BSC070N10NS5_L0 + +***************** + +.SUBCKT BSC070N10NS5SC_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 300p +Rs s1 s2 140u TC=3m + +Rg g1 g2 1 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=182.6 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.07m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS BSC070N10NS5SC_L0 + +***************** + +.SUBCKT BSC098N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 371u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 133.7 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 6.94m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.43n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.9n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.5p N=1.12 RS=0.14u EG=1.12 TT=20n) +Rdiode d1 21 1.69m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.55 CJO=0.4n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS BSC098N10NS5_L0 + +****** + +.SUBCKT BSZ097N10NS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 534u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 133.7 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 6.94m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.43n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.9n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.5p N=1.12 RS=0.14u EG=1.12 TT=20n) +Rdiode d1 21 1.69m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.55 CJO=0.4n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS BSZ097N10NS5_L0 + +****** + +.SUBCKT BSC034N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 412u TC=3m + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 383.6 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 2.26m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=1.38n VJ=2.5V) +Rsp s2 s3 0.65 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=5.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=49.4p N=1.12 RS=0.04u EG=1.12 TT=20n) +Rdiode d1 21 0.53m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.27n +.MODEL DGD D(M=0.55 CJO=1.27n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.92n + +.ENDS BSC034N10LS5_L0 + +****** + +.SUBCKT BSC070N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 300p +Rs s1 s2 367u TC=3m + +Rg g1 g2 1 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=164.4 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 5.24m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.59n VJ=2.5V) +Rsp s2 s3 0.43 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=2.52n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.2p N=1.12 RS=0.1u EG=1.12 TT=20n) +Rdiode d1 21 1.24m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.54n +.MODEL DGD D(M=0.55 CJO=0.54n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.11n + +.ENDS BSC070N10LS5_L0 + +***************** + +.SUBCKT BSC096N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 375u TC=3m + +Rg g1 g2 1.2 + +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP=120.3 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 7.15m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.43n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.9n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.5p N=1.12 RS=0.14u EG=1.12 TT=20n) +Rdiode d1 21 1.69m TC=1m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.55 CJO=0.4n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS BSC096N10LS5_L0 + +***************** + +.SUBCKT BSZ096N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 534u TC=3m + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 120.3 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 7.16m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.43n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.9n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.5p N=1.12 RS=0.14u EG=1.12 TT=20n) +Rdiode d1 21 1.69m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.4n +.MODEL DGD D(M=0.55 CJO=0.4n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS BSZ096N10LS5_L0 + +****** + +.SUBCKT BSC146N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 371u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 78.1 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 11.02m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.28n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.29n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=10.1p N=1.12 RS=0.21u EG=1.12 TT=20n) +Rdiode d1 21 2.6m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.26n +.MODEL DGD D(M=0.55 CJO=0.26n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1n + +.ENDS BSC146N10LS5_L0 + +****** + +.SUBCKT BSZ146N10LS5_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 608u TC=3m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 78.1 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 11.02m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.28n VJ=2.5V) +Rsp s2 s3 0.57 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=1.29n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=10.1p N=1.12 RS=0.21u EG=1.12 TT=20n) +Rdiode d1 21 2.6m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.26n +.MODEL DGD D(M=0.55 CJO=0.26n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1n + +.ENDS BSZ146N10LS5_L0 + +****** + +.SUBCKT IRL100HS121_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 0.3n +Rs s1 s2 2.25m TC=3m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 29.4 VTO=2.46 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3) +Rd d1 d2 29.27m TC=7m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=107 M=0.75 CJO=0.11n VJ=2.5V) +Rsp s2 s3 1.1 +Dbd1 s3 d2 Dbt1 +.MODEL Dbt1 D(BV=1000 M=0.75 CJO=0.56n VJ=2.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.12 RS=0.57u EG=1.12 TT=20n) +Rdiode d1 21 6.92m TC=1m + + + + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.1n +.MODEL DGD D(M=0.55 CJO=0.1n VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.38n + +.ENDS IRL100HS121_L0 + +****** + diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_LinearFET_100V.lib b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_LinearFET_100V.lib new file mode 100755 index 0000000..51096f6 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_LinearFET_100V.lib @@ -0,0 +1,618 @@ +***************************************************************** +* INFINEON Power Transistors * +* PSPICE Library for * +* OptiMOS5 LinearFET 100V * +* n-channel Transistors * +* Version 13012020 * +* * +***************************************************************** +* * +* The Simulation Model is subject to change without notice. In * +* addition, models can be a useful tool in evaluating device * +* performance, they cannot reflect the accurate device * +* performance under all conditions, nor are they intended to * +* replace bread boarding for final verification. Infineon * +* therefore does not assume any warranty or liability * +* whatsoever arising from their use. Infineon does not assume * +* any warranty or liability for the values and functions of the * +* Simulation Model. * +* The methods and results of the Simulation Model are to the * +* best of our knowledge * +* correct. However, the user is fully responsible to verify and * +* validate these results under the operating conditions and in * +* the environment of its application. Infineon will not bear * +* the responsibility arising out of or in connection with any * +* malfunction of the Simulation Models. * +* Models provided by Infineon are not warranted by Infineon as * +* completely and comprehensively representing all the * +* specifications and operating characteristics of the * +* semiconductor products to which these models relate. The * +* models describe the characteristics of typical devices. In * +* all cases, the current data sheet information for a given * +* device is the conclusive design guideline and the only actual * +* performance specification. * +* * +* * +* This library contains models of the following INFINEON * +* transistors: * +* * +* OptiMOS5 LinearFET 100V * +* IPB017N10N5LF * +* IPB020N10N5LF * +* IPB033N10N5LF * +* * +***************************************************************** +* thermal nodes of level 3 models: * +* * +* .SUBCKT IPB017N10N5LF drain gate source Tj Tcase * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Tcase : node where the boundary contition - external heat * +* sinks etc - have to be connected (ideal heat sink * +* can be modeled by using a voltage source stating the * +* ambient temperature in °C between Tcase and ground. * +* * +***************************************************************** + +.SUBCKT S5_100_lf_var dd g gl s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM Fm=0.15 Fn=0.5 al=0.5 +.PARAM c=1.5 Vth0=3.99 auth=3.5m +.PARAM UT=100m ab=50m lB=-23 UB=107 + +.PARAM b0l=2.6 b0=52 p0=7.919 p1=-29.8m p2=53u + +.PARAM Rdl=200m Rd=24.4m nmu=3.12 Tref=298 T0=273 lnIsj=-27.7 +.PARAM ndi=1.07 Rdi=5m nmu2=0 td=30n ta=30n +.PARAM Rf=0.54 nmu3=1.3 rpara=30u nisj=0 + +.PARAM kbq=85.8u + +.PARAM f3l=20p f3=428p + +.PARAM f3al=3p f3a=84p + +.PARAM f2=120p U0=3 nd=0.8 + +.PARAM q81=33.7p +.PARAM x0=17.6 x1=50 dx={x1-x0} + +.PARAM qs1=14.5p qs2=6.1p qs3=-2.59m qs4=111p qs5=-36.5m f2r=7.71 + +.PARAM ps1=40p ps2=-1 ps3=45.6p ps4=-0.0766 ps5=1.8p ps6=2p +.PARAM f4=7.728p f5=4.49p sl=0.19p ps0=25p +.PARAM x2=23.6 x3=40.7 dx2={x3-x2} + +.PARAM ps0l=1.25p ps1l=2.3p ps2l=-0.0491 ps3l=1.3p ps4l=-0.545 ps5l=0.688p + +.PARAM Vmin=2.99 Vmax=4.99 dCmax=0.33 +.PARAM a0={a} +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM dRdl={Rdl/a} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM betl=b0l +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+1.5*dCmax*limit(dC,0,1)} + +.PARAM Cdspn={f2*a*dC1} + +.PARAM Cgs0={f3*a0*dC1} +.PARAM Cgs1={f3a*a0*dC1} +.PARAM Cgs0l={f3l*a*dC1} +.PARAM Cgs1l={f3al*a*dC1} +.PARAM dRdi={Rdi/a} + +.PARAM Cox1={(ps1*a0+ps0*sqrt(a0))*dC1} +.PARAM Cox2={ps3*a0*dC1} +.PARAM Cox3={(ps5*a0+ps6)*dC1} +.PARAM Cox4={(f5*a0+(ps5*a0+ps6))*dC1} +.PARAM Cox1l={(ps1l*a+ps0l*sqrt(a))*dC1} +.PARAM Cox2l={ps3l*a*dC1} +.PARAM Cox4l={ps5l*a*dC1} + +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cds3={(q81+qs1)*a*dC1} +.PARAM Cds1={qs2*(1+f2r/sqrt(a))*a*dC1} + +.FUNC VBR(Udsp) {UB} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC J(d,g,T,da,s,x) ++ {a*(s*(Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn+1*limit(-d,0,1))+exp(min(lB+(d-VBR(x)-ab*(T-Tref))/UT,25))))} + +.FUNC Igl(Uds,T,p,Uee) {betl*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jl(d,g,T,da,s,x) ++ {a*(s*(Igl(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn+1*limit(-d,0,1))+exp(min(lB+(d-VBR(x)-ab*(T-Tref))/UT,25))))} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} + +.FUNC QCds(x) {Cds3*min(x,x1)+Cds0*max(x-x1,0)+(Cds3-Cds0)*((limit(x,x0,x1)-x0)**3/(dx*dx)*((limit(x,x0,x1)-x0)/(2*dx)-1))} +.FUNC QCdg(x) {Cox4*min(x,x3)+Cox3*max(x-x3,0)+(Cox4-Cox3)*((limit(x,x2,x3)-x2)**3/(dx2*dx2)*((limit(x,x2,x3)-x2)/(2*dx2)-1))} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +E_Edg3 d ox2 VALUE {V(d,g)-QCdg(V(d,g))/Cox4} +C_Cdg3 ox2 g {Cox4} + +E_Edg1l d oxl VALUE {if(V(d,gl)>0,V(d,gl)-(exp(ps2l*max(V(d,gl),0))-1)/ps2l,0)} +C_Cdg1l oxl gl {Cox1l} +E_Edg2l d ox1l VALUE {if(V(d,gl)>0,V(d,gl)-(exp(ps4l*max(V(d,gl),0))-1)/ps4l,0)} +C_Cdg2l ox1l gl {Cox2l} +C_Cdg3l d gl {Cox4l} + +E_Eds d edep VALUE {V(d,s)-1/(1-nd)*U0*((limit(1+V(d,s)/U0,0,2*UB))**(1-nd)-1)} +C_Cds edep s {Cdspn*0.99} + +E_Eds1 d edep1 VALUE {V(d,sp)-QCds(V(d,sp))/Cds3} +C_Cds1 edep1 sp {Cds3} +E_Eds2 d edep2 VALUE {if(V(d,sp)>0,V(d,sp)-(exp(qs5*max(V(d,sp),0))-1)/qs5,0)} +C_Cds2 edep2 sp {Cds2} +E_Eds3 d edep3 VALUE {if(V(d,sp)>0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/qs3,0)} +C_Cds3 edep3 sp {Cds1} + +C_Cgs g s {Cgs0} +C_Cgsl gl s {Cgs0l} +C_Cgs1 g sp {Cgs1} +C_Cgs1l gl sp {Cgs1l} + +Rfp s sp {Rsp} + +V_sense dd d1 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sm d d5 0 +Rd06 d5 d5a 0.1u +G_chan d5a s VALUE={J(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d5a,s)))-1)/2/al,sgn(V(d5a,s)),V(sp,s))} + +V_sensel dd d1l 0 +G_RMosl d1l dl VALUE={V(d1l,dl)/(Rf*dRdl+(1-Rf)*dRdl*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sensel)/a)**2)} +V_sml dl d5l 0 +Rd06l d5l d5al 0.1u +G_chanl d5al s VALUE={Jl(V(d5al,s),V(gl,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d5al,s)))-1)/2/al,sgn(V(d5al,s)),V(sp,s))} + + +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +Dbody s d3 dbody +.model dbody D (BV= {UB*10},CJO ={Cdspn/1000},TT ={ta},IS ={a*exp(lnIsj)} m={0.5} RS={dRdi*1m} n={ndi}) + +R1 g s 1G +R1l gl s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+I(V_sensel)*V(d1l,s)+Pr(V(s,s0),V(s,sp))} + +.ENDS + +****************** + +.SUBCKT IPB017N10N5LF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=414u Rg=1.9 Rgl=44 Rd=20u Rm=140u +.PARAM Inn=100 Unn=10 Rmax=1.7m gmin=32 +.PARAM RRf=391m Rrbond=6m Rtb=3.8 g2=656m +.PARAM act=27.15 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g gl s sp Tj S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1l 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.14m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.21m+limit(Zthtype,0,1)*446.19u} +Rth2 t1 t2 {13.28m+limit(Zthtype,0,1)*4.92m} +Rth3 t2 t3 {29.27m+limit(Zthtype,0,1)*6.8m} +Rth4 t3 t4 {65.21m+limit(Zthtype,0,1)*28.89m} +Rth5 t4 Tcase {173.22m+limit(Zthtype,0,1)*76.75m} +Cth1 Tj 0 377.988u +Cth2 t1 0 858.067u +Cth3 t2 0 3.528m +Cth4 t3 0 4.615m +Cth5 t4 0 136.611m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPB020N10N5LF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=656u Rg=1.9 Rgl=44 Rd=50u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2m gmin=28 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.15 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g gl s sp Tj S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1l 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.21m+limit(Zthtype,0,1)*446.19u} +Rth2 t1 t2 {13.28m+limit(Zthtype,0,1)*4.92m} +Rth3 t2 t3 {29.27m+limit(Zthtype,0,1)*6.8m} +Rth4 t3 t4 {65.21m+limit(Zthtype,0,1)*28.89m} +Rth5 t4 Tcase {173.22m+limit(Zthtype,0,1)*76.75m} +Cth1 Tj 0 377.988u +Cth2 t1 0 858.067u +Cth3 t2 0 3.528m +Cth4 t3 0 4.615m +Cth5 t4 0 136.611m +Cth6 Tcase 0 190m + + +.ENDS + +************************************** + +.SUBCKT IPB033N10N5LF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=674u Rg=1.8 Rgl=40 Rd=50u Rm=181u +.PARAM Inn=100 Unn=10 Rmax=3.3m gmin=21 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=14.73 Rsp=0.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g gl s sp Tj S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1l 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.23m+limit(Zthtype,0,1)*822.89u} +Rth2 t1 t2 {24.22m+limit(Zthtype,0,1)*8.96m} +Rth3 t2 t3 {52.83m+limit(Zthtype,0,1)*12.63m} +Rth4 t3 t4 {70m+limit(Zthtype,0,1)*69.88m} +Rth5 t4 Tcase {229.42m+limit(Zthtype,0,1)*229.01m} +Cth1 Tj 0 205.074u +Cth2 t1 0 470.748u +Cth3 t2 0 1.963m +Cth4 t3 0 2.504m +Cth5 t4 0 88.491m +Cth6 Tcase 0 190m + +.ENDS + +********** + + +.SUBCKT IPB017N10N5LF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=414u Rg=1.9 Rgl=44 Rd=20u Rm=140u +.PARAM Inn=100 Unn=10 Rmax=1.7m gmin=32 +.PARAM act=27.15 Rsp=0.47 + +X1 d1 g gl s sp Tj1 S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE = ++{V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(z,g)*V(z,g)/Rg+V(g1l,gl)*V(g1l,gl)/Rgl+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R10 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB020N10N5LF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=656u Rg=1.9 Rgl=44 Rd=50u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2m gmin=28 +.PARAM act=27.15 Rsp=0.47 + +X1 d1 g gl s sp Tj1 S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE = ++{V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(z,g)*V(z,g)/Rg+V(g1l,gl)*V(g1l,gl)/Rgl+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R10 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB033N10N5LF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=674u Rg=1.8 Rgl=40 Rd=50u Rm=181u +.PARAM Inn=100 Unn=10 Rmax=3.3m gmin=23 +.PARAM act=14.73 Rsp=0.5 + +X1 d1 g gl s sp Tj1 S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE = ++{V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(z,g)*V(z,g)/Rg+V(g1l,gl)*V(g1l,gl)/Rgl+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R10 w 0 1u + +.ENDS + +********** + + + + diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_LinearFET_100V_LTSpice.lib b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_LinearFET_100V_LTSpice.lib new file mode 100755 index 0000000..762dc3e --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS5/OptiMOS5_LinearFET_100V_LTSpice.lib @@ -0,0 +1,620 @@ +***************************************************************** +* INFINEON Power Transistors * +* LTSPICE Library for * +* OptiMOS5 LinearFET 100V * +* n-channel Transistors * +* Version 15052020 * +* * +***************************************************************** +* * +* The Simulation Model is subject to change without notice. In * +* addition, models can be a useful tool in evaluating device * +* performance, they cannot reflect the accurate device * +* performance under all conditions, nor are they intended to * +* replace bread boarding for final verification. Infineon * +* therefore does not assume any warranty or liability * +* whatsoever arising from their use. Infineon does not assume * +* any warranty or liability for the values and functions of the * +* Simulation Model. * +* The methods and results of the Simulation Model are to the * +* best of our knowledge * +* correct. However, the user is fully responsible to verify and * +* validate these results under the operating conditions and in * +* the environment of its application. Infineon will not bear * +* the responsibility arising out of or in connection with any * +* malfunction of the Simulation Models. * +* Models provided by Infineon are not warranted by Infineon as * +* completely and comprehensively representing all the * +* specifications and operating characteristics of the * +* semiconductor products to which these models relate. The * +* models describe the characteristics of typical devices. In * +* all cases, the current data sheet information for a given * +* device is the conclusive design guideline and the only actual * +* performance specification. * +* * +* * +* This library contains models of the following INFINEON * +* transistors: * +* * +* OptiMOS5 LinearFET 100V * +* IPB017N10N5LF * +* IPB020N10N5LF * +* IPB033N10N5LF * +* * +***************************************************************** +* thermal nodes of level 3 models: * +* * +* .SUBCKT IPB017N10N5LF drain gate source Tj Tcase * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Tcase : node where the boundary contition - external heat * +* sinks etc - have to be connected (ideal heat sink * +* can be modeled by using a voltage source stating the * +* ambient temperature in °C between Tcase and ground. * +* * +***************************************************************** + +.options Thev_Induc=1 + +.SUBCKT S5_100_lf_var dd g gl s0 sp Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u + +.PARAM Fm=0.15 Fn=0.5 al=0.5 +.PARAM c=1.5 Vth0=3.99 auth=3.5m +.PARAM UT=100m ab=50m lB=-23 UB=107 + +.PARAM b0l=2.6 b0=52 p0=7.919 p1=-29.8m p2=53u + +.PARAM Rdl=200m Rd=24.4m nmu=3.12 Tref=298 T0=273 lnIsj=-27.7 +.PARAM ndi=1.07 Rdi=5m nmu2=0 td=30n ta=30n +.PARAM Rf=0.54 nmu3=1.3 rpara=30u nisj=0 + +.PARAM kbq=85.8u + +.PARAM f3l=20p f3=428p + +.PARAM f3al=3p f3a=84p + +.PARAM f2=120p U0=3 nd=0.8 + +.PARAM q81=33.7p +.PARAM x0=17.6 x1=50 dx={x1-x0} + +.PARAM qs1=14.5p qs2=6.1p qs3=-2.59m qs4=111p qs5=-36.5m f2r=7.71 + +.PARAM ps1=40p ps2=-1 ps3=45.6p ps4=-0.0766 ps5=1.8p ps6=2p +.PARAM f4=7.728p f5=4.49p sl=0.19p ps0=25p +.PARAM x2=23.6 x3=40.7 dx2={x3-x2} + +.PARAM ps0l=1.25p ps1l=2.3p ps2l=-0.0491 ps3l=1.3p ps4l=-0.545 ps5l=0.688p + +.PARAM Vmin=2.99 Vmax=4.99 dCmax=0.33 +.PARAM a0={a} +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM dRdl={Rdl/a} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM betl=b0l +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+1.5*dCmax*limit(dC,0,1)} + +.PARAM Cdspn={f2*a*dC1} + +.PARAM Cgs0={f3*a0*dC1} +.PARAM Cgs1={f3a*a0*dC1} +.PARAM Cgs0l={f3l*a*dC1} +.PARAM Cgs1l={f3al*a*dC1} +.PARAM dRdi={Rdi/a} + +.PARAM Cox1={(ps1*a0+ps0*sqrt(a0))*dC1} +.PARAM Cox2={ps3*a0*dC1} +.PARAM Cox3={(ps5*a0+ps6)*dC1} +.PARAM Cox4={(f5*a0+(ps5*a0+ps6))*dC1} +.PARAM Cox1l={(ps1l*a+ps0l*sqrt(a))*dC1} +.PARAM Cox2l={ps3l*a*dC1} +.PARAM Cox4l={ps5l*a*dC1} + +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cds3={(q81+qs1)*a*dC1} +.PARAM Cds1={qs2*(1+f2r/sqrt(a))*a*dC1} + +.FUNC VBR(Udsp) {UB} + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC J(d,g,T,da,s,x) ++ {a*(s*(Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn+1*limit(-d,0,1))+exp(min(lB+(d-VBR(x)-ab*(T-Tref))/UT,25))))} + +.FUNC Igl(Uds,T,p,Uee) {betl*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC Jl(d,g,T,da,s,x) ++ {a*(s*(Igl(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn+1*limit(-d,0,1))+exp(min(lB+(d-VBR(x)-ab*(T-Tref))/UT,25))))} + +.FUNC Pr(Vss0,Vssp) {Vss0*Vss0/Rm+Vssp*Vssp/Rsp} + +.FUNC QCds(x) {Cds3*min(x,x1)+Cds0*max(x-x1,0)+(Cds3-Cds0)*((limit(x,x0,x1)-x0)**3/(dx*dx)*((limit(x,x0,x1)-x0)/(2*dx)-1))} +.FUNC QCdg(x) {Cox4*min(x,x3)+Cox3*max(x-x3,0)+(Cox4-Cox3)*((limit(x,x2,x3)-x2)**3/(dx2*dx2)*((limit(x,x2,x3)-x2)/(2*dx2)-1))} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +E_Edg3 d ox2 VALUE {V(d,g)-QCdg(V(d,g))/Cox4} +C_Cdg3 ox2 g {Cox4} + +E_Edg1l d oxl VALUE {if(V(d,gl)>0,V(d,gl)-(exp(ps2l*max(V(d,gl),0))-1)/ps2l,0)} +C_Cdg1l oxl gl {Cox1l} +E_Edg2l d ox1l VALUE {if(V(d,gl)>0,V(d,gl)-(exp(ps4l*max(V(d,gl),0))-1)/ps4l,0)} +C_Cdg2l ox1l gl {Cox2l} +C_Cdg3l d gl {Cox4l} + +E_Eds d edep VALUE {V(d,s)-1/(1-nd)*U0*((limit(1+V(d,s)/U0,0,2*UB))**(1-nd)-1)} +C_Cds edep s {Cdspn*0.99} + +E_Eds1 d edep1 VALUE {V(d,sp)-QCds(V(d,sp))/Cds3} +C_Cds1 edep1 sp {Cds3} +E_Eds2 d edep2 VALUE {if(V(d,sp)>0,V(d,sp)-(exp(qs5*max(V(d,sp),0))-1)/qs5,0)} +C_Cds2 edep2 sp {Cds2} +E_Eds3 d edep3 VALUE {if(V(d,sp)>0,V(d,sp)-(exp(qs3*max(V(d,sp),0))-1)/qs3,0)} +C_Cds3 edep3 sp {Cds1} + +C_Cgs g s {Cgs0} +C_Cgsl gl s {Cgs0l} +C_Cgs1 g sp {Cgs1} +C_Cgs1l gl sp {Cgs1l} + +Rfp s sp {Rsp} + +V_sense dd d1 0 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sense)/a)**2)} +V_sm d d5 0 +Rd06 d5 d5a 0.1u +G_chan d5a s VALUE={J(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d5a,s)))-1)/2/al,sgn(V(d5a,s)),V(sp,s))} + +V_sensel dd d1l 0 +G_RMosl d1l dl VALUE={V(d1l,dl)/(Rf*dRdl+(1-Rf)*dRdl*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpara*(I(V_sensel)/a)**2)} +V_sml dl d5l 0 +Rd06l d5l d5al 0.1u +G_chanl d5al s VALUE={Jl(V(d5al,s),V(gl,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d5al,s)))-1)/2/al,sgn(V(d5al,s)),V(sp,s))} + + +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +Dbody s d3 dbody +.model dbody D (BV= {UB*10},CJO ={Cdspn/1000},TT ={ta},IS ={a*exp(lnIsj)} m={0.5} RS={dRdi*1m} n={ndi}) + +R1 g s 1G +R1l gl s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k +Rssp g sp 100Meg + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)+I(V_sensel)*V(d1l,s)+Pr(V(s,s0),V(s,sp))} + +.ENDS + +****************** + +.SUBCKT IPB017N10N5LF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=414u Rg=1.9 Rgl=44 Rd=20u Rm=140u +.PARAM Inn=100 Unn=10 Rmax=1.7m gmin=32 +.PARAM RRf=391m Rrbond=6m Rtb=3.8 g2=656m +.PARAM act=27.15 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g gl s sp Tj S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1l 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 10.14m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.21m+limit(Zthtype,0,1)*446.19u} +Rth2 t1 t2 {13.28m+limit(Zthtype,0,1)*4.92m} +Rth3 t2 t3 {29.27m+limit(Zthtype,0,1)*6.8m} +Rth4 t3 t4 {65.21m+limit(Zthtype,0,1)*28.89m} +Rth5 t4 Tcase {173.22m+limit(Zthtype,0,1)*76.75m} +Cth1 Tj 0 377.988u +Cth2 t1 0 858.067u +Cth3 t2 0 3.528m +Cth4 t3 0 4.615m +Cth5 t4 0 136.611m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPB020N10N5LF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=656u Rg=1.9 Rgl=44 Rd=50u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2m gmin=28 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=27.15 Rsp=0.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g gl s sp Tj S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1l 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.21m+limit(Zthtype,0,1)*446.19u} +Rth2 t1 t2 {13.28m+limit(Zthtype,0,1)*4.92m} +Rth3 t2 t3 {29.27m+limit(Zthtype,0,1)*6.8m} +Rth4 t3 t4 {65.21m+limit(Zthtype,0,1)*28.89m} +Rth5 t4 Tcase {173.22m+limit(Zthtype,0,1)*76.75m} +Cth1 Tj 0 377.988u +Cth2 t1 0 858.067u +Cth3 t2 0 3.528m +Cth4 t3 0 4.615m +Cth5 t4 0 136.611m +Cth6 Tcase 0 190m + + +.ENDS + +************************************** + +.SUBCKT IPB033N10N5LF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=674u Rg=1.8 Rgl=40 Rd=50u Rm=181u +.PARAM Inn=100 Unn=10 Rmax=3.3m gmin=21 +.PARAM RRf=350m Rrbond=12m Rtb=5.3 g2=729m +.PARAM act=14.73 Rsp=0.5 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g gl s sp Tj S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +Rsb source s1 10 +Rga gate g1l 10 +Rdb drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.05m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.23m+limit(Zthtype,0,1)*822.89u} +Rth2 t1 t2 {24.22m+limit(Zthtype,0,1)*8.96m} +Rth3 t2 t3 {52.83m+limit(Zthtype,0,1)*12.63m} +Rth4 t3 t4 {70m+limit(Zthtype,0,1)*69.88m} +Rth5 t4 Tcase {229.42m+limit(Zthtype,0,1)*229.01m} +Cth1 Tj 0 205.074u +Cth2 t1 0 470.748u +Cth3 t2 0 1.963m +Cth4 t3 0 2.504m +Cth5 t4 0 88.491m +Cth6 Tcase 0 190m + +.ENDS + +********** + + +.SUBCKT IPB017N10N5LF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=414u Rg=1.9 Rgl=44 Rd=20u Rm=140u +.PARAM Inn=100 Unn=10 Rmax=1.7m gmin=32 +.PARAM act=27.15 Rsp=0.47 + +X1 d1 g gl s sp Tj1 S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE = ++{V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(z,g)*V(z,g)/Rg+V(g1l,gl)*V(g1l,gl)/Rgl+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R10 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB020N10N5LF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.8n Ld=1n Lg=4n + +.PARAM Rs=656u Rg=1.9 Rgl=44 Rd=50u Rm=163u +.PARAM Inn=100 Unn=10 Rmax=2m gmin=28 +.PARAM act=27.15 Rsp=0.47 + +X1 d1 g gl s sp Tj1 S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE = ++{V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(z,g)*V(z,g)/Rg+V(g1l,gl)*V(g1l,gl)/Rgl+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R10 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB033N10N5LF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2.5n Lg=4n + +.PARAM Rs=674u Rg=1.8 Rgl=40 Rd=50u Rm=181u +.PARAM Inn=100 Unn=10 Rmax=3.3m gmin=23 +.PARAM act=14.73 Rsp=0.5 + +X1 d1 g gl s sp Tj1 S5_100_lf_var PARAMS: a={act} Rsp={Rsp} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} + +.MODEL D01 D(BV=330 CJO=1p VJ=0.9 M=0.5 RS=1k) +.MODEL D02 D(BV=4.5 CJO=1p VJ=0.91 M=0.47) +.MODEL D03 D(BV=5 CJO=1p VJ=0.91 M=0.47 RS=1k) +.MODEL D04 D(BV=30 CJO=1p VJ=0.9 M=0.5) +.MODEL PMOS PMOS ( LEVEL=1 VTO=-2.1 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) +.MODEL NMOS NMOS ( LEVEL=1 VTO=0.9 KP=40U LAMBDA=.001 GAMMA=.6 PHI=0.8 TOX=40n CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 ++ MJ=0.5 PB=0.95) + +M1 a1 a2 a3 a3 PMOS L=1.6u W=4.536m +M2 a4 a5 a6 a6 NMOS L=1.6u W=453.6u + +G1 d1 a8 VALUE={min(V(d1,a8),1.55)/1.2Meg} +G2 a2 a3 VALUE={if(V(a2,a3)<0,V(a2,a3)/10Meg,V(a2,a3)/1.7Meg)} + +D1 a8 d1 D01 +D2 a8 a2 D02 +D3 s a8 D03 +D4 z a7 D04 + +R2 a8 a5 4.8Meg +R3 a5 s 2.4Meg +R4 a4 a7 39.7 TC=10m +R5 s a6 7.94 TC=10n +R6 z a1 7.9m TC=10m +R7 g1l a3 6.35 TC=10m +R8 a2 a3 1G +R9 d1 a8 100G + +C1 a8 d1 3p + +Rg z g {Rg} +Rgl g1l gl {Rgl} +Lgl gate g1l {Lg*if(dgfs==99,0,1)} + +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E2 Tj w VALUE={TEMP} +Vp Tj1 Tj 0 +R1 Tj Tj1 1u +G_power 0 Tj VALUE = ++{V(s1,s)*V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)+V(z,g)*V(z,g)/Rg+V(g1l,gl)*V(g1l,gl)/Rgl+V(d1,d2)*V(d1,d2)/Rd+I(Vp)} +R10 w 0 1u + +.ENDS + +********** + + + + diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/OptiMOS_100V_small_signal_PSpice.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/OptiMOS_100V_small_signal_PSpice.slb new file mode 100755 index 0000000..18f93cd --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/OptiMOS_100V_small_signal_PSpice.slb @@ -0,0 +1,640 @@ +*version 9.1 546938296 +@index +symloc DMOS_S2_L3_n 0 1664 b +symloc BSS119N:DMOS_S2_L3_n 1664 550 +symloc DMOS_S2_L1_n 2214 1268 b +symloc BSS119N_L1:DMOS_S2_L1_n 3482 485 +symloc BSS119N_L0 3967 1054 +symloc BSS123N:DMOS_S2_L3_n 5021 550 +symloc BSP296N:DMOS_S2_L3_n 5571 550 +symloc BSP372N:DMOS_S2_L3_n 6121 550 +symloc BSP373N:DMOS_S2_L3_n 6671 550 +symloc BSS123N_L1:DMOS_S2_L1_n 7221 485 +symloc BSP296N_L1:DMOS_S2_L1_n 7706 485 +symloc BSP372N_L1:DMOS_S2_L1_n 8191 485 +symloc BSP373N_L1:DMOS_S2_L1_n 8676 485 +symloc BSS123N_L0 9161 1054 +symloc BSP296N_L0 10215 1054 +symloc BSP373N_L0 11269 1054 +symloc BSP372N_L0 12323 1054 +*symbol DMOS_S2_L3_n b +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tcase n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 30 20 +20 20 +; +v 0 10 20 +15 20 +; +v 0 15 10 +15 30 +; +v 0 30 20 +30 30 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +v 0 20 23 +20 17 +; +v 0 38 10 +30 10 +; +v 0 30 30 +38 30 +38 10 +; +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 5 d_info:,,,,,,,,,,,,,5, +Tcase +*symbol BSS119N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSS119N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSS119N +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 50 hlb 100 dZth= +*symbol DMOS_S2_L1_n b +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1_n +a 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+; +v 0 20 13 +20 7 +; +*symbol BSS119N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSS119N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSS119N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSS119N_L0 +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSS119N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSS119N_L0 +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol BSS123N ako DMOS_S2_L3_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 38 -3 hln 100 PART=BSS123N +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tcase @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 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0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSS123N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSS123N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSP296N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSP296N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSP296N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSP372N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSP372N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSP372N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSP373N_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSP373N_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSP373N_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSS123N_L0 +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes 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d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol BSP372N_L0 +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=BSP372N_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSP372N_L0 +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 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a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/SmallSignal_a_L0.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/SmallSignal_a_L0.slb new file mode 100755 index 0000000..cb21519 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/SmallSignal_a_L0.slb @@ -0,0 +1,230 @@ +*version 9.1 1966487578 +@index +symloc DMOS 0 1038 b +symloc DMOS_depletion 1038 1063 b +symloc BSP296_L0:DMOS 2101 277 +symloc BSS123_L0:DMOS 2378 277 +symloc BSP123_L0:DMOS 2655 277 +symloc BSS119_L0:DMOS 2932 277 +symloc BSS169_L0:DMOS_depletion 3209 302 +symloc SISC0_5N10D_L0:DMOS_depletion 3511 317 +symloc BSP372_L0:DMOS 3828 277 +symloc BSL296SN_L0:DMOS 4105 283 +symloc BSL372SN_L0:DMOS 4388 283 +symloc BSL373SN_L0:DMOS 4671 283 +*symbol DMOS b +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol DMOS_depletion b +d Infineon n-channel depletion mode DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 27 +20 10 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol BSP296_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 71 38 hcn 100 PART=BSP296_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSP296_L0 +*symbol BSS123_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 71 38 hcn 100 PART=BSS123_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSS123_L0 +*symbol BSP123_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 71 38 hcn 100 PART=BSP123_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSP123_L0 +*symbol BSS119_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 71 38 hcn 100 PART=BSS119_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSS119_L0 +*symbol BSS169_L0 ako DMOS_depletion +d Infineon n-channel DMOS depletion mode transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 71 38 hcn 100 PART=BSS169_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSS169_L0 +*symbol SISC0_5N10D_L0 ako DMOS_depletion +d Infineon n-channel DMOS depletion mode transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 91 36 hcn 100 PART=SISC0_5N10D_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=SISC0_5N10D_L0 +*symbol BSP372_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 71 38 hcn 100 PART=BSP372_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSP372_L0 +*symbol BSL296SN_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 71 38 hcn 100 PART=BSL296SN_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSL296SN_L0 +*symbol BSL372SN_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 71 38 hcn 100 PART=BSL372SN_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSL372SN_L0 +*symbol BSL373SN_L0 ako DMOS +d Infineon n-channel DMOS transistor +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 71 38 hcn 100 PART=BSL373SN_L0 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSL373SN_L0 diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/SmallSignal_a_L1.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/SmallSignal_a_L1.slb new file mode 100755 index 0000000..8be81bb --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/SmallSignal_a_L1.slb @@ -0,0 +1,265 @@ +*version 9.1 3529091409 +@index +symloc DMOS_S2_L1_n 0 1267 b +symloc BSP296_L1:DMOS_S2_L1_n 1267 481 +symloc BSS123_L1:DMOS_S2_L1_n 1748 481 +symloc BSP123_L1:DMOS_S2_L1_n 2229 481 +symloc BSS119_L1:DMOS_S2_L1_n 2710 481 +symloc BSS169_L1:DMOS_S2_L1d_n 3191 483 +symloc SISC0_5N10D_L1:DMOS_S2_L1d_n 3674 497 +symloc DMOS_S2_L1d_n 4171 1281 b +symloc BSL296SN_L1:DMOS_S2_L1_n 5452 487 +symloc BSL372SN_L1:DMOS_S2_L1_n 5939 487 +symloc BSL373SN_L1:DMOS_S2_L1_n 6426 487 +*symbol DMOS_S2_L1_n b +d Infineon n-channel DMOS +@type p 9.2 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1_n +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS_S2_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 23 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 13 +20 7 +; +*symbol BSP296_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 70 37 hcn 100 PART=BSP296_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSP296_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSS123_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 70 37 hcn 100 PART=BSS123_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSS123_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSP123_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 70 37 hcn 100 PART=BSP123_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSP123_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSS119_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 8.0 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 70 37 hcn 100 PART=BSS119_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSS119_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSS169_L1 ako DMOS_S2_L1d_n +d Infineon n-channel DMOS +@type p 9.2 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 70 37 hcn 100 PART=BSS169_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSS169_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol SISC0_5N10D_L1 ako DMOS_S2_L1d_n +d Infineon n-channel DMOS +@type p 9.2 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 70 37 hcn 100 PART=SISC0_5N10D_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=SISC0_5N10D_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol DMOS_S2_L1d_n b +d Infineon n-channel depletion DMOS +@type p 9.2 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 87 34 hcn 100 PART=DMOS_S2_L1d_n +a 0 sp 0:13 0 4 40 hcn 100 MODEL=DMOS_S2_L1d +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +@graphics 46 40 0 20 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 38 10 +38 30 +28 30 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 25 16 +20 20 +; +v 0 20 20 +25 24 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +30 30 +; +v 0 30 20 +20 20 +; +v 0 38 10 +30 10 +; +v 0 15 10 +15 30 +; +v 0 10 20 +15 20 +; +v 0 20 10 +30 10 +; +v 0 20 30 +30 30 +; +v 0 20 27 +20 17 +; +v 0 20 33 +20 27 +; +v 0 20 17 +20 7 +; +*symbol BSL296SN_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 70 37 hcn 100 PART=BSL296SN_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSL296SN_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSL372SN_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 70 37 hcn 100 PART=BSL372SN_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSL372SN_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= +*symbol BSL373SN_L1 ako DMOS_S2_L1_n +d Infineon n-channel DMOS +@type p 9.1 +@attributes +a 1 sp 0 0 0 0 hcn 100 TEMPLATE=X^@refdes %drain %gate %source @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| +a 0 s 9 0 61 12 hcn 100 REFDES=X? +a 0 sp 11 0 70 37 hcn 100 PART=BSL373SN_L1 +a 0 sp 0:13 0 4 40 hcn 100 MODEL=BSL373SN_L1 +a 0 u 0:13 0 0 10 hcn 100 dVth= +a 0 u 0:13 0 0 20 hcn 100 dRdson= +a 0 u 0:13 0 0 30 hcn 100 dgfs= +a 0 u 0:13 0 0 40 hcn 100 dC= diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/SmallSignal_a_L3.slb b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/SmallSignal_a_L3.slb new file mode 100755 index 0000000..90e6708 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/SmallSignal_a_L3.slb @@ -0,0 +1,298 @@ +*version 9.1 704753418 +@index +symloc DMOS_K_L3_SSP_n 0 1698 b +symloc BSP296:DMOS_K_L3_SSP_n 1698 557 +symloc BSS123:DMOS_K_L3_SSP_n 2255 557 +symloc BSP123:DMOS_K_L3_SSP_n 2812 557 +symloc BSS119:DMOS_K_L3_SSP_n 3369 557 +symloc BSS169:DMOS_K_L3d_SSP_n 3926 558 +symloc SISC0_5N10D:DMOS_K_L3d_SSP_n 4484 573 +symloc DMOS_K_L3d_SSP_n 5057 1699 b +symloc BSL296SN:DMOS_K_L3_SSP_n 6756 563 +symloc BSL372SN:DMOS_K_L3_SSP_n 7319 563 +symloc BSL373SN:DMOS_K_L3_SSP_n 7882 563 +*symbol DMOS_K_L3_SSP_n b +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tsolder_joint n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 30 30 +38 30 +38 10 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 20 20 +25 24 +; +v 0 25 16 +20 20 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +20 20 +; +v 0 20 13 +20 7 +; +v 0 15 10 +15 30 +; +v 0 20 30 +30 30 +; +v 0 10 20 +15 20 +; +v 0 30 20 +30 30 +; +v 0 38 10 +30 10 +; +v 0 20 10 +30 10 +; +v 0 20 33 +20 27 +; +v 0 20 23 +20 17 +; +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 13 d_info:,0/128/0,,,,,,,,,,,,5, +Tsolder_joint +*symbol BSP296 ako DMOS_K_L3_SSP_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=BSP296 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSP296 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +*symbol BSS123 ako DMOS_K_L3_SSP_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=BSS123 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSS123 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +*symbol BSP123 ako DMOS_K_L3_SSP_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=BSP123 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSP123 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +*symbol BSS119 ako DMOS_K_L3_SSP_n +d Infineon DMOS with thermal network +@type p 8.0 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=BSS119 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSS119 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +*symbol BSS169 ako DMOS_K_L3d_SSP_n +d Infineon DMOS with thermal network +@type p 9.2 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=BSS169 +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSS169 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +*symbol SISC0_5N10D ako DMOS_K_L3d_SSP_n +d Infineon DMOS with thermal network +@type p 9.2 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=SISC0_5N10D +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=SISC0_5N10D +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +*symbol DMOS_K_L3d_SSP_n b +d Infineon DMOS with thermal network +@type p 9.2 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=DMOS_S2_L3_n +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=DMOS_L3 +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +@pins +p 0 25 40 hcn 100 source n 30 40 v +a 0 s 0:1 0 31 38 hln 100 PIN=3 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 10 20 hcn 100 gate n 0 20 h +a 0 s 0:1 0 1 18 hln 100 PIN=2 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 25 10 hcn 100 drain n 30 0 d +a 0 s 0:1 0 31 -2 hln 100 PIN=1 +a 0 s 0 0 0 0 hln 100 ERC=x +p 0 70 8 hrn 100 Tj n 60 10 u +a 0 s 0:1 0 51 16 hln 100 PIN=4 +a 0 s 0:13 0 60 10 hln 100 ERC=x +a 0 s 0:13 0 0 10 hln 100 FLOAT=r +p 0 88 26 hrn 100 Tsolder_joint n 60 30 u +a 0 s 0:1 0 51 36 hln 100 PIN=5 +a 0 s 0:13 0 60 30 hln 100 ERC=x +@graphics 60 40 0 0 10 +c 0 25 20 20 d_info:,0/0/0,,,,,,,,,,,,, +v 0 30 30 +38 30 +38 10 +; +v 0 38 18 d_info:,,,,4/1/6/6,ON,0/0/255,,,,,,,, +35 22 +41 22 +38 18 +; +v 0 20 20 +25 24 +; +v 0 25 16 +20 20 +; +r 0 35 17 41 18 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 30 1 d_info:,,,,,ON,0/0/255,,,,,,,, +c 0 30 10 1 d_info:,,,,,ON,0/0/255,,,,,,,, +v 0 30 20 +20 20 +; +v 0 20 17 +20 7 +; +v 0 15 10 +15 30 +; +v 0 20 30 +30 30 +; +v 0 10 20 +15 20 +; +v 0 30 20 +30 30 +; +v 0 38 10 +30 10 +; +v 0 20 10 +30 10 +; +v 0 20 33 +20 27 +; +v 0 20 27 +20 17 +; +z 26 54 6 hln 100 2 d_info:,,,,,,,,,,,,,5, +Tj +z 26 46 27 hln 100 13 d_info:,0/128/0,,,,,,,,,,,,5, +Tsolder_joint +*symbol BSL296SN ako DMOS_K_L3_SSP_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=BSL296SN +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSL296SN +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +*symbol BSL372SN ako DMOS_K_L3_SSP_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=BSL372SN +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSL372SN +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= +*symbol BSL373SN ako DMOS_K_L3_SSP_n +d Infineon DMOS with thermal network +@type p 9.1 +@attributes +a 0 sp 11 0 39 62 hln 100 PART=BSL373SN +a 0 sp 0 0 0 0 hln 100 TEMPLATE=X^@refdes %drain %gate %source %Tj %Tsolder_joint @MODEL PARAMS: ?dVth|dVth=@dVth| ?dRdson|dRdson=@dRdson| ?dgfs|dgfs=@dgfs| ?dC|dC=@dC| ?dZth|Zthtype=@dZth| +a 0 s 9 0 -3 0 hcn 100 REFDES=X? +a 0 sp 0:13 0 5 50 hcn 100 MODEL=BSL373SN +a 0 u 0:13 0 0 10 hlb 100 dVth= +a 0 u 0:13 0 0 20 hlb 100 dRdson= +a 0 u 0:13 0 0 30 hlb 100 dgfs= +a 0 u 0:13 0 0 40 hlb 100 dC= +a 0 u 0:13 0 0 10 hlb 100 dZth= diff --git a/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/small_signal_100V.lib b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/small_signal_100V.lib new file mode 100755 index 0000000..cdae7b9 --- /dev/null +++ b/spice/Infineon/Infineon-OptiMOS_PowerMOSFET_PSpice_100V_N-Channel-SimulationModels-v01_01-EN/OptiMOS_small_signal/small_signal_100V.lib @@ -0,0 +1,1932 @@ +***************************************************************** +* INFINEON Power Transistors * +* Level-1 / 3 PSPICE Library for small signal transistors * +* Version 240715 * +* * +* * +* Models provided by Infineon are not warranted by Infineon as * +* fully representing all the specifications and operating * +* characteristics of the semiconductor product to which the * +* model relates. The models describe the characteristics of * +* typical devices. * +* In all cases, the current data sheet information for a given * +* device is the final design guideline and the only actual * +* performance specification. * +* Although models can be a useful tool in evaluating device * +* performance, they cannot model exact device performance under * +* all conditions, nor are they intended to replace bread- * +* boarding for final verification. INFINEON therefore does not * +* assume any liability arising from their use. * +* INFINEON reserves the right to change models without prior * +* notice. * +* * +***************************************************************** +* * +* This library contains models of the following INFINEON * +* transistors: * +* BSP296 (n-channel, 100 V enhancement) * +* BSS123 (n-channel, 100 V enhancement) * +* BSP123 (n-channel, 100 V enhancement) * +* BSS119 (n-channel, 100 V enhancement) * +* BSS169 (n-channel, 100 V depletion) * +* SISC0_5N10D (n-channel, 100 V depletion) * +* * +* BSP372 (n-channel, 100 V enhancement, Level 0 only) * +* BSS119N (n-channel, 100 V enhancement) * +* BSS123N (n-channel, 100 V enhancement) * +* BSL296SN (n-channel, 100 V enhancement) * +* BSL372SN (n-channel, 100 V enhancement) * +* BSL373SN (n-channel, 100 V enhancement) * +* BSP296N (n-channel, 100 V enhancement) * +* BSP372N (n-channel, 100 V enhancement) * +* BSP373N (n-channel, 100 V enhancement) * +***************************************************************** +* * +***************************************************************** +* thermal nodes of level 3 models: * +* * +* .SUBCKT BSP296 drain gate source Tj Tcase * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Tcase/Tsolder_joint : * +* node where the boundary contition - external heat * +* sinks etc - have to be connected (ideal heat sink * +* can be modeled by using a voltage source stating the * +* ambient temperature in °C between Tcase and ground. * +* * +***************************************************************** + +.SUBCKT K_100_a_var dd g s Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 heat=1 + +.PARAM Vth0=1.45 beta4c=0.215 ph0=25.7 ph1=0.038 Ubr=150 +.PARAM Rd=0.6 nmu=2.6 Rf=0.2 rpa=0.02925 lnIsj=-24.6 +.PARAM Rdi=0.073 + +.PARAM Tref=298 T0=273 auth=3m c=0.82 mu_bet=0.4 +.PARAM f_bet=-2 ndi=1.2 UTnbr=207m lnBr=-23 kbq=85.8u +.PARAM Wcml={beta4c*4*c} +.PARAM aubr={0.93m*UBr} +.PARAM dvgs={0.1-0.06*Vth0} + +.PARAM f1=118p f2=94p f3=140p f4=205p f5=267p +.PARAM U0=0.5 nd=0.48 nc=0.5 g1=4 bb=-3.2 +.PARAM sl=58p remp=0p ta=60n td=20n + +.PARAM Vmin=0.8 Vmax=1.8 dCmax=0.35 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM p0={Wcml*a*((1-f_bet)*(T0/Tref)**mu_bet+f_bet) } +.PARAM Rlim={(Rmax-Rs-(Unn-Vth0-Inn*Rs-SQRT((Unn-Vth0-Inn*Rs)**2-4*c*Inn/p0))/(2*c*Inn))/(1+rpa*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a,0),0)} +.PARAM bet={Wcml} + +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM Cox={f1*a*dC1} +.PARAM Cds0={f2*a*dC1} +.PARAM Cgs0={f3*a*dC1} +.PARAM Cox1={f5*a*dC1} +.PARAM Crand={remp*SQRT(a)} +.PARAM dRdi={Rdi/a} + +.FUNC U1(Uds,T) {(SQRT(1+4*(0.4+(T-T0-25)*2m)*abs(Uds))-1)/2/(0.4+(T-T0-25)*2m)} +.FUNC I2(p,Uee,z1,pp) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp-(min(0,Uee))**2)/p))} +.FUNC Ig(Uds,T,p,Uee) {bet*((1-f_bet)*(T0/T)**mu_bet+f_bet)*I2(p,Uee,min(Uds,Uee/(2*c)),min(2*p,p+c*Uds))} +.FUNC Iges(Uds,Ugs,T) + +{a*(sgn(Uds)*Ig(U1(Uds,T),T,1/(ph0-ph1*T),Ugs-Vth+auth*(T-Tref))+exp(min(lnBr+(abs(Uds)-UBr-aubr*(T-Tref))/UTnbr,25)))} + +.FUNC Isjt(Tj) {exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),9))*(Tj/Tref)**1.5} +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),9))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,Isjt(Tj))} + +.FUNC QCdg(x,z) {if(f4>f5,(f5**2-(f4-z*sl)**2)/(2*sl)+f5*min(x,(f4-f5)/sl),f4*z-sl*z**2/2-f5*max((f4-f5)/sl-x,0))} + +E_Edg d ox VALUE {V(d,g)-(min(V(d,g),-bb)+1/(g1*(1-nc))*((1/(1+g1*max(V(d,g)+bb,0)))**(nc-1)-1))} +C_Cdg ox g {Cox} +E_Edg1 d ox1 VALUE {V(d,g)-QCdg(V(d,g),limit(V(d,g),(f4-f5)/sl,f4/sl))/f5} +C_Cdg1 ox1 g {Cox1} +C_Cdg2 d g {Crand} + +E_Eds d edep VALUE {(V(d2,s)-I(V_sense3)/Cds0)} +C_Cds edep s {Cds0} +C_Cds2 d2 s {Cds0/500} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={Iges(V(d,s),V(g,s),T0+limit(V(Tj),-200,350))} +E_RMos d1 d VALUE={I(V_sense)*(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)*(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d2 VALUE={Idiod(V(s,d2),T0+limit(V(Tj),-200,499))} +R_Rdio d2 d3 {dRdi} +V_sense2 d1 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c f 0 +R_sense3 f 0 1 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {1Meg*Cds0*(1/(1-nd)*U0**nd*(limit(U0+V(d2,s),U0/2,2*UBr))**(1-nd)+2**nd*min(V(d2,s)+U0/2,0))} +R_R002 e c 1Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 10k + +G_TH 0 Tj VALUE = {heat*LIMIT(I(V_sense)*V(dd,s),0,100k)} + +.ENDS +*$ + +************************************************************************************** + + +.SUBCKT K_100_b_var dd g s Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 heat=1 + +.PARAM Vth0=1.6 beta4c=0.303 ph0=25.7 ph1=0.038 Ubr=150 +.PARAM Rd=0.6 nmu=2.6 Rf=0.2 rpa=0.02925 lnIsj=-24.6 +.PARAM Rdi=0.073 + +.PARAM Tref=298 T0=273 auth=3m c=0.82 mu_bet=0.4 +.PARAM f_bet=-2 ndi=1.2 UTnbr=207m lnBr=-23 kbq=85.8u +.PARAM Wcml={beta4c*4*c} +.PARAM aubr={0.93m*UBr} +.PARAM dvgs={0.1-0.06*Vth0} + +.PARAM f1=118p f2=118p f3=207p f4=205p f5=217p +.PARAM U0=0.5 nd=0.42 nc=0.5 g1=4 bb=-3.2 +.PARAM sl=58p remp=0p ta=60n td=20n + +.PARAM Vmin=0.8 Vmax=1.8 dCmax=0.35 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM p0={Wcml*a*((1-f_bet)*(T0/Tref)**mu_bet+f_bet) } +.PARAM Rlim={(Rmax-Rs-(Unn-Vth0-Inn*Rs-SQRT((Unn-Vth0-Inn*Rs)**2-4*c*Inn/p0))/(2*c*Inn))/(1+rpa*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a,0),0)} +.PARAM bet={Wcml} + +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM Cox={f1*a*dC1} +.PARAM Cds0={f2*a*dC1} +.PARAM Cgs0={f3*a*dC1} +.PARAM Cox1={f5*a*dC1} +.PARAM Crand={remp*SQRT(a)} +.PARAM dRdi={Rdi/a} + +.FUNC U1(Uds,T) {(SQRT(1+4*(0.4+(T-T0-25)*2m)*abs(Uds))-1)/2/(0.4+(T-T0-25)*2m)} +.FUNC I2(p,Uee,z1,pp) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp-(min(0,Uee))**2)/p))} +.FUNC Ig(Uds,T,p,Uee) {bet*((1-f_bet)*(T0/T)**mu_bet+f_bet)*I2(p,Uee,min(Uds,Uee/(2*c)),min(2*p,p+c*Uds))} +.FUNC Iges(Uds,Ugs,T) + +{a*(sgn(Uds)*Ig(U1(Uds,T),T,1/(ph0-ph1*T),Ugs-Vth+auth*(T-Tref))+exp(min(lnBr+(abs(Uds)-UBr-aubr*(T-Tref))/UTnbr,25)))} + +.FUNC Isjt(Tj) {exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),9))*(Tj/Tref)**1.5} +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),9))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,Isjt(Tj))} + +.FUNC QCdg(x,z) {if(f4>f5,(f5**2-(f4-z*sl)**2)/(2*sl)+f5*min(x,(f4-f5)/sl),f4*z-sl*z**2/2-f5*max((f4-f5)/sl-x,0))} + +E_Edg d ox VALUE {V(d,g)-(min(V(d,g),-bb)+1/(g1*(1-nc))*((1/(1+g1*max(V(d,g)+bb,0)))**(nc-1)-1))} +C_Cdg ox g {Cox} +E_Edg1 d ox1 VALUE {V(d,g)-QCdg(V(d,g),limit(V(d,g),(f4-f5)/sl,f4/sl))/f5} +C_Cdg1 ox1 g {Cox1} +C_Cdg2 d g {Crand} + +E_Eds d edep VALUE {(V(d2,s)-I(V_sense3)/Cds0)} +C_Cds edep s {Cds0} +C_Cds2 d2 s {Cds0/500} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={Iges(V(d,s),V(g,s),T0+limit(V(Tj),-200,350))} +E_RMos d1 d VALUE={I(V_sense)*(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)*(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d2 VALUE={Idiod(V(s,d2),T0+limit(V(Tj),-200,499))} +R_Rdio d2 d3 {dRdi} +V_sense2 d1 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c f 0 +R_sense3 f 0 1 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {1Meg*Cds0*(1/(1-nd)*U0**nd*(limit(U0+V(d2,s),U0/2,2*UBr))**(1-nd)+2**nd*min(V(d2,s)+U0/2,0))} +R_R002 e c 1Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 10k + +G_TH 0 Tj VALUE = {heat*LIMIT(I(V_sense)*V(dd,s),0,100k)} + +.ENDS +*$ + +************************************************************************************** + + +.SUBCKT K_100_c_var dd g s Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 heat=1 + +.PARAM Vth0=2.07 beta4c=0.303 ph0=25.7 ph1=0.038 Ubr=150 +.PARAM Rd=0.6 nmu=2.6 Rf=0.2 rpa=0.02925 lnIsj=-24.6 +.PARAM Rdi=0.073 + +.PARAM Tref=298 T0=273 auth=3m c=0.82 mu_bet=0.4 +.PARAM f_bet=-2 ndi=1.2 UTnbr=207m lnBr=-23 kbq=85.8u +.PARAM Wcml={beta4c*4*c} +.PARAM aubr={0.93m*UBr} +.PARAM dvgs={0.1-0.06*Vth0} + +.PARAM f1=118p f2=118p f3=207p f4=205p f5=217p +.PARAM U0=0.5 nd=0.42 nc=0.5 g1=4 bb=-3.2 +.PARAM sl=58p remp=0p ta=60n td=20n + +.PARAM Vmin=1.3 Vmax=2.3 dCmax=0.35 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM p0={Wcml*a*((1-f_bet)*(T0/Tref)**mu_bet+f_bet) } +.PARAM Rlim={(Rmax-Rs-(Unn-Vth0-Inn*Rs-SQRT((Unn-Vth0-Inn*Rs)**2-4*c*Inn/p0))/(2*c*Inn))/(1+rpa*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a,0),0)} +.PARAM bet={Wcml} + +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM Cox={f1*a*dC1} +.PARAM Cds0={f2*a*dC1} +.PARAM Cgs0={f3*a*dC1} +.PARAM Cox1={f5*a*dC1} +.PARAM Crand={remp*SQRT(a)} +.PARAM dRdi={Rdi/a} + +.FUNC U1(Uds,T) {(SQRT(1+4*(0.4+(T-T0-25)*2m)*abs(Uds))-1)/2/(0.4+(T-T0-25)*2m)} +.FUNC I2(p,Uee,z1,pp) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp-(min(0,Uee))**2)/p))} +.FUNC Ig(Uds,T,p,Uee) {bet*((1-f_bet)*(T0/T)**mu_bet+f_bet)*I2(p,Uee,min(Uds,Uee/(2*c)),min(2*p,p+c*Uds))} +.FUNC Iges(Uds,Ugs,T) + +{a*(sgn(Uds)*Ig(U1(Uds,T),T,1/(ph0-ph1*T),Ugs-Vth+auth*(T-Tref))+exp(min(lnBr+(abs(Uds)-UBr-aubr*(T-Tref))/UTnbr,25)))} + +.FUNC Isjt(Tj) {exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),9))*(Tj/Tref)**1.5} +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),9))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,Isjt(Tj))} + +.FUNC QCdg(x,z) {if(f4>f5,(f5**2-(f4-z*sl)**2)/(2*sl)+f5*min(x,(f4-f5)/sl),f4*z-sl*z**2/2-f5*max((f4-f5)/sl-x,0))} + +E_Edg d ox VALUE {V(d,g)-(min(V(d,g),-bb)+1/(g1*(1-nc))*((1/(1+g1*max(V(d,g)+bb,0)))**(nc-1)-1))} +C_Cdg ox g {Cox} +E_Edg1 d ox1 VALUE {V(d,g)-QCdg(V(d,g),limit(V(d,g),(f4-f5)/sl,f4/sl))/f5} +C_Cdg1 ox1 g {Cox1} +C_Cdg2 d g {Crand} + +E_Eds d edep VALUE {(V(d2,s)-I(V_sense3)/Cds0)} +C_Cds edep s {Cds0} +C_Cds2 d2 s {Cds0/500} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={Iges(V(d,s),V(g,s),T0+limit(V(Tj),-200,350))} +E_RMos d1 d VALUE={I(V_sense)*(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)*(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d2 VALUE={Idiod(V(s,d2),T0+limit(V(Tj),-200,499))} +R_Rdio d2 d3 {dRdi} +V_sense2 d1 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c f 0 +R_sense3 f 0 1 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {1Meg*Cds0*(1/(1-nd)*U0**nd*(limit(U0+V(d2,s),U0/2,2*UBr))**(1-nd)+2**nd*min(V(d2,s)+U0/2,0))} +R_R002 e c 1Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 10k + +G_TH 0 Tj VALUE = {heat*LIMIT(I(V_sense)*V(dd,s),0,100k)} + +.ENDS +*$ + +************************************************************************************** + + +.SUBCKT K_100_d_var dd g s Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 heat=1 + +.PARAM Vth0=-1.8 beta4c=0.303 ph0=20 ph1=0.026 Ubr=150 +.PARAM Rd=0.6 nmu=2.6 Rf=0.2 rpa=0.02925 lnIsj=-24.6 +.PARAM Rdi=0.073 + +.PARAM Tref=298 T0=273 auth=3m c=0.82 mu_bet=0.4 +.PARAM f_bet=-2 ndi=1.2 UTnbr=207m lnBr=-23 kbq=85.8u +.PARAM Wcml={beta4c*4*c} +.PARAM aubr={0.93m*UBr} +.PARAM dvgs={0.1-0.06*Vth0} + +.PARAM f1=118p f2=118p f3=207p f4=330p f5=217p +.PARAM U0=0.5 nd=0.42 nc=0.5 g1=4 bb=-10.8 +.PARAM sl=30p remp=0p ta=60n td=20n + +.PARAM Vmin=-2.9 Vmax=-1.8 dCmax=0.35 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM p0={Wcml*a*((1-f_bet)*(T0/Tref)**mu_bet+f_bet) } +.PARAM Rlim={(Rmax-Rs-(Unn-Vth0-Inn*Rs-SQRT((Unn-Vth0-Inn*Rs)**2-4*c*Inn/p0))/(2*c*Inn))/(1+rpa*(Inn/a)**2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a,0),0)} +.PARAM bet={Wcml} + +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM Cox={f1*a*dC1} +.PARAM Cds0={f2*a*dC1} +.PARAM Cgs0={f3*a*dC1} +.PARAM Cox1={f5*a*dC1} +.PARAM Crand={remp*SQRT(a)} +.PARAM dRdi={Rdi/a} + +.FUNC U1(Uds,T) {(SQRT(1+4*(0.4+(T-T0-25)*2m)*abs(Uds))-1)/2/(0.4+(T-T0-25)*2m)} +.FUNC I2(p,Uee,z1,pp) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp-(min(0,Uee))**2)/p))} +.FUNC Ig(Uds,T,p,Uee) {bet*((1-f_bet)*(T0/T)**mu_bet+f_bet)*I2(p,Uee,min(Uds,Uee/(2*c)),min(2*p,p+c*Uds))} +.FUNC Iges(Uds,Ugs,T) + +{a*(sgn(Uds)*Ig(U1(Uds,T),T,1/(ph0-ph1*T),Ugs-Vth+auth*(T-Tref))+exp(min(lnBr+(abs(Uds)-UBr-aubr*(T-Tref))/UTnbr,25)))} + +.FUNC Isjt(Tj) {exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),9))*(Tj/Tref)**1.5} +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),9))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,Isjt(Tj))} + +.FUNC QCdg(x,z) {if(f4>f5,(f5**2-(f4-z*sl)**2)/(2*sl)+f5*min(x,(f4-f5)/sl),f4*z-sl*z**2/2-f5*max((f4-f5)/sl-x,0))} + +E_Edg d ox VALUE {V(d,g)-(min(V(d,g),-bb)+1/(g1*(1-nc))*((1/(1+g1*max(V(d,g)+bb,0)))**(nc-1)-1))} +C_Cdg ox g {Cox} +E_Edg1 d ox1 VALUE {V(d,g)-QCdg(V(d,g),limit(V(d,g),(f4-f5)/sl,f4/sl))/f5} +C_Cdg1 ox1 g {Cox1} +C_Cdg2 d g {Crand} + +E_Eds d edep VALUE {(V(d2,s)-I(V_sense3)/Cds0)} +C_Cds edep s {Cds0} +C_Cds2 d2 s {Cds0/500} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={Iges(V(d,s),V(g,s),T0+limit(V(Tj),-200,350))} +E_RMos d1 d VALUE={I(V_sense)*(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)*(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d2 VALUE={Idiod(V(s,d2),T0+limit(V(Tj),-200,499))} +R_Rdio d2 d3 {dRdi} +V_sense2 d1 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c f 0 +R_sense3 f 0 1 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {1Meg*Cds0*(1/(1-nd)*U0**nd*(limit(U0+V(d2,s),U0/2,2*UBr))**(1-nd)+2**nd*min(V(d2,s)+U0/2,0))} +R_R002 e c 1Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 10k + +G_TH 0 Tj VALUE = {heat*LIMIT(I(V_sense)*V(dd,s),0,100k)} + +.ENDS +*$ + +***************************************************************************************************** + +.SUBCKT BSP296 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.027 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.1 Unn=10 Rmax=0.7 +.PARAM act=2 + +X1 d1 g s Tj K_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=1 + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {118.56m+limit(Zthtype,0,1)*43.88m} +Rth2 t1 t2 {347.23m+limit(Zthtype,0,1)*128.51m} +Rth3 t2 t3 {3.59+limit(Zthtype,0,1)*120.87m} +Rth4 t3 t4 {7.52+limit(Zthtype,0,1)*2.58} +Rth5 t4 Tcase {7.85+limit(Zthtype,0,1)*2.7} +Cth1 Tj 0 36.815u +Cth2 t1 0 164.552u +Cth3 t2 0 417.212u +Cth4 t3 0 5.466m +Cth5 t4 0 48.845m + + +.ENDS +*$ + +******************** + +.SUBCKT BSS123 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.074 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.17 Unn=10 Rmax=6 +.PARAM act=0.25 + +X1 d1 g s Tj K_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=1 + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {626.01m+limit(Zthtype,0,1)*231.69m} +Rth2 t1 t2 {2.86+limit(Zthtype,0,1)*1.06} +Rth3 t2 t3 {6.1+limit(Zthtype,0,1)*1.02} +Rth4 t3 t4 {68.15+limit(Zthtype,0,1)*57.85} +Rth5 t4 Tcase {79.56+limit(Zthtype,0,1)*67.54} +Cth1 Tj 0 4.89u +Cth2 t1 0 15.613u +Cth3 t2 0 132.666u +Cth4 t3 0 374.154u +Cth5 t4 0 4.696m + + +.ENDS +*$ + +******************** + +.SUBCKT BSP123 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.027 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.37 Unn=10 Rmax=6 +.PARAM act=0.25 + +X1 d1 g s Tj K_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=1 + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {626.01m+limit(Zthtype,0,1)*231.69m} +Rth2 t1 t2 {2.86+limit(Zthtype,0,1)*1.06} +Rth3 t2 t3 {4.57+limit(Zthtype,0,1)*1.02} +Rth4 t3 t4 {4.5+limit(Zthtype,0,1)*853.28m} +Rth5 t4 Tcase {7.8+limit(Zthtype,0,1)*1.48} +Cth1 Tj 0 4.89u +Cth2 t1 0 15.613u +Cth3 t2 0 132.666u +Cth4 t3 0 5.466m +Cth5 t4 0 48.845m + + +.ENDS +*$ + +******************** + +.SUBCKT BSS119 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.074 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.17 Unn=10 Rmax=6 +.PARAM act=0.25 + +X1 d1 g s Tj K_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=1 + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {626.01m+limit(Zthtype,0,1)*231.69m} +Rth2 t1 t2 {2.86+limit(Zthtype,0,1)*1.06} +Rth3 t2 t3 {6.1+limit(Zthtype,0,1)*1.02} +Rth4 t3 t4 {68.15+limit(Zthtype,0,1)*57.85} +Rth5 t4 Tcase {79.56+limit(Zthtype,0,1)*67.54} +Cth1 Tj 0 4.89u +Cth2 t1 0 15.613u +Cth3 t2 0 132.666u +Cth4 t3 0 374.154u +Cth5 t4 0 4.696m + + +.ENDS +*$ + +******************** + +.SUBCKT BSS169 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.074 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.05 Unn=0 Rmax=12 +.PARAM act=0.25 + +X1 d1 g s Tj K_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=1 + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {626.01m+limit(Zthtype,0,1)*231.69m} +Rth2 t1 t2 {2.86+limit(Zthtype,0,1)*1.06} +Rth3 t2 t3 {6.1+limit(Zthtype,0,1)*1.02} +Rth4 t3 t4 {68.15+limit(Zthtype,0,1)*57.85} +Rth5 t4 Tcase {79.56+limit(Zthtype,0,1)*67.54} +Cth1 Tj 0 4.89u +Cth2 t1 0 15.613u +Cth3 t2 0 132.666u +Cth4 t3 0 374.154u +Cth5 t4 0 4.696m + + +.ENDS +*$ + +******************** + +.SUBCKT SISC0_5N10D drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.005 Rg=10 +.PARAM Inn=0.05 Unn=0 Rmax=12 +.PARAM act=0.25 + +X1 drain g s Tj K_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=1 + +Rg gate g {Rg} + +Gs source s VALUE={V(source,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa source s 1Meg + + + +Rth1 Tj t1 {626.01m+limit(Zthtype,0,1)*231.69m} +Rth2 t1 t2 {2.86+limit(Zthtype,0,1)*1.06} +Rth3 t2 t3 {3.57+limit(Zthtype,0,1)*1.02} +Rth4 t3 t4 {1p+limit(Zthtype,0,1)*0p} +Rth5 t4 Tcase {1p+limit(Zthtype,0,1)*0p} +Cth1 Tj 0 4.89u +Cth2 t1 0 15.613u +Cth3 t2 0 132.666u +Cth4 t3 0 1p +Cth5 t4 0 1p + + +.ENDS +*$ + +******************** + +.SUBCKT BSP296_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.027 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.1 Unn=10 Rmax=0.7 +.PARAM act=2 + +X1 d1 g s Tj K_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS +*$ + +********** + +.SUBCKT BSS123_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.074 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.17 Unn=10 Rmax=6 +.PARAM act=0.25 + +X1 d1 g s Tj K_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS +*$ + +********** + +.SUBCKT BSP123_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.027 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.37 Unn=10 Rmax=6 +.PARAM act=0.25 + +X1 d1 g s Tj K_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS +*$ + +********** + +.SUBCKT BSS119_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.074 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.17 Unn=10 Rmax=6 +.PARAM act=0.25 + +X1 d1 g s Tj K_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS +*$ + +********** + +.SUBCKT BSS169_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.074 Rg=10 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.05 Unn=0 Rmax=12 +.PARAM act=0.25 + +X1 d1 g s Tj K_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS +*$ + +********** + +.SUBCKT SISC0_5N10D_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.005 Rg=10 +.PARAM Inn=0.05 Unn=0 Rmax=12 +.PARAM act=0.25 + +X1 drain g s Tj K_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} heat=0 +Rg gate g {Rg} + +Gs source s VALUE={V(source,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa source s 1Meg + + + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS +*$ + +********** + + +.SUBCKT K_100_x_var dd g s Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 + +.PARAM Fm=0.15 Fn=0.5 al=1 +.PARAM c=1 Vth0=2.45 auth=2.68m +.PARAM UT=100m ab=90m lB=-22.1 UB=106 + +.PARAM b0=14.72 p0=6.573 p1=-22.5m p2=36u + +.PARAM Rd=142m nmu=2.66 Tref=298 T0=273 lnIsj=-22.11 +.PARAM ndi=1.32 Rdi=16.2m nmu2=0.071 ta=30n +.PARAM Rf=0.2 nmu3=1.5 + +.PARAM kbq=85.8u +.PARAM rand=1 + +.PARAM f3=210p +.PARAM f2=195p U0=1 nd=0.7 f2b=1p +.PARAM f1=500p nc=1.15 g1=0.95 bb=0 remp=5p + +.PARAM Vmin=1.95 Vmax=2.95 dCmax=0.33 + +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+1.5*dCmax*limit(dC,0,1)} + +.PARAM Cds0={f2*a*dC1} +.PARAM Cox={f1*a*dC2} +.PARAM Cox1={remp*SQRT(a)*dC2} +.Param Cgs0={f3*a*dC1} +.PARAM dRdi={Rdi/a} + + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC J(d,g,T,da,s) ++ {a*(s*(Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn+1*limit(-d,0,1))+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +E_Edg d ox VALUE {1*(max(V(d,g),-bb)-(1/(g1*(1-nc))*((1/(1+g1*max(V(d,g)+bb,0)))**(nc-1)-(1/(1+g1*bb))**(nc-1))))} +C_Cdg ox g {Cox} +C_Cdg1 d g {Cox1} + +E_Eds d edep VALUE {V(d,s)-1/(1-nd)*U0*((limit(1+V(d,s)/U0,0,2*UB))**(1-nd)-1)} +C_Cds edep s {Cds0*0.99} + +C_Cgs g s {Cgs0} + +G_chan d5a s VALUE={J(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d5a,s)))-1)/2/al,sgn(V(d5a,s)))} +Rd06 d5a d5 0.1u +V_sm d d5 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)} +V_sense dd d1 0 + +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +Dbody s d3 dbody +.model dbody D (BV= {UB*10},CJO ={Cds0/100},TT ={ta},IS ={a*exp(lnIsj)} m={0.5} RS={dRdi*1m} n={ndi}) + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)} + +.ENDS + +************* + + +.SUBCKT K_100_y_var dd g s Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 + +.PARAM Fm=0.15 Fn=0.5 al=1 +.PARAM c=0.738 Vth0=1.87 auth=2.16m +.PARAM UT=100m ab=90m lB=-22.1 UB=106 + +.PARAM b0=15.44 p0=4.896 p1=-15m p2=24u + +.PARAM Rd=142m nmu=2.66 Tref=298 T0=273 lnIsj=-22.11 +.PARAM ndi=1.329 Rdi=16.2m nmu2=0.071 ta=30n +.PARAM Rf=0.2 nmu3=1.5 + +.PARAM kbq=85.8u +.PARAM rand=1 + +.PARAM f3=210p +.PARAM f2=195p U0=1 nd=0.7 f2b=1p +.PARAM f1=500p nc=1.15 g1=0.95 bb=0 remp=5p + +.PARAM Vmin=1.37 Vmax=2.37 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+1.5*dCmax*limit(dC,0,1)} + +.PARAM Cds0={f2*a*dC1} +.PARAM Cox={f1*a*dC2} +.PARAM Cox1={remp*SQRT(a)*dC2} +.Param Cgs0={f3*a*dC1} +.PARAM dRdi={Rdi/a} + + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC J(d,g,T,da,s) ++ {a*(s*(Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn+1*limit(-d,0,1))+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +E_Edg d ox VALUE {1*(max(V(d,g),-bb)-(1/(g1*(1-nc))*((1/(1+g1*max(V(d,g)+bb,0)))**(nc-1)-(1/(1+g1*bb))**(nc-1))))} +C_Cdg ox g {Cox} +C_Cdg1 d g {Cox1} + +E_Eds d edep VALUE {V(d,s)-1/(1-nd)*U0*((limit(1+V(d,s)/U0,0,2*UB))**(1-nd)-1)} +C_Cds edep s {Cds0*0.99} + +C_Cgs g s {Cgs0} + +G_chan d5a s VALUE={J(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d5a,s)))-1)/2/al,sgn(V(d5a,s)))} +Rd06 d5a d5 0.1u +V_sm d d5 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)} +V_sense dd d1 0 + +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +Dbody s d3 dbody +.model dbody D (BV= {UB*10},CJO ={Cds0/100},TT ={ta},IS ={a*exp(lnIsj)} m={0.5} RS={dRdi*1m} n={ndi}) + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)} + +.ENDS + +************* + +.SUBCKT K_100_z_var dd g s Tj PARAMS: a=1 Rsp=1 dVth=0 dR=0 dgfs=0 Inn=1 ++Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 + +.PARAM Fm=0.6 Fn=0.5 al=1 +.PARAM c=1.5 Vth0=4.18 auth=3.7m +.PARAM UT=100m ab=90m lB=-22.1 UB=106 + +.PARAM b0=12.8 p0=7.083 p1=-21.5m p2=37u + +.PARAM Rd=162m nmu=2.66 Tref=298 T0=273 lnIsj=-23.6 +.PARAM ndi=1.28 Rdi=16.2m nmu2=0.071 ta=30n +.PARAM Rf=0.2 nmu3=1.5 + +.PARAM kbq=85.8u +.PARAM rand=1 + +.PARAM f3=170p +.PARAM f2=195p U0=1 nd=0.7 f2b=1p +.PARAM f1=250p nc=3.04 g1=0.11 bb=0 remp=8.9p + +.PARAM Vmin=3.38 Vmax=4.98 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} +.PARAM dC2={1+1.5*dCmax*limit(dC,0,1)} + +.PARAM Cds0={f2*a*dC1} +.PARAM Cox={f1*a*dC2} +.PARAM Cox1={remp*SQRT(a)*dC2} +.Param Cgs0={f3*a*dC1} +.PARAM dRdi={Rdi/a} + + +.FUNC I0(Uee,p,pp,z1) {if(Uee>pp,(Uee-c*z1)*z1,p*(pp-p)/c*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+c*Uds),min(Uds,Uee/(2*c)))} +.FUNC J(d,g,T,da,s) ++ {a*(s*(Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn+1*limit(-d,0,1))+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +E_Edg d ox VALUE {1*(max(V(d,g),-bb)-(1/(g1*(1-nc))*((1/(1+g1*max(V(d,g)+bb,0)))**(nc-1)-(1/(1+g1*bb))**(nc-1))))} +C_Cdg ox g {Cox} +C_Cdg1 d g {Cox1} + +E_Eds d edep VALUE {V(d,s)-1/(1-nd)*U0*((limit(1+V(d,s)/U0,0,2*UB))**(1-nd)-1)} +C_Cds edep s {Cds0*0.99} + +C_Cgs g s {Cgs0} + +G_chan d5a s VALUE={J(V(d5a,s),V(g,s),T0+limit(V(Tj),-200,500),(SQRT(1+4*al*abs(V(d5a,s)))-1)/2/al,sgn(V(d5a,s)))} +Rd06 d5a d5 0.1u +V_sm d d5 +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)} +V_sense dd d1 0 + +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +Dbody s d3 dbody +.model dbody D (BV= {UB*10},CJO ={Cds0/100},TT ={ta},IS ={a*exp(lnIsj)} m={0.5} RS={dRdi*1m} n={ndi}) + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +G_TH 0 Tj VALUE = ++{(I(V_sense)-I(V_sense2))*V(d1,d)+I(V_sm)*V(d,s)+I(V_sense2)*V(d1,s)} + +.ENDS + + +************************************************************************************************ + +.SUBCKT BSS119N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.06 Rg=12 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.19 Unn=10 Rmax=6 +.PARAM act=0.065 + +X1 d1 g s Tj K_100_x_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {699.7m+limit(Zthtype,0,1)*258.95m} +Rth2 t1 t2 {5.28+limit(Zthtype,0,1)*1.95} +Rth3 t2 t3 {12.37+limit(Zthtype,0,1)*6.68} +Rth4 t3 t4 {43.48+limit(Zthtype,0,1)*23.24} +Rth5 t4 Tcase {30+limit(Zthtype,0,1)*16.04} +Cth1 Tj 0 496.224n +Cth2 t1 0 2.173u +Cth3 t2 0 19.129u +Cth4 t3 0 414u +Cth5 t4 0 6.75m + + +.ENDS + +********** + +.SUBCKT BSS123N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.06 Rg=12 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.19 Unn=10 Rmax=6 +.PARAM act=0.065 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {699.7m+limit(Zthtype,0,1)*258.95m} +Rth2 t1 t2 {5.28+limit(Zthtype,0,1)*1.95} +Rth3 t2 t3 {12.37+limit(Zthtype,0,1)*6.68} +Rth4 t3 t4 {43.48+limit(Zthtype,0,1)*23.24} +Rth5 t4 Tcase {30+limit(Zthtype,0,1)*16.04} +Cth1 Tj 0 496.224n +Cth2 t1 0 2.173u +Cth3 t2 0 19.129u +Cth4 t3 0 414u +Cth5 t4 0 6.75m + + +.ENDS + +********** + +.SUBCKT BSL296SN drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.012 Rg=14.5 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.39 Unn=10 Rmax=0.46 +.PARAM act=0.5 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {79.28m+limit(Zthtype,0,1)*29.34m} +Rth2 t1 t2 {788.03m+limit(Zthtype,0,1)*291.64m} +Rth3 t2 t3 {3.96+limit(Zthtype,0,1)*832.48m} +Rth4 t3 t4 {9.61+limit(Zthtype,0,1)*0p} +Rth5 t4 Tcase {16.11+limit(Zthtype,0,1)*0p} +Cth1 Tj 0 4.328u +Cth2 t1 0 13.013u +Cth3 t2 0 122.254u +Cth4 t3 0 153.479u +Cth5 t4 0 2.69m + + +.ENDS + +******************** + +.SUBCKT BSP296N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.027 Rg=14.5 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.1 Unn=10 Rmax=0.6 +.PARAM act=0.5 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {79.28m+limit(Zthtype,0,1)*29.34m} +Rth2 t1 t2 {788.03m+limit(Zthtype,0,1)*291.64m} +Rth3 t2 t3 {3.96+limit(Zthtype,0,1)*832.48m} +Rth4 t3 t4 {7.52+limit(Zthtype,0,1)*1.79} +Rth5 t4 Tcase {7.85+limit(Zthtype,0,1)*1.86} +Cth1 Tj 0 4.328u +Cth2 t1 0 13.013u +Cth3 t2 0 122.254u +Cth4 t3 0 6.586m +Cth5 t4 0 48.845m + + +.ENDS + +********** + +.SUBCKT BSL373SN drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.012 Rg=23 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.97 Unn=10 Rmax=0.23 +.PARAM act=1.088 + +X1 d1 g s Tj K_100_z_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {36.28m+limit(Zthtype,0,1)*13.42m} +Rth2 t1 t2 {354.32m+limit(Zthtype,0,1)*131.13m} +Rth3 t2 t3 {2.1+limit(Zthtype,0,1)*389.18m} +Rth4 t3 t4 {4.79+limit(Zthtype,0,1)*126.56m} +Rth5 t4 Tcase {16.62+limit(Zthtype,0,1)*439.11m} +Cth1 Tj 0 9.457u +Cth2 t1 0 28.085u +Cth3 t2 0 256.579u +Cth4 t3 0 137.027u +Cth5 t4 0 2.441m + + +.ENDS + +******************** + +.SUBCKT BSP373N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.014 Rg=23 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.8 Unn=10 Rmax=0.24 +.PARAM act=1.088 + +X1 d1 g s Tj K_100_z_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {36.28m+limit(Zthtype,0,1)*13.42m} +Rth2 t1 t2 {354.32m+limit(Zthtype,0,1)*131.13m} +Rth3 t2 t3 {2.1+limit(Zthtype,0,1)*389.18m} +Rth4 t3 t4 {7.52+limit(Zthtype,0,1)*3.23} +Rth5 t4 Tcase {7.85+limit(Zthtype,0,1)*3.37} +Cth1 Tj 0 9.457u +Cth2 t1 0 28.085u +Cth3 t2 0 256.579u +Cth4 t3 0 6.76m +Cth5 t4 0 48.845m + + +.ENDS + +********** + +.SUBCKT BSL372SN drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.012 Rg=23 Ls=3n Ld=1n Lg=3n +.PARAM Inn=2 Unn=10 Rmax=0.22 +.PARAM act=1.088 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {36.28m+limit(Zthtype,0,1)*13.42m} +Rth2 t1 t2 {354.32m+limit(Zthtype,0,1)*131.13m} +Rth3 t2 t3 {2.1+limit(Zthtype,0,1)*389.18m} +Rth4 t3 t4 {4.79+limit(Zthtype,0,1)*126.56m} +Rth5 t4 Tcase {16.62+limit(Zthtype,0,1)*439.11m} +Cth1 Tj 0 9.457u +Cth2 t1 0 28.085u +Cth3 t2 0 256.579u +Cth4 t3 0 137.027u +Cth5 t4 0 2.441m + + +.ENDS + +******************** + +.SUBCKT BSP372N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 + +.PARAM Rs=0.014 Rg=23 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.8 Unn=10 Rmax=0.23 +.PARAM act=1.088 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} + +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +Rth1 Tj t1 {36.28m+limit(Zthtype,0,1)*13.42m} +Rth2 t1 t2 {354.32m+limit(Zthtype,0,1)*131.13m} +Rth3 t2 t3 {2.1+limit(Zthtype,0,1)*389.18m} +Rth4 t3 t4 {7.52+limit(Zthtype,0,1)*3.23} +Rth5 t4 Tcase {7.85+limit(Zthtype,0,1)*3.37} +Cth1 Tj 0 9.457u +Cth2 t1 0 28.085u +Cth3 t2 0 256.579u +Cth4 t3 0 6.76m +Cth5 t4 0 48.845m + + +.ENDS + +********** + +.SUBCKT BSS119N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.06 Rg=12 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.19 Unn=10 Rmax=6 +.PARAM act=0.065 + +X1 d1 g s Tj K_100_x_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSS123N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.06 Rg=12 Ls=3n Ld=1n Lg=3n +.PARAM Inn=0.19 Unn=10 Rmax=6 +.PARAM act=0.065 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSL296SN_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.012 Rg=14.5 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.39 Unn=10 Rmax=0.46 +.PARAM act=0.5 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSP296N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.027 Rg=14.5 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.1 Unn=10 Rmax=0.6 +.PARAM act=0.5 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSL373SN_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.012 Rg=23 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.97 Unn=10 Rmax=0.23 +.PARAM act=1.088 + +X1 d1 g s Tj K_100_z_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSP373N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.014 Rg=23 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.8 Unn=10 Rmax=0.24 +.PARAM act=1.088 + +X1 d1 g s Tj K_100_z_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSL372SN_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.012 Rg=23 Ls=3n Ld=1n Lg=3n +.PARAM Inn=2 Unn=10 Rmax=0.22 +.PARAM act=1.088 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSP372N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 + +.PARAM Rs=0.014 Rg=23 Ls=3n Ld=1n Lg=3n +.PARAM Inn=1.8 Unn=10 Rmax=0.23 +.PARAM act=1.088 + +X1 d1 g s Tj K_100_y_var PARAMS: a={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} + +Rmax={Rmax} dgfs={dgfs} Rs={Rs} dC={dC} +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m))} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Ld drain d1 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSP296_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.027 + +Rg g1 g2 10 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1.5 VTO=1.6 THETA=0 VMAX=1.5e5 ETA=0 LEVEL=3) +Rd d2 d1a 0.25 TC=11m +.MODEL MVDR NMOS (KP=7 VTO=-1.4 LAMBDA=0.1) +Mr d1 d2a d1a d1a MVDR W=1u L=1u +Rx d2a d1a 1m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=150 M=0.45 CJO=246p VJ=0.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=50p N=1.2 RS=67u EG=1.12 TT=60n) +Rdiode d1 21 36.5m TC=5m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 770p +.MODEL DGD D(M=0.8 CJO=770p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 280p + +.ENDS BSP296_L0 + +****** + +.SUBCKT BSS123_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.074 + +Rg g1 g2 10 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 0.278 VTO=1.8 THETA=0 VMAX=1.5e5 ETA=0 LEVEL=3) +Rd d2 d1a 2 TC=11m +.MODEL MVDR NMOS (KP=0.88 VTO=-1.4 LAMBDA=0.1) +Mr d1 d2a d1a d1a MVDR W=1u L=1u +Rx d2a d1a 1m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=150 M=0.45 CJO=30.75p VJ=0.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=6.3p N=1.2 RS=532u EG=1.12 TT=60n) +Rdiode d1 21 292m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 83.75p +.MODEL DGD D(M=0.74 CJO=83.75p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 51.75p + +.ENDS BSS123_L0 + +****** + +.SUBCKT BSP123_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.027 + +Rg g1 g2 10 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 0.278 VTO=1.8 THETA=0 VMAX=1.5e5 ETA=0 LEVEL=3) +Rd d2 d1a 2 TC=11m +.MODEL MVDR NMOS (KP=0.88 VTO=-1.4 LAMBDA=0.1) +Mr d1 d2a d1a d1a MVDR W=1u L=1u +Rx d2a d1a 1m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=150 M=0.45 CJO=30.75p VJ=0.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=6.3p N=1.2 RS=532u EG=1.12 TT=60n) +Rdiode d1 21 292m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 83.75p +.MODEL DGD D(M=0.74 CJO=83.75p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 51.75p + +.ENDS BSP123_L0 + +****** + +.SUBCKT BSS119_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.074 + +Rg g1 g2 10 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 0.278 VTO=2.27 THETA=0 VMAX=1.5e5 ETA=0 LEVEL=3) +Rd d2 d1a 2 TC=11m +.MODEL MVDR NMOS (KP=0.88 VTO=-1.4 LAMBDA=0.1) +Mr d1 d2a d1a d1a MVDR W=1u L=1u +Rx d2a d1a 1m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=150 M=0.45 CJO=30.75p VJ=0.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=6.3p N=1.2 RS=532u EG=1.12 TT=60n) +Rdiode d1 21 292m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 83.75p +.MODEL DGD D(M=0.74 CJO=83.75p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 51.75p + +.ENDS BSS119_L0 + +****** + +.SUBCKT BSS169_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.074 + +Rg g1 g2 10 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 0.278 VTO=-1.6 THETA=0 VMAX=1.5e5 ETA=0 LEVEL=3) +Rd d2 d1a 2 TC=11m +.MODEL MVDR NMOS (KP=0.88 VTO=-1.4 LAMBDA=0.15) +Mr d1 d2a d1a d1a MVDR W=1u L=1u +Rx d2a d1a 1m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=150 M=0.45 CJO=30.75p VJ=0.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=6.3p N=1.2 RS=532u EG=1.12 TT=60n) +Rdiode d1 21 292m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 83.75p +.MODEL DGD D(M=0.47 CJO=83.75p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 51.75p + +.ENDS BSS169_L0 + +****** + +.SUBCKT SISC0_5N10D_L0 drain gate source + + + + +Rs source s2 0.005 + +Rg gate g2 10 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 0.278 VTO=-1.6 THETA=0 VMAX=1.5e5 ETA=0 LEVEL=3) +Rd d2 d1a 2 TC=11m +.MODEL MVDR NMOS (KP=0.88 VTO=-1.4 LAMBDA=0.15) +Mr drain d2a d1a d1a MVDR W=1u L=1u +Rx d2a d1a 1m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=150 M=0.45 CJO=30.75p VJ=0.5V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=6.3p N=1.2 RS=532u EG=1.12 TT=60n) +Rdiode drain 21 292m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 83.75p +.MODEL DGD D(M=0.47 CJO=83.75p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 51.75p + +.ENDS SISC0_5N10D_L0 + +************************************************************************************************************ + +.SUBCKT BSP372_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 35m + +Rg g1 g2 10 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 9 VTO=1.8 THETA=0 VMAX=1.5e5 ETA=0.000 LEVEL=3) +Rd d1 d2 175m TC=9m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=110 M=0.5 CJO=250p VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.0 RS=2.41u EG=1.12 TT=65n) +Rdiode d1 21 100m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 800p +.MODEL DGD D(M=2 CJO=800p VJ=1) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cox1 d2 g2 15p +Cgs g2 s2 370p + +.ENDS BSP372_L0 + +****** + +.SUBCKT BSS119N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.06 + +Rg g1 g2 12 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 0.748 VTO=2.45 THETA=0 VMAX=1.5e5 ETA=0.004 LEVEL=3) +Rd d2 d1 2.185 TC=10m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=106 M=0.75 CJO=12.68p VJ=1V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=7.2p N=1.32 RS=246u EG=1.12 TT=30n) +Rdiode d1 21 246.15m TC=0 + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 32.5p +.MODEL DGD D(M=0.85 CJO=32.5p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 13.65p +Cox1 d2 g2 1.27p + +.ENDS BSS119N_L0 + +****** + +.SUBCKT BSS123N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.06 + +Rg g1 g2 12 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 1.053 VTO=1.87 THETA=0 VMAX=1.5e5 ETA=0.004 LEVEL=3) +Rd d2 d1 2.308 TC=10m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=106 M=0.75 CJO=12.68p VJ=1V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=9.6p N=1.329 RS=246u EG=1.12 TT=30n) +Rdiode d1 21 246.15m TC=5m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 32.5p +.MODEL DGD D(M=0.85 CJO=32.5p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 13.65p +Cox1 d2 g2 1.27p + +.ENDS BSS123N_L0 + +****** + +.SUBCKT BSL296SN_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.012 + +Rg g1 g2 14.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 8.1 VTO=1.87 THETA=0 VMAX=1.5e5 ETA=0.004 LEVEL=3) +Rd d2 d1 0.3 TC=10m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=106 M=0.75 CJO=97.5p VJ=1V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=73.5p N=1.329 RS=32u EG=1.12 TT=30n) +Rdiode d1 21 32m TC=5m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 250p +.MODEL DGD D(M=0.85 CJO=250p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 105p +Cox1 d2 g2 3.54p + +.ENDS BSL296SN_L0 + +****** + +.SUBCKT BSP296N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.027 + +Rg g1 g2 14.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 8.1 VTO=1.87 THETA=0 VMAX=1.5e5 ETA=0.004 LEVEL=3) +Rd d2 d1 0.3 TC=10m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=106 M=0.75 CJO=97.5p VJ=1V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=73.5p N=1.329 RS=32u EG=1.12 TT=30n) +Rdiode d1 21 32m TC=5m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 250p +.MODEL DGD D(M=0.85 CJO=250p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 105p +Cox1 d2 g2 3.54p + +.ENDS BSP296N_L0 + +****** + +.SUBCKT BSL373SN_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.012 + +Rg g1 g2 23 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 6.963 VTO=3.9 THETA=0 VMAX=1.5e5 ETA=0.01 LEVEL=3) +Rd d2 d1 0.146 TC=10m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=106 M=0.75 CJO=212.16p VJ=1V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=38.1p N=1.28 RS=15u EG=1.12 TT=30n) +Rdiode d1 21 14.71m TC=5m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 272p +.MODEL DGD D(M=0.75 CJO=272p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 184.96p +Cox1 d2 g2 9.28p + +.ENDS BSL373SN_L0 + +****** + +.SUBCKT BSP373N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.014 + +Rg g1 g2 23 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 6.963 VTO=3.9 THETA=0 VMAX=1.5e5 ETA=0.01 LEVEL=3) +Rd d2 d1 0.146 TC=10m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=106 M=0.75 CJO=212.16p VJ=1V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=38.1p N=1.28 RS=15u EG=1.12 TT=30n) +Rdiode d1 21 14.71m TC=5m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 272p +.MODEL DGD D(M=0.75 CJO=272p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 184.96p +Cox1 d2 g2 9.28p + +.ENDS BSP373N_L0 + +****** + +.SUBCKT BSL372SN_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.012 + +Rg g1 g2 23 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17.626 VTO=1.87 THETA=0 VMAX=1.5e5 ETA=0.004 LEVEL=3) +Rd d2 d1 0.138 TC=10m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=106 M=0.75 CJO=212.16p VJ=1V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=159.9p N=1.329 RS=15u EG=1.12 TT=30n) +Rdiode d1 21 14.71m TC=5m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 544p +.MODEL DGD D(M=0.85 CJO=544p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 228.48p +Cox1 d2 g2 5.22p + +.ENDS BSL372SN_L0 + +****** + +.SUBCKT BSP372N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 0.014 + +Rg g1 g2 23 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17.626 VTO=1.87 THETA=0 VMAX=1.5e5 ETA=0.004 LEVEL=3) +Rd d2 d1 0.138 TC=10m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=106 M=0.75 CJO=212.16p VJ=1V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=159.9p N=1.329 RS=15u EG=1.12 TT=30n) +Rdiode d1 21 14.71m TC=5m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 544p +.MODEL DGD D(M=0.85 CJO=544p VJ=0.5) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 228.48p +Cox1 d2 g2 5.22p + +.ENDS BSP372N_L0 + +****** \ No newline at end of file diff --git a/spice/STMicroelectronics/stl3n10f7_spice/STL3N10F7_V2.LIB b/spice/STMicroelectronics/stl3n10f7_spice/STL3N10F7_V2.LIB new file mode 100755 index 0000000..6fdbd09 --- /dev/null +++ b/spice/STMicroelectronics/stl3n10f7_spice/STL3N10F7_V2.LIB @@ -0,0 +1,184 @@ +******************************************************************* +******STMicroelectronics MOSFET, IGBT and Bipolar Library ********* +******************************************************************* +* * +* Models provided by STMicroelectronics are not guaranteed to * +* fully represent all the specifications and operating * +* characteristics of the product behavior that they reproduce. * +* The model describes the characteristics of a typical device. * +* In all cases, the current product data sheet contains all * +* information to be used like final design guidelines and the * +* only actual performance specification. * +* Altough models can be a useful tool in evaluating device * +* performance, they cannot model exact device performance under * +* all conditions. * +* STMicroelectronics therefore does not assume any * +* responsibility arising from their use. * +* STMicroelectronics reserves the right to change models * +* without prior notice. * +* * +* Note: The model doesn't take into account the drain, gate, * +* source inductances.If these contributions have to be * +* considered it is possible include the inductors externally. * +* For this package the values can be estimated as follow * +* * +* Ldrain= 1nH ,Lsource=2nH and Lgate=2.5nH * +* * +* Rev 2.0 - 10 April 2013 * +******************************************************************* + +.SUBCKT STL3N10F7_V2 1 2 3 +******************************************************************* +E1 Tj val_T VALUE={TEMP} +R1 val_T 0 1E-03 +*********************************************************** +Rtk Tj 0 1E10 +Rtk1 Tj 0 1E10 +************************************ +VLd 1 d1k 0 +VLs ss 3 0 +VLG 2 g2 0 +rg1 g2 g {rg} +Rdsx s dx 100k +Cdx dx d 50p +******************************************************************* +.PARAM Area=1 BVDSS=1 raval=121m +*************************************************** +.PARAM rg=1.85 Vth0=4 drs=10u +.PARAM lambda=0.001 +.PARAM kpsat0=3.3 kplin0=20 + + +.PARAM rd=53.6m +.PARAM rpa=1E-05 + +*********************************** +.PARAM unt =-1.8 vthx=4.5m ksat=-1 klin=-1 +.PARAM a=1 b=1 Rx=1.1 +.param rr=1 + + +*********************************************************** +.FUNC r_s(T) {drs*((T+273)/300)**(rr)} +.FUNC vth1(x) {vth0-vthx*(x-27)} +.FUNC kpsat(x) {kpsat0*((x+273)/300)**(ksat)} +.FUNC kplin(x) {kplin0*((x+273)/300)**(klin)} +.FUNC un(T) {b*((T+273)/300)**(unt)} + +*********************************************************** +*********************************************************** +Gmos d s value {Area*(IF(V(d,s)>0,(IF(v(g,s)2.3) +B1 5 2 I=(8m-0.05u)*(V(7)-V(2)>2.3)*(V(5)-V(2)>2.6)*(V(5)-V(2)<=7.5)+0.05u +B_GC7 OFFS 2 V=15m*tanh((V(INT_FLT)-V(2))/15m) +B2 N001 2 V=(V(DET_out)<=V(REF_p66))*(V(DET_out)-V(REF_p66))+V(REF_p66)-V(2) +B3 N006 2 V=(V(AMP2)<=V(REF_4p75))*(V(AMP2)-V(REF_4p75))+V(REF_4p75)-V(2) +B4 AMP2 2 V=(V(AMP1)>=V(REF_p4))*(V(AMP1)-V(REF_p4))+V(REF_p4)-V(2) +R19 AMP1 2 100k +R20 AMP2 2 100k +B_D1b 2 N007 I={I_D1b}*(COSH(0.25*(V(GC1_in)-V(2))/{denom})-1)/(COSH(0.25*(V(GC1_in)-V(2))/{denom})+1) +B_D1c 2 N007 I={I_D1c}*(COSH(45m*(V(GC1_in)-V(2))/{denom})-1)/(COSH(45m*(V(GC1_in)-V(2))/{denom})+1) +R30 7 2 85.7k +XU1 N006 N004 VCC_INT 2 N004 level.2 Avol=1Meg GBW=25Meg Slew=100Meg ilimit=5m rail=0 Vos=0 phimargin=45 en=0 enk=0 in=0 ink=0 Rin=500Meg +R33 4 N004 0.05 +R31 INT_FLT N022 7.1e7 +R32 2 OFFS 1e8 +C18 INT_FLT 2 33p +S1 5 VCC_INT CTRL 2 vcc_switch +B_OFLT1 CTRL 2 V=(V(7)-V(2)>2.3)*(V(5)-V(2)>2.6)*(V(5)-V(2)<=7.5) +R24 VCC_INT 2 1e8 +B_0p4 REF_p4 2 V=0.4*(V(CTRL)>0.5) +B_0p66 REF_p66 2 V=0.66*(V(CTRL)>0.5) +B_4p75 REF_4p75 2 V=4.75*(V(CTRL)>0.5) +V1 CM_IN 2 3.2578 +V5 3 INT_FLT 1.75 +.param I_GC1=998.692u +.param I_GC2=904.1875u +.param I_GC3=903.975u +.param I_GC4=801.8u +.param I_GC5=896.75u +.param I_GC6=977.5u +.param T_GC1=TEMP+287.775 +.param T_GC2=TEMP+287.334488 +.param T_GC3=TEMP+287.7372 +.param T_GC4=TEMP+301.1642 +.param T_GC5=TEMP+301.1642 +.param T_GC6=TEMP+273.2804 +.param I_D1a=7.132n*TEMP + 27.5784u +.param I_D1b=4.7n*TEMP + 26.8338u +.param I_D1c=9.564n*TEMP + 31.8017u +.param I_D2 =7.76n*TEMP + 29.8147u +.param I_D3 =.9885n*TEMP + 29.70868u +.param I_D4 =.9885n*TEMP + 29.70868u +.param I_D5 =3.954n*TEMP + 29.6286u +.param I_D6 =7.908n*TEMP + 29.5219u +.param I_D7 =37.46n*TEMP + 57.0747u +.param denom=172.5u*(TEMP+274.15) +.param Ain=1.58 +.model vcc_switch SW(Ron=1m, Roff=1e9, Vt=0.5) +.lib UniversalOpamps2.sub +.ends AD8310 diff --git a/spice/copy/sub/AD8452.sub b/spice/copy/sub/AD8452.sub new file mode 100755 index 0000000..ce38cec Binary files /dev/null and b/spice/copy/sub/AD8452.sub differ diff --git a/spice/copy/sub/ADA4098-1.lib b/spice/copy/sub/ADA4098-1.lib new file mode 100755 index 0000000..188a3b2 --- /dev/null +++ b/spice/copy/sub/ADA4098-1.lib @@ -0,0 +1,112 @@ +* Copyright (c) 1998-2021 Analog Devices, Inc. All rights reserved. +* +.subckt ADA4098-1 1 2 3 4 5 6 +B1 0 N006 I=10u*dnlim(uplim(V(1),V(4)+69.3,.1), V(4)-.15, .1)+1n*V(1)-10.72254n +B2 N006 0 I=10u*dnlim(uplim(V(2),V(4)+69.3,.1), V(4)-.16, .1)+1n*V(2) +C10 N006 0 50f Rpar=100K noiseless +M1 N019 NG 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 NG N022 DLIMN1 +M2 P001 N007 N004 N004 PI temp=27 +A3 N014 N016 4 4 4 4 N007 4 OTA g=2u ref=-.305 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +D6 NG 4 DLIMN2 +C16 N016 5 12p +A5 N012 0 N014 N014 N014 N014 N016 N014 OTA g=70u isource=10.3u Vlow=-1e308 Vhigh=1e308 +G1 4 NG N016 N014 140n +D9 N016 N014 DLIM +C7 2 0 2.7p Rser=1k Rpar=100G noiseless +C13 3 4 10p +C1 N009 0 30f +G2 0 N014 4 0 .5m +G4 0 N014 3 0 .5m +C18 N014 0 200p Rpar=1K noiseless +C6 1 0 2.7p Rser=1k Rpar=100G noiseless +D3 3 N004 DSBD +C5 3 N004 100f Rpar=10Meg noiseless +D4 N004 N007 DLIMP +D2 N009 0 DLIM0 +D1 4 5 DESD +D8 4 1 DESD +D10 4 2 DESD +A2 N015 0 0 0 0 0 0 0 OTA g=0 in=1.8p ink=15 +D11 5 N019 DNR +C15 N019 4 100f Rpar=10Meg noiseless +D7 N007 3 DLIMPR +A6 4 3 M M M M N005 M OTA g=2u iout=1u ref=-2.5 Rout=1Meg Cout=100f vlow=-1e308 vhigh=1e308 +S4 N021 N023 N005 0 SBiasN +D13 3 N013 DBiasDrop +C14 N021 4 100f +S2 N004 N007 0 N005 SHUT +S3 NG 4 0 N005 SHUT +D16 2 1 D1Meg +C17 N010 0 174.26f noiseless Rser=2.667Meg Rpar=1Meg +G3 0 N010 N009 0 1µ +D17 0 N009 DNLIN +C20 N012 0 47f Rpar=1Meg noiseless +G5 0 N012 N011 0 1µ +S5 N014 N016 4 5 SGK +C3 3 N007 .9p Rser=700k noiseless +C12 NG 4 .9p Rser=700k noiseless +D14 2 N013 DBiasOTT +D15 1 N021 DBiasOTT +S1 0 N008 3 2 SNOI +A7 N008 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=145f ink=6 +GNOI_I 1 2 N015 0 1µ +S6 0 N015 3 2 SNOI +A4 0 N006 0 0 0 0 N009 0 OTA g=1u linear en=16.95n*(1+freq/12e5) enk=3.3 Vhigh=1e308 Vlow=-1e308 +GNOI_V N006 0 N008 0 10n +I1 0 1 1.76n +S9 3 4 N017 0 SP +S10 3 N007 N017 0 SHUT2 +S11 NG 4 N017 0 SHUT2 +A8 6 4 0 0 0 0 N017 0 SCHMITT Vt=1.5 Vh=1m Trise=1u Tfall=100u +S7 5 0 N017 0 SHUT2 +S8 P001 5 0 N017 SHUT3 +S13 N018 4 0 N017 SHUT3 +G6 0 M 3 0 500µ +R1 M 0 1k noiseless +G7 0 M 4 0 500µ +R2 N026 0 48 noiseless +C4 N027 N026 10n Rpar=47.9K noiseless +R3 N027 0 1 noiseless +G8 0 N027 1 0 5.25m +G9 0 N027 2 0 5.25m +G10 0 N027 0 3 5.25m +G11 0 N027 0 4 5.25m +G12 0 N006 0 N026 1µ +D12 3 N018 DP +S12 N013 N021 0 N017 SHUT3 +D18 4 6 DSHUT1 +C9 6 0 100f +C19 N011 0 174.26f noiseless Rser=3.667Meg Rpar=1Meg +G13 0 N011 N010 0 1µ +S14 N023 4 0 N017 SHUT3 +S15 N022 4 0 N017 SHUT3 +I2 0 2 2.04n +.model DP D(Ron=1k Roff=1G Vfwd=2.5 epsilon=100m ilimit=1.4u noiseless) +.model SP SW(Ron=100 Roff=1G vt=.5 vh=10m ilimit=17u noiseless) +.model DESD D(Ron=1k Roff=1G vfwd=700m epsilon=100m noiseless) +.model SNOI SW(Ron=1 Roff=1Meg vt=1.2 vh=-100m noiseless) +.model NI VDMOS(Vto=325.5m kp=72.3m Mtriode=.9 lambda=.01) +.model PI VDMOS(Vto=-325.5m Kp=341m lambda=.01 pchan is=0) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=1 epsilon=100m Vrev=1 epsilon=100m noiseless) +.model DNLIN D(Roff=1.8Meg Ron=800k vfwd=0 epsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=2.949Meg Vfwd=700m Vrev=100m epsilon=10m revepsilon=10 noiseless) +.model SHUT SW(level=2 Ron=10k Roff=100G vt=-.5 vh=-.2 noiseless) +.model DSHUT1 D(Ron=1000 Roff=0.823E6 Vfwd=1 epsilon=100m Vrev=1 epsilon=100m ilimit=100n revilimit=0.1n noiseless) +.model DSBD D( Ron=15 Roff=100Meg Vfwd=-58.5m epsilon=50m Vrev=100 revepsilon=10m noiseless) +.model DNR D(Ron=1 Roff=100Meg Vfwd=-6.5m epsilon=300m noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.378 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=44n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=0.63 epsilon=10m noiseless) +.model DLIMPR D(Ron=5Meg Roff=1G Vfwd=100m epsilon=10m noiseless) +.model SGK SW(level=2 Ron=65k Roff=100G vt=-260m vh=150m oneway epsilon=10m noiseless) +.model SBiasN SW(level=2 Ron=5k Roff=1g vt=.5 vh=-.2 ilimit=8u noiseless) +.model DBiasDrop D(Ron=1k Roff=1G vfwd=2.37 epsilon=200m noiseless) +.model DBiasOTT D(Ron=500 Roff=1G vfwd=700m epsilon=200m noiseless) +.model D1Meg D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=10n revilimit=10n noiseless) +.model SHUT3 SW(Ron=10 Roff=10G vt=-0.5 vh=100m noiseless) +.model SHUT2 SW(Ron=10 Roff=10G vt=0.5 vh=100m noiseless) +.ends ADA4098-1 diff --git a/spice/copy/sub/ADA4099-1.lib b/spice/copy/sub/ADA4099-1.lib new file mode 100755 index 0000000..0bf5492 --- /dev/null +++ b/spice/copy/sub/ADA4099-1.lib @@ -0,0 +1,112 @@ +* Copyright (c) 1998-2021 Analog Devices, Inc. All rights reserved. +* +.subckt ADA4099-1 1 2 3 4 5 6 +B1 0 N006 I=10u*dnlim(uplim(V(1),V(4)+69.1,.1), V(4)-.15, .1)+1n*V(1)-10.72254n +B2 N006 0 I=10u*dnlim(uplim(V(2),V(4)+69.1,.1), V(4)-.16, .1)+1n*V(2) +C10 N006 0 50f Rpar=100K noiseless +M1 N018 NG 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 NG N022 DLIMN1 +M2 P001 N007 N004 N004 PI temp=27 +A3 N013 N015 4 4 4 4 N007 4 OTA g=2u ref=-.305 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +D6 NG 4 DLIMN2 +C16 N015 5 1.8p +A5 N011 0 N013 N013 N013 N013 N015 N013 OTA g=50u iout=9.8u Vlow=-1e308 Vhigh=1e308 +G1 4 NG N015 N013 140n +D9 N015 N013 DLIM +C7 2 0 2.7p Rser=1k Rpar=100G noiseless +C13 3 4 10p +C1 N009 0 7f +G2 0 N013 4 0 .5m +G4 0 N013 3 0 .5m +C18 N013 0 200p Rpar=1K noiseless +C6 1 0 2.7p Rser=1k Rpar=100G noiseless +D3 3 N004 DSBD +C5 3 N004 100f Rpar=10Meg noiseless +D4 N004 N007 DLIMP +D2 N009 0 DLIM0 +D1 4 5 DESD +D8 4 1 DESD +D10 4 2 DESD +A2 N014 0 0 0 0 0 0 0 OTA g=0 en=8n enk=5 in=5p ink=15 +D11 5 N018 DNR +C15 N018 4 100f Rpar=10Meg noiseless +D7 N007 3 DLIMPR +A6 4 3 M M M M N005 M OTA g=2u iout=1u ref=-2.5 Rout=1Meg Cout=100f vlow=-1e308 vhigh=1e308 +S4 N020 N021 N005 0 SBiasN +D13 3 N012 DBiasDrop +C14 N020 4 100f +S2 N004 N007 0 N005 SHUT +S3 NG 4 0 N005 SHUT +D16 2 1 D100k +C17 N010 0 80.26f noiseless Rser=2.667Meg Rpar=1Meg +G3 0 N010 N009 0 1µ +D17 0 N009 DNLIN +C19 N011 0 6f Rpar=1Meg noiseless +G5 0 N011 N010 0 1µ +S5 N013 N015 4 5 SGK +C3 3 N007 .9p Rser=700k noiseless +C12 NG 4 .9p Rser=700k noiseless +D14 2 N012 DBiasOTT +D15 1 N020 DBiasOTT +S1 0 N008 3 2 SNOI +A7 N008 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=500f ink=6 +GNOI_I 1 2 N014 0 1µ +S6 0 N014 3 2 SNOI +A4 0 N006 0 0 0 0 N009 0 OTA g=1u linear en=7n*(1+freq/40e6) enk=6 Vhigh=1e308 Vlow=-1e308 +GNOI_V N006 0 N008 0 10n +I1 1 0 1.4n +S9 3 4 N016 0 SP +S10 3 N007 N016 0 SHUT2 +S11 NG 4 N016 0 SHUT2 +A8 6 4 0 0 0 0 N016 0 SCHMITT Vt=1.5 Vh=1m Trise=1u Tfall=12u +S7 5 0 N016 0 SHUT2 +S8 P001 5 0 N016 SHUT3 +S13 N017 4 0 N016 SHUT3 +G6 0 M 3 0 500µ +R1 M 0 1k noiseless +G7 0 M 4 0 500µ +R2 N025 0 48 noiseless +C4 N026 N025 10n Rpar=47.9K noiseless +R3 N026 0 1 noiseless +G8 0 N026 1 0 5.25m +G9 0 N026 2 0 5.25m +G10 0 N026 0 3 5.25m +G11 0 N026 0 4 5.25m +G12 0 N006 0 N025 1µ +D12 3 N017 DP +S12 N012 N020 0 N016 SHUT3 +S14 N021 4 0 N016 SHUT3 +S16 N022 4 0 N016 SHUT3 +D18 4 6 DSHUT1 +C8 6 0 100f +.model DP D(Ron=1k Roff=1G Vfwd=2.5 epsilon=100m ilimit=0.49m noiseless) +.model SP SW(Ron=100 Roff=1G vt=.5 vh=10m ilimit=24u noiseless) +.model DESD D(Ron=1k Roff=1G vfwd=700m epsilon=100m noiseless) +.model SNOI SW(Ron=1 Roff=1Meg vt=1.2 vh=-100m noiseless) +.model NI VDMOS(Vto=220m kp=60m Mtriode=.9 lambda=.01) +.model PI VDMOS(Vto=-220m Kp=120m lambda=.01 pchan is=0) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=1 epsilon=100m Vrev=1 epsilon=100m noiseless) +.model DNLIN D(Roff=1.8Meg Ron=800k vfwd=0 epsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=4.111Meg Vfwd=700m Vrev=100m epsilon=10m revepsilon=10 noiseless) +.model SHUT SW(level=2 Ron=10k Roff=100G vt=-.5 vh=-.2 noiseless) +.model DSHUT1 D(Ron=1000 Roff=0.823E6 Vfwd=1 epsilon=100m Vrev=1 epsilon=100m ilimit=100n revilimit=0.1n noiseless) +.model DSBD D( Ron=15 Roff=100Meg Vfwd=-48.5m epsilon=50m Vrev=100 revepsilon=10m noiseless) +.model DNR D(Ron=1 Roff=100Meg Vfwd=-8.5m epsilon=300m noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.378 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=44n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=0.815 epsilon=10m noiseless) +.model DLIMPR D(Ron=5Meg Roff=1G Vfwd=100m epsilon=10m noiseless) +.model SGK SW(level=2 Ron=65k Roff=100G vt=-260m vh=150m oneway epsilon=10m noiseless) +.model SBiasN SW(level=2 Ron=5k Roff=1g vt=.5 vh=-.2 ilimit=82.5u noiseless) +.model DBiasDrop D(Ron=1k Roff=1G vfwd=2.37 epsilon=200m noiseless) +.model DBiasOTT D(Ron=500 Roff=1G vfwd=700m epsilon=200m noiseless) +.model D100k D(Ron=100k Roff=100k vfwd=0 vrev=0 ilimit=10n revilimit=10n noiseless) +.model 600nA D(Ron=1Meg Roff=1G Ilimit=600n epsilon=1 Vfwd=1 noiseless) +.model 300nA D(Ron=1Meg Roff=1G Ilimit=300n epsilon=1 Vfwd=0 noiseless) +.model SHUT3 SW(Ron=10 Roff=10G vt=-0.5 vh=100m noiseless) +.model SHUT2 SW(Ron=10 Roff=10G vt=0.5 vh=100m noiseless) +.model SHUTD SW(Ron=10 Roff=10G vt=0 vh=100m ilimit=300n noiseless) +.ends ADA4099-1 diff --git a/spice/copy/sub/ADA4254.sub b/spice/copy/sub/ADA4254.sub new file mode 100755 index 0000000..c20444f Binary files /dev/null and b/spice/copy/sub/ADA4254.sub differ diff --git a/spice/copy/sub/ADA4523-1.sub b/spice/copy/sub/ADA4523-1.sub new file mode 100755 index 0000000..bb94f37 Binary files /dev/null and b/spice/copy/sub/ADA4523-1.sub differ diff --git a/spice/copy/sub/ADG.lib b/spice/copy/sub/ADG.lib new file mode 100755 index 0000000..b32563e --- /dev/null +++ b/spice/copy/sub/ADG.lib @@ -0,0 +1,627 @@ +* Copyright © Analog Devices, Inc. 2019. All rights reserved. +* +* +.subckt ADG1611 1 2 3 4 5 6 7 8 9 10 11 12 13 +C1 1 5 5p +C2 4 5 63p +C5 13 5 63p +A1 1 5 5 5 5 5 N002 5 SCHMITT Vt=1.4 Vh=1m tripdt=10n Trise=250n Tfall=500n +S1 N004 13 5 N002 TN +S2 4 N004 N002 5 BN +S3 13 N006 N002 5 TP +S4 N006 4 5 N002 BP +C6 2 5 63p +C7 3 5 63p +M1 2 N004 3 3 N +M2 3 N006 2 2 P +D1 3 13 S +D2 4 2 S +D3 2 13 S +D4 4 3 S +.model N VDMOS(Kp=.12 Vto= .5 Is=0 mtriode=1.3 Cgs=24p Ksubthres=.4 nlev=3 gdsnoi=2) +.model P VDMOS(Kp=.12 Vto=-.5 pchan Is=0 mtriode=1.3 Cgs=24p Ksubthres=.4 nlev=3 gdsnoi=2) +.model TN SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model BN SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model TP SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model BP SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model S D(Ron=5 Roff=1G Vfwd=.4 epsilon=1) +.ends ADG1611 +* +.subckt ADG1612 1 2 3 4 5 6 7 8 9 10 11 12 13 +C1 1 5 5p +C2 4 5 63p +C5 13 5 63p +A1 1 5 5 5 5 N002 5 5 SCHMITT Vt=1.4 Vh=1m tripdt=10n Trise=250n Tfall=500n +S1 N004 13 5 N002 TN +S2 4 N004 N002 5 BN +S3 13 N006 N002 5 TP +S4 N006 4 5 N002 BP +C6 2 5 63p +C7 3 5 63p +M1 2 N004 3 3 N +M2 3 N006 2 2 P +D1 3 13 S +D2 4 2 S +D3 2 13 S +D4 4 3 S +.model N VDMOS(Kp=.12 Vto= .5 Is=0 mtriode=1.3 Cgs=24p Ksubthres=.4 nlev=3 gdsnoi=2) +.model P VDMOS(Kp=.12 Vto=-.5 pchan Is=0 mtriode=1.3 Cgs=24p Ksubthres=.4 nlev=3 gdsnoi=2) +.model TN SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model BN SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model TP SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model BP SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model S D(Ron=5 Roff=1G Vfwd=.4 epsilon=1) +.ends ADG1612 +* +.subckt ADG1633 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C1 15 16 8p +C2 13 16 63p +C5 1 16 63p +S1 N004 1 16 N002 TN +S2 13 N004 N002 16 BN +S3 1 N009 N002 16 TP +S4 N009 13 16 N002 BP +C6 3 16 33p +C7 2 16 19p +M1 3 N004 2 2 N m=.22 +M2 2 N009 3 3 P m=.22 +D1 2 1 S +D2 13 3 S +D3 3 1 S +D4 13 2 S +A2 15 16 16 16 16 N007 N005 16 SCHMITT Vt=1.4 Vh=1m tripdt=5n Trise=100n Td=80n +S5 N015 1 16 N012 TN +S6 13 N015 N012 16 BN +S7 1 N014 N012 16 TP +S8 N014 13 16 N012 BP +C11 4 16 19p +M3 3 N015 4 4 N m=.22 +M4 4 N014 3 3 P m=.22 +D5 4 1 S +D6 13 3 S +D7 3 1 S +D8 13 4 S +C8 14 16 8p +A3 14 16 16 16 16 N008 16 16 SCHMITT Vt=1.4 Vh=1m tripdt=5n Trise=100n Tfall=225n +A5 16 N005 16 N008 16 N002 16 16 AND Trise=90n Tfall=10n tripdt=5n +A1 16 N007 16 N008 16 N012 16 16 AND Trise=90n Tfall=10n tripdt=5n +.model N VDMOS(Kp=.12 Vto= .5 Is=0 mtriode=1.3 Cgs=10p Ksubthres=.4 nlev=3 gdsnoi=2) +.model P VDMOS(Kp=.12 Vto=-.5 pchan Is=0 mtriode=1.3 Cgs=10p Ksubthres=.4 nlev=3 gdsnoi=2) +.model TN SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model BN SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model TP SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model BP SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model S D(Ron=5 Roff=1G Vfwd=.4 epsilon=1) +.ends ADG1633 +* +.subckt ADG5248F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +C2 3 14 63p +C5 13 14 63p +S1 N046 13 14 N042 TN +S2 3 N046 N042 14 BN +S3 13 N049 N042 14 TP +S4 N049 3 14 N042 BP +C7 7 14 3p +M1 N021 N046 N043 N043 N +M2 N043 N049 N021 N021 P +A4 UVLO N028 N029 N047 N040 S1 14 14 AND Trise=50n Tfall=250n tripdt=5n +A16 1 14 14 14 14 N028 N033 14 SCHMITT Vt=1.4 Vh=1m Trise=100n Tfall=150n +C3 2 14 8p +C4 1 14 8p +C9 16 14 8p +C10 15 14 8p +S5 N038 13 14 N035 TN +S6 3 N038 N035 14 BN +S7 13 N039 N035 14 TP +S8 N039 3 14 N035 BP +C8 6 14 3p +M3 N021 N038 N036 N036 N +M4 N036 N039 N021 N021 P +S9 N026 13 14 N024 TN +S10 3 N026 N024 14 BN +S11 13 N027 N024 14 TP +S12 N027 3 14 N024 BP +C12 5 14 3p +M5 N021 N026 N025 N025 N +M6 N025 N027 N021 N021 P +S13 N018 13 14 N015 TN +S14 3 N018 N015 14 BN +S15 13 N020 N015 14 TP +S16 N020 3 14 N015 BP +C13 8 14 12p +C14 4 14 3p +M7 N021 N018 N016 N016 N +M8 N016 N020 N021 N021 P +S17 N074 13 14 N061 TN +S18 3 N074 N061 14 BN +S19 13 N075 N061 14 TP +S20 N075 3 14 N061 BP +C16 9 14 3p +M9 N021 N074 N072 N072 N +M10 N072 N075 N021 N021 P +S21 N070 13 14 N059 TN +S22 3 N070 N059 14 BN +S23 13 N071 N059 14 TP +S24 N071 3 14 N059 BP +C18 10 14 3p +M11 N021 N070 N068 N068 N +M12 N068 N071 N021 N021 P +S25 N066 13 14 N056 TN +S26 3 N066 N056 14 BN +S27 13 N067 N056 14 TP +S28 N067 3 14 N056 BP +C20 11 14 3p +M13 N021 N066 N064 N064 N +M14 N064 N067 N021 N021 P +S29 N057 13 14 N052 TN +S30 3 N057 N052 14 BN +S31 13 N060 N052 14 TP +S32 N060 3 14 N052 BP +C22 12 14 3p +M15 N021 N057 N054 N054 N +M16 N054 N060 N021 N021 P +A9 16 14 14 14 14 N029 N034 14 SCHMITT Vt=1.4 Vh=1m Trise=100n Tfall=150n +A10 2 14 14 14 14 N031 N040 14 SCHMITT Vt=1.4 Vh=1m Trise=100n Tfall=150n +A11 15 14 14 14 14 N047 N053 14 SCHMITT Vt=1.4 Vh=1m Trise=100n Tfall=150n +D33 14 2 ESD +D34 14 15 ESD +D35 14 16 ESD +D36 14 1 ESD +C6 18 14 20p +C11 17 14 20p +A13 17 4 14 14 14 14 S1L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +D37 S1H F1 OR +D38 S1L F1 OR +D39 S2H F2 OR +D40 S2L F2 OR +D41 S3H F3 OR +D42 S3L F3 OR +D43 S4H F4 OR +D44 S4L F4 OR +D45 S5H F5 OR +D46 S5L F5 OR +D47 S6H F6 OR +D48 S6L F6 OR +D49 S7H F7 OR +D50 S7L F7 OR +D51 S8H F8 OR +D52 S8L F8 OR +D53 F1 N011 OR +D54 F2 N011 OR +D55 F3 N011 OR +D56 F4 N011 OR +D57 F5 N011 OR +D58 F6 N011 OR +D59 F7 N011 OR +M17 13 14 N001 N001 3V +C15 N001 14 10p +S33 19 14 N014 14 OUT +S34 N001 19 N009 14 OUT +A30 14 N008 14 UVLO 14 14 N009 14 AND Trise=15n Ref=.95 +D60 14 19 ESD +A29 14 UVLO 14 N013 14 14 N014 14 AND Trise=15n Ref=.95 +C17 19 14 4p +A32 13 3 14 14 14 14 UVLO 14 SCHMITT Vt=7.9 Vh=50m Rhigh=1K Rlow=10 +A33 18 14 14 14 14 14 UVLO 14 SCHMITT Vt=4.44 Vh=50m Rhigh=1K Rlow=10 +A34 13 18 14 14 14 14 UVLO 14 SCHMITT Vt=-50m Vh=25m Rhigh=1K Rlow=10 +A35 17 3 14 14 14 14 UVLO 14 SCHMITT Vt=-50m Vh=25m Rhigh=1K Rlow=10 +A36 17 14 14 14 14 UVLO 14 14 SCHMITT Vt=50m Vh=25m Rhigh=1K Rlow=10 +D61 F1 N015 OR +D62 S1 N015 OR +B1 14 FX2 I=(!V(S1,14) & V(S1L,14))|(!V(S2,14)&V(S2L,14))|(!V(S3,14)&V(S3L,14))|(!V(S4,14)&V(S4L,14))|(!V(S5,14)&V(S5L,14))|(!V(S6,14)&V(S6L,14))|(!V(S7,14)&V(S7L,14))|(!V(S8,14)&V(S8L,14)) Rpar=1 Cpar=1n NoJacob +B2 14 FX1 I=(!V(S1,14)&V(S1H,14))|(!V(S2,14)&V(S2H,14))|(!V(S3,14)&V(S3H,14))|(!V(S4,14)&V(S4H,14))|(!V(S5,14)&V(S5H,14))|(!V(S6,14)&V(S6H,14))|(!V(S7,14)&V(S7H,14))|(!V(S8,14)&V(S8H,14)) Rpar=1 Cpar=1n NoJacob +S35 8 18 N019 14 20µA +S36 8 17 N023 14 20µA +D63 S2 N024 OR +D64 S3 N035 OR +D65 S4 N042 OR +D66 S5 N052 OR +D67 S6 N056 OR +D68 S7 N059 OR +D69 S8 N061 OR +D70 F2 N024 OR +D71 F3 N035 OR +D72 F4 N042 OR +D73 F5 N052 OR +D74 F6 N056 OR +D75 F7 N059 OR +A12 4 18 14 14 14 14 S1H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A37 14 N028 N029 N031 14 14 Q1 14 AND Trise=90n Tfall=120n tripdt=5n +A38 14 N033 N029 N031 14 14 Q2 14 AND Trise=90n Tfall=120n tripdt=5n +A39 14 N028 N034 N031 14 14 Q3 14 AND Trise=90n Tfall=120n tripdt=5n +A40 14 N033 N034 N031 14 14 Q4 14 AND Trise=90n Tfall=120n tripdt=5n +A41 14 N028 N029 N040 14 14 Q5 14 AND Trise=90n Tfall=120n tripdt=5n +A42 14 N033 N029 N040 14 14 Q6 14 AND Trise=90n Tfall=120n tripdt=5n +A43 14 N028 N034 N040 14 14 Q7 14 AND Trise=90n Tfall=120n tripdt=5n +A44 14 N033 N034 N040 14 14 Q8 14 AND Trise=90n Tfall=120n tripdt=5n +S37 20 14 N007 14 OUT +S38 N001 20 N003 14 OUT +A45 14 N002 14 UVLO 14 14 N003 14 AND Trise=15n Ref=.95 +D77 14 20 ESD +A46 14 UVLO 14 N006 14 14 N007 14 AND Trise=15n Ref=.95 +C19 20 14 5p +A47 N005 14 14 14 14 N006 N002 14 BUF Trise=15n +D78 F8 N011 OR +B3 14 N005 I=(V(Q1,14)&V(F1,14))|(V(Q2,14)&V(F2,14))|(V(Q3,14)&V(F3,14))|(V(Q4,14)&V(F4,14))|(V(Q5,14)&V(F5,14))|(V(Q6,14)&V(F6,14))|(V(Q7,14)&V(F7,14))|(V(Q8,14)&V(F8,14)) Rpar=1 Cpar=1n NoJacob +S39 4 N016 14 F1 DC +S40 5 N025 14 F2 DC +S41 6 N036 14 F3 DC +S42 7 N043 14 F4 DC +S43 12 N054 14 F5 DC +S44 11 N064 14 F6 DC +S45 10 N068 14 F7 DC +S46 9 N072 14 F8 DC +B4 SX 0 V= !V(S1) ? V(4) :(!V(S2) ? V(5) : (!V(S3) ? V(6) : (!V(S4) ? V(7) :(!V(S5) ? V(12) : (!V(S6) ? V(11) : (!V(S7) ? V(10) : V(9))))))) +R2 8 N021 R=1Meg*(V(SX,8)/V(13,3))**10+10 +A48 14 14 14 N030 N032 _ON ON 14 DFLOP Cout=10n +A52 UVLO 14 14 14 14 N032 14 14 BUF +A53 14 FX1 14 ON 14 14 N019 14 AND Trise=100n +A54 14 FX2 14 ON 14 14 N023 14 AND Trise=100n +D79 _ON N052 OR +D80 _ON N056 OR +D81 _ON N059 OR +D82 _ON N061 OR +D83 _ON N015 OR +D84 _ON N024 OR +D85 _ON N035 OR +D86 _ON N042 OR +A1 UVLO N033 N029 N047 N040 S2 14 14 AND Trise=50n Tfall=250n tripdt=5n +A2 UVLO N028 N034 N047 N040 S3 14 14 AND Trise=50n Tfall=250n tripdt=5n +A3 UVLO N033 N034 N047 N040 S4 14 14 AND Trise=50n Tfall=250n tripdt=5n +A5 UVLO N028 N029 N053 N040 S5 14 14 AND Trise=50n Tfall=250n tripdt=5n +A6 UVLO N033 N029 N053 N040 S6 14 14 AND Trise=50n Tfall=250n tripdt=5n +A7 UVLO N028 N034 N053 N040 S7 14 14 AND Trise=50n Tfall=250n tripdt=5n +A8 UVLO N033 N034 N053 N040 S8 14 14 AND Trise=50n Tfall=250n tripdt=5n +A14 17 5 14 14 14 14 S2L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A15 5 18 14 14 14 14 S2H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A17 6 18 14 14 14 14 S3H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A18 17 6 14 14 14 14 S3L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A19 7 18 14 14 14 14 S4H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A20 17 7 14 14 14 14 S4L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A21 12 18 14 14 14 14 S5H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A22 17 12 14 14 14 14 S5L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A23 17 11 14 14 14 14 S6L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A24 11 18 14 14 14 14 S6H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A25 10 18 14 14 14 14 S7H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A26 17 10 14 14 14 14 S7L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A27 9 18 14 14 14 14 S8H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A28 17 9 14 14 14 14 S8L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A55 N011 14 14 14 14 14 N012 14 BUF Trise=10n Tfall=70u +A31 N012 14 14 14 14 N013 N008 14 SCHMITT Vt=.5 Vh=.45 Trise=10n +C21 N021 14 1p +C23 14 N016 1p +C24 14 N025 1p +C25 14 N036 1p +C26 14 N043 1p +C27 14 N054 1p +C28 14 N064 1p +C29 14 N068 1p +C30 14 N072 1p +A49 FX1 14 FX2 14 N032 N030 14 14 OR +D1 F8 N061 OR +B5 _ON 14 I=smallsig() +.model N VDMOS(Kp=2m Vto= .5 Is=0 mtriode=1 Cgs=.049p Ksubthres=.4 nlev=3 gdsnoi=2) +.model P VDMOS(Kp=2m Vto=-.5 pchan Is=0 mtriode=1 Cgs=.049p Ksubthres=.4 nlev=3 gdsnoi=2) +.model TN SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model BN SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model TP SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model BP SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model ESD D(Ron=1 Roff=1G epsilon=1) +.model OR D(Ron=1 Roff=1G epsilon=.25) +.model OUT SW(Ron=150 Roff=10Meg Vt=.5 Vh=-.4) +.model 3V VDMOS(Kp=200m Vto=-3 Ksubthres=.1) +.model 20µA SW(Ron=20K Roff=10T Vt=.5 Vh=-10m Ilimit=20u level=2) +.model DC SW(Ron=190 Roff=1G Vt=-.5 Vh=-.4) +.ends ADG5248F +* +.subckt ADG5249F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +C2 3 14 63p +C5 13 14 63p +S1 N046 13 14 N042 TN +S2 3 N046 N042 14 BN +S3 13 N048 N042 14 TP +S4 N048 3 14 N042 BP +C7 7 14 3p +M1 N021 N046 N043 N043 N +M2 N043 N048 N021 N021 P +A4 UVLO N028 N029 14 N040 S1 14 14 AND Trise=50n Tfall=250n tripdt=5n +A16 1 14 14 14 14 N028 N033 14 SCHMITT Vt=1.4 Vh=1m Trise=100n Tfall=150n +C3 2 14 8p +C4 1 14 8p +C9 16 14 8p +S5 N038 13 14 N035 TN +S6 3 N038 N035 14 BN +S7 13 N039 N035 14 TP +S8 N039 3 14 N035 BP +C8 6 14 3p +M3 N021 N038 N036 N036 N +M4 N036 N039 N021 N021 P +S9 N026 13 14 N024 TN +S10 3 N026 N024 14 BN +S11 13 N027 N024 14 TP +S12 N027 3 14 N024 BP +C12 5 14 3p +M5 N021 N026 N025 N025 N +M6 N025 N027 N021 N021 P +S13 N018 13 14 N015 TN +S14 3 N018 N015 14 BN +S15 13 N020 N015 14 TP +S16 N020 3 14 N015 BP +C13 8 14 12p +C14 4 14 3p +M7 N021 N018 N016 N016 N +M8 N016 N020 N021 N021 P +S17 N075 13 14 N061 TN +S18 3 N075 N061 14 BN +S19 13 N076 N061 14 TP +S20 N076 3 14 N061 BP +C16 9 14 3p +M9 N059 N075 N073 N073 N +M10 N073 N076 N059 N059 P +S21 N071 13 14 N057 TN +S22 3 N071 N057 14 BN +S23 13 N072 N057 14 TP +S24 N072 3 14 N057 BP +C18 10 14 3p +M11 N059 N071 N069 N069 N +M12 N069 N072 N059 N059 P +S25 N067 13 14 N053 TN +S26 3 N067 N053 14 BN +S27 13 N068 N053 14 TP +S28 N068 3 14 N053 BP +C20 11 14 3p +M13 N059 N067 N065 N065 N +M14 N065 N068 N059 N059 P +S29 N054 13 14 N050 TN +S30 3 N054 N050 14 BN +S31 13 N058 N050 14 TP +S32 N058 3 14 N050 BP +C22 12 14 3p +M15 N059 N054 N051 N051 N +M16 N051 N058 N059 N059 P +A9 16 14 14 14 14 N029 N034 14 SCHMITT Vt=1.4 Vh=1m Trise=100n Tfall=150n +A10 2 14 14 14 14 N031 N040 14 SCHMITT Vt=1.4 Vh=1m Trise=100n Tfall=150n +D33 14 2 ESD +D35 14 16 ESD +D36 14 1 ESD +C6 18 14 20p +C11 17 14 20p +A13 17 4 14 14 14 14 S1L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +D37 S1H F1 OR +D38 S1L F1 OR +D39 S2H F2 OR +D40 S2L F2 OR +D41 S3H F3 OR +D42 S3L F3 OR +D43 S4H F4 OR +D44 S4L F4 OR +D45 S5H F5 OR +D46 S5L F5 OR +D47 S6H F6 OR +D48 S6L F6 OR +D49 S7H F7 OR +D50 S7L F7 OR +D51 S8H F8 OR +D52 S8L F8 OR +D53 F1 N011 OR +D54 F2 N011 OR +D55 F3 N011 OR +D56 F4 N011 OR +D57 F5 N011 OR +D58 F6 N011 OR +D59 F7 N011 OR +M17 13 14 N001 N001 3V +C15 N001 14 10p +S33 19 14 N014 14 OUT +S34 N001 19 N009 14 OUT +A30 14 N008 14 UVLO 14 14 N009 14 AND Trise=15n Ref=.95 +D60 14 19 ESD +A29 14 UVLO 14 N013 14 14 N014 14 AND Trise=15n Ref=.95 +C17 19 14 4p +A32 13 3 14 14 14 14 UVLO 14 SCHMITT Vt=7.9 Vh=50m Rhigh=1K Rlow=10 +A33 18 14 14 14 14 14 UVLO 14 SCHMITT Vt=4.44 Vh=50m Rhigh=1K Rlow=10 +A34 13 18 14 14 14 14 UVLO 14 SCHMITT Vt=-50m Vh=25m Rhigh=1K Rlow=10 +A35 17 3 14 14 14 14 UVLO 14 SCHMITT Vt=-50m Vh=25m Rhigh=1K Rlow=10 +A36 17 14 14 14 14 UVLO 14 14 SCHMITT Vt=50m Vh=25m Rhigh=1K Rlow=10 +D61 F1 N015 OR +D62 S1 N015 OR +B1 14 FX2A I=(!V(S1,14)&V(S1L,14))|(!V(S2,14)&V(S2L,14))|(!V(S3,14)&V(S3L,14))|(!V(S4,14)&V(S4L,14)) Rpar=1 Cpar=1n NoJacob +B2 14 FX1A I=(!V(S1,14)&V(S1H,14))|(!V(S2,14)&V(S2H,14))|(!V(S3,14)&V(S3H,14))|(!V(S4,14)&V(S4H,14)) Rpar=1 Cpar=1n NoJacob +S35 8 18 N019 14 20µA +S36 8 17 N023 14 20µA +D63 S2 N024 OR +D64 S3 N035 OR +D65 S4 N042 OR +D66 S5 N050 OR +D67 S6 N053 OR +D68 S7 N057 OR +D69 S8 N061 OR +D70 F2 N024 OR +D71 F3 N035 OR +D72 F4 N042 OR +D73 F5 N050 OR +D74 F6 N053 OR +D75 F7 N057 OR +A12 4 18 14 14 14 14 S1H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A37 14 N028 N029 N031 14 14 Q1 14 AND Trise=90n Tfall=120n tripdt=5n +A38 14 N033 N029 N031 14 14 Q2 14 AND Trise=90n Tfall=120n tripdt=5n +A39 14 N028 N034 N031 14 14 Q3 14 AND Trise=90n Tfall=120n tripdt=5n +A40 14 N033 N034 N031 14 14 Q4 14 AND Trise=90n Tfall=120n tripdt=5n +A41 14 N028 N029 N040 14 14 Q5 14 AND Trise=90n Tfall=120n tripdt=5n +A42 14 N033 N029 N040 14 14 Q6 14 AND Trise=90n Tfall=120n tripdt=5n +A43 14 N028 N034 N040 14 14 Q7 14 AND Trise=90n Tfall=120n tripdt=5n +A44 14 N033 N034 N040 14 14 Q8 14 AND Trise=90n Tfall=120n tripdt=5n +S37 20 14 N007 14 OUT +S38 N001 20 N003 14 OUT +A45 14 N002 14 UVLO 14 14 N003 14 AND Trise=15n Ref=.95 +D77 14 20 ESD +A46 14 UVLO 14 N006 14 14 N007 14 AND Trise=15n Ref=.95 +C19 20 14 5p +A47 N005 14 14 14 14 N006 N002 14 BUF Trise=15n +D78 F8 N011 OR +B3 14 N005 I=(V(Q1,14)&V(F1,14))|(V(Q2,14)&V(F2,14))|(V(Q3,14)&V(F3,14))|(V(Q4,14)&V(F4,14))|(V(Q5,14)&V(F5,14))|(V(Q6,14)&V(F6,14))|(V(Q7,14)&V(F7,14))|(V(Q8,14)&V(F8,14)) Rpar=1 Cpar=1n NoJacob +S39 4 N016 14 F1 DC +S40 5 N025 14 F2 DC +S41 6 N036 14 F3 DC +S42 7 N043 14 F4 DC +S43 12 N051 14 F5 DC +S44 11 N065 14 F6 DC +S45 10 N069 14 F7 DC +S46 9 N073 14 F8 DC +B4 SX1 0 V= !V(S1) ? V(4) : (!V(S2) ? V(5) : (!V(S3) ? V(6) : V(7))) +R2 8 N021 R=1Meg*(V(SX1,8)/V(13,3))**10+10 +A48 14 14 14 N030 N032 _ON ON 14 DFLOP Trise=20n +A52 UVLO 14 14 14 14 N032 14 14 BUF +A53 14 FX1A 14 ON 14 14 N019 14 AND Trise=100n +A54 14 FX2A 14 ON 14 14 N023 14 AND Trise=100n +D79 _ON N050 OR +D80 _ON N053 OR +D81 _ON N057 OR +D82 _ON N061 OR +D83 _ON N015 OR +D84 _ON N024 OR +D85 _ON N035 OR +D86 _ON N042 OR +A1 UVLO N033 N029 14 N040 S2 14 14 AND Trise=50n Tfall=250n tripdt=5n +A2 UVLO N028 N034 14 N040 S3 14 14 AND Trise=50n Tfall=250n tripdt=5n +A3 UVLO N033 N034 14 N040 S4 14 14 AND Trise=50n Tfall=250n tripdt=5n +A5 UVLO N028 N029 14 N040 S5 14 14 AND Trise=50n Tfall=250n tripdt=5n +A6 UVLO N033 N029 14 N040 S6 14 14 AND Trise=50n Tfall=250n tripdt=5n +A7 UVLO N028 N034 14 N040 S7 14 14 AND Trise=50n Tfall=250n tripdt=5n +A8 UVLO N033 N034 14 N040 S8 14 14 AND Trise=50n Tfall=250n tripdt=5n +A14 17 5 14 14 14 14 S2L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A15 5 18 14 14 14 14 S2H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A17 6 18 14 14 14 14 S3H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A18 17 6 14 14 14 14 S3L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A19 7 18 14 14 14 14 S4H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A20 17 7 14 14 14 14 S4L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A21 12 18 14 14 14 14 S5H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A22 17 12 14 14 14 14 S5L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A23 17 11 14 14 14 14 S6L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A24 11 18 14 14 14 14 S6H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A25 10 18 14 14 14 14 S7H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A26 17 10 14 14 14 14 S7L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A27 9 18 14 14 14 14 S8H 14 SCHMITT Vt=.7 Vh=0 Trise=120n Tfall=1.4u +A28 17 9 14 14 14 14 S8L 14 SCHMITT Vt=-.7 Vh=10m Trise=120n Tfall=1.4u +A55 N011 14 14 14 14 14 N012 14 BUF Trise=10n Tfall=70u +A31 N012 14 14 14 14 N013 N008 14 SCHMITT Vt=.5 Vh=.45 Trise=10n +C21 N021 14 1p +C23 14 N016 1p +C24 14 N025 1p +C25 14 N036 1p +C26 14 N043 1p +C27 14 N051 1p +C28 14 N065 1p +C29 14 N069 1p +C30 14 N073 1p +A49 FX1A FX2A FX1B FX2B N032 N030 14 14 OR +D1 F8 N061 OR +C31 15 14 12p +B5 14 FX2B I=(!V(S5,14)&V(S5L,14))|(!V(S6,14)&V(S6L,14))|(!V(S7,14)&V(S7L,14))|(!V(S8,14)&V(S8L,14)) Rpar=1 Cpar=1n NoJacob +B6 14 FX1B I=(!V(S5,14)&V(S5H,14))|(!V(S6,14)&V(S6H,14))|(!V(S7,14)&V(S7H,14))|(!V(S8,14)&V(S8H,14)) Rpar=1 Cpar=1n NoJacob +S47 15 18 N056 14 20µA +S48 15 17 N063 14 20µA +B7 SX2 0 V= !V(S5) ? V(12) : (!V(S6) ? V(11) : (!V(S7) ? V(10) : V(9))) +R1 15 N059 R=1Meg*(V(SX2,15)/V(13,3))**10+10 +A11 14 FX1B 14 ON 14 14 N056 14 AND Trise=100n +A50 14 FX2B 14 ON 14 14 N063 14 AND Trise=100n +B8 _ON 14 I=smallsig() +.model N VDMOS(Kp=2m Vto= .5 Is=0 mtriode=1 Cgs=.049p Ksubthres=.4 nlev=3 gdsnoi=2) +.model P VDMOS(Kp=2m Vto=-.5 pchan Is=0 mtriode=1 Cgs=.049p Ksubthres=.4 nlev=3 gdsnoi=2) +.model TN SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model BN SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model TP SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model BP SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model ESD D(Ron=1 Roff=1G epsilon=1) +.model OR D(Ron=1 Roff=1G epsilon=.25) +.model OUT SW(Ron=150 Roff=10Meg Vt=.5 Vh=-.4) +.model 3V VDMOS(Kp=200m Vto=-3 Ksubthres=.1) +.model 20µA SW(Ron=20K Roff=10T Vt=.5 Vh=-10m Ilimit=20u level=2) +.model DC SW(Ron=190 Roff=1G Vt=-.5 Vh=-.4) +.ends ADG5249F +* +.subckt ADG918 1 2 3 4 5 6 7 8 +C1 2 3 5p +C5 1 3 63p +A1 2 N008 3 3 3 N009 N001 3 SCHMITT Vt=0 Vh=1m tripdt=10n Trise=10n +S1 N010 1 3 N009 TN +S2 3 N010 N009 3 BN +S3 1 N011 N009 3 TP +S4 N011 3 3 N009 BP +C6 8 3 .4p +C7 4 3 .4p +M1 8 N010 4 4 N +M2 4 N011 8 8 P +D1 4 1 S +D2 3 8 S +D3 8 1 S +D4 3 4 S +S5 N004 1 3 N001 TN +S6 3 N004 N001 3 BN +S7 1 N005 N001 3 TP +S8 N005 3 3 N001 BP +C3 5 3 .4p +M3 4 N004 5 5 N +M4 5 N005 4 4 P +D5 5 1 S +D6 3 4 S +D7 4 1 S +D8 3 5 S +G1 3 N008 1 3 .5m +R3 N008 3 1K +C2 4 8 54f +C4 5 4 54f +S9 3 8 N009 3 TERM +S10 3 5 N001 3 TERM +.model N VDMOS(Kp=.12 Vto= .5 Is=0 mtriode=1.05 Cgs=.2p Ksubthres=.02 nlev=3 gdsnoi=2) +.model P VDMOS(Kp=.12 Vto=-.5 pchan Is=0 mtriode=1.05 Cgs=.2p Ksubthres=.02 nlev=3 gdsnoi=2) +.model TN SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model BN SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model TP SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model BP SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model S D(Ron=5 Roff=1G Vfwd=.4 epsilon=1) +.model TERM SW(Ron=50 Roff=1G Vt=.5 Vh=-.4) +.ends ADG918 +* +.subckt ADG919 1 2 3 4 5 6 7 8 +C1 2 3 5p +C5 1 3 63p +A1 2 N008 3 3 3 N009 N001 3 SCHMITT Vt=0 Vh=1m tripdt=10n Trise=10n +S1 N010 1 3 N009 TN +S2 3 N010 N009 3 BN +S3 1 N011 N009 3 TP +S4 N011 3 3 N009 BP +C6 8 3 .4p +C7 4 3 .4p +M1 8 N010 4 4 N +M2 4 N011 8 8 P +D1 4 1 S +D2 3 8 S +D3 8 1 S +D4 3 4 S +S5 N004 1 3 N001 TN +S6 3 N004 N001 3 BN +S7 1 N005 N001 3 TP +S8 N005 3 3 N001 BP +C3 5 3 .4p +M3 4 N004 5 5 N +M4 5 N005 4 4 P +D5 5 1 S +D6 3 4 S +D7 4 1 S +D8 3 5 S +G1 3 N008 1 3 .5m +R3 N008 3 1K +C2 4 8 54f +C4 5 4 54f +S9 3 8 N009 3 TERM +S10 3 5 N001 3 TERM +.model N VDMOS(Kp=.12 Vto= .5 Is=0 mtriode=1.05 Cgs=.2p Ksubthres=.02 nlev=3 gdsnoi=2) +.model P VDMOS(Kp=.12 Vto=-.5 pchan Is=0 mtriode=1.05 Cgs=.2p Ksubthres=.02 nlev=3 gdsnoi=2) +.model TN SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model BN SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model TP SW(Ron=500 Roff=1G Vt=.6 Vh=-.1) +.model BP SW(Ron=500 Roff=1G Vt=-.4 Vh=-.1) +.model S D(Ron=5 Roff=1G Vfwd=.4 epsilon=1) +.model TERM SW(Ron=.5 Roff=1G Vt=.5 Vh=-.4) +.ends ADG919 diff --git a/spice/copy/sub/ADG1201.sub b/spice/copy/sub/ADG1201.sub new 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s/¶R‚Öâm=å)PWå·`Ì^q#ÚAIÞ›{¡tFe»2eß ¦y6*à;´ŸýZV»(Pݧ¦Oµm«f4·>y­þðø{ tZEˆ1”Nà8lRX›ŠÍ, ¯=gog±!ä6¢ö· +5²Ëv Bjˆ4êY =pº½ïv85@B씩{=0, V(m,x)*(Gb + Gbx*V(m,x)),0) +B2 N005 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0) +D21 X 3 ESD +D22 4 X ESD +D5 N005 3 X1 +D6 4 N005 X2 +G2 0 M 3 0 500µ +R4 M 0 1K noiseless +G3 0 M 4 0 500µ +S1 X M 4 3 SD +A2 2 1 0 0 0 0 0 0 OTA g=0 in=.4p ink=200k incm=.04p incmk=200k +C11 3 1 .8p Rpar=160Meg noiseless +C4 N004 0 1.2p Rpar=1K noiseless +L1 N004 N006 1.2µ +C6 N006 0 1.2p Rpar=1K noiseless +C2 3 N005 1p +C3 3 5 1p +C7 5 4 1p +C8 N005 4 1p +D3 3 4 IQ +C5 1 4 .8p Rpar=160Meg noiseless +C9 2 4 .8p Rpar=160Meg noiseless +C10 3 2 .8p Rpar=160Meg noiseless +R1 2 1 280.49K noiseless +D4 3 2 450nA +D7 3 1 450nA +B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)+.6,.1), V(4)-.6, .1)+100n*V(1) +B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)+.6,.1), V(4)-.6, .1)+100n*V(2) +D2 5 N005 BB +D1 5 N005 AA +.param Cf = 1p +.param Ro = 5.2K +.param Avol = 15k +.param RL = 1K +.param AVmid = 80 +.param FmidA = 1Meg +.param Zomid = .6 +.param FmidZ = 1Meg +.param Vslew = 32Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.param Gbx = Gb +.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-5m epsilon=10m noiseless) +.model X2 D(Ron=1m Roff={2*Ro} Vfwd=-5m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model IQ D(Ron=1K Roff=100Meg epsilon=1 Ilimit=800u noiseless) +.model AA D(Ron=38 Vrev=0 Ilimit=35m revIlimit=35m noiseless) +.model BB D(Ron=150 Roff=10Meg Ilimit=15m epsilon=.5 noiseless) +.model 450nA D(Ron=150K Ilimit=.45u revilimit=.45u Vfwd=1.1 Vrev=-1.1 noiseless) +.ends AD8031 +* +.subckt AD8033 1 2 3 4 5 +C1 N006 X {Cf} +A1 N005 0 M M M M X M OTA g={Ga} Iout={Islew} en=11n enk=8k Vhigh=1e308 Vlow=-1e308 +D21 X 3 ESD +D22 4 X ESD +D5 N006 3 X1 +D6 4 N006 X1 +G2 0 M 3 0 500µ +R4 M 0 1K noiseless +G3 0 M 4 0 500µ +S1 X M 4 3 SD +A2 2 1 0 0 0 0 0 0 OTA g=0 in=7f ink=10 incm=.007f incmk=10 +C4 N004 0 2.1p Rpar=1K noiseless +L1 N004 N005 2.1µ +C6 N005 0 2.1p Rpar=1K noiseless +C2 3 N006 1p +C3 3 5 1p +C7 5 4 1p +C8 N006 4 1p +D3 3 4 IQ +D4 3 2 2p +D7 3 1 2p +D1 5 N006 AA +D8 2 1 ED2 +C5 3 1 .575p Rpar=4T noiseless +C9 1 4 .575p Rpar=4T noiseless +C10 2 4 .575p Rpar=4T noiseless +C11 3 2 .575p Rpar=4T noiseless +C18 2 1 1.125p +B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)-2.9,.1), V(4)-.1, .1)+100n*V(1) +B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)-2.9,.1), V(4)-.1, .1)+100n*V(2) +D2 5 3 X2 +D9 4 5 X2 +B1 3 N006 I=if(V(m,x)>=0, V(m,x)*Gb,0) +B2 N006 4 I=if(V(x,m)>0, V(x,m)*Gb,0) +.param Cf = .5p +.param Ro = 5K +.param Avol = 63K +.param RL = 1K +.param AVmid = 30 ; 80 +.param FmidA = 1Meg +.param Zomid = .1 +.param FmidZ = 200K +.param Vslew = 80Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.model ESD D(Ron=10 Roff=1T Vfwd=3 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff={4*Ro} Vfwd=.287 epsilon=10m noiseless) +.model X2 D(Ron=1m Roff={4*Ro} Vfwd=-20m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model IQ D(Ron=1K Roff=100Meg epsilon=1 Ilimit=1.8m noiseless) +.model AA D(Ron=30 Vrev=0 Ilimit=60m revIlimit=60m noiseless) +.model 2p D(Ron=1T epsilon=1 Ilimit=2p noiseless) +.model ED2 D(Ron=1 Roff=1.3T Vfwd=1 epsilon=1 Vrev=.75 revepsilon=1 noiseless) +.ends AD8033 +* +.subckt AD8038 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=600f ink=1k incm=60f incmk=1k +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C3 3 5 1p +C4 5 4 1p +A2 0 N005 M M M M N004 M OTA g=330u Isrc=43u en=8n enk=1k Vlow=-1e308 Vhigh=1e308 Cout= .1p asym +C10 N003 0 {.12p*x} Rpar=1K noiseless +D1 N004 5 Y +D6 5 N004 Y +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N004 M 4 3 UVLO +D3 N004 3 X +D4 4 N004 X +C2 3 2 1p Rpar=20Meg noiseless +C5 2 4 1p Rpar=20Meg noiseless +C6 3 1 1p Rpar=20Meg noiseless +C7 1 4 1p Rpar=20Meg noiseless +B1 N003 0 I=1m*dnlim(uplim(V(2),V(3)-.9,.1), V(4)+.9, .1)+100n*V(2) +B2 0 N003 I=1m*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+.9, .1)+100n*V(1) +C1 N005 0 {.12p*x} Rpar=1K noiseless +L1 N003 N005 {.12u*x} +.model X D(Ron=2K Roff=20Meg Vfwd=-1.1 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=1.2 epsilon=.1 noiseless) +.model N VDMOS(Vto=-100m Kp=.12 Ksubthres=.1 noiseless) +.model P VDMOS(Vto=100m Kp=.12 pchan Ksubthres=.1 noiseless) +.model UVLO SW(Ron=1K Roff=5G Vt=-3.75 Vh=.25 noiseless) +.param x =1.3 +.ends AD8038 +* +.subckt AD8029 1 2 3 4 5 6 +C1 N005 X {Cf} +A1 N006 0 M M M M X M OTA g={Ga} Iout={Islew} en=16.5n enk=500 Vhigh=1e308 Vlow=-1e308 +D21 X 3 ESD +D22 4 X ESD +D5 N005 3 X1 +D6 4 N005 X1 +G2 0 M 3 0 500µ +R4 M 0 1K noiseless +G3 0 M 4 0 500µ +S1 X M 4 3 SD +A2 2 1 0 0 0 0 0 0 OTA g=0 in=1.1p ink=4K incm=.1p incmk=4K +C11 3 1 1p Rpar=12Meg noiseless +C4 N004 0 {.5p*x} Rpar=1K noiseless +L1 N004 N006 {.5µ*x} +C6 N006 0 {.5p*x} Rpar=1K noiseless +C2 3 N005 {1p*y} +D4 3 2 bias +D1 5 N005 AA +D8 2 1 ED2 +C5 1 4 1p Rpar=12Meg noiseless +C9 2 4 1p Rpar=12Meg noiseless +C10 3 2 1p Rpar=12Meg noiseless +D7 3 1 bias +B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)+.3,.1), V(4)-.3, .1)+100n*V(2) +B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+100n*V(1) +D2 5 N005 BB +C3 3 5 {1p*y} +C7 5 4 {1p*y} +C8 N005 4 {1p*y} +D9 3 6 6.5uA +C12 6 4 1p Rpar=10Meg +S2 X M 4 6 DIS +S3 4 3 6 4 IQ +D3 3 4 IQ +B1 3 N005 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0) +B2 N005 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0) +.param Cf = 1.8p +.param Ro = 50K +.param Avol = 5K +.param RL = 1K +.param AVmid = 125 +.param FmidA = 1Meg +.param Zomid = 1.6 +.param FmidZ = 1Meg +.param Vslew = 50Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.param Gbx = 2*Gb +.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-15m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model IQ D(Ron=10K Roff=1G epsilon=1 Ilimit=90u noiseless) +.model IQ SW(Ron=1K Roff=100Meg Ilimit=1.25m level=2 Vt=1 Vh=-.2 noiseless) +.model AA D(Ron=40 Vrev=0 Ilimit=50m revIlimit=50m noiseless) +.model BB D(Ron=5 Vrev=1 Vfwd=1 epsilon=1 revepsilon=1 Ilimit=115m revIlimit=115m noiseless) +.model ED2 D(Ron=1 Roff=1T Vfwd=1.2 epsilon=1 Vrev=1.2 revepsilon=1 noiseless) +.model bias D(Ron=50K Ilimit=1.7u revilimit=.7u Vfwd=.5 Vrev=-.5 noiseless) +.model 6.5uA D(Ron=30K Vfwd=1 epsilon=1 Ilimit=6.5u noiseless) +.model DIS SW(Ron=1m Roff=1T Vt=-1 Vh=.2) +.param X=.7 y=.5 +.ends AD8029 +* +.subckt AD8040 1 2 3 4 5 +C1 N005 X {Cf} +A1 N006 0 M M M M X M OTA g={Ga} Iout={Islew} en=16.5n enk=500 Vhigh=1e308 Vlow=-1e308 +D21 X 3 ESD +D22 4 X ESD +D5 N005 3 X1 +D6 4 N005 X1 +G2 0 M 3 0 500µ +R4 M 0 1K noiseless +G3 0 M 4 0 500µ +S1 X M 4 3 SD +A2 2 1 0 0 0 0 0 0 OTA g=0 in=1.1p ink=4K incm=.1p incmk=4K +C11 3 1 1p Rpar=12Meg noiseless +C4 N004 0 {.5p*x} Rpar=1K noiseless +L1 N004 N006 {.5µ*x} +C6 N006 0 {.5p*x} Rpar=1K noiseless +C2 3 N005 {1p*y} +D3 3 4 IQ +D4 3 2 bias +D1 5 N005 AA +D8 2 1 ED2 +C5 1 4 1p Rpar=12Meg noiseless +C9 2 4 1p Rpar=12Meg noiseless +C10 3 2 1p Rpar=12Meg noiseless +D7 3 1 bias +B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)+.3,.1), V(4)-.3, .1)+100n*V(2) +B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+100n*V(1) +D2 5 N005 BB +C3 3 5 {1p*y} +C7 5 4 {1p*y} +C8 N005 4 {1p*y} +B1 3 N005 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0) +B2 N005 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0) +.param Cf = 1.8p +.param Ro = 50K +.param Avol = 5K +.param RL = 1K +.param AVmid = 125 +.param FmidA = 1Meg +.param Zomid = 1.6 +.param FmidZ = 1Meg +.param Vslew = 50Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.param Gbx = 2*Gb +.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-15m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model IQ D(Ron=1K Roff=100Meg epsilon=1 Ilimit=1.25m noiseless) +.model AA D(Ron=40 Vrev=0 Ilimit=50m revIlimit=50m noiseless) +.model BB D(Ron=5 Vrev=1 Vfwd=1 epsilon=1 revepsilon=1 Ilimit=115m revIlimit=115m noiseless) +.model ED2 D(Ron=1 Roff=1T Vfwd=1.2 epsilon=1 Vrev=1.2 revepsilon=1 noiseless) +.model bias D(Ron=50K Ilimit=1.7u revilimit=.7u Vfwd=.5 Vrev=-.5 noiseless) +.param X=.7 y=.5 +.ends AD8040 +* +.subckt AD8041 1 2 3 4 5 6 +C1 N005 X {Cf} Rser=150 +A1 N006 0 M M M M X M OTA g={Ga} Iout={Islew} en=16n enk=850 Vhigh=1e308 Vlow=-1e308 +D21 X 3 ESD +D22 4 X ESD +D5 N005 3 X1 +D6 4 N005 X1 +G2 0 M 3 0 500µ +R4 M 0 1K noiseless +G3 0 M 4 0 500µ +S1 X M 4 3 SD +A2 2 1 0 0 0 0 0 0 OTA g=0 in=600f ink=2K incm=60f incmk=2K +C11 3 1 .9p Rpar=320K noiseless +C4 N004 0 {.5p*x} Rpar=1K noiseless +L1 N004 N006 {.5µ*x} +C6 N006 0 {.5p*x} Rpar=1K noiseless +C2 3 N005 1p +D1 5 N005 AA +C3 3 5 1p +C7 5 4 1p +C8 N005 4 1p +C12 3 6 1p Rpar=2Meg noiseless +S2 M X 3 6 DIS +S3 3 4 6 3 IQ +D3 3 4 IQ +I1 3 1 1.2µ load +I2 3 2 1.2µ load +C5 1 4 .9p Rpar=320K noiseless +C9 2 4 .9p Rpar=320K noiseless +C10 3 2 .9p Rpar=320K noiseless +B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)-.9,.1), V(4)-.3, .1)+100n*V(2) +B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)-.9,.1), V(4)-.3, .1)+100n*V(1) +D2 5 N005 BB +B1 3 N005 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0) +B2 N005 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0) +.param Cf = 1p +.param Ro = 6.5K +.param Avol = 70K +.param RL = 2K +.param AVmid = 150 +.param FmidA = 1Meg +.param Zomid = 5.5 +.param FmidZ = 1Meg +.param Vslew = 160Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.param Gbx = 20*Gb +.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model IQ D(Ron=10K Roff=1G epsilon=1 Ilimit=1.6m noiseless) +.model IQ SW(Ron=200 Roff=100Meg Ilimit=4.2m level=2 Vt=-2 Vh=-.2 noiseless) +.model AA D(Ron=33 Vrev=0 Ilimit=50m revIlimit=50m noiseless) +.model BB D(Ron=3 Vrev=1 Vfwd=.1 epsilon=.1 revepsilon=.5 Ilimit=100m revIlimit=50m noiseless) +.model bias D(Ron=50K Ilimit=1.7u revilimit=.7u Vfwd=.5 Vrev=-.5 noiseless) +.model 6.5uA D(Ron=30K Vfwd=1 epsilon=1 Ilimit=6.5u noiseless) +.model DIS SW(Ron=1m Roff=1T Vt=2 Vh=.2) +.param X=.7 +.ends AD8041 +* +* AD8042a Spice Macro-model +* Description: Amplifier +* Generic Desc: Dual 160MHz Rail-to-rail amplifier +* Developed by: +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (09/1996) +* Copyright 1996, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* Distortion and noise are not characterized +* +* Parameters modeled include: +* open loop gain and phase vs frequency +* output clamping voltage and current +* input common mode range +* CMRR vs freq +* I bias vs Vcm in +* Slew rate +* Output currents are reflected to V supplies +* Vos is static and will not vary with Vcm in +* Step response is modeled at unity gain w/1k load +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8042a 1 2 99 50 61 +*#ASSOC Category="Op-amps" symbol=opamp + +***** Input bias current source + +ecm 20 0 99 3 1 +d1 20 21 dx +v3 21 22 0.2 +r20 22 0 100 +f1 0 25 v3 1 +r22 25 0 1k +r23 26 28 8 +d3 25 26 dx +v5 28 0 .3 +g1 1 0 0 25 400e-9 +g2 2 0 0 25 400e-9 + +***** Input Stage + +R1 1 3 80k +R2 3 2 80k +C1 1 2 1.8pf +rcm1 1 0 5e6 +rcm2 2 0 5e6 +R3 1 98 40e6 +R4 2 98 40e6 +r9 15 7 764 +r10 16 7 764 +q1 5 1 15 qp1 +q2 6 4 16 qp1 +r5 50 5 1254 +r6 50 6 1254 +ib3 99 7 1e-4 +eos 2 4 poly(1) (108,98) 2e-3 1 + +***** gain stage/pole at 3200hz/clamp circuitry + +g3 99 31 6 5 7.97e-4 +g4 31 50 5 6 7.97e-4 +r7 99 31 63e6 +r8 31 50 63e6 +c3 99 31 0.635e-12 +c4 31 50 0.635e-12 + +vc1 99 45 0.72 +vc2 46 50 0.72 +dc1 31 45 dx +dc2 46 31 dx + +***** pole at 200mhz + +e1 32 98 31 98 1 +rflt 32 33 1k +cflt 33 98 0.796e-12 + +***** internal reference + +rdiv1 99 97 100k +rdiv2 97 50 100k +Eref 98 0 97 0 1 +rref 98 0 1e6 + +***** Common mode gain network + +gacm1 99 100 3 98 2e-13 +gacm2 100 50 98 3 2e-13 +racm1 99 100 1e4 +racm2 100 50 1e4 + +***** Common mode gain network/zero at 3200hz + +ecm1 101 98 100 98 1e6 +racm3 101 102 1e6 +racm4 102 103 1 +lacm1 103 98 40u + +***** Common mode gain network/zero at 100khz/pole at 60mhz + +ecm2 104 98 102 98 300 +racm5 104 105 300 +racm6 105 106 1 +lacm2 106 98 .78u + +***** Common mode gain network/pole at 60mhz + +ecm3 107 98 105 98 1 +racm7 107 108 10k +cacm1 108 98 0.265e-12 + +***** buffer to output stage + +gbuf 98 34 33 98 1e-4 +re1 34 98 10k + +***** output stage + +fo1 98 110 vcd 1 +do1 110 111 dx +do2 112 110 dx +vi1 111 98 0 +vi2 98 112 0 + +fsy 99 50 poly(2) vi1 vi2 4.73e-3 1 1 + +go3 60 99 99 34 0.1 +go4 50 60 34 50 0.1 +r03 60 99 10 +r04 60 50 10 +vcd 60 62 0 +lo1 62 61 2n +ro2 61 98 1e9 +do5 34 70 dx +do6 71 34 dx +vo1 70 60 -0.31 +vo2 60 71 -0.05 + +.model dx d(is=1e-15) +.model qn1 npn(bf=500 vaf=100) +.model qp1 pnp(bf=500 vaf=60) +.ends AD8042a + + + + + +* AD8044a Spice Macro-model +* Description: Amplifier +* Generic Desc: Quad 150MHz Rail-to-rail amplifier +* Developed by: +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (09/1996) +* Copyright 1996, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* Distortion and noise are not characterized +* +* Parameters modeled include: +* open loop gain and phase vs frequency +* output clamping voltage and current +* input common mode range +* CMRR vs freq +* I bias vs Vcm in +* Slew rate +* Output currents are reflected to V supplies +* Vos is static and will not vary with Vcm in +* Step response is modeled at unity gain w/1k load +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8044a 1 2 99 50 61 +*#ASSOC Category="Op-amps" symbol=opamp + +***** Input bias current source + +ecm 20 0 99 3 1 +d1 20 21 dx +v3 21 22 0.2 +r20 22 0 100 +f1 0 25 v3 1 +r22 25 0 1k +r23 26 28 8 +d3 25 26 dx +v5 28 0 .3 +g1 1 0 0 25 400e-9 +g2 2 0 0 25 400e-9 + +***** Input Stage + +R1 1 3 80k +R2 3 2 80k +C1 1 2 1.8pf +rcm1 1 0 5e6 +rcm2 2 0 5e6 +R3 1 98 40e6 +R4 2 98 40e6 +r9 15 7 764 +r10 16 7 764 +q1 5 1 15 qp1 +q2 6 4 16 qp1 +r5 50 5 1254 +r6 50 6 1254 +ib3 99 7 1e-4 +eos 2 4 poly(1) 108 98 2e-3 1 + +***** gain stage/pole at 3200hz/clamp circuitry + +*g3 99 31 6 5 7.97e-4 +*g4 31 50 5 6 7.97e-4 +*r7 99 31 63e6 +*r8 31 50 63e6 +*c3 99 31 0.635e-12 +*c4 31 50 0.635e-12 +g3 99 31 6 5 6.37e-4 +g4 31 50 5 6 6.37e-4 +r7 99 31 82.9e6 +r8 31 50 82.9e6 +c3 99 31 0.6e-12 +c4 31 50 0.6e-12 + +vc1 99 45 0.72 +vc2 46 50 0.72 +dc1 31 45 dx +dc2 46 31 dx + +***** pole at 100mhz + +e1 32 98 31 98 1 +rflt 32 33 1k +cflt 33 98 1.6e-12 + +***** internal reference + +rdiv1 99 97 100k +rdiv2 97 50 100k +Eref 98 0 97 0 1 +rref 98 0 1e6 + +***** Common mode gain network + +gacm1 99 100 3 98 2e-13 +gacm2 100 50 98 3 2e-13 +racm1 99 100 1e4 +racm2 100 50 1e4 + +***** Common mode gain network/zero at 3200hz + +ecm1 101 98 100 98 1e6 +racm3 101 102 1e6 +racm4 102 103 1 +lacm1 103 98 40u + +***** Common mode gain network/zero at 100khz/pole at 60mhz + +ecm2 104 98 102 98 300 +racm5 104 105 300 +racm6 105 106 1 +lacm2 106 98 .78u + +***** Common mode gain network/pole at 60mhz + +ecm3 107 98 105 98 1 +racm7 107 108 10k +cacm1 108 98 0.265e-12 + +***** buffer to output stage + +gbuf 98 34 33 98 1e-4 +re1 34 98 10k + +***** output stage + +fo1 98 110 vcd 1 +do1 110 111 dx +do2 112 110 dx +vi1 111 98 0 +vi2 98 112 0 + +fsy 99 50 poly(2) vi1 vi2 4.73e-3 1 1 + +go3 60 99 99 34 0.1 +go4 50 60 34 50 0.1 +r03 60 99 10 +r04 60 50 10 +vcd 60 62 0 +lo1 62 61 2n +ro2 61 98 1e9 +do5 34 70 dx +do6 71 34 dx +vo1 70 60 -0.31 +vo2 60 71 -0.05 + +.model dx d(is=1e-15) +.model qn1 npn(bf=500 vaf=100) +.model qp1 pnp(bf=500 vaf=60) +.ends AD8044a + + + + + + +* AD8047 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 250MHz (G=1) voltage feedback op amp +* Developed by: JCH / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (11/1997) +* Copyright 1997, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* CAUTION: NOISE PERFORMANCE IS NOT INCLUDED IN THIS MODEL. NOISE +* MODELING WILL BE INCLUDED IN A LATER REVISION. +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8047 3 1 99 50 44 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE AND POLE AT 800MHZ +* +I1 8 50 1E-3 +Q1 4 1 6 QN +Q2 5 2 7 QN +R1 99 4 862 +R2 99 5 862 +C1 4 5 0.116p +R3 6 8 810.5 +R4 7 8 810.5 +RCM1 1 20 5G +RCM2 3 20 5G +IOS 1 3 3u +EOS 3 2 POLY(1) (16,98) 1E-3 1 +CIN1 1 99 1.5PF +CIN2 2 99 1.5PF +* +* GAIN STAGE AND DOMINANT POLE AT 110KHZ +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +G1 98 9 (4,5) 1.16E-3 +R5 9 98 1.085E6 +C2 9 98 1.333E-12 +D1 9 10 DX +D2 11 9 DX +H1 99 10 POLY(1) Vout 1.87 37.9 -3.94E2 2.44E3 +H2 11 50 POLY(1) Vout 1.93 -40.3 -4.51E2 -2.70E3 +* +*POLE AT 1.1GHZ +* +GP1 98 12 (9,98) 1 +RP1 98 12 1 +CP1 98 12 0.14N +* +*POLE AT 1.1GHZ +* +GP2 98 13 (12,98) 1 +RP2 98 13 1 +CP2 98 13 0.14N +* +*POLE AT 1.1GHZ +* +GP3 98 14 (13,98) 1 +RP3 98 14 1 +CP3 98 14 0.14N +* +*POLE AT 1.3GHZ +* +GP4 98 17 (14,98) 1 +RP4 98 17 1 +CP4 98 17 0.12N +* +*COMMON-MODE ZERO AT 113KHZ +* +GCM1 98 15 20 98 1E-10 +RCM3 15 16 1MEG +LCM1 16 98 1.4 +* +* BUFFER TO OUTPUT STAGE +* +GB11 98 40 (14,98) 200m +RB11 98 40 5 +* +* OUTPUT STAGE +* +RO1 99 45 0.4 +RO2 45 50 0.4 +G7 45 99 (99,40) 2.5 +G8 50 45 (40,50) 2.5 +G9 98 60 (45,40) 2.5 +D7 60 61 DX +D8 62 60 DX +V7 61 98 DC 0 +V8 98 62 DC 0 +FSY 99 50 POLY(2) V7 V8 4E-3 1 1 +D9 41 45 DX +D10 45 42 DX +V5 40 41 0.68 +V6 42 40 0.68 +Vout 45 46 0 +LO 46 44 .06E-9 +* +* MODELS USED +* +.MODEL DX D +.MODEL QN NPN(BF=500) +.ENDS AD8047 + + + + + + +*AD8065 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.2.1 Jun 2015-ZZ +*Copyright 2015 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +.Subckt AD8065 100 101 102 103 104 +*#ASSOC Category="Op-Amps" symbol=opamp +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.64e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 5.76e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 400e-6 +IbiasP 110 2 dc 2e-12 +IbiasN 110 9 dc 2e-12 +RinCMP 110 2 Rideal 10000e6 +RinCMN 9 110 Rideal 10000e6 +CinCMP 110 2 1.1e-12 +CinCMN 9 110 1.1e-12 +IOS 9 2 1e-12 +RinDiff 9 2 Rideal 10000e3 +CinDiff 9 2 4e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 3.06 +VinN 42 112 dc 0.46 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2 +VPD1 81 0 dc 1.5 +RPD 111 106 Rideal 0.286e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 150 Hz*** +g210 210 110 200 110 1.684e-6 +R210 210 110 Rideal 1061.03e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.176 +VoutN 64 66 dc 5.072 +e60 65 110 111 110 1.038 +e61 66 110 112 110 1.038 +* +* +***Pole at 90MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 1.7684e-12 +* +***Pole at 1400MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.1137e-12 +* +***Pole at 1800MHz*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +C240 240 110 0.0884e-12 +* +***Zero at 1000MHz*** +g245 245 110 240 110 0.001 +R245 245 246 Rideal 1000 +L245 246 110 0.1592e-6 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +* +***Peak: f=210MHz, Zeta=0.999999999999999, Gain=2.3dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 3.789e-9 +C290 291 292 151.576e-12 +R291 292 110 Rideal 32.985 +e295 295 110 292 110 1.3032 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 4.9 +Lout 303 310 7e-9 +Cout 310 110 46e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 8.336 +VIoutN 304 306 dc 8.336 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.735 +VoutN1 74 112 dc 0.715 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=107.367) +.model DzSlewN D(BV=107.367) +.model DVnoisy D(IS=1.41e-15 KF=1.05e-15) +.model DINnoisy D(IS=3.81e-23 KF=0.00e0) +.model DIPnoisy D(IS=3.81e-23 KF=0.00e0) +.model Rideal res(T_ABS=-273) +* +.ends AD8065 + +*AD8066 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.2.1 Jun 2015-ZZ +*Copyright 2015 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +.Subckt AD8066 100 101 102 103 104 +*#ASSOC Category="Op-Amps" symbol=opamp +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.64e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 5.76e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 400e-6 +IbiasP 110 2 dc 2e-12 +IbiasN 110 9 dc 2e-12 +RinCMP 110 2 Rideal 10000e6 +RinCMN 9 110 Rideal 10000e6 +CinCMP 110 2 1.1e-12 +CinCMN 9 110 1.1e-12 +IOS 9 2 1e-12 +RinDiff 9 2 Rideal 10000e3 +CinDiff 9 2 4e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 3.06 +VinN 42 112 dc 0.46 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2 +VPD1 81 0 dc 1.5 +RPD 111 106 Rideal 0.286e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 150 Hz*** +g210 210 110 200 110 1.684e-6 +R210 210 110 Rideal 1061.03e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.176 +VoutN 64 66 dc 5.072 +e60 65 110 111 110 1.038 +e61 66 110 112 110 1.038 +* +* +***Pole at 90MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 1.7684e-12 +* +***Pole at 1400MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.1137e-12 +* +***Pole at 1800MHz*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +C240 240 110 0.0884e-12 +* +***Zero at 1000MHz*** +g245 245 110 240 110 0.001 +R245 245 246 Rideal 1000 +L245 246 110 0.1592e-6 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +* +***Peak: f=210MHz, Zeta=0.999999999999999, Gain=2.3dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 3.789e-9 +C290 291 292 151.576e-12 +R291 292 110 Rideal 32.985 +e295 295 110 292 110 1.3032 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 4.9 +Lout 303 310 7e-9 +Cout 310 110 46e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 8.336 +VIoutN 304 306 dc 8.336 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.735 +VoutN1 74 112 dc 0.715 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=107.367) +.model DzSlewN D(BV=107.367) +.model DVnoisy D(IS=1.41e-15 KF=1.05e-15) +.model DINnoisy D(IS=3.81e-23 KF=0.00e0) +.model DIPnoisy D(IS=3.81e-23 KF=0.00e0) +.model Rideal res(T_ABS=-273) +* +.ends AD8066 + +*AD8067 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.2.1 Jun 2015-ZZ +*Copyright 2015 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +.Subckt AD8067 100 101 102 103 104 +*#ASSOC Category="Op-Amps" symbol=opamp +* +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.65e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 5.85e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 200e-6 +IbiasP 110 2 dc 0.6e-12 +IbiasN 110 9 dc 0.6e-12 +RinCMP 110 2 Rideal 10000e6 +RinCMN 9 110 Rideal 10000e6 +CinCMP 110 2 0.8e-12 +CinCMN 9 110 0.8e-12 +IOS 9 2 0.2e-12 +RinDiff 9 2 Rideal 10000e3 +CinDiff 9 2 4e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 3.46 +VinN 42 112 dc 0.46 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2.6 +VPD1 81 0 dc 0.1 +RPD 111 106 Rideal 1e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 280 Hz*** +g210 210 110 200 110 6.2719e-6 +R210 210 110 Rideal 568.41e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.289 +VoutN 64 66 dc 5.34 +e60 65 110 111 110 1.038 +e61 66 110 112 110 1.038 +* +* +***Pole at 100MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 1.5915e-12 +* +***Pole at 550MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.2894e-12 +* +***Pole at 550MHz*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +C240 240 110 0.2894e-12 +* +***Pole at 550MHz*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +C245 245 110 0.2894e-12 +* +***Pole at 580MHz*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +C250 250 110 0.2744e-12 +* +***Pole at 600MHz*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +C255 255 110 0.2653e-12 +* +***Pole at 600MHz*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +C260 260 110 0.2653e-12 +* +***Pole at 1690MHz*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +C265 265 110 0.0942e-12 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +* +***Peak: f=80MHz, Zeta=1.1, Gain=0.2dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 9.043e-9 +C290 291 292 437.676e-12 +R291 292 110 Rideal 429.314 +e295 295 110 292 110 1.0233 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 5 +Lout 303 310 29e-9 +Cout 310 110 6e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 9.836 +VIoutN 304 306 dc 9.836 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.765 +VoutN1 74 112 dc 0.765 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=0.105,Voff=0.095,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=102.518) +.model DzSlewN D(BV=102.518) +.model DVnoisy D(IS=1.49e-15 KF=3.61e-16) +.model DINnoisy D(IS=1.37e-23 KF=5.70e-19) +.model DIPnoisy D(IS=1.37e-23 KF=5.70e-19) +.model Rideal res(T_ABS=-273) +* +.ends AD8067 + +* AD8091 SPICE Macro-model +* Description: Amplifier +* Generic Desc: Single 110MHz rail-to-rail op amp 2.7V +* Developed by: TRW / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (02/2002) +* Copyright 1998, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* CMRR IS NOT MODELED +* +* Parameters modeled include: +* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V) +* +* END Notes +* +* Node assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8091 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +Q1 4 3 5 QPI +Q2 6 2 7 QPI +RC1 50 4 20.5k +RC2 50 6 20.5k +RE1 5 8 5k +RE2 7 8 5k +EOS 3 1 POLY(1) 53 98 1.7E-3 1 +IOS 1 2 0.1u +FNOI1 1 0 VMEAS2 1E-4 +FNOI2 2 0 VMEAS2 1E-4 + +CPAR1 3 50 1.7p +CPAR2 2 50 1.7p +VCMH1 99 9 1 +VCMH2 99 10 1 +D1 5 9 DX +D2 7 10 DX +IBIAS 99 8 73u +* +* INTERNAL VOLTAGE REFERENCE +* +EREF1 98 0 POLY(2) 99 0 50 0 0 0.5 0.5 +EREF2 97 0 POLY(2) 1 0 2 0 0 0.5 0.5 +GREF2 97 0 97 0 1E-6 +* +*VOLTAGE NOISE STAGE +* +DN1 51 52 DNOI1 +VN1 51 98 0.61 +VMEAS 52 98 0 +RNOI1 52 98 6.5E-3 + +H1 53 98 VMEAS 1 +RNOI2 53 98 1 +* +*CURRENT NOISE STAGE +* +DN2 61 62 DNOI2 +VN2 61 98 0.545 +VMEAS2 62 98 0 +RNOI3 62 98 2E-4 +* +* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz +* +G1 98 20 4 6 1E-3 +RP1 98 20 550 +CP1 98 20 3p +* +* GAIN STAGE WITH DOMINANT POLE +* +G4 98 30 20 98 2.6E-3 +RG1 30 98 155k +CF1 30 45 13.5p +D5 31 99 DX +D6 50 32 DX +V1 31 30 0.6 +V2 30 32 0.6 +* +* OUTPUT STAGE +* +Q3 45 42 99 QPOX +Q4 45 44 50 QNOX +EO3 99 42 POLY(1) 98 30 0.7175 0.5 +EO4 44 50 POLY(1) 30 98 0.7355 0.5 +* +* MODELS +* +.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6) +.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3) +.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6) +.MODEL DX D(IS=1E-16) +.MODEL DZ D(IS=1E-14,BV=6.6) +.MODEL DNOI1 D(KF=9E-10) +.MODEL DNOI2 D(KF=1E-8) +.ENDS AD8091 + + + + + + +* AD8092 SPICE Macro-model +* Description: Amplifier +* Generic Desc: Dual 110MHz rail-to-rail op amp 2.7V +* Developed by: TRW / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (02/2002) +* Copyright 1998, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* CMRR IS NOT MODELED +* +* Parameters modeled include: +* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V) +* +* END Notes +* +* Node assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8092 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +Q1 4 3 5 QPI +Q2 6 2 7 QPI +RC1 50 4 20.5k +RC2 50 6 20.5k +RE1 5 8 5k +RE2 7 8 5k +EOS 3 1 POLY(1) 53 98 1.7E-3 1 +IOS 1 2 0.1u +FNOI1 1 0 VMEAS2 1E-4 +FNOI2 2 0 VMEAS2 1E-4 + +CPAR1 3 50 1.7p +CPAR2 2 50 1.7p +VCMH1 99 9 1 +VCMH2 99 10 1 +D1 5 9 DX +D2 7 10 DX +IBIAS 99 8 73u +* +* INTERNAL VOLTAGE REFERENCE +* +EREF1 98 0 POLY(2) 99 0 50 0 0 0.5 0.5 +EREF2 97 0 POLY(2) 1 0 2 0 0 0.5 0.5 +GREF2 97 0 97 0 1E-6 +* +*VOLTAGE NOISE STAGE +* +DN1 51 52 DNOI1 +VN1 51 98 0.61 +VMEAS 52 98 0 +RNOI1 52 98 6.5E-3 + +H1 53 98 VMEAS 1 +RNOI2 53 98 1 +* +*CURRENT NOISE STAGE +* +DN2 61 62 DNOI2 +VN2 61 98 0.545 +VMEAS2 62 98 0 +RNOI3 62 98 2E-4 +* +* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz +* +G1 98 20 4 6 1E-3 +RP1 98 20 550 +CP1 98 20 3p +* +* GAIN STAGE WITH DOMINANT POLE +* +G4 98 30 20 98 2.6E-3 +RG1 30 98 155k +CF1 30 45 13.5p +D5 31 99 DX +D6 50 32 DX +V1 31 30 0.6 +V2 30 32 0.6 +* +* OUTPUT STAGE +* +Q3 45 42 99 QPOX +Q4 45 44 50 QNOX +EO3 99 42 POLY(1) 98 30 0.7175 0.5 +EO4 44 50 POLY(1) 30 98 0.7355 0.5 +* +* MODELS +* +.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6) +.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3) +.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6) +.MODEL DX D(IS=1E-16) +.MODEL DZ D(IS=1E-14,BV=6.6) +.MODEL DNOI1 D(KF=9E-10) +.MODEL DNOI2 D(KF=1E-8) +.ENDS AD8092 + + + + + + +* AD811 SPICE Macro-model +* Description: Amplifier +* Generic Desc: High Performance Video Op Amp +* Developed by: JCB / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/1991) +* Copyright 1991, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD811 1 2 99 50 28 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +R1 99 8 1E3 +R2 10 50 1E3 +V1 99 9 11 +D1 9 8 DX +V2 11 50 11 +D2 10 11 DX +I1 99 5 920E-6 +I2 4 50 920E-6 +Q1 5 5 3 QN +Q2 4 4 3 QP +Q3 8 5 30 QN +Q4 10 4 30 QP +* +* INPUT ERROR SOURCES +* +GB1 99 1 POLY(1) 1 22 2E-6 1E-6 +GB2 99 30 POLY(1) 1 22 2E-6 1E-6 +VOS 3 1 500E-6 +LS1 30 2 4E-8 +CS1 99 2 0.5E-12 +CS2 50 2 0.5E-12 +CIN 1 50 2E-12 +* +EREF 97 0 22 0 1 +* +* GAIN STAGE & DOMINANT POLE +* +R5 12 97 1.5E6 +C3 12 97 3.9E-12 +G1 97 12 99 8 1E-3 +G2 12 97 10 50 1E-3 +V3 99 13 2.9 +V4 14 50 2.9 +D3 12 13 DX +D4 14 12 DX +* +* POLE AT 400 MHZ +* +R8 17 97 1E6 +C4 17 97 0.530E-15 +G4 97 17 12 22 1E-6 +* +* ZERO AT 150 MHZ +* +R20 18 19 1E6 +R21 19 97 1 +C20 18 19 -.530E-15 +E20 18 97 17 22 1E6 +* +* POLE AT 200 MHZ +* +R12 21 97 1E6 +C8 21 97 0.395E-15 +G8 97 21 19 22 1E-6 +* +* OUTPUT STAGE +* +ISY 99 50 14.7E-3 +R13 22 99 16.7E3 +R14 22 50 16.7E3 +R15 27 99 22 +R16 27 50 22 +L2 27 28 1E-8 +G9 25 50 21 27 45.45E-3 +G10 26 50 27 21 45.45E-3 +G11 27 99 99 21 45.45E-3 +G12 50 27 21 50 45.45E-3 +V5 23 27 1.3 +V6 27 24 1.3 +D5 21 23 DX +D6 24 21 DX +D7 99 25 DX +D8 99 26 DX +D9 50 25 DY +D10 50 26 DY +* +* MODELS USED +* +.MODEL QN NPN(BF=1E9 IS=1E-15) +.MODEL QP PNP(BF=1E9 IS=1E-15) +.MODEL DX D(IS=1E-15) +.MODEL DY D(IS=1E-15 BV=50) +.ENDS AD811 + + + + + + +* AD815 Spice Macro-model +* Description: Amplifier +* Generic Desc: High output differential driver amp +* Developed by: +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (09/1996) +* Copyright 1996, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. +* Use of this model indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* distortion is not characterized +* +* Parameters modeled include: +* closed loop gain and phase vs bandwidth +* output current and voltage limiting +* offset voltage (is static, will not vary with vcm) +* ibias (again, is static, will not vary with vcm) +* slew rate and step response performance +* (slew rate is based on 10-90% of step response) +* current on output will be reflected to the supplies +* vnoise, referred to the input +* inoise, referred to the input +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD815 1 2 99 50 61 +*#ASSOC Category="Op-amps" symbol=opamp + + +***** Input Stage + +q1 50 41 4 qp1 +q2 99 41 3 qn1 +i1 99 4 1e-4 +i2 3 50 1e-4 + +fni 99 2 vn2 1 +fnn 99 1 vn2 0.1 + +*ibneg 2 99 10e-6 +*ibpos 1 99 2e-6 + +cin1 4 88 1.4pf +cin2 2 88 1.4pf + +q3 9 4 2 qn2 +q4 10 3 2 qp2 + +rxxa 99 4 28k +rxxb 3 50 28k + + +VT1 99 9 0 ;ammeters for monitoring +VT2 50 10 0 ;current thru Q3, Q4 +eos 41 1 poly(1) 43 88 5e-3 1 + +***** internal vnoise source + +dn1 42 88 dnv +rn1 42 88 5e-3 +vn1 42 88 0 + +hn1 43 88 vn1 1 +rn2 43 88 1 + +***** internal inoise source + +dn2 72 88 dniinv +rn3 72 88 50 +vn2 72 88 0 + +hn2 73 88 vn2 1 +rn4 73 88 1 + +***** internal reference + +Eref 88 0 poly(2) 99 0 50 0 0 0.5 0.5 + +***** gain stage/dominant pole/clamp circuitry + +f3 88 31 vt1 0.7e-4 +f4 88 31 vt2 0.7e-4 +dgain1 88 31 dy +dgain2 31 88 dy + +egain1 28 88 31 88 143000 +r3 28 29 5 +c1 29 88 4500nf + +vc1 99 45 3.65 +vc2 46 50 3.65 +dc1 29 45 dx +dc2 46 29 dx + +***** pole at 100MHz + +egain2 32 88 88 29 1 +r4 32 44 0.001 +c3 44 88 1500000p + +***** buffer to output stage + +gbuf 34 88 44 88 1e-2 +re1 34 88 100 + +***** output stage + +fo1 88 110 vcd 1 +do1 110 111 dx +do2 112 110 dx +vi1 111 88 0 +vi2 88 112 0 + +fsy 99 50 poly(2) vi1 vi2 5.61e-4 1 1 + +go3 60 99 99 34 0.385 +go4 50 60 34 50 0.385 +r03 60 99 2.6 +r04 60 50 2.6 +vcd 60 62 0 +lo1 62 61 1e-10 +ro2 61 88 1e9 +do5 34 70 dx +do6 71 34 dx +vo1 70 60 0.45 +vo2 60 71 0.45 + +.model dx d(is=1e-13 kf=1e-30 af=0) +.model dy d(is=26e-9 kf=1e-30 af=0) +.model dnv d(is=1e-15 kf=2e-15 af=0) +.model dniinv d(is=1e-15 kf=1e-19 af=0) +.model qn1 npn(bf=200 kf=1e-30 af=0) +.model qn2 npn(bf=200 kf=1e-30 af=0) +.model qp1 pnp(bf=200 kf=1e-30 af=0) +.model qp2 pnp(bf=200 kf=1e-30 af=0) +.ends ad815 +* +.subckt AD823 1 2 3 4 5 +C1 N006 X {Cf} +A1 N005 0 M M M M X M OTA g={Ga} Iout={Islew} en=16n enk=250 Vhigh=1e308 Vlow=-1e308 +B1 3 N006 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0) +B2 N006 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0) +D21 X 3 ESD +D22 4 X ESD +D5 N006 3 X1 +D6 4 N006 X2 +G2 0 M 3 0 500µ +R4 M 0 1K noiseless +G3 0 M 4 0 500µ +S1 X M 4 3 SD +A2 2 1 0 0 0 0 0 0 OTA g=0 in=1f ink=100 incm=.08f incmk=100 +C11 3 1 .9p Rpar=2e13 noiseless +C4 N004 0 5p Rpar=1K noiseless +L1 N004 N005 5µ +C6 N005 0 5p Rpar=1K noiseless +I3 3 4 50µ load +C2 3 N006 1p +C3 3 5 1p +C7 5 4 1p +C8 N006 4 1p +C5 1 4 .9p Rpar=2e13 noiseless +C10 2 4 .9p Rpar=2e13 noiseless +C12 3 2 .9p Rpar=2e13 noiseless +B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)+-.3, .1)+100n*V(1) +B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)-1.1,.1), V(4)+-.3, .1)+100n*V(2) +D3 3 4 IQ +I1 3 2 5p load +I2 3 1 5p load +D1 5 N006 A +.param Cf = 1p +.param Ro = 11K +.param Avol = 149K +.param RL = 2K +.param AVmid = 16 +.param FmidA = 1Meg +.param Zomid = .2 +.param FmidZ = 100K +.param Vslew = 25Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.param Gbx = Gb +.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless) +.model X2 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model IQ D(Ron=1K Roff=10Meg epsilon=1 Ilimit=2.6m noiseless) +.model 1uA D(Ron=1Meg Vfwd=2 epsilon=1 Ilimit=1u noiseless) +.model A D(Ron=20 Roff=20 epsilon=10m Ilimit=80m revIlimit=60m Vrev=0 noiseless) +.ends AD823 +* +* +* +.subckt AD823A 1 2 3 4 5 +C1 N006 X {Cf} +A1 N005 0 M M M M X M OTA g={Ga} Iout={Islew} en=16n enk=250 Vhigh=1e308 Vlow=-1e308 +B1 3 N006 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0) +B2 N006 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0) +D21 X 3 ESD +D22 4 X ESD +D5 N006 3 X1 +D6 4 N006 X2 +G2 0 M 3 0 500µ +R4 M 0 1K noiseless +G3 0 M 4 0 500µ +S1 X M 4 3 SD +A2 2 1 0 0 0 0 0 0 OTA g=0 in=1f ink=100 incm=.08f incmk=100 +C11 3 1 .9p Rpar=2e13 noiseless +C4 N004 0 5p Rpar=1K noiseless +L1 N004 N005 5µ +C6 N005 0 5p Rpar=1K noiseless +I3 3 4 50µ load +C2 3 N006 1p +C3 3 5 1p +C7 5 4 1p +C8 N006 4 1p +C5 1 4 .9p Rpar=2e13 noiseless +C10 2 4 .9p Rpar=2e13 noiseless +C12 3 2 .9p Rpar=2e13 noiseless +B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)+-.3, .1)+100n*V(1) +B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)-1.1,.1), V(4)+-.3, .1)+100n*V(2) +D3 3 4 IQ +I1 3 2 5p load +I2 3 1 5p load +D1 5 N006 A +.param Cf = 1p +.param Ro = 11K +.param Avol = 149K +.param RL = 2K +.param AVmid = 16 +.param FmidA = 1Meg +.param Zomid = .2 +.param FmidZ = 100K +.param Vslew = 25Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.param Gbx = Gb +.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless) +.model X2 D(Ron=1m Roff={2*Ro} Vfwd=-40m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model IQ D(Ron=1K Roff=10Meg epsilon=1 Ilimit=2.6m noiseless) +.model 1uA D(Ron=1Meg Vfwd=2 epsilon=1 Ilimit=1u noiseless) +.model A D(Ron=20 Roff=20 epsilon=10m Ilimit=80m revIlimit=60m Vrev=0 noiseless) +.ends AD823A +* +* +.subckt AD8510 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.01p ink=10 incm=.001p incmk=10 +C6 3 1 2.875p Rpar=62.5G noiseless +C1 2 1 6.25p noiseless +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N005 M 4 3 UVLO +D3 N005 3 X1 +D4 4 N005 X2 +D2 3 4 IQ +C7 1 4 2.875p Rpar=62.5G noiseless +C8 3 2 2.875p Rpar=62.5G noiseless +C9 2 4 2.875p Rpar=62.5G noiseless +I1 3 2 21p load +I2 3 1 21p load +A2 0 N006 M M M M N005 M OTA g=82u Iout=18u Isink=-28u en=7.55n enk=174.5 Vlow=-1e308 Vhigh=1e308 Cout= 1.3p asym +C10 N006 0 10p Rpar=1K noiseless +L1 N003 N006 10p +B1 N003 0 I=2m*dnlim(uplim(V(2),V(3)-(2.64-25m*V(3,4)),.1), V(4)+3.65-75m*V(3,4)-.01, .1)+100n*V(2) +B2 0 N003 I=2m*dnlim(uplim(V(1),V(3)-(2.65-25m*V(3,4)),.1), V(4)+3.65-75m*V(3,4), .1)+100n*V(1) +C5 N003 0 10p Rpar=1K noiseless +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C3 3 5 2p +C4 5 4 2p +C13 5 N004 5p Rser=1Meg noiseless +R5 N004 N005 1Meg +D1 5 N004 Y2A +D6 5 N004 Y2B +D9 N004 5 Y1 +.model X1 D(Ron=1K Roff=100G Vfwd=-0.8 epsilon=.1 noiseless) +.model X2 D(Ron=10 Roff=100G Vfwd=-0.12 epsilon=.1 noiseless) +.model Y1 D(Ron=18k Roff=100G Vfwd=650m epsilon=500m noiseless) +.model Y2A D(Ron=25k Roff=100G Vfwd=250m epsilon=500m noiseless) +.model Y2B D(Ron=5k Roff=100G Vfwd=450m epsilon=500m noiseless) +.model N VDMOS(Vto=-40m Kp=100m Ksubthres=100m noiseless) +.model P VDMOS(Vto=40m Kp=300m pchan Ksubthres=100m noiseless) +.model UVLO SW(Ron=1K Roff=3G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=0.08m noiseless) +.ends AD8510 +* + +* AD8515 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 1.8/5V, CMOS, OP, Low Pwr, RRIO, 1X +* Developed by: RM / ADSiv +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (07/2003) +* Copyright 2002, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8515 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=81.24E-6 +M2 6 2 8 8 PIX L=1E-6 W=81.24E-6 +M3 11 7 10 10 NIX L=1E-6 W=81.24E-6 +M4 12 2 10 10 NIX L=1E-6 W=81.24E-6 +RC1 4 14 0.001E+3 +RC2 6 16 0.001E+3 +RC3 17 11 0.001E+3 +RC4 18 12 0.001E+3 +RC5 14 50 10E+3 +RC6 16 50 10E+3 +RC7 99 17 10E+3 +RC8 99 18 10E+3 +*Set the secondary pole at 17MHz using c1,c2 and RC5.. +C1 14 16 0.70E-12 +C2 17 18 0.70E-12 +I1 99 8 60E-6 +I2 10 50 60E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-3 1 1 1 +IOS 1 2 1E-12 +* +* CMRR 75dB, ZERO AT 20kHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 281.170E+3 +CCM1 21 22 2.83E-11 +RCM2 22 98 50 +* +* PSRR=85dB, ZERO AT 200Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 795.774E+3 +CPS3 72 73 10.0E-9 +RPS4 73 98 44.74 +* +* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 22 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 4E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 17MHz, POLE AT 83.9MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .6270 .6270 +R2 32 33 2.378E+3 +R3 33 98 9.362E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 6.3E-5 +R1 30 98 1.48E+8 +CF 45 30 13.2E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=3.23E-3 +M6 45 47 50 50 NOX L=1E-6 W=3.58E-3 +EG1 99 46 POLY(1) (98,30) 0.4394 1 +EG2 47 50 POLY(1) (30,98) 0.4336 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8515 +* +*$ + + + + + +* AD8538 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 1X +* Developed by: ADISJ HH +* Revision History: 08/10/2012 - Updated to new header style +* 1.1 (10/2007) +* Copyright 2007, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8538 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=2.844E-05 +M2 16 2 8 8 PIX L=1E-6 W=2.844E-05 +M3 17 7 10 10 NIX L=1E-6 W=2.844E-05 +M4 18 2 10 10 NIX L=1E-6 W=2.844E-05 +RD1 14 50 2.667E+04 +RD2 16 50 2.667E+04 +RD3 99 17 2.667E+04 +RD4 99 18 2.667E+04 +C1 14 16 6.700E-12 +C2 17 18 6.700E-12 +I1 99 8 1.500E-05 +I2 10 50 1.500E-05 +V1 99 9 0.997E+00 +V2 13 50 0.997E+00 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(4) (22,98) (73,98) (83,98) (70,98) 5.00E-06 1 1 1.2 1 +IOS 1 2 1.00E-11 +* +*CMRR=135dB, POLE AT 9 Hz ZERO AT 2.5 MHz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 7.113E-02 7.113E-02 +R10 21 22 1.592E+04 +R20 22 98 1.989E-02 +C10 21 22 1.000E-06 +* +* PSRR=95dB, POLE AT 100 Hz +* +EPSY 72 98 POLY(1) (99,50) -8.89E-01 1.78E-00 +CPS3 72 73 1.00E-06 +RPS3 72 73 3.98E+04 +RPS4 73 98 3.98E-02 +* +* VOLTAGE NOISE REFERENCE OF 60nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-05 +* +HN 81 98 VN1 60E+00 +RNHH1 81 183 5.3 +CHH1 183 98 1uF +* +CHH2 183 184 2.7E-07 +RNHH2 184 98 10 +* +RNHH3 184 83 100k +CHH3 83 98 2.41E-10 +* +* FLICKER NOISE CORNER = 0.000001 Hz +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -242.5E-6 2.5E-06 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +G1 98 30 POLY(2) (14,16) (17,18) 0 2.678E-02 2.678E-02 +R1 30 98 1.00E+06 +V3 32 30 -3.603E-00 +V4 30 33 -3.733E-00 +EZ (145 0) (45 0) 1 +CF 145 31 4.400E-08 +RZ 30 31 3.800E+00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +M5 45 46 99 99 POX L=1E-6 W=2.238E-05 +M6 45 47 50 50 NOX L=1E-6 W=2.152E-05 +EG1 99 46 POLY(1) (98,30) 1.299E+00 1 +EG2 47 50 POLY(1) (30,98) 1.217E+00 1 +* +* MODELS +.MODEL POX PMOS (LEVEL=2,KP=6.00E-05,VTO=-0.6,LAMBDA=0.02,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=8.00E-05,VTO=+0.6,LAMBDA=0.02,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-0.5,LAMBDA=0.02) +.MODEL NIX NMOS (LEVEL=2,KP=5.00E-05,VTO=0.5, LAMBDA=0.02) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=2.50E-18) +* +.ENDS AD8538 +* +*$ + + + + + +* AD8539 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 2X +* Developed by: ADISJ HH +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/2010) +* Copyright 2007, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8539 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=2.844E-05 +M2 16 2 8 8 PIX L=1E-6 W=2.844E-05 +M3 17 7 10 10 NIX L=1E-6 W=2.844E-05 +M4 18 2 10 10 NIX L=1E-6 W=2.844E-05 +RD1 14 50 2.667E+04 +RD2 16 50 2.667E+04 +RD3 99 17 2.667E+04 +RD4 99 18 2.667E+04 +C1 14 16 6.700E-12 +C2 17 18 6.700E-12 +I1 99 8 1.500E-05 +I2 10 50 1.500E-05 +V1 99 9 0.997E+00 +V2 13 50 0.997E+00 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(4) (22,98) (73,98) (83,98) (70,98) 5.00E-06 1 1 1.2 1 +IOS 1 2 1.00E-11 +* +*CMRR=135dB, POLE AT 9 Hz ZERO AT 2.5 MHz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 7.113E-02 7.113E-02 +R10 21 22 1.592E+04 +R20 22 98 1.989E-02 +C10 21 22 1.000E-06 +* +* PSRR=95dB, POLE AT 100 Hz +* +EPSY 72 98 POLY(1) (99,50) -8.89E-01 1.78E-00 +CPS3 72 73 1.00E-06 +RPS3 72 73 3.98E+04 +RPS4 73 98 3.98E-02 +* +* VOLTAGE NOISE REFERENCE OF 60nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-05 +* +HN 81 98 VN1 60E+00 +RNHH1 81 183 5.3 +CHH1 183 98 1uF +* +CHH2 183 184 2.7E-07 +RNHH2 184 98 10 +* +RNHH3 184 83 100k +CHH3 83 98 2.41E-10 +* +* FLICKER NOISE CORNER = 0.000001 Hz +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -242.5E-6 2.5E-06 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +G1 98 30 POLY(2) (14,16) (17,18) 0 2.678E-02 2.678E-02 +R1 30 98 1.00E+06 +V3 32 30 -3.603E-00 +V4 30 33 -3.733E-00 +EZ (145 0) (45 0) 1 +CF 145 31 4.400E-08 +RZ 30 31 3.800E+00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +M5 45 46 99 99 POX L=1E-6 W=2.238E-05 +M6 45 47 50 50 NOX L=1E-6 W=2.152E-05 +EG1 99 46 POLY(1) (98,30) 1.299E+00 1 +EG2 47 50 POLY(1) (30,98) 1.217E+00 1 +* +* MODELS +.MODEL POX PMOS (LEVEL=2,KP=6.00E-05,VTO=-0.6,LAMBDA=0.02,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=8.00E-05,VTO=+0.6,LAMBDA=0.02,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-0.5,LAMBDA=0.02) +.MODEL NIX NMOS (LEVEL=2,KP=5.00E-05,VTO=0.5, LAMBDA=0.02) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=2.50E-18) +* +.ENDS AD8539 +* +*$ + + + + + +* AD8541 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Low Pwr, RRIO, 1X +* Developed by: TAM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (06/1998) +* Copyright 1998, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8541 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 1 8 8 PIX L=0.6E-6 W=16E-6 +M2 6 7 8 8 PIX L=0.6E-6 W=16E-6 +M3 11 1 10 10 NIX L=0.6E-6 W=16E-6 +M4 12 7 10 10 NIX L=0.6E-6 W=16E-6 +RC1 4 50 20E3 +RC2 6 50 20E3 +RC3 99 11 20E3 +RC4 99 12 20E3 +C1 4 6 1.5E-12 +C2 11 12 1.5E-12 +I1 99 8 1E-5 +I2 10 50 1E-5 +V1 99 9 0.2 +V2 13 50 0.2 +D1 8 9 DX +D2 13 10 DX +EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 64dB, ZERO AT 20kHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 79.6E3 +CCM1 21 22 100E-12 +RCM2 22 98 50 +* +* PSRR=90dB, ZERO AT 200Hz +* +RPS1 70 0 1E6 +RPS2 71 0 1E6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 1.59E6 +CPS3 72 73 500E-12 +RPS4 73 98 25 +* +* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz) +* +VN1 80 0 0 +RN1 80 0 16.45E-3 +HN 81 0 VN1 35 +RN2 81 0 1 +* +* INTERNAL VOLTAGE REFERENCE +* +VFIX 90 98 DC 1 +S1 90 91 (50,99) VSY_SWITCH +VSN1 91 92 DC 0 +RSY 92 98 1E3 +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 0 3.7E-6 +* +* ADAPTIVE GAIN STAGE +* AT Vsy>+4.2, AVol=45 V/mv +* AT Vsy<+3.8, AVol=450 V/mv +* +G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5 +VR1 30 31 DC 0 +H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9 +CF 45 30 10E-12 +D3 30 99 DX +D4 50 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=0.6E-6 W=375E-6 +M6 45 47 50 50 NOX L=0.6E-6 W=500E-6 +EG1 99 46 POLY(1) (98,30) 1.05 1 +EG2 47 50 POLY(1) (30,98) 1.04 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067) +.MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067) +.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31) +.MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31) +.MODEL DX D(IS=1E-14) +.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5) +.ENDS AD8541 + + + + + +* AD8542 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Low Pwr, RRIO, 2X +* Developed by: TAM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (06/1998) +* Copyright 1998, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8542 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 1 8 8 PIX L=0.6E-6 W=16E-6 +M2 6 7 8 8 PIX L=0.6E-6 W=16E-6 +M3 11 1 10 10 NIX L=0.6E-6 W=16E-6 +M4 12 7 10 10 NIX L=0.6E-6 W=16E-6 +RC1 4 50 20E3 +RC2 6 50 20E3 +RC3 99 11 20E3 +RC4 99 12 20E3 +C1 4 6 1.5E-12 +C2 11 12 1.5E-12 +I1 99 8 1E-5 +I2 10 50 1E-5 +V1 99 9 0.2 +V2 13 50 0.2 +D1 8 9 DX +D2 13 10 DX +EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 64dB, ZERO AT 20kHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 79.6E3 +CCM1 21 22 100E-12 +RCM2 22 98 50 +* +* PSRR=90dB, ZERO AT 200Hz +* +RPS1 70 0 1E6 +RPS2 71 0 1E6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 1.59E6 +CPS3 72 73 500E-12 +RPS4 73 98 25 +* +* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz) +* +VN1 80 0 0 +RN1 80 0 16.45E-3 +HN 81 0 VN1 35 +RN2 81 0 1 +* +* INTERNAL VOLTAGE REFERENCE +* +VFIX 90 98 DC 1 +S1 90 91 (50,99) VSY_SWITCH +VSN1 91 92 DC 0 +RSY 92 98 1E3 +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 0 3.7E-6 +* +* ADAPTIVE GAIN STAGE +* AT Vsy>+4.2, AVol=45 V/mv +* AT Vsy<+3.8, AVol=450 V/mv +* +G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5 +VR1 30 31 DC 0 +H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9 +CF 45 30 10E-12 +D3 30 99 DX +D4 50 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=0.6E-6 W=375E-6 +M6 45 47 50 50 NOX L=0.6E-6 W=500E-6 +EG1 99 46 POLY(1) (98,30) 1.05 1 +EG2 47 50 POLY(1) (30,98) 1.04 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067) +.MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067) +.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31) +.MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31) +.MODEL DX D(IS=1E-14) +.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5) +.ENDS AD8542 + + + + + +* AD8544 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Low Pwr, RRIO, 4X +* Developed by: TAM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (06/1998) +* Copyright 1998, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8544 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 1 8 8 PIX L=0.6E-6 W=16E-6 +M2 6 7 8 8 PIX L=0.6E-6 W=16E-6 +M3 11 1 10 10 NIX L=0.6E-6 W=16E-6 +M4 12 7 10 10 NIX L=0.6E-6 W=16E-6 +RC1 4 50 20E3 +RC2 6 50 20E3 +RC3 99 11 20E3 +RC4 99 12 20E3 +C1 4 6 1.5E-12 +C2 11 12 1.5E-12 +I1 99 8 1E-5 +I2 10 50 1E-5 +V1 99 9 0.2 +V2 13 50 0.2 +D1 8 9 DX +D2 13 10 DX +EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 64dB, ZERO AT 20kHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 79.6E3 +CCM1 21 22 100E-12 +RCM2 22 98 50 +* +* PSRR=90dB, ZERO AT 200Hz +* +RPS1 70 0 1E6 +RPS2 71 0 1E6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 1.59E6 +CPS3 72 73 500E-12 +RPS4 73 98 25 +* +* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz) +* +VN1 80 0 0 +RN1 80 0 16.45E-3 +HN 81 0 VN1 35 +RN2 81 0 1 +* +* INTERNAL VOLTAGE REFERENCE +* +VFIX 90 98 DC 1 +S1 90 91 (50,99) VSY_SWITCH +VSN1 91 92 DC 0 +RSY 92 98 1E3 +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 0 3.7E-6 +* +* ADAPTIVE GAIN STAGE +* AT Vsy>+4.2, AVol=45 V/mv +* AT Vsy<+3.8, AVol=450 V/mv +* +G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5 +VR1 30 31 DC 0 +H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9 +CF 45 30 10E-12 +D3 30 99 DX +D4 50 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=0.6E-6 W=375E-6 +M6 45 47 50 50 NOX L=0.6E-6 W=500E-6 +EG1 99 46 POLY(1) (98,30) 1.05 1 +EG2 47 50 POLY(1) (30,98) 1.04 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067) +.MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067) +.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31) +.MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31) +.MODEL DX D(IS=1E-14) +.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5) +.ENDS AD8544 + + + + + +* AD8546 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 3/18V, CMOS, OP, Low Pwr, RRIO, 2X +* Developed by: VW ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (01/2011) +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8546 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L= 1.000E-06 W= 1.532E-04 +M2 6 2 8 8 PIX L= 1.000E-06 W=1.532E-04 +M3 14 7 18 18 NIX L=1.000E-06 W=4.085E-04 +M4 16 2 18 18 NIX L=1.000E-06 W=4.085E-04 +RD1 4 50 2.0E+04 +RD2 6 50 2.0E+04 +RD3 99 14 2.0E+04 +RD4 99 16 2.0E+04 +C1 4 6 9.4750E-12 +C2 14 16 9.4750E-12 +I1 99 8 1.722E-05 +I2 18 50 1.722E-05 +V1 99 9 1.429E-01 +V2 19 50 1.429E-01 +D1 8 9 DX +D2 19 18 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 3E-03 1 1 1 1 +IOS 1 2 2.000E-11 +CDiff 1 2 3.5E-12 +Cin1 1 50 10.5E-12 +Cin2 2 50 10.5E-12 +* +* +* CMRR +* +E1 72 98 POLY(2) (1,98) (2,98) 0 6.817E-02 6.817E-02 +R10 72 73 2.894E+02 +R20 73 98 1.592E-02 +C10 72 73 1.000E-06 +* +* PSRR +* +EPSY 21 98 POLY(1) (99,50) -1.757E+02 9.762E+00 +RPS1 21 22 3.183E+03 +RPS2 22 98 7.958E-01 +CPS1 21 22 1.000E-06 +* +* VOLTAGE NOISE +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 4.5165E+01 +RN2 81 98 1 +* +* FLICKER NOISE +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.000E-03 1.000E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -1.74975E-05 5.031E-08 +EVP 97 98 POLY(1) (99,50) -1.05 0.25 +EVN 51 98 POLY(1) (50,99) 1.45 0.3 + +* +* GAIN STAGE +* +G1 98 30 POLY(2) (4,6) (14,16) 0 5.693E-05 5.693E-05 +R1 30 98 1.000E+06 +RZ 30 31 8.2720E+03 +CF 45 31 5.605E-10 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L= 2.000E-06 W=2.450E-04 +M6 45 47 50 50 NOX L= 2.000E-06 W=1.591E-04 +EG1 99 46 POLY(1) (98,30) 3.347E-01 1 +EG2 47 50 POLY(1) (30,98) 3.216E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.000E-05,VTO=-0.3,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=4.000E-05,VTO=+0.3,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=4.000E-05,VTO=-0.5,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=1.500E-05,VTO=0.5,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.5E-10) +* +* +.ENDS AD8546 +* +*$ + + + + + + +* AD8548 SPICE Macro-model Typical values at Vsy=18V +* Description: Amplifier +* Generic Desc: 2.7/18V, CMOS, RRIO +* Developed by: VW +* Revision History: +* 1.0 (8/2012) - VW - initial release +* Copyright 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html +* for License Statement. Use of this model indicates your acceptance +* of the terms and provisions in the License Statement. +* +* +* BEGIN Notes: +* +* Not Modeled: +* Temperature effects +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8548 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L= 1.000E-06 W= 1.532E-04 +M2 6 2 8 8 PIX L= 1.000E-06 W=1.532E-04 +M3 14 7 18 18 NIX L=1.000E-06 W=4.085E-04 +M4 16 2 18 18 NIX L=1.000E-06 W=4.085E-04 +RD1 4 50 2.0E+04 +RD2 6 50 2.0E+04 +RD3 99 14 2.0E+04 +RD4 99 16 2.0E+04 +C1 4 6 9.4750E-12 +C2 14 16 9.4750E-12 +I1 99 8 1.722E-05 +I2 18 50 1.722E-05 +V1 99 9 1.429E-01 +V2 19 50 1.429E-01 +D1 8 9 DX +D2 19 18 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 3E-03 1 1 1 1 +IOS 1 2 2.000E-11 +CDiff 1 2 3.5E-12 +Cin1 1 50 10.5E-12 +Cin2 2 50 10.5E-12 +* +* +* CMRR +* +E1 72 98 POLY(2) (1,98) (2,98) 0 6.817E-02 6.817E-02 +R10 72 73 2.894E+02 +R20 73 98 1.592E-02 +C10 72 73 1.000E-06 +* +* PSRR +* +EPSY 21 98 POLY(1) (99,50) -1.757E+02 9.762E+00 +RPS1 21 22 3.183E+03 +RPS2 22 98 7.958E-01 +CPS1 21 22 1.000E-06 +* +* VOLTAGE NOISE +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 4.5165E+01 +RN2 81 98 1 +* +* FLICKER NOISE +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.000E-03 1.000E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -1.74975E-05 5.031E-08 +EVP 97 98 POLY(1) (99,50) -1.05 0.25 +EVN 51 98 POLY(1) (50,99) 1.45 0.3 + +* +* GAIN STAGE +* +G1 98 30 POLY(2) (4,6) (14,16) 0 5.693E-05 5.693E-05 +R1 30 98 1.000E+06 +RZ 30 31 8.2720E+03 +CF 45 31 5.605E-10 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L= 2.000E-06 W=2.450E-04 +M6 45 47 50 50 NOX L= 2.000E-06 W=1.591E-04 +EG1 99 46 POLY(1) (98,30) 3.347E-01 1 +EG2 47 50 POLY(1) (30,98) 3.216E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.000E-05,VTO=-0.3,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=4.000E-05,VTO=+0.3,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=4.000E-05,VTO=-0.5,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=1.500E-05,VTO=0.5,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.5E-10) +* +* +.ENDS AD8548 +* +*$ + + +* AD8551 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 1X +* Developed by: TAM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/1999) +* Copyright 1999, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8551 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 +M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 +M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 +M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 +RC1 4 14 9E+3 +RC2 6 16 9E+3 +RC3 17 11 9E+3 +RC4 18 12 9E+3 +RC5 14 50 1E+3 +RC6 16 50 1E+3 +RC7 99 17 1E+3 +RC8 99 18 1E+3 +C1 14 16 30E-12 +C2 17 18 30E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 120dB, ZERO AT 20Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 50E+6 +CCM1 21 22 159E-12 +RCM2 22 98 50 +* +* PSRR=120dB, ZERO AT 1Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 15.9E+6 +CPS3 72 73 10E-9 +RPS4 73 98 16 +* +* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 45 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 7MHz, POLE AT 50MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 +R2 32 33 3.7E+3 +R3 33 98 22.74E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 22.7E-6 +R1 30 98 259.1E+6 +CF 45 30 45.4E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.111E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 +EG1 99 46 POLY(1) (98,30) 1.1936 1 +EG2 47 50 POLY(1) (30,98) 1.2324 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8551 + + + + + + +* AD8552 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 2X +* Developed by: TAM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/1999) +* Copyright 1999, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8552 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 +M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 +M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 +M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 +RC1 4 14 9E+3 +RC2 6 16 9E+3 +RC3 17 11 9E+3 +RC4 18 12 9E+3 +RC5 14 50 1E+3 +RC6 16 50 1E+3 +RC7 99 17 1E+3 +RC8 99 18 1E+3 +C1 14 16 30E-12 +C2 17 18 30E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 120dB, ZERO AT 20Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 50E+6 +CCM1 21 22 159E-12 +RCM2 22 98 50 +* +* PSRR=120dB, ZERO AT 1Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 15.9E+6 +CPS3 72 73 10E-9 +RPS4 73 98 16 +* +* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 45 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 7MHz, POLE AT 50MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 +R2 32 33 3.7E+3 +R3 33 98 22.74E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 22.7E-6 +R1 30 98 259.1E+6 +CF 45 30 45.4E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.111E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 +EG1 99 46 POLY(1) (98,30) 1.1936 1 +EG2 47 50 POLY(1) (30,98) 1.2324 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8552 + + + + + + +* AD8554 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 4X +* Developed by: TAM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/1999) +* Copyright 1999, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8554 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 +M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 +M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 +M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 +RC1 4 14 9E+3 +RC2 6 16 9E+3 +RC3 17 11 9E+3 +RC4 18 12 9E+3 +RC5 14 50 1E+3 +RC6 16 50 1E+3 +RC7 99 17 1E+3 +RC8 99 18 1E+3 +C1 14 16 30E-12 +C2 17 18 30E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 120dB, ZERO AT 20Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 50E+6 +CCM1 21 22 159E-12 +RCM2 22 98 50 +* +* PSRR=120dB, ZERO AT 1Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 15.9E+6 +CPS3 72 73 10E-9 +RPS4 73 98 16 +* +* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 45 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 7MHz, POLE AT 50MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 +R2 32 33 3.7E+3 +R3 33 98 22.74E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 22.7E-6 +R1 30 98 259.1E+6 +CF 45 30 45.4E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.111E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 +EG1 99 46 POLY(1) (98,30) 1.1936 1 +EG2 47 50 POLY(1) (30,98) 1.2324 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8554 + + + + + + +* AD8571 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 1X +* Developed by: TAM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (10/1999) +* Copyright 1999, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8571 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 +M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 +M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 +M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 +RC1 4 14 9E+3 +RC2 6 16 9E+3 +RC3 17 11 9E+3 +RC4 18 12 9E+3 +RC5 14 50 1E+3 +RC6 16 50 1E+3 +RC7 99 17 1E+3 +RC8 99 18 1E+3 +C1 14 16 30E-12 +C2 17 18 30E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 120dB, ZERO AT 20Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 50E+6 +CCM1 21 22 159E-12 +RCM2 22 98 50 +* +* PSRR=120dB, ZERO AT 1Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 15.9E+6 +CPS3 72 73 10E-9 +RPS4 73 98 16 +* +* VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 51 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 7MHz, POLE AT 50MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 +R2 32 33 3.7E+3 +R3 33 98 22.74E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 22.7E-6 +R1 30 98 259.1E+6 +CF 45 30 45.4E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.111E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 +EG1 99 46 POLY(1) (98,30) 1.1936 1 +EG2 47 50 POLY(1) (30,98) 1.2324 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8571 + + + + + + +* AD8572 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 2X +* Developed by: TAM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (10/1999) +* Copyright 1999, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8572 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 +M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 +M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 +M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 +RC1 4 14 9E+3 +RC2 6 16 9E+3 +RC3 17 11 9E+3 +RC4 18 12 9E+3 +RC5 14 50 1E+3 +RC6 16 50 1E+3 +RC7 99 17 1E+3 +RC8 99 18 1E+3 +C1 14 16 30E-12 +C2 17 18 30E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 120dB, ZERO AT 20Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 50E+6 +CCM1 21 22 159E-12 +RCM2 22 98 50 +* +* PSRR=120dB, ZERO AT 1Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 15.9E+6 +CPS3 72 73 10E-9 +RPS4 73 98 16 +* +* VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 51 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 7MHz, POLE AT 50MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 +R2 32 33 3.7E+3 +R3 33 98 22.74E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 22.7E-6 +R1 30 98 259.1E+6 +CF 45 30 45.4E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.111E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 +EG1 99 46 POLY(1) (98,30) 1.1936 1 +EG2 47 50 POLY(1) (30,98) 1.2324 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8572 + + + + + + +* AD8574 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 4X +* Developed by: TAM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (10/1999) +* Copyright 1999, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8574 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 +M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 +M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 +M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 +RC1 4 14 9E+3 +RC2 6 16 9E+3 +RC3 17 11 9E+3 +RC4 18 12 9E+3 +RC5 14 50 1E+3 +RC6 16 50 1E+3 +RC7 99 17 1E+3 +RC8 99 18 1E+3 +C1 14 16 30E-12 +C2 17 18 30E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 120dB, ZERO AT 20Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 50E+6 +CCM1 21 22 159E-12 +RCM2 22 98 50 +* +* PSRR=120dB, ZERO AT 1Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 15.9E+6 +CPS3 72 73 10E-9 +RPS4 73 98 16 +* +* VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 51 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 7MHz, POLE AT 50MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 +R2 32 33 3.7E+3 +R3 33 98 22.74E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 22.7E-6 +R1 30 98 259.1E+6 +CF 45 30 45.4E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.111E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 +EG1 99 46 POLY(1) (98,30) 1.1936 1 +EG2 47 50 POLY(1) (30,98) 1.2324 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-1,LAMBDA=0.001,RD=8) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+1,LAMBDA=0.001,RD=5) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8574 + + + + + +* AD8601 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Low Vos, RRIO, 1X +* Developed by: OEB / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (03/2000) +* Copyright 1999, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8601 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=982E-6 +M2 16 2 8 8 PIX L=1E-6 W=982E-6 +M3 17 7 10 10 NIX L=1E-6 W=982E-6 +M4 18 2 10 10 NIX L=1E-6 W=982E-6 +RC5 14 50 4E+3 +RC6 16 50 4E+3 +RC7 99 17 4E+3 +RC8 99 18 4E+3 +C1 14 16 0.6E-12 +C2 17 18 0.6E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 300E-6 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 90dB, ZERO AT 15kHz, POLE AT 2MHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 +CCM1 21 22 3.54E-10 +RCM1 21 22 30000 +RCM2 22 98 1 +* +* PSRR=100dB, ZERO AT 300Hz +* +EPSY 98 72 POLY(1) (99,50) 0 1 +CPS3 72 73 5.30E-9 +RPS3 72 73 100E+3 +RPS4 73 98 1 +* +* +* VOLTAGE NOISE REFERENCE OF 33nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 33 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 POLY(1) (99,50) -0.6 0.5 +EVN 51 98 POLY(1) (50,99) 0.6 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 375E-6 375E-6 +R1 30 98 2.53E+6 +CF 45 30 50E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.6E-3 +M6 45 47 50 50 NOX L=1E-6 W=3.33E-3 +EG1 99 46 POLY(1) (98,30) 0.5216 1 +EG2 47 50 POLY(1) (30,98) 0.4622 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3) +.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8601 +* +*$ + + + + + +* AD8602 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Low Vos, RRIO, 2X +* Developed by: OEB / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (03/2000) +* Copyright 1999, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8602 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=982E-6 +M2 16 2 8 8 PIX L=1E-6 W=982E-6 +M3 17 7 10 10 NIX L=1E-6 W=982E-6 +M4 18 2 10 10 NIX L=1E-6 W=982E-6 +RC5 14 50 4E+3 +RC6 16 50 4E+3 +RC7 99 17 4E+3 +RC8 99 18 4E+3 +C1 14 16 0.6E-12 +C2 17 18 0.6E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 300E-6 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 90dB, ZERO AT 15kHz, POLE AT 2MHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 +CCM1 21 22 3.54E-10 +RCM1 21 22 30000 +RCM2 22 98 1 +* +* PSRR=100dB, ZERO AT 300Hz +* +EPSY 98 72 POLY(1) (99,50) 0 1 +CPS3 72 73 5.30E-9 +RPS3 72 73 100E+3 +RPS4 73 98 1 +* +* +* VOLTAGE NOISE REFERENCE OF 33nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 33 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 POLY(1) (99,50) -0.6 0.5 +EVN 51 98 POLY(1) (50,99) 0.6 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 375E-6 375E-6 +R1 30 98 2.53E+6 +CF 45 30 50E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.6E-3 +M6 45 47 50 50 NOX L=1E-6 W=3.33E-3 +EG1 99 46 POLY(1) (98,30) 0.5216 1 +EG2 47 50 POLY(1) (30,98) 0.4622 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3) +.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8602 +* +*$ + + + + + +* AD8604 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Low Vos, RRIO, 4X +* Developed by: OEB / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/2010) - from AD8601-3/00v1 +* Copyright 1999, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8604 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=982E-6 +M2 16 2 8 8 PIX L=1E-6 W=982E-6 +M3 17 7 10 10 NIX L=1E-6 W=982E-6 +M4 18 2 10 10 NIX L=1E-6 W=982E-6 +RC5 14 50 4E+3 +RC6 16 50 4E+3 +RC7 99 17 4E+3 +RC8 99 18 4E+3 +C1 14 16 0.6E-12 +C2 17 18 0.6E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 300E-6 1 1 1 +IOS 1 2 2.5E-12 +* +* CMRR 90dB, ZERO AT 15kHz, POLE AT 2MHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 +CCM1 21 22 3.54E-10 +RCM1 21 22 30000 +RCM2 22 98 1 +* +* PSRR=100dB, ZERO AT 300Hz +* +EPSY 98 72 POLY(1) (99,50) 0 1 +CPS3 72 73 5.30E-9 +RPS3 72 73 100E+3 +RPS4 73 98 1 +* +* +* VOLTAGE NOISE REFERENCE OF 33nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 33 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 POLY(1) (99,50) -0.6 0.5 +EVN 51 98 POLY(1) (50,99) 0.6 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 375E-6 375E-6 +R1 30 98 2.53E+6 +CF 45 30 50E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.6E-3 +M6 45 47 50 50 NOX L=1E-6 W=3.33E-3 +EG1 99 46 POLY(1) (98,30) 0.5216 1 +EG2 47 50 POLY(1) (30,98) 0.4622 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3) +.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-31,AF=1,TOX=100E-3) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8604 +* +* + + + + + + +* AD8605 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Low Noise, RRIO, 1X +* Developed by: SB, ADSiV apps +* Revision History: +* 2.0 (05/2016) - Fixed flicker noise model - Emman.A (ADGT) +* 08/10/2012 - Updated to new header style +* 1.0 (05/2002) - from AD8601-3/00v1 +* Copyright 2002, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8605 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=1600E-6 +M2 16 2 8 8 PIX L=1E-6 W=1600E-6 +M3 17 7 10 10 NIX L=1E-6 W=1600E-6 +M4 18 2 10 10 NIX L=1E-6 W=1600E-6 +RC5 14 50 4E+3 +RC6 16 50 4E+3 +RC7 99 17 4E+3 +RC8 99 18 4E+3 +C1 14 16 0.6E-12 +C2 17 18 0.6E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 10E-6 1 1 1 +IOS 1 2 0.05E-12 +* +* CMRR 100dB, POLE AT 4.5KHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 +CCM1 21 22 3.54E-10 +RCM1 21 22 100E3 +RCM2 22 98 1 +* +* PSRR=95dB, ZERO AT 534Hz +* +EPSY 98 72 POLY(1) (99,50) 0 1 +CPS3 72 73 5.30E-9 +RPS3 72 73 56234 +RPS4 73 98 1 +* +* +* VOLTAGE NOISE REFERENCE OF 8nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 5.8 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 POLY(1) (99,50) -0.6 0.5 +EVN 51 98 POLY(1) (50,99) 0.6 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 56.3E-6 56.3E-6 +R1 30 98 5.43E8 +CF 45 30 9E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.08E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.61E-3 +EG1 99 46 POLY(1) (98,30) 0.4644 1 +EG2 47 50 POLY(1) (30,98) 0.4394 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3) +.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8605 +* +*$ + + + + + +* AD8606 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Low Noise, RRIO, 2X +* Developed by: ADSJ-HH +* Revision History: +* 2.0 (05/2016) - Fixed flicker noise model - Emman.A (ADGT) +* 08/10/2012 - Updated to new header style +* 1.0 (05/2002) - from AD8601-3/00v1 +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8606 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=1600E-6 +M2 16 2 8 8 PIX L=1E-6 W=1600E-6 +M3 17 7 10 10 NIX L=1E-6 W=1600E-6 +M4 18 2 10 10 NIX L=1E-6 W=1600E-6 +RC5 14 50 4E+3 +RC6 16 50 4E+3 +RC7 99 17 4E+3 +RC8 99 18 4E+3 +C1 14 16 0.6E-12 +C2 17 18 0.6E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 10E-6 1 1 1 +IOS 1 2 0.05E-12 +* +* CMRR 100dB, POLE AT 4.5KHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 +CCM1 21 22 3.54E-10 +RCM1 21 22 100E3 +RCM2 22 98 1 +* +* PSRR=95dB, ZERO AT 534Hz +* +EPSY 98 72 POLY(1) (99,50) 0 1 +CPS3 72 73 5.30E-9 +RPS3 72 73 56234 +RPS4 73 98 1 +* +* +* VOLTAGE NOISE REFERENCE OF 8nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 5.8 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 POLY(1) (99,50) -0.6 0.5 +EVN 51 98 POLY(1) (50,99) 0.6 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 56.3E-6 56.3E-6 +R1 30 98 5.43E8 +CF 45 30 9E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.08E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.61E-3 +EG1 99 46 POLY(1) (98,30) 0.4644 1 +EG2 47 50 POLY(1) (30,98) 0.4394 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3) +.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8606 +* +* + + + + +* AD8608 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Low Noise, RRIO, 4X +* Developed by: ADSJ HH +* Revision History: +* 2.0 (05/2016) - Fixed flicker noise model - Emman.A (ADGT) +* 08/10/2012 - Updated to new header style +* 0.0 (05/2002) - from AD8601-3/00v1 +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8608 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=1600E-6 +M2 16 2 8 8 PIX L=1E-6 W=1600E-6 +M3 17 7 10 10 NIX L=1E-6 W=1600E-6 +M4 18 2 10 10 NIX L=1E-6 W=1600E-6 +RC5 14 50 4E+3 +RC6 16 50 4E+3 +RC7 99 17 4E+3 +RC8 99 18 4E+3 +C1 14 16 0.6E-12 +C2 17 18 0.6E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 10E-6 1 1 1 +IOS 1 2 0.05E-12 +* +* CMRR 100dB, POLE AT 4.5KHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 +CCM1 21 22 3.54E-10 +RCM1 21 22 100E3 +RCM2 22 98 1 +* +* PSRR=95dB, ZERO AT 534Hz +* +EPSY 98 72 POLY(1) (99,50) 0 1 +CPS3 72 73 5.30E-9 +RPS3 72 73 56234 +RPS4 73 98 1 +* +* +* VOLTAGE NOISE REFERENCE OF 8nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 5.8 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 48E-6 +EVP 97 98 POLY(1) (99,50) -0.6 0.5 +EVN 51 98 POLY(1) (50,99) 0.6 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 56.3E-6 56.3E-6 +R1 30 98 5.43E8 +CF 45 30 9E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.08E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.61E-3 +EG1 99 46 POLY(1) (98,30) 0.4644 1 +EG2 47 50 POLY(1) (30,98) 0.4394 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3) +.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=0.045E-31,AF=1,TOX=100E-3) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8608 +* +* + + + + +* AD8614/AD8644 SPICE Macro-model +* Description: Amplifier +* Generic Desc: Single high-voltage LCD driver +* Developed by: Troy Murphy / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (11/1999) +* Copyright 1996, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8614 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* RAIL-TO-RAIL INPUT STAGE +* +Q1 5 7 3 PIX +Q2 6 2 4 PIX +Q3 11 7 13 NIX +Q4 12 2 14 NIX +RC1 5 50 2310 +RC2 6 50 2310 +RC3 99 11 2310 +RC4 99 12 2310 +RE1 3 10 620 +RE2 4 10 620 +RE3 13 15 620 +RE4 14 15 620 +I1 99 10 300E-6 +I2 15 50 300E-6 +RCM1 10 99 5.58E+5 +RCM2 15 50 5.58E+5 +CCM1 10 99 1.43E-11 +CCM2 15 50 1.43E-11 +C1 5 6 1.19E-12 +C2 11 12 1.19E-12 +D1 3 8 DX +D2 4 9 DX +D3 16 13 DX +D4 17 14 DX +V1 99 8 DC 0.7 +V2 99 9 DC 0.7 +V3 16 50 DC 0.7 +V4 17 50 DC 0.7 +EOS 7 1 POLY(2) (73,98) (81,98) 1E-3 1 1 +IOS 1 2 10E-9 +* +* PSRR=100dB, ZERO AT 100Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 15.9E+6 +CPS3 72 73 50E-12 +RPS4 73 98 159 +* +* VOLTAGE NOISE REFERENCE OF 10nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 10 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 41.121E-6 5E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (5,6) (11,12) 0 3.125E-4 3.125E-4 +R1 30 98 2.25E+6 +CF 30 45 49E-12 +D5 30 97 DX +D6 51 30 DX +* +* RAIL-TO-RAIL OUTPUT STAGE +* +Q5 45 41 99 POUT +Q6 45 43 50 NOUT +EB1 99 40 POLY(1) (98,30) 0.7129 1 +EB2 42 50 POLY(1) (30,98) 0.7129 1 +RB1 40 41 500 +RB2 42 43 500 +D7 46 99 DX +D8 47 43 DX +V5 46 41 0.5 +V6 47 50 0.5 +* +.MODEL NIX NPN (BF=220,IS=1E-16,VAF=130,KF=2.5E-14) +.MODEL PIX PNP (BF=220,IS=1E-16,VAF=130,KF=2.5E-14) +.MODEL POUT PNP (BF=100,IS=1E-16,VAF=200,RC=4) +.MODEL NOUT NPN (BF=100,IS=1E-16,VAF=200,RC=4) +.MODEL DX D(IS=1E-16,RS=5) +.ENDS AD8614 + + + + + + + + +* AD8618 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Fast, RRIO, 4X +* Developed by: Soufiane Bendaoud, ADSiV apps, TRW +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (05/2004) +* Copyright 2004, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: Typical Values at Vs=+/-2.5V +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8618 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=1580E-6 +M2 16 2 8 8 PIX L=1E-6 W=1580E-6 +M3 17 7 10 10 NIX L=1E-6 W=1580E-6 +M4 18 2 10 10 NIX L=1E-6 W=1580E-6 +RC5 14 50 4E+3 +RC6 16 50 4E+3 +RC7 99 17 4E+3 +RC8 99 18 4E+3 +C1 14 16 0.08E-12 +C2 17 18 0.08E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.2 +V2 13 50 0.2 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 27.326e-3 1 1 1 1 +IOS 1 2 0.05E-12 + +* +*CMRR=100dB, ZERO AT 1MHz +* + E1 21 98 POLY(2) (1,98) (2,98) 0 0.001255943 0.001255943 + R10 21 22 1.59E1 + R20 22 98 1.59E-1 + C10 21 22 1E-6 + +* +* PSRR=95dB, ZERO AT 534Hz +* +EPSY 98 72 POLY(1) (99,50) 0 0.5 +CPS3 72 73 1E-6 +RPS3 72 73 3.98E1 +RPS4 73 98 7.96E-3 +* +* +* VOLTAGE NOISE REFERENCE OF 8nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 7 +RN2 81 98 1 + +*flicker noise + +D5 69 98 DNOISE +VSN 69 98 DC .6551 +H1 70 98 VSN 25.3 +RN 70 98 1 + +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 240E-6 +EVP 97 98 POLY(1) (99,50) -0.6 0.5 +EVN 51 98 POLY(1) (50,99) 0.6 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 2.1E-4 2.1E-4 +R1 30 98 3.634E7 +CF 45 30 14E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=4.03E-3 +M6 45 47 50 50 NOX L=1E-6 W=4.03E-3 +EG1 99 46 POLY(1) (98,30) 0.45 1 +EG2 47 50 POLY(1) (30,98) 0.45 1 + + +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,TOX=100E-3) +.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,TOX=100E-3) +.MODEL DX D(IS=1E-14,RS=5,KF=1E-15) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=1E-15) + +.ENDS AD8618 +* + + + + + + + + +* AD8622/AD8624 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 5/30V, BIP, OP, Low Noise, RRO, 4X +* Developed by: VW ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (01/2010) +* Copyright 2009, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: VSY=5V, T=25degC +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8624 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +*INPUT STAGE +* +Q1 15 7 60 NIX +Q2 6 2 61 NIX +IOS 1 2 1.75E-11 +I1 5 50 50e-6 +EOS 7 1 POLY(4) (14,98) (73,98) (81,98) (70,98) 10E-6 1 1 1 1 +RC1 11 15 2.6E4 +RC2 11 6 2.6E4 +RE1 60 5 0.896E2 +RE2 61 5 0.896E2 +C1 15 6 6.25E-13 +D1 50 9 DX +V1 5 9 DC 0.3 +D10 99 10 DX +V6 10 11 0.3 +* +* CMRR +* +ECM 13 98 POLY(2) (1,98) (2,98) 0 7.192E-4 7.192E-4 +RCM1 13 14 2.15E2 +RCM2 14 98 5.31E-1 +CCM1 13 14 1E-6 +* +* PSRR +* +EPSY 72 98 POLY(1) (99,50) -1.683 0.056 +CPS3 72 73 1E-6 +RPS3 72 73 7.9577E+0 +RPS4 73 98 1.5915E-3 +* +* EXTRA POLE AND ZERO +* +G1 21 98 (6,15) 1E-6 +R1 21 98 1E6 +R2 21 22 7E5 +C2 22 98 1.7614E-12 +D3 21 99 DX +D4 50 21 DX +* +* VOLTAGE NOISE +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 7.98 +RN2 81 98 1 +* +* FLICKER NOISE +* +D5 69 98 DNOISE +VSN 69 98 DC .6551 +H1 70 98 VSN 40.85 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) -25E-6 1.7495E-8 +* +* GAIN STAGE +* +G2 98 25 (21,98) 1E-6 +R5 25 98 9.9E7 +CF 45 25 2.69E-12 +V4 25 33 5.3 +D7 51 33 DX +EVN 51 98 (50,99) 0.5 +V3 32 25 5.3 +D6 32 97 DX +EVP 97 98 (99,50) 0.5 +* +* OUTPUT STAGE +* +Q3 45 41 99 POUT +Q4 45 43 50 NOUT +RB1 40 41 7.25E4 +RB2 42 43 7.25E4 +EB1 99 40 POLY(1) (98,25) 0.7153 1 +EB2 42 50 POLY(1) (25,98) 0.7153 1 +* +* MODELS +* +.MODEL NIX NPN (BF=71429,IS=1E-16) +.MODEL POUT PNP (BF=200,VAF=50,BR=70,IS=1E-15,RC=71.25) +.MODEL NOUT NPN (BF=200,VAF=50,BR=22,IS=1E-15,RC=29.2) +.MODEL DX D(IS=1E-16, RS=5, KF=1E-15) +.MODEL DNOISE D(IS=1E-16,RS=0,KF=1.095E-14) + +.ENDS AD8624 + + + + + + +* AD8628 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 1X +* Developed by: RM / ADSiv +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (03/2002) +* Copyright 2002, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8628 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=174.1E-6 +M2 6 2 8 8 PIX L=1E-6 W=174.1E-6 +M3 11 7 10 10 NIX L=1E-6 W=174.1E-6 +M4 12 2 10 10 NIX L=1E-6 W=174.1E-6 +RC1 4 14 0.001E+3 +RC2 6 16 0.001E+3 +RC3 17 11 0.001E+3 +RC4 18 12 0.001E+3 +RC5 14 50 6E+3 +RC6 16 50 6E+3 +RC7 99 17 6E+3 +RC8 99 18 6E+3 +*Set teh secondary pole at 17MHz using c1,c2 and RC5.. +C1 14 16 5.40E-12 +C2 17 18 5.40E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 +IOS 1 2 25E-12 +* +* CMRR 120dB, ZERO AT 20Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 50E+6 +CCM1 21 22 159E-12 +RCM2 22 98 50 +* +* PSRR=115dB, ZERO AT 20Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 28.9E+6 +CPS3 72 73 .25E-9 +RPS4 73 98 40 +* +* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 20 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 44E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 17MHz, POLE AT 50.3MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .6689 .6689 +R2 32 33 3.164E+3 +R3 33 98 9.362E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 25E-6 +R1 30 98 2.46E+9 +CF 45 30 12.4E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.47E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.90E-3 +EG1 99 46 POLY(1) (98,30) 0.5303 1 +EG2 47 50 POLY(1) (30,98) 0.5058 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8628 +* +*$ + + + + + +* AD8629 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 2X +* Developed by: RM / ADSiv +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/2010) +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8629 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=174.1E-6 +M2 6 2 8 8 PIX L=1E-6 W=174.1E-6 +M3 11 7 10 10 NIX L=1E-6 W=174.1E-6 +M4 12 2 10 10 NIX L=1E-6 W=174.1E-6 +RC1 4 14 0.001E+3 +RC2 6 16 0.001E+3 +RC3 17 11 0.001E+3 +RC4 18 12 0.001E+3 +RC5 14 50 6E+3 +RC6 16 50 6E+3 +RC7 99 17 6E+3 +RC8 99 18 6E+3 +*Set teh secondary pole at 17MHz using c1,c2 and RC5.. +C1 14 16 5.40E-12 +C2 17 18 5.40E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 +IOS 1 2 25E-12 +* +* CMRR 120dB, ZERO AT 20Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 50E+6 +CCM1 21 22 159E-12 +RCM2 22 98 50 +* +* PSRR=115dB, ZERO AT 20Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 28.9E+6 +CPS3 72 73 .25E-9 +RPS4 73 98 40 +* +* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 20 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 44E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 17MHz, POLE AT 50.3MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .6689 .6689 +R2 32 33 3.164E+3 +R3 33 98 9.362E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 25E-6 +R1 30 98 2.46E+9 +CF 45 30 12.4E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.47E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.90E-3 +EG1 99 46 POLY(1) (98,30) 0.5303 1 +EG2 47 50 POLY(1) (30,98) 0.5058 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8629 +* + + + + + + + +* AD8630 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Zero Drift, RRIO, 4X +* Developed by: RM / ADSiv +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/2010) +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8630 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=174.1E-6 +M2 6 2 8 8 PIX L=1E-6 W=174.1E-6 +M3 11 7 10 10 NIX L=1E-6 W=174.1E-6 +M4 12 2 10 10 NIX L=1E-6 W=174.1E-6 +RC1 4 14 0.001E+3 +RC2 6 16 0.001E+3 +RC3 17 11 0.001E+3 +RC4 18 12 0.001E+3 +RC5 14 50 6E+3 +RC6 16 50 6E+3 +RC7 99 17 6E+3 +RC8 99 18 6E+3 +*Set teh secondary pole at 17MHz using c1,c2 and RC5.. +C1 14 16 5.40E-12 +C2 17 18 5.40E-12 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 99 9 0.3 +V2 13 50 0.3 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 1E-6 1 1 1 +IOS 1 2 25E-12 +* +* CMRR 120dB, ZERO AT 20Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 50E+6 +CCM1 21 22 159E-12 +RCM2 22 98 50 +* +* PSRR=115dB, ZERO AT 20Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 28.9E+6 +CPS3 72 73 .25E-9 +RPS4 73 98 40 +* +* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 20 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 44E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 17MHz, POLE AT 50.3MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .6689 .6689 +R2 32 33 3.164E+3 +R3 33 98 9.362E+3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 (33,98) 25E-6 +R1 30 98 2.46E+9 +CF 45 30 12.4E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.47E-3 +M6 45 47 50 50 NOX L=1E-6 W=1.90E-3 +EG1 99 46 POLY(1) (98,30) 0.5303 1 +EG2 47 50 POLY(1) (30,98) 0.5058 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=100E-6,VTO=-1,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=100E-6,VTO=+1,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8630 +* + + + + + + + +* AD8641 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 5/26V, JFET, OP, RRO, S SPLY, 1X +* Developed by: ADSJ-HH, Soufiane Bendaoud, ADSiV +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (12/2010) - Switched to NFETs, Corrected Zout, Vdo, GBW, Ibias +* 1.0 (12/2004) - Soufiane Bendaoud, ADSiV apps +* Copyright 2004, 2008, 2010, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* CAUTION!! To aid in convergence, most Spice simulators add a +* conductance on every node to insure that no node is floating. +* This is GMIN, and the default value is usually 1E-12. To properly +* simulate the low input bias current and low current noise, the +* Spice simulator options have to be set to the following: +* .OPTIONS GMIN=0.01p +* .OPTIONS ABSTOL=0.01pA +* +* Not Modeled: +* +* Parameters modeled include: +* This model simulates typical values at Vs=+/-13V +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8641 1 2 99 50 30 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +CIN 1 2 4.5E-12 +CCM1 1 50 3E-12 +CCM2 2 50 3E-12 +J1 5 7 4 JX; DGS +J2 6 2 4 JX; +R3 99 5 1.500E+04 +R4 99 6 1.500E+04 +CCOMP 5 6 6.35E-13 +I1 4 50 4.000E-05 +Vclamp 99 101 3.8 +Dclamp 4 101 DY +IOS 1 2 0.25E-12 +EOS 7 1 POLY(3) (142,0) (73,98) (22,98) 70E-6 1 1 1 +GB1 2 50 POLY(3) (4,2) (5,2) (50,2) -0.2E-12 2E-14 2E-14 2E-14 +GB2 7 50 POLY(3) (4,7) (6,7) (50,7) -0.3E-12 1E-14 1E-14 -0.2E-14 +* +EREF 98 0 24 0 1 +R14 24 99 500E3 +R15 24 50 500E3 +* +* SECOND STAGE +G1 9 98 (6,5) 5.022E-04 +R105 9 98 1.0E+06 +D1 9 8 DX +V2 8 98 0.085; +D2 10 9 DX +V3 10 98 -0.065; +RZ 451 453 1.95E+02 +CZ 453 9 1.33E-10 +* +* POLE AT 15 MHZ +* +R13 18 98 1E3 +C9 18 98 1.75E-16; -11 +G105 (18,98) (98,9) 1E-3 +* +* COMMON-MODE GAIN NETWORK +* +E1 72 98 POLY(2) (1 98) (2 98) 0 3.132E-03 3.132E-03 +R10 72 73 7.958E+01 +R20 73 98 6.366E-02 +C10 72 73 1.000E-06 +* +* PSRR +* +EPSY 98 21 POLY(1) (99,50) 3.646 1.402E-01 +RPS1 21 22 4.421E+05 +RPS2 22 98 1.989E+01 +CPS1 21 22 1.000E-09 +* +* VOLTAGE NOISE GENERATOR +* +VN1 141 0 DC 2 +DN1 141 142 DEN +DN2 142 143 DEN +VN2 0 143 DC 2 +* +* OUTPUT STAGE +* +Q3 451 41 99 POUT +RB1 40 41 1.5E+3 +EB1 99 40 POLY(1) (98, 18) 6.173E-01 1E-0; +Q4 451 43 50 NOUT +RB2 42 43 2.0E+3 +EB2 42 50 POLY(1) (18, 98) 6.08E-01 1E-0; +Lout 30 451 10E-14 +* +GSY 99 50 POLY(1) (99 50) 81.13E-6 1.632E-06 +* +* MODELS +* +.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130) +.MODEL POUT PNP (BF=70,IS=2.8E-15,VA=130); +.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=200); +.MODEL JX NJF(BETA=1.400E-03 VTO=-1.00 IS=2E-18 RD=1 ++ RS=1 CGD=3E-12 CGS=3E-12 lambda=7.0E-03) +.MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) +.MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) +.MODEL DEN D(IS=1E-12 RS=7.63E4, KF=9.665E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) +* +.ENDS AD8641 +* +$ + + + + + +* AD8642 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 5/26V, JFET, OP, RRO, S SPLY, 2X +* Developed by: ADSJ-HH, Soufiane Bendaoud, ADSiV +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (12/2010) - Switched to NFETs, Corrected Zout, Vdo, GBW, Ibias +* 1.0 (12/2004) - Soufiane Bendaoud, ADSiV apps +* Copyright 2004, 2008, 2010, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* CAUTION!! To aid in convergence, most Spice simulators add a +* conductance on every node to insure that no node is floating. +* This is GMIN, and the default value is usually 1E-12. To properly +* simulate the low input bias current and low current noise, the +* Spice simulator options have to be set to the following: +* .OPTIONS GMIN=0.01p +* .OPTIONS ABSTOL=0.01pA +* +* Not Modeled: +* +* Parameters modeled include: +* This model simulates typical values at Vs=+/-13V +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8642 1 2 99 50 30 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +CIN 1 2 4.5E-12 +CCM1 1 50 3E-12 +CCM2 2 50 3E-12 +J1 5 7 4 JX; DGS +J2 6 2 4 JX; +R3 99 5 1.500E+04 +R4 99 6 1.500E+04 +CCOMP 5 6 6.35E-13 +I1 4 50 4.000E-05 +Vclamp 99 101 3.8 +Dclamp 4 101 DY +IOS 1 2 0.25E-12 +EOS 7 1 POLY(3) (142,0) (73,98) (22,98) 70E-6 1 1 1 +GB1 2 50 POLY(3) (4,2) (5,2) (50,2) -0.2E-12 2E-14 2E-14 2E-14 +GB2 7 50 POLY(3) (4,7) (6,7) (50,7) -0.3E-12 1E-14 1E-14 -0.2E-14 +* +EREF 98 0 24 0 1 +R14 24 99 500E3 +R15 24 50 500E3 +* +* SECOND STAGE +G1 9 98 (6,5) 5.022E-04 +R105 9 98 1.0E+06 +D1 9 8 DX +V2 8 98 0.085; +D2 10 9 DX +V3 10 98 -0.065; +RZ 451 453 1.95E+02 +CZ 453 9 1.33E-10 +* +* POLE AT 15 MHZ +* +R13 18 98 1E3 +C9 18 98 1.75E-16; -11 +G105 (18,98) (98,9) 1E-3 +* +* COMMON-MODE GAIN NETWORK +* +E1 72 98 POLY(2) (1 98) (2 98) 0 3.132E-03 3.132E-03 +R10 72 73 7.958E+01 +R20 73 98 6.366E-02 +C10 72 73 1.000E-06 +* +* PSRR +* +EPSY 98 21 POLY(1) (99,50) 3.646 1.402E-01 +RPS1 21 22 4.421E+05 +RPS2 22 98 1.989E+01 +CPS1 21 22 1.000E-09 +* +* VOLTAGE NOISE GENERATOR +* +VN1 141 0 DC 2 +DN1 141 142 DEN +DN2 142 143 DEN +VN2 0 143 DC 2 +* +* OUTPUT STAGE +* +Q3 451 41 99 POUT +RB1 40 41 1.5E+3 +EB1 99 40 POLY(1) (98, 18) 6.173E-01 1E-0; +Q4 451 43 50 NOUT +RB2 42 43 2.0E+3 +EB2 42 50 POLY(1) (18, 98) 6.08E-01 1E-0; +Lout 30 451 10E-14 +* +GSY 99 50 POLY(1) (99 50) 81.13E-6 1.632E-06 +* +* MODELS +* +.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130) +.MODEL POUT PNP (BF=70,IS=2.8E-15,VA=130); +.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=200); +.MODEL JX NJF(BETA=1.400E-03 VTO=-1.00 IS=2E-18 RD=1 ++ RS=1 CGD=3E-12 CGS=3E-12 lambda=7.0E-03) +.MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) +.MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) +.MODEL DEN D(IS=1E-12 RS=7.63E4, KF=9.665E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) +* +.ENDS AD8642 +* +$ + + + + + +* AD8643 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 5/26V, JFET, OP, RRO, S SPLY, 4X +* Developed by: ADSJ-HH, Soufiane Bendaoud, ADSiV +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (12/2010) - Switched to NFETs, Corrected Zout, Vdo, GBW, Ibias +* 1.0 (12/2004) - Soufiane Bendaoud, ADSiV apps +* Copyright 2004, 2008, 2010, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* CAUTION!! To aid in convergence, most Spice simulators add a +* conductance on every node to insure that no node is floating. +* This is GMIN, and the default value is usually 1E-12. To properly +* simulate the low input bias current and low current noise, the +* Spice simulator options have to be set to the following: +* .OPTIONS GMIN=0.01p +* .OPTIONS ABSTOL=0.01pA +* +* Not Modeled: +* +* Parameters modeled include: +* This model simulates typical values at Vs=+/-13V +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8643 1 2 99 50 30 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +CIN 1 2 4.5E-12 +CCM1 1 50 3E-12 +CCM2 2 50 3E-12 +J1 5 7 4 JX; DGS +J2 6 2 4 JX; +R3 99 5 1.500E+04 +R4 99 6 1.500E+04 +CCOMP 5 6 6.35E-13 +I1 4 50 4.000E-05 +Vclamp 99 101 3.8 +Dclamp 4 101 DY +IOS 1 2 0.25E-12 +EOS 7 1 POLY(3) (142,0) (73,98) (22,98) 70E-6 1 1 1 +GB1 2 50 POLY(3) (4,2) (5,2) (50,2) -0.2E-12 2E-14 2E-14 2E-14 +GB2 7 50 POLY(3) (4,7) (6,7) (50,7) -0.3E-12 1E-14 1E-14 -0.2E-14 +* +EREF 98 0 24 0 1 +R14 24 99 500E3 +R15 24 50 500E3 +* +* SECOND STAGE +G1 9 98 (6,5) 5.022E-04 +R105 9 98 1.0E+06 +D1 9 8 DX +V2 8 98 0.085; +D2 10 9 DX +V3 10 98 -0.065; +RZ 451 453 1.95E+02 +CZ 453 9 1.33E-10 +* +* POLE AT 15 MHZ +* +R13 18 98 1E3 +C9 18 98 1.75E-16; -11 +G105 (18,98) (98,9) 1E-3 +* +* COMMON-MODE GAIN NETWORK +* +E1 72 98 POLY(2) (1 98) (2 98) 0 3.132E-03 3.132E-03 +R10 72 73 7.958E+01 +R20 73 98 6.366E-02 +C10 72 73 1.000E-06 +* +* PSRR +* +EPSY 98 21 POLY(1) (99,50) 3.646 1.402E-01 +RPS1 21 22 4.421E+05 +RPS2 22 98 1.989E+01 +CPS1 21 22 1.000E-09 +* +* VOLTAGE NOISE GENERATOR +* +VN1 141 0 DC 2 +DN1 141 142 DEN +DN2 142 143 DEN +VN2 0 143 DC 2 +* +* OUTPUT STAGE +* +Q3 451 41 99 POUT +RB1 40 41 1.5E+3 +EB1 99 40 POLY(1) (98, 18) 6.173E-01 1E-0; +Q4 451 43 50 NOUT +RB2 42 43 2.0E+3 +EB2 42 50 POLY(1) (18, 98) 6.08E-01 1E-0; +Lout 30 451 10E-14 +* +GSY 99 50 POLY(1) (99 50) 81.13E-6 1.632E-06 +* +* MODELS +* +.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130) +.MODEL POUT PNP (BF=70,IS=2.8E-15,VA=130); +.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=200); +.MODEL JX NJF(BETA=1.400E-03 VTO=-1.00 IS=2E-18 RD=1 ++ RS=1 CGD=3E-12 CGS=3E-12 lambda=7.0E-03) +.MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) +.MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) +.MODEL DEN D(IS=1E-12 RS=7.63E4, KF=9.665E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) +* +.ENDS AD8643 +* +$ + + + + + +* AD8648 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/5V, CMOS, OP, Fast, RRIO, 4X +* Developed by: HH-SJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 ( 07/2010) - Modify 1/f circuit +* 1.0 (04/2008) +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8648 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=2E-6 W=6.443E-03 +M2 6 2 8 8 PIX L=2E-6 W=6.443E-03 +M3 14 7 18 18 NIX L=2E-6 W=6.443E-03 +M4 16 2 18 18 NIX L=2E-6 W=6.443E-03 +RD1 4 50 1.818E+03 +RD2 6 50 1.818E+03 +RD3 99 14 1.818E+03 +RD4 99 16 1.818E+03 +C1 4 611 2.900E-13 +rcx1 611 6 3.8m +C2 14 1611 2.900E-13 +rcx2 1611 16 3.8m +I1 99 8 2.20E-04 +I2 18 50 2.20E-04 +V1 99 9 1.117E+00 +V2 19 50 1.117E+00 +D1 8 9 DX +D2 19 18 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 6.00E-04 1 1 1 1 +IOS 1 2 2.50E-11 +* +*CMRR=90dB, POLE AT 12000 Hz +* +E1 72 98 POLY(2) (1,98) (2,98) 0 9.438E-02 9.438E-02 +R10 72 73 1.326E+01 +R20 73 98 2.274E-03 +C10 72 73 1.000E-06 +* +* PSRR=80dB, POLE AT 7000 Hz +* +EPSY 21 98 POLY(1) (99,50) -14.865E+00 2.973E-00 +RPS1 21 22 4.301E+01 +RPS2 22 98 1.447E-03 +CPS1 21 22 1.000E-06 +* +* VOLTAGE NOISE REFERENCE OF 6nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 20.70E-3 +HN 81 98 VN1 6.20E+00 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 900 Hz +* +DFN 82 98 DNOISE 1000 +IFN 98 82 DC 1E-03 +DFN2 182 98 DY +IFN2 98 182 DC 1E-06 +GFN 83 98 POLY(1) (182,82) 1.00E-13 1.00E-01 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -308.0E-06 78.0E-06 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (4,6) (14,16) 0 4.574E-04 4.574E-04 +R1 30 98 1.00E+06 +CF 30 31 2.400E-11 +RZ 45 31 3.221E+01 +V3 32 30 1.108E+00 +V4 30 33 1.193E-00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 455 46 99 99 POX L=1E-6 W=6.079E-03 +M6 455 47 50 50 NOX L=1E-6 W=5.983E-03 +EG1 99 46 POLY(1) (98,30) 5.115E-01 1 +EG2 47 50 POLY(1) (30,98) 5.130E-01 1 +Lout 45 455 1nH +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.5,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=1.00E-05,VTO=0.5,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DY D(IS=1E-16,RS=0.1) +.MODEL DNOISE D(IS=1E-16,RS=0,KF=3.85E-12) +* +.ENDS AD8648 +* +*$ + + + + + +* AD8663 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 1X +* Developed by: HH - ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (04/2008) +* Copyright 2008, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: VSY=16V, T=25degC +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8663 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=2E-6 W=2.894E-04 +M2 6 2 8 8 PIX L=2E-6 W=2.894E-04 +RD1 4 50 5.333E+03 +RD2 6 50 5.333E+03 +C1 4 6 1.300E-11; +I1 99 8 75.00E-06 +V1 9 8 1.602E+00 +D1 9 99 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 1.10E-014 1 1 1 1 +IOS 1 2 5.00E-11 +* +* CMRR=87dB, POLE AT 14 kHz +* +E1 72 98 POLY(2) (1,98) (2,98) 0 4.786E-03 4.786E-03 +R10 72 73 1.137E+01 +R20 73 98 5.305E-02 +C10 72 73 1.00E-06 +* +* PSRR=95dB, POLE AT 200 Hz +* +EPSY 21 98 POLY(1) (99,50) -2.128+00 0.133E+00 +RPS1 21 22 1.061E+03 +RPS2 22 98 1.592E-01 +CPS1 21 22 1.000E-06 +* +* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 1.910E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 200 Hz +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -18.60E-06 1.110E-06 +* +* GAIN STAGE +* +G1 98 30 (4,6) 1.427E-03 +R1 30 98 1.000E+06 +CF 30 31 1.544E-09; 1.595E-9 +RZ 455 31 5.639E-00 +EZ 455 98 (45 98) 1 +EVP 32 98 POLY(1) (99,50) -1.10 +0.38E-00; +EVN 33 98 POLY(1) (50,99) +0.00 +0.45E-00; +D3a 30 32 DX +D4a 33 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=5.008E-05 +M6 45 47 50 50 NOX L=1E-6 W=1.099E-04 +EG1 99 46 POLY(1) (98,30) 7.607E-01 1 +EG2 47 50 POLY(1) (30,98) 6.201E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=3.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=3.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.449E-11) +* +* +.ENDS AD8663 +* +*$ + + + + + +* AD8667 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 2X +* Developed by: VW ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (04/2008) +* Copyright 2008, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: VSY=16V, T=25degC +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8667 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* +M1 4 7 8 8 PIX L=2E-6 W=5.371e-04 +M2 6 2 8 8 PIX L=2E-6 W=5.371E-04 +RD1 4 50 2.000E+04 +RD2 6 50 2.000E+04 +C1 4 6 2.84E-12 +I1 99 8 2.000E-05 +V1 9 8 1.614E+00 +D1 9 99 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 4.00E-05 1 1 1 1 +IOS 1 2 1.00E-13 +* +* +E1 72 98 POLY(2) (1,98) (2,98) 0 1.976E-02 1.976E-02 +R10 72 73 3.979E+01 +R20 73 98 3.183E-02 +C10 72 73 2.8E-7 +* +* +EPSY 21 98 POLY(1) (99,50) -14.226e+00 8.891E-01 +RPS1 21 22 7.96E+03 +RPS2 22 98 1.59E-01 +CPS1 21 22 1.00E-06 +* +* +VN1 80 98 0 +RN1 80 98 21.50E-3 +HN 81 98 VN1 1.924E+01 +RN2 81 98 1 +* +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) 5.8E-05 1.70E-7 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* +G1 98 30 (4,6) 3.641E-04 +R1 30 98 1.00E+07 +CF 30 31 3.86E-10 +Ez 31 98 45 98 1 +V3 32 30 3.104E+00 +V4 30 33 0.544E+00 +D3 32 97 DX +D4 51 33 DX +* +* +M5 45 46 99 99 POX L=2E-6 W=2.860E-04 +M6 45 47 50 50 NOX L=2E-6 W=6.473E-04 +EG1 99 46 POLY(1) (98,30) 7.386E-01 1 +EG2 47 50 POLY(1) (30,98) 6.010E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.100E-11) +* +* +.ENDS AD8667 +* +*$ + + + + + +* AD8669 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 4X +* Developed by: HH/ADI-SJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (10/2007) +* Copyright 2007, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8669 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=2.525E-03 +M2 16 2 8 8 PIX L=1E-6 W=2.525E-03 +RC5 14 50 2.00E+03 +RC6 16 50 2.00E+03 +C1 14 16 3.220E-11 +I1 99 8 2.000E-04 +V1 99 9 2.097E+00 +D1 8 9 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 3.00E-05 1 1 1 1 +IOS 1 2 1.00E-13 +* +* CMRR=114B, POLE AT 800 Hz +* +E1 21 98 POLY(2) (1,98) (2,98) 8.199E-03 8.199E-03 +R10 21 22 1.326E+02 +R20 22 98 3.183E-02 +C10 21 22 1.000E-06 +* +* PSRR=100dB, POLE AT 10 Hz +* +EPSY 72 98 POLY(1) (99,50) -111.596E+00 6.975E+00 +RPS3 72 73 2.468E+04 +RPS4 73 98 1.989E-02 +CPS3 72 73 1.000E-06 +* +* VOLTAGE NOISE REFERENCE OF 20.7nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 17.04E-3 +HN 81 98 VN1 2.07E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 90 Hz +* +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -0.1298E-03 9.0E-07 +EVP 97 98 POLY(1) (99,50) 0 0.5E-09 +EVN 51 98 POLY(1) (50,99) 0 0.5E-09 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (14,16) 0 1.286E-02 +R1 30 98 1.00E+06 +V3 32 30 -4.108E+00 +V4 30 33 -6.421E+00 +EZ (145 0) (45 0) 1 +CF 145 31 1.270E-08 +RZ 30 31 0.100E+00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.673E-04 +M6 45 47 50 50 NOX L=1E-6 W=3.762E-04 +EG1 99 46 POLY(1) (98,30) 7.233E-01 1 +EG2 47 50 POLY(1) (30,98) 5.916E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0.1) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0.1) +.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.53E-11) +* +* +.ENDS AD8669 +* +*$ + + + + + +* AD8671 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 10/30V, BIP, OP, Low Noise, Low Ib, 1X +* Developed by: HH/ADI-SJ, Soufiane Bendaoud ADI Silicon valley +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (12/2009) - Corrected unpowered Ibais, PM, PSRR, IVR. Changed noise gen, +* Added input C. +* 1.0 ( 07/2003) +* Copyright 2003, 2009, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* This model simulates typical values at Vs=+/-15V +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8671 1 2 99 50 39 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +R3 5 99 2.033E+04 +R4 6 99 2.033E+04 +CIN 1 2 7.45E-12 +CCM1 1 50 6.25E-12 +CCM2 2 50 6.25E-12 +RC 5 56 5.3E+03 +CC 56 6 2.14E-13 +I1 4 50 300E-06 +VI1 450 50 2.7 +DI1 450 4 DX +IOS 1 2 3E-9 +EOS 9 1 POLY(4) (31 98) (81 98) (83 98) (73 98) 20E-6 1 1 1 1 +Q1 5 2 4 QINN +Q2 6 9 4 QINN +D1 2 1 DX +D2 1 2 DX +GN1 50 2 (60 61) 1.453E-05 +GN2 50 1 (62 63) 1.453E-05 +* +* GAIN STAGE +* +R7 20 98 1.652E+05 +C3 20 98 5.61E-07 +G1 98 20 (5 6) 3.603E-01 +EV1 98 21 POLY(1) (99 98) -2.0E0 10E-1 +EV2 22 98 POLY(1) (98 50) -2.3E0 10E-1 +D5 21 20 DX +D6 20 22 DX +EPLUS 97 0 99 0 1 +ENEG 51 0 50 0 1 +Rtemp1 97 51 1meg +* +* COMMON-MODE GAIN NETWORK +* +E5 30 98 POLY(2) (2 50) (1 50) 0 4.196E-03 4.196E-03 +RCM1 30 31 1.061E+03 +RCM2 31 98 1.592E-01 +CCM 30 31 1.000E-06 +* +* PSRR NETWORK +* +EPSY 98 72 POLY(1) (99,50) 3.350E-03 9.375E-01 +CPS3 72 73 1.000E-06 +RPS3 72 73 9.947E+02 +RPS4 73 98 1.061E-02 +* +* VOLTAGE NOISE REFERENCE OF 2.8nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 26.34E-3 +HN 81 98 VN1 2.80E+00 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.65520 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +D60 60 0 DIN1 1000 +I60 0 60 1m +D61 61 0 DIN1 +I61 0 61 1u +* +* SECOND CURRENT NOISE SOURCE +* +D62 62 0 DIN1 +I62 0 62 1u +D63 63 0 DIN1 +I63 0 63 1u +* +R17 33 99 1meg +R18 33 50 1meg +C178 33 50 1E-06 +C188 33 99 1E-06 +EREF 98 0 33 0 1 +* +GSY 99 50 POLY(1) 99 50 2.24E-3 15E-6 +* +* OUTPUT STAGE +* +R19 34 99 100 +R20 34 50 100 +G9 34 99 99 20 1.000E-02 +G10 50 34 20 50 1.000E-02 +* +V3 35 34 0.65 +D9 20 35 DX +V4 34 36 0.52; +D10 36 20 DX +* +G7 37 50 20 34 1.0E-2 +G8 38 50 34 20 1.0E-2 +D11 99 37 DX +D12 99 38 DX +D13 50 37 DY +D14 50 38 DY +* +F1 34 0 V3 1 +F2 0 34 V4 1 +* +L3 34 39 1E-8; 39 is output pin +* +* MODELS USED +* +.MODEL QINN NPN(BF=3.0E4, VA=130) +.MODEL DX D(IS=1E-15, RS=1m) +.MODEL DY D(IS=1E-15 BV=50) +.MODEL DEN D(IS=1E-12, RS=4.0E+2, KF=1.08E-16, AF=1) +.MODEL DNOISE D(IS=1E-14,RS=1E-1,KF=3.14E-14) +.MODEL DIN D(IS=1E-18, RS=1.0E-6, KF=1.82E-14, AF=1) +.MODEL DIN1 D(IS=1E-16, RS=1.0E-0, KF=3.7E-16, AF=1) +.ENDS AD8671 +*$ + + + + + +* AD8672 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 10/30V, BIP, OP, Low Noise, Low Ib, 2X +* Developed by: HH/ADI-SJ, Soufiane Bendaoud ADI Silicon valley +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (12/2009) - Corrected unpowered Ibais, PM, PSRR, IVR. Changed noise gen, +* Added input C. +* 1.0 ( 07/2003) +* Copyright 2003, 2009, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* This model simulates typical values at Vs=+/-15V +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8672 1 2 99 50 39 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +R3 5 99 2.033E+04 +R4 6 99 2.033E+04 +CIN 1 2 7.45E-12 +CCM1 1 50 6.25E-12 +CCM2 2 50 6.25E-12 +RC 5 56 5.3E+03 +CC 56 6 2.14E-13 +I1 4 50 300E-06 +VI1 450 50 2.7 +DI1 450 4 DX +IOS 1 2 3E-9 +EOS 9 1 POLY(4) (31 98) (81 98) (83 98) (73 98) 20E-6 1 1 1 1 +Q1 5 2 4 QINN +Q2 6 9 4 QINN +D1 2 1 DX +D2 1 2 DX +GN1 50 2 (60 61) 1.453E-05 +GN2 50 1 (62 63) 1.453E-05 +* +* GAIN STAGE +* +R7 20 98 1.652E+05 +C3 20 98 5.61E-07 +G1 98 20 (5 6) 3.603E-01 +EV1 98 21 POLY(1) (99 98) -2.0E0 10E-1 +EV2 22 98 POLY(1) (98 50) -2.3E0 10E-1 +D5 21 20 DX +D6 20 22 DX +EPLUS 97 0 99 0 1 +ENEG 51 0 50 0 1 +Rtemp1 97 51 1meg +* +* COMMON-MODE GAIN NETWORK +* +E5 30 98 POLY(2) (2 50) (1 50) 0 4.196E-03 4.196E-03 +RCM1 30 31 1.061E+03 +RCM2 31 98 1.592E-01 +CCM 30 31 1.000E-06 +* +* PSRR NETWORK +* +EPSY 98 72 POLY(1) (99,50) 3.350E-03 9.375E-01 +CPS3 72 73 1.000E-06 +RPS3 72 73 9.947E+02 +RPS4 73 98 1.061E-02 +* +* VOLTAGE NOISE REFERENCE OF 2.8nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 26.34E-3 +HN 81 98 VN1 2.80E+00 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.65520 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +D60 60 0 DIN1 1000 +I60 0 60 1m +D61 61 0 DIN1 +I61 0 61 1u +* +* SECOND CURRENT NOISE SOURCE +* +D62 62 0 DIN1 +I62 0 62 1u +D63 63 0 DIN1 +I63 0 63 1u +* +R17 33 99 1meg +R18 33 50 1meg +C178 33 50 1E-06 +C188 33 99 1E-06 +EREF 98 0 33 0 1 +* +GSY 99 50 POLY(1) 99 50 2.24E-3 15E-6 +* +* OUTPUT STAGE +* +R19 34 99 100 +R20 34 50 100 +G9 34 99 99 20 1.000E-02 +G10 50 34 20 50 1.000E-02 +* +V3 35 34 0.65 +D9 20 35 DX +V4 34 36 0.52; +D10 36 20 DX +* +G7 37 50 20 34 1.0E-2 +G8 38 50 34 20 1.0E-2 +D11 99 37 DX +D12 99 38 DX +D13 50 37 DY +D14 50 38 DY +* +F1 34 0 V3 1 +F2 0 34 V4 1 +* +L3 34 39 1E-8; 39 is output pin +* +* MODELS USED +* +.MODEL QINN NPN(BF=3.0E4, VA=130) +.MODEL DX D(IS=1E-15, RS=1m Cjo=10f) +.MODEL DY D(IS=1E-15 BV=50 Cjo=10f) +.MODEL DEN D(IS=1E-12, RS=4.0E+2, KF=1.08E-16, AF=1 Cjo=10f) +.MODEL DNOISE D(IS=1E-14,RS=1E-1,KF=3.14E-14) +.MODEL DIN D(IS=1E-18, RS=1.0E-6, KF=1.82E-14, AF=1) +.MODEL DIN1 D(IS=1E-16, RS=1.0E-0, KF=3.7E-16, AF=1) +.ENDS AD8672 +*$ + + + + + +* AD8674 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 10/30V, BIP, OP, Low Noise, Low Ib, 4X +* Developed by: HH/ADI-SJ, Soufiane Bendaoud ADI Silicon valley +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (12/2009) - Corrected unpowered Ibais, PM, PSRR, IVR. Changed noise gen, +* Added input C. +* 1.0 ( 07/2003) +* Copyright 2003, 2009, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* This model simulates typical values at Vs=+/-15V +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8674 1 2 99 50 39 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +R3 5 99 2.033E+04 +R4 6 99 2.033E+04 +CIN 1 2 7.45E-12 +CCM1 1 50 6.25E-12 +CCM2 2 50 6.25E-12 +RC 5 56 5.3E+03 +CC 56 6 2.14E-13 +I1 4 50 300E-06 +VI1 450 50 2.7 +DI1 450 4 DX +IOS 1 2 3E-9 +EOS 9 1 POLY(4) (31 98) (81 98) (83 98) (73 98) 20E-6 1 1 1 1 +Q1 5 2 4 QINN +Q2 6 9 4 QINN +D1 2 1 DX +D2 1 2 DX +GN1 50 2 (60 61) 1.453E-05 +GN2 50 1 (62 63) 1.453E-05 +* +* GAIN STAGE +* +R7 20 98 1.652E+05 +C3 20 98 5.61E-07 +G1 98 20 (5 6) 3.603E-01 +EV1 98 21 POLY(1) (99 98) -2.0E0 10E-1 +EV2 22 98 POLY(1) (98 50) -2.3E0 10E-1 +D5 21 20 DX +D6 20 22 DX +EPLUS 97 0 99 0 1 +ENEG 51 0 50 0 1 +Rtemp1 97 51 1meg +* +* COMMON-MODE GAIN NETWORK +* +E5 30 98 POLY(2) (2 50) (1 50) 0 4.196E-03 4.196E-03 +RCM1 30 31 1.061E+03 +RCM2 31 98 1.592E-01 +CCM 30 31 1.000E-06 +* +* PSRR NETWORK +* +EPSY 98 72 POLY(1) (99,50) 3.350E-03 9.375E-01 +CPS3 72 73 1.000E-06 +RPS3 72 73 9.947E+02 +RPS4 73 98 1.061E-02 +* +* VOLTAGE NOISE REFERENCE OF 2.8nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 26.34E-3 +HN 81 98 VN1 2.80E+00 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.65520 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +D60 60 0 DIN1 1000 +I60 0 60 1m +D61 61 0 DIN1 +I61 0 61 1u +* +* SECOND CURRENT NOISE SOURCE +* +D62 62 0 DIN1 +I62 0 62 1u +D63 63 0 DIN1 +I63 0 63 1u +* +R17 33 99 1meg +R18 33 50 1meg +C178 33 50 1E-06 +C188 33 99 1E-06 +EREF 98 0 33 0 1 +* +GSY 99 50 POLY(1) 99 50 2.24E-3 15E-6 +* +* OUTPUT STAGE +* +R19 34 99 100 +R20 34 50 100 +G9 34 99 99 20 1.000E-02 +G10 50 34 20 50 1.000E-02 +* +V3 35 34 0.65 +D9 20 35 DX +V4 34 36 0.52; +D10 36 20 DX +* +G7 37 50 20 34 1.0E-2 +G8 38 50 34 20 1.0E-2 +D11 99 37 DX +D12 99 38 DX +D13 50 37 DY +D14 50 38 DY +* +F1 34 0 V3 1 +F2 0 34 V4 1 +* +L3 34 39 1E-8; 39 is output pin +* +* MODELS USED +* +.MODEL QINN NPN(BF=3.0E4, VA=130) +.MODEL DX D(IS=1E-15, RS=1m) +.MODEL DY D(IS=1E-15 BV=50) +.MODEL DEN D(IS=1E-12, RS=4.0E+2, KF=1.08E-16, AF=1) +.MODEL DNOISE D(IS=1E-14,RS=1E-1,KF=3.14E-14) +.MODEL DIN D(IS=1E-18, RS=1.0E-6, KF=1.82E-14, AF=1) +.MODEL DIN1 D(IS=1E-16, RS=1.0E-0, KF=3.7E-16, AF=1) +.ENDS AD8674 +* +.subckt AD8675 1 2 3 4 5 +C1 N006 N005 {Cf} +A1 N009 0 N010 N010 N010 N010 N005 N010 OTA g={Ga} Iout={Islew} en=2.8n enk=4.5 Vhigh=1e308 Vlow=-1e308 +D5 N006 3 X1 +D6 4 N006 X2 +G2 0 N010 3 0 500µ +R4 N010 0 1K noiseless +G3 0 N010 4 0 500µ +S1 N005 N010 4 3 SD +C4 N004 0 {5p*x} Rpar=1K noiseless +C11 3 2 .95p Rpar=1T noiseless +C18 2 1 8.65p Rpar=1T noiseless +D8 3 1 1nA m=.5 +C3 3 5 .25p +C7 5 4 .25p +A2 2 1 0 0 0 0 0 0 OTA g=0 in=.1p ink=1.5K incm=.1p incmk=1.5k +Ö1 N006 3 4 N005 N010 Gm1={Gb} Ibias=2.3m +C2 2 4 .95p Rpar=1T noiseless +C5 3 1 .95p Rpar=1T noiseless +C6 1 4 .95p Rpar=1T noiseless +D1 3 2 1nA m=.5 +B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)-2,.1), V(4)+2, .1)+100n*V(2) +B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)-2,.1), V(4)+2, .1)+100n*V(1) +D3 N005 N010 IO +R5 5 N006 22 +L1 N004 N007 {5µ*x} +L2 N008 N009 {5µ*x} +C10 N009 0 {5p*x} Rpar=1K noiseless +C8 N007 0 {10p*x} +L3 N007 N008 {5µ*x} +C12 N008 0 {10p*x} +.param Cf = 6p +.param Ro = 5K +.param Avol = 4Meg +.param RL = 2K +.param AVmid = 10 +.param FmidA = 1Meg +.param Zomid = 5 +.param FmidZ = 1Meg +.param Vslew = 2.5Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.model X1 D(Ron=1m Roff=1G Vfwd=0 epsilon=10m noiseless) +.model X2 D(Ron=1m Roff=1G Vfwd=20m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model 1nA D(Ron=500Meg epsilon=.5 Ilimit=1n noiseless) +.model IO D(Ron=2K Roff=1T Vfwd={32m/Gb} Vrev={32m/Gb} revepsilon=.1 epsilon=.1 noiseless) +.param X=.6 +.ends AD8675 +* +* Robert Ritchie +.subckt AD8691 1 2 3 4 5 +M1 14A 7A 8A 8A PIXN temp=27 +RC5 14A 4 8.00E+02 noiseless +C1 14A 16A 6.29E-12 +IOS 1 2 5.00E-14 +R1 30A 0 1.00E+06 noiseless +CF N004 30A 1.34E-09 Rser=3.5 noiseless +M5 5 46A 3 3 POXN temp=27 +M6 5 47A 4 4 NOXN temp=27 +E2 N004 0 5 Mid 1 +R4 22A 0 15.9 noiseless +C2 N008 22A 10n Rpar=2.59K noiseless +R5 N008 0 1 noiseless +B1 N008 0 V=1.58m*(V(1)+V(2)-V(3)-V(4)) +R6 73A 0 15.9 noiseless +C3 N007 73A 10n Rpar=3.98K noiseless +B2 N007 0 V=-70.3m+14.1m*V(3,4) +RC1 16A 4 8.00E+02 noiseless +A1 0 0 1 1 1 1 7A 1 OTA g=.1 linear Rout=10 en=8.3n enk=280 vlow=-1e308 vhigh=1e308 +I2 1 7A 40µ +G2 1 7A 22A 0 100m +G3 1 7A 73A 0 100m +R7 N007 0 1 noiseless +G4 46A 3 0 30A 1 +R8 3 46A 1 noiseless +I3 46A 3 602.3m +R9 47A 4 1 noiseless +I4 4 47A 533.7m +G5 4 47A 30A 0 1 +R10 3 Mid 20K noiseless +R11 Mid 4 20K noiseless +D1 3 8A Dptail +M2 16A 2 8A 8A PIXN temp=27 +B3 0 30A I=16.7m*V(14A,16A)*(.5+.5*tanh(V(30A,Limlow)/100m))*(.5+.5*tanh(V(Limhigh,30A)/100m)) +G1 0 Limhigh 3 4 .5m +I1 Limhigh 0 729µ +G6 0 Limhigh 14A 16A 90µ +R12 Limhigh 0 1K noiseless +G7 0 Limlow 4 3 .5m +R13 Limlow 0 1K noiseless +I5 Limlow 0 7µ +G8 0 Limlow 14A 16A 90µ +B4 4 3 I=332u*(.5+.5*tanh((V(3,4)-300m)/120m)) +.model PIXN VDMOS(Vto=-.5 Kp=112m lambda=10m Cgs=100f pchan noiseless) +.model NOXN VDMOS(Vto=.328 Kp=27.8m lambda=10m) +.model POXN VDMOS(Vto=-.328 Kp=15.6m Lambda=10m pchan) +.model Dptail D(Ron=100 Roff=1G vfwd=.52 epsilon=100m ilimit=500u noiseless) +.ends AD8691 +* +.subckt ADA4000 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.01p ink=10 incm=.001p incmk=10 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 2p +C4 5 4 2p +A2 0 N004 M M M M N005 M OTA g=118u Isrc=90u Isink=-110u en=16n enk=100 Vlow=-1e308 Vhigh=1e308 Cout= 3.15p asym +C10 N004 0 16.45p Rpar=1K noiseless +D1 N005 5 Y +D6 5 N005 Y +C1 2 1 2.625p Rpar=10.1G noiseless +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N005 M 4 3 UVLO +D3 N005 3 X1 +D4 4 N005 X2 +D2 3 4 IQ +I1 1 4 5p load +I2 2 4 5p load +B1 N004 0 I=1m*dnlim(uplim(V(2),V(3)-0,.1), V(4)+4, .1)+100n*V(2) +B2 0 N004 I=1m*dnlim(uplim(V(1),V(3)-1,.1), V(4)+3.5, .1)+100n*V(1) +C6 3 2 1.375p Rpar=4T noiseless +C2 2 4 1.375p Rpar=4T noiseless +C5 3 1 1.375p Rpar=4T noiseless +C7 1 4 1.375p Rpar=4T noiseless +.model X1 D(Ron=2K Roff=100G Vfwd=-.82 epsilon=.1 noiseless) +.model X2 D(Ron=2K Roff=100G Vfwd=-1.27 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=1.2 epsilon=.1 noiseless) +.model N VDMOS(Vto=-250m Kp=24m Ksubthres=.2 noiseless) +.model P VDMOS(Vto=250m Kp=24m pchan Ksubthres=.2 noiseless) +.model UVLO SW(Ron=1K Roff=5G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=.35m noiseless) +.ends ADA4000 +* +* ADA4051 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 1.8/5V, CMOS, OP, Zero Drift, RRIO, 2X +* Developed by: HH/ADSJ, GEC/ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (07/2010) - Modified for 1.8 to 5V Vsy +* 1.0 (11/2009) +* Copyright 2009, 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: Typical Values at Vsy=5V, Ta=25degC +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT ADA4051 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=2E-6 W=2.321E-04; ** D G S +M2 6 2 8 8 PIX L=2E-6 W=2.321E-04 +M3 14 7 18 18 NIX L=2E-6 W=8.911E-05 +M4 16 2 18 18 NIX L=2E-6 W=8.911E-05 +Cincmp 1 50 5E-12 +Cincmn 2 50 5E-12 +Cindm 1 2 2E-12 +RD1 4 50 2E+05 +RD2 6 50 2E+05 +RD3 99 14 2E+05 +RD4 99 16 2E+05 +C1 4 6 3.361E-12 +C2 14 16 3.361E-12 +I1 99 8 2E-06 +I2 18 50 2E-06 +V1 99 9 0.166E+00 +D1 8 9 DX +V2 19 50 0.157E+00 +D2 19 18 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 2.00E-06 1 1 1 1 +IOS 1 2 2.00E-11 +* +*CMRR +* +E1 72 98 POLY(2) (1,98) (2,98) 0 4.708E-04 4.708E-04 +R10 72 73 1.061E+01 +R20 73 98 1.592E-01 +C10 72 73 1.00E-06 +* +* PSRR +* +EPSY 21 98 POLY(1) (99, 50) -8.000E-03 1.600E-03 +RPS1 21 22 3.183E+01 +RPS2 22 98 1.989E-01 +CPS1 21 22 1.00E-06 +* +* VOLTAGE NOISE REFERENCE OF 95nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 9.3564E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +EVP 97 98 (99,50) 0.36 +EVN 51 98 (50,99) 0.36 +GSY 99 50 POLY(1) (99,50) 7.6E-06 8.00E-08 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (4,6) (14,16) 0 2.608E-04 2.608E-04 +R1 30 98 1.00E+06 +RZ 45 31 1.855E+3 +CF 30 31 5.57E-09 +EV3 32 98 Poly(1) (99,50) 0.18125 0.03375; +EV4 98 33 Poly(1) (99,50) -0.13125 0.06625; +D3 30 32 DX +D4 33 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=3E-6 W=2.041E-03 +M6 45 47 50 50 NOX L=3E-6 W=8.333E-03 +EG1 99 46 POLY(1) (98,30) 7.091E-01 1 +EG2 47 50 POLY(1) (30,98) 6.090E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.7,LAMBDA=0.047,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.6,LAMBDA=0.022,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.50E-05,VTO=-0.5,LAMBDA=0.03) +.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5,LAMBDA=0.02) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=0E+00) +* +.ENDS ADA4051 +* +*$ +* ADA4077 SPICE DMod model Typical values +* Description: Amplifier +* Generic Desc: 30V, BIP, OP, Low Noise, Low THD, 2X +* Developed by: RM ADSJ +* Revision History: 1.0 03/31/2015 - Updated to new header style +* 0.0 (11/2012) +* Copyright 2008, 2012,2015 by Analog Devices +* +* Refer to "README.DOC" file for License Statement. Use of this +* model indicates your acceptance of the terms and provisions in +* the License Statement. +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT ADA4077-2 1 2 99 50 45 +* +*INPUT STAGE +**4input sacled poly +Q1 15 7 60 NIX +Q2 6 2 61 NIX +IOS 1 2 1.75E-10 +I1 5 50 77e-6 +EOS 7 1 POLY(4) (14,98) (73,98) (81,98) (70,98) 10E-6 1 1 1 1 +RC1 11 15 2.6E4 +RC2 11 6 2.6E4 +RE1 60 5 0.896E2 +RE2 61 5 0.896E2 +C1 15 6 4.25E-13 +D1 50 9 DX +V1 5 9 DC 1.8 +D10 99 10 DX +V6 10 11 1.3 +* +* CMRR +* +ECM 13 98 POLY(2) (1,98) (2,98) 0 7.192E-4 7.192E-4 +RCM1 13 14 2.15E2 +RCM2 14 98 5.31E-3 +CCM1 13 14 1E-6 +* +* PSRR +* +EPSY 72 98 POLY(1) (99,50) -1.683 0.056 +CPS3 72 73 1E-6 +RPS3 72 73 7.9577E+1 +RPS4 73 98 6.5915E-4 +* +* EXTRA POLE AND ZERO +* +G1 21 98 (6,15) 26E-6 +R1 21 98 9.8E4 +R2 21 22 9E6 +C2 22 98 1.7614E-12 +D3 21 99 DX +D4 50 21 DX +* +* VOLTAGE NOISE +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 6 +RN2 81 98 1 +* +* FLICKER NOISE +* +D5 69 98 DNOISE +VSN 69 98 DC .60551 +H1 70 98 VSN 30.85 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 130E-6 1.7495E-10 +* +* GAIN STAGE +* +G2 98 25 (21,98) 1E-6 +R5 25 98 9.9E7 +CF 45 25 2.69E-12 +V4 25 33 5.3 +D7 51 33 DX +EVN 51 98 (50,99) 0.5 +V3 32 25 5.3 +D6 32 97 DX +EVP 97 98 (99,50) 0.5 +* +* OUTPUT STAGE +* +Q3 45 41 99 POUT +Q4 45 43 50 NOUT +RB1 40 41 9.25E-4 +RB2 42 43 9.25E-4 +EB1 99 40 POLY(1) (98,25) 0.7153 1 +EB2 42 50 POLY(1) (25,98) 0.7153 1 +* +* MODELS +* +.MODEL NIX NPN (BF=71429,IS=1E-16) +.MODEL POUT PNP (BF=200,VAF=50,BR=70,IS=1E-15,RC=71.25) +.MODEL NOUT NPN (BF=200,VAF=50,BR=22,IS=1E-15,RC=29.2) +.MODEL DX D(IS=1E-16, RS=5, KF=1E-15) +.MODEL DNOISE D(IS=1E-16,RS=0,KF=1.095E-14) +.ENDS ADA4077-2 +*$ + + +*$ + +* ADA4091 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/30V, BIP, OP, Low Pwr, RRIO, 2X +* Developed by: HH / AD-SJ +* Revision History: 08/10/2012 - Updated to new header style +* 05/14/2014 - ported to Simplis (JSW) +* 0.0 (04/2009) +* Copyright 2008, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT ADA4091 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +I1 99 7 8.00E-06 +Q1 6 4 7A QP +Q2 5 3 7B QP +RE1 7A 7 7.774E+02 +RE2 7B 7 7.774E+02 +D1 3 99 DX +D2 4 99 DX +D3 50 3 DX +D4 50 4 DX +D5 3 4 DX +D6 4 3 DX +R1 3 8 5E+03 +R2 4 2 5E+03 +R3 5 50 7.500E4; +R4 6 50 7.500E4; +Cph 5 5A 0.235E-12 +Rph 5A 6 300 +EOS 8 1 POLY(4) (73,98) (22,98) (81,98) (83,98) -400E-9 1 1 1 1 +IOS 3 4 -50E-12 +CDiff 1 2 2.5E-12 +Cin1 1 50 2E-12 +Cin2 2 50 2E-12 +* +* INPUT PROTECTION NETWORK +* +X_in1 1 50 Diac1 +X_in2 2 50 Diac1 +X_in3 1 99 Diac1 +X_in4 2 99 Diac1 +* +* +RS1 99 39 400.0E3 +RS2 39 50 400.0E3 +EREF 98 0 (39,0) 1 +* +* 1ST GAIN STAGE +* +G1 9 98 (6,5) 1.0E-06 +R7 9 98 1E6 +* +* 2ND GAIN STAGE AND DOMINANT POLE +* +R8 12 98 1.094E+08 +G2 12 98 (98,9) 3.881E-06 +D7 12 13 DX +D8 14 12 DX +V1 13 98 +0.2; source +V2 14 98 -0.2; sink +* +* Provision for second pole +* +G3 18 98 (98,12) 1E-05 +R11 18 98 1E5 +* +* CMRR=90dB, Pole at 1100 Hz +* +ECM 21 98 POLY(2) (1,98) (2,98) 0 1.318E-01 1.318E-01 +R10 21 22 1.326E+05 +R20 22 98 1.592E+01 +C10 21 22 1E-9 +* +* PSRR=85dB, POLE AT 300 Hz +* +EPSY 72 98 POLY(1) (99,50) +0.1E-1 1.770E+01 +RPS1 72 73 7.958E+02 +RPS2 73 98 3.183E-03 +CPS1 72 73 1.00E-06 +* +* VOLTAGE NOISE REFERENCE OF 24nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 96.300E-3 +HN 81 98 VN1 2.397E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 300 Hz +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* OUTPUT STAGE +* +Q3 451 41 99 POUT +RB1 40 41 1.5E+03 +EB1 99 40 POLY(1) (98,18) 6.190E-01 1E-0; +Q4 451 43 50 NOUT +RB2 42 43 2.0E+03 +EB2 42 50 POLY(1) (18,98) 6.155E-01 1E-0; +Lout 45 451 10E-10 +RZ 45 453 100 +CZ 453 12 4.67E-12 +* +GSY 99 50 POLY(1) (99 50) 106.2E-6 -0.89E-06 +* +* MODELS +* +.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130) +.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130,IK=6E+00,BR=15,VAR=14.4, RC=30) +.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250,IK=11E+00,BR=30, VAR=20.0, RC=7) +.MODEL DW D(IS=1E-18) +.MODEL DX D() +.MODEL DY D(IS=1E-9) +.MODEL DZ D(IS=1E-6) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=8.640E-12) +* +.SUBCKT Diac1 1 2 +Done 1 3 DZ42hh +Dtwo 2 3 DZ42hh +.MODEL DZ42hh D(IS=3.3179E-6, N=2.0, RS=1.0000E-3, CJO=10.00E-12, M=.31349, VJ=.3905, ISR=2.9061E-9, BV=42.0, IBV=5.0E-03, TT=300.0E-9) +.ENDS Diac1 +* +* +.ENDS ADA4091 +* + +* ADA4092 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/30V, BIP, OP, Low Pwr, RRIO, 4X +* Developed by: HH / AD-SJ +* Revision History: 08/10/2012 - Updated to new header style +* 05/14/2014 - Ported to Simplis (JSW) +* 0.0 (12/2010) +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT ADA4092 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +Q1 6 4 7A QP +Q2 5 3 7B QP +RE1 7A 7 5.656E+02 +RE2 7B 7 5.656E+02 +I1 99 7 8.00E-06 +D1 3 99 DX +D2 4 99 DX +D3 50 3 DX +D4 50 4 DX +D5 3 4 DX +D6 4 3 DX +R1 3 8 5E+03 +R2 4 2 5E+03 +R3 5 50 7.500E4; +R4 6 50 7.500E4; +Cph 5 5A 0.23E-12 +Rph 5A 6 300 +EOS 8 1 POLY(4) (73,98) (22,98) (81,98) (83,98) -1.4E-03 1 1 1 1 +IOS 3 4 -2.0E-09 +CDiff 1 2 2.5E-12 +Cin1 1 50 2E-12 +Cin2 2 50 2E-12 +* +* INPUT PROTECTION NETWORK +* +X_in1 1 50 Diac1 +X_in2 2 50 Diac1 +X_in3 1 99 Diac1 +X_in4 2 99 Diac1 +* +* +RS1 99 39 400.0E3 +RS2 39 50 400.0E3 +EREF 98 0 (39,0) 1 +* +* 1ST GAIN STAGE +* +R7 9 98 3.266E+08 +G1 9 98 (6,5) 4.303E-06 +D7 9 13 DX +D8 14 9 DX +V1 13 98 0.37; sink +V2 14 98 +0.017; source +* +* 2ND GAIN STAGE AND DOMINANT POLE +* +R8 12 98 1.0E+06 +G2 12 98 (98,9) 1.0E-06 +* +* Provision for second pole +* +G3 18 98 (98,12) 1E-05 +R11 18 98 1E5 +* +* CMRR +* +ECM 21 98 POLY(2) (1,98) (2,98) 0 7.813E-02 7.813E-02 +R10 21 22 2.487E+04 +R20 22 98 1.592E+01 +C10 21 22 1E-9 +* +* PSRR +* +EPSY 72 98 POLY(1) (99,50) +0.1E-6 1.485E+01 +RPS1 72 73 5.305E+02 +RPS2 73 98 3.183E-03 +CPS1 72 73 1.00E-06 +* +* VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 25.5E-3 +HN 81 98 VN1 3.0E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* OUTPUT STAGE +* +Q3 451 41 99 POUT +RB1 40 41 1.5E+03 +EB1 99 40 POLY(1) (98,18) 6.190E-01 1E-0; +Q4 451 43 50 NOUT +RB2 42 43 2.0E+03 +EB2 42 50 POLY(1) (18,98) 6.155E-01 1E-0; +Lout 45 451 6.2E-12 +RZ 451 453 100 +CZ 453 9 4.6E-12 +* +GSY 99 50 POLY(1) (99 50) 79.9E-6 -1.04E-06 +* +* MODELS +* +.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130) +.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130, BR=3,VAR=15, RC=38); +.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250, BR=7, VAR=20, RC=8); +.MODEL DW D(IS=1E-18) +.MODEL DX D() +.MODEL DY D(IS=1E-9) +.MODEL DZ D(IS=1E-6) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.15E-12) +* +.SUBCKT Diac1 1 2 +Done 1 3 DZ42hh +Dtwo 2 3 DZ42hh +.MODEL DZ42hh D(IS=3.3179E-6, N=2.0, RS=1.0000E-3, CJO=10.00E-12, M=.31349, VJ=.3905, ISR=2.9061E-9, BV=42.0, IBV=5.0E-03, TT=300.0E-9) +.ENDS Diac1 +.ENDS ADA4092 +* +* + + + + + +* ADA4096 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 3/30V, BIP, OP, OVP, RRIO, 2X +* Developed by: HH / AD-SJ +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (07/2011) +* Copyright 2011, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT ADA4096 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +I1 99 7 8.00E-06 +RE1 7 7A 3.714E+03 +RE2 7 7B 3.714E+03 +Q1 6 4 7A QP +Q2 5 3 7B QP +D1 3 99 DX +D2 4 99 DX +D3 50 3 DX +D4 50 4 DX +D5 3 4 DX +D6 4 3 DX +R1 202 8 5E-03 +R2 204 4 5E-03 +R3 5 50 7.500E4; +R4 6 50 7.500E4; +Cph 5 5A 6.3E-13 +Rph 5A 6 400 +EOS 8 3 POLY(4) (73,98) (22,98) (81,98) (83,98) -250E-06 1 1 1 1 +IOS 3 4 -1.0E-09 +CDiff 1 2 6.35E-12 +Cin1 1 50 0.67E-12 +Cin2 2 50 0.67E-12 +* +* INPUT PROTECTION NETWORK +* +J1 1 201 202 JXB ; +J2 201 201 202 JXL ; +J3 2 203 204 JXB ; +J4 203 203 204 JXL +* +* 1ST GAIN STAGE +* +G1 9 98 (6,5) 1.0E-06 +R7 9 98 1E6 +* +* 2ND GAIN STAGE AND DOMINANT POLE +* +G2 12 98 (98,9) 3.375E-06 +R8 12 98 3.4E+08 +D7 12 13 DX +D8 14 12 DX +V1 13 98 +0.5; +V2 14 98 -0.2; +* +* Provision for second pole +* +G3 18 98 (98,12) 1E-05 +R11 18 98 1E5 +C11x 18 98 1E-14 +* +* CMRR +* +ECM 21 98 POLY(2) (1,98) (2,98) 0 2.635E-01 2.635E-01 +R10 21 22 1.326E+05 +R20 22 98 7.958E+00 +C10 21 22 1E-9 +* +* PSRR +* +EPSY 72 98 POLY(1) (99,50) -1.514E+3 5.048E+01 +RPS1 72 73 1.592E+03 +RPS2 73 98 1.989E-03 +CPS1 72 73 1.00E-06 +* +* VOLTAGE NOISE REFERENCE +* +VN1 80 98 0 +RN1 80 98 96.300E-3 +HN 81 98 VN1 2.397E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE 1000 +IFN 98 82 DC 1E-03 +DFN2 182 98 DY +IFN2 98 182 DC 1E-06 +GFN 83 98 POLY(1) (182,82) 1.00E-13 1.00E-01 +RFN 83 98 1 +* +* Current Noise +D60 60 98 DN1 1000 +I60 98 60 1E-03 +D61 61 98 DN4 +I61 98 61 1E-06 +G60 1 50 61 60 1.23E-05 +G61 2 50 61 60 1.33E-05 +* +RS1 99 39 400.0E3 +RS2 39 50 400.0E3 +EREF 98 0 (39,0) 1 +* +GSY 99 50 POLY(1) (99 50) -23.8E-6 -1.109E-06 +* +* OUTPUT STAGE +* +Q3 451 41 99 POUT +RB1 40 41 4.37E+03 +EB1 99 40 POLY(1) (98,18) 6.218E-01 1E-0; +Q4 451 43 50 NOUT +RB2 42 43 10E+03 +EB2 42 50 POLY(1) (18,98) 6.170E-01 1E-0; +Lout 45 451 10E-10 +EZ 453 98 (45 98) 1 +CZ 453 12 4.94E-12 +R99T 201 202 450k +* +* MODELS +* +.MODEL QP PNP(BF=300, IS=1.00E-16, VA=130) +.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130,BR=4.3,VAR=20, RC=75); +.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250,BR=9.5, VAR=18, RC=42); +.MODEL DN1 D IS=1E-16 +.MODEL DN4 D IS=1E-16 AF=1 KF=4.35E-17 +.MODEL DW D(IS=1E-18) +.MODEL DX D(IS=1E-16) +.MODEL DY D(IS=1E-16,RS=0.1) +.MODEL DZ D(IS=1E-6) +.MODEL DNOISE D(IS=1E-16,RS=0,KF=2.6E-13) +.MODEL JXL PJF(BETA=4E-05 VTO=-2.0 IS=1E-18 LAMBDA=0.008 RD=1E-1 ++ RS=5E1 CGD=1E-12 CGS=1E-12) +.MODEL JXB PJF(BETA=10E-05 VTO=-1.6 IS=1E-19 LAMBDA=0.005 RD=1E-1 RS=1.41E3) +.ENDS ADA4096 +* +* ADA4500 SPICE Macro-model +* Function: Amplifier +* Revision History: +* 1.0 (3/2013) - PH/DB - initial release + +* Copyright 2013 by Analog Devices +* +*Refer to +*http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Statement. +* +* +* Notes: +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT ADA4500 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* input stage +G_TAIL 99 8 40 98 120e-6 +mp1 11 7 8 8 pix +mp2 12 2 8 8 pix +RD1 11 50 2.0k +RD2 12 50 2.0k +C1 11 50 5.0pf +C2 12 50 5.0pf +C11 1 50 2.5pf +C12 2 50 2.5pf +C13 1 2 2.0pf +* +* gain stage +* basic gain stage +EXP1 13 98 11 12 10 +EXP2 16 98 14 98 1 +EXP3 18 98 17 98 1 +G1 98 30 19 98 60E-6 +R1 30 98 1E6 +R13 13 14 1.0K +R15 16 17 2.0K +R16 18 19 1.0K +C15 14 98 1.0PF +C16 17 98 1.0PF +C17 19 98 1.0PF +* +* slew rate enhance +D1 13 15 dx +D2 15 13 dx +G2 98 30 15 98 200E-6 +* GR1 is a noiseless 10K resistor +GR1 15 98 15 98 1.0E-4 +* +* overload clamp +EVN 98 29 40 98 2.8 +EVp 28 98 40 98 2.4 +D3 30 28 dx +D4 29 30 dx +* +* output stage +EG1 42 44 98 30 1 +EG2 43 41 30 98 1 +EG3 47 42 47 33 1 +EG4 41 46 32 46 1 +EVH 99 47 40 98 0.006 +EVL 46 50 40 98 0.006 +GG5 33 32 40 98 600E-6 +mn6 45 43 46 50 nox +mn8 32 32 46 50 nox +mp5 45 44 47 47 pox +mp7 33 33 47 47 pox +RZ 31 45 560 +CC1 30 31 30pf +CC2 30 45 2.0pf +* +* gnd bias +EREF 98 50 99 50 0.50 +* +* start up and bias generator +EB1 38 98 36 50 0.755 +EB2 40 38 36 37 9.65 +GB1 99 37 99 35 5e-6 +GB2 99 36 99 35 50e-6 +D39 34 52 dx +D40 35 34 dx +D41 99 35 dx +D42 37 50 dx +D43 36 50 dx +R39 52 50 20K +R40 99 34 20K +R41 99 35 40K +R42 37 50 20e6 +R43 36 50 2e6 +CB1 99 34 40pf +* +* input Vos adjust +* CMRR (set E23 K = 0.00 to remove CMRR adj) +*E23 23 1 72 98 0.0 +E23 23 1 72 98 0.50 +* +* This gnd is the only system ground used in this macromodel +* Different versions of SPICE may need gnd, gnd!, GND, GND!, or node 0 +* Note gnd is not a pin on the amp macromodel schematic, but gnd is in +* both the amp subckt call pin list and in the subckt header pin list +E71 71 98 8 0 1.0 ;orig = E71 71 98 8 gnd 1.0 +* +R71 71 72 500K +R72 72 98 1.0 +R73 71 73 100 +C72 73 72 200PF +* +* SHOT and FLICKER NOISE (set E25 & E26 K = 0.00 to remove shot noise) +*E25 25 23 81 98 0.00 +*E26 25 26 98 82 0.00 +E25 25 23 81 98 9.0E-3 +E26 25 26 98 82 9.0E-3 +G81 82 81 40 98 50E-6 +D81 81 98 dnoise +D82 98 82 dnoise +R81 81 98 1.0e6 +R82 98 82 1.0e6 +* +* WHITE NOISE (set E27 K = 0.00 to remove white noise) +*E27 27 26 98 83 0.00 +E27 27 26 98 83 0.690 +R83 83 98 20K +R84 83 98 20K +* +* VOS ADJUST (set E28 K = 0.00 to remove VOS adj) +*E28 7 27 40 98 0.00 +E28 7 27 40 98 -0.8e-6 +* +* +* ESD DIODES +D11 50 1 dx +D12 50 2 dx +D13 1 99 dx +D14 2 99 dx +D15 50 45 dx +D16 45 99 dx +D17 50 99 dz8p50 +* +************************************************************************************** +* +.model pix pmos (kp=1.00e-05, vto=-0.700, lambda=0.001, rd=0, w=2000u, l=1.0u) +.model pox pmos (kp=1.00e-05, vto=-0.700, lambda=0.020, rd=0, w=1400u, l=1.0u) +.model nox nmos (kp=2.00e-05, vto=+0.650, lambda=0.020, rd=0, w=700u, l=1.0u) +.model dx d (is=1e-14, rs=1.0) +.model dz8p50 d (is=1e-13, rs=1.0, bv=8.50, ibv=5e-4) +.model dnoise d (is=1e-14, rs=1.0, kf=4.78e-11) +* +************************************************************************************** +* +.ENDS ADA4500 +* +************************************************************************************** + +************************************************************************************** +* ADA4505 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 1.8/5V, CMOS, OP, ZCO, RRIO, 2X +* Developed by: GEC/ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/2009) +* Copyright 2009, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: VSY=5V, T=25°C +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT ADA4505 1 2 99x 50x 45 +* +* INPUT STAGE +* +M1 4 7x 8 8 PIX L=1E-6 W=7.80E-02 +M2 6 2x 8 8 PIX L=1E-6 W=7.80E-02 +* Cinp 1 98 4.7pF +* Cinn 2 98 4.7pF +* Cdiff 7 2 2.5pF +RD1 4 50 800 +RD2 6 50 800 +C1 4 6 1.26E-09 +I1 99 8 5.00E-04 +V1 9 8 0.015E-00 +D1 9 99 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 5.00E-04 1 1 1 1 +IOS 1 2 1.30E-14 + +RCM1 1 98 223E9 noiseless +RCM2 2 98 223E9 noiseless +Rdiff 7 2 1E6 noiseless + +Ibias1 1 98 0.5p +Ibias2 2 98 0.5p + +Cinp 1 98 1.3pF +Cinn 2 98 1.3pF +Cdiff 1 2 2.5pF + +Einn 2x 98 2 98 1 +Einp 7x 98 7 98 1 + +*Supply Current + +Esupply_plus 99 0 99x 0 1 +Esupply_minus 50 0 50x 0 1 +Isupply 99x 50x 9.24u + +* +* CMRR=107dB, POLE AT 350 Hz +* +*E1 72 98 POLY(2) (1,98) (2,98) 0 0.06381194E-00 0.06381194E-00 +E1 72 98 POLY(2) (1,98) (2,98) 0 0.02381194E-00 0.02381194E-00 +R10 72 73 454.728E+00 +R20 73 98 3.18E-02 +C10 72 73 1.00E-06 +* +* PSRR=105dB, POLE AT 0.5 Hz +* +*EPSY 21 98 POLY(1) (99,50) -1.374048E-00 .9898096E-00 +EPSY 21 98 POLY(1) (99,50) -3.374048E-00 .0988096E-00 +RPS1 21 22 3.18E+04 +RPS2 22 98 2.65E+00 +CPS1 21 22 1.00E-06 +* +**Inoise*** +FnIN 2 98 Vmeas3 0.7071068 +Vmeas3 510 98 dc 0 +VnIN 500 98 dc 0.535 +DnIN 500 510 DINnoisy +FnIN1 98 2 Vmeas4 0.7071068 +Vmeas4 53 98 dc 0 +VnIN1 52 98 dc 0.535 +DnIN1 52 53 DINnoisy +* +FnIP 1 98 Vmeas5 0.7071068 +Vmeas5 310 98 dc 0 +VnIP 300 98 dc 0.535 +DnIP 300 310 DIPnoisy +FnIP1 98 1 Vmeas6 0.7071068 +Vmeas6 330 98 dc 0 +VnIP1 320 98 dc 0.535 +DnIP1 320 330 DIPnoisy +* +* VOLTAGE NOISE REFERENCE OF 53nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +*HN 81 98 VN1 5.30E+01 +HN 81 98 VN1 6.50E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 25 Hz +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.647 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -4.9999E-04 0.1E-10 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* Extra Poles + +*G2 98 999 4 6 26E-6 +G2 98 999 4 6 3.6E-6 +R2 999 98 3.19E5 +R3 999 N027 1e3 +C2 N027 98 9.947e-12 +D2 999 99 DX +D5 50 999 DX + + +* GAIN STAGE +* +*G1 98 30 (4,6) 7.809E-05 +G1 98 30 (999,98) 4.809E-05 +R1 30 98 1E+06 +*CF 30 31 3.124E-09 +CF 30 31 2.624E-09 +RZ 45 31 1.697E+03 +V3 32 30 5.43E-01 +V4 30 33 5.42E-01 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=1.10E-03 +M6 45 47 50 50 NOX L=1E-6 W=1.38E-03 +EG1 99 46 POLY(1) (98,30) 3.649E-01 1 +EG2 47 50 POLY(1) (30,98) 3.610E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=4.78E-11) +.model DINnoisy D(IS=1.38e-18 KF=0.00e0) +.model DIPnoisy D(IS=1.38e-18 KF=0.00e0) +* +* +.ENDS ADA4505 +* +************************************************************************************** +* + +* Copyright (c) 1998-2021 Analog Devices, Inc. All rights reserved. +* +.subckt ADA4522-1 1 2 3 4 5 +D6 4 1 DX +Ccm1 1 4 35p Rser=100 noiseless +Cdm 1 2 7p Rser=200 noiseless +CF N007 N009 7.1p Rser=15k noiseless +M5 5 N006 3 3 POXN temp=27 +M6 5 N012 4 4 NOXN temp=27 +R4 N010 0 48 noiseless +C3 N011 N010 10n Rpar=18.9K noiseless +R5 N011 0 1 noiseless +G1 0 N011 1 0 5.25m +G8 0 N011 2 0 5.25m +G9 0 N011 0 3 5.25m +G10 0 N011 0 4 5.25m +D9 3 4 Dburn +R10 3 Mid 100Meg noiseless +D10 2 1 Din +G12 0 N009 5 Mid 100m +R12 N009 0 1K noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-.2, .1)+1n*V(1) + 2.93p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-.21, .1)+1n*V(2) +C1 N004 0 .01f Rpar=100K noiseless +C2 3 N006 15f Rser=3 Rpar=100Meg noiseless +A1 0 N007 3 3 3 3 N006 3 OTA g=10u linear ref=-33.8m vlow=-2.2 vhigh=0 +C5 N012 4 15f Rser=3 Rpar=100Meg noiseless +A3 0 N007 4 4 4 4 N012 4 OTA g=10u linear ref=33.8m vlow=0 vhigh=1.7 +D1 N007 0 DANTISAT +A5 N005 0 0 0 0 0 N007 0 OTA g=120u asym isource=6.43u isink=-12.7u vlow=-1e308 vhigh=1e308 +L1 N009 0 500n Rser=10 noiseless +G7 3 N006 5 3 10m vto=-10m dir=1 +G6 N012 4 4 5 10m vto=-8m dir=1 +C8 3 5 1p Rpar=100Meg noiseless +C9 5 4 1p Rpar=100Meg noiseless +C10 Mid 4 50p Rser=1Meg Rpar=100Meg noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear Rout=1Meg Cout=90f en=sqrt( ( (7.3n*(1+(freq/600K)**2)*(1+freq/10Meg))/((1+(freq/920K)**3.2)))**2+((17p*((freq/350k)**4.6))/(((1+freq/2.4Meg)**1.4)*((1+freq/10Meg)**4)*((1+freq/6.8Meg)**2)*((1+freq/9Meg)**2)))**2) + (.1n*(1+freq/9Meg)**3.5)/(1+freq/70Meg) vlow=-1e308 vhigh=1e308 +G2 0 N004 0 N010 1µ +Ccm2 2 4 35p Rser=100 noiseless +D2 1 3 DX +D3 2 3 DX +D4 4 2 DX +D5 3 1 DBIAS +D7 3 2 DBIAS +A2 0 2 0 0 0 0 0 0 OTA g=0 in=.66p*((1+MIN(freq,4k)/15k)**3)/((MAX(freq,5k)/5k)**1.5) +A6 0 1 0 0 0 0 0 0 OTA g=0 in=.66p*((1+MIN(freq,4k)/15k)**3)/((MAX(freq,5k)/5k)**1.5) +.model DX D(IS=1E-14,RS=0.1 noiseless) +.model NOXN VDMOS(Vto=.83 Mtriode=.7 Kp=53.33m RD=38 noiseless) +.model POXN VDMOS(Vto=-.83 Mtriode=.55 Kp=26.67m Theta=10m Rd=7 pchan noiseless) +.model Din D(Ron=150 Roff=30K Rrev=600 vfwd=5.1 epsilon=600m vrev=5.5 revepsilon=600m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=600m ilimit=211.8u noiseless) +.model DANTISAT D(Ron=1k Roff=30Meg vfwd=1 epsilon=100m vrev=600m revepsilon=100m noiseless) +.model DBIAS D(Ron=100Meg Roff=1T vfwd=600m epsilon=500m ilimit=100p noiseless) +.ends ADA4522-1 +* +* +.subckt ADA4522 1 2 3 4 5 +D6 4 1 DX +Ccm1 1 4 35p Rser=100 noiseless +Cdm 1 2 7p Rser=200 noiseless +CF N007 N009 7.1p Rser=25k noiseless +M5 5 N006 3 3 POXN temp=27 +M6 5 N012 4 4 NOXN temp=27 +R4 N010 0 48 noiseless +C3 N011 N010 10n Rpar=18.9K noiseless +R5 N011 0 1 noiseless +G1 0 N011 1 0 5.25m +G8 0 N011 2 0 5.25m +G9 0 N011 0 3 5.25m +G10 0 N011 0 4 5.25m +D9 3 4 Dburn +R10 3 Mid 100Meg noiseless +D10 2 1 Din +G12 0 N009 5 Mid 100m +R12 N009 0 1K noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-.2, .1)+1n*V(1) + 2.93p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-.21, .1)+1n*V(2) +C1 N004 0 .01f Rpar=100K noiseless +C2 3 N006 15f Rser=3 Rpar=100Meg noiseless +A1 0 N007 3 3 3 3 N006 3 OTA g=300n linear ref=-33.8m vlow=-2.2 vhigh=0 +C5 N012 4 15f Rser=3 Rpar=100Meg noiseless +A3 0 N007 4 4 4 4 N012 4 OTA g=300n linear ref=33.8m vlow=0 vhigh=1.7 +D1 N007 0 DANTISAT +A5 N005 0 0 0 0 0 N007 0 OTA g=120u asym isource=6.43u isink=-12.7u vlow=-1e308 vhigh=1e308 +L1 N009 0 500n Rser=10 noiseless +G7 3 N006 5 3 10m vto=-10m dir=1 +G6 N012 4 4 5 10m vto=-8m dir=1 +C8 3 5 1p Rpar=100Meg noiseless +C9 5 4 1p Rpar=100Meg noiseless +C10 Mid 4 50p Rser=1Meg Rpar=100Meg noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear Rout=1Meg Cout=90f en=sqrt( ( (7.3n*(1+(freq/600K)**2)*(1+freq/10Meg))/((1+(freq/920K)**3.2)))**2+((17p*((freq/350k)**4.6))/(((1+freq/2.4Meg)**1.4)*((1+freq/10Meg)**4)*((1+freq/6.8Meg)**2)*((1+freq/9Meg)**2)))**2) + (.1n*(1+freq/9Meg)**3.5)/(1+freq/70Meg) vlow=-1e308 vhigh=1e308 +G2 0 N004 0 N010 1µ +Ccm2 2 4 35p Rser=100 noiseless +D2 1 3 DX +D3 2 3 DX +D4 4 2 DX +D5 3 1 DBIAS +D7 3 2 DBIAS +A2 0 2 0 0 0 0 0 0 OTA g=0 in=.66p*((1+MIN(freq,4k)/15k)**3)/((MAX(freq,5k)/5k)**1.5) +A6 0 1 0 0 0 0 0 0 OTA g=0 in=.66p*((1+MIN(freq,4k)/15k)**3)/((MAX(freq,5k)/5k)**1.5) +.model DX D(IS=1E-14,RS=0.1 noiseless) +.model NOXN VDMOS(Vto=.83 Mtriode=.7 Kp=53.33m RD=38 noiseless) +.model POXN VDMOS(Vto=-.83 Mtriode=.55 Kp=26.67m Theta=10m Rd=7 pchan noiseless) +.model Din D(Ron=150 Roff=30K Rrev=600 vfwd=5.1 epsilon=600m vrev=5.5 revepsilon=600m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=600m ilimit=211.8u noiseless) +.model DANTISAT D(Ron=1k Roff=30Meg vfwd=1 epsilon=100m vrev=600m revepsilon=100m noiseless) +.model DBIAS D(Ron=100Meg Roff=1T vfwd=600m epsilon=500m ilimit=100p noiseless) +.ends ADA4522 +* +* +* +.subckt ADA4528 1 2 3 4 5 +Ccm1 1 4 15.75p Rser=100 noiseless +Cdm 1 2 15.7p Rser=200 noiseless +CF N006 N008 3.8p +M5 5 N005 3 3 POXN temp=27 +M6 5 N010 4 4 NOXN temp=27 +D9 3 4 Dburn +R10 3 Mid 100Meg noiseless +G12 0 N008 5 Mid 100m +R12 N008 0 10 noiseless +B1 0 N007 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1) + 2.93p +B2 N007 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.2, .1)+1n*V(2) +C1 N007 0 .01f Rpar=100K noiseless +C2 3 N005 400f Rser=300k Rpar=10Meg noiseless +A1 0 N006 3 3 3 3 N005 3 OTA g=3u linear ref=-33.5m vlow=-2 vhigh=0 +A3 0 N006 4 4 4 4 N010 4 OTA g=3u linear ref=33.5m vlow=0 vhigh=2 +D1 N006 0 Dantisat +A5 N004 0 0 0 0 0 N006 0 OTA g=95u iout=1.91u Cout=1p vlow=-1e308 vhigh=1e308 +G7 3 N005 5 3 100m vto=-4.8m dir=1 +G6 N010 4 4 5 100m vto=-4.3m dir=1 +C8 3 5 1p Rpar=100Meg noiseless +C9 5 4 1p Rpar=100Meg noiseless +C10 Mid 4 50p Rser=1Meg Rpar=100Meg noiseless +A4 0 N007 0 0 0 0 N004 0 OTA g=1u linear en=6n*((1+(uplim(freq,170k,10K)/150k)**18)/(1+(uplim(freq,280k,10k)/250k)**18))*(((1+freq/10.2k)/(1+freq/9.8k))**4)*(1+(uplim(freq,1.15Meg,200k)/1Meg)**5)/((1+freq/5Meg)**2) Rout=1Meg Cout=22f vlow=-1e308 vhigh=1e308 +D2 1 3 DX temp=27 +A2 0 2 0 0 0 0 0 0 OTA g=0 in=.6p +A6 0 1 0 0 0 0 0 0 OTA g=0 in=.6p +C4 N010 4 400f Rser=300k Rpar=10Meg noiseless +D3 2 3 DX temp=27 +D4 4 2 DX temp=27 +D5 4 1 DX temp=27 +Ccm3 3 1 15.75p Rser=100 noiseless +Ccm2 2 4 15.75p Rser=100 noiseless +Ccm4 3 2 15.75p Rser=100 noiseless +D6 1 4 Dbias1 +S1 1 3 3 4 Sbias1 +D7 3 2 Dbias1 +S2 4 2 3 4 Sbias1 +D8 2 1 Din +D10 1 2 Din +C5 3 4 20p Rpar=25k noiseless +.model DX D(IS=1E-16,RS=100 noiseless) +.model NOXN VDMOS(Vto=.8 Mtriode=1.8 Kp=30m noiseless) +.model POXN VDMOS(Vto=-.8 Mtriode=1.2 Kp=40m pchan noiseless) +.model Din D(Ron=400k Roff=400k ilimit=5u noiseless) +.model Dburn D(Ron=100 Roff=1G vfwd=600m epsilon=600m ilimit=576.5u noiseless) +.model Dantisat D(Ron=1k Roff=30Meg vfwd=300m epsilon=100m vrev=300m revepsilon=100m noiseless) +.model DBIAS1 D(Ron=1Meg Roff=1Meg ilimit=220p noiseless) +.model SBIAS1 SW(level=2 Ron=1Meg Roff=1e40 vt=.5 vh=-1.5 ilimit= 130p noiseless) +.param RL=10K +.ends ADA4528 +* +* ADA4665 SPICE Macro-model Typical Values at Vsy=+/-8V +* Description: Amplifier +* Generic Desc: 5/16V, CMOS, OP, Low Pwr, RRIO, 2X +* Developed by: VW ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 0.2 (05/2009) +* Copyright 2009, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* Not Modeled: +* +* Parameters modeled include: Vsy = 16V, Ta = 25C +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT ADA4665 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=2E-6 W=2.72e-4 +M2 6 2 8 8 PIX L=2E-6 W=2.72e-4 +M3 14 7 18 18 NIX L=2E-6 W=2.72e-4 +M4 16 2 18 18 NIX L=2E-6 W=2.72e-4 +Rd1 4 50 1.6E+4 +Rd2 6 50 1.6E+4 +Rd3 99 14 1.6E+4 +Rd4 99 16 1.6E+4 +C1 4 6 2.58E-12 +C2 14 16 2.58E-12 +I1 99 8 2.5E-5 +I2 18 50 2.5E-5 +V1 99 9 0.940 +V2 19 50 0.940 +D1 8 9 DX +D2 19 18 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (83,98) 1e-3 1 1 1 1 +IOS 1 2 0.05E-12 + +* +* CMRR +* +E1 72 98 POLY(2) (1,98) (2,98) 0 2.24e-3 2.24e-3 +R10 72 73 3.98E1 +R20 73 98 3.18e-1 +C10 72 73 1E-6 + +* +* PSRR +* +EPSY 21 98 POLY(1) (99,50) -18.083 1.1302 +CPS3 21 22 1E-6 +RPS1 21 22 3.18e3 +RPS2 22 98 5.31E-2 + +* +* VOLTAGE NOISE REFERENCE +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +*HN 81 98 VN1 24.5 +HN 81 98 VN1 25.5 +RN2 81 98 1 + +* +* FLICKER NOISE +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1e-3 1 +RFN 83 98 1 + +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) 8.615e-5 4.95e-7 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 + + +* +* GAIN STAGE +* +G1 98 30 POLY(2) (4,6) (14,16) 0 3.54e-3 3.54e-3 +R1 30 98 1e6 +CF 31 30 1.99e-9 +RZ 31 100 9 +EZ 100 98 (45,98) 1 +V3 32 30 3.35 +V4 30 33 0.85 +D3 32 97 DX +D4 51 33 DX + +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=3E-6 W=5.43E-4 +M6 45 47 50 50 NOX L=3E-6 W=1.197E-3 +EG1 99 46 POLY(1) (98,30) 7e-1 1 +EG2 47 50 POLY(1) (30,98) 6e-1 1 + +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.02,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.02,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.02,TOX=100E-3) +.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.02,TOX=100E-3) +.MODEL DX D(IS=1E-14,RS=5,KF=1E-15) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.94E-10) + +.ENDS ADA4665 +* +*$ + + + + + +.Subckt ADA4805 100 101 102 103 104 106 +* ADA4805 SPICE Macro-model +* Function: Amplifier +* +* Revision History: +* Rev. 2.0 Jul 2014 -BP +* Copyright 2014 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +* for License Statement. Use of this model indicates your acceptance +* of the terms and provisions in the License Staement. +* +* Tested on MultiSim, SiMetrix(NGSpice), PSICE +* +* Not modeled: Distortion, PSRR, Overload recovery, Slew Rate Enhancment, +* ShutDown Turn On/Turn Off time +* +* Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, CMRR, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality, Single supply & offset supply functionality. +* +* Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | ShutDown BAR +* | | | | | | +*Subckt ADA4805 100 101 102 103 104 106 +*#ASSOC Category="Op-Amps" symbol=opamp_6_pd_bar +* +***Power Supplies*** +Ibias 102 103 dc 7.4e-6 +DzPS 98 102 diode +Iquies 102 98 dc 562.6e-6 +S1 98 103 106 113 Switch +R1 102 99 Rideal 1e7 +R2 99 103 Rideal 1e7 +e1 111 110 102 110 1 +e2 110 112 110 103 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 9e-6 +IbiasP 110 2 dc 470e-9 +IbiasN 110 9 dc 470e-9 +RinCMP 110 2 Rideal 5e7 +RinCMN 9 110 Rideal 5e7 +CinCMP 110 2 1e-15 +CinCMN 9 110 1e-15 +IOS 9 2 dc 4e-10 +RinDiff 9 2 Rideal 260e3 +CinDiff 9 2 1e-012 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 1.55 +VinN 42 112 dc 0.45 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.1067812 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.1067812 +Vmeas2 22 110 DC 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.70710678 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.70710678 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.70710678 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.70710678 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e7 +RcmrrN 10 9 Rideal 1e7 +g10 11 110 10 110 6e-11 +Lcmrr 11 12 5e-3 +Rcmrr 12 110 Rideal 1E3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 110 80 dc 0.8 +VPD1 81 0 dc 0.4 +RPD 110 106 Rideal 5.4e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 106 113 Switch +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***1st Pole*** +g210 210 110 200 110 928.1e-9 +R210 210 110 Rideal 1.0827e9 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.1 +VoutN 64 66 dc 5.1 +e60 65 110 111 110 1.05 +e61 66 110 112 110 1.05 +* +* +*** 11 frequency stages *** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 0.9947e-12 +* +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.7579e-12 +* +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +C240 240 110 0.6366e-12 +* +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +C245 245 110 0.6121e-12 +* +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +C250 250 110 0.6121e-12 +* +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +C255 255 110 1e-15 +* +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +C260 260 110 1e-15 +* +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +C265 265 110 1e-15 +* +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +C270 270 110 1e-15 +* +e280 280 110 270 110 1 +R280 280 285 Rideal 1 +L280 285 281 1e-12 +C280 281 282 1e-15 +R281 282 110 Rideal 1e3 +* +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 3.36e-9 +C290 291 292 227.4e-12 +R291 292 110 Rideal 3.3545 +e295 295 110 292 110 3.9811 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 301 302 Rideal 50 +Lout 302 310 1e-009 +Cout 310 110 6e-012 +* +* +***Output Current Limit*** +VIoutP 71 310 dc 3.65 +VIoutN 310 72 dc 2.97 +DIoutP 70 71 diode +DIoutN 72 70 diode +Rx3 70 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.71 +VoutN1 74 112 dc 0.71 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 DC 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 DC 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common models*** +.model diode d(bv=100) +.model Switch vswitch(Von=0.401,Voff=0.399,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=181.24) +.model DzSlewN D(BV=181.24) +.model DVnoisy D(IS=1.03e-015 KF=8.94e-018) +.model DINnoisy D(IS=1.86e-017 KF=9.41e-017) +.model DIPnoisy D(IS=1.86e-017 KF=9.41e-017) +.model Rideal res(T_ABS=-273) +.ends ADA4805 +^ +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +.subckt ADA4807-1 1 2 3 4 5 6 +A1 0 X0 0 0 0 0 X1 0 OTA g=1m linear en=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? 3n*(1+4/freq) : 6n*(1+15/freq)) Vlow= -1e308 Vhigh=1e308 +C4 X0 0 1e-20 Rpar=1K noiseless +D4 N004 2 bias1 +B3 0 X0 I=1m*dnlim(uplim(V(1),V(3)+.6,.1), V(4)-.6, .1)+100n*V(1) - 2.53264n +B4 X0 0 I=1m*dnlim(uplim(V(2),V(3)+.6,.1), V(4)-.6, .1)+100n*V(2) +C5 1 4 .5p Rpar=180Meg noiseless +C9 3 1 .5p Rpar=180Meg noiseless +C10 2 4 .5p Rpar=180Meg noiseless +C11 3 2 .5p Rpar=180Meg noiseless +C18 2 1 .5p Rpar=35K noiseless +D7 N004 1 bias1 +D8 3 2 bias2 +D9 3 1 bias2 +D2 1 3 ED1 +D10 4 1 ED1 +D11 2 3 ED1 +D12 4 2 ED1 +A2 0 2 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K +R10 N005 0 {RH*2} noiseless +C1 N005 N007 {Cf} +C2 X2 0 {C1_PZ1} Rser={R1_PZ1} Rpar={R2_PZ1} noiseless +G4 0 XX N005 0 {alpha_PZ2} +C3 XX 0 {C1_PZ2} Rser={R1_PZ2} Rpar={R2_PZ2} noiseless +G5 0 X2 X1 0 {alpha_PZ1} +C6 X1 0 200f Rpar=1K noiseless +M1 5 PG 3 3 PI temp=27 +M2 5 NG 4 4 NI temp=27 +D1 3 PG DLIMP +D5 NG 4 DLIMN +C7 3 PG {CX} Rser={RX} Lser={LX} RLshunt={RLS} noiseless +B1 4 NG I=(.5+.5*tanh((V(ON)-.5)/100m))*dnlim(vminn/1e6+1.3u*(V(XX)+voffn),vminn/1e6,100n) +B2 PG 3 I=(.5+.5*tanh((V(ON)-.5)/100m))*dnlim(vminp/1e6-1.3u*(V(XX)-voffp),vminp/1e6,100n) +C8 NG 4 {CX} Rser={RX} Lser={LX} RLshunt={RLS} noiseless +C12 3 5 1p Rpar=100Meg Rser=100 noiseless +G1 0 N007 5 Mid 100m +L1 N007 0 1.5n Rser=10 noiseless +A5 X2 0 0 0 0 0 XSMIN 0 OTA g=1.8m asym isource=130u isink=-120u Rout=10k Vhigh=1e308 Vlow=-1e308 +D6 2 1 ED2 +R11 3 Mid 5Meg noiseless +C13 5 4 1p Rpar=100Meg Rser=100 noiseless +C14 3 N006 6p Rpar=100Meg Rser=100 noiseless +C15 N006 4 6p Rpar=100Meg Rser=100 noiseless +S1 N006 5 0 ON SDIS +C16 N006 5 100f +D13 N005 0 DLIMOD +R12 Mid 4 5Meg noiseless +A6 0 1 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K +S2 3 4 ON 0 Iq +B5 0 N005 I=200u*uplim(dnlim(-V(X2)-600m,0,100m),1,100m)-250u*uplim(dnlim(V(X2)-600m,0,100m),1,100m) +D14 X2 X1 DLS +S3 N004 3 ON 0 SBIAS +C17 3 N004 10f +D15 N004 3 bias3 +D16 3 4 DBURN +R4 N011 ON 10Meg noiseless +A4 0 XSMIN ON 0 0 0 N005 0 OTA g=100u linear vlow=-1e308 vhigh=1e308 +R6 ON 0 100Meg noiseless +G2 4 N010 3 4 1µ +R5 N010 4 1Meg noiseless +D3 3 6 470nA +A3 N010 6 0 0 0 N011 0 0 SCHMITT Vt=0 Vh=150m Trise=3.5u Tfall=425n vlow=0 vhigh=1.1 +I1 N010 4 3.5µ +G3 4 N010 4 N010 100µ vto=-1.335 dir=1 +.param Cf = 1p +.param Ro = 5K +.param Avol = 3.16Meg +.param RL = 1K +.param AVmid = 260 +.param FmidA = 1Meg +.param Zomid = 2.1 +.param FmidZ = 10Meg +.param Vslew = 225Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff=1G Vfwd=-17m epsilon=10m noiseless) +.model X2 D(Ron=1m Roff=1G Vfwd=-47m epsilon=10m noiseless) +.model X SW(Ron={2*Ro} Roff=1T Vt=.5 Vh=-.4 noiseless) +.model IQ SW(Ron=1K Roff=1G Vt=.5 Vh=-.4 Ilimit=151.5u noiseless) +.model bias1 D(Ron=50K Vfwd=1.1 Vrev=-1.1 noiseless) +.model bias2 D(Ron=19Meg Vfwd=1.1 epsilon=.5 noiseless) +.model bias3 D(Ron=100k vfwd=-500m epsilon=500m ilimit=950n noiseless) +.model ED1 D(Ron=1 Roff=1T Vfwd=.5 epsilon=1 noiseless) +.model ED2 D(Ron=100 Roff=1T Vfwd=1.2 epsilon=1 Vrev=1 revepsilon=1 noiseless) +.model 470nA D(Ron=1Meg Roff=1G Ilimit=470n epsilon=1 Vfwd=1 noiseless) +.param alpha_PZ1=1.0e-6 pole_PZ1=8.8e6 zero_PZ1=22e6 ++ R2_PZ1=1.0/alpha_PZ1 R1_PZ1=1.0/(alpha_PZ1*(zero_PZ1/pole_PZ1 - 1.0)) ++C1_PZ1=1.0/(2.0*pi*zero_PZ1*R1_PZ1) +.param alpha_PZ2=1.0e-3 pole_PZ2=70e6 zero_PZ2=90e6 ++ R2_PZ2=1.0/alpha_PZ2 R1_PZ2=1.0/(alpha_PZ2*(zero_PZ2/pole_PZ2 - 1.0)) ++C1_PZ2=1.0/(2.0*pi*zero_PZ2*R1_PZ2) +.param vminp = 400m +.param voffp = 105.8m +.param vminn=400m +.param voffn = 100m +.model PI VDMOS(VTO=-300m mtriode=3 KP=30m pchan noiseless) +.model NI VDMOS(VTO=300m mtriode=4.4 KP=32m noiseless) +.model SDIS SW(Ron=1 Roff=100Meg vt=-.5 vh=-200m noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2.45 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2.45 epsilon=100m noiseless) +.model DLIMOD D(Ron=10 Roff={RH*2} vfwd=1.5 epsilon=200m vrev=2 revepsilon=200m noiseless) +.model DLS D(Ron=10 Roff=10G vfwd=300m epsilon=100m vrev=300m revepsilon=100m noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=10G vt=500m vh=-200m ilimit=1.8u epsilon=100m oneway noiseless) +.model DBURN D(Ron=100k Roff=1G vfwd=1 epsilon=1 ilimit=200n noiseless) +.param CX=4f +.param RX = 400k +.param LX=1.8m +.param RLS = 1Meg +.param vs = 5 +.ends ADA4807-1 +* +* +* +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +.subckt ADA4807 1 2 3 4 5 6 +A1 0 X0 0 0 0 0 X1 0 OTA g=1m linear en=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? 3n*(1+4/freq) : 6n*(1+15/freq)) Vlow= -1e308 Vhigh=1e308 +C4 X0 0 1e-20 Rpar=1K noiseless +D4 N004 2 bias1 +B3 0 X0 I=1m*dnlim(uplim(V(1),V(3)+.6,.1), V(4)-.6, .1)+100n*V(1) - 2.53264n +B4 X0 0 I=1m*dnlim(uplim(V(2),V(3)+.6,.1), V(4)-.6, .1)+100n*V(2) +C5 1 4 .5p Rpar=180Meg noiseless +C9 3 1 .5p Rpar=180Meg noiseless +C10 2 4 .5p Rpar=180Meg noiseless +C11 3 2 .5p Rpar=180Meg noiseless +C18 2 1 .5p Rpar=35K noiseless +D7 N004 1 bias1 +D8 3 2 bias2 +D9 3 1 bias2 +D2 1 3 ED1 +D10 4 1 ED1 +D11 2 3 ED1 +D12 4 2 ED1 +A2 0 2 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K +R10 N005 0 {RH*2} noiseless +C1 N005 N007 {Cf} +C2 X2 0 {C1_PZ1} Rser={R1_PZ1} Rpar={R2_PZ1} noiseless +G4 0 XX N005 0 {alpha_PZ2} +C3 XX 0 {C1_PZ2} Rser={R1_PZ2} Rpar={R2_PZ2} noiseless +G5 0 X2 X1 0 {alpha_PZ1} +C6 X1 0 200f Rpar=1K noiseless +M1 5 PG 3 3 PI temp=27 +M2 5 NG 4 4 NI temp=27 +D1 3 PG DLIMP +D5 NG 4 DLIMN +C7 3 PG {CX} Rser={RX} Lser={LX} RLshunt={RLS} noiseless +B1 4 NG I=(.5+.5*tanh((V(ON)-.5)/100m))*dnlim(vminn/1e6+1.3u*(V(XX)+voffn),vminn/1e6,100n) +B2 PG 3 I=(.5+.5*tanh((V(ON)-.5)/100m))*dnlim(vminp/1e6-1.3u*(V(XX)-voffp),vminp/1e6,100n) +C8 NG 4 {CX} Rser={RX} Lser={LX} RLshunt={RLS} noiseless +C12 3 5 1p Rpar=100Meg Rser=100 noiseless +G1 0 N007 5 Mid 100m +L1 N007 0 1.5n Rser=10 noiseless +A5 X2 0 0 0 0 0 XSMIN 0 OTA g=1.8m asym isource=130u isink=-120u Rout=10k Vhigh=1e308 Vlow=-1e308 +D6 2 1 ED2 +R11 3 Mid 5Meg noiseless +C13 5 4 1p Rpar=100Meg Rser=100 noiseless +C14 3 N006 6p Rpar=100Meg Rser=100 noiseless +C15 N006 4 6p Rpar=100Meg Rser=100 noiseless +S1 N006 5 0 ON SDIS +C16 N006 5 100f +D13 N005 0 DLIMOD +R12 Mid 4 5Meg noiseless +A6 0 1 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K +S2 3 4 ON 0 Iq +B5 0 N005 I=200u*uplim(dnlim(-V(X2)-600m,0,100m),1,100m)-250u*uplim(dnlim(V(X2)-600m,0,100m),1,100m) +D14 X2 X1 DLS +S3 N004 3 ON 0 SBIAS +C17 3 N004 10f +D15 N004 3 bias3 +D16 3 4 DBURN +R4 N011 ON 10Meg noiseless +A4 0 XSMIN ON 0 0 0 N005 0 OTA g=100u linear vlow=-1e308 vhigh=1e308 +R6 ON 0 100Meg noiseless +G2 4 N010 3 4 1µ +R5 N010 4 1Meg noiseless +D3 3 6 470nA +A3 N010 6 0 0 0 N011 0 0 SCHMITT Vt=0 Vh=150m Trise=3.5u Tfall=425n vlow=0 vhigh=1.1 +I1 N010 4 3.5µ +G3 4 N010 4 N010 100µ vto=-1.335 dir=1 +.param Cf = 1p +.param Ro = 5K +.param Avol = 3.16Meg +.param RL = 1K +.param AVmid = 260 +.param FmidA = 1Meg +.param Zomid = 2.1 +.param FmidZ = 10Meg +.param Vslew = 225Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff=1G Vfwd=-17m epsilon=10m noiseless) +.model X2 D(Ron=1m Roff=1G Vfwd=-47m epsilon=10m noiseless) +.model X SW(Ron={2*Ro} Roff=1T Vt=.5 Vh=-.4 noiseless) +.model IQ SW(Ron=1K Roff=1G Vt=.5 Vh=-.4 Ilimit=151.5u noiseless) +.model bias1 D(Ron=50K Vfwd=1.1 Vrev=-1.1 noiseless) +.model bias2 D(Ron=19Meg Vfwd=1.1 epsilon=.5 noiseless) +.model bias3 D(Ron=100k vfwd=-500m epsilon=500m ilimit=950n noiseless) +.model ED1 D(Ron=1 Roff=1T Vfwd=.5 epsilon=1 noiseless) +.model ED2 D(Ron=100 Roff=1T Vfwd=1.2 epsilon=1 Vrev=1 revepsilon=1 noiseless) +.model 470nA D(Ron=1Meg Roff=1G Ilimit=470n epsilon=1 Vfwd=1 noiseless) +.param alpha_PZ1=1.0e-6 pole_PZ1=8.8e6 zero_PZ1=22e6 ++ R2_PZ1=1.0/alpha_PZ1 R1_PZ1=1.0/(alpha_PZ1*(zero_PZ1/pole_PZ1 - 1.0)) ++C1_PZ1=1.0/(2.0*pi*zero_PZ1*R1_PZ1) +.param alpha_PZ2=1.0e-3 pole_PZ2=70e6 zero_PZ2=90e6 ++ R2_PZ2=1.0/alpha_PZ2 R1_PZ2=1.0/(alpha_PZ2*(zero_PZ2/pole_PZ2 - 1.0)) ++C1_PZ2=1.0/(2.0*pi*zero_PZ2*R1_PZ2) +.param vminp = 400m +.param voffp = 105.8m +.param vminn=400m +.param voffn = 100m +.model PI VDMOS(VTO=-300m mtriode=3 KP=30m pchan noiseless) +.model NI VDMOS(VTO=300m mtriode=4.4 KP=32m noiseless) +.model SDIS SW(Ron=1 Roff=100Meg vt=-.5 vh=-200m noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2.45 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2.45 epsilon=100m noiseless) +.model DLIMOD D(Ron=10 Roff={RH*2} vfwd=1.5 epsilon=200m vrev=2 revepsilon=200m noiseless) +.model DLS D(Ron=10 Roff=10G vfwd=300m epsilon=100m vrev=300m revepsilon=100m noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=10G vt=500m vh=-200m ilimit=1.8u epsilon=100m oneway noiseless) +.model DBURN D(Ron=100k Roff=1G vfwd=1 epsilon=1 ilimit=200n noiseless) +.param CX=4f +.param RX = 400k +.param LX=1.8m +.param RLS = 1Meg +.param vs = 5 +.ends ADA4807 +* +* +.subckt ADA4807-4 1 2 3 4 5 +C1 N006 X {Cf} +A1 N005 0 M M M M X M OTA g={Ga} Iout={Islew} en=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? 3n*(1+4/freq) : 6n*(1+15/freq)) Vhigh=1e308 Vlow=-1e308 +D21 X 3 ESD +D22 4 X ESD +D5 N006 3 X1 +D6 4 N006 X2 +G2 0 M 3 0 500µ +R4 M 0 1K noiseless +G3 0 M 4 0 500µ +S1 X M 4 3 SD +C4 N004 0 20p Rpar=1K Rser=10 noiseless +C2 3 N006 .25p +D3 3 4 IQ +D4 3 2 bias1 +B3 0 N004 I=1m*dnlim(uplim(V(1),V(3)+.6,.1), V(4)-.6, .1)+100n*V(1) +B4 N004 0 I=1m*dnlim(uplim(V(2),V(3)+.6,.1), V(4)-.6, .1)+100n*V(2) +D1 N007 N006 AA +C5 1 4 .25p Rpar=180Meg noiseless +C9 3 1 .25p Rpar=180Meg noiseless +C10 2 4 .25p Rpar=180Meg noiseless +C11 3 2 .25p Rpar=180Meg noiseless +C18 2 1 .75p Rpar=35K noiseless +D7 3 1 bias1 +D8 3 2 bias2 +D9 3 1 bias2 +D2 1 3 ED1 +D10 4 1 ED1 +D11 2 3 ED1 +D12 4 2 ED1 +D13 2 1 ED2 +D14 5 3 ED1 +D15 4 5 ED1 +G4 0 N005 N004 0 1m +L1 N005 0 20µ Cpar=.7p Rser=2k Rpar=2K noiseless +C3 3 5 .25p +C7 5 4 .25p +C8 N006 4 .25p +L2 N007 5 100n Rpar=10 noiseless +A2 2 1 0 0 0 0 0 0 OTA g=0 in=((V(3)-.5*(V(1)+V(2)) > 1.1 ? 1 : 0) ? .7p : .42p) ink=1.5K incm=.1p incmk=1.5k +B1 3 N006 I=if(V(m,x)>=0, V(m,x)*Gb,0) +B2 N006 4 I=if(V(x,m)>0, V(x,m)*Gb,0) +.param Cf = 6p +.param Ro = 5K +.param Avol = 3.16Meg +.param RL = 1K +.param AVmid = 10 +.param FmidA = 18Meg +.param Zomid = 2.1 +.param FmidZ = 10Meg +.param Vslew = 225Meg +.param Vmin = 2 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.model ESD D(Ron=10 Roff=1T Vfwd=1 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-17m epsilon=10m noiseless) +.model X2 D(Ron=1m Roff={2*Ro} Vfwd=-47m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model IQ D(Ron=1K Roff=100Meg epsilon=1 Ilimit=500u noiseless) +.model AA D(Ron=5 Vrev=0 Ilimit=80m revIlimit=80m noiseless) +.model bias1 D(Ron=50K Ilimit=.9u revilimit=.45u Vfwd=1.1 Vrev=-1.1 noiseless) +.model bias2 D(Ron=19Meg Vfwd=1.1 epsilon=.5 noiseless) +.model ED1 D(Ron=1 Roff=1T Vfwd=.5 epsilon=1 noiseless) +.model ED2 D(Ron=1 Roff=1T Vfwd=1 epsilon=1 Vrev=1 revepsilon=1 noiseless) +.ends ADA4807-4 +* +*ADA4841 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.x Oct 2015-ZZ +*Copyright 2015 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | PD +* | | | | | | +.Subckt ADA4841 100 101 102 103 104 106 +*#ASSOC Category="Op-Amps" symbol=opamp_6_pd +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.04e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 1.16e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 40e-6 +IbiasP 110 2 dc 3e-6 +IbiasN 110 9 dc 3e-6 +RinCMP 110 2 Rideal 180e6 +RinCMN 9 110 Rideal 180e6 +CinCMP 110 2 1.5e-12 +CinCMN 9 110 1.5e-12 +IOS 9 2 0.1e-6 +RinDiff 9 2 Rideal 25e3 +CinDiff 9 2 3e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 1.46 +VinN 42 112 dc 0.36 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 1.89 +VPD1 81 0 dc 0.42 +RPD 111 106 Rideal 0.769e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 50 Hz*** +g210 210 110 200 110 1.2566e-6 +R210 210 110 Rideal 3183.1e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.109 +VoutN 64 66 dc 5.109 +e60 65 110 111 110 1.086 +e61 66 110 112 110 1.086 +* +* +***Pole at 128MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 1.2434e-12 +* +***Buffer*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +* +***Buffer*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +* +***Buffer*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Notch: f=110MHz, Zeta=2, Gain=2.6dB*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +L280 285 281 13.983e-9 +C280 281 282 149.715e-12 +R281 282 110 Rideal 28.656 +* +***Buffer*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +e295 295 110 292 110 1 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 43 +Lout 303 310 80e-9 +Cout 310 110 8e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 2.336 +VIoutN 304 306 dc 5.336 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.69 +VoutN1 74 112 dc 0.69 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=0.425,Voff=0.415,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=9.273) +.model DzSlewN D(BV=9.273) +.model DVnoisy D(IS=1.67e-16 KF=3.26e-17) +.model DINnoisy D(IS=7.39e-17 KF=3.69e-16) +.model DIPnoisy D(IS=7.39e-17 KF=3.69e-16) +.model Rideal res(T_ABS=-273) +* +.ends ADA4841 + +* ADA4851 SPICE Macro-model +* Description: Amplifier +* Generic Desc: Low Cost Voltage Feedback RR Dual +* Developed by: +* Revision History: 08/10/2012 - Updated to new header style +* +* Copyright 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* END Notes +* +* Node assignments +.SUBCKT ADA4851 INV NINV OUT VCC VEE +*#ASSOC Category="Op-amps" symbol=opamp +*************************************** +* Analog Devices ADA4851 +* 2005.03.20 v1.1 +* OP AMP modeling services provided by: +* Interface Technologies +* www.i-t.com +*************************************** +* Features included in model +* 1. Open loop gain and phase +* 2. Output voltage and current +* 3. Input Common mode range +* 4. Input Bias current +* 5. Input voltage noise +* 6. Slew rate +* 7. Output current reflected in Vs supplies +* 8. Transient Response +* 9. Frequency Response +*************************************** +Q_Q1 V5 92 7 NPN +D_DN5 96 97 DIN +V_V1 VCC_INT N129837 2.7 +I_I1 4 VEE_INT DC .05 +V_VN2 37 0 2Vdc +R_R3 ISUPP1 0 RCOLD 10meg +C_C1 100 81 4p +E_E5 VEE_INT 0 VEE 0 1 +G_G7 100 CMRRP2 CMRRP1 100 .01 +G_G2 100 N10305 10 100 1e-2 +R_RP1 10 100 RCOLD 100 +C_CP3 100 100 1.0610e-12 +G_G1 100 10 N06761 100 7.1 +D_DN6 97 98 DIN +D_D8 VCC ISUPP1 DNOM +Q_Q2 V6 INV 8 NPN +G_GV 100 N06761 V6 V5 .001 +V_VP VCC_INT VCCVPBAT .499 +R_RCM2a CMRRP1 100 RCOLD 100 +G_G3a 100 MAINP2 N10305 100 1e-2 +V_VN3 0 93 2 +D_D9 ISUPP2 VEE DNOM +C_CP1 100 10 8.07e-6 +E_E4 VCC_INT 0 VCC 0 1 +R_RCM3 CMRRP2 100 RCOLD 100 +R_RC1 VCC_INT V5 RCOLD 101.034 +V_VN4 95 0 2 +G_GN1 0 NINV 94 0 2.15e-9 +R_R4 0 ISUPP2 RCOLD 10meg +D_D5 INV N129837 DP +V_VN VEEVNBAT VEE_INT .505 +G_G5 100 30 VINMID 100 3.162e-8 +R_RCM 31 100 RCOLD 1E2 +V_VN5 0 96 2 +C_CCM2a 100 CMRRP1 2.6526e-11 +R_RC2 VCC_INT V6 RCOLD 101.034 +D_DZ2 100 16 DLIM +R_RCM1 NINV VINMID RCOLD 1000MEG +E_EBUF 80 100 MAINP2 100 1 +V_VN6 98 0 2 +G_G10 0 INV 97 0 2.15e-9 +C_CCM3 100 CMRRP2 1.9894e-11 +L_LCM 31 30 2.274e-3 +E_ENIN 92 9 36 0 2.5e-7 +R_RE1 7 4 RCOLD 100 +D_DN1 35 36 DEN +G_G3 ISUPP1 0 80 81 .02 +R_RCM4 CMRR_V 100 RCOLD 100 +D_DZ1 N06761 16 DLIM +D_DN2 36 37 DEN +D_D_VCCclamp 10 VCCVPBAT DP +E_EOS NINV 9 POLY(1) CMRR_V 100 0.0 1 +R_RE2 8 4 RCOLD 100 +R_RCM2 VINMID INV RCOLD 1000MEG +G_G4 0 ISUPP2 80 81 -.02 +L_Lout OUT 81 60n +R_RP2 N10305 100 RCOLD 100 +I_IQP ISUPP1 0 DC 2.5m +E_E1 100 0 103 0 1 +D_D6 0 ISUPP1 DZ +G_G8 100 CMRR_V CMRRP2 100 .01 +D_DN3 93 94 DIN +E_E6 103 VEE_INT VALUE { (V(VCC_INT)-V(VEE_INT))/2 } +G_G6 100 CMRRP1 30 100 .01 +D_D_VEEclamp VEEVNBAT 10 DN +D_D7 ISUPP2 0 DZ +R_RP3 MAINP2 100 RCOLD 100 +I_IQM 0 ISUPP2 DC 2.5m +R_Rout 80 81 RCOLD 50 +D_DN4 94 95 DIN +C_CCM4 100 CMRR_V 1.9894e-12 +R_RV N06761 100 RCOLD 500k +V_VN1 0 35 2Vdc +C_CP2 100 N10305 1.326e-11 +.MODEL DLIM D(IS=1E-15 BV=1010) +.MODEL DEN D(IS=1E-8 RS=1 KF=1E-15 AF=1) +.MODEL DIN D(IS=.75E-12 RS=100 KF=3e-15 AF=1) +.MODEL DNOM D(IS=1E-15 T_ABS=-100) +.MODEL DZ D(IS=1E-15 BV=50 T_ABS=-100) +.MODEL RCOLD RES T_ABS=-273 +.MODEL DILIM D(IS=1E-15) +.MODEL NPN NPN(BF=1.47e4) +.MODEL DP D(IS=5E-10 BV=700 ) +.MODEL DN D(IS=5E-10 BV=700 ) +.ENDS ADA4851 + + + +*ADA4891 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.2.1 Oct 2016-JL +*Copyright 2016 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents. +* +* +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +* | | | | | +.Subckt ADA4891 100 101 102 103 104 +* +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.01e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 4.39e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 2.5e-3 +IbiasP 110 2 dc 2e-12 +IbiasN 110 9 dc 2e-12 +RinCMP 110 2 Rideal 5000e6 +RinCMN 9 110 Rideal 5000e6 +CinCMP 110 2 2.2e-12 +CinCMN 9 110 2.2e-12 +IOS 9 2 1e-15 +RinDiff 9 2 Rideal 10000e3 +CinDiff 9 2 0.8e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 1.26 +VinN 42 112 dc 0.16 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -8.437e-9 +Lcmrr 11 12 8e-3 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2 +VPD1 81 0 dc 1.5 +RPD 111 106 Rideal 1e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 8.88 Hz*** +g210 210 110 200 110 3.378e-6 +R210 210 110 Rideal 17.92e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.121 +VoutN 64 66 dc 5.095 +e60 65 110 111 110 1.27 +e61 66 110 112 110 1.27 +* +* +***Pole at 500MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 0.3183e-12 +* +***Pole at 800MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.1989e-12 +* +***Pole at 1200MHz*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +C240 240 110 0.1326e-12 +* +***Pole at 1500MHz*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +C245 245 110 0.1061e-12 +* +***Pole at 1700MHz*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +C250 250 110 0.0936e-12 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +* +***Peak: f=210MHz, Zeta=0.7, Gain=0.2dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 5.413e-9 +C290 291 292 106.103e-12 +R291 292 110 Rideal 429.314 +e295 295 110 292 110 1.0233 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 36 +Lout 303 310 7e-9 +Cout 310 110 1.3e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 19.836 +VIoutN 304 306 dc 30.036 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.705 +VoutN1 74 112 dc 0.695 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=50.802) +.model DzSlewN D(BV=62.643) +.model DVnoisy D(IS=2.99e-15 KF=1.02e-14) +.model DINnoisy D(IS=3.81e-19 KF=0.00e0) +.model DIPnoisy D(IS=3.81e-19 KF=0.00e0) +.model Rideal res(T_ABS=-273) +* +.ends ADA4891 + +*ADA4895 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.2.1 Jul 2016-JL +*Copyright 2016 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | PD +* | | | | | | +.Subckt ADA4895 100 101 102 103 104 106 +*#ASSOC Category="Op-Amps" symbol=opamp_6_pd_bar +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.1e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 2.8e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 53e-6 +IbiasP 110 2 dc 11e-6 +IbiasN 110 9 dc 11e-6 +RinCMP 110 2 Rideal 10e6 +RinCMN 9 110 Rideal 10e6 +CinCMP 110 2 3e-12 +CinCMN 9 110 3e-12 +IOS 9 2 -0.02e-6 +RinDiff 9 2 Rideal 10e3 +CinDiff 9 2 11e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 1.36 +VinN 42 112 dc 0.56 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -0.746e-9 +Lcmrr 11 12 22.7e-3 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2 +VPD1 81 0 dc 1.5 +RPD 111 106 Rideal 1e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 9.5 Hz*** +g210 210 110 200 110 75.503e-6 +R210 210 110 Rideal 16.75e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.386 +VoutN 64 66 dc 5.251 +e60 65 110 111 110 1.681 +e61 66 110 112 110 1.681 +* +* +***Pole at 110MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 1.4469e-12 +* +***Pole at 3500MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.0455e-12 +* +***Zero at 2500MHz*** +g240 240 110 230 110 0.001 +R240 240 241 Rideal 1000 +L240 241 110 0.0637e-6 +* +***Pole at 4500MHz*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +C245 245 110 0.0354e-12 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Notch: f=66MHz, Zeta=1.7, Gain=4.4dB*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +L280 285 281 17.845e-9 +C280 281 282 325.857e-12 +R281 282 110 Rideal 15.161 +* +***Peak: f=660MHz, Zeta=1.3, Gain=6.2dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 0.927e-9 +C290 291 292 62.697e-12 +R291 292 110 Rideal 9.599 +e295 295 110 292 110 2.0417 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 50 +Lout 303 310 1.1e-9 +Cout 310 110 2.6e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 10.936 +VIoutN 304 306 dc 10.436 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.725 +VoutN1 74 112 dc 0.715 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=12.965) +.model DzSlewN D(BV=12.965) +.model DVnoisy D(IS=3.75e-17 KF=9.78e-18) +.model DINnoisy D(IS=9.69e-17 KF=2.44e-16) +.model DIPnoisy D(IS=9.69e-17 KF=2.44e-16) +.model Rideal res(T_ABS=-273) +* +.ends ADA4895 + +*ADA4896 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.3.1 Jul 2016-rv +*Copyright 2016 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +.Subckt ADA4896 100 101 102 103 104 +* +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +R3 96 0 Rideal 1e3 +S6 97 96 1020 1030 Sswitch +V2 97 0 dc 2 +gBias 1020 1030 96 0 0.3e-3 +DzPS 98 1020 diode +gQuies 1020 98 96 0 2.7e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc -28e-6 +IbiasP 110 2 dc -11e-6 +IbiasN 110 9 dc -11e-6 +RinCMP 110 2 Rideal 1e7 +RinCMN 9 110 Rideal 1e7 +CinCMP 110 2 2.6e-12 +CinCMN 9 110 2.6e-12 +IOS 9 2 -0.02e-6 +RinDiff 9 2 Rideal 1e4 +CinDiff 9 2 3.4e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 0.56 +VinN 42 112 dc 0.56 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 3.4 +VPD1 81 0 dc 1.5 +RPD 111 106 Rideal 0.286e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***Gain Split*** +g200 200 110 7 9 1 +R200 200 110 Rideal 1e4 +* +* +***Dominant Pole at 452 Hz*** +g210 210 110 Value={limit(V(200,110)*8.976e-4,1.459,-1.459)} +R210 210 110 Rideal 3.523e4 +C210 210 110 1e-8 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.328 +VoutN 64 66 dc 5.195 +e60 65 110 111 110 1.216 +e61 66 110 112 110 1.216 +* +* +***Pole at 360MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 0.4421e-12 +* +***Pole at 460MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.346e-12 +* +***Buffer*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +* +***Buffer*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Notch: f=94MHz, Zeta=1.9, Gain=3.8dB*** +e280 280 110 270 110 1 +L280 285 281 12.574e-9 +C280 281 282 227.983e-12 +R281 282 110 Rideal 18.221 +R280 280 285 Rideal 10 +* +***Peak: f=90MHz, Zeta=1.7, Gain=0.4dB*** +e290 290 110 285 110 1 +L290 290 291 5.201e-9 +C290 291 292 601.251e-12 +R291 292 110 Rideal 212.186 +e295 295 110 292 110 1.0471 +R290 290 292 Rideal 10 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 18 +Lout 303 310 6e-9 +Cout 310 110 13e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 12.836 +VIoutN 304 306 dc 12.836 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.795 +VoutN1 74 112 dc 0.785 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6) +.model Sswitch vswitch(Von=3,Voff=0.1,ron=1000,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DVnoisy D(IS=3.8e-17 KF=1.33e-17) +.model DINnoisy D(IS=2.99e-16 KF=4.63e-17) +.model DIPnoisy D(IS=2.99e-16 KF=4.63e-17) +.model Rideal res(T_ABS=-273) +* +.ends +* +.subckt ADTL082 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.01p ink=10 incm=.001p incmk=10 +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C3 3 5 2p +C4 5 4 2p +C6 3 1 1.375p Rpar=250G noiseless +A2 0 N003 M M M M N004 M OTA g=150u Isrc=90u Isink=-120u en=16n enk=100 Vlow=-1e308 Vhigh=1e308 Cout= 4p asym +C10 N003 0 2p Rpar=1K noiseless +D1 N004 5 Y +D6 5 N004 Y +C1 2 1 4.125p noiseless +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N004 M 4 3 UVLO +D3 N004 3 X +D4 4 N004 X +D2 3 4 IQ +C7 1 4 1.375p Rpar=250G noiseless +C8 3 2 1.375p Rpar=250G noiseless +C9 2 4 1.375p Rpar=250G noiseless +I1 1 4 2p load +I2 2 4 2p load +B1 N003 0 I=1m*dnlim(uplim(V(2),V(3)-1,.1), V(4)+3.5, .1)+100n*V(2) +B2 0 N003 I=1m*dnlim(uplim(V(1),V(3)-1,.1), V(4)+3.5, .1)+100n*V(1) +.model X D(Ron=10K Roff=100G Vfwd=-1.25 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=2 epsilon=.1 noiseless) +.model N VDMOS(Vto=-250m Kp=10m Ksubthres=.2 noiseless) +.model P VDMOS(Vto=250m Kp=10m pchan Ksubthres=.2 noiseless) +.model UVLO SW(Ron=1K Roff=5G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=4.7m noiseless) +.ends ADTL082 +* +.SUBCKT OP113 3 2 7 4 6 +* +* INPUT STAGE +* +R3 4 19 1.5E3 +R4 4 20 1.5E3 +C1 19 20 5.31E-12 +I1 7 18 106E-6 +IOS 2 3 25E-09 +EOS 12 5 POLY(1) 51 4 25E-06 1 +Q1 19 3 18 PNP1 +Q2 20 12 18 PNP1 +CIN 3 2 3E-12 +D1 3 1 DY +D2 2 1 DY +EN 5 2 22 0 1 +GN1 0 2 25 0 1E-5 +GN2 0 3 28 0 1E-5 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +DN1 21 22 DEN +DN2 22 23 DEN +VN1 21 0 DC 2 +VN2 0 23 DC 2 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +DN3 24 25 DIN +DN4 25 26 DIN +VN3 24 0 DC 2 +VN4 0 26 DC 2 +* +* SECOND CURRENT NOISE SOURCE +* +DN5 27 28 DIN +DN6 28 29 DIN +VN5 27 0 DC 2 +VN6 0 29 DC 2 +* +* GAIN STAGE & DOMINANT POLE AT 2HZ +* +G2 34 36 19 20 2.65E-04 +R7 34 36 39E6 +V3 35 4 DC 6 +D4 36 35 DX +VB2 34 4 1.6 +* +* SUPPLY/2 GENERATOR +* +ISY 7 4 0.2E-3 +R10 7 60 40E3 +R11 60 4 40E3 +C3 60 0 1E-9 +* +* CMRR STAGE & POLE AT 6kHZ +* +ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8 +CCM 50 51 26.5E-12 +RCM1 50 51 1E6 +RCM2 51 4 1 +* +* OUTPUT STAGE +* +R12 37 36 1E3 +R13 38 36 500 +C4 37 6 20E-12 +C5 38 39 20E-12 +M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +D5 39 47 DX +D6 47 45 DX +Q3 39 40 41 QPA 8 +VB 7 40 DC 0.861 +R14 7 41 375 +Q4 41 7 43 QNA 1 +R17 7 43 15 +Q5 43 39 6 QNA 20 +Q6 46 45 6 QPA 20 +R18 46 4 15 +Q7 36 46 4 QNA 1 +M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 +* +* NONLINEAR MODELS USED +* +.MODEL DX D (IS=1E-15) +.MODEL DY D (IS=1E-15 BV=7) +.MODEL PNP1 PNP (BF=220) +.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) +.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 ++ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 ++ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12 ++ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) +.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 ++ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 ++ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 ++ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) +.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 ++ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 ++ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 ++ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33) +.ENDS OP113 + +* OP177A SPICE Macro-model +* Description: Amplifier +* Generic Desc: 6/30V, BIP, OP, Low Vos, Low TcVos, 1X +* Developed by: JCB / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (12/1990) - Re-ordered subcircuit call out nodes to put the output node last. +* - Changed Ios from 1E-9 to 0.5E-9 +* - Added F1 and F2 to fix short circuit current limit. +* Copyright 1990, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* This version of the OP-177 model simulates the worst case +* parameters of the 'A' grade. The worst case parameters +* used correspond to those in the data book. +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP177A 1 2 99 50 39 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE & POLE AT 6 MHZ +* +R1 2 3 5E11 +R2 1 3 5E11 +R3 5 97 0.0606 +R4 6 97 0.0606 +CIN 1 2 4E-12 +C2 5 6 218.9E-9 +I1 4 51 1 +IOS 1 2 0.5E-9 +EOS 9 10 POLY(1) 30 33 10E-6 1 +Q1 5 2 7 QX +Q2 6 9 8 QX +R5 7 4 0.009 +R6 8 4 0.009 +D1 2 1 DX +D2 1 2 DX +EN 10 1 12 0 1 +GN1 0 2 15 0 1 +GN2 0 1 18 0 1 +* +EREF 98 0 33 0 1 +EPLUS 97 0 99 0 1 +ENEG 51 0 50 0 1 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +DN1 11 12 DEN +DN2 12 13 DEN +VN1 11 0 DC 2 +VN2 0 13 DC 2 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +DN3 14 15 DIN +DN4 15 16 DIN +VN3 14 0 DC 2 +VN4 0 16 DC 2 +* +* SECOND CURRENT NOISE SOURCE +* +DN5 17 18 DIN +DN6 18 19 DIN +VN5 17 0 DC 2 +VN6 0 19 DC 2 +* +* FIRST GAIN STAGE +* +R7 20 98 1 +G1 98 20 5 6 119.8 +D3 20 21 DX +D4 22 20 DX +E1 97 21 POLY(1) 97 33 -2.4 1 +E2 22 51 POLY(1) 33 51 -2.4 1 +* +* GAIN STAGE & DOMINANT POLE AT 0.127 HZ +* +R8 23 98 1.253E9 +C3 23 98 1E-9 +G2 98 23 20 33 33.3E-6 +V1 97 24 1.8 +V2 25 51 1.8 +D5 23 24 DX +D6 25 23 DX +* +* NEGATIVE ZERO AT -4MHZ +* +R9 26 27 1 +C4 26 27 -39.75E-9 +R10 27 98 1E-6 +E3 26 98 23 33 1E6 +* +* COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ +* +R13 30 31 1 +L2 31 98 2.52E-3 +G4 98 30 3 33 0.316E-6 +D7 30 97 DX +D8 51 30 DX +* +* POLE AT 2 MHZ +* +R14 32 98 1 +C5 32 98 79.5E-9 +G5 98 32 27 33 1 +* +* OUTPUT STAGE +* +R15 33 97 1 +R16 33 51 1 +GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 +F1 34 0 V3 1 +F2 0 34 V4 1 +R17 34 99 400 +R18 34 50 400 +L3 34 39 2E-7 +G6 37 50 32 34 2.5E-3 +G7 38 50 34 32 2.5E-3 +G8 34 99 99 32 2.5E-3 +G9 50 34 32 50 2.5E-3 +V3 35 34 6.8 +V4 34 36 4.4 +D9 32 35 DX +D10 36 32 DX +D11 99 37 DX +D12 99 38 DX +D13 50 37 DY +D14 50 38 DY +* +* MODELS USED +* +.MODEL QX NPN(BF=333.3E6) +.MODEL DX D(IS=1E-15) +.MODEL DY D(IS=1E-15 BV=50) +.MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) +.MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) +.ENDS OP177A + + + +* OP191 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/12V, BIP, OP, RRIO, OVP, 1X +* Developed by: ARG / PMI. TRW / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (11/1994) +* Copyright 1994, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP191 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +I1 99 7 8.06E-6 +Q1 6 4 7 QP +Q2 5 3 7 QP +D1 3 99 DX +D2 4 99 DX +D3 3 4 DX +D4 4 3 DX +R1 3 8 5E3 +R2 4 2 5E3 +R3 5 50 6.4654E3 +R4 6 50 6.4654E3 +EOS 8 1 POLY(1) 16 39 -80E-6 1 +IOS 3 4 50E-12 +GB1 3 98 21 98 50E-9 +GB2 4 98 21 98 50E-9 +CIN 1 2 1E-12 +* +* 1ST GAIN STAGE +* +EREF 98 0 39 0 1 +G1 98 9 6 5 31.667E-6 +R7 9 98 1E6 +EC1 99 10 POLY(1) 99 39 -0.52 1 +EC2 11 50 POLY(1) 39 50 -0.52 1 +D5 9 10 DX +D6 11 9 DX +* +* 2ND GAIN STAGE AND DOMINANT POLE AT 36HZ +* +G2 98 12 9 39 8E-6 +R8 12 98 276.311E6 +C2 12 98 16E-12 +D7 12 13 DX +D8 14 12 DX +V1 99 13 0.58 +V2 14 50 0.58 +* +* COMMON MODE STAGE +* +ECM 15 98 POLY(2) 1 39 2 39 0 0.5 0.5 +R9 15 16 1E6 +R10 16 98 10 +* +* POLE AT 2.5MHZ +* +G3 98 18 12 39 1E-6 +R11 18 98 1E6 +C4 18 98 63.662E-15 +* +* BIAS CURRENT-VS-COMMON MODE VOLTAGE +* +EP 97 0 99 0 1 +VB 99 17 1.3 +RB 17 50 1E9 +E3 19 0 15 17 16 +D13 19 20 DX +R12 20 0 1E6 +G4 98 21 20 0 1E-3 +R13 21 98 5E3 +D14 21 22 DY +E4 97 22 POLY(1) 99 98 -0.765 1 +* +* POLE AT 100MHZ +* +G6 98 40 18 39 1E-6 +R20 40 98 1E6 +C10 40 98 1.592E-15 +* +* OUTPUT STAGE +* +RS1 99 39 109.375E3 +RS2 39 50 109.375E3 +RO1 99 45 41.667 +RO2 45 50 41.667 +G7 45 99 99 40 24E-3 +G8 50 45 40 50 24E-3 +G9 98 60 45 40 24E-3 +D9 60 61 DX +D10 62 60 DX +V7 61 98 DC 0 +V8 98 62 DC 0 +FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1 +D11 41 45 DZ +D12 45 42 DZ +V5 40 41 0.131 +V6 42 40 0.131 +.MODEL DX D() +.MODEL DY D(IS=1E-9) +.MODEL DZ D(IS=1E-6) +.MODEL QP PNP(BF=133.333) +.ENDS OP191 + + + + + + +* OP213 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 4/30V, BIP, OP, Low Noise, Low Drift, 2X +* Developed by: JCB / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (09/1992) +* Copyright 1992, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP213 3 2 7 4 6 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +R3 4 19 1.5E3 +R4 4 20 1.5E3 +C1 19 20 5.31E-12 +I1 7 18 106E-6 +IOS 2 3 25E-09 +EOS 12 5 POLY(1) 51 4 25E-06 1 +Q1 19 3 18 PNP1 +Q2 20 12 18 PNP1 +CIN 3 2 3E-12 +D1 3 1 DY +D2 2 1 DY +EN 5 2 22 0 1 +GN1 0 2 25 0 1E-5 +GN2 0 3 28 0 1E-5 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +DN1 21 22 DEN +DN2 22 23 DEN +VN1 21 0 DC 2 +VN2 0 23 DC 2 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +DN3 24 25 DIN +DN4 25 26 DIN +VN3 24 0 DC 2 +VN4 0 26 DC 2 +* +* SECOND CURRENT NOISE SOURCE +* +DN5 27 28 DIN +DN6 28 29 DIN +VN5 27 0 DC 2 +VN6 0 29 DC 2 +* +* GAIN STAGE & DOMINANT POLE AT .2000E+01 HZ +* +G2 34 36 19 20 2.65E-04 +R7 34 36 39E+06 +V3 35 4 DC 6 +D4 36 35 DX +VB2 34 4 1.6 +* +* SUPPLY/2 GENERATOR +* +ISY 7 4 0.2E-3 +R10 7 60 40E+3 +R11 60 4 40E+3 +C3 60 0 1E-9 +* +* CMRR STAGE & POLE AT 6 kHZ +* +ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8 +CCM 50 51 26.5E-12 +RCM1 50 51 1E6 +RCM2 51 4 1 +* +* OUTPUT STAGE +* +R12 37 36 1E3 +R13 38 36 500 +C4 37 6 20E-12 +C5 38 39 20E-12 +M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +D5 39 47 DX +D6 47 45 DX +Q3 39 40 41 QPA 8 +VB 7 40 DC 0.861 +R14 7 41 375 +Q4 41 7 43 QNA 1 +R17 7 43 15 +Q5 43 39 6 QNA 20 +Q6 46 45 6 QPA 20 +R18 46 4 15 +Q7 36 46 4 QNA 1 +M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 +* +* NONLINEAR MODELS USED +* +.MODEL DX D (IS=1E-15) +.MODEL DY D (IS=1E-15 BV=7) +.MODEL PNP1 PNP (BF=220) +.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) +.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 ++ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 ++ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12 ++ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) +.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 ++ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 ++ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 ++ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) +.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 ++ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 ++ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 ++ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33) +* +.ENDS OP213 + + + + + + +* OP291 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/12V, BIP, OP, RRIO, OVP, 2X +* Developed by: ARG / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 1.1 (02/2011) - Remove extraneous "(" in E4 line +* 1.0 (05/1994) +* Copyright 1994, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP291 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +I1 99 7 8.06E-6 +Q1 6 4 7 QP +Q2 5 3 7 QP +D1 3 99 DX +D2 4 99 DX +D3 3 4 DX +D4 4 3 DX +R1 3 8 5E3 +R2 4 2 5E3 +R3 5 50 6.4654E3 +R4 6 50 6.4654E3 +EOS 8 1 POLY(1) (16,39) -80E-6 1 +IOS 3 4 50E-12 +GB1 3 98 (21,98) 50E-9 +GB2 4 98 (21,98) 50E-9 +CIN 1 2 1E-12 +* +* 1ST GAIN STAGE +* +EREF 98 0 (39,0) 1 +G1 98 9 (6,5) 31.667E-6 +R7 9 98 1E6 +EC1 99 10 POLY(1) (99,39) -0.52 1 +EC2 11 50 POLY(1) (39,50) -0.52 1 +D5 9 10 DX +D6 11 9 DX +* +* 2ND GAIN STAGE AND DOMINANT POLE AT 36HZ +* +G2 98 12 (9,39) 8E-6 +R8 12 98 276.311E6 +C2 12 98 16E-12 +D7 12 13 DX +D8 14 12 DX +V1 99 13 0.58 +V2 14 50 0.58 +* +* COMMON MODE STAGE +* +ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 +R9 15 16 1E6 +R10 16 98 10 +* +* POLE AT 2.5MHZ +* +G3 98 18 (12,39) 1E-6 +R11 18 98 1E6 +C4 18 98 63.662E-15 +* +* BIAS CURRENT-VS-COMMON MODE VOLTAGE +* +EP 97 0 (99,0) 1 +VB 99 17 1.3 +RB 17 50 1E9 +E3 19 0 (15,17) 16 +D13 19 20 DX +R12 20 0 1E6 +G4 98 21 (20,0) 1E-3 +R13 21 98 5E3 +D14 21 22 DY +E4 97 22 POLY(1) (99,98) -0.765 1 +* +* POLE AT 100MHZ +* +G6 98 40 (18,39) 1E-6 +R20 40 98 1E6 +C10 40 98 1.592E-15 +* +* OUTPUT STAGE +* +RS1 99 39 109.375E3 +RS2 39 50 109.375E3 +RO1 99 45 41.667 +RO2 45 50 41.667 +G7 45 99 (99,40) 24E-3 +G8 50 45 (40,50) 24E-3 +G9 98 60 (45,40) 24E-3 +D9 60 61 DX +D10 62 60 DX +V7 61 98 DC 0 +V8 98 62 DC 0 +FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1 +D11 41 45 DZ +D12 45 42 DZ +V5 40 41 0.131 +V6 42 40 0.131 +.MODEL DX D() +.MODEL DY D(IS=1E-9) +.MODEL DZ D(IS=1E-6) +.MODEL QP PNP(BF=133.333) +.ENDS OP291 +*$ + + + + + + + + +* OP296 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 3/15V, BIP, OP, Low Pwr, RRIO, 2X +* Developed by: ARG / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (05/1995) +* Copyright 1995, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP296 1 2 99 50 49 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +IREF 21 50 1U +QB1 21 21 99 99 QP 1 +QB2 22 21 99 99 QP 1 +QB3 4 21 99 99 QP 1.5 +QB4 22 22 50 50 QN 2 +QB5 11 22 50 50 QN 3 +Q1 5 4 7 50 QN 2 +Q2 6 4 8 50 QN 2 +Q3 4 4 7 50 QN 1 +Q4 4 4 8 50 QN 1 +Q5 50 1 7 99 QP 2 +Q6 50 3 8 99 QP 2 +EOS 3 2 POLY(1) (17,98) 35U 1 +Q7 99 1 9 50 QN 2 +Q8 99 3 10 50 QN 2 +Q9 12 11 9 99 QP 2 +Q10 13 11 10 99 QP 2 +Q11 11 11 9 99 QP 1 +Q12 11 11 10 99 QP 1 +R1 99 5 50K +R2 99 6 50K +R3 12 50 50K +R4 13 50 50K +IOS 1 2 0.75N +C10 5 6 3.183P +C11 12 13 3.183P +CIN 1 2 1P +* +* GAIN STAGE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U +R10 15 98 251.641MEG +CC 15 49 8P +D1 15 99 DX +D2 50 15 DX +* +* COMMON MODE STAGE +* +ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 +R11 16 17 1E6 +R12 17 98 10 +* +* OUTPUT STAGE +* +ISY 99 50 20E-6 +EIN 35 50 POLY(1) (15,98) 1.42735 1 +Q24 37 35 36 50 QN 1 +QD4 37 37 38 99 QP 1 +Q27 40 37 38 99 QP 1 +R5 36 39 150K +R6 99 38 45K +Q26 39 42 50 50 QN 3 +QD5 40 40 39 50 QN 1 +Q28 41 40 44 50 QN 1 +QL1 37 41 99 99 QP 1 +R7 99 41 10.7K +I4 99 43 2U +QD7 42 42 50 50 QN 2 +QD6 43 43 42 50 QN 2 +Q29 47 43 44 50 QN 1 +Q30 44 45 50 50 QN 1.5 +QD10 45 46 50 50 QN 1 +R9 45 46 175 +Q31 46 47 48 99 QP 1 +QD8 47 47 48 99 QP 1 +QD9 48 48 51 99 QP 5 +R8 99 51 2.9K +I5 99 46 1U +Q32 49 48 99 99 QP 10 +Q33 49 44 50 50 QN 4 +.MODEL DX D() +.MODEL QN NPN(BF=120 VAF=100) +.MODEL QP PNP(BF=80 VAF=60) +.ENDS OP296 +* +.subckt OP27 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.4p ink=140 incm=.001p incmk=10 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 2p Rpar=20K noiseless +C6 3 1 1.375p Rpar=12G noiseless +A2 0 N006 M M M M N005 M OTA g=130u Iout=8u en=3n enk=2.7 Vlow=-1e308 Vhigh=1e308 Cout=2.5p +C10 N004 0 100p Rpar=1K noiseless +D1 N005 5 Y +D6 5 N005 Y +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N005 M 4 3 UVLO +D3 N005 3 X +D4 4 N005 X +D2 3 4 IQ +C7 1 4 1.375p Rpar=12G noiseless +C8 3 2 1.375p Rpar=12G noiseless +C9 2 4 1.375p Rpar=12G noiseless +B1 N004 0 I=1m*dnlim(uplim(V(2),V(3)-2.7,.1), V(4)+2.7, .1)+100n*V(2) +B2 0 N004 I=1m*dnlim(uplim(V(1),V(3)-2.7,.1), V(4)+2.7, .1)+100n*V(1) +C1 2 1 1.375p noiseless +D7 2 1 IN +G3 0 N006 N004 0 1.1m +L1 N006 0 30µ Rser=1K Cpar=1p Rpar=10K noiseless +C2 5 4 2p Rpar=20K noiseless +.model IN D(Ron=.2 Roff=6Meg Vfwd=.65 epsilon=.5 Vrev=.65 revepsilon=.5 noiseless) +.model X D(Ron=200K Roff=100G Vfwd=-2.5 epsilon=.1 noiseless) +.model Y D(Ron=10K Roff=1T Vfwd=.28 epsilon=.1 noiseless) +.model N VDMOS(Vto=-65m Kp=.3 Ksubthres=.1 mtriode=2 noiseless) +.model P VDMOS(Vto=65m Kp=.3 pchan Ksubthres=.1 mtriode=2 noiseless) +.model UVLO SW(Ron=1K Roff=30G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=.5m noiseless) +.ends OP27 +* +.subckt OP37 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.4p ink=140 incm=.001p incmk=10 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 2p Rpar=20K noiseless +C6 3 1 1.375p Rpar=12G noiseless +A2 0 N006 M M M M N005 M OTA g=130u Iout=8u en=3n enk=2.7 Vlow=-1e308 Vhigh=1e308 Cout=.3p +C10 N004 0 100p Rpar=1K noiseless +D1 N005 5 Y +D6 5 N005 Y +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N005 M 4 3 UVLO +D3 N005 3 X +D4 4 N005 X +D2 3 4 IQ +C7 1 4 1.375p Rpar=12G noiseless +C8 3 2 1.375p Rpar=12G noiseless +C9 2 4 1.375p Rpar=12G noiseless +B1 N004 0 I=1m*dnlim(uplim(V(2),V(3)-2.7,.1), V(4)+2.7, .1)+100n*V(2) +B2 0 N004 I=1m*dnlim(uplim(V(1),V(3)-2.7,.1), V(4)+2.7, .1)+100n*V(1) +C1 2 1 1.375p noiseless +D7 2 1 IN +G3 0 N006 N004 0 1.1m +L1 N006 0 30µ Rser=1K Cpar=1p Rpar=10K noiseless +C2 5 4 2p Rpar=20K noiseless +.model IN D(Ron=.2 Roff=6Meg Vfwd=.65 epsilon=.5 Vrev=.65 revepsilon=.5 noiseless) +.model X D(Ron=200K Roff=100G Vfwd=-2.5 epsilon=.1 noiseless) +.model Y D(Ron=10K Roff=1T Vfwd=.28 epsilon=.1 noiseless) +.model N VDMOS(Vto=-65m Kp=.3 Ksubthres=.1 mtriode=2 noiseless) +.model P VDMOS(Vto=65m Kp=.3 pchan Ksubthres=.1 mtriode=2 noiseless) +.model UVLO SW(Ron=1K Roff=30G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=.5m noiseless) +.ends OP37 +* +* OP413 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 4/30V, BIP, OP, Low Noise, Low Drift, 4X +* Developed by: ARG / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (03/1994) +* Copyright 1992, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP413 3 2 7 4 6 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +R3 4 19 1.5E3 +R4 4 20 1.5E3 +C1 19 20 5.31E-12 +I1 7 18 106E-6 +IOS 2 3 25E-09 +EOS 12 5 POLY(1) 51 4 25E-06 1 +Q1 19 3 18 PNP1 +Q2 20 12 18 PNP1 +CIN 3 2 3E-12 +D1 3 1 DY +D2 2 1 DY +EN 5 2 22 0 1 +GN1 0 2 25 0 1E-5 +GN2 0 3 28 0 1E-5 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +DN1 21 22 DEN +DN2 22 23 DEN +VN1 21 0 DC 2 +VN2 0 23 DC 2 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +DN3 24 25 DIN +DN4 25 26 DIN +VN3 24 0 DC 2 +VN4 0 26 DC 2 +* +* SECOND CURRENT NOISE SOURCE +* +DN5 27 28 DIN +DN6 28 29 DIN +VN5 27 0 DC 2 +VN6 0 29 DC 2 +* +* GAIN STAGE & DOMINANT POLE AT 2HZ +* +G2 34 36 19 20 2.65E-04 +R7 34 36 39E6 +V3 35 4 DC 6 +D4 36 35 DX +VB2 34 4 1.6 +* +* SUPPLY/2 GENERATOR +* +ISY 7 4 0.2E-3 +R10 7 60 40E3 +R11 60 4 40E3 +C3 60 0 1E-9 +* +* CMRR STAGE & POLE AT 6kHZ +* +ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8 +CCM 50 51 26.5E-12 +RCM1 50 51 1E6 +RCM2 51 4 1 +* +* OUTPUT STAGE +* +R12 37 36 1E3 +R13 38 36 500 +C4 37 6 20E-12 +C5 38 39 20E-12 +M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +D5 39 47 DX +D6 47 45 DX +Q3 39 40 41 QPA 8 +VB 7 40 DC 0.861 +R14 7 41 375 +Q4 41 7 43 QNA 1 +R17 7 43 15 +Q5 43 39 6 QNA 20 +Q6 46 45 6 QPA 20 +R18 46 4 15 +Q7 36 46 4 QNA 1 +M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 +* +* NONLINEAR MODELS USED +* +.MODEL DX D (IS=1E-15) +.MODEL DY D (IS=1E-15 BV=7) +.MODEL PNP1 PNP (BF=220) +.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) +.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 ++ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 ++ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12 ++ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) +.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 ++ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 ++ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 ++ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) +.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 ++ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 ++ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 ++ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33) +.ENDS OP413 + + + + + + +* OP491 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 2.7/12V, BIP, OP, RRIO, OVP, 4X +* Developed by: ARG / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (05/1994) +* Copyright 1994, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP491 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +I1 99 7 8.06E-6 +Q1 6 4 7 QP +Q2 5 3 7 QP +D1 3 99 DX +D2 4 99 DX +D3 3 4 DX +D4 4 3 DX +R1 3 8 5E3 +R2 4 2 5E3 +R3 5 50 6.4654E3 +R4 6 50 6.4654E3 +EOS 8 1 POLY(1) (16,39) -80E-6 1 +IOS 3 4 50E-12 +GB1 3 98 (21,98) 50E-9 +GB2 4 98 (21,98) 50E-9 +CIN 1 2 1E-12 +* +* 1ST GAIN STAGE +* +EREF 98 0 (39,0) 1 +G1 98 9 (6,5) 31.667E-6 +R7 9 98 1E6 +EC1 99 10 POLY(1) (99,39) -0.52 1 +EC2 11 50 POLY(1) (39,50) -0.52 1 +D5 9 10 DX +D6 11 9 DX +* +* 2ND GAIN STAGE AND DOMINANT POLE AT 36HZ +* +G2 98 12 (9,39) 8E-6 +R8 12 98 276.311E6 +C2 12 98 16E-12 +D7 12 13 DX +D8 14 12 DX +V1 99 13 0.58 +V2 14 50 0.58 +* +* COMMON MODE STAGE +* +ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 +R9 15 16 1E6 +R10 16 98 10 +* +* POLE AT 2.5MHZ +* +G3 98 18 (12,39) 1E-6 +R11 18 98 1E6 +C4 18 98 63.662E-15 +* +* BIAS CURRENT-VS-COMMON MODE VOLTAGE +* +EP 97 0 (99,0) 1 +VB 99 17 1.3 +RB 17 50 1E9 +E3 19 0 (15,17) 16 +D13 19 20 DX +R12 20 0 1E6 +G4 98 21 (20,0) 1E-3 +R13 21 98 5E3 +D14 21 22 DY +E4 97 22 POLY(1) (99,98) -0.765 1 +* +* POLE AT 100MHZ +* +G6 98 40 (18,39) 1E-6 +R20 40 98 1E6 +C10 40 98 1.592E-15 +* +* OUTPUT STAGE +* +RS1 99 39 109.375E3 +RS2 39 50 109.375E3 +RO1 99 45 41.667 +RO2 45 50 41.667 +G7 45 99 (99,40) 24E-3 +G8 50 45 (40,50) 24E-3 +G9 98 60 (45,40) 24E-3 +D9 60 61 DX +D10 62 60 DX +V7 61 98 DC 0 +V8 98 62 DC 0 +FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1 +D11 41 45 DZ +D12 45 42 DZ +V5 40 41 0.131 +V6 42 40 0.131 +.MODEL DX D() +.MODEL DY D(IS=1E-9) +.MODEL DZ D(IS=1E-6) +.MODEL QP PNP(BF=133.333) +.ENDS OP491 + + + + + + +* OP492 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 4.5/33V, BIP, OP, Low Cost, S SPLY, 4X +* Developed by: ARG / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (03/1995) +* Copyright 1993, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP492 2 1 99 50 34 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE AND POLE AT 40MHZ +* +I1 99 4 50E-6 +IOS 2 1 10E-9 +EOS 2 3 POLY(1) (21,30) 1.5E-3 75 +CIN 1 2 3E-12 +Q1 5 1 7 QP +Q2 6 3 8 QP +R3 5 50 2E3 +R4 6 50 2E3 +R5 4 7 966 +R6 4 8 966 +C1 5 6 .995E-12 +* +* GAIN STAGE +* +EREF 98 0 (30,0) 1 +G1 98 9 (5,6) 500E-6 +R7 9 98 210.819E3 +D1 9 10 DX +D2 11 9 DX +V1 99 10 .6 +V2 11 50 .6 +* +* ZERO/POLE AT 6MHZ/12MHZ +* +E1 12 98 (9,30) 2 +R8 12 13 1 +R9 13 98 1 +C3 12 13 26.526E-9 +* +* ZERO AT 15MHZ +* +E2 14 98 (13,30) 1E6 +R10 14 15 1E6 +R11 15 98 1 +C4 14 15 10.610E-15 +* +* COMMON MODE STAGE WITH ZERO AT 40KHZ +* +ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 +R20 20 21 1E6 +R21 21 98 1 +C5 20 21 3.979E-12 +* +* POLE AT 100MHZ +* +G2 98 16 (15,30) 1 +R12 16 98 1 +C6 16 98 1.592E-9 +* +* OUTPUT STAGE +* +RS1 99 30 1E6 +RS2 30 50 1E6 +ISY 99 50 .44E-3 +G3 31 50 POLY(1) (16,30) -1.635E-6 4E-6 +R16 31 50 1E6 +DCL 50 31 DZ +I2 99 32 250E-6 +RCL 33 50 56 +M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +CC 31 32 14E-12 +Q3 99 32 34 QNA +Q4 33 32 34 QPA +Q5 31 33 50 QNA +.MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 ++ ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 ++ ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 ++ CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 ++ CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) +.MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 ++ ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 ++ ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 ++ CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 ++ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) +.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 ++ TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 ++ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 ++ MJ=0.407 CJSW=0.5E-9 MJSW=0.33) +.MODEL QP PNP(BF=61.5) +.MODEL DX D +.MODEL DZ D(BV=3.6) +.ENDS OP492 + + + + + + +* OP495 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 3/30V, BIP, OP, RRO, S SPLY, 4X +* Developed by: ARG / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (02/1995) +* Copyright 1995, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP495 1 2 99 50 20 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +I1 99 4 2.016E-6 +R1 1 6 5E3 +R2 2 5 5E3 +CIN 1 2 2E-12 +IOS 1 2 0.5E-9 +D1 5 3 DZ +D2 6 3 DZ +EOS 7 6 POLY(1) (31,39) 30E-6 0.024 +Q1 8 5 4 QP +Q2 9 7 4 QP +R3 8 50 25.861E3 +R4 9 50 25.861E3 +* +* GAIN STAGE +* +R7 10 98 270E6 +G1 98 10 POLY(1) (9,8) -4.26712E-9 27.8E-6 +EREF 98 0 (39,0) 1 +R5 99 39 417E3 +R6 39 50 417E3 +* +* COMMON MODE STAGE +* +ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 +R12 30 31 1E6 +R13 31 98 100 +* +* OUTPUT STAGE +* +ISY 99 50 49E-6 +I2 18 50 1.59E-6 +V2 99 12 DC 2.2763 +Q4 10 14 50 QNA 1.0 +R11 14 50 33 +M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 +M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 +D8 10 22 DX +V3 22 50 DC 6 +M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 +Q5 17 17 99 QPA 1.0 +Q6 18 17 99 QPA 4.0 +R8 18 99 2.2E6 +Q7 18 19 99 QPA 1.0 +R9 99 19 8 +C2 18 99 20E-12 +M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 +M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 +D4 21 18 DX +V4 99 21 DC 6 +R10 10 11 6E3 +C3 11 20 54E-12 +.MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 ++ ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 ++ ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 ++ CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 ++ CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) +.MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 ++ ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 ++ ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 ++ CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 ++ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) +.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 ++ TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 ++ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 ++ MJ=0.407 CJSW=0.5E-9 MJSW=0.33) +.MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 ++ TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 ++ XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 ++ MJ=0.442 CJSW=0.4E-9 MJSW=0.33) +.MODEL DX D(IS=1E-15) +.MODEL DZ D(IS=1E-15, BV=7) +.MODEL QP PNP(BF=125) +.ENDS OP495 + + + + + + +* OP727 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/30V, BIP, OP, S SPLY, RRO, 2X +* Developed by: RM / ADSC, HH / ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.2 (04/2009) - Corrected EVP, EVN +* 1.1 (08/2000) +* Copyright 2000, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT OP727 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* PNP INPUT STAGE +* +Q1 5 7 3 PIX +Q2 6 2 3 PIX +RC1 5 50 8000 +RC2 6 50 8000 +C1 5 6 0.5E-12 +D1 3 8 DX +V1 99 8 DC 1.0 +I1 99 3 50E-6 +EOS 7 1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1 +IOS 2 1 1E-9 +* +* PSRR=120dB, ZERO AT 150Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 1E+6 +CPS3 72 73 1.06E-9 +RPS4 73 98 1 +* +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 15 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 0 2.6E-6 +* +* +* CMRR 110dB, ZERO AT 400Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 1E+6 +CCM1 21 22 0.397E-9 +RCM2 22 98 1 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (5,6) 0 28.8E-6 +R1 30 98 2.02E+8 +CF 45 30 50E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=0.329E-3 +M6 45 47 50 50 NOX L=1E-6 W=0.496E-3 +EG1 99 46 POLY(1) (98,30) 0.6299 1 +EG2 47 50 POLY(1) (30,98) 0.5739 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS OP727 + + + + + + +* OP747 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/30V, BIP, OP, S SPLY, RRO, 4X +* Developed by: RM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.2 (04/2009) - Corrected EVP, EVN +* 1.1 (08/2000) +* Copyright 2000, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT OP747 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* PNP INPUT STAGE +* +Q1 5 7 3 PIX +Q2 6 2 3 PIX +RC1 5 50 8000 +RC2 6 50 8000 +C1 5 6 0.5E-12 +D1 3 8 DX +V1 99 8 DC 1.0 +I1 99 3 50E-6 +EOS 7 1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1 +IOS 2 1 1E-9 +* +* PSRR=120dB, ZERO AT 150Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 1E+6 +CPS3 72 73 1.06E-9 +RPS4 73 98 1 +* +* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 15 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 0 2.6E-6 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* +* CMRR 110dB, ZERO AT 400Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 1E+6 +CCM1 21 22 0.397E-9 +RCM2 22 98 1 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (5,6) 0 28.8E-6 +R1 30 98 2.02E+8 +CF 45 30 50E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=0.329E-3 +M6 45 47 50 50 NOX L=1E-6 W=0.496E-3 +EG1 99 46 POLY(1) (98,30) 0.6299 1 +EG2 47 50 POLY(1) (30,98) 0.5739 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS OP747 + + + + + + +* OP77 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 6/30V, BIP, OP, Low Vos, Precision, 1X +* Developed by: JCB / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (12/1990) - Re-ordered subcircuit call out nodes to put the output node last. +* - Changed Ios from 0.3E-9 to 0.15E-9 +* - Added F1 and F2 to fix short circuit current limit. +* Copyright 1990, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP77 1 2 99 50 39 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE & POLE AT 6 MHZ +* +R1 2 3 5E11 +R2 1 3 5E11 +R3 5 97 0.0606 +R4 6 97 0.0606 +CIN 1 2 4E-12 +C2 5 6 218.9E-9 +I1 4 51 1 +IOS 1 2 0.15E-9 +EOS 9 10 POLY(1) 30 33 10E-6 1 +Q1 5 2 7 QX +Q2 6 9 8 QX +R5 7 4 0.009 +R6 8 4 0.009 +D1 2 1 DX +D2 1 2 DX +EN 10 1 12 0 1 +GN1 0 2 15 0 1 +GN2 0 1 18 0 1 +* +EREF 98 0 33 0 1 +EPLUS 97 0 99 0 1 +ENEG 51 0 50 0 1 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +DN1 11 12 DEN +DN2 12 13 DEN +VN1 11 0 DC 2 +VN2 0 13 DC 2 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +DN3 14 15 DIN +DN4 15 16 DIN +VN3 14 0 DC 2 +VN4 0 16 DC 2 +* +* SECOND CURRENT NOISE SOURCE +* +DN5 17 18 DIN +DN6 18 19 DIN +VN5 17 0 DC 2 +VN6 0 19 DC 2 +* +* FIRST GAIN STAGE +* +R7 20 98 1 +G1 98 20 5 6 59.91 +D3 20 21 DX +D4 22 20 DX +E1 97 21 POLY(1) 97 33 -2.4 1 +E2 22 51 POLY(1) 33 51 -2.4 1 +* +* GAIN STAGE & DOMINANT POLE AT 0.053 HZ +* +R8 23 98 6.01E9 +C3 23 98 500E-12 +G2 98 23 20 33 33.3E-6 +V1 97 24 1.3 +V2 25 51 1.3 +D5 23 24 DX +D6 25 23 DX +* +* NEGATIVE ZERO AT -4MHZ +* +R9 26 27 1 +C4 26 27 -39.75E-9 +R10 27 98 1E-6 +E3 26 98 23 33 1E6 +* +* COMMON-MODE GAIN NETWORK WITH ZERO AT 20 HZ +* +R13 30 31 1 +L2 31 98 7.96E-3 +G4 98 30 3 33 1.0E-7 +D7 30 97 DX +D8 51 30 DX +* +* POLE AT 2 MHZ +* +R14 32 98 1 +C5 32 98 79.5E-9 +G5 98 32 27 33 1 +* +* OUTPUT STAGE +* +R15 33 97 1 +R16 33 51 1 +GSY 99 50 POLY(1) 99 50 0.325E-3 0.0425E-3 +F1 34 0 V3 1 +F2 0 34 V4 1 +R17 34 99 400 +R18 34 50 400 +L3 34 39 2E-7 +G6 37 50 32 34 2.5E-3 +G7 38 50 34 32 2.5E-3 +G8 34 99 99 32 2.5E-3 +G9 50 34 32 50 2.5E-3 +V3 35 34 6.8 +V4 34 36 4.4 +D9 32 35 DX +D10 36 32 DX +D11 99 37 DX +D12 99 38 DX +D13 50 37 DY +D14 50 38 DY +* +* MODELS USED +* +.MODEL QX NPN(BF=417E6) +.MODEL DX D(IS=1E-15) +.MODEL DY D(IS=1E-15 BV=50) +.MODEL DEN D(IS=1E-12, RS=12.08K, KF=1E-17, AF=1) +.MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=1.55E-15, AF=1) +.ENDS OP77 + + + +* OP777 SPICE Macro-model Typical Values +* Description: Amplifier +* Generic Desc: 2.7/30V, BIP, OP, S SPLY, RRO, 1X +* Developed by: RM / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 1.2 (04/2009) - Corrected EVP, EVN +* 1.1 (08/2000) +* Copyright 2000, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT OP777 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* PNP INPUT STAGE +* +Q1 5 7 3 PIX +Q2 6 2 3 PIX +RC1 5 50 8000 +RC2 6 50 8000 +C1 5 6 0.5E-12 +D1 3 8 DX +V1 99 8 DC 1.0 +I1 99 3 50E-6 +EOS 7 1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1 +IOS 2 1 1E-9 +* +* PSRR=120dB, ZERO AT 150Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 1E+6 +CPS3 72 73 1.06E-9 +RPS4 73 98 1 +* +* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 15 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 0 2.6E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* +* CMRR 110dB, ZERO AT 400Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 1E+6 +CCM1 21 22 0.397E-9 +RCM2 22 98 1 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (5,6) 0 28.8E-6 +R1 30 98 2.02E+8 +CF 45 30 50E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=0.329E-3 +M6 45 47 50 50 NOX L=1E-6 W=0.496E-3 +EG1 99 46 POLY(1) (98,30) 0.6299 1 +EG2 47 50 POLY(1) (30,98) 0.5739 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS OP777 +* +.subckt ADHV4702-1 1 2 3 4 5 6 7 +C10 N005 0 .1f Rpar=100K noiseless +C16 N004 N006 24p +C7 4 1 3.95p Rser=1k noiseless +C4 2 1 12.9p Rser=1k noiseless +C13 4 5 10p +D1 3 4 DESD +D2 5 3 DESD +C20 N004 0 1p +D3 N004 0 DANTISAT +G4 0 N008 N007 0 1m +D5 2 4 DESD +D8 5 2 DESD +D11 1 4 DESD +D12 5 1 DESD +D13 2 1 DINCLP N=4 +C21 N008 0 7p Rpar=1k noiseless +R5 N006 0 1 noiseless +G3 0 N006 N009 Mid 1 +A6 N005 0 _SHDN 0 0 0 N007 0 OTA g=1m linear en=8n*(1+freq/10Meg)**1.9 enk=15 vlow=-1e309 vhigh=1e309 +C12 4 3 5p +C14 3 5 5p +G5 0 XX N004 0 1m +C9 XX 0 151.2p noiseless Rser=52.6 Rpar=1k +C1 1 5 3.95p Rser=1k noiseless +C3 4 2 3.95p Rser=1k noiseless +C5 2 5 3.95p Rser=1k noiseless +M1 N009 PG 4 4 PI temp=27 +D6 4 PG DLIMP +C6 4 PG 200f Rser=600k noiseless +B3 PG 4 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(100n-1.2u*(23.6*V(XX)-750m),100n,100n) +M2 N009 NG 5 5 NI temp=27 +D7 NG 5 DLIMN +C11 NG 5 200f Rser=600k noiseless +B4 5 NG I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(100n+1.2u*(23.6*V(XX)+650m),100n,100n) +C2 N007 0 7p Rpar=1k noiseless +C8 X3 0 7p Rpar=1k noiseless +C15 PG N009 3f +C17 N009 NG 3f +A2 0 N008 0 0 0 0 X3 0 OTA g=1m linear vlow=-1e308 vhigh=1e308 +C18 N012 0 100p Rpar=1k noiseless +C19 SLWFAC2 0 100p Rpar=100Meg noiseless +D9 N012 SLWFAC2 DRISE +D10 SLWFAC2 N012 DFALL +B5 0 N004 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*uplim(dnlim(703u*V(X3),-1.8m*uplim(V(SLWFAC2),1,50m),100u),1.8m*uplim(V(SLWFAC2),1,50m),100u) +B6 0 N012 I=uplim(dnlim(300u*ABS(V(X3))-200u,0,100u)+100u,2m,200u) +S1 N014 4 6 N014 SREG +R7 N014 7 400K noiseless +C22 6 7 1p +D14 N014 5 DBSD +C23 5 N014 1p +A3 7 6 0 0 0 0 _SHDN 0 SCHMITT vt=1.2 vh=400m trise=300u +S2 4 5 _SHDN 0 SPOW +B1 N005 0 I=10u*dnlim(uplim(V(2),V(4)-2.89,.1), V(5)+2.89, .1)+1n*V(2) +B2 0 N005 I=10u*dnlim(uplim(V(1),V(4)-2.9,.1), V(5)+2.9, .1)+1n*V(1) +R10 4 Mid 10Meg noiseless +R11 Mid 5 500Meg noiseless +A1 3 N009 N009 N009 N009 N009 3 N009 OTA g=1 iout=25m vlow=-1e308 vhigh=1e308 +.param vs=220 +.model PI VDMOS(Vto=-300m kp=8m mtriode=430m ksubthres=10m pchan noiseless) +.model NI VDMOS(Vto=300m kp=12m mtriode=430m ksubthres=10m noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=3.4 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=4.8 epsilon=100m noiseless) +.model DRISE D(Ron=1 Roff=10Meg vfwd= 0 epsilon=10m noiseless) +.model DFALL D(Ron=1 Roff=10Meg vfwd= 0 epsilon=10m ilimit=80u noiseless) +.model DINCLP D(Ron=250 Roff=100T vfwd=720m epsilon=800m vrev=720m revepsilon=800m noiseless) +.model DANTISAT D(Ron=100 Roff=127.3Meg vfwd=3 epsilon=100m vrev=3 revepsilon=100m noiseless) +.model SREG SW(level=2 Ron=10k Roff=1G vt=-5.2 vh=-100m noiseless) +.model DBSD D(Ron=10k Roff=1G vfwd=2 epsilon=300m ilimit=155.8u noiseless) +.model SPOW SW(Ron=100 Roff=10G vt=.5 vh=-.3 ilimit=890u noiseless) +.model DESD D(Ron=100 Roff=1g Vfwd=700m epsilon=500m noiseless) +.ends ADHV4702-1 +* +.subckt SSM2141 1 2 3 4 5 6 7 +M1 7 N004 6 6 N temp=27 +M2 4 N004 6 6 P temp=27 +C3 7 6 2p +C4 6 4 2p +A2 0 N007 M M M M N004 M OTA g=41u Isrc=10u en=10n enk=150 Vlow=-1e308 Vhigh=1e308 Cout= 1p +C10 N003 0 20p Rpar=1K noiseless +D1 N004 6 Y +D6 6 N004 Y N=.525 +G1 0 M 7 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N004 M 4 7 UVLO +D3 N004 7 X +D4 4 N004 X +L2 N003 N007 20µ +C2 N007 0 20p Rpar=1K noiseless +D2 7 4 IQ +B1 N003 0 I=2m*dnlim(uplim(V(A),V(7)-4,.1), V(4)+4, .1)+100n*V(A) +B2 0 N003 I=2m*dnlim(uplim(V(B),V(7)-4,.1), V(4)+4, .1)+100n*V(1) +R2 A 2 25K +R1 B 3 25K +R4 5 A 25K +R5 1 B 25K +.model X D(Ron=1K Roff=100G Vfwd=-2.57 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=2.2 epsilon=.1 noiseless) +.model N VDMOS(Vto=-250m Kp=15m Ksubthres=.2 noiseless) +.model P VDMOS(Vto=250m Kp=15m pchan Ksubthres=.2 noiseless) +.model UVLO SW(Ron=1K Roff=100G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=1.8m noiseless) +.ends SSM2141 +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +.subckt AD820 1 2 3 4 5 +A1 N009 0 0 0 0 0 N005 0 OTA g=66u Iout=40u Vhigh=1e308 Vlow=-1e308 +C12 3 2 .25p Rser=2k noiseless +B3 0 N006 I=1m*dnlim(uplim(V(1),V(3)-.9,.1), V(4)-.2, .1)+100n*V(1)-941.26p +B4 N006 0 I=1m*dnlim(uplim(V(2),V(3)-.91,.1), V(4)-.21, .1)+100n*V(2) +C4 N006 0 1f Rpar=1K noiseless +D1 3 4 IQ +R5 2 1 10T noiseless +C2 N005 N008 10p +C3 N005 0 100f +D2 N005 0 DANTISAT1 +G2 0 N008 5 Mid 1 +R4 N008 0 1 noiseless +R6 3 Mid 312.5k noiseless +R7 Mid 4 312.5k noiseless +C6 N004 0 {C1_P1} Rpar={1/alpha_P1} noiseless +G5 0 N009 N004 0 {alpha_P1} +M1 5 PG 3 3 PI temp=27 +M2 5 NG 4 4 NI temp=27 +D3 3 PG DLIMP +D4 NG 4 DLIMN +C8 3 PG 10f Rser=400k noiseless +C9 NG 4 10f Rser=400k noiseless +B2 4 NG I=dnlim(vminn/1e6+1.8u*(V(XX)+voffn),vminn/1e6,100n) +B5 PG 3 I=dnlim(vminp/1e6-1.8u*(V(XX)-voffp),vminp/1e6,100n) +C13 3 5 1p +C15 5 4 1p +D5 N005 0 DANTISAT2 +G1 2 3 2 3 10m vto=300m dir=1 +G6 1 3 1 3 10m vto=300m dir=1 +G7 4 2 4 2 10m vto=21 dir=1 +G8 4 1 4 1 10m vto=21 dir=1 +C16 2 1 2.8p Rser=1k noiseless +C17 N007 4 1p Rpar=1k noiseless +G9 4 N007 3 4 .5m +I1 4 N007 5m +D10 N007 2 DBIAS2 +D11 N007 1 DBIAS2 +D6 3 2 DBIAS1 +D7 3 1 DBIAS1 +G10 0 VBD1 3 0 50µ +C18 VBD1 0 1p Rpar=1k noiseless +G11 VBD1 0 2 0 25µ +G12 VBD1 0 1 0 25µ +I2 VBD1 0 400µ +D12 VBD2 0 DBIAS3 temp=27 +R8 VBD2 VBD1 1k noiseless +G13 3 2 VBD1 VBD2 1.6n +G14 3 1 VBD1 VBD2 1.6n +C19 XX 0 {C1_PZ1} Rpar={R2_PZ1} Rser={R1_PZ1} noiseless +G15 0 XX N005 0 {alpha_PZ1*1.3} +A3 0 N006 0 0 0 0 N004 0 OTA g=20u linear en=13n enk=45 vlow=-1e308 vhigh=1e308 +C1 N009 0 {C1_P1} Rpar={1/alpha_P1} noiseless +A4 0 2 0 0 0 0 0 0 OTA g=0 in=.8f ink=.5 +A2 0 1 0 0 0 0 0 0 OTA g=0 in=.8f ink=.5 +C5 2 4 .25p Rser=2k noiseless +C7 3 1 .25p Rser=2k noiseless +C10 1 4 .25p Rser=2k noiseless +G3 2 3 2 3 10µ vto=-800m dir=1 +G4 1 3 1 3 10µ vto=-800m dir=1 +.model DANTISAT1 D(Ron=10Meg Roff=95.6Meg vfwd=100m epsilon=100m vrev=100m revepsilon=100m noiseless) +.model DANTISAT2 D(Ron=1k Roff=95.6Meg vfwd=4 epsilon=100m vrev=4 revepsilon=100m noiseless) +.param alpha_PZ1=1.0e-3 pole_PZ1=150k zero_PZ1=700k ++ R2_PZ1=1.0/alpha_PZ1 R1_PZ1=1.0/(alpha_PZ1*(zero_PZ1/pole_PZ1 - 1.0)) ++C1_PZ1=1.0/(2.0*pi*zero_PZ1*R1_PZ1) +.param alpha_P1=1.0e-5 pole_P1=11.0e6 ++ C1_P1 = alpha_P1/(2*pi*pole_P1) +.param vadj = -12m +.param vminp = 418m +.param voffp = {45m+vadj} +.param vminn=400m +.param voffn ={5m-vadj} +.model NI VDMOS(VTO=300m mtriode=1.1 KP=45m ksubthres=10m lambda=.001 noiseless) +.model PI VDMOS(VTO=-300m mtriode=.65 KP=36m ksubthres=10m lambda=.001 pchan noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=1.5 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=1.4 epsilon=100m noiseless) +.model DBIAS1 D(Ron=1k Roff=10T vfwd=0 epsilon=100m ilimit=1p noiseless) +.model DBIAS2 D(Ron=5T Roff=30T vfwd=500m epsilon=100m noiseless) +.model DBIAS3 D(IS=1e-18 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=53.13u noiseless) +.ends AD820 + +* +.subckt AD8205 1 2 3 4 5 6 7 8 +R4 1 N003 150K +R5 N003 N009 38K +R6 N009 2 12K +R7 8 N006 150K +R8 N006 N011 38K +R9 N011 2 12K +R13 7 N011 {2*REF} +R14 N011 3 {2*REF} +R1 5 N009 {REF} +D1 2 N006 X +D2 2 N003 X +Q1 5 N005 6 0 P temp=27 +D3 5 2 301uA +A2 N006 N003 6 6 6 6 N004 6 OTA Vhigh=0 Vlow=-1 G=1.35m Cout=200n en=.25u Iout=6000u epsilon=.1 +S1 6 N004 2 6 UV +R3 N005 N004 500K noiseless +C2 7 2 3p +C1 8 2 3p +C3 5 2 3p +C4 6 2 3p +C5 1 2 3p +C6 3 2 3p +I1 6 5 1µ load +D4 6 2 IQ +.param Ref = 1.791Meg +.model X D(Ron=10 Vfwd=.5 epsilon=.1 Vrev=16.23 revepsilon=1 noiseless) +.model 301uA D(Ron=25 Vfwd=48m epsilon=50m Ilimit=301u noiseless) +.model P PNP(BF=100K noiseless) +.model UV SW(Ron=100 Roff=1T Vt=.3 Vh=-.5 noiseless) +.model IQ D(Ron=1K epsilon=1 Ilimit=1.25m noiseless) +.ends AD8205 +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +.subckt AD8479 1 2 3 4 5 6 7 +M1 7 N004 6 6 N temp=27 +M2 4 N004 6 6 P temp=27 +C3 7 6 2p +C4 6 4 2p +A2 0 N007 M M M M N004 M OTA g=100u Isrc=10.1u en=10n enk=2.3 Vlow=-1e308 Vhigh=1e308 Cout=1.1p +C10 N003 0 2p Rpar=1K noiseless +D1 N004 6 Y +D6 6 N004 Y +G1 0 M 7 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N004 M 4 7 UVLO +D3 N004 7 X +D4 4 N004 X +D2 7 4 IQ +B1 N003 0 I=2m*dnlim(uplim(V(A),V(7)-4,.1), V(4)+4, .1)+100000n*V(A) +B2 0 N003 I=2m*dnlim(uplim(V(B),V(7)-4,.1), V(4)+4, .1)+100000n*V(B) +R2 A 2 1060310.61 +R1 B N009 530155.305 +R4 6 N001 118694 +R5 5 B 17671.43509 +R7 N009 3 530155.305 +R8 N001 A 15693.6 +R9 N001 1 2011.7645 +L1 N003 N007 2µ +C2 N007 0 2p Rpar=1K noiseless +C1 N009 0 35e-16 +C5 A B 5.2p +I1 A 2 4.7156e-10 +.model X D(Ron=100 Roff=100G Vfwd=-0.1 epsilon=.1 noiseless) +.model Y D(Ron=100 Roff=1T Vfwd=2.36 epsilon=.1 noiseless) +.model N VDMOS(Vto=-250m Kp=16m Ksubthres=.1 noiseless) +.model P VDMOS(Vto=250m Kp=16m pchan Ksubthres=.1 noiseless) +.model UVLO SW(Ron=1K Roff=100G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=18u noiseless) +.ends AD8479 + + diff --git a/spice/copy/sub/ADI1.lib b/spice/copy/sub/ADI1.lib new file mode 100755 index 0000000..03dde1b --- /dev/null +++ b/spice/copy/sub/ADI1.lib @@ -0,0 +1,9079 @@ +* Copyright (c) 1998-2019 Analog Devices, Inc. All rights reserved. +* +.subckt AD549 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.11f ink=1 incm=.0011f incmk=1 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 2p +C4 5 4 2p +C6 3 1 .2p Rpar=4000T noiseless +C7 1 4 .2p noiseless Rpar=4000T +C8 2 4 .2p Rpar=4000T noiseless +C9 3 2 .2p Rpar=4000T noiseless +A2 0 N006 M M M M N005 M OTA g=36u Iout=17u en=35n enk=55 Vlow=-1e308 Vhigh=1e308 Cout= 5.5p +D1 N005 5 Y +D6 5 N005 Y +C1 2 1 .8p Rpar=10T noiseless +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N005 M 4 3 UVLO +D3 N005 3 X +D4 4 N005 X +B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)-.8,.1), V(4)+3, .1)+100n*V(1) +B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)-1.25,.1), V(4)+3, .1)+100n*V(2) +C12 N004 0 20p Rpar=1K noiseless +C2 N006 0 20p Rpar=1K noiseless +L1 N004 N006 20µ +.model X D(Ron=5K Roff=100G Vfwd=-1.25 epsilon=.1 noiseless) +.model Y D(Ron=5K Roff=1T Vfwd=2.5 epsilon=.1 noiseless) +.model N VDMOS(Vto=-250m Kp=4m Ksubthres=.1 noiseless) +.model P VDMOS(Vto=250m Kp=4m pchan Ksubthres=1. noiseless) +.model UVLO SW(Ron=1K Roff=100G Vt=-3.75 Vh=.25 noiseless) +.ends AD549 +* +.subckt AD712 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.01p ink=10 incm=.001p incmk=10 +M1 3 N006 5 5 N temp=27 +M2 4 N006 5 5 P temp=27 +C3 3 5 2p +C4 5 4 2p +C6 3 1 1.375p Rpar=750G noiseless +A2 0 N005 M M M M N006 M OTA g=130u Isrc=90u Isink=-120u en=16n enk=100 Vlow=-1e308 Vhigh=1e308 Cout= 4p asym +C10 N005 0 .5p Rpar=1K noiseless +D1 N006 5 Y +D6 5 N006 Y +C1 2 1 4.125p noiseless +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N006 M 4 3 UVLO +D3 N006 3 X +D4 4 N006 X +D2 3 4 IQ +C7 1 4 1.375p Rpar=750G noiseless +C8 3 2 1.375p Rpar=750G noiseless +C9 2 4 1.375p Rpar=750G noiseless +I1 1 4 25p load +I2 2 4 25p load +B1 N005 0 I=1m*dnlim(uplim(V(2),V(3)-1,.1), V(4)+3.5, .1)+100n*V(2) +B2 0 N005 I=1m*dnlim(uplim(V(1),V(3)-1,.1), V(4)+3.5, .1)+100n*V(1) +.model X D(Ron=10K Roff=100G Vfwd=-1.25 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=2.86 epsilon=.1 noiseless) +.model N VDMOS(Vto=-250m Kp=5m Ksubthres=.2 noiseless) +.model P VDMOS(Vto=250m Kp=5m pchan Ksubthres=.2 noiseless) +.model UVLO SW(Ron=1K Roff=5G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=4.7m noiseless) +.ends AD712 +* +.subckt AD746 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.01p ink=10 incm=.001p incmk=10 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 2p +C4 5 4 2p +C6 3 1 1.375p Rpar=62.5G noiseless +D1 N005 5 Y +D6 5 N005 Y +C1 2 1 4.125p noiseless +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N005 M 4 3 UVLO +D3 N005 3 X +D4 4 N005 X +D2 3 4 IQ +C7 1 4 1.375p Rpar=62.5G noiseless +C8 3 2 1.375p Rpar=62.5G noiseless +C9 2 4 1.375p Rpar=62.5G noiseless +I1 1 4 110p load +I2 2 4 110p load +B1 N004 0 I=2m*dnlim(uplim(V(2),V(3)-0.5,.1), V(4)+3.5, .1)+100n*V(2) +B2 0 N004 I=2m*dnlim(uplim(V(1),V(3)-0.5,.1), V(4)+3.5, .1)+100n*V(1) +A2 0 N006 M M M M N005 M OTA g=130u Isrc=180u en=16n enk=100 Vlow=-1e308 Vhigh=1e308 Cout= 1.4p Isink=-120u asym +C5 N004 0 5p Rpar=1K noiseless +C10 N006 0 5p Rpar=1K noiseless +L1 N004 N006 5µ +.model X D(Ron=10K Roff=100G Vfwd=-1.25 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=2.86 epsilon=.1 noiseless) +.model N VDMOS(Vto=-250m Kp=5m Ksubthres=.2 noiseless) +.model P VDMOS(Vto=250m Kp=5m pchan Ksubthres=.2 noiseless) +.model UVLO SW(Ron=1K Roff=3G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=4.7m noiseless) +.ends AD746 +* +.subckt AD795 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.6f ink=250 incm=.06f incmk=250 +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C3 3 5 2p +C4 5 4 2p +B1 0 N003 I=2m*dnlim(uplim(V(1),V(3)-.15,.1), V(4)+4, .1)+100n*V(1) +B2 N003 0 I=2m*dnlim(uplim(V(2),V(3)-.15,.1), V(4)+4, .1)+100n*V(2) +C6 3 1 .55p Rpar=400T noiseless +C7 1 4 .55p noiseless Rpar=400T +C8 2 4 .55p Rpar=400T noiseless +C9 3 2 .55p Rpar=400T noiseless +A2 0 N006 M M M M N004 M OTA g=36u Isrc=8u Isink=-5u en=9n enk=200 Vlow=-1e308 Vhigh=1e308 Cout= 4.3p asym +C10 N003 0 22p Rpar=1K noiseless +D1 N004 5 Y +D6 5 N004 Y +C1 2 1 1.45p Rpar=1.01T noiseless +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N004 M 4 3 UVLO +D3 N004 3 X +D4 4 N004 X +L1 N003 N005 22µ +L2 N005 N006 22µ +C2 N006 0 22p Rpar=1K noiseless +C5 N005 0 44p +D2 3 4 IQ +.model X D(Ron=1K Roff=100G Vfwd=-2.5 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=2.2 epsilon=.1 noiseless) +.model N VDMOS(Vto=-250m Kp=5m Ksubthres=.2 noiseless) +.model P VDMOS(Vto=250m Kp=5m pchan Ksubthres=.2 noiseless) +.model UVLO SW(Ron=1K Roff=100G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=1m noiseless) +.ends AD795 +* +.subckt AD820 1 2 3 4 5 +C1 N006 X {Cf} +A1 N005 0 M M M M X M OTA g={Ga} Iout={Islew} en=13n enk=20 Vhigh=1e308 Vlow=-1e308 +D21 X 3 ESD +D22 4 X ESD +D5 N006 3 X1 +D6 4 N006 X2 +C2 3 N006 1p +C3 N006 4 1p +G2 0 M 3 0 500µ +R4 M 0 1K noiseless +G3 0 M 4 0 500µ +S1 X M 4 3 SD +A2 2 1 0 0 0 0 0 0 OTA g=0 in=.8f ink=1 incm=.08f incmk=1 +I1 1 4 2p load +I2 2 4 2p load +C11 3 1 .7p Rpar=40T noiseless +C5 1 4 .7p Rpar=40T noiseless +C10 2 4 .7p Rpar=40T noiseless +C12 3 2 .7p Rpar=40T noiseless +B3 0 N004 I=2m*dnlim(uplim(V(1),V(3)-1,.1), V(4)+-.2, .1)+100n*V(1) +B4 N004 0 I=2m*dnlim(uplim(V(2),V(3)-1,.1), V(4)+-.2, .1)+100n*V(2) +C4 N004 0 35p Rpar=1K noiseless +D1 3 4 IQ +L1 N004 N005 35µ +C6 N005 0 35p Rpar=1K noiseless +C7 3 5 1p +C8 5 4 1p +R5 2 1 13.35T noiseless +B1 3 N006 I=if(V(m,x)>=0, V(m,x)*(Gb+Gbx*V(m,x)),0) +B2 N006 4 I=if(V(x,m)>0, V(x,m)*(Gb+Gbx*V(x,m)),0) +D2 N006 N007 20Ohm +D3 5 N007 45mA +C9 3 N007 1p +C13 N007 4 1p +.param Cf = 1p +.param Ro = 1Meg +.param Avol = 60K +.param RL = 2K +.param AVmid = 200 +.param FmidA = 10K +.param Zomid = .3 +.param FmidZ = 10K +.param Iout = 25m +.param Vslew = 4Meg +.param Vmin = 2.5 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.param Gbx = 50*Gb +.model ESD D(Ron=10 Roff=1T Vfwd=0 epsilon=1 noiseless) +.model X1 D(Ron=1m Roff={2*Ro} Vfwd=-3m epsilon=10m noiseless) +.model X2 D(Ron=1m Roff={2*Ro} Vfwd=-6m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-100m noiseless) +.model 20Ohm D(Ron=10 Roff=30 epsilon=10m noiseless) +.model 45mA D(Ron=10 Vrev=0 Ilimit=45m revIlimit=45m) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=.7m noiseless) +.ends AD820 +* +*AD8682 Macro-model +*Revision History: +*Rev.1 Nov 2016-ZZ +*Copyright 2016 by Analog Devices +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +.Subckt AD8682 100 101 102 103 104 +* +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.44e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 3.96e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 2.5e-3 +IbiasP 110 2 dc 2e-12 +IbiasN 110 9 dc 2e-12 +RinCMP 110 2 Rideal 2000e6 +RinCMN 9 110 Rideal 2000e6 +CinCMP 110 2 2.2e-12 +CinCMN 9 110 2.2e-12 +IOS 9 2 1e-15 +RinDiff 9 2 Rideal 10000e3 +CinDiff 9 2 0.8e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 0.46 +VinN 42 112 dc 4.46 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -6.325e-9 +Lcmrr 11 12 15.9e-3 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2 +VPD1 81 0 dc 1.5 +RPD 111 106 Rideal 1e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 0.08 Hz*** +g210 210 110 200 110 0.0636e-6 +R210 210 110 Rideal 1989.43e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 6.095 +VoutN 64 66 dc 6.095 +e60 65 110 111 110 1 +e61 66 110 112 110 1 +* +* +***Pole at 12MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 13.2629e-12 +* +***Pole at 12MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 13.2629e-12 +* +***Pole at 12MHz*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +C240 240 110 13.2629e-12 +* +***Pole at 50MHz*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +C245 245 110 3.1831e-12 +* +***Pole at 50MHz*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +C250 250 110 3.1831e-12 +* +***Pole at 50MHz*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +C255 255 110 3.1831e-12 +* +***Pole at 50MHz*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +C260 260 110 3.1831e-12 +* +***Pole at 50MHz*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +C265 265 110 3.1831e-12 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +* +***Peak: f=50MHz, Zeta=0.7, Gain=0.2dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 22.736e-9 +C290 291 292 445.633e-12 +R291 292 110 Rideal 429.314 +e295 295 110 292 110 1.0233 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal .3 +Lout 303 310 1e-9 +Cout 310 110 1e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc -0.364 +VIoutN 304 306 dc 0.136 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 1.785 +VoutN1 74 112 dc 1.785 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=142.026) +.model DzSlewN D(BV=142.026) +.model DVnoisy D(IS=4.90e-14 KF=3.04e-18) +.model DINnoisy D(IS=3.81e-21 KF=0.00e0) +.model DIPnoisy D(IS=3.81e-21 KF=0.00e0) +.model Rideal res(T_ABS=-273) +* +.ends +*AD8684 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.1 Nov 2016-ZZ +*Copyright 2016 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Quiescent and dynamic supply currents, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +.Subckt AD8684 100 101 102 103 104 +*#ASSOC Category="Op-amps" symbol=opamp +* +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.44e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 3.96e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 3.5e-3 +IbiasP 110 2 dc 5e-12 +IbiasN 110 9 dc 5e-12 +RinCMP 110 2 Rideal 2000e6 +RinCMN 9 110 Rideal 2000e6 +CinCMP 110 2 2.2e-12 +CinCMN 9 110 2.2e-12 +IOS 9 2 10e-15 +RinDiff 9 2 Rideal 10000e3 +CinDiff 9 2 0.8e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 0.46 +VinN 42 112 dc 4.46 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -6.325e-9 +Lcmrr 11 12 22.59e-3 +Rcmrr 12 110 Rideal 5e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2 +VPD1 81 0 dc 1.5 +RPD 111 106 Rideal 1e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 0.08 Hz*** +g210 210 110 200 110 0.0636e-6 +R210 210 110 Rideal 1989.43e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 6.095 +VoutN 64 66 dc 6.095 +e60 65 110 111 110 1 +e61 66 110 112 110 1 +* +* +***Pole at 12MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 13.2629e-12 +* +***Pole at 12MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 13.2629e-12 +* +***Pole at 12MHz*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +C240 240 110 13.2629e-12 +* +***Pole at 50MHz*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +C245 245 110 3.1831e-12 +* +***Pole at 50MHz*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +C250 250 110 3.1831e-12 +* +***Pole at 50MHz*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +C255 255 110 3.1831e-12 +* +***Pole at 50MHz*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +C260 260 110 3.1831e-12 +* +***Pole at 50MHz*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +C265 265 110 3.1831e-12 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +* +***Peak: f=50MHz, Zeta=0.7, Gain=0.2dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 22.736e-9 +C290 291 292 445.633e-12 +R291 292 110 Rideal 429.314 +e295 295 110 292 110 1.0233 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal .3 +Lout 303 310 1e-9 +Cout 310 110 1e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc -0.364 +VIoutN 304 306 dc 0.136 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 1.785 +VoutN1 74 112 dc 1.785 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=142.026) +.model DzSlewN D(BV=142.026) +.model DVnoisy D(IS=4.90e-14 KF=3.04e-18) +.model DINnoisy D(IS=3.81e-21 KF=0.00e0) +.model DIPnoisy D(IS=3.81e-21 KF=0.00e0) +.model Rideal res(T_ABS=-273) +* +.ends AD8684 + +* ADA4091 SPICE Macro-model +* Developed by: HH / AD-SJ +* Revision History: 08/10/2012 - Updated to new header style +* 05/14/2014 - ported to Simplis (JSW) +* 0.0 (04/2009) +* Copyright 2008, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT ADA4091 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +I1 99 7 8.00E-06 +Q1 6 4 7A QP +Q2 5 3 7B QP +RE1 7A 7 7.774E+02 +RE2 7B 7 7.774E+02 +D1 3 99 DX +D2 4 99 DX +D3 50 3 DX +D4 50 4 DX +D5 3 4 DX +D6 4 3 DX +R1 3 8 5E+03 +R2 4 2 5E+03 +R3 5 50 7.500E4; +R4 6 50 7.500E4; +Cph 5 5A 0.235E-12 +Rph 5A 6 300 +EOS 8 1 POLY(4) (73,98) (22,98) (81,98) (83,98) -400E-9 1 1 1 1 +IOS 3 4 -50E-12 +CDiff 1 2 2.5E-12 +Cin1 1 50 2E-12 +Cin2 2 50 2E-12 +* +* INPUT PROTECTION NETWORK +* +X_in1 1 50 Diac1 +X_in2 2 50 Diac1 +X_in3 1 99 Diac1 +X_in4 2 99 Diac1 +* +* +RS1 99 39 400.0E3 +RS2 39 50 400.0E3 +EREF 98 0 (39,0) 1 +* +* 1ST GAIN STAGE +* +G1 9 98 (6,5) 1.0E-06 +R7 9 98 1E6 +* +* 2ND GAIN STAGE AND DOMINANT POLE +* +R8 12 98 1.094E+08 +G2 12 98 (98,9) 3.881E-06 +D7 12 13 DX +D8 14 12 DX +V1 13 98 +0.2; source +V2 14 98 -0.2; sink +* +* Provision for second pole +* +G3 18 98 (98,12) 1E-05 +R11 18 98 1E5 +* +* CMRR=90dB, Pole at 1100 Hz +* +ECM 21 98 POLY(2) (1,98) (2,98) 0 1.318E-01 1.318E-01 +R10 21 22 1.326E+05 +R20 22 98 1.592E+01 +C10 21 22 1E-9 +* +* PSRR=85dB, POLE AT 300 Hz +* +EPSY 72 98 POLY(1) (99,50) +0.1E-1 1.770E+01 +RPS1 72 73 7.958E+02 +RPS2 73 98 3.183E-03 +CPS1 72 73 1.00E-06 +* +* VOLTAGE NOISE REFERENCE OF 24nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 96.300E-3 +HN 81 98 VN1 2.397E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 300 Hz +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* OUTPUT STAGE +* +Q3 451 41 99 POUT +RB1 40 41 1.5E+03 +EB1 99 40 POLY(1) (98,18) 6.190E-01 1E-0; +Q4 451 43 50 NOUT +RB2 42 43 2.0E+03 +EB2 42 50 POLY(1) (18,98) 6.155E-01 1E-0; +Lout 45 451 10E-10 +RZ 45 453 100 +CZ 453 12 4.67E-12 +* +GSY 99 50 POLY(1) (99 50) 106.2E-6 -0.89E-06 +* +* MODELS +* +.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130) +.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130,IK=6E+00,BR=15,VAR=14.4, RC=30) +.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250,IK=11E+00,BR=30, VAR=20.0, RC=7) +.MODEL DW D(IS=1E-18) +.MODEL DX D() +.MODEL DY D(IS=1E-9) +.MODEL DZ D(IS=1E-6) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=8.640E-12) +* +.SUBCKT Diac1 1 2 +Done 1 3 DZ42hh +Dtwo 2 3 DZ42hh +.MODEL DZ42hh D(IS=3.3179E-6, N=2.0, RS=1.0000E-3, CJO=10.00E-12, M=.31349, VJ=.3905, ISR=2.9061E-9, BV=42.0, IBV=5.0E-03, TT=300.0E-9) +.ENDS Diac1 +* +* +.ENDS ADA4091 +* +* ADA4092 SPICE Macro-model +* Developed by: HH / AD-SJ +* Revision History: 08/10/2012 - Updated to new header style +* 05/14/2014 - Ported to Simplis (JSW) +* 0.0 (12/2010) +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT ADA4092 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +Q1 6 4 7A QP +Q2 5 3 7B QP +RE1 7A 7 5.656E+02 +RE2 7B 7 5.656E+02 +I1 99 7 8.00E-06 +D1 3 99 DX +D2 4 99 DX +D3 50 3 DX +D4 50 4 DX +D5 3 4 DX +D6 4 3 DX +R1 3 8 5E+03 +R2 4 2 5E+03 +R3 5 50 7.500E4; +R4 6 50 7.500E4; +Cph 5 5A 0.23E-12 +Rph 5A 6 300 +EOS 8 1 POLY(4) (73,98) (22,98) (81,98) (83,98) -1.4E-03 1 1 1 1 +IOS 3 4 -2.0E-09 +CDiff 1 2 2.5E-12 +Cin1 1 50 2E-12 +Cin2 2 50 2E-12 +* +* INPUT PROTECTION NETWORK +* +X_in1 1 50 Diac1 +X_in2 2 50 Diac1 +X_in3 1 99 Diac1 +X_in4 2 99 Diac1 +* +* +RS1 99 39 400.0E3 +RS2 39 50 400.0E3 +EREF 98 0 (39,0) 1 +* +* 1ST GAIN STAGE +* +R7 9 98 3.266E+08 +G1 9 98 (6,5) 4.303E-06 +D7 9 13 DX +D8 14 9 DX +V1 13 98 0.37; sink +V2 14 98 +0.017; source +* +* 2ND GAIN STAGE AND DOMINANT POLE +* +R8 12 98 1.0E+06 +G2 12 98 (98,9) 1.0E-06 +* +* Provision for second pole +* +G3 18 98 (98,12) 1E-05 +R11 18 98 1E5 +* +* CMRR +* +ECM 21 98 POLY(2) (1,98) (2,98) 0 7.813E-02 7.813E-02 +R10 21 22 2.487E+04 +R20 22 98 1.592E+01 +C10 21 22 1E-9 +* +* PSRR +* +EPSY 72 98 POLY(1) (99,50) +0.1E-6 1.485E+01 +RPS1 72 73 5.305E+02 +RPS2 73 98 3.183E-03 +CPS1 72 73 1.00E-06 +* +* VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 25.5E-3 +HN 81 98 VN1 3.0E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* OUTPUT STAGE +* +Q3 451 41 99 POUT +RB1 40 41 1.5E+03 +EB1 99 40 POLY(1) (98,18) 6.190E-01 1E-0; +Q4 451 43 50 NOUT +RB2 42 43 2.0E+03 +EB2 42 50 POLY(1) (18,98) 6.155E-01 1E-0; +Lout 45 451 6.2E-12 +RZ 451 453 100 +CZ 453 9 4.6E-12 +* +GSY 99 50 POLY(1) (99 50) 79.9E-6 -1.04E-06 +* +* MODELS +* +.MODEL QP PNP(BF=80, IS=1.00E-16, VA=130) +.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130, BR=3,VAR=15, RC=38); +.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250, BR=7, VAR=20, RC=8); +.MODEL DW D(IS=1E-18) +.MODEL DX D() +.MODEL DY D(IS=1E-9) +.MODEL DZ D(IS=1E-6) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.15E-12) +* +.SUBCKT Diac1 1 2 +Done 1 3 DZ42hh +Dtwo 2 3 DZ42hh +.MODEL DZ42hh D(IS=3.3179E-6, N=2.0, RS=1.0000E-3, CJO=10.00E-12, M=.31349, VJ=.3905, ISR=2.9061E-9, BV=42.0, IBV=5.0E-03, TT=300.0E-9) +.ENDS Diac1 +.ENDS ADA4092 +* +* ADA4096 SPICE Macro-model +* Developed by: HH / AD-SJ +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (07/2011) +* Copyright 2011, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT ADA4096 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +I1 99 7 8.00E-06 +RE1 7 7A 3.714E+03 +RE2 7 7B 3.714E+03 +Q1 6 4 7A QP +Q2 5 3 7B QP +D1 3 99 DX +D2 4 99 DX +D3 50 3 DX +D4 50 4 DX +D5 3 4 DX +D6 4 3 DX +R1 202 8 5E-03 +R2 204 4 5E-03 +R3 5 50 7.500E4; +R4 6 50 7.500E4; +Cph 5 5A 6.3E-13 +Rph 5A 6 400 +EOS 8 3 POLY(4) (73,98) (22,98) (81,98) (83,98) -250E-06 1 1 1 1 +IOS 3 4 -1.0E-09 +CDiff 1 2 6.35E-12 +Cin1 1 50 0.67E-12 +Cin2 2 50 0.67E-12 +* +* INPUT PROTECTION NETWORK +* +J1 1 201 202 JXB ; +J2 201 201 202 JXL ; +J3 2 203 204 JXB ; +J4 203 203 204 JXL +* +* 1ST GAIN STAGE +* +G1 9 98 (6,5) 1.0E-06 +R7 9 98 1E6 +* +* 2ND GAIN STAGE AND DOMINANT POLE +* +G2 12 98 (98,9) 3.375E-06 +R8 12 98 3.4E+08 +D7 12 13 DX +D8 14 12 DX +V1 13 98 +0.5; +V2 14 98 -0.2; +* +* Provision for second pole +* +G3 18 98 (98,12) 1E-05 +R11 18 98 1E5 +C11x 18 98 1E-14 +* +* CMRR +* +ECM 21 98 POLY(2) (1,98) (2,98) 0 2.635E-01 2.635E-01 +R10 21 22 1.326E+05 +R20 22 98 7.958E+00 +C10 21 22 1E-9 +* +* PSRR +* +EPSY 72 98 POLY(1) (99,50) -1.514E+3 5.048E+01 +RPS1 72 73 1.592E+03 +RPS2 73 98 1.989E-03 +CPS1 72 73 1.00E-06 +* +* VOLTAGE NOISE REFERENCE +* +VN1 80 98 0 +RN1 80 98 96.300E-3 +HN 81 98 VN1 2.397E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE 1000 +IFN 98 82 DC 1E-03 +DFN2 182 98 DY +IFN2 98 182 DC 1E-06 +GFN 83 98 POLY(1) (182,82) 1.00E-13 1.00E-01 +RFN 83 98 1 +* +* Current Noise +D60 60 98 DN1 1000 +I60 98 60 1E-03 +D61 61 98 DN4 +I61 98 61 1E-06 +G60 1 50 61 60 1.23E-05 +G61 2 50 61 60 1.33E-05 +* +RS1 99 39 400.0E3 +RS2 39 50 400.0E3 +EREF 98 0 (39,0) 1 +* +GSY 99 50 POLY(1) (99 50) -23.8E-6 -1.109E-06 +* +* OUTPUT STAGE +* +Q3 451 41 99 POUT +RB1 40 41 4.37E+03 +EB1 99 40 POLY(1) (98,18) 6.218E-01 1E-0; +Q4 451 43 50 NOUT +RB2 42 43 10E+03 +EB2 42 50 POLY(1) (18,98) 6.170E-01 1E-0; +Lout 45 451 10E-10 +EZ 453 98 (45 98) 1 +CZ 453 12 4.94E-12 +R99T 201 202 450k +* +* MODELS +* +.MODEL QP PNP(BF=300, IS=1.00E-16, VA=130) +.MODEL POUT PNP (BF=80,IS=2.8E-15,VA=130,BR=4.3,VAR=20, RC=75); +.MODEL NOUT NPN (BF=120,IS=3.2E-15,VA=250,BR=9.5, VAR=18, RC=42); +.MODEL DN1 D IS=1E-16 +.MODEL DN4 D IS=1E-16 AF=1 KF=4.35E-17 +.MODEL DW D(IS=1E-18) +.MODEL DX D(IS=1E-16) +.MODEL DY D(IS=1E-16,RS=0.1) +.MODEL DZ D(IS=1E-6) +.MODEL DNOISE D(IS=1E-16,RS=0,KF=2.6E-13) +.MODEL JXL PJF(BETA=4E-05 VTO=-2.0 IS=1E-18 LAMBDA=0.008 RD=1E-1 ++ RS=5E1 CGD=1E-12 CGS=1E-12) +.MODEL JXB PJF(BETA=10E-05 VTO=-1.6 IS=1E-19 LAMBDA=0.005 RD=1E-1 RS=1.41E3) +.ENDS ADA4096 +* +*$ +*ADA4610 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.2.1 Feb 2016-ZZ +*Copyright 2016 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +.Subckt ADA4610 100 101 102 103 104 +*#ASSOC Category="Op-Amps" symbol=opamp +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.33e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 2.97e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 0.2e-6 +IbiasP 110 2 dc 5e-12 +IbiasN 110 9 dc 5e-12 +RinCMP 110 2 Rideal 20000000000000e6 +RinCMN 9 110 Rideal 20000000000000e6 +CinCMP 110 2 5.7e-12 +CinCMN 9 110 5.7e-12 +IOS 9 2 2e-12 +RinDiff 9 2 Rideal 20000000000000e3 +CinDiff 9 2 2.2e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 2.96 +VinN 42 112 dc 2.96 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2 +VPD1 81 0 dc 1.5 +RPD 111 106 Rideal 0.286e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 350 Hz*** +g210 210 110 200 110 0.3502e-6 +R210 210 110 Rideal 454.73e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.709 +VoutN 64 66 dc 5.428 +e60 65 110 111 110 1.34 +e61 66 110 112 110 1.34 +* +* +***Pole-Zero at 84KHz, 180KHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +R221 220 221 Rideal 0.875e3 +C220 221 110 1010.5064e-12 +* +***Pole at 110MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 1.4469e-12 +* +***Buffer*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +* +***Buffer*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Notch: f=2.2MHz, Zeta=1.2, Gain=0.8dB*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +L280 285 281 3425.757e-9 +C280 281 282 1527.698e-12 +R281 282 110 Rideal 103.65 +* +***Peak: f=0.5MHz, Zeta=3.1, Gain=5.1dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 513.402e-9 +C290 291 292 197351.907e-12 +R291 292 110 Rideal 12.518 +e295 295 110 292 110 1.7989 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 163 +Lout 303 310 80e-9 +Cout 310 110 6e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 5.736 +VIoutN 304 306 dc 5.736 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.785 +VoutN1 74 112 dc 0.785 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=174.665) +.model DzSlewN D(BV=174.665) +.model DVnoisy D(IS=2.03e-15 KF=8.16e-18) +.model DINnoisy D(IS=1.45e-22 KF=8.13e-18) +.model DIPnoisy D(IS=1.45e-22 KF=8.13e-18) +.model Rideal res(T_ABS=-273) +* +.ends ADA4610 +* +* ADA4622 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 30V, JFET, OP, S SPLY, RRO +* Developed by: DB/ ADSJ +* Revision History: +* 1.0 (11/2015) +* 2.0 (12/2017) +* 12/2017 - corrected pin order to standard by AR / ADGT +* 3.0 (8/2020) +* 8/2020 - added CMRR, PSRR, Input Clamp, Fixed the ff: Vos, Ib, Input Impedance, Short circuit current by AR/ADGT +* Copyright 2015 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* +* Notes: This model simulates typical values @ Vsy=±15V, T=25°C. +* Ibias and Vos are static and will not vary with Vcm. +* Distortion is not modelled. +* (ada4622 DMod model) +* +* Usage:- + +*X1 3 2 7 4 6 ADA4622 +* | | | | | +* | | | | Output +* | | | Negative Supply +* | | Positive Supply +* | Inverting Input +* Non-Inverting Input + +.SUBCKT ADA4622 3 2 7 4 6 + +* Input Impedances + +GI1 3b 0 VALUE = {IF(V(7,0)>5, 14.600E-012, 4.600E-012)} +GI2 2 0 VALUE = {IF(V(7,0)>5, 11.800E-012, 5.800E-012)} +EOS 3b 3 POLY(4) (14,0) (72,0) (60,0) (63,0) 1E-6 1 1 1 1 +R3 3b 2 1.333E+013 +R4 3b 0 2.000E+013 +R5 2 0 2.000E+013 +C1 3b 0 3.600E-012 +C2 2 0 3.600E-012 +C3 3b 2 4.000E-013 +D5a 3b 43x DL +E1a 43x 0 VALUE = {V(7)- 1.2} +D5b 2 43y DL +E1b 43y 0 VALUE = {V(7)- 1.2} + +* CMRR +* +ECM 13 0 POLY(2) (3,0) (2,0) 0 10.999E-02 10.999E-02 +RCM1 13 14 1.021E+02 +RCM2 14 0 10.842E-03 +CCM1 13 14 1E-6 +* +* PSRR +* +EPSY 71 0 POLY(1) (7,4) -2.4375E-00 14.1250E-02 +RPS1 71 72 9.947E+05 +RPS2 72 0 1.224E+02 +CPS1 71 72 1E-9 + +* Preconditioning Gain Stage and Sum Node for +* Transconductance Control and Noise Insertion + +G1 0 41 POLY(4) 3 2 60 63 14 0 72 0 0.000E+000 2.377E-003 1.947E-003 0.436E-003 0.436E-003 + +* Limiting Section for Slew-Rate Control + +D5 41 43 DL +V1 43 0 1.082E+002 +D6 42 41 DL +V2 0 42 8.170E+001 +G2 41 0 41 0 1.0E-5 +E6 20 0 POLY(1) 41 0 0 1 ++0 -6.562164E-006 0 -5.302485E-012 ++0 3.817254E-016 0 -1.371241E-021 + +.MODEL DL D IS=1E-18 EG=0.1 N=0.2 + +* Second-Order Frequency Shaping + +R50 20 21 5 +C50 21 0 1.224E-009 +R52 21 23 35 +C51 23 0 5.350E-011 +R54 23 25 245 +C52 25 0 7.642E-012 +R56 25 27 1715 +C53 27 0 1.031E-012 +R58 27 40 12005 +C54 40 0 1.105E-013 + +* Primary Gain Block and Dominant Pole/Zero + +G3 0 44 POLY(3) 45 6 40 0 0 54 0 -1.033E-003 1E-5 5E-4 +G4 44 0 44 0 1.981E-011 +C4 44 4 4.348E-013 + +* Output Stage and Swing Limiting Network + +E2 46 0 POLY(1) 7 0 -1.178E+000 1.000E+002 +E3 47 0 POLY(1) 4 0 2.801E-001 1.000E+002 +D7 44 46 DL +D8 47 44 DL +G7 45 6 45 6 100 +E5 55 0 6 0 1.00E+002 +C5 55 50 4.348E-013 +R7 50 44 1.150E+005 +E4 53 0 45 6 2.863E+005 +V7 53 56 11.734E+001 +D9 56 54 DL +V8 57 53 144.2 +D10 54 57 DL +G5 54 0 54 0 9.1E-6 +G8 45 7 POLY(2) 7 0 0 44 0 2.500E-002 2.500E-004 +G9 45 4 POLY(2) 4 0 0 44 0 2.500E-002 2.500E-004 +R12 7 45 4.000E+001 +R13 4 45 4.000E+001 +G10 58 59 POLY(2) 0 45 44 0 0 2.500E-002 2.500E-004 +G11 51 0 51 0 100 +G12 52 0 52 0 100 +G13 4 7 POLY(2) 51 0 52 0 0 100 100 +D11 59 0 DX +D12 51 59 DX +D13 52 58 DX +D14 58 0 DX +R10 58 0 7.00E+003 +R11 59 0 7.00E+003 + +.MODEL DX D IS=1E-14 EG=0.6 + +* Quiescent Supply Current + +GI9 7 4 VALUE = {IF(V(7,0)>5, 7.15E-004, 6.500E-004)} + +* Noise Modeling + +D60 60 0 DN1 1000 +I60 0 60 1E-3 +D63 63 0 DN2 +I63 0 63 1E-6 + +.MODEL DN1 D IS=1E-16 +.MODEL DN2 D IS=1E-16 AF=1 KF=7.715E-018 + +.ENDS ADA4622 +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* BR 06/03/2020 +* +.subckt ADA4625-1 1 2 3 4 5 +D6 4 1 DX +Cdm 1 2 8.6p Rser=200 noiseless +D9 3 4 Dburn +R10 3 Mid 100Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-3.48,10m), V(4)-.3, .1)+100p*V(1) + 332f +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-3.48,10m), V(4)-.3, .1)+100p*V(2) +C1 N004 0 1f Rpar=200K noiseless +C8 3 5 1p Rpar=100Meg noiseless +C9 5 4 1p Rpar=100Meg noiseless +C10 Mid 4 50p Rser=1Meg Rpar=100Meg noiseless +A4 0 N004 0 0 0 0 N007 0 OTA g=1m linear en=3.3n enk=17 vlow=-1e308 vhigh=1e308 +D4 4 2 DX +Q1 XDUM N005 3 0 PNPout1 temp=27 +Q2 XDUM N009 4 0 NPNout1 temp=27 +A1 X3 0 4 4 4 4 N005 4 OTA g=1m asym isource=10u isink=-500u ref=6.8m vlow=0 vhigh=42 +D8 N005 4 DoutBias1 +D11 3 N009 DoutBias1 +A2 X3 0 3 3 3 3 N009 3 OTA g=1m asym isource=500u isink=-10u ref=-6.8m vlow=-42 vhigh=0 +C4 X3 0 100f +Q3 5 N006 3 0 PNPout2 temp=27 +R5 3 N006 10Meg noiseless +Q4 5 N010 4 0 NPNout2 temp=27 +A6 X3 0 4 4 4 4 N006 4 OTA g=1m asym isource=10u isink=-500u ref=6.8m vlow=0 vhigh=42 +D12 N006 4 DoutBias1 +D13 3 N010 DoutBias1 +A7 X3 0 3 3 3 3 N010 3 OTA g=1m asym isource=500u isink=-10u ref=-6.8m vlow=-42 vhigh=0 +C14 3 XDUM 5p +C16 N007 0 2p Rpar=1K noiseless +C2 X3 0 3p Rser=20 Rpar=200Meg noiseless +C15 XDUM 4 5p +C6 N006 5 100f Rser=100 noiseless +B3 X3 0 I=dnlim(1m*(V(X3)-.52-97m*V(3,4)),0,100u) +B4 0 X3 I=dnlim(1m*(-2.26-48m*V(3,4)-V(X3)),0,100u) +C7 5 XDUM 1p Rpar=10k noiseless +D2 2 3 DX +D3 1 3 DX +C12 3 2 5.65p Rser=100 noiseless +C19 3 1 5.65p Rser=100 noiseless +C21 2 4 5.65p Rser=100 noiseless +D5 5 3 DESD +D7 4 5 DESD +C20 1 4 5.65p Rser=100 noiseless +C13 5 N010 100f Rser=100 noiseless +R4 N010 4 10Meg noiseless +R6 3 N005 10Meg noiseless +R7 N009 4 10Meg noiseless +CF2 X3 N014 10p Rser=100 noiseless +G3 0 N014 Mid 5 10m +C22 N014 0 1p Rpar=100 noiseless +C18 N005 XDUM 100f +C23 XDUM N009 100f +R12 N005 4 100Meg noiseless +A5 0 2 0 0 0 0 0 0 OTA g=0 in=4.5f +A8 0 1 0 0 0 0 0 0 OTA g=0 in=4.5f +G5 0 N012 N008 0 1m +C24 N012 0 2p Rpar=1k noiseless +G8 0 N008 N007 0 1m +C26 N008 0 2p Rpar=1k noiseless +C27 3 4 20p +A3 XDUM 5 5 5 5 5 XDUM 5 OTA g=12.5m iout=14.6m vlow=-1e308 vhigh=1e308 +G4 0 N011 Mid XDUM 10m +C28 X3 N011 13.5p Rser=10 noiseless +R9 N011 0 100 noiseless +G1 0 X3 N012 0 2m +D14 N012 0 DSLW1 +B5 0 N004 I=dnlim(V(1,2)-100m,0,10m)*100u*V(1,2)**2- dnlim(V(2,1)-100m,0,10m)*100u*V(2,1)**2 +D10 N004 0 DSLW0 +S1 N015 0 4 3 SVARSLW +C3 N015 0 1p +D15 N012 N015 DSLW2 +.model DX D(IS=1e-16 RS=100 noiseless) +.model DESD D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=600m ilimit=2.908m noiseless) +.model PNPout1 PNP(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f noiseless) +.model NPNout1 NPN(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f noiseless) +.model PNPout2 PNP(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f RC=6 VAF=50 noiseless) +.model NPNout2 NPN(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f RC=6 VAF=50 noiseless) +.model DoutBias1 D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=12u noiseless) +.model DSLW0 D(Ron=100 Roff=200k vfwd=5 epsilon=100m vrev=5 revepsilon=100m noiseless) +.model DSLW1 D(Ron=1 Roff=100k vfwd=550m epsilon=100m vrev=550m revepsilon=100m noiseless) +.model DSLW2 D(Ron=1 Roff=100k vfwd=320m epsilon=100m vrev=320m revepsilon=100m noiseless) +.model SVARSLW SW(Ron=1 Roff=500 vt=-15 vh=-30 noiseless) +.ends ADA4625-1 +* +* +* +* +.subckt ADA4625 1 2 3 4 5 +D6 4 1 DX +Cdm 1 2 8.6p Rser=200 noiseless +D9 3 4 Dburn +R10 3 Mid 100Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-3.48,10m), V(4)-.3, .1)+100p*V(1) + 332f +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-3.48,10m), V(4)-.3, .1)+100p*V(2) +C1 N004 0 1f Rpar=200K noiseless +C8 3 5 1p Rpar=100Meg noiseless +C9 5 4 1p Rpar=100Meg noiseless +C10 Mid 4 50p Rser=1Meg Rpar=100Meg noiseless +A4 0 N004 0 0 0 0 N007 0 OTA g=1m linear en=3.3n enk=17 vlow=-1e308 vhigh=1e308 +D4 4 2 DX +Q1 XDUM N005 3 0 PNPout1 temp=27 +Q2 XDUM N009 4 0 NPNout1 temp=27 +A1 X3 0 4 4 4 4 N005 4 OTA g=1m asym isource=10u isink=-500u ref=6.8m vlow=0 vhigh=42 +D8 N005 4 DoutBias1 +D11 3 N009 DoutBias1 +A2 X3 0 3 3 3 3 N009 3 OTA g=1m asym isource=500u isink=-10u ref=-6.8m vlow=-42 vhigh=0 +C4 X3 0 100f +Q3 5 N006 3 0 PNPout2 temp=27 +R5 3 N006 10Meg noiseless +Q4 5 N010 4 0 NPNout2 temp=27 +A6 X3 0 4 4 4 4 N006 4 OTA g=1m asym isource=10u isink=-500u ref=6.8m vlow=0 vhigh=42 +D12 N006 4 DoutBias1 +D13 3 N010 DoutBias1 +A7 X3 0 3 3 3 3 N010 3 OTA g=1m asym isource=500u isink=-10u ref=-6.8m vlow=-42 vhigh=0 +C14 3 XDUM 5p +C16 N007 0 2p Rpar=1K noiseless +C2 X3 0 3p Rser=20 Rpar=200Meg noiseless +C15 XDUM 4 5p +C6 N006 5 100f Rser=100 noiseless +B3 X3 0 I=dnlim(1m*(V(X3)-.52-97m*V(3,4)),0,100u) +B4 0 X3 I=dnlim(1m*(-2.26-48m*V(3,4)-V(X3)),0,100u) +C7 5 XDUM 1p Rpar=10k noiseless +D2 2 3 DX +D3 1 3 DX +C12 3 2 5.65p Rser=100 noiseless +C19 3 1 5.65p Rser=100 noiseless +C21 2 4 5.65p Rser=100 noiseless +D5 5 3 DESD +D7 4 5 DESD +C20 1 4 5.65p Rser=100 noiseless +C13 5 N010 100f Rser=100 noiseless +R4 N010 4 10Meg noiseless +R6 3 N005 10Meg noiseless +R7 N009 4 10Meg noiseless +CF2 X3 N014 10p Rser=100 noiseless +G3 0 N014 Mid 5 10m +C22 N014 0 1p Rpar=100 noiseless +C18 N005 XDUM 100f +C23 XDUM N009 100f +R12 N005 4 100Meg noiseless +A5 0 2 0 0 0 0 0 0 OTA g=0 in=4.5f +A8 0 1 0 0 0 0 0 0 OTA g=0 in=4.5f +G5 0 N012 N008 0 1m +C24 N012 0 2p Rpar=1k noiseless +G8 0 N008 N007 0 1m +C26 N008 0 2p Rpar=1k noiseless +C27 3 4 20p +A3 XDUM 5 5 5 5 5 XDUM 5 OTA g=12.5m iout=14.6m vlow=-1e308 vhigh=1e308 +G4 0 N011 Mid XDUM 10m +C28 X3 N011 13.5p Rser=10 noiseless +R9 N011 0 100 noiseless +G1 0 X3 N012 0 2m +D14 N012 0 DSLW1 +B5 0 N004 I=dnlim(V(1,2)-100m,0,10m)*100u*V(1,2)**2- dnlim(V(2,1)-100m,0,10m)*100u*V(2,1)**2 +D10 N004 0 DSLW0 +S1 N015 0 4 3 SVARSLW +C3 N015 0 1p +D15 N012 N015 DSLW2 +.model DX D(IS=1e-16 RS=100 noiseless) +.model DESD D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=600m ilimit=2.908m noiseless) +.model PNPout1 PNP(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f noiseless) +.model NPNout1 NPN(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f noiseless) +.model PNPout2 PNP(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f RC=6 VAF=50 noiseless) +.model NPNout2 NPN(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f RC=6 VAF=50 noiseless) +.model DoutBias1 D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=12u noiseless) +.model DSLW0 D(Ron=100 Roff=200k vfwd=5 epsilon=100m vrev=5 revepsilon=100m noiseless) +.model DSLW1 D(Ron=1 Roff=100k vfwd=550m epsilon=100m vrev=550m revepsilon=100m noiseless) +.model DSLW2 D(Ron=1 Roff=100k vfwd=320m epsilon=100m vrev=320m revepsilon=100m noiseless) +.model SVARSLW SW(Ron=1 Roff=500 vt=-15 vh=-30 noiseless) +.ends ADA4625 + +* +* +* +.subckt ADA4625-2 1 2 3 4 5 +D6 4 1 DX +Cdm 1 2 8.6p Rser=200 noiseless +D9 3 4 Dburn +R10 3 Mid 100Meg noiseless +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+1n*V(1) + 2.93p +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)+.31,.1), V(4)-.31, .1)+1n*V(2) +C1 N005 0 1f Rpar=100K noiseless +C8 3 5 1p Rpar=100Meg noiseless +C9 5 4 1p Rpar=100Meg noiseless +C10 Mid 4 50p Rser=1Meg Rpar=100Meg noiseless +A4 0 N005 0 0 0 0 N008 0 OTA g=1m linear en=3.3n enk=17 vlow=-1e308 vhigh=1e308 +D4 4 2 DX +Q1 XDUM N006 3 0 PNPout1 temp=27 +Q2 XDUM N010 4 0 NPNout1 temp=27 +A1 0 N003 4 4 4 4 N006 4 OTA g=1m asym isource=10u isink=-500u ref=6.8m vlow=0 vhigh=42 +D8 N006 4 DoutBias1 +D11 3 N010 DoutBias1 +A2 0 N003 3 3 3 3 N010 3 OTA g=1m asym isource=500u isink=-10u ref=-6.8m vlow=-42 vhigh=0 +C4 X3 0 100f +G1 0 N003 0 X3 100m +C3 N003 0 1p Rpar=10 noiseless +G2 0 N003 0 N012 100m +Q3 5 N007 3 0 PNPout2 temp=27 +R5 3 N007 10Meg noiseless +Q4 5 N011 4 0 NPNout2 temp=27 +A6 0 N003 4 4 4 4 N007 4 OTA g=1m asym isource=10u isink=-500u ref=6.8m vlow=0 vhigh=42 +D12 N007 4 DoutBias1 +D13 3 N011 DoutBias1 +A7 0 N003 3 3 3 3 N011 3 OTA g=1m asym isource=500u isink=-10u ref=-6.8m vlow=-42 vhigh=0 +C14 3 XDUM 5p +C16 N008 0 4p Rpar=1K noiseless +C2 X3 0 3p Rser=20 Rpar=100Meg noiseless +C15 XDUM 4 5p +C6 N007 5 100f Rser=100 noiseless +C5 N012 0 5p Rpar=1k Rser=50 noiseless +G6 0 N012 N013 0 1m +B3 X3 0 I=dnlim(1m*(V(X3)-V(3,Mid)-3),0,100u) +B4 0 X3 I=dnlim(1m*(V(4,Mid)-5-V(X3)),0,100u) +C7 5 XDUM 1p Rpar=10k noiseless +D2 2 3 DX +D3 1 3 DX +C12 3 2 5.65p Rser=100 noiseless +C19 3 1 5.65p Rser=100 noiseless +C21 2 4 5.65p Rser=100 noiseless +D5 5 3 DESD +D7 4 5 DESD +C20 1 4 5.65p Rser=100 noiseless +C13 5 N011 100f Rser=100 noiseless +R4 N011 4 10Meg noiseless +R6 3 N006 10Meg noiseless +R7 N010 4 10Meg noiseless +CF2 X3 N017 10p Rser=100 noiseless +G3 0 N017 Mid 5 10m +C22 N017 0 1p Rpar=100 noiseless +C18 N006 XDUM 100f +C23 XDUM N010 100f +R12 N006 4 100Meg noiseless +A5 0 2 0 0 0 0 0 0 OTA g=0 in=4.5f +A8 0 1 0 0 0 0 0 0 OTA g=0 in=4.5f +G5 0 N014 N009 0 1m +C24 N014 0 2p Rpar=1k noiseless +L1 N013 0 227m Rser=142.8m Rpar=1K noiseless +G7 0 N013 Mid XDUM 1m +A9 0 N014 N016 0 0 0 X3 0 OTA g=2m linear vlow=-1e308 vhigh=1e308 +I1 0 N016 1µ +S1 N016 0 2 3 SGKILL +S2 N016 0 1 3 SGKILL +C25 N016 0 1p Rpar=1Meg noiseless +G8 0 N009 N008 0 1m +C26 N009 0 5p Rpar=1k noiseless +D10 N014 0 DSLW1 +D14 N014 N018 DSLW2 +S3 N018 0 4 3 SVARSLW +C17 N018 0 1p +C27 3 4 20p +A3 XDUM 5 5 5 5 5 XDUM 5 OTA g=12.5m iout=14.6m vlow=-1e308 vhigh=1e308 +.model DX D(IS=1e-16 RS=100 noiseless) +.model DESD D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=600m ilimit=3.076m noiseless) +.model PNPout1 PNP(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f noiseless) +.model NPNout1 NPN(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f noiseless) +.model PNPout2 PNP(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f RC=6 noiseless) +.model NPNout2 NPN(Is=1e-18 Isc=3e-11 NC=1.7 BF=75 BR=10 CJE=100f RC=6 noiseless) +.model DoutBias1 D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=12u noiseless) +.model SGKILL SW(level=2 Ron=5k Roff=1G vt=-2 vh=-300m noiseless) +.model DSLW1 D(Ron=1 Roff=100k vfwd=538m epsilon=100m vrev=538m revepsilon=100m noiseless) +.model DSLW2 D(Ron=1 Roff=100k vfwd=375m epsilon=100m vrev=375m revepsilon=100m noiseless) +.model SVARSLW SW(Ron=1 Roff=500 vt=-15 vh=-30 noiseless) +.param CL = 1f +.ends ADA4625-2 +* +* ADA4627 SPICE Macro-model +* Developed by: HH / ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (07/2009) +* Copyright 2009, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* CAUTION!! To aid in convergence, most Spice simulators add a +* conductance on every node to insure that no node is floating. +* This is GMIN, and the default value is usually 1E-12. To properly +* simulate the low input bias current and low current noise, the +* Spice simulator options have to be set to the following: +* .OPTIONS GMIN=0.01p +* .OPTIONS ABSTOL=0.01pA +* .OPTIONS ITL1=500 +* .OPTIONS ITL2=200 +* .OPTIONS ITL4=100 +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT ADA4627 1 2 99 50 30 +* +* INPUT STAGE +* +Cdiff 1 2 4.7E-12 +Cin1 1 50 7.5E-12 +Cin2 2 50 7.5E-12 +* +R3 5 99 1.478E+03 +R4 6 99 1.478E+03 +J1 5 2 4 JX +J2 6 7 4 JX +* +I1 4 50 2.70E-03 +DI1 4a 4 DX +VI1 4a 50 5.5V +IOS 1 2 0.25E-12 +EOS 60 1 POLY(2) (17,24) (73,98) 110E-6 1 1 +EN 7 60 42 0 1 +* +EREF 98 0 24 0 1 +* +* SECOND STAGE +* +R5 9 98 4.097E+05 +C3 9 98 3.850E-09 +G1 98 9 5 6 7.700E-02 +V2 99 8 2.86 +V3 10 50 2.41; +D1 9 8 DX +D2 10 9 DX +* +* 2nd POLE +* +R13 18 98 1.000E+03 +C9 18 98 1.0E-14 +G5 98 18 9 24 1E-3 +* +* COMMON-MODE GAIN NETWORK +* +R11 16 17 2.698E-01 +R12 17 98 1.326E-04 +E3 16 98 POLY(2) 1 98 2 98 0 8.459E-03 8.459E-03 +C8 16 17 100E-6 +* +* PSRR NETWORK +* +EPSY 98 72 POLY(1) (99,50) 3.350E-03 1.005E-01 +CPS3 72 73 1.000E-09 +RPS3 72 73 9.947E+05 +RPS4 73 98 1.326E+02 +* +* VOLTAGE NOISE GENERATOR +* +VN1 41 0 DC 2 +DN1 41 42 DEN +DN2 42 43 DEN +VN2 0 43 DC 2 +* +* CURRENT NOISE GENERATOR +* +VN3 44 0 DC 2 +DN3 44 45 DIN +DN4 45 46 DIN +VN4 0 46 DC 2 +* +* CURRENT NOISE GENERATOR +* +VN5 47 0 DC 2 +DN5 47 48 DIN +DN6 48 49 DIN +VN6 0 49 DC 2 +* +* OUTPUT STAGE +* +R14 24 99 500E3 +R15 24 50 500E3 +GSY 99 50 POLY(1) (99,50) 4.079E-03 2.985E-06 +R16 29 99 100 +R17 29 50 100 +G6 27 50 18 29 10.0E-3 +G7 28 50 29 18 10.0E-3 +G8 29 99 POLY(1) 99 18 1E-16 1.00E-2 +G9 50 29 POLY(1) 18 50 1E-16 1.00E-2 +* +V4 25 29 1.99; Isc high side +V5 29 26 2.4 +D3 18 25 DX +D4 26 18 DX +* +D5 99 27 DX +D6 99 28 DX +D7 50 27 DY +D8 50 28 DY +F1 29 0 V4 1 +F2 0 29 V5 1 +L1 29 30a 1E-15 +R24 30a 30 1m +* +* MODELS USED +* +.MODEL JX NJF(BETA=3.400E-03 VTO=-1.500 IS=7E-13 RD=1 ++ RS=1 CGD=1.5E-12 CGS=1.5E-12 ) +*.MODEL JX PJF(BETA=1.4E-3 VTO=-1.000 IS=20E-12 RD=0 +*+ RS=0 CGD=3E-12 CGS=3E-12) +.MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) +.MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) +.MODEL DEN D(IS=1E-12 RS=1.7E3, KF=6.53E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) +.ENDS ADA4627 + +.subckt OP1177 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=0.2p ink=10 incm=.001p incmk=10 +C6 3 1 1.25p Rpar=280G noiseless +C1 2 1 1p noiseless +G1 0 M 3 0 1m +G2 0 M 4 0 1m +R3 M 0 1K noiseless +S1 N004 M 4 3 UVLO +D3 N004 3 X1 +D4 4 N004 X2 +C7 1 4 1.25p Rpar=280G noiseless +C8 3 2 1.25p Rpar=280G noiseless +C9 2 4 1.25p Rpar=280G noiseless +I1 3 2 2n load +I2 3 1 2n load +A2 0 N006 M M M M N004 M OTA g=20u Iout=1.8u en=7.9n enk=0.42 Vlow=-1e308 Vhigh=1e308 Cout=2.3p asym +C10 N005 0 44p +L1 N002 N005 22p +C5 N002 0 22p Rpar=1K noiseless +M1 3 N003 5 5 N temp=27 +M2 4 N003 5 5 P temp=27 +C3 3 5 2p +C4 5 4 2p +C13 5 N003 5p Rser=1Meg noiseless +R5 N003 N004 1Meg +D1 5 N003 Y2A +D6 5 N003 Y2B +D9 N003 5 Y1 +B1 N002 0 I=2m*dnlim(uplim(V(2),V(3)-1.4,.1), V(4)+1.4, .1)+100n*V(2) +B2 0 N002 I=2m*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.4, .1)+100n*V(1) +L3 N005 N006 22µ +C2 N006 0 22p Rpar=1K noiseless +D2 3 4 IQ +.model X1 D(Ron=1K Roff=100G Vfwd=-0.75 epsilon=.1 noiseless) +.model X2 D(Ron=10 Roff=100G Vfwd=-0.75 epsilon=.1 noiseless) +.model Y1 D(Ron=18k Roff=100G Vfwd=582m epsilon=500m noiseless) +.model Y2A D(Ron=25k Roff=100G Vfwd=350m epsilon=500m noiseless) +.model Y2B D(Ron=5k Roff=100G Vfwd=590m epsilon=500m noiseless) +.model N VDMOS(Vto=-55m Kp=75m Ksubthres=100m noiseless) +.model P VDMOS(Vto=55m Kp=125m pchan Ksubthres=100m noiseless) +.model UVLO SW(Ron=1K Roff=3G Vt=-3.75 Vh=.25 noiseless) +.model IQ D(Ron=2K Vfwd=2 epsilon=1 Ilimit=0.014m noiseless) +.param Vs=15 +.ends OP1177 + + +* OP213 SPICE Macro-model +* Developed by: JCB / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (09/1992) +* Copyright 1992, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP213 3 2 7 4 6 +* +* INPUT STAGE +* +R3 4 19 1.5E3 +R4 4 20 1.5E3 +C1 19 20 5.31E-12 +I1 7 18 106E-6 +IOS 2 3 25E-09 +EOS 12 5 POLY(1) 51 4 25E-06 1 +Q1 19 3 18 PNP1 +Q2 20 12 18 PNP1 +CIN 3 2 3E-12 +D1 3 1 DY +D2 2 1 DY +EN 5 2 22 0 1 +GN1 0 2 25 0 1E-5 +GN2 0 3 28 0 1E-5 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +DN1 21 22 DEN +DN2 22 23 DEN +VN1 21 0 DC 2 +VN2 0 23 DC 2 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +DN3 24 25 DIN +DN4 25 26 DIN +VN3 24 0 DC 2 +VN4 0 26 DC 2 +* +* SECOND CURRENT NOISE SOURCE +* +DN5 27 28 DIN +DN6 28 29 DIN +VN5 27 0 DC 2 +VN6 0 29 DC 2 +* +* GAIN STAGE & DOMINANT POLE AT .2000E+01 HZ +* +G2 34 36 19 20 2.65E-04 +R7 34 36 39E+06 +V3 35 4 DC 6 +D4 36 35 DX +VB2 34 4 1.6 +* +* SUPPLY/2 GENERATOR +* +ISY 7 4 0.2E-3 +R10 7 60 40E+3 +R11 60 4 40E+3 +C3 60 0 1E-9 +* +* CMRR STAGE & POLE AT 6 kHZ +* +ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8 +CCM 50 51 26.5E-12 +RCM1 50 51 1E6 +RCM2 51 4 1 +* +* OUTPUT STAGE +* +R12 37 36 1E3 +R13 38 36 500 +C4 37 6 20E-12 +C5 38 39 20E-12 +M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +D5 39 47 DX +D6 47 45 DX +Q3 39 40 41 QPA 8 +VB 7 40 DC 0.861 +R14 7 41 375 +Q4 41 7 43 QNA 1 +R17 7 43 15 +Q5 43 39 6 QNA 20 +Q6 46 45 6 QPA 20 +R18 46 4 15 +Q7 36 46 4 QNA 1 +M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 +* +* NONLINEAR MODELS USED +* +.MODEL DX D (IS=1E-15) +.MODEL DY D (IS=1E-15 BV=7) +.MODEL PNP1 PNP (BF=220) +.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) +.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 ++ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 ++ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12 ++ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) +.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 ++ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 ++ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 ++ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) +.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 ++ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 ++ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 ++ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33) +* +.ENDS + + +* OP2177 SPICE Macro-model +* Developed by: SB, ADSiV apps +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (05/2002) +* Copyright 2002, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: Vsy=±15V +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT OP2177 1 2 99 50 34 +* +* INPUT STAGE & POLE AT 100 MHZ +* +R3 5 51 6.8E3 +R4 6 51 6.8E3 +CIN 1 2 1.5E-12 +C2 5 6 3.5E-12 +I1 97 4 500E-6 +IOS 1 2 0.1E-9 +EOS 9 3 POLY(2) (26, 28) (73, 98) 15E-6 1 1 +Q1 5 2 7 QX +Q2 6 9 8 QX +R5 7 4 50 +R6 8 4 50 +D1 2 36 DZ +D2 1 36 DZ +EN 3 1 10 0 1 +GN1 0 2 13 0 1 +GN2 0 1 16 0 1 +* +EREF 98 0 28 0 1 +EP 97 0 99 0 1 +EM 51 0 50 0 1 +* +* VOLTAGE NOISE SOURCE +* +DN1 35 10 DEN +DN2 10 11 DEN +VN1 35 0 DC 2 +VN2 0 11 DC 2 +* +* CURRENT NOISE SOURCE +* +DN3 12 13 DIN +DN4 13 14 DIN +VN3 12 0 DC 2 +VN4 0 14 DC 2 +* +* CURRENT NOISE SOURCE +* +DN5 15 16 DIN +DN6 16 17 DIN +VN5 15 0 DC 2 +VN6 0 17 DC 2 +* +* GAIN STAGE & DOMINANT POLE AT 0.439 HZ +* +R7 18 98 1.45E7 +C3 18 98 25E-9 +G1 98 18 5 6 5.15E-3 +V2 97 19 1.5 +V3 20 51 1.5 +D3 18 19 DX +D4 20 18 DX +* +* POLE/ZERO PAIR AT 1.5MHz/12.7MHz +* +R8 21 98 1E3 +R9 21 22 1.25E3 +C4 22 98 10E-12 +G2 98 21 18 28 1E-3 +* +* POLE AT 2568 MHz +* +R10 23 98 1 +C5 23 98 62E-12 +G3 98 23 21 28 1 +* +* POLE AT 2568 MHz +* +R11 24 98 1 +C6 24 98 62E-12 +G4 98 24 23 28 1 +* +* POLE AT 2568 MHz +* +R14 27 98 1 +C8 27 98 62E-12 +G5 98 27 24 28 1 +* +* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ +* +R12 25 26 1E6 +C7 25 26 159.155E-12 +R13 26 98 1 +E2 25 98 POLY(2) 1 98 2 98 0 0.28 0.28 +* +*PSRR=121dB +EPSY 98 72 POLY(1) (99,50) 0 1 +RPS3 72 73 1E6 +CPS3 72 73 3E-9 +RPS4 73 98 1 + +* OUTPUT STAGE +* +R15 28 99 100E3 +R16 28 50 100E3 +C9 28 50 1E-6 +ISY 99 50 250E-6 +R17 29 99 100 +R18 29 50 100 +L2 29 34 1E-9 +G6 32 50 27 29 10E-3 +G7 33 50 29 27 10E-3 +G8 29 99 99 27 10E-3 +G9 50 29 27 50 10E-3 +V4 30 29 1.3 +V5 29 31 3.8 +F1 29 0 V4 1 +F2 0 29 V5 1 +D5 27 30 DX +D6 31 27 DX +D7 99 32 DX +D8 99 33 DX +D9 50 32 DY +D10 50 33 DY +* +* MODELS USED +* +.MODEL QX PNP(BF=5E5) +.MODEL DX D(IS=1E-12) +.MODEL DY D(IS=1E-15 BV=50) +.MODEL DZ D(IS=1E-15 BV=7.0) +.MODEL DEN D(IS=1E-12 RS=6.8E3 KF=1.95E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=77.3E-6 KF=3.38E-15 AF=1) +.ENDS OP2177 + + +* OP284 SPICE Macro-model +* Developed by: HH / ADSJ, ARG / ADSC +* Revision History: 08/10/2012 - Updated to new header style +* 4.0 (09/2009) - Increased Ccm, Cdiff +* 3.0 - Adjusted Ccm, Cdiff, and en. +* 2.0 (11/1995) - Changed input transistor betas to conform to final data sheet Ios typical spec of 60nA. +* Copyright 1993, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP284 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +Q1 5 2 3 QIN 1 +Q2 6 11 3 QIN 1 +Q3 7 2 4 QIP 1 +Q4 8 11 4 QIP 1 +DC1 2 11 DC +DC2 11 2 DC +Q5 4 9 99 QIP 1 +Q6 9 9 99 QIP 1 +Q7 3 10 50 QIN 1 +Q8 10 10 50 QIN 1 +R1 99 5 4E3 +R2 99 6 4E3 +R3 7 50 4E3 +R4 8 50 4E3 +IREF 9 10 50.5E-6 +EOS 1 11 POLY(2) (22,98) (14,98) -25E-6 1E-2 1 +IOS 2 1 5E-9 +CIN 1 2 2.3E-12 +CCM1 1 50 7.2E-12 +CCM2 2 50 7.2E-12 +GN1 98 1 (17,98) 1E-3 +GN2 98 2 (23,98) 1E-3 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +VN1 13 98 DC 2 +VN2 98 15 DC 2 +DN1 13 14 DEN +DN2 14 15 DEN +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +VN3 16 98 DC 2 +VN4 98 18 DC 2 +DN3 16 17 DIN +DN4 17 18 DIN +* +* 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE +* +VN5 19 98 DC 2 +VN6 98 24 DC 2 +DN5 19 23 DIN +DN6 23 24 DIN +* +* GAIN STAGE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 +R9 20 98 1E3 +* +* COMMON MODE STAGE WITH ZERO AT 100HZ +* +ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 +R10 21 22 1 +R11 22 98 100E-6 +C4 21 22 1.592E-3 +* +* NEGATIVE ZERO AT 20MHZ +* +E1 27 98 (20,98) 1E6 +R17 27 28 1 +R18 28 98 1E-6 +C8 25 26 7.958E-9 +ENZ 25 98 (27,28) 1 +VNZ 26 98 DC 0 +FNZ 27 28 VNZ -1 +* +* POLE AT 40MHZ +* +G4 98 29 (28,98) 1 +R19 29 98 1 +C9 29 98 3.979E-9 +* +* POLE AT 40MHZ +* +G5 98 30 (29,98) 1 +R20 30 98 1 +C10 30 98 3.979E-9 +* +* OUTUT STAGE +* +ISY 99 50 0.276E-3 +GIN 50 31 POLY(1) (30,98) .862574E-6 505.879E-6 +RIN 31 50 2.75E6 +VB 99 32 0.7 +Q11 32 31 33 QON 1 +R21 33 34 4.5E3 +I1 34 50 50E-6 +R22 99 35 6E3 +Q12 36 36 35 QOP 1 +I2 36 50 50E-6 +R23 99 37 2.6E3 +R24 34 38 5E3 +Q13 39 36 37 QOP 1 +Q14 39 38 40 QON 1.5 +R25 40 50 40 +Q15 39 39 41 QON 1 +R26 41 42 1E3 +R27 99 43 220 +Q16 44 44 43 QOP 1.5 +Q17 44 39 42 QON 1 +R28 42 50 2E3 +VSCP 99 97 DC 0 +FSCP 46 99 VSCP 1 +RSCP 46 99 40 +Q20 44 46 99 QOP 1 +Q18 45 44 97 QOP 4.5 +Q19 45 34 51 QON 4.5 +VSCN 51 50 DC 0 +FSCN 50 47 VSCN 1 +RSCN 47 50 40 +Q21 34 47 50 QON 1 +CC2 31 45 20E-12 +CF1 31 34 15E-12 +CF2 31 42 15E-12 +CO1 34 45 15E-12 +CO2 42 45 5E-12 +D3 45 99 DX +D4 50 45 DX +.MODEL DC D(IS=130E-21) +.MODEL DX D() +.MODEL DEN D(RS=380 KF=6E-15 AF=1) +.MODEL DIN D(RS=5.358 KF=56E-15 AF=1) +.MODEL QIN NPN(BF=120 VA=200 IS=0.5E-16) +.MODEL QIP PNP(BF=90 VA=60 IS=0.5E-16) +.MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50) +.MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160) +.ENDS OP284 + + +* OP285 SPICE Macro-model +* Developed by: ARG / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (06/1992) +* Copyright 1992, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT OP285 1 2 99 50 34 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE & POLE AT 100 MHZ +* +R3 5 51 2.188 +R4 6 51 2.188 +CIN 1 2 1.5E-12 +C2 5 6 364E-12 +I1 97 4 100E-3 +IOS 1 2 1E-9 +EOS 9 3 POLY(1) 26 28 35E-6 1 +Q1 5 2 7 QX +Q2 6 9 8 QX +R5 7 4 1.672 +R6 8 4 1.672 +D1 2 36 DZ +D2 1 36 DZ +EN 3 1 10 0 1 +GN1 0 2 13 0 1 +GN2 0 1 16 0 1 +* +EREF 98 0 28 0 1 +EP 97 0 99 0 1 +EM 51 0 50 0 1 +* +* VOLTAGE NOISE SOURCE +* +DN1 35 10 DEN +DN2 10 11 DEN +VN1 35 0 DC 2 +VN2 0 11 DC 2 +* +* CURRENT NOISE SOURCE +* +DN3 12 13 DIN +DN4 13 14 DIN +VN3 12 0 DC 2 +VN4 0 14 DC 2 +CN1 13 0 7.53E-3 +* +* CURRENT NOISE SOURCE +* +DN5 15 16 DIN +DN6 16 17 DIN +VN5 15 0 DC 2 +VN6 0 17 DC 2 +CN2 16 0 7.53E-3 +* +* GAIN STAGE & DOMINANT POLE AT 32 HZ +* +R7 18 98 1.09E6 +C3 18 98 4.55E-9 +G1 98 18 5 6 4.57E-1 +V2 97 19 1.4 +V3 20 51 1.4 +D3 18 19 DX +D4 20 18 DX +* +* POLE/ZERO PAIR AT 1.5MHz/2.7MHz +* +R8 21 98 1E3 +R9 21 22 1.25E3 +C4 22 98 47.2E-12 +G2 98 21 18 28 1E-3 +* +* POLE AT 100 MHZ +* +R10 23 98 1 +C5 23 98 1.59E-9 +G3 98 23 21 28 1 +* +* POLE AT 100 MHZ +* +R11 24 98 1 +C6 24 98 1.59E-9 +G4 98 24 23 28 1 +* +* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ +* +R12 25 26 1E6 +C7 25 26 159.155E-12 +R13 26 98 1 +E2 25 98 POLY(2) 1 98 2 98 0 2.506 2.506 +* +* POLE AT 100 MHZ +* +R14 27 98 1 +C8 27 98 1.59E-9 +G5 98 27 24 28 1 +* +* OUTPUT STAGE +* +R15 28 99 100E3 +R16 28 50 100E3 +C9 28 50 1E-6 +ISY 99 50 1.85E-3 +R17 29 99 100 +R18 29 50 100 +L2 29 34 1E-9 +G6 32 50 27 29 10E-3 +G7 33 50 29 27 10E-3 +G8 29 99 99 27 10E-3 +G9 50 29 27 50 10E-3 +V4 30 29 1.3 +V5 29 31 3.8 +F1 29 0 V4 1 +F2 0 29 V5 1 +D5 27 30 DX +D6 31 27 DX +D7 99 32 DX +D8 99 33 DX +D9 50 32 DY +D10 50 33 DY +* +* MODELS USED +* +.MODEL QX PNP(BF=5E5) +.MODEL DX D(IS=1E-12) +.MODEL DY D(IS=1E-15 BV=50) +.MODEL DZ D(IS=1E-15 BV=7.0) +.MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=77.3E-6 KF=3.38E-15 AF=1) +.ENDS OP285 + + +* OP292 SPICE Macro-model +* Developed by: ARG / PMI +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (03/1995) +* Copyright 1993, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP292 2 1 99 50 34 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE AND POLE AT 40MHZ +* +I1 99 4 50E-6 +IOS 2 1 10E-9 +EOS 2 3 POLY(1) (21,30) 1.5E-3 75 +CIN 1 2 3E-12 +Q1 5 1 7 QP +Q2 6 3 8 QP +R3 5 50 2E3 +R4 6 50 2E3 +R5 4 7 966 +R6 4 8 966 +C1 5 6 .995E-12 +* +* GAIN STAGE +* +EREF 98 0 (30,0) 1 +G1 98 9 (5,6) 500E-6 +R7 9 98 210.819E3 +D1 9 10 DX +D2 11 9 DX +V1 99 10 .6 +V2 11 50 .6 +* +* ZERO/POLE AT 6MHZ/12MHZ +* +E1 12 98 (9,30) 2 +R8 12 13 1 +R9 13 98 1 +C3 12 13 26.526E-9 +* +* ZERO AT 15MHZ +* +E2 14 98 (13,30) 1E6 +R10 14 15 1E6 +R11 15 98 1 +C4 14 15 10.610E-15 +* +* COMMON MODE STAGE WITH ZERO AT 40KHZ +* +ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 +R20 20 21 1E6 +R21 21 98 1 +C5 20 21 3.979E-12 +* +* POLE AT 100MHZ +* +G2 98 16 (15,30) 1 +R12 16 98 1 +C6 16 98 1.592E-9 +* +* OUTPUT STAGE +* +RS1 99 30 1E6 +RS2 30 50 1E6 +ISY 99 50 .44E-3 +G3 31 50 POLY(1) (16,30) -1.635E-6 4E-6 +R16 31 50 1E6 +DCL 50 31 DZ +I2 99 32 250E-6 +RCL 33 50 56 +M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +CC 31 32 14E-12 +Q3 99 32 34 QNA +Q4 33 32 34 QPA +Q5 31 33 50 QNA +.MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 ++ ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 ++ ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 ++ CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 ++ CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) +.MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 ++ ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 ++ ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 ++ CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 ++ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) +.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 ++ TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 ++ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 ++ MJ=0.407 CJSW=0.5E-9 MJSW=0.33) +.MODEL QP PNP(BF=61.5) +.MODEL DX D +.MODEL DZ D(BV=3.6) +.ENDS OP292 + + + +* OP413 SPICE Macro-model +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (03/1994) +* Copyright 1992, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP413 3 2 7 4 6 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +R3 4 19 1.5E3 +R4 4 20 1.5E3 +C1 19 20 5.31E-12 +I1 7 18 106E-6 +IOS 2 3 25E-09 +EOS 12 5 POLY(1) 51 4 25E-06 1 +Q1 19 3 18 PNP1 +Q2 20 12 18 PNP1 +CIN 3 2 3E-12 +D1 3 1 DY +D2 2 1 DY +EN 5 2 22 0 1 +GN1 0 2 25 0 1E-5 +GN2 0 3 28 0 1E-5 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +DN1 21 22 DEN +DN2 22 23 DEN +VN1 21 0 DC 2 +VN2 0 23 DC 2 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +DN3 24 25 DIN +DN4 25 26 DIN +VN3 24 0 DC 2 +VN4 0 26 DC 2 +* +* SECOND CURRENT NOISE SOURCE +* +DN5 27 28 DIN +DN6 28 29 DIN +VN5 27 0 DC 2 +VN6 0 29 DC 2 +* +* GAIN STAGE & DOMINANT POLE AT 2HZ +* +G2 34 36 19 20 2.65E-04 +R7 34 36 39E6 +V3 35 4 DC 6 +D4 36 35 DX +VB2 34 4 1.6 +* +* SUPPLY/2 GENERATOR +* +ISY 7 4 0.2E-3 +R10 7 60 40E3 +R11 60 4 40E3 +C3 60 0 1E-9 +* +* CMRR STAGE & POLE AT 6kHZ +* +ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8 +CCM 50 51 26.5E-12 +RCM1 50 51 1E6 +RCM2 51 4 1 +* +* OUTPUT STAGE +* +R12 37 36 1E3 +R13 38 36 500 +C4 37 6 20E-12 +C5 38 39 20E-12 +M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +D5 39 47 DX +D6 47 45 DX +Q3 39 40 41 QPA 8 +VB 7 40 DC 0.861 +R14 7 41 375 +Q4 41 7 43 QNA 1 +R17 7 43 15 +Q5 43 39 6 QNA 20 +Q6 46 45 6 QPA 20 +R18 46 4 15 +Q7 36 46 4 QNA 1 +M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 +* +* NONLINEAR MODELS USED +* +.MODEL DX D (IS=1E-15) +.MODEL DY D (IS=1E-15 BV=7) +.MODEL PNP1 PNP (BF=220) +.MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) +.MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 ++ IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 ++ MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12 ++ VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) +.MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 ++ IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 ++ VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 ++ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) +.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 ++ LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 ++ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 ++ PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33) +.ENDS OP413 + + +* OP4177 SPICE Macro-model +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (05/2002) +* Copyright 2002, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: Vsy=+/-15V +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT OP4177 1 2 99 50 34 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE & POLE AT 100 MHZ +* +R3 5 51 6.8E3 +R4 6 51 6.8E3 +CIN 1 2 1.5E-12 +C2 5 6 3.5E-12 +I1 97 4 500E-6 +IOS 1 2 0.1E-9 +EOS 9 3 POLY(2) (26, 28) (73, 98) 15E-6 1 1 +Q1 5 2 7 QX +Q2 6 9 8 QX +R5 7 4 50 +R6 8 4 50 +D1 2 36 DZ +D2 1 36 DZ +EN 3 1 10 0 1 +GN1 0 2 13 0 1 +GN2 0 1 16 0 1 +* +EREF 98 0 28 0 1 +EP 97 0 99 0 1 +EM 51 0 50 0 1 +* +* VOLTAGE NOISE SOURCE +* +DN1 35 10 DEN +DN2 10 11 DEN +VN1 35 0 DC 2 +VN2 0 11 DC 2 +* +* CURRENT NOISE SOURCE +* +DN3 12 13 DIN +DN4 13 14 DIN +VN3 12 0 DC 2 +VN4 0 14 DC 2 +* +* CURRENT NOISE SOURCE +* +DN5 15 16 DIN +DN6 16 17 DIN +VN5 15 0 DC 2 +VN6 0 17 DC 2 +* +* GAIN STAGE & DOMINANT POLE AT 0.439 HZ +* +R7 18 98 1.45E7 +C3 18 98 25E-9 +G1 98 18 5 6 5.15E-3 +V2 97 19 1.5 +V3 20 51 1.5 +D3 18 19 DX +D4 20 18 DX +* +* POLE/ZERO PAIR AT 1.5MHz/12.7MHz +* +R8 21 98 1E3 +R9 21 22 1.25E3 +C4 22 98 10E-12 +G2 98 21 18 28 1E-3 +* +* POLE AT 2568 MHz +* +R10 23 98 1 +C5 23 98 62E-12 +G3 98 23 21 28 1 +* +* POLE AT 2568 MHz +* +R11 24 98 1 +C6 24 98 62E-12 +G4 98 24 23 28 1 +* +* POLE AT 2568 MHz +* +R14 27 98 1 +C8 27 98 62E-12 +G5 98 27 24 28 1 +* +* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ +* +R12 25 26 1E6 +C7 25 26 159.155E-12 +R13 26 98 1 +E2 25 98 POLY(2) 1 98 2 98 0 0.28 0.28 +* +*PSRR=121dB +EPSY 98 72 POLY(1) (99,50) 0 1 +RPS3 72 73 1E6 +CPS3 72 73 3E-9 +RPS4 73 98 1 + +* OUTPUT STAGE +* +R15 28 99 100E3 +R16 28 50 100E3 +C9 28 50 1E-6 +ISY 99 50 250E-6 +R17 29 99 100 +R18 29 50 100 +L2 29 34 1E-9 +G6 32 50 27 29 10E-3 +G7 33 50 29 27 10E-3 +G8 29 99 99 27 10E-3 +G9 50 29 27 50 10E-3 +V4 30 29 1.3 +V5 29 31 3.8 +F1 29 0 V4 1 +F2 0 29 V5 1 +D5 27 30 DX +D6 31 27 DX +D7 99 32 DX +D8 99 33 DX +D9 50 32 DY +D10 50 33 DY +* +* MODELS USED +* +.MODEL QX PNP(BF=5E5) +.MODEL DX D(IS=1E-12) +.MODEL DY D(IS=1E-15 BV=50) +.MODEL DZ D(IS=1E-15 BV=7.0) +.MODEL DEN D(IS=1E-12 RS=6.8E3 KF=1.95E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=77.3E-6 KF=3.38E-15 AF=1) +.ENDS OP4177 + + + + + + + +* OP484 SPICE Macro-model +* 1.0 (11/1995) +* Copyright 1993, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP484 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +Q1 5 2 3 QIN 1 +Q2 6 11 3 QIN 1 +Q3 7 2 4 QIP 1 +Q4 8 11 4 QIP 1 +DC1 2 11 DC +DC2 11 2 DC +Q5 4 9 99 QIP 1 +Q6 9 9 99 QIP 1 +Q7 3 10 50 QIN 1 +Q8 10 10 50 QIN 1 +R1 99 5 4E3 +R2 99 6 4E3 +R3 7 50 4E3 +R4 8 50 4E3 +IREF 9 10 50.5E-6 +EOS 1 11 POLY(2) (22,98) (14,98) -25E-6 1E-2 1 +IOS 2 1 1E-9 +CIN 1 2 2E-12 +GN1 98 1 (17,98) 1E-3 +GN2 98 2 (23,98) 1E-3 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +VN1 13 98 DC 2 +VN2 98 15 DC 2 +DN1 13 14 DEN +DN2 14 15 DEN +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +VN3 16 98 DC 2 +VN4 98 18 DC 2 +DN3 16 17 DIN +DN4 17 18 DIN +* +* 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE +* +VN5 19 98 DC 2 +VN6 98 24 DC 2 +DN5 19 23 DIN +DN6 23 24 DIN +* +* GAIN STAGE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 +R9 20 98 1E3 +* +* COMMON MODE STAGE WITH ZERO AT 100HZ +* +ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 +R10 21 22 1 +R11 22 98 100E-6 +C4 21 22 1.592E-3 +* +* NEGATIVE ZERO AT 20MHZ +* +E1 27 98 (20,98) 1E6 +R17 27 28 1 +R18 28 98 1E-6 +C8 25 26 7.958E-9 +ENZ 25 98 (27,28) 1 +VNZ 26 98 DC 0 +FNZ 27 28 VNZ -1 +* +* POLE AT 40MHZ +* +G4 98 29 (28,98) 1 +R19 29 98 1 +C9 29 98 3.979E-9 +* +* POLE AT 40MHZ +* +G5 98 30 (29,98) 1 +R20 30 98 1 +C10 30 98 3.979E-9 +* +* OUTUT STAGE +* +ISY 99 50 0.276E-3 +GIN 50 31 POLY(1) (30,98) .862574E-6 505.879E-6 +RIN 31 50 2.75E6 +VB 99 32 0.7 +Q11 32 31 33 QON 1 +R21 33 34 4.5E3 +I1 34 50 50E-6 +R22 99 35 6E3 +Q12 36 36 35 QOP 1 +I2 36 50 50E-6 +R23 99 37 2.6E3 +R24 34 38 5E3 +Q13 39 36 37 QOP 1 +Q14 39 38 40 QON 1.5 +R25 40 50 40 +Q15 39 39 41 QON 1 +R26 41 42 1E3 +R27 99 43 220 +Q16 44 44 43 QOP 1.5 +Q17 44 39 42 QON 1 +R28 42 50 2E3 +VSCP 99 97 DC 0.088 +FSCP 46 99 VSCP 1 +RSCP 46 99 40 +Q20 44 46 99 QOP 1 +Q18 45 44 97 QOP 4.5 +Q19 45 34 51 QON 4.5 +VSCN 51 50 DC 0.081 +FSCN 50 47 VSCN 1 +RSCN 47 50 40 +Q21 34 47 50 QON 1 +CC2 31 45 20E-12 +CF1 31 34 15E-12 +CF2 31 42 15E-12 +CO1 34 45 15E-12 +CO2 42 45 5E-12 +D3 45 99 DX +D4 50 45 DX +.MODEL DC D(IS=130E-21) +.MODEL DX D() +.MODEL DEN D(RS=100 KF=12E-15 AF=1) +.MODEL DIN D(RS=5.358 KF=56E-15 AF=1) +.MODEL QIN NPN(BF=120 VA=200 IS=0.5E-16) +.MODEL QIP PNP(BF=90 VA=60 IS=0.5E-16) +.MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50) +.MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160) +.ENDS OP484 + + +* OP492 SPICE Macro-model +* 2.0 (03/1995) +* Copyright 1993, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP492 2 1 99 50 34 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE AND POLE AT 40MHZ +* +I1 99 4 50E-6 +IOS 2 1 10E-9 +EOS 2 3 POLY(1) (21,30) 1.5E-3 75 +CIN 1 2 3E-12 +Q1 5 1 7 QP +Q2 6 3 8 QP +R3 5 50 2E3 +R4 6 50 2E3 +R5 4 7 966 +R6 4 8 966 +C1 5 6 .995E-12 +* +* GAIN STAGE +* +EREF 98 0 (30,0) 1 +G1 98 9 (5,6) 500E-6 +R7 9 98 210.819E3 +D1 9 10 DX +D2 11 9 DX +V1 99 10 .6 +V2 11 50 .6 +* +* ZERO/POLE AT 6MHZ/12MHZ +* +E1 12 98 (9,30) 2 +R8 12 13 1 +R9 13 98 1 +C3 12 13 26.526E-9 +* +* ZERO AT 15MHZ +* +E2 14 98 (13,30) 1E6 +R10 14 15 1E6 +R11 15 98 1 +C4 14 15 10.610E-15 +* +* COMMON MODE STAGE WITH ZERO AT 40KHZ +* +ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 +R20 20 21 1E6 +R21 21 98 1 +C5 20 21 3.979E-12 +* +* POLE AT 100MHZ +* +G2 98 16 (15,30) 1 +R12 16 98 1 +C6 16 98 1.592E-9 +* +* OUTPUT STAGE +* +RS1 99 30 1E6 +RS2 30 50 1E6 +ISY 99 50 .44E-3 +G3 31 50 POLY(1) (16,30) -1.635E-6 4E-6 +R16 31 50 1E6 +DCL 50 31 DZ +I2 99 32 250E-6 +RCL 33 50 56 +M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 +CC 31 32 14E-12 +Q3 99 32 34 QNA +Q4 33 32 34 QPA +Q5 31 33 50 QNA +.MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 ++ ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 ++ ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 ++ CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 ++ CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) +.MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 ++ ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 ++ ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 ++ CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 ++ CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) +.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 ++ TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 ++ XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 ++ MJ=0.407 CJSW=0.5E-9 MJSW=0.33) +.MODEL QP PNP(BF=61.5) +.MODEL DX D +.MODEL DZ D(BV=3.6) +.ENDS OP492 + + +* OP727 SPICE Macro-model Typical Values +* Revision History: 08/10/2012 - Updated to new header style +* 1.2 (04/2009) - Corrected EVP, EVN +* 1.1 (08/2000) +* Copyright 2000, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT OP727 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* PNP INPUT STAGE +* +Q1 5 7 3 PIX +Q2 6 2 3 PIX +RC1 5 50 8000 +RC2 6 50 8000 +C1 5 6 0.5E-12 +D1 3 8 DX +V1 99 8 DC 1.0 +I1 99 3 50E-6 +EOS 7 1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1 +IOS 2 1 1E-9 +* +* PSRR=120dB, ZERO AT 150Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 1E+6 +CPS3 72 73 1.06E-9 +RPS4 73 98 1 +* +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 15 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 0 2.6E-6 +* +* +* CMRR 110dB, ZERO AT 400Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 1E+6 +CCM1 21 22 0.397E-9 +RCM2 22 98 1 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (5,6) 0 28.8E-6 +R1 30 98 2.02E+8 +CF 45 30 50E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=0.329E-3 +M6 45 47 50 50 NOX L=1E-6 W=0.496E-3 +EG1 99 46 POLY(1) (98,30) 0.6299 1 +EG2 47 50 POLY(1) (30,98) 0.5739 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS OP727 + + +* OP747 SPICE Macro-model Typical Values +* 1.2 (04/2009) - Corrected EVP, EVN +* 1.1 (08/2000) +* Copyright 2000, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT OP747 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* PNP INPUT STAGE +* +Q1 5 7 3 PIX +Q2 6 2 3 PIX +RC1 5 50 8000 +RC2 6 50 8000 +C1 5 6 0.5E-12 +D1 3 8 DX +V1 99 8 DC 1.0 +I1 99 3 50E-6 +EOS 7 1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1 +IOS 2 1 1E-9 +* +* PSRR=120dB, ZERO AT 150Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 1E+6 +CPS3 72 73 1.06E-9 +RPS4 73 98 1 +* +* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 15 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 0 2.6E-6 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* +* CMRR 110dB, ZERO AT 400Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 1E+6 +CCM1 21 22 0.397E-9 +RCM2 22 98 1 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (5,6) 0 28.8E-6 +R1 30 98 2.02E+8 +CF 45 30 50E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=0.329E-3 +M6 45 47 50 50 NOX L=1E-6 W=0.496E-3 +EG1 99 46 POLY(1) (98,30) 0.6299 1 +EG2 47 50 POLY(1) (30,98) 0.5739 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS OP747 + + + + + +* OP777 SPICE Macro-model Typical Values +* 1.2 (04/2009) - Corrected EVP, EVN +* 1.1 (08/2000) +* Copyright 2000, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT OP777 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* PNP INPUT STAGE +* +Q1 5 7 3 PIX +Q2 6 2 3 PIX +RC1 5 50 8000 +RC2 6 50 8000 +C1 5 6 0.5E-12 +D1 3 8 DX +V1 99 8 DC 1.0 +I1 99 3 50E-6 +EOS 7 1 POLY(3) (73,98) (81,98) (22,98) 0.08E-3 1 1 1 +IOS 2 1 1E-9 +* +* PSRR=120dB, ZERO AT 150Hz +* +RPS1 70 0 1E+6 +RPS2 71 0 1E+6 +CPS1 99 70 1E-5 +CPS2 50 71 1E-5 +EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +RPS3 72 73 1E+6 +CPS3 72 73 1.06E-9 +RPS4 73 98 1 +* +* VOLTAGE NOISE REFERENCE OF 15nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 15 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 0 2.6E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* +* CMRR 110dB, ZERO AT 400Hz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 1E+6 +CCM1 21 22 0.397E-9 +RCM2 22 98 1 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (5,6) 0 28.8E-6 +R1 30 98 2.02E+8 +CF 45 30 50E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=0.329E-3 +M6 45 47 50 50 NOX L=1E-6 W=0.496E-3 +EG1 99 46 POLY(1) (98,30) 0.6299 1 +EG2 47 50 POLY(1) (30,98) 0.5739 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=2.5E-23,AF=1) +.MODEL PIX PNP (BF=2273,IS=1E-14,VAF=130) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS OP777 + +* AD8235 SPICE Macro-model +* 1.0 (12/2009) +* Copyright 2009, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this +* model indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: VSY=5V, T=25°C +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* -input +* | rg1 +* | | rg2 +* | | | +input +* | | | | shutdwn Neg Supply +* | | | | | | ref +* | | | | | | | out +* | | | | | | | | Pos Supply +* | | | | | | | | | +.SUBCKT AD8235 Vin- RG- RG+ Vin+ SDN VNEG REF VOUT VPOS +*Amplifiers +X_U1 Vin- RG- 1 2 9 AMPA +X_U2 Vin+ 7 1 2 VOUT AMPB +*Gain Error for RG resistor +R5 7 RG+ 6 +*Adjustable Supply Current for Low Supply Voltage +I3 1 2 6.5E-6 +G1 1 2 2 1 1.5E-6 +* Shutdown Switches +S1 1 VPOS SDN VNEG SW +S2 2 VNEG SDN VNEG SW +*Resistor Network +R1 REF RG- 209.8K +R2 RG- 9 52.5K +R3 9 7 52.5K +R4 7 VOUT 209.85K +*Switch Model +.MODEL SW VSWITCH(VON=1.3 VOFF=0.5 RON=1 ROFF=1E9) +.ENDS AD8235 +*$ +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AMPA 1 2 99 50 45 +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=2E-6 W=9.070E-04 +M2 6 2 8 8 PIX L=2E-6 W=9.070E-04 +Cinp 1 50 4.2pF +Cinn 2 50 4.2pF +Cdiff 1 2 3pF +RD1 4 50 5.333E+04 +RD2 6 50 5.333E+04 +C1 4 6 7.650E-12 +I1 99 8 7.500E-06 +V1 9 8 +0.025E-00 +D1 9 99 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 0 1 1 1 1 +IOS 1 2 -5.0E-12 +* +* CMRR=95dB, POLE AT 3500 Hz +* +E1 72 98 POLY(2) (1,98) (2,98) 0 1.289E-02 1.289E-02 +R10 72 73 4.613E+01 +R20 73 98 3.183E-02 +C10 72 73 1.000E-06 +* +* PSRR=100dB, POLE AT 100 Hz +* +EPSY 21 98 POLY(1) (99,50) -0.181E-00 -0.03E-00 +RPS1 21 22 1.274E+04 +RPS2 22 98 2.989E-00 +CPS1 21 22 0.20E-07 +* +* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 17.500E-3 +HN 81 98 VN1 4.62E+1 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 20000 Hz +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6531 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) +0.580E-06 0.2710E-06 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* GAIN STAGE +* +G1 98 30 (4,6) 4.474E-04 +R1 30 98 1.00E+06 +CF 30 31 1.55E-08 +RZ 455 31 1.2280E-03 +EZ 455 98 (451 98) 1 +V3 32 30 0.279E+00 +V4 30 33 0.362E-00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 451 46 99 99 POX L=1E-6 W=3.940E-04 +M6 451 47 50 50 NOX L=1E-6 W=4.598E-04 +Lout 451 45 10pH +EG1 99 46 POLY(1) (98,30) 3.598E-01 1 +EG2 47 50 POLY(1) (30,98) 3.574E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=3.00E-05,VTO=-0.328,LAMBDA=0.015,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=3.00E-05,VTO=+0.328,LAMBDA=0.015,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=12.400E-11) +* +* +.ENDS AMPA +* +*$ +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AMPB 1 2 99 50 45 +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=2E-6 W=9.070E-04 +M2 6 2 8 8 PIX L=2E-6 W=9.070E-04 +Cinp 1 50 4.2pF +Cinn 2 50 4.2pF +Cdiff 1 2 3pF +RD1 4 50 5.333E+04 +RD2 6 50 5.333E+04 +C1 4 6 7.650E-12 +I1 99 8 7.500E-06 +V1 9 8 +0.025E-00 +D1 9 99 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 0.926m 1 1 1 1 +IOS 1 2 -10E-12 +* +* CMRR=95dB, POLE AT 3500 Hz +* +E1 72 98 POLY(2) (1,98) (2,98) 0 1.289E-02 1.289E-02 +R10 72 73 4.613E+01 +R20 73 98 3.183E-02 +C10 72 73 1.000E-06 +* +* PSRR=100dB, POLE AT 100 Hz +* +EPSY 21 98 POLY(1) (99,50) -0.181E-00 0.03E-00 +RPS1 21 22 2.274E+04 +RPS2 22 98 1.989E-00 +CPS1 21 22 0.20E-07 +* +* VOLTAGE NOISE REFERENCE OF 45nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 17.500E-3 +HN 81 98 VN1 4.62E+1 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 20000 Hz +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6531 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) +0.580E-06 0.2710E-06 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* GAIN STAGE +* +G1 98 30 (4,6) 4.474E-04 +R1 30 98 1.00E+06 +CF 30 31 1.55E-08 +RZ 455 31 1.2280E-03 +EZ 455 98 (451 98) 1 +V3 32 30 0.279E+00 +V4 30 33 0.362E-00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 451 46 99 99 POX L=1E-6 W=3.940E-04 +M6 451 47 50 50 NOX L=1E-6 W=4.598E-04 +Lout 451 45 10pH +EG1 99 46 POLY(1) (98,30) 3.598E-01 1 +EG2 47 50 POLY(1) (30,98) 3.574E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=3.00E-05,VTO=-0.328,LAMBDA=0.015,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=3.00E-05,VTO=+0.328,LAMBDA=0.015,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=12.400E-11) +* +* +.ENDS AMPB +* +* AD8236 SPICE Macro-model +* Copyright 2009, 2015 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +* BEGIN Notes: VSY=5V, T=25°C +**Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Supply Current, Input CM limits and Typ output voltge swing over full supply range, +* Bandwidth over all gains, Slew Rate, Output current limits, Voltage & Current Noise, +* Capacitive load drive, CMRR, Output Swing vs. Load Resistance +* Single supply & offset supply functionality. +* END Notes +* +* +* Node Assignments +* -input +* | rg1 +* | | rg2 +* | | | +input +* | | | | +* | | | | Neg Supply +* | | | | | ref out +* | | | | | | | Pos Supply +* | | | | | | | | +* +.SUBCKT AD8236 Vin- RG- RG+ Vin+ VNEG REF VOUT VPOS +* +*Amplifiers +X_U1 Vin- RG- VPOSa VNEGa 9 AMPA +X_U2 Vin+ 7 VPOSa VNEGa VOUT AMPB +* +*Charge pump for VPOS and VNEG +VposCP VPOSa VPOS dc 0.58 +VnegCP VNEG VNEGa dc 0.57 +* +*Gain Error for RG resistor +R5 7 RG+ 6 +* +*Adjustable Supply Current for Low Supply Voltage +*I3 VPOS VNEG 6.5E-6 +*G1 VPOS VNEG VNEG VPOS 1.5E-6 +* +*Resistor Network +R1 REF RG- 209.8K +R2 RG- 9 52.5K +R3 9 7 52.5K +R4 7 VOUT 209.85K +.Subckt AMPA 100 101 102 103 104 +* +***Power Supplies*** +Rz1 102 1020 1e-6 +Rz2 103 1030 1e-6 +Ibias 1020 1030 dc 0.001e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 0.015e-3 +RSW1 98 1030 1e-3 +R1 1020 99 1e7 +R2 99 1030 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +RSW2 1 100 1e-3 +RSW3 9 101 1e-3 +VOS 1 2 dc -500e-6 +IbiasP 110 2 dc 1.5e-12 +IbiasN 110 9 dc 1.5e-12 +RinCMP 110 2 110000e6 +RinCMN 9 110 110000e6 +CinCMP 110 2 4.2e-12 +CinCMN 9 110 4.2e-12 +IOS 9 2 0.0000005e-6 +RinDiff 9 2 220000e3 +CinDiff 9 2 3e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 1e3 +RX1 40 3 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 0.46 +VinN 42 112 dc 0.46 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.4071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.4071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.4071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.4071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 1e12 +RcmrrN 10 9 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 1e3 +e4 5 3 11 110 1 +* +* +* +***Feedback Pin*** +*RF 105 104 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 0.1 Hz*** +g210 210 110 200 110 0.0025e-6 +R210 210 110 1591547.63e6 +C210 210 110 1e-12 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.022 +VoutN 64 66 dc 5.022 +e60 65 110 111 110 1.01 +e61 66 110 112 110 1.01 +* +* +***Pole at 1000000Hz*** +g220 220 110 210 110 0.001 +R220 220 110 1000 +C220 220 110 159.1548e-12 +* +***Pole at 0.4MHz*** +g230 230 110 220 110 0.001 +R230 230 110 1000 +C230 230 110 397.8869e-12 +* +***Pole at 0.5MHz*** +g240 240 110 230 110 0.001 +R240 240 110 1000 +C240 240 110 318.3095e-12 +* +***Buffer*** +g245 245 110 240 110 0.001 +R245 245 110 1000 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 10 +* +***Buffer*** +e290 290 110 285 110 1 +R290 290 292 10 +e295 295 110 292 110 1 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 1000 +e301 301 110 300 110 1 +Rout 302 303 180 +Lout 303 310 10e-9 +Cout 310 110 2e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 3.836 +VIoutN 304 306 dc 3.836 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 1.27 +VoutN1 74 112 dc 1.26 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +RSW4 104 313 1e-3 +* +* +*** Common Models *** +.model diode d(bv=100) +.model DClamp D(IS=1E-15 IBV=1E-13 VJ=0.1) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=10.821) +.model DzSlewN D(BV=2.842) +.model DVnoisy D(IS=7.49e-14 KF=9.87e-18) +.model DINnoisy D(IS=8.58e-21 KF=0.00e0) +.model DIPnoisy D(IS=8.58e-21 KF=0.00e0) +* +* +.ENDS AMPA +* +.subckt AMPB 100 101 102 103 104 +* +***Power Supplies*** +Rz1 102 1020 1e-6 +Rz2 103 1030 1e-6 +Ibias 1020 1030 dc 0.001e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 0.015e-3 +RSW1 98 1030 1e-3 +R1 1020 99 1e7 +R2 99 1030 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +RSW2 1 100 1e-3 +RSW3 9 101 1e-3 +VOS 1 2 dc 500e-6 +IbiasP 110 2 dc 0.000001e-6 +IbiasN 110 9 dc 0.000001e-6 +RinCMP 110 2 110000e6 +RinCMN 9 110 110000e6 +CinCMP 110 2 4.2e-12 +CinCMN 9 110 4.2e-12 +IOS 9 2 0.0000005e-6 +RinDiff 9 2 220000e3 +CinDiff 9 2 3e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 1e3 +RX1 40 3 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 0.46 +VinN 42 112 dc 0.46 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.4071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.4071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.4071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.4071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 1e12 +RcmrrN 10 9 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 1e3 +e4 5 3 11 110 1 +* +* +** +* +***Feedback Pin*** +*RF 105 104 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 0.1 Hz*** +g210 210 110 200 110 0.0025e-6 +R210 210 110 1591547.63e6 +C210 210 110 1e-12 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.022 +VoutN 64 66 dc 5.022 +e60 65 110 111 110 1.01 +e61 66 110 112 110 1.01 +* +* +***Pole at 1000000Hz*** +g220 220 110 210 110 0.001 +R220 220 110 1000 +C220 220 110 159.1548e-12 +* +***Pole at 0.4MHz*** +g230 230 110 220 110 0.001 +R230 230 110 1000 +C230 230 110 397.8869e-12 +* +***Pole at 0.5MHz*** +g240 240 110 230 110 0.001 +R240 240 110 1000 +C240 240 110 318.3095e-12 +* +***Buffer*** +g245 245 110 240 110 0.001 +R245 245 110 1000 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 10 +* +***Buffer*** +e290 290 110 285 110 1 +R290 290 292 10 +e295 295 110 292 110 1 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 1000 +e301 301 110 300 110 1 +Rout 302 303 180 +Lout 303 310 1e-9 +Cout 310 110 2e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 3.836 +VIoutN 304 306 dc 3.836 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 1.27 +VoutN1 74 112 dc 1.26 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +RSW4 104 313 1e-3 +* +* +*** Common Models *** +.model diode d(bv=100) +.model DClamp D(IS=1E-15 IBV=1E-13 VJ=0.1) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=10.821) +.model DzSlewN D(BV=2.842) +.model DVnoisy D(IS=7.49e-14 KF=9.87e-18) +.model DINnoisy D(IS=8.58e-21 KF=0.00e0) +.model DIPnoisy D(IS=8.58e-21 KF=0.00e0) +* +.ENDS AMPB +.ENDS AD8236 +* +* + +* AD8634 SPICE Macro-model +* Function: Amplifier +* +* Revision History: +* Rev. 0.0 (Mar 2014) ADSJ-RM +* Copyright 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html +* for License Statement. Use of this model indicates your acceptance +* of the terms and provisions in the License Statement. +* +* modeled: +* +/-15V (30V) only, not checked at lower voltages +* modeling based on the typical values stated in the datasheet table +* +* Parameters modeled include:VOS , CMRR, PSRR, voltage noise, +* Vdo, gbw & phase margin, slew rate, CL Zout, Isy, ISC +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8634 1 2 99 50 45 + + +* INPUT STAGE +* +Q1 5 11 301 QIN 1; 301 +Q2 6 2 302 QIN 1; 302 +Cx1 5 6 7.0E-12 +Q3 7 11 303 QIP 1; 303 +Q4 8 2 304 QIP 1; 304 +Cx2 7 8 7.0E-12 +DC1 2 11 DC +DC2 11 2 DC +Q5 4 9 99 QIP 1; +Q6 9 9 99 QIP 1 +Q7 3 10 50 QIN 1; +Q8 10 10 50 QIN 1 +R1 99 5 4.5E3 +R2 99 6 4.5E3 +R3 7 50 4.0E3 +R4 8 50 4.0E3 +RE1 301 3 12.0E+1 +RE2 302 3 12.0E+1 +RE3 303 4 12.0E+1 +RE4 304 4 12.0E+1 +IREF 9 10 69E-06 +GREF 9 10 POLY(1) (99,50) 0 2.5E-07 +EOS 1 11 POLY(4) (81,98)(83,98)(22,98)(73,98) -90E-6 1 1 1 1 +IOS 1 2 -10E-09 +CIN 1 2 1.1E-12 +CICM1 1 50 2.4E-12 +CICM2 2 50 2.4E-12 +Dinp1 1 99 DC +Dinp2 50 1 DC +Dinn1 2 99 DC +Dinn2 50 2 DC +GN1 1 98 POLY(1) (1,50) 53E-09 -2.15E-9 +GN2 2 98 POLY(1) (2,50) 56E-09 -2.11E-9 +* + +G101 98 211 POLY(2) (5,6) (7,8) 0 5.3E-04 5.3E-04 +R101 211 98 1.0E6 +* +E201 311 98 POLY(1) (211,98)0 2.0E+0 +R202 311 321 1.8E+3; +C202 311 321 8E-16 +R203 321 98 1.8E+3 +* +E3 252 98 (321 98) 2E-0 +R31 252 253 1.0E+3 +C31 253 252 9E-11; -12 +R32 253 98 1.0E+3 +* +* GAIN STAGE +* +G2 98 251 (253, 98) 1.0E-06 +R5 251 98 8.2E5 +RF 251 250 75.0E+00 +CF 245 250 40.5E-11 +EF (245 98) (45,98) 1 +D3 251 451 DX +D4 452 251 DX +V1 451 98 -0.038 ; +V2 452 98 -0.29 +* +* CMRR +* +ECM 72 98 POLY(2) (1,98) (2,98) 0 3.42E-03 3.42E-03 +RCM1 72 73 3.061E+01 +RCM2 73 98 7.958E-03 +CCM1 72 73 1.0E-6 +* +* PSRR +* +EPSY 21 98 POLY(1) (99,50) -197.534E+00 6.584E-00 +RPS1 21 22 5.341E+03 +RPS2 22 98 7.958E-04 +CPS1 21 22 1.000E-06 +* +* VOLTAGE NOISE +* +VN1 80 98 0 +RN1 80 98 43.5E-3 +HN 81 98 VN1 5.3 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE 1000 +IFN 98 82 DC 1E-03 +DFN2 182 98 DNOISE +IFN2 98 182 DC 1E-06 +GFN 83 98 POLY(1) (182,82) 1.00E-13 1.00E-04 +RFN 83 98 1 +* +D60 60 0 DN1 1000 +I60 0 60 1M +D61 61 0 DN4 +I61 0 61 1U +D62 62 0 DN3 +I62 0 62 1U +D63 63 0 DN2 +I63 0 63 1U +G60 3 50 61 60 .007 +G61 2 50 61 60 .008 +G62 3 2 62 60 .000092 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 POLY(1) (99,50) 403E-6 6.036E-6 +* +* OUTPUT STAGE +* +Q33 450 41 99 POUT +Cco1 450 41 2.5E-12 +RB1 40 41 1.5E3 +EB1 99 40 POLY(1) (98,251) 7.535E-01 1; +Q34 450 43 50 NOUT +Cco2 450 43 5E-12 +RB2 42 43 2.0E3 +EB2 42 50 POLY(1) (251,98) 7.520E-01 1; +Lout 45 450 1E-09 +* +* MODELS +* +.MODEL DC D(IS=1E-14,CJO=1E-15) +.MODEL DX D(IS=1E-14,CJO=1E-15) +.MODEL DY D(IS=1E-16,RS=0.1) +.MODEL DIN1 D(RS=5.358 KF=56E-15 AF=1) +.MODEL DIN2 D(RS=5.358 KF=56E-15 AF=1) +.MODEL DN1 D IS=1E-16 +.MODEL DN2 D IS=1E-16 AF=1 KF=1.05E-17 +.MODEL DN3 D IS=1E-16 AF=1 KF=2.8E-17 +.MODEL DN4 D IS=1E-16 AF=1 KF=4.5E-17 + +.MODEL DNOISE D(IS=1E-16,RS=1E-3,KF=1.14E-11) +.MODEL QIN NPN(BF=130 VA=200 IS=0.5E-16) +.MODEL QIP PNP(BF=80 VA=140 IS=0.5E-16) +.MODEL NOUT NPN(BF=140 VA=350 IS=0.5E-16 BR=8.4 VAR=20 RC=4.0E1) +.MODEL POUT PNP(BF=80 VA=130 IS=0.5E-16 BR=5 VAR=20 RC=6.0E1) +* +.ENDS AD8634 + +* AD8220 SPICE Macro-model 09/09, Rev. C +* PRB IAP ADI +* +* Revision History: +* +* Node assignments +* inverting input +* | RG +* | | RG +* | | | non_inverting input +* | | | | negative supply +* | | | | | ref +* | | | | | | output +* | | | | | | | positive supply +* | | | | | | | | +.SUBCKT AD8220 IN- RG- RG+ IN+ -Vs REF VOUT +Vs +** INPUT STAGE +R1 N009 N008 20E3 +R2 N008 Inverting_Out 20E3 +R3 N013 noninverting_out 20.002e3 +R4 REF N013 20e3 +R5 RG- N003 24700 +R6 RG+ N012 24724 +D3 N003 P001 D +D4 P002 N003 D +V3 P002 VNEGx 0.84 +V4 VPOSx P001 2.35 +D5 N012 P003 D +D6 P004 N012 D +V5 P004 VNEGx 0.84 +V6 VPOSx P003 2.35 +D7 N005 P005 D +D8 P006 N005 D +V7 P006 VNEGx -10 +V8 VPOSx P005 -10 +D9 N019 P007 D +D10 P008 N019 D +V9 P008 VNEGx -10 +V10 VPOSx P007 -10 +D11 N009 P009 D +D12 P010 N009 D +V11 P010 N016 1.03 +V12 N010 P009 1 +D13 REF P011 D +D14 P012 REF D +V13 P012 VNEGx .3 +V14 VPOSx P011 .3 +D15 N013 P013 D +D16 P014 N013 D +V15 P014 VNEGx 0.6 +V16 VPOSx P013 0.6 +E4 Inverting_Out 0 N003 0 1 +E5 noninverting_out 0 N012 0 1 +Q1 Inv_Fdbk N002 RG- 0 PNP +Q2 Pos_Fdbk N015 RG+ 0 PNP +V1 VBIAS -Vs -10 +I1 Pos_Fdbk VBIAS 9E-6 +I2 Inv_Fdbk VBIAS 9E-6 + +C1 N003 Inv_Fdbk 3.8035e-12 +C2 N012 Pos_Fdbk 3.8e-12 +E8 N002 0 N005 0 1 +E9 N015 0 N019 0 1 +VOSI_Neg N004 IN- 25E-6 +VOSI_Pos IN+ N017 24E-6 +VOSO VOUT N011 300E-6 +C3 RG- 0 .200e-12 +C4 RG+ 0 .135e-12 +I23 IN- 0 3E-12 +I24 IN+ 0 3.2E-12 +G1 0 IN+ N020 N021 .7e-9 +R13 IN+ N020 10e9 +R14 N020 IN- 10e9 +R15 +Vs N021 10e9 +R16 N021 -Vs 10e9 +G2 0 IN- N020 N021 .7e-9 +E10 VPOSx 0 +Vs 0 1 +I3 +Vs -Vs 725E-6 +G3 +Vs -Vs +Vs -Vs 1e-6 +E11 VNEGx 0 -Vs 0 1 + +R17 VBIAS Inv_Fdbk 10e9 +R18 Pos_Fdbk VBIAS 10e9 +H3 N006 N004 V24 14 +V24 N001 0 0 +R19 N001 0 .0166 +H4 N011 N009 V25 100 +V25 N007 0 0 +R20 N007 0 .0166 +H5 N018 N017 V26 14 +V26 N014 0 0 +R21 N014 0 .0166 +G4 0 N005 N006 N005 1E-3 +G5 0 N019 N018 N019 1E-3 +G6 0 N003 VBIAS Inv_Fdbk 1 +G7 0 N012 VBIAS Pos_Fdbk 1 +G8 0 N009 N013 N008 1 +R10 N005 0 10e9 +R7 N003 0 10E9 +R11 N019 0 10E9 +R8 N012 0 10E9 +R9 N009 0 10E9 +*C5 N008 N009 8e-12 + + +H1 VPOSx N010 POLY(1) VOSO 0 0 8000 +H2 N016 VNEGx POLY(1) VOSO 0 0 8000 + +* MODELS USED +* +.model D D +.model PNP PNP (BF=10E5 VAF=20000) +.ENDS AD8220 + +* AD8221 SPICE Macro-model +* Revision History: +* A (10/2010) - PRB (Changed Negative Zero stage to remove the +* negative capacitor value.) +* C (09/2014) - SH (Improved convergence of input clamps, added 1/f noise and current noise, removed LIMIT statement, +* load currents from output and preamplifier are reflected in the supplies, bug fixes, organized netlist) +* Copyright 2010, 2014 by Analog Devices. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* Temperature effects +* PSRR +* +* Parameters modeled include: +* Gain error, Vos, Ibias +* Bandwidth +* Voltage and current noise with 1/f noise +* CMRR vs frequency +* Supply current incl preamp and output load currents +* Output clamp vs load +* Input common-mode range limitations +* Slew Rate +* Pulse response vs cap load +* +* END Notes +* +* Node assignments +* inverting input +* | RG +* | | RG +* | | | non_inverting input +* | | | | negative supply +* | | | | | ref +* | | | | | | output +* | | | | | | | positive supply +* | | | | | | | | +.SUBCKT AD8221 IN- RG- RG+ IN+ -Vs REF VOUT +Vs +** INPUT STAGE *** +FIBIAS1 IN- 0 POLY(1) V21 1.4e-9 4e-5 +VOSI_Neg 3 IN- 25E-6 +H3 4 3 V24 3 +G4 0 5 4 0 2e-3 +R10 5 0 500 +D7 5 9 D +D8 10 5 D +V7 10 VNEGx 1.8 +V8 VPOSx 9 1.1 +E8 22 0 5 0 1 +FIBIAS2 IN+ 0 POLY(1) V23 0.8e-9 4e-5 +VOSI_Pos IN+ 6 24E-6 +H5 7 6 V26 3 +G5 0 8 7 0 2e-3 +R11 8 0 500 +D9 8 11 D +D10 12 8 D +V9 12 VNEGx 1.8 +V10 VPOSx 11 1.1 +E9 15 0 8 0 1 +G1 0 IN+ 13 14 .0025e-9 +R13 IN+ 13 10e9 +R14 13 IN- 10e9 +R15 +Vs 14 10e9 +R16 14 -Vs 10e9 +G2 0 IN- 13 14 .0025e-9 +* +*** PREAMPLIFIER STAGE *** +Q1 Pos_Fdbk 15 RG+ 0 NPN +C4 RG+ 0 .135e-12 +R6 RG+ 17 24735 +VCS2 noninverting_out 17 0 +I1 VBIAS Pos_Fdbk 20E-6 +R23 Pos_Fdbk VBIAS 1e9 +G7 0 18 VBIAS Pos_Fdbk 1 +R8 18 0 10E9 +C2 noninverting_out Pos_Fdbk 9.2e-12 +R25 19 18 100 +D5 19 20 D +D6 21 19 D +V5 21 VNEGx 0.3 +V6 VPOSx 20 2.1 +Q2 Inv_Fdbk 22 RG- 0 NPN +C3 RG- 0 .200e-12 +R5 RG- 24 24735 +VCS1 Inverting_Out 24 0 +I2 VBIAS Inv_Fdbk 20E-6 +R18 VBIAS Inv_Fdbk 1e9 +G6 0 25 VBIAS Inv_Fdbk 1 +R7 25 0 10E9 +C1 Inverting_Out Inv_Fdbk 9.235e-12 +R24 26 25 100 +D3 26 27 D +D4 28 26 D +V3 28 VNEGx 0.3 +V4 VPOSx 27 2.1 +V1 VBIAS VPOSx 20 +D40 Inv_Fdbk VBIAS D +D41 Pos_Fdbk VBIAS D +* +*** SUBTRACTOR STAGE *** +E4 Inverting_Out 0 26 0 1 +E5 noninverting_out 0 19 0 1 +R1 31 sub_neg 10E3 +R2 sub_neg 24 10E3 +R3 sub_pos 17 10001 +R4 REF sub_pos 10E3 +VCS3 sub_out 31 0 +G8 0 sub_out sub_pos sub_neg 1 +R9 sub_out 0 10E9 +D13 REF 38 D +D14 39 REF D +V13 39 VNEGx .3 +V14 VPOSx 38 .3 +D15 sub_pos 36 D +D16 37 sub_pos D +V15 37 VNEGx 0.9 +V16 VPOSx 36 0.9 +R22 sub_out_cl sub_out 100 +D1 sub_out_cl 33 D +V2 32 33 1.15 +D2 34 sub_out_cl D +V17 34 35 1.05 +H6 VPOSx 32 POLY(1) VOSO 0 0 8000 +H7 35 VNEGx POLY(1) VOSO 0 0 8000 +H4 VX sub_out_cl V25 64 +* +*** SLEW RATE AND OUTPUT STAGE *** +G11 0 VZ VX VY 1e-3 +R26 VZ 0 100E6 +D21 40 VZ DSLEWP +D22 40 0 DSLEWN +G12 0 VY VZ 0 1E-4 +C7 VY 0 1E-9 +R30 VY 0 10e9 +G9 0 41 VY 42 1 +R12 41 0 1e10 +C5 41 0 1.4e-7 +G10 0 42 41 0 .002 +R17 42 0 500 +C6 42 0 700e-12 +R27 43 42 0.1 +D11 43 45 D +D12 46 43 D +V11 46 47 1.05 +V12 44 45 1.15 +H1 VPOSx 44 POLY(1) VOSO 0 0 8000 +H2 47 VNEGx POLY(1) VOSO 0 0 8000 +VOSO VOUT 43 300E-6 +* +*** NOISE *** +V24 60 0 0 +R19 60 0 .0166 +D17 61 60 DN +V18 61 0 0.2 +V26 62 0 0 +R21 62 0 .0166 +D18 63 62 DN +V19 63 0 0.2 +V25 64 0 0 +R20 64 0 .0166 +D19 65 64 DN +V20 65 0 0.2 +V21 70 0 0 +R28 70 0 .0166 +D38 71 70 DIN +V22 71 0 0.2 +V23 72 0 0 +R29 72 0 .0166 +D39 73 72 DIN +V27 73 0 0.2 +* +*** SUPPLY CURRENT AND BIASING *** +ISUP +Vs -Vs 800E-6 +GSUP +Vs -Vs +Vs -Vs 1e-6 +FSUP1 56 0 VOSO -1 +D20 +Vs 90 D +D23 52 -Vs D +D24 56 90 DZ +D25 52 56 DZ +FSUP2 57 0 VCS1 1 +D26 +Vs 91 D +D27 53 -Vs D +D28 57 91 DZ +D29 53 57 DZ +FSUP3 58 0 VCS2 1 +D30 +Vs 92 D +D31 54 -Vs D +D32 58 92 DZ +D33 54 58 DZ +FSUP4 59 0 VCS3 1 +D34 +Vs 93 D +D35 55 -Vs D +D36 59 93 DZ +D37 55 59 DZ +E10 VPOSx 0 +Vs 0 1 +E11 VNEGx 0 -Vs 0 1 +* +* +.MODEL NPN NPN +.MODEL D D(IS=1e-15 N=0.1) +.MODEL DN D(IS=1e-15 KF=3e-6) +.MODEL DIN D(IS=1e-15 KF=5e1 AF=1.5) +.MODEL DZ D(IS=1e-15 BV=50 RS=1) +.MODEL DSLEWP D(IS=1e-15 BV=19.5 RS=0.1) +.MODEL DSLEWN D(IS=1e-15 BV=19.5 RS=0.1) +* +.ENDS AD8221 +* +* AD8222 SPICE Macro-model +* Revision History: +* A (10/2010) - PRB (The AD8222 is a dual of the AD8221, this SPICE model +* is a single channel) +* C (09/2014) - SH (Improved convergence of input clamps, added 1/f noise and current noise, removed LIMIT statement, +* load currents from output and preamplifier are reflected in the supplies, bug fixes, organized netlist) +* Copyright 2010, 2014 by Analog Devices. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* Temperature effects +* PSRR +* +* Parameters modeled include: +* Gain error, Vos, Ibias +* Bandwidth +* Voltage and current noise with 1/f noise +* CMRR vs frequency +* Supply current incl preamp and output load currents +* Output clamp vs load +* Input common-mode range vs output swing limitations +* Slew Rate +* Pulse response vs cap load +* +* END Notes +* +* Node assignments +* inverting input +* | RG +* | | RG +* | | | non_inverting input +* | | | | negative supply +* | | | | | ref +* | | | | | | output +* | | | | | | | positive supply +* | | | | | | | | +.SUBCKT AD8222 IN- RG- RG+ IN+ -Vs REF VOUT +Vs +** INPUT STAGE *** +FIBIAS1 IN- 0 POLY(1) V21 1.4e-9 4e-5 +VOSI_Neg 3 IN- 25E-6 +H3 4 3 V24 3 +G4 0 5 4 0 2e-3 +R10 5 0 500 +D7 5 9 D +D8 10 5 D +V7 10 VNEGx 1.8 +V8 VPOSx 9 1.1 +E8 22 0 5 0 1 +FIBIAS2 IN+ 0 POLY(1) V23 0.8e-9 4e-5 +VOSI_Pos IN+ 6 24E-6 +H5 7 6 V26 3 +G5 0 8 7 0 2e-3 +R11 8 0 500 +D9 8 11 D +D10 12 8 D +V9 12 VNEGx 1.8 +V10 VPOSx 11 1.1 +E9 15 0 8 0 1 +G1 0 IN+ 13 14 .0025e-9 +R13 IN+ 13 10e9 +R14 13 IN- 10e9 +R15 +Vs 14 10e9 +R16 14 -Vs 10e9 +G2 0 IN- 13 14 .0025e-9 +* +*** PREAMPLIFIER STAGE *** +Q1 Pos_Fdbk 15 RG+ 0 NPN +C4 RG+ 0 .135e-12 +R6 RG+ 17 24735 +VCS2 noninverting_out 17 0 +I1 VBIAS Pos_Fdbk 20E-6 +R23 Pos_Fdbk VBIAS 1e9 +G7 0 18 VBIAS Pos_Fdbk 1 +R8 18 0 10E9 +C2 noninverting_out Pos_Fdbk 9.2e-12 +R25 19 18 100 +D5 19 20 D +D6 21 19 D +V5 21 VNEGx 0.3 +V6 VPOSx 20 2.1 +Q2 Inv_Fdbk 22 RG- 0 NPN +C3 RG- 0 .200e-12 +R5 RG- 24 24735 +VCS1 Inverting_Out 24 0 +I2 VBIAS Inv_Fdbk 20E-6 +R18 VBIAS Inv_Fdbk 1e9 +G6 0 25 VBIAS Inv_Fdbk 1 +R7 25 0 10E9 +C1 Inverting_Out Inv_Fdbk 9.235e-12 +R24 26 25 100 +D3 26 27 D +D4 28 26 D +V3 28 VNEGx 0.3 +V4 VPOSx 27 2.1 +V1 VBIAS VPOSx 20 +D40 Inv_Fdbk VBIAS D +D41 Pos_Fdbk VBIAS D +* +*** SUBTRACTOR STAGE *** +E4 Inverting_Out 0 26 0 1 +E5 noninverting_out 0 19 0 1 +R1 31 sub_neg 10E3 +R2 sub_neg 24 10E3 +R3 sub_pos 17 10001 +R4 REF sub_pos 10E3 +VCS3 sub_out 31 0 +G8 0 sub_out sub_pos sub_neg 1 +R9 sub_out 0 10E9 +D13 REF 38 D +D14 39 REF D +V13 39 VNEGx .3 +V14 VPOSx 38 .3 +D15 sub_pos 36 D +D16 37 sub_pos D +V15 37 VNEGx 0.9 +V16 VPOSx 36 0.9 +R22 sub_out_cl sub_out 100 +D1 sub_out_cl 33 D +V2 32 33 1.15 +D2 34 sub_out_cl D +V17 34 35 1.05 +H6 VPOSx 32 POLY(1) VOSO 0 0 8000 +H7 35 VNEGx POLY(1) VOSO 0 0 8000 +H4 VX sub_out_cl V25 64 +* +*** SLEW RATE AND OUTPUT STAGE *** +G11 0 VZ VX VY 1e-3 +R26 VZ 0 100E6 +D21 40 VZ DSLEWP +D22 40 0 DSLEWN +G12 0 VY VZ 0 1E-4 +C7 VY 0 1E-9 +R30 VY 0 10e9 +G9 0 41 VY 42 1 +R12 41 0 1e10 +C5 41 0 1.4e-7 +G10 0 42 41 0 .002 +R17 42 0 500 +C6 42 0 700e-12 +R27 43 42 0.1 +D11 43 45 D +D12 46 43 D +V11 46 47 1.05 +V12 44 45 1.15 +H1 VPOSx 44 POLY(1) VOSO 0 0 8000 +H2 47 VNEGx POLY(1) VOSO 0 0 8000 +VOSO VOUT 43 300E-6 +* +*** NOISE *** +V24 60 0 0 +R19 60 0 .0166 +D17 61 60 DN +V18 61 0 0.2 +V26 62 0 0 +R21 62 0 .0166 +D18 63 62 DN +V19 63 0 0.2 +V25 64 0 0 +R20 64 0 .0166 +D19 65 64 DN +V20 65 0 0.2 +V21 70 0 0 +R28 70 0 .0166 +D38 71 70 DIN +V22 71 0 0.2 +V23 72 0 0 +R29 72 0 .0166 +D39 73 72 DIN +V27 73 0 0.2 +* +*** SUPPLY CURRENT AND BIASING *** +ISUP +Vs -Vs 800E-6 +GSUP +Vs -Vs +Vs -Vs 1e-6 +FSUP1 56 0 VOSO -1 +D20 +Vs 90 D +D23 52 -Vs D +D24 56 90 DZ +D25 52 56 DZ +FSUP2 57 0 VCS1 1 +D26 +Vs 91 D +D27 53 -Vs D +D28 57 91 DZ +D29 53 57 DZ +FSUP3 58 0 VCS2 1 +D30 +Vs 92 D +D31 54 -Vs D +D32 58 92 DZ +D33 54 58 DZ +FSUP4 59 0 VCS3 1 +D34 +Vs 93 D +D35 55 -Vs D +D36 59 93 DZ +D37 55 59 DZ +E10 VPOSx 0 +Vs 0 1 +E11 VNEGx 0 -Vs 0 1 +* +* +.MODEL NPN NPN +.MODEL D D(IS=1e-15 N=0.1) +.MODEL DN D(IS=1e-15 KF=3e-6) +.MODEL DIN D(IS=1e-15 KF=5e1 AF=1.5) +.MODEL DZ D(IS=1e-15 BV=50 RS=1) +.MODEL DSLEWP D(IS=1e-15 BV=19.5 RS=0.1) +.MODEL DSLEWN D(IS=1e-15 BV=19.5 RS=0.1) +* +.ENDS AD8222 +*$ +* AD8224 SPICE Macro-model 09/09, Rev. C +* PRB IAP ADI +* +* Revision History: +* +* Node assignments +* inverting input +* | RG +* | | RG +* | | | non_inverting input +* | | | | negative supply +* | | | | | ref +* | | | | | | output +* | | | | | | | positive supply +* | | | | | | | | +.SUBCKT AD8224 IN- RG- RG+ IN+ -Vs REF VOUT +Vs +** INPUT STAGE +R1 N009 N008 20E3 +R2 N008 Inverting_Out 20E3 +R3 N013 noninverting_out 20.002e3 +R4 REF N013 20e3 +R5 RG- N003 24700 +R6 RG+ N012 24724 +D3 N003 P001 D +D4 P002 N003 D +V3 P002 VNEGx 0.84 +V4 VPOSx P001 2.35 +D5 N012 P003 D +D6 P004 N012 D +V5 P004 VNEGx 0.84 +V6 VPOSx P003 2.35 +D7 N005 P005 D +D8 P006 N005 D +V7 P006 VNEGx -10 +V8 VPOSx P005 -10 +D9 N019 P007 D +D10 P008 N019 D +V9 P008 VNEGx -10 +V10 VPOSx P007 -10 +D11 N009 P009 D +D12 P010 N009 D +V11 P010 N016 1.03 +V12 N010 P009 1 +D13 REF P011 D +D14 P012 REF D +V13 P012 VNEGx .3 +V14 VPOSx P011 .3 +D15 N013 P013 D +D16 P014 N013 D +V15 P014 VNEGx 0.6 +V16 VPOSx P013 0.6 +E4 Inverting_Out 0 N003 0 1 +E5 noninverting_out 0 N012 0 1 +Q1 Inv_Fdbk N002 RG- 0 PNP +Q2 Pos_Fdbk N015 RG+ 0 PNP +V1 VBIAS -Vs -10 +I1 Pos_Fdbk VBIAS 9E-6 +I2 Inv_Fdbk VBIAS 9E-6 + +C1 N003 Inv_Fdbk 3.8035e-12 +C2 N012 Pos_Fdbk 3.8e-12 +E8 N002 0 N005 0 1 +E9 N015 0 N019 0 1 +VOSI_Neg N004 IN- 25E-6 +VOSI_Pos IN+ N017 24E-6 +VOSO VOUT N011 300E-6 +C3 RG- 0 .200e-12 +C4 RG+ 0 .135e-12 +I23 IN- 0 3E-12 +I24 IN+ 0 3.2E-12 +G1 0 IN+ N020 N021 .7e-9 +R13 IN+ N020 10e9 +R14 N020 IN- 10e9 +R15 +Vs N021 10e9 +R16 N021 -Vs 10e9 +G2 0 IN- N020 N021 .7e-9 +E10 VPOSx 0 +Vs 0 1 +I3 +Vs -Vs 725E-6 +G3 +Vs -Vs +Vs -Vs 1e-6 +E11 VNEGx 0 -Vs 0 1 + +R17 VBIAS Inv_Fdbk 10e9 +R18 Pos_Fdbk VBIAS 10e9 +H3 N006 N004 V24 14 +V24 N001 0 0 +R19 N001 0 .0166 +H4 N011 N009 V25 100 +V25 N007 0 0 +R20 N007 0 .0166 +H5 N018 N017 V26 14 +V26 N014 0 0 +R21 N014 0 .0166 +G4 0 N005 N006 N005 1E-3 +G5 0 N019 N018 N019 1E-3 +G6 0 N003 VBIAS Inv_Fdbk 1 +G7 0 N012 VBIAS Pos_Fdbk 1 +G8 0 N009 N013 N008 1 +R10 N005 0 10e9 +R7 N003 0 10E9 +R11 N019 0 10E9 +R8 N012 0 10E9 +R9 N009 0 10E9 +*C5 N008 N009 8e-12 + + +H1 VPOSx N010 POLY(1) VOSO 0 0 8000 +H2 N016 VNEGx POLY(1) VOSO 0 0 8000 + +* MODELS USED +* +.model D D +.model PNP PNP (BF=10E5 VAF=20000) +.ENDS AD8224 + +* AD8226 SPICE Macro-model +* Copyright 2012 by Analog Devices. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node assignments +* inverting input +* | RG +* | | RG +* | | | non_inverting input +* | | | | negative supply +* | | | | | ref +* | | | | | | output +* | | | | | | | positive supply +* | | | | | | | | +.SUBCKT AD8226 IN- RG- RG+ IN+ -Vs REF VOUT +Vs +** INPUT STAGE +R1 N009 N008 50E3 +R2 N008 Inverting_Out 50E3 +R3 N013 noninverting_out 50000 +R4 REF N013 50k +R5 RG- N003 24700 +R6 RG+ N012 24724 +D3 N003 P001 D +D4 P002 N003 D +V3 P002 VNEGx 0.84 +V4 VPOSx P001 .61 +D5 N012 P003 D +D6 P004 N012 D +V5 P004 VNEGx 0.84 +V6 VPOSx P003 .61 +D7 N005 P005 D +D8 P006 N005 D +V7 P006 VNEGx 0 +V8 VPOSx P005 0 +D9 N019 P007 D +D10 P008 N019 D +V9 P008 VNEGx 0 +V10 VPOSx P007 0 +D11 N009 P009 D +D12 P010 N009 D +V11 P010 N016 0.750 +V12 N010 P009 0.83 +D13 REF P011 D +D14 P012 REF D +V13 P012 VNEGx .3 +V14 VPOSx P011 .3 +D15 N013 P013 D +D16 P014 N013 D +V15 P014 VNEGx 0.6 +V16 VPOSx P013 0.6 +E4 Inverting_Out 0 N003 0 1 +E5 noninverting_out 0 N012 0 1 +Q1 Inv_Fdbk N002 RG- 0 PNP +Q2 Pos_Fdbk N015 RG+ 0 PNP +V1 VBIAS -Vs -10 +I1 Pos_Fdbk VBIAS 2E-6 +I2 Inv_Fdbk VBIAS 2E-6 + +C1 N003 Inv_Fdbk 4.035e-12 +C2 N012 Pos_Fdbk 4.0e-12 +E8 N002 0 N005 0 1 +E9 N015 0 N019 0 1 +VOSI_Neg N004 IN- 25E-6 +VOSI_Pos IN+ N017 24E-6 +VOSO VOUT N011 300E-6 +C3 RG- 0 .242e-12 +C4 RG+ 0 .1635e-12 +I23 IN- 0 -22.3E-9 +I24 IN+ 0 -22E-9 +G1 0 IN+ N020 N021 .7e-9 +R13 IN+ N020 10e9 +R14 N020 IN- 10e9 +R15 +Vs N021 10e9 +R16 N021 -Vs 10e9 +G2 0 IN- N020 N021 .7e-9 +E10 VPOSx 0 +Vs 0 1 +I3 +Vs -Vs 300E-6 +G3 +Vs -Vs +Vs -Vs 1e-6 +E11 VNEGx 0 -Vs 0 1 + +R17 VBIAS Inv_Fdbk 10e9 +R18 Pos_Fdbk VBIAS 10e9 +H3 N006 N004 V24 14 +V24 N001 0 0 +R19 N001 0 .0166 +H4 N011 N009 V25 100 +V25 N007 0 0 +R20 N007 0 .0166 +H5 N018 N017 V26 14 +V26 N014 0 0 +R21 N014 0 .0166 +G4 0 N005 N006 N005 1E-3 +G5 0 N019 N018 N019 1E-3 +G6 0 N003 VBIAS Inv_Fdbk 1 +G7 0 N012 VBIAS Pos_Fdbk 1 +G8 0 N009 N013 N008 1 +R10 N005 0 10e9 +R7 N003 0 10E9 +R11 N019 0 10E9 +R8 N012 0 10E9 +R9 N009 0 10E9 + + +H1 VPOSx N010 POLY(1) VOSO 0 0 8000 +H2 N016 VNEGx POLY(1) VOSO 0 0 8000 + +* MODELS USED +* +.model D D +.model PNP PNP (BF=10E5 VAF=20000) +.ENDS AD8226 + +* AD8227 SPICE Macro-model +* Revision History: +* 1.0 (09/2010) - PRB (Original Model) +* 1.1 (08/2012) - PRB (Updated to new header style) +* 2.0 (12/2014) - SH (Bug fixes and major performance improvements. Added slew rate, current noise and 1/f noise. +* Load currents reflected in supply. Organized and commented netlist.) +* Copyright 2010, 2014 by Analog Devices. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* Temperature effects +* PSRR +* +* Parameters Modeled Include: +* Gain error, Vos, Ibias +* Bandwidth +* Voltage and current noise with 1/f noise +* CMRR vs frequency +* Supply current incl preamp and output load currents +* Output clamp vs load +* Input range and internal voltage limitations +* Slew Rate +* Pulse response vs cap load +* Input impedance +* +* Typical Specifications from ±15V Table Used in Model +* +* END Notes +* +* Node Assignments +* inverting input +* | RG +* | | RG +* | | | non_inverting input +* | | | | negative supply +* | | | | | ref +* | | | | | | output +* | | | | | | | positive supply +* | | | | | | | | +.SUBCKT AD8227 IN- RG- RG+ IN+ -Vs REF VOUT +Vs +*** INPUT STAGE *** +FIBIAS1 IN- 0 POLY(1) V21 -19.5E-9 1.0E-4 +H3 4 IN- V24 21.265 +G4 0 5 4 0 257.8E-6 +R10 5 0 3878.788 +D7 5 9 D +D8 10 5 D +V7 10 VNEGx -0.06 +V8 VPOSx 9 0.84 +E8 22 0 5 0 1 +FIBIAS2 IN+ 0 POLY(1) V23 -20.5E-9 1.0E-4 +VOSI 7 IN+ -100.0E-6 +G5 0 8 7 0 257.8E-6 +R11 8 0 3878.788 +D9 8 9 D +D10 10 8 D +E9 15 0 8 0 1 +G1 IN+ 0 POLY(2) (IN+, VMID) (IN+, IN-) 0 1.25E-9 1.25E-9 +G2 IN- 0 POLY(2) (IN-, VMID) (IN-, IN+) 0 1.25E-9 1.25E-9 +CCM1 IN+ 0 1.0E-12 +CCM2 IN- 0 1.0E-12 +CDIFF IN+ IN- 1.5E-12 +* +*** PREAMPLIFIER STAGE *** +GP1 16 Pos_Fdbk 16 15 115.0E-6 +VSH1 RG+ 16 0.553 +C4 RG+ 0 31.84E-12 +R6 RG+ 17 8010.4 +VCS2 noninverting_out 17 0 +I1 Pos_Fdbk VBIAS 10.0E-6 +R23 Pos_Fdbk VBIAS 1E9 +G7 0 18 VBIAS Pos_Fdbk 1 +R8 18 0 10E9 +C2 noninverting_out Pos_Fdbk 18.17E-12 +R25 19 18 100 +D5 19 20 D +D6 21 19 D +V5 21 VNEGx 0.35 +V6 VPOSx 20 0.15 +GP2 23 Inv_Fdbk 23 22 115.0E-6 +VSH2 RG- 23 0.553 +C3 RG- 0 31.74E-12 +R5 RG- 24 8010.4 +VCS1 Inverting_Out 24 0 +I2 Inv_Fdbk VBIAS 10.0E-6 +R18 VBIAS Inv_Fdbk 1E9 +G6 0 25 VBIAS Inv_Fdbk 1 +R7 25 0 10E9 +C1 Inverting_Out Inv_Fdbk 18.26E-12 +R24 26 25 100 +D3 26 20 D +D4 21 26 D +V1 -Vs VBIAS 20 +D40 Inv_Fdbk VBIAS D +D41 Pos_Fdbk VBIAS D +D42 VBIAS Inv_Fdbk D +D43 VBIAS Pos_Fdbk D +* +*** SUBTRACTOR STAGE *** +E4 Inverting_Out 0 26 0 1 +E5 noninverting_out 0 19 0 1 +R1 31 sub_neg 50000.0 +R2 sub_neg 24 9998.05 +R3 sub_pos 17 9997.45 +R4 REF sub_pos 50000.0 +VCS3 sub_out 31 0 +G8 0 sub_out sub_pos sub_neg 1E3 +R9 sub_out 0 10E6 +D13 REF 38 D +D14 39 REF D +V13 39 VNEGx 0.3 +V14 VPOSx 38 0.3 +D15 sub_pos 36 D +D16 37 sub_pos D +V15 37 VNEGx 0.05 +V16 VPOSx 36 0.95 +R22 sub_out_cl sub_out 100 +D1 sub_out_cl 45 D +D2 46 sub_out_cl D +H4 VX sub_out_cl V25 294.46 +* +*** SLEW RATE AND OUTPUT STAGE *** +G11 0 VZ VX VY 1e-3 +R26 VZ 0 100E6 +D21 40 VZ DSLEWP +D22 40 0 DSLEWN +G12 0 VY VZ 0 40.0E-6 +C7 VY 0 1E-9 +R30 VY 0 10e9 +G9 0 41 VY 42 1 +R12 41 0 1e10 +C5 41 0 851.7E-9 +G10 0 42 41 0 1.0E-3 +R17 42 0 1000.0 +C6 42 0 340.7E-12 +R27 43 42 0.1 +D11 43 45 D +D12 46 43 D +H1 VPOSx 45 POLY(1) VSRC 0.15 0 14793 +H2 46 VNEGx POLY(1) VSNK 0.15 0 14793 +VOSO VOUT 43 464.0E-6 +* +*** NOISE *** +V24 60 0 0 +R19 60 0 .0166 +D17 61 60 DN +V18 61 0 0.2 +V25 64 0 0 +R20 64 0 .0166 +D19 65 64 DN +V20 65 0 0.202 +V21 70 0 0 +R28 70 0 .0166 +D38 71 70 DIN +V22 71 0 0.2 +V23 72 0 0 +R29 72 0 .0166 +D39 73 72 DIN +V27 73 0 0.2 +* +*** SUPPLY CURRENT AND BIASING *** +GSUP +Vs -Vs POLY(1) (+Vs,-Vs) 290.5E-6 916.0E-9 +FSUP1 56 0 VOSO -1 +D24 90 +Vs DZ +D25 -Vs 52 DZ +D20 90 95 D +VSRC 95 56 0 +D23 55 52 D +VSNK 56 55 0 +FSUP2 57 0 VCS1 1 +D26 90 57 D +D27 57 52 D +FSUP3 58 0 VCS2 1 +D30 90 58 D +D31 58 52 D +FSUP4 59 0 VCS3 1 +D34 90 59 D +D35 59 52 D +E10 VPOSx 0 +Vs 0 1 +E11 VNEGx 0 -Vs 0 1 +EMID VMID 0 POLY(2) (+Vs, 0) (-Vs, 0) 0 0.5 0.5 +* +* +.MODEL D D(IS=1e-15 N=0.1 RS=1e-3) +.MODEL DN D(IS=1e-15 KF=2.946E-7) +.MODEL DIN D(IS=1e-15 KF=2.592E-6) +.MODEL DZ D(IS=1e-15 BV=50 RS=1) +.MODEL DSLEWP D(IS=1e-15 BV=19.5 RS=0.1) +.MODEL DSLEWN D(IS=1e-15 BV=19.5 RS=0.1) +* +* +.ENDS AD8227 +* +* AD8418A MACROMODEL +* Copyright 2013 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* Temperature +* PSRR +* Parameters modeled include: +* Offset Voltage +* Bias Current vs. Common Mode Voltage +* DC Transfer Characteristic +* DC CMRR +* Gain vs. Frequency +* CMRR vs. Frequency +* Spectral Noise +* Slew Rate +* Pulse Response +* Capacitive Loading Effects +* Common-Mode Step Response +* END Notes +* +************************ +.SUBCKT AD8418A VIN- GND REF2 VOUT VS REF1 VIN+ +*#ASSOC Category="Current Sense Amplifiers" Symbol=ADICurSense7p Mapping=1,2,5,7,6,3,4 + +D24 36 37 DIODE +V14 0 38 dc 2.35 +D26 38 2 DIODE +D25 2 VIN- DIODE +V12 0 36 dc 2.35 +D23 37 VIN+ DIODE +R9 35 REF2x 100000 +R8 35 REF1x 100000 +RRef2 5 REF2 100000 +RRef1 5 REF1 100000 +I6 4 0 dc 8e-005 +V9 34 0 dc 1.5 +D22 34 4 DIODE +D21 VIN+ 4 DIODE +R6 VIN+ 35 720000 +R5 VIN- 0 1575000 +Lcm 18 33 0.0027 +D19 29 6 DIODE +D13 28 29 DIODE +D18 25 20 DIODE +D17 20 27 DIODE +D16 27 26 DIODE +D15 26 12 DIODE +D14 12 28 DIODE +D12 8 25 DIODE +D6 9 8 DIODE +D5 10 9 DIODE +D4 11 10 DIODE +D3 6 11 DIODE +R14 0 20 1 +GI11 0 20 VIN+ 0 1 +V13 V85 22 dc 1.5 +D10 20 22 DIODE +V7 21 VNEG4 dc 1.5 +D9 21 20 DIODE +R13 0 6 1 +GI10 0 6 VIN- 0 1 +V4 19 VNEG4 dc 1.5 +D8 19 6 DIODE +V2 V85 17 dc 1.5 +D7 6 17 DIODE +EV8 Vsl+in 0 20 0 1 +EV6 7 0 6 0 1 +Vos 3 7 dc 0.0002 +R7 Vo1 0 1000000000 +R4 1 5 1450000 +R3 Vsl+out 1 75000 +R2 33 Vo1 1500000 +Rcm 3 18 75007.5 +GI1 0 Vo1 1 33 1 + +* Noise + +V11 15 0 dc 0 +Rn 16 15 0.00166 +Vn 16 0 dc 0 +Hn 32 Vo1 Vn 620 + +V10 0 30 dc 100 +D20 30 14 DIODE +V19 0 24 dc -100 +D11 14 24 DIODE +V5 VS 13 dc 0.85 +D1 VOUT 13 DIODE +V1 23 GND dc 0.85 +D2 23 VOUT DIODE + +* Gain stage + +Rg2 VOUT 0 454.5 +Cg2 VOUT 0 1.4e-009 +GIg2 0 VOUT 14 0 0.0022 +Cg1 0 14 6.37e-007 +Rg1 0 14 1000000 +GIg1 0 14 31 VOUT 1 + +* Slew Rate + +GIsl 0 31 VALUE={LIMIT(1*V(32,31),0.1,-0.1)} +Rsl 31 0 1000000000 +Csl 31 0 1e-007 + +* Supplies + +EV20 REF2x 0 REF2 0 1 +EV18 REF1x 0 REF1 0 1 +V16 0 VNEG4 dc 4 +V15 V85 0 dc 85 +I4 VS GND dc 0.002 + +* Common-Mode Step Response + +R1 Vsl+out 0 1000000000 +C1 Vsl+out 0 1e-009 +GI2 0 Vsl+out VALUE={LIMIT(1*V(Vsl+in,Vsl+out),15,-15)} + +.model DIODE D(Is=1E-14) + +.ENDS AD8418A + +* AD8421 SPICE Macro-model +* Revision History: +* 0(09/2012) - MI Initial Rev +* A(04/2013) - SH (Updated to new header style. Modified diamond plot and bandwidth parameters) +* Copyright 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* +* BEGIN Notes: +* +* Not Modeled: +* Temperature effects +* PSRR +* +* Parameters modeled include: +* Output swing vs Common-mode Voltage +* Supply current vs power supplies +* DC errors, Vos, Ibias +* Noise +* Bandwidth +* Slew rate +* CMRR vs frequency +* Small signal pulse response +* +* Supply range: +* Single Supply: 5V to 36V +* Dual Supplies: +/-2.5V to +/-18V +* +* END Notes +* +* Node assignments +* inverting input +* | RG +* | | RG +* | | | non_inverting input +* | | | | negative supply +* | | | | | ref +* | | | | | | output +* | | | | | | | positive supply +* | | | | | | | | +.SUBCKT AD8421 IN- RG- RG+ IN+ -Vs REF VOUT +Vs +R1 sub_out sub_neg 10e3 +R2 sub_neg Inverting_Out 10e3 +R3 sub_pos Non-inverting_Out 10001.8 +R4 REF sub_pos 10e3 +R5 RG- N004 4.96e3 +R6 RG+ N016 4.95e3 +D3 N005 P001 D +D4 P002 N005 D +V3 P002 VNEGx 2 +V4 VPOSx P001 4.4 +D5 N023 P003 D +D6 P004 N023 D +V5 P004 VNEGx 2 +V6 VPOSx P003 4.4 +D7 N008 P005 D +D8 P006 N008 D +V7 P006 VNEGx 2.9 +V8 VPOSx P005 2.4 +D9 N027 P007 D +D10 P008 N027 D +V9 P008 VNEGx 2.9 +V10 VPOSx P007 2.4 +D11 N015 P009 D +D12 P010 N015 D +V11 P010 N028 1.8 +V12 N013 P009 2.2 +D13 REF P011 D +D14 P012 REF D +V13 P012 VNEGx .3 +V14 VPOSx P011 .3 +D15 sub_pos P013 D +D16 P014 sub_pos D +V15 P014 VNEGx 1.8 +V16 VPOSx P013 1.8 +E4 Inverting_Out 0 N005 0 1 +E5 Non-inverting_Out 0 N023 0 1 +V1 VBIAS1 +Vs 5 +I1 VBIAS2 Pos_Fdbk 200e-6 +I2 VBIAS1 Inv_Fdbk 200e-6 +C1 N011 Inv_Fdbk 4.25e-12 +C2 N022 Pos_Fdbk 4.3e-12 +E8 N003 0 N008 0 1 +E9 N021 0 N027 0 1 +VOSI_Neg N006 IN- 0 +VOSI_Pos N024 IN+ 60e-6 +VOSO VOUT N015 -1.65e-3 +C3 RG- 0 4.3e-12 +C4 RG+ 0 4.15e-12 +I23 IN- 0 -1.5e-9 +I24 IN+ 0 0.5e-9 +G1 0 IN+ N029 N030 -0.033e-9 +R13 IN+ N029 15e9 +R14 N029 IN- 15e9 +R15 +Vs N030 10e9 +R16 N030 -Vs 10e9 +G2 0 IN- N029 N030 -0.033e-9 +E10 VPOSx 0 +Vs 0 1 +I3 +Vs -Vs 2.1e-3 +G3 +Vs -Vs +Vs -Vs 5e-6 +E11 VNEGx 0 -Vs 0 1 +H1 VPOSx N013 POLY(1) VOSO 0 -29.4 588.5 -6078 +H2 N028 VNEGx POLY(1) VOSO 0 50 -1882 31700 +H3 N009 N006 V24 1.95 +V24 N001 0 0 +R19 N001 0 .0166 +H4 VX N014 V25 47.34 +V25 N010 0 0 +R20 N010 0 .0166 +H5 N025 N024 V26 1.95 +V26 N017 0 0 +R21 N017 0 .0166 +G4 0 N007 N009 N007 1 +G5 0 N026 N025 N026 1 +G6 0 N004 VBIAS1 Inv_Fdbk 1 +G7 0 N016 VBIAS2 Pos_Fdbk 1 +G8 0 sub_out sub_pos sub_neg 1 +R10 N007 0 10e9 +R7 N004 0 10e9 +R11 N026 0 10E9 +R8 N016 0 10e9 +R9 sub_out 0 10E9 +Q1 Pos_Fdbk N021 RG+ 0 NPN +Q2 Inv_Fdbk N003 RG- 0 NPN +G9 0 N018 VY N019 1 +G10 0 N019 N018 0 8.32e-3 +R12 N018 0 1e9 +R17 N019 0 120.13 +C5 N018 0 10E-9 +C6 N019 0 300e-12 +C8 VY 0 1e-9 +G11 0 VY VALUE = { LIMIT( 1*V(VX,VY), .035, -.035) } +R22 VY 0 1e9 +R18 VBIAS1 Inv_Fdbk 1e9 +R23 Pos_Fdbk VBIAS2 1e9 +D1 N014 P015 D +V2 VPOSx P015 2.2 +D2 P016 N014 D +V17 P016 VNEGx 1.8 +I4 +Vs 0 -435e-6 +R26 N016 N022 1.5k +R27 N004 N011 1.5k +V18 N031 -Vs 5 +E1 VBIAS2 N031 +Vs -Vs 1 +R25 N007 N008 1 +R28 N026 N027 1 +R29 N016 N023 1 +R30 N004 N005 1 +R31 sub_out N014 1 +R32 N019 N015 0.1 +V19 N020 0 0.1 +D17 N020 N017 DNoise +V20 N002 0 0.1 +D18 N002 N001 DNoise +V21 N012 0 0.12 +D19 N012 N010 DNoise + + +* MODELS USED +* +.model D D +.model DNoise D (Is=1e-11, kf=8e-9) +.model NPN NPN +.ENDS AD8421 + +* AD8422 SPICE Macro-model +* Copyright 2015 by Analog Devices. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* Temperature effects +* PSRR +* +* Parameters Modeled Include: +* Gain error, Vos, Ibias +* Bandwidth +* Voltage and current noise with 1/f noise +* CMRR vs frequency +* Supply current incl preamp and output load currents +* Output clamp vs load +* Input range and internal voltage limitations +* Slew Rate +* Pulse response vs cap load +* Input impedance +* +* Typical Specifications from ±15V Table Used in Model +* +* END Notes +* +* Node Assignments +* inverting input +* | RG +* | | RG +* | | | non_inverting input +* | | | | negative supply +* | | | | | ref +* | | | | | | output +* | | | | | | | positive supply +* | | | | | | | | +.SUBCKT AD8422 IN- RG- RG+ IN+ -Vs REF VOUT +Vs +*** INPUT STAGE *** +FIBIAS1 IN- 0 POLY(1) V21 600.0E-12 9.0E-5 +H3 4 IN- V24 6.645 +G4 0 5 4 0 2.64E-3 +R10 5 0 378.788 +D7 5 9 D +D8 10 5 D +V7 10 VNEGx 1.24 +V8 VPOSx 9 1.24 +E8 22 0 5 0 1 +FIBIAS2 IN+ 0 POLY(1) V23 400.0E-12 9.0E-5 +VOSI 7 IN+ -25.0E-6 +G5 0 8 7 0 2.64E-3 +R11 8 0 378.788 +D9 8 9 D +D10 10 8 D +E9 15 0 8 0 1 +G1 IN+ 0 POLY(2) (IN+, VMID) (IN+, IN-) 0 2.5E-12 5.0E-12 +G2 IN- 0 POLY(2) (IN-, VMID) (IN-, IN+) 0 2.5E-12 5.0E-12 +CCM1 IN+ 0 1.0E-12 +CCM2 IN- 0 1.0E-12 +CDIFF IN+ IN- 1.5E-12 +* +*** PREAMPLIFIER STAGE *** +GN1 Pos_Fdbk 16 15 16 778.8E-6 +VSH1 RG+ 16 -0.474 +C4 RG+ 0 3.688E-12 +R6 RG+ 17 9802.94 +VCS2 noninverting_out 17 0 +I1 VBIAS Pos_Fdbk 20.0E-6 +R23 Pos_Fdbk VBIAS 1E9 +G7 0 18 VBIAS Pos_Fdbk 1 +R8 18 0 10E9 +C2 noninverting_out Pos_Fdbk 10.19E-12 +R25 19 18 100 +D5 19 20 D +D6 21 19 D +V5 21 VNEGx 0.19 +V6 VPOSx 20 0.19 +GN2 Inv_Fdbk 23 22 23 778.8E-6 +VSH2 RG- 23 -0.474 +C3 RG- 0 3.692E-12 +R5 RG- 24 9802.94 +VCS1 Inverting_Out 24 0 +I2 VBIAS Inv_Fdbk 20.0E-6 +R18 VBIAS Inv_Fdbk 1E9 +G6 0 25 VBIAS Inv_Fdbk 1 +R7 25 0 10E9 +C1 Inverting_Out Inv_Fdbk 10.31E-12 +R24 26 25 100 +D3 26 20 D +D4 21 26 D +V1 VBIAS +Vs 20 +D40 Inv_Fdbk VBIAS D +D41 Pos_Fdbk VBIAS D +D42 VBIAS Inv_Fdbk D +D43 VBIAS Pos_Fdbk D +* +*** SUBTRACTOR STAGE *** +E4 Inverting_Out 0 26 0 1 +E5 noninverting_out 0 19 0 1 +R1 31 sub_neg 10000.0 +R2 sub_neg 24 9999.05 +R3 sub_pos 17 9998.85 +R4 REF sub_pos 10000.0 +VCS3 sub_out 31 0 +G8 0 sub_out sub_pos sub_neg 1E3 +R9 sub_out 0 10E6 +D13 REF 38 D +D14 39 REF D +V13 39 VNEGx 0.3 +V14 VPOSx 38 0.3 +D15 sub_pos 36 D +D16 37 sub_pos D +V15 37 VNEGx 0.05 +V16 VPOSx 36 1.05 +R22 sub_out_cl sub_out 100 +D1 sub_out_cl 45 D +D2 46 sub_out_cl D +H4 VX sub_out_cl V25 71.74 +* +*** SLEW RATE AND OUTPUT STAGE *** +G11 0 VZ VX VY 1e-3 +R26 VZ 0 100E6 +D21 40 VZ DSLEWP +D22 40 0 DSLEWN +G12 0 VY VZ 0 40.0E-6 +C7 VY 0 1E-9 +R30 VY 0 10e9 +G9 0 41 VY 42 1 +R12 41 0 1e10 +C5 41 0 56.15E-9 +G10 0 42 41 0 1.0E-3 +R17 42 0 1000.0 +C6 42 0 87.03E-12 +R27 43 42 0.1 +D11 43 45 D +D12 46 43 D +H1 VPOSx 45 POLY(1) VSRC 0.15 0 3E3 +H2 46 VNEGx POLY(1) VSNK 0.15 0 3E3 +VOSO VOUT 43 157.0E-6 +* +*** NOISE *** +V24 60 0 0 +R19 60 0 .0166 +D17 61 60 DN +V18 61 0 0.2 +V25 64 0 0 +R20 64 0 .0166 +D19 65 64 DN +V20 65 0 0.209 +V21 70 0 0 +R28 70 0 .0166 +D38 71 70 DIN +V22 71 0 0.2 +V23 72 0 0 +R29 72 0 .0166 +D39 73 72 DIN +V27 73 0 0.2 +* +*** SUPPLY CURRENT AND BIASING *** +GSUP +Vs -Vs POLY(1) (+Vs,-Vs) 195.2E-6 1.0E-6 +FSUP1 56 0 VOSO -1 +D24 90 +Vs DZ +D25 -Vs 52 DZ +D20 90 95 D +VSRC 95 56 0 +D23 55 52 D +VSNK 56 55 0 +FSUP2 57 0 VCS1 1 +D26 90 57 D +D27 57 52 D +FSUP3 58 0 VCS2 1 +D30 90 58 D +D31 58 52 D +FSUP4 59 0 VCS3 1 +D34 90 59 D +D35 59 52 D +E10 VPOSx 0 +Vs 0 1 +E11 VNEGx 0 -Vs 0 1 +EMID VMID 0 POLY(2) (+Vs, 0) (-Vs, 0) 0 0.5 0.5 +* +* +.MODEL D D(IS=1e-15 N=0.1 RS=1e-3) +.MODEL DN D(IS=1e-15 KF=3.142E-7) +.MODEL DIN D(IS=1e-15 KF=6.221E-6) +.MODEL DZ D(IS=1e-15 BV=50 RS=1) +.MODEL DSLEWP D(IS=1e-15 BV=19.5 RS=0.1) +.MODEL DSLEWN D(IS=1e-15 BV=19.5 RS=0.1) +* +* +.ENDS AD8422 +*$ +* AD8429 SPICE Macro-model +* Generic Desc: 36V 1nV/rtHz Low Noise, Low Distortion, High Speed In-Amp +* Developed by: ADI - LPG +* +* Revision History: +* 4.0 (10/2012) - PRB (Updated to new header style) +* 5.0 (9/2014) - SH (Performance improvements, bug fixes, organized netlist) +* Copyright 2012, 2014 by Analog Devices. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* Temperature effects +* PSRR +* +* Parameters Modeled Include: +* Gain error, Vos, Ibias +* Bandwidth +* Voltage and current noise with 1/f noise +* CMRR vs frequency +* Supply current incl preamp and output load currents +* Output clamp vs load +* Input range and internal voltage limitations +* Slew Rate +* Pulse response vs cap load +* Input impedance +* +* Typical Specifications from ±15V Table Used in Model +* +* END Notes +* +* Node Assignments +* inverting input +* | RG +* | | RG +* | | | non_inverting input +* | | | | negative supply +* | | | | | ref +* | | | | | | output +* | | | | | | | positive supply +* | | | | | | | | +.SUBCKT AD8429 IN- RG- RG+ IN+ -Vs REF VOUT +Vs +*** INPUT STAGE *** +FIBIAS1 IN- 0 POLY(1) V21 165.0E-9 1.5E-3 +H3 4 IN- V24 0.886 +G4 0 5 4 0 148.5E-3 +R10 5 0 6.734 +D7 5 9 D +D8 10 5 D +V7 10 VNEGx 2.85 +V8 VPOSx 9 2.55 +E8 22 0 5 0 1 +FIBIAS2 IN+ 0 POLY(1) V23 135.0E-9 1.5E-3 +VOSI 7 IN+ -50.0E-6 +G5 0 8 7 0 148.5E-3 +R11 8 0 6.734 +D9 8 11 D +D10 12 8 D +V9 12 VNEGx 2.85 +V10 VPOSx 11 2.55 +E9 15 0 8 0 1 +G1 IN+ 0 13 14 666.7E-12 +G2 IN- 0 13 14 666.7E-12 +R13 IN+ 13 1.5E9 +R14 13 IN- 1.5E9 +R15 +Vs 14 10E9 +R16 14 -Vs 10E9 +CCM1 IN+ 0 3.0E-12 +CCM2 IN- 0 3.0E-12 +* +*** PREAMPLIFIER STAGE *** +GN1 Pos_Fdbk 16 15 16 11.78E-3 +VSH1 RG+ 16 -0.744 +IBOT1 RG+ -Vs 660.0E-6 +C4 RG+ 0 7.65E-12 +R6 RG+ 17 3003.9 +VCS2 noninverting_out 17 0 +I1 VBIAS Pos_Fdbk 660.0E-6 +R23 Pos_Fdbk VBIAS 1E9 +G7 0 18 VBIAS Pos_Fdbk 1 +R8 18 0 10E9 +C2 noninverting_out Pos_Fdbk 7.544E-12 +R25 19 18 100 +D5 19 20 D +D6 21 19 D +V5 21 VNEGx 2.4 +V6 VPOSx 20 2.45 +GN2 Inv_Fdbk 23 22 23 11.78E-3 +VSH2 RG- 23 -0.744 +IBOT2 RG- -Vs 660.0E-6 +C3 RG- 0 16.37E-12 +R5 RG- 24 3003.9 +VCS1 Inverting_Out 24 0 +I2 VBIAS Inv_Fdbk 660.0E-6 +R18 VBIAS Inv_Fdbk 1E9 +G6 0 25 VBIAS Inv_Fdbk 1 +R7 25 0 10E9 +C1 Inverting_Out Inv_Fdbk 16.6E-12 +R24 26 25 100 +D3 26 27 D +D4 28 26 D +V3 28 VNEGx 2.4 +V4 VPOSx 27 2.45 +V1 VBIAS +Vs 20 +D40 Inv_Fdbk VBIAS D +D41 Pos_Fdbk VBIAS D +D42 VBIAS Inv_Fdbk D +D43 VBIAS Pos_Fdbk D +* +*** SUBTRACTOR STAGE *** +E4 Inverting_Out 0 26 0 1 +E5 noninverting_out 0 19 0 1 +R1 31 sub_neg 5000.0 +R2 sub_neg 24 4999.079 +R3 sub_pos 17 4998.763 +R4 REF sub_pos 5000.0 +VCS3 sub_out 31 0 +G8 0 sub_out sub_pos sub_neg 1E3 +R9 sub_out 0 10E6 +D13 REF 38 D +D14 39 REF D +V13 39 VNEGx 0.3 +V14 VPOSx 38 0.3 +D15 sub_pos 36 D +D16 37 sub_pos D +V15 37 VNEGx 2.05 +V16 VPOSx 36 0.25 +R22 sub_out_cl sub_out 100 +D1 sub_out_cl 33 D +V2 32 33 1.15 +D2 34 sub_out_cl D +V17 34 35 1.75 +H6 VPOSx 32 POLY(1) VOSO 0 0 2041 +H7 35 VNEGx POLY(1) VOSO 0 0 2041 +H4 VX sub_out_cl V25 40.13 +* +*** SLEW RATE AND OUTPUT STAGE *** +G11 0 VZ VX VY 1e-3 +R26 VZ 0 100E6 +D21 40 VZ DSLEWP +D22 40 0 DSLEWN +G12 0 VY VZ 0 1.1E-3 +C7 VY 0 1E-9 +R30 VY 0 10e9 +G9 0 41 VY 42 1 +R12 41 0 1e10 +C5 41 0 11.71E-9 +G10 0 42 41 0 1.0E-2 +R17 42 0 100.0 +C6 42 0 152.3E-12 +R27 43 42 0.1 +D11 43 45 D +D12 46 43 D +V11 46 47 1.75 +V12 44 45 1.15 +H1 VPOSx 44 POLY(1) VOSO 0 0 2041 +H2 47 VNEGx POLY(1) VOSO 0 0 2041 +VOSO VOUT 43 525.3E-6 +* +*** NOISE *** +V24 60 0 0 +R19 60 0 .0166 +D17 61 60 DN +V18 61 0 0.2 +V25 64 0 0 +R20 64 0 .0166 +D19 65 64 DN +V20 65 0 0.231 +V21 70 0 0 +R28 70 0 .0166 +D38 71 70 DIN +V22 71 0 0.2 +V23 72 0 0 +R29 72 0 .0166 +D39 73 72 DIN +V27 73 0 0.2 +* +*** SUPPLY CURRENT AND BIASING *** +GSUP +Vs -Vs POLY(1) (+Vs,-Vs) 4.7E-3 20.0E-6 +FSUP1 56 0 VOSO -1 +D24 90 +Vs DZ +D25 -Vs 52 DZ +D20 90 56 D +D23 56 52 D +FSUP2 57 0 VCS1 1 +D26 90 57 D +D27 57 52 D +FSUP3 58 0 VCS2 1 +D30 90 58 D +D31 58 52 D +FSUP4 59 0 VCS3 1 +D34 90 59 D +D35 59 52 D +E10 VPOSx 0 +Vs 0 1 +E11 VNEGx 0 -Vs 0 1 +* +* +.MODEL D D(IS=1e-15 N=0.1) +.MODEL DN D(IS=1e-15 KF=3.142E-6) +.MODEL DIN D(IS=1e-15 KF=4.147E-5) +.MODEL DZ D(IS=1e-15 BV=50 RS=1) +.MODEL DSLEWP D(IS=1e-15 BV=19.5 RS=0.1) +.MODEL DSLEWN D(IS=1e-15 BV=19.5 RS=0.1) +* +* +.ENDS AD8429 +*$ +* AD8505 SPICE Macro-model +* Generic Desc: 1.8/5V, CMOS, OP, ZCO, RRIO, 1X +* Developed by: HH ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (04/2008) +* Copyright 2008, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: VSY=5V, T=25degC +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8505 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=2E-6 W=9.070E-04 +M2 6 2 8 8 PIX L=2E-6 W=9.070E-04 +Cinp 1 50 4.2pF +Cinn 2 50 4.2pF +Cdiff 1 2 3pF +RD1 4 50 5.333E+04 +RD2 6 50 5.333E+04 +C1 4 6 7.650E-12 +I1 99 8 7.500E-06 +V1 9 8 +0.025E-00 +D1 9 99 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 5.00E-04 1 1 1 1 +IOS 1 2 1.50E-12 +* +* CMRR=95dB, POLE AT 3500 Hz +* +E1 72 98 POLY(2) (1,98) (2,98) 0 1.289E-02 1.289E-02 +R10 72 73 4.613E+01 +R20 73 98 3.183E-02 +C10 72 73 1.000E-06 +* +* PSRR=100dB, POLE AT 100 Hz +* +EPSY 21 98 POLY(1) (99,50) -0.181E-00 0.036E-00 +RPS1 21 22 2.274E+04 +RPS2 22 98 1.989E-00 +CPS1 21 22 1.00E-06 +* +* VOLTAGE NOISE REFERENCE OF 37nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 17.500E-3 +HN 81 98 VN1 3.651E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 20000 Hz +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6531 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) +0.580E-06 0.2710E-06 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* GAIN STAGE +* +G1 98 30 (4,6) 4.474E-04 +R1 30 98 1.00E+06 +CF 30 31 1.350E-08 +RZ 455 31 1.2280E-03 +EZ 455 98 (451 98) 1 +V3 32 30 0.279E+00 +V4 30 33 0.362E-00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 451 46 99 99 POX L=1E-6 W=3.940E-04 +M6 451 47 50 50 NOX L=1E-6 W=4.598E-04 +Lout 451 45 10pH +EG1 99 46 POLY(1) (98,30) 3.598E-01 1 +EG2 47 50 POLY(1) (30,98) 3.574E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=3.00E-05,VTO=-0.328,LAMBDA=0.015,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=3.00E-05,VTO=+0.328,LAMBDA=0.015,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=12.400E-11) +.ENDS AD8505 + + +* AD8506 SPICE Macro-model +* Generic Desc: 1.8/5V, CMOS, OP, ZCO, RRIO, 2X +* Developed by: HH ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (04/2008) +* Copyright 2008, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: VSY=5V, T=25degC +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8506 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=2E-6 W=9.070E-04 +M2 6 2 8 8 PIX L=2E-6 W=9.070E-04 +Cinp 1 50 4.2pF +Cinn 2 50 4.2pF +Cdiff 1 2 3pF +RD1 4 50 5.333E+04 +RD2 6 50 5.333E+04 +C1 4 6 7.650E-12 +I1 99 8 7.500E-06 +V1 9 8 +0.025E-00 +D1 9 99 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 5.00E-04 1 1 1 1 +IOS 1 2 1.50E-12 +* +* CMRR=95dB, POLE AT 3500 Hz +* +E1 72 98 POLY(2) (1,98) (2,98) 0 1.289E-02 1.289E-02 +R10 72 73 4.613E+01 +R20 73 98 3.183E-02 +C10 72 73 1.000E-06 +* +* PSRR=100dB, POLE AT 100 Hz +* +EPSY 21 98 POLY(1) (99,50) -0.181E-00 0.036E-00 +RPS1 21 22 2.274E+04 +RPS2 22 98 1.989E-00 +CPS1 21 22 1.00E-06 +* +* VOLTAGE NOISE REFERENCE OF 37nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 17.500E-3 +HN 81 98 VN1 3.651E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 20000 Hz +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6531 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) +0.580E-06 0.2710E-06 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* GAIN STAGE +* +G1 98 30 (4,6) 4.474E-04 +R1 30 98 1.00E+06 +CF 30 31 1.350E-08 +RZ 455 31 1.2280E-03 +EZ 455 98 (451 98) 1 +V3 32 30 0.279E+00 +V4 30 33 0.362E-00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 451 46 99 99 POX L=1E-6 W=3.940E-04 +M6 451 47 50 50 NOX L=1E-6 W=4.598E-04 +Lout 451 45 10pH +EG1 99 46 POLY(1) (98,30) 3.598E-01 1 +EG2 47 50 POLY(1) (30,98) 3.574E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=3.00E-05,VTO=-0.328,LAMBDA=0.015,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=3.00E-05,VTO=+0.328,LAMBDA=0.015,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=12.400E-11) +.ENDS AD8506 +* + + +* AD8508 SPICE Macro-model +* Generic Desc: 1.8/5V, CMOS, OP, ZCO, RRIO, 4X +* Developed by: HH ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (04/2008) +* Copyright 2008, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: VSY=5V, T=25degC +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8508 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=2E-6 W=9.070E-04 +M2 6 2 8 8 PIX L=2E-6 W=9.070E-04 +Cinp 1 50 4.2pF +Cinn 2 50 4.2pF +Cdiff 1 2 3pF +RD1 4 50 5.333E+04 +RD2 6 50 5.333E+04 +C1 4 6 7.650E-12 +I1 99 8 7.500E-06 +V1 9 8 +0.025E-00 +D1 9 99 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 5.00E-04 1 1 1 1 +IOS 1 2 1.50E-12 +* +* CMRR=95dB, POLE AT 3500 Hz +* +E1 72 98 POLY(2) (1,98) (2,98) 0 1.289E-02 1.289E-02 +R10 72 73 4.613E+01 +R20 73 98 3.183E-02 +C10 72 73 1.000E-06 +* +* PSRR=100dB, POLE AT 100 Hz +* +EPSY 21 98 POLY(1) (99,50) -0.181E-00 0.036E-00 +RPS1 21 22 2.274E+04 +RPS2 22 98 1.989E-00 +CPS1 21 22 1.00E-06 +* +* VOLTAGE NOISE REFERENCE OF 37nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 17.500E-3 +HN 81 98 VN1 3.651E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 20000 Hz +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6531 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) +0.580E-06 0.2710E-06 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* GAIN STAGE +* +G1 98 30 (4,6) 4.474E-04 +R1 30 98 1.00E+06 +CF 30 31 1.350E-08 +RZ 455 31 1.2280E-03 +EZ 455 98 (451 98) 1 +V3 32 30 0.279E+00 +V4 30 33 0.362E-00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 451 46 99 99 POX L=1E-6 W=3.940E-04 +M6 451 47 50 50 NOX L=1E-6 W=4.598E-04 +Lout 451 45 10pH +EG1 99 46 POLY(1) (98,30) 3.598E-01 1 +EG2 47 50 POLY(1) (30,98) 3.574E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=3.00E-05,VTO=-0.328,LAMBDA=0.015,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=3.00E-05,VTO=+0.328,LAMBDA=0.015,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=5.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=12.400E-11) +* +* +.ENDS AD8508 + + +* AD8565 SPICE Macro-model Typical Values +* Generic Desc: Single LCD driver amp - 16V rail-rail +* Developed by: RM / ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (06/2007) +* Copyright 2004, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8565 1 2 99 50 45 +* +* INPUT STAGE +* +Q1 4 7 18 PIX +Q2 6 2 17 PIX +Q3 11 7 15 NIX +Q4 12 2 16 NIX +RC1 4 50 2000 +RC2 6 50 2000 +RC3 99 11 2000 +RC4 99 12 2000 +C1 4 6 3.3E-12 +C2 11 12 3.3E-12 +RE1 8 18 1.2E3 +RE2 8 17 1.2E3 +RE3 15 10 1.2E3 +RE4 16 10 1.2E3 +I1 99 8 100E-6 +I2 10 50 100E-6 +V1 9 8 1 +V2 13 50 1 +D1 9 99 DX +D2 13 10 DX +EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 2E-3 1 1 1 +IOS 1 2 5E-9 +* +* CMRR 95dB, ZERO AT 20kHz +* +ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 +RCM1 21 22 500E3 +CCM1 21 22 15.9E-12 +RCM2 22 98 8.9 +* +* PSRR=100dB, ZERO AT 100Hz +* +* RPS1 70 0 1E6 +* RPS2 71 0 1E6 +* CPS1 99 70 1E-5 +* CPS2 50 71 1E-5 +* EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 +EPSY 98 72 POLY(2) (99,0) (0,50) 0 1 1 +RPS1 72 73 1.59E6 +CPS1 72 73 1E-9 +RPS2 73 98 50 +* +* VOLTAGE NOISE REFERENCE OF 24nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 24 +RN2 81 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 +GSY 99 50 (99,50) 12.5E-6 +EVP 97 98 (99,50) 0.5 +EVN 51 98 (50,99) 0.5 +* +* LHP ZERO AT 7MHz, POLE AT 50MHz +* +E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 +R2 32 33 3.7E3 +R3 33 98 22.74E3 +C3 32 33 1E-12 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (4,6) (11,12) 0 150E-6 150E-6 +R1 30 98 542E3 +CF 45 30 10E-12 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1u W=1610u +M6 45 47 50 50 NOX L=1u W=1610u +EG1 99 46 POLY(1) (98,30) 0.5209 1 +EG2 47 50 POLY(1) (30,98) 0.5209 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PNP (BF=103,IS=1E-14,VA=100,KF=4.3E-14) +.MODEL NIX NPN (BF=124,IS=1E-14,VA=100,KF=4.3E-14) +.MODEL DX D(IS=1E-14,RS=5) +.ENDS AD8565 + + + +* AD8613 SPICE Macro-model +* Generic Desc: 1.8/5V, CMOS, OP, Low Pwr, RRIO, 1X +* Developed by: RM +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (02/2007) +* 1.0 (08/2012) - Updated to new header style +* 2.0 (03/2017) - Revised CMRR section to 100dB - KF +* Copyright 2007, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8613 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=2.37E-04 +M2 16 2 8 8 PIX L=1E-6 W=2.37E-04 +M3 17 7 10 10 NIX L=1E-6 W=8.88E-05 +M4 18 2 10 10 NIX L=1E-6 W=8.88E-05 +RD1 14 50 8.00E+04 +RD2 16 50 8.00E+04 +RD3 99 17 8.00E+04 +RD4 99 18 8.00E+04 +C1 14 16 8.08E-13 +C2 17 18 8.08E-13 +I1 99 8 5.00E-06 +I2 10 50 5.00E-06 +V1 99 9 2.625E-01 +V2 13 50 1.625E-01 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 4.00E-04 1 1 1 1 +IOS 1 2 5.00E-14 +* +*CMRR=95dB, POLE AT 1000 Hz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 8.89E-03 8.89E-03 +R10 21 22 1.59E+04 +R20 22 98 1.59E-01 +C10 21 22 1.00E-09 +* +* PSRR=90dB, POLE AT 100 Hz +* +EPSY 72 98 POLY(1) (99,50) -1.58113883 0.316227766 +CPS3 72 73 1.00E-06 +RPS3 72 73 1.59E+03 +RPS4 73 98 1.59E-01 +* +* VOLTAGE NOISE REFERENCE OF 22nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 1.98E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 100 Hz +* +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -8.09E-06 3.0E-06 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 4.15E-05 4.15E-05 +R1 30 98 1.00E+06 +RZ 30 31 7.91E+02 +CF 45 31 3.32E-10 +V3 32 30 3.53E-01 +V4 30 33 -7.53E-01 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=2.50E-04 +M6 45 47 50 50 NOX L=1E-6 W=1.93E-03 +EG1 99 46 POLY(1) (98,30) 7.465E-01 1 +EG2 47 50 POLY(1) (30,98) 6.335E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.7,LAMBDA=0.047,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.6,LAMBDA=0.022,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.50E-05,VTO=-0.5,LAMBDA=0.047) +.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5,LAMBDA=0.022) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=4.84E-11) +* +* +.ENDS AD8613 +* + +* AD8617 SPICE Macro-model +* Generic Desc: 1.8/5V, CMOS, OP, Low Pwr, RRIO, 2X +* Developed by: VW ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (02/2010) +* 3.0 (03/2017) - Followed AD8613 model, dual version only +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: VSY=5V, T=25degC +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8617 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=2.37E-04 +M2 16 2 8 8 PIX L=1E-6 W=2.37E-04 +M3 17 7 10 10 NIX L=1E-6 W=8.88E-05 +M4 18 2 10 10 NIX L=1E-6 W=8.88E-05 +RD1 14 50 8.00E+04 +RD2 16 50 8.00E+04 +RD3 99 17 8.00E+04 +RD4 99 18 8.00E+04 +C1 14 16 8.08E-13 +C2 17 18 8.08E-13 +I1 99 8 5.00E-06 +I2 10 50 5.00E-06 +V1 99 9 2.625E-01 +V2 13 50 1.625E-01 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 4.00E-04 1 1 1 1 +IOS 1 2 5.00E-14 +* +*CMRR=95dB, POLE AT 1000 Hz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 8.89E-03 8.89E-03 +R10 21 22 1.59E+04 +R20 22 98 1.59E-01 +C10 21 22 1.00E-09 +* +* PSRR=90dB, POLE AT 100 Hz +* +EPSY 72 98 POLY(1) (99,50) -1.58113883 0.316227766 +CPS3 72 73 1.00E-06 +RPS3 72 73 1.59E+03 +RPS4 73 98 1.59E-01 +* +* VOLTAGE NOISE REFERENCE OF 22nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 1.98E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 100 Hz +* +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -8.09E-06 3.0E-06 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 4.15E-05 4.15E-05 +R1 30 98 1.00E+06 +RZ 30 31 7.91E+02 +CF 45 31 3.32E-10 +V3 32 30 3.53E-01 +V4 30 33 -7.53E-01 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=2.50E-04 +M6 45 47 50 50 NOX L=1E-6 W=1.93E-03 +EG1 99 46 POLY(1) (98,30) 7.465E-01 1 +EG2 47 50 POLY(1) (30,98) 6.335E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.7,LAMBDA=0.047,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.6,LAMBDA=0.022,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.50E-05,VTO=-0.5,LAMBDA=0.047) +.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5,LAMBDA=0.022) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=4.84E-11) +* +* +.ENDS AD8617 + + + +* AD8619 SPICE Macro-model +* Generic Desc: 1.8/5V, CMOS, OP, Low Pwr, RRIO, 4X +* Developed by: VW ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 2.0 (02/2010) +* 3.0 (03/201) - Revised to follow AD8613 model, quad version - KF +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: VSY=5V, T=25degC +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8619 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=2.37E-04 +M2 16 2 8 8 PIX L=1E-6 W=2.37E-04 +M3 17 7 10 10 NIX L=1E-6 W=8.88E-05 +M4 18 2 10 10 NIX L=1E-6 W=8.88E-05 +RD1 14 50 8.00E+04 +RD2 16 50 8.00E+04 +RD3 99 17 8.00E+04 +RD4 99 18 8.00E+04 +C1 14 16 8.08E-13 +C2 17 18 8.08E-13 +I1 99 8 5.00E-06 +I2 10 50 5.00E-06 +V1 99 9 2.625E-01 +V2 13 50 1.625E-01 +D1 8 9 DX +D2 13 10 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 4.00E-04 1 1 1 1 +IOS 1 2 5.00E-14 +* +*CMRR=95dB, POLE AT 1000 Hz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 8.89E-03 8.89E-03 +R10 21 22 1.59E+04 +R20 22 98 1.59E-01 +C10 21 22 1.00E-09 +* +* PSRR=90dB, POLE AT 100 Hz +* +EPSY 72 98 POLY(1) (99,50) -1.58113883 0.316227766 +CPS3 72 73 1.00E-06 +RPS3 72 73 1.59E+03 +RPS4 73 98 1.59E-01 +* +* VOLTAGE NOISE REFERENCE OF 22nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 1.98E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 100 Hz +* +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -8.09E-06 3.0E-06 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (14,16) (17,18) 0 4.15E-05 4.15E-05 +R1 30 98 1.00E+06 +RZ 30 31 7.91E+02 +CF 45 31 3.32E-10 +V3 32 30 3.53E-01 +V4 30 33 -7.53E-01 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=2.50E-04 +M6 45 47 50 50 NOX L=1E-6 W=1.93E-03 +EG1 99 46 POLY(1) (98,30) 7.465E-01 1 +EG2 47 50 POLY(1) (30,98) 6.335E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.7,LAMBDA=0.047,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.6,LAMBDA=0.022,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.50E-05,VTO=-0.5,LAMBDA=0.047) +.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5,LAMBDA=0.022) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=4.84E-11) +* +* +.ENDS AD8619 + + +* AD8657 SPICE Macro-model Typical Values +* Generic Desc: 3/18V, CMOS, OP, Low Pwr, RRIO, 2X +* Developed by: VW ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 1.1 (01/2011) +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: VSY=18V, T=25°C +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8657 1 2 99 50 45 +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L= 1.000E-06 W= 1.532E-04 +M2 6 2 8 8 PIX L= 1.000E-06 W=1.532E-04 +M3 14 7 18 18 NIX L=1.000E-06 W=4.085E-04 +M4 16 2 18 18 NIX L=1.000E-06 W=4.085E-04 +RD1 4 50 2.0E+04 +RD2 6 50 2.0E+04 +RD3 99 14 2.0E+04 +RD4 99 16 2.0E+04 +C1 4 6 9.4750E-12 +C2 14 16 9.4750E-12 +I1 99 8 1.722E-05 +I2 18 50 1.722E-05 +V1 99 9 1.429E-01 +V2 19 50 1.429E-01 +D1 8 9 DX +D2 19 18 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 3.500E-04 1 1 1 1 +IOS 1 2 2.000E-11 +CDiff 1 2 3.5E-12 +Cin1 1 50 10.5E-12 +Cin2 2 50 10.5E-12 +* +* +* CMRR +* +E1 72 98 POLY(2) (1,98) (2,98) 0 6.817E-02 6.817E-02 +R10 72 73 2.894E+02 +R20 73 98 1.592E-02 +C10 72 73 1.000E-06 +* +* PSRR +* +EPSY 21 98 POLY(1) (99,50) -1.757E+02 9.762E+00 +RPS1 21 22 3.183E+03 +RPS2 22 98 7.958E-01 +CPS1 21 22 1.000E-06 +* +* VOLTAGE NOISE +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 4.5165E+01 +RN2 81 98 1 +* +* FLICKER NOISE +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6551 +HFN 83 98 POLY(1) VFN 1.000E-03 1.000E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -1.74975E-05 5.031E-08 +EVP 97 98 POLY(1) (99,50) -1.05 0.25 +EVN 51 98 POLY(1) (50,99) 1.45 0.3 + +* +* GAIN STAGE +* +G1 98 30 POLY(2) (4,6) (14,16) 0 5.693E-05 5.693E-05 +R1 30 98 1.000E+06 +RZ 30 31 8.2720E+03 +CF 45 31 5.60E-10 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L= 2.000E-06 W=2.450E-04 +M6 45 47 50 50 NOX L= 2.000E-06 W=1.591E-04 +EG1 99 46 POLY(1) (98,30) 3.347E-01 1 +EG2 47 50 POLY(1) (30,98) 3.216E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.000E-05,VTO=-0.3,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=4.000E-05,VTO=+0.3,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=4.000E-05,VTO=-0.5,LAMBDA=0.01) +.MODEL NIX NMOS (LEVEL=2,KP=1.500E-05,VTO=0.5,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.5E-10) +* +* +.ENDS AD8657 +* + + + +* AD8662 SPICE Macro-model +* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 2X +* Developed by: RM, ADSJ-HH +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8662 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=3.02E-03 +M2 16 2 8 8 PIX L=1E-6 W=3.02E-03 +RC5 14 50 8.00E+02 +RC6 16 50 8.00E+02 +C1 14 16 1.00E-11 +I1 99 8 5.00E-04 +V1 99 9 2.071E+00 +D1 8 9 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 5.00E-05 1 1 1 1 +IOS 1 2 1.00E-13 +* +* +* CMRR=110dB, POLE AT 250 Hz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 1.26E-01 1.26E-01 +R10 21 22 6.37E+02 +R20 22 98 7.96E-03 +C10 21 22 1.00E-06 +* +* PSRR=115dB, POLE AT 20 Hz +* +EPSY 72 98 POLY(1) (99,50) -2.13E+01 1.33E+00 +CPS3 72 73 1.00E-06 +RPS3 72 73 7.96E+03 +RPS4 73 98 1.06E-02 +* +* VOLTAGE NOISE REFERENCE OF 10nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 9.89E+00 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 300 Hz +* +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -1.34E-05 1.10E-05 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (14,16) 0 4.83E-04 +R1 30 98 1.00E+06 +RZ 30 31 2.05E+02 +CF 45 31 5.52E-11 +V3 32 30 2.89E+00 +V4 30 33 -1.86E+00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=2.23E-04 +M6 45 47 50 50 NOX L=1E-6 W=7.38E-04 +EG1 99 46 POLY(1) (98,30) 9.639E-01 1 +EG2 47 50 POLY(1) (30,98) 6.777E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.00E-11) +* +* +.ENDS AD8662 +* +* + + + + +* AD8664 SPICE Macro-model +* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 4X +* Developed by: RM +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (04/2008) +* Copyright 2010, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8664 1 2 99 50 45 +*#ASSOC Category="Op-amps" symbol=opamp +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=3.02E-03 +M2 16 2 8 8 PIX L=1E-6 W=3.02E-03 +RC5 14 50 8.00E+02 +RC6 16 50 8.00E+02 +C1 14 16 1.00E-11 +I1 99 8 5.00E-04 +V1 99 9 2.071E+00 +D1 8 9 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 5.00E-05 1 1 1 1 +IOS 1 2 1.00E-13 +* +* +* CMRR=110dB, POLE AT 250 Hz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 1.26E-01 1.26E-01 +R10 21 22 6.37E+02 +R20 22 98 7.96E-03 +C10 21 22 1.00E-06 +* +* PSRR=115dB, POLE AT 20 Hz +* +EPSY 72 98 POLY(1) (99,50) -2.13E+01 1.33E+00 +CPS3 72 73 1.00E-06 +RPS3 72 73 7.96E+03 +RPS4 73 98 1.06E-02 +* +* VOLTAGE NOISE REFERENCE OF 10nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 9.89E+00 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 300 Hz +* +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -1.34E-05 1.10E-05 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (14,16) 0 4.83E-04 +R1 30 98 1.00E+06 +RZ 30 31 2.05E+02 +CF 45 31 5.52E-11 +V3 32 30 2.89E+00 +V4 30 33 -1.86E+00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=2.23E-04 +M6 45 47 50 50 NOX L=1E-6 W=7.38E-04 +EG1 99 46 POLY(1) (98,30) 9.639E-01 1 +EG2 47 50 POLY(1) (30,98) 6.777E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.00E-11) +* +* +.ENDS AD8664 +* +* + + + + +* AD8665 SPICE Macro-model +* 0.9Beta Rev (10/14/2013) +* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 1X +* Developed by: RM +* Revsion history: 02/06/2015 (KF) - fixed output swing +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (05/2008) + +* Copyright 2006, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8665 1 2 99 50 45 +* +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=3.02E-03 +M2 16 2 8 8 PIX L=1E-6 W=3.02E-03 +RC5 14 50 8.00E+02 +RC6 16 50 8.00E+02 +C1 14 16 1.00E-11 +I1 99 8 5.00E-04 +V1 99 9 2.071E+00 +D1 8 9 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 6.00E-04 1 1 1 1 +IOS 1 2 1.00E-13 +* +* +* CMRR=110dB, POLE AT 250 Hz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 1.26E-01 1.26E-01 +R10 21 22 6.37E+02 +R20 22 98 7.96E-03 +C10 21 22 1.00E-06 +* +* PSRR=115dB, POLE AT 20 Hz +* +EPSY 72 98 POLY(1) (99,50) -2.13E+01 1.33E+00 +CPS3 72 73 1.00E-06 +RPS3 72 73 7.96E+03 +RPS4 73 98 1.06E-02 +* +* VOLTAGE NOISE REFERENCE OF 10nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 9.89E+00 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 300 Hz +* +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -1.34E-05 1.10E-05 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (14,16) 0 4.83E-04 +R1 30 98 1.00E+06 +RZ 30 31 2.05E+02 +CF 45 31 5.52E-11 +*V3 32 30 2.89E+00 +V3 32 30 5.59E+00 +V4 30 33 -0.16E+00 +*V4 30 33 -0.86E+00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=2.23E-04 +*M5 45 46 99 99 POX L=1E-6 W=7.23E-04 +M6 45 47 50 50 NOX L=1E-6 W=7.38E-04 +EG1 99 46 POLY(1) (98,30) 6.639E-01 1 +*EG1 99 46 POLY(1) (98,30) 20.639E-01 1 +*EG2 47 50 POLY(1) (30,98) 6.77E-01 1 +EG2 47 50 POLY(1) (30,98) 6.77E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.00E-11) +* +* +.ENDS AD8665 +* +*$ + + + +* AD8666 SPICE Macro-model +* 0.9Beta Rev (10/14/2013) +* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 1X +* Developed by: RM +* Revsion history: 02/06/2015 (KF) - fixed output swing +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (05/2008) + +* Copyright 2006, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8666 1 2 99 50 45 +* +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=3.02E-03 +M2 16 2 8 8 PIX L=1E-6 W=3.02E-03 +RC5 14 50 8.00E+02 +RC6 16 50 8.00E+02 +C1 14 16 1.00E-11 +I1 99 8 5.00E-04 +V1 99 9 2.071E+00 +D1 8 9 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 6.00E-04 1 1 1 1 +IOS 1 2 1.00E-13 +* +* +* CMRR=110dB, POLE AT 250 Hz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 1.26E-01 1.26E-01 +R10 21 22 6.37E+02 +R20 22 98 7.96E-03 +C10 21 22 1.00E-06 +* +* PSRR=115dB, POLE AT 20 Hz +* +EPSY 72 98 POLY(1) (99,50) -2.13E+01 1.33E+00 +CPS3 72 73 1.00E-06 +RPS3 72 73 7.96E+03 +RPS4 73 98 1.06E-02 +* +* VOLTAGE NOISE REFERENCE OF 10nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 9.89E+00 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 300 Hz +* +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -1.34E-05 1.10E-05 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (14,16) 0 4.83E-04 +R1 30 98 1.00E+06 +RZ 30 31 2.05E+02 +CF 45 31 5.52E-11 +*V3 32 30 2.89E+00 +V3 32 30 5.59E+00 +V4 30 33 -0.16E+00 +*V4 30 33 -0.86E+00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=2.23E-04 +*M5 45 46 99 99 POX L=1E-6 W=7.23E-04 +M6 45 47 50 50 NOX L=1E-6 W=7.38E-04 +EG1 99 46 POLY(1) (98,30) 6.639E-01 1 +*EG1 99 46 POLY(1) (98,30) 20.639E-01 1 +*EG2 47 50 POLY(1) (30,98) 6.77E-01 1 +EG2 47 50 POLY(1) (30,98) 6.77E-01 1 +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.00E-11) +* +* +.ENDS AD8666 +* +*$ + + + +* AD8668 SPICE Macro-model +* 0.9Beta Rev (10/14/2013) +* Generic Desc: 5/16V, CMOS, OP, Low Noise, S SPLY, 1X +* Developed by: RM +* Revsion history: 02/06/2015 (KF) - fixed output swing +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (05/2008) + +* Copyright 2006, 2012 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* +* END Notes +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8668 1 2 99 50 45 +* +* +* INPUT STAGE +* +M1 14 7 8 8 PIX L=1E-6 W=3.02E-03 +M2 16 2 8 8 PIX L=1E-6 W=3.02E-03 +RC5 14 50 8.00E+02 +RC6 16 50 8.00E+02 +C1 14 16 1.00E-11 +I1 99 8 5.00E-04 +V1 99 9 2.071E+00 +D1 8 9 DX +EOS 7 1 POLY(4) (22,98) (73,98) (81,98) (70,98) 6.00E-04 1 1 1 1 +IOS 1 2 1.00E-13 +* +* +* CMRR=110dB, POLE AT 250 Hz +* +E1 21 98 POLY(2) (1,98) (2,98) 0 1.26E-01 1.26E-01 +R10 21 22 6.37E+02 +R20 22 98 7.96E-03 +C10 21 22 1.00E-06 +* +* PSRR=115dB, POLE AT 20 Hz +* +EPSY 72 98 POLY(1) (99,50) -2.13E+01 1.33E+00 +CPS3 72 73 1.00E-06 +RPS3 72 73 7.96E+03 +RPS4 73 98 1.06E-02 +* +* VOLTAGE NOISE REFERENCE OF 10nV/rt(Hz) +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 9.89E+00 +RN2 81 98 1 +* +* FLICKER NOISE CORNER = 300 Hz +* +D5 69 98 DNOISE +VSN 69 98 DC 0.6551 +H1 70 98 POLY(1) VSN 1.00E-03 1.00E+00 +RN 70 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) -1.34E-05 1.10E-05 +EVP 97 98 POLY(1) (99,50) 0 0.5 +EVN 51 98 POLY(1) (50,99) 0 0.5 +* +* GAIN STAGE +* +G1 98 30 POLY(1) (14,16) 0 4.83E-04 +R1 30 98 1.00E+06 +RZ 30 31 2.05E+02 +CF 45 31 5.52E-11 +*V3 32 30 2.89E+00 +V3 32 30 5.59E+00 +V4 30 33 -0.16E+00 +*V4 30 33 -0.86E+00 +D3 32 97 DX +D4 51 33 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=1E-6 W=2.23E-04 +*M5 45 46 99 99 POX L=1E-6 W=7.23E-04 +M6 45 47 50 50 NOX L=1E-6 W=7.38E-04 +EG1 99 46 POLY(1) (98,30) 6.639E-01 1 +*EG1 99 46 POLY(1) (98,30) 20.639E-01 1 +*EG2 47 50 POLY(1) (30,98) 6.77E-01 1 +EG2 47 50 POLY(1) (30,98) 6.77E-01 1 +* +* MODELS +.MODEL POX PMOS (LEVEL=2,KP=1.00E-05,VTO=-0.328,LAMBDA=0.01,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.328,LAMBDA=0.01,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.00E-05,VTO=-5.00E-01,LAMBDA=0.01) +.MODEL DX D(IS=1E-14,RS=5) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=3.00E-11) +.ENDS AD8668 +* +.subckt ADA4177-1 1 2 3 4 5 +C1 N006 N005 {Cf} +A1 N009 0 N010 N010 N010 N010 N005 N010 OTA g={Ga} Iout={Islew} en=8n enk=12 Vhigh=1e308 Vlow=-1e308 +D5 N006 3 X +D6 4 N006 X +G2 0 N010 3 0 500µ +R4 N010 0 1K noiseless +G3 0 N010 4 0 500µ +S1 N005 N010 4 3 SD +C4 N004 0 {5p*x} Rpar=1K noiseless +C18 2 1 1p Rpar=4Meg noiseless +D8 3 1 1nA m=.4 +C3 3 5 1p +C7 5 4 .25p +A2 2 1 0 0 0 0 0 0 OTA g=0 in=.2p ink=1.5K incm=.02p incmk=1.5k +Ö1 N006 3 4 N005 N010 Gm1={Gb} Ibias=500u +D1 3 2 1nA m=.4 +R5 5 N006 25 +L2 N004 N007 {5µ*x} +C10 N007 0 {5p*x} Rpar=1K noiseless +D2 2 3 OVP1 +D4 2 3 OVP2 +D7 4 1 OVP1 +D9 4 1 OVP2 +C2 3 2 2p +C5 3 1 2p +C6 2 4 2p +C11 1 4 2p +D10 2 1 DIN +B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)-1.4,.1), V(4)+1.4, .1)+100n*V(2) +B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.4, .1)+100n*V(1) +D11 N010 N005 IO +L1 N008 0 10µ Rser=1K noiseless +G1 0 N008 N007 0 1m +L3 N009 0 10µ Rser=1K noiseless +G4 0 N009 N008 0 1m +.param Cf = 1p +.param Ro = 11.8K +.param Avol = 320K +.param RL = 2K +.param AVmid = 3.5 +.param FmidA = 1Meg +.param Zomid = .08 +.param FmidZ = 1k +.param Vslew = 1.5Meg +.param Vmin = 3.5 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.model X D(Ron=1m Roff=1G Vfwd=-25m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model 1nA D(Ron=500Meg epsilon=.5 Ilimit=1n noiseless) +.model IO D(Ron=2K Roff=1T Vfwd={51m/Gb} Vrev={64m/Gb} revepsilon=.1 epsilon=.1 noiseless) +.model OVP1 D(Ron=400 Roff=400G epsilon=1 Ilimit=8m noiseless) +.model OVP2 D(Ron=12K Roff=400G Vfwd=6 epsilon=1 noiseless) +.model DIN D(Ron=300 epsilon=.5 Vfwd=1 Ilimit=10m revIlimit=10m Vrev=1 revepsilon=.5 noiseless) +.param X=2.5 +.ends ADA4177-1 +* +* +.subckt ADA4177 1 2 3 4 5 +C1 N006 N005 {Cf} +A1 N009 0 N010 N010 N010 N010 N005 N010 OTA g={Ga} Iout={Islew} en=8n enk=12 Vhigh=1e308 Vlow=-1e308 +D5 N006 3 X +D6 4 N006 X +G2 0 N010 3 0 500µ +R4 N010 0 1K noiseless +G3 0 N010 4 0 500µ +S1 N005 N010 4 3 SD +C4 N004 0 {5p*x} Rpar=1K noiseless +C18 2 1 1p Rpar=4Meg noiseless +D8 3 1 1nA m=.4 +C3 3 5 1p +C7 5 4 .25p +A2 2 1 0 0 0 0 0 0 OTA g=0 in=.2p ink=1.5K incm=.02p incmk=1.5k +Ö1 N006 3 4 N005 N010 Gm1={Gb} Ibias=500u +D1 3 2 1nA m=.4 +R5 5 N006 25 +L2 N004 N007 {5µ*x} +C10 N007 0 {5p*x} Rpar=1K noiseless +D2 2 3 OVP1 +D4 2 3 OVP2 +D7 4 1 OVP1 +D9 4 1 OVP2 +C2 3 2 2p +C5 3 1 2p +C6 2 4 2p +C11 1 4 2p +D10 2 1 DIN +B3 N004 0 I=2m*dnlim(uplim(V(2),V(3)-1.4,.1), V(4)+1.4, .1)+100n*V(2) +B4 0 N004 I=2m*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.4, .1)+100n*V(1) +D11 N010 N005 IO +L1 N008 0 10µ Rser=1K noiseless +G1 0 N008 N007 0 1m +L3 N009 0 10µ Rser=1K noiseless +G4 0 N009 N008 0 1m +.param Cf = 1p +.param Ro = 11.8K +.param Avol = 320K +.param RL = 2K +.param AVmid = 3.5 +.param FmidA = 1Meg +.param Zomid = .08 +.param FmidZ = 1k +.param Vslew = 1.5Meg +.param Vmin = 3.5 +.param Roe = 1/(1/RL+1/Ro) +.param Gb = ((FmidZ/FmidA)*(Roe/(AVmid*Zomid))-1)/Roe +.param Ga = 2*pi*FmidZ*Cf/(Zomid*gb) +.param RH = Avol/(Ga*Gb*Roe) +.param Islew = Vslew*Cf*(1+1/(Roe*Gb)) +.model X D(Ron=1m Roff=1G Vfwd=-25m epsilon=10m noiseless) +.model SD SW(Ron=10m Roff={RH} Vt={-Vmin-100m} Vh=-.1 noiseless) +.model 1nA D(Ron=500Meg epsilon=.5 Ilimit=1n noiseless) +.model IO D(Ron=2K Roff=1T Vfwd={51m/Gb} Vrev={64m/Gb} revepsilon=.1 epsilon=.1 noiseless) +.model OVP1 D(Ron=400 Roff=400G epsilon=1 Ilimit=8m noiseless) +.model OVP2 D(Ron=12K Roff=400G Vfwd=6 epsilon=1 noiseless) +.model DIN D(Ron=300 epsilon=.5 Vfwd=1 Ilimit=10m revIlimit=10m Vrev=1 revepsilon=.5 noiseless) +.param X=2.5 +.ends ADA4177 +* + +* +* +* ADA4637 SPICE Macro-model +* Description: Amplifier +* Generic Desc: 8/30V, JFET, OP, Low Noise, Low Ib, 1X +* Developed by: HH / ADSJ +* Revision History: 08/10/2012 - Updated to new header style +* 04/15/2021 - Corrected output voltage limit versus supply voltage. +* 1.0 (08/2010) +* Copyright 2010, 2012, 2021 by Analog Devices +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* CAUTION!! To aid in convergence, most Spice simulators add a +* conductance on every node to insure that no node is floating. +* This is GMIN, and the default value is usually 1E-12. To properly +* simulate the low input bias current and low current noise, the +* Spice simulator options have to be set to the following: +* .OPTIONS GMIN=0.01p +* .OPTIONS ABSTOL=0.01pA +* .OPTIONS ITL1=500 +* .OPTIONS ITL2=200 +* .OPTIONS ITL4=100 +* +* Not Modeled: +* +* Parameters modeled include: +* This model simulates typical values at Vs=±15V +* The ADA4637 is decompensated. Operate at a noise gain >5 +* +* END Notes +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT ADA4637 1 2 99 50 30 +* +* INPUT STAGE +* +Cdiff 1 2 3E-12 +Cin1 1 50 5E-12 +Cin2 2 50 5E-12 +* +R3 5 99a 2.579E+02 +R4 6 99a 2.579E+02 +Ddp 99b 99a DX +VCP 99 99b -0.3V +J1 5 2 4 JX +J2 6 7 4 JX +* +I1 4 50 3.877E-03 +IOS 1 2 67.25E-12 +EOS 7 1 POLY(3) (17,24) (73,98) (42,0) 110E-6 1 1 1 1 +* +EREF 98 0 24 0 1 +* +* SECOND STAGE +* +R5 9 98 3.974E+05 +C3 9 98 1.000E-9 +G1 98 9 5 6 1.700E-01 +V2 99 8 2.7; source +V3 10 50 2.3; sink +D1 9 8 DX2 +D2 10 9 DX2 +* +* 2nd +* +G5 98 18 9 98 1E-03 +R13 18 19 1.0E+03 +R13a 19 98 4.0E-3 +C13a 18 98 2E-13 +* +* COMMON-MODE GAIN NETWORK +* +R11 16 17 1.447E+01 +R12 17 98 1.768E-03 +E3 16 98 POLY(2) 1 98 2 98 0 7.192E-02 7.192E-02 +C8 16 17 1.0E-6 +* +* PSRR NETWORK +* +EPSY 98 72 POLY(1) (99,50) 2.897E-04 8.692E-03 +CPS3 72 73 1.000E-09 +RPS3 72 73 8.603E+04 +RPS4 73 98 1.326E+02 +* +* VOLTAGE NOISE GENERATOR +* +VN1 41 0 DC 2 +DN1 41 42 DEN +DN2 42 43 DEN +VN2 0 43 DC 2 +* +* +GSY 99 50 POLY(1) (99,50) 3.615E-03 11.7E-06 +* +* OUTPUT STAGE +* +R14 24 99 500E3 +R15 24 50 500E3 +R16 29 99 100 +R17 29 50 100 +G8 29 99 POLY(1) 99 18 1E-16 1.00E-2 +G9 50 29 POLY(1) 18 50 1E-16 1.00E-2 +* +V4 25 29 2.02; Isc high side +V5 29 26 1.83 +D3 18 25 DX +D4 26 18 DX +* +G6 27 50 18 29 10.0E-03 +G7 28 50 29 18 10.0E-03 +D5 99 27 DX +D6 99 28 DX +D7 50 27 DY +D8 50 28 DY +F1 29 0 V4 1 +F2 0 29 V5 1 +* +L1 29 30a 1E-15 +R24 30a 30 1m; 30 is output pin +* +* MODELS USED +* +.MODEL JX NJF(BETA=1.699E-02 VTO=-1.500 IS=7E-13 RD=1m ++ RS=1m CGD=1.5E-14 CGS=1.5E-14 LAMBDA=0.01 ) +*.MODEL JX PJF(BETA=1.4E-3 VTO=-1.000 IS=20E-12 RD=0 +*+ RS=0 CGD=3E-12 CGS=3E-12) +.MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) +.MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) +.MODEL DEN D(IS=1E-12 RS=2.4E3, KF=3.7E-15 AF=1) +.MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) +.MODEL DX2 D(Ron=1m Roff=1G Vfwd=0 Epsilon=0.3) +* +.ENDS ADA4637 +* + +* ADA4661-2 SPICE Macro-model +* Typical Values +* 07/13, Version 0 +* VW ADSJ +* +* Copyright 2013 by Analog Devices +* +* VSY=18V, T=25°C +* +* Refer to "README.DOC" file for License Statement. Use of this +* model indicates your acceptance of the terms and provisions in +* the License Statement. +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT ADA4661-2 1 2 99 50 45 +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=2.65E-04 +M2 6 2 8 8 PIX L=1E-6 W=2.65E-04 +M3 14 7 18 18 NIX L=1E-6 W=1.18E-04 +M4 16 2 18 18 NIX L=1E-6 W=1.18E-04 +RD1 4 50 1.33E+04 +RD2 6 50 1.33E+04 +RD3 99 14 1.33E+04 +RD4 99 16 1.33E+04 +C1 4 6 8.15E-13 +C2 14 16 8.15E-13 +I1 99 8 3.00E-05 +I2 18 50 3.00E-05 +V1 99 9 2.113E+00 +V2 19 50 1.203E-01 +D1 8 9 DX +D2 19 18 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 1.50E-04 1 1 1 1 +IOS 1 2 1.50E-12 +Ccm1 1 50 3E-12 +Ccm2 2 50 3E-12 +Cdm 1 2 8.5E-12 +* +*CMRR +* +E1 72 98 POLY(2) (1,98) (2,98) 0 5.25E-03 5.25E-03 +R10 72 73 1.89E+02 +R20 73 98 7.959E-02 +C10 72 73 1.00E-06 +* +* PSRR +* +EPSY 21 98 POLY(1) (99,50) -2.074E+02 1.152E+1 +RPS1 21 22 1.59E+05 +RPS2 22 98 3.18E-02 +CPS1 21 22 1.00E-06 +* +* VOLTAGE NOISE +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 1.07E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6441 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) 4.575E-04 -1.55E-6 +EVP 97 98 POLY(1)(99,50) 0.5 0.175 +EVN 51 98 POLY(1)(50,99) 0.5 0.375 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (4,6) (14,16) 0 7.103E-03 7.103E-03 +R1 30 98 1.00E+06 +RZ 455 31 0.195E+00 +CF 30 31 2.95E-9 +EZ 455 98 (45,98) 1 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=3E-6 W=5.99E-04 +M6 45 47 50 50 NOX L=3E-6 W=5.99E-03 +EG1 99 46 POLY(1) (98,30) 8.523E-01 1 +EG2 47 50 POLY(1) (30,98) 6.964E-01 1 + +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.7,LAMBDA=0.047,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.6,LAMBDA=0.022,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.50E-05,VTO=-0.5,LAMBDA=0.047) +.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5,LAMBDA=0.022) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.53E-10) +* +* +.ENDS ADA4661-2 +* +*$ +* ADA4666-2 SPICE Macro-model +* Typical Values +* 07/13, Version 0 +* VW ADSJ +* +* Copyright 2013 by Analog Devices +* +* VSY=18V, T=25°C +* +* Refer to "README.DOC" file for License Statement. Use of this +* model indicates your acceptance of the terms and provisions in +* the License Statement. +* +* Node Assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT ADA4666-2 1 2 99 50 45 +* +* INPUT STAGE +* +M1 4 7 8 8 PIX L=1E-6 W=2.65E-04 +M2 6 2 8 8 PIX L=1E-6 W=2.65E-04 +M3 14 7 18 18 NIX L=1E-6 W=1.18E-04 +M4 16 2 18 18 NIX L=1E-6 W=1.18E-04 +RD1 4 50 1.33E+04 +RD2 6 50 1.33E+04 +RD3 99 14 1.33E+04 +RD4 99 16 1.33E+04 +C1 4 6 8.15E-13 +C2 14 16 8.15E-13 +I1 99 8 3.00E-05 +I2 18 50 3.00E-05 +V1 99 9 2.113E+00 +V2 19 50 1.203E-01 +D1 8 9 DX +D2 19 18 DX +EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) 2.2E-03 1 1 1 1 +IOS 1 2 1.50E-12 +Ccm1 1 50 3E-12 +Ccm2 2 50 3E-12 +Cdm 1 2 8.5E-12 +* +*CMRR +* +E1 72 98 POLY(2) (1,98) (2,98) 0 5.25E-03 5.25E-03 +R10 72 73 1.89E+02 +R20 73 98 7.959E-02 +C10 72 73 1.00E-06 +* +* PSRR +* +EPSY 21 98 POLY(1) (99,50) -2.074E+02 1.152E+1 +RPS1 21 22 1.59E+05 +RPS2 22 98 3.18E-02 +CPS1 21 22 1.00E-06 +* +* VOLTAGE NOISE +* +VN1 80 98 0 +RN1 80 98 16.45E-3 +HN 81 98 VN1 1.07E+01 +RN2 81 98 1 +* +* FLICKER NOISE CORNER +* +DFN 82 98 DNOISE +VFN 82 98 DC 0.6441 +HFN 83 98 POLY(1) VFN 1.00E-03 1.00E+00 +RFN 83 98 1 +* +* INTERNAL VOLTAGE REFERENCE +* +EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 +GSY 99 50 POLY(1) (99,50) 4.575E-04 -1.55E-6 +EVP 97 98 POLY(1)(99,50) 0.5 0.175 +EVN 51 98 POLY(1)(50,99) 0.5 0.375 +* +* GAIN STAGE +* +G1 98 30 POLY(2) (4,6) (14,16) 0 7.103E-03 7.103E-03 +R1 30 98 1.00E+06 +RZ 455 31 0.195E+00 +CF 30 31 2.95E-9 +EZ 455 98 (45,98) 1 +D3 30 97 DX +D4 51 30 DX +* +* OUTPUT STAGE +* +M5 45 46 99 99 POX L=3E-6 W=5.99E-04 +M6 45 47 50 50 NOX L=3E-6 W=5.99E-03 +EG1 99 46 POLY(1) (98,30) 8.523E-01 1 +EG2 47 50 POLY(1) (30,98) 6.964E-01 1 + +* +* MODELS +* +.MODEL POX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.7,LAMBDA=0.047,RD=0) +.MODEL NOX NMOS (LEVEL=2,KP=1.00E-05,VTO=+0.6,LAMBDA=0.022,RD=0) +.MODEL PIX PMOS (LEVEL=2,KP=1.50E-05,VTO=-0.5,LAMBDA=0.047) +.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5,LAMBDA=0.022) +.MODEL DX D(IS=1E-14,RS=0.1) +.MODEL DNOISE D(IS=1E-14,RS=0,KF=1.53E-10) +* +* +.ENDS ADA4666-2 +* +* Generic Desc: 10V/100V, BIPOLAR +* Developed by: DB / ADSJ +* Revision History: +*02/18/2014 - initial release +*02/26/2014 rev 0.1 - Edited subckt line +* 0.1 (02/2014) +* +* Copyright 2014 by Analog Devices +* +* T=25°C +* +* Refer to "README.DOC" file for License Statement. Use of this +* model indicates your acceptance of the terms and provisions in +* the License Statement. + +***************************************************** +* in+ in- vps+ vps- out +.SUBCKT ADA4700-1 1 2 99 50 5 +* +***************************************************** +* +***************************************************** +* input gm (voltage -> current) stage +q1 99 3 6 50 npn1 10 +q2 99 4 7 50 npn1 10 +q3 50 3 6 50 pnp1 1 +q4 50 4 7 50 pnp1 1 +c3 1 50 5.0pf +c4 2 50 5.0pf +c5 3 4 0.5pf +r5 1 3 2k +r6 2 4 2k +d01 6 8 d1 +d02 7 9 d1 +d03 9 8 d1 +d04 8 9 d1 +g01 8 50 56 55 160e-6 +g02 9 50 56 55 160e-6 +e01 10 55 87 9 1.00 +e02 91 55 11 55 1.00 +e03 92 55 12 55 1.00 +e04 93 91 56 55 12e-3 +e05 92 94 56 55 12e-3 +d05 10 11 d1 +d06 12 10 d1 +d07 95 93 d1 +d08 94 96 d1 +r7 55 95 200 +r8 96 55 200 +g04 55 14 55 95 3.00e-3 +g05 15 55 96 55 3.00e-3 +g06 11 14 56 55 100e-6 +g07 15 12 56 55 100e-6 +* +* input (NPN) base current caneclation +q5 99 45 44 50 npn1 10 +g14 44 50 56 55 160e-6 +e15 99 46 56 55 0.6 +g20 99 45 46 45 10e-6 +g21 99 3 46 45 10e-6 +g22 99 4 46 45 10e-6 +* +******************************************************** +* current mirror, voltage gain, and compensation at negative supply +g08 14 50 14 50 0.5e-3 +g09 18 50 14 50 0.5e-3 +c13 16 20 3.0pf +c15 20 18 15pf +c17 14 50 4.0pf +c19 20 50 3.0pf +r13 14 16 2.0k +c22 18 50 6.0pf +c23 21 50 20pf +r10 14 50 1e9 +r21 18 50 400e6 +* +******************************************************** +* current mirror, voltage gain, and compensation at postive supply +g10 99 15 99 15 0.5e-3 +g11 99 19 99 15 0.5e-3 +c14 17 20 3.0pf +c16 20 19 15pf +c18 99 15 4.0pf +c20 99 20 3.0pf +r14 15 17 2.0k +c24 19 99 6.0pf +c25 22 99 20pf +r11 99 15 1e9 +r23 19 99 400e6 +* +******************************************************** +* unit gain voltage buffer and output drive and bias +q12 34 34 29 50 pnp1 600 +q13 35 35 29 50 npn1 300 +e06 28 50 27 50 1.0 +d9 23 21 d1 +d10 24 23 d1 +d11 20 24 d1 +d12 25 20 d1 +d13 26 25 d1 +d14 22 26 d1 +d15 32 27 d1 +d16 27 33 d1 +d21 34 29 d1 +d22 29 35 d1 +r15 21 18 1.2k +r16 19 22 1.2k +r19 20 21 7.0k +r20 22 20 7.0k +r27 29 28 2.0k +* noiseless 40k resistors +g18 20 27 20 27 25e-6 +* +g12 34 50 56 55 100e-6 +g13 99 35 56 55 100e-6 +e13 32 50 54 55 2.6 +e14 99 33 54 55 2.7 +* +* output transistors w/short current limit and output feedback compensation +q17 99 37 39 50 npn1 300 +q18 50 36 38 50 pnp1 600 +q19 43 39 38 50 npn1 1 +q20 42 38 39 50 pnp1 1 +d19 22 43 d1 +d20 42 21 d1 +r3 39 5 20 +r4 5 38 20 +r17 35 37 2.0k +r18 34 36 1.0k +* current boost for output transistors +g16 36 50 36 34 15e-3 +g17 99 37 35 37 3.0e-3 +* +r25 42 21 100k +r26 22 43 100k +* +c1 5 41 20.0pf +r1 22 41 5.0k +c2 5 40 20.0pf +r2 21 40 5.0k +* +******************************************************** +* macromodel turn on control and bias +* +* Generate 1.0 volt reference +qb1 60 60 99 50 pnp1 1 +qb2 62 61 50 50 npn1 1 +qb3 64 62 63 50 npn1 10 +d64 65 64 d1 +d65 99 65 d1 +d66 66 64 d1 +d67 67 55 d1 +d68 68 55 d1 +rb1 60 61 2e6 +rb2 61 62 1.0k +rb3 61 50 500k +rb4 63 50 300 +rb5 65 64 20k +rb6 99 65 20k +rb7 99 66 20k +rb8 67 55 10e6 +rb9 68 55 160e6 +g67 99 67 99 66 160e-6 +g68 99 68 99 66 10e-6 +e67 69 55 67 55 0.77 +e68 70 69 67 68 7.90 +* +* Buffer and filter 1.0 volt reference +r51 70 51 10k +c51 51 55 40pf +e51 53 55 51 55 1.00 +r52 53 52 10k +c52 52 55 40pf +e52 56 55 52 55 1.00 +* +* Generate voltage half way between the power suppplies +eb1 55 50 99 50 0.50 +* +* Generate one diode voltage +g54 55 54 56 55 100e-6 +d40 54 55 d1 +rb10 54 55 20k +* +******************************************************** +* input error adjusts and input noise +* +* Vos +e84 84 8 56 55 1e-15 +* +* Input Voltage Noise flat band and 1/f +e87 87 84 78 79 1.6 +d76 76 55 dnoise +d77 77 55 dnoise +g76 55 76 56 55 160e-6 +g77 55 77 56 55 160e-6 +c77 79 78 5.0pf +r77 79 78 2.0k +r78 76 78 300k +r79 77 79 300k +* +* Input Current Noise flat band and 1/f +d80 80 55 dnoise +d81 81 55 dnoise +d82 82 55 dnoise +g80 55 80 56 55 160e-6 +g81 55 81 56 55 160e-6 +g82 55 82 56 55 160e-6 +g31 2 50 81 80 0.20e-6 +g32 1 50 82 80 0.20e-6 +* +******************************************************** +* adjust supply current +* +* set supply current at low voltage supply voltage +g15 99 50 56 55 600e-6 +* +* set supply current change with supply voltage change +r30 99 50 1.0e6 +* +******************************************************** +* esd diodes +d51 50 1 d2 +d52 1 99 d2 +d53 50 2 d2 +d54 2 99 d2 +d55 50 5 d2 +d56 5 99 d2 +d57 50 99 dz120 +* +******************************************************** +* models +* +.MODEL npn1 NPN is=1e-16, bf=200, vaf=150, ikf=100e-6 +*.MODEL npn1 NPN is=1e-16, bf=400, vaf=150, ikf=100e-6 +.MODEL pnp1 PNP is=1e-16, bf=100, vaf=100, ikf=50e-6 +* +*.model d1 d is=1e-14, rs=1.0 +.model d1 d is=1e-14, rs=10 +.model d2 d is=1e-14, rs=1.0 +.model dnoise d is=1e-14, rs=1.0, kf=5.0e-11 +.model dz120 d is=1e-13, rs=1.0, bv=120, ibv=5e-4 +* +******************************************************** +* generator format +* g_gen out_sink out_source input_pos input_neg gain(amp/volt) +* e_gen out_pos out_neg input_pos input_neg gain(volt/volt) +******************************************************** +* +.ENDS ADA4700-1 +* +***************************************************** +*ADA4830 Macro-model +*Function:Video Amplifier +* +*Revision History: +*Rev.1.0 Nov 2017-CJG +*Copyright 2017 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultiSim, SiMetrix, LTSpice +* +*Not modeled: +* PSRR, CMR, Output Offset Voltage, Distortion +* +* +* +*Parameters modeled include: +* Input CM limits and Typ output voltge swing over full supply range, +* Gain, Output current limits, Voltage Noise, Input Clamps, Output Clamps, +* Power Down,Quiescent supply current, Short-to-battery flag. +* +* +* +* Node assignments +* voltage reference +* | non-inverting input +* | | inverting input +* | | | positive supply +* | | | | negative supply +* | | | | | enable +* | | | | | | short-to-battery +* | | | | | | | output +* | | | | | | | | +.SUBCKT ADA4830 VREF INP INN VSY GND ENA STB OUT + + + +**Power Supplies** + +R11 VSY 17 Rideal 1e-006 +D4 GND 17 DIODE +I1 17 34 dc 0.01 +S6 34 GND ENA ENAN SWITCHe +E11 VSY1 GND 17 GND 1 +V9 VCL GND dc 10 +V11 VEE GND dc -10 +****************************************************************************************** + +**Input Stage** + +Rdiff INN INP Rideal 6700 +Rcm1 INP GND Rideal 2000 +Rcm2 INN GND Rideal 2000 +S1 INP 29 ENA ENAN SWITCHe +S2 INN 30 ENA ENAN SWITCHe +E1 INPCL GND 29 GND 1 +E2 INNCL GND 30 GND 1 +****************************************************************************************** + +**Input Clamp** + +R15 INPCL OPCL Rideal 10 +D6 OPCL 36 DIODE +D7 37 OPCL DIODE +V5 37 VEE dc 0.8 +V6 VCL 36 dc 1.28 +R16 INNCL ONCL Rideal 10 +D8 ONCL 19 DIODE +D9 23 ONCL DIODE +V18 23 VEE dc 0.8 +V19 VCL 19 dc 1.28 +E3 INPx GND OPCL GND 1 +E4 INNx GND ONCL GND 1 +****************************************************************************************** + +**Filter Stage** + +R2 2 INPx Rideal 1 +R4 6 INNx Rideal 1 +C1 2 GND 9.8e-010 +C4 6 GND 9.8e-010 +L1 2 3 2.679e-009 +L4 6 12 2.679e-009 +C2 3 GND 3.66e-009 +C5 12 GND 3.66e-009 +L2 3 4 3.66e-009 +L5 12 16 3.66e-009 +C3 4 GND 2.679e-009 +C6 16 GND 2.679e-009 +L3 4 5 4e-010 +L6 16 18 4e-010 +R3 GND 5 Rideal 1 +R5 GND 18 Rideal 1 +E5 FPO GND 5 GND 2 +E6 FNO GND 18 GND 2 +****************************************************************************************** + +**Voltage Reference** + +Rref1 VREF VSY1 Rideal 40000 +Rref2 VREF GND Rideal 40000 +E7 14 GND VREF GND 1 +R1 33 43 Rideal 5000 +S3 33 VREFx ENA ENAN SWITCHe + +****************************************************************************************** + +**Vref Clamp** + +R19 14 43 Rideal 10 +D10 43 31 DIODE +D11 32 43 DIODE +V20 VSY 31 dc 1.9 +V32 32 GND dc 0.93 +****************************************************************************************** + +**Gain Stage** + +R6 VREFx FPO Rideal 10000 +R7 1 FNO Rideal 10000 +G1 GND Vox VREFx 1 1 +R8 GND Vox Rideal 1000000 +R9 Vox 1 Rideal 5000 +C7 GND Vox 3e-010 +****************************************************************************************** + +**Enable** + +R14 ENA 26 Rideal 1600000000 +E12 24 27 26 GND 1 +V13 GND 27 dc 1 +R18 24 25 Rideal 1000000 +D5 GND 25 DIODE +E13 26 28 25 GND 1 +E14 28 ENAN 21 GND 1 +V4 20 GND dc 2 +R17 22 20 Rideal 0.1 +S5 22 21 ENA ENAN SWITCHe +R13 GND 21 Rideal 100 +C8 21 GND 1e-012 +****************************************************************************************** + +**Spectral Noise** + +h1 10 Vox Vmeas1 1 +Vmeas1 8 GND dc 0 +R10 8 GND Rideal 0.0167 +D1 9 8 DNOISE +V30 9 GND dc 0.1 +E8 7 GND 10 GND 1 +****************************************************************************************** + +**Output Clamp** + +R12 11 7 Rideal 100 +D2 11 13 DIODE +D3 41 11 DIODE +V21 41 GND dc 0.75 +V3 VSY 13 dc 0.987 +E9 15 GND 11 GND 1 +****************************************************************************************** + +**Output Current** + +E10 42 GND 15 GND 1 +h2 42 38 Vmeas2 20 +Vmeas2 42 35 dc 0 +D12 15 40 DIODE +D13 39 15 DIODE +V22 38 39 dc 1.805 +V23 40 38 dc 1.805 +S4 35 OUT ENA ENAN SWITCHe +****************************************************************************************** + +**Short to Battery Flag** +Vstb1 46 GND dc 0.11 +Vstb2 47 GND dc 0.11 +R20 44 46 Rideal 152 +R21 45 47 Rideal 152 +S7 44 STB INP GND SWITCHstb +S8 45 STB INN GND SWITCHstb +****************************************************************************************** + +**Models** + +.model SWITCHe vswitch(Von=5,Voff=0,ron=0.01,roff=1e06) +.model SWITCHstb vswitch(Von=11.5,Voff=10.5,ron=0.01,roff=1e016) +.model DIODE D +.model DNOISE D(KF=1.375e03) +.model Rideal res(T_ABS=-273) + +.ends ADA4830*TEST3 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.2.1 Nov 2016-JL +*Power Down Function Updated - 11/21/2016 (JL) +*Copyright 2016 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time, CMRR +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Removed FB pin for LTSPICE (temporary) +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +* | | | | | PD +* | | | | | | +.Subckt ADA4857 100 101 102 103 104 106 +* +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.35e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 4.65e-3 +S1 98 1030 113 106 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 113 106 Switch +S3 9 101 113 106 Switch +VOS 1 2 dc 2e-3 +IbiasP 110 2 dc -2e-6 +IbiasN 110 9 dc -2e-6 +RinCMP 110 2 Rideal 8e6 +RinCMN 9 110 Rideal 8e6 +CinCMP 110 2 0.4e-12 +CinCMN 9 110 0.4e-12 +IOS 9 2 0.05e-6 +RinDiff 9 2 Rideal 4000e3 +CinDiff 9 2 0.25e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 1.46 +VinN 42 112 dc 1.46 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2 +VPD1 81 0 dc 2.2 +RPD 111 106 Rideal 0.2e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 613 Hz*** +g210 210 110 200 110 10.9069e-6 +R210 210 110 Rideal 0.26e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 6.567 +VoutN 64 66 dc 6.567 +e60 65 110 111 110 1.209 +e61 66 110 112 110 1.209 +* +* +***Pole at 810MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 0.1965e-12 +* +***Pole at 12200MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.013e-12 +* +***Buffer*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +* +***Buffer*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +* +***Peak: f=3100MHz, Zeta=1.6, Gain=2.6dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 0.16e-9 +C290 291 292 16.429e-12 +R291 292 110 Rideal 28.656 +e295 295 110 292 110 1.349 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 19 +Lout 303 310 3.6e-9 +Cout 310 110 1.25e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 11.836 +VIoutN 304 306 dc 11.836 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 1.685 +VoutN1 74 112 dc 1.685 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 113 106 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=2.205,Voff=2.195,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=257.194) +.model DzSlewN D(BV=257.194) +.model DVnoisy D(IS=5.51e-16 KF=1.09e-14) +.model DINnoisy D(IS=7.97e-17 KF=2.45e-15) +.model DIPnoisy D(IS=7.97e-17 KF=2.45e-15) +.model Rideal res(T_ABS=-273) +* +.ends +* +* +* Copyright (c) 1998-2021 Analog Devices, Inc. All rights reserved. +* +.subckt ADA4860 1 2 3 4 5 6 +Cinp INp 0 {Cinp} Rpar={Rinp} Noiseless +Ibp INp 0 {Ibp} +Ibn N003 0 {Ibn} +Berr 0 Err I=(V(Binp,Binn)/{Rinn})*V(GO) Rpar=1 +Ro N007 N003 {Rinn} Noiseless +G1 0 N004 Zol5 0 10 +R1 N004 0 100m Noiseless +A1 6 4 0 0 0 _PD 0 0 SCHMITT Vt={PDVt} Vh=10m Trise={PDTon*2} Tfall={PDToff*2} Vlow=0 Vhigh=1 +A2 0 N003 0 0 0 0 0 0 OTA G=0 In={Inn} Ink={Inkn} +A3 0 INp 0 0 0 0 0 0 OTA G=0 In={Inp} Ink={Inkp} +G3 0 Zol2 Vclamp 0 1m +C1 Zol2 0 {Cfp2} Rpar=1k Noiseless +G4 0 Zol3 Zol2 0 1m +C2 Zol3 0 {Cfp2} Rpar=1k Noiseless +Cinn N003 0 {Cinn} +Binp 0 Binp I=Uplim(Dnlim(V(INp)+{Vos}, V(Vcm_min), 0.3), V(Vcm_max), 0.3) Rpar=1 +Binn 0 Binn I=Uplim(Dnlim(V(2), V(Vcm_min), 0.3), V(Vcm_max), 0.3) Rpar=1 +R2 Zol1 0 {Zol} Noiseless +R3 N003 2 1µ Noiseless +R4 INp 1 1µ Noiseless +Bpd 6 0 I={Ipd_off}+V(_PD)* {Ipd_on-Ipd_off} +Bq 3 4 I={Iq_off}+V(_PD)* {Iq_on-Iq_off}+V(Imon) +G7 0 Vs 3 4 1m +R9 Vs 0 1k Noiseless +A7 VminGD 0 _PD 0 VmaxGD 0 GO 0 AND Tau=1n +A5 Vs 0 0 0 0 0 VminGD 0 SCHMITT Vt={Vsmin-50m} Vh=10m Tau=1n +A6 Vs 0 0 0 0 VmaxGD 0 0 SCHMITT Vt={Vsmax-50m} Vh=10m Tau=1n +R_Iout N004 N002 1µ +Bimon 0 Imon I=1m*I(R_Iout) Rpar=1k Cpar=1p +Bhi 0 Hi I=1m*(V(3)-Table(V(Imon), 4m, 0.9, 20m, 1.9, 27m, 3, 85m, 5)) Rpar=1k +Blo 0 Lo I=1m*(V(4)+Table(-V(Imon), 4m, 0.9, 20m, 1.9, 27m, 3, 85m, 5)) Rpar=1k +A4 0 Err 0 0 0 0 Zol1 0 OTA G=1 Cout={Cfp1} Asym Isrc={Isrc} Isink={Isink} En={En} Enk={Enk} Vhigh=1e308 Vlow=-1e308 +BVclamp 0 Vclamp I=1m*Uplim(Dnlim(V(ZOL1), V(Lo), 0.3), V(Hi), 0.3) Rpar=1k +D2 N002 5 Iscp +D1 5 N002 Iscn +G11 0 Zol4 Zol3 0 1m +C8 Zol4 0 {Cfp2} Rpar=1k Noiseless +G12 0 Zol5 Zol4 0 1m +C9 Zol5 0 {Cfp2} Rpar=1k Noiseless +Bbuf 0 N007 I=(V(INp) +{Vos})*V(GO) +R11 N007 0 1 +BVcm_min 0 Vcm_min I=V(4)+{Vcm_min} Rpar=1 +BVcm_max 0 Vcm_max I=V(3)+{Vcm_max} Rpar=1 +.param Rinp=12Meg Cinp=1.5p +.param Rinn=90 Cinn=680f +.param Zol=700k fp1=260k fp2=3.2G fp3=1T +.param SRp=980 SRn=-790 +.param En=4n Enk=450 +.param Inp=1.5p Inkp=7k +.param Inn=7.7p Inkn=1.75k +.param Vcm_min=1.2 Vcm_max=-1.3 +.param Vos=-3.5m +.param Ibp=-1u Ibn=1.5u +.param PDVt=0.6 PDTon=200n PDToff=3.5u +.param Ipd_on=130u Ipd_off=-250n +.param Iq_on=6m Iq_off=250u +.param Vsmin=5 Vsmax=12 +.param Iscp=85m Iscn=-85m +.param Cfp1 = {1 / (2 * pi * fp1 * Zol)} +.param Cfp2 = {1 / (2 * pi * fp2 * 1k)} +.param Cfp3 = {1 / (2 * pi * fp3 * 1k)} +.param Isrc = {Cfp1 * SRp * 1e6} +.param Isink= {Cfp1 * SRn * 1e6} +.model Iscp D(Ron=1m Roff=1G Ilimit={Iscp} Epsilon=50m) +.model Iscn D(Ron=1m Roff=1G Ilimit={-Iscn} Epsilon=50m) +.ends ADA4860 + +* +* +.subckt ADA4530-1 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-.2, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +D9 N008 0 DLIM +C13 3 4 10p +A1 0 2 0 0 0 0 0 0 OTA g=0 in=.07f +G1 0 N016 5 Mid 100m +C8 N008 N016 38p +C6 2 4 4p Rser=100k noiseless +A4 N004 0 0 0 0 0 N007 0 OTA g=1m linear enk=330 en=13.8n*(1+freq/5Meg) Rout=1k Cout=15p Vlow=-1e308 Vhigh=1e308 +C7 3 2 4p Rser=100k noiseless +A7 0 N006 0 0 0 0 N008 0 OTA g=500u linear Cout=10f Vhigh=1e308 Vlow=-1e308 +D3 3 4 DBURN +G5 0 Mid 3 0 .5m +G6 0 Mid 4 0 .5m +R4 Mid 0 1K noiseless +M1 5 N014 4 4 NI temp=27 M=10 +C2 3 5 1p Rpar=1G Rser=10k noiseless +M2 5 N009 3 3 PI temp=27 M=10 +A2 3 N009 4 4 4 4 N014 4 OTA g=1u linear ref=1.4 vlow=0 vhigh=3.4 +C3 3 N009 1f Rpar=1Meg Rser=500k noiseless +A3 0 N010 3 3 3 3 N009 3 OTA g=20u linear ref=-37.7515m vlow=-3.5 vhigh=2.5 +C11 N014 4 1p Rpar=1Meg Rser=10Meg noiseless +D4 5 4 DoutMin +D5 3 5 DoutMin +S1 N008 0 4 3 SNLG +C4 3 1 4p Rser=100k noiseless +C5 1 4 4p Rser=100k noiseless +C12 N008 0 2p +C19 N009 5 1.5p Rser=75k noiseless +M3 3 N011 6 6 NG temp=27 +M4 4 N011 6 6 PG temp=27 +C17 3 6 500f +C21 6 4 500f +C22 N011 Mid 28.937f Rpar=2Meg noiseless +G3 Mid N011 1 Mid 1µ +S2 N011 Mid N011 3 Suplim +A5 1 0 0 0 0 0 0 0 OTA g=0 in=.07f +D6 2 6 DIN +D7 6 1 DIN +C23 2 6 200f +C25 6 1 200f +C14 N016 0 3n Rser=20 Rpar=10 noiseless +C9 5 4 1p Rpar=1G Rser=10k noiseless +A6 0 N005 0 0 0 0 N006 0 OTA g=1m linear Rout=1k Cout=15p vlow=-105.5m vhigh=105.5m +C15 N005 0 15p Rpar=1k noiseless +A9 0 N008 0 0 0 0 N010 0 OTA g=20m iout=1m Rout=1k Cout=40p vlow=-1e308 vhigh=1e308 +G2 0 N005 N007 0 1m +C1 5 N014 1.5p Rser=1Meg noiseless +.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=500m ilimit=703.57u noiseless) +.model DoutMin D(Ron=100 Roff=100 ilimit=20u noiseless) +.model SNLG SW(level=2 Ron=2Meg Roff=50Meg vt=-3 vh=-1.5 noiseless) +.param CL=10p +.model PI VDMOS(kp=280u vto=-500m mtriode=2.3 ksubthres=100m pchan noiseless) +.model NI VDMOS(kp=700u vto=500m mtriode=1.6 ksubthres=100m noiseless) +.model DLIM D(Ron=1k Roff=2G Vfwd=1.8 Vrev=1.8 epsilon=100m revepsilon=100m noiseless) +.model PG VDMOS(kp=1.72m vto=300m mtriode=2 ksubthres=100m pchan noiseless) +.model NG VDMOS(kp=1.72m vto=-300m ksubthres=100m noiseless) +.model Suplim SW(Ron=1 Roff=2Meg vt=-1.39 vh=-100m noiseless) +.model DIN D(Ron=1k Roff=30T vfwd=600m epsilon=300m vrev=600m revepsilon=300m noiseless) +.ends ADA4530-1 +* +* +* +.subckt ADA4530 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-.2, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +D9 N008 0 DLIM +C13 3 4 10p +A1 0 2 0 0 0 0 0 0 OTA g=0 in=.07f +G1 0 N016 5 Mid 100m +C8 N008 N016 38p +C6 2 4 4p Rser=100k noiseless +A4 N004 0 0 0 0 0 N007 0 OTA g=1m linear enk=330 en=13.8n*(1+freq/5Meg) Rout=1k Cout=15p Vlow=-1e308 Vhigh=1e308 +C7 3 2 4p Rser=100k noiseless +A7 0 N006 0 0 0 0 N008 0 OTA g=500u linear Cout=10f Vhigh=1e308 Vlow=-1e308 +D3 3 4 DBURN +G5 0 Mid 3 0 .5m +G6 0 Mid 4 0 .5m +R4 Mid 0 1K noiseless +M1 5 N014 4 4 NI temp=27 M=10 +C2 3 5 1p Rpar=1G Rser=10k noiseless +M2 5 N009 3 3 PI temp=27 M=10 +A2 3 N009 4 4 4 4 N014 4 OTA g=1u linear ref=1.4 vlow=0 vhigh=3.4 +C3 3 N009 1f Rpar=1Meg Rser=500k noiseless +A3 0 N010 3 3 3 3 N009 3 OTA g=20u linear ref=-37.7515m vlow=-3.5 vhigh=2.5 +C11 N014 4 1p Rpar=1Meg Rser=10Meg noiseless +D4 5 4 DoutMin +D5 3 5 DoutMin +S1 N008 0 4 3 SNLG +C4 3 1 4p Rser=100k noiseless +C5 1 4 4p Rser=100k noiseless +C12 N008 0 2p +C19 N009 5 1.5p Rser=75k noiseless +M3 3 N011 6 6 NG temp=27 +M4 4 N011 6 6 PG temp=27 +C17 3 6 500f +C21 6 4 500f +C22 N011 Mid 28.937f Rpar=2Meg noiseless +G3 Mid N011 1 Mid 1µ +S2 N011 Mid N011 3 Suplim +A5 1 0 0 0 0 0 0 0 OTA g=0 in=.07f +D6 2 6 DIN +D7 6 1 DIN +C23 2 6 200f +C25 6 1 200f +C14 N016 0 3n Rser=20 Rpar=10 noiseless +C9 5 4 1p Rpar=1G Rser=10k noiseless +A6 0 N005 0 0 0 0 N006 0 OTA g=1m linear Rout=1k Cout=15p vlow=-105.5m vhigh=105.5m +C15 N005 0 15p Rpar=1k noiseless +A9 0 N008 0 0 0 0 N010 0 OTA g=20m iout=1m Rout=1k Cout=40p vlow=-1e308 vhigh=1e308 +G2 0 N005 N007 0 1m +C1 5 N014 1.5p Rser=1Meg noiseless +.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=500m ilimit=703.57u noiseless) +.model DoutMin D(Ron=100 Roff=100 ilimit=20u noiseless) +.model SNLG SW(level=2 Ron=2Meg Roff=50Meg vt=-3 vh=-1.5 noiseless) +.param CL=10p +.model PI VDMOS(kp=280u vto=-500m mtriode=2.3 ksubthres=100m pchan noiseless) +.model NI VDMOS(kp=700u vto=500m mtriode=1.6 ksubthres=100m noiseless) +.model DLIM D(Ron=1k Roff=2G Vfwd=1.8 Vrev=1.8 epsilon=100m revepsilon=100m noiseless) +.model PG VDMOS(kp=1.72m vto=300m mtriode=2 ksubthres=100m pchan noiseless) +.model NG VDMOS(kp=1.72m vto=-300m ksubthres=100m noiseless) +.model Suplim SW(Ron=1 Roff=2Meg vt=-1.39 vh=-100m noiseless) +.model DIN D(Ron=1k Roff=30T vfwd=600m epsilon=300m vrev=600m revepsilon=300m noiseless) +.ends ADA4530 +* diff --git a/spice/copy/sub/ADM7150_1.sub b/spice/copy/sub/ADM7150_1.sub new file mode 100755 index 0000000..16d9590 Binary files /dev/null and b/spice/copy/sub/ADM7150_1.sub differ diff --git a/spice/copy/sub/ADM7154_5.sub b/spice/copy/sub/ADM7154_5.sub new file mode 100755 index 0000000..b38f413 Binary files /dev/null and b/spice/copy/sub/ADM7154_5.sub differ diff --git a/spice/copy/sub/ADM7160-x.x.sub b/spice/copy/sub/ADM7160-x.x.sub new file mode 100755 index 0000000..585d137 Binary files /dev/null and b/spice/copy/sub/ADM7160-x.x.sub differ diff --git a/spice/copy/sub/ADM7170.sub b/spice/copy/sub/ADM7170.sub new file mode 100755 index 0000000..ee9ff0b Binary files /dev/null and b/spice/copy/sub/ADM7170.sub differ diff --git a/spice/copy/sub/ADM7171.sub b/spice/copy/sub/ADM7171.sub new file mode 100755 index 0000000..4191755 Binary files /dev/null and b/spice/copy/sub/ADM7171.sub differ diff --git a/spice/copy/sub/ADM7172.sub b/spice/copy/sub/ADM7172.sub new file mode 100755 index 0000000..3361efd Binary files /dev/null and b/spice/copy/sub/ADM7172.sub differ diff --git a/spice/copy/sub/ADN8834.sub b/spice/copy/sub/ADN8834.sub new file mode 100755 index 0000000..1331da3 Binary files /dev/null and b/spice/copy/sub/ADN8834.sub differ diff --git a/spice/copy/sub/ADP1071-1.sub b/spice/copy/sub/ADP1071-1.sub new file mode 100755 index 0000000..cdabe9f Binary files /dev/null and b/spice/copy/sub/ADP1071-1.sub differ diff --git a/spice/copy/sub/ADP1071-2.sub b/spice/copy/sub/ADP1071-2.sub new file mode 100755 index 0000000..3802562 Binary files /dev/null and b/spice/copy/sub/ADP1071-2.sub differ diff --git a/spice/copy/sub/ADP1074.sub b/spice/copy/sub/ADP1074.sub new file mode 100755 index 0000000..c88934b Binary files /dev/null and b/spice/copy/sub/ADP1074.sub differ diff --git a/spice/copy/sub/ADP121.sub b/spice/copy/sub/ADP121.sub new file mode 100755 index 0000000..670c88b Binary files /dev/null and b/spice/copy/sub/ADP121.sub differ diff --git a/spice/copy/sub/ADP122.sub b/spice/copy/sub/ADP122.sub new file mode 100755 index 0000000..31c0420 Binary files /dev/null and b/spice/copy/sub/ADP122.sub differ diff --git a/spice/copy/sub/ADP123.sub b/spice/copy/sub/ADP123.sub new file mode 100755 index 0000000..5b081fc Binary files /dev/null and b/spice/copy/sub/ADP123.sub differ diff --git a/spice/copy/sub/ADP124.sub b/spice/copy/sub/ADP124.sub new file mode 100755 index 0000000..b5ef7ef Binary files /dev/null and b/spice/copy/sub/ADP124.sub differ diff --git a/spice/copy/sub/ADP125.sub b/spice/copy/sub/ADP125.sub new file mode 100755 index 0000000..fb7fb50 Binary files /dev/null and b/spice/copy/sub/ADP125.sub differ diff --git a/spice/copy/sub/ADP150-x.x.sub b/spice/copy/sub/ADP150-x.x.sub new file mode 100755 index 0000000..d95aa7e Binary files /dev/null and b/spice/copy/sub/ADP150-x.x.sub differ diff --git a/spice/copy/sub/ADP151-x.x.sub b/spice/copy/sub/ADP151-x.x.sub new file mode 100755 index 0000000..13f0199 Binary files /dev/null and b/spice/copy/sub/ADP151-x.x.sub differ diff --git a/spice/copy/sub/ADP1606.sub b/spice/copy/sub/ADP1606.sub new file mode 100755 index 0000000..63e3b8a Binary files /dev/null and b/spice/copy/sub/ADP1606.sub differ diff --git a/spice/copy/sub/ADP1607-001.sub b/spice/copy/sub/ADP1607-001.sub new file mode 100755 index 0000000..4bca858 Binary files /dev/null and b/spice/copy/sub/ADP1607-001.sub differ diff --git a/spice/copy/sub/ADP1607.sub b/spice/copy/sub/ADP1607.sub new file mode 100755 index 0000000..4f2b18d Binary files /dev/null and b/spice/copy/sub/ADP1607.sub differ diff --git a/spice/copy/sub/ADP1612.sub b/spice/copy/sub/ADP1612.sub new file mode 100755 index 0000000..ff5bbc7 Binary files /dev/null and b/spice/copy/sub/ADP1612.sub differ diff --git a/spice/copy/sub/ADP1613.sub b/spice/copy/sub/ADP1613.sub new file mode 100755 index 0000000..8b88c26 Binary files /dev/null and b/spice/copy/sub/ADP1613.sub differ diff --git a/spice/copy/sub/ADP1614-1.3.sub b/spice/copy/sub/ADP1614-1.3.sub new file mode 100755 index 0000000..0a8ee1f Binary files /dev/null and b/spice/copy/sub/ADP1614-1.3.sub differ diff --git a/spice/copy/sub/ADP1614-650.sub b/spice/copy/sub/ADP1614-650.sub new file mode 100755 index 0000000..f8c730d Binary files /dev/null and b/spice/copy/sub/ADP1614-650.sub differ diff --git a/spice/copy/sub/ADP1614.sub b/spice/copy/sub/ADP1614.sub new file mode 100755 index 0000000..6f7ddea Binary files /dev/null and b/spice/copy/sub/ADP1614.sub differ diff --git a/spice/copy/sub/ADP1621.sub b/spice/copy/sub/ADP1621.sub new file mode 100755 index 0000000..2a58924 Binary files /dev/null and b/spice/copy/sub/ADP1621.sub differ diff --git a/spice/copy/sub/ADP16x.lib b/spice/copy/sub/ADP16x.lib new file mode 100755 index 0000000..db6b98a --- /dev/null +++ b/spice/copy/sub/ADP16x.lib @@ -0,0 +1,91 @@ +* Copyright © Analog Devices, Inc. 2019. All rights reserved. +* +.subckt ADP16xa 1 2 3 4 5 +M1 4 N003 1 1 P +D1 2 4 S +A1 N005 5 1 1 1 1 N003 1 OTA G=4.55u Iout=3u en=60n enk=20k Vhigh=0 Vlow=-1 +C4 1 N003 320p Rpar=53MEG Rser=671k Cpar=0.5p noiseless +M2 2 N003 1 1 P m=333u +R4 N006 N005 350K noiseless +C2 1 N005 100f Rser=100MEG Rpar=3G noiseless +C3 4 2 20p +C6 1 2 20p +A2 3 2 2 2 2 2 N008 2 SCHMITT Vt=800m Vh=400m Trise=1u +A3 1 2 2 2 2 2 N004 2 SCHMITT Vt=1.895 Vh=295m Trise=1u +A4 2 N004 2 N008 2 2 N006 2 AND Cout=100p Rhigh=3Meg Rlow=100k +C5 3 2 1p +G1 1 2 N004 2 50n +G2 1 2 N006 2 525n +.model P VDMOS( pchan Kp=10 Ksubthres=10m Vto=-750m mtriode=600m lambda=50m noiseless) +.model S D(Ron=10 Roff=1G epsilon=1) +.model DIS SW(Roff=300 Ron=1G Vt=0.5 Vh=-0.4) +.ends ADP16xa +* +.subckt ADP16xad 1 2 3 4 5 +M1 4 N003 1 1 P +D1 2 4 S +A1 N005 5 1 1 1 1 N003 1 OTA G=4.55u Iout=3u en=60n enk=20k Vhigh=0 Vlow=-1 +C4 1 N003 320p Rpar=53MEG Rser=671k Cpar=0.5p noiseless +M2 2 N003 1 1 P m=333u +R4 N006 N005 350K noiseless +C2 1 N005 100f Rser=100MEG Rpar=3G noiseless +C3 4 2 20p +C6 1 2 20p +A2 3 2 2 2 2 2 N008 2 SCHMITT Vt=800m Vh=400m Trise=1u +S1 4 2 N006 2 DIS +A3 1 2 2 2 2 2 N004 2 SCHMITT Vt=1.895 Vh=295m Trise=1u +A4 2 N004 2 N008 2 2 N006 2 AND Cout=100p Rhigh=3Meg Rlow=100k +C5 3 2 1p +G1 1 2 N004 2 50n +G2 1 2 N006 2 525n +.model P VDMOS( pchan Kp=10 Ksubthres=10m Vto=-750m mtriode=600m lambda=50m noiseless) +.model S D(Ron=10 Roff=1G epsilon=1) +.model DIS SW(Roff=300 Ron=1G Vt=0.5 Vh=-0.4) +.ends ADP16xad +* +.subckt ADP16xf 1 2 3 4 +M1 4 N003 1 1 P +D1 2 4 S +A1 N005 N006 1 1 1 1 N003 1 OTA G=4.55u Iout=3u en=60n enk=20k Vhigh=0 Vlow=-1 +C4 1 N003 320p Rpar=53MEG Rser=671k Cpar=0.5p noiseless +M2 2 N003 1 1 P m=333u +R4 N007 N005 350K noiseless +C2 1 N005 100f Rser=100MEG Rpar=3G noiseless +C3 4 2 20p +C6 1 2 20p +A2 3 2 2 2 2 2 N008 2 SCHMITT Vt=800m Vh=400m Trise=1u +A3 1 2 2 2 2 2 N004 2 SCHMITT Vt=1.895 Vh=295m Trise=1u +A4 2 N004 2 N008 2 2 N007 2 AND Cout=100p Rhigh=3Meg Rlow=100k +C5 3 2 1p +G1 1 2 N004 2 50n +G2 1 2 N007 2 525n +G3 2 N006 4 2 {K} +C7 N006 2 1p Rpar=1k +.model P VDMOS( pchan Kp=10 Ksubthres=10m Vto=-750m mtriode=600m lambda=50m noiseless) +.model S D(Ron=10 Roff=1G epsilon=1) +.model DIS SW(Roff=300 Ron=1G Vt=0.5 Vh=-0.4) +.ends ADP16xf +* +.subckt ADP16xfd 1 2 3 4 +M1 4 N003 1 1 P +D1 2 4 S +A1 N005 N006 1 1 1 1 N003 1 OTA G=4.55u Iout=3u en=60n enk=20k Vhigh=0 Vlow=-1 +C4 1 N003 320p Rpar=53MEG Rser=671k Cpar=0.5p noiseless +M2 2 N003 1 1 P m=333u +R4 N007 N005 350K noiseless +C2 1 N005 100f Rser=100MEG Rpar=3G noiseless +C3 4 2 20p +C6 1 2 20p +A2 3 2 2 2 2 2 N008 2 SCHMITT Vt=800m Vh=400m Trise=1u +S1 4 2 N007 2 DIS +A3 1 2 2 2 2 2 N004 2 SCHMITT Vt=1.895 Vh=295m Trise=1u +A4 2 N004 2 N008 2 2 N007 2 AND Cout=100p Rhigh=3Meg Rlow=100k +C5 3 2 1p +G1 1 2 N004 2 50n +G2 1 2 N007 2 525n +G3 2 N006 4 2 {K} +C7 N006 2 1p Rpar=1k +.model P VDMOS( pchan Kp=10 Ksubthres=10m Vto=-750m mtriode=600m lambda=50m noiseless) +.model S D(Ron=10 Roff=1G epsilon=1) +.model DIS SW(Roff=300 Ron=1G Vt=0.5 Vh=-0.4) +.ends ADP16xfd diff --git a/spice/copy/sub/ADP1708.sub b/spice/copy/sub/ADP1708.sub new file mode 100755 index 0000000..5dd3a36 Binary files /dev/null and b/spice/copy/sub/ADP1708.sub differ diff --git a/spice/copy/sub/ADP1850.sub b/spice/copy/sub/ADP1850.sub new file mode 100755 index 0000000..68b8844 Binary files /dev/null and b/spice/copy/sub/ADP1850.sub differ diff --git a/spice/copy/sub/ADP1851.sub b/spice/copy/sub/ADP1851.sub new file mode 100755 index 0000000..93766d6 Binary files /dev/null and b/spice/copy/sub/ADP1851.sub differ diff --git a/spice/copy/sub/ADP1853.sub b/spice/copy/sub/ADP1853.sub new file mode 100755 index 0000000..f38b562 Binary files /dev/null and b/spice/copy/sub/ADP1853.sub differ diff --git a/spice/copy/sub/ADP2108-x.x.sub b/spice/copy/sub/ADP2108-x.x.sub new file mode 100755 index 0000000..3995c7f Binary files /dev/null and b/spice/copy/sub/ADP2108-x.x.sub differ diff --git a/spice/copy/sub/ADP2109-x.x.sub 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All rights reserved. +* +.subckt ADP1761 1 2 3 4 5 6 7 8 9 10 +A1 2 7 7 7 7 7 N014 7 SCHMITT Vt=.97 Vh=40m +C1 2 7 10p +C2 10 7 3p Rpar={Radj} +C3 1 7 3p noiseless +C4 3 7 3p +C5 4 7 3p +C6 5 7 3p +C7 6 7 3p +C8 8 7 3p +A2 3 7 7 7 7 7 N016 7 SCHMITT Vt=.6025 Vh=22.5m Trise=105u Tfall=1u +A3 7 N014 7 N016 7 7 EN 7 AND Tau=1u Ref=.1 +D1 8 N008 10µA +A4 N008 7 7 7 7 7 N020 7 BUF Trise=.6m Tfall=10u +D2 N018 8 X +D3 N018 N020 X +M1 2 EN 1 1 VREG temp=27 +S1 10 2 EN 7 50µA +G1 7 N010 N015 7 3m +C11 N010 7 10p Rpar=1K noiseless +A5 7 N014 7 N016 7 7 N008 7 AND Tau=1u Ref=.95 +M2 2 N010 9 9 REF temp=27 +C9 9 7 10p +D4 9 7 100µA +M3 N009 N006 2 2 P temp=27 +A6 N007 N005 2 2 2 2 N006 2 OTA G=240u Vhigh=0 en=1.5n+200/(75+freq)**4 Iout=10u Ref=-0.95m Vlow=-1.26 +S2 2 N006 7 N008 EN +B1 7 N026 I=1m*V(4,7)/V(9,7) Rpar=1K Cpar=10p +A7 N026 7 7 7 7 7 N025 7 SCHMITT Vt=.9375 Vh=12.5m +A8 N008 7 7 7 7 7 N023 7 BUF Trise=.8m Tfall=10u +A9 7 N014 7 N024 7 7 N022 7 AND Tau=1u Ref=.95 +S3 7 6 N022 7 PG +A10 7 N023 7 N025 7 N024 7 7 AND Vt=.95 +D5 N015 10 X +D6 N015 N018 X +D7 7 4 S +M5 N006 N006 P001 P001 P m=.212m temp=27 +R2 P001 2 1Meg noiseless +M6 N004 N006 2 2 P m=1.28m temp=27 +R4 N004 N009 20 +C14 N002 N004 50p +R5 5 N002 35K noiseless +G2 7 N005 N002 9 10µ +C15 N005 7 10p noiseless Rser=100k Rpar=100k +B2 4 7 I=V(EN,7)*V(Id) NoJacob +B3 0 ID I=table(-Id(M3), 0, 4.5m, 10m, 4.9m, 100m, 5.5m,1,7.5m) Rpar=1 Cpar=10n NoJacob +C16 2 N007 3f +R6 7 N007 1Meg noiseless +D8 N009 4 10mV +.model P VDMOS(Kp=45 Vto=-1 Ksubthres=50m Is=0 lambda=.3 mtriode=5 pchan noiseless) +.model 10µA D(Ron=10 Roff=100 RevIlimit=10u epsilon=10m Vrev=0 noiseless) +.model X D(Ron=1K Roff=1T epsilon=10m noiseless) +.model Vreg VDMOS(Kp=1 Vto=0 Ksubthres=10m noiseless) +.model REF VDMOS(Kp=1 Vto=-11.5m Ksubthres=10m noiseless) +.model 50µA SW(Ron=100 Roff=1T Ilimit=50u level=2 Vt=.5 Vh=-.1 noiseless) +.model 100µA D(Ron=200 epsilon=50m Ilimit=100u noiseless) +.model EN SW(Ron=10 Roff=1T Vt=-.5 Vh=-.4 noiseless) +.model PG SW(Ron=100 Roff=1G Vt=.5 Vh=-.4 noiseless) +.model S D(Ron=.2 epsilon=.2) +.model 10mV D(Ron=1m Roff=1K Vfwd=9m epsilon=10m) +.ends ADP1761 +* +.subckt ADP1762 1 2 3 4 5 6 7 8 9 10 +A1 2 7 7 7 7 7 N014 7 SCHMITT Vt=.97 Vh=40m +C1 2 7 10p +C2 10 7 3p Rpar={Radj} +C3 1 7 3p noiseless +C4 3 7 3p +C5 4 7 3p +C6 5 7 3p +C7 6 7 3p +C8 8 7 3p +A2 3 7 7 7 7 7 N016 7 SCHMITT Vt=.6025 Vh=22.5m Trise=105u Tfall=1u +A3 7 N014 7 N016 7 7 EN 7 AND Tau=1u Ref=.1 +D1 8 N008 10µA +A4 N008 7 7 7 7 7 N020 7 BUF Trise=.6m Tfall=10u +D2 N018 8 X +D3 N018 N020 X +M1 2 EN 1 1 VREG temp=27 +S1 10 2 EN 7 50µA +G1 7 N010 N015 7 3m +C11 N010 7 10p Rpar=1K noiseless +A5 7 N014 7 N016 7 7 N008 7 AND Tau=1u Ref=.95 +M2 2 N010 9 9 REF temp=27 +C9 9 7 10p +D4 9 7 100µA +M3 N009 N006 2 2 P temp=27 +A6 N007 N005 2 2 2 2 N006 2 OTA G=240u Vhigh=0 en=1.5n+200/(75+freq)**4 Iout=20u Ref=-1.5m Vlow=-1.26 +S2 2 N006 7 N008 EN +B1 7 N026 I=1m*V(4,7)/V(9,7) Rpar=1K Cpar=10p +A7 N026 7 7 7 7 7 N025 7 SCHMITT Vt=.9375 Vh=12.5m +A8 N008 7 7 7 7 7 N023 7 BUF Trise=.8m Tfall=10u +A9 7 N014 7 N024 7 7 N022 7 AND Tau=1u Ref=.95 +S3 7 6 N022 7 PG +A10 7 N023 7 N025 7 N024 7 7 AND Vt=.95 +D5 N015 10 X +D6 N015 N018 X +D7 7 4 S +M5 N006 N006 P001 P001 P m=.212m temp=27 +R2 P001 2 1Meg noiseless +M6 N004 N006 2 2 P m=1.28m temp=27 +R4 N004 N009 17 +C14 N002 N004 50p +R5 5 N002 35K noiseless +G2 7 N005 N002 9 10µ +C15 N005 7 10p noiseless Rser=100k Rpar=100k +B2 4 7 I=V(EN,7)*V(Id) NoJacob +B3 0 ID I=table(-Id(M3), 0, 4.5m, 10m, 4.9m, 100m, 5.5m,2, 9.4m) Rpar=1 Cpar=10n NoJacob +C16 2 N007 3f +R6 7 N007 1Meg noiseless +D8 N009 4 10mV m=2 +.model P VDMOS(Kp=70 Vto=-1 Ksubthres=.1 Is=0 lambda=.3 mtriode=3 pchan noiseless) +.model 10µA D(Ron=10 Roff=100 RevIlimit=10u epsilon=10m Vrev=0 noiseless) +.model X D(Ron=1K Roff=1T epsilon=10m noiseless) +.model Vreg VDMOS(Kp=1 Vto=0 Ksubthres=10m noiseless) +.model REF VDMOS(Kp=1 Vto=-11.5m Ksubthres=10m noiseless) +.model 50µA SW(Ron=100 Roff=1T Ilimit=50u level=2 Vt=.5 Vh=-.1 noiseless) +.model 100µA D(Ron=200 epsilon=50m Ilimit=100u noiseless) +.model EN SW(Ron=10 Roff=1T Vt=-.5 Vh=-.4 noiseless) +.model PG SW(Ron=100 Roff=1G Vt=.5 Vh=-.4 noiseless) +.model S D(Ron=.2 epsilon=.2) +.model 10mV D(Ron=1m Roff=1K Vfwd=9m epsilon=10m) +.ends ADP1762 +* +.subckt ADP1763 1 2 3 4 5 6 7 8 9 10 +A1 2 7 7 7 7 7 N014 7 SCHMITT Vt=.97 Vh=40m +C1 2 7 10p +C2 10 7 3p Rpar={Radj} +C3 1 7 3p noiseless +C4 3 7 3p +C5 4 7 3p +C6 5 7 3p +C7 6 7 3p +C8 8 7 3p +A2 3 7 7 7 7 7 N016 7 SCHMITT Vt=.6025 Vh=22.5m Trise=105u Tfall=1u +A3 7 N014 7 N016 7 7 EN 7 AND Tau=1u Ref=.1 +D1 8 N008 10µA +A4 N008 7 7 7 7 7 N020 7 BUF Trise=.6m Tfall=10u +D2 N018 8 X +D3 N018 N020 X +M1 2 EN 1 1 VREG temp=27 +S1 10 2 EN 7 50µA +G1 7 N010 N015 7 3m +C11 N010 7 10p Rpar=1K noiseless +A5 7 N014 7 N016 7 7 N008 7 AND Tau=1u Ref=.95 +M2 2 N010 9 9 REF temp=27 +C9 9 7 10p +D4 9 7 100µA +M3 N009 N006 2 2 P temp=27 +A6 N007 N005 2 2 2 2 N006 2 OTA G=240u Vhigh=0 en=1.5n+200/(75+freq)**4 Iout=100u Ref=-1.6m Vlow=-1.26 +S2 2 N006 7 N008 EN +B1 7 N026 I=1m*V(4,7)/V(9,7) Rpar=1K Cpar=10p +A7 N026 7 7 7 7 7 N025 7 SCHMITT Vt=.9375 Vh=12.5m +A8 N008 7 7 7 7 7 N023 7 BUF Trise=.8m Tfall=10u +A9 7 N014 7 N024 7 7 N022 7 AND Tau=1u Ref=.95 +S3 7 6 N022 7 PG +A10 7 N023 7 N025 7 N024 7 7 AND Vt=.95 +D5 N015 10 X +D6 N015 N018 X +D7 7 4 S +M5 N006 N006 P001 P001 P m=.212m temp=27 +R2 P001 2 1Meg noiseless +M6 N004 N006 2 2 P m=1.28m temp=27 +R4 N004 N009 23 +C14 N002 N004 50p +R5 5 N002 35K noiseless +G2 7 N005 N002 9 10µ +C15 N005 7 10p noiseless Rser=100k Rpar=100k +B2 4 7 I=V(EN,7)*V(Id) NoJacob +B3 0 ID I=table(-Id(M3), 0, 4.5m, 10m, 4.9m, 100m, 5.5m,3,12m) Rpar=1 Cpar=10n NoJacob +C16 2 N007 3f +R6 7 N007 1Meg noiseless +D8 N009 4 10mV m=3 +.model P VDMOS(Kp=95 Vto=-1 Ksubthres=.1 Is=0 lambda=.3 mtriode=2.2 Rd=1m pchan noiseless) +.model 10µA D(Ron=10 Roff=100 RevIlimit=10u epsilon=10m Vrev=0 noiseless) +.model X D(Ron=1K Roff=1T epsilon=10m noiseless) +.model Vreg VDMOS(Kp=1 Vto=0 Ksubthres=10m noiseless) +.model REF VDMOS(Kp=1 Vto=-11.5m Ksubthres=10m noiseless) +.model 50µA SW(Ron=100 Roff=1T Ilimit=50u level=2 Vt=.5 Vh=-.1 noiseless) +.model 100µA D(Ron=200 epsilon=50m Ilimit=100u noiseless) +.model EN SW(Ron=10 Roff=1T Vt=-.5 Vh=-.4 noiseless) +.model PG SW(Ron=100 Roff=1G Vt=.5 Vh=-.4 noiseless) +.model S D(Ron=.2 epsilon=.2) +.model 10mV D(Ron=1m Roff=1K Vfwd=9m epsilon=10m) +.ends ADP1763 +* +.subckt ADP1764 1 2 3 4 5 6 7 8 9 10 +A1 2 7 7 7 7 7 N013 7 SCHMITT Vt=.965 Vh=35m +C1 2 7 10p +C2 10 7 3p Rpar={Radj} +C3 1 7 3p noiseless +C4 3 7 3p +C5 4 7 3p +C6 5 7 3p +C7 6 7 3p +C8 8 7 3p +A2 3 7 7 7 7 7 N015 7 SCHMITT Vt=.625 Vh=25m Trise=105u Tfall=1u +A3 7 N013 7 N015 7 7 EN 7 AND Tau=1u Ref=.1 +D1 8 N008 10µA +A4 N008 7 7 7 7 7 N019 7 BUF Trise=.6m Tfall=10u +D2 N017 8 X +D3 N017 N019 X +M1 2 EN 1 1 VREG temp=27 +S1 10 2 EN 7 50µA +G1 7 N010 N014 7 2.99m +C11 N010 7 10p Rpar=1K noiseless +A5 7 N013 7 N015 7 7 N008 7 AND Tau=1u Ref=.95 +M2 2 N010 9 9 REF temp=27 +C9 9 7 10p +D4 9 7 100µA +M3 N009 N006 2 2 P temp=27 +A6 N007 N005 2 2 2 2 N006 2 OTA G=240u Vhigh=0 en=1n+6u/(.1+freq**.9) Iout=100u Ref=-1.3m Vlow=-1.26 +S2 2 N006 7 N008 EN +B1 7 N025 I=1m*V(4,7)/V(9,7) Rpar=1K Cpar=10p +A7 N025 7 7 7 7 7 N024 7 SCHMITT Vt=.9375 Vh=12.5m +A8 N008 7 7 7 7 7 N022 7 BUF Trise=.8m Tfall=10u +A9 7 N013 7 N023 7 7 N021 7 AND Tau=1u Ref=.95 +S3 7 6 N021 7 PG +A10 7 N022 7 N024 7 N023 7 7 AND Vt=.95 +D5 N014 10 X +D6 N014 N017 X +D7 7 4 S +M5 N006 N006 P002 P002 P m=.212m temp=27 +R2 P002 2 1Meg noiseless +M6 N004 N006 2 2 P m=1.28m temp=27 +R4 N004 N009 15.5 +C14 N002 N004 100p Rser=1 +R5 5 N002 40K noiseless +G2 7 N005 N002 9 10µ +C15 N005 7 20p noiseless Rser=100k Rpar=100k +B2 4 7 I=V(EN,7)*V(Id) NoJacob +B3 0 ID I=table(-Id(M3),100m,5.5m,4,11m) Rpar=1 Cpar=10n NoJacob +C16 2 N007 3f +R6 7 N007 4Meg noiseless +D8 N009 4 25mV m=4 +.model P VDMOS(Kp=152 Vto=-1 Ksubthres=50m Is=0 lambda=1 mtriode=9 pchan noiseless) +.model 10µA D(Ron=10 Roff=100 RevIlimit=10u epsilon=10m Vrev=0) +.model X D(Ron=1K Roff=1T epsilon=10m noiseless) +.model Vreg VDMOS(Kp=1 Vto=0 Ksubthres=10m noiseless) +.model REF VDMOS(Kp=1 Vto=-11.5m Ksubthres=10m noiseless) +.model 50µA SW(Ron=100 Roff=1T Ilimit=50u level=2 Vt=.5 Vh=-.1 noiseless) +.model 100µA D(Ron=200 epsilon=50m Ilimit=100u noiseless) +.model EN SW(Ron=10 Roff=1T Vt=-.5 Vh=-.4 noiseless) +.model PG SW(Ron=100 Roff=1G Vt=.5 Vh=-.4) +.model S D(Ron=10 Roff=1G epsilon=1) +.model 25mV D(Ron=1m Roff=1K Vfwd=25m epsilon=10m) +.ends ADP1764 +* +.subckt ADP1765 1 2 3 4 5 6 7 8 9 10 +A1 2 7 7 7 7 7 N014 7 SCHMITT Vt=1.015 Vh=85m +C1 2 7 10p +C2 10 7 3p Rpar={Radj} +C3 1 7 3p noiseless +C4 3 7 3p +C5 4 7 3p +C6 5 7 3p +C7 6 7 3p +C8 8 7 3p +A2 3 7 7 7 7 7 N016 7 SCHMITT Vt=.625 Vh=25m Trise=105u Tfall=1u +A3 7 N014 7 N016 7 7 EN 7 AND Tau=1u Ref=.1 +D1 8 N008 10µA +A4 N008 7 7 7 7 7 N020 7 BUF Trise=.6m Tfall=10u +D2 N018 8 X +D3 N018 N020 X +M1 2 EN 1 1 VREG temp=27 +S1 10 2 EN 7 50µA +G1 7 N010 N015 7 2.99m +C11 N010 7 10p Rpar=1K noiseless +A5 7 N014 7 N016 7 7 N008 7 AND Tau=1u Ref=.95 +M2 2 N010 9 9 REF temp=27 +C9 9 7 10p +D4 9 7 100µA +M3 N009 N006 2 2 P temp=27 +A6 N007 N005 2 2 2 2 N006 2 OTA G=120u Vhigh=0 en=1n+6u/(.1+freq**.9) Iout=100u Ref=-2.5m Vlow=-1.26 +S2 2 N006 7 N008 EN +B1 7 N026 I=1m*V(4,7)/V(9,7) Rpar=1K Cpar=10p +A7 N026 7 7 7 7 7 N025 7 SCHMITT Vt=.9375 Vh=12.5m +A8 N008 7 7 7 7 7 N023 7 BUF Trise=.8m Tfall=10u +A9 7 N014 7 N024 7 7 N022 7 AND Tau=1u Ref=.95 +S3 7 6 N022 7 PG +A10 7 N023 7 N025 7 N024 7 7 AND Vt=.95 +D5 N015 10 X +D6 N015 N018 X +D7 7 4 S +M5 N006 N006 P001 P001 P m=.212m temp=27 +R2 P001 2 1Meg noiseless +M6 N004 N006 2 2 P m=1.28m temp=27 +R4 N004 N009 15.5 +C14 N002 N004 100p +R5 5 N002 40K noiseless +G2 7 N005 N002 9 10µ +C15 N005 7 20p noiseless Rser=100k Rpar=100k +B2 4 7 I=V(EN,7)*V(Id) NoJacob +B3 0 ID I=table(-Id(M3),100m,5.5m,5,12m) Rpar=1 Cpar=10n NoJacob +C16 2 N007 3f +R6 7 N007 4Meg noiseless +D8 N009 4 25mV m=5 +.model P VDMOS(Kp=186 Vto=-1 Ksubthres=50m Is=0 lambda=.3 mtriode=6 pchan noiseless) +.model 10µA D(Ron=10 Roff=100 RevIlimit=10u epsilon=10m Vrev=0 ) +.model X D(Ron=1K Roff=1T epsilon=10m noiseless) +.model Vreg VDMOS(Kp=1 Vto=0 Ksubthres=10m noiseless) +.model REF VDMOS(Kp=1 Vto=-11.5m Ksubthres=10m noiseless) +.model 50µA SW(Ron=100 Roff=1T Ilimit=50u level=2 Vt=.5 Vh=-.1) +.model 100µA D(Ron=200 epsilon=50m Ilimit=100u noiseless) +.model EN SW(Ron=10 Roff=1T Vt=-.5 Vh=-.4) +.model PG SW(Ron=100 Roff=1G Vt=.5 Vh=-.4) +.model S D(Ron=.2 epsilon=.2) +.model 25mV D(Ron=1m Roff=1K Vfwd=25m epsilon=10m) +.ends ADP1765 +* +.subckt ADP7102 1 2 3 4 5 6 +M1 P N005 1 1 P temp=27 +A3 3 6 6 6 6 6 N009 6 SCHMITT Vt=1.175 Vh=45m Trise=160u Tfall=10u +C3 3 6 3p Rpar=10Meg +C4 1 6 10p +A4 6 N008 6 N009 6 6 EN 6 AND Tau=1u +D2 N011 N012 1µA +A7 6 N011 N015 N015 N015 N015 6 N015 VARISTOR table(0 0 1.22 {Vref}) +R6 N012 N015 100K +G1 6 N007 N002 N014 10µ +C7 N007 6 6p noiseless Rser=100k Rpar=100k +C8 2 6 1p Rpar=100Meg +C5 N011 6 474p +A2 1 6 6 6 6 6 N008 6 SCHMITT Vt=2.575 Vh=.125 +S4 6 N011 6 EN S +G3 1 6 1 6 table(5,18u,20,40u) +C11 5 6 10p +D3 N010 N005 X +C9 N010 1 100p Rpar=1K +D5 P 5 15mV +G2 N010 1 P 5 table(15.12m,1.196m, 16.79mm,1.2m,17.83m, 1.216m) +M3 6 N005 1 1 P2 +B3 5 6 I=V(EN,6)*table(V(P,5) ,15.2m,400u,15.7m,450u, 17.44m,650u,18.43m,700u) +M2 N001 N005 1 1 P m=20m temp=27 +R5 N001 5 10 +C2 N002 N001 25p +R7 2 N002 25K noiseless +R4 N014 N015 500K noiseless +C12 N014 6 250p +M4 N005 N005 P001 P001 P m=7.143m temp=27 +R8 P001 1 500K noiseless +A5 N006 N007 1 1 1 1 N005 1 OTA G=600u linear Iout=60u en=3u/freq**.44 Ref=-1.5m Rout=1Meg Vhigh=0 Vlow=-1.22 +S1 1 N005 6 EN S +C10 1 N006 10f +R2 6 N006 500K noiseless +B1 6 N012 I=1m*min(V(1,6),min({Vref+2.1},9.5)) Rpar=1k Cpar=3p +D4 6 5 S +S2 6 4 N019 6 PG +A1 N018 6 6 6 6 N019 6 6 SCHMITT Vt=.9215 Vh=13.5m Trise=50n +C13 4 6 2p Rpar=1G +B2 6 N018 I=IF(V(P,5)>19.2m,0,1m*V(2,6)/Vref) Rpar=1K Cpar=10p NoJacob +S3 N005 5 5 1 Rev +B4 1 6 I=table(V(1,5),-55m,.3u, 0, 0) +.model P VDMOS(mtriode=.6 Kp=15 Ksubthres=10m Lambda=.3 Vto=-1 Is=0 pchan) +.model P2 VDMOS( mtriode=.35 Kp=11 Ksubthres=10m Vto=-1.21 Is=0 pchan) +.model S SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4) +.model S D(Ron=10 Roff=1G epsilon=1) +.model 1µA D(Ron=400 Roff=400 RevIlimit=1u Vrev=0) +.model 15mV D(Ron=1m Roff=1K Vfwd=15m epsilon=20m) +.model X D(Ron=1K Roff=1T epsilon=10m) +.model PG SW(Ron=100 Roff=1G Vt=.75 Vh=-.23) +.model Rev SW(Ron=1 Roff=1T Vt=50m vh=-5m noiseless) +.ends ADP7102 +* +.subckt ADP7104 1 2 3 4 5 6 +M1 P N005 1 1 P temp=27 +A3 3 6 6 6 6 6 N009 6 SCHMITT Vt=1.175 Vh=45m Trise=160u Tfall=10u +C3 3 6 3p Rpar=10Meg +C4 1 6 10p +A4 6 N008 6 N009 6 6 EN 6 AND Tau=1u +D2 N011 N012 1µA +A7 6 N011 N015 N015 N015 N015 6 N015 VARISTOR table(0 0 1.22 {Vref}) +R6 N012 N015 100K +G1 6 N007 N002 N014 10µ +C7 N007 6 6p noiseless Rser=100k Rpar=100k +C8 2 6 1p Rpar=100Meg +C5 N011 6 758p +A2 1 6 6 6 6 6 N008 6 SCHMITT Vt=2.575 Vh=.125 +S4 6 N011 6 EN S +G3 1 6 1 6 table(5,18u,20,40u) +C11 5 6 10p +D3 N010 N005 X +C9 N010 1 100p Rpar=1K +D5 P 5 15mV m=2.5 +G2 N010 1 P 5 table(15.12m,1.196m,15.41mm, 1.198m, 16.79mm,1.2m,17.83m, 1.216m) +M3 6 N005 1 1 P2 +M2 N001 N005 1 1 P m=20m temp=27 +R5 N001 P 10 +C2 N002 N001 25p +R7 2 N002 25K noiseless +R4 N014 N015 500K noiseless +C12 N014 6 250p +M4 N005 N005 P001 P001 P m=7.143m temp=27 +R8 P001 1 500K noiseless +A5 N006 N007 1 1 1 1 N005 1 OTA G=600u Iout=60u en=3u/freq**.44 Ref=-1.5m Rout=1Meg Vhigh=0 Vlow=-1.22 +S1 1 N005 6 EN S +C10 1 N006 10f +R2 6 N006 500K noiseless +B1 6 N012 I=1m*min(V(1,6),min({Vref+2.1},9.5)) Rpar=1k Cpar=3p +D4 6 5 S +S2 6 4 N019 6 PG +A1 N018 6 6 6 6 N019 6 6 SCHMITT Vt=.9215 Vh=13.5m Trise=50n +C13 4 6 2p Rpar=1G +B2 6 N018 I=IF(V(P,5)>18.6m,0,1m*V(2,6)/{Vref}) Rpar=1K Cpar=10p NoJacob +S3 N005 5 5 1 Rev +B4 1 6 I=table(V(1,5),-55m,.3u, 0, 0) +B3 1 6 I=V(EN,6)*table(V(P,5) ,15.1m,400u, 15.4m,450u,17.19m,700u,17.83,800u) +.model P VDMOS(mtriode=.35 Kp=25 Ksubthres=10m Lambda=.3 Vto=-1 Is=0 Rd=30m pchan) +.model P2 VDMOS( mtriode=.35 Kp=11 Ksubthres=10m Vto=-1.21 Is=0 pchan) +.model S SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4) +.model S D(Ron=10 Roff=1G epsilon=1) +.model 1µA D(Ron=400 Roff=400 RevIlimit=1u Vrev=0) +.model 15mV D(Ron=1m Roff=1K Vfwd=15m epsilon=20m) +.model X D(Ron=1K Roff=1T epsilon=10m) +.model PG SW(Ron=100 Roff=1G Vt=.75 Vh=-.23) +.model Rev SW(Ron=1 Roff=1T Vt=50m vh=-5m noiseless) +.ends ADP7104 +* +.subckt ADP7105 1 2 3 4 5 6 7 +M1 P N005 1 1 P temp=27 +A3 3 6 6 6 6 6 N009 6 SCHMITT Vt=1.175 Vh=45m Trise=160u Tfall=10u +C3 3 6 3p Rpar=20Meg +C4 1 6 10p +A4 6 N008 6 N009 6 6 EN 6 AND Tau=1u +D2 4 N012 1µA +A7 6 4 N015 N015 N015 N015 6 N015 VARISTOR table(0 0 1.22 {Vref}) +R6 N012 N015 100K +G1 6 N007 N002 N014 10µ +C7 N007 6 6p noiseless Rser=100k Rpar=100k +C8 2 6 1p Rpar=100Meg +A2 1 6 6 6 6 6 N008 6 SCHMITT Vt=2.575 Vh=.125 +S4 6 4 6 EN S +G3 1 6 1 6 table(5,18u,20,40u) +C11 5 6 10p +D3 N010 N005 X +C9 N010 1 100p Rpar=1K +D5 P 5 15mV m=2.5 +G2 N010 1 P 5 table(15.12m,1.196m,15.41mm, 1.198m, 16.79mm,1.2m,17.83m, 1.216m) +M3 6 N005 1 1 P2 +B3 5 6 I=V(EN,6)*table(V(P,5) ,15.1m,400u, 15.4m,450u,17.19m,700u,17.83,800u) +M2 N001 N005 1 1 P m=20m temp=27 +R5 N001 P 10 +C2 N002 N001 25p +R7 2 N002 25K noiseless +R4 N014 N015 500K noiseless +C12 N014 6 250p +M4 N005 N005 P001 P001 P m=7.143m temp=27 +R8 P001 1 500K noiseless +A5 N006 N007 1 1 1 1 N005 1 OTA G=600u Iout=60u en=3u/freq**.44 Ref=-1.5m Rout=1Meg Vhigh=0 Vlow=-1.22 +S1 1 N005 6 EN S +C10 1 N006 10f +R2 6 N006 500K noiseless +B1 6 N012 I=1m*min(V(1,6),min({Vref+2.1},5.5)) Rpar=1k Cpar=3p +D4 6 5 S +S2 6 7 N019 6 PG +A1 N018 6 6 6 6 N019 6 6 SCHMITT Vt=.9215 Vh=13.5m Trise=50n +C13 7 6 2p Rpar=1G +B2 6 N018 I=IF(V(P,5)>18.6m,0,1m*V(2,6)/Vref) Rpar=1K Cpar=10p NoJacob +S3 N005 5 5 1 Rev +B4 1 6 I=table(V(1,5),-55m,.3u, 0, 0) +C6 4 6 10p +.model P VDMOS(mtriode=.35 Kp=25 Ksubthres=10m Lambda=.3 Vto=-1 Is=0 Rd=30m pchan) +.model P2 VDMOS( mtriode=.35 Kp=11 Ksubthres=10m Vto=-1.21 Is=0 pchan) +.model S SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4) +.model S D(Ron=10 Roff=1G epsilon=1) +.model 1µA D(Ron=400 Roff=400 RevIlimit=1u Vrev=0) +.model 15mV D(Ron=1m Roff=1K Vfwd=15m epsilon=20m) +.model X D(Ron=1K Roff=1T epsilon=10m) +.model PG SW(Ron=100 Roff=1G Vt=.75 Vh=-.23) +.model Rev SW(Ron=1 Roff=1T Vt=50m vh=-5m noiseless) +.ends ADP7105 +* +.subckt ADP7118 1 2 3 4 5 6 +M1 P N005 1 1 P temp=27 +A3 3 6 6 6 6 6 N009 6 SCHMITT Vt=1.17 Vh=50m Trise=160u Tfall=10u +C3 3 6 3p Rpar=20Meg +C4 1 6 10p +A4 6 N008 6 N009 6 6 EN 6 AND Tau=1u +D2 4 N012 1µA +A7 6 4 N014 N014 N014 N014 6 N014 VARISTOR table(0 0 .6 {Vref}) +R6 N012 N014 100K +G1 6 N007 N002 N013 10µ +C7 N007 6 6p noiseless Rser=100k Rpar=100k Cpar=1p +C8 2 6 1f noiseless Rpar=120Meg +C5 4 6 10p +A2 1 6 6 6 6 6 N008 6 SCHMITT Vt=2.315 Vh=.115 +S4 6 4 6 EN S +G3 1 6 1 6 table(5,1.8u,20,3u) +C11 5 6 10p +D3 N010 N005 X +C9 N010 1 100p Rpar=1K +D5 P 5 20mV +G2 N010 1 P 5 table(20.5m,1.19m,20.7m, 1.20m, 21.3m,1.206m, 22.5m,1.209m, 22.8m, 1.21m) +M3 6 N005 1 1 P2 +B3 5 6 I=V(EN,6)*table(V(P,5) ,20.1m,50u,20.6m,80u,22.9m,160u) +M2 N001 N005 1 1 P m=20m temp=27 +R5 N001 P 10 +C2 N002 N001 25p +R7 2 N002 25K noiseless +R4 N013 N014 500K noiseless +C12 N013 6 250p +M4 N005 N005 P001 P001 P m=7.143m temp=27 +R8 P001 1 500K noiseless +A5 N006 N007 1 1 1 1 N005 1 OTA G=200u Iout=20u en=1.5n+2.2u/freq**.44 Ref=-18.2m Rout=300k Cout=1p Vhigh=0 Vlow=-1.22 +S1 1 N005 6 EN S +C10 1 N006 1f +R2 6 N006 500K noiseless +B1 6 N012 I=1m*min(V(1,6),min({Vref+2.1},5.5)) Rpar=1k Cpar=3p +D4 6 5 S +.model P VDMOS(mtriode=.65 Kp=10 Ksubthres=10m Lambda=.08 Vto=-1 Is=0 pchan) +.model P2 VDMOS( Kp=1.5 Ksubthres=10m Vto=-1.19 Is=0 pchan) +.model S SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4) +.model S D(Ron=10 Roff=1G epsilon=1) +.model 1µA D(Ron=400 Roff=400 RevIlimit=1.15u Vrev=0) +.model 20mV D(Ron=1m Roff=1K Vfwd=20m epsilon=20m) +.model X D(Ron=1K Roff=1T epsilon=10m) +.ends ADP7118 diff --git a/spice/copy/sub/ADP7156-1.2.sub b/spice/copy/sub/ADP7156-1.2.sub new file mode 100755 index 0000000..221695f Binary files /dev/null and b/spice/copy/sub/ADP7156-1.2.sub differ diff --git a/spice/copy/sub/ADP7158_9.sub b/spice/copy/sub/ADP7158_9.sub new file mode 100755 index 0000000..81b4767 Binary files /dev/null and b/spice/copy/sub/ADP7158_9.sub differ diff --git a/spice/copy/sub/ADP7182.sub b/spice/copy/sub/ADP7182.sub new file mode 100755 index 0000000..e8d0b80 Binary files /dev/null and b/spice/copy/sub/ADP7182.sub differ diff --git a/spice/copy/sub/ADR.lib b/spice/copy/sub/ADR.lib new file mode 100755 index 0000000..0c017c0 --- /dev/null +++ b/spice/copy/sub/ADR.lib @@ -0,0 +1,87 @@ +* Copyright ? Analog Devices, Inc. 2019. All rights reserved. +* +.subckt AD590 1 2 +D1 N003 2 X N=2.3 +R2 N002 0 T 1 +I2 0 N002 .3002m +C1 1 N003 10p +C2 N003 2 10p +D2 2 1 S +D3 N003 1 Y +G1 1 N003 N002 0 1m +.model X D(Eg=1.4 Rs=2.5K) +.model Y D(Ron=1K Roff=1G Vfwd=-.1 epsilon=1 +.model S D(Ron=1 Roff=1T epsilon=1) +.model T R(R=1K tc1=0.003331667499583541) +.ends AD590 +* +.subckt ADR225 1 2 3 +C2 1 2 10p +C20 3 2 10p Rpar=250K +A1 N005 3 1 1 1 1 N006 1 OTA Ref=0 Rclamp=1Meg Vhigh=.5 Vlow=-.5 en=400n enk=10 Rout=400Meg epsilon=1 Iout=1u G=3u +M2 N003 N006 1 1 P temp=27 +D1 2 N006 X +A2 1 2 2 2 2 2 N005 2 SCHMITT Vhigh=2.5 Vt=2. Vh=1m Rout=250 Cout=1n +D2 2 3 S +R2 1 N005 10Meg +C3 1 N006 1p Rser=3Meg Cpar=.1p +D3 N003 3 1V +C4 N003 2 10p +.model P VDMOS(Kp=2 Vto=0 Ksubthres=100m pchan) +.model X D(Ron=1 Roff=1T epsilon=.5) +.model S D(Ron=1 Roff=1G epsilon=1) +.model 1V D(Ron=10 Roff=1G Vfwd=.8 epsilon=.1) +.ends ADR225 +* +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +.subckt ADR4525 1 2 3 +B1 N005 0 I=8.6u*(V(OUTS,GNDS)-2.4999998) +C1 N005 0 0.1f Rpar=100K noiseless +A1 N002 0 0 0 0 0 N003 0 OTA g=50u iout=200u Cout=5p Vhigh=1e308 Vlow=-1e308 +D1 N003 0 DLIM +C2 1 2 1000p +D2 1 2 DP +A2 0 N005 0 0 0 0 N002 0 OTA g=1m linear en=200n/(4*tanh(.35*freq)+900m*dnlim(freq-7.3k,1,1k)) Cout=5p Rout=1.5k Vlow=-1e308 Vhigh=1e308 +M1 OUTS N009 GNDS GNDS NI temp=27 +C4 1 OUTS .1p Rpar=100Meg noiseless +M2 OUTS N004 1 1 PI temp=27 +C5 OUTS 2 .1p Rpar=10Meg noiseless +M3 N004 N004 1 1 PI temp=27 M=10m +M4 N009 N009 2 2 NI temp=27 M=10m +A3 0 N006 1 1 1 1 N009 1 OTA g=1m asym isource=300u isink=-10u vlow=-1e308 vhigh=1e308 +D3 1 N004 DLIMP +C6 N003 N002 18p Rser=400k noiseless +C7 N003 N002 18.7p Rser=450k noiseless +C8 1 N004 1p +C9 N009 2 1p +R1 N008 2 100k noiseless +R2 GNDS 2 78m noiseless +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear Vlow=-1e308 Vhigh=1e308 +R3 3 OUTS 71.2m noiseless +A5 OUTS 3 0 0 0 0 N011 0 OTA g=1 asym ref=-400n isource=100n Isink=-80n Rout=1Meg Vlow=-1e308 Vhigh=1e308 +G2 0 VDO 3 1 38.5µ +A6 3 OUTS 0 0 0 0 VDO 0 OTA g=.7 asym isource=4.7u Isink=-.1u Vhigh=1e308 Vlow=-1e308 +D4 OUTS GNDS DIVOS +D5 N006 0 DNLG +G3 1 N005 1 2 21.5p +G4 0 VDO OUTS 3 .05 +G5 0 N003 VDO N011 10m vto=0 dir=1 +A7 0 N006 2 2 2 2 N004 2 OTA g=.5m asym isource=1u Isink=-400u in=5.5p/(0.8+2.5m*dnlim(freq-4.7k,1,3k)) Vlow=-1e308 Vhigh=1e308 +D6 N004 2 DIMIN +G6 0 VDO 3 1 10m vto=-510m dir=1 +C11 VDO 0 100f Rpar=20k noiseless +C12 GNDS 2 10p +G7 2 N005 N008 2 8n +C10 1 N008 400p Rser=50k Lser=3.2 Cpar=4f +.model DP D(Roff=1G Ron=100 Vfwd=.5 epsilon=.5 ilimit=484u noiseless) +.model PI VDMOS(Vto=-300m Kp=40m pchan Cgs=1f oneway) +.model NI VDMOS(Vto=300m Kp=40m Cgs=1f) +.model DLIM D(Ron=100 Roff=100Meg Vfwd=7 Vrev=3.5 epsilon=100m revepsilon=100m noiseless) +.model DNLG D(Ron=3Meg Roff=800k vfwd=50m epsilon=50m vrev=10m revepsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=3.5 epsilon=100m noiseless) +.model DIVOS D(Ron=1k Roff=1g vfwd=1 epsilon=1 ilimit=86u noiseless) +.model DIMIN D(Ron=100 Roff=1g vfwd=700m epsilon=700m ilimit=2.7u noiseless) +.ends ADR4525 + diff --git a/spice/copy/sub/ADR4525.sub b/spice/copy/sub/ADR4525.sub new file mode 100755 index 0000000..222ca1b Binary files /dev/null and b/spice/copy/sub/ADR4525.sub differ diff --git a/spice/copy/sub/ADR5040.sub b/spice/copy/sub/ADR5040.sub new file mode 100755 index 0000000..233ac59 Binary files /dev/null and b/spice/copy/sub/ADR5040.sub differ diff --git a/spice/copy/sub/ADuM4120xx.sub b/spice/copy/sub/ADuM4120xx.sub new file mode 100755 index 0000000..75c81a3 Binary files /dev/null and b/spice/copy/sub/ADuM4120xx.sub differ diff --git a/spice/copy/sub/ADuM4121xx.sub b/spice/copy/sub/ADuM4121xx.sub new file mode 100755 index 0000000..717bbbd Binary files /dev/null and b/spice/copy/sub/ADuM4121xx.sub differ diff --git a/spice/copy/sub/ADuM4122x.sub b/spice/copy/sub/ADuM4122x.sub new file mode 100755 index 0000000..84c9799 Binary files /dev/null and b/spice/copy/sub/ADuM4122x.sub differ diff --git a/spice/copy/sub/ADuM4135.sub b/spice/copy/sub/ADuM4135.sub new file mode 100755 index 0000000..247469f Binary files /dev/null and b/spice/copy/sub/ADuM4135.sub differ diff --git a/spice/copy/sub/ADuM4136.sub b/spice/copy/sub/ADuM4136.sub new file mode 100755 index 0000000..96f0f79 Binary files /dev/null and b/spice/copy/sub/ADuM4136.sub differ diff --git a/spice/copy/sub/CNY17.sub b/spice/copy/sub/CNY17.sub new file mode 100755 index 0000000..549015e --- /dev/null +++ b/spice/copy/sub/CNY17.sub @@ -0,0 +1,11 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000. All rights reserved. +* +.subckt CNY17 1 2 3 4 5 +R1 N003 2 2 +D1 1 N003 LD +G1 3 5 N003 2 {Igain} +C1 1 2 18p +Q1 3 5 4 [4] NP +.model LD D(Is=1e-20 Cjo=18p) +.model NP NPN(Bf=610 Vaf=140 Ikf=15m Rc=1 Cjc=19p Cje=7p Cjs=7p C2=1e-15) +.ends CNY17 diff --git a/spice/copy/sub/Contrib/Toshiba/nmos/2SK1828.lib b/spice/copy/sub/Contrib/Toshiba/nmos/2SK1828.lib new file mode 100755 index 0000000..ec297f3 Binary files /dev/null and b/spice/copy/sub/Contrib/Toshiba/nmos/2SK1828.lib differ diff --git a/spice/copy/sub/Contrib/Toshiba/nmos/2SK2009.lib b/spice/copy/sub/Contrib/Toshiba/nmos/2SK2009.lib new file mode 100755 index 0000000..dcf9f6e Binary files /dev/null and b/spice/copy/sub/Contrib/Toshiba/nmos/2SK2009.lib differ diff --git a/spice/copy/sub/Contrib/Toshiba/nmos/2SK2313.lib b/spice/copy/sub/Contrib/Toshiba/nmos/2SK2313.lib new file mode 100755 index 0000000..1dd94e8 Binary files /dev/null and b/spice/copy/sub/Contrib/Toshiba/nmos/2SK2313.lib differ diff --git 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a/spice/copy/sub/Contrib/Toshiba/pmos/TPH1R712MD.lib b/spice/copy/sub/Contrib/Toshiba/pmos/TPH1R712MD.lib new file mode 100755 index 0000000..ae867f1 Binary files /dev/null and b/spice/copy/sub/Contrib/Toshiba/pmos/TPH1R712MD.lib differ diff --git a/spice/copy/sub/Contrib/Toshiba/pmos/TPN4R712MD.lib b/spice/copy/sub/Contrib/Toshiba/pmos/TPN4R712MD.lib new file mode 100755 index 0000000..66af071 Binary files /dev/null and b/spice/copy/sub/Contrib/Toshiba/pmos/TPN4R712MD.lib differ diff --git a/spice/copy/sub/Contrib/Wurth/WE-CCMF.lib b/spice/copy/sub/Contrib/Wurth/WE-CCMF.lib new file mode 100755 index 0000000..2bacb28 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CCMF.lib @@ -0,0 +1,1401 @@ +*$ +* BEGIN ANSOFT HEADER +* node 1 Port1 +* node 2 Port2 +* node 3 Port3 +* node 4 Port4 +* Project: Project1 +* Format: Spice +* Topckt: WE_CCMF_748020024 +* Date: Fri Oct 11 16:26:18 2019 +* Notes: Frequency range: 1.5e+007 to 1.5e+010 Hz, 1000 points +* : Maximum number of poles: 10000 +* : S-Matrix fitting error tolerance: 0.005 +* : Causality check tolerance: auto +* : Passivity enforcement: off +* : Causality enforcement: off +* : Fitting method: TWA +* : Matrix fitting: By entire matrix +* : Ensure Z-parameter accuracy: on +* : Relative error control: off +* : Common ground option: on +* : Final fitting error: 0.511468 +* : Final model order: 88 +* END ANSOFT HEADER + +.subckt WE_CCMF_748020024 1 2 3 4 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 + +Ca1 ns1 0 1e-012 +Ca2 ns2 0 1e-012 +Ra1 ns1 0 147.219400304 +Ra2 ns2 0 147.219400304 +Ga1 ns1 0 ns2 0 -0.00204136883855 +Ga2 ns2 0 ns1 0 0.00204136883855 +Ca3 ns3 0 1e-012 +Ca4 ns4 0 1e-012 +Ra3 ns3 0 229.546477593 +Ra4 ns4 0 229.546477593 +Ga3 ns3 0 ns4 0 -0.00836983773395 +Ga4 ns4 0 ns3 0 0.00836983773395 +Ca5 ns5 0 1e-012 +Ca6 ns6 0 1e-012 +Ra5 ns5 0 145.303135369 +Ra6 ns6 0 145.303135369 +Ga5 ns5 0 ns6 0 -0.0221791727372 +Ga6 ns6 0 ns5 0 0.0221791727372 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 125.51202363 +Ra8 ns8 0 125.51202363 +Ga7 ns7 0 ns8 0 -0.0390361561464 +Ga8 ns8 0 ns7 0 0.0390361561464 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 1099.82097604 +Ra10 ns10 0 1099.82097604 +Ga9 ns9 0 ns10 0 -0.0431338846321 +Ga10 ns10 0 ns9 0 0.0431338846321 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 89.6349355902 +Ra12 ns12 0 89.6349355902 +Ga11 ns11 0 ns12 0 -0.0527305240232 +Ga12 ns12 0 ns11 0 0.0527305240232 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 116.544388093 +Ra14 ns14 0 116.544388093 +Ga13 ns13 0 ns14 0 -0.0596819754204 +Ga14 ns14 0 ns13 0 0.0596819754204 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 157.874603033 +Ra16 ns16 0 157.874603033 +Ga15 ns15 0 ns16 0 -0.070138824588 +Ga16 ns16 0 ns15 0 0.070138824588 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 185.317195465 +Ra18 ns18 0 185.317195465 +Ga17 ns17 0 ns18 0 -0.073707531923 +Ga18 ns18 0 ns17 0 0.073707531923 +Ca19 ns19 0 1e-012 +Ca20 ns20 0 1e-012 +Ra19 ns19 0 138.938682675 +Ra20 ns20 0 138.938682675 +Ga19 ns19 0 ns20 0 -0.0818972981799 +Ga20 ns20 0 ns19 0 0.0818972981799 +Ca21 ns21 0 1e-012 +Ca22 ns22 0 1e-012 +Ra21 ns21 0 176.387891511 +Ra22 ns22 0 176.387891511 +Ga21 ns21 0 ns22 0 -0.0916634820428 +Ga22 ns22 0 ns21 0 0.0916634820428 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 147.219400304 +Ra24 ns24 0 147.219400304 +Ga23 ns23 0 ns24 0 -0.00204136883855 +Ga24 ns24 0 ns23 0 0.00204136883855 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 229.546477593 +Ra26 ns26 0 229.546477593 +Ga25 ns25 0 ns26 0 -0.00836983773395 +Ga26 ns26 0 ns25 0 0.00836983773395 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 145.303135369 +Ra28 ns28 0 145.303135369 +Ga27 ns27 0 ns28 0 -0.0221791727372 +Ga28 ns28 0 ns27 0 0.0221791727372 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 125.51202363 +Ra30 ns30 0 125.51202363 +Ga29 ns29 0 ns30 0 -0.0390361561464 +Ga30 ns30 0 ns29 0 0.0390361561464 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 1099.82097604 +Ra32 ns32 0 1099.82097604 +Ga31 ns31 0 ns32 0 -0.0431338846321 +Ga32 ns32 0 ns31 0 0.0431338846321 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 89.6349355902 +Ra34 ns34 0 89.6349355902 +Ga33 ns33 0 ns34 0 -0.0527305240232 +Ga34 ns34 0 ns33 0 0.0527305240232 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 116.544388093 +Ra36 ns36 0 116.544388093 +Ga35 ns35 0 ns36 0 -0.0596819754204 +Ga36 ns36 0 ns35 0 0.0596819754204 +Ca37 ns37 0 1e-012 +Ca38 ns38 0 1e-012 +Ra37 ns37 0 157.874603033 +Ra38 ns38 0 157.874603033 +Ga37 ns37 0 ns38 0 -0.070138824588 +Ga38 ns38 0 ns37 0 0.070138824588 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 185.317195465 +Ra40 ns40 0 185.317195465 +Ga39 ns39 0 ns40 0 -0.073707531923 +Ga40 ns40 0 ns39 0 0.073707531923 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 138.938682675 +Ra42 ns42 0 138.938682675 +Ga41 ns41 0 ns42 0 -0.0818972981799 +Ga42 ns42 0 ns41 0 0.0818972981799 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 176.387891511 +Ra44 ns44 0 176.387891511 +Ga43 ns43 0 ns44 0 -0.0916634820428 +Ga44 ns44 0 ns43 0 0.0916634820428 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 147.219400304 +Ra46 ns46 0 147.219400304 +Ga45 ns45 0 ns46 0 -0.00204136883855 +Ga46 ns46 0 ns45 0 0.00204136883855 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 229.546477593 +Ra48 ns48 0 229.546477593 +Ga47 ns47 0 ns48 0 -0.00836983773395 +Ga48 ns48 0 ns47 0 0.00836983773395 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 145.303135369 +Ra50 ns50 0 145.303135369 +Ga49 ns49 0 ns50 0 -0.0221791727372 +Ga50 ns50 0 ns49 0 0.0221791727372 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 125.51202363 +Ra52 ns52 0 125.51202363 +Ga51 ns51 0 ns52 0 -0.0390361561464 +Ga52 ns52 0 ns51 0 0.0390361561464 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 1099.82097604 +Ra54 ns54 0 1099.82097604 +Ga53 ns53 0 ns54 0 -0.0431338846321 +Ga54 ns54 0 ns53 0 0.0431338846321 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 89.6349355902 +Ra56 ns56 0 89.6349355902 +Ga55 ns55 0 ns56 0 -0.0527305240232 +Ga56 ns56 0 ns55 0 0.0527305240232 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 116.544388093 +Ra58 ns58 0 116.544388093 +Ga57 ns57 0 ns58 0 -0.0596819754204 +Ga58 ns58 0 ns57 0 0.0596819754204 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 157.874603033 +Ra60 ns60 0 157.874603033 +Ga59 ns59 0 ns60 0 -0.070138824588 +Ga60 ns60 0 ns59 0 0.070138824588 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 185.317195465 +Ra62 ns62 0 185.317195465 +Ga61 ns61 0 ns62 0 -0.073707531923 +Ga62 ns62 0 ns61 0 0.073707531923 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 138.938682675 +Ra64 ns64 0 138.938682675 +Ga63 ns63 0 ns64 0 -0.0818972981799 +Ga64 ns64 0 ns63 0 0.0818972981799 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 176.387891511 +Ra66 ns66 0 176.387891511 +Ga65 ns65 0 ns66 0 -0.0916634820428 +Ga66 ns66 0 ns65 0 0.0916634820428 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 147.219400304 +Ra68 ns68 0 147.219400304 +Ga67 ns67 0 ns68 0 -0.00204136883855 +Ga68 ns68 0 ns67 0 0.00204136883855 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 229.546477593 +Ra70 ns70 0 229.546477593 +Ga69 ns69 0 ns70 0 -0.00836983773395 +Ga70 ns70 0 ns69 0 0.00836983773395 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 145.303135369 +Ra72 ns72 0 145.303135369 +Ga71 ns71 0 ns72 0 -0.0221791727372 +Ga72 ns72 0 ns71 0 0.0221791727372 +Ca73 ns73 0 1e-012 +Ca74 ns74 0 1e-012 +Ra73 ns73 0 125.51202363 +Ra74 ns74 0 125.51202363 +Ga73 ns73 0 ns74 0 -0.0390361561464 +Ga74 ns74 0 ns73 0 0.0390361561464 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 1099.82097604 +Ra76 ns76 0 1099.82097604 +Ga75 ns75 0 ns76 0 -0.0431338846321 +Ga76 ns76 0 ns75 0 0.0431338846321 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 89.6349355902 +Ra78 ns78 0 89.6349355902 +Ga77 ns77 0 ns78 0 -0.0527305240232 +Ga78 ns78 0 ns77 0 0.0527305240232 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 116.544388093 +Ra80 ns80 0 116.544388093 +Ga79 ns79 0 ns80 0 -0.0596819754204 +Ga80 ns80 0 ns79 0 0.0596819754204 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 157.874603033 +Ra82 ns82 0 157.874603033 +Ga81 ns81 0 ns82 0 -0.070138824588 +Ga82 ns82 0 ns81 0 0.070138824588 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 185.317195465 +Ra84 ns84 0 185.317195465 +Ga83 ns83 0 ns84 0 -0.073707531923 +Ga84 ns84 0 ns83 0 0.073707531923 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 138.938682675 +Ra86 ns86 0 138.938682675 +Ga85 ns85 0 ns86 0 -0.0818972981799 +Ga86 ns86 0 ns85 0 0.0818972981799 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 176.387891511 +Ra88 ns88 0 176.387891511 +Ga87 ns87 0 ns88 0 -0.0916634820428 +Ga88 ns88 0 ns87 0 0.0916634820428 + +Gb1_1 ns1 0 ni1 0 0.00740607376079 +Gb3_1 ns3 0 ni1 0 0.0106373084965 +Gb5_1 ns5 0 ni1 0 0.0243146978621 +Gb7_1 ns7 0 ni1 0 0.0406623124611 +Gb9_1 ns9 0 ni1 0 0.0431530508946 +Gb11_1 ns11 0 ni1 0 0.0550909114427 +Gb13_1 ns13 0 ni1 0 0.060915574619 +Gb15_1 ns15 0 ni1 0 0.0707108521743 +Gb17_1 ns17 0 ni1 0 0.0741025861314 +Gb19_1 ns19 0 ni1 0 0.082529832467 +Gb21_1 ns21 0 ni1 0 0.0920141258003 +Gb23_2 ns23 0 ni2 0 0.00740607376079 +Gb25_2 ns25 0 ni2 0 0.0106373084965 +Gb27_2 ns27 0 ni2 0 0.0243146978621 +Gb29_2 ns29 0 ni2 0 0.0406623124611 +Gb31_2 ns31 0 ni2 0 0.0431530508946 +Gb33_2 ns33 0 ni2 0 0.0550909114427 +Gb35_2 ns35 0 ni2 0 0.060915574619 +Gb37_2 ns37 0 ni2 0 0.0707108521743 +Gb39_2 ns39 0 ni2 0 0.0741025861314 +Gb41_2 ns41 0 ni2 0 0.082529832467 +Gb43_2 ns43 0 ni2 0 0.0920141258003 +Gb45_3 ns45 0 ni3 0 0.00740607376079 +Gb47_3 ns47 0 ni3 0 0.0106373084965 +Gb49_3 ns49 0 ni3 0 0.0243146978621 +Gb51_3 ns51 0 ni3 0 0.0406623124611 +Gb53_3 ns53 0 ni3 0 0.0431530508946 +Gb55_3 ns55 0 ni3 0 0.0550909114427 +Gb57_3 ns57 0 ni3 0 0.060915574619 +Gb59_3 ns59 0 ni3 0 0.0707108521743 +Gb61_3 ns61 0 ni3 0 0.0741025861314 +Gb63_3 ns63 0 ni3 0 0.082529832467 +Gb65_3 ns65 0 ni3 0 0.0920141258003 +Gb67_4 ns67 0 ni4 0 0.00740607376079 +Gb69_4 ns69 0 ni4 0 0.0106373084965 +Gb71_4 ns71 0 ni4 0 0.0243146978621 +Gb73_4 ns73 0 ni4 0 0.0406623124611 +Gb75_4 ns75 0 ni4 0 0.0431530508946 +Gb77_4 ns77 0 ni4 0 0.0550909114427 +Gb79_4 ns79 0 ni4 0 0.060915574619 +Gb81_4 ns81 0 ni4 0 0.0707108521743 +Gb83_4 ns83 0 ni4 0 0.0741025861314 +Gb85_4 ns85 0 ni4 0 0.082529832467 +Gb87_4 ns87 0 ni4 0 0.0920141258003 + +Gc1_1 0 n2 ns1 0 -0.0481253057691 +Gc1_2 0 n2 ns2 0 -0.0596402932528 +Gc1_3 0 n2 ns3 0 0.00752736067566 +Gc1_4 0 n2 ns4 0 -0.0074084118514 +Gc1_5 0 n2 ns5 0 -0.0113650667706 +Gc1_6 0 n2 ns6 0 -0.00394231073944 +Gc1_7 0 n2 ns7 0 -0.00229949444909 +Gc1_8 0 n2 ns8 0 -0.00131757923003 +Gc1_9 0 n2 ns9 0 -9.84363258406e-005 +Gc1_10 0 n2 ns10 0 2.7523488714e-005 +Gc1_11 0 n2 ns11 0 -0.00627006930415 +Gc1_12 0 n2 ns12 0 0.00922495737249 +Gc1_13 0 n2 ns13 0 -0.0089975603813 +Gc1_14 0 n2 ns14 0 -0.00893855898535 +Gc1_15 0 n2 ns15 0 0.00152653865379 +Gc1_16 0 n2 ns16 0 -0.000819302602467 +Gc1_17 0 n2 ns17 0 -0.00167074451981 +Gc1_18 0 n2 ns18 0 -0.00285085644892 +Gc1_19 0 n2 ns19 0 6.67231332448e-006 +Gc1_20 0 n2 ns20 0 -0.00156451109989 +Gc1_21 0 n2 ns21 0 -0.000301226398416 +Gc1_22 0 n2 ns22 0 -0.000473910797718 +Gc1_23 0 n2 ns23 0 0.013609690519 +Gc1_24 0 n2 ns24 0 0.00463953759832 +Gc1_25 0 n2 ns25 0 0.00952180445444 +Gc1_26 0 n2 ns26 0 0.00394434388338 +Gc1_27 0 n2 ns27 0 0.00133507073509 +Gc1_28 0 n2 ns28 0 -0.000225883397833 +Gc1_29 0 n2 ns29 0 0.00383317429164 +Gc1_30 0 n2 ns30 0 0.00322223383552 +Gc1_31 0 n2 ns31 0 -4.22222627333e-005 +Gc1_32 0 n2 ns32 0 3.47366293412e-006 +Gc1_33 0 n2 ns33 0 -0.000728275696648 +Gc1_34 0 n2 ns34 0 -0.00660155748911 +Gc1_35 0 n2 ns35 0 0.00465981660769 +Gc1_36 0 n2 ns36 0 0.00329438818996 +Gc1_37 0 n2 ns37 0 0.00646348929953 +Gc1_38 0 n2 ns38 0 0.00218243712696 +Gc1_39 0 n2 ns39 0 -0.00388427613035 +Gc1_40 0 n2 ns40 0 0.00244625762359 +Gc1_41 0 n2 ns41 0 -0.000141670783265 +Gc1_42 0 n2 ns42 0 0.000739811499601 +Gc1_43 0 n2 ns43 0 -0.000837939513942 +Gc1_44 0 n2 ns44 0 0.00114455422267 +Gc1_45 0 n2 ns45 0 -0.00196742747959 +Gc1_46 0 n2 ns46 0 0.0128610310469 +Gc1_47 0 n2 ns47 0 0.00564334343304 +Gc1_48 0 n2 ns48 0 0.00915868592321 +Gc1_49 0 n2 ns49 0 0.0102118091476 +Gc1_50 0 n2 ns50 0 0.000634081855902 +Gc1_51 0 n2 ns51 0 -0.00167158094478 +Gc1_52 0 n2 ns52 0 -0.00314987499513 +Gc1_53 0 n2 ns53 0 6.45753418973e-005 +Gc1_54 0 n2 ns54 0 -2.17649889982e-005 +Gc1_55 0 n2 ns55 0 0.001506477089 +Gc1_56 0 n2 ns56 0 0.00215066248408 +Gc1_57 0 n2 ns57 0 0.00421891676213 +Gc1_58 0 n2 ns58 0 0.00492338744356 +Gc1_59 0 n2 ns59 0 -7.6953297705e-005 +Gc1_60 0 n2 ns60 0 0.00165850467171 +Gc1_61 0 n2 ns61 0 -0.00103416013108 +Gc1_62 0 n2 ns62 0 -0.00127534396565 +Gc1_63 0 n2 ns63 0 -0.00151261811196 +Gc1_64 0 n2 ns64 0 0.00123632577124 +Gc1_65 0 n2 ns65 0 -0.000312330103352 +Gc1_66 0 n2 ns66 0 0.000891567867762 +Gc1_67 0 n2 ns67 0 0.0143265553778 +Gc1_68 0 n2 ns68 0 0.00672122682366 +Gc1_69 0 n2 ns69 0 0.00872257514111 +Gc1_70 0 n2 ns70 0 0.00470395130504 +Gc1_71 0 n2 ns71 0 0.000660357112417 +Gc1_72 0 n2 ns72 0 -0.000293258802625 +Gc1_73 0 n2 ns73 0 0.00205256177245 +Gc1_74 0 n2 ns74 0 0.00278156027639 +Gc1_75 0 n2 ns75 0 5.73082404113e-005 +Gc1_76 0 n2 ns76 0 -1.02757589666e-005 +Gc1_77 0 n2 ns77 0 0.00465054778114 +Gc1_78 0 n2 ns78 0 0.00280033870859 +Gc1_79 0 n2 ns79 0 -0.00159970462656 +Gc1_80 0 n2 ns80 0 0.000268846819924 +Gc1_81 0 n2 ns81 0 0.000595336651121 +Gc1_82 0 n2 ns82 0 0.00281957549478 +Gc1_83 0 n2 ns83 0 -0.000911173414912 +Gc1_84 0 n2 ns84 0 5.67533191682e-005 +Gc1_85 0 n2 ns85 0 -0.000874289752461 +Gc1_86 0 n2 ns86 0 0.000760347075436 +Gc1_87 0 n2 ns87 0 0.000637887123607 +Gc1_88 0 n2 ns88 0 -0.000442499808627 +Gd1_1 0 n2 ni1 0 -0.0150756254366 +Gd1_2 0 n2 ni2 0 0.00896002734602 +Gd1_3 0 n2 ni3 0 0.00416062326128 +Gd1_4 0 n2 ni4 0 0.00473339222916 +Gc2_1 0 n4 ns1 0 0.0136664032411 +Gc2_2 0 n4 ns2 0 0.00467809277143 +Gc2_3 0 n4 ns3 0 0.00953608135482 +Gc2_4 0 n4 ns4 0 0.00395720732544 +Gc2_5 0 n4 ns5 0 0.00134689592354 +Gc2_6 0 n4 ns6 0 -0.000229067747563 +Gc2_7 0 n4 ns7 0 0.00385631604085 +Gc2_8 0 n4 ns8 0 0.00321956752141 +Gc2_9 0 n4 ns9 0 -4.21916697085e-005 +Gc2_10 0 n4 ns10 0 3.72864248341e-006 +Gc2_11 0 n4 ns11 0 -0.000690076685458 +Gc2_12 0 n4 ns12 0 -0.00657639840027 +Gc2_13 0 n4 ns13 0 0.00463850952013 +Gc2_14 0 n4 ns14 0 0.00331329739265 +Gc2_15 0 n4 ns15 0 0.00646727090811 +Gc2_16 0 n4 ns16 0 0.00218812473025 +Gc2_17 0 n4 ns17 0 -0.0038947492028 +Gc2_18 0 n4 ns18 0 0.00244900311738 +Gc2_19 0 n4 ns19 0 -0.000147966106615 +Gc2_20 0 n4 ns20 0 0.000736605599077 +Gc2_21 0 n4 ns21 0 -0.000840400081286 +Gc2_22 0 n4 ns22 0 0.00114493141547 +Gc2_23 0 n4 ns23 0 -0.0106144384664 +Gc2_24 0 n4 ns24 0 -0.00818390841432 +Gc2_25 0 n4 ns25 0 0.00752247639657 +Gc2_26 0 n4 ns26 0 0.00582850491057 +Gc2_27 0 n4 ns27 0 -0.012677754283 +Gc2_28 0 n4 ns28 0 0.000924385148274 +Gc2_29 0 n4 ns29 0 -0.00318885717456 +Gc2_30 0 n4 ns30 0 -0.00293100446684 +Gc2_31 0 n4 ns31 0 -5.45538625535e-005 +Gc2_32 0 n4 ns32 0 2.30789956037e-005 +Gc2_33 0 n4 ns33 0 0.000276674062965 +Gc2_34 0 n4 ns34 0 0.0042806831622 +Gc2_35 0 n4 ns35 0 -0.00669253260903 +Gc2_36 0 n4 ns36 0 -0.00387190752321 +Gc2_37 0 n4 ns37 0 0.00506361867839 +Gc2_38 0 n4 ns38 0 0.00293341899973 +Gc2_39 0 n4 ns39 0 -0.00439437950939 +Gc2_40 0 n4 ns40 0 -0.00200416960091 +Gc2_41 0 n4 ns41 0 -0.00215317507371 +Gc2_42 0 n4 ns42 0 -0.000696027398857 +Gc2_43 0 n4 ns43 0 -0.000360373647221 +Gc2_44 0 n4 ns44 0 -0.000282162140293 +Gc2_45 0 n4 ns45 0 0.0157058424033 +Gc2_46 0 n4 ns46 0 0.00723893927849 +Gc2_47 0 n4 ns47 0 0.00939294286136 +Gc2_48 0 n4 ns48 0 0.00476430115531 +Gc2_49 0 n4 ns49 0 0.00137748257137 +Gc2_50 0 n4 ns50 0 -0.000136708565665 +Gc2_51 0 n4 ns51 0 0.00195862100593 +Gc2_52 0 n4 ns52 0 0.00233201611015 +Gc2_53 0 n4 ns53 0 5.89774606979e-005 +Gc2_54 0 n4 ns54 0 -5.38910114983e-006 +Gc2_55 0 n4 ns55 0 0.00785317924429 +Gc2_56 0 n4 ns56 0 0.00137141626393 +Gc2_57 0 n4 ns57 0 -0.00183781862018 +Gc2_58 0 n4 ns58 0 0.00327684902246 +Gc2_59 0 n4 ns59 0 -0.000817102213878 +Gc2_60 0 n4 ns60 0 0.002484548931 +Gc2_61 0 n4 ns61 0 -0.000599552149635 +Gc2_62 0 n4 ns62 0 -0.000101247422086 +Gc2_63 0 n4 ns63 0 -0.000622289866519 +Gc2_64 0 n4 ns64 0 0.00089867139158 +Gc2_65 0 n4 ns65 0 0.000571158747285 +Gc2_66 0 n4 ns66 0 -1.58124096369e-006 +Gc2_67 0 n4 ns67 0 -0.00771495995578 +Gc2_68 0 n4 ns68 0 0.00709576434391 +Gc2_69 0 n4 ns69 0 0.00570531084256 +Gc2_70 0 n4 ns70 0 0.00686680319246 +Gc2_71 0 n4 ns71 0 0.00935082636571 +Gc2_72 0 n4 ns72 0 -0.00119010986338 +Gc2_73 0 n4 ns73 0 -0.00214316252798 +Gc2_74 0 n4 ns74 0 -0.00277305168909 +Gc2_75 0 n4 ns75 0 5.92832172229e-005 +Gc2_76 0 n4 ns76 0 -5.89156078934e-006 +Gc2_77 0 n4 ns77 0 0.00182273741779 +Gc2_78 0 n4 ns78 0 0.00244972210709 +Gc2_79 0 n4 ns79 0 0.00442159791602 +Gc2_80 0 n4 ns80 0 0.00347726587611 +Gc2_81 0 n4 ns81 0 -0.000863251301323 +Gc2_82 0 n4 ns82 0 0.00123163032798 +Gc2_83 0 n4 ns83 0 -0.000304664810963 +Gc2_84 0 n4 ns84 0 -0.00124519994314 +Gc2_85 0 n4 ns85 0 -0.000961311455468 +Gc2_86 0 n4 ns86 0 0.0024138910578 +Gc2_87 0 n4 ns87 0 -0.000379735007065 +Gc2_88 0 n4 ns88 0 0.000645563157363 +Gd2_1 0 n4 ni1 0 0.00896780307422 +Gd2_2 0 n4 ni2 0 -0.0135138846614 +Gd2_3 0 n4 ni3 0 0.0056307464846 +Gd2_4 0 n4 ni4 0 0.00340028157587 +Gc3_1 0 n6 ns1 0 -0.00186962065562 +Gc3_2 0 n6 ns2 0 0.012995147315 +Gc3_3 0 n6 ns3 0 0.00563645385865 +Gc3_4 0 n6 ns4 0 0.00918803373897 +Gc3_5 0 n6 ns5 0 0.0102356839252 +Gc3_6 0 n6 ns6 0 0.000641346414804 +Gc3_7 0 n6 ns7 0 -0.00166394043586 +Gc3_8 0 n6 ns8 0 -0.00314135823511 +Gc3_9 0 n6 ns9 0 6.48232574069e-005 +Gc3_10 0 n6 ns10 0 -2.17537763e-005 +Gc3_11 0 n6 ns11 0 0.00151485091789 +Gc3_12 0 n6 ns12 0 0.00215932416695 +Gc3_13 0 n6 ns13 0 0.00422645633363 +Gc3_14 0 n6 ns14 0 0.00495933686252 +Gc3_15 0 n6 ns15 0 -0.000102529392153 +Gc3_16 0 n6 ns16 0 0.0016750438224 +Gc3_17 0 n6 ns17 0 -0.00104015381635 +Gc3_18 0 n6 ns18 0 -0.00129399947062 +Gc3_19 0 n6 ns19 0 -0.00151729788745 +Gc3_20 0 n6 ns20 0 0.00123319887898 +Gc3_21 0 n6 ns21 0 -0.000311176068949 +Gc3_22 0 n6 ns22 0 0.00089065270453 +Gc3_23 0 n6 ns23 0 0.0156113065654 +Gc3_24 0 n6 ns24 0 0.00714358931567 +Gc3_25 0 n6 ns25 0 0.00939119240311 +Gc3_26 0 n6 ns26 0 0.00473753538432 +Gc3_27 0 n6 ns27 0 0.00136393937206 +Gc3_28 0 n6 ns28 0 -0.000141484188049 +Gc3_29 0 n6 ns29 0 0.00194427241002 +Gc3_30 0 n6 ns30 0 0.00232775040735 +Gc3_31 0 n6 ns31 0 5.90818106547e-005 +Gc3_32 0 n6 ns32 0 -5.34097690405e-006 +Gc3_33 0 n6 ns33 0 0.00784126007089 +Gc3_34 0 n6 ns34 0 0.00135899054272 +Gc3_35 0 n6 ns35 0 -0.00183705540269 +Gc3_36 0 n6 ns36 0 0.00327369167124 +Gc3_37 0 n6 ns37 0 -0.000823785381442 +Gc3_38 0 n6 ns38 0 0.00248720657534 +Gc3_39 0 n6 ns39 0 -0.000598023039958 +Gc3_40 0 n6 ns40 0 -0.000107654172629 +Gc3_41 0 n6 ns41 0 -0.00061898248816 +Gc3_42 0 n6 ns42 0 0.000892397014269 +Gc3_43 0 n6 ns43 0 0.000574020874682 +Gc3_44 0 n6 ns44 0 -2.64430416307e-006 +Gc3_45 0 n6 ns45 0 -0.0593383198323 +Gc3_46 0 n6 ns46 0 -0.0735828516722 +Gc3_47 0 n6 ns47 0 0.00622363336467 +Gc3_48 0 n6 ns48 0 -0.0130071314472 +Gc3_49 0 n6 ns49 0 -0.00995628444817 +Gc3_50 0 n6 ns50 0 -0.00605491706667 +Gc3_51 0 n6 ns51 0 -0.00102526907966 +Gc3_52 0 n6 ns52 0 4.06599683626e-005 +Gc3_53 0 n6 ns53 0 -8.87905359305e-005 +Gc3_54 0 n6 ns54 0 2.06682954552e-005 +Gc3_55 0 n6 ns55 0 -0.00317509459669 +Gc3_56 0 n6 ns56 0 0.00323250156007 +Gc3_57 0 n6 ns57 0 -0.00525374750053 +Gc3_58 0 n6 ns58 0 -0.00147598862992 +Gc3_59 0 n6 ns59 0 -0.00339118904103 +Gc3_60 0 n6 ns60 0 0.00291773911587 +Gc3_61 0 n6 ns61 0 -0.00115957912504 +Gc3_62 0 n6 ns62 0 -0.0033090322364 +Gc3_63 0 n6 ns63 0 -0.0010444280023 +Gc3_64 0 n6 ns64 0 -0.00273127822918 +Gc3_65 0 n6 ns65 0 -0.00107546381708 +Gc3_66 0 n6 ns66 0 -0.00136240183917 +Gc3_67 0 n6 ns67 0 0.0286948333406 +Gc3_68 0 n6 ns68 0 0.0268324979238 +Gc3_69 0 n6 ns69 0 0.00666047134928 +Gc3_70 0 n6 ns70 0 0.0111231854313 +Gc3_71 0 n6 ns71 0 -0.00268802713551 +Gc3_72 0 n6 ns72 0 0.0031470075387 +Gc3_73 0 n6 ns73 0 0.00128456529825 +Gc3_74 0 n6 ns74 0 0.00203281356196 +Gc3_75 0 n6 ns75 0 -4.59889921531e-005 +Gc3_76 0 n6 ns76 0 6.25999851261e-006 +Gc3_77 0 n6 ns77 0 -0.00275326905367 +Gc3_78 0 n6 ns78 0 -0.00424377561213 +Gc3_79 0 n6 ns79 0 0.00150842420655 +Gc3_80 0 n6 ns80 0 -0.000663267836694 +Gc3_81 0 n6 ns81 0 0.00251618399354 +Gc3_82 0 n6 ns82 0 -0.00138435567206 +Gc3_83 0 n6 ns83 0 0.00130824862215 +Gc3_84 0 n6 ns84 0 0.0025095494155 +Gc3_85 0 n6 ns85 0 0.0012845457475 +Gc3_86 0 n6 ns86 0 0.000462926036445 +Gc3_87 0 n6 ns87 0 -0.000705758174556 +Gc3_88 0 n6 ns88 0 0.00152099822198 +Gd3_1 0 n6 ni1 0 0.00415288714196 +Gd3_2 0 n6 ni2 0 0.00561741499607 +Gd3_3 0 n6 ni3 0 -0.0178815190119 +Gd3_4 0 n6 ni4 0 0.00902490379672 +Gc4_1 0 n8 ns1 0 0.0144285582063 +Gc4_2 0 n8 ns2 0 0.00682394470379 +Gc4_3 0 n8 ns3 0 0.00873922939655 +Gc4_4 0 n8 ns4 0 0.00473349748016 +Gc4_5 0 n8 ns5 0 0.000669887449411 +Gc4_6 0 n8 ns6 0 -0.0002870801197 +Gc4_7 0 n8 ns7 0 0.00207630136286 +Gc4_8 0 n8 ns8 0 0.00280102908977 +Gc4_9 0 n8 ns9 0 5.72424579871e-005 +Gc4_10 0 n8 ns10 0 -1.01552806319e-005 +Gc4_11 0 n8 ns11 0 0.00465884824921 +Gc4_12 0 n8 ns12 0 0.00283977755579 +Gc4_13 0 n8 ns13 0 -0.00162372104665 +Gc4_14 0 n8 ns14 0 0.00026550482306 +Gc4_15 0 n8 ns15 0 0.000596953459254 +Gc4_16 0 n8 ns16 0 0.00283885421187 +Gc4_17 0 n8 ns17 0 -0.000919828419142 +Gc4_18 0 n8 ns18 0 4.78347385061e-005 +Gc4_19 0 n8 ns19 0 -0.000878261185386 +Gc4_20 0 n8 ns20 0 0.000758560274352 +Gc4_21 0 n8 ns21 0 0.000637116922194 +Gc4_22 0 n8 ns22 0 -0.000450429971812 +Gc4_23 0 n8 ns23 0 -0.00780074486337 +Gc4_24 0 n8 ns24 0 0.00696197514461 +Gc4_25 0 n8 ns25 0 0.00571476170245 +Gc4_26 0 n8 ns26 0 0.00685423150301 +Gc4_27 0 n8 ns27 0 0.00935478104232 +Gc4_28 0 n8 ns28 0 -0.00120210343955 +Gc4_29 0 n8 ns29 0 -0.00215374306384 +Gc4_30 0 n8 ns30 0 -0.0027767336754 +Gc4_31 0 n8 ns31 0 5.95976813689e-005 +Gc4_32 0 n8 ns32 0 -6.0584804425e-006 +Gc4_33 0 n8 ns33 0 0.00182600250151 +Gc4_34 0 n8 ns34 0 0.00246507442796 +Gc4_35 0 n8 ns35 0 0.00442303691073 +Gc4_36 0 n8 ns36 0 0.00346857391896 +Gc4_37 0 n8 ns37 0 -0.000876197517794 +Gc4_38 0 n8 ns38 0 0.00123412447969 +Gc4_39 0 n8 ns39 0 -0.000302941381168 +Gc4_40 0 n8 ns40 0 -0.00125495597139 +Gc4_41 0 n8 ns41 0 -0.000955712963674 +Gc4_42 0 n8 ns42 0 0.00241774336134 +Gc4_43 0 n8 ns43 0 -0.000377749171731 +Gc4_44 0 n8 ns44 0 0.0006457138437 +Gc4_45 0 n8 ns45 0 0.0286976450791 +Gc4_46 0 n8 ns46 0 0.0268259853463 +Gc4_47 0 n8 ns47 0 0.00666906797481 +Gc4_48 0 n8 ns48 0 0.0111247571811 +Gc4_49 0 n8 ns49 0 -0.00268727380411 +Gc4_50 0 n8 ns50 0 0.00315199090889 +Gc4_51 0 n8 ns51 0 0.00129174333478 +Gc4_52 0 n8 ns52 0 0.00203871573561 +Gc4_53 0 n8 ns53 0 -4.6020247808e-005 +Gc4_54 0 n8 ns54 0 6.41465603227e-006 +Gc4_55 0 n8 ns55 0 -0.00277311464619 +Gc4_56 0 n8 ns56 0 -0.00421280410236 +Gc4_57 0 n8 ns57 0 0.00149744799758 +Gc4_58 0 n8 ns58 0 -0.000672982094246 +Gc4_59 0 n8 ns59 0 0.00250952235138 +Gc4_60 0 n8 ns60 0 -0.00138652910401 +Gc4_61 0 n8 ns61 0 0.00130991812408 +Gc4_62 0 n8 ns62 0 0.002503872233 +Gc4_63 0 n8 ns63 0 0.00128273049778 +Gc4_64 0 n8 ns64 0 0.000454602409393 +Gc4_65 0 n8 ns65 0 -0.000703784510173 +Gc4_66 0 n8 ns66 0 0.0015222456204 +Gc4_67 0 n8 ns67 0 -0.0364478084663 +Gc4_68 0 n8 ns68 0 -0.0425185168063 +Gc4_69 0 n8 ns69 0 0.00466461384306 +Gc4_70 0 n8 ns70 0 -0.00478771843757 +Gc4_71 0 n8 ns71 0 -0.0111793147288 +Gc4_72 0 n8 ns72 0 -0.00296016517041 +Gc4_73 0 n8 ns73 0 -0.00200233213205 +Gc4_74 0 n8 ns74 0 -0.0014011060539 +Gc4_75 0 n8 ns75 0 -7.9543820724e-005 +Gc4_76 0 n8 ns76 0 1.47684765654e-005 +Gc4_77 0 n8 ns77 0 -0.00019804760673 +Gc4_78 0 n8 ns78 0 0.000306421255309 +Gc4_79 0 n8 ns79 0 -0.00468232038902 +Gc4_80 0 n8 ns80 0 0.000430738353135 +Gc4_81 0 n8 ns81 0 -0.00113654214409 +Gc4_82 0 n8 ns82 0 0.0021601158761 +Gc4_83 0 n8 ns83 0 -0.000573907844554 +Gc4_84 0 n8 ns84 0 -0.00151345063785 +Gc4_85 0 n8 ns85 0 -0.00153726254936 +Gc4_86 0 n8 ns86 0 -0.00193858814605 +Gc4_87 0 n8 ns87 0 -0.000645229914007 +Gc4_88 0 n8 ns88 0 -0.00031302218305 +Gd4_1 0 n8 ni1 0 0.00472690430176 +Gd4_2 0 n8 ni2 0 0.00338809736277 +Gd4_3 0 n8 ni3 0 0.00901055490318 +Gd4_4 0 n8 ni4 0 -0.0156575865921 +.ends +*$ +* BEGIN ANSOFT HEADER +* node 1 Port1 +* node 2 Port2 +* node 3 Port3 +* node 4 Port4 +* Project: Project10 +* Format: PSpice +* Topckt: s748030024_sp +* Date: Fri Sep 11 16:42:50 2020 +* Notes: Frequency range: 1e+007 to 1e+010 Hz, 1000 points +* : Maximum number of poles: 10000 +* : S-Matrix fitting error tolerance: 0.005 +* : Causality check tolerance: auto +* : Passivity enforcement: off +* : Causality enforcement: off +* : Fitting method: TWA +* : Matrix fitting: By entire matrix +* : Ensure Z-parameter accuracy: on +* : Relative error control: off +* : Common ground option: on +* : Final fitting error: 0.103285 +* : Final model order: 40 +* END ANSOFT HEADER + +.subckt WE-CCMF_748030024 1 4 2 3 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 + +Ca1 ns1 0 1e-012 +Ca2 ns2 0 1e-012 +Ra1 ns1 0 196.057879393 +Ra2 ns2 0 196.057879393 +Ga1 ns1 0 ns2 0 -0.00906136858812 +Ga2 ns2 0 ns1 0 0.00906136858812 +Ca3 ns3 0 1e-012 +Ca4 ns4 0 1e-012 +Ra3 ns3 0 70.5014537058 +Ra4 ns4 0 70.5014537058 +Ga3 ns3 0 ns4 0 -0.0196146706844 +Ga4 ns4 0 ns3 0 0.0196146706844 +Ca5 ns5 0 1e-012 +Ca6 ns6 0 1e-012 +Ra5 ns5 0 79.3029027028 +Ra6 ns6 0 79.3029027028 +Ga5 ns5 0 ns6 0 -0.0395669021713 +Ga6 ns6 0 ns5 0 0.0395669021713 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 1026.61532806 +Ra8 ns8 0 1026.61532806 +Ga7 ns7 0 ns8 0 -0.0454193177237 +Ga8 ns8 0 ns7 0 0.0454193177237 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 92.1744418237 +Ra10 ns10 0 92.1744418237 +Ga9 ns9 0 ns10 0 -0.0571889056546 +Ga10 ns10 0 ns9 0 0.0571889056546 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 196.057879393 +Ra12 ns12 0 196.057879393 +Ga11 ns11 0 ns12 0 -0.00906136858812 +Ga12 ns12 0 ns11 0 0.00906136858812 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 70.5014537058 +Ra14 ns14 0 70.5014537058 +Ga13 ns13 0 ns14 0 -0.0196146706844 +Ga14 ns14 0 ns13 0 0.0196146706844 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 79.3029027028 +Ra16 ns16 0 79.3029027028 +Ga15 ns15 0 ns16 0 -0.0395669021713 +Ga16 ns16 0 ns15 0 0.0395669021713 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 1026.61532806 +Ra18 ns18 0 1026.61532806 +Ga17 ns17 0 ns18 0 -0.0454193177237 +Ga18 ns18 0 ns17 0 0.0454193177237 +Ca19 ns19 0 1e-012 +Ca20 ns20 0 1e-012 +Ra19 ns19 0 92.1744418237 +Ra20 ns20 0 92.1744418237 +Ga19 ns19 0 ns20 0 -0.0571889056546 +Ga20 ns20 0 ns19 0 0.0571889056546 +Ca21 ns21 0 1e-012 +Ca22 ns22 0 1e-012 +Ra21 ns21 0 196.057879393 +Ra22 ns22 0 196.057879393 +Ga21 ns21 0 ns22 0 -0.00906136858812 +Ga22 ns22 0 ns21 0 0.00906136858812 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 70.5014537058 +Ra24 ns24 0 70.5014537058 +Ga23 ns23 0 ns24 0 -0.0196146706844 +Ga24 ns24 0 ns23 0 0.0196146706844 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 79.3029027028 +Ra26 ns26 0 79.3029027028 +Ga25 ns25 0 ns26 0 -0.0395669021713 +Ga26 ns26 0 ns25 0 0.0395669021713 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 1026.61532806 +Ra28 ns28 0 1026.61532806 +Ga27 ns27 0 ns28 0 -0.0454193177237 +Ga28 ns28 0 ns27 0 0.0454193177237 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 92.1744418237 +Ra30 ns30 0 92.1744418237 +Ga29 ns29 0 ns30 0 -0.0571889056546 +Ga30 ns30 0 ns29 0 0.0571889056546 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 196.057879393 +Ra32 ns32 0 196.057879393 +Ga31 ns31 0 ns32 0 -0.00906136858812 +Ga32 ns32 0 ns31 0 0.00906136858812 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 70.5014537058 +Ra34 ns34 0 70.5014537058 +Ga33 ns33 0 ns34 0 -0.0196146706844 +Ga34 ns34 0 ns33 0 0.0196146706844 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 79.3029027028 +Ra36 ns36 0 79.3029027028 +Ga35 ns35 0 ns36 0 -0.0395669021713 +Ga36 ns36 0 ns35 0 0.0395669021713 +Ca37 ns37 0 1e-012 +Ca38 ns38 0 1e-012 +Ra37 ns37 0 1026.61532806 +Ra38 ns38 0 1026.61532806 +Ga37 ns37 0 ns38 0 -0.0454193177237 +Ga38 ns38 0 ns37 0 0.0454193177237 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 92.1744418237 +Ra40 ns40 0 92.1744418237 +Ga39 ns39 0 ns40 0 -0.0571889056546 +Ga40 ns40 0 ns39 0 0.0571889056546 + +Gb1_1 ns1 0 ni1 0 0.0119323977363 +Gb3_1 ns3 0 ni1 0 0.0298717292417 +Gb5_1 ns5 0 ni1 0 0.0435856409986 +Gb7_1 ns7 0 ni1 0 0.0454402079866 +Gb9_1 ns9 0 ni1 0 0.0592470090122 +Gb11_2 ns11 0 ni2 0 0.0119323977363 +Gb13_2 ns13 0 ni2 0 0.0298717292417 +Gb15_2 ns15 0 ni2 0 0.0435856409986 +Gb17_2 ns17 0 ni2 0 0.0454402079866 +Gb19_2 ns19 0 ni2 0 0.0592470090122 +Gb21_3 ns21 0 ni3 0 0.0119323977363 +Gb23_3 ns23 0 ni3 0 0.0298717292417 +Gb25_3 ns25 0 ni3 0 0.0435856409986 +Gb27_3 ns27 0 ni3 0 0.0454402079866 +Gb29_3 ns29 0 ni3 0 0.0592470090122 +Gb31_4 ns31 0 ni4 0 0.0119323977363 +Gb33_4 ns33 0 ni4 0 0.0298717292417 +Gb35_4 ns35 0 ni4 0 0.0435856409986 +Gb37_4 ns37 0 ni4 0 0.0454402079866 +Gb39_4 ns39 0 ni4 0 0.0592470090122 + +Gc1_1 0 n2 ns1 0 0.00827443729507 +Gc1_2 0 n2 ns2 0 0.0105718336197 +Gc1_3 0 n2 ns3 0 -0.0323946448638 +Gc1_4 0 n2 ns4 0 -0.00718530743036 +Gc1_5 0 n2 ns5 0 -0.00419651931046 +Gc1_6 0 n2 ns6 0 -0.00822873441929 +Gc1_7 0 n2 ns7 0 -0.000140439367629 +Gc1_8 0 n2 ns8 0 -3.752946839e-005 +Gc1_9 0 n2 ns9 0 -0.00196066161788 +Gc1_10 0 n2 ns10 0 -0.00603064793702 +Gc1_11 0 n2 ns11 0 0.0113325377752 +Gc1_12 0 n2 ns12 0 0.00497408047365 +Gc1_13 0 n2 ns13 0 0.0263499247867 +Gc1_14 0 n2 ns14 0 0.0237011826153 +Gc1_15 0 n2 ns15 0 -0.00737057980628 +Gc1_16 0 n2 ns16 0 -0.000681869297365 +Gc1_17 0 n2 ns17 0 8.57208996725e-005 +Gc1_18 0 n2 ns18 0 -8.33302599927e-005 +Gc1_19 0 n2 ns19 0 0.00122002123692 +Gc1_20 0 n2 ns20 0 0.00837023740702 +Gc1_21 0 n2 ns21 0 0.00723557696477 +Gc1_22 0 n2 ns22 0 -0.00116630801645 +Gc1_23 0 n2 ns23 0 0.00399502765434 +Gc1_24 0 n2 ns24 0 -0.00612216175079 +Gc1_25 0 n2 ns25 0 0.00933127770103 +Gc1_26 0 n2 ns26 0 0.0082691455855 +Gc1_27 0 n2 ns27 0 -0.000120144268182 +Gc1_28 0 n2 ns28 0 -3.1122260051e-006 +Gc1_29 0 n2 ns29 0 -0.00394634455854 +Gc1_30 0 n2 ns30 0 0.00293682501457 +Gc1_31 0 n2 ns31 0 0.00694367216828 +Gc1_32 0 n2 ns32 0 0.00265569737877 +Gc1_33 0 n2 ns33 0 -0.00804012167287 +Gc1_34 0 n2 ns34 0 -0.00432511407254 +Gc1_35 0 n2 ns35 0 -0.0053690041341 +Gc1_36 0 n2 ns36 0 0.00415473345791 +Gc1_37 0 n2 ns37 0 9.70814628266e-005 +Gc1_38 0 n2 ns38 0 -7.62743134284e-005 +Gc1_39 0 n2 ns39 0 0.000335618969677 +Gc1_40 0 n2 ns40 0 -0.00486871534518 +Gd1_1 0 n2 ni1 0 -0.0100802409167 +Gd1_2 0 n2 ni2 0 0.00687313331598 +Gd1_3 0 n2 ni3 0 0.00621711894339 +Gd1_4 0 n2 ni4 0 -0.000595936200015 +Gc2_1 0 n4 ns1 0 0.0113380109753 +Gc2_2 0 n4 ns2 0 0.00497028772114 +Gc2_3 0 n4 ns3 0 0.0263646454212 +Gc2_4 0 n4 ns4 0 0.0237198781733 +Gc2_5 0 n4 ns5 0 -0.00737065468879 +Gc2_6 0 n4 ns6 0 -0.000675192036592 +Gc2_7 0 n4 ns7 0 8.57545126957e-005 +Gc2_8 0 n4 ns8 0 -8.3297773122e-005 +Gc2_9 0 n4 ns9 0 0.00120858217865 +Gc2_10 0 n4 ns10 0 0.00837115636756 +Gc2_11 0 n4 ns11 0 0.00663207917813 +Gc2_12 0 n4 ns12 0 0.0115899432883 +Gc2_13 0 n4 ns13 0 -0.0306550872591 +Gc2_14 0 n4 ns14 0 -0.00915755665949 +Gc2_15 0 n4 ns15 0 -0.00210709468849 +Gc2_16 0 n4 ns16 0 -0.0045579256312 +Gc2_17 0 n4 ns17 0 -2.48851721971e-005 +Gc2_18 0 n4 ns18 0 0.000116962968059 +Gc2_19 0 n4 ns19 0 -0.00429170931073 +Gc2_20 0 n4 ns20 0 -0.00475322685481 +Gc2_21 0 n4 ns21 0 0.00691286773885 +Gc2_22 0 n4 ns22 0 0.00188967359296 +Gc2_23 0 n4 ns23 0 -0.00552396242701 +Gc2_24 0 n4 ns24 0 -0.00433724262392 +Gc2_25 0 n4 ns25 0 -0.00345316616088 +Gc2_26 0 n4 ns26 0 0.00535839910392 +Gc2_27 0 n4 ns27 0 4.29796611488e-005 +Gc2_28 0 n4 ns28 0 -0.000156788745642 +Gc2_29 0 n4 ns29 0 8.96814739919e-005 +Gc2_30 0 n4 ns30 0 -0.003666101777 +Gc2_31 0 n4 ns31 0 0.00661461259806 +Gc2_32 0 n4 ns32 0 0.00339036658429 +Gc2_33 0 n4 ns33 0 -0.0111894139647 +Gc2_34 0 n4 ns34 0 -0.0091108117516 +Gc2_35 0 n4 ns35 0 0.00667329160307 +Gc2_36 0 n4 ns36 0 -0.00142363347024 +Gc2_37 0 n4 ns37 0 -8.63065743492e-006 +Gc2_38 0 n4 ns38 0 0.000142867677687 +Gc2_39 0 n4 ns39 0 -0.00147155197554 +Gc2_40 0 n4 ns40 0 0.000780425090323 +Gd2_1 0 n4 ni1 0 0.0068698602196 +Gd2_2 0 n4 ni2 0 -0.0137097166172 +Gd2_3 0 n4 ni3 0 0.000366457096238 +Gd2_4 0 n4 ni4 0 0.00413454492673 +Gc3_1 0 n6 ns1 0 0.00723702363545 +Gc3_2 0 n6 ns2 0 -0.00116651551077 +Gc3_3 0 n6 ns3 0 0.00400472148349 +Gc3_4 0 n6 ns4 0 -0.00612402588771 +Gc3_5 0 n6 ns5 0 0.00932933456373 +Gc3_6 0 n6 ns6 0 0.00827789796486 +Gc3_7 0 n6 ns7 0 -0.000120168291872 +Gc3_8 0 n6 ns8 0 -3.18385774536e-006 +Gc3_9 0 n6 ns9 0 -0.00394905804139 +Gc3_10 0 n6 ns10 0 0.00293291860988 +Gc3_11 0 n6 ns11 0 0.00691309255951 +Gc3_12 0 n6 ns12 0 0.00189008918035 +Gc3_13 0 n6 ns13 0 -0.00552897932507 +Gc3_14 0 n6 ns14 0 -0.00433367630973 +Gc3_15 0 n6 ns15 0 -0.00345833091311 +Gc3_16 0 n6 ns16 0 0.00535334789308 +Gc3_17 0 n6 ns17 0 4.3058244992e-005 +Gc3_18 0 n6 ns18 0 -0.000156736895102 +Gc3_19 0 n6 ns19 0 9.06541482853e-005 +Gc3_20 0 n6 ns20 0 -0.00366805524891 +Gc3_21 0 n6 ns21 0 0.00925928276806 +Gc3_22 0 n6 ns22 0 0.00798688152503 +Gc3_23 0 n6 ns23 0 -0.0267660774488 +Gc3_24 0 n6 ns24 0 -0.00626601080631 +Gc3_25 0 n6 ns25 0 -0.000731535965374 +Gc3_26 0 n6 ns26 0 -0.00755678039327 +Gc3_27 0 n6 ns27 0 -7.14582692204e-005 +Gc3_28 0 n6 ns28 0 9.77275536312e-005 +Gc3_29 0 n6 ns29 0 -0.000962988130602 +Gc3_30 0 n6 ns30 0 -0.00360234736809 +Gc3_31 0 n6 ns31 0 0.010107847264 +Gc3_32 0 n6 ns32 0 0.00604681261385 +Gc3_33 0 n6 ns33 0 0.0233830055275 +Gc3_34 0 n6 ns34 0 0.0204709428359 +Gc3_35 0 n6 ns35 0 -0.00817101531568 +Gc3_36 0 n6 ns36 0 -0.000380432515635 +Gc3_37 0 n6 ns37 0 6.16184411032e-005 +Gc3_38 0 n6 ns38 0 -9.21026281571e-005 +Gc3_39 0 n6 ns39 0 0.00180685160109 +Gc3_40 0 n6 ns40 0 0.00698324698169 +Gd3_1 0 n6 ni1 0 0.00622002817608 +Gd3_2 0 n6 ni2 0 0.000364039736222 +Gd3_3 0 n6 ni3 0 -0.00514400997755 +Gd3_4 0 n6 ni4 0 0.00588983758969 +Gc4_1 0 n8 ns1 0 0.00694689627469 +Gc4_2 0 n8 ns2 0 0.00265689347465 +Gc4_3 0 n8 ns3 0 -0.00803344246832 +Gc4_4 0 n8 ns4 0 -0.00432999632276 +Gc4_5 0 n8 ns5 0 -0.00537272303639 +Gc4_6 0 n8 ns6 0 0.00415273631928 +Gc4_7 0 n8 ns7 0 9.71351160062e-005 +Gc4_8 0 n8 ns8 0 -7.62116131592e-005 +Gc4_9 0 n8 ns9 0 0.00034275029589 +Gc4_10 0 n8 ns10 0 -0.00486784018089 +Gc4_11 0 n8 ns11 0 0.00661931058903 +Gc4_12 0 n8 ns12 0 0.00338708607407 +Gc4_13 0 n8 ns13 0 -0.0111789850537 +Gc4_14 0 n8 ns14 0 -0.00910992558827 +Gc4_15 0 n8 ns15 0 0.0066775161667 +Gc4_16 0 n8 ns16 0 -0.00141874190069 +Gc4_17 0 n8 ns17 0 -8.81622854197e-006 +Gc4_18 0 n8 ns18 0 0.000142906639511 +Gc4_19 0 n8 ns19 0 -0.001471051705 +Gc4_20 0 n8 ns20 0 0.000781571676441 +Gc4_21 0 n8 ns21 0 0.0101013043623 +Gc4_22 0 n8 ns22 0 0.00604916509816 +Gc4_23 0 n8 ns23 0 0.0233762728652 +Gc4_24 0 n8 ns24 0 0.0204745521727 +Gc4_25 0 n8 ns25 0 -0.00818165570166 +Gc4_26 0 n8 ns26 0 -0.000384183271732 +Gc4_27 0 n8 ns27 0 6.15307217012e-005 +Gc4_28 0 n8 ns28 0 -9.22461011585e-005 +Gc4_29 0 n8 ns29 0 0.00180296760161 +Gc4_30 0 n8 ns30 0 0.00697690485047 +Gc4_31 0 n8 ns31 0 0.00903248244643 +Gc4_32 0 n8 ns32 0 0.0102721086863 +Gc4_33 0 n8 ns33 0 -0.0263918555748 +Gc4_34 0 n8 ns34 0 -0.00862179791354 +Gc4_35 0 n8 ns35 0 0.00175901038286 +Gc4_36 0 n8 ns36 0 -0.00316796870082 +Gc4_37 0 n8 ns37 0 -7.0714788761e-005 +Gc4_38 0 n8 ns38 0 0.000143225005806 +Gc4_39 0 n8 ns39 0 -0.00420755894251 +Gc4_40 0 n8 ns40 0 -0.00222812858356 +Gd4_1 0 n8 ni1 0 -0.000584932757019 +Gd4_2 0 n8 ni2 0 0.00414273895197 +Gd4_3 0 n8 ni3 0 0.00588036864334 +Gd4_4 0 n8 ni4 0 -0.0100504535737 +.ends +*$ +* BEGIN ANSOFT HEADER +* node 1 Port1 +* node 2 Port2 +* node 3 Port3 +* node 4 Port4 +* Project: Project10 +* Format: PSpice +* Topckt: s748032455_sp +* Date: Fri Sep 11 16:44:16 2020 +* Notes: Frequency range: 1e+007 to 1e+010 Hz, 1000 points +* : Maximum number of poles: 10000 +* : S-Matrix fitting error tolerance: 0.005 +* : Causality check tolerance: auto +* : Passivity enforcement: off +* : Causality enforcement: off +* : Fitting method: TWA +* : Matrix fitting: By entire matrix +* : Ensure Z-parameter accuracy: on +* : Relative error control: off +* : Common ground option: on +* : Final fitting error: 0.147149 +* : Final model order: 32 +* END ANSOFT HEADER + +.subckt WE-CCMF_748032455 1 4 2 3 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 + +Ca1 ns1 0 1e-012 +Ca2 ns2 0 1e-012 +Ra1 ns1 0 137.905263418 +Ra2 ns2 0 137.905263418 +Ga1 ns1 0 ns2 0 -0.0114719812296 +Ga2 ns2 0 ns1 0 0.0114719812296 +Ca3 ns3 0 1e-012 +Ca4 ns4 0 1e-012 +Ra3 ns3 0 72.7955566495 +Ra4 ns4 0 72.7955566495 +Ga3 ns3 0 ns4 0 -0.0264867147809 +Ga4 ns4 0 ns3 0 0.0264867147809 +Ca5 ns5 0 1e-012 +Ca6 ns6 0 1e-012 +Ra5 ns5 0 131.988444403 +Ra6 ns6 0 131.988444403 +Ga5 ns5 0 ns6 0 -0.0412398646493 +Ga6 ns6 0 ns5 0 0.0412398646493 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 73.6333491313 +Ra8 ns8 0 73.6333491313 +Ga7 ns7 0 ns8 0 -0.057905345779 +Ga8 ns8 0 ns7 0 0.057905345779 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 137.905263418 +Ra10 ns10 0 137.905263418 +Ga9 ns9 0 ns10 0 -0.0114719812296 +Ga10 ns10 0 ns9 0 0.0114719812296 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 72.7955566495 +Ra12 ns12 0 72.7955566495 +Ga11 ns11 0 ns12 0 -0.0264867147809 +Ga12 ns12 0 ns11 0 0.0264867147809 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 131.988444403 +Ra14 ns14 0 131.988444403 +Ga13 ns13 0 ns14 0 -0.0412398646493 +Ga14 ns14 0 ns13 0 0.0412398646493 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 73.6333491313 +Ra16 ns16 0 73.6333491313 +Ga15 ns15 0 ns16 0 -0.057905345779 +Ga16 ns16 0 ns15 0 0.057905345779 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 137.905263418 +Ra18 ns18 0 137.905263418 +Ga17 ns17 0 ns18 0 -0.0114719812296 +Ga18 ns18 0 ns17 0 0.0114719812296 +Ca19 ns19 0 1e-012 +Ca20 ns20 0 1e-012 +Ra19 ns19 0 72.7955566495 +Ra20 ns20 0 72.7955566495 +Ga19 ns19 0 ns20 0 -0.0264867147809 +Ga20 ns20 0 ns19 0 0.0264867147809 +Ca21 ns21 0 1e-012 +Ca22 ns22 0 1e-012 +Ra21 ns21 0 131.988444403 +Ra22 ns22 0 131.988444403 +Ga21 ns21 0 ns22 0 -0.0412398646493 +Ga22 ns22 0 ns21 0 0.0412398646493 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 73.6333491313 +Ra24 ns24 0 73.6333491313 +Ga23 ns23 0 ns24 0 -0.057905345779 +Ga24 ns24 0 ns23 0 0.057905345779 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 137.905263418 +Ra26 ns26 0 137.905263418 +Ga25 ns25 0 ns26 0 -0.0114719812296 +Ga26 ns26 0 ns25 0 0.0114719812296 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 72.7955566495 +Ra28 ns28 0 72.7955566495 +Ga27 ns27 0 ns28 0 -0.0264867147809 +Ga28 ns28 0 ns27 0 0.0264867147809 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 131.988444403 +Ra30 ns30 0 131.988444403 +Ga29 ns29 0 ns30 0 -0.0412398646493 +Ga30 ns30 0 ns29 0 0.0412398646493 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 73.6333491313 +Ra32 ns32 0 73.6333491313 +Ga31 ns31 0 ns32 0 -0.057905345779 +Ga32 ns32 0 ns31 0 0.057905345779 + +Gb1_1 ns1 0 ni1 0 0.0160555092211 +Gb3_1 ns3 0 ni1 0 0.0336113422738 +Gb5_1 ns5 0 ni1 0 0.042631773986 +Gb7_1 ns7 0 ni1 0 0.0610905129583 +Gb9_2 ns9 0 ni2 0 0.0160555092211 +Gb11_2 ns11 0 ni2 0 0.0336113422738 +Gb13_2 ns13 0 ni2 0 0.042631773986 +Gb15_2 ns15 0 ni2 0 0.0610905129583 +Gb17_3 ns17 0 ni3 0 0.0160555092211 +Gb19_3 ns19 0 ni3 0 0.0336113422738 +Gb21_3 ns21 0 ni3 0 0.042631773986 +Gb23_3 ns23 0 ni3 0 0.0610905129583 +Gb25_4 ns25 0 ni4 0 0.0160555092211 +Gb27_4 ns27 0 ni4 0 0.0336113422738 +Gb29_4 ns29 0 ni4 0 0.042631773986 +Gb31_4 ns31 0 ni4 0 0.0610905129583 + +Gc1_1 0 n2 ns1 0 0.0163759606718 +Gc1_2 0 n2 ns2 0 0.0060410177421 +Gc1_3 0 n2 ns3 0 -0.0101830953862 +Gc1_4 0 n2 ns4 0 -0.00303559015589 +Gc1_5 0 n2 ns5 0 0.010060807327 +Gc1_6 0 n2 ns6 0 0.0017993618469 +Gc1_7 0 n2 ns7 0 -0.00542107660207 +Gc1_8 0 n2 ns8 0 0.00468072312836 +Gc1_9 0 n2 ns9 0 0.0165104213982 +Gc1_10 0 n2 ns10 0 0.00654394319145 +Gc1_11 0 n2 ns11 0 0.020655294427 +Gc1_12 0 n2 ns12 0 0.018282647217 +Gc1_13 0 n2 ns13 0 0.000744429962273 +Gc1_14 0 n2 ns14 0 0.00263565251694 +Gc1_15 0 n2 ns15 0 -0.00915557648611 +Gc1_16 0 n2 ns16 0 0.00816361265957 +Gc1_17 0 n2 ns17 0 0.0120001260226 +Gc1_18 0 n2 ns18 0 -0.00334843428593 +Gc1_19 0 n2 ns19 0 -0.00320017453016 +Gc1_20 0 n2 ns20 0 2.74451083931e-005 +Gc1_21 0 n2 ns21 0 0.00630611970698 +Gc1_22 0 n2 ns22 0 -0.00168040769958 +Gc1_23 0 n2 ns23 0 0.00363593878528 +Gc1_24 0 n2 ns24 0 0.00425421977003 +Gc1_25 0 n2 ns25 0 0.0109754352364 +Gc1_26 0 n2 ns26 0 -0.00108363073468 +Gc1_27 0 n2 ns27 0 -0.00386092026955 +Gc1_28 0 n2 ns28 0 0.00169032348478 +Gc1_29 0 n2 ns29 0 0.000752020574444 +Gc1_30 0 n2 ns30 0 0.00162953486663 +Gc1_31 0 n2 ns31 0 0.00122842609369 +Gc1_32 0 n2 ns32 0 0.00294067903568 +Gd1_1 0 n2 ni1 0 -0.00181674046838 +Gd1_2 0 n2 ni2 0 0.00215954989418 +Gd1_3 0 n2 ni3 0 0.0099080886979 +Gd1_4 0 n2 ni4 0 0.00102517617064 +Gc2_1 0 n4 ns1 0 0.0165125021765 +Gc2_2 0 n4 ns2 0 0.00654680500644 +Gc2_3 0 n4 ns3 0 0.0206549268088 +Gc2_4 0 n4 ns4 0 0.0182861639603 +Gc2_5 0 n4 ns5 0 0.000742612114314 +Gc2_6 0 n4 ns6 0 0.0026353048325 +Gc2_7 0 n4 ns7 0 -0.00915834554232 +Gc2_8 0 n4 ns8 0 0.00816381131904 +Gc2_9 0 n4 ns9 0 0.0101119872239 +Gc2_10 0 n4 ns10 0 0.00938425794409 +Gc2_11 0 n4 ns11 0 -0.0243404447362 +Gc2_12 0 n4 ns12 0 0.0029808869958 +Gc2_13 0 n4 ns13 0 0.00158800156115 +Gc2_14 0 n4 ns14 0 -0.000367737162894 +Gc2_15 0 n4 ns15 0 -0.00590687749443 +Gc2_16 0 n4 ns16 0 -0.00415251659627 +Gc2_17 0 n4 ns17 0 0.0113669879357 +Gc2_18 0 n4 ns18 0 -0.00209134392696 +Gc2_19 0 n4 ns19 0 -0.00115303184172 +Gc2_20 0 n4 ns20 0 0.000805574050304 +Gc2_21 0 n4 ns21 0 0.0021481817679 +Gc2_22 0 n4 ns22 0 0.00214376550053 +Gc2_23 0 n4 ns23 0 0.00168255672679 +Gc2_24 0 n4 ns24 0 0.0047483340738 +Gc2_25 0 n4 ns25 0 0.00748645292094 +Gc2_26 0 n4 ns26 0 0.00223920691868 +Gc2_27 0 n4 ns27 0 -0.0135430791358 +Gc2_28 0 n4 ns28 0 0.0007503523917 +Gc2_29 0 n4 ns29 0 0.0012937396973 +Gc2_30 0 n4 ns30 0 0.000937412610374 +Gc2_31 0 n4 ns31 0 -0.00184119557215 +Gc2_32 0 n4 ns32 0 -0.00447466538019 +Gd2_1 0 n4 ni1 0 0.00215590410319 +Gd2_2 0 n4 ni2 0 -0.0233432722319 +Gd2_3 0 n4 ni3 0 0.00269252278597 +Gd2_4 0 n4 ni4 0 -0.00167966971907 +Gc3_1 0 n6 ns1 0 0.0120068016928 +Gc3_2 0 n6 ns2 0 -0.00335214629302 +Gc3_3 0 n6 ns3 0 -0.00319713021974 +Gc3_4 0 n6 ns4 0 3.21626451775e-005 +Gc3_5 0 n6 ns5 0 0.00630673482663 +Gc3_6 0 n6 ns6 0 -0.0016802991944 +Gc3_7 0 n6 ns7 0 0.00363646912492 +Gc3_8 0 n6 ns8 0 0.00425584043779 +Gc3_9 0 n6 ns9 0 0.0113704185993 +Gc3_10 0 n6 ns10 0 -0.00209270619742 +Gc3_11 0 n6 ns11 0 -0.00115235931971 +Gc3_12 0 n6 ns12 0 0.000809468915486 +Gc3_13 0 n6 ns13 0 0.00214691269647 +Gc3_14 0 n6 ns14 0 0.00214304838332 +Gc3_15 0 n6 ns15 0 0.00168323686028 +Gc3_16 0 n6 ns16 0 0.00474793363943 +Gc3_17 0 n6 ns17 0 0.0158309230168 +Gc3_18 0 n6 ns18 0 0.00669546985649 +Gc3_19 0 n6 ns19 0 -0.0112057124689 +Gc3_20 0 n6 ns20 0 -0.00417978159798 +Gc3_21 0 n6 ns21 0 0.00963844848896 +Gc3_22 0 n6 ns22 0 0.00182079491498 +Gc3_23 0 n6 ns23 0 -0.00412581707681 +Gc3_24 0 n6 ns24 0 0.00425528143529 +Gc3_25 0 n6 ns25 0 0.0161038168044 +Gc3_26 0 n6 ns26 0 0.00613425379329 +Gc3_27 0 n6 ns27 0 0.021708011572 +Gc3_28 0 n6 ns28 0 0.0166004200489 +Gc3_29 0 n6 ns29 0 0.00250023382171 +Gc3_30 0 n6 ns30 0 0.00333853225408 +Gc3_31 0 n6 ns31 0 -0.00931626057888 +Gc3_32 0 n6 ns32 0 0.00878717212091 +Gd3_1 0 n6 ni1 0 0.00991185183934 +Gd3_2 0 n6 ni2 0 0.00269373841587 +Gd3_3 0 n6 ni3 0 -0.00134975577885 +Gd3_4 0 n6 ni4 0 0.00372986450169 +Gc4_1 0 n8 ns1 0 0.0109859425896 +Gc4_2 0 n8 ns2 0 -0.0010870658907 +Gc4_3 0 n8 ns3 0 -0.00385577661707 +Gc4_4 0 n8 ns4 0 0.00169544555725 +Gc4_5 0 n8 ns5 0 0.00075291278233 +Gc4_6 0 n8 ns6 0 0.00163271360514 +Gc4_7 0 n8 ns7 0 0.0012273294198 +Gc4_8 0 n8 ns8 0 0.00294460471098 +Gc4_9 0 n8 ns9 0 0.00749216340753 +Gc4_10 0 n8 ns10 0 0.00223884186439 +Gc4_11 0 n8 ns11 0 -0.0135457802023 +Gc4_12 0 n8 ns12 0 0.000753185734976 +Gc4_13 0 n8 ns13 0 0.001293637751 +Gc4_14 0 n8 ns14 0 0.000937782237717 +Gc4_15 0 n8 ns15 0 -0.00184114911193 +Gc4_16 0 n8 ns16 0 -0.00447558975404 +Gc4_17 0 n8 ns17 0 0.0161001523174 +Gc4_18 0 n8 ns18 0 0.00613689777898 +Gc4_19 0 n8 ns19 0 0.0217049795393 +Gc4_20 0 n8 ns20 0 0.0166014288453 +Gc4_21 0 n8 ns21 0 0.00249924911241 +Gc4_22 0 n8 ns22 0 0.00333804874764 +Gc4_23 0 n8 ns23 0 -0.00931956630649 +Gc4_24 0 n8 ns24 0 0.00878440923794 +Gc4_25 0 n8 ns25 0 0.00858837026407 +Gc4_26 0 n8 ns26 0 0.0109210409471 +Gc4_27 0 n8 ns27 0 -0.0268534493041 +Gc4_28 0 n8 ns28 0 0.00149700570657 +Gc4_29 0 n8 ns29 0 0.000765248523118 +Gc4_30 0 n8 ns30 0 0.000249141088958 +Gc4_31 0 n8 ns31 0 -0.00688126874059 +Gc4_32 0 n8 ns32 0 -0.0049427298681 +Gd4_1 0 n8 ni1 0 0.0010266231635 +Gd4_2 0 n8 ni2 0 -0.00167862387423 +Gd4_3 0 n8 ni3 0 0.00372546366711 +Gd4_4 0 n8 ni4 0 -0.0256218701932 +.ends diff --git a/spice/copy/sub/Contrib/Wurth/WE-CFWI.lib b/spice/copy/sub/Contrib/Wurth/WE-CFWI.lib new file mode 100755 index 0000000..2cb7d12 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CFWI.lib @@ -0,0 +1,311 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Coupled Flatwire Inductor +* Matchcode: WE-CFWI +* Library Type: Ltspice +* Version: rev18a +* Created/modified by: Fredo +* Date and Time : 3/15/2018 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 1310_74485540080_0.8u 1 2 3 4 PARAMS: ++ Cww=108p ++ Rp1=705.4 ++ Cp1=2.628p ++ Lp1=0.908u ++ Rp2=705.4 ++ Cp2=2.628p ++ Lp2=0.908u ++ RDC1=0.0016 ++ RDC2=0.0016 ++ K=0.925337776166087 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1310_74485540120_1.2u 1 2 3 4 PARAMS: ++ Cww=223p ++ Rp1=960.7 ++ Cp1=3.927p ++ Lp1=1.261u ++ Rp2=960.7 ++ Cp2=3.927p ++ Lp2=1.261u ++ RDC1=0.0024 ++ RDC2=0.0024 ++ K=0.944722181384559 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1310_74485540170_1.7u 1 2 3 4 PARAMS: ++ Cww=254p ++ Rp1=1234 ++ Cp1=3.572p ++ Lp1=1.659u ++ Rp2=1234 ++ Cp2=3.572p ++ Lp2=1.659u ++ RDC1=0.0033 ++ RDC2=0.0033 ++ K=0.958859616787506 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1310_74485540220_2.2u 1 2 3 4 PARAMS: ++ Cww=279p ++ Rp1=1606 ++ Cp1=3.806p ++ Lp1=2.279u ++ Rp2=1606 ++ Cp2=3.806p ++ Lp2=2.279u ++ RDC1=0.0042 ++ RDC2=0.0042 ++ K=0.956793888700459 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1310_74485540290_2.9u 1 2 3 4 PARAMS: ++ Cww=384p ++ Rp1=2102 ++ Cp1=3.772p ++ Lp1=2.772u ++ Rp2=2102 ++ Cp2=3.772p ++ Lp2=2.772u ++ RDC1=0.0056 ++ RDC2=0.0056 ++ K=0.964543844304761 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1310_74485540350_3.5u 1 2 3 4 PARAMS: ++ Cww=417p ++ Rp1=2626 ++ Cp1=3.533p ++ Lp1=3.53u ++ Rp2=2626 ++ Cp2=3.533p ++ Lp2=3.53u ++ RDC1=0.0075 ++ RDC2=0.0075 ++ K=0.969241234899017 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1312_74485540680_6.8u 1 2 3 4 PARAMS: ++ Cww=556p ++ Rp1=4005 ++ Cp1=4.764p ++ Lp1=6.508u ++ Rp2=4005 ++ Cp2=4.764p ++ Lp2=6.508u ++ RDC1=0.0113 ++ RDC2=0.0113 ++ K=0.986154146165801 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1312_74485540820_8.2u 1 2 3 4 PARAMS: ++ Cww=573p ++ Rp1=5043 ++ Cp1=4.715p ++ Lp1=9.462u ++ Rp2=5043 ++ Cp2=4.715p ++ Lp2=9.462u ++ RDC1=0.013 ++ RDC2=0.013 ++ K=0.987420882906575 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1312_74485540101_10u 1 2 3 4 PARAMS: ++ Cww=684p ++ Rp1=5877 ++ Cp1=4.596p ++ Lp1=9.706u ++ Rp2=5877 ++ Cp2=4.596p ++ Lp2=9.706u ++ RDC1=0.0139 ++ RDC2=0.0139 ++ K=0.989141041510259 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1813_74485542680_6.8u 1 2 3 4 PARAMS: ++ Cww=549p ++ Rp1=3794 ++ Cp1=6.578p ++ Lp1=6.782u ++ Rp2=3794 ++ Cp2=6.578p ++ Lp2=6.782u ++ RDC1=0.0061 ++ RDC2=0.0061 ++ K=0.983541021603304 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1813_74485542820_8.2u 1 2 3 4 PARAMS: ++ Cww=645p ++ Rp1=6040 ++ Cp1=7.414p ++ Lp1=8.521u ++ Rp2=6040 ++ Cp2=7.414p ++ Lp2=8.521u ++ RDC1=0.0084 ++ RDC2=0.0084 ++ K=0.985875864149334 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1813_74485542101_10u 1 2 3 4 PARAMS: ++ Cww=767p ++ Rp1=7360 ++ Cp1=6.196p ++ Lp1=10.196u ++ Rp2=7360 ++ Cp2=6.196p ++ Lp2=10.196u ++ RDC1=0.011 ++ RDC2=0.011 ++ K=0.987420882906575 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** diff --git a/spice/copy/sub/Contrib/Wurth/WE-CMB.lib b/spice/copy/sub/Contrib/Wurth/WE-CMB.lib new file mode 100755 index 0000000..0daeaa3 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CMB.lib @@ -0,0 +1,991 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-CMB +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT CMB 1 2 3 4 PARAMS: +R_R9 N12325 3 {R2} +R_R8 N13265 N13287 {Rs4} +Kn_K6 L_L11 L_L12 ++ L_L13 L_L14 0.9999 +R_R3 N12571 N12583 {Rs3} +R_R10 N13777 4 {R2} +C_C10 N13029 N12821 {ck} +R_R20 N13215 N13229 {dR4} +L_L11 N12821 N12295 {dL4} +R_R17 N12267 N12273 {dR3} +L_L8 N13265 N13287 {L4} +R_R7 N13287 N13305 {Rs3} +L_L9 N12295 N12307 {L5} +Kn_K4 L_L7 L_L8 1 +R_R2 N12583 N12599 {Rs2} +Kn_K5 L_L9 L_L10 1 +R_R16 N13229 N13249 {dR6} +Kn_K7 L_L15 L_L16 ++ L_L17 L_L18 0.9999 +C_C5 N12273 N12289 {dC4} +L_L6 N13287 N13305 {L3} +L_L7 N12307 N12571 {L4} +R_R6 N13305 N13319 {Rs2} +R_R21 1 N12257 {Rdc} +Kn_K3 L_L5 L_L6 1 +L_L16 N12257 N12799 {dL3} +C_C8 N13215 N13741 {dC3} +L_L18 N13023 N13215 {dL3} +R_R1 N12599 3 {Rs1} +R_R13 N12289 N12295 {dR5} +L_L4 N13305 N13319 {L2} +L_L5 N12571 N12583 {L3} +R_R15 N13755 N13249 {dR5} +R_R5 N13319 4 {Rs1} +R_R18 N12257 N12273 {dR4} +Kn_K2 L_L3 L_L4 1 +R_R19 N13741 N13229 {dR3} +L_L15 N12799 N12273 {dL3} +L_L17 N13229 N13023 {dL3} +L_L3 N12583 N12599 {L2} +R_R11 N12295 N12307 {Rs5} +L_L2 N13319 4 {L1} +C_C4 N13249 N13265 {C2} +L_L10 N13249 N13265 {L5} +Kn_K1 L_L1 L_L2 1 +R_R14 N12273 N12295 {dR6} +C_C6 N13229 N13755 {dC4} +L_L12 N12273 N12821 {dL4} +L_L14 N13029 N13229 {dL4} +L_L1 N12599 3 {L1} +C_C1 N12307 N12325 {C1} +R_R12 N13249 N13265 {Rs5} +C_C2 N13265 N13777 {C1} +R_R22 2 N13215 {Rdc} +C_C9 N13023 N12799 {ck} +R_R4 N12307 N12571 {Rs4} +C_C3 N12295 N12307 {C2} +L_L13 N13249 N13029 {dL4} +C_C7 N12257 N12267 {dC3} +.ends CMB +**** +.subckt XS_744821201_1m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=7u ++ DL4=18n ++ DC3=0.2p ++ DC4=10p ++ DR3=7000 ++ DR4=7000 ++ DR5=60000 ++ DR6=7000 ++ Rdc=0.33 ++ ck=40pF ++ L1=15m ++ L2=10u ++ L3=2n ++ L4=35n ++ L5=0.25n ++ C1=25p ++ C2=25p ++ RS1=200000 ++ RS2=7000 ++ RS3=5000 ++ RS4=5000 ++ RS5=4000 ++ R2=0.08 +.ends XS_744821201_1m +**** +.subckt XS_744821240_4m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000015 ++ DL4=0.000000047 ++ DC3=0.000000000014 ++ DC4=0.000000000008 ++ DR3=17 ++ dR4=20k ++ DR5=23 ++ dR6=5k ++ Rdc=0.082 ++ ck=2pF ++ L1=3.2m ++ L2=0.7m ++ L3=23u ++ L4=4u ++ L5=570.4n ++ C1=10p ++ C2=6p ++ Rs1=18k ++ Rs2=29k ++ RS3=500 ++ RS4=600 ++ RS5=2000 ++ R2=10.41 +.ends XS_744821240_4m +**** +.subckt XS_744821150_5m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000018 ++ DL4=0.000000064 ++ DC3=0.0000000000125 ++ DC4=0.000000000005 ++ DR3=17 ++ dR4=15k ++ DR5=30 ++ dR6=2k ++ Rdc=0.168 ++ ck=2pF ++ L1=3.6m ++ L2=0.8m ++ L3=23u ++ L4=4u ++ L5=800.4n ++ C1=11.5p ++ C2=4p ++ Rs1=19k ++ Rs2=19k ++ RS3=500 ++ RS4=200 ++ RS5=2500 ++ R2=1 +.ends XS_744821150_5m +**** +.subckt XS_744821110_10m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000052 ++ DL4=0.000000005 ++ DC3=0.000000000022 ++ DC4=0.000000000006 ++ DR3=17 ++ dR4=25k ++ dR5=30k ++ dR6=5k ++ Rdc=0.266 ++ ck=6pF ++ L1=8.8m ++ L2=0.180m ++ L3=23u ++ L4=4u ++ L5=520.4n ++ C1=14p ++ C2=10p ++ Rs1=69k ++ Rs2=20k ++ RS3=500 ++ RS4=200 ++ RS5=800 ++ R2=1 +.ends XS_744821110_10m +**** +.subckt XS_744821120_20m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.000011 ++ DL4=0.000000007 ++ DC3=0.000000000019 ++ DC4=0.000000000001 ++ DR3=17 ++ dR4=30k ++ DR5=30 ++ dR6=8k ++ Rdc=0.779 ++ ck=12pF ++ L1=19.8m ++ L2=1.8m ++ L3=23u ++ L4=4u ++ L5=2.920u ++ C1=11p ++ C2=15p ++ Rs1=129k ++ Rs2=20k ++ RS3=500 ++ RS4=200 ++ RS5=2200 ++ R2=20.41 +.ends XS_744821120_20m +**** +.subckt XS_744821039_39m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.000022 ++ DL4=0.000000225 ++ DC3=0.000000000027 ++ DC4=0.000000000038 ++ DR3=17 ++ dR4=127k ++ DR5=23 ++ dR6=1.5k ++ Rdc=1.905 ++ ck=3pF ++ L1=37.5m ++ L2=1.8m ++ L3=23u ++ L4=4u ++ L5=630n ++ C1=27p ++ C2=90p ++ Rs1=499k ++ Rs2=29k ++ RS3=500 ++ RS4=200 ++ RS5=1000 ++ R2=1 +.ends XS_744821039_39m +**** +.subckt S_744822301_1m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ L1=0.00060538 ++ L2=0.00010035 ++ L3=0.00004247 ++ L4=0.00001022 ++ L5=0.000000036 ++ C1=0.000000000003 ++ C2=0.000000000001 ++ RS1=8828 ++ RS2=1447 ++ RS3=703 ++ RS4=678 ++ RS5=509 ++ R2=0.11 ++ DL3=0.00000031037 ++ DL4=0.00000001106 ++ DC3=0.00000000000019056 ++ DC4=0.000000000007 ++ DR3=1000 ++ DR4=4500 ++ DR5=11000 ++ DR6=438 ++ Rdc=0.021 ++ ck=12.5pF +.ends S_744822301_1m +**** +.subckt S_744822233_3.3m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000014 ++ DL4=0.000000003 ++ DC3=0.0000000000083 ++ DC4=0.000000000002 ++ DR3=17 ++ dR4=22k ++ DR5=30 ++ dR6=2k ++ Rdc=0.079 ++ ck=3pF ++ L1=3m ++ L2=0.58m ++ L3=23u ++ L4=4u ++ L5=210.4n ++ C1=8p ++ C2=8p ++ Rs1=38k ++ Rs2=6k ++ RS3=500 ++ RS4=200 ++ RS5=1200 ++ R2=1.41 +.ends S_744822233_3.3m +**** +.subckt S_744822110_10m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000035 ++ DL4=0.000000104 ++ DC3=0.0000000000192 ++ DC4=0.000000000019 ++ DR3=17 ++ dR4=27k ++ DR5=30 ++ dR6=12k ++ Rdc=0.236 ++ ck=4pF ++ L1=11.6m ++ L2=800u ++ L3=23u ++ L4=4u ++ L5=1.8u ++ C1=14.5p ++ C2=8p ++ Rs1=79k ++ Rs2=19k ++ RS3=500 ++ RS4=200 ++ RS5=5000 ++ R2=10.41 +.ends S_744822110_10m +**** +.subckt S_744822120_20m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000068 ++ DL4=0.00000001 ++ DC3=0.000000000032 ++ DC4=0.000000000003 ++ DR3=17 ++ dR4=27k ++ DR5=30 ++ dR6=2k ++ Rdc=0.355 ++ ck=10pF ++ L1=16.6m ++ L2=800u ++ L3=23u ++ L4=4u ++ L5=80.4n ++ C1=26.5p ++ C2=28p ++ Rs1=340k ++ Rs2=19k ++ RS3=500 ++ RS4=200 ++ RS5=800 ++ R2=1.41 +.ends S_744822120_20m +**** +.subckt M_744823305_5m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ L1=0.0000149932488790583 ++ L2=0.0000219946000050973 ++ L3=0.0000734873979778146 ++ L4=0.00545630375790193 ++ L5=9.38962438216997E-10 ++ C1=1.50319062754058E-11 ++ C2=5.341200990649E-12 ++ RS1=5265.31166846459 ++ RS2=7902.70514846992 ++ RS3=1651.19231206434 ++ RS4=39361.136544689 ++ RS5=9214.69726890499 ++ R2=0.109490257696781 ++ DL3=0.0000017 ++ DL4=0.00000002 ++ DC3=0.000000000033 ++ DC4=0.00000000006 ++ DR3=4 ++ DR4=1120 ++ DR5=6 ++ DR6=800 ++ Rdc=60.229m ++ ck=4pF +.ends M_744823305_5m +**** +.subckt M_744823601_1m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.00000024233 ++ DC3=0.00000000001 ++ DL4=0.00000001079 ++ DC4=0.00000000000421 ++ DR3=10 ++ DR4=3300 ++ DR5=173 ++ DR6=2705 ++ Rdc=8.952m ++ ck=2.005pF ++ L1=0.00001849 ++ L2=0.000039 ++ L3=0.000019 ++ L4=0.0009 ++ L5=0.00000001869 ++ C1=0.00000000000305 ++ C2=0.00000000000415 ++ RS1=745 ++ RS2=200 ++ RS3=332 ++ RS4=3200 ++ RS5=362 ++ R2=11 +.ends M_744823601_1m +**** +.subckt M_744823422_2.2m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ L1=3m ++ L2=800.72u ++ L3=523.19u ++ L4=242.84u ++ L5=42.11n ++ C1=3.43p ++ C2=4.39p ++ RS1=7554 ++ RS2=1544 ++ RS3=1544 ++ RS4=2457 ++ RS5=561 ++ R2=39 ++ dL3=532.17n ++ dC3=11.33p ++ dL4=27.79n ++ dC4=4.13p ++ DR3=28 ++ DR4=10212 ++ DR5=23 ++ DR6=2190 ++ Rdc=24.288m ++ ck=2p +.ends M_744823422_2.2m +**** +.subckt M_744823333_3.3m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000008388 ++ DC3=0.0000000000124 ++ DL4=0.00000004038 ++ DC4=0.00000000000673 ++ DR3=0.21 ++ DR4=7180 ++ DR5=45 ++ DR6=1197 ++ Rdc=45.566m ++ ck=2.005pF ++ L1=2m ++ L2=0.00038766 ++ L3=0.00021925 ++ L4=0.007228 ++ L5=0.000000082 ++ C1=0.00000000000368 ++ C2=0.00000000000359 ++ RS1=549 ++ RS2=539 ++ RS3=539 ++ RS4=18717 ++ RS5=756 ++ R2=39 +.ends M_744823333_3.3m +**** +.subckt M_744823210_10m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.00000268 ++ DC3=0.000000000026 ++ DL4=0.00000007674 ++ DC4=0.000000000032 ++ DR3=1.43 ++ DR4=11000 ++ DR5=0.019 ++ DR6=1052 ++ Rdc=99.542m ++ ck=2.005pF ++ L1=10m ++ L2=2m ++ L3=203u ++ L4=104u ++ L5=900.4n ++ C1=16.7p ++ C2=20p ++ Rs1=48k ++ Rs2=29k ++ Rs3=5k ++ Rs4=5k ++ Rs5=2k ++ R2=40.41 +.ends M_744823210_10m +**** +.subckt M_744823220_20m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000062 ++ DL4=0.000000095 ++ DC3=0.000000000032 ++ DC4=0.00000000006 ++ DR3=17 ++ dR4=30k ++ DR5=23 ++ dR6=4k ++ Rdc=216.759m ++ ck=3pF ++ L1=19m ++ L2=0.000059 ++ L3=0.000092 ++ L4=0.000021 ++ L5=0.000000124 ++ C1=0.000000000022 ++ C2=0.00000000003 ++ Rs1=124k ++ Rs2=199k ++ RS3=561 ++ RS4=915 ++ RS5=894 ++ R2=1 +.ends M_744823220_20m +**** +.subckt L_744824101_1m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.00000040534 ++ DC3=0.00000000001907 ++ DL4=0.00000001675 ++ DC4=0.00000000000382 ++ DR3=10 ++ DR4=4300 ++ DR5=0.63 ++ DR6=1750 ++ Rdc=6.372m ++ ck=2.005pF ++ L1=0.00172384 ++ L2=0.00089876 ++ L3=0.00015148 ++ L4=0.0001977 ++ L5=0.0000001268 ++ C1=0.00000000000832 ++ C2=0.00000000000548 ++ RS1=565 ++ RS2=470 ++ RS3=557 ++ RS4=2992 ++ RS5=643 ++ R2=0.56 +.ends L_744824101_1m +**** +.subckt L_744824622_2.2m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.00000068242 ++ DC3=0.00000000001367 ++ DL4=0.000000029 ++ DC4=0.00000000000971 ++ DR3=0.02 ++ DR4=6278 ++ DR5=28 ++ DR6=821 ++ Rdc=16.345m ++ ck=2pF ++ L1=0.00000897 ++ L2=0.00016374 ++ L3=0.00013744 ++ L4=0.00443191 ++ L5=0.00000010639 ++ C1=0.00000000000399 ++ C2=0.00000000000211 ++ RS1=10 ++ RS2=943 ++ RS3=928 ++ RS4=8391 ++ RS5=765 ++ R2=4 +.ends L_744824622_2.2m +**** +.subckt L_744824433_3.3m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ dL3=1u ++ dL4=50.25n ++ dC3=15.595p ++ dC4=8.4p ++ DR3=0.1 ++ dR4=8k ++ DR5=0.1 ++ DR6=900 ++ Rdc=28.429m ++ ck=2pF ++ L1=0.000001023 ++ L2=0.00013929 ++ L3=0.00017837 ++ L4=0.00099218 ++ L5=0.0000000783 ++ C1=0.00000000000471 ++ C2=0.00000000000684 ++ RS1=504 ++ RS2=500 ++ RS3=545 ++ RS4=11862 ++ RS5=676 ++ R2=11 +.ends L_744824433_3.3m +**** +.subckt L_744824220_20m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000077 ++ DL4=0.000000485 ++ DC3=0.000000000028 ++ DC4=0.000000000011 ++ DR3=17 ++ dR4=50k ++ DR5=30 ++ dR6=5k ++ Rdc=175.322m ++ ck=5pF ++ L1=18.2m ++ L2=0.7m ++ L3=23u ++ L4=4u ++ L5=2.2u ++ C1=32p ++ C2=23p ++ Rs1=46k ++ Rs2=39k ++ RS3=500 ++ RS4=600 ++ RS5=3000 ++ R2=10.41 +.ends L_744824220_20m +**** +.subckt L_744824310_10m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ L1=0.00975054658861754 ++ L2=1.14140874719913E-06 ++ L3=0.0000194215546747162 ++ L4=1.85397202790917E-06 ++ L5=1.37528846983612E-06 ++ C1=1.06648809782419E-11 ++ C2=1.54875317445924E-11 ++ RS1=68798.4459196234 ++ RS2=49005.5273080916 ++ RS3=4486.62345566418 ++ RS4=361.356712407375 ++ RS5=1960.56329938029 ++ R2=11.2784542155485 ++ DL3=3.33880176803062E-06 ++ DC3=1.51444689487349E-11 ++ DL4=4.03878815013849E-09 ++ DC4=6.73761021204444E-12 ++ DR3=0.717429786820428 ++ DR4=17180.6679766708 ++ DR5=55.0109730646157 ++ DR6=3197.74941444441 ++ Rdc=85.225m ++ ck=4pF +.ends L_744824310_10m +**** +.subckt XL_7448251201_1m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000003 ++ DC3=0.00000000001 ++ DL4=0.00000000951 ++ DC4=0.00000000000463 ++ DR3=0.18 ++ DR4=2680 ++ DR5=0.78 ++ DR6=366 ++ Rdc=5.598m ++ ck=5pF ++ L1=0.00022 ++ L2=0.00019 ++ L3=0.00022 ++ L4=0.00064 ++ L5=0.00000001398 ++ C1=0.00000000000335 ++ C2=0.00000000000531 ++ RS1=560 ++ RS2=550 ++ RS3=1500 ++ RS4=798 ++ RS5=269 ++ R2=7 +.ends XL_7448251201_1m +**** +.subckt XL_7448258022_2.2m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.00000058 ++ DL4=0.000000025 ++ DC3=0.0000000000165 ++ DC4=0.00000000001 ++ DR3=17 ++ dR4=7k ++ DR5=23 ++ dR6=3k ++ Rdc=11.1m ++ ck=1pF ++ L1=1.8m ++ L2=80u ++ L3=23u ++ L4=4u ++ L5=135n ++ C1=4.5p ++ C2=1.5p ++ RS1=4000 ++ RS2=1600 ++ RS3=1500 ++ RS4=200 ++ RS5=800 ++ R2=1 +.ends XL_7448258022_2.2m +**** +.subckt XL_7448256033_3.3m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.00000085 ++ DL4=0.000000058 ++ DC3=0.0000000000144 ++ DC4=0.000000000001 ++ DR3=17 ++ dR4=9k ++ DR5=23 ++ dR6=2k ++ Rdc=18.752m ++ ck=4pF ++ L1=2.6m ++ L2=700u ++ L3=23u ++ L4=4u ++ L5=110.4n ++ C1=5p ++ C2=2.8p ++ Rs1=16k ++ Rs2=6k ++ RS3=500 ++ RS4=600 ++ RS5=900 ++ R2=10.41 +.ends XL_7448256033_3.3m +**** +.subckt XL_744825605_5m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.00000133 ++ DC3=0.00000000001775 ++ DL4=0.00000003977 ++ DC4=0.00000000002487 ++ DR3=13 ++ DR4=7090 ++ DR5=13 ++ DR6=6762 ++ Rdc=35.042m ++ ck=2pF ++ L1=0.00034616 ++ L2=0.00025028 ++ L3=0.00025626 ++ L4=0.00065136 ++ L5=0.0000001087 ++ C1=0.00000000000515 ++ C2=0.00000000000874 ++ RS1=2558 ++ RS2=2548 ++ RS3=6527 ++ RS4=2609 ++ RS5=674 ++ R2=15 +.ends XL_744825605_5m +**** +.subckt XL_744825510_10m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000027 ++ DL4=0.000000081 ++ DC3=0.000000000037 ++ DC4=0.000000000005 ++ DR3=17 ++ dR4=30k ++ DR5=23 ++ dR6=12k ++ Rdc=40.604m ++ ck=5pF ++ L1=8m ++ L2=1m ++ L3=23u ++ L4=4u ++ L5=600.4n ++ C1=22p ++ C2=16p ++ Rs1=60k ++ RS2=6000 ++ RS3=500 ++ RS4=600 ++ RS5=1600 ++ R2=1.41 +.ends XL_744825510_10m +**** +.subckt XL_744825320_20m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.0000059 ++ DL4=0.00000014 ++ DC3=0.000000000036 ++ DC4=0.000000000046 ++ DR3=17 ++ dR4=35k ++ DR5=23 ++ dR6=9k ++ Rdc=123.197m ++ ck=5pF ++ L1=16m ++ L2=580u ++ L3=23u ++ L4=4u ++ L5=900.4n ++ C1=31p ++ C2=48p ++ Rs1=62k ++ Rs2=6k ++ RS3=500 ++ RS4=600 ++ RS5=1600 ++ R2=1.41 +.ends XL_744825320_20m +**** +.subckt XL_744825433_33m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ L1=0.0282615082580083 ++ L2=0.00151069974592023 ++ L3=0.0000635319123130355 ++ L4=0.0000802861920160678 ++ L5=8.4783967316618E-07 ++ C1=3.31973088954225E-11 ++ C2=8.99664633755108E-11 ++ RS1=271189.203553144 ++ RS2=68603.4021105262 ++ RS3=958.938477130436 ++ RS4=557.325344506158 ++ RS5=1527.4005919289 ++ R2=54.5016446977904 ++ DL3=9.83880176803062E-06 ++ DC3=4.9444689487349E-11 ++ DL4=2.00387881501384E-07 ++ DC4=4.17376102120444E-11 ++ DR3=0.217429786820428 ++ DR4=19180.6679766708 ++ DR5=39.0109730646157 ++ DR6=5197.74941444441 ++ Rdc=187.34m ++ ck=4pF +.ends XL_744825433_33m +**** +.subckt XXL_7448262510_1m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ L1=0.00030889 ++ L2=0.00039029 ++ L3=0.00005 ++ L4=0.00005 ++ L5=0.00032526 ++ C1=0.0000000000218 ++ C2=0.00000000000527 ++ RS1=3140 ++ RS2=2206 ++ RS3=3254 ++ RS4=4188 ++ RS5=3190 ++ R2=0.054 ++ DL3=0.00000049 ++ DC3=0.0000000000129 ++ DL4=0.00000003711 ++ DC4=0.00000000000007 ++ DR3=0.48 ++ DR4=3680 ++ DR5=18 ++ DR6=366 ++ Rdc=3.427m ++ ck=4pF +.ends XXL_7448262510_1m +**** +.subckt XXL_7448261418_1.8m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ L1=0.00140889 ++ L2=0.00039029 ++ L3=0.00005 ++ L4=0.00005 ++ L5=0.00012526 ++ C1=0.0000000000098 ++ C2=0.00000000000987 ++ RS1=8140 ++ RS2=8206 ++ RS3=3254 ++ RS4=4188 ++ RS5=2500 ++ R2=0.054 ++ DL3=0.00000094 ++ DC3=0.0000000000176 ++ DL4=0.00000005111 ++ DC4=0.00000000000233 ++ DR3=0.48 ++ DR4=6680 ++ DR5=0.58 ++ DR6=566 ++ Rdc=7.79m ++ ck=4pF +.ends XXL_7448261418_1.8m +**** +.subckt XXL_7448262013_1.3m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ L1=0.00060889 ++ L2=0.00059029 ++ L3=0.00005 ++ L4=0.00001 ++ L5=0.00012526 ++ C1=0.0000000000108 ++ C2=0.00000000000687 ++ RS1=4140 ++ RS2=2206 ++ RS3=2254 ++ RS4=3188 ++ RS5=2100 ++ R2=0.054 ++ DL3=0.00000062 ++ DC3=0.0000000000148 ++ DL4=0.00000003811 ++ DC4=0.00000000000213 ++ DR3=0.48 ++ DR4=4680 ++ DR5=0.58 ++ DR6=446 ++ Rdc=4.8m ++ ck=4pF +.ends XXL_7448262013_1.3m +**** +.subckt XXL_7448263505_0.5m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ L1=0.000209496782810346 ++ L2=0.000207729580657503 ++ L3=0.000244939980673891 ++ L4=4.35416881861321E-06 ++ L5=0.0000181955270659663 ++ C1=7.22232517664312E-11 ++ C2=6.74966861088266E-11 ++ RS1=12.914504794244 ++ RS2=2355.13991346187 ++ RS3=1395.50992687538 ++ RS4=13415.8487785026 ++ RS5=260.107405675112 ++ R2=40.2708746893173 ++ DL3=0.00000023 ++ DC3=0.0000000000106 ++ DL4=0.00000001211 ++ DC4=0.00000000000033 ++ DR3=0.48 ++ DR4=1580 ++ DR5=0.58 ++ DR6=166 ++ Rdc=1.84m ++ ck=4pF +.ends XXL_7448263505_0.5m +**** +.subckt S_744822222_2.2m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.68u ++ DL4=3n ++ DC3=8.3p ++ DC4=2p ++ DR3=17 ++ dR4=6k ++ DR5=30 ++ dR6=2k ++ Rdc=0.079 ++ ck=3pF ++ L1=1.75m ++ L2=0.58m ++ L3=23u ++ L4=4u ++ L5=210.4n ++ C1=6.5p ++ C2=8p ++ Rs1=17.5k ++ Rs2=6k ++ RS3=500 ++ RS4=200 ++ RS5=1200 ++ R2=1.41 +.ends S_744822222_2.2m +**** +.subckt L_744824407_7m 1 2 3 4 +X1 1 2 3 4 CMB PARAMS: ++ DL3=0.00000228242 ++ DC3=0.00000000001367 ++ DL4=0.000000159 ++ DC4=0.00000000000971 ++ DR3=0.02 ++ DR4=8278 ++ DR5=28 ++ DR6=821 ++ Rdc=16.345m ++ ck=2pF ++ L1=0.00000897 ++ L2=0.00016374 ++ L3=0.00221744 ++ L4=0.00443191 ++ L5=0.00000010639 ++ C1=0.00000000002399 ++ C2=0.00000000001211 ++ RS1=10 ++ RS2=943 ++ RS3=30928 ++ RS4=30391 ++ RS5=765 ++ R2=4 +.ends L_744824407_7m +**** diff --git a/spice/copy/sub/Contrib/Wurth/WE-CMBH.lib b/spice/copy/sub/Contrib/Wurth/WE-CMBH.lib new file mode 100755 index 0000000..c76476e --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CMBH.lib @@ -0,0 +1,264 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-CMBH +* Library Type: LTspice +* Version: rev20a +* Created/modified by: Paul +* Date and Time : 2020-03-05 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT CMBH 1 2 3 4 PARAMS: +R_R9 N12325 3 {R2} +R_R8 N13265 N13287 {Rs4} +Kn_K6 L_L11 L_L12 ++ L_L13 L_L14 0.9999 +R_R3 N12571 N12583 {Rs3} +R_R10 N13777 4 {R2} +C_C10 N13029 N12821 {ck} +R_R20 N13215 N13229 {dR4} +L_L11 N12821 N12295 {dL4} +R_R17 N12267 N12273 {dR3} +L_L8 N13265 N13287 {L4} +R_R7 N13287 N13305 {Rs3} +L_L9 N12295 N12307 {L5} +Kn_K4 L_L7 L_L8 1 +R_R2 N12583 N12599 {Rs2} +Kn_K5 L_L9 L_L10 1 +R_R16 N13229 N13249 {dR6} +Kn_K7 L_L15 L_L16 ++ L_L17 L_L18 0.9999 +C_C5 N12273 N12289 {dC4} +L_L6 N13287 N13305 {L3} +L_L7 N12307 N12571 {L4} +R_R6 N13305 N13319 {Rs2} +R_R21 1 N12257 {Rdc} +Kn_K3 L_L5 L_L6 1 +L_L16 N12257 N12799 {dL3} +C_C8 N13215 N13741 {dC3} +L_L18 N13023 N13215 {dL3} +R_R1 N12599 3 {Rs1} +R_R13 N12289 N12295 {dR5} +L_L4 N13305 N13319 {L2} +L_L5 N12571 N12583 {L3} +R_R15 N13755 N13249 {dR5} +R_R5 N13319 4 {Rs1} +R_R18 N12257 N12273 {dR4} +Kn_K2 L_L3 L_L4 1 +R_R19 N13741 N13229 {dR3} +L_L15 N12799 N12273 {dL3} +L_L17 N13229 N13023 {dL3} +L_L3 N12583 N12599 {L2} +R_R11 N12295 N12307 {Rs5} +L_L2 N13319 4 {L1} +C_C4 N13249 N13265 {C2} +L_L10 N13249 N13265 {L5} +Kn_K1 L_L1 L_L2 1 +R_R14 N12273 N12295 {dR6} +C_C6 N13229 N13755 {dC4} +L_L12 N12273 N12821 {dL4} +L_L14 N13029 N13229 {dL4} +L_L1 N12599 3 {L1} +C_C1 N12307 N12325 {C1} +R_R12 N13249 N13265 {Rs5} +C_C2 N13265 N13777 {C1} +R_R22 2 N13215 {Rdc} +C_C9 N13023 N12799 {ck} +R_R4 N12307 N12571 {Rs4} +C_C3 N12295 N12307 {C2} +L_L13 N13249 N13029 {dL4} +C_C7 N12257 N12267 {dC3} +.ends CMBH +**** +.SUBCKT L_744834101_1m 1 2 3 4 +X1 1 2 3 4 CMBH PARAMS: ++ L1=200.14u ++ L2=200.53u ++ L3=254.10u ++ L4=250.1u ++ L5=10n ++ C1=18000.06f ++ C2=540.02f ++ Rs1=1856.63 ++ Rs2=1278.77 ++ Rs3=1496.33 ++ Rs4=18000 ++ Rs5=1636.33 ++ R2=7 ++ dL3=380e-009 ++ dC3=6.5e-012 ++ dL4=13.51e-009 ++ dC4=7.63e-012 ++ dR3=0.48 ++ dR4=3550 ++ dR5=0.78 ++ dR6=466 ++ Rdc=8m ++ ck=2pF +.ends L_744834101_1m + **** +.SUBCKT L_744834405_5m 1 2 3 4 +X1 1 2 3 4 CMBH PARAMS: ++ L1=300.14u ++ L2=500.53u ++ L3=3024.10u ++ L4=900.1u ++ L5=300n ++ C1=16700.06f ++ C2=13400.02f ++ Rs1=28566.63 ++ Rs2=2578.77 ++ Rs3=24966.33 ++ Rs4=640000 ++ Rs5=1636.33 ++ R2=1 ++ dL3=1.9e-006 ++ dL4=35e-009 ++ dC3=19.5e-012 ++ dC4=3.7e-011 ++ dR3=0.08 ++ dR4=16100 ++ dR5=11 ++ dR6=19850 ++ Rdc=35m ++ ck=4pF +.ends L_744834405_5m +**** +.SUBCKT L_744834407_7m 1 2 3 4 +X1 1 2 3 4 CMBH PARAMS: ++ L1=600.14u ++ L2=600.53u ++ L3=3924.10u ++ L4=500.1u ++ L5=500n ++ C1=19700.06f ++ C2=20400.02f ++ Rs1=18566.63 ++ Rs2=5578.77 ++ Rs3=51966.33 ++ Rs4=540000 ++ Rs5=636.33 ++ R2=1 ++ dL3=2.6e-006 ++ dL4=45e-009 ++ dC3=19e-012 ++ dC4=4.5e-011 ++ dR3=0.08 ++ dR4=19100 ++ dR5=28 ++ dR6=59850 ++ Rdc=55.27m ++ ck=4pF +.ends L_744834407_7m + **** +.SUBCKT L_744834433_3.3m 1 2 3 4 +X1 1 2 3 4 CMBH PARAMS: ++ L1=3.5m ++ L2=350u ++ L3=33u ++ L4=2u ++ L5=100.4n ++ C1=11p ++ C2=1p ++ Rs1=21k ++ Rs2=10k ++ Rs3=300 ++ Rs4=660 ++ Rs5=660 ++ R2=1.41 ++ dL3=1500e-009 ++ dC3=16e-012 ++ dL4=5.51e-009 ++ dC4=13.63e-012 ++ dR3=0.48 ++ dR4=11680 ++ dR5=0.78 ++ dR6=266 ++ Rdc=28m ++ ck=4pF +.ends L_744834433_3.3m +**** +.SUBCKT L_744834622_2.2m 1 2 3 4 +X1 1 2 3 4 CMBH PARAMS: ++ L1=1.9m ++ L2=250u ++ L3=13u ++ L4=.1u ++ L5=170.4n ++ C1=10p ++ C2=1.2p ++ Rs1=21k ++ Rs2=2k ++ Rs3=200 ++ Rs4=260 ++ Rs5=460 ++ R2=1.41 ++ dL3=900e-009 ++ dC3=12.6e-012 ++ dL4=12.51e-009 ++ dC4=11.63e-012 ++ dR3=0.49 ++ dR4=9680 ++ dR5=17 ++ dR6=866 ++ Rdc=14.74m ++ ck=4pF +.ends L_744834622_2.2m +**** +.SUBCKT L_744834220_20m 1 2 3 4 +X1 1 2 3 4 CMBH PARAMS: ++ L1=20m ++ L2=250u ++ L3=13u ++ L4=.1u ++ L5=100.4n ++ C1=33p ++ C2=1.2p ++ Rs1=210k ++ Rs2=2k ++ Rs3=200 ++ Rs4=260 ++ Rs5=460 ++ R2=1.41 ++ dL3=7800e-009 ++ dC3=41e-012 ++ dL4=12.51e-009 ++ dC4=11.63e-012 ++ dR3=0.49 ++ dR4=15380 ++ dR5=17 ++ dR6=866 ++ Rdc=14.74m ++ ck=4pF +.ends +**** +.SUBCKT L_744834310_10m 1 2 3 4 +X1 1 2 3 4 CMBH PARAMS: ++ L1=10m ++ L2=250u ++ L3=13u ++ L4=.1u ++ L5=100.4n ++ C1=21p ++ C2=1.2p ++ Rs1=93k ++ Rs2=2k ++ Rs3=200 ++ Rs4=260 ++ Rs5=460 ++ R2=1.41 ++ dL3=3800e-009 ++ dC3=21e-012 ++ dL4=12.51e-009 ++ dC4=11.63e-012 ++ dR3=0.49 ++ dR4=15380 ++ dR5=17 ++ dR6=866 ++ Rdc=14.74m ++ ck=4pF +.ends +**** + + \ No newline at end of file diff --git a/spice/copy/sub/Contrib/Wurth/WE-CMBHC.lib b/spice/copy/sub/Contrib/Wurth/WE-CMBHC.lib new file mode 100755 index 0000000..a83df73 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CMBHC.lib @@ -0,0 +1,181 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-CMBHC +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT CMBHC 1 2 3 4 PARAMS: +R_R9 N12325 3 {R2} +R_R8 N13265 N13287 {Rs4} +Kn_K6 L_L11 L_L12 ++ L_L13 L_L14 0.9999 +R_R3 N12571 N12583 {Rs3} +R_R10 N13777 4 {R2} +C_C10 N13029 N12821 {ck} +R_R20 N13215 N13229 {dR4} +L_L11 N12821 N12295 {dL4} +R_R17 N12267 N12273 {dR3} +L_L8 N13265 N13287 {L4} +R_R7 N13287 N13305 {Rs3} +L_L9 N12295 N12307 {L5} +Kn_K4 L_L7 L_L8 1 +R_R2 N12583 N12599 {Rs2} +Kn_K5 L_L9 L_L10 1 +R_R16 N13229 N13249 {dR6} +Kn_K7 L_L15 L_L16 ++ L_L17 L_L18 0.9999 +C_C5 N12273 N12289 {dC4} +L_L6 N13287 N13305 {L3} +L_L7 N12307 N12571 {L4} +R_R6 N13305 N13319 {Rs2} +R_R21 1 N12257 {Rdc} +Kn_K3 L_L5 L_L6 1 +L_L16 N12257 N12799 {dL3} +C_C8 N13215 N13741 {dC3} +L_L18 N13023 N13215 {dL3} +R_R1 N12599 3 {Rs1} +R_R13 N12289 N12295 {dR5} +L_L4 N13305 N13319 {L2} +L_L5 N12571 N12583 {L3} +R_R15 N13755 N13249 {dR5} +R_R5 N13319 4 {Rs1} +R_R18 N12257 N12273 {dR4} +Kn_K2 L_L3 L_L4 1 +R_R19 N13741 N13229 {dR3} +L_L15 N12799 N12273 {dL3} +L_L17 N13229 N13023 {dL3} +L_L3 N12583 N12599 {L2} +R_R11 N12295 N12307 {Rs5} +L_L2 N13319 4 {L1} +C_C4 N13249 N13265 {C2} +L_L10 N13249 N13265 {L5} +Kn_K1 L_L1 L_L2 1 +R_R14 N12273 N12295 {dR6} +C_C6 N13229 N13755 {dC4} +L_L12 N12273 N12821 {dL4} +L_L14 N13029 N13229 {dL4} +L_L1 N12599 3 {L1} +C_C1 N12307 N12325 {C1} +R_R12 N13249 N13265 {Rs5} +C_C2 N13265 N13777 {C1} +R_R22 2 N13215 {Rdc} +C_C9 N13023 N12799 {ck} +R_R4 N12307 N12571 {Rs4} +C_C3 N12295 N12307 {C2} +L_L13 N13249 N13029 {dL4} +C_C7 N12257 N12267 {dC3} +.ends CMBHC + **** +.SUBCKT S_7448225007_0.7m 1 2 3 4 +X1 1 2 3 4 CMBHC PARAMS: ++ L1=385.38e-6 ++ L2=60.35e-006 ++ L3=92.47e-006 ++ L4=80.22e-006 ++ L5=18e-009 ++ C1=2e-012 ++ C2=1e-012 ++ Rs1=2928 ++ Rs2=837 ++ Rs3=1193 ++ Rs4=1278 ++ Rs5=549 ++ R2=0.11 ++ dL3=200e-009 ++ dC3=5.3e-012 ++ dL4=4.01e-009 ++ dC4=4.63e-012 ++ dR3=0.48 ++ dR4=2980 ++ dR5=0.98 ++ dR6=366 ++ Rdc=13.15m ++ ck=4pF +.ends S_7448225007_0.7m + **** +.SUBCKT S_7448227005_0.45m 1 2 3 4 +X1 1 2 3 4 CMBHC PARAMS: ++ L1=208.89e-006 ++ L2=40.29e-006 ++ L3=50e-06 ++ L4=50e-06 ++ L5=125.26e-006 ++ C1=9.80e-012 ++ C2=1.87e-012 ++ Rs1=1440 ++ Rs2=1206 ++ Rs3=254 ++ Rs4=188 ++ Rs5=1400 ++ R2=0.054 ++ dL3=140e-009 ++ dC3=4.6e-012 ++ dL4=4.11e-009 ++ dC4=0.33e-012 ++ dR3=0.48 ++ dR4=2280 ++ dR5=10 ++ dR6=316 ++ Rdc=8.47m ++ ck=4pF +.ends S_7448227005_0.45m + **** +.SUBCKT S_7448229004_0.35m 1 2 3 4 +X1 1 2 3 4 CMBHC PARAMS: ++ L1=60u ++ L2=50u ++ L3=72u ++ L4=2.5u ++ L5=3.8n ++ C1=1.4p ++ C2=2.1p ++ Rs1=600 ++ Rs2=500 ++ Rs3=500 ++ Rs4=.600 ++ Rs5=200 ++ R2=1.41 ++ dL3=50n ++ dC3=3.5p ++ dL4=1.31n ++ dC4=1.03p ++ dR3=0.48 ++ dR4=801 ++ dR5=0.78 ++ dR6=126 ++ Rdc=4.95m ++ ck=4pF +.ends S_7448229004_0.35m + **** +.SUBCKT S_74482210002_0.175m 1 2 3 4 +X1 1 2 3 4 CMBHC PARAMS: ++ L1=38.89e-006 ++ L2=20.29e-006 ++ L3=1e-09 ++ L4=1e-09 ++ L5=105.26e-006 ++ C1=2263.80e-015 ++ C2=3.13e-012 ++ Rs1=440 ++ Rs2=206 ++ Rs3=254 ++ Rs4=188 ++ Rs5=1200 ++ R2=0.054 ++ dL3=50e-009 ++ dC3=3e-012 ++ dL4=1.351e-009 ++ dC4=1.43e-015 ++ dR3=0.48 ++ dR4=880 ++ dR5=1.88 ++ dR6=166 ++ Rdc=3.223m ++ ck=4pF +.ends S_74482210002_0.175m + diff --git a/spice/copy/sub/Contrib/Wurth/WE-CMBHV.lib b/spice/copy/sub/Contrib/Wurth/WE-CMBHV.lib new file mode 100755 index 0000000..d3504b6 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CMBHV.lib @@ -0,0 +1,850 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-CMBHV +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt XL_744830007215_0.7m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.0038 +.param L1=660.38e-006 +.param L2=80.35e-006 +.param L3=90.47e-006 +.param L4=157.22e-006 +.param L5=3.5e-009 +.param C1=1.5e-011 +.param C2=2.0e-016 +.param Rs1=3098 +.param Rs2=837 +.param Rs3=1193 +.param Rs4=1278 +.param Rs5=6490 +.param R2=16 +.param dL3=29.8e-08 +.param dC3=13.8e-012 +.param dL4=9.51e-009 +.param dC4=100e-09 +.param dR3=0.19 +.param dR4=1930 +.param dR5=1 +.param dR6=200 +.param ck=0.001pF +.backanno +.ends XL_744830007215_0.7m +*-------------------------------------------------------- +.subckt XL_744830010185_1m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.0055 +.param L1=880.38e-006 +.param L2=199.35e-006 +.param L3=185.47e-006 +.param L4=225.22e-006 +.param L5=2.8e-010 +.param C1=1.280e-011 +.param C2=1.4e-016 +.param Rs1=5000 +.param Rs2=3700 +.param Rs3=593 +.param Rs4=1578 +.param Rs5=7490 +.param R2=17 +.param dL3=44.1e-08 +.param dC3=15e-012 +.param dL4=9.51e-09 +.param dC4=100e-09 +.param dR3=0.19 +.param dR4=3550 +.param dR5=1 +.param dR6=200 +.param ck=0.2pF +.backanno +.ends XL_744830010185_1m +*-------------------------------------------------------- +.subckt XL_744830017132_1.7m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.01 +.param L1=1760.38e-006 +.param L2=700.35e-006 +.param L3=95.47e-006 +.param L4=99.22e-006 +.param L5=2.5e-010 +.param C1=1.98e-011 +.param C2=3e-016 +.param Rs1=12128 +.param Rs2=837 +.param Rs3=1493 +.param Rs4=1378 +.param Rs5=7490 +.param R2=17 +.param dL3=70e-08 +.param dC3=20e-012 +.param dL4=9.51e-09 +.param dC4=10e-09 +.param dR3=0.19 +.param dR4=4950 +.param dR5=1 +.param dR6=200 +.param ck=0.2pF +.backanno +.ends XL_744830017132_1.7m +*-------------------------------------------------------------- +.subckt XL_744830025103_2.5m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.018 +.param L1=2610.38e-006 +.param L2=700.35e-006 +.param L3=950.47e-006 +.param L4=200.22e-006 +.param L5=2.75e-010 +.param C1=2.20e-011 +.param C2=2.7e-011 +.param Rs1=23600 +.param Rs2=837 +.param Rs3=1493 +.param Rs4=1378 +.param Rs5=8490 +.param R2=16 +.param dL3=118e-08 +.param dC3=20.6e-012 +.param dL4=9.51e-09 +.param dC4=100e-09 +.param dR3=0.19 +.param dR4=7000 +.param dR5=1 +.param dR6=200 +.param ck=0.1pF +.backanno +.ends XL_744830025103_2.5m +*-------------------------------------------------------------- +.subckt XL_744830039080_3.9m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.031 +.param L1=3398.38e-006 +.param L2=700.35e-006 +.param L3=950.47e-006 +.param L4=85.22e-006 +.param L5=2.75e-010 +.param C1=2.15e-011 +.param C2=2.75e-011 +.param Rs1=37000 +.param Rs2=837 +.param Rs3=1493 +.param Rs4=13780 +.param Rs5=8490 +.param R2=16 +.param dL3=144e-08 +.param dC3=27.9e-012 +.param dL4=9.51e-09 +.param dC4=100e-09 +.param dR3=0.19 +.param dR4=9050 +.param dR5=1 +.param dR6=200 +.param ck=0.1pF +.backanno +.ends XL_744830039080_3.9m +*-------------------------------------------------------------- +.subckt XXL_744831010205_1m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.0055 +.param L1=879.38e-006 +.param L2=80.35e-006 +.param L3=95.47e-006 +.param L4=85.22e-006 +.param L5=2.0e-009 +.param C1=2.050e-011 +.param C2=3e-016 +.param Rs1=11928 +.param Rs2=837 +.param Rs3=1193 +.param Rs4=1278 +.param Rs5=6490 +.param R2=12 +.param dL3=62e-08 +.param dC3=18.5e-012 +.param dL4=9.51e-009 +.param dC4=10e-09 +.param dR3=0.19 +.param dR4=4050 +.param dR5=1 +.param dR6=10 +.param ck=0.5pF +.backanno +.ends XXL_744831010205_1m +*-------------------------------------------------------------- +.subckt XXL_744831016164_1.6m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.0055 +.param L1=1550.38e-006 +.param L2=80.35e-006 +.param L3=95.47e-006 +.param L4=85.22e-006 +.param L5=2.0e-009 +.param C1=2.250e-011 +.param C2=3e-016 +.param Rs1=19928 +.param Rs2=837 +.param Rs3=1193 +.param Rs4=1278 +.param Rs5=6490 +.param R2=12 +.param dL3=91e-08 +.param dC3=24.6e-012 +.param dL4=9.51e-09 +.param dC4=45e-09 +.param dR3=3 +.param dR4=5950 +.param dR5=1 +.param dR6=10 +.param ck=1pF +.backanno +.ends XXL_744831016164_1.6m +*-------------------------------------------------------------- +.subckt XXL_744831020133_2m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.013 +.param L1=1863.38e-006 +.param L2=80.35e-006 +.param L3=95.47e-006 +.param L4=85.22e-006 +.param L5=2.0e-009 +.param C1=2.060e-011 +.param C2=3e-016 +.param Rs1=24928 +.param Rs2=837 +.param Rs3=1193 +.param Rs4=1278 +.param Rs5=6490 +.param R2=10 +.param dL3=130e-08 +.param dC3=21.5e-012 +.param dL4=9.51e-09 +.param dC4=45e-09 +.param dR3=3 +.param dR4=6100 +.param dR5=1 +.param dR6=10 +.param ck=0.01pF +.backanno +.ends XXL_744831020133_2m +*-------------------------------------------------------------- +.subckt XXL_744831034090_3.4m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.013 +.param L1=1.80e-003 +.param L2=5.80e-004 +.param L3=4.95e-004 +.param L4=4.85e-004 +.param L5=2.50e-009 +.param C1=2.650e-011 +.param C2=2.5e-016 +.param Rs1=48928 +.param Rs2=5837 +.param Rs3=5893 +.param Rs4=5878 +.param Rs5=6490 +.param R2=10 +.param dL3=205e-08 +.param dC3=23.6e-012 +.param dL4=9.51e-09 +.param dC4=45e-09 +.param dR3=3 +.param dR4=10580 +.param dR5=1 +.param dR6=10 +.param ck=0.01pF +.backanno +.ends XXL_744831034090_3.4m +*-------------------------------------------------------------- +.subckt XXL_744831047068_4.7m 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.044 +.param L1=5050.380e-006 +.param L2=80.35e-006 +.param L3=95.47e-006 +.param L4=85.22e-006 +.param L5=2.0e-009 +.param C1=2.750e-011 +.param C2=3e-016 +.param Rs1=92028 +.param Rs2=8380050 +.param Rs3=1193 +.param Rs4=1278 +.param Rs5=10490 +.param R2=15 +.param dL3=305e-08 +.param dC3=28.8e-012 +.param dL4=9.51e-09 +.param dC4=45e-09 +.param dR3=3 +.param dR4=12100 +.param dR5=1 +.param dR6=10 +.param ck=0.01pF +.backanno +.ends XXL_744831047068_4.7m diff --git a/spice/copy/sub/Contrib/Wurth/WE-CMBNC.lib b/spice/copy/sub/Contrib/Wurth/WE-CMBNC.lib new file mode 100755 index 0000000..087dd15 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CMBNC.lib @@ -0,0 +1,1309 @@ +********************************************************* +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-CMBNC +* Library Type: Pspice +* Version: rev17b +* Created/modified by: Fredo +* Date and Time : 2017-12-19 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +******************************************************** +.SUBCKT CMBNC 1 2 3 4 PARAMS: ++ L1=0.00060538 ++ L2=0.00010035 ++ L3=0.00004247 ++ L4=0.00001022 ++ L5=0.000000036 ++ C1=0.000000000003 ++ C2=0.000000000001 ++ RS1=8828 ++ RS2=1447 ++ RS3=703 ++ RS4=678 ++ RS5=509 ++ R2=0.11 ++ DL3=0.00000031037 ++ DL4=0.00000001106 ++ DC3=0.00000000000019056 ++ DC4=0.000000000007 ++ DR3=1000 ++ DR4=4500 ++ DR5=11000 ++ DR6=438 ++ Rdc=0.43 ++ ck=12.5pF +L5 N010 N009 {L3} +R50 N010 N009 {Rs3} +C3 N500 N001 {C1} +R500 4 N500 {R2} +L1 4 N011 {L1} +R51 4 N011 {Rs1} +L3 N011 N010 {L2} +R52 N011 N010 {Rs2} +L6 N014 N013 {L3} +R53 N014 N013 {Rs3} +C4 N501 N012 {C1} +R501 3 N501 {R2} +L2 3 N015 {L1} +R54 3 N015 {Rs1} +L4 N015 N014 {L2} +R55 N015 N014 {Rs2} +L8 N013 N012 {L4} +R56 N013 N012 {Rs4} +L7 N009 N001 {L4} +R57 N009 N001 {Rs4} +L9 N001 N006 {L5} +R58 N001 N006 {Rs5} +C50 N001 N006 {C2} +L10 N012 N020 {L5} +R59 N012 N020 {Rs5} +C51 N012 N020 {C2} +R1 N002 1 {Rdc} +R6 N016 2 {Rdc} +R2 N006 N004 {dR6} +C1 N005 N004 {dC3} +L11 N008 N004 {dL3} +L12 N018 N019 {dL3} +C2 N008 N019 {ck} +R3 N006 N005 {dR5} +R4 N020 N022 {dR3} +C5 N022 N018 {dC3} +R5 N020 N018 {dR4} +L13 N006 N008 {dL3} +L14 N019 N020 {dL3} +R8 N004 N002 {dR6} +C6 N003 N002 {dC4} +L15 N007 N002 {dL4} +L16 N016 N017 {dL4} +C7 N007 N017 {ck} +R9 N004 N003 {dR5} +R10 N018 N021 {dR5} +C8 N021 N016 {dC4} +R11 N018 N016 {dR6} +L17 N004 N007 {dL4} +L18 N017 N018 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K6 L13 L14 L11 L12 0.9999 +K7 L15 L16 L17 L18 0.9999 +.ends CMBNC +******** +.subckt XS_7448010911_11m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.354999989271164 ++ ck=9.15709522097963E-12 ++ DC4=2.33921881864774E-10 ++ DL4=1.09498807887576E-06 ++ DR5=14846.5380859375 ++ DR6=18534.806640625 ++ DC3=3.33897409721118E-10 ++ DL3=4.54652031578462E-08 ++ DR3=1045.89575195313 ++ DR4=88924.546875 ++ L1=0.00869298074394464 ++ L2=0.000467057310743257 ++ L3=0.00135353673249483 ++ L4=0.0000196324490389088 ++ RS1=6607.99658203125 ++ RS2=24180.732421875 ++ RS3=9770.07421875 ++ RS4=23873.265625 ++ C1=4.78700456010839E-12 ++ R2=3.01428484916687 ++ C2=2.04170937934123E-08 ++ L5=0.0000910909293452278 ++ RS5=3.74318003654479 +.ends XS_7448010911_11m +******** +.subckt XS_7448011008_8m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.277999997138977 ++ ck=6.0024012669968E-12 ++ DC4=2.73229737446368E-11 ++ DL4=8.14368092960649E-07 ++ DR5=7221.44482421875 ++ DR6=224451.9375 ++ DC3=4.37110303508348E-09 ++ DL3=5.67908315929344E-08 ++ DR3=1169528.5 ++ DR4=1024759.75 ++ L1=0.0063436389900744 ++ L2=0.00109203590545803 ++ L3=0.000217066946788691 ++ L4=0.00028052440029569 ++ RS1=4582.064453125 ++ RS2=7006.28369140625 ++ RS3=47439.70703125 ++ RS4=6601.64892578125 ++ C1=3.50304941304502E-12 ++ R2=2.29911279678345 ++ C2=3.43900770491054E-13 ++ L5=4.0811581891731E-10 ++ RS5=0.41453218460083 +.ends XS_7448011008_8m +******** +.subckt XS_7448011305_5m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.168999999761581 ++ ck=2.25999994678825E-14 ++ DC4=3.65080535247309E-12 ++ DL4=4.60730888107719E-07 ++ DR5=3.52454352378845 ++ DR6=6065.509765625 ++ DC3=9.47457065060553E-13 ++ DL3=2.40244109050991E-08 ++ DR3=2051.99462890625 ++ DR4=625860.9375 ++ L1=0.00129573908634484 ++ L2=0.00273191463202238 ++ L3=0.000747762445826083 ++ L4=0.000185409357072785 ++ RS1=467.464172363281 ++ RS2=2900.0927734375 ++ RS3=5651.88671875 ++ RS4=13813.4619140625 ++ C1=3.34747615911291E-12 ++ R2=1.03841233253479 ++ C2=1.40755517050867E-13 ++ L5=3.38628881879632E-11 ++ RS5=2.2954523563385 +.ends XS_7448011305_5m +******** +.subckt XS_7448012002_1m6 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0860000029206276 ++ ck=1.69815030093279E-12 ++ DC4=1.18014398167027E-12 ++ DL4=1.16388264359557E-07 ++ DR5=61385.6328125 ++ DR6=4105.31884765625 ++ DC3=1.93209701709884E-11 ++ DL3=6.56655041453291E-09 ++ DR3=989.751708984375 ++ DR4=2804660.25 ++ L1=0.000852709752507508 ++ L2=0.0000577403297938872 ++ L3=0.000388926739105955 ++ L4=0.000112803296360653 ++ RS1=1605.56591796875 ++ RS2=6322.48046875 ++ RS3=88.5050964355469 ++ RS4=1702.09875488281 ++ C1=6.25561939488622E-13 ++ R2=0.483416646718979 ++ C2=6.73252102956212E-08 ++ L5=0.0000249020140472567 ++ RS5=42.8821487426758 +.ends XS_7448012002_1m6 +******** +.subckt XS_7448012501_1m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.046000000089407 ++ ck=1.64943427839737E-12 ++ DC4=1.08074528544397E-16 ++ DL4=9.4963432673012E-08 ++ DR5=0.0133064752444625 ++ DR6=3555.86938476563 ++ DC3=5.14609996664903E-15 ++ DL3=4.60131088786397E-09 ++ DR3=0.0543990135192871 ++ DR4=759.391662597656 ++ L1=0.000334763084538281 ++ L2=0.000046876710257493 ++ L3=9.42685255722608E-06 ++ L4=1.71062623621765E-07 ++ RS1=366.980529785156 ++ RS2=800.131530761719 ++ RS3=1728.64892578125 ++ RS4=12222.5107421875 ++ C1=5.7560862543396E-13 ++ R2=1.7486914396286 ++ C2=1.55494833588982E-12 ++ L5=0.00108504469972104 ++ RS5=0.578695297241211 +.ends XS_7448012501_1m +******** +.subckt XS_7448013501_0m5 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0280000008642673 ++ ck=1.49062598202299E-12 ++ DC4=3.27661922388481E-14 ++ DL4=5.61172690538569E-08 ++ DR5=0.0279833115637302 ++ DR6=2767.52563476563 ++ DC3=1.85868383401414E-13 ++ DL3=3.45350348318618E-09 ++ DR3=9.8975133895874 ++ DR4=660.719970703125 ++ L1=0.000502295675687492 ++ L2=0.000081971287727356 ++ L3=1.63714980772056E-06 ++ L4=0.0000160957752086688 ++ RS1=516.5498046875 ++ RS2=1053.02941894531 ++ RS3=817.908447265625 ++ RS4=2101.67431640625 ++ C1=6.00873409188629E-13 ++ R2=0.37173655629158 ++ C2=4.61719800171068E-08 ++ L5=0.0000011568936315598 ++ RS5=0.534857392311096 +.ends XS_7448013501_0m5 +******** +.subckt XS_7448014501_0m4 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0280000008642673 ++ ck=4.0635138483236E-13 ++ DC4=1.10570688889589E-12 ++ DL4=3.89507022191538E-08 ++ DR5=0.0495046675205231 ++ DR6=2381.40185546875 ++ DC3=2.40370576090956E-13 ++ DL3=3.79364450964204E-09 ++ DR3=1.26773536205292 ++ DR4=14691058 ++ L1=0.000311136245727539 ++ L2=0.0000403032790927682 ++ L3=2.99775706480432E-06 ++ L4=8.61158605403034E-06 ++ RS1=381.889678955078 ++ RS2=724.102416992188 ++ RS3=1262.0439453125 ++ RS4=896.188537597656 ++ C1=6.8501947820751E-13 ++ R2=2.54812860488892 ++ C2=3.12969011817543E-10 ++ L5=0.000000796946153514 ++ RS5=1.18781542778015 +.ends XS_7448014501_0m4 +******** +.subckt M_7448030333_33m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0799999982118607 ++ ck=1.73772524147964E-11 ++ DC4=5.54359835813756E-10 ++ DL4=1.26350835216726E-06 ++ DR5=385153.40625 ++ DR6=7327.30810546875 ++ DC3=1.13417142344474E-09 ++ DL3=4.8234202409958E-08 ++ DR3=34255.38671875 ++ DR4=22879832 ++ L1=0.0247995257377625 ++ L2=0.00917641445994377 ++ L3=0.000879100640304387 ++ L4=0.00202385382726789 ++ RS1=4350.64990234375 ++ RS2=7612.5126953125 ++ RS3=2848405.25 ++ RS4=9349.84765625 ++ C1=8.26555230509785E-12 ++ R2=37.8868217468262 ++ C2=6.62411048324429E-06 ++ L5=0.158110871911049 ++ RS5=26937344 +.ends M_7448030333_33m +******** +.subckt M_7448030417_17m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0379999987781048 ++ ck=1.562340014305E-11 ++ DC4=3.28442655017636E-12 ++ DL4=6.19997422290908E-07 ++ DR5=46.389778137207 ++ DR6=4362.0078125 ++ DC3=1.29215174259241E-13 ++ DL3=2.67301807355125E-08 ++ DR3=100.374443054199 ++ DR4=4953.90087890625 ++ L1=0.0151557568460703 ++ L2=0.00327215413562953 ++ L3=0.000534946040716022 ++ L4=0.000178101676283404 ++ RS1=2870.03051757813 ++ RS2=3019.1796875 ++ RS3=6627.37109375 ++ RS4=68425.8984375 ++ C1=1.00611168701858E-11 ++ R2=0.00632000016048551 ++ C2=2.80000008638995E-13 ++ L5=1.00000001335143E-10 ++ RS5=1 +.ends M_7448030417_17m +******** +.subckt M_7448030509_9m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0219999998807907 ++ ck=1.16532920466095E-11 ++ DC4=5.88655253014325E-12 ++ DL4=3.66745098290266E-07 ++ DR5=125392.9609375 ++ DR6=3499.224609375 ++ DC3=1.43253794243625E-11 ++ DL3=1.70972960233939E-08 ++ DR3=5723.576171875 ++ DR4=23600734208 ++ L1=0.0120000001043081 ++ L2=0.0020000000949949 ++ L3=0.000500000023748726 ++ L4=0.000150000007124618 ++ RS1=1880 ++ RS2=1900 ++ RS3=4000 ++ RS4=5000 ++ C1=5.99999997602518E-12 ++ R2=0.400000005960464 ++ C2=2.80000008638995E-13 ++ L5=1.00000001335143E-10 ++ RS5=1 +.ends M_7448030509_9m +******** +.subckt M_7448031002_2m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.00499999988824129 ++ ck=2.87433163208284E-12 ++ DC4=2.24046193923744E-12 ++ DL4=5.47510552451058E-08 ++ DR5=6099.224609375 ++ DR6=3090.13427734375 ++ DC3=1.15601473706095E-12 ++ DL3=3.14217163399633E-09 ++ DR3=845.783081054688 ++ DR4=1123.61694335938 ++ L1=0.00150000001303852 ++ L2=0.000199999994947575 ++ L3=0.0000599999984842725 ++ L4=3.80000005861802E-06 ++ RS1=400 ++ RS2=500 ++ RS3=1400 ++ RS4=2300 ++ C1=9.00000018087821E-13 ++ R2=0.400000005960464 ++ C2=2.80000008638995E-13 ++ L5=1.00000001335143E-10 ++ RS5=1 +.ends M_7448031002_2m +******** +.subckt M_7448031501_1m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0020000000949949 ++ ck=2.57202570873305E-12 ++ DC4=9.20577524800292E-13 ++ DL4=3.5461745540033E-08 ++ DR5=3732.66748046875 ++ DR6=3327.22192382813 ++ DC3=4.05753745489831E-13 ++ DL3=2.54755616602154E-09 ++ DR3=43.6796455383301 ++ DR4=2774.19946289063 ++ L1=0.00102942250669003 ++ L2=0.0000951876281760633 ++ L3=0.000016293502994813 ++ L4=8.00845043613663E-07 ++ RS1=322.377105712891 ++ RS2=490.611419677734 ++ RS3=1189.74926757813 ++ RS4=3580.23168945313 ++ C1=8.14731420349657E-13 ++ R2=0.567472815513611 ++ C2=3.6251337760633E-13 ++ L5=1.25527727101726E-10 ++ RS5=1.34631204605103 +.ends M_7448031501_1m +******** +.subckt L_7448040382_82m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.135000005364418 ++ ck=5.98668475904063E-11 ++ DC4=2.36828053912577E-13 ++ DL4=3.88230228054454E-06 ++ DR5=674.824829101563 ++ DR6=9586.4306640625 ++ DC3=1.14751775789901E-11 ++ DL3=1.91542204319717E-09 ++ DR3=21.6521663665771 ++ DR4=512807040 ++ L1=0.0829947218298912 ++ L2=0.0101475343108177 ++ L3=0.000536222942173481 ++ L4=0.000365290936315432 ++ RS1=20239.140625 ++ RS2=28361.994140625 ++ RS3=40298.8671875 ++ RS4=5075.22265625 ++ C1=2.74228764696183E-11 ++ R2=0.286605805158615 ++ C2=1.52322865432097E-08 ++ L5=1.36148946694448E-06 ++ RS5=1.43727397918701 +.ends L_7448040382_82m +******** +.subckt L_7448040435_35m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0640000030398369 ++ ck=3.41574164786085E-11 ++ DC4=1.86840939855187E-13 ++ DL4=1.59136141064664E-06 ++ DR5=834.48291015625 ++ DR6=8056.29541015625 ++ DC3=3.03443589699803E-11 ++ DL3=5.20691649519289E-12 ++ DR3=18.1167163848877 ++ DR4=766605248 ++ L1=0.0434059202671051 ++ L2=0.00645833602175117 ++ L3=0.00101479911245406 ++ L4=0.00159177230671048 ++ RS1=6704.43017578125 ++ RS2=8743.3896484375 ++ RS3=85064.4453125 ++ RS4=9577.373046875 ++ C1=1.56000004580825E-11 ++ R2=0.104000002145767 ++ C2=6.16184820501076E-07 ++ L5=0.000372471375158057 ++ RS5=302.954345703125 +.ends L_7448040435_35m +******** +.subckt L_7448040515_15m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0299999993294477 ++ ck=2.09951552671006E-11 ++ DC4=5.35570069196134E-13 ++ DL4=6.62409661345009E-07 ++ DR5=177.84440612793 ++ DR6=5423.15185546875 ++ DC3=2.21240335079864E-11 ++ DL3=2.08324335559951E-09 ++ DR3=25.7555999755859 ++ DR4=790799680 ++ L1=0.0313526727259159 ++ L2=0.000232258913456462 ++ L3=0.00022412148246076 ++ L4=0.00299568800255656 ++ RS1=2645.89135742188 ++ RS2=3905.26733398438 ++ RS3=60462.76953125 ++ RS4=7249.16162109375 ++ C1=7.88850842287081E-12 ++ R2=2.64605188369751 ++ C2=2.70506433253104E-07 ++ L5=7.29241946828552E-06 ++ RS5=18.6724090576172 +.ends L_7448040515_15m +******** +.subckt L_7448040707_7m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0149999996647239 ++ ck=1.90952613964013E-12 ++ DC4=1.85547193928826E-12 ++ DL4=2.65392174014778E-07 ++ DR5=7.91325426101685 ++ DR6=5166.0283203125 ++ DC3=1.44351640016249E-11 ++ DL3=1.07662325235514E-11 ++ DR3=20.0794124603271 ++ DR4=573485056 ++ L1=0.00819584168493748 ++ L2=0.000104253798781428 ++ L3=0.000717621645890176 ++ L4=0.0000629422720521688 ++ RS1=1761.64501953125 ++ RS2=10478.921875 ++ RS3=3873.51904296875 ++ RS4=243.744842529297 ++ C1=1.1602503896882E-12 ++ R2=0.516414642333984 ++ C2=1.75105725475078E-08 ++ L5=1.16033824326678E-07 ++ RS5=3.20607089996338 +.ends L_7448040707_7m +******** +.subckt L_7448041104_4m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.00600000005215406 ++ ck=4.35271480317412E-12 ++ DC4=1.22982657044246E-11 ++ DL4=1.54030630028501E-07 ++ DR5=93915.5234375 ++ DR6=3881.001953125 ++ DC3=1.73222519661564E-10 ++ DL3=4.94894569769144E-09 ++ DR3=7971.07861328125 ++ DR4=4366635 ++ L1=0.00809952709823847 ++ L2=0.000668641470838338 ++ L3=0.0000666780688334256 ++ L4=6.14096097706351E-06 ++ RS1=967.972229003906 ++ RS2=2600.03564453125 ++ RS3=4233.78271484375 ++ RS4=2245.02856445313 ++ C1=1.06666368446251E-12 ++ R2=0.651606798171997 ++ C2=7.86708866939989E-08 ++ L5=0.0000273303194262553 ++ RS5=72.0766448974609 +.ends L_7448041104_4m +******** +.subckt L_7448041502_2m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.00300000002607703 ++ ck=6.9133678816391E-12 ++ DC4=6.34493915740997E-11 ++ DL4=7.75969937194532E-08 ++ DR5=3128.60888671875 ++ DR6=39471.07421875 ++ DC3=1.05417675185914E-13 ++ DL3=2.37918595935582E-09 ++ DR3=274.328552246094 ++ DR4=217580.609375 ++ L1=0.00251754769124091 ++ L2=0.000312576012220234 ++ L3=0.0000346227570844349 ++ L4=0.0000161843363457592 ++ RS1=388.493408203125 ++ RS2=987.174682617188 ++ RS3=915.368774414063 ++ RS4=2395.36376953125 ++ C1=9.77613064286065E-13 ++ R2=0.805560827255249 ++ C2=2.31705442593072E-13 ++ L5=2.30107197185525E-10 ++ RS5=1.80797374248505 +.ends L_7448041502_2m +******** +.subckt L_7448041801_1m5 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0020000000949949 ++ ck=3.53989407231303E-12 ++ DC4=5.1319879742313E-14 ++ DL4=7.49445590031428E-08 ++ DR5=0.180175602436066 ++ DR6=2204.73461914063 ++ DC3=1.54048421154712E-12 ++ DL3=4.0160017533708E-09 ++ DR3=4.79514217376708 ++ DR4=1317.73986816406 ++ L1=0.00288988836109638 ++ L2=0.000365983025403693 ++ L3=0.000186753182788379 ++ L4=0.0000447224119852763 ++ RS1=335.088470458984 ++ RS2=270.503509521484 ++ RS3=602.089050292969 ++ RS4=2233.65698242188 ++ C1=1.2156046568651E-12 ++ R2=0.46083676815033 ++ C2=6.94929056521687E-08 ++ L5=1.52263805830444E-06 ++ RS5=1.9443267583847 +.ends L_7448041801_1m5 +******** +.subckt L_7448042001_1m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0020000000949949 ++ ck=3.54854752353251E-12 ++ DC4=4.14999997799641E-14 ++ DL4=4.42646452825102E-08 ++ DR5=66.5085525512695 ++ DR6=1859.89624023438 ++ DC3=5.74410988609178E-14 ++ DL3=2.73839506625961E-09 ++ DR3=149.318984985352 ++ DR4=2838661 ++ L1=0.00169906951487064 ++ L2=0.000165815101354383 ++ L3=0.0000243897702603135 ++ L4=0.0000125612896226812 ++ RS1=320.175964355469 ++ RS2=535.458984375 ++ RS3=377.848846435547 ++ RS4=1364.71984863281 ++ C1=9.1106137391217E-13 ++ R2=0.665103912353516 ++ C2=5.02737158569744E-08 ++ L5=1.29639533952286E-06 ++ RS5=1.57858121395111 +.ends L_7448042001_1m +******** +.subckt XL_7448050219_190m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.270000010728836 ++ ck=1.23371704020304E-13 ++ DC4=3.71604483295762E-11 ++ DL4=0.0000128481315186946 ++ DR5=178.67951965332 ++ DR6=344187.3125 ++ DC3=2.00057175686608E-11 ++ DL3=2.56449358276845E-11 ++ DR3=56.1910705566406 ++ DR4=10705463 ++ L1=0.0765414461493492 ++ L2=0.102970354259014 ++ L3=0.0401266478002071 ++ L4=0.00139641796704382 ++ RS1=9568.2236328125 ++ RS2=22181.89453125 ++ RS3=44593.328125 ++ RS4=43461.74609375 ++ C1=3.402876938563E-11 ++ R2=1.27523076534271 ++ C2=4.27454374118952E-08 ++ L5=1.66677966717543E-06 ++ RS5=3.19618940353394 +.ends XL_7448050219_190m +******** +.subckt XL_7448050490_90m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0900000035762787 ++ ck=1.74373070236516E-12 ++ DC4=2.11479150163951E-11 ++ DL4=5.81994072490488E-06 ++ DR5=20.3653221130371 ++ DR6=16725.390625 ++ DC3=4.20192353134397E-12 ++ DL3=1.90801571875454E-07 ++ DR3=0.840387582778931 ++ DR4=23183.978515625 ++ L1=0.0633048415184021 ++ L2=0.0527161695063114 ++ L3=0.00819597952067852 ++ L4=0.000813116610515863 ++ RS1=7977.4462890625 ++ RS2=21052.81640625 ++ RS3=34378.23828125 ++ RS4=21288.916015625 ++ C1=1.64609645358915E-11 ++ R2=0.626191973686218 ++ C2=2.81210930097586E-08 ++ L5=1.18083221423149E-06 ++ RS5=0.190767958760262 +.ends XL_7448050490_90m +******** +.subckt XL_7448050530_30m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0390000008046627 ++ ck=2.78509385692738E-11 ++ DC4=2.03024242925211E-13 ++ DL4=1.95580855688604E-06 ++ DR5=1 ++ DR6=8138.7958984375 ++ DC3=9.44529177093756E-12 ++ DL3=1.24510735055594E-10 ++ DR3=6.0740008354187 ++ DR4=968572096 ++ L1=0.0328281410038471 ++ L2=0.00365898618474603 ++ L3=0.00248376303352416 ++ L4=0.000128349827718921 ++ RS1=6471.7998046875 ++ RS2=5428.32861328125 ++ RS3=22317.498046875 ++ RS4=4520.37890625 ++ C1=1.15296400898801E-11 ++ R2=0.2381861358881 ++ C2=1.21399867936134E-08 ++ L5=3.81026836748788E-07 ++ RS5=0.376253843307495 +.ends XL_7448050530_30m +******** +.subckt XL_7448051012_12m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0130000002682209 ++ ck=1.29404375669856E-12 ++ DC4=4.20166375650344E-12 ++ DL4=5.41214205895812E-07 ++ DR5=20.7590198516846 ++ DR6=7527.47265625 ++ DC3=3.50737125974498E-12 ++ DL3=2.78807057441099E-08 ++ DR3=1.97621190547943 ++ DR4=164737248 ++ L1=0.0120416963472962 ++ L2=0.000347881024936214 ++ L3=0.00163540430366993 ++ L4=0.000174639615579508 ++ RS1=2931.60400390625 ++ RS2=9359.2822265625 ++ RS3=3876.35083007813 ++ RS4=4537.236328125 ++ C1=1.85642104987005E-12 ++ R2=0.539597749710083 ++ C2=4.17126173601901E-08 ++ L5=1.18381808533741E-06 ++ RS5=1.67514705657959 +.ends XL_7448051012_12m +******** +.subckt XL_7448051804_4m5 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0130000002682209 ++ ck=2.97196208615125E-12 ++ DC4=4.81861989545807E-12 ++ DL4=1.26532995636808E-07 ++ DR5=127.255516052246 ++ DR6=4357.1591796875 ++ DC3=1.48002392134396E-13 ++ DL3=6.84395544681138E-08 ++ DR3=197.913146972656 ++ DR4=2891.45288085938 ++ L1=0.00452137878164649 ++ L2=0.000352744333213195 ++ L3=0.0000765442819101736 ++ L4=0.0000105745393739198 ++ RS1=1277.31860351563 ++ RS2=2638.7890625 ++ RS3=3978.26245117188 ++ RS4=5125.6875 ++ C1=2.37914874433309E-12 ++ R2=0.514503955841064 ++ C2=1.71329492815175E-08 ++ L5=1.84958048521366E-06 ++ RS5=1.35451459884644 +.ends XL_7448051804_4m5 +******** +.subckt XL_7448052303_3m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0020000000949949 ++ ck=7.26791630351054E-12 ++ DC4=4.80728391122343E-12 ++ DL4=1.6081330045381E-07 ++ DR5=5729.1328125 ++ DR6=5042.890625 ++ DC3=1.36911168166498E-11 ++ DL3=4.67032634787756E-09 ++ DR3=587.157775878906 ++ DR4=343236.9375 ++ L1=0.00362045993097126 ++ L2=0.000298893282888457 ++ L3=0.0000368153596355114 ++ L4=0.0000126412960526068 ++ RS1=818.961853027344 ++ RS2=2084.45874023438 ++ RS3=1956.18017578125 ++ RS4=3705.36303710938 ++ C1=2.2923399289887E-12 ++ R2=1.01931715011597 ++ C2=1.24323151773353E-09 ++ L5=0.0000270433974947082 ++ RS5=168.055801391602 +.ends XL_7448052303_3m +******** +.subckt XL_7448052502_2m5 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.00100000004749745 ++ ck=8.29554849292313E-13 ++ DC4=5.57796829558921E-11 ++ DL4=1.43946996544742E-08 ++ DR5=179.459518432617 ++ DR6=4292.69921875 ++ DC3=1.32724040091681E-12 ++ DL3=1.11804851599118E-07 ++ DR3=19.6222877502441 ++ DR4=314498368 ++ L1=0.00263017346151173 ++ L2=0.000105558763607405 ++ L3=0.00042800308438018 ++ L4=8.12618600321002E-06 ++ RS1=506.157012939453 ++ RS2=2328.259765625 ++ RS3=739.272888183594 ++ RS4=10990.73046875 ++ C1=1.75593979460931E-12 ++ R2=1.93624866008759 ++ C2=8.57131610132456E-08 ++ L5=1.50932783071767E-06 ++ RS5=1.53144800662994 +.ends XL_7448052502_2m5 +******** +.subckt XL_7448053201_0m9 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0007999999797903 ++ ck=1.2583327392221E-12 ++ DC4=4.28396727814029E-12 ++ DL4=4.20275760859568E-08 ++ DR5=14.1212711334229 ++ DR6=2775.19506835938 ++ DC3=1.25812283768151E-12 ++ DL3=3.20948245757791E-09 ++ DR3=3.85115766525269 ++ DR4=75660016 ++ L1=0.000637456309050322 ++ L2=0.000282176537439227 ++ L3=0.0000572315802855883 ++ L4=8.29354667075677E-06 ++ RS1=125.572998046875 ++ RS2=288.548736572266 ++ RS3=825.164855957031 ++ RS4=1331.63842773438 ++ C1=2.28750894094854E-12 ++ R2=5.2646689414978 ++ C2=9.61421654094297E-12 ++ L5=6.94416075930349E-06 ++ RS5=5.94270849227905 +.ends XL_7448053201_0m9 +******** +.subckt XXL_7448060535_35m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0839999988675117 ++ ck=4.96077831591002E-12 ++ DC4=1.98334820789015E-11 ++ DL4=4.59804095953587E-06 ++ DR5=56.921085357666 ++ DR6=16531.955078125 ++ DC3=8.23022986568001E-12 ++ DL3=7.6840516172183E-09 ++ DR3=10.2092542648315 ++ DR4=250876416 ++ L1=0.0213536079972982 ++ L2=0.00678884657099843 ++ L3=0.00133800145704299 ++ L4=0.00335024832747877 ++ RS1=20953.0625 ++ RS2=84818.890625 ++ RS3=2855.02490234375 ++ RS4=4198.51025390625 ++ C1=1.84510011436156E-11 ++ R2=0.82143372297287 ++ C2=6.83071235130228E-08 ++ L5=2.43707540903415E-06 ++ RS5=3.06103205680847 +.ends XXL_7448060535_35m +******** +.subckt XXL_7448060620_20m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0839999988675117 ++ ck=6.01277014289359E-12 ++ DC4=2.21204807943076E-11 ++ DL4=3.06558172269433E-06 ++ DR5=64.8782348632813 ++ DR6=16196.1728515625 ++ DC3=5.84814271661904E-12 ++ DL3=2.1627684088088E-09 ++ DR3=9.9702091217041 ++ DR4=221807968 ++ L1=0.0094672292470932 ++ L2=0.00699292682111263 ++ L3=0.00153509667143226 ++ L4=0.00171207438688725 ++ RS1=8777.9384765625 ++ RS2=48527.07421875 ++ RS3=868.967224121094 ++ RS4=2137.66088867188 ++ C1=1.78616791496333E-11 ++ R2=0.608646094799042 ++ C2=2.94578068604778E-08 ++ L5=1.20935953873413E-06 ++ RS5=1.22790324687958 +.ends XXL_7448060620_20m +******** +.subckt XXL_7448060814_14m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0189999993890524 ++ ck=2.93837593146051E-11 ++ DC4=2.35259562941792E-08 ++ DL4=1.98842303689162E-06 ++ DR5=5169.552734375 ++ DR6=61153.6484375 ++ DC3=2.04652362222578E-13 ++ DL3=7.74112933754623E-08 ++ DR3=640.601013183594 ++ DR4=870.611022949219 ++ L1=0.00970976520329714 ++ L2=0.0021861451677978 ++ L3=0.00137306982651353 ++ L4=0.000958601187448949 ++ RS1=9313.65234375 ++ RS2=39263.6171875 ++ RS3=1550.61120605469 ++ RS4=3058.95092773438 ++ C1=1.05860155710791E-11 ++ R2=0.815732479095458 ++ C2=4.0503952192239E-08 ++ L5=0.000001271036126127 ++ RS5=1.93002426624298 +.ends XXL_7448060814_14m +******** +.subckt XXL_7448061309_9m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.00999999977648258 ++ ck=4.06722919232827E-11 ++ DC4=9.56819845576717E-10 ++ DL4=1.31716421947203E-06 ++ DR5=5652.556640625 ++ DR6=7768.02001953125 ++ DC3=3.17585888143235E-12 ++ DL3=6.4419936052218E-08 ++ DR3=412.457611083984 ++ DR4=28079.703125 ++ L1=0.00698916474357247 ++ L2=0.00125871121417731 ++ L3=0.00168122875038534 ++ L4=0.00100450566969812 ++ RS1=5720.06201171875 ++ RS2=84753.640625 ++ RS3=1992.466796875 ++ RS4=4123.216796875 ++ C1=1.80235514013471E-11 ++ R2=1.04356241226196 ++ C2=6.42019486463141E-08 ++ L5=1.81636323759449E-06 ++ RS5=2.22242593765259 +.ends XXL_7448061309_9m +******** +.subckt XXL_7448061507_7m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.00600000005215406 ++ ck=1.01505988944067E-12 ++ DC4=1.75113951117467E-11 ++ DL4=8.6810319999131E-07 ++ DR5=10.5465259552002 ++ DR6=4638.55908203125 ++ DC3=2.46688300077061E-14 ++ DL3=7.08466174614841E-08 ++ DR3=0.705563604831696 ++ DR4=10381737 ++ L1=0.00506870495155454 ++ L2=0.000874682678841054 ++ L3=0.001658228575252 ++ L4=0.000639679667074233 ++ RS1=4715.02490234375 ++ RS2=81134.6484375 ++ RS3=1441.15991210938 ++ RS4=3041.09594726563 ++ C1=1.54103171196018E-11 ++ R2=0.507139205932617 ++ C2=3.47771305087008E-08 ++ L5=8.98760902146023E-07 ++ RS5=0.978153824806213 +.ends XXL_7448061507_7m +******** +.subckt XXL_7448062105_5m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.00400000018998981 ++ ck=2.95758348367592E-11 ++ DC4=1.89999993277686E-14 ++ DL4=6.64122239868448E-07 ++ DR5=361.794647216797 ++ DR6=3127.68603515625 ++ DC3=7.73666634229508E-12 ++ DL3=2.58115697704397E-08 ++ DR3=710.999084472656 ++ DR4=20627.453125 ++ L1=0.00311436993069947 ++ L2=0.000626115943305194 ++ L3=0.000886573339812458 ++ L4=0.000768705387599766 ++ RS1=2827.06518554688 ++ RS2=56696.171875 ++ RS3=1517.8466796875 ++ RS4=2845.55834960938 ++ C1=1.39394138592985E-11 ++ R2=0.461454510688782 ++ C2=2.40371633708492E-08 ++ L5=1.36279641083092E-06 ++ RS5=0.996920466423035 +.ends XXL_7448062105_5m +******** +.subckt XXL_7448062603_3m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.00300000002607703 ++ ck=3.01888652964877E-11 ++ DC4=5.33317801813121E-13 ++ DL4=4.35371049434252E-07 ++ DR5=1458.11145019531 ++ DR6=3074.376953125 ++ DC3=1.59807948124646E-11 ++ DL3=1.70473359872858E-08 ++ DR3=1219.49731445313 ++ DR4=137247.921875 ++ L1=0.00224578683264554 ++ L2=0.000199999994947575 ++ L3=0.00104663299862295 ++ L4=0.000203529634745792 ++ RS1=1250.37756347656 ++ RS2=2809.2333984375 ++ RS3=2588.65380859375 ++ RS4=5889.67919921875 ++ C1=1.18381771399556E-11 ++ R2=1.23012852668762 ++ C2=5.88680322266555E-08 ++ L5=3.70975021724007E-06 ++ RS5=1.8262939453125 +.ends XXL_7448062603_3m +******** +.subckt XXL_7448063801_1m5 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0020000000949949 ++ ck=2.9528837708348E-11 ++ DC4=1.81107342664411E-12 ++ DL4=1.52490713389852E-07 ++ DR5=136.359634399414 ++ DR6=1262.17468261719 ++ DC3=2.40683558153099E-12 ++ DL3=8.66488214512628E-09 ++ DR3=143.967742919922 ++ DR4=609.906372070313 ++ L1=0.000600735598709434 ++ L2=0.00102119834627956 ++ L3=0.000730740721337497 ++ L4=0.000193675368791446 ++ RS1=6 ++ RS2=517.475830078125 ++ RS3=1116.78527832031 ++ RS4=4681.90576171875 ++ C1=1.46737066941682E-11 ++ R2=0.624236047267914 ++ C2=3.67227634967549E-08 ++ L5=1.21822552046069E-06 ++ RS5=0.940431714057922 +.ends XXL_7448063801_1m5 +******** +.subckt S_7448020680_80m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=1 ++ ck=2.3668475904063E-11 ++ DC4=1.706828053912577E-13 ++ DL4=4.698230228054454E-06 ++ DR5=674.824829101563 ++ DR6=11886.4306640625 ++ DC3=1.04751775789901E-12 ++ DL3=1.91542204319717E-09 ++ DR3=21.6521663665771 ++ DR4=512807040 ++ L1=0.08729947218298912 ++ L2=0.0101475343108177 ++ L3=0.000536222942173481 ++ L4=0.000365290936315432 ++ RS1=50239.140625 ++ RS2=55361.994140625 ++ RS3=40298.8671875 ++ RS4=5075.22265625 ++ C1=1.00810228764696183E-11 ++ R2=28.6605805158615 ++ C2=1.52322865432097E-08 ++ L5=1.36148946694448E-06 ++ RS5=1.43727397918701 +.ends S_7448020680_80m +******** +.subckt S_7448021230_30m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.28640000030398369 ++ ck=2.01574164786085E-11 ++ DC4=1.86840939855187E-13 ++ DL4=1.59136141064664E-06 ++ DR5=704.48291015625 ++ DR6=6556.29541015625 ++ DC3=3.03443589699803E-11 ++ DL3=5.20691649519289E-12 ++ DR3=18.1167163848877 ++ DR4=766605248 ++ L1=0.0208004059202671051 ++ L2=0.00845833602175117 ++ L3=0.00101479911245406 ++ L4=0.00159177230671048 ++ RS1=7904.43017578125 ++ RS2=8743.3896484375 ++ RS3=85064.4453125 ++ RS4=19577.373046875 ++ C1=0.92000004580825E-11 ++ R2=0.104000002145767 ++ C2=5.06184820501076E-07 ++ L5=0.000372471375158057 ++ RS5=302.954345703125 +.ends S_7448021230_30m +******** +.subckt S_7448022010_10m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.08509 ++ ck=1.51552671006E-11 ++ DC4=5.35570069196134E-13 ++ DL4=6.62409661345009E-07 ++ DR5=177.84440612793 ++ DR6=3723.15185546875 ++ DC3=2.21240335079864E-11 ++ DL3=2.08324335559951E-09 ++ DR3=25.7555999755859 ++ DR4=790799680 ++ L1=0.0082831352 ++ L2=0.000232258913456462 ++ L3=0.00022412148246076 ++ L4=0.00299568800255656 ++ RS1=2645.89135742188 ++ RS2=3905.26733398438 ++ RS3=60462.76953125 ++ RS4=7249.16162109375 ++ C1=7.88850842287081E-12 ++ R2=2.64605188369751 ++ C2=2.70506433253104E-07 ++ L5=7.29241946828552E-06 ++ RS5=18.6724090576172 +.ends S_7448022010_10m +******** +.subckt S_7448023005_5m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.040999996647239 ++ ck=1.080952613964013E-12 ++ DC4=1.85547193928826E-12 ++ DL4=2.75392174014778E-07 ++ DR5=7.91325426101685 ++ DR6=3766.0283203125 ++ DC3=1.44351640016249E-11 ++ DL3=1.87662325235514E-11 ++ DR3=20.0794124603271 ++ DR4=573485056 ++ L1=0.00519584168493748 ++ L2=0.000204253798781428 ++ L3=0.000717621645890176 ++ L4=0.0000629422720521688 ++ RS1=1561.64501953125 ++ RS2=10478.921875 ++ RS3=3173.51904296875 ++ RS4=243.744842529297 ++ C1=1.32802503896882E-12 ++ R2=0.516414642333984 ++ C2=1.75105725475078E-08 ++ L5=1.16033824326678E-07 ++ RS5=3.20607089996338 +.ends S_7448023005_5m +******** +.subckt S_7448024503_3m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0206 ++ ck=3.900271480317412E-12 ++ DC4=1.22982657044246E-11 ++ DL4=1.54030630028501E-07 ++ DR5=13915.5234375 ++ DR6=3881.001953125 ++ DC3=1.73222519661564E-10 ++ DL3=4.94894569769144E-09 ++ DR3=7971.07861328125 ++ DR4=4366635 ++ L1=0.002809952709823847 ++ L2=0.0007168641470838338 ++ L3=0.0000966780688334256 ++ L4=6.14096097706351E-06 ++ RS1=967.972229003906 ++ RS2=2600.03564453125 ++ RS3=4833.78271484375 ++ RS4=2245.02856445313 ++ C1=1.06666368446251E-12 ++ R2=0.651606798171997 ++ C2=5.86708866939989E-010 ++ L5=0.0000273303194262553 ++ RS5=72.0766448974609 +.ends S_7448024503_3m +******** +.subckt S_7448025003_2m5 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.00300000002607703 ++ ck=4.5133678816391E-12 ++ DC4=6.34493915740997E-11 ++ DL4=13.15969937194532E-08 ++ DR5=3128.60888671875 ++ DR6=10471.07421875 ++ DC3=2.05417675185914E-13 ++ DL3=2.37918595935582E-09 ++ DR3=274.328552246094 ++ DR4=17580.609375 ++ L1=0.0015502154769124091 ++ L2=0.000812576012220234 ++ L3=0.0001546227570844349 ++ L4=0.0001061843363457592 ++ RS1=388.493408203125 ++ RS2=987.174682617188 ++ RS3=915.368774414063 ++ RS4=4195.36376953125 ++ C1=9.97613064286065E-13 ++ R2=0.805560827255249 ++ C2=14.31705442593072E-14 ++ L5=2.30107197185525E-10 ++ RS5=1.80797374248505 +.ends S_7448025003_2m5 +******** +.subckt S_7448026002_1m5 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0080000000949949 ++ ck=3.23989407231303E-12 ++ DC4=5.1319879742313E-16 ++ DL4=7.69445590031428E-08 ++ DR5=0.180175602436066 ++ DR6=1754.73461914063 ++ DC3=1.54048421154712E-16 ++ DL3=4.0160017533708E-09 ++ DR3=4.79514217376708 ++ DR4=1317.73986816406 ++ L1=0.00118988836109638 ++ L2=0.0002305983025403693 ++ L3=0.000206753182788379 ++ L4=0.0000300147224119852763 ++ RS1=335.088470458984 ++ RS2=270.503509521484 ++ RS3=602.089050292969 ++ RS4=2833.65698242188 ++ C1=1.0156046568651E-12 ++ R2=0.46083676815033 ++ C2=6.94929056521687E-08 ++ L5=1.52263805830444E-06 ++ RS5=1.9443267583847 +.ends S_7448026002_1m5 +******** +.subckt S_7448027001_1m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0060000000949949 ++ ck=3.4854752353251E-12 ++ DC4=4.14999997799641E-14 ++ DL4=5.1646452825102E-08 ++ DR5=66.5085525512695 ++ DR6=1249.89624023438 ++ DC3=5.74410988609178E-14 ++ DL3=2.73839506625961E-09 ++ DR3=149.318984985352 ++ DR4=2838661 ++ L1=0.0009006951487064 ++ L2=0.00025815101354383 ++ L3=0.000050897702603135 ++ L4=0.0000325612896226812 ++ RS1=320.175964355469 ++ RS2=535.458984375 ++ RS3=377.848846435547 ++ RS4=2064.71984863281 ++ C1=1.1106137391217E-12 ++ R2=0.665103912353516 ++ C2=4.02737158569744E-08 ++ L5=1.29639533952286E-06 ++ RS5=1.57858121395111 +.ends S_7448027001_1m +******** +.subckt XL_7448051307_7m 1 2 3 4 +X1 1 2 3 4 CMBNC PARAMS: ++ Rdc=0.0130000002682209 ++ ck=1.29404375669856E-12 ++ DC4=6.80166375650344E-12 ++ DL4=4.51214205895812E-07 ++ DR5=1.7590198516846 ++ DR6=3457.47265625 ++ DC3=5.50737125974498E-12 ++ DL3=2.78807057441099E-08 ++ DR3=1.97621190547943 ++ DR4=164737248 ++ L1=0.0075416963472962 ++ L2=0.000347881024936214 ++ L3=0.00103540430366993 ++ L4=0.000174639615579508 ++ RS1=2931.60400390625 ++ RS2=3059.2822265625 ++ RS3=3576.35083007813 ++ RS4=3537.236328125 ++ C1=8.05642104987005E-12 ++ R2=0.539597749710083 ++ C2=4.17126173601901E-08 ++ L5=1.18381808533741E-06 ++ RS5=1.67514705657959 +.ends XL_7448051307_7m +******** \ No newline at end of file diff --git a/spice/copy/sub/Contrib/Wurth/WE-CMBNiZn.lib b/spice/copy/sub/Contrib/Wurth/WE-CMBNiZn.lib new file mode 100755 index 0000000..a559e4b --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CMBNiZn.lib @@ -0,0 +1,404 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-CMBNiZn +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT COM_IND 1 2 3 4 PARAMS: +L5 N011 N010 {L3} +R50 N011 N010 {Rs3} +C3 N500 N001 {C1} +R500 4 N500 {R2} +L1 4 N012 {L1} +R51 4 N012 {Rs1} +L3 N012 N011 {L2} +R52 N012 N011 {Rs2} +L6 N015 N014 {L3} +R53 N015 N014 {Rs3} +C4 N501 N013 {C1} +R501 3 N501 {R2} +L2 3 N016 {L1} +R54 3 N016 {Rs1} +L4 N016 N015 {L2} +R55 N016 N015 {Rs2} +L8 N014 N013 {L4} +R56 N014 N013 {Rs4} +L7 N010 N001 {L4} +R57 N010 N001 {Rs4} +L9 N001 N007 {L5} +R58 N001 N007 {Rs5} +C50 N001 N007 {C2} +L10 N013 N022 {L5} +R59 N013 N022 {Rs5} +C51 N013 N022 {C2} +L11 N007 N006 {L6} +R60 N007 N006 {Rs6} +C52 N007 N006 {C3} +L12 N022 N021 {L6} +R61 N022 N021 {Rs6} +C53 N022 N021 {C3} +R1 N002 1 {Rdc} +R2 N004 N002 {dR4} +C1 N003 N002 {dC3} +L17 N008 N002 {dL3} +L18 N017 N018 {dL3} +C2 N008 N018 {ck} +R3 N004 N003 {dR3} +R4 N019 N023 {dR3} +C9 N023 N017 {dC3} +R5 N019 N017 {dR4} +L19 N004 N008 {dL3} +L20 N018 N019 {dL3} +R6 N017 2 {Rdc} +R8 N006 N004 {dR6} +C10 N005 N004 {dC4} +L13 N009 N004 {dL4} +L14 N019 N020 {dL4} +C11 N009 N020 {ck} +R9 N006 N005 {dR5} +R10 N021 N024 {dR5} +C12 N024 N019 {dC4} +R11 N021 N019 {dR6} +L15 N006 N009 {dL4} +L16 N020 N021 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K6 L11 L12 1 +K8 L17 L18 L19 L20 0.9999 +K7 L13 L14 L15 L16 0.9999 +.ends COM_IND +***** +.SUBCKT COM_IND23 1 2 3 4 PARAMS: +R_R9 N12325 3 {R2} +R_R8 N13265 N13287 {Rs4} +Kn_K6 L_L11 L_L12 ++ L_L13 L_L14 0.9999 +R_R3 N12571 N12583 {Rs3} +R_R10 N13777 4 {R2} +C_C10 N13029 N12821 {ck} +R_R20 N13215 N13229 {dR4} +L_L11 N12821 N12295 {dL4} +R_R17 N12267 N12273 {dR3} +L_L8 N13265 N13287 {L4} +R_R7 N13287 N13305 {Rs3} +L_L9 N12295 N12307 {L5} +Kn_K4 L_L7 L_L8 1 +R_R2 N12583 N12599 {Rs2} +Kn_K5 L_L9 L_L10 1 +R_R16 N13229 N13249 {dR6} +Kn_K7 L_L15 L_L16 ++ L_L17 L_L18 0.9999 +C_C5 N12273 N12289 {dC4} +L_L6 N13287 N13305 {L3} +L_L7 N12307 N12571 {L4} +R_R6 N13305 N13319 {Rs2} +R_R21 1 N12257 {Rdc} +Kn_K3 L_L5 L_L6 1 +L_L16 N12257 N12799 {dL3} +C_C8 N13215 N13741 {dC3} +L_L18 N13023 N13215 {dL3} +R_R1 N12599 3 {Rs1} +R_R13 N12289 N12295 {dR5} +L_L4 N13305 N13319 {L2} +L_L5 N12571 N12583 {L3} +R_R15 N13755 N13249 {dR5} +R_R5 N13319 4 {Rs1} +R_R18 N12257 N12273 {dR4} +Kn_K2 L_L3 L_L4 1 +R_R19 N13741 N13229 {dR3} +L_L15 N12799 N12273 {dL3} +L_L17 N13229 N13023 {dL3} +L_L3 N12583 N12599 {L2} +R_R11 N12295 N12307 {Rs5} +L_L2 N13319 4 {L1} +C_C4 N13249 N13265 {C2} +L_L10 N13249 N13265 {L5} +Kn_K1 L_L1 L_L2 1 +R_R14 N12273 N12295 {dR6} +C_C6 N13229 N13755 {dC4} +L_L12 N12273 N12821 {dL4} +L_L14 N13029 N13229 {dL4} +L_L1 N12599 3 {L1} +C_C1 N12307 N12325 {C1} +R_R12 N13249 N13265 {Rs5} +C_C2 N13265 N13777 {C1} +R_R22 2 N13215 {Rdc} +C_C9 N13023 N12799 {ck} +R_R4 N12307 N12571 {Rs4} +C_C3 N12295 N12307 {C2} +L_L13 N13249 N13029 {dL4} +C_C7 N12257 N12267 {dC3} +.ends COM_IND23 +***** +.subckt XS_744841330_30u 1 2 3 4 +X1 1 2 3 4 COM_IND PARAMS: ++ L1=0.00002389 ++ L2=0.00000429 ++ L3=0.000001 ++ L4=0.000001 ++ L5=0.00000002526 ++ L6=0.00000001951 ++ C1=0.0000000000008638 ++ C2=0.00000000000173 ++ C3=0.0000000000002182 ++ RS1=2340 ++ RS2=2506 ++ RS3=2254 ++ RS4=88 ++ RS5=0.09 ++ RS6=783 ++ R2=0.054 ++ DL3=0.0000001489 ++ DC3=3.13E-23 ++ DL4=0.00000000085255 ++ DC4=0.00000000000002967 ++ DR3=425 ++ DR4=5517 ++ DR5=127 ++ DR6=164 ++ Rdc=14.665m ++ ck=4pF +.ends XS_744841330_30u +***** +.subckt XS_744841210_0.1m 1 2 3 4 +X1 1 2 3 4 COM_IND PARAMS: ++ L1=0.00006594 ++ L2=0.0000059 ++ L3=0.00000232 ++ L4=0.00000103 ++ L5=0.00000000628 ++ L6=0.00000001156 ++ C1=0.000000000000887951 ++ C2=0.00000000000362 ++ C3=0.00000000000006055 ++ RS1=8033 ++ RS2=5161 ++ RS3=7079 ++ RS4=7651 ++ RS5=372 ++ RS6=858 ++ R2=11 ++ DL3=0.00000038 ++ DC3=3.58E-25 ++ DL4=0.00000000032782 ++ DC4=0.00000000001881 ++ DR3=31 ++ DR4=15181 ++ DR5=1 ++ DR6=4000 ++ Rdc=51m ++ ck=4pF +.ends XS_744841210_0.1m +***** +.subckt XS_744841247_47u 1 2 3 4 +X1 1 2 3 4 COM_IND PARAMS: ++ L1=0.00003889 ++ L2=0.00000429 ++ L3=0.000001 ++ L4=0.000009 ++ L5=0.00000001526 ++ L6=0.00000000726 ++ C1=0.0000000000008638 ++ C2=0.00000000000000473 ++ C3=0.00000000000000923 ++ RS1=4540 ++ RS2=2506 ++ RS3=2254 ++ RS4=288 ++ RS5=300 ++ RS6=80 ++ R2=0.054 ++ DL3=0.00000027 ++ DC3=0.0000000000007 ++ DL4=0.000000001551 ++ DC4=0.000000000000163 ++ DR3=0.48 ++ DR4=11680 ++ DR5=0.78 ++ DR6=7066 ++ Rdc=23.9m ++ ck=4pF +.ends XS_744841247_47u +***** +.subckt S_7448421016_16u 1 2 3 4 +X1 1 2 3 4 COM_IND PARAMS: ++ L1=5u ++ L2=5u ++ L3=3u ++ L4=1.9u ++ L5=8.1n ++ L6=8n ++ C1=1.0p ++ C2=1.05p ++ C3=1f ++ RS1=900 ++ RS2=250 ++ RS3=500 ++ RS4=880 ++ RS5=900 ++ RS6=1100 ++ R2=1.41 ++ DL3=0.000000055 ++ DC3=0.0000000000018 ++ DL4=0.00000000051 ++ DC4=0.00000000000053 ++ DR3=0.48 ++ DR4=2680 ++ DR5=0.78 ++ DR6=866 ++ Rdc=2.7m ++ ck=4pF +.ends S_7448421016_16u +***** +.subckt S_744842565_65u 1 2 3 4 +X1 1 2 3 4 COM_IND PARAMS: ++ L1=0.00002089 ++ L2=0.00001829 ++ L3=0.000003 ++ L4=0.000003 ++ L5=0.0000000126 ++ L6=0.00000001951 ++ C1=0.0000000000011638 ++ C2=0.00000000000063 ++ C3=0.0000000000002182 ++ RS1=2740 ++ RS2=2506 ++ RS3=3254 ++ RS4=508 ++ RS5=500 ++ RS6=100 ++ R2=0.054 ++ DL3=0.00000021 ++ DC3=0.0000000000017 ++ DL4=0.00000000389 ++ DC4=0.00000000000033 ++ DR3=0.48 ++ DR4=8680 ++ DR5=0.1 ++ DR6=1066 ++ Rdc=13m ++ ck=4pF +.ends S_744842565_65u +***** +.subckt S_744842742_42u 1 2 3 4 +X1 1 2 3 4 COM_IND PARAMS: ++ L1=.024m ++ L2=.01m ++ L3=0.7u ++ L4=0.5u ++ L5=12.4n ++ L6=33.4n ++ C1=1p ++ C2=.55p ++ C3=.65f ++ Rs1=2k ++ Rs2=3.8k ++ RS3=1100 ++ RS4=90 ++ RS5=900 ++ RS6=200 ++ R2=1.41 ++ DL3=0.00000013 ++ DC3=0.0000000000015 ++ DL4=0.0000000011 ++ DC4=0.00000000000000173 ++ DR3=0.21 ++ DR4=6680 ++ DR5=385 ++ DR6=1990.66 ++ Rdc=8.1m ++ ck=4pF +.ends S_744842742_42u +***** +.subckt S_744842932_32u 1 2 3 4 +X1 1 2 3 4 COM_IND PARAMS: ++ L1=0.00001089 ++ L2=0.00001029 ++ L3=0.000003 ++ L4=0.000009 ++ L5=0.0000000126 ++ L6=0.00000001951 ++ C1=0.0000000000011638 ++ C2=0.00000000000063 ++ C3=0.0000000000002182 ++ RS1=340 ++ RS2=306 ++ RS3=1254 ++ RS4=2808 ++ RS5=500 ++ RS6=100 ++ R2=0.054 ++ DL3=0.0000001 ++ DC3=0.0000000000021 ++ DL4=0.0000000005 ++ DC4=0.00000000000233 ++ DR3=0.48 ++ DR4=5680 ++ DR5=0.58 ++ DR6=766 ++ Rdc=5.5m ++ ck=4pF +.ends S_744842932_32u +***** +.subckt XS_744841414_14u 1 2 3 4 +X1 1 2 3 4 COM_IND23 PARAMS: ++ L1=1.54u ++ L2=1.23u ++ L3=0.70u ++ L4=9.9u ++ L5=8n ++ C1=800.06f ++ C2=900.02f ++ RS1=666.63 ++ RS2=678.77 ++ RS3=666.33 ++ RS4=740 ++ RS5=336.33 ++ R2=12 ++ DL3=0.000000067 ++ DL4=0.00000000085 ++ DC3=0.0000000000003 ++ DC4=0.000000000000000002 ++ DR3=6 ++ DR4=3101 ++ DR5=10 ++ DR6=350 ++ Rdc=6.043m ++ ck=4pF +.ends XS_744841414_14u +***** +***** +.subckt S_744842311_0.11m 1 2 3 4 +X1 1 2 3 4 COM_IND23 PARAMS: ++ L1=.06m ++ L2=.06m ++ L3=3u ++ L4=9u ++ L5=33.4n ++ C1=1p ++ C2=.65p ++ Rs1=6k ++ Rs2=6k ++ RS3=800 ++ RS4=90 ++ RS5=1600 ++ R2=1.41 ++ DL3=0.00000038 ++ DC3=0.0000000000016 ++ DL4=0.00000000111 ++ DC4=0.00000000000433 ++ DR3=0.48 ++ DR4=11680 ++ DR5=0.58 ++ DR6=1066 ++ Rdc=31m ++ ck=4pF +.ends S_744842311_0.11m diff --git a/spice/copy/sub/Contrib/Wurth/WE-CNSW.lib b/spice/copy/sub/Contrib/Wurth/WE-CNSW.lib new file mode 100755 index 0000000..689467e --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CNSW.lib @@ -0,0 +1,853 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-CNSW +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT CNSW 1 2 3 4 PARAMS: +R_R47 N21893 N21911 {Rs3} +R_R43 N21425 N21441 {Rs2} +R_R4 N22217 N21871 {dR3} +L_L3 N21425 N21441 {L2} +L_L8 N21871 N21893 {L4} +Kn_K1 L_L1 L_L2 1 +R_R37 N21241 3 {R2} +R_R48 N21911 N21925 {Rs2} +R_R44 N21441 3 {Rs1} +C_C4 N21871 N22231 {C1} +L_L1 N21441 3 {L1} +C_C1 N21207 N21217 {dC3} +L_L6 N21893 N21911 {L3} +R_R1 1 N21207 {Rdc} +L_L17 N21207 N21585 {dL3} +R_R49 N21925 4 {Rs1} +Kn_K5 L_L17 L_L18 ++ L_L19 L_L20 0.9999 +R_R3 N21217 N21223 {dR3} +R_R55 N22231 4 {R2} +L_L4 N21911 N21925 {L2} +R_R2 N21207 N21223 {dR4} +L_L19 N21585 N21223 {dL3} +R_R6 2 N21857 {Rdc} +C_C2 N21731 N21585 {ck} +Kn_K4 L_L7 L_L8 1 +L_L2 N21925 4 {L1} +R_R41 N21223 N21413 {Rs4} +L_L7 N21223 N21413 {L4} +R_R5 N21857 N21871 {dR4} +L_L18 N21731 N21857 {dL3} +Kn_K3 L_L5 L_L6 1 +R_R46 N21871 N21893 {Rs4} +R_R42 N21413 N21425 {Rs3} +L_L5 N21413 N21425 {L3} +C_C9 N21857 N22217 {dC3} +L_L20 N21871 N21731 {dL3} +Kn_K2 L_L3 L_L4 1 +C_C3 N21223 N21241 {C1} +.ends CNSW +***** +.subckt 0603_744230121_120ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ DL3=3.21356440083719E-10 ++ DC3=8.12514784156175E-10 ++ DR3=121.365600810607 ++ DR4=67.9989469136311 ++ Rdc=0.175 ++ ck=1.8pF ++ L1=1.03776366835462E-07 ++ L2=2.85677171523081E-07 ++ L3=1.00000000901773E-09 ++ L4=3.79555466759053E-08 ++ C1=2.60105208926701E-16 ++ RS1=6.19761662005791 ++ RS2=260.853288265391 ++ RS3=237.589274315202 ++ RS4=714.407442512723 ++ R2=0.177252883973335 +.ends 0603_744230121_120ohm +***** +.subckt 0603_744230181_180ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ DL3=3.0267438167563E-10 ++ DC3=3.33831866585721E-11 ++ DR3=832.258524528865 ++ DR4=456.856178522626 ++ Rdc=0.2 ++ ck=2.64p ++ L1=1.51800159040882E-08 ++ L2=4.31019180860367E-07 ++ L3=8.07362821331113E-08 ++ L4=5.08654968567098E-08 ++ C1=2.3275544138354E-14 ++ RS1=292.605026922307 ++ RS2=309.909870040185 ++ RS3=181.488732454158 ++ RS4=994.310575635818 ++ R2=458.908496550785 +.ends 0603_744230181_180ohm +***** +.subckt 0603_744230220_22ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ DL3=0.00000000019 ++ DC3=0.00000000012 ++ DR3=124.9 ++ DR4=71.7 ++ Rdc=0.2 ++ ck=2.64p ++ L1=5.34317340558565E-09 ++ L2=8.60115622182272E-08 ++ L3=1.00000000000001E-14 ++ L4=4.14464958795088E-09 ++ C1=2.6021588829417E-15 ++ RS1=227.07018435115 ++ RS2=44.1045008464177 ++ RS3=142.794989197713 ++ RS4=171.457886084178 ++ R2=21.6590097709174 +.ends 0603_744230220_22ohm +***** +.subckt 0603_744230251_250ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=1.78130283754455E-08 ++ L2=7.56550033933199E-07 ++ L3=1.51732881489898E-08 ++ L4=9.25299457255913E-09 ++ C1=8.69848087139472E-14 ++ RS1=6834.45776655021 ++ RS2=669.173532792915 ++ RS3=5737.4458234728 ++ RS4=1483.23981576039 ++ R2=0.69290914169179 ++ DL3=3.09086132419024E-10 ++ DC3=7.51847021856422E-12 ++ DR3=158.699703923207 ++ DR4=180.832117119793 ++ Rdc=0.31 ++ ck=4.77436431106064E-12 +.ends 0603_744230251_250ohm +***** +.subckt 0603_744230450_45ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ DL3=2.30743523631809E-10 ++ DC3=1.87201966401594E-09 ++ DR3=114.9307793754 ++ DR4=55.8672000989 ++ Rdc=0.1 ++ ck=.93p ++ L1=8.06194410104808E-08 ++ L2=7.22820473671359E-08 ++ L3=9.59758487690461E-10 ++ L4=1.24033958470548E-08 ++ C1=1.29346472503743E-16 ++ RS1=80.9681291684029 ++ RS2=18.4208412943615 ++ RS3=70.5917411257508 ++ RS4=222.475102366592 ++ R2=6.10531126153076 +.ends 0603_744230450_45ohm +***** +.subckt 0603_744230900_90ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ DL3=0.00000000028 ++ DC3=0.0000000012 ++ DR3=1124.9 ++ DR4=131.7 ++ Rdc=0.13 ++ ck=1.68p ++ L1=2.17726723091073E-07 ++ L2=6.25188018150591E-09 ++ L3=2.57400654656263E-08 ++ L4=6.68329302271038E-09 ++ C1=4.26112117561339E-16 ++ RS1=171.9721829612 ++ RS2=18.7206073606971 ++ RS3=528.705436547341 ++ RS4=1577.90540608866 ++ R2=2.63697832467138 +.ends 0603_744230900_90ohm +***** +.subckt 0805_744231061_67ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=88.51n ++ L2=62.49n ++ L3=19.28n ++ L4=48.40n ++ C1=15.24p ++ RS1=136.59 ++ RS2=10 ++ RS3=819.22 ++ RS4=3492.3 ++ R2=498.02 ++ dL3=302.14p ++ dC3=6.17p ++ DR3=640.51 ++ DR4=37.32 ++ Rdc=0.14 ++ ck=1.3pF +.ends 0805_744231061_67ohm +***** +.subckt 0805_744231061A_67ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=88.51n ++ L2=62.49n ++ L3=19.28n ++ L4=48.40n ++ C1=15.24p ++ RS1=136.59 ++ RS2=10 ++ RS3=819.22 ++ RS4=3492.3 ++ R2=498.02 ++ dL3=302.14p ++ dC3=6.17p ++ DR3=640.51 ++ DR4=37.32 ++ Rdc=0.14 ++ ck=1.3pF +.ends 0805_744231061A_67ohm +***** +.subckt 0805_744231091_90ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=90.3n ++ L2=34.92n ++ L3=25.56n ++ L4=7.15n ++ C1=0.055p ++ RS1=1086.39 ++ RS2=162.52 ++ RS3=379.56 ++ RS4=409.81 ++ R2=324.66 ++ dL3=395p ++ dC3=0.1p ++ DR3=168.1 ++ DR4=359.47 ++ Rdc=0.18 ++ ck=2.41p +.ends 0805_744231091_90ohm +***** +.subckt 0805_744231091A_90ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=90.3n ++ L2=34.92n ++ L3=25.56n ++ L4=7.15n ++ C1=0.055p ++ RS1=1086.39 ++ RS2=162.52 ++ RS3=379.56 ++ RS4=409.81 ++ R2=324.66 ++ dL3=395p ++ dC3=0.1p ++ DR3=168.1 ++ DR4=359.47 ++ Rdc=0.18 ++ ck=2.41p +.ends 0805_744231091A_90ohm +***** +.subckt 0805_744231121_120ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=256.43n ++ L2=186.53n ++ L3=86.19n ++ L4=36.04n ++ C1=0.0529p ++ RS1=170.67 ++ RS2=27.78 ++ RS3=155.67 ++ RS4=693.55 ++ R2=35.41 ++ dL3=392.5pH ++ dC3=0.01pF ++ DR3=10 ++ DR4=50 ++ Rdc=0.185 ++ ck=1.99pF +.ends 0805_744231121_120ohm +***** +.subckt 0805_744231121A_120ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=256.43n ++ L2=186.53n ++ L3=86.19n ++ L4=36.04n ++ C1=0.0529p ++ RS1=170.67 ++ RS2=27.78 ++ RS3=155.67 ++ RS4=693.55 ++ R2=35.41 ++ dL3=392.5pH ++ dC3=0.01pF ++ DR3=10 ++ DR4=50 ++ Rdc=0.185 ++ ck=1.99pF +.ends 0805_744231121A_120ohm +***** +.subckt 0805_744231181_180ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=263.22n ++ L2=91.45n ++ L3=22.74n ++ L4=33.31n ++ C1=0.009p ++ RS1=273.32 ++ RS2=348.57 ++ RS3=421.97 ++ RS4=506.83 ++ R2=20.07 ++ dL3=411.67p ++ dC3=17.92p ++ DR3=232.39 ++ DR4=528.2 ++ Rdc=0.22 ++ ck=2.33p +.ends 0805_744231181_180ohm +***** +.subckt 0805_744231181A_180ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=263.22n ++ L2=91.45n ++ L3=22.74n ++ L4=33.31n ++ C1=0.009p ++ RS1=273.32 ++ RS2=348.57 ++ RS3=421.97 ++ RS4=506.83 ++ R2=20.07 ++ dL3=411.67p ++ dC3=17.92p ++ DR3=232.39 ++ DR4=528.2 ++ Rdc=0.22 ++ ck=2.33p +.ends 0805_744231181A_180ohm +***** +.subckt 0805_744231261_260ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=469.75n ++ L2=199.99n ++ L3=138.06n ++ L4=32.17n ++ C1=0.014p ++ RS1=264.12 ++ RS2=478.71 ++ RS3=478.71 ++ RS4=478.71 ++ R2=12.92 ++ dL3=874p ++ dC3=0.011p ++ DR3=1 ++ DR4=288 ++ Rdc=0.28 ++ ck=2p +.ends 0805_744231261_260ohm +***** +.subckt 0805_744231261A_260ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=469.75n ++ L2=199.99n ++ L3=138.06n ++ L4=32.17n ++ C1=0.014p ++ RS1=264.12 ++ RS2=478.71 ++ RS3=478.71 ++ RS4=478.71 ++ R2=12.92 ++ dL3=874p ++ dC3=0.011p ++ DR3=1 ++ DR4=288 ++ Rdc=0.28 ++ ck=2p +.ends 0805_744231261A_260ohm +***** +.subckt 0805_744231371_370ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=813.59n ++ L2=258.61n ++ L3=120.61n ++ L4=59.28n ++ C1=0.034p ++ RS1=360.86 ++ RS2=589.54 ++ RS3=589.54 ++ RS4=601.39 ++ R2=13.96 ++ dL3=0.6n ++ dC3=0.07p ++ DR3=10 ++ DR4=118 ++ Rdc=0.38 ++ ck=3.91p +.ends 0805_744231371_370ohm +***** +.subckt 0805_744231371A_370ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=813.59n ++ L2=258.61n ++ L3=120.61n ++ L4=59.28n ++ C1=0.034p ++ RS1=360.86 ++ RS2=589.54 ++ RS3=589.54 ++ RS4=601.39 ++ R2=13.96 ++ dL3=0.6n ++ dC3=0.07p ++ DR3=10 ++ DR4=118 ++ Rdc=0.38 ++ ck=3.91p +.ends 0805_744231371A_370ohm +***** +.subckt 1206_744232090_90ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=404.99n ++ L2=14.03n ++ L3=20.64n ++ L4=0.61n ++ C1=0.136p ++ RS1=196.36 ++ RS2=71.04 ++ RS3=2245.23 ++ RS4=2245.23 ++ R2=197.59 ++ dL3=0.5n ++ dC3=0.07p ++ DR3=10 ++ DR4=78 ++ Rdc=0.16 ++ ck=1.71p +.ends 1206_744232090_90ohm +***** +.subckt 1206_744232090A_90ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=404.99n ++ L2=14.03n ++ L3=20.64n ++ L4=0.61n ++ C1=0.136p ++ RS1=196.36 ++ RS2=71.04 ++ RS3=2245.23 ++ RS4=2245.23 ++ R2=197.59 ++ dL3=0.5n ++ dC3=0.07p ++ DR3=10 ++ DR4=78 ++ Rdc=0.16 ++ ck=1.71p +.ends 1206_744232090A_90ohm +***** +.subckt 1206_744232102_1000ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=1.64u ++ L2=64.03n ++ L3=347.3n ++ L4=133.04n ++ C1=0.1p ++ RS1=1575.61 ++ RS2=1046.84 ++ RS3=1462.2 ++ RS4=1046.84 ++ R2=14.07 ++ dL3=977.65p ++ dC3=7.91p ++ DR3=309.77 ++ DR4=138.01 ++ Rdc=0.45 ++ ck=9.32p +.ends 1206_744232102_1000ohm +***** +.subckt 1206_744232102A_1000ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=1.64u ++ L2=64.03n ++ L3=347.3n ++ L4=133.04n ++ C1=0.1p ++ RS1=1575.61 ++ RS2=1046.84 ++ RS3=1462.2 ++ RS4=1046.84 ++ R2=14.07 ++ dL3=977.65p ++ dC3=7.91p ++ DR3=309.77 ++ DR4=138.01 ++ Rdc=0.45 ++ ck=9.32p +.ends 1206_744232102A_1000ohm +***** +.subckt 1206_744232161_160ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=358.5n ++ L2=140.9n ++ L3=40.57n ++ L4=27.43n ++ C1=0.03p ++ RS1=165.67 ++ RS2=246.51 ++ RS3=931.87 ++ RS4=106.2 ++ R2=172.41 ++ dL3=500p ++ dC3=0.001p ++ DR3=1436.81 ++ DR4=1178.6 ++ Rdc=0.21 ++ ck=2.34p +.ends 1206_744232161_160ohm +***** +.subckt 1206_744232161A_160ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=358.5n ++ L2=140.9n ++ L3=40.57n ++ L4=27.43n ++ C1=0.03p ++ RS1=165.67 ++ RS2=246.51 ++ RS3=931.87 ++ RS4=106.2 ++ R2=172.41 ++ dL3=500p ++ dC3=0.001p ++ DR3=1436.81 ++ DR4=1178.6 ++ Rdc=0.21 ++ ck=2.34p +.ends 1206_744232161A_160ohm +***** +.subckt 1206_744232222_2200ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=3.1u ++ L2=456.9n ++ L3=794.49n ++ L4=530.88n ++ C1=0.08p ++ RS1=2061.24 ++ RS2=2061.24 ++ RS3=1662.57 ++ RS4=1702.13 ++ R2=10.88 ++ dL3=1.2n ++ dC3=2.5p ++ DR3=10 ++ DR4=95 ++ Rdc=0.7 ++ ck=14.34p +.ends 1206_744232222_2200ohm +***** +.subckt 1206_744232222A_2200ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=3.1u ++ L2=456.9n ++ L3=794.49n ++ L4=530.88n ++ C1=0.08p ++ RS1=2061.24 ++ RS2=2061.24 ++ RS3=1662.57 ++ RS4=1702.13 ++ R2=10.88 ++ dL3=1.2n ++ dC3=2.5p ++ DR3=10 ++ DR4=95 ++ Rdc=0.7 ++ ck=14.34p +.ends 1206_744232222A_2200ohm +***** +.subckt 1206_744232222M_2200ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=3.1u ++ L2=456.9n ++ L3=794.49n ++ L4=530.88n ++ C1=0.08p ++ RS1=2061.24 ++ RS2=2061.24 ++ RS3=1662.57 ++ RS4=1702.13 ++ R2=10.88 ++ dL3=1.2n ++ dC3=2.5p ++ DR3=10 ++ DR4=95 ++ Rdc=0.7 ++ ck=14.34p +.ends 1206_744232222M_2200ohm +***** +.subckt 1206_744232261_260ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=69.88n ++ L2=938.9n ++ L3=32.32n ++ L4=13.33n ++ C1=0.06p ++ RS1=423.22 ++ RS2=537.78 ++ RS3=651.87 ++ RS4=992.88 ++ R2=45.99 ++ dL3=740.8p ++ dC3=0.1p ++ DR3=400 ++ DR4=200 ++ Rdc=0.25 ++ ck=3.5p +.ends 1206_744232261_260ohm +***** +.subckt 1206_744232261A_260ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=69.88n ++ L2=938.9n ++ L3=32.32n ++ L4=13.33n ++ C1=0.06p ++ RS1=423.22 ++ RS2=537.78 ++ RS3=651.87 ++ RS4=992.88 ++ R2=45.99 ++ dL3=740.8p ++ dC3=0.1p ++ DR3=400 ++ DR4=200 ++ Rdc=0.25 ++ ck=3.5p +.ends 1206_744232261A_260ohm +***** +.subckt 1206_744232601_600ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=980.39n ++ L2=1u ++ L3=148.04n ++ L4=30.78n ++ C1=0.09p ++ RS1=1404.92 ++ RS2=222.94 ++ RS3=3552.29 ++ RS4=1249.35 ++ R2=2.65 ++ dL3=872.39p ++ dC3=0.869p ++ DR3=81.43 ++ DR4=227 ++ Rdc=0.41 ++ ck=5.48p +.ends 1206_744232601_600ohm +***** +.subckt 1206_744232601A_600ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=980.39n ++ L2=1u ++ L3=148.04n ++ L4=30.78n ++ C1=0.09p ++ RS1=1404.92 ++ RS2=222.94 ++ RS3=3552.29 ++ RS4=1249.35 ++ R2=2.65 ++ dL3=872.39p ++ dC3=0.869p ++ DR3=81.43 ++ DR4=227 ++ Rdc=0.41 ++ ck=5.48p +.ends 1206_744232601A_600ohm +***** +.subckt 1812_744235101_8000ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=0.0000797330260317076 ++ L2=9.88094162242991E-06 ++ L3=1.44068328704984E-06 ++ L4=9.85148481422561E-08 ++ C1=1.3645243390331E-13 ++ RS1=27155.0098359823 ++ RS2=19801.2021163916 ++ RS3=3707.15015579865 ++ RS4=4502.76026046935 ++ R2=0.805434695527514 ++ DL3=0.00000001 ++ DC3=0.0000000000076 ++ DR3=436.759904482883 ++ DR4=390.738116581923 ++ Rdc=1.30857872175911 ++ ck=1.98982670454923E-11 +.ends 1812_744235101_8000ohm +***** +.subckt 1812_744235110_5000ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=8.85047647829296E-06 ++ L2=0.0000034430683879953 ++ L3=3.38096411330201E-08 ++ L4=1.00652585896406E-08 ++ C1=1.31229796204887E-13 ++ RS1=7427.18723080165 ++ RS2=1810.64222257634 ++ RS3=34746.6565929217 ++ RS4=3695.42782092552 ++ R2=216.5 ++ DL3=2.01815820812556E-09 ++ DC3=3.07079198420314E-12 ++ DR3=155.69656586632 ++ DR4=156.010213182894 ++ Rdc=0.501580452433977 ++ ck=2.0478163676467E-11 +.ends 1812_744235110_5000ohm +***** +.subckt 1812_744235220_8000ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=0.0000125216320217548 ++ L2=6.54898754606424E-06 ++ L3=3.16988794176413E-08 ++ L4=5.77278199506278E-08 ++ C1=1.25221813175292E-13 ++ RS1=12209.6414311128 ++ RS2=5886.4259377264 ++ RS3=35052 ++ RS4=1895.91901883094 ++ R2=216.065118673868 ++ DL3=3.21815820812556E-09 ++ DC3=3.07079198420314E-12 ++ DR3=155.69656586632 ++ DR4=206.010213182894 ++ Rdc=1.25158045243397 ++ ck=2.0478163676467E-11 +.ends 1812_744235220_8000ohm +***** +.subckt 1812_744235601_600ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=0.0000008 ++ L2=1.00918818391007E-07 ++ L3=6.74713187330646E-08 ++ L4=9.06669630529321E-09 ++ C1=1.25543915842331E-13 ++ RS1=1440 ++ RS2=746.462802494614 ++ RS3=631.277065514465 ++ RS4=595.93833408099 ++ R2=2.28453043609872 ++ DL3=8.71486162216049E-10 ++ DC3=7.13861411629978E-13 ++ DR3=350.007574955035 ++ DR4=216.761640479245 ++ Rdc=0.09 ++ ck=7.8992687241322E-12 +.ends 1812_744235601_600ohm +***** +.subckt 1812_744235801_800ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=7.25497523126998E-08 ++ L2=8.69343176099444E-07 ++ L3=3.32504748284714E-07 ++ L4=4.44200461773326E-09 ++ C1=1.30888075079623E-13 ++ RS1=222.796562921102 ++ RS2=2020.74697055982 ++ RS3=836.191552474128 ++ RS4=1617.07077919562 ++ R2=4.19037398671819 ++ DL3=1.29077433972439E-09 ++ DC3=9.75947927079038E-14 ++ DR3=114.898321630312 ++ DR4=133.300124119974 ++ Rdc=0.160020622709807 ++ ck=1.52131288040157E-11 +.ends 1812_744235801_800ohm +***** +.subckt 1812_744235900_90ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=0.000000008 ++ L2=1.00087759037915E-07 ++ L3=3.54912711744498E-08 ++ L4=9.8487642227681E-09 ++ C1=1.50590541068679E-14 ++ RS1=5366.19028477718 ++ RS2=199.551788174208 ++ RS3=369.589376742879 ++ RS4=606.815261196718 ++ R2=1.19063066786614 ++ DL3=1.22301162813465E-09 ++ DC3=5.49045546039065E-12 ++ DR3=463.914430187231 ++ DR4=801.208304688174 ++ Rdc=0.0742528369720532 ++ ck=8.66866041980135E-13 +.ends 1812_744235900_90ohm +****************** +.subckt 1206_744232101_6000ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=100u ++ L2=100n ++ L3=50n ++ L4=20n ++ C1=0.2p ++ RS1=50800 ++ RS2=2500 ++ RS3=200 ++ RS4=200 ++ R2=100 ++ dL3=15000p ++ dC3=500p ++ DR3=3000 ++ DR4=2000 ++ Rdc=7 ++ ck=9.32p +.ends 1206_744232101_6000ohm +************ +.subckt 1812_744235251_10000ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=165u ++ L2=100u ++ L3=10u ++ L4=10n ++ C1=0.125p ++ RS1=40000 ++ RS2=1300 ++ RS3=20000 ++ RS4=20000 ++ R2=50 ++ DL3=8n ++ DC3=8p ++ DR3=250 ++ DR4=250 ++ Rdc=1.8 ++ ck=35p +.ends 1812_744235251_10000ohm +***** +.subckt 1812_744235510_3000ohm 1 2 3 4 +X1 1 2 3 4 CNSW PARAMS: ++ L1=0.04m ++ L2=0.04m ++ L3=67n ++ L4=9n ++ C1=0.15p ++ RS1=600 ++ RS2=27000 ++ RS3=40000 ++ RS4=10000 ++ R2=0.25 ++ DL3=6n ++ DC3=13p ++ DR3=365 ++ DR4=5000 ++ Rdc=0.85 ++ ck=25p +.ends 1812_744235510_3000ohm +***** diff --git a/spice/copy/sub/Contrib/Wurth/WE-CNSW_HF.lib b/spice/copy/sub/Contrib/Wurth/WE-CNSW_HF.lib new file mode 100755 index 0000000..8f00f72 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-CNSW_HF.lib @@ -0,0 +1,154 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-CNSW HF +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT CNSWHF 1 2 3 4 PARAMS: +R_R47 N21893 N21911 {Rs3} +R_R43 N21425 N21441 {Rs2} +R_R4 N22217 N21871 {dR3} +L_L3 N21425 N21441 {L2} +L_L8 N21871 N21893 {L4} +Kn_K1 L_L1 L_L2 1 +R_R37 N21241 3 {R2} +R_R48 N21911 N21925 {Rs2} +R_R44 N21441 3 {Rs1} +C_C4 N21871 N22231 {C1} +L_L1 N21441 3 {L1} +C_C1 N21207 N21217 {dC3} +L_L6 N21893 N21911 {L3} +R_R1 1 N21207 {Rdc} +L_L17 N21207 N21585 {dL3} +R_R49 N21925 4 {Rs1} +Kn_K5 L_L17 L_L18 ++ L_L19 L_L20 0.9999 +R_R3 N21217 N21223 {dR3} +R_R55 N22231 4 {R2} +L_L4 N21911 N21925 {L2} +R_R2 N21207 N21223 {dR4} +L_L19 N21585 N21223 {dL3} +R_R6 2 N21857 {Rdc} +C_C2 N21731 N21585 {ck} +Kn_K4 L_L7 L_L8 1 +L_L2 N21925 4 {L1} +R_R41 N21223 N21413 {Rs4} +L_L7 N21223 N21413 {L4} +R_R5 N21857 N21871 {dR4} +L_L18 N21731 N21857 {dL3} +Kn_K3 L_L5 L_L6 1 +R_R46 N21871 N21893 {Rs4} +R_R42 N21413 N21425 {Rs3} +L_L5 N21413 N21425 {L3} +C_C9 N21857 N22217 {dC3} +L_L20 N21871 N21731 {dL3} +Kn_K2 L_L3 L_L4 1 +C_C3 N21223 N21241 {C1} +.ends CNSWHF + ******* +.SUBCKT 0805_744233121_120ohm 1 2 3 4 +X1 1 2 3 4 CNSWHF PARAMS: ++ L1=8.00000000000001e-009 ++ L2=1.79925339212877e-007 ++ L3=6.63649322239021e-008 ++ L4=5.83450032811588e-009 ++ C1=5.51684894769137e-014 ++ Rs1=1741.05155918371 ++ Rs2=212.549482460289 ++ Rs3=488.688963633822 ++ Rs4=317.330962811994 ++ R2=3.13238113177141 ++ dL3=4.98917896272065e-010 ++ dC3=4.96686318546251e-012 ++ dR3=484.521469508698 ++ dR4=997.199948678582 ++ Rdc=0.31 ++ ck=7.70527948525304e-013 +.ends 0805_744233121_120ohm + ******* +.SUBCKT 0504_7442335600_60ohm 1 2 3 4 +X1 1 2 3 4 CNSWHF PARAMS: ++ L1=8.20080273786633e-009 ++ L2=1.34584427660833e-007 ++ L3=1.48025426584176e-008 ++ L4=3e-9 ++ C1=9.07227616542299e-015 ++ Rs1=140.47411946825 ++ Rs2=67.1126466735985 ++ Rs3=352.002895573163 ++ Rs4=143.399231133472 ++ R2=1.63228304262423 ++ dL3=2.70000000000084e-010 ++ dC3=1.05490512357034e-012 ++ dR3=141.912693330686 ++ dR4=18.5692729246812 ++ Rdc=0.171903611525802 ++ ck=9.6298290910808e-012 +.ends 0504_7442335600_60ohm +******* +.SUBCKT 0504_7442335900_90ohm 1 2 3 4 +X1 1 2 3 4 CNSWHF PARAMS: ++ L1=1.74287180653563e-008 ++ L2=1.90945624886655e-007 ++ L3=1.48e-8 ++ L4=3e-009 ++ C1=9.10936547148042e-015 ++ Rs1=143.861231643254 ++ Rs2=179.249147258704 ++ Rs3=411.115533962585 ++ Rs4=612.101638621577 ++ R2=12.7671309676373 ++ dL3=472.39p ++ dC3=0.769p ++ dR3=41.43 ++ dR4=40 ++ Rdc=0.31 ++ ck=1.48p +.ends 0504_7442335900_90ohm + ***** +.SUBCKT 0805_744233670_67ohm 1 2 3 4 +X1 1 2 3 4 CNSWHF PARAMS: ++ L1=8e-9 ++ L2=1.03965078520108e-007 ++ L3=5.15314863498072e-008 ++ L4=5.01970036415237e-009 ++ C1=1.45809726575575e-014 ++ Rs1=1974.62758526815 ++ Rs2=61.0008722307059 ++ Rs3=352 ++ Rs4=129.000000000009 ++ R2=1.06969192478433 ++ dL3=4.18668923581979e-010 ++ dC3=2.86773504891341e-012 ++ dR3=500.929543289747 ++ dR4=130.15628545093 ++ Rdc=0.25 ++ ck=7.49201368989462e-013 +.ends 0805_744233670_67ohm + ***** +.SUBCKT 0805_744233900_90ohm 1 2 3 4 +X1 1 2 3 4 CNSWHF PARAMS: ++ L1=1.01386268060263e-008 ++ L2=1.24219683189412e-007 ++ L3=5.54736496935708e-008 ++ L4=4.71686177909884e-009 ++ C1=3.38968008807148e-014 ++ Rs1=1425.83638350492 ++ Rs2=152.864244869111 ++ Rs3=523.822968137063 ++ Rs4=242.557110773796 ++ R2=0.777808206219933 ++ dL3=4.82291048560715e-010 ++ dC3=7.54540952966445e-012 ++ dR3=501 ++ dR4=1100 ++ Rdc=0.31 ++ ck=8.10041154972036e-013 +.ends 0805_744233900_90ohm + + diff --git a/spice/copy/sub/Contrib/Wurth/WE-DCT.lib b/spice/copy/sub/Contrib/Wurth/WE-DCT.lib new file mode 100755 index 0000000..eb3eab6 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-DCT.lib @@ -0,0 +1,286 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Double Choke with Toroidal Core +* Matchcode: WE-DCT +* Library Type: +* Version: version +* Created/modified by: Fredo +* Date and Time : 2/1/2019 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt SH_744851016_0.16u 1 2 3 4 PARAMS: ++ Cww=5.47p ++ Rp1=448.31 ++ Cp1=2.69p ++ Lp1=0.15u ++ Rp2=448.31 ++ Cp2=2.69p ++ Lp2=0.15u ++ RDC1=0.0034 ++ RDC2=0.0034 ++ K=0.790569415042095 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_744851027_0.27u 1 2 3 4 PARAMS: ++ Cww=5.69p ++ Rp1=484.21 ++ Cp1=2.9p ++ Lp1=0.23u ++ Rp2=484.21 ++ Cp2=2.9p ++ Lp2=0.23u ++ RDC1=0.004 ++ RDC2=0.004 ++ K=0.805076485899413 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_744851039_0.39u 1 2 3 4 PARAMS: ++ Cww=9.85p ++ Rp1=560.46 ++ Cp1=3.58p ++ Lp1=0.34u ++ Rp2=560.46 ++ Cp2=3.58p ++ Lp2=0.34u ++ RDC1=0.0047 ++ RDC2=0.0047 ++ K=0.847318545736323 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_744851100_1u 1 2 3 4 PARAMS: ++ Cww=26.77p ++ Rp1=979.21 ++ Cp1=4.21p ++ Lp1=0.93u ++ Rp2=979.21 ++ Cp2=4.21p ++ Lp2=0.93u ++ RDC1=0.0074 ++ RDC2=0.0074 ++ K=0.888819441731559 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_744851102_100u 1 2 3 4 PARAMS: ++ Cww=83.4p ++ Rp1=12038.43 ++ Cp1=6.01p ++ Lp1=98.69u ++ Rp2=12038.43 ++ Cp2=6.01p ++ Lp2=98.69u ++ RDC1=0.265 ++ RDC2=0.265 ++ K=0.989696923305312 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_744851220_2.2u 1 2 3 4 PARAMS: ++ Cww=24.5p ++ Rp1=957.02 ++ Cp1=4.22p ++ Lp1=1.86u ++ Rp2=957.02 ++ Cp2=4.22p ++ Lp2=1.86u ++ RDC1=0.0074 ++ RDC2=0.0074 ++ K=0.939051746081217 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_744851221_22u 1 2 3 4 PARAMS: ++ Cww=53.07p ++ Rp1=3820.23 ++ Cp1=6.74p ++ Lp1=19.85u ++ Rp2=3820.23 ++ Cp2=6.74p ++ Lp2=19.85u ++ RDC1=0.034 ++ RDC2=0.034 ++ K=0.983962305264698 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_744851330_3.3u 1 2 3 4 PARAMS: ++ Cww=27.7p ++ Rp1=1315.27 ++ Cp1=5.25p ++ Lp1=2.82u ++ Rp2=1315.27 ++ Cp2=5.25p ++ Lp2=2.82u ++ RDC1=0.009 ++ RDC2=0.009 ++ K=0.955050371509907 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_744851471_47u 1 2 3 4 PARAMS: ++ Cww=63.16p ++ Rp1=6139.47 ++ Cp1=5.56p ++ Lp1=42.39u ++ Rp2=6139.47 ++ Cp2=5.56p ++ Lp2=42.39u ++ RDC1=0.13 ++ RDC2=0.13 ++ K=0.988228589285319 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_7448510091_91n 1 2 3 4 PARAMS: ++ Cww=3.4p ++ Rp1=431.01 ++ Cp1=2.17p ++ Lp1=0.075u ++ Rp2=431.01 ++ Cp2=2.17p ++ Lp2=0.075u ++ RDC1=0.0028 ++ RDC2=0.0028 ++ K=0.671229804574745 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt SH_744851470_4.7u 1 2 3 4 PARAMS: ++ Cww=31.6p ++ Rp1=1745 ++ Cp1=6.15p ++ Lp1=4.25u ++ Rp2=1756 ++ Cp2=6.22p ++ Lp2=4.28u ++ RDC1=0.0103 ++ RDC2=0.0103 ++ K=0.963702964743452 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** diff --git a/spice/copy/sub/Contrib/Wurth/WE-DD.lib b/spice/copy/sub/Contrib/Wurth/WE-DD.lib new file mode 100755 index 0000000..575b2a4 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-DD.lib @@ -0,0 +1,639 @@ + + +.SUBCKT 7448700015 1 2 3 4 +L1 4 1 1.27122123005E-06 Ipk=8.6 Rser = 0.014750000089407 Rpar =3222.084477671 Cpar = 4.951310638861E-12 +L2 3 2 1.27122123005E-06 Ipk=8.6 Rser = 0.014750000089407 Rpar =3222.084477671 Cpar = 4.951310638861E-12 +C1 3 4 0.000000000007693 +C2 1 2 0.000000000007693 +k L1 L2 0.959440559585571 +.ENDS 7448700015 + + +.SUBCKT 744870003 1 2 3 4 +L1 4 1 2.80417209167E-06 Ipk=7.1 Rser = 1.89999993890524E-02 Rpar =5382.339685984 Cpar = 7.844809681588E-12 +L2 3 2 2.80417209167E-06 Ipk=7.1 Rser = 1.89999993890524E-02 Rpar =5382.339685984 Cpar = 7.844809681588E-12 +C1 3 4 0.00000000001087 +C2 1 2 0.00000000001087 +k L1 L2 0.949579831963951 +.ENDS 744870003 + + +.SUBCKT 744870004 1 2 3 4 +L1 4 1 3.612400361744E-06 Ipk=3.6 Rser = 1.99999995529652E-02 Rpar =7101.347013185 Cpar = 1.0877274927613E-11 +L2 3 2 3.612400361744E-06 Ipk=3.6 Rser = 1.99999995529652E-02 Rpar =7101.347013185 Cpar = 1.0877274927613E-11 +C1 3 4 0.00000000001509 +C2 1 2 0.00000000001509 +k L1 L2 0.961492176542446 +.ENDS 744870004 + + +.SUBCKT 744870006 1 2 3 4 +L1 4 1 5.692951549774E-06 Ipk=3.2 Rser = 2.57500004954636E-02 Rpar =10061.52839868 Cpar = 1.4121788277862E-11 +L2 3 2 5.692951549774E-06 Ipk=3.2 Rser = 2.57500004954636E-02 Rpar =10061.52839868 Cpar = 1.4121788277862E-11 +C1 3 4 0.00000000001835 +C2 1 2 0.00000000001835 +k L1 L2 0.978478093287351 +.ENDS 744870006 + + +.SUBCKT 744870100 1 2 3 4 +L1 4 1 9.326342545728E-06 Ipk=2.7 Rser = 3.70000004768372E-02 Rpar =16815.56073978 Cpar = 9.528438992978E-12 +L2 3 2 9.326342545728E-06 Ipk=2.7 Rser = 3.70000004768372E-02 Rpar =16815.56073978 Cpar = 9.528438992978E-12 +C1 3 4 0.00000000001631 +C2 1 2 0.00000000001631 +k L1 L2 0.954787233525386 +.ENDS 744870100 + + +.SUBCKT 744870101 1 2 3 4 +L1 4 1 8.374741809743E-05 Ipk=1.4 Rser = 0.217000000178814 Rpar =40646.06015403 Cpar = 3.565143913824E-11 +L2 3 2 8.374741809743E-05 Ipk=1.4 Rser = 0.217000000178814 Rpar =40646.06015403 Cpar = 3.565143913824E-11 +C1 3 4 0.00000000002686 +C2 1 2 0.00000000002686 +k L1 L2 0.951572062174784 +.ENDS 744870101 + + +.SUBCKT 744870220 1 2 3 4 +L1 4 1 1.966833504973E-05 Ipk=2.45 Rser = 6.10000006854534E-02 Rpar =20416.76173605 Cpar = 2.154489116668E-11 +L2 3 2 1.966833504973E-05 Ipk=2.45 Rser = 6.10000006854534E-02 Rpar =20416.76173605 Cpar = 2.154489116668E-11 +C1 3 4 0.00000000002065 +C2 1 2 0.00000000002065 +k L1 L2 0.959947183989084 +.ENDS 744870220 + + +.SUBCKT 744870221 1 2 3 4 +L1 4 1 1.847367536363E-04 Ipk=0.9 Rser = 0.452000007033348 Rpar =44970.70312592 Cpar = 4.805567458023E-11 +L2 3 2 1.847367536363E-04 Ipk=0.9 Rser = 0.452000007033348 Rpar =44970.70312592 Cpar = 4.805567458023E-11 +C1 3 4 0.00000000003547 +C2 1 2 0.00000000003547 +k L1 L2 0.961599538237512 +.ENDS 744870221 + + +.SUBCKT 744870470 1 2 3 4 +L1 4 1 3.788594480847E-05 Ipk=1.45 Rser = 0.105750001966953 Rpar =32122.07459394 Cpar = 3.511039719801E-11 +L2 3 2 3.788594480847E-05 Ipk=1.45 Rser = 0.105750001966953 Rpar =32122.07459394 Cpar = 3.511039719801E-11 +C1 3 4 0.00000000002437 +C2 1 2 0.00000000002437 +k L1 L2 0.960083064394537 +.ENDS 744870470 + + +.SUBCKT 744870471 1 2 3 4 +L1 4 1 4.118554999624E-04 Ipk=0.7 Rser = 0.979749977588654 Rpar =58843.19082114 Cpar = 5.091881570195E-11 +L2 3 2 4.118554999624E-04 Ipk=0.7 Rser = 0.979749977588654 Rpar =58843.19082114 Cpar = 5.091881570195E-11 +C1 3 4 0.00000000003974 +C2 1 2 0.00000000003974 +k L1 L2 0.956139379483666 +.ENDS 744870471 + + +.SUBCKT 744870680 1 2 3 4 +L1 4 1 5.773600099531E-05 Ipk=1.35 Rser = 0.154500000178814 Rpar =45061.65124881 Cpar = 3.245509896857E-11 +L2 3 2 5.773600099531E-05 Ipk=1.35 Rser = 0.154500000178814 Rpar =45061.65124881 Cpar = 3.245509896857E-11 +C1 3 4 0.00000000002324 +C2 1 2 0.00000000002324 +k L1 L2 0.940892640994621 +.ENDS 744870680 + + +.SUBCKT 7448709022 1 2 3 4 +L1 4 1 2.04254489984E-06 Ipk=4.1 Rser = 1.67500004172325E-02 Rpar =4571.89909972 Cpar = 4.377137093905E-12 +L2 3 2 2.04254489984E-06 Ipk=4.1 Rser = 1.67500004172325E-02 Rpar =4571.89909972 Cpar = 4.377137093905E-12 +C1 3 4 0.000000000015397 +C2 1 2 0.000000000015397 +k L1 L2 0.93166089804381 +.ENDS 7448709022 + + +.SUBCKT 7448709033 1 2 3 4 +L1 4 1 2.871069399387E-06 Ipk=3.7 Rser = 0.018499999307096 Rpar =5734.002646107 Cpar = 4.826841480055E-12 +L2 3 2 2.871069399387E-06 Ipk=3.7 Rser = 0.018499999307096 Rpar =5734.002646107 Cpar = 4.826841480055E-12 +C1 3 4 0.000000000016758 +C2 1 2 0.000000000016758 +k L1 L2 0.948495190413777 +.ENDS 7448709033 + + +.SUBCKT 7448709047 1 2 3 4 +L1 4 1 3.653348053149E-06 Ipk=3.6 Rser = 0.019749999511987 Rpar =7323.889458193 Cpar = 6.320129473245E-12 +L2 3 2 3.653348053149E-06 Ipk=3.6 Rser = 0.019749999511987 Rpar =7323.889458193 Cpar = 6.320129473245E-12 +C1 3 4 0.000000000017045 +C2 1 2 0.000000000017045 +k L1 L2 0.924393723985322 +.ENDS 7448709047 + + +.SUBCKT 7448709068 1 2 3 4 +L1 4 1 6.044956452362E-06 Ipk=3.3 Rser = 2.27500000037253E-02 Rpar =8686.592099699 Cpar = 1.0370323770498E-11 +L2 3 2 6.044956452362E-06 Ipk=3.3 Rser = 2.27500000037253E-02 Rpar =8686.592099699 Cpar = 1.0370323770498E-11 +C1 3 4 0.000000000022053 +C2 1 2 0.000000000022053 +k L1 L2 0.957483236357168 +.ENDS 7448709068 + + +.SUBCKT 7448709100 1 2 3 4 +L1 4 1 9.092163844674E-06 Ipk=3.2 Rser = 3.20000001229346E-02 Rpar =15108.50684971 Cpar = 4.809452174944E-12 +L2 3 2 9.092163844674E-06 Ipk=3.2 Rser = 3.20000001229346E-02 Rpar =15108.50684971 Cpar = 4.809452174944E-12 +C1 3 4 0.000000000019605 +C2 1 2 0.000000000019605 +k L1 L2 0.965028354684641 +.ENDS 7448709100 + + +.SUBCKT 7448709220 1 2 3 4 +L1 4 1 1.867311530234E-05 Ipk=3.5 Rser = 6.35000001639128E-02 Rpar =22274.55537681 Cpar = 1.0192199908148E-11 +L2 3 2 1.867311530234E-05 Ipk=3.5 Rser = 6.35000001639128E-02 Rpar =22274.55537681 Cpar = 1.0192199908148E-11 +C1 3 4 0.000000000027985 +C2 1 2 0.000000000027985 +k L1 L2 0.970093458055336 +.ENDS 7448709220 + + +.SUBCKT 7448709330 1 2 3 4 +L1 4 1 2.881007759381E-05 Ipk=2 Rser = 8.15000012516975E-02 Rpar =24284.43136206 Cpar = 2.100908036781E-11 +L2 3 2 2.881007759381E-05 Ipk=2 Rser = 8.15000012516975E-02 Rpar =24284.43136206 Cpar = 2.100908036781E-11 +C1 3 4 0.00000000003237 +C2 1 2 0.00000000003237 +k L1 L2 0.969081540939246 +.ENDS 7448709330 + + +.SUBCKT 7448709470 1 2 3 4 +L1 4 1 3.947609509549E-05 Ipk=1.9 Rser = 0.106000000610948 Rpar =25379.79072803 Cpar = 3.525875980975E-11 +L2 3 2 3.947609509549E-05 Ipk=1.9 Rser = 0.106000000610948 Rpar =25379.79072803 Cpar = 3.525875980975E-11 +C1 3 4 0.000000000032925 +C2 1 2 0.000000000032925 +k L1 L2 0.970071567724498 +.ENDS 7448709470 + + +.SUBCKT 744871004 1 2 3 4 +L1 4 1 3.73454586566E-06 Ipk=3 Rser = 2.17499998398125E-02 Rpar =6466.134965155 Cpar = 1.0474822618877E-11 +L2 3 2 3.73454586566E-06 Ipk=3 Rser = 2.17499998398125E-02 Rpar =6466.134965155 Cpar = 1.0474822618877E-11 +C1 3 4 0.000000000008435 +C2 1 2 0.000000000008435 +k L1 L2 0.923497267759563 +.ENDS 744871004 + + +.SUBCKT 744871006 1 2 3 4 +L1 4 1 5.912058604035E-06 Ipk=2.8 Rser = 0.029250000603497 Rpar =9328.218597861 Cpar = 1.3421191062565E-11 +L2 3 2 5.912058604035E-06 Ipk=2.8 Rser = 0.029250000603497 Rpar =9328.218597861 Cpar = 1.3421191062565E-11 +C1 3 4 0.00000000001186 +C2 1 2 0.00000000001186 +k L1 L2 0.932857144336311 +.ENDS 744871006 + + +.SUBCKT 744871101 1 2 3 4 +L1 4 1 7.872494041094E-05 Ipk=1.5 Rser = 0.254249997437 Rpar =68675.31663075 Cpar = 2.305282500058E-11 +L2 3 2 7.872494041094E-05 Ipk=1.5 Rser = 0.254249997437 Rpar =68675.31663075 Cpar = 2.305282500058E-11 +C1 3 4 0.00000000001908 +C2 1 2 0.00000000001908 +k L1 L2 0.933112129244154 +.ENDS 744871101 + + +.SUBCKT 744871121 1 2 3 4 +L1 4 1 1.1105196158214E-04 Ipk=1.4 Rser = 0.310499995946884 Rpar =54306.65346327 Cpar = 2.523936262956E-11 +L2 3 2 1.1105196158214E-04 Ipk=1.4 Rser = 0.310499995946884 Rpar =54306.65346327 Cpar = 2.523936262956E-11 +C1 3 4 0.00000000002089 +C2 1 2 0.00000000002089 +k L1 L2 0.938142673294376 +.ENDS 744871121 + + +.SUBCKT 744871151 1 2 3 4 +L1 4 1 1.315687932159E-04 Ipk=1.2 Rser = 0.386999994516373 Rpar =73779.48903859 Cpar = 2.583148004533E-11 +L2 3 2 1.315687932159E-04 Ipk=1.2 Rser = 0.386999994516373 Rpar =73779.48903859 Cpar = 2.583148004533E-11 +C1 3 4 0.00000000002127 +C2 1 2 0.00000000002127 +k L1 L2 0.94355070032694 +.ENDS 744871151 + + +.SUBCKT 744871220 1 2 3 4 +L1 4 1 1.83534998017E-05 Ipk=1.85 Rser = 6.65000006556511E-02 Rpar =22638.73967817 Cpar = 1.511440936641E-11 +L2 3 2 1.83534998017E-05 Ipk=1.85 Rser = 6.65000006556511E-02 Rpar =22638.73967817 Cpar = 1.511440936641E-11 +C1 3 4 0.00000000001151 +C2 1 2 0.00000000001151 +k L1 L2 0.916852926963767 +.ENDS 744871220 + + +.SUBCKT 744871221 1 2 3 4 +L1 4 1 0.00018084576967 Ipk=0.84 Rser = 0.543250001966953 Rpar =59949.17070077 Cpar = 2.232455555177E-11 +L2 3 2 0.00018084576967 Ipk=0.84 Rser = 0.543250001966953 Rpar =59949.17070077 Cpar = 2.232455555177E-11 +C1 3 4 0.00000000002063 +C2 1 2 0.00000000002063 +k L1 L2 0.925113464520109 +.ENDS 744871221 + + +.SUBCKT 744871330 1 2 3 4 +L1 4 1 2.742134037793E-05 Ipk=1.2 Rser = 0.10050000064075 Rpar =37975.78013716 Cpar = 1.575831604781E-11 +L2 3 2 2.742134037793E-05 Ipk=1.2 Rser = 0.10050000064075 Rpar =37975.78013716 Cpar = 1.575831604781E-11 +C1 3 4 0.00000000001009 +C2 1 2 0.00000000001009 +k L1 L2 0.930766843975673 +.ENDS 744871330 + + +.SUBCKT 744871470 1 2 3 4 +L1 4 1 3.857634631342E-05 Ipk=1.1 Rser = 0.152000002563 Rpar =34885.54369855 Cpar = 2.222568355332E-11 +L2 3 2 3.857634631342E-05 Ipk=1.1 Rser = 0.152000002563 Rpar =34885.54369855 Cpar = 2.222568355332E-11 +C1 3 4 0.0000000000126 +C2 1 2 0.0000000000126 +k L1 L2 0.925190486042731 +.ENDS 744871470 + + +.SUBCKT 744873001 1 2 3 4 +L1 4 1 1.326037918037E-06 Ipk=6.25 Rser = 1.25000001862645E-02 Rpar =3179.980596959 Cpar = 3.69693462104E-12 +L2 3 2 1.326037918037E-06 Ipk=6.25 Rser = 1.25000001862645E-02 Rpar =3179.980596959 Cpar = 3.69693462104E-12 +C1 3 4 0.000000000011968 +C2 1 2 0.000000000011968 +k L1 L2 0.973492379672641 +.ENDS 744873001 + + +.SUBCKT 744873002 1 2 3 4 +L1 4 1 1.918664789395E-06 Ipk=6 Rser = 1.82499997317791E-02 Rpar =4235.211415115 Cpar = 4.625030347934E-12 +L2 3 2 1.918664789395E-06 Ipk=6 Rser = 1.82499997317791E-02 Rpar =4235.211415115 Cpar = 4.625030347934E-12 +C1 3 4 0.000000000019521 +C2 1 2 0.000000000019521 +k L1 L2 0.970918155773269 +.ENDS 744873002 + + +.SUBCKT 744873003 1 2 3 4 +L1 4 1 2.896370793236E-06 Ipk=5.14 Rser = 1.70000004582107E-02 Rpar =5723.951563496 Cpar = 5.152783352594E-12 +L2 3 2 2.896370793236E-06 Ipk=5.14 Rser = 1.70000004582107E-02 Rpar =5723.951563496 Cpar = 5.152783352594E-12 +C1 3 4 0.000000000013548 +C2 1 2 0.000000000013548 +k L1 L2 0.947466007467791 +.ENDS 744873003 + + +.SUBCKT 744873004 1 2 3 4 +L1 4 1 4.571914179852E-06 Ipk=4.87 Rser = 2.24999999627471E-02 Rpar =8435.054138396 Cpar = 6.778913148162E-12 +L2 3 2 4.571914179852E-06 Ipk=4.87 Rser = 2.24999999627471E-02 Rpar =8435.054138396 Cpar = 6.778913148162E-12 +C1 3 4 0.000000000021102 +C2 1 2 0.000000000021102 +k L1 L2 0.949351193582894 +.ENDS 744873004 + + +.SUBCKT 744873100 1 2 3 4 +L1 4 1 8.513877592868E-06 Ipk=4.2 Rser = 3.54999992996454E-02 Rpar =12583.82463009 Cpar = 1.0016172539864E-11 +L2 3 2 8.513877592868E-06 Ipk=4.2 Rser = 3.54999992996454E-02 Rpar =12583.82463009 Cpar = 1.0016172539864E-11 +C1 3 4 0.000000000041216 +C2 1 2 0.000000000041216 +k L1 L2 0.961139368819532 +.ENDS 744873100 + + +.SUBCKT 744873101 1 2 3 4 +L1 4 1 8.27768210747E-05 Ipk=1.38 Rser = 0.232749998569489 Rpar =72334.68788369 Cpar = 1.409239864408E-11 +L2 3 2 8.27768210747E-05 Ipk=1.38 Rser = 0.232749998569489 Rpar =72334.68788369 Cpar = 1.409239864408E-11 +C1 3 4 0.000000000110259 +C2 1 2 0.000000000110259 +k L1 L2 0.98291435820526 +.ENDS 744873101 + + +.SUBCKT 744873150 1 2 3 4 +L1 4 1 1.343905101848E-05 Ipk=3.3 Rser = 4.42500002682209E-02 Rpar =18573.85180638 Cpar = 1.0657424319299E-11 +L2 3 2 1.343905101848E-05 Ipk=3.3 Rser = 4.42500002682209E-02 Rpar =18573.85180638 Cpar = 1.0657424319299E-11 +C1 3 4 0.000000000044002 +C2 1 2 0.000000000044002 +k L1 L2 0.971622221204837 +.ENDS 744873150 + + +.SUBCKT 744873330 1 2 3 4 +L1 4 1 0.000029765153975 Ipk=2.25 Rser = 9.27499998360872E-02 Rpar =33295.18594266 Cpar = 1.3158260549498E-11 +L2 3 2 0.000029765153975 Ipk=2.25 Rser = 9.27499998360872E-02 Rpar =33295.18594266 Cpar = 1.3158260549498E-11 +C1 3 4 0.000000000096042 +C2 1 2 0.000000000096042 +k L1 L2 0.991448267910977 +.ENDS 744873330 + + +.SUBCKT 744873470 1 2 3 4 +L1 4 1 3.930147682288E-05 Ipk=2.02 Rser = 0.105999998748302 Rpar =34850.99124481 Cpar = 1.2284197732004E-11 +L2 3 2 3.930147682288E-05 Ipk=2.02 Rser = 0.105999998748302 Rpar =34850.99124481 Cpar = 1.2284197732004E-11 +C1 3 4 0.000000000085902 +C2 1 2 0.000000000085902 +k L1 L2 0.98720524709673 +.ENDS 744873470 + + +.SUBCKT 744873680 1 2 3 4 +L1 4 1 5.518804013847E-05 Ipk=1.66 Rser = 0.163499999791384 Rpar =76318.8455852 Cpar = 1.228415302188E-11 +L2 3 2 5.518804013847E-05 Ipk=1.66 Rser = 0.163499999791384 Rpar =76318.8455852 Cpar = 1.228415302188E-11 +C1 3 4 0.000000000078195 +C2 1 2 0.000000000078195 +k L1 L2 0.970331864576172 +.ENDS 744873680 + + +.SUBCKT 744874001 1 2 3 4 +L1 4 1 1.480304877396E-06 Ipk=5.85 Rser = 1.25750000588596E-02 Rpar =3588.593577704 Cpar = 3.43458631932E-12 +L2 3 2 1.480304877396E-06 Ipk=5.85 Rser = 1.25750000588596E-02 Rpar =3588.593577704 Cpar = 3.43458631932E-12 +C1 3 4 0.00000000001433 +C2 1 2 0.00000000001433 +k L1 L2 0.967824967992805 +.ENDS 744874001 + + +.SUBCKT 744874002 1 2 3 4 +L1 4 1 1.983532843425E-06 Ipk=5.5 Rser = 1.60000002942979E-02 Rpar =4371.841321223 Cpar = 4.538141294918E-12 +L2 3 2 1.983532843425E-06 Ipk=5.5 Rser = 1.60000002942979E-02 Rpar =4371.841321223 Cpar = 4.538141294918E-12 +C1 3 4 0.000000000012942 +C2 1 2 0.000000000012942 +k L1 L2 0.967543859162966 +.ENDS 744874002 + + +.SUBCKT 744874003 1 2 3 4 +L1 4 1 2.658542862975E-06 Ipk=4.91 Rser = 0.017750000115484 Rpar =5182.94430527 Cpar = 5.459005654292E-12 +L2 3 2 2.658542862975E-06 Ipk=4.91 Rser = 0.017750000115484 Rpar =5182.94430527 Cpar = 5.459005654292E-12 +C1 3 4 0.000000000018867 +C2 1 2 0.000000000018867 +k L1 L2 0.977743431537725 +.ENDS 744874003 + + +.SUBCKT 744874004 1 2 3 4 +L1 4 1 3.577820387445E-06 Ipk=4.22 Rser = 2.14999997988343E-02 Rpar =7252.217154838 Cpar = 4.787769338256E-12 +L2 3 2 3.577820387445E-06 Ipk=4.22 Rser = 2.14999997988343E-02 Rpar =7252.217154838 Cpar = 4.787769338256E-12 +C1 3 4 0.000000000020012 +C2 1 2 0.000000000020012 +k L1 L2 0.971647687479421 +.ENDS 744874004 + + +.SUBCKT 744874006 1 2 3 4 +L1 4 1 5.819272506529E-06 Ipk=3.9 Rser = 2.85000000149012E-02 Rpar =10116.401455619 Cpar = 6.030296345694E-12 +L2 3 2 5.819272506529E-06 Ipk=3.9 Rser = 2.85000000149012E-02 Rpar =10116.401455619 Cpar = 6.030296345694E-12 +C1 3 4 0.000000000025762 +C2 1 2 0.000000000025762 +k L1 L2 0.967054814110566 +.ENDS 744874006 + + +.SUBCKT 744874101 1 2 3 4 +L1 4 1 8.329460529805E-05 Ipk=1.2 Rser = 0.261249996721745 Rpar =72707.1601373 Cpar = 8.140489777278E-12 +L2 3 2 8.329460529805E-05 Ipk=1.2 Rser = 0.261249996721745 Rpar =72707.1601373 Cpar = 8.140489777278E-12 +C1 3 4 0.000000000116482 +C2 1 2 0.000000000116482 +k L1 L2 0.989836155124135 +.ENDS 744874101 + + +.SUBCKT 744874220 1 2 3 4 +L1 4 1 1.875592922927E-05 Ipk=2.47 Rser = 6.82500004768372E-02 Rpar =32689.83553238 Cpar = 6.433632078578E-12 +L2 3 2 1.875592922927E-05 Ipk=2.47 Rser = 6.82500004768372E-02 Rpar =32689.83553238 Cpar = 6.433632078578E-12 +C1 3 4 0.000000000051575 +C2 1 2 0.000000000051575 +k L1 L2 0.983396296444086 +.ENDS 744874220 + + +.SUBCKT 744874470 1 2 3 4 +L1 4 1 3.879437797437E-05 Ipk=1.8 Rser = 0.127999998629093 Rpar =48834.09303325 Cpar = 6.610644800184E-12 +L2 3 2 3.879437797437E-05 Ipk=1.8 Rser = 0.127999998629093 Rpar =48834.09303325 Cpar = 6.610644800184E-12 +C1 3 4 0.000000000030316 +C2 1 2 0.000000000030316 +k L1 L2 0.941562519798931 +.ENDS 744874470 + + +.SUBCKT 744877001 1 2 3 4 +L1 4 1 1.483081091204E-06 Ipk=4.7 Rser = 0.02625000057742 Rpar =3735.482360635 Cpar = 4.157668652089E-12 +L2 3 2 1.483081091204E-06 Ipk=4.7 Rser = 0.02625000057742 Rpar =3735.482360635 Cpar = 4.157668652089E-12 +C1 3 4 0.00000000000494 +C2 1 2 0.00000000000494 +k L1 L2 0.968553458367985 +.ENDS 744877001 + + +.SUBCKT 744877002 1 2 3 4 +L1 4 1 2.031508130452E-06 Ipk=4.2 Rser = 3.05000012740493E-02 Rpar =4399.661140784 Cpar = 5.306931952009E-12 +L2 3 2 2.031508130452E-06 Ipk=4.2 Rser = 3.05000012740493E-02 Rpar =4399.661140784 Cpar = 5.306931952009E-12 +C1 3 4 0.00000000000635 +C2 1 2 0.00000000000635 +k L1 L2 0.912499999006589 +.ENDS 744877002 + + +.SUBCKT 744877003 1 2 3 4 +L1 4 1 3.24681399793E-06 Ipk=3.7 Rser = 4.17499989271164E-02 Rpar =6729.932531648 Cpar = 6.276574117184E-12 +L2 3 2 3.24681399793E-06 Ipk=3.7 Rser = 4.17499989271164E-02 Rpar =6729.932531648 Cpar = 6.276574117184E-12 +C1 3 4 0.00000000000775 +C2 1 2 0.00000000000775 +k L1 L2 0.955801103257612 +.ENDS 744877003 + + +.SUBCKT 744877004 1 2 3 4 +L1 4 1 3.800255270261E-06 Ipk=1.55 Rser = 4.62500005960464E-02 Rpar =7330.545982911 Cpar = 6.625178973507E-12 +L2 3 2 3.800255270261E-06 Ipk=1.55 Rser = 4.62500005960464E-02 Rpar =7330.545982911 Cpar = 6.625178973507E-12 +C1 3 4 0.00000000000675 +C2 1 2 0.00000000000675 +k L1 L2 0.935267854600727 +.ENDS 744877004 + + +.SUBCKT 744877004A 1 2 3 4 +L1 4 1 3.667592046042E-06 Ipk=1.55 Rser = 4.75000012665987E-02 Rpar =7531.460755888 Cpar = 6.182532980013E-12 +L2 3 2 3.667592046042E-06 Ipk=1.55 Rser = 4.75000012665987E-02 Rpar =7531.460755888 Cpar = 6.182532980013E-12 +C1 3 4 0.00000000000627 +C2 1 2 0.00000000000627 +k L1 L2 0.933025402249583 +.ENDS 744877004A + + +.SUBCKT 744877005 1 2 3 4 +L1 4 1 4.815919780821E-06 Ipk=1.9 Rser = 6.64999997243285E-02 Rpar =9678.501698923 Cpar = 5.246342504626E-12 +L2 3 2 4.815919780821E-06 Ipk=1.9 Rser = 6.64999997243285E-02 Rpar =9678.501698923 Cpar = 5.246342504626E-12 +C1 3 4 0.000000000006645 +C2 1 2 0.000000000006645 +k L1 L2 0.938125567833223 +.ENDS 744877005 + + +.SUBCKT 744877006 1 2 3 4 +L1 4 1 6.536803658278E-06 Ipk=1.8 Rser = 7.87499994039536E-02 Rpar =11623.77221658 Cpar = 7.115754050699E-12 +L2 3 2 6.536803658278E-06 Ipk=1.8 Rser = 7.87499994039536E-02 Rpar =11623.77221658 Cpar = 7.115754050699E-12 +C1 3 4 7.1625E-12 +C2 1 2 7.1625E-12 +k L1 L2 0.946575341975852 +.ENDS 744877006 + + +.SUBCKT 744877008 1 2 3 4 +L1 4 1 7.874363281789E-06 Ipk=1.7 Rser = 8.32500010728836E-02 Rpar =12142.64744534 Cpar = 7.866482393082E-12 +L2 3 2 7.874363281789E-06 Ipk=1.7 Rser = 8.32500010728836E-02 Rpar =12142.64744534 Cpar = 7.866482393082E-12 +C1 3 4 0.0000000000082 +C2 1 2 0.0000000000082 +k L1 L2 0.960045662954863 +.ENDS 744877008 + + +.SUBCKT 744877100 1 2 3 4 +L1 4 1 8.504394301672E-06 Ipk=1.1 Rser = 8.99999998509884E-02 Rpar =11554.12199734 Cpar = 1.0971494144547E-11 +L2 3 2 8.504394301672E-06 Ipk=1.1 Rser = 8.99999998509884E-02 Rpar =11554.12199734 Cpar = 1.0971494144547E-11 +C1 3 4 0.000000000008415 +C2 1 2 0.000000000008415 +k L1 L2 0.947530863334485 +.ENDS 744877100 + + +.SUBCKT 744877101 1 2 3 4 +L1 4 1 8.900392736262E-05 Ipk=0.65 Rser = 0.901500016450882 Rpar =60156.7589142 Cpar = 1.666620330062E-11 +L2 3 2 8.900392736262E-05 Ipk=0.65 Rser = 0.901500016450882 Rpar =60156.7589142 Cpar = 1.666620330062E-11 +C1 3 4 0.00000000001317 +C2 1 2 0.00000000001317 +k L1 L2 0.957361554101469 +.ENDS 744877101 + + +.SUBCKT 744877220 1 2 3 4 +L1 4 1 1.93530956566778E-05 Ipk=0.8 Rser = 0.190500002354383 Rpar =20724.9180642 Cpar = 1.28132294158889E-11 +L2 3 2 1.93530956566778E-05 Ipk=0.8 Rser = 0.190500002354383 Rpar =20724.9180642 Cpar = 1.28132294158889E-11 +C1 3 4 0.00000000001037 +C2 1 2 0.00000000001037 +k L1 L2 0.956810631447276 +.ENDS 744877220 + + +.SUBCKT 744877220 1 2 3 4 +L1 4 1 1.92122065786E-05 Ipk=0.8 Rser = 0.190500002354383 Rpar =22461.8486926 Cpar = 1.09870677065E-11 +L2 3 2 1.92122065786E-05 Ipk=0.8 Rser = 0.190500002354383 Rpar =22461.8486926 Cpar = 1.09870677065E-11 +C1 3 4 0.00000000001037 +C2 1 2 0.00000000001037 +k L1 L2 0.956810631447276 +.ENDS 744877220 + + +.SUBCKT 744877330 1 2 3 4 +L1 4 1 3.058837073111E-05 Ipk=0.7 Rser = 0.338250003755093 Rpar =30858.1675609 Cpar = 1.1079332484208E-11 +L2 3 2 3.058837073111E-05 Ipk=0.7 Rser = 0.338250003755093 Rpar =30858.1675609 Cpar = 1.1079332484208E-11 +C1 3 4 0.000000000009715 +C2 1 2 0.000000000009715 +k L1 L2 0.934893489056838 +.ENDS 744877330 + + +.SUBCKT 744878001 1 2 3 4 +L1 4 1 1.135025179597E-06 Ipk=4.4 Rser = 2.67499997280538E-02 Rpar =3052.234844177 Cpar = 4.69655033783E-12 +L2 3 2 1.135025179597E-06 Ipk=4.4 Rser = 2.67499997280538E-02 Rpar =3052.234844177 Cpar = 4.69655033783E-12 +C1 3 4 4.1875E-12 +C2 1 2 4.1875E-12 +k L1 L2 0.960317459801232 +.ENDS 744878001 + + +.SUBCKT 744878002 1 2 3 4 +L1 4 1 2.14408628271E-06 Ipk=3.6 Rser = 4.05000001192093E-02 Rpar =5302.644154298 Cpar = 4.396748958066E-12 +L2 3 2 2.14408628271E-06 Ipk=3.6 Rser = 4.05000001192093E-02 Rpar =5302.644154298 Cpar = 4.396748958066E-12 +C1 3 4 4.9625E-12 +C2 1 2 4.9625E-12 +k L1 L2 0.941544882014607 +.ENDS 744878002 + + +.SUBCKT 744878003 1 2 3 4 +L1 4 1 2.829370009363E-06 Ipk=3.3 Rser = 4.55000000074506E-02 Rpar =6277.400426277 Cpar = 4.327343439359E-12 +L2 3 2 2.829370009363E-06 Ipk=3.3 Rser = 4.55000000074506E-02 Rpar =6277.400426277 Cpar = 4.327343439359E-12 +C1 3 4 0.00000000000413 +C2 1 2 0.00000000000413 +k L1 L2 0.94551281906777 +.ENDS 744878003 + + +.SUBCKT 744878004 1 2 3 4 +L1 4 1 3.923743823943E-06 Ipk=1.3 Rser = 6.32500005885959E-02 Rpar =8272.09663569 Cpar = 5.400933342016E-12 +L2 3 2 3.923743823943E-06 Ipk=1.3 Rser = 6.32500005885959E-02 Rpar =8272.09663569 Cpar = 5.400933342016E-12 +C1 3 4 0.00000000000492 +C2 1 2 0.00000000000492 +k L1 L2 0.908994710922295 +.ENDS 744878004 + + +.SUBCKT 744878005 1 2 3 4 +L1 4 1 5.336219581368E-06 Ipk=1.5 Rser = 8.37500002235174E-02 Rpar =9428.694075054 Cpar = 6.074558702798E-12 +L2 3 2 5.336219581368E-06 Ipk=1.5 Rser = 8.37500002235174E-02 Rpar =9428.694075054 Cpar = 6.074558702798E-12 +C1 3 4 0.00000000000453 +C2 1 2 0.00000000000453 +k L1 L2 0.919672132166314 +.ENDS 744878005 + + +.SUBCKT 744878006 1 2 3 4 +L1 4 1 6.117137346139E-06 Ipk=1.4 Rser = 8.95000025629997E-02 Rpar =11220.88323414 Cpar = 6.088135735101E-12 +L2 3 2 6.117137346139E-06 Ipk=1.4 Rser = 8.95000025629997E-02 Rpar =11220.88323414 Cpar = 6.088135735101E-12 +C1 3 4 0.00000000000495 +C2 1 2 0.00000000000495 +k L1 L2 0.921795797899602 +.ENDS 744878006 + + +.SUBCKT 744878008 1 2 3 4 +L1 4 1 6.925907479861E-06 Ipk=1.3 Rser = 0.103250002488494 Rpar =11772.616750928 Cpar = 6.316033400206E-12 +L2 3 2 6.925907479861E-06 Ipk=1.3 Rser = 0.103250002488494 Rpar =11772.616750928 Cpar = 6.316033400206E-12 +C1 3 4 0.000000000005305 +C2 1 2 0.000000000005305 +k L1 L2 0.915596330074557 +.ENDS 744878008 + + +.SUBCKT 744878100 1 2 3 4 +L1 4 1 8.442790496906E-06 Ipk=1 Rser = 0.127750001847744 Rpar =14085.14549534 Cpar = 5.803172523208E-12 +L2 3 2 8.442790496906E-06 Ipk=1 Rser = 0.127750001847744 Rpar =14085.14549534 Cpar = 5.803172523208E-12 +C1 3 4 0.00000000000535 +C2 1 2 0.00000000000535 +k L1 L2 0.922675024972665 +.ENDS 744878100 + + +.SUBCKT 744878101 1 2 3 4 +L1 4 1 8.702321671935E-05 Ipk=0.3 Rser = 1.16899999976158 Rpar =63426.1945521 Cpar = 1.0419700222087E-11 +L2 3 2 8.702321671935E-05 Ipk=0.3 Rser = 1.16899999976158 Rpar =63426.1945521 Cpar = 1.0419700222087E-11 +C1 3 4 0.00000000000941 +C2 1 2 0.00000000000941 +k L1 L2 0.938248462535577 +.ENDS 744878101 + + +.SUBCKT 744878220 1 2 3 4 +L1 4 1 1.867164732777E-05 Ipk=0.7 Rser = 0.244000002741814 Rpar =23974.33598126 Cpar = 7.743012783924E-12 +L2 3 2 1.867164732777E-05 Ipk=0.7 Rser = 0.244000002741814 Rpar =23974.33598126 Cpar = 7.743012783924E-12 +C1 3 4 0.00000000000651 +C2 1 2 0.00000000000651 +k L1 L2 0.918906395956803 +.ENDS 744878220 + + +.SUBCKT 744878221 1 2 3 4 +L1 4 1 0.000204882929533 Ipk=0.35 Rser = 2.49775004386902 Rpar =90246.93173925 Cpar = 1.6736468533692E-11 +L2 3 2 0.000204882929533 Ipk=0.35 Rser = 2.49775004386902 Rpar =90246.93173925 Cpar = 1.6736468533692E-11 +C1 3 4 0.000000000012375 +C2 1 2 0.000000000012375 +k L1 L2 0.925925927227771 +.ENDS 744878221 + + +.SUBCKT 744878470 1 2 3 4 +L1 4 1 4.344145091395E-05 Ipk=0.9 Rser = 0.569999992847443 Rpar =39039.49084463 Cpar = 9.373403111728E-12 +L2 3 2 4.344145091395E-05 Ipk=0.9 Rser = 0.569999992847443 Rpar =39039.49084463 Cpar = 9.373403111728E-12 +C1 3 4 0.000000000009525 +C2 1 2 0.000000000009525 +k L1 L2 0.944001678058741 +.ENDS 744878470 diff --git a/spice/copy/sub/Contrib/Wurth/WE-DPC.lib b/spice/copy/sub/Contrib/Wurth/WE-DPC.lib new file mode 100755 index 0000000..2f919c1 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-DPC.lib @@ -0,0 +1,261 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Dual Powerchoke +* Matchcode: WE-DPC +* Library Type: Ltspice +* Version: rev18a +* Created/modified by: Fredo +* Date and Time : 10/15/2018 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 5838_7448844010_1u 1 2 3 4 PARAMS: ++ Cww=6.2p ++ Rp1=429 ++ Cp1=2.58p ++ Lp1=1.031u ++ Rp2=457 ++ Cp2=2.361p ++ Lp2=1.127u ++ RDC1=0.017 ++ RDC2=0.017 ++ K=0.91214034007931 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5838_7448844022_2.2u 1 2 3 4 PARAMS: ++ Cww=9.8p ++ Rp1=1461 ++ Cp1=2.822p ++ Lp1=2.162u ++ Rp2=1446 ++ Cp2=2.333p ++ Lp2=2.114u ++ RDC1=0.028 ++ RDC2=0.028 ++ K=0.960113629638795 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5838_7448844033_3.3u 1 2 3 4 PARAMS: ++ Cww=12p ++ Rp1=2267 ++ Cp1=3.321p ++ Lp1=3.307u ++ Rp2=2260 ++ Cp2=3.305p ++ Lp2=3.382u ++ RDC1=0.034 ++ RDC2=0.034 ++ K=0.971253485622231 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5838_7448844047_4.7u 1 2 3 4 PARAMS: ++ Cww=14p ++ Rp1=3591 ++ Cp1=3.123p ++ Lp1=5.309u ++ Rp2=3588 ++ Cp2=3.114p ++ Lp2=5.324u ++ RDC1=0.047 ++ RDC2=0.047 ++ K=0.979035565389671 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5838_7448844068_6.8u 1 2 3 4 PARAMS: ++ Cww=16p ++ Rp1=5036 ++ Cp1=3.513p ++ Lp1=7.215u ++ Rp2=4915 ++ Cp2=3.412p ++ Lp2=7.301u ++ RDC1=0.058 ++ RDC2=0.058 ++ K=0.982942760585903 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5838_7448844100_10u 1 2 3 4 PARAMS: ++ Cww=18p ++ Rp1=6481 ++ Cp1=3.658p ++ Lp1=10.064u ++ Rp2=6790 ++ Cp2=3.637p ++ Lp2=10.122u ++ RDC1=0.08 ++ RDC2=0.08 ++ K=0.987319603775799 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5838_7448844150_15u 1 2 3 4 PARAMS: ++ Cww=26p ++ Rp1=9883 ++ Cp1=3.112p ++ Lp1=15.297u ++ Rp2=9817 ++ Cp2=3.1p ++ Lp2=15.487u ++ RDC1=0.13 ++ RDC2=0.13 ++ K=0.990689995239008 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5838_7448844220_22u 1 2 3 4 PARAMS: ++ Cww=37p ++ Rp1=13155 ++ Cp1=3.458p ++ Lp1=19.733u ++ Rp2=13014 ++ Cp2=3.444p ++ Lp2=19.816u ++ RDC1=0.169 ++ RDC2=0.169 ++ K=0.992013562957135 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5838_7448844330_33u 1 2 3 4 PARAMS: ++ Cww=40p ++ Rp1=20313 ++ Cp1=3.751p ++ Lp1=33.361u ++ Rp2=21415 ++ Cp2=3.704p ++ Lp2=33.15u ++ RDC1=0.22 ++ RDC2=0.22 ++ K=0.992883770548286 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5838_7448844470_47u 1 2 3 4 PARAMS: ++ Cww=47p ++ Rp1=27605 ++ Cp1=3.898p ++ Lp1=43.106u ++ Rp2=26311 ++ Cp2=3.843p ++ Lp2=44.746u ++ RDC1=0.24 ++ RDC2=0.24 ++ K=0.993596518992086 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** diff --git a/spice/copy/sub/Contrib/Wurth/WE-DPC_HV.lib b/spice/copy/sub/Contrib/Wurth/WE-DPC_HV.lib new file mode 100755 index 0000000..00b7d91 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-DPC_HV.lib @@ -0,0 +1,348 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Dual Powerchoke +* Matchcode: WE-DPC_HV +* Library Type: Ltspice +* Version: rev18a +* Created/modified by: Fredo +* Date and Time : 3/15/2018 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 5030_7448841010_1u 1 2 3 4 PARAMS: ++ Cww=6.54p ++ Rp1=1666 ++ Cp1=0.725p ++ Lp1=0.9u ++ Rp2=1666 ++ Cp2=0.725p ++ Lp2=0.9u ++ RDC1=0.032 ++ RDC2=0.032 ++ K=0.964365076099295 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841015_1.5u 1 2 3 4 PARAMS: ++ Cww=6.98p ++ Rp1=3088 ++ Cp1=0.917p ++ Lp1=1.818u ++ Rp2=3088 ++ Cp2=0.917p ++ Lp2=1.818u ++ RDC1=0.048 ++ RDC2=0.048 ++ K=0.972967967955095 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841022_2.2u 1 2 3 4 PARAMS: ++ Cww=7.46p ++ Rp1=4172 ++ Cp1=1.291p ++ Lp1=2.312u ++ Rp2=4172 ++ Cp2=1.291p ++ Lp2=2.312u ++ RDC1=0.05 ++ RDC2=0.05 ++ K=0.971175482691886 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841033_3.3u 1 2 3 4 PARAMS: ++ Cww=9.17p ++ Rp1=5673 ++ Cp1=3.09p ++ Lp1=3.682u ++ Rp2=5673 ++ Cp2=3.09p ++ Lp2=3.682u ++ RDC1=0.084 ++ RDC2=0.084 ++ K=0.980105127323626 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841047_4.7u 1 2 3 4 PARAMS: ++ Cww=10.01p ++ Rp1=7766 ++ Cp1=2.824p ++ Lp1=5.957u ++ Rp2=7766 ++ Cp2=2.824p ++ Lp2=5.957u ++ RDC1=0.102 ++ RDC2=0.102 ++ K=0.982831341995416 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841068_6.8u 1 2 3 4 PARAMS: ++ Cww=12.45p ++ Rp1=10491 ++ Cp1=3.221p ++ Lp1=7.657u ++ Rp2=10491 ++ Cp2=3.221p ++ Lp2=7.657u ++ RDC1=0.168 ++ RDC2=0.168 ++ K=0.987420882906575 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841082_8.2u 1 2 3 4 PARAMS: ++ Cww=14.15p ++ Rp1=12475 ++ Cp1=1.798p ++ Lp1=9.357u ++ Rp2=12475 ++ Cp2=1.798p ++ Lp2=9.357u ++ RDC1=0.18 ++ RDC2=0.18 ++ K=0.988655159492047 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841150_15u 1 2 3 4 PARAMS: ++ Cww=18.34p ++ Rp1=19909 ++ Cp1=3.339p ++ Lp1=15.865u ++ Rp2=19909 ++ Cp2=3.339p ++ Lp2=15.865u ++ RDC1=0.325 ++ RDC2=0.325 ++ K=0.990622699787025 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841220_22u 1 2 3 4 PARAMS: ++ Cww=20.85p ++ Rp1=24214 ++ Cp1=1.81p ++ Lp1=23.72u ++ Rp2=24214 ++ Cp2=1.81p ++ Lp2=23.72u ++ RDC1=0.455 ++ RDC2=0.455 ++ K=0.990637994609351 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841330_33u 1 2 3 4 PARAMS: ++ Cww=21.63p ++ Rp1=40443 ++ Cp1=1.779p ++ Lp1=36.041u ++ Rp2=40443 ++ Cp2=1.779p ++ Lp2=36.041u ++ RDC1=0.718 ++ RDC2=0.718 ++ K=0.990408547473764 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841470_47u 1 2 3 4 PARAMS: ++ Cww=25.4p ++ Rp1=37674 ++ Cp1=1.88p ++ Lp1=50.004u ++ Rp2=37674 ++ Cp2=1.88p ++ Lp2=50.004u ++ RDC1=0.84 ++ RDC2=0.84 ++ K=0.990916188997345 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448441100_10u 1 2 3 4 PARAMS: ++ Cww=16.48p ++ Rp1=16318 ++ Cp1=1.474p ++ Lp1=13.695u ++ Rp2=16318 ++ Cp2=1.474p ++ Lp2=13.695u ++ RDC1=0.21 ++ RDC2=0.21 ++ K=0.990454441 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_7448841100_10u 1 2 3 4 PARAMS: ++ Cww=16.48p ++ Rp1=16318 ++ Cp1=1.474p ++ Lp1=13.695u ++ Rp2=16318 ++ Cp2=1.474p ++ Lp2=13.695u ++ RDC1=0.21 ++ RDC2=0.21 ++ K=0.990454441 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** + + + + + + + + + + + + diff --git a/spice/copy/sub/Contrib/Wurth/WE-EHPI.lib b/spice/copy/sub/Contrib/Wurth/WE-EHPI.lib new file mode 100755 index 0000000..b5e663c --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-EHPI.lib @@ -0,0 +1,73 @@ +************************************************** +.subckt 5838_74488540250_25u 1 2 3 4 PARAMS: ++ Cww=7.92p ++ Rp1=1694 ++ Cp1=3.793n ++ Lp1=24.543u ++ Rp2=656715 ++ Cp2=11.347p ++ Lp2=10.366m ++ RDC1=0.040 ++ RDC2=0.2 ++ K=0.97899637 +C_C1 1 4 {Cww/2} +C_C2 2 3 {Cww/2} +C_C5 2 1 {Cp1} +R_R1 2 N05454 {RDC1} +R_R2 2 1 {Rp1} +L_L1 N05454 1 {Lp1} +L_L2 N05750 4 {Lp2} +C_C6 3 4 {Cp2} +R_R3 3 4 {Rp2} +R_R4 3 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +************************************************** +.subckt 5838_74488540120_13u 1 2 3 4 PARAMS: ++ Cww=6.28p ++ Rp1=550 ++ Cp1=17n ++ Lp1=13.01u ++ Rp2=275585 ++ Cp2=8.98p ++ Lp2=33.116m ++ RDC1=0.135 ++ RDC2=0.09 ++ K=0.975605608 +C_C1 1 4 {Cww/2} +C_C2 2 3 {Cww/2} +C_C5 2 1 {Cp1} +R_R1 2 N05454 {RDC1} +R_R2 2 1 {Rp1} +L_L1 N05454 1 {Lp1} +L_L2 N05750 4 {Lp2} +C_C6 3 4 {Cp2} +R_R3 3 4 {Rp2} +R_R4 3 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +************************************************** +.subckt 5838_74488540070_7u 1 2 3 4 PARAMS: ++ Cww=6.91p ++ Rp1=280 ++ Cp1=70n ++ Lp1=6.8u ++ Rp2=248260 ++ Cp2=8.797p ++ Lp2=69.487m ++ RDC1=0.205 ++ RDC2=0.085 ++ K=0.969535971 +C_C1 1 4 {Cww/2} +C_C2 2 3 {Cww/2} +C_C5 2 1 {Cp1} +R_R1 2 N05454 {RDC1} +R_R2 2 1 {Rp1} +L_L1 N05454 1 {Lp1} +L_L2 N05750 4 {Lp2} +C_C6 3 4 {Cp2} +R_R3 3 4 {Rp2} +R_R4 3 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** \ No newline at end of file diff --git a/spice/copy/sub/Contrib/Wurth/WE-ExB.lib b/spice/copy/sub/Contrib/Wurth/WE-ExB.lib new file mode 100755 index 0000000..4c7375d --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-ExB.lib @@ -0,0 +1,355 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-ExB +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt TypeL_744844101_100u 1 2 3 4 +L5 N010 N009 {L3} Rpar={Rs3} +C3 4 N001 {C1} Rser={R2} +L1 4 N011 {L1} Rpar={Rs1} +L3 N011 N010 {L2} Rpar={Rs2} +L6 N014 N013 {L3} Rpar={Rs3} +C4 3 N012 {C1} Rser={R2} +L2 3 N015 {L1} Rpar={Rs1} +L4 N015 N014 {L2} Rpar={Rs2} +L8 N013 N012 {L4} Rpar={Rs4} +L7 N009 N001 {L4} Rpar={Rs4} +L9 N001 N006 {L5} Rpar={Rs5} Cpar={C2} +L10 N012 N020 {L5} Rpar={Rs5} Cpar={C2} +R1 N002 1 {Rdc} +R2 N004 N002 {dR4} +C1 N003 N002 {dC3} +L17 N007 N002 {dL3} +L18 N016 N017 {dL3} +C2 N007 N017 {ck} +R3 N004 N003 {dR3} +R4 N018 N021 {dR3} +C9 N021 N016 {dC3} +R5 N018 N016 {dR4} +L19 N004 N007 {dL3} +L20 N017 N018 {dL3} +R6 N016 2 {Rdc} +R8 N006 N004 {dR6} +C10 N005 N004 {dC4} +L13 N008 N004 {dL4} +L14 N018 N019 {dL4} +C11 N008 N019 {ck} +R9 N006 N005 {dR5} +R10 N020 N022 {dR5} +C12 N022 N018 {dC4} +R11 N020 N018 {dR6} +L15 N006 N008 {dL4} +L16 N019 N020 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K7 L17 L18 L19 L20 0.9999 +K6 L13 L14 L15 L16 0.9999 +.param dl3=0.0000001409405 +.param dc3=0.0000000000000333 +.param dl4=0.000000001351 +.param dc4=0.00000000000143 +.param dr3=0.48 +.param dr4=2100 +.param dr5=1.88 +.param dr6=166 +.param ck=8.4pF +.param L1=0.460098919891953E-05 +.param L2=0.0000909908 +.param L3=0.0000018 +.param L4=0.000018 +.param L5=0.0000018 +.param C1=1.22922309E-12 +.param C2=0.00000000002754 +.param Rs1=590 +.param Rs2=670 +.param Rs3=703 +.param Rs4=78 +.param Rs5=109 +.param R2=0.11 +.param Rdc=6m +.ends TypeL_744844101_100u +******** +.subckt TypeL_744844102_1000u 1 2 3 4 +L5 N010 N009 {L3} Rpar={Rs3} +C3 4 N001 {C1} Rser={R2} +L1 4 N011 {L1} Rpar={Rs1} +L3 N011 N010 {L2} Rpar={Rs2} +L6 N014 N013 {L3} Rpar={Rs3} +C4 3 N012 {C1} Rser={R2} +L2 3 N015 {L1} Rpar={Rs1} +L4 N015 N014 {L2} Rpar={Rs2} +L8 N013 N012 {L4} Rpar={Rs4} +L7 N009 N001 {L4} Rpar={Rs4} +L9 N001 N006 {L5} Rpar={Rs5} Cpar={C2} +L10 N012 N020 {L5} Rpar={Rs5} Cpar={C2} +R1 N002 1 {Rdc} +R2 N004 N002 {dR4} +C1 N003 N002 {dC3} +L17 N007 N002 {dL3} +L18 N016 N017 {dL3} +C2 N007 N017 {ck} +R3 N004 N003 {dR3} +R4 N018 N021 {dR3} +C9 N021 N016 {dC3} +R5 N018 N016 {dR4} +L19 N004 N007 {dL3} +L20 N017 N018 {dL3} +R6 N016 2 {Rdc} +R8 N006 N004 {dR6} +C10 N005 N004 {dC4} +L13 N008 N004 {dL4} +L14 N018 N019 {dL4} +C11 N008 N019 {ck} +R9 N006 N005 {dR5} +R10 N020 N022 {dR5} +C12 N022 N018 {dC4} +R11 N020 N018 {dR6} +L15 N006 N008 {dL4} +L16 N019 N020 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K7 L17 L18 L19 L20 0.9999 +K6 L13 L14 L15 L16 0.9999 +.param dl3=0.0000009960 +.param dc3=0.0000000000000433 +.param dl4=0.0000000165351 +.param dc4=0.0000000000143 +.param dr3=0.48 +.param dr4=9700 +.param dr5=1.88 +.param dr6=766 +.param ck=17.15pF +.param L1=0.0009410059538 +.param L2=0.00002050035 +.param L3=0.000000000847 +.param L4=0.00000004222 +.param L5=0.000089965 +.param C1=0.00000000000717309 +.param C2=0.0000000000059294 +.param Rs1=10185 +.param Rs2=8447 +.param Rs3=5703 +.param Rs4=5678 +.param Rs5=7009 +.param R2=0.11 +.param Rdc=42m +.ends TypeL_744844102_1000u +******** +.subckt TypeL_744844221_220u 1 2 3 4 +L5 N010 N009 {L3} Rpar={Rs3} +C3 4 N001 {C1} Rser={R2} +L1 4 N011 {L1} Rpar={Rs1} +L3 N011 N010 {L2} Rpar={Rs2} +L6 N014 N013 {L3} Rpar={Rs3} +C4 3 N012 {C1} Rser={R2} +L2 3 N015 {L1} Rpar={Rs1} +L4 N015 N014 {L2} Rpar={Rs2} +L8 N013 N012 {L4} Rpar={Rs4} +L7 N009 N001 {L4} Rpar={Rs4} +L9 N001 N006 {L5} Rpar={Rs5} Cpar={C2} +L10 N012 N020 {L5} Rpar={Rs5} Cpar={C2} +R1 N002 1 {Rdc} +R2 N004 N002 {dR4} +C1 N003 N002 {dC3} +L17 N007 N002 {dL3} +L18 N016 N017 {dL3} +C2 N007 N017 {ck} +R3 N004 N003 {dR3} +R4 N018 N021 {dR3} +C9 N021 N016 {dC3} +R5 N018 N016 {dR4} +L19 N004 N007 {dL3} +L20 N017 N018 {dL3} +R6 N016 2 {Rdc} +R8 N006 N004 {dR6} +C10 N005 N004 {dC4} +L13 N008 N004 {dL4} +L14 N018 N019 {dL4} +C11 N008 N019 {ck} +R9 N006 N005 {dR5} +R10 N020 N022 {dR5} +C12 N022 N018 {dC4} +R11 N020 N018 {dR6} +L15 N006 N008 {dL4} +L16 N019 N020 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K7 L17 L18 L19 L20 0.9999 +K6 L13 L14 L15 L16 0.9999 +.param dl3=0.00000026 +.param dc3=0.0000000000000333 +.param dl4=0.000000001351 +.param dc4=0.00000000000143 +.param dr3=0.48 +.param dr4=3800 +.param dr5=1.88 +.param dr6=166 +.param ck=12.4pF +.param L1=1.40000989198919E-05 +.param L2=0.000228 +.param L3=0.0000018 +.param L4=0.000018 +.param L5=0.0000018 +.param C1=1.82922309E-12 +.param C2=0.00000000002754 +.param Rs1=1600 +.param Rs2=1610 +.param Rs3=703 +.param Rs4=78 +.param Rs5=109 +.param R2=0.11 +.param Rdc=9m +.ends TypeL_744844221_220u +******** +.subckt TypeL_744844470_47u 1 2 3 4 +L5 N010 N009 {L3} Rpar={Rs3} +C3 4 N001 {C1} Rser={R2} +L1 4 N011 {L1} Rpar={Rs1} +L3 N011 N010 {L2} Rpar={Rs2} +L6 N014 N013 {L3} Rpar={Rs3} +C4 3 N012 {C1} Rser={R2} +L2 3 N015 {L1} Rpar={Rs1} +L4 N015 N014 {L2} Rpar={Rs2} +L8 N013 N012 {L4} Rpar={Rs4} +L7 N009 N001 {L4} Rpar={Rs4} +L9 N001 N006 {L5} Rpar={Rs5} Cpar={C2} +L10 N012 N020 {L5} Rpar={Rs5} Cpar={C2} +R1 N002 1 {Rdc} +R2 N004 N002 {dR4} +C1 N003 N002 {dC3} +L17 N007 N002 {dL3} +L18 N016 N017 {dL3} +C2 N007 N017 {ck} +R3 N004 N003 {dR3} +R4 N018 N021 {dR3} +C9 N021 N016 {dC3} +R5 N018 N016 {dR4} +L19 N004 N007 {dL3} +L20 N017 N018 {dL3} +R6 N016 2 {Rdc} +R8 N006 N004 {dR6} +C10 N005 N004 {dC4} +L13 N008 N004 {dL4} +L14 N018 N019 {dL4} +C11 N008 N019 {ck} +R9 N006 N005 {dR5} +R10 N020 N022 {dR5} +C12 N022 N018 {dC4} +R11 N020 N018 {dR6} +L15 N006 N008 {dL4} +L16 N019 N020 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K7 L17 L18 L19 L20 0.9999 +K6 L13 L14 L15 L16 0.9999 +.param dl3=0.000000054541 +.param dc3=0.0000000000000333 +.param dl4=0.000000001351 +.param dc4=0.00000000000143 +.param dr3=0.48 +.param dr4=1580 +.param dr5=1.88 +.param dr6=166 +.param ck=7pF +.param L1=0.00000169198919538 +.param L2=0.000045991035 +.param L3=0.000000537 +.param L4=0.0000000391634222 +.param L5=0.000000004425 +.param C1=0.000000000001522309 +.param C2=0.00000000000154 +.param Rs1=310 +.param Rs2=410 +.param Rs3=703 +.param Rs4=78 +.param Rs5=109 +.param R2=0.11 +.param Rdc=4.6m +.ends TypeL_744844470_47u +******** +.subckt TypeL_744844471_470u 1 2 3 4 +L5 N010 N009 {L3} Rpar={Rs3} +C3 4 N001 {C1} Rser={R2} +L1 4 N011 {L1} Rpar={Rs1} +L3 N011 N010 {L2} Rpar={Rs2} +L6 N014 N013 {L3} Rpar={Rs3} +C4 3 N012 {C1} Rser={R2} +L2 3 N015 {L1} Rpar={Rs1} +L4 N015 N014 {L2} Rpar={Rs2} +L8 N013 N012 {L4} Rpar={Rs4} +L7 N009 N001 {L4} Rpar={Rs4} +L9 N001 N006 {L5} Rpar={Rs5} Cpar={C2} +L10 N012 N020 {L5} Rpar={Rs5} Cpar={C2} +R1 N002 1 {Rdc} +R2 N004 N002 {dR4} +C1 N003 N002 {dC3} +L17 N007 N002 {dL3} +L18 N016 N017 {dL3} +C2 N007 N017 {ck} +R3 N004 N003 {dR3} +R4 N018 N021 {dR3} +C9 N021 N016 {dC3} +R5 N018 N016 {dR4} +L19 N004 N007 {dL3} +L20 N017 N018 {dL3} +R6 N016 2 {Rdc} +R8 N006 N004 {dR6} +C10 N005 N004 {dC4} +L13 N008 N004 {dL4} +L14 N018 N019 {dL4} +C11 N008 N019 {ck} +R9 N006 N005 {dR5} +R10 N020 N022 {dR5} +C12 N022 N018 {dC4} +R11 N020 N018 {dR6} +L15 N006 N008 {dL4} +L16 N019 N020 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K7 L17 L18 L19 L20 0.9999 +K6 L13 L14 L15 L16 0.9999 +.param dl3=0.000000513805 +.param dc3=0.0000000000000333 +.param dl4=0.000000001351 +.param dc4=0.00000000000143 +.param dr3=0.48 +.param dr4=6380 +.param dr5=1.88 +.param dr6=166 +.param ck=15.2pF +.param L1=3.00098919891953E-05 +.param L2=0.000508 +.param L3=0.0000018 +.param L4=0.000018 +.param L5=0.0000018 +.param C1=2.72922309E-12 +.param C2=0.00000000002754 +.param Rs1=5000 +.param Rs2=3610 +.param Rs3=703 +.param Rs4=78 +.param Rs5=109 +.param R2=0.11 +.param Rdc=16m +.ends TypeL_744844471_470u \ No newline at end of file diff --git a/spice/copy/sub/Contrib/Wurth/WE-FC.lib b/spice/copy/sub/Contrib/Wurth/WE-FC.lib new file mode 100755 index 0000000..97bb45d --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-FC.lib @@ -0,0 +1,799 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-FC +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT FC 1 2 3 4 PARAMS: +L5 N011 N010 {L3} +R50 N011 N010 {Rs3} +C3 N500 N001 {C1} +R500 4 N500 {R2} +L1 4 N012 {L1} +R51 4 N012 {Rs1} +L3 N012 N011 {L2} +R52 N012 N011 {Rs2} +L6 N015 N014 {L3} +R53 N015 N014 {Rs3} +C4 N501 N013 {C1} +R501 3 N501 {R2} +L2 3 N016 {L1} +R54 3 N016 {Rs1} +L4 N016 N015 {L2} +R55 N016 N015 {Rs2} +L8 N014 N013 {L4} +R56 N014 N013 {Rs4} +L7 N010 N001 {L4} +R57 N010 N001 {Rs4} +L9 N001 N007 {L5} +R58 N001 N007 {Rs5} +C50 N001 N007 {C2} +L10 N013 N022 {L5} +R59 N013 N022 {Rs5} +C51 N013 N022 {C2} +L11 N007 N006 {L6} +R60 N007 N006 {Rs6} +C52 N007 N006 {C3} +L12 N022 N021 {L6} +R61 N022 N021 {Rs6} +C53 N022 N021 {C3} +R1 N002 1 {Rdc} +R2 N004 N002 {dR4} +C1 N003 N002 {dC3} +L17 N008 N002 {dL3} +L18 N017 N018 {dL3} +C2 N008 N018 {ck} +Ropen N008 N018 1000g +R3 N004 N003 {dR3} +R4 N019 N023 {dR3} +C9 N023 N017 {dC3} +R5 N019 N017 {dR4} +L19 N004 N008 {dL3} +L20 N018 N019 {dL3} +R6 N017 2 {Rdc} +R8 N006 N004 {dR6} +C10 N005 N004 {dC4} +L13 N009 N004 {dL4} +L14 N019 N020 {dL4} +C11 N009 N020 {ck} +R9 N006 N005 {dR5} +R10 N021 N024 {dR5} +C12 N024 N019 {dC4} +R11 N021 N019 {dR6} +L15 N006 N009 {dL4} +L16 N020 N021 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K6 L11 L12 1 +K8 L17 L18 L19 L20 0.9999 +K7 L13 L14 L15 L16 0.9999 +.ends FC +*********** +.subckt ET20H_7448640395_0.82m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.00133660190142394 ++ L2=0.00066701705440674 ++ L3=0.000693004088894302 ++ L4=0.000224826199486956 ++ L5=6.65504570380959E-08 ++ L6=2.78498066135292E-09 ++ C1=2.46181731944311E-12 ++ C2=6.73670849014524E-12 ++ C3=5.97097127528123E-12 ++ RS1=1337.81419587115 ++ RS2=3155.91701442969 ++ RS3=192.411087825075 ++ RS4=5573.70200019057 ++ RS5=52.0826799302894 ++ RS6=929.380663145605 ++ R2=39.6163187388244 ++ DL3=0.000000738 ++ DC3=0.00000000000205 ++ DL4=0.00000000811 ++ DC4=0.0000000000000833 ++ DR3=0.48 ++ DR4=8680 ++ DR5=0.58 ++ DR6=266 ++ Rdc=0.067 ++ ck=1.6pF +.ends ET20H_7448640395_0.82m +*********** +.subckt ET20H_7448640396_1.8m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000419223341788641 ++ L2=0.0000184444809801961 ++ L3=0.00122353116043503 ++ L4=0.000608286488459203 ++ L5=2.63691058688461E-07 ++ L6=2.07373482216634E-08 ++ C1=2.3907543616794E-12 ++ C2=5.90370575995892E-11 ++ C3=7.9473024968741E-13 ++ RS1=380.450393991046 ++ RS2=2692.70730521348 ++ RS3=7812.053257593 ++ RS4=13618.6906089575 ++ RS5=71.696142463382 ++ RS6=888.81447808711 ++ R2=12.9995362506247 ++ DL3=0.000001738 ++ DC3=0.00000000000195 ++ DL4=0.00000000811 ++ DC4=0.0000000000000833 ++ DR3=0.48 ++ DR4=16680 ++ DR5=0.58 ++ DR6=266 ++ Rdc=0.154 ++ ck=2.32pF +.ends ET20H_7448640396_1.8m +*********** +.subckt ET20H_7448640397_2.7m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.0016169019162156 ++ L2=0.00163541824472393 ++ L3=0.000812998902402452 ++ L4=0.000555575905230456 ++ L5=1.85398834316071E-08 ++ L6=1.93742978105865E-07 ++ C1=2.84225221668491E-12 ++ C2=1.13999338673358E-12 ++ C3=1.08665921785653E-14 ++ RS1=5034.50230419101 ++ RS2=5313.38268635357 ++ RS3=5445.06055288674 ++ RS4=17228.0372034505 ++ RS5=1999.11326525974 ++ RS6=53.0747995048 ++ R2=161.349314520953 ++ DL3=0.000002538 ++ DC3=0.00000000000245 ++ DL4=0.00000000811 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=26680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.295 ++ ck=1.44pF +.ends ET20H_7448640397_2.7m +*********** +.subckt ET20H_7448640398_3.3m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.00124489196334796 ++ L2=0.00059637669243615 ++ L3=0.00180625851181269 ++ L4=0.000940503345906996 ++ L5=1.85237149375554E-09 ++ L6=7.5024967585581E-10 ++ C1=2.93998328976033E-12 ++ C2=4.49266712649602E-11 ++ C3=1.02656554890703E-10 ++ RS1=6345.33803822565 ++ RS2=2766.32754292941 ++ RS3=7035.48808621277 ++ RS4=16502.1388324551 ++ RS5=362.388245576368 ++ RS6=19.7318592643 ++ R2=3.594725011606 ++ DL3=0.000003238 ++ DC3=0.00000000000265 ++ DL4=0.000000001411 ++ DC4=0.00000000001433 ++ DR3=0.48 ++ DR4=27680 ++ DR5=0.48 ++ DR6=39266 ++ Rdc=0.562 ++ ck=1.2pF +.ends ET20H_7448640398_3.3m +*********** +.subckt ET20H_7448640399_3.9m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.00104643349948583 ++ L2=0.00111714898557354 ++ L3=0.000947609427637273 ++ L4=0.00305560903889871 ++ L5=7.98303962582749E-09 ++ L6=2.29465946382189E-09 ++ C1=2.87273581850198E-12 ++ C2=1.03979521373402E-11 ++ C3=9.70337184704443E-13 ++ RS1=2762.37435745242 ++ RS2=5472.57186748623 ++ RS3=6417.84360895059 ++ RS4=21909.735060152 ++ RS5=1397.54829863792 ++ RS6=6.35510657295 ++ R2=6.902676801912 ++ DL3=0.000003538 ++ DC3=0.00000000000285 ++ DL4=0.00000000811 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=45680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.278 ++ ck=1.54pF +.ends ET20H_7448640399_3.9m +*********** +.subckt ET20H_7448640400_5.6m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.00204643349948583 ++ L2=0.00111714898557354 ++ L3=0.000947609427637273 ++ L4=0.00305560903889871 ++ L5=7.98303962582749E-09 ++ L6=2.29465946382189E-09 ++ C1=2.87273581850198E-12 ++ C2=1.03979521373402E-11 ++ C3=9.70337184704443E-13 ++ RS1=14762.3743574524 ++ RS2=5472.57186748623 ++ RS3=6417.84360895059 ++ RS4=21909.735060152 ++ RS5=1397.54829863792 ++ RS6=6.35510657295 ++ R2=6.902676801912 ++ DL3=0.000004638 ++ DC3=0.00000000000285 ++ DL4=0.000000000811 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=35680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.514 ++ ck=1.4pF +.ends ET20H_7448640400_5.6m +*********** +.subckt ET20H_7448640401_6.8m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.00404643349948583 ++ L2=0.00111714898557354 ++ L3=0.000947609427637273 ++ L4=0.00305560903889871 ++ L5=7.98303962582749E-09 ++ L6=2.29465946382189E-09 ++ C1=2.87273581850198E-12 ++ C2=5.3979521373402E-12 ++ C3=9.70337184704443E-13 ++ RS1=24762.3743574524 ++ RS2=5472.57186748623 ++ RS3=6417.84360895059 ++ RS4=21909.735060152 ++ RS5=1397.54829863792 ++ RS6=6.35510657295 ++ R2=6.902676801912 ++ DL3=0.000005838 ++ DC3=0.00000000000285 ++ DL4=0.000000000811 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=35680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.604 ++ ck=1.4pF +.ends ET20H_7448640401_6.8m +*********** +.subckt ET20H_7448640402_10m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.0100464334994858 ++ L2=0.00111714898557354 ++ L3=0.000947609427637273 ++ L4=0.00305560903889871 ++ L5=7.98303962582749E-09 ++ L6=2.29465946382189E-09 ++ C1=2.87273581850198E-12 ++ C2=5.3979521373402E-12 ++ C3=9.70337184704443E-13 ++ RS1=74762.3743574524 ++ RS2=5472.57186748623 ++ RS3=6417.84360895059 ++ RS4=21909.735060152 ++ RS5=1397.54829863792 ++ RS6=6.35510657295 ++ R2=6.902676801912 ++ DL3=0.000009238 ++ DC3=0.00000000000285 ++ DL4=0.000000000811 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=35680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=1.02 ++ ck=2.9pF +.ends ET20H_7448640402_10m +*********** +.subckt ET20H_7448640403_18m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.0200464334994858 ++ L2=0.00511714898557354 ++ L3=0.000947609427637273 ++ L4=0.00305560903889871 ++ L5=7.98303962582749E-09 ++ L6=2.29465946382189E-09 ++ C1=2.87273581850198E-12 ++ C2=5.3979521373402E-12 ++ C3=9.70337184704443E-13 ++ RS1=124762.374357452 ++ RS2=5472.57186748623 ++ RS3=6417.84360895059 ++ RS4=21909.735060152 ++ RS5=1397.54829863792 ++ RS6=6.35510657295 ++ R2=6.902676801912 ++ DL3=0.000015238 ++ DC3=0.00000000000285 ++ DL4=0.000000000811 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=81680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=1.66 ++ ck=2.5pF +.ends ET20H_7448640403_18m +*********** +.subckt ET20H_7448640404_22m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.0300464334994858 ++ L2=0.00311714898557354 ++ L3=0.00147609427637273 ++ L4=0.00305560903889871 ++ L5=9.98303962582749E-09 ++ L6=2.29465946382189E-09 ++ C1=3.27273581850198E-12 ++ C2=5.3979521373402E-12 ++ C3=9.70337184704443E-13 ++ RS1=154762.374357452 ++ RS2=5472.57186748623 ++ RS3=6417.84360895059 ++ RS4=21909.735060152 ++ RS5=397.548298637929 ++ RS6=6.35510657295 ++ R2=6.902676801912 ++ DL3=0.000020238 ++ DC3=0.00000000000285 ++ DL4=0.000000000811 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=81680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=2.25 ++ ck=2.22pF +.ends ET20H_7448640404_22m +*********** +.subckt ET20H_7448640405_33m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.0400464334994858 ++ L2=0.00311714898557354 ++ L3=0.00147609427637273 ++ L4=0.00305560903889871 ++ L5=9.98303962582749E-09 ++ L6=2.29465946382189E-09 ++ C1=2.87273581850198E-12 ++ C2=5.3979521373402E-12 ++ C3=9.70337184704443E-13 ++ RS1=154762.374357452 ++ RS2=5472.57186748623 ++ RS3=6417.84360895059 ++ RS4=21909.735060152 ++ RS5=397.548298637929 ++ RS6=6.35510657295 ++ R2=6.902676801912 ++ DL3=0.000027238 ++ DC3=0.00000000000285 ++ DL4=0.000000000811 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=61680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=1.67 ++ ck=2.77pF +.ends ET20H_7448640405_33m +*********** +.subckt UT20V_7448640406_0.82m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000349839836666115 ++ L2=0.0000449848865674813 ++ L3=0.000729291843546601 ++ L4=5.67471514731328E-06 ++ L5=2.80321824811854E-09 ++ L6=2.08079707052894E-09 ++ C1=2.8982109209806E-12 ++ C2=3.46709914794984E-11 ++ C3=1.00756521123558E-13 ++ RS1=827.9893905354 ++ RS2=580.507263268679 ++ RS3=7922.16754059154 ++ RS4=13530.2674514301 ++ RS5=166.714388201208 ++ RS6=572.241272489226 ++ R2=34.2040695486952 ++ DL3=0.000000838 ++ DC3=0.00000000000265 ++ DL4=0.000000000811 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=11680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.0835 ++ ck=1.93pF +.ends UT20V_7448640406_0.82m +*********** +.subckt UT20V_7448640407_1.2m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.0000703119823707213 ++ L2=8.92995056511769E-06 ++ L3=0.00136528584770519 ++ L4=0.000166116194345672 ++ L5=2.13094924434655E-08 ++ L6=1.68982192415501E-08 ++ C1=3.82714587936407E-12 ++ C2=2.8240142937601E-09 ++ C3=8.25610019971753E-13 ++ RS1=1053.2663013811 ++ RS2=563.465266931374 ++ RS3=7575.65692823315 ++ RS4=4366.27293811896 ++ RS5=197.759329542719 ++ RS6=948.80036590475 ++ R2=1.47015015628146 ++ DL3=0.000001438 ++ DC3=0.00000000000265 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=11680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.12 ++ ck=2.31pF +.ends UT20V_7448640407_1.2m +*********** +.subckt UT20V_7448640408_1.8m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000349839836666115 ++ L2=0.000849848865674813 ++ L3=0.0017292918435466 ++ L4=5.67471514731328E-06 ++ L5=6.96173877496358E-07 ++ L6=9.96452624158199E-09 ++ C1=3.33463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=91.5793662352201 ++ RS2=8542.09260314847 ++ RS3=8432.76947949667 ++ RS4=84352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000001438 ++ DC3=0.00000000000265 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=11680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.162 ++ ck=3.6pF +.ends UT20V_7448640408_1.8m +*********** +.subckt UT20V_7448640409_2.2m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000149839836666115 ++ L2=0.00149848865674813 ++ L3=0.0015292918435466 ++ L4=5.67471514731328E-06 ++ L5=1.69617387749635E-06 ++ L6=9.96452624158199E-09 ++ C1=3.33463669795708E-12 ++ C2=1.87024559806227E-10 ++ C3=2.529379663444E-12 ++ RS1=291.57936623522 ++ RS2=11542.0926031484 ++ RS3=8432.76947949667 ++ RS4=84352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000002438 ++ DC3=0.00000000000265 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=26680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.215 ++ ck=2.66pF +.ends UT20V_7448640409_2.2m +*********** +.subckt UT20V_7448640410_2.7m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000749839836666115 ++ L2=0.000849848865674813 ++ L3=0.0027292918435466 ++ L4=5.67471514731328E-06 ++ L5=6.96173877496358E-07 ++ L6=9.96452624158199E-09 ++ C1=3.73463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=111.57936623522 ++ RS2=11542.0926031484 ++ RS3=13432.7694794966 ++ RS4=84352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000002938 ++ DC3=0.00000000000365 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=26680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.189 ++ ck=3.37pF +.ends UT20V_7448640410_2.7m +*********** +.subckt UT20V_7448640411_3.3m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000949839836666115 ++ L2=0.000849848865674813 ++ L3=0.0039292918435466 ++ L4=5.67471514731328E-06 ++ L5=6.96173877496358E-07 ++ L6=9.96452624158199E-09 ++ C1=3.53463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=111.57936623522 ++ RS2=19542.0926031484 ++ RS3=17432.7694794966 ++ RS4=94352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000003198 ++ DC3=0.00000000000355 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=26680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.217 ++ ck=3.03pF +.ends UT20V_7448640411_3.3m +*********** +.subckt UT20V_7448640413_5.6m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000949839836666115 ++ L2=0.000849848865674813 ++ L3=0.0069292918435466 ++ L4=5.67471514731328E-06 ++ L5=6.96173877496358E-07 ++ L6=9.96452624158199E-09 ++ C1=2.93463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=111.57936623522 ++ RS2=29542.0926031484 ++ RS3=32432.7694794966 ++ RS4=94352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000006198 ++ DC3=0.00000000000255 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=36680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.418 ++ ck=3.53pF +.ends UT20V_7448640413_5.6m +*********** +.subckt UT20V_7448640414_6.8m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000949839836666115 ++ L2=0.000849848865674813 ++ L3=0.0089292918435466 ++ L4=5.67471514731328E-06 ++ L5=6.96173877496358E-07 ++ L6=9.96452624158199E-09 ++ C1=3.53463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=111.57936623522 ++ RS2=59542.0926031484 ++ RS3=48432.7694794966 ++ RS4=94352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000007198 ++ DC3=0.00000000000315 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=56680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.47 ++ ck=2.8pF +.ends UT20V_7448640414_6.8m +*********** +.subckt UT20V_7448640415_10m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000449839836666115 ++ L2=0.000449848865674813 ++ L3=0.0129292918435466 ++ L4=5.67471514731328E-06 ++ L5=6.96173877496358E-07 ++ L6=9.96452624158199E-09 ++ C1=3.53463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=211.57936623522 ++ RS2=69542.0926031484 ++ RS3=68432.7694794966 ++ RS4=94352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000010198 ++ DC3=0.00000000000315 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=56680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.718 ++ ck=3.7pF +.ends UT20V_7448640415_10m +*********** +.subckt UT20V_7448640416_18m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.000449839836666115 ++ L2=0.000449848865674813 ++ L3=0.0229292918435466 ++ L4=5.67471514731328E-06 ++ L5=6.96173877496358E-07 ++ L6=9.96452624158199E-09 ++ C1=3.23463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=411.57936623522 ++ RS2=89542.0926031484 ++ RS3=118432.769479496 ++ RS4=94352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000018198 ++ DC3=0.00000000000315 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=56680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=1.22 ++ ck=4.71pF +.ends UT20V_7448640416_18m +*********** +.subckt UT20V_7448640417_22m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.0000449839836666115 ++ L2=0.0000449848865674813 ++ L3=0.0329292918435466 ++ L4=9.67471514731328E-06 ++ L5=6.96173877496358E-07 ++ L6=9.96452624158199E-09 ++ C1=3.93463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=111.57936623522 ++ RS2=159542.092603148 ++ RS3=188432.769479496 ++ RS4=94352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000023198 ++ DC3=0.00000000000405 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=56680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=1.7 ++ ck=3.22pF +.ends UT20V_7448640417_22m +*********** +.subckt UT20V_7448640418_33m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=4.49839836666115E-06 ++ L2=4.49848865674813E-06 ++ L3=0.0529292918435466 ++ L4=9.67471514731328E-06 ++ L5=6.96173877496358E-07 ++ L6=9.96452624158199E-09 ++ C1=3.53463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=111.57936623522 ++ RS2=159542.092603148 ++ RS3=188432.769479496 ++ RS4=94352.7577365101 ++ RS5=246.529234933992 ++ RS6=611.815693524294 ++ R2=1.4422510600994 ++ DL3=0.000037198 ++ DC3=0.00000000000315 ++ DL4=0.000000001011 ++ DC4=0.00000000000833 ++ DR3=0.48 ++ DR4=66680 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=2.5 ++ ck=3.27pF +.ends UT20V_7448640418_33m +*********** +.subckt UT20V_7448640412_3.9m 1 2 3 4 +X1 1 2 3 4 FC PARAMS: ++ L1=0.949839836666115m ++ L2=0.849848865674813m ++ L3=2.5292918435466m ++ L4=2.07471514731328E-06 ++ L5=2.96173877496358E-07 ++ L6=2.96452624158199E-09 ++ C1=6.50463669795708E-12 ++ C2=8.70245598062277E-11 ++ C3=2.529379663444E-12 ++ RS1=111.57936623522 ++ RS2=19542.0926031484 ++ RS3=17032.7694794966 ++ RS4=94352.7577365101 ++ RS5=245.529234933992 ++ RS6=6.815693524294 ++ R2=1.4422510600994 ++ DL3=2.4u ++ DC3=7.5p ++ DL4=1.011n ++ DC4=10.33p ++ DR3=0.48 ++ DR4=24000 ++ DR5=0.58 ++ DR6=9266 ++ Rdc=0.217 ++ ck=3.03pF +.ends UT20V_7448640412_3.9m +*********** diff --git a/spice/copy/sub/Contrib/Wurth/WE-FCL.lib b/spice/copy/sub/Contrib/Wurth/WE-FCL.lib new file mode 100755 index 0000000..e51afc2 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-FCL.lib @@ -0,0 +1,258 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-FCL +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT FCL 1 2 3 4 PARAMS: +L5 N011 N010 {L3} +R50 N011 N010 {Rs3} +C3 N500 N001 {C1} +R500 4 N500 {R2} +L1 4 N012 {L1} +R51 4 N012 {Rs1} +L3 N012 N011 {L2} +R52 N012 N011 {Rs2} +L6 N015 N014 {L3} +R53 N015 N014 {Rs3} +C4 N501 N013 {C1} +R501 3 N501 {R2} +L2 3 N016 {L1} +R54 3 N016 {Rs1} +L4 N016 N015 {L2} +R55 N016 N015 {Rs2} +L8 N014 N013 {L4} +R56 N014 N013 {Rs4} +L7 N010 N001 {L4} +R57 N010 N001 {Rs4} +L9 N001 N007 {L5} +R58 N001 N007 {Rs5} +C50 N001 N007 {C2} +L10 N013 N022 {L5} +R59 N013 N022 {Rs5} +C51 N013 N022 {C2} +L11 N007 N006 {L6} +R60 N007 N006 {Rs6} +C52 N007 N006 {C3} +L12 N022 N021 {L6} +R61 N022 N021 {Rs6} +C53 N022 N021 {C3} +R1 N002 1 {Rdc} +R2 N004 N002 {dR4} +C1 N003 N002 {dC3} +L17 N008 N002 {dL3} +L18 N017 N018 {dL3} +C2 N008 N018 {ck} +Ropen N008 N018 1000g +R3 N004 N003 {dR3} +R4 N019 N023 {dR3} +C9 N023 N017 {dC3} +R5 N019 N017 {dR4} +L19 N004 N008 {dL3} +L20 N018 N019 {dL3} +R6 N017 2 {Rdc} +R8 N006 N004 {dR6} +C10 N005 N004 {dC4} +L13 N009 N004 {dL4} +L14 N019 N020 {dL4} +C11 N009 N020 {ck} +R9 N006 N005 {dR5} +R10 N021 N024 {dR5} +C12 N024 N019 {dC4} +R11 N021 N019 {dR6} +L15 N006 N009 {dL4} +L16 N020 N021 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K6 L11 L12 1 +K8 L17 L18 L19 L20 0.9999 +K7 L13 L14 L15 L16 0.9999 +.ends FCL +********** +.SUBCKT ET35_744866103_10m 1 2 3 4 +X1 1 2 3 4 FCL PARAMS: ++ L1=0.00149839836666115 ++ L2=0.000389848865674813 ++ L3=0.011429291843546601 ++ L4=9.67471514731328e-006 ++ L5=6.96173877496358e-004 ++ L6=6.56452624158199e-008 ++ C1=9.93463669795708e-012 ++ C2=8.70245598062277e-011 ++ C3=3.9379663444007e-013 ++ Rs1=11.5793662352201 ++ Rs2=159542.09260314847 ++ Rs3=63732.76947949667 ++ Rs4=94352.7577365101 ++ Rs5=246.5292349339921 ++ Rs6=1411.8156935242947 ++ R2=12.4422510600994 ++ dL3=47198e-010 ++ dC3=9.5e-012 ++ dL4=5.11e-9 ++ dC4=5.33e-07 ++ dR3=1.48 ++ dR4=22668 ++ dR5=400.58 ++ dR6=5266 ++ Rdc=94.5m ++ ck=3.4p +.ends ET35_744866103_10m +******* +.SUBCKT ET35_744866104_100m 1 2 3 4 +X1 1 2 3 4 FCL PARAMS: ++ L1=0.0449839836666115 ++ L2=0.0799848865674813 ++ L3=0.011429291843546601 ++ L4=9.67471514731328e-006 ++ L5=6.96173877496358e-004 ++ L6=6.56452624158199e-008 ++ C1=9.33463669795708e-012 ++ C2=8.70245598062277e-011 ++ C3=3.9379663444007e-013 ++ Rs1=1100.5793662352201 ++ Rs2=852142.09260314847 ++ Rs3=163732.76947949667 ++ Rs4=94352.7577365101 ++ Rs5=246.5292349339921 ++ Rs6=711.8156935242947 ++ R2=30.4422510600994 ++ dL3=4719e-08 ++ dC3=1e-011 ++ dL4=6.11e-9 ++ dC4=6.33e-08 ++ dR3=1.48 ++ dR4=56768 ++ dR5=350.58 ++ dR6=9266 ++ Rdc=0.74 ++ ck=3.4p +.ends ET35_744866104_100m +******* +.SUBCKT ET35_744866223_22m 1 2 3 4 +X1 1 2 3 4 FCL PARAMS: ++ L1=0.0449839836666115 ++ L2=0.0159848865674813 ++ L3=0.011429291843546601 ++ L4=9.67471514731328e-006 ++ L5=6.96173877496358e-004 ++ L6=6.46452624158199e-008 ++ C1=9.13463669795708e-012 ++ C2=8.70245598062277e-011 ++ C3=3.9379663444007e-013 ++ Rs1=11.5793662352201 ++ Rs2=130542.09260314847 ++ Rs3=63732.76947949667 ++ Rs4=94352.7577365101 ++ Rs5=246.5292349339921 ++ Rs6=1111.8156935242947 ++ R2=12.4422510600994 ++ dL3=879e-08 ++ dC3=1.2e-011 ++ dL4=4.11e-9 ++ dC4=5.33e-05 ++ dR3=1.48 ++ dR4=36768 ++ dR5=200.58 ++ dR6=9266 ++ Rdc=0.1836 ++ ck=3.4p +.ends ET35_744866223_22m + ****** +.SUBCKT ET35_744866392_3.9m 1 2 3 4 +X1 1 2 3 4 FCL PARAMS: ++ L1=0.000299839836666115 ++ L2=0.000199848865674813 ++ L3=0.004929291843546601 ++ L4=9.67471514731328e-006 ++ L5=6.96173877496358e-004 ++ L6=4.06452624158199e-008 ++ C1=9.93463669795708e-012 ++ C2=8.70245598062277e-011 ++ C3=9.9379663444007e-013 ++ Rs1=211.5793662352201 ++ Rs2=19942.09260314847 ++ Rs3=23032.76947949667 ++ Rs4=9352.7577365101 ++ Rs5=256.5292349339921 ++ Rs6=1411.8156935242947 ++ R2=12.4422510600994 ++ dL3=20798e-010 ++ dC3=9.5e-012 ++ dL4=4.51e-9 ++ dC4=3.33e-07 ++ dR3=1.48 ++ dR4=13168 ++ dR5=600.58 ++ dR6=52606 ++ Rdc=52.08m ++ ck=3.4p +.ends ET35_744866392_3.9m +****** +.SUBCKT ET35_744866563_56m 1 2 3 4 +X1 1 2 3 4 FCL PARAMS: ++ L1=0.0299839836666115 ++ L2=0.0199848865674813 ++ L3=0.03629291843546601 ++ L4=9.67471514731328e-006 ++ L5=6.96173877496358e-004 ++ L6=4.56452624158199e-008 ++ C1=9.23463669795708e-012 ++ C2=8.70245598062277e-011 ++ C3=12.9379663444007e-013 ++ Rs1=1211.5793662352201 ++ Rs2=1109942.09260314847 ++ Rs3=1530032.76947949667 ++ Rs4=9352.7577365101 ++ Rs5=256.5292349339921 ++ Rs6=511.8156935242947 ++ R2=12.4422510600994 ++ dL3=28198e-09 ++ dC3=9.5e-012 ++ dL4=4.11e-9 ++ dC4=5.33e-08 ++ dR3=1.48 ++ dR4=72668 ++ dR5=100.58 ++ dR6=19266 ++ Rdc=480m ++ ck=3.4p +.ends ET35_744866563_56m +********** +.SUBCKT ET35_744866692_6.9m 1 2 3 4 +X1 1 2 3 4 FCL PARAMS: ++ L1=3m ++ L2=3m ++ L3=0.004929291843546601 ++ L4=9.67471514731328e-006 ++ L5=6.96173877496358e-004 ++ L6=4.06452624158199e-008 ++ C1=8p ++ C2=8.70245598062277e-011 ++ C3=9.9379663444007e-013 ++ Rs1=50000 ++ Rs2=38000 ++ Rs3=23032.76947949667 ++ Rs4=9352.7577365101 ++ Rs5=256.5292349339921 ++ Rs6=1411.8156935242947 ++ R2=12.4422510600994 ++ dL3=4u ++ dC3=1p ++ dL4=4.51e-9 ++ dC4=3.33e-07 ++ dR3=0.2 ++ dR4=20800 ++ dR5=600.58 ++ dR6=52606 ++ Rdc=0.5 ++ ck=5.5p +.ends ET35_744866692_6.9m diff --git a/spice/copy/sub/Contrib/Wurth/WE-HIDA_DUAL.lib b/spice/copy/sub/Contrib/Wurth/WE-HIDA_DUAL.lib new file mode 100755 index 0000000..598429a --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-HIDA_DUAL.lib @@ -0,0 +1,119 @@ +.subckt 1415_7444211415082_8.2u 1 2 3 4 +L1 1 N1 7.433u +Rdc1 N1 4 9.2m +Cp1 1 4 8.399p +Rp1 1 4 2314 +L2 2 N2 7.433u +Rdc2 N2 3 9.2m +Cp2 2 3 8.399p +Rp2 2 3 2314 +Rg1 1 0 500meg +Rg2 2 0 500meg +Rg3 3 0 500meg +Rg4 4 0 500meg +.ends +******* +.subckt 1415_7444211415100_10u 1 2 3 4 +L1 1 N1 9.038u +Rdc1 N1 4 9.2m +Cp1 1 4 9.155p +Rp1 1 4 2396 +L2 2 N2 9.038u +Rdc2 N2 3 9.2m +Cp2 2 3 9.155p +Rp2 2 3 2396 +Rg1 1 0 500meg +Rg2 2 0 500meg +Rg3 3 0 500meg +Rg4 4 0 500meg +.ends +******* +.subckt 1415_7444211415150_15u 1 2 3 4 +L1 1 N1 13.628u +Rdc1 N1 4 14.6m +Cp1 1 4 11.718p +Rp1 1 4 2908 +L2 2 N2 13.628u +Rdc2 N2 3 14.6m +Cp2 2 3 11.718p +Rp2 2 3 2908 +Rg1 1 0 500meg +Rg2 2 0 500meg +Rg3 3 0 500meg +Rg4 4 0 500meg +.ends +******* +.subckt 1415_7444211415220_22u 1 2 3 4 +L1 1 N1 19.457u +Rdc1 N1 4 14.8m +Cp1 1 4 11.402p +Rp1 1 4 3381 +L2 2 N2 19.457u +Rdc2 N2 3 14.8m +Cp2 2 3 11.402p +Rp2 2 3 3381 +Rg1 1 0 500meg +Rg2 2 0 500meg +Rg3 3 0 500meg +Rg4 4 0 500meg +.ends +******* +.subckt 1521_74441521082_8.2u 1 2 3 4 +L1 1 N1 7.498u +Rdc1 N1 4 6.2m +Cp1 1 4 7.178p +Rp1 1 4 2854 +L2 2 N2 7.498u +Rdc2 N2 3 6.2m +Cp2 2 3 7.178p +Rp2 2 3 2854 +Rg1 1 0 500meg +Rg2 2 0 500meg +Rg3 3 0 500meg +Rg4 4 0 500meg +.ends +******* +.subckt 1521_74441521100_10u 1 2 3 4 +L1 1 N1 9.098u +Rdc1 N1 4 6.3m +Cp1 1 4 7.474p +Rp1 1 4 2870 +L2 2 N2 9.098u +Rdc2 N2 3 6.3m +Cp2 2 3 7.474p +Rp2 2 3 2870 +Rg1 1 0 500meg +Rg2 2 0 500meg +Rg3 3 0 500meg +Rg4 4 0 500meg +.ends +******* +.subckt 1521_74441521150_15u 1 2 3 4 +L1 1 N1 14.504u +Rdc1 N1 4 8.5m +Cp1 1 4 7.06p +Rp1 1 4 3720 +L2 2 N2 14.504u +Rdc2 N2 3 8.5m +Cp2 2 3 7.06p +Rp2 2 3 3720 +Rg1 1 0 500meg +Rg2 2 0 500meg +Rg3 3 0 500meg +Rg4 4 0 500meg +.ends +******* +.subckt 1521_74441521220_22u 1 2 3 4 +L1 1 N1 21.78u +Rdc1 N1 4 13.6m +Cp1 1 4 7.729p +Rp1 1 4 5558 +L2 2 N2 21.78u +Rdc2 N2 3 13.6m +Cp2 2 3 7.729p +Rp2 2 3 5558 +Rg1 1 0 500meg +Rg2 2 0 500meg +Rg3 3 0 500meg +Rg4 4 0 500meg +.ends diff --git a/spice/copy/sub/Contrib/Wurth/WE-LF.lib b/spice/copy/sub/Contrib/Wurth/WE-LF.lib new file mode 100755 index 0000000..0b233b3 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-LF.lib @@ -0,0 +1,1658 @@ +********************************************************* +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-LF +* Library Type: LTspice +* Version: rev17b +* Created/modified by: Fredo +* Date and Time : 2017-12-19 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +******************************************************** +.SUBCKT LF 1 2 3 4 PARAMS: ++ L1=0.00060538 ++ L2=0.00010035 ++ L3=0.00004247 ++ L4=0.00001022 ++ L5=0.000000036 ++ C1=0.000000000003 ++ C2=0.000000000001 ++ RS1=8828 ++ RS2=1447 ++ RS3=703 ++ RS4=678 ++ RS5=509 ++ R2=0.11 ++ DL3=0.00000031037 ++ DL4=0.00000001106 ++ DC3=0.00000000000019056 ++ DC4=0.000000000007 ++ DR3=1000 ++ DR4=4500 ++ DR5=11000 ++ DR6=438 ++ Rdc=0.43 ++ ck=12.5pF +R_R9 N12325 3 {R2} +R_R8 N13265 N13287 {Rs4} +Kn_K6 L_L11 L_L12 ++ L_L13 L_L14 0.9999 +R_R3 N12571 N12583 {Rs3} +R_R10 N13777 4 {R2} +C_C10 N13029 N12821 {ck} +R_R20 N13215 N13229 {dR4} +L_L11 N12821 N12295 {dL4} +R_R17 N12267 N12273 {dR3} +L_L8 N13265 N13287 {L4} +R_R7 N13287 N13305 {Rs3} +L_L9 N12295 N12307 {L5} +Kn_K4 L_L7 L_L8 1 +R_R2 N12583 N12599 {Rs2} +Kn_K5 L_L9 L_L10 1 +R_R16 N13229 N13249 {dR6} +Kn_K7 L_L15 L_L16 ++ L_L17 L_L18 0.9999 +C_C5 N12273 N12289 {dC4} +L_L6 N13287 N13305 {L3} +L_L7 N12307 N12571 {L4} +R_R6 N13305 N13319 {Rs2} +R_R21 1 N12257 {Rdc} +Kn_K3 L_L5 L_L6 1 +L_L16 N12257 N12799 {dL3} +C_C8 N13215 N13741 {dC3} +L_L18 N13023 N13215 {dL3} +R_R1 N12599 3 {Rs1} +R_R13 N12289 N12295 {dR5} +L_L4 N13305 N13319 {L2} +L_L5 N12571 N12583 {L3} +R_R15 N13755 N13249 {dR5} +R_R5 N13319 4 {Rs1} +R_R18 N12257 N12273 {dR4} +Kn_K2 L_L3 L_L4 1 +R_R19 N13741 N13229 {dR3} +L_L15 N12799 N12273 {dL3} +L_L17 N13229 N13023 {dL3} +L_L3 N12583 N12599 {L2} +R_R11 N12295 N12307 {Rs5} +L_L2 N13319 4 {L1} +C_C4 N13249 N13265 {C2} +L_L10 N13249 N13265 {L5} +Kn_K1 L_L1 L_L2 1 +R_R14 N12273 N12295 {dR6} +C_C6 N13229 N13755 {dC4} +L_L12 N12273 N12821 {dL4} +L_L14 N13029 N13229 {dL4} +L_L1 N12599 3 {L1} +C_C1 N12307 N12325 {C1} +R_R12 N13249 N13265 {Rs5} +C_C2 N13265 N13777 {C1} +R_R22 2 N13215 {Rdc} +C_C9 N13023 N12799 {ck} +R_R4 N12307 N12571 {Rs4} +C_C3 N12295 N12307 {C2} +L_L13 N13249 N13029 {dL4} +C_C7 N12257 N12267 {dC3} +.ends LF +***** +.SUBCKT LF26 1 2 3 4 PARAMS: ++ L1=11m ++ L2=0.08m ++ L3=155m ++ L4=162.5m ++ L5=1090n ++ L6=1.99964526241581E-07 ++ C1=47p ++ C2=43p ++ C3=2.529379663444E-12 ++ Rs1=110k ++ RS2=400 ++ RS3=400 ++ RS4=400 ++ RS5=570 ++ RS6=1 ++ R2=1.4422510600994 ++ DL3=0.000005 ++ DL4=0.000000145 ++ DC3=0.000000000044 ++ DC4=0.0000000000484 ++ DR3=17 ++ dR4=12k ++ DR5=23 ++ dR6=.6k ++ Rdc=0.073 ++ ck=1pF +L5 N011 N010 {L3} +R50 N011 N010 {Rs3} +C3 N500 N001 {C1} +R500 3 N500 {R2} +L1 3 N012 {L1} +R51 3 N012 {Rs1} +L3 N012 N011 {L2} +R52 N012 N011 {Rs2} +L6 N015 N014 {L3} +R53 N015 N014 {Rs3} +C4 N501 N013 {C1} +R501 4 N501 {R2} +L2 4 N016 {L1} +R54 4 N016 {Rs1} +L4 N016 N015 {L2} +R55 N016 N015 {Rs2} +L8 N014 N013 {L4} +R56 N014 N013 {Rs4} +L7 N010 N001 {L4} +R57 N010 N001 {Rs4} +L9 N001 N007 {L5} +R58 N001 N007 {Rs5} +C50 N001 N007 {C2} +L10 N013 N022 {L5} +R59 N013 N022 {Rs5} +C51 N013 N022 {C2} +L11 N007 N006 {L6} +R60 N007 N006 {Rs6} +C52 N007 N006 {C3} +L12 N022 N021 {L6} +R61 N022 N021 {Rs6} +C53 N022 N021 {C3} +R1 N002 1 {Rdc} +R2 N004 N002 {dR4} +C1 N003 N002 {dC3} +L17 N008 N002 {dL3} +L18 N017 N018 {dL3} +C2 N008 N018 {ck} +R3 N004 N003 {dR3} +R4 N019 N023 {dR3} +C9 N023 N017 {dC3} +R5 N019 N017 {dR4} +L19 N004 N008 {dL3} +L20 N018 N019 {dL3} +R6 N017 2 {Rdc} +R8 N006 N004 {dR6} +C10 N005 N004 {dC4} +L13 N009 N004 {dL4} +L14 N019 N020 {dL4} +C11 N009 N020 {ck} +R9 N006 N005 {dR5} +R10 N021 N024 {dR5} +C12 N024 N019 {dC4} +R11 N021 N019 {dR6} +L15 N006 N009 {dL4} +L16 N020 N021 {dL4} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K6 L11 L12 1 +K8 L17 L18 L19 L20 0.9999 +K7 L13 L14 L15 L16 0.9999 +.ends LF26 +***** +.subckt LF_SV_74461240004_0m4 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000000185 ++ DC3=0.000000000007 ++ DL4=0.000000007 ++ DC4=0.000000000005 ++ DR3=27 ++ DR4=3000 ++ DR5=23 ++ DR6=990 ++ Rdc=0.013 ++ ck=1pF ++ L1=0.4m ++ L2=0.3m ++ L3=1u ++ L4=2u ++ L5=25n ++ C1=2300.06f ++ C2=1270.02f ++ RS1=3000 ++ RS2=122 ++ RS3=1 ++ RS4=1 ++ RS5=600 ++ R2=1.41 +.ends LF_SV_74461240004_0m4 +***** +.subckt LF_SV_7446122001_1m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ dL3=370n ++ dL4=17n ++ dC3=7p ++ dC4=2p ++ DR3=1 ++ DR4=3200 ++ DR5=1 ++ DR6=500 ++ Rdc=0.04 ++ ck=2pF ++ L1=0.000721 ++ L2=0.000107 ++ L3=0.00013 ++ L4=0.00000077 ++ L5=0.00000005 ++ C1=0.00000000000222 ++ C2=0.00000000000137 ++ RS1=5213 ++ RS2=405 ++ RS3=309 ++ RS4=3423 ++ RS5=690 ++ R2=6 +.ends LF_SV_7446122001_1m +***** +.subckt LF_SV_7446122003_3m3 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000145 ++ DL4=0.000000067 ++ DC3=0.000000000014 ++ DC4=0.000000000017 ++ DR3=27 ++ dR4=20k ++ DR5=23 ++ DR6=3990 ++ Rdc=0.1 ++ ck=1pF ++ L1=2.2m ++ L2=1m ++ L3=1m ++ L4=4u ++ L5=210.4n ++ C1=4.5p ++ C2=20p ++ Rs1=20k ++ RS2=5600 ++ RS3=500 ++ RS4=600 ++ RS5=900 ++ R2=10.41 +.ends LF_SV_7446122003_3m3 +***** +.subckt LF_SV_7446121007_6m8 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000023 ++ DL4=0.000000097 ++ DC3=0.000000000014 ++ DC4=0.000000000015 ++ DR3=27 ++ dR4=18k ++ DR5=23 ++ DR6=2500 ++ Rdc=0.2 ++ ck=2pF ++ L1=6.2m ++ L2=1m ++ L3=1m ++ L4=4u ++ L5=500.4n ++ C1=5.2p ++ C2=28p ++ Rs1=25k ++ Rs2=10k ++ RS3=500 ++ RS4=600 ++ RS5=900 ++ R2=10.41 +.ends LF_SV_7446121007_6m8 +***** +.subckt LF_SV_7446121010_10m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000036 ++ DL4=0.00000021 ++ DC3=0.000000000014 ++ DC4=0.000000000015 ++ DR3=27 ++ dR4=20k ++ DR5=23 ++ DR6=3000 ++ Rdc=0.366 ++ ck=5.8pF ++ L1=8.6m ++ L2=1m ++ L3=1m ++ L4=5u ++ L5=610n ++ C1=6.8p ++ C2=28p ++ Rs1=42k ++ Rs2=23k ++ RS3=500 ++ RS4=600 ++ RS5=1600 ++ R2=10.41 +.ends LF_SV_7446121010_10m +***** +.subckt LF_SV_7446121018_18m 1 2 3 4 +X1 1 2 3 4 LF26 PARAMS: ++ L1=20.2m ++ L2=0.08m ++ L3=1m ++ L4=4u ++ L5=900.4n ++ L6=1.99964526241581E-07 ++ C1=7.1p ++ C2=28p ++ C3=2.529379663444E-12 ++ Rs1=120k ++ RS2=400 ++ RS3=400 ++ RS4=400 ++ RS5=900 ++ RS6=1 ++ R2=10.4422510600994 ++ DL3=0.000007 ++ DL4=0.000000297 ++ DC3=0.0000000000095 ++ DC4=0.000000000015 ++ DR3=47 ++ dR4=32k ++ DR5=23 ++ DR6=2800 ++ Rdc=0.5 ++ ck=1pF +.ends LF_SV_7446121018_18m +***** +.subckt LF_SV_7446120027_27m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00001 ++ DL4=0.000000118 ++ DC3=0.000000000018 ++ DC4=0.00000000001 ++ DR3=27 ++ dR4=25k ++ DR5=23 ++ DR6=2000 ++ Rdc=0.8 ++ ck=9.8pF ++ L1=21m ++ L2=12m ++ L3=1m ++ L4=5u ++ L5=70n ++ C1=20p ++ C2=28p ++ Rs1=99k ++ Rs2=33k ++ RS3=500 ++ RS4=600 ++ RS5=1000 ++ R2=10.41 +.ends LF_SV_7446120027_27m +***** +.subckt LF_SV_7446120039_39m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000017 ++ DL4=0.000000042 ++ DC3=0.000000000019 ++ DC4=0.00000000001 ++ DR3=27 ++ dR4=45k ++ DR5=23 ++ DR6=2000 ++ Rdc=1.13 ++ ck=9.8pF ++ L1=20m ++ L2=12m ++ L3=1m ++ L4=5u ++ L5=620n ++ C1=22p ++ C2=28p ++ RS1=220000 ++ RS2=83000 ++ RS3=500 ++ RS4=600 ++ RS5=600 ++ R2=10.41 +.ends LF_SV_7446120039_39m +***** +.subckt LF_SV_7446120047_47m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000014 ++ DL4=0.000001342 ++ DC3=0.000000000014 ++ DC4=0.000000000001 ++ DR3=27 ++ dR4=35k ++ DR5=230 ++ dR6=22k ++ Rdc=1.73 ++ ck=11pF ++ L1=36m ++ L2=12m ++ L3=1m ++ L4=5u ++ L5=255n ++ C1=9p ++ C2=14p ++ Rs1=220k ++ Rs2=83k ++ RS3=500 ++ RS4=600 ++ RS5=1400 ++ R2=10.41 +.ends LF_SV_7446120047_47m +***** +.subckt LF_MV_74462250007_0m7 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000025 ++ DL4=0.000000067 ++ DC3=0.000000000014 ++ DC4=0.000000000017 ++ DR3=27 ++ dR4=20k ++ DR5=23 ++ DR6=1990 ++ Rdc=0.013 ++ ck=1pF ++ L1=5m ++ L2=0.9m ++ L3=1m ++ L4=5u ++ L5=190n ++ C1=6.3p ++ C2=26p ++ Rs1=32k ++ Rs2=6k ++ RS3=500 ++ RS4=600 ++ RS5=600 ++ R2=10.41 +.ends LF_MV_74462250007_0m7 +***** +.subckt LF_MV_7446223001_1m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000000405 ++ DL4=0.000000012 ++ DC3=0.000000000009 ++ DC4=0.000000000012 ++ DR3=27 ++ dR4=5k ++ DR5=23 ++ DR6=4990 ++ Rdc=0.026 ++ ck=0.8pF ++ L1=0.000764 ++ L2=0.000362 ++ L3=0.000001 ++ L4=0.00000221 ++ L5=0.000000033 ++ C1=0.0000000000032 ++ C2=0.0000000000049 ++ RS1=4628 ++ RS2=629 ++ RS3=1222 ++ RS4=4989 ++ RS5=383 ++ R2=15 +.ends LF_MV_7446223001_1m +***** +.subckt LF_MV_7446222002_2m2 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000012 ++ DL4=0.000000038 ++ DC3=0.000000000017 ++ DC4=0.000000000012 ++ DR3=27 ++ dR4=10k ++ DR5=23 ++ DR6=4990 ++ Rdc=0.04 ++ ck=2.2pF ++ L1=2.5m ++ L2=90u ++ L3=100u ++ L4=5u ++ L5=105n ++ C1=4.3p ++ C2=6p ++ Rs1=15k ++ RS2=800 ++ RS3=500 ++ RS4=600 ++ RS5=1200 ++ R2=10.41 +.ends LF_MV_7446222002_2m2 +***** +.subckt LF_MV_7446222003_3m3 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000022 ++ DL4=0.000000088 ++ DC3=0.0000000000125 ++ DC4=0.0000000000115 ++ DR3=27 ++ dR4=14k ++ DR5=23 ++ DR6=2990 ++ Rdc=0.08 ++ ck=2.2pF ++ L1=4.5m ++ L2=900u ++ L3=100u ++ L4=5u ++ L5=180n ++ C1=5.3p ++ C2=6p ++ Rs1=20k ++ RS2=800 ++ RS3=500 ++ RS4=600 ++ RS5=1300 ++ R2=10.41 +.ends LF_MV_7446222003_3m3 +***** +.subckt LF_MV_7446222004_4m2 1 2 3 4 +X1 1 2 3 4 LF26 PARAMS: ++ L1=7.2m ++ L2=0.03m ++ L3=.5m ++ L4=4u ++ L5=900.4n ++ L6=1.99964526241581E-07 ++ C1=9.8p ++ C2=20p ++ C3=2.529379663444E-12 ++ Rs1=35k ++ RS2=400 ++ RS3=400 ++ RS4=400 ++ RS5=1900 ++ RS6=1 ++ R2=10.4422510600994 ++ DL3=0.0000028 ++ DL4=0.000000108 ++ DC3=0.0000000000125 ++ DC4=0.0000000000115 ++ DR3=27 ++ dR4=14k ++ DR5=23 ++ DR6=2990 ++ Rdc=0.13 ++ ck=1pF +.ends LF_MV_7446222004_4m2 +***** +.subckt LF_MV_7446222007_6m8 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000015 ++ DL4=0.000000058 ++ DC3=0.0000000000155 ++ DC4=0.000000000012 ++ DR3=27 ++ dR4=14k ++ DR5=23 ++ DR6=5990 ++ Rdc=0.05 ++ ck=2.2pF ++ L1=3m ++ L2=1m ++ L3=110u ++ L4=5u ++ L5=250n ++ C1=4.3p ++ C2=4p ++ Rs1=15k ++ RS2=800 ++ RS3=500 ++ RS4=600 ++ RS5=1600 ++ R2=10.41 +.ends LF_MV_7446222007_6m8 +***** +.subckt LF_MV_7446221010_10m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000049 ++ DL4=0.000000138 ++ DC3=0.0000000000108 ++ DC4=0.000000000022 ++ DR3=27 ++ dR4=30k ++ DR5=23 ++ DR6=2990 ++ Rdc=0.16 ++ ck=2.2pF ++ L1=8.6m ++ L2=5m ++ L3=410u ++ L4=5u ++ L5=279n ++ C1=5.7p ++ C2=15p ++ Rs1=49k ++ Rs2=15k ++ RS3=500 ++ RS4=2500 ++ RS5=1100 ++ R2=10.41 +.ends LF_MV_7446221010_10m +***** +.subckt LF_MV_7446221012_12m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000062 ++ DL4=0.000000078 ++ DC3=0.0000000000228 ++ DC4=0.000000000048 ++ DR3=27 ++ dR4=18k ++ DR5=23 ++ DR6=1990 ++ Rdc=0.186 ++ ck=2.2pF ++ L1=8.7m ++ L2=5m ++ L3=410u ++ L4=5u ++ L5=979n ++ C1=6.9p ++ C2=15p ++ Rs1=59k ++ Rs2=15k ++ RS3=500 ++ RS4=2500 ++ RS5=1100 ++ R2=10.41 +.ends LF_MV_7446221012_12m +***** +.subckt LF_MV_7446221027_27m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000128 ++ DL4=0.00000019 ++ DC3=0.0000000000228 ++ DC4=0.000000000048 ++ DR3=27 ++ dR4=25k ++ DR5=23 ++ DR6=5990 ++ Rdc=0.46 ++ ck=1.5pF ++ L1=32.7m ++ L2=5m ++ L3=0.41m ++ L4=5u ++ L5=769n ++ C1=6.9p ++ C2=15p ++ Rs1=110k ++ Rs2=65k ++ RS3=500 ++ RS4=2500 ++ RS5=1400 ++ R2=10.41 +.ends LF_MV_7446221027_27m +***** +.subckt LF_MV_7446220047_47m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000238 ++ DL4=0.00000042 ++ DC3=0.0000000000238 ++ DC4=0.000000000048 ++ DR3=27 ++ dR4=70k ++ DR5=23 ++ DR6=2990 ++ Rdc=1.06 ++ ck=1.3pF ++ L1=39m ++ L2=5m ++ L3=0.2m ++ L4=5u ++ L5=2u ++ C1=6.9p ++ C2=15p ++ Rs1=180k ++ Rs2=65k ++ RS3=500 ++ RS4=2500 ++ RS5=3500 ++ R2=10.41 +.ends LF_MV_7446220047_47m +***** +.subckt LF_LV_7446326002_1m8 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000005 ++ DL4=0.000000018 ++ DC3=0.0000000000165 ++ DC4=0.000000000014 ++ DR3=27 ++ dR4=6k ++ DR5=23 ++ dR6=7k ++ Rdc=0.013 ++ ck=0.8pF ++ L1=1.8m ++ L2=80u ++ L3=23u ++ L4=4u ++ L5=105n ++ C1=4.5p ++ C2=1.5p ++ RS1=4000 ++ RS2=1600 ++ RS3=1500 ++ RS4=200 ++ RS5=900 ++ R2=1 +.ends LF_LV_7446326002_1m8 +***** +.subckt LF_LV_7446323003_2m7 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000009 ++ DL4=0.000000026 ++ DC3=0.0000000000165 ++ DC4=0.000000000014 ++ DR3=27 ++ dR4=8k ++ DR5=23 ++ dR6=7k ++ Rdc=0.04 ++ ck=1.8pF ++ L1=2.8m ++ L2=280u ++ L3=23u ++ L4=4u ++ L5=110n ++ C1=3.9p ++ C2=2.9p ++ RS1=5000 ++ RS2=3200 ++ RS3=1500 ++ RS4=200 ++ RS5=900 ++ R2=1 +.ends LF_LV_7446323003_2m7 +***** +.subckt LF_LV_7446323004_4m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000145 ++ DL4=0.000000048 ++ DC3=0.00000000002 ++ DC4=0.000000000018 ++ DR3=27 ++ dR4=11k ++ DR5=23 ++ dR6=7k ++ Rdc=0.046 ++ ck=2pF ++ L1=4.6m ++ L2=280u ++ L3=23u ++ L4=4u ++ L5=152n ++ C1=5.2p ++ C2=4.9p ++ Rs1=20k ++ RS2=2200 ++ RS3=1500 ++ RS4=200 ++ RS5=950 ++ R2=1 +.ends LF_LV_7446323004_4m +***** +.subckt LF_LV_7446322007_6m8 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000175 ++ DL4=0.000000099 ++ DC3=0.000000000017 ++ DC4=0.000000000009 ++ DR3=27 ++ dR4=16k ++ DR5=23 ++ dR6=6k ++ Rdc=0.106 ++ ck=2pF ++ L1=6.6m ++ L2=280u ++ L3=23u ++ L4=4u ++ L5=230n ++ C1=5.1p ++ C2=4.9p ++ Rs1=34k ++ RS2=2200 ++ RS3=1500 ++ RS4=200 ++ RS5=1250 ++ R2=1 +.ends LF_LV_7446322007_6m8 +***** +.subckt LF_LV_7446322010_10m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000031 ++ DL4=0.000000149 ++ DC3=0.0000000000183 ++ DC4=0.000000000012 ++ DR3=27 ++ dR4=16k ++ DR5=23 ++ dR6=4k ++ Rdc=0.12 ++ ck=2.2pF ++ L1=12m ++ L2=280u ++ L3=23u ++ L4=4u ++ L5=380n ++ C1=6.6p ++ C2=7.9p ++ Rs1=64k ++ RS2=1200 ++ RS3=1500 ++ RS4=200 ++ RS5=1750 ++ R2=1 +.ends LF_LV_7446322010_10m +***** +.subckt LF_LV_7446321027_27m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000087 ++ DL4=0.0000003 ++ DC3=0.000000000026 ++ DC4=0.000000000025 ++ DR3=27 ++ dR4=26k ++ DR5=23 ++ dR6=4.4k ++ Rdc=0.426 ++ ck=2.2pF ++ L1=24m ++ L2=280u ++ L3=23u ++ L4=4u ++ L5=700n ++ C1=7.5p ++ C2=9.9p ++ Rs1=64k ++ RS2=1200 ++ RS3=1500 ++ RS4=200 ++ RS5=1550 ++ R2=1 +.ends LF_LV_7446321027_27m +***** +.subckt LF_LV_7446321033_33m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000097 ++ DL4=0.00000028 ++ DC3=0.000000000027 ++ DC4=0.000000000025 ++ DR3=27 ++ dR4=26k ++ DR5=23 ++ dR6=4.4k ++ Rdc=0.566 ++ ck=2.8pF ++ L1=35m ++ L2=280u ++ L3=23u ++ L4=4u ++ L5=650n ++ C1=7.1p ++ C2=9.9p ++ Rs1=84k ++ RS2=1200 ++ RS3=1500 ++ RS4=200 ++ RS5=2000 ++ R2=1 +.ends LF_LV_7446321033_33m +***** +.subckt LF_LV_7446321050_50m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000168 ++ DL4=0.00000068 ++ DC3=0.000000000023 ++ DC4=0.000000000022 ++ DR3=27 ++ dR4=32k ++ DR5=23 ++ dR6=6k ++ Rdc=0.8 ++ ck=2.8pF ++ L1=60m ++ L2=4.2m ++ L3=23u ++ L4=4u ++ L5=1.2u ++ C1=8p ++ C2=16p ++ Rs1=220k ++ RS2=1200 ++ RS3=1500 ++ RS4=200 ++ RS5=2500 ++ R2=1 +.ends LF_LV_7446321050_50m +***** +.subckt LF_XV_7446424002_2m2 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000085 ++ DL4=0.000000062 ++ DC3=0.000000000018 ++ DC4=0.000000000008 ++ DR3=27 ++ dR4=7k ++ DR5=23 ++ DR6=2590 ++ Rdc=0.025 ++ ck=1.4pF ++ L1=1.5m ++ L2=0.28m ++ L3=23u ++ L4=4u ++ L5=130n ++ C1=4.5p ++ C2=4p ++ RS1=5500 ++ RS2=2000 ++ RS3=1000 ++ RS4=200 ++ RS5=600 ++ R2=1 +.ends LF_XV_7446424002_2m2 +***** +.subckt LF_XV_7446424003_3m3 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000145 ++ DL4=0.000000062 ++ DC3=0.000000000029 ++ DC4=0.000000000027 ++ DR3=27 ++ dR4=10k ++ DR5=23 ++ DR6=5590 ++ Rdc=0.0566 ++ ck=1.4pF ++ L1=2.5m ++ L2=0.28m ++ L3=23u ++ L4=4u ++ L5=260n ++ C1=5.5p ++ C2=3p ++ Rs1=14.5k ++ RS2=2400 ++ RS3=400 ++ RS4=200 ++ RS5=1000 ++ R2=1 +.ends LF_XV_7446424003_3m3 +***** +.subckt LF_XV_7446422007_6m8 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000285 ++ DL4=0.000000122 ++ DC3=0.0000000000185 ++ DC4=0.000000000017 ++ DR3=27 ++ dR4=15k ++ DR5=23 ++ DR6=5590 ++ Rdc=0.08 ++ ck=0.9pF ++ L1=5.5m ++ L2=0.28m ++ L3=23u ++ L4=4u ++ L5=400n ++ C1=4.8p ++ C2=4.3p ++ Rs1=14.5k ++ RS2=5400 ++ RS3=400 ++ RS4=200 ++ RS5=1600 ++ R2=1 +.ends LF_XV_7446422007_6m8 +***** +.subckt LF_SH_74466240007_0m7 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000031 ++ DL4=0.00000002 ++ DC3=0.0000000000075 ++ DC4=0.0000000000008 ++ DR3=17 ++ dR4=4.5k ++ DR5=23 ++ dR6=2k ++ Rdc=0.2 ++ ck=2.3pF ++ L1=500u ++ L2=80u ++ L3=23u ++ L4=4u ++ L5=60n ++ C1=2.8p ++ C2=0.5p ++ RS1=5500 ++ RS2=1400 ++ RS3=400 ++ RS4=200 ++ RS5=800 ++ R2=1 +.ends LF_SH_74466240007_0m7 +***** +.subckt LF_SH_7446622001_1m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000051 ++ DL4=0.000000034 ++ DC3=0.0000000000085 ++ DC4=0.0000000000008 ++ DR3=17 ++ dR4=6k ++ DR5=23 ++ dR6=1.5k ++ Rdc=0.04 ++ ck=2pF ++ L1=1.2m ++ L2=120u ++ L3=23u ++ L4=4u ++ L5=90n ++ C1=3.1p ++ C2=0.7p ++ RS1=6500 ++ RS2=1400 ++ RS3=400 ++ RS4=200 ++ RS5=1000 ++ R2=1 +.ends LF_SH_7446622001_1m +***** +.subckt LF_SH_7446622002_2m2 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000009 ++ DL4=0.000000044 ++ DC3=0.000000000011 ++ DC4=0.0000000000065 ++ DR3=17 ++ dR4=8k ++ DR5=23 ++ dR6=1.5k ++ Rdc=0.066 ++ ck=1.5pF ++ L1=2m ++ L2=620u ++ L3=23u ++ L4=4u ++ L5=120n ++ C1=3.7p ++ C2=2p ++ Rs1=10k ++ RS2=6400 ++ RS3=400 ++ RS4=200 ++ RS5=1000 ++ R2=1 +.ends LF_SH_7446622002_2m2 +***** +.subckt LF_SH_7446622003_3m3 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000016 ++ DL4=0.000000044 ++ DC3=0.000000000008 ++ DC4=0.000000000013 ++ DR3=17 ++ dR4=12k ++ DR5=23 ++ dR6=1k ++ Rdc=0.106 ++ ck=1.5pF ++ L1=4m ++ L2=620u ++ L3=23u ++ L4=4u ++ L5=110n ++ C1=3.9p ++ C2=4p ++ Rs1=17k ++ RS2=9400 ++ RS3=400 ++ RS4=200 ++ RS5=1100 ++ R2=1 +.ends LF_SH_7446622003_3m3 +***** +.subckt LF_SH_7446621007_6m8 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000003 ++ DL4=0.000000056 ++ DC3=0.0000000000132 ++ DC4=0.000000000024 ++ DR3=17 ++ dR4=15k ++ DR5=23 ++ dR6=5k ++ Rdc=0.2 ++ ck=1pF ++ L1=7m ++ L2=820u ++ L3=23u ++ L4=4u ++ L5=300n ++ C1=4.2p ++ C2=7p ++ Rs1=35k ++ Rs2=12k ++ RS3=400 ++ RS4=200 ++ RS5=1400 ++ R2=1 +.ends LF_SH_7446621007_6m8 +***** +.subckt LF_SH_7446621010_10m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000053 ++ DL4=0.000000096 ++ DC3=0.0000000000097 ++ DC4=0.000000000036 ++ DR3=17 ++ dR4=25k ++ DR5=23 ++ dR6=6k ++ Rdc=0.36 ++ ck=1pF ++ L1=12m ++ L2=1.3m ++ L3=23u ++ L4=4u ++ L5=300n ++ C1=4.4p ++ C2=7p ++ Rs1=58k ++ Rs2=12k ++ RS3=400 ++ RS4=200 ++ RS5=1400 ++ R2=1 +.ends LF_SH_7446621010_10m +***** +.subckt LF_SH_7446620015_15m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000075 ++ DL4=0.00000019 ++ DC3=0.0000000000125 ++ DC4=0.000000000028 ++ DR3=17 ++ dR4=35k ++ DR5=23 ++ dR6=6k ++ Rdc=0.553 ++ ck=1pF ++ L1=14m ++ L2=1.3m ++ L3=23u ++ L4=4u ++ L5=540n ++ C1=5.3p ++ C2=9p ++ Rs1=110k ++ Rs2=42k ++ RS3=400 ++ RS4=200 ++ RS5=1900 ++ R2=1 +.ends LF_SH_7446620015_15m +***** +.subckt LF_SH_7446620027_27m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000012 ++ DL4=0.00000025 ++ DC3=0.0000000000185 ++ DC4=0.000000000037 ++ DR3=17 ++ dR4=35k ++ DR5=23 ++ dR6=2k ++ Rdc=0.8 ++ ck=1.2pF ++ L1=30m ++ L2=1.2m ++ L3=23u ++ L4=4u ++ L5=0.9u ++ C1=5.9p ++ C2=12p ++ Rs1=160k ++ Rs2=42k ++ RS3=400 ++ RS4=200 ++ RS5=1700 ++ R2=1 +.ends LF_SH_7446620027_27m +***** +.subckt LF_SH_7446620039_39m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000016 ++ DL4=0.000000325 ++ DC3=0.00000000001 ++ DC4=0.000000000037 ++ DR3=17 ++ dR4=35k ++ DR5=23 ++ dR6=12k ++ Rdc=0.8 ++ ck=2.2pF ++ L1=33m ++ L2=1.3m ++ L3=23u ++ L4=4u ++ L5=1200n ++ C1=5.1p ++ C2=13p ++ Rs1=180k ++ Rs2=42k ++ RS3=400 ++ RS4=200 ++ RS5=1700 ++ R2=1 +.ends LF_SH_7446620039_39m +***** +.subckt LF_MH_7446723001_1m2 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000055 ++ DL4=0.000000019 ++ DC3=0.0000000000107 ++ DC4=0.000000000014 ++ DR3=17 ++ dR4=5.5k ++ DR5=23 ++ dR6=3k ++ Rdc=0.0266 ++ ck=1pF ++ L1=1m ++ L2=0.3m ++ L3=23u ++ L4=4u ++ L5=120n ++ C1=3.1p ++ C2=0.5p ++ RS1=5500 ++ RS2=800 ++ RS3=100 ++ RS4=100 ++ RS5=1100 ++ R2=1 +.ends LF_MH_7446723001_1m2 +***** +.subckt LF_MH_7446722002_2m2 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000001 ++ DL4=0.000000049 ++ DC3=0.0000000000115 ++ DC4=0.0000000000045 ++ DR3=17 ++ dR4=8k ++ DR5=23 ++ dR6=2k ++ Rdc=0.04 ++ ck=3pF ++ L1=2m ++ L2=0.3m ++ L3=0.1m ++ L4=40u ++ L5=190n ++ C1=3.3p ++ C2=0.5p ++ Rs1=12.5k ++ RS2=1800 ++ RS3=400 ++ RS4=200 ++ RS5=600 ++ R2=1 +.ends LF_MH_7446722002_2m2 +***** +.subckt LF_MH_7446722004_4m2 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000021 ++ DL4=0.000000095 ++ DC3=0.0000000000155 ++ DC4=0.0000000000055 ++ DR3=17 ++ dR4=14k ++ DR5=23 ++ dR6=2.5k ++ Rdc=0.08 ++ ck=3pF ++ L1=4m ++ L2=0.97m ++ L3=0.403m ++ L4=200u ++ L5=180n ++ C1=5p ++ C2=8p ++ Rs1=25.5k ++ RS2=9800 ++ RS3=400 ++ RS4=200 ++ RS5=1000 ++ R2=1 +.ends LF_MH_7446722004_4m2 +***** +.subckt LF_MH_7446722007_6m8 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000003 ++ DL4=0.000000165 ++ DC3=0.0000000000125 ++ DC4=0.000000000007 ++ DR3=17 ++ dR4=19k ++ DR5=23 ++ dR6=3.5k ++ Rdc=0.133 ++ ck=3pF ++ L1=7m ++ L2=0.97m ++ L3=0.403m ++ L4=0.200m ++ L5=330n ++ C1=6.4p ++ C2=8p ++ Rs1=49.5k ++ RS2=9800 ++ RS3=400 ++ RS4=200 ++ RS5=1400 ++ R2=1 +.ends LF_MH_7446722007_6m8 +***** +.subckt LF_MH_7446721010_10m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000005 ++ DL4=0.000000205 ++ DC3=0.0000000000122 ++ DC4=0.000000000009 ++ DR3=17 ++ dR4=22k ++ DR5=23 ++ dR6=1k ++ Rdc=0.166 ++ ck=3pF ++ L1=9.4m ++ L2=1.27m ++ L3=403u ++ L4=200u ++ L5=330n ++ C1=7.4p ++ C2=8p ++ Rs1=49.5k ++ RS2=9800 ++ RS3=400 ++ RS4=200 ++ RS5=1400 ++ R2=1 +.ends LF_MH_7446721010_10m +***** +.subckt LF_MH_7446721027_27m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000125 ++ DL4=0.000000375 ++ DC3=0.000000000021 ++ DC4=0.000000000019 ++ DR3=17 ++ dR4=24k ++ DR5=23 ++ dR6=2.5k ++ Rdc=0.466 ++ ck=3pF ++ L1=30m ++ L2=2.2m ++ L3=403u ++ L4=200u ++ L5=730n ++ C1=6.4p ++ C2=12p ++ Rs1=189k ++ Rs2=19k ++ RS3=400 ++ RS4=200 ++ RS5=1800 ++ R2=1 +.ends LF_MH_7446721027_27m +***** +.subckt LF_MH_7446720447_47m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000025 ++ DL4=0.000000575 ++ DC3=0.0000000000225 ++ DC4=0.000000000028 ++ DR3=17 ++ dR4=30k ++ DR5=23 ++ dR6=4k ++ Rdc=1.06 ++ ck=3pF ++ L1=49m ++ L2=2.27m ++ L3=403u ++ L4=200u ++ L5=1630n ++ C1=6.4p ++ C2=18p ++ Rs1=249.5k ++ Rs2=29.8k ++ RS3=400 ++ RS4=200 ++ RS5=1900 ++ R2=1 +.ends LF_MH_7446720447_47m +***** +.subckt LF_LH_7446823003_2m7 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000085 ++ DL4=0.000000034 ++ DC3=0.000000000014 ++ DC4=0.000000000012 ++ DR3=27 ++ dR4=10k ++ DR5=23 ++ DR6=3590 ++ Rdc=0.04 ++ ck=1.1pF ++ L1=2m ++ L2=0.27m ++ L3=43u ++ L4=20u ++ L5=130n ++ C1=3.4p ++ C2=2p ++ RS1=6500 ++ RS2=200 ++ RS3=400 ++ RS4=400 ++ RS5=1400 ++ R2=1 +.ends LF_LH_7446823003_2m7 +***** +.subckt LF_LH_7446822006_5m6 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.000002 ++ DL4=0.000000062 ++ DC3=0.000000000021 ++ DC4=0.000000000027 ++ DR3=27 ++ dR4=13k ++ DR5=23 ++ dR6=14k ++ Rdc=0.106 ++ ck=0.9pF ++ L1=5m ++ L2=2m ++ L3=1m ++ L4=0.5m ++ L5=238n ++ C1=4.9p ++ C2=5p ++ Rs1=16.5k ++ RS2=200 ++ RS3=400 ++ RS4=400 ++ RS5=1600 ++ R2=1 +.ends LF_LH_7446822006_5m6 +***** +.subckt LF_LH_7446823006_5m6 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000019 ++ DL4=0.00000005 ++ DC3=0.000000000022 ++ DC4=0.000000000021 ++ DR3=27 ++ dR4=13k ++ DR5=23 ++ dR6=14k ++ Rdc=0.06 ++ ck=0.9pF ++ L1=6m ++ L2=2m ++ L3=1m ++ L4=0.5m ++ L5=180n ++ C1=5.4p ++ C2=5p ++ Rs1=22.5k ++ RS2=200 ++ RS3=400 ++ RS4=400 ++ RS5=1000 ++ R2=1 +.ends LF_LH_7446823006_5m6 +***** +.subckt LF_LH_7446821027_27m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000092 ++ DL4=0.00000033 ++ DC3=0.000000000031 ++ DC4=0.000000000025 ++ DR3=27 ++ dR4=23k ++ DR5=23 ++ dR6=3k ++ Rdc=0.426 ++ ck=0.9pF ++ L1=22m ++ L2=12m ++ L3=5m ++ L4=2.5m ++ L5=680n ++ C1=8.8p ++ C2=12p ++ Rs1=99.5k ++ Rs2=22.2k ++ RS3=400 ++ RS4=400 ++ RS5=1800 ++ R2=1 +.ends LF_LH_7446821027_27m +***** +.subckt LF_XH_7446926002_1m8 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.00000073 ++ DL4=0.000000053 ++ DC3=0.00000000002 ++ DC4=0.0000000000084 ++ DR3=17 ++ dR4=6k ++ DR5=23 ++ dR6=1.2k ++ Rdc=0.02 ++ ck=1pF ++ L1=1.2m ++ L2=0.8m ++ L3=150u ++ L4=125u ++ L5=128n ++ C1=4.8p ++ C2=3p ++ RS1=6900 ++ RS2=3500 ++ RS3=400 ++ RS4=400 ++ RS5=600 ++ R2=1 +.ends LF_XH_7446926002_1m8 +***** +.subckt LF_XH_7446924003_3m3 1 2 3 4 +X1 1 2 3 4 LF26 PARAMS: ++ L1=0.00196289392486891 ++ L2=1.00000000001427E-06 ++ L3=0.000362784502684758 ++ L4=0.000826806877150703 ++ L5=0.0000252879136448232 ++ L6=1n ++ C1=5.52336505663546E-12 ++ C2=3.21929744946232E-11 ++ C3=0.000000000001 ++ RS1=8043.06001702957 ++ RS2=7280.08333963672 ++ RS3=3663.93618097763 ++ RS4=5994.7324618714 ++ RS5=1592.20878782089 ++ RS6=1 ++ R2=26.8683635170806 ++ DL3=0.00000157 ++ DL4=0.000000068 ++ DC3=0.0000000000157 ++ DC4=0.0000000000124 ++ DR3=17 ++ dR4=8.8k ++ DR5=50 ++ dR6=55.2k ++ Rdc=0.0466 ++ ck=1pF +.ends LF_XH_7446924003_3m3 +***** +.subckt LF_XH_7446923010_10m 1 2 3 4 +X1 1 2 3 4 LF26 PARAMS: ++ L1=11m ++ L2=0.08m ++ L3=155m ++ L4=162.5m ++ L5=1090n ++ L6=1.99964526241581E-07 ++ C1=47p ++ C2=43p ++ C3=2.529379663444E-12 ++ Rs1=110k ++ RS2=400 ++ RS3=400 ++ RS4=400 ++ RS5=570 ++ RS6=1 ++ R2=1.4422510600994 ++ DL3=0.000005 ++ DL4=0.000000145 ++ DC3=0.000000000044 ++ DC4=0.0000000000484 ++ DR3=17 ++ dR4=12k ++ DR5=23 ++ dR6=.6k ++ Rdc=0.073 ++ ck=1pF +.ends LF_XH_7446923010_10m +***** +.subckt LF_XH_7446921027_27m 1 2 3 4 +X1 1 2 3 4 LF PARAMS: ++ DL3=0.0000143 ++ DL4=0.000000345 ++ DC3=0.000000000021 ++ DC4=0.0000000000484 ++ DR3=17 ++ dR4=26k ++ DR5=23 ++ dR6=5k ++ Rdc=0.266 ++ ck=1pF ++ L1=22m ++ L2=5m ++ L3=5m ++ L4=2.5m ++ L5=890n ++ C1=9p ++ C2=13p ++ Rs1=140k ++ Rs2=45k ++ RS3=400 ++ RS4=400 ++ RS5=2400 ++ R2=1 +.ends LF_XH_7446921027_27m diff --git a/spice/copy/sub/Contrib/Wurth/WE-LF_SMD.lib b/spice/copy/sub/Contrib/Wurth/WE-LF_SMD.lib new file mode 100755 index 0000000..10456fd --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-LF_SMD.lib @@ -0,0 +1,315 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-LF SMD +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT LFSMD 1 2 3 4 PARAMS: +R_R9 N12325 3 {R2} +R_R8 N13265 N13287 {Rs4} +Kn_K6 L_L11 L_L12 ++ L_L13 L_L14 0.9999 +R_R3 N12571 N12583 {Rs3} +R_R10 N13777 4 {R2} +C_C10 N13029 N12821 {ck} +R_R20 N13215 N13229 {dR4} +L_L11 N12821 N12295 {dL4} +R_R17 N12267 N12273 {dR3} +L_L8 N13265 N13287 {L4} +R_R7 N13287 N13305 {Rs3} +L_L9 N12295 N12307 {L5} +Kn_K4 L_L7 L_L8 1 +R_R2 N12583 N12599 {Rs2} +Kn_K5 L_L9 L_L10 1 +R_R16 N13229 N13249 {dR6} +Kn_K7 L_L15 L_L16 ++ L_L17 L_L18 0.9999 +C_C5 N12273 N12289 {dC4} +L_L6 N13287 N13305 {L3} +L_L7 N12307 N12571 {L4} +R_R6 N13305 N13319 {Rs2} +R_R21 1 N12257 {Rdc} +Kn_K3 L_L5 L_L6 1 +L_L16 N12257 N12799 {dL3} +C_C8 N13215 N13741 {dC3} +L_L18 N13023 N13215 {dL3} +R_R1 N12599 3 {Rs1} +R_R13 N12289 N12295 {dR5} +L_L4 N13305 N13319 {L2} +L_L5 N12571 N12583 {L3} +R_R15 N13755 N13249 {dR5} +R_R5 N13319 4 {Rs1} +R_R18 N12257 N12273 {dR4} +Kn_K2 L_L3 L_L4 1 +R_R19 N13741 N13229 {dR3} +L_L15 N12799 N12273 {dL3} +L_L17 N13229 N13023 {dL3} +L_L3 N12583 N12599 {L2} +R_R11 N12295 N12307 {Rs5} +L_L2 N13319 4 {L1} +C_C4 N13249 N13265 {C2} +L_L10 N13249 N13265 {L5} +Kn_K1 L_L1 L_L2 1 +R_R14 N12273 N12295 {dR6} +C_C6 N13229 N13755 {dC4} +L_L12 N12273 N12821 {dL4} +L_L14 N13029 N13229 {dL4} +L_L1 N12599 3 {L1} +C_C1 N12307 N12325 {C1} +R_R12 N13249 N13265 {Rs5} +C_C2 N13265 N13777 {C1} +R_R22 2 N13215 {Rdc} +C_C9 N13023 N12799 {ck} +R_R4 N12307 N12571 {Rs4} +C_C3 N12295 N12307 {C2} +L_L13 N13249 N13029 {dL4} +C_C7 N12257 N12267 {dC3} +.ends LFSMD +****** +.subckt SH_74466340007_0.7m 1 2 3 4 +X1 1 2 3 4 LFSMD PARAMS: ++ DL3=0.00000031 ++ DL4=0.00000002 ++ DC3=0.0000000000075 ++ DC4=0.0000000000008 ++ DR3=17 ++ dR4=4.5k ++ DR5=23 ++ dR6=2k ++ Rdc=0.025 ++ ck=2.3pF ++ L1=500u ++ L2=80u ++ L3=23u ++ L4=4u ++ L5=60n ++ C1=2.8p ++ C2=0.5p ++ RS1=5500 ++ RS2=1400 ++ RS3=400 ++ RS4=200 ++ RS5=800 ++ R2=1 +.ends SH_74466340007_0.7m +****** +.subckt SH_7446632001_1m 1 2 3 4 +X1 1 2 3 4 LFSMD PARAMS: ++ DL3=0.00000051 ++ DL4=0.000000034 ++ DC3=0.0000000000085 ++ DC4=0.0000000000008 ++ DR3=17 ++ dR4=6k ++ DR5=23 ++ dR6=1.5k ++ Rdc=0.05 ++ ck=2pF ++ L1=1.2m ++ L2=120u ++ L3=23u ++ L4=4u ++ L5=90n ++ C1=3.1p ++ C2=0.7p ++ RS1=6500 ++ RS2=1400 ++ RS3=400 ++ RS4=200 ++ RS5=1000 ++ R2=1 +.ends SH_7446632001_1m +****** +.subckt SH_7446632002_2.2m 1 2 3 4 +X1 1 2 3 4 LFSMD PARAMS: ++ DL3=0.0000009 ++ DL4=0.000000044 ++ DC3=0.000000000011 ++ DC4=0.0000000000065 ++ DR3=17 ++ dR4=8k ++ DR5=23 ++ dR6=1.5k ++ Rdc=0.08 ++ ck=1.5pF ++ L1=2m ++ L2=620u ++ L3=23u ++ L4=4u ++ L5=120n ++ C1=3.7p ++ C2=2p ++ Rs1=10k ++ RS2=6400 ++ RS3=400 ++ RS4=200 ++ RS5=1000 ++ R2=1 +.ends SH_7446632002_2.2m +****** +.subckt SH_7446632003_3.3m 1 2 3 4 +X1 1 2 3 4 LFSMD PARAMS: ++ DL3=0.0000016 ++ DL4=0.000000044 ++ DC3=0.000000000008 ++ DC4=0.000000000013 ++ DR3=17 ++ dR4=12k ++ DR5=23 ++ dR6=1k ++ Rdc=0.125 ++ ck=1.5pF ++ L1=4m ++ L2=620u ++ L3=23u ++ L4=4u ++ L5=110n ++ C1=3.9p ++ C2=4p ++ Rs1=17k ++ RS2=9400 ++ RS3=400 ++ RS4=200 ++ RS5=1100 ++ R2=1 +.ends SH_7446632003_3.3m +****** +.subckt SH_7446631007_6.8m 1 2 3 4 +X1 1 2 3 4 LFSMD PARAMS: ++ DL3=0.000003 ++ DL4=0.000000056 ++ DC3=0.0000000000132 ++ DC4=0.000000000024 ++ DR3=17 ++ dR4=15k ++ DR5=23 ++ dR6=5k ++ Rdc=0.25 ++ ck=1pF ++ L1=7m ++ L2=820u ++ L3=23u ++ L4=4u ++ L5=300n ++ C1=4.2p ++ C2=7p ++ Rs1=35k ++ Rs2=12k ++ RS3=400 ++ RS4=200 ++ RS5=1400 ++ R2=1 +.ends SH_7446631007_6.8m +****** +.subckt SH_7446631010_10m 1 2 3 4 +X1 1 2 3 4 LFSMD PARAMS: ++ DL3=0.0000053 ++ DL4=0.000000096 ++ DC3=0.0000000000097 ++ DC4=0.000000000036 ++ DR3=17 ++ dR4=25k ++ DR5=23 ++ dR6=6k ++ Rdc=0.48 ++ ck=1pF ++ L1=12m ++ L2=1.3m ++ L3=23u ++ L4=4u ++ L5=300n ++ C1=4.4p ++ C2=7p ++ Rs1=58k ++ Rs2=12k ++ RS3=400 ++ RS4=200 ++ RS5=1400 ++ R2=1 +.ends SH_7446631010_10m +****** +.subckt SH_7446630027_27m 1 2 3 4 +X1 1 2 3 4 LFSMD PARAMS: ++ DL3=0.000012 ++ DL4=0.00000025 ++ DC3=0.0000000000185 ++ DC4=0.000000000037 ++ DR3=17 ++ dR4=35k ++ DR5=23 ++ dR6=2k ++ Rdc=1.05 ++ ck=1.2pF ++ L1=30m ++ L2=1.2m ++ L3=23u ++ L4=4u ++ L5=0.9u ++ C1=5.9p ++ C2=12p ++ Rs1=160k ++ Rs2=42k ++ RS3=400 ++ RS4=200 ++ RS5=1700 ++ R2=1 +.ends SH_7446630027_27m +****** +.subckt SH_7446630039_39m 1 2 3 4 +X1 1 2 3 4 LFSMD PARAMS: ++ DL3=0.000016 ++ DL4=0.000000325 ++ DC3=0.00000000001 ++ DC4=0.000000000037 ++ DR3=17 ++ dR4=35k ++ DR5=23 ++ dR6=12k ++ Rdc=1.5 ++ ck=2.2pF ++ L1=33m ++ L2=1.3m ++ L3=23u ++ L4=4u ++ L5=1200n ++ C1=5.1p ++ C2=13p ++ Rs1=180k ++ Rs2=42k ++ RS3=400 ++ RS4=200 ++ RS5=1700 ++ R2=1 +.ends SH_7446630039_39m +****** +.subckt SH_7446630047_47m 1 2 3 4 +X1 1 2 3 4 LFSMD PARAMS: ++ DL3=0.000014 ++ DL4=0.000001342 ++ DC3=0.000000000014 ++ DC4=0.000000000001 ++ DR3=27 ++ dR4=35k ++ DR5=230 ++ dR6=22k ++ Rdc=2.1 ++ ck=11pF ++ L1=36m ++ L2=12m ++ L3=1m ++ L4=5u ++ L5=255n ++ C1=9p ++ C2=14p ++ Rs1=220k ++ Rs2=83k ++ RS3=500 ++ RS4=600 ++ RS5=1400 ++ R2=10.41 +.ends SH_7446630047_47m diff --git a/spice/copy/sub/Contrib/Wurth/WE-LHMD.lib b/spice/copy/sub/Contrib/Wurth/WE-LHMD.lib new file mode 100755 index 0000000..2aa4656 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-LHMD.lib @@ -0,0 +1,129 @@ +.subckt 1008_74434301008082_8.2u 1 2 3 4 +Rdc1 1 N1 32m +Rp1 1 4 4786 +Cp1 1 4 24.714p +L1 N1 4 9.395u + +Rdc2 2 N2 32m +Rp2 2 3 4786 +Cp2 2 3 24.714p +L2 N2 3 9.395u + +Rg1 1 0 100meg +Rg2 2 0 100meg +Rg3 3 0 100meg +Rg4 4 0 100meg +.ends 1008_74434301008082_8.2u +****** +.subckt 1008_74434301008100_10u 1 2 +Rdc1 1 N1 45m +Rp1 1 4 4842 +Cp1 1 4 28.715p +L1 N1 4 10.382u + +Rdc2 2 N2 45m +Rp2 2 3 4842 +Cp2 2 3 28.715p +L2 N2 3 10.382u +Rg1 1 0 100meg +Rg2 2 0 100meg +Rg3 3 0 100meg +Rg4 4 0 100meg +.ends 1008_74434301008100_10u +****** +.subckt 1008_74434301008150_15u 1 2 +Rdc1 1 N1 65m +Rp1 1 4 6736 +Cp1 1 4 31.878p +L1 N1 4 16.8u + +Rdc2 2 N2 65m +Rp2 2 3 6736 +Cp2 2 3 31.878p +L2 N2 3 16.8u +Rg1 1 0 100meg +Rg2 2 0 100meg +Rg3 3 0 100meg +Rg4 4 0 100meg +.ends 1008_74434301008150_15u +****** +.subckt 1008_74434301008220_22u 1 2 +Rdc1 1 N1 105m +Rp1 1 4 5961 +Cp1 1 4 27.708p +L1 N1 4 24.587u + +Rdc2 2 N2 105m +Rp2 2 3 5961 +Cp2 2 3 27.708p +L2 N2 3 24.587u +Rg1 1 0 100meg +Rg2 2 0 100meg +Rg3 3 0 100meg +Rg4 4 0 100meg +.ends 1008_74434301008220_22u +****** +.subckt 1213_74434301213082_8.2u 1 2 +Rdc1 1 N1 16m +Rp1 1 4 2383 +Cp1 1 4 36.728p +L1 N1 4 9.245u + +Rdc2 2 N2 16m +Rp2 2 3 2383 +Cp2 2 3 36.728p +L2 N2 3 9.245u +Rg1 1 0 100meg +Rg2 2 0 100meg +Rg3 3 0 100meg +Rg4 4 0 100meg +.ends 1213_74434301213082_8.2u +****** +.subckt 1213_74434301213100_10u 1 2 +Rdc1 1 N1 20.5m +Rp1 1 4 2117 +Cp1 1 4 37.603p +L1 N1 4 10.762u + +Rdc2 2 N2 20.5m +Rp2 2 3 2117 +Cp2 2 3 37.603p +L2 N2 3 10.762u +Rg1 1 0 100meg +Rg2 2 0 100meg +Rg3 3 0 100meg +Rg4 4 0 100meg +.ends 1213_74434301213100_10u +****** +.subckt 1213_74434301213150_15u 1 2 +Rdc1 1 N1 33.2m +Rp1 1 4 2122 +Cp1 1 4 43.189p +L1 N1 4 16.33u + +Rdc2 2 N2 33.2m +Rp2 2 3 2122 +Cp2 2 3 43.189p +L2 N2 3 16.33u +Rg1 1 0 100meg +Rg2 2 0 100meg +Rg3 3 0 100meg +Rg4 4 0 100meg +.ends 1213_74434301213150_15u +****** +.subckt 1213_74434301213220_22u 1 2 +Rdc1 1 N1 50m +Rp1 1 4 4301 +Cp1 1 4 40.517p +L1 N1 4 23.319u + +Rdc2 2 N2 50m +Rp2 2 3 4301 +Cp2 2 3 40.517p +L2 N2 3 23.319u +Rg1 1 0 100meg +Rg2 2 0 100meg +Rg3 3 0 100meg +Rg4 4 0 100meg +.ends 1213_74434301213220_22u +****** diff --git a/spice/copy/sub/Contrib/Wurth/WE-LPCC.lib b/spice/copy/sub/Contrib/Wurth/WE-LPCC.lib new file mode 100755 index 0000000..f6f9181 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-LPCC.lib @@ -0,0 +1,430 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-LPCC +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 7448680100_450u 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.0096 +.param L1=0.0003221975088665 +.param L2=0.000138806014097662 +.param L3=7.97843988970392e-005 +.param L4=0.000144978504397109 +.param L5=2.78474418896237e-009 +.param C1=2.22385066019387e-012 +.param C2=1.27890165252899e-010 +.param Rs1=1098.61272349974 +.param Rs2=953.146619380167 +.param Rs3=407.027890762303 +.param Rs4=891.145501401177 +.param Rs5=678.132914563373 +.param R2=27.3015949665267 +.param dL3=9.72189206246018e-007 +.param dL4=4.19596980009255e-008 +.param dC3=7.88193146340315e-012 +.param dC4=5.12601360569342e-007 +.param dR3=0.0761815621331065 +.param dR4=3220.67501105579 +.param dR5=0.969914342682361 +.param dR6=1397.34960720296 +.param ck=0.001pF +.backanno +.ends 7448680100_450u +***************** +.subckt 7448680120_330u 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.006 +.param L1=0.000140937619986914 +.param L2=4.39657828747604e-005 +.param L3=0.000228812259298393 +.param L4=2.09686818217626e-005 +.param L5=1.80996796801061e-009 +.param C1=2.62473145062263e-012 +.param C2=1.63288004918243e-010 +.param Rs1=887.652263869152 +.param Rs2=122.215118100556 +.param Rs3=1199.87862879898 +.param Rs4=162.811026527533 +.param Rs5=253.660260908156 +.param R2=2.82649376860016 +.param dL3=6.97796037928061e-007 +.param dL4=3.36415012186165e-008 +.param dC3=8.41169616027121e-012 +.param dC4=4.36820246625976e-007 +.param dR3=0.806367379842407 +.param dR4=2368.20342131664 +.param dR5=1.97725336386679 +.param dR6=1145.0509725041 +.param ck=0.001pF +.backanno +.ends 7448680120_330u +************** +.subckt 7448680140_230u 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.0036 +.param L1=9.17505820928204e-005 +.param L2=4.55431387495439e-005 +.param L3=0.000158398832956116 +.param L4=2.90032026604691e-005 +.param L5=1.70580399894645e-009 +.param C1=2.41938718795632e-012 +.param C2=1.27548331987044e-010 +.param Rs1=417.400070459493 +.param Rs2=260.350887703824 +.param Rs3=755.106239369326 +.param Rs4=171.389325640953 +.param Rs5=298.867701181834 +.param R2=26.4737055397191 +.param dL3=4.9808207293008e-007 +.param dL4=3.61129405642388e-008 +.param dC3=8.13205464021318e-012 +.param dC4=2.54260987283725e-007 +.param dR3=0.635735394449898 +.param dR4=1634.44212144151 +.param dR5=0.789247201779795 +.param dR6=381.135413958701 +.param ck=0.001pF +.backanno +.ends 7448680140_230u +*************** +.subckt 7448680180_150u 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.0019 +.param L1=5.94696365448658e-005 +.param L2=5.35995806002837e-005 +.param L3=2.99470000000001e-005 +.param L4=9.02845058072998e-005 +.param L5=8.88507500226719e-010 +.param C1=2.58233340391014e-012 +.param C2=2.44995987282382e-011 +.param Rs1=359.694127476125 +.param Rs2=237.304374645143 +.param Rs3=174.676210628111 +.param Rs4=199.998443202317 +.param Rs5=185.012410435095 +.param R2=53.2303666048204 +.param dL3=3.05917332555267e-007 +.param dL4=2.74094071239454e-008 +.param dC3=7.5254925075227e-012 +.param dC4=7.03919303399164e-007 +.param dR3=0.0327773452949108 +.param dR4=1011.52911069511 +.param dR5=2.89048479883329 +.param dR6=612.971531654816 +.param ck=0.001pF +.backanno +.ends 7448680180_150u +********** +.subckt 7448680200_120u 1 2 3 4 +R1 N004 1 {Rdc} +R2 N006 N004 {dR4} +C1 N005 N004 {dC3} +L1 N011 N004 {dL3} +L2 N018 N019 {dL3} +C2 N011 N019 {ck} +R3 N006 N005 {dR3} +R4 N020 N022 {dR3} +C3 N022 N018 {dC3} +R5 N020 N018 {dR4} +L3 N006 N011 {dL3} +L4 N019 N020 {dL3} +R6 N018 2 {Rdc} +R8 N001 N006 {dR6} +C4 N007 N006 {dC4} +L5 N012 N006 {dL4} +L6 N020 N021 {dL4} +C5 N012 N021 {ck} +R9 N001 N007 {dR5} +R10 N013 N023 {dR5} +C6 N023 N020 {dC4} +R11 N013 N020 {dR6} +L7 N001 N012 {dL4} +L8 N021 N013 {dL4} +L9 N009 N008 {L3} +C7 N003 N002 {C1} +R13 N009 N008 {Rs3} +L10 4 N010 {L1} +R14 4 N010 {Rs1} +L11 N010 N009 {L2} +R15 N010 N009 {Rs2} +L12 N016 N015 {L3} +C8 N024 N014 {C1} +L13 3 N017 {L1} +L14 N017 N016 {L2} +R16 4 N003 {R2} +R17 3 N024 {R2} +L15 N015 N014 {L4} +R18 N008 N002 {Rs4} +L16 N008 N002 {L4} +R21 3 N017 {Rs1} +R22 N017 N016 {Rs2} +R23 N016 N015 {Rs3} +R24 N015 N014 {Rs4} +R25 N002 N001 {Rs5} +R26 N014 N013 {Rs5} +C9 N002 N001 {C2} +C10 N014 N013 {C2} +L17 N002 N001 {L5} +L18 N014 N013 {L5} +K7 L1 L3 L2 L4 0.9999 +K6 L5 L7 L6 L8 0.9999 +K3 L9 L12 1 +K2 L11 L14 1 +K1 L10 L13 1 +K4 L16 L15 1 +K5 L17 L18 1 +.param Rdc=0.0014 +.param L1=2.22537299710507e-005 +.param L2=1.27897312638484e-005 +.param L3=8.14890797193895e-005 +.param L4=1.68292511804643e-005 +.param L5=2.61567100901019e-010 +.param C1=2.82744800265351e-012 +.param C2=1.09642127093973e-011 +.param Rs1=115.161430475641 +.param Rs2=74.2938925681102 +.param Rs3=440.832631283561 +.param Rs4=86.2417269707834 +.param Rs5=80.4606641868868 +.param R2=2.23977734039555 +.param dL3=2.24931687710815e-007 +.param dL4=2.18643574852112e-009 +.param dC3=8.43903858557102e-012 +.param dC4=5.97301161330001e-007 +.param dR3=0.212521248974478 +.param dR4=736.197549992419 +.param dR5=2.22895647395249 +.param dR6=142.37716329747 +.param ck=0.001pF +.backanno +.ends 7448680200_120u \ No newline at end of file diff --git a/spice/copy/sub/Contrib/Wurth/WE-MCRI.lib b/spice/copy/sub/Contrib/Wurth/WE-MCRI.lib new file mode 100755 index 0000000..6666a08 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-MCRI.lib @@ -0,0 +1,311 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Molded Coupled Inductor +* Matchcode: WE-MCRI +* Library Type: Ltspice +* Version: rev18a +* Created/modified by: Fredo +* Date and Time : 10/15/2018 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 1090_7448990010_1u 1 2 3 4 PARAMS: ++ Cww=76p ++ Rp1=2131 ++ Cp1=18.45p ++ Lp1=1.112u ++ Rp2=2113 ++ Cp2=19.055p ++ Lp2=1.076u ++ RDC1=0.007 ++ RDC2=0.007 ++ K=0.9 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990015_1.5u 1 2 3 4 PARAMS: ++ Cww=79p ++ Rp1=2700 ++ Cp1=19.49p ++ Lp1=1.454u ++ Rp2=2741 ++ Cp2=19.35p ++ Lp2=1.554u ++ RDC1=0.016 ++ RDC2=0.016 ++ K=0.921592824046137 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990022_2.2u 1 2 3 4 PARAMS: ++ Cww=90p ++ Rp1=4880 ++ Cp1=26.707p ++ Lp1=2.555u ++ Rp2=4518 ++ Cp2=26.989p ++ Lp2=2.528u ++ RDC1=0.022 ++ RDC2=0.022 ++ K=0.945082968940727 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990033_3.3u 1 2 3 4 PARAMS: ++ Cww=99p ++ Rp1=6700 ++ Cp1=20.581p ++ Lp1=3.316u ++ Rp2=6635 ++ Cp2=20.7p ++ Lp2=3.297u ++ RDC1=0.028 ++ RDC2=0.028 ++ K=0.9613752775282 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990047_4.7u 1 2 3 4 PARAMS: ++ Cww=98p ++ Rp1=4913 ++ Cp1=22.582p ++ Lp1=4.574u ++ Rp2=5004 ++ Cp2=22.507p ++ Lp2=4.559u ++ RDC1=0.035 ++ RDC2=0.035 ++ K=0.972275243403929 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990068_6.8u 1 2 3 4 PARAMS: ++ Cww=131p ++ Rp1=6400 ++ Cp1=23.196p ++ Lp1=6.671u ++ Rp2=6631 ++ Cp2=23.057p ++ Lp2=6.712u ++ RDC1=0.048 ++ RDC2=0.048 ++ K=0.980696031338127 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990082_8.2u 1 2 3 4 PARAMS: ++ Cww=162p ++ Rp1=4896 ++ Cp1=25.504p ++ Lp1=8.998u ++ Rp2=4972 ++ Cp2=25.148p ++ Lp2=9.125u ++ RDC1=0.059 ++ RDC2=0.059 ++ K=0.983398785199426 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990100_10u 1 2 3 4 PARAMS: ++ Cww=178p ++ Rp1=7321 ++ Cp1=28.172p ++ Lp1=10.072u ++ Rp2=7421 ++ Cp2=28.127p ++ Lp2=10.088u ++ RDC1=0.064 ++ RDC2=0.064 ++ K=0.986154146165801 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990150_15u 1 2 3 4 PARAMS: ++ Cww=199p ++ Rp1=8298 ++ Cp1=26.456p ++ Lp1=15.755u ++ Rp2=8175 ++ Cp2=26.386p ++ Lp2=15.757u ++ RDC1=0.075 ++ RDC2=0.075 ++ K=0.990252493054171 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990220_22u 1 2 3 4 PARAMS: ++ Cww=226p ++ Rp1=9865 ++ Cp1=24.449p ++ Lp1=20.839u ++ Rp2=10350 ++ Cp2=24.482p ++ Lp2=20.811u ++ RDC1=0.099 ++ RDC2=0.099 ++ K=0.99304398877208 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990330_33u 1 2 3 4 PARAMS: ++ Cww=345p ++ Rp1=11110 ++ Cp1=29.2p ++ Lp1=32.34u ++ Rp2=11322 ++ Cp2=29.225p ++ Lp2=32.429u ++ RDC1=0.129 ++ RDC2=0.129 ++ K=0.994530496812898 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 1090_7448990470_47u 1 2 3 4 PARAMS: ++ Cww=363p ++ Rp1=26460 ++ Cp1=26.452p ++ Lp1=44.153u ++ Rp2=28240 ++ Cp2=29.49p ++ Lp2=44.089u ++ RDC1=0.222 ++ RDC2=0.222 ++ K=0.996162850909386 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** diff --git a/spice/copy/sub/Contrib/Wurth/WE-MTCI.lib b/spice/copy/sub/Contrib/Wurth/WE-MTCI.lib new file mode 100755 index 0000000..c45f90b --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-MTCI.lib @@ -0,0 +1,236 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Multi-Tum Ratio Coupled Inductor +* Matchcode: WE-MTCI +* Library Type: Ltspice +* Version: rev18a +* Created/modified by: Fredo +* Date and Time : 10/15/2018 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 5030_744889015100_10u 1 2 3 4 PARAMS: ++ Cww=9.5p ++ Rp1=9168 ++ Cp1=9.155p ++ Lp1=10u ++ Rp2=20761 ++ Cp2=5.514p ++ Lp2=22.5u ++ RDC1=0.349 ++ RDC2=0.408 ++ K=0.992191737742481 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_744889020100_10u 1 2 3 4 PARAMS: ++ Cww=10.2p ++ Rp1=6032 ++ Cp1=13.907p ++ Lp1=10u ++ Rp2=31099 ++ Cp2=3.902p ++ Lp2=40u ++ RDC1=0.358 ++ RDC2=0.552 ++ K=0.993856126408647 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_744889030100_10u 1 2 3 4 PARAMS: ++ Cww=13.6p ++ Rp1=5042 ++ Cp1=29.032p ++ Lp1=10u ++ Rp2=57172 ++ Cp2=4.282p ++ Lp2=90u ++ RDC1=0.363 ++ RDC2=0.846 ++ K=0.996828303504002 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_744889015220_22u 1 2 3 4 PARAMS: ++ Cww=12.1p ++ Rp1=19692 ++ Cp1=8.558p ++ Lp1=22u ++ Rp2=19477 ++ Cp2=8.547p ++ Lp2=49.5u ++ RDC1=0.662 ++ RDC2=0.874 ++ K=0.993615985817825 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_744889020220_22u 1 2 3 4 PARAMS: ++ Cww=13.2p ++ Rp1=16198 ++ Cp1=17.947p ++ Lp1=22u ++ Rp2=34255 ++ Cp2=5.509p ++ Lp2=88u ++ RDC1=0.712 ++ RDC2=1.208 ++ K=0.99572951785476 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_744889030220_22u 1 2 3 4 PARAMS: ++ Cww=14.9p ++ Rp1=11548 ++ Cp1=29.125p ++ Lp1=22u ++ Rp2=127841 ++ Cp2=4.581p ++ Lp2=198u ++ RDC1=0.732 ++ RDC2=1.872 ++ K=0.997851226740274 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_744889015330_33u 1 2 3 4 PARAMS: ++ Cww=17.9p ++ Rp1=14271 ++ Cp1=8.324p ++ Lp1=33u ++ Rp2=63698 ++ Cp2=5.312p ++ Lp2=74.25u ++ RDC1=1.338 ++ RDC2=1.782 ++ K=0.995342690085717 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_744889020330_33u 1 2 3 4 PARAMS: ++ Cww=18.9p ++ Rp1=16972 ++ Cp1=15.439p ++ Lp1=33u ++ Rp2=55012 ++ Cp2=4.466p ++ Lp2=132u ++ RDC1=1.383 ++ RDC2=2.418 ++ K=0.996775103050134 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 5030_744889030330_33u 1 2 3 4 PARAMS: ++ Cww=21.7p ++ Rp1=21944 ++ Cp1=27.563p ++ Lp1=33u ++ Rp2=183718 ++ Cp2=5.313p ++ Lp2=297u ++ RDC1=1.466 ++ RDC2=3.758 ++ K=0.998399392428374 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** diff --git a/spice/copy/sub/Contrib/Wurth/WE-SCC.lib b/spice/copy/sub/Contrib/Wurth/WE-SCC.lib new file mode 100755 index 0000000..823a2a1 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-SCC.lib @@ -0,0 +1,174 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-SCC +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT SCC 1 2 3 4 PARAMS: +R_R1 1 N00270 {Rdc} TC=0,0 +R_R2 2 N00427 {Rdc} TC=0,0 +R_R3 N00304 N00289 {dR5} TC=0,0 +R_R4 N00270 N00289 {dR6} TC=0,0 +R_R5 N00427 N00408 {dR6} TC=0,0 +R_R6 N00423 N00408 {dR5} TC=0,0 +L_L1 N00270 N00285 {dL4} +L_L2 N00285 N00289 {dL4} +L_L3 N00369 N00427 {dL4} +L_L4 N00408 N00369 {dL4} +C_C1 N00270 N00304 {dC4} TC=0,0 +C_C2 N00427 N00423 {dC4} TC=0,0 +C_C3 N00369 N00285 {ck} TC=0,0 +L_L5 N00289 4 {L1} +L_L8 N00408 3 {L1} +R_R7 N00289 4 {R1} TC=0,0 +C_C4 N00289 4 {C1} TC=0,0 +R_R10 N00408 3 {R1} TC=0,0 +C_C7 N00408 3 {C1} TC=0,0 +Kn_K1 L_L1 L_L2 ++ L_L3 L_L4 0.9999 +Kn_K2 L_L5 L_L8 1 +R_R13 N00369 N00285 100g TC=0,0 + +.ends SCC + +************* +.SUBCKT 7345_744281100_10u 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=0.075n ++ dC4=1n ++ dL4=5n ++ dR5=128 ++ dR6=1000 ++ Rdc=0.42 ++ L1=12u ++ C1=2.2p ++ R1=20500 +.ends 7345_744281100_10u +************ +.SUBCKT 7345_744281101_100u 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=2.59424871509595e-010 ++ dC4=3.90749966372341e-007 ++ dL4=6.54822049179388e-008 ++ dR5=107.99036952448 ++ dR6=1153.7966609136363 ++ Rdc=0.93 ++ L1=9.5E-5 ++ C1=2.8E-12 ++ R1=1.05e5 +.ends 7345_744281101_100u +************* +.SUBCKT 7345_744281471_470u 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=3.67863759838795e-011 ++ dC4=2.01445437944939e-008 ++ dL4=6.80562709915258e-009 ++ dR5=693.907429910977 ++ dR6=1268.24951963994 ++ Rdc=4.085 ++ L1=4.15E-4 ++ C1=3.05E-12 ++ R1=2.3e5 +.ends 7345_744281471_470u +************* +.SUBCKT 1260_744282010_1u 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=2.3961850087583e-011 ++ dC4=3.2753790145783e-006 ++ dL4=3.7872128552487e-009 ++ dR5=1231.728842566627 ++ dR6=145 ++ Rdc=0.0095 ++ L1=0.96E-6 ++ C1=1.7E-12 ++ R1=3.3e3 +.ends 1260_744282010_1u +************* +.SUBCKT 1260_744282100_10u 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=4.09424871509595e-011 ++ dC4=3.90749966372341e-006 ++ dL4=1.549179388e-008 ++ dR5=905.99036952448 ++ dR6=300 ++ Rdc=0.236 ++ L1=0.96E-5 ++ C1=2.6E-12 ++ R1=17.7e3 +.ends 1260_744282100_10u +************* +.SUBCKT 1260_744282101_100u 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=1.29424871509595e-010 ++ dC4=3.90749966372341e-006 ++ dL4=0.449179388e-007 ++ dR5=1905.99036952448 ++ dR6=190 ++ Rdc=0.58 ++ L1=0.88E-4 ++ C1=3.25E-12 ++ R1=84e3 +.ends 1260_744282101_100u +************* +.SUBCKT 1260_744282102_1m 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=3.29424871509595e-010 ++ dC4=3.90749966372341e-009 ++ dL4=1.349179388e-006 ++ dR5=3205.99036952448 ++ dR6=298 ++ Rdc=2.575 ++ L1=0.46E-3 ++ C1=8.46E-12 ++ R1=152e3 ++ L2=0.46E-3 ++ C2=8.46E-12 ++ R2=152e3 +.ends 1260_744282102_1m +************* +.SUBCKT 1210_744284100_10u 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=8.67863759838795e-011 ++ dC4=2.01445437944939e-008 ++ dL4=7.50562709915258e-009 ++ dR5=1260.907429910977 ++ dR6=206.24951963994 ++ Rdc=0.0293 ++ L1=0.9E-5 ++ C1=1.66E-12 ++ R1=24e3 +.ends 1210_744284100_10u +************* +.SUBCKT 1210_744284101_100u 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=2.67863759838795e-010 ++ dC4=2.01445437944939e-008 ++ dL4=2.0562709915258e-008 ++ dR5=5260.907429910977 ++ dR6=226.24951963994 ++ Rdc=0.237 ++ L1=0.89E-4 ++ C1=0.87E-11 ++ R1=83e3 +.ends 1210_744284101_100u +************* +.SUBCKT 1210_744284102_1m 1 2 3 4 +X1 1 2 3 4 SCC PARAMS: ++ ck=4.57863759838795e-010 ++ dC4=2.01445437944939e-006 ++ dL4=3.400562709915258e-007 ++ dR5=260.907429910977 ++ dR6=540.24951963994 ++ Rdc=2.355 ++ L1=0.45E-3 ++ C1=2.1E-11 ++ R1=144e3 ++ L2=0.45E-3 ++ C2=2.1E-11 ++ R2=144e3 +.ends 1210_744284102_1m diff --git a/spice/copy/sub/Contrib/Wurth/WE-SL.lib b/spice/copy/sub/Contrib/Wurth/WE-SL.lib new file mode 100755 index 0000000..5561d40 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-SL.lib @@ -0,0 +1,411 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-SL +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 1310_744202_1m 1 2 3 4 +L5 N010 N009 {L3} Rpar={Rs3} +C1 3 N001 {C1} Rser={R2} +L1 3 N011 {L1} Rpar={Rs1} +L3 N011 N010 {L2} Rpar={Rs2} +L6 N015 N014 {L3} Rpar={Rs3} +C2 4 N013 {C1} Rser={R2} +L2 4 N016 {L1} Rpar={Rs1} +L4 N016 N015 {L2} Rpar={Rs2} +L8 N014 N013 {L4} Rpar={Rs4} +L7 N009 N001 {L4} Rpar={Rs4} +L9 N001 N008 {L5} Rpar={Rs5} Cpar={C2} +L10 N013 N012 {L5} Rpar={Rs5} Cpar={C2} +R1 N002 1 {Rdc} +R2 N012 2 {Rdc} +O1 N002 0 N003 0 mysl1 +R4 N003 N002 {dR4} +O2 N003 0 N004 0 mysl2 +R5 N004 N003 {dR5} +O3 N004 0 N005 0 mysl2 +R6 N005 N004 {dR5} +O4 N005 0 N006 0 mysl1 +R7 N006 N005 {dR4} +O5 N006 0 N007 0 mysl1 +R8 N007 N006 {dR4} +O6 N007 0 N008 0 mysl2 +R9 N008 N007 {dR5} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +.param L1=341.04u +.param L2=448.57u +.param L3=136.82u +.param L4=49.76u +.param L5=90n +.param C1=2.9p +.param C2=1.5p +.param Rs1=4964.13 +.param Rs2=2973.53 +.param Rs3=2668.71 +.param Rs4=965.96 +.param Rs5=690 +.param R2=1.41 +.param Rdc=0.5 +.param L=65mm +.param dL3=720n +.param dC3=56p +.param dR3=0.6 +.param dR4=230 +.model mysl1 LTRA(len={L} R={dR3} L={dL3} C={dC3}) +.model mysl2 LTRA(len={L100} R={dR5} L={dL4} C={dC4}) +.param L100=65mm +.param dL4=19000n +.param dC4=19p +.param dR5=0.01 +.param dR6=200k +.backanno +.ends 1310_744202_1m +********* +.subckt 1310_744203_0.5m 1 2 3 4 +L5 N011 N010 {L3} Rpar={Rs3} +C1 3 N001 {C1} Rser={R2} +L1 3 N012 {L1} Rpar={Rs1} +L3 N012 N011 {L2} Rpar={Rs2} +L6 N015 N014 {L3} Rpar={Rs3} +C2 4 N013 {C1} Rser={R2} +L2 4 N016 {L1} Rpar={Rs1} +L4 N016 N015 {L2} Rpar={Rs2} +L8 N014 N013 {L4} Rpar={Rs4} +L7 N010 N001 {L4} Rpar={Rs4} +L9 N001 N009 {L5} Rpar={Rs5} Cpar={C2} +L10 N013 N018 {L5} Rpar={Rs5} Cpar={C2} +L11 N009 N008 {L6} Rpar={Rs6} Cpar={C3} +L12 N018 N017 {L6} Rpar={Rs6} Cpar={C3} +R2 N002 1 {Rdc} +R3 N017 2 {Rdc} +O1 N002 0 N003 0 mysl1 +R4 N003 N002 {dR4} +O2 N003 0 N004 0 mysl2 +R5 N004 N003 {dR5} +O3 N004 0 N005 0 mysl2 +R6 N005 N004 {dR5} +O4 N005 0 N006 0 mysl1 +R7 N006 N005 {dR4} +O5 N006 0 N007 0 mysl1 +R8 N007 N006 {dR4} +O6 N007 0 N008 0 mysl2 +R9 N008 N007 {dR5} +.param L1=370e-006 +.param L2=506e-009 +.param L3=1.158e-006 +.param L4=681e-009 +.param L5 =3.48e-006 +.param L6 =0.0012u +.param C1=1.69e-012 +.param C2=3.17e-012 +.param C3=2.75e-012 +.param Rs1=5950 +.param Rs2=14800 +.param Rs3=4400 +.param Rs4=50 +.param Rs5=960 +.param Rs6=4765 + .param R2=99 +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K6 L11 L12 1 +.param Rdc=0.36 +.param L=65mm +.param dL3=630n +.param dC3=20p +.param dR3=0.36 +.param dR4=340 +.model mysl1 LTRA(len={L} R={dR3} L={dL3} C={dC3}) +.model mysl2 LTRA(len={L100} R={dR5} L={dL4} C={dC4}) +.param L100=65mm +.param dL4=8000n +.param dC4=19p +.param dR5=0.01 +.param dR6=0.350 +.backanno +.ends 1310_744203_0.5m +********* +.subckt 1310_744204_0.25m 1 2 3 4 +L5 N011 N010 {L3} Rpar={Rs3} +C3 3 N001 {C1} Rser={R2} +L0 3 N013 {L0} Rpar={Rs1} +L3 N012 N011 {L2} Rpar={Rs2} +L6 N016 N015 {L3} Rpar={Rs3} +C4 4 N014 {C1} Rser={R2} +L 4 N018 {L0} Rpar={Rs1} +L4 N017 N016 {L2} Rpar={Rs2} +L8 N015 N014 {L4} Rpar={Rs4} +L7 N010 N001 {L4} Rpar={Rs4} +L9 N001 N009 {L5} Rpar={Rs5} Cpar={C2} +L10 N014 N020 {L5} Rpar={Rs5} Cpar={C2} +L11 N009 N008 {L6} Rpar={Rs6} Cpar={C3} +L12 N020 N019 {L6} Rpar={Rs6} Cpar={C3} +R1 N002 1 {Rdc} +R2 N019 2 {Rdc} +O1 N002 0 N003 0 mysl1 +R4 N003 N002 {dR4} +O2 N003 0 N004 0 mysl2 +R5 N004 N003 {dR5} +O3 N004 0 N005 0 mysl2 +R6 N005 N004 {dR5} +O4 N005 0 N006 0 mysl1 +R7 N006 N005 {dR4} +O5 N006 0 N007 0 mysl1 +R8 N007 N006 {dR4} +O6 N007 0 N008 0 mysl2 +R9 N008 N007 {dR5} +L1 N013 N012 {L1} Rpar={Rs1} +L2 N018 N017 {L1} Rpar={Rs1} +.param L0=25e-006 +.param L1=0.9e-009 +.param L2=142e-06 +.param L3=5.67e-006 +.param L4=1e-006 +.param L5 =2.8e-006 +.param L6 =4.5n +.param C1=2.7e-012 +.param C2=1.75e-012 +.param C3=7.59e-013 +.param Rs1=1100 +.param Rs2=1925 +.param Rs3=73 +.param Rs4=1461 +.param Rs5=1083 +.param Rs6=1021 +.param Rs0=849 +.param R2=90 +K3 L5 L6 1 +K2 L3 L4 1 +K0 L0 L 1 +K4 L7 L8 1 +K6 L9 L10 1 +K7 L11 L12 1 +* differential mode +K1 L1 L2 1 +.model mysl2 LTRA(len={L1} R={dR5} L={dL4} C={dC4}) +.param L1=65mm +.param dL4=8000n +.param dC4=15.5p +.param dR5=0.01 +.param dR6=10 +.param Rdc=0.36 +.param L=65mm +.param dL3=370n +.param dC3=26p +.param dR3=0.36 +.param dR4=500 +.model mysl1 LTRA(len={L} R={dR3} L={dL3} C={dC3}) +.backanno +.ends 1310_744204_0.25m +********* +.subckt 1310_744205_0.1m 1 2 3 4 +C1 N004 N003 {C1} +L2 3 N010 {L1} +R2 3 N010 {Rs1} +C2 N016 N013 {C1} +L3 4 N014 {L1} +R12 3 N004 {R2} +R13 4 N016 {R2} +L9 N014 N013 {L2} +R8 N010 N003 {Rs4} +L8 N010 N003 {L2} +R16 N001 N009 {Rdc} +R17 N011 N015 {Rdc} +R30 4 N014 {Rs1} +R9 N014 N013 {Rs4} +R10 N003 N002 {Rs5} +R11 N013 N012 {Rs5} +C3 N003 N002 {C2} +C4 N013 N012 {C2} +L10 N003 N002 {L3} +L11 N013 N012 {L3} +R19 N002 N001 {Rs6} +R20 N012 N011 {Rs6} +C5 N002 N001 {C3} +C6 N012 N011 {C3} +L12 N002 N001 {L4} +L13 N012 N011 {L4} +R1 N005 1 {Rdc} +R3 N015 2 {Rdc} +O1 N005 0 N006 0 mysl1 +R4 N006 N005 {dR4} +O2 N006 0 N007 0 mysl2 +R5 N007 N006 {dR5} +O3 N007 0 N008 0 mysl2 +R6 N008 N007 {dR5} +O4 N008 0 N009 0 mysl1 +R7 N009 N008 {dR4} +K1 L2 L3 1 +K2 L8 L9 1 +.param L1=70u +.param L2=20u +.param L3=10n +.param L4=10n +.param C1=650.06f +.param C2=90.02f +.param C3=10.02f +.param Rs1=1100 +.param Rs4=15 +.param Rs5=420 +.param Rs6=5 +.param R2=4.41 +K3 L10 L11 1 +K4 L12 L13 1 +.param Rdc=0.10 +.param L=65mm +.param dL3=840n +.param dC3=18p +.param dR3=0.2 +.param dR4=800 +.model mysl1 LTRA(len={L} R={dR3} L={dL3} C={dC3}) +.model mysl2 LTRA(len={L100} R={dR5} L={dL4} C={dC4}) +.param L100=65mm +.param dL4=2400n +.param dC4=9p +.param dR5=0.01 +.param dR6=250 +.backanno +.ends 1310_744205_0.1m +********* +.subckt 1310_744206_60u 1 2 3 4 +L5 N011 N010 {L3} Rpar={Rs3} +C1 3 N001 {C1} Rser={R2} +L1 3 N012 {L1} Rpar={Rs1} +L3 N012 N011 {L2} Rpar={Rs2} +L6 N017 N016 {L3} Rpar={Rs3} +C2 4 N015 {C1} Rser={R2} +L2 4 N018 {L1} Rpar={Rs1} +L4 N018 N017 {L2} Rpar={Rs2} +L8 N016 N015 {L4} Rpar={Rs4} +L7 N010 N001 {L4} Rpar={Rs4} +L9 N001 N009 {L5} Rpar={R5} Cpar={C5} +L10 N015 N014 {L5} Rpar={R5} Cpar={C5} +L11 N009 N008 {L6} Rpar={R6} Cpar={C6} +L12 N014 N013 {L6} Rpar={R6} Cpar={C6} +R1 N002 1 {Rdc} +R2 N013 2 {Rdc} +O1 N002 0 N003 0 mysl1 +R4 N003 N002 {dR4} +O2 N003 0 N004 0 mysl2 +R5 N004 N003 {dR5} +O3 N004 0 N005 0 mysl2 +R6 N005 N004 {dR5} +O4 N005 0 N006 0 mysl1 +R7 N006 N005 {dR4} +O5 N006 0 N007 0 mysl1 +R8 N007 N006 {dR4} +O6 N007 0 N008 0 mysl2 +R9 N008 N007 {dR5} +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K6 L11 L12 1 +.param L1=59e-006 +.param L2=897e-009 +.param L3=8.39e-006 +.param L4=4.64e-006 +.param L5 =3.685e-009 +.param L6 =0.0012e-006 +.param C1=468e-015 +.param C5=185e-015 +.param C6=328e-015 +.param Rs1=2134 +.param Rs2=2105 +.param Rs3=1710 +.param Rs4=669 +.param R5=677 +.param R6=2919 +.param R2=0.05 +* differential mode +.param Rdc=0.16 +.param L=65mm +.param dL3=330n +.param dC3=34p +.param dR3=0.16 +.param dR4=390 +.model mysl1 LTRA(len={L} R={dR3} L={dL3} C={dC3}) +.model mysl2 LTRA(len={L100} R={dR5} L={dL4} C={dC4}) +.param L100=65mm +.param dL4=8000n +.param dC4=19p +.param dR5=0.01 +.param dR6=0.350 +.backanno +.ends 1310_744206_60u +********* +.subckt 1310_744207_35u 1 2 3 4 +R17 N002 1 {Rdc} +R18 N015 2 {Rdc} +L5 N009 N008 {L3} Rpar={Rs3} +C3 3 N001 {C1} Rser={R2} +L1 3 N010 {L1} Rpar={Rs1} +L3 N010 N009 {L2} Rpar={Rs2} +L6 N013 N012 {L3} Rpar={Rs3} +C4 4 N011 {C1} Rser={R2} +L2 4 N014 {L1} Rpar={Rs1} +L4 N014 N013 {L2} Rpar={Rs2} +L8 N012 N011 {L4} Rpar={Rs4} +L7 N008 N001 {L4} Rpar={Rs4} +L9 N001 N007 {L5} Rpar={Rs5} Cpar={C2} +L10 N011 N016 {L5} Rpar={Rs5} Cpar={C2} +L11 N007 N006 {L6} Rpar={Rs6} Cpar={C3} +L12 N016 N015 {L6} Rpar={Rs6} Cpar={C3} +O1 N002 0 N003 0 mysl1 +R3 N003 N002 {dR4} +O2 N003 0 N004 0 mysl2 +R4 N004 N003 {dR5} +O3 N004 0 N005 0 mysl2 +R5 N005 N004 {dR5} +O4 N005 0 N006 0 mysl1 +R6 N006 N005 {dR4} +.param L1=37e-006 +.param L2=300e-009 +.param L3=5.66e-006 +.param L4=3.16e-006 +.param L5 =3.17e-009 +.param L6 =0.0012u +.param C1=422e-015 +.param C2=384e-015 +.param C3=4e-014 +.param Rs1=1070 +.param Rs2=280 +.param Rs3=1095 +.param Rs4=282 +.param Rs5=1315 +.param Rs6=2156 + .param R2=1.715 +K3 L5 L6 1 +K2 L3 L4 1 +K1 L1 L2 1 +K4 L7 L8 1 +K5 L9 L10 1 +K6 L11 L12 1 +.param Rdc=0.10 +.param L=65mm +.param dL3=530n +.param dC3=46p +.param dR3=0.1 +.param dR4=570 +.model mysl1 LTRA(len={L} R={dR3} L={dL3} C={dC3}) +.model mysl2 LTRA(len={L100} R={dR5} L={dL4} C={dC4}) +.param L100=65mm +.param dL4=8000n +.param dC4=9p +.param dR5=0.01 +.param dR6=900 +.backanno +.ends 1310_744207_35u diff --git a/spice/copy/sub/Contrib/Wurth/WE-SL1.lib b/spice/copy/sub/Contrib/Wurth/WE-SL1.lib new file mode 100755 index 0000000..44d0f81 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-SL1.lib @@ -0,0 +1,259 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-SL1 +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT SL1 1 2 3 4 PARAMS: +L3 N004 N003 {L3} +R50 N004 N003 {Rs3} +C1 4 N500 {C1} +R500 N500 N002 {R2} +L7 4 N005 {L1} +R51 4 N005 {Rs1} +L5 N005 N004 {L2} +R52 N005 N004 {Rs2} +L4 N011 N010 {L3} +R53 N011 N010 {Rs3} +C2 3 N501 {C1} +R501 N501 N009 {R2} +L8 3 N012 {L1} +R54 3 N012 {Rs1} +L6 N012 N011 {L2} +R55 N012 N011 {Rs2} +L2 N010 N009 {L4} +R56 N010 N009 {Rs4} +L1 N003 N002 {L4} +R57 N003 N002 {Rs4} +R17 N001 1 {Rdc} +R18 N007 2 {Rdc} +R14 N002 N001 {dR4} +C3 N002 N502 {dC3} +R502 N502 N001 {dR3} +L9 N006 N001 {dL3} +L10 N007 N008 {dL3} +C4 N006 N008 {ck} +R1000 N006 N008 1000G +C5 N009 N503 {dC3} +R503 N503 N007 {dR3} +R15 N009 N007 {dR4} +L11 N002 N006 {dL3} +L12 N008 N009 {dL3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L9 L10 L11 L12 1 +.ends SL1 +********* +.SUBCKT 6536_744212100_10u 1 2 3 4 +X1 1 2 3 4 SL1 PARAMS: ++ L1=7.65u ++ L2=0.56u ++ L3=5u ++ L4=1u ++ C1=0.0722p ++ Rs1=161.14 ++ Rs2=250.06 ++ Rs3=1124.92 ++ Rs4=752.83 ++ R2=43.37 ++ dL3=50.21nH ++ dC3=0.196pF ++ dR3=679.74 ++ dR4=3904 ++ Rdc=0.153 ++ ck=0.405pF +.ends 6536_744212100_10u +********* +.SUBCKT 6536_744212470_47u 1 2 3 4 +X1 1 2 3 4 SL1 PARAMS: ++ Rdc=0.106 ++ ck=1.52pF ++ L1=20.21u ++ L2=5.57u ++ L3=6.01u ++ L4=2.91u ++ C1=0.178pF ++ Rs1=158.72 ++ Rs2=151.2 ++ Rs3=117.13 ++ Rs4=193.86 ++ R2=8.77 ++ dL3=21.71nH ++ dC3=0.221pF ++ dR3=2.09 ++ dR4=903.16 +.ends 6536_744212470_47u +********* +.SUBCKT 6536_744212510_51u 1 2 3 4 +X1 1 2 3 4 SL1 PARAMS: ++ Rdc=0.106 ++ ck=1.52pF ++ L1=14.02u ++ L2=5.8u ++ L3=5.87u ++ L4=1.64u ++ C1=0.208pF ++ Rs1=133.15 ++ Rs2=137.36 ++ Rs3=173.16 ++ Rs4=199.71 ++ R2=8.54 ++ dL3=21.02nH ++ dC3=0.350pF ++ dR3=2.79 ++ dR4=850.8 +.ends 6536_744212510_51u +********* +.SUBCKT 6536_744212820_82u 1 2 3 4 +X1 1 2 3 4 SL1 PARAMS: ++ Rdc=0.12 ++ ck=1.52pF ++ L1=39.03u ++ L2=12.08u ++ L3=12.54u ++ L4=5.77u ++ C1=0.264p ++ Rs1=187.39 ++ Rs2=284.35 ++ Rs3=193.82 ++ Rs4=318.52 ++ R2=18.87 ++ dL3=29.14nH ++ dC3=0.434pF ++ dR3=2.99 ++ dR4=1153.55 +.ends 6536_744212820_82u +********* +.SUBCKT 6536_744212101_100u 1 2 3 4 +X1 1 2 3 4 SL1 PARAMS: ++ dL3=38.34nH ++ dC3=0.294pF ++ dR3=1.58 ++ dR4=1448.71 ++ Rdc=0.124 ++ ck=1.45pF ++ L1=33.14u ++ L2=14.15u ++ L3=5.52u ++ L4=2.9u ++ C1=0.256p ++ Rs1=291.03 ++ Rs2=295.04 ++ Rs3=296.6 ++ Rs4=281.33 ++ R2=10.41 +.ends 6536_744212101_100u +********* +.SUBCKT 6536_744212181_180u 1 2 3 4 +X1 1 2 3 4 SL1 PARAMS: ++ dL3=58.81nH ++ dC3=0.569pF ++ dR3=5.13 ++ dR4=1858.61 ++ Rdc=0.185 ++ ck=2.34pF ++ L1=72.36u ++ L2=21.67u ++ L3=13.81u ++ L4=7.48u ++ C1=0.436p ++ Rs1=565.42 ++ Rs2=534.65 ++ Rs3=580.20 ++ Rs4=557.03 ++ R2=13.23 +.ends 6536_744212181_180u +********* +.SUBCKT 6536_744212221_220u 1 2 3 4 +X1 1 2 3 4 SL1 PARAMS: ++ Rdc=0.18 ++ ck=2.46pF ++ L1=67.72u ++ L2=28.42u ++ L3=17.39u ++ L4=5.27u ++ C1=0.441p ++ Rs1=704.83 ++ Rs2=690.79 ++ Rs3=689.89 ++ Rs4=698.14 ++ R2=6.2 ++ dL3=73.02nH ++ dC3=0.332pF ++ dR3=4.91 ++ dR4=2342.19 +.ends 6536_744212221_220u +********* +.SUBCKT 6536_744212331_330u 1 2 3 4 PARAMS: ++ dL3=84.50nH ++ dC3=0.726pF ++ dR3=3.34 ++ dR4=2466.51 ++ Rdc=0.233 ++ ck=2.9pF ++ L1=97.37u ++ L2=75.64u ++ L3=24.92u ++ L4=13.85u ++ C1=0.416p ++ Rs1=214.02 ++ Rs2=2450.86 ++ Rs3=287.54 ++ Rs4=1007.24 ++ R2=30.64 ++ dL5=21n ++ dR5=530 ++ dC5=0.45p +L3 N005 N004 {L3} +R50 N005 N004 {Rs3} +C1 4 N500 {C1} +R500 N500 N003 {R2} +L7 4 N006 {L1} +R51 4 N006 {Rs1} +L5 N006 N005 {L2} +R52 N006 N005 {Rs2} +L4 N013 N012 {L3} +R53 N013 N012 {Rs3} +C2 3 N501 {C1} +R501 N501 N011 {R2} +L8 3 N014 {L1} +R54 3 N014 {Rs1} +L6 N014 N013 {L2} +R55 N014 N013 {Rs2} +L2 N012 N011 {L4} +R56 N012 N011 {Rs4} +L1 N004 N003 {L4} +R57 N004 N003 {Rs4} +R17 N001 1 {Rdc} +R18 N008 2 {Rdc} +R14 N002 N001 {dR4} +C3 N002 N502 {dC3} +R502 N502 N001 {dR3} +L9 N007 N001 {dL3} +L10 N008 N009 {dL3} +C4 N007 N009 {ck} +C5 N010 N503 {dC3} +R503 N503 N008 {dR3} +R15 N010 N008 {dR4} +L11 N002 N007 {dL3} +L12 N009 N010 {dL3} +L13 N003 N002 {dL5} +R58 N003 N002 {dR5} +C58 N003 N002 {dC5} +L14 N011 N010 {dL5} +R59 N011 N010 {dR5} +C59 N011 N010 {dC5} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L9 L10 L11 L12 1 +K5 L13 L14 1 +.ends 6536_744212331_330u diff --git a/spice/copy/sub/Contrib/Wurth/WE-SL2.lib b/spice/copy/sub/Contrib/Wurth/WE-SL2.lib new file mode 100755 index 0000000..b326057 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-SL2.lib @@ -0,0 +1,1172 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-SL2 +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 9260_744220_4.7m 1 2 3 4 PARAMS: ++ L1=4.0m ++ L2=0.02m ++ L3=1u ++ L4=1u ++ C1=4.192p ++ RS1=0.027meg ++ RS2=0.01meg ++ RS3=1 ++ RS4=1 ++ R2=0.999 ++ L5=10n ++ R5=1100 ++ C5=1p ++ Rdc=0.53 ++ dL3=5.0n ++ dC3=3.7pF ++ DR3=900 +L3 N013 N012 {L3} +R50 N013 N012 {Rs3} +C1 N500 N001 {C1} +R500 N500 4 {R2} +L7 4 N014 {L1} +R51 4 N014 {Rs1} +L5 N014 N013 {L2} +R52 N014 N013 {Rs2} +L4 N027 N026 {L3} +R53 N027 N026 {Rs3} +C2 N501 N025 {C1} +R501 N501 3 {R2} +L8 3 N028 {L1} +R54 3 N028 {Rs1} +L6 N028 N027 {L2} +R55 N028 N027 {Rs2} +L2 N026 N025 {L4} +R56 N026 N025 {Rs4} +L1 N012 N001 {L4} +R57 N012 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N023 2 {Rdc} +L13 N001 N003 {L5} +R58 N001 N003 {R5} +C50 N001 N003 {C5} +L14 N025 N024 {L5} +R59 N025 N024 {R5} +C51 N025 N024 {C5} +L9 N004 N002 {dL3} +C3 N004 N015 {dC3} +L10 N005 N004 {dL3} +L11 N023 N015 {dL3} +L12 N015 N016 {dL3} +C4 N005 N016 {dC3} +L15 N006 N005 {dL3} +L16 N016 N017 {dL3} +C5 N006 N017 {dC3} +L17 N007 N006 {dL3} +L18 N017 N018 {dL3} +C6 N007 N018 {dC3} +L19 N008 N007 {dL3} +L20 N018 N019 {dL3} +R1 N003 N002 {dR3} +R2 N024 N023 {dR3} +C7 N008 N019 {dC3} +L21 N009 N008 {dL3} +L22 N019 N020 {dL3} +L23 N010 N009 {dL3} +L24 N020 N021 {dL3} +C8 N009 N020 {dC3} +L25 N011 N010 {dL3} +L26 N021 N022 {dL3} +C9 N010 N021 {dC3} +L27 N003 N011 {dL3} +L28 N022 N024 {dL3} +C10 N011 N022 {dC3} +R3 N004 N015 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +K16 L23 L24 1 +K17 L25 L26 1 +K18 L27 L28 1 +.ends 9260_744220_4.7m +****** +.subckt 9260_744221_2m 1 2 3 4 PARAMS: ++ L1=1031.58u ++ L2=415.51u ++ L3=181.58u ++ L4=140.75u ++ C1=3.02p ++ RS1=6684.17 ++ RS2=4684.17 ++ RS3=4862.1 ++ RS4=4684.17 ++ R2=6.84 ++ L5=11n ++ R5=700 ++ C5=0.3p ++ Rdc=0.315 ++ dL3=2.9n ++ dC3=3.1pF ++ DR3=325 +L3 N013 N012 {L3} +R50 N013 N012 {Rs3} +C1 N500 N001 {C1} +R500 N500 4 {R2} +L7 4 N014 {L1} +R51 4 N014 {Rs1} +L5 N014 N013 {L2} +R52 N014 N013 {Rs2} +L4 N027 N026 {L3} +R53 N027 N026 {Rs3} +C2 N501 N025 {C1} +R501 N501 3 {R2} +L8 3 N028 {L1} +R54 3 N028 {Rs1} +L6 N028 N027 {L2} +R55 N028 N027 {Rs2} +L2 N026 N025 {L4} +R56 N026 N025 {Rs4} +L1 N012 N001 {L4} +R57 N012 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N023 2 {Rdc} +L13 N001 N003 {L5} +R58 N001 N003 {R5} +C50 N001 N003 {C5} +L14 N025 N024 {L5} +R59 N025 N024 {R5} +C51 N025 N024 {C5} +L9 N004 N002 {dL3} +C3 N004 N015 {dC3} +L10 N005 N004 {dL3} +L11 N023 N015 {dL3} +L12 N015 N016 {dL3} +C4 N005 N016 {dC3} +L15 N006 N005 {dL3} +L16 N016 N017 {dL3} +C5 N006 N017 {dC3} +L17 N007 N006 {dL3} +L18 N017 N018 {dL3} +C6 N007 N018 {dC3} +L19 N008 N007 {dL3} +L20 N018 N019 {dL3} +R1 N003 N002 {dR3} +R2 N024 N023 {dR3} +C7 N008 N019 {dC3} +L21 N009 N008 {dL3} +L22 N019 N020 {dL3} +L23 N010 N009 {dL3} +L24 N020 N021 {dL3} +C8 N009 N020 {dC3} +L25 N011 N010 {dL3} +L26 N021 N022 {dL3} +C9 N010 N021 {dC3} +L27 N003 N011 {dL3} +L28 N022 N024 {dL3} +C10 N011 N022 {dC3} +R3 N004 N015 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +K16 L23 L24 1 +K17 L25 L26 1 +K18 L27 L28 1 +.ends 9260_744221_2m +****** +.subckt 9260_744222_1m 1 2 3 4 PARAMS: ++ L1=903.92u ++ L2=150u ++ L3=31.34u ++ L4=80.58u ++ C1=2.11p ++ RS1=4851.44 ++ RS2=5010.9 ++ RS3=5838.5 ++ RS4=2481.47 ++ R2=0.278 ++ L5=80n ++ R5=900 ++ C5=1p ++ Rdc=0.228 ++ dL3=2.6n ++ dC3=2.5pF ++ DR3=375 +L3 N012 N011 {L3} +R50 N012 N011 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N013 {L1} +R51 4 N013 {Rs1} +L5 N013 N012 {L2} +R52 N013 N012 {Rs2} +L4 N025 N024 {L3} +R53 N025 N024 {Rs3} +C2 N501 N023 {C1} +R501 3 N501 {R2} +L8 3 N026 {L1} +R54 3 N026 {Rs1} +L6 N026 N025 {L2} +R55 N026 N025 {Rs2} +L2 N024 N023 {L4} +R56 N024 N023 {Rs4} +L1 N011 N001 {L4} +R57 N011 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N015 2 {Rdc} +L13 N001 N003 {L5} +R58 N001 N003 {R5} +C50 N001 N003 {C5} +L14 N023 N022 {L5} +R59 N023 N022 {R5} +C51 N023 N022 {C5} +L9 N004 N002 {dL3} +C3 N004 N014 {dC3} +L10 N005 N004 {dL3} +L11 N015 N014 {dL3} +L12 N014 N016 {dL3} +C4 N005 N016 {dC3} +L15 N006 N005 {dL3} +L16 N016 N017 {dL3} +C5 N006 N017 {dC3} +L17 N007 N006 {dL3} +L18 N017 N018 {dL3} +C6 N007 N018 {dC3} +L19 N008 N007 {dL3} +L20 N018 N019 {dL3} +R1 N003 N002 {dR3} +R2 N022 N015 {dR3} +C7 N008 N019 {dC3} +L21 N009 N008 {dL3} +L22 N019 N020 {dL3} +L23 N010 N009 {dL3} +L24 N020 N021 {dL3} +C8 N009 N020 {dC3} +L25 N003 N010 {dL3} +L26 N021 N022 {dL3} +C9 N010 N021 {dC3} +R3 N004 N014 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +K16 L23 L24 1 +K17 L25 L26 1 +.ends 9260_744222_1m +****** +.subckt 9260_744223_0.5m 1 2 3 4 PARAMS: ++ L1=275.25u ++ L2=110.72u ++ L3=99.33u ++ L4=1u ++ C1=0.999p ++ RS1=1390.05 ++ RS2=3069.35 ++ RS3=2848.62 ++ RS4=3191.56 ++ R2=116.68 ++ Rdc=0.12 ++ dL3=3n ++ dC3=3.09pF ++ DR3=100 +L3 N009 N008 {L3} +R50 N009 N008 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N010 {L1} +R51 4 N010 {Rs1} +L5 N010 N009 {L2} +R52 N010 N009 {Rs2} +L4 N019 N018 {L3} +R53 N019 N018 {Rs3} +C2 N501 N017 {C1} +R501 3 N501 {R2} +L8 3 N020 {L1} +R54 3 N020 {Rs1} +L6 N020 N019 {L2} +R55 N020 N019 {Rs2} +L2 N018 N017 {L4} +R56 N018 N017 {Rs4} +L1 N008 N001 {L4} +R57 N008 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N012 2 {Rdc} +L9 N003 N002 {dL3} +C3 N003 N011 {dC3} +L10 N004 N003 {dL3} +L11 N012 N011 {dL3} +L12 N011 N013 {dL3} +C4 N004 N013 {dC3} +L15 N005 N004 {dL3} +L16 N013 N014 {dL3} +C5 N005 N014 {dC3} +L17 N006 N005 {dL3} +L18 N014 N015 {dL3} +C6 N006 N015 {dC3} +L19 N007 N006 {dL3} +L20 N015 N016 {dL3} +R1 N001 N002 {dR3} +R2 N017 N012 {dR3} +C7 N007 N016 {dC3} +L21 N001 N007 {dL3} +L22 N016 N017 {dL3} +R3 N003 N011 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +.ends 9260_744223_0.5m +****** +.subckt 9260_744224_0.25m 1 2 3 4 PARAMS: ++ L1=57.16u ++ L2=95.94u ++ L3=37.44u ++ L4=4.53u ++ C1=1.1923p ++ RS1=901.29 ++ RS2=2901.98 ++ RS3=106.96 ++ RS4=109.69 ++ R2=0.923 ++ L5=19n ++ R5=220 ++ C5=1p ++ Rdc=0.13 ++ dL3=3.4n ++ dC3=3.1pF ++ DR3=325 +L3 N008 N007 {L3} +R50 N008 N007 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N009 {L1} +R51 4 N009 {Rs1} +L5 N009 N008 {L2} +R52 N009 N008 {Rs2} +L4 N017 N016 {L3} +R53 N017 N016 {Rs3} +C2 N501 N015 {C1} +R501 3 N501 {R2} +L8 3 N018 {L1} +R54 3 N018 {Rs1} +L6 N018 N017 {L2} +R55 N018 N017 {Rs2} +L2 N016 N015 {L4} +R56 N016 N015 {Rs4} +L1 N007 N001 {L4} +R57 N007 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N010 2 {Rdc} +L13 N001 N003 {L5} +R58 N001 N003 {R5} +C50 N001 N003 {C5} +L14 N015 N014 {L5} +R59 N015 N014 {R5} +C51 N015 N014 {C5} +L9 N004 N002 {dL3} +C3 N004 N011 {dC3} +R900 N004 N011 1000g +L10 N005 N004 {dL3} +L11 N010 N011 {dL3} +L12 N011 N012 {dL3} +C4 N005 N012 {dC3} +L15 N006 N005 {dL3} +L16 N012 N013 {dL3} +C5 N006 N013 {dC3} +L17 N003 N006 {dL3} +L18 N013 N014 {dL3} +R1 N003 N002 {dR3} +R2 N014 N010 {dR3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +.ends 9260_744224_0.25m +****** +.subckt 9260_744225_40u 1 2 3 4 PARAMS: ++ L1=35.25u ++ L2=8.5u ++ L3=11.2u ++ L4=5.31u ++ C1=0.328p ++ RS1=1909.47 ++ RS2=2460.94 ++ RS3=2527.33 ++ RS4=3068.24 ++ R2=63.57 ++ Rdc=0.25 ++ dL3=2.9n ++ dC3=2.9pF ++ DR3=350 +L3 N009 N008 {L3} +R50 N009 N008 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N010 {L1} +R51 4 N010 {Rs1} +L5 N010 N009 {L2} +R52 N010 N009 {Rs2} +L4 N019 N018 {L3} +R53 N019 N018 {Rs3} +C2 N501 N017 {C1} +R501 3 N501 {R2} +L8 3 N020 {L1} +R54 3 N020 {Rs1} +L6 N020 N019 {L2} +R55 N020 N019 {Rs2} +L2 N018 N017 {L4} +R56 N018 N017 {Rs4} +L1 N008 N001 {L4} +R57 N008 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N011 2 {Rdc} +L9 N003 N002 {dL3} +C3 N003 N012 {dC3} +R600 N003 N012 1000g +L10 N004 N003 {dL3} +L11 N011 N012 {dL3} +L12 N012 N013 {dL3} +C4 N004 N013 {dC3} +L15 N005 N004 {dL3} +L16 N013 N014 {dL3} +C5 N005 N014 {dC3} +L17 N006 N005 {dL3} +L18 N014 N015 {dL3} +C6 N006 N015 {dC3} +L19 N007 N006 {dL3} +L20 N015 N016 {dL3} +R1 N001 N002 {dR3} +R2 N017 N011 {dR3} +C7 N007 N016 {dC3} +L21 N001 N007 {dL3} +L22 N016 N017 {dL3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +.ends 9260_744225_40u +****** +.subckt 9260_744226_10u 1 2 3 4 PARAMS: ++ L1=4.42u ++ L2=1.76u ++ L3=5.05u ++ L4=1.01u ++ C1=0.287p ++ RS1=561.68 ++ RS2=1407.84 ++ RS3=657.84 ++ RS4=540.95 ++ R2=43 ++ Rdc=0.064 ++ dL3=3.1n ++ dC3=2.1pF ++ DR3=400 +L3 N007 N006 {L3} +R50 N007 N006 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N008 {L1} +R51 4 N008 {Rs1} +L5 N008 N007 {L2} +R52 N008 N007 {Rs2} +L4 N015 N014 {L3} +R53 N015 N014 {Rs3} +C2 N501 N013 {C1} +R501 3 N501 {R2} +L8 3 N016 {L1} +R54 3 N016 {Rs1} +L6 N016 N015 {L2} +R55 N016 N015 {Rs2} +L2 N014 N013 {L4} +R56 N014 N013 {Rs4} +L1 N006 N001 {L4} +R57 N006 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N009 2 {Rdc} +L9 N003 N002 {dL3} +C3 N003 N010 {dC3} +R900 N003 N010 1000g +L10 N004 N003 {dL3} +L11 N009 N010 {dL3} +L12 N010 N011 {dL3} +C4 N004 N011 {dC3} +L15 N005 N004 {dL3} +L16 N011 N012 {dL3} +C5 N005 N012 {dC3} +L17 N001 N005 {dL3} +L18 N012 N013 {dL3} +R1 N001 N002 {dR3} +R2 N013 N009 {dR3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +.ends 9260_744226_10u +****** +.subckt 9260_744227_51u 1 2 3 4 PARAMS: ++ L1=47.41u ++ L2=2.86u ++ L3=2.85u ++ L4=2.77u ++ C1=2.126p ++ RS1=5559.15 ++ RS2=5675.07 ++ RS3=5504.73 ++ RS4=5293.47 ++ R2=1.66 ++ L5=42n ++ R5=850 ++ C5=0.490p ++ Rdc=0.113 ++ dL3=2.95n ++ dC3=3.3pF ++ DR3=275 +L3 N010 N009 {L3} +R50 N010 N009 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N011 {L1} +R51 4 N011 {Rs1} +L5 N011 N010 {L2} +R52 N011 N010 {Rs2} +L4 N021 N020 {L3} +R53 N021 N020 {Rs3} +C2 N501 N019 {C1} +R501 3 N501 {R2} +L8 3 N022 {L1} +R54 3 N022 {Rs1} +L6 N022 N021 {L2} +R55 N022 N021 {Rs2} +L2 N020 N019 {L4} +R56 N020 N019 {Rs4} +L1 N009 N001 {L4} +R57 N009 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N012 2 {Rdc} +L13 N001 N003 {L5} +R58 N001 N003 {R5} +C50 N001 N003 {C5} +L14 N019 N018 {L5} +R59 N019 N018 {R5} +C51 N019 N018 {C5} +L9 N004 N002 {dL3} +C3 N004 N013 {dC3} +R900 N004 N013 1000g +L10 N005 N004 {dL3} +L11 N012 N013 {dL3} +L12 N013 N014 {dL3} +C4 N005 N014 {dC3} +L15 N006 N005 {dL3} +L16 N014 N015 {dL3} +C5 N006 N015 {dC3} +L17 N007 N006 {dL3} +L18 N015 N016 {dL3} +R1 N003 N002 {dR3} +R2 N018 N012 {dR3} +C6 N007 N016 {dC3} +L19 N008 N007 {dL3} +L20 N016 N017 {dL3} +C7 N008 N017 {dC3} +L21 N003 N008 {dL3} +L22 N017 N018 {dL3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +.ends 9260_744227_51u +****** +.subckt 9260_744228_25u 1 2 3 4 PARAMS: ++ L1=18.58u ++ L2=13.91u ++ L3=6.75u ++ L4=3.32u ++ C1=0.439p ++ RS1=410.16 ++ RS2=2686.01 ++ RS3=695.54 ++ RS4=3420.44 ++ R2=31.34 ++ Rdc=0.096 ++ dL3=3.6n ++ dC3=3.25pF ++ DR3=325 +L3 N007 N006 {L3} +R50 N007 N006 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N008 {L1} +R51 4 N008 {Rs1} +L5 N008 N007 {L2} +R52 N008 N007 {Rs2} +L4 N015 N014 {L3} +R53 N015 N014 {Rs3} +C2 N501 N013 {C1} +R501 3 N501 {R2} +L8 3 N016 {L1} +R54 3 N016 {Rs1} +L6 N016 N015 {L2} +R55 N016 N015 {Rs2} +L2 N014 N013 {L4} +R56 N014 N013 {Rs4} +L1 N006 N001 {L4} +R57 N006 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N009 2 {Rdc} +L9 N003 N002 {dL3} +C3 N003 N010 {dC3} +R900 N003 N010 1000g +L10 N004 N003 {dL3} +L11 N009 N010 {dL3} +L12 N010 N011 {dL3} +C4 N004 N011 {dC3} +L15 N005 N004 {dL3} +L16 N011 N012 {dL3} +C5 N005 N012 {dC3} +L17 N001 N005 {dL3} +L18 N012 N013 {dL3} +R1 N001 N002 {dR3} +R2 N013 N009 {dR3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +.ends 9260_744228_25u +****** +.subckt 9260_744229_6.5m 1 2 3 4 PARAMS: ++ L1=1.2m ++ L2=2.06m ++ L3=3.41m ++ L4=666.81u ++ C1=3.97p ++ RS1=12435.13 ++ RS2=10260.61 ++ RS3=14669.58 ++ RS4=14575.64 ++ R2=128.68 ++ L5=120n ++ R5=1100 ++ C5=2p ++ Rdc=0.77 ++ dL3=4n ++ dC3=2.7pF ++ DR3=195 ++ L6=9n ++ R6=700 ++ C6=1p +L3 N019 N018 {L3} +R50 N019 N018 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N020 {L1} +R51 4 N020 {Rs1} +L5 N020 N019 {L2} +R52 N020 N019 {Rs2} +L4 N039 N038 {L3} +R53 N039 N038 {Rs3} +C2 N501 N037 {C1} +R501 3 N501 {R2} +L8 3 N040 {L1} +R54 3 N040 {Rs1} +L6 N040 N039 {L2} +R55 N040 N039 {Rs2} +L2 N038 N037 {L4} +R56 N038 N037 {Rs4} +L1 N018 N001 {L4} +R57 N018 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N021 2 {Rdc} +L13 N001 N017 {L5} +R58 N001 N017 {R5} +C50 N001 N017 {C5} +L14 N037 N036 {L5} +R59 N037 N036 {R5} +C51 N037 N036 {C5} +L9 N004 N002 {dL3} +C3 N004 N022 {dC3} +R900 N004 N022 1000g +L10 N005 N004 {dL3} +L11 N021 N022 {dL3} +L12 N022 N023 {dL3} +C4 N005 N023 {dC3} +L15 N006 N005 {dL3} +L16 N023 N024 {dL3} +C5 N006 N024 {dC3} +L17 N007 N006 {dL3} +L18 N024 N025 {dL3} +R1 N003 N002 {dR3} +R2 N035 N021 {dR3} +L19 N017 N003 {L6} +R60 N017 N003 {R6} +C52 N017 N003 {C6} +L20 N036 N035 {L6} +R61 N036 N035 {R6} +C61 N036 N035 {C6} +C6 N007 N025 {dC3} +L21 N008 N007 {dL3} +L22 N025 N026 {dL3} +C7 N008 N026 {dC3} +L23 N009 N008 {dL3} +L24 N026 N027 {dL3} +C8 N009 N027 {dC3} +L25 N010 N009 {dL3} +L26 N027 N028 {dL3} +C9 N010 N028 {dC3} +L27 N011 N010 {dL3} +L28 N028 N029 {dL3} +C10 N011 N029 {dC3} +L29 N012 N011 {dL3} +L30 N029 N030 {dL3} +C11 N012 N030 {dC3} +L31 N013 N012 {dL3} +L32 N030 N031 {dL3} +C12 N013 N031 {dC3} +L33 N014 N013 {dL3} +L34 N031 N032 {dL3} +C13 N014 N032 {dC3} +L35 N015 N014 {dL3} +L36 N032 N033 {dL3} +C14 N015 N033 {dC3} +L37 N016 N015 {dL3} +L38 N033 N034 {dL3} +C15 N016 N034 {dC3} +L39 N003 N016 {dL3} +L40 N034 N035 {dL3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K6 L19 L20 1 +K14 L21 L22 1 +K15 L23 L24 1 +K16 L25 L26 1 +K17 L27 L28 1 +K18 L29 L30 1 +K19 L31 L32 1 +K20 L33 L34 1 +K21 L35 L36 1 +K22 L37 L38 1 +K23 L39 L40 1 +.ends 9260_744229_6.5m +****** + +.subckt 9260_744220103_10m 1 2 3 4 PARAMS: ++ L1=11.5m ++ L2=0.1u ++ L3=0.1u ++ L4=0.1u ++ C1=12.9p ++ RS1=137498.68 ++ RS2=131011.22 ++ RS3=30411.71 ++ RS4=30168.52 ++ R2=78150.5 ++ dL3=0.020uH ++ dC3=10pF ++ DR3=100 ++ DR4=20000 ++ Rdc=0.139 ++ ck=1pF +L3 N004 N003 {L3} +R50 N004 N003 {Rs3} +C1 4 N002 {C1} +R500 4 N002 {R2} +L7 4 N005 {L1} +R51 4 N005 {Rs1} +L5 N005 N004 {L2} +R52 N005 N004 {Rs2} +L4 N011 N010 {L3} +R53 N011 N010 {Rs3} +C2 N501 N009 {C1} +R501 3 N501 {R2} +L8 3 N012 {L1} +R54 3 N012 {Rs1} +L6 N012 N011 {L2} +R55 N012 N011 {Rs2} +L2 N010 N009 {L4} +R56 N010 N009 {Rs4} +L1 N003 N002 {L4} +R57 N003 N002 {Rs4} +R17 N001 1 {Rdc} +R18 N007 2 {Rdc} +R14 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N006 N001 {dL3} +L10 N007 N008 {dL3} +C4 N006 N008 {ck} +R900 N006 N008 1000g +C5 N503 N007 {dC3} +R503 N009 N503 {dR3} +R15 N009 N007 {dR4} +L11 N002 N006 {dL3} +L12 N008 N009 {dL3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L9 L10 L11 L12 1 +.ends 9260_744220103_10m +****** +.subckt 9260_744220203_20m 1 2 3 4 PARAMS: ++ L1=24.5m ++ L2=0.1u ++ L3=0.1u ++ L4=0.1u ++ C1=15.0p ++ RS1=307498.68 ++ RS2=301011.22 ++ RS3=300411.71 ++ RS4=300168.52 ++ R2=138150.5 ++ dL3=0.0320uH ++ dC3=10pF ++ DR3=1 ++ DR4=100meg ++ Rdc=0.139 ++ ck=1pF +L3 N004 N003 {L3} +R50 N004 N003 {Rs3} +C1 4 N002 {C1} +R500 4 N002 {R2} +L7 4 N005 {L1} +R51 4 N005 {Rs1} +L5 N005 N004 {L2} +R52 N005 N004 {Rs2} +L4 N011 N010 {L3} +R53 N011 N010 {Rs3} +C2 N501 N009 {C1} +R501 3 N501 {R2} +L8 3 N012 {L1} +R54 3 N012 {Rs1} +L6 N012 N011 {L2} +R55 N012 N011 {Rs2} +L2 N010 N009 {L4} +R56 N010 N009 {Rs4} +L1 N003 N002 {L4} +R57 N003 N002 {Rs4} +R17 N001 1 {Rdc} +R18 N007 2 {Rdc} +R14 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N006 N001 {dL3} +L10 N007 N008 {dL3} +C4 N006 N008 {ck} +R900 N006 N008 1000g +C5 N503 N007 {dC3} +R503 N009 N503 {dR3} +R15 N009 N007 {dR4} +L11 N002 N006 {dL3} +L12 N008 N009 {dL3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L9 L10 L11 L12 1 +.ends 9260_744220203_20m + + + +.subckt 9260_744225S_40u 1 2 3 4 PARAMS: ++ dL3=133.89nH ++ dC3=0.761pF ++ DR3=151.37 ++ DR4=8295.7 ++ Rdc=0.196 ++ ck=1.1pF ++ L5=127n ++ R5=1800 ++ C5=0.575p ++ L1=18.83u ++ L2=3.47u ++ L3=18.77u ++ L4=2.83u ++ C1=0.2808p ++ RS1=2685 ++ RS2=3490 ++ RS3=2400 ++ RS4=3490 ++ R2=16 +L3 N005 N004 {L3} +R50 N005 N004 {Rs3} +C1 N500 N003 {C1} +R500 4 N500 {R2} +L7 4 N006 {L1} +R51 4 N006 {Rs1} +L5 N006 N005 {L2} +R52 N006 N005 {Rs2} +L4 N013 N012 {L3} +R53 N013 N012 {Rs3} +C2 N501 N011 {C1} +R501 3 N501 {R2} +L8 3 N014 {L1} +R54 3 N014 {Rs1} +L6 N014 N013 {L2} +R55 N014 N013 {Rs2} +L2 N012 N011 {L4} +R56 N012 N011 {Rs4} +L1 N004 N003 {L4} +R57 N004 N003 {Rs4} +R17 N001 1 {Rdc} +R18 N008 2 {Rdc} +R14 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N007 N001 {dL3} +L10 N008 N009 {dL3} +C4 N007 N009 {ck} +R900 N007 N009 1000g +C5 N503 N008 {dC3} +R503 N010 N503 {dR3} +R15 N010 N008 {dR4} +L11 N002 N007 {dL3} +L12 N009 N010 {dL3} +L13 N003 N002 {L5} +R58 N003 N002 {R5} +C50 N003 N002 {C5} +L14 N011 N010 {L5} +R59 N011 N010 {R5} +C51 N011 N010 {C5} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L9 L10 L11 L12 1 +K6 L13 L14 1 +.ends 9260_744225S_40u +****** +.subckt 9260_744226S_10u 1 2 3 4 PARAMS: ++ L1=3.27u ++ L2=1.12u ++ L3=5.19u ++ L4=1.02u ++ C1=0.223p ++ RS1=497.8 ++ RS2=909.05 ++ RS3=643.4 ++ RS4=681.85 ++ R2=39.85 ++ dL3=47.66nH ++ dC3=0.347pF ++ DR3=234.83 ++ DR4=3590.58 ++ Rdc=0.0615 ++ ck=0.9pF +L3 N004 N003 {L3} +R50 N004 N003 {Rs3} +C1 N500 N002 {C1} +R500 4 N500 {R2} +L7 4 N005 {L1} +R51 4 N005 {Rs1} +L5 N005 N004 {L2} +R52 N005 N004 {Rs2} +L4 N011 N010 {L3} +R53 N011 N010 {Rs3} +C2 N501 N009 {C1} +R501 3 N501 {R2} +L8 3 N012 {L1} +R54 3 N012 {Rs1} +L6 N012 N011 {L2} +R55 N012 N011 {Rs2} +L2 N010 N009 {L4} +R56 N010 N009 {Rs4} +L1 N003 N002 {L4} +R57 N003 N002 {Rs4} +R17 N001 1 {Rdc} +R18 N007 2 {Rdc} +R14 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N006 N001 {dL3} +L10 N007 N008 {dL3} +C4 N006 N008 {ck} +R900 N006 N008 1000g +C5 N503 N007 {dC3} +R503 N009 N503 {dR3} +R15 N009 N007 {dR4} +L11 N002 N006 {dL3} +L12 N008 N009 {dL3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L9 L10 L11 L12 1 +.ends 9260_744226S_10u +****** +.subckt 9260_744227S_51u 1 2 3 4 PARAMS: ++ L1=24.45u ++ L2=11.18u ++ L3=6.45u ++ L4=5.02u ++ C1=0.4027p ++ RS1=3561.59 ++ RS2=3846.11 ++ RS3=2081.67 ++ RS4=1967.35 ++ R2=86.7 ++ dL3=210.35nH ++ dC3=0.33028pF ++ DR3=40 ++ DR4=6357.71 ++ Rdc=0.209 ++ ck=1.67pF +L3 N004 N003 {L3} +R50 N004 N003 {Rs3} +C1 N500 N002 {C1} +R500 4 N500 {R2} +L7 4 N005 {L1} +R51 4 N005 {Rs1} +L5 N005 N004 {L2} +R52 N005 N004 {Rs2} +L4 N011 N010 {L3} +R53 N011 N010 {Rs3} +C2 N501 N009 {C1} +R501 3 N501 {R2} +L8 3 N012 {L1} +R54 3 N012 {Rs1} +L6 N012 N011 {L2} +R55 N012 N011 {Rs2} +L2 N010 N009 {L4} +R56 N010 N009 {Rs4} +L1 N003 N002 {L4} +R57 N003 N002 {Rs4} +R17 N001 1 {Rdc} +R18 N007 2 {Rdc} +R14 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N006 N001 {dL3} +L10 N007 N008 {dL3} +C4 N006 N008 {ck} +R900 N006 N008 1000g +C5 N503 N007 {dC3} +R503 N009 N503 {dR3} +R15 N009 N007 {dR4} +L11 N002 N006 {dL3} +L12 N008 N009 {dL3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L9 L10 L11 L12 1 +.ends 9260_744227S_51u +****** +.subckt 9260_744228S_25u 1 2 3 4 PARAMS: ++ L1=14.28u ++ L2=13.1u ++ L3=2.1u ++ L4=0.1u ++ C1=0.281p ++ RS1=13498.68 ++ RS2=1011.22 ++ RS3=6411.71 ++ RS4=6168.52 ++ R2=6150.5 ++ dL3=99.87nH ++ dC3=0.555pF ++ DR3=123.17 ++ DR4=5477.23 ++ Rdc=0.139 ++ ck=1pF +L3 N004 N003 {L3} +R50 N004 N003 {Rs3} +C1 4 N002 {C1} +R500 4 N002 {R2} +L7 4 N005 {L1} +R51 4 N005 {Rs1} +L5 N005 N004 {L2} +R52 N005 N004 {Rs2} +L4 N011 N010 {L3} +R53 N011 N010 {Rs3} +C2 N501 N009 {C1} +R501 3 N501 {R2} +L8 3 N012 {L1} +R54 3 N012 {Rs1} +L6 N012 N011 {L2} +R55 N012 N011 {Rs2} +L2 N010 N009 {L4} +R56 N010 N009 {Rs4} +L1 N003 N002 {L4} +R57 N003 N002 {Rs4} +R17 N001 1 {Rdc} +R18 N007 2 {Rdc} +R14 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N006 N001 {dL3} +L10 N007 N008 {dL3} +C4 N006 N008 {ck} +R900 N006 N008 1000g +C5 N503 N007 {dC3} +R503 N009 N503 {dR3} +R15 N009 N007 {dR4} +L11 N002 N006 {dL3} +L12 N008 N009 {dL3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K5 L9 L10 L11 L12 1 +.ends 9260_744228S_25u +****** \ No newline at end of file diff --git a/spice/copy/sub/Contrib/Wurth/WE-SL3.lib b/spice/copy/sub/Contrib/Wurth/WE-SL3.lib new file mode 100755 index 0000000..26eefa5 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-SL3.lib @@ -0,0 +1,413 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-SL3 +* Library Type: Pspice +* Version: rev20a +* Created/modified by: Paul +* Date and Time : 2020-03-05 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT 9065_744252101_0.1m 1 2 3 4 PARAMS: ++ L1=62.14u ++ L2=20.53u ++ L3=14.10u ++ L4=5.1u ++ C1=0.56p ++ Rs1=2566.63 ++ Rs2=5578.77 ++ Rs3=2566.33 ++ Rs4=2566.33 ++ R2=2.41 ++ Rdc=0.5 ++ dL3=2.6n ++ dC3=2.2pF ++ dR3=550 ++ L5=14n ++ R5=1400 ++ C5=0.2p +L3 N010 N009 {L3} +R50 N010 N009 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N011 {L1} +R51 4 N011 {Rs1} +L5 N011 N010 {L2} +R52 N011 N010 {Rs2} +L4 N021 N020 {L3} +R53 N021 N020 {Rs3} +C2 N501 N019 {C1} +R501 3 N501 {R2} +L8 3 N022 {L1} +R54 3 N022 {Rs1} +L6 N022 N021 {L2} +R55 N022 N021 {Rs2} +L2 N020 N019 {L4} +R56 N020 N019 {Rs4} +L1 N009 N001 {L4} +R57 N009 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N013 2 {Rdc} +L9 N004 N002 {dL3} +C3 N004 N012 {dC3} +L10 N005 N004 {dL3} +L11 N013 N012 {dL3} +L12 N012 N014 {dL3} +C4 N005 N014 {dC3} +L15 N006 N005 {dL3} +L16 N014 N015 {dL3} +C5 N006 N015 {dC3} +L17 N007 N006 {dL3} +L18 N015 N016 {dL3} +R1 N003 N002 {dR3} +R2 N018 N013 {dR3} +L13 N001 N003 {L5} +R58 N001 N003 {R5} +C50 N001 N003 {C5} +L14 N019 N018 {L5} +R59 N019 N018 {R5} +C51 N019 N018 {C5} +C6 N007 N016 {dC3} +L19 N008 N007 {dL3} +L20 N016 N017 {dL3} +C7 N008 N017 {dC3} +L21 N003 N008 {dL3} +L22 N017 N018 {dL3} +R3 N004 N012 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K5 L13 L14 1 +K14 L19 L20 1 +K15 L21 L22 1 +.ends 9065_744252101_0.1m +******* +.SUBCKT 9065_744252220_22u 1 2 3 4 PARAMS: ++ L1=16.30u ++ L2=0.977u ++ L3=3.18u ++ L4=5.29u ++ C1=0.188p ++ Rs1=801.40 ++ Rs2=959.93 ++ Rs3=710.48 ++ Rs4=1059.89 ++ R2=238.55 ++ Rdc=0.142 ++ dL3=2.8n ++ dC3=1.3pF ++ dR3=775 +L3 N007 N006 {L3} +R50 N007 N006 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N008 {L1} +R51 4 N008 {Rs1} +L5 N008 N007 {L2} +R52 N008 N007 {Rs2} +L4 N015 N014 {L3} +R53 N015 N014 {Rs3} +C2 N501 N013 {C1} +R501 3 N501 {R2} +L8 3 N016 {L1} +R54 3 N016 {Rs1} +L6 N016 N015 {L2} +R55 N016 N015 {Rs2} +L2 N014 N013 {L4} +R56 N014 N013 {Rs4} +L1 N006 N001 {L4} +R57 N006 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N009 2 {Rdc} +L9 N003 N002 {dL3} +C3 N003 N010 {dC3} +R900 N003 N010 1000g +L10 N004 N003 {dL3} +L11 N009 N010 {dL3} +L12 N010 N011 {dL3} +C4 N004 N011 {dC3} +L15 N005 N004 {dL3} +L16 N011 N012 {dL3} +C5 N005 N012 {dC3} +L17 N001 N005 {dL3} +L18 N012 N013 {dL3} +R1 N001 N002 {dR3} +R2 N013 N009 {dR3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +.ends 9065_744252220_22u +********** +.SUBCKT 9065_744252470_47u 1 2 3 4 PARAMS: ++ L1=53.96u ++ L2=10.09u ++ L3=6.05u ++ L4=11.67u ++ C1=0.278p ++ Rs1=1645.53 ++ Rs2=1245.53 ++ Rs3=2245.53 ++ Rs4=2045.53 ++ R2=32.3 ++ Rdc=0.2 ++ dL3=4n ++ dC3=1.775pF ++ dR3=525 +L3 N007 N006 {L3} +R50 N007 N006 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N008 {L1} +R51 4 N008 {Rs1} +L5 N008 N007 {L2} +R52 N008 N007 {Rs2} +L4 N015 N014 {L3} +R53 N015 N014 {Rs3} +C2 N501 N013 {C1} +R501 3 N501 {R2} +L8 3 N016 {L1} +R54 3 N016 {Rs1} +L6 N016 N015 {L2} +R55 N016 N015 {Rs2} +L2 N014 N013 {L4} +R56 N014 N013 {Rs4} +L1 N006 N001 {L4} +R57 N006 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N009 2 {Rdc} +L9 N003 N002 {dL3} +C3 N003 N010 {dC3} +R900 N003 N010 1000g +L10 N004 N003 {dL3} +L11 N009 N010 {dL3} +L12 N010 N011 {dL3} +C4 N004 N011 {dC3} +L15 N005 N004 {dL3} +L16 N011 N012 {dL3} +C5 N005 N012 {dC3} +L17 N001 N005 {dL3} +L18 N012 N013 {dL3} +R1 N001 N002 {dR3} +R2 N013 N009 {dR3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +.ends 9065_744252470_47u +************ +.SUBCKT 9065_744252510_51u 1 2 3 4 PARAMS: ++ L1=34.3u ++ L2=27.38u ++ L3=14.5u ++ L4=4.2u ++ C1=0.257p ++ Rs1=444.39 ++ Rs2=2200.17 ++ Rs3=2554.11 ++ Rs4=2091.98 ++ R2=329 ++ Rdc=0.239 ++ dL3=3.8n ++ dC3=1.9pF ++ dR3=530 +L3 N007 N006 {L3} +R50 N007 N006 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N008 {L1} +R51 4 N008 {Rs1} +L5 N008 N007 {L2} +R52 N008 N007 {Rs2} +L4 N015 N014 {L3} +R53 N015 N014 {Rs3} +C2 N501 N013 {C1} +R501 3 N501 {R2} +L8 3 N016 {L1} +R54 3 N016 {Rs1} +L6 N016 N015 {L2} +R55 N016 N015 {Rs2} +L2 N014 N013 {L4} +R56 N014 N013 {Rs4} +L1 N006 N001 {L4} +R57 N006 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N009 2 {Rdc} +L9 N003 N002 {dL3} +C3 N003 N010 {dC3} +R900 N003 N010 1000g +L10 N004 N003 {dL3} +L11 N009 N010 {dL3} +L12 N010 N011 {dL3} +C4 N004 N011 {dC3} +L15 N005 N004 {dL3} +L16 N011 N012 {dL3} +C5 N005 N012 {dC3} +L17 N001 N005 {dL3} +L18 N012 N013 {dL3} +R1 N001 N002 {dR3} +R2 N013 N009 {dR3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +.ends 9065_744252510_51u +********************** +.subckt 9065_744253200_20u 1 2 3 4 PARAMS: ++ L1=10.30u ++ L2=1.977u ++ L3=10.18u ++ L4=3.29u ++ C1=0.188p ++ Rs1=521.40 ++ Rs2=559.93 ++ Rs3=470.48 ++ Rs4=1059.89 ++ R2=238.55 ++ Rdc=0.142 ++ dL3=3.8n ++ dC3=1.9pF ++ dR3=500 +L3 N007 N006 {L3} +R50 N007 N006 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N008 {L1} +R51 4 N008 {Rs1} +L5 N008 N007 {L2} +R52 N008 N007 {Rs2} +L4 N015 N014 {L3} +R53 N015 N014 {Rs3} +C2 N501 N013 {C1} +R501 3 N501 {R2} +L8 3 N016 {L1} +R54 3 N016 {Rs1} +L6 N016 N015 {L2} +R55 N016 N015 {Rs2} +L2 N014 N013 {L4} +R56 N014 N013 {Rs4} +L1 N006 N001 {L4} +R57 N006 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N009 2 {Rdc} +L9 N003 N002 {dL3} +C3 N003 N010 {dC3} +R900 N003 N010 1000g +L10 N004 N003 {dL3} +L11 N009 N010 {dL3} +L12 N010 N011 {dL3} +C4 N004 N011 {dC3} +L15 N005 N004 {dL3} +L16 N011 N012 {dL3} +C5 N005 N012 {dC3} +L17 N001 N005 {dL3} +L18 N012 N013 {dL3} +R1 N001 N002 {dR3} +R2 N013 N009 {dR3} +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +.ends 9065_744253200_20u +********* +.SUBCKT 9065_744253101_0.1m 1 2 3 4 PARAMS: ++ L1=20u ++ L2=80u ++ L3=0.1p ++ L4=1u ++ C1=0.55p ++ Rs1=6000 ++ Rs2=5000 ++ Rs3=500 ++ Rs4=500 ++ R2=2 ++ Rdc=0.2 ++ dL3=2.9n ++ dC3=1.8pF ++ dR3=370 ++ L5=0.1p ++ R5=150 ++ C5=0.2p +L3 N010 N009 {L3} +R50 N010 N009 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N011 {L1} +R51 4 N011 {Rs1} +L5 N011 N010 {L2} +R52 N011 N010 {Rs2} +L4 N021 N020 {L3} +R53 N021 N020 {Rs3} +C2 N501 N019 {C1} +R501 3 N501 {R2} +L8 3 N022 {L1} +R54 3 N022 {Rs1} +L6 N022 N021 {L2} +R55 N022 N021 {Rs2} +L2 N020 N019 {L4} +R56 N020 N019 {Rs4} +L1 N009 N001 {L4} +R57 N009 N001 {Rs4} +R17 N002 1 {Rdc} +R18 N013 2 {Rdc} +L9 N004 N002 {dL3} +C3 N004 N012 {dC3} +L10 N005 N004 {dL3} +L11 N013 N012 {dL3} +L12 N012 N014 {dL3} +C4 N005 N014 {dC3} +L15 N006 N005 {dL3} +L16 N014 N015 {dL3} +C5 N006 N015 {dC3} +L17 N007 N006 {dL3} +L18 N015 N016 {dL3} +R1 N003 N002 {dR3} +R2 N018 N013 {dR3} +L13 N001 N003 {L5} +R58 N001 N003 {R5} +C50 N001 N003 {C5} +L14 N019 N018 {L5} +R59 N019 N018 {R5} +C51 N019 N018 {C5} +C6 N007 N016 {dC3} +L19 N008 N007 {dL3} +L20 N016 N017 {dL3} +C7 N008 N017 {dC3} +L21 N003 N008 {dL3} +L22 N017 N018 {dL3} +R3 N004 N012 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K5 L13 L14 1 +K14 L19 L20 1 +K15 L21 L22 1 +.ends 9065_744253101_0.1m +******* \ No newline at end of file diff --git a/spice/copy/sub/Contrib/Wurth/WE-SL5.lib b/spice/copy/sub/Contrib/Wurth/WE-SL5.lib new file mode 100755 index 0000000..07ada56 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-SL5.lib @@ -0,0 +1,760 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-SL5 +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT 1087_744272102_1m 1 2 3 4 PARAMS: ++ L1=953.27u ++ L2=174.16u ++ L3=138.94u ++ L4=84.94u ++ C1=1.16p ++ Rs1=1664.14 ++ Rs2=723.16 ++ Rs3=2150.48 ++ Rs4=2129.37 ++ R2=48.77 ++ L5=40n ++ R5=600 ++ C5=0.55p ++ dL3=361.34nH ++ dC3=1.39pF ++ dR3=501.94 ++ dR4=14255.21 ++ Rdc=0.143 ++ ck=5.71pF +L3 N005 N004 {L3} +R50 N005 N004 {Rs3} +C1 N500 N003 {C1} +R500 4 N500 {R2} +L7 4 N006 {L1} +R51 4 N006 {Rs1} +L5 N006 N005 {L2} +R52 N006 N005 {Rs2} +L4 N013 N012 {L3} +R53 N013 N012 {Rs3} +C2 N501 N011 {C1} +R501 3 N501 {R2} +L8 3 N014 {L1} +R54 3 N014 {Rs1} +L6 N014 N013 {L2} +R55 N014 N013 {Rs2} +L2 N012 N011 {L4} +R56 N012 N011 {Rs4} +L1 N004 N003 {L4} +R57 N004 N003 {Rs4} +L13 N003 N002 {L5} +R58 N003 N002 {R5} +C50 N003 N002 {C5} +L14 N011 N010 {L5} +R59 N011 N010 {R5} +C51 N011 N010 {C5} +R1 N001 1 {Rdc} +R2 N009 2 {Rdc} +R3 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N007 N001 {dL3} +L10 N009 N008 {dL3} +C4 N007 N008 {ck} +C5 N503 N009 {dC3} +R503 N010 N503 {dR3} +R4 N010 N009 {dR4} +L11 N002 N007 {dL3} +L12 N008 N010 {dL3} +R5 N007 N008 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K6 L13 L14 1 +K5 L9 L10 L11 L12 1 +.ends 1087_744272102_1m +********** +.SUBCKT 1087_744272121_120u 1 2 3 4 PARAMS: ++ L1=153.26u ++ L2=13.12u ++ L3=18.62u ++ L4=8.85u ++ C1=0.631p ++ Rs1=121.2 ++ Rs2=313.15 ++ Rs3=210.35 ++ Rs4=293.08 ++ R2=16.68 ++ L5=9n ++ R5=3600 ++ C5=0.3p ++ dL3=49.17nH ++ dC3=1.3pF ++ dR3=637.27 ++ dR4=6930.35 ++ Rdc=0.155 ++ ck=3.8pF +L3 N005 N004 {L3} +R50 N005 N004 {Rs3} +C1 N500 N003 {C1} +R500 4 N500 {R2} +L7 4 N006 {L1} +R51 4 N006 {Rs1} +L5 N006 N005 {L2} +R52 N006 N005 {Rs2} +L4 N013 N012 {L3} +R53 N013 N012 {Rs3} +C2 N501 N011 {C1} +R501 3 N501 {R2} +L8 3 N014 {L1} +R54 3 N014 {Rs1} +L6 N014 N013 {L2} +R55 N014 N013 {Rs2} +L2 N012 N011 {L4} +R56 N012 N011 {Rs4} +L1 N004 N003 {L4} +R57 N004 N003 {Rs4} +L13 N003 N002 {L5} +R58 N003 N002 {R5} +C50 N003 N002 {C5} +L14 N011 N010 {L5} +R59 N011 N010 {R5} +C51 N011 N010 {C5} +R1 N001 1 {Rdc} +R2 N009 2 {Rdc} +R3 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N007 N001 {dL3} +L10 N009 N008 {dL3} +C4 N007 N008 {ck} +C5 N503 N009 {dC3} +R503 N010 N503 {dR3} +R4 N010 N009 {dR4} +L11 N002 N007 {dL3} +L12 N008 N010 {dL3} +R5 N007 N008 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K6 L13 L14 1 +K5 L9 L10 L11 L12 1 +.ends 1087_744272121_120u +********** +.SUBCKT 1087_744272221_220u 1 2 3 4 PARAMS: ++ L1=136.42u ++ L2=11.01u ++ L3=31.73u ++ L4=10.65u ++ C1=0.766p ++ Rs1=238.39 ++ Rs2=356.39 ++ Rs3=489.72 ++ Rs4=358.73 ++ R2=0.1 ++ L5=10n ++ R5=1000 ++ C5=0.3p ++ dL3=77.03nH ++ dC3=0.357pF ++ dR3=760.87 ++ dR4=2511.33 ++ Rdc=0.0235 ++ ck=4.4pF +L3 N005 N004 {L3} +R50 N005 N004 {Rs3} +C1 N500 N003 {C1} +R500 4 N500 {R2} +L7 4 N006 {L1} +R51 4 N006 {Rs1} +L5 N006 N005 {L2} +R52 N006 N005 {Rs2} +L4 N013 N012 {L3} +R53 N013 N012 {Rs3} +C2 N501 N011 {C1} +R501 3 N501 {R2} +L8 3 N014 {L1} +R54 3 N014 {Rs1} +L6 N014 N013 {L2} +R55 N014 N013 {Rs2} +L2 N012 N011 {L4} +R56 N012 N011 {Rs4} +L1 N004 N003 {L4} +R57 N004 N003 {Rs4} +L13 N003 N002 {L5} +R58 N003 N002 {R5} +C50 N003 N002 {C5} +L14 N011 N010 {L5} +R59 N011 N010 {R5} +C51 N011 N010 {C5} +R1 N001 1 {Rdc} +R2 N009 2 {Rdc} +R3 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N007 N001 {dL3} +L10 N009 N008 {dL3} +C4 N007 N008 {ck} +C5 N503 N009 {dC3} +R503 N010 N503 {dR3} +R4 N010 N009 {dR4} +L11 N002 N007 {dL3} +L12 N008 N010 {dL3} +R5 N007 N008 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K6 L13 L14 1 +K5 L9 L10 L11 L12 1 +.ends 1087_744272221_220u +********** +.SUBCKT 1087_744272251_250u 1 2 3 4 PARAMS: ++ L1=344.54u ++ L2=70.01u ++ L3=21.72u ++ L4=29.91u ++ C1=1.21p ++ Rs1=328.19 ++ Rs2=315.21 ++ Rs3=658.23 ++ Rs4=643.55 ++ R2=0.11 ++ L5=11n ++ R5=600 ++ C5=0.45p ++ dL3=98.32nH ++ dC3=1.18pF ++ dR3=1194.47 ++ dR4=13765.42 ++ Rdc=0.054 ++ ck=5.6pF +L3 N005 N004 {L3} +R50 N005 N004 {Rs3} +C1 N500 N003 {C1} +R500 4 N500 {R2} +L7 4 N006 {L1} +R51 4 N006 {Rs1} +L5 N006 N005 {L2} +R52 N006 N005 {Rs2} +L4 N013 N012 {L3} +R53 N013 N012 {Rs3} +C2 N501 N011 {C1} +R501 3 N501 {R2} +L8 3 N014 {L1} +R54 3 N014 {Rs1} +L6 N014 N013 {L2} +R55 N014 N013 {Rs2} +L2 N012 N011 {L4} +R56 N012 N011 {Rs4} +L1 N004 N003 {L4} +R57 N004 N003 {Rs4} +L13 N003 N002 {L5} +R58 N003 N002 {R5} +C50 N003 N002 {C5} +L14 N011 N010 {L5} +R59 N011 N010 {R5} +C51 N011 N010 {C5} +R1 N001 1 {Rdc} +R2 N009 2 {Rdc} +R3 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N007 N001 {dL3} +L10 N009 N008 {dL3} +C4 N007 N008 {ck} +C5 N503 N009 {dC3} +R503 N010 N503 {dR3} +R4 N010 N009 {dR4} +L11 N002 N007 {dL3} +L12 N008 N010 {dL3} +R5 N007 N008 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K6 L13 L14 1 +K5 L9 L10 L11 L12 1 +.ends 1087_744272251_250u +********** +.SUBCKT 1087_744272471_470u 1 2 3 4 PARAMS: ++ L1=439.54u ++ L2=43.43u ++ L3=65.47u ++ L4=24.79u ++ C1=1.39p ++ Rs1=777.17 ++ Rs2=949.82 ++ Rs3=1089.23 ++ Rs4=984.54 ++ R2=3.68 ++ L5=15n ++ R5=600 ++ C5=0.55p ++ dL3=201.86nH ++ dC3=0.897pF ++ dR3=1499.05 ++ dR4=6803.19 ++ Rdc=0.063 ++ ck=6.26pF +L3 N005 N004 {L3} +R50 N005 N004 {Rs3} +C1 N500 N003 {C1} +R500 4 N500 {R2} +L7 4 N006 {L1} +R51 4 N006 {Rs1} +L5 N006 N005 {L2} +R52 N006 N005 {Rs2} +L4 N013 N012 {L3} +R53 N013 N012 {Rs3} +C2 N501 N011 {C1} +R501 3 N501 {R2} +L8 3 N014 {L1} +R54 3 N014 {Rs1} +L6 N014 N013 {L2} +R55 N014 N013 {Rs2} +L2 N012 N011 {L4} +R56 N012 N011 {Rs4} +L1 N004 N003 {L4} +R57 N004 N003 {Rs4} +L13 N003 N002 {L5} +R58 N003 N002 {R5} +C50 N003 N002 {C5} +L14 N011 N010 {L5} +R59 N011 N010 {R5} +C51 N011 N010 {C5} +R1 N001 1 {Rdc} +R2 N009 2 {Rdc} +R3 N002 N001 {dR4} +C3 N502 N001 {dC3} +R502 N002 N502 {dR3} +L9 N007 N001 {dL3} +L10 N009 N008 {dL3} +C4 N007 N008 {ck} +C5 N503 N009 {dC3} +R503 N010 N503 {dR3} +R4 N010 N009 {dR4} +L11 N002 N007 {dL3} +L12 N008 N010 {dL3} +R5 N007 N008 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K6 L13 L14 1 +K5 L9 L10 L11 L12 1 +.ends 1087_744272471_470u +********** +.SUBCKT 1087_744272222_2.2m 1 2 3 4 PARAMS: ++ L1=25.84m ++ L2=1.4m ++ L3=482.43u ++ L4=186.2u ++ C1=2.21p ++ Rs1=2438.41 ++ Rs2=2357.43 ++ Rs3=4143.93 ++ Rs4=5386.09 ++ R2=76.12 ++ L5=95n ++ R5=1100 ++ C5=1.4p ++ dL3=2.9n ++ dC3=3.15pF ++ dR3=280 ++ Rdc=0.308 +L3 N014 N013 {L3} +R50 N014 N013 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N015 {L1} +R51 4 N015 {Rs1} +L5 N015 N014 {L2} +R52 N015 N014 {Rs2} +L4 N029 N028 {L3} +R53 N029 N028 {Rs3} +C2 N501 N027 {C1} +R501 3 N501 {R2} +L8 3 N030 {L1} +R54 3 N030 {Rs1} +L6 N030 N029 {L2} +R55 N030 N029 {Rs2} +L2 N028 N027 {L4} +R56 N028 N027 {Rs4} +L1 N013 N001 {L4} +R57 N013 N001 {Rs4} +L13 N001 N003 {L5} +R58 N001 N003 {R5} +C50 N001 N003 {C5} +L14 N027 N026 {L5} +R59 N027 N026 {R5} +C51 N027 N026 {C5} +R1 N002 1 {Rdc} +R2 N017 2 {Rdc} +L9 N004 N002 {dL3} +C3 N004 N016 {dC3} +L10 N005 N004 {dL3} +L11 N017 N016 {dL3} +L12 N016 N018 {dL3} +C4 N005 N018 {dC3} +L15 N006 N005 {dL3} +L16 N018 N019 {dL3} +C5 N006 N019 {dC3} +L17 N007 N006 {dL3} +L18 N019 N020 {dL3} +R3 N003 N002 {dR3} +R4 N026 N017 {dR3} +C6 N007 N020 {dC3} +L19 N008 N007 {dL3} +L20 N020 N021 {dL3} +C7 N008 N021 {dC3} +L21 N009 N008 {dL3} +L22 N021 N022 {dL3} +C8 N009 N022 {dC3} +L23 N010 N009 {dL3} +L24 N022 N023 {dL3} +C9 N010 N023 {dC3} +L25 N011 N010 {dL3} +L26 N023 N024 {dL3} +C10 N011 N024 {dC3} +L27 N012 N011 {dL3} +L28 N024 N025 {dL3} +C11 N012 N025 {dC3} +L29 N003 N012 {dL3} +L30 N025 N026 {dL3} +R5 N004 N016 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K6 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +K16 L23 L24 1 +K17 L25 L26 1 +K18 L27 L28 1 +K19 L29 L30 1 +.ends 1087_744272222_2.2m +********** +.SUBCKT 1087_744272332_3.3m 1 2 3 4 PARAMS: ++ L1=22.04m ++ L2=300.57u ++ L3=758.21u ++ L4=264.69u ++ C1=2.47p ++ Rs1=5431.79 ++ Rs2=5377.15 ++ Rs3=505.07 ++ Rs4=5496.33 ++ R2=38.28 ++ L5=165n ++ R5=1300 ++ C5=2.4p ++ dL3=2.9n ++ dC3=4.1pF ++ dR3=280 ++ Rdc=0.457 ++ L6=11n ++ R6=600 ++ C6=0.4p +L3 N015 N014 {L3} +R50 N015 N014 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N016 {L1} +R51 4 N016 {Rs1} +L5 N016 N015 {L2} +R52 N016 N015 {Rs2} +L4 N031 N030 {L3} +R53 N031 N030 {Rs3} +C2 N501 N029 {C1} +R501 3 N501 {R2} +L8 3 N032 {L1} +R54 3 N032 {Rs1} +L6 N032 N031 {L2} +R55 N032 N031 {Rs2} +L2 N030 N029 {L4} +R56 N030 N029 {Rs4} +L1 N014 N001 {L4} +R57 N014 N001 {Rs4} +L13 N001 N013 {L5} +R58 N001 N013 {R5} +C50 N001 N013 {C5} +L14 N029 N028 {L5} +R59 N029 N028 {R5} +C51 N029 N028 {C5} +R1 N002 1 {Rdc} +R2 N018 2 {Rdc} +L9 N004 N002 {dL3} +C3 N004 N017 {dC3} +L10 N005 N004 {dL3} +L11 N018 N017 {dL3} +L12 N017 N019 {dL3} +C4 N005 N019 {dC3} +L15 N006 N005 {dL3} +L16 N019 N020 {dL3} +C5 N006 N020 {dC3} +L17 N007 N006 {dL3} +L18 N020 N021 {dL3} +R3 N003 N002 {dR3} +R4 N027 N018 {dR3} +C6 N007 N021 {dC3} +L19 N008 N007 {dL3} +L20 N021 N022 {dL3} +C7 N008 N022 {dC3} +L21 N009 N008 {dL3} +L22 N022 N023 {dL3} +C8 N009 N023 {dC3} +L23 N010 N009 {dL3} +L24 N023 N024 {dL3} +C9 N010 N024 {dC3} +L25 N011 N010 {dL3} +L26 N024 N025 {dL3} +C10 N011 N025 {dC3} +L27 N012 N011 {dL3} +L28 N025 N026 {dL3} +C11 N012 N026 {dC3} +L29 N003 N012 {dL3} +L30 N026 N027 {dL3} +L31 N013 N003 {L6} +R60 N013 N003 {R6} +C52 N013 N003 {C6} +L32 N028 N027 {L6} +R61 N028 N027 {R6} +C53 N028 N027 {C6} +R5 N004 N017 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K6 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +K16 L23 L24 1 +K17 L25 L26 1 +K18 L27 L28 1 +K19 L29 L30 1 +K7 L31 L32 1 +.ends 1087_744272332_3.3m +********** +.SUBCKT 1087_744272392_3.9m 1 2 3 4 PARAMS: ++ L1=104.4m ++ L2=4.07m ++ L3=202.74u ++ L4=300.61u ++ C1=2.26p ++ Rs1=3902.24 ++ Rs2=6341.76 ++ Rs3=4390.46 ++ Rs4=5001.97 ++ R2=66.46 ++ L5=175n ++ R5=1400 ++ C5=2.4p ++ dL3=3.5n ++ dC3=4pF ++ dR3=240 ++ Rdc=0.406 ++ L6=8n ++ R6=600 ++ C6=0.4p +L3 N015 N014 {L3} +R50 N015 N014 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N016 {L1} +R51 4 N016 {Rs1} +L5 N016 N015 {L2} +R52 N016 N015 {Rs2} +L4 N031 N030 {L3} +R53 N031 N030 {Rs3} +C2 N501 N029 {C1} +R501 3 N501 {R2} +L8 3 N032 {L1} +R54 3 N032 {Rs1} +L6 N032 N031 {L2} +R55 N032 N031 {Rs2} +L2 N030 N029 {L4} +R56 N030 N029 {Rs4} +L1 N014 N001 {L4} +R57 N014 N001 {Rs4} +L13 N001 N013 {L5} +R58 N001 N013 {R5} +C50 N001 N013 {C5} +L14 N029 N028 {L5} +R59 N029 N028 {R5} +C51 N029 N028 {C5} +R1 N002 1 {Rdc} +R2 N018 2 {Rdc} +L9 N004 N002 {dL3} +C3 N004 N017 {dC3} +L10 N005 N004 {dL3} +L11 N018 N017 {dL3} +L12 N017 N019 {dL3} +C4 N005 N019 {dC3} +L15 N006 N005 {dL3} +L16 N019 N020 {dL3} +C5 N006 N020 {dC3} +L17 N007 N006 {dL3} +L18 N020 N021 {dL3} +R3 N003 N002 {dR3} +R4 N027 N018 {dR3} +C6 N007 N021 {dC3} +L19 N008 N007 {dL3} +L20 N021 N022 {dL3} +C7 N008 N022 {dC3} +L21 N009 N008 {dL3} +L22 N022 N023 {dL3} +C8 N009 N023 {dC3} +L23 N010 N009 {dL3} +L24 N023 N024 {dL3} +C9 N010 N024 {dC3} +L25 N011 N010 {dL3} +L26 N024 N025 {dL3} +C10 N011 N025 {dC3} +L27 N012 N011 {dL3} +L28 N025 N026 {dL3} +C11 N012 N026 {dC3} +L29 N003 N012 {dL3} +L30 N026 N027 {dL3} +L31 N013 N003 {L6} +R60 N013 N003 {R6} +C52 N013 N003 {C6} +L32 N028 N027 {L6} +R61 N028 N027 {R6} +C53 N028 N027 {C6} +R5 N004 N017 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K6 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +K16 L23 L24 1 +K17 L25 L26 1 +K18 L27 L28 1 +K19 L29 L30 1 +K7 L31 L32 1 +.ends 1087_744272392_3.9m +********** +.SUBCKT 1087_744272472_4.7m 1 2 3 4 PARAMS: ++ L1=279.91u ++ L2=8.01m ++ L3=4.28m ++ L4=103.67u ++ C1=3.66p ++ Rs1=7341.26 ++ Rs2=7341.26 ++ Rs3=7341.26 ++ Rs4=7341.26 ++ R2=52.39 ++ L5=195n ++ R5=1900 ++ C5=2.4p ++ dL3=3.5n ++ dC3=4.6pF ++ dR3=270 ++ Rdc=0.406 ++ L6=12n ++ R6=800 ++ C6=0.4p +L3 N015 N014 {L3} +R50 N015 N014 {Rs3} +C1 N500 N001 {C1} +R500 4 N500 {R2} +L7 4 N016 {L1} +R51 4 N016 {Rs1} +L5 N016 N015 {L2} +R52 N016 N015 {Rs2} +L4 N031 N030 {L3} +R53 N031 N030 {Rs3} +C2 N501 N029 {C1} +R501 3 N501 {R2} +L8 3 N032 {L1} +R54 3 N032 {Rs1} +L6 N032 N031 {L2} +R55 N032 N031 {Rs2} +L2 N030 N029 {L4} +R56 N030 N029 {Rs4} +L1 N014 N001 {L4} +R57 N014 N001 {Rs4} +L13 N001 N013 {L5} +R58 N001 N013 {R5} +C50 N001 N013 {C5} +L14 N029 N028 {L5} +R59 N029 N028 {R5} +C51 N029 N028 {C5} +R1 N002 1 {Rdc} +R2 N018 2 {Rdc} +L9 N004 N002 {dL3} +C3 N004 N017 {dC3} +L10 N005 N004 {dL3} +L11 N018 N017 {dL3} +L12 N017 N019 {dL3} +C4 N005 N019 {dC3} +L15 N006 N005 {dL3} +L16 N019 N020 {dL3} +C5 N006 N020 {dC3} +L17 N007 N006 {dL3} +L18 N020 N021 {dL3} +R3 N003 N002 {dR3} +R4 N027 N018 {dR3} +C6 N007 N021 {dC3} +L19 N008 N007 {dL3} +L20 N021 N022 {dL3} +C7 N008 N022 {dC3} +L21 N009 N008 {dL3} +L22 N022 N023 {dL3} +C8 N009 N023 {dC3} +L23 N010 N009 {dL3} +L24 N023 N024 {dL3} +C9 N010 N024 {dC3} +L25 N011 N010 {dL3} +L26 N024 N025 {dL3} +C10 N011 N025 {dC3} +L27 N012 N011 {dL3} +L28 N025 N026 {dL3} +C11 N012 N026 {dC3} +L29 N003 N012 {dL3} +L30 N026 N027 {dL3} +L31 N013 N003 {L6} +R60 N013 N003 {R6} +C52 N013 N003 {C6} +L32 N028 N027 {L6} +R61 N028 N027 {R6} +C53 N028 N027 {C6} +R5 N004 N017 1000g +K2 L3 L4 1 +K3 L5 L6 1 +K4 L7 L8 1 +K1 L1 L2 1 +K6 L13 L14 1 +K10 L9 L11 1 +K11 L10 L12 1 +K12 L15 L16 1 +K13 L17 L18 1 +K14 L19 L20 1 +K15 L21 L22 1 +K16 L23 L24 1 +K17 L25 L26 1 +K18 L27 L28 1 +K19 L29 L30 1 +K7 L31 L32 1 +.ends 1087_744272472_4.7m \ No newline at end of file diff --git a/spice/copy/sub/Contrib/Wurth/WE-SL5HC.lib b/spice/copy/sub/Contrib/Wurth/WE-SL5HC.lib new file mode 100755 index 0000000..20aaa49 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-SL5HC.lib @@ -0,0 +1,134 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-SL5 HC +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT WE-SL5HC 1 2 3 4 PARAMS: +R_R47 N21893 N21911 {Rs3} +R_R43 N21425 N21441 {Rs2} +R_R4 N22217 N21871 {dR3} +L_L3 N21425 N21441 {L2} +L_L8 N21871 N21893 {L4} +Kn_K1 L_L1 L_L2 1 +R_R37 N21241 4 {R2} +R_R48 N21911 N21925 {Rs2} +R_R44 N21441 4 {Rs1} +C_C4 N21871 N22231 {C1} +L_L1 N21441 4 {L1} +C_C1 N21207 N21217 {dC3} +L_L6 N21893 N21911 {L3} +R_R1 1 N21207 {Rdc} +L_L17 N21207 N21585 {dL3} +R_R49 N21925 3 {Rs1} +Kn_K5 L_L17 L_L18 ++ L_L19 L_L20 0.9999 +R_R3 N21217 N21223 {dR3} +R_R55 N22231 3 {R2} +L_L4 N21911 N21925 {L2} +R_R2 N21207 N21223 {dR4} +L_L19 N21585 N21223 {dL3} +R_R6 2 N21857 {Rdc} +C_C2 N21731 N21585 {ck} +R_R500 N21731 N21585 1000g +Kn_K4 L_L7 L_L8 1 +L_L2 N21925 3 {L1} +R_R41 N21223 N21413 {Rs4} +L_L7 N21223 N21413 {L4} +R_R5 N21857 N21871 {dR4} +L_L18 N21731 N21857 {dL3} +Kn_K3 L_L5 L_L6 1 +R_R46 N21871 N21893 {Rs4} +R_R42 N21413 N21425 {Rs3} +L_L5 N21413 N21425 {L3} +C_C9 N21857 N22217 {dC3} +L_L20 N21871 N21731 {dL3} +Kn_K2 L_L3 L_L4 1 +C_C3 N21223 N21241 {C1} +.ends WE-SL5HC +********** +.SUBCKT 9381_744273102_11u 1 2 3 4 +X1 1 2 3 4 WE-SL5HC PARAMS: ++ dL3=8.06429777947728e-008 ++ dC3=5.81235445708605e-013 ++ dR3=1.17124465558291 ++ dR4=2590.50229091806 ++ Rdc=20.1m ++ ck=0.16p ++ L1=1.5e-6 ++ L2=5.1e-8 ++ L3=2.3e-8 ++ L4=9u ++ C1=.38p ++ Rs1=1000 ++ Rs2=330 ++ Rs3=550 ++ Rs4=1170 ++ R2=10 +.ends 9381_744273102_11u +********** +.SUBCKT 9381_744273222_30u 1 2 3 4 +X1 1 2 3 4 WE-SL5HC PARAMS: ++ dL3=1.9347898070121e-007 ++ dC3=4.36997592474516e-013 ++ dR3=70.4582642501494 ++ dR4=5888.65352901148 ++ Rdc=49.6m ++ ck=0.7p ++ L1=9.05935790096774e-006 ++ L2=3.9126229725683e-006 ++ L3=8.40613114272888e-007 ++ L4=1.60693825679297e-005 ++ C1=2.70788008553559e-013 ++ Rs1=1235.29664616861 ++ Rs2=2165.46826500008 ++ Rs3=2200 ++ Rs4=2000 ++ R2=19.514735620877 +.ends 9381_744273222_30u +********** +.SUBCKT 9381_744273501_5u 1 2 3 4 +X1 1 2 3 4 WE-SL5HC PARAMS: ++ dL3=3.93e-8 ++ dC3=0.35e-12 ++ dR3=13 ++ dR4=1671 ++ Rdc=5.45m ++ ck=0.7p ++ L1=1.70052241211097e-007 ++ L2=3.28274952647289e-006 ++ L3=2.55081340176458e-007 ++ L4=6.43263664471381e-007 ++ C1=3.22930375411713e-013 ++ Rs1=16.058088983099 ++ Rs2=625.149891133385 ++ Rs3=78.6498315729959 ++ Rs4=660.530733763676 ++ R2=18.8618617984175 +.ends 9381_744273501_5u +********** +.SUBCKT 9381_744273801_9u 1 2 3 4 +X1 1 2 3 4 WE-SL5HC PARAMS: ++ dL3=6.08964329298372e-008 ++ dC3=3.33707038180949e-013 ++ dR3=152.176867768252 ++ dR4=2646.73687491363 ++ Rdc=11.14m ++ ck=.7p ++ L1=2.96000149874127e-006 ++ L2=2.95115820659312e-006 ++ L3=1.14971476193807e-006 ++ L4=2.74879474900035e-007 ++ C1=3.77271706082393e-013 ++ Rs1=258.50646466325 ++ Rs2=1133.43225325348 ++ Rs3=261.645717438879 ++ Rs4=980.665595606167 ++ R2=26.5362339479427 +.ends 9381_744273801_9u + diff --git a/spice/copy/sub/Contrib/Wurth/WE-SLM.lib b/spice/copy/sub/Contrib/Wurth/WE-SLM.lib new file mode 100755 index 0000000..deb461e --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-SLM.lib @@ -0,0 +1,240 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-SLM +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT 6033_744242101_100u 1 2 3 4 PARAMS: ++ L1=59.81u ++ L2=26.14u ++ L3=14.50u ++ L4=9.20u ++ C1=2.24p ++ Rs1=2289.57 ++ Rs2=2513.24 ++ Rs3=2225.23 ++ Rs4=3549.67 ++ R2=92.30 ++ L5=50n ++ R5=1100 ++ C5=0.2p ++ Rdc=0.416 ++ dL3=2.5n ++ dC3=2.6pF ++ dR3=250 +R_R7 N27348 3 {R2} +C_C10 N26704 N26214 {dC3} +L_L12 N26238 N26246 {dL3} +Kn_K5 L_L5 L_L6 1 +R_R2 N25820 N26286 {Rs4} +L_L11 N26246 N25848 {dL3} +L_L32 N26804 N26720 {dL3} +R_R1 N25828 4 {R2} +L_L1 N25820 N26286 {L4} +L_L17 N25840 N26214 {dL3} +R_R12 N26852 3 {Rs1} +C_C14 N26720 N26246 {dC3} +L_L31 N26720 N26716 {dL3} +L_L9 N26840 N26852 {L2} +R_R13 N25840 N25848 {dR3} +C_C1 N25820 N25828 {C1} +Kn_K3 L_L3 L_L9 1 +L_L13 N26222 N26230 {dL3} +C_C4 N26804 N26812 {C5} +R_R11 N26840 N26852 {Rs2} +C_C2 N25848 N25820 {C5} +L_L14 N26230 N26238 {dL3} +Kn_K1 L_L1 L_L7 1 +L_L8 N26828 N26840 {L3} +C_C13 N26716 N26238 {dC3} +L_L29 N26712 N26708 {dL3} +R_R3 N26286 N26298 {Rs3} +L_L5 N25848 N25820 {L5} +Kn_K10 L_L17 L_L27 1 +L_L18 N26214 N26222 {dL3} +C_C3 N26812 N27348 {C1} +Kn_K11 L_L18 L_L28 1 +Kn_K15 L_L11 L_L32 1 +R_R16 2 N26898 {Rdc} +R_R9 N26812 N26828 {Rs4} +L_L30 N26716 N26712 {dL3} +Kn_K4 L_L4 L_L10 1 +Kn_K13 L_L14 L_L30 1 +Kn_K12 L_L13 L_L29 1 +L_L4 N26310 4 {L1} +Kn_K2 L_L2 L_L8 1 +R_R15 N26898 N26804 {dR3} +C_C12 N26712 N26230 {dC3} +R_R5 N26310 4 {Rs1} +L_L3 N26298 N26310 {L2} +Kn_K14 L_L12 L_L31 1 +R_R8 N26804 N26812 {R5} +L_L2 N26286 N26298 {L3} +L_L7 N26812 N26828 {L4} +L_L28 N26708 N26704 {dL3} +R_R14 1 N25840 {Rdc} +L_L10 N26852 3 {L1} +R_R6 N25848 N25820 {R5} +L_L27 N26704 N26898 {dL3} +C_C11 N26708 N26222 {dC3} +R_R4 N26298 N26310 {Rs2} +R_R10 N26828 N26840 {Rs3} +L_L6 N26804 N26812 {L5} +R_R17 N26704 N26214 1000g +.ends 6033_744242101_100u +******** +.SUBCKT WE-SLM 1 2 3 4 PARAMS: ++ L1=15.25u ++ L2=7.6u ++ L3=1.97u ++ L4=1.83u ++ C1=0.252p ++ Rs1=565.11 ++ Rs2=845.82 ++ Rs3=966.67 ++ Rs4=603.91 ++ R2=11.49 ++ Rdc=0.149 ++ dL3=1.7n ++ dC3=2.7pF ++ dR3=260 +R_R7 N27348 3 {R2} +C_C10 N26704 N26214 {dC3} +R_R2 N25820 N26286 {Rs4} +R_R1 N25828 4 {R2} +L_L1 N25820 N26286 {L4} +L_L17 N25840 N26214 {dL3} +R_R12 N26852 3 {Rs1} +L_L9 N26840 N26852 {L2} +R_R13 N25840 N25820 {dR3} +C_C1 N25820 N25828 {C1} +Kn_K3 L_L3 L_L9 1 +L_L13 N26222 N26230 {dL3} +R_R11 N26840 N26852 {Rs2} +L_L14 N26230 N25820 {dL3} +Kn_K1 L_L1 L_L7 1 +L_L8 N26828 N26840 {L3} +L_L29 N26712 N26708 {dL3} +R_R3 N26286 N26298 {Rs3} +Kn_K10 L_L17 L_L27 1 +L_L18 N26214 N26222 {dL3} +C_C3 N26820 N27348 {C1} +Kn_K11 L_L18 L_L28 1 +R_R16 2 N26898 {Rdc} +R_R9 N26820 N26828 {Rs4} +L_L30 N26820 N26712 {dL3} +Kn_K4 L_L4 L_L10 1 +Kn_K13 L_L14 L_L30 1 +Kn_K12 L_L13 L_L29 1 +L_L4 N26310 4 {L1} +Kn_K2 L_L2 L_L8 1 +R_R15 N26898 N26820 {dR3} +C_C12 N26712 N26230 {dC3} +R_R5 N26310 4 {Rs1} +L_L3 N26298 N26310 {L2} +L_L2 N26286 N26298 {L3} +L_L7 N26820 N26828 {L4} +L_L28 N26708 N26704 {dL3} +R_R14 1 N25840 {Rdc} +L_L10 N26852 3 {L1} +L_L27 N26704 N26898 {dL3} +C_C11 N26708 N26222 {dC3} +R_R4 N26298 N26310 {Rs2} +R_R10 N26828 N26840 {Rs3} +R_R17 N26704 N26214 1000g +.ends WE-SLM +******** +.SUBCKT 6033_744242110_11u 1 2 3 4 +X1 1 2 3 4 WE-SLM PARAMS: ++ L1=7.45u ++ L2=1.95u ++ L3=1.8u ++ L4=0.85u ++ C1=0.267p ++ Rs1=348 ++ Rs2=209.46 ++ Rs3=364.54 ++ Rs4=512.61 ++ R2=9.64 ++ Rdc=0.108 ++ dL3=2.1n ++ dC3=1.4pF ++ dR3=550 +.ends 6033_744242110_11u +******** +.SUBCKT 6033_744242220_22u 1 2 3 4 +X1 1 2 3 4 WE-SLM PARAMS: ++ L1=15.25u ++ L2=7.6u ++ L3=1.97u ++ L4=1.83u ++ C1=0.252p ++ Rs1=565.11 ++ Rs2=845.82 ++ Rs3=966.67 ++ Rs4=603.91 ++ R2=11.49 ++ Rdc=0.149 ++ dL3=1.7n ++ dC3=2.7pF ++ dR3=260 +.ends 6033_744242220_22u +******** +.SUBCKT 6033_744242330_33u 1 2 3 4 +X1 1 2 3 4 WE-SLM PARAMS: ++ L1=22.39u ++ L2=4.32u ++ L3=6.94u ++ L4=1.94u ++ C1=0.194p ++ Rs1=887 ++ Rs2=1323.9 ++ Rs3=804.8 ++ Rs4=834.89 ++ R2=7.96 ++ Rdc=0.169 ++ dL3=1.9n ++ dC3=3.2pF ++ dR3=230 +.ends 6033_744242330_33u +******** +.SUBCKT 6033_744242471_470u 1 2 3 4 +X1 1 2 3 4 WE-SLM PARAMS: ++ L1=50.33u ++ L2=20.09u ++ L3=110.09u ++ L4=0.26u ++ C1=0.5p ++ Rs1=1620.93 ++ Rs2=329.7 ++ Rs3=2543.93 ++ Rs4=1673.06 ++ R2=30.84 ++ Rdc=0.383 ++ dL3=2.4n ++ dC3=2.83pF ++ dR3=260 +.ends 6033_744242471_470u +******** +.SUBCKT 6033_744242510_51u 1 2 3 4 +X1 1 2 3 4 WE-SLM PARAMS: ++ L1=40.33u ++ L2=1.09u ++ L3=9.09u ++ L4=0.96u ++ C1=0.331p ++ Rs1=2220.93 ++ Rs2=329.7 ++ Rs3=2543.93 ++ Rs4=1673.06 ++ R2=158.84 ++ Rdc=0.223 ++ dL3=2.2n ++ dC3=4.1pF ++ dR3=200 +.ends 6033_744242510_51u \ No newline at end of file diff --git a/spice/copy/sub/Contrib/Wurth/WE-TDC.lib b/spice/copy/sub/Contrib/Wurth/WE-TDC.lib new file mode 100755 index 0000000..d3fd2f1 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-TDC.lib @@ -0,0 +1,561 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SEPIC SMD Coupled Inductor +* Matchcode: WE-TDC +* Library Type: Ltspice +* Version: rev18a +* Created/modified by: Fredo +* Date and Time : 3/15/2018 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 8018_744894300033_0.33u 1 2 3 4 PARAMS: ++ Cww=0.485p ++ Rp1=763 ++ Cp1=1.62p ++ Lp1=0.21u ++ Rp2=763 ++ Cp2=1.62p ++ Lp2=0.21u ++ RDC1=0.0111 ++ RDC2=0.0111 ++ K=0.813 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_744894300068_0.68u 1 2 3 4 PARAMS: ++ Cww=1.2175p ++ Rp1=1283.06 ++ Cp1=1.52p ++ Lp1=0.45u ++ Rp2=1283.06 ++ Cp2=1.52p ++ Lp2=0.45u ++ RDC1=0.0163 ++ RDC2=0.0163 ++ K=0.904 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_74489430010_1u 1 2 3 4 PARAMS: ++ Cww=1.6225p ++ Rp1=1948.86 ++ Cp1=1.81p ++ Lp1=0.7u ++ Rp2=1948.86 ++ Cp2=1.81p ++ Lp2=0.7u ++ RDC1=0.0222 ++ RDC2=0.0222 ++ K=0.93 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_74489430022_2.2u 1 2 3 4 PARAMS: ++ Cww=2.1975p ++ Rp1=3806.4 ++ Cp1=1.89p ++ Lp1=1.53u ++ Rp2=3806.4 ++ Cp2=1.89p ++ Lp2=1.53u ++ RDC1=0.0495 ++ RDC2=0.0495 ++ K=0.477 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_74489430027_2.7u 1 2 3 4 PARAMS: ++ Cww=3.4525p ++ Rp1=4838.14 ++ Cp1=2.29p ++ Lp1=1.98u ++ Rp2=4838.14 ++ Cp2=2.29p ++ Lp2=1.98u ++ RDC1=0.0695 ++ RDC2=0.0695 ++ K=0.962 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_74489430039_3.9u 1 2 3 4 PARAMS: ++ Cww=3.905p ++ Rp1=5329.33 ++ Cp1=2.36p ++ Lp1=2.66u ++ Rp2=5329.33 ++ Cp2=2.36p ++ Lp2=2.66u ++ RDC1=0.082 ++ RDC2=0.082 ++ K=0.976 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_74489430056_5.6u 1 2 3 4 PARAMS: ++ Cww=5.7725p ++ Rp1=7670.19 ++ Cp1=2.2p ++ Lp1=4.34u ++ Rp2=7670.19 ++ Cp2=2.2p ++ Lp2=4.34u ++ RDC1=0.114 ++ RDC2=0.114 ++ K=0.997 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_74489430100_10u 1 2 3 4 PARAMS: ++ Cww=5.8025p ++ Rp1=11623.01 ++ Cp1=2.17p ++ Lp1=7.32u ++ Rp2=11623.01 ++ Cp2=2.17p ++ Lp2=7.32u ++ RDC1=0.19 ++ RDC2=0.19 ++ K=0.984 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_74489430120_12u 1 2 3 4 PARAMS: ++ Cww=6.195p ++ Rp1=11.97 ++ Cp1=2.49p ++ Lp1=8.4u ++ Rp2=11.97 ++ Cp2=2.49p ++ Lp2=8.4u ++ RDC1=0.202 ++ RDC2=0.202 ++ K=0.985 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_74489430150_15u 1 2 3 4 PARAMS: ++ Cww=6.1975p ++ Rp1=15148.49 ++ Cp1=2.15p ++ Lp1=11.26u ++ Rp2=15148.49 ++ Cp2=2.15p ++ Lp2=11.26u ++ RDC1=0.262 ++ RDC2=0.262 ++ K=0.981 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_74489430180_18u 1 2 3 4 PARAMS: ++ Cww=7.5125p ++ Rp1=15346.68 ++ Cp1=2.43p ++ Lp1=13.42u ++ Rp2=15346.68 ++ Cp2=2.43p ++ Lp2=13.42u ++ RDC1=0.345 ++ RDC2=0.345 ++ K=0.987 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_744894400039_0.39u 1 2 3 4 PARAMS: ++ Cww=0.2625p ++ Rp1=924.87 ++ Cp1=1.12p ++ Lp1=0.26u ++ Rp2=924.87 ++ Cp2=1.12p ++ Lp2=0.26u ++ RDC1=0.0116 ++ RDC2=0.0116 ++ K=0.84 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_744894400082_0.82u 1 2 3 4 PARAMS: ++ Cww=1.115p ++ Rp1=1715.37 ++ Cp1=1.36p ++ Lp1=0.57u ++ Rp2=1715.37 ++ Cp2=1.36p ++ Lp2=0.57u ++ RDC1=0.0159 ++ RDC2=0.0159 ++ K=0.93 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_74489440012_1.2u 1 2 3 4 PARAMS: ++ Cww=1.995p ++ Rp1=2576.03 ++ Cp1=1.62p ++ Lp1=1.05u ++ Rp2=2576.03 ++ Cp2=1.62p ++ Lp2=1.05u ++ RDC1=0.0202 ++ RDC2=0.0202 ++ K=0.954 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_74489440018_1.8u 1 2 3 4 PARAMS: ++ Cww=1.8625p ++ Rp1=3094.71 ++ Cp1=1.71p ++ Lp1=1.68u ++ Rp2=3094.71 ++ Cp2=1.71p ++ Lp2=1.68u ++ RDC1=0.0255 ++ RDC2=0.0255 ++ K=0.979 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_74489440027_2.7u 1 2 3 4 PARAMS: ++ Cww=3.9225p ++ Rp1=4176.26 ++ Cp1=3.13p ++ Lp1=2.05u ++ Rp2=4176.26 ++ Cp2=3.13p ++ Lp2=2.05u ++ RDC1=0.0345 ++ RDC2=0.0345 ++ K=0.954 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_74489440036_3.6u 1 2 3 4 PARAMS: ++ Cww=3.4775p ++ Rp1=5788.12 ++ Cp1=3.41p ++ Lp1=2.95u ++ Rp2=5788.12 ++ Cp2=3.41p ++ Lp2=2.95u ++ RDC1=0.047 ++ RDC2=0.047 ++ K=0.941 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_74489440047_4.7u 1 2 3 4 PARAMS: ++ Cww=4.7775p ++ Rp1=5491.59 ++ Cp1=3.91p ++ Lp1=2.95u ++ Rp2=5491.59 ++ Cp2=3.91p ++ Lp2=2.95u ++ RDC1=0.0545 ++ RDC2=0.0545 ++ K=0.973 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_74489440120_12u 1 2 3 4 PARAMS: ++ Cww=10.53p ++ Rp1=10897.48 ++ Cp1=5.06p ++ Lp1=9.7u ++ Rp2=10897.48 ++ Cp2=5.06p ++ Lp2=9.7u ++ RDC1=0.117 ++ RDC2=0.117 ++ K=0.652 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_74489440150_15u 1 2 3 4 PARAMS: ++ Cww=6.245p ++ Rp1=11343.48 ++ Cp1=5.23p ++ Lp1=12.14u ++ Rp2=11343.48 ++ Cp2=5.23p ++ Lp2=12.14u ++ RDC1=0.165 ++ RDC2=0.165 ++ K=0.981 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_74489440180_18u 1 2 3 4 PARAMS: ++ Cww=8.58p ++ Rp1=15599.47 ++ Cp1=5.29p ++ Lp1=15.73u ++ Rp2=15599.47 ++ Cp2=5.29p ++ Lp2=15.73u ++ RDC1=0.179 ++ RDC2=0.179 ++ K=0.972 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_74489440220_22u 1 2 3 4 PARAMS: ++ Cww=12.9825p ++ Rp1=17240.33 ++ Cp1=4.81p ++ Lp1=18.11u ++ Rp2=17240.33 ++ Cp2=4.81p ++ Lp2=18.11u ++ RDC1=0.203 ++ RDC2=0.203 ++ K=0.988 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** diff --git a/spice/copy/sub/Contrib/Wurth/WE-TDC_HV.lib b/spice/copy/sub/Contrib/Wurth/WE-TDC_HV.lib new file mode 100755 index 0000000..4a84b1c --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-TDC_HV.lib @@ -0,0 +1,236 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Coupled Inductor +* Matchcode: WE-TDC_HV +* Library Type: Ltspice +* Version: rev18a +* Created/modified by: Fredo +* Date and Time : 10/15/2018 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 8018_76889430056_5.6u 1 2 3 4 PARAMS: ++ Cww=8.6p ++ Rp1=8208 ++ Cp1=1.977p ++ Lp1=5.656u ++ Rp2=7955 ++ Cp2=1.937p ++ Lp2=5.773u ++ RDC1=0.19 ++ RDC2=0.19 ++ K=0.976509820007678 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_76889430100_10u 1 2 3 4 PARAMS: ++ Cww=12.4p ++ Rp1=13109 ++ Cp1=2.029p ++ Lp1=10.107u ++ Rp2=12977 ++ Cp2=1.984p ++ Lp2=10.335u ++ RDC1=0.28 ++ RDC2=0.28 ++ K=0.983869910099907 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_76889430150_15u 1 2 3 4 PARAMS: ++ Cww=15.2p ++ Rp1=15047 ++ Cp1=2.095p ++ Lp1=14.376u ++ Rp2=16822 ++ Cp2=2.015p ++ Lp2=14.925u ++ RDC1=0.38 ++ RDC2=0.38 ++ K=0.986576572463249 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8018_76889430220_22u 1 2 3 4 PARAMS: ++ Cww=17.8p ++ Rp1=21154 ++ Cp1=1.94p ++ Lp1=23.731u ++ Rp2=22726 ++ Cp2=1.925p ++ Lp2=23.91u ++ RDC1=0.7 ++ RDC2=0.7 ++ K=0.983962305264698 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_76889440047_4.7u 1 2 3 4 PARAMS: ++ Cww=12.6p ++ Rp1=7500 ++ Cp1=3.185p ++ Lp1=4.296u ++ Rp2=6917 ++ Cp2=3.174p ++ Lp2=4.312u ++ RDC1=0.085 ++ RDC2=0.085 ++ K=0.987151500584578 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_76889440100_10u 1 2 3 4 PARAMS: ++ Cww=24.3p ++ Rp1=9559 ++ Cp1=3.858p ++ Lp1=9.541u ++ Rp2=8982 ++ Cp2=3.914p ++ Lp2=9.583u ++ RDC1=0.16 ++ RDC2=0.16 ++ K=0.986407623652615 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_76889440150_15u 1 2 3 4 PARAMS: ++ Cww=25.9p ++ Rp1=18540 ++ Cp1=3.658p ++ Lp1=15.397u ++ Rp2=17890 ++ Cp2=3.697p ++ Lp2=15.234u ++ RDC1=0.3 ++ RDC2=0.3 ++ K=0.987252078583108 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_76889440220_22u 1 2 3 4 PARAMS: ++ Cww=26.4p ++ Rp1=22949 ++ Cp1=4.049p ++ Lp1=20.842u ++ Rp2=25003 ++ Cp2=4.096p ++ Lp2=20.599u ++ RDC1=0.39 ++ RDC2=0.39 ++ K=0.987420882906575 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** +.subckt 8038_76889440330_33u 1 2 3 4 PARAMS: ++ Cww=28.5p ++ Rp1=25849 ++ Cp1=4.343p ++ Lp1=35.633u ++ Rp2=25432 ++ Cp2=4.343p ++ Lp2=35.63u ++ RDC1=0.575 ++ RDC2=0.575 ++ K=0.990102535247249 +C_C1 2 1 {Cww/2} +R_R50 2 1 5000g +C_C2 3 4 {Cww/2} +C_C5 3 2 {Cp1} +R_R1 3 N05454 {RDC1} +R_R2 3 2 {Rp1} +L_L1 N05454 2 {Lp1} +L_L2 N05750 1 {Lp2} +C_C6 4 1 {Cp2} +R_R3 4 1 {Rp2} +R_R4 4 N05750 {RDC2} +Kn_K1 L_L1 L_L2 {K} +.ends +****** diff --git a/spice/copy/sub/Contrib/Wurth/WE-TFC.lib b/spice/copy/sub/Contrib/Wurth/WE-TFC.lib new file mode 100755 index 0000000..b3881d6 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-TFC.lib @@ -0,0 +1,321 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-TFC +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT TFC 1 2 3 4 PARAMS: +L_L22 N15506 N16048 {dL3} +C_C18 N16464 N16990 {dC3} +L_L30 N16272 N16464 {dL3} +L_L28 N15832 N15848 {L2} +L_L36 N16554 N16568 {L2} +R_R33 N17026 4 {R2} +C_C15 N15564 N15574 {C1} +R_R24 N15564 N15820 {Rs4} +R_R31 N16568 4 {Rs1} +Kn_K13 L_L28 L_L36 1 +C_C13 N15506 N15516 {dC3} +R_R20 N16990 N16478 {dR3} +L_L23 N16048 N15522 {dL3} +L_L31 N16478 N16272 {dL3} +L_L29 N15848 3 {L1} +R_R32 N15574 3 {R2} +L_L37 N16568 4 {L1} +R_R25 N15820 N15832 {Rs3} +Kn_K14 L_L29 L_L37 1 +R_R12 N15516 N15522 {dR3} +C_C19 N16478 N17004 {dC4} +L_L24 N15522 N16070 {dL4} +L_L32 N16278 N16478 {dL4} +L_L21 N15544 N15556 {L6} +C_C21 N15544 N15556 {C3} +R_R26 N15832 N15848 {Rs2} +R_R17 2 N16464 {Rdc} +C_C16 N16272 N16048 {ck} +C_C14 N15522 N15538 {dC4} +R_R21 N17004 N16498 {dR5} +L_L25 N16070 N15544 {dL4} +L_L33 N16498 N16278 {dL4} +Kn_K9 L_L24 L_L25 ++ L_L32 L_L33 0.9999 +R_R14 1 N15506 {Rdc} +R_R28 N16522 N16536 {Rs4} +R_R27 N15848 3 {Rs1} +C_C17 N16278 N16070 {ck} +R_R18 N16464 N16478 {dR4} +L_L34 N16522 N16536 {L4} +R_R13 N15538 N15544 {dR5} +L_L26 N15564 N15820 {L4} +R_R29 N16536 N16554 {Rs3} +R_R15 N15506 N15522 {dR4} +Kn_K11 L_L26 L_L34 1 +R_R19 N16478 N16498 {dR6} +Kn_K8 L_L22 L_L23 ++ L_L30 L_L31 0.9999 +Kn_K10 L_L21 L_L41 1 +L_L27 N15820 N15832 {L3} +L_L35 N16536 N16554 {L3} +R_R22 N15544 N15556 {Rs6} +C_C20 N16522 N17026 {C1} +R_R30 N16554 N16568 {Rs2} +R_R16 N15522 N15544 {dR6} +Kn_K12 L_L27 L_L35 1 +R_R35 N17743 N16522 {Rs5} +R_R34 N15556 N15564 {Rs5} +L_L40 N17743 N16522 {L5} +L_L39 N15556 N15564 {L5} +C_C24 N17743 N16522 {C2} +C_C23 N15556 N15564 {C2} +R_R36 N16498 N17743 {Rs6} +L_L41 N16498 N17743 {L6} +C_C25 N16498 N17743 {C3} +Kn_K15 L_L39 L_L40 1 +.ends TFC + ********* +.SUBCKT UU_744862018_1.8m 1 2 3 4 +X1 1 2 3 4 TFC PARAMS: ++ L1=0.00123660190142394 ++ L2=0.00006701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=4.65504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=8.46181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=19837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=2.0826799302894 ++ Rs6=1129.380663145605 ++ R2=39.6163187388244 ++ dL3=9e-07 ++ dC3=9.7e-012 ++ dL4=3.11e-009 ++ dC4=18.33e-014 ++ dR3=0.48 ++ dR4=8680 ++ dR5=0.58 ++ dR6=366 ++ Rdc=0.31 ++ ck=3.4pF +.ends UU_744862018_1.8m + ********* +.SUBCKT UU_744862033_3.3m 1 2 3 4 +X1 1 2 3 4 TFC PARAMS: ++ L1=0.00323660190142394 ++ L2=0.00006701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=2.65504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=8.46181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=49837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=200.0826799302894 ++ Rs6=1129.380663145605 ++ R2=6.6163187388244 ++ dL3=2e-06 ++ dC3=9.9e-012 ++ dL4=6.11e-009 ++ dC4=13.33e-014 ++ dR3=0.48 ++ dR4=11080 ++ dR5=0.58 ++ dR6=366 ++ Rdc=0.51 ++ ck=3.4pF +.ends UU_744862033_3.3m + ********* +.SUBCKT UU_744862056_5.6m 1 2 3 4 +X1 1 2 3 4 TFC PARAMS: ++ L1=0.00553660190142394 ++ L2=0.00006701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=3.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=8.46181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=92837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=200.0826799302894 ++ Rs6=1129.380663145605 ++ R2=6.6163187388244 ++ dL3=3.2e-06 ++ dC3=9.9e-012 ++ dL4=3.11e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=14080 ++ dR5=0.58 ++ dR6=266 ++ Rdc=0.83 ++ ck=3.4pF +.ends UU_744862056_5.6m + ********* +.SUBCKT UU_744862082_8.2m 1 2 3 4 +X1 1 2 3 4 TFC PARAMS: ++ L1=0.00803660190142394 ++ L2=0.00008701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=3.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=9.06181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=142837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=200.0826799302894 ++ Rs6=1129.380663145605 ++ R2=6.6163187388244 ++ dL3=5.2e-06 ++ dC3=9.9e-012 ++ dL4=3.61e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=15080 ++ dR5=0.58 ++ dR6=166 ++ Rdc=1.3 ++ ck=3.4pF +.ends UU_744862082_8.2m + ********* +.SUBCKT UU_744862120_12m 1 2 3 4 +X1 1 2 3 4 TFC PARAMS: ++ L1=0.01253660190142394 ++ L2=0.00008701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=2.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=1.09181731944311e-011 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=245837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=70.0826799302894 ++ Rs6=1129.380663145605 ++ R2=8.6163187388244 ++ dL3=7.5e-06 ++ dC3=1.2e-011 ++ dL4=3.61e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=15080 ++ dR5=0.58 ++ dR6=126 ++ Rdc=2 ++ ck=3.4pF +.ends UU_744862120_12m + ********* +.SUBCKT UU_744862180_18m 1 2 3 4 +X1 1 2 3 4 TFC PARAMS: ++ L1=0.01753660190142394 ++ L2=0.00008701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=2.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=9.39181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=345837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=70.0826799302894 ++ Rs6=1129.380663145605 ++ R2=8.6163187388244 ++ dL3=1.15e-05 ++ dC3=1.05e-011 ++ dL4=3.61e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=20080 ++ dR5=0.58 ++ dR6=126 ++ Rdc=3.1 ++ ck=3.4pF +.ends UU_744862180_18m + ********* +.SUBCKT UU_744862250_25m 1 2 3 4 +X1 1 2 3 4 TFC PARAMS: ++ L1=0.02553660190142394 ++ L2=0.00008701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=2.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=8.69181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=705837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=70.0826799302894 ++ Rs6=829.380663145605 ++ R2=23.6163187388244 ++ dL3=1.6e-05 ++ dC3=1.0e-011 ++ dL4=3.61e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=21080 ++ dR5=0.58 ++ dR6=26 ++ Rdc=3.6 ++ ck=3.4pF +.ends UU_744862250_25m + ********* +.SUBCKT UU_744862100_10m 1 2 3 4 +X1 1 2 3 4 TFC PARAMS: ++ L1=0.01053660190142394 ++ L2=0.00020701705440674 ++ L3=0.20003004088894302 ++ L4=0.000284826199486956 ++ L5=3.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=12.06181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=167000.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=200.0826799302894 ++ Rs6=1129.380663145605 ++ R2=6.6163187388244 ++ dL3=5.95e-06 ++ dC3=11.95e-012 ++ dL4=3.61e-009 ++ dC4=30.33e-014 ++ dR3=0.48 ++ dR4=15700 ++ dR5=0.58 ++ dR6=200 ++ Rdc=1.65 ++ ck=3.4pF +.ends UU_744862100_10m + + diff --git a/spice/copy/sub/Contrib/Wurth/WE-TFCH.lib b/spice/copy/sub/Contrib/Wurth/WE-TFCH.lib new file mode 100755 index 0000000..337071e --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-TFCH.lib @@ -0,0 +1,320 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: Common Mode Power Line Choke +* Matchcode: WE-TFCH +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.SUBCKT TFCH 1 2 3 4 PARAMS: +L_L22 N15506 N16048 {dL3} +C_C18 N16464 N16990 {dC3} +L_L30 N16272 N16464 {dL3} +L_L28 N15832 N15848 {L2} +L_L36 N16554 N16568 {L2} +R_R33 N17026 4 {R2} +C_C15 N15564 N15574 {C1} +R_R24 N15564 N15820 {Rs4} +R_R31 N16568 4 {Rs1} +Kn_K13 L_L28 L_L36 1 +C_C13 N15506 N15516 {dC3} +R_R20 N16990 N16478 {dR3} +L_L23 N16048 N15522 {dL3} +L_L31 N16478 N16272 {dL3} +L_L29 N15848 3 {L1} +R_R32 N15574 3 {R2} +L_L37 N16568 4 {L1} +R_R25 N15820 N15832 {Rs3} +Kn_K14 L_L29 L_L37 1 +R_R12 N15516 N15522 {dR3} +C_C19 N16478 N17004 {dC4} +L_L24 N15522 N16070 {dL4} +L_L32 N16278 N16478 {dL4} +L_L21 N15544 N15556 {L6} +C_C21 N15544 N15556 {C3} +R_R26 N15832 N15848 {Rs2} +R_R17 2 N16464 {Rdc} +C_C16 N16272 N16048 {ck} +C_C14 N15522 N15538 {dC4} +R_R21 N17004 N16498 {dR5} +L_L25 N16070 N15544 {dL4} +L_L33 N16498 N16278 {dL4} +Kn_K9 L_L24 L_L25 ++ L_L32 L_L33 0.9999 +R_R14 1 N15506 {Rdc} +R_R28 N16522 N16536 {Rs4} +R_R27 N15848 3 {Rs1} +C_C17 N16278 N16070 {ck} +R_R18 N16464 N16478 {dR4} +L_L34 N16522 N16536 {L4} +R_R13 N15538 N15544 {dR5} +L_L26 N15564 N15820 {L4} +R_R29 N16536 N16554 {Rs3} +R_R15 N15506 N15522 {dR4} +Kn_K11 L_L26 L_L34 1 +R_R19 N16478 N16498 {dR6} +Kn_K8 L_L22 L_L23 ++ L_L30 L_L31 0.9999 +Kn_K10 L_L21 L_L41 1 +L_L27 N15820 N15832 {L3} +L_L35 N16536 N16554 {L3} +R_R22 N15544 N15556 {Rs6} +C_C20 N16522 N17026 {C1} +R_R30 N16554 N16568 {Rs2} +R_R16 N15522 N15544 {dR6} +Kn_K12 L_L27 L_L35 1 +R_R35 N17743 N16522 {Rs5} +R_R34 N15556 N15564 {Rs5} +L_L40 N17743 N16522 {L5} +L_L39 N15556 N15564 {L5} +C_C24 N17743 N16522 {C2} +C_C23 N15556 N15564 {C2} +R_R36 N16498 N17743 {Rs6} +L_L41 N16498 N17743 {L6} +C_C25 N16498 N17743 {C3} +Kn_K15 L_L39 L_L40 1 +.ends TFCH + ******** +.SUBCKT UU_744861018_1.8m 1 2 3 4 +X1 1 2 3 4 TFCH PARAMS: ++ L1=0.00193660190142394 ++ L2=0.00002701705440674 ++ L3=0.0000023004088894302 ++ L4=0.000001826199486956 ++ L5=4.65504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=8.46181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.57097127528123e-012 ++ Rs1=12837.81419587115 ++ Rs2=155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=573.70200019057 ++ Rs5=2.0826799302894 ++ Rs6=1629.380663145605 ++ R2=3.6163187388244 ++ dL3=9e-07 ++ dC3=8.0e-012 ++ dL4=4.81e-009 ++ dC4=5.33e-018 ++ dR3=0.048 ++ dR4=9280 ++ dR5=11.8 ++ dR6=766 ++ Rdc=0.31 ++ ck=2.32pF +.ends UU_744861018_1.8m + ******** +.SUBCKT UU_744861033_3.3m 1 2 3 4 +X1 1 2 3 4 TFCH PARAMS: ++ L1=0.00323660190142394 ++ L2=0.00006701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=1.65504570380959e-008 ++ L6=1.78498066135292e-008 ++ C1=8.46181731944311e-012 ++ C2=2.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=49837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=200.0826799302894 ++ Rs6=1129.380663145605 ++ R2=16.6163187388244 ++ dL3=1.9e-06 ++ dC3=7e-012 ++ dL4=7.5e-009 ++ dC4=13.33e-014 ++ dR3=0.48 ++ dR4=12780 ++ dR5=0.58 ++ dR6=266 ++ Rdc=0.51 ++ ck=2.32pF +.ends UU_744861033_3.3m + ******** +.SUBCKT UU_744861056_5.6m 1 2 3 4 +X1 1 2 3 4 TFCH PARAMS: ++ L1=0.00553660190142394 ++ L2=0.00006701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=1.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=8.06181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=57837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=200.0826799302894 ++ Rs6=1129.380663145605 ++ R2=36.6163187388244 ++ dL3=3.2e-06 ++ dC3=7.8e-012 ++ dL4=3.11e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=14080 ++ dR5=0.58 ++ dR6=366 ++ Rdc=0.83 ++ ck=2.32pF +.ends UU_744861056_5.6m + ******** +.SUBCKT UU_744861082_8.2m 1 2 3 4 +X1 1 2 3 4 TFCH PARAMS: ++ L1=0.00823660190142394 ++ L2=0.00008701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=3.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=8.16181731944311e-012 ++ C2=1.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=110837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=20.0826799302894 ++ Rs6=729.380663145605 ++ R2=16.6163187388244 ++ dL3=5e-06 ++ dC3=7.7e-012 ++ dL4=3.61e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=16280 ++ dR5=0.58 ++ dR6=166 ++ Rdc=1.3 ++ ck=2.32pF +.ends UU_744861082_8.2m + ******** +.SUBCKT UU_744861100_10m 1 2 3 4 +X1 1 2 3 4 TFCH PARAMS: ++ L1=0.01023660190142394 ++ L2=0.00008701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=3.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=12.16181731944311e-012 ++ C2=1.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=170837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=20.0826799302894 ++ Rs6=1029.380663145605 ++ R2=1.6163187388244 ++ dL3=6.8e-06 ++ dC3=10.5e-012 ++ dL4=4.61e-009 ++ dC4=8.33e-014 ++ dR3=0.48 ++ dR4=16280 ++ dR5=0.58 ++ dR6=466 ++ Rdc=1.65 ++ ck=2.32pF +.ends UU_744861100_10m + ******** +.SUBCKT UU_744861120_12m 1 2 3 4 +X1 1 2 3 4 TFCH PARAMS: ++ L1=0.01253660190142394 ++ L2=0.00008701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=2.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=1.49181731944311e-011 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=275837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=70.0826799302894 ++ Rs6=1129.380663145605 ++ R2=15.6163187388244 ++ dL3=8.1e-06 ++ dC3=1.3e-011 ++ dL4=3.61e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=16080 ++ dR5=0.58 ++ dR6=96 ++ Rdc=2 ++ ck=2.32pF +.ends UU_744861120_12m + ******** +.SUBCKT UU_744861180_18m 1 2 3 4 +X1 1 2 3 4 TFCH PARAMS: ++ L1=0.01753660190142394 ++ L2=0.00008701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=2.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=15.99181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=331837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=70.0826799302894 ++ Rs6=1129.380663145605 ++ R2=8.6163187388244 ++ dL3=1.15e-05 ++ dC3=1.55e-011 ++ dL4=3.61e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=17080 ++ dR5=0.58 ++ dR6=126 ++ Rdc=3.1 ++ ck=2.32pF +.ends UU_744861180_18m + ******** +.SUBCKT UU_744861250_25m 1 2 3 4 +X1 1 2 3 4 TFCH PARAMS: ++ L1=0.03353660190142394 ++ L2=0.00008701705440674 ++ L3=0.000493004088894302 ++ L4=0.000224826199486956 ++ L5=2.25504570380959e-008 ++ L6=2.78498066135292e-008 ++ C1=13.69181731944311e-012 ++ C2=3.73670849014524e-012 ++ C3=1.27097127528123e-012 ++ Rs1=555837.81419587115 ++ Rs2=7155.91701442969 ++ Rs3=192.411087825075 ++ Rs4=5573.70200019057 ++ Rs5=70.0826799302894 ++ Rs6=829.380663145605 ++ R2=23.6163187388244 ++ dL3=1.6e-05 ++ dC3=1.3e-011 ++ dL4=3.61e-009 ++ dC4=10.33e-014 ++ dR3=0.48 ++ dR4=21080 ++ dR5=0.58 ++ dR6=26 ++ Rdc=3.6 ++ ck=2.32pF +.ends UU_744861250_25m + diff --git a/spice/copy/sub/Contrib/Wurth/WE-TPB.lib b/spice/copy/sub/Contrib/Wurth/WE-TPB.lib new file mode 100755 index 0000000..c819602 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-TPB.lib @@ -0,0 +1,8163 @@ + + +.subckt 744833005240 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 262410420.914 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 16360593.1152 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 7450187.22211 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 482889.219939 +Ca5 ns5 0 1e-012 +Ca6 ns6 0 1e-012 +Ra5 ns5 0 3178807.98814 +Ra6 ns6 0 3178807.98814 +Ga5 ns5 0 ns6 0 -8.05370424866e-006 +Ga6 ns6 0 ns5 0 8.05370424866e-006 +Ca7 ns7 0 1e-012 +Ra7 ns7 0 78592.2262071 +Ca8 ns8 0 1e-012 +Ra8 ns8 0 26063.5943057 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 18032.7608079 +Ra10 ns10 0 18032.7608079 +Ga9 ns9 0 ns10 0 5.67204692722e-006 +Ga10 ns10 0 ns9 0 -5.67204692722e-006 +Ca11 ns11 0 1e-012 +Ra11 ns11 0 2475.71988514 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 4595.59837407 +Ra13 ns13 0 4595.59837407 +Ga12 ns12 0 ns13 0 0.000715150699712 +Ga13 ns13 0 ns12 0 -0.000715150699712 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 3821.80080974 +Ra15 ns15 0 3821.80080974 +Ga14 ns14 0 ns15 0 0.000731480112776 +Ga15 ns15 0 ns14 0 -0.000731480112776 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 38119.6325933 +Ra17 ns17 0 38119.6325933 +Ga16 ns16 0 ns17 0 0.000800833624449 +Ga17 ns17 0 ns16 0 -0.000800833624449 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 27657.3095937 +Ra19 ns19 0 27657.3095937 +Ga18 ns18 0 ns19 0 0.000990021424588 +Ga19 ns19 0 ns18 0 -0.000990021424588 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 1021.84714331 +Ra21 ns21 0 1021.84714331 +Ga20 ns20 0 ns21 0 -0.000575085083328 +Ga21 ns21 0 ns20 0 0.000575085083328 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 4576.16665122 +Ra23 ns23 0 4576.16665122 +Ga22 ns22 0 ns23 0 0.00137480973644 +Ga23 ns23 0 ns22 0 -0.00137480973644 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 24419.9145383 +Ra25 ns25 0 24419.9145383 +Ga24 ns24 0 ns25 0 0.00143622065148 +Ga25 ns25 0 ns24 0 -0.00143622065148 +Ca26 ns26 0 1e-012 +Ca27 ns27 0 1e-012 +Ra26 ns26 0 10866.227104 +Ra27 ns27 0 10866.227104 +Ga26 ns26 0 ns27 0 0.00195075799473 +Ga27 ns27 0 ns26 0 -0.00195075799473 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 1536.49223219 +Ra29 ns29 0 1536.49223219 +Ga28 ns28 0 ns29 0 0.00192521311741 +Ga29 ns29 0 ns28 0 -0.00192521311741 +Ca30 ns30 0 1e-012 +Ca31 ns31 0 1e-012 +Ra30 ns30 0 2025.51403767 +Ra31 ns31 0 2025.51403767 +Ga30 ns30 0 ns31 0 0.00215175337384 +Ga31 ns31 0 ns30 0 -0.00215175337384 +Ca32 ns32 0 1e-012 +Ca33 ns33 0 1e-012 +Ra32 ns32 0 5295.98860587 +Ra33 ns33 0 5295.98860587 +Ga32 ns32 0 ns33 0 -0.00260845931481 +Ga33 ns33 0 ns32 0 0.00260845931481 +Ca34 ns34 0 1e-012 +Ca35 ns35 0 1e-012 +Ra34 ns34 0 1371.66069475 +Ra35 ns35 0 1371.66069475 +Ga34 ns34 0 ns35 0 -0.00263050707209 +Ga35 ns35 0 ns34 0 0.00263050707209 +Ca36 ns36 0 1e-012 +Ca37 ns37 0 1e-012 +Ra36 ns36 0 2110.44338255 +Ra37 ns37 0 2110.44338255 +Ga36 ns36 0 ns37 0 0.00335743763387 +Ga37 ns37 0 ns36 0 -0.00335743763387 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 262410420.914 +Ca39 ns39 0 1e-012 +Ra39 ns39 0 16360593.1152 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 7450187.22211 +Ca41 ns41 0 1e-012 +Ra41 ns41 0 482889.219939 +Ca42 ns42 0 1e-012 +Ca43 ns43 0 1e-012 +Ra42 ns42 0 3178807.98814 +Ra43 ns43 0 3178807.98814 +Ga42 ns42 0 ns43 0 -8.05370424866e-006 +Ga43 ns43 0 ns42 0 8.05370424866e-006 +Ca44 ns44 0 1e-012 +Ra44 ns44 0 78592.2262071 +Ca45 ns45 0 1e-012 +Ra45 ns45 0 26063.5943057 +Ca46 ns46 0 1e-012 +Ca47 ns47 0 1e-012 +Ra46 ns46 0 18032.7608079 +Ra47 ns47 0 18032.7608079 +Ga46 ns46 0 ns47 0 5.67204692722e-006 +Ga47 ns47 0 ns46 0 -5.67204692722e-006 +Ca48 ns48 0 1e-012 +Ra48 ns48 0 2475.71988514 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 4595.59837407 +Ra50 ns50 0 4595.59837407 +Ga49 ns49 0 ns50 0 0.000715150699712 +Ga50 ns50 0 ns49 0 -0.000715150699712 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 3821.80080974 +Ra52 ns52 0 3821.80080974 +Ga51 ns51 0 ns52 0 0.000731480112776 +Ga52 ns52 0 ns51 0 -0.000731480112776 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 38119.6325933 +Ra54 ns54 0 38119.6325933 +Ga53 ns53 0 ns54 0 0.000800833624449 +Ga54 ns54 0 ns53 0 -0.000800833624449 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 27657.3095937 +Ra56 ns56 0 27657.3095937 +Ga55 ns55 0 ns56 0 0.000990021424588 +Ga56 ns56 0 ns55 0 -0.000990021424588 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 1021.84714331 +Ra58 ns58 0 1021.84714331 +Ga57 ns57 0 ns58 0 -0.000575085083328 +Ga58 ns58 0 ns57 0 0.000575085083328 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 4576.16665122 +Ra60 ns60 0 4576.16665122 +Ga59 ns59 0 ns60 0 0.00137480973644 +Ga60 ns60 0 ns59 0 -0.00137480973644 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 24419.9145383 +Ra62 ns62 0 24419.9145383 +Ga61 ns61 0 ns62 0 0.00143622065148 +Ga62 ns62 0 ns61 0 -0.00143622065148 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 10866.227104 +Ra64 ns64 0 10866.227104 +Ga63 ns63 0 ns64 0 0.00195075799473 +Ga64 ns64 0 ns63 0 -0.00195075799473 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 1536.49223219 +Ra66 ns66 0 1536.49223219 +Ga65 ns65 0 ns66 0 0.00192521311741 +Ga66 ns66 0 ns65 0 -0.00192521311741 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 2025.51403767 +Ra68 ns68 0 2025.51403767 +Ga67 ns67 0 ns68 0 0.00215175337384 +Ga68 ns68 0 ns67 0 -0.00215175337384 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 5295.98860587 +Ra70 ns70 0 5295.98860587 +Ga69 ns69 0 ns70 0 -0.00260845931481 +Ga70 ns70 0 ns69 0 0.00260845931481 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 1371.66069475 +Ra72 ns72 0 1371.66069475 +Ga71 ns71 0 ns72 0 -0.00263050707209 +Ga72 ns72 0 ns71 0 0.00263050707209 +Ca73 ns73 0 1e-012 +Ca74 ns74 0 1e-012 +Ra73 ns73 0 2110.44338255 +Ra74 ns74 0 2110.44338255 +Ga73 ns73 0 ns74 0 0.00335743763387 +Ga74 ns74 0 ns73 0 -0.00335743763387 +Ca75 ns75 0 1e-012 +Ra75 ns75 0 262410420.914 +Ca76 ns76 0 1e-012 +Ra76 ns76 0 16360593.1152 +Ca77 ns77 0 1e-012 +Ra77 ns77 0 7450187.22211 +Ca78 ns78 0 1e-012 +Ra78 ns78 0 482889.219939 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 3178807.98814 +Ra80 ns80 0 3178807.98814 +Ga79 ns79 0 ns80 0 -8.05370424866e-006 +Ga80 ns80 0 ns79 0 8.05370424866e-006 +Ca81 ns81 0 1e-012 +Ra81 ns81 0 78592.2262071 +Ca82 ns82 0 1e-012 +Ra82 ns82 0 26063.5943057 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 18032.7608079 +Ra84 ns84 0 18032.7608079 +Ga83 ns83 0 ns84 0 5.67204692722e-006 +Ga84 ns84 0 ns83 0 -5.67204692722e-006 +Ca85 ns85 0 1e-012 +Ra85 ns85 0 2475.71988514 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 4595.59837407 +Ra87 ns87 0 4595.59837407 +Ga86 ns86 0 ns87 0 0.000715150699712 +Ga87 ns87 0 ns86 0 -0.000715150699712 +Ca88 ns88 0 1e-012 +Ca89 ns89 0 1e-012 +Ra88 ns88 0 3821.80080974 +Ra89 ns89 0 3821.80080974 +Ga88 ns88 0 ns89 0 0.000731480112776 +Ga89 ns89 0 ns88 0 -0.000731480112776 +Ca90 ns90 0 1e-012 +Ca91 ns91 0 1e-012 +Ra90 ns90 0 38119.6325933 +Ra91 ns91 0 38119.6325933 +Ga90 ns90 0 ns91 0 0.000800833624449 +Ga91 ns91 0 ns90 0 -0.000800833624449 +Ca92 ns92 0 1e-012 +Ca93 ns93 0 1e-012 +Ra92 ns92 0 27657.3095937 +Ra93 ns93 0 27657.3095937 +Ga92 ns92 0 ns93 0 0.000990021424588 +Ga93 ns93 0 ns92 0 -0.000990021424588 +Ca94 ns94 0 1e-012 +Ca95 ns95 0 1e-012 +Ra94 ns94 0 1021.84714331 +Ra95 ns95 0 1021.84714331 +Ga94 ns94 0 ns95 0 -0.000575085083328 +Ga95 ns95 0 ns94 0 0.000575085083328 +Ca96 ns96 0 1e-012 +Ca97 ns97 0 1e-012 +Ra96 ns96 0 4576.16665122 +Ra97 ns97 0 4576.16665122 +Ga96 ns96 0 ns97 0 0.00137480973644 +Ga97 ns97 0 ns96 0 -0.00137480973644 +Ca98 ns98 0 1e-012 +Ca99 ns99 0 1e-012 +Ra98 ns98 0 24419.9145383 +Ra99 ns99 0 24419.9145383 +Ga98 ns98 0 ns99 0 0.00143622065148 +Ga99 ns99 0 ns98 0 -0.00143622065148 +Ca100 ns100 0 1e-012 +Ca101 ns101 0 1e-012 +Ra100 ns100 0 10866.227104 +Ra101 ns101 0 10866.227104 +Ga100 ns100 0 ns101 0 0.00195075799473 +Ga101 ns101 0 ns100 0 -0.00195075799473 +Ca102 ns102 0 1e-012 +Ca103 ns103 0 1e-012 +Ra102 ns102 0 1536.49223219 +Ra103 ns103 0 1536.49223219 +Ga102 ns102 0 ns103 0 0.00192521311741 +Ga103 ns103 0 ns102 0 -0.00192521311741 +Ca104 ns104 0 1e-012 +Ca105 ns105 0 1e-012 +Ra104 ns104 0 2025.51403767 +Ra105 ns105 0 2025.51403767 +Ga104 ns104 0 ns105 0 0.00215175337384 +Ga105 ns105 0 ns104 0 -0.00215175337384 +Ca106 ns106 0 1e-012 +Ca107 ns107 0 1e-012 +Ra106 ns106 0 5295.98860587 +Ra107 ns107 0 5295.98860587 +Ga106 ns106 0 ns107 0 -0.00260845931481 +Ga107 ns107 0 ns106 0 0.00260845931481 +Ca108 ns108 0 1e-012 +Ca109 ns109 0 1e-012 +Ra108 ns108 0 1371.66069475 +Ra109 ns109 0 1371.66069475 +Ga108 ns108 0 ns109 0 -0.00263050707209 +Ga109 ns109 0 ns108 0 0.00263050707209 +Ca110 ns110 0 1e-012 +Ca111 ns111 0 1e-012 +Ra110 ns110 0 2110.44338255 +Ra111 ns111 0 2110.44338255 +Ga110 ns110 0 ns111 0 0.00335743763387 +Ga111 ns111 0 ns110 0 -0.00335743763387 +Ca112 ns112 0 1e-012 +Ra112 ns112 0 262410420.914 +Ca113 ns113 0 1e-012 +Ra113 ns113 0 16360593.1152 +Ca114 ns114 0 1e-012 +Ra114 ns114 0 7450187.22211 +Ca115 ns115 0 1e-012 +Ra115 ns115 0 482889.219939 +Ca116 ns116 0 1e-012 +Ca117 ns117 0 1e-012 +Ra116 ns116 0 3178807.98814 +Ra117 ns117 0 3178807.98814 +Ga116 ns116 0 ns117 0 -8.05370424866e-006 +Ga117 ns117 0 ns116 0 8.05370424866e-006 +Ca118 ns118 0 1e-012 +Ra118 ns118 0 78592.2262071 +Ca119 ns119 0 1e-012 +Ra119 ns119 0 26063.5943057 +Ca120 ns120 0 1e-012 +Ca121 ns121 0 1e-012 +Ra120 ns120 0 18032.7608079 +Ra121 ns121 0 18032.7608079 +Ga120 ns120 0 ns121 0 5.67204692722e-006 +Ga121 ns121 0 ns120 0 -5.67204692722e-006 +Ca122 ns122 0 1e-012 +Ra122 ns122 0 2475.71988514 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 4595.59837407 +Ra124 ns124 0 4595.59837407 +Ga123 ns123 0 ns124 0 0.000715150699712 +Ga124 ns124 0 ns123 0 -0.000715150699712 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 3821.80080974 +Ra126 ns126 0 3821.80080974 +Ga125 ns125 0 ns126 0 0.000731480112776 +Ga126 ns126 0 ns125 0 -0.000731480112776 +Ca127 ns127 0 1e-012 +Ca128 ns128 0 1e-012 +Ra127 ns127 0 38119.6325933 +Ra128 ns128 0 38119.6325933 +Ga127 ns127 0 ns128 0 0.000800833624449 +Ga128 ns128 0 ns127 0 -0.000800833624449 +Ca129 ns129 0 1e-012 +Ca130 ns130 0 1e-012 +Ra129 ns129 0 27657.3095937 +Ra130 ns130 0 27657.3095937 +Ga129 ns129 0 ns130 0 0.000990021424588 +Ga130 ns130 0 ns129 0 -0.000990021424588 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 1021.84714331 +Ra132 ns132 0 1021.84714331 +Ga131 ns131 0 ns132 0 -0.000575085083328 +Ga132 ns132 0 ns131 0 0.000575085083328 +Ca133 ns133 0 1e-012 +Ca134 ns134 0 1e-012 +Ra133 ns133 0 4576.16665122 +Ra134 ns134 0 4576.16665122 +Ga133 ns133 0 ns134 0 0.00137480973644 +Ga134 ns134 0 ns133 0 -0.00137480973644 +Ca135 ns135 0 1e-012 +Ca136 ns136 0 1e-012 +Ra135 ns135 0 24419.9145383 +Ra136 ns136 0 24419.9145383 +Ga135 ns135 0 ns136 0 0.00143622065148 +Ga136 ns136 0 ns135 0 -0.00143622065148 +Ca137 ns137 0 1e-012 +Ca138 ns138 0 1e-012 +Ra137 ns137 0 10866.227104 +Ra138 ns138 0 10866.227104 +Ga137 ns137 0 ns138 0 0.00195075799473 +Ga138 ns138 0 ns137 0 -0.00195075799473 +Ca139 ns139 0 1e-012 +Ca140 ns140 0 1e-012 +Ra139 ns139 0 1536.49223219 +Ra140 ns140 0 1536.49223219 +Ga139 ns139 0 ns140 0 0.00192521311741 +Ga140 ns140 0 ns139 0 -0.00192521311741 +Ca141 ns141 0 1e-012 +Ca142 ns142 0 1e-012 +Ra141 ns141 0 2025.51403767 +Ra142 ns142 0 2025.51403767 +Ga141 ns141 0 ns142 0 0.00215175337384 +Ga142 ns142 0 ns141 0 -0.00215175337384 +Ca143 ns143 0 1e-012 +Ca144 ns144 0 1e-012 +Ra143 ns143 0 5295.98860587 +Ra144 ns144 0 5295.98860587 +Ga143 ns143 0 ns144 0 -0.00260845931481 +Ga144 ns144 0 ns143 0 0.00260845931481 +Ca145 ns145 0 1e-012 +Ca146 ns146 0 1e-012 +Ra145 ns145 0 1371.66069475 +Ra146 ns146 0 1371.66069475 +Ga145 ns145 0 ns146 0 -0.00263050707209 +Ga146 ns146 0 ns145 0 0.00263050707209 +Ca147 ns147 0 1e-012 +Ca148 ns148 0 1e-012 +Ra147 ns147 0 2110.44338255 +Ra148 ns148 0 2110.44338255 +Ga147 ns147 0 ns148 0 0.00335743763387 +Ga148 ns148 0 ns147 0 -0.00335743763387 +Ca149 ns149 0 1e-012 +Ra149 ns149 0 262410420.914 +Ca150 ns150 0 1e-012 +Ra150 ns150 0 16360593.1152 +Ca151 ns151 0 1e-012 +Ra151 ns151 0 7450187.22211 +Ca152 ns152 0 1e-012 +Ra152 ns152 0 482889.219939 +Ca153 ns153 0 1e-012 +Ca154 ns154 0 1e-012 +Ra153 ns153 0 3178807.98814 +Ra154 ns154 0 3178807.98814 +Ga153 ns153 0 ns154 0 -8.05370424866e-006 +Ga154 ns154 0 ns153 0 8.05370424866e-006 +Ca155 ns155 0 1e-012 +Ra155 ns155 0 78592.2262071 +Ca156 ns156 0 1e-012 +Ra156 ns156 0 26063.5943057 +Ca157 ns157 0 1e-012 +Ca158 ns158 0 1e-012 +Ra157 ns157 0 18032.7608079 +Ra158 ns158 0 18032.7608079 +Ga157 ns157 0 ns158 0 5.67204692722e-006 +Ga158 ns158 0 ns157 0 -5.67204692722e-006 +Ca159 ns159 0 1e-012 +Ra159 ns159 0 2475.71988514 +Ca160 ns160 0 1e-012 +Ca161 ns161 0 1e-012 +Ra160 ns160 0 4595.59837407 +Ra161 ns161 0 4595.59837407 +Ga160 ns160 0 ns161 0 0.000715150699712 +Ga161 ns161 0 ns160 0 -0.000715150699712 +Ca162 ns162 0 1e-012 +Ca163 ns163 0 1e-012 +Ra162 ns162 0 3821.80080974 +Ra163 ns163 0 3821.80080974 +Ga162 ns162 0 ns163 0 0.000731480112776 +Ga163 ns163 0 ns162 0 -0.000731480112776 +Ca164 ns164 0 1e-012 +Ca165 ns165 0 1e-012 +Ra164 ns164 0 38119.6325933 +Ra165 ns165 0 38119.6325933 +Ga164 ns164 0 ns165 0 0.000800833624449 +Ga165 ns165 0 ns164 0 -0.000800833624449 +Ca166 ns166 0 1e-012 +Ca167 ns167 0 1e-012 +Ra166 ns166 0 27657.3095937 +Ra167 ns167 0 27657.3095937 +Ga166 ns166 0 ns167 0 0.000990021424588 +Ga167 ns167 0 ns166 0 -0.000990021424588 +Ca168 ns168 0 1e-012 +Ca169 ns169 0 1e-012 +Ra168 ns168 0 1021.84714331 +Ra169 ns169 0 1021.84714331 +Ga168 ns168 0 ns169 0 -0.000575085083328 +Ga169 ns169 0 ns168 0 0.000575085083328 +Ca170 ns170 0 1e-012 +Ca171 ns171 0 1e-012 +Ra170 ns170 0 4576.16665122 +Ra171 ns171 0 4576.16665122 +Ga170 ns170 0 ns171 0 0.00137480973644 +Ga171 ns171 0 ns170 0 -0.00137480973644 +Ca172 ns172 0 1e-012 +Ca173 ns173 0 1e-012 +Ra172 ns172 0 24419.9145383 +Ra173 ns173 0 24419.9145383 +Ga172 ns172 0 ns173 0 0.00143622065148 +Ga173 ns173 0 ns172 0 -0.00143622065148 +Ca174 ns174 0 1e-012 +Ca175 ns175 0 1e-012 +Ra174 ns174 0 10866.227104 +Ra175 ns175 0 10866.227104 +Ga174 ns174 0 ns175 0 0.00195075799473 +Ga175 ns175 0 ns174 0 -0.00195075799473 +Ca176 ns176 0 1e-012 +Ca177 ns177 0 1e-012 +Ra176 ns176 0 1536.49223219 +Ra177 ns177 0 1536.49223219 +Ga176 ns176 0 ns177 0 0.00192521311741 +Ga177 ns177 0 ns176 0 -0.00192521311741 +Ca178 ns178 0 1e-012 +Ca179 ns179 0 1e-012 +Ra178 ns178 0 2025.51403767 +Ra179 ns179 0 2025.51403767 +Ga178 ns178 0 ns179 0 0.00215175337384 +Ga179 ns179 0 ns178 0 -0.00215175337384 +Ca180 ns180 0 1e-012 +Ca181 ns181 0 1e-012 +Ra180 ns180 0 5295.98860587 +Ra181 ns181 0 5295.98860587 +Ga180 ns180 0 ns181 0 -0.00260845931481 +Ga181 ns181 0 ns180 0 0.00260845931481 +Ca182 ns182 0 1e-012 +Ca183 ns183 0 1e-012 +Ra182 ns182 0 1371.66069475 +Ra183 ns183 0 1371.66069475 +Ga182 ns182 0 ns183 0 -0.00263050707209 +Ga183 ns183 0 ns182 0 0.00263050707209 +Ca184 ns184 0 1e-012 +Ca185 ns185 0 1e-012 +Ra184 ns184 0 2110.44338255 +Ra185 ns185 0 2110.44338255 +Ga184 ns184 0 ns185 0 0.00335743763387 +Ga185 ns185 0 ns184 0 -0.00335743763387 +Ca186 ns186 0 1e-012 +Ra186 ns186 0 262410420.914 +Ca187 ns187 0 1e-012 +Ra187 ns187 0 16360593.1152 +Ca188 ns188 0 1e-012 +Ra188 ns188 0 7450187.22211 +Ca189 ns189 0 1e-012 +Ra189 ns189 0 482889.219939 +Ca190 ns190 0 1e-012 +Ca191 ns191 0 1e-012 +Ra190 ns190 0 3178807.98814 +Ra191 ns191 0 3178807.98814 +Ga190 ns190 0 ns191 0 -8.05370424866e-006 +Ga191 ns191 0 ns190 0 8.05370424866e-006 +Ca192 ns192 0 1e-012 +Ra192 ns192 0 78592.2262071 +Ca193 ns193 0 1e-012 +Ra193 ns193 0 26063.5943057 +Ca194 ns194 0 1e-012 +Ca195 ns195 0 1e-012 +Ra194 ns194 0 18032.7608079 +Ra195 ns195 0 18032.7608079 +Ga194 ns194 0 ns195 0 5.67204692722e-006 +Ga195 ns195 0 ns194 0 -5.67204692722e-006 +Ca196 ns196 0 1e-012 +Ra196 ns196 0 2475.71988514 +Ca197 ns197 0 1e-012 +Ca198 ns198 0 1e-012 +Ra197 ns197 0 4595.59837407 +Ra198 ns198 0 4595.59837407 +Ga197 ns197 0 ns198 0 0.000715150699712 +Ga198 ns198 0 ns197 0 -0.000715150699712 +Ca199 ns199 0 1e-012 +Ca200 ns200 0 1e-012 +Ra199 ns199 0 3821.80080974 +Ra200 ns200 0 3821.80080974 +Ga199 ns199 0 ns200 0 0.000731480112776 +Ga200 ns200 0 ns199 0 -0.000731480112776 +Ca201 ns201 0 1e-012 +Ca202 ns202 0 1e-012 +Ra201 ns201 0 38119.6325933 +Ra202 ns202 0 38119.6325933 +Ga201 ns201 0 ns202 0 0.000800833624449 +Ga202 ns202 0 ns201 0 -0.000800833624449 +Ca203 ns203 0 1e-012 +Ca204 ns204 0 1e-012 +Ra203 ns203 0 27657.3095937 +Ra204 ns204 0 27657.3095937 +Ga203 ns203 0 ns204 0 0.000990021424588 +Ga204 ns204 0 ns203 0 -0.000990021424588 +Ca205 ns205 0 1e-012 +Ca206 ns206 0 1e-012 +Ra205 ns205 0 1021.84714331 +Ra206 ns206 0 1021.84714331 +Ga205 ns205 0 ns206 0 -0.000575085083328 +Ga206 ns206 0 ns205 0 0.000575085083328 +Ca207 ns207 0 1e-012 +Ca208 ns208 0 1e-012 +Ra207 ns207 0 4576.16665122 +Ra208 ns208 0 4576.16665122 +Ga207 ns207 0 ns208 0 0.00137480973644 +Ga208 ns208 0 ns207 0 -0.00137480973644 +Ca209 ns209 0 1e-012 +Ca210 ns210 0 1e-012 +Ra209 ns209 0 24419.9145383 +Ra210 ns210 0 24419.9145383 +Ga209 ns209 0 ns210 0 0.00143622065148 +Ga210 ns210 0 ns209 0 -0.00143622065148 +Ca211 ns211 0 1e-012 +Ca212 ns212 0 1e-012 +Ra211 ns211 0 10866.227104 +Ra212 ns212 0 10866.227104 +Ga211 ns211 0 ns212 0 0.00195075799473 +Ga212 ns212 0 ns211 0 -0.00195075799473 +Ca213 ns213 0 1e-012 +Ca214 ns214 0 1e-012 +Ra213 ns213 0 1536.49223219 +Ra214 ns214 0 1536.49223219 +Ga213 ns213 0 ns214 0 0.00192521311741 +Ga214 ns214 0 ns213 0 -0.00192521311741 +Ca215 ns215 0 1e-012 +Ca216 ns216 0 1e-012 +Ra215 ns215 0 2025.51403767 +Ra216 ns216 0 2025.51403767 +Ga215 ns215 0 ns216 0 0.00215175337384 +Ga216 ns216 0 ns215 0 -0.00215175337384 +Ca217 ns217 0 1e-012 +Ca218 ns218 0 1e-012 +Ra217 ns217 0 5295.98860587 +Ra218 ns218 0 5295.98860587 +Ga217 ns217 0 ns218 0 -0.00260845931481 +Ga218 ns218 0 ns217 0 0.00260845931481 +Ca219 ns219 0 1e-012 +Ca220 ns220 0 1e-012 +Ra219 ns219 0 1371.66069475 +Ra220 ns220 0 1371.66069475 +Ga219 ns219 0 ns220 0 -0.00263050707209 +Ga220 ns220 0 ns219 0 0.00263050707209 +Ca221 ns221 0 1e-012 +Ca222 ns222 0 1e-012 +Ra221 ns221 0 2110.44338255 +Ra222 ns222 0 2110.44338255 +Ga221 ns221 0 ns222 0 0.00335743763387 +Ga222 ns222 0 ns221 0 -0.00335743763387 + +Gb1_1 ns1 0 ni1 0 3.81082426726e-009 +Gb2_1 ns2 0 ni1 0 6.11224784432e-008 +Gb3_1 ns3 0 ni1 0 1.34224814785e-007 +Gb4_1 ns4 0 ni1 0 2.07086834559e-006 +Gb5_1 ns5 0 ni1 0 8.06599209385e-006 +Gb7_1 ns7 0 ni1 0 1.27239047456e-005 +Gb8_1 ns8 0 ni1 0 3.83676935832e-005 +Gb9_1 ns9 0 ni1 0 5.60347777266e-005 +Gb11_1 ns11 0 ni1 0 0.000403922917936 +Gb12_1 ns12 0 ni1 0 0.000781359893234 +Gb14_1 ns14 0 ni1 0 0.000825076994629 +Gb16_1 ns16 0 ni1 0 0.000801692955072 +Gb18_1 ns18 0 ni1 0 0.000991341915889 +Gb20_1 ns20 0 ni1 0 0.00131656815235 +Gb22_1 ns22 0 ni1 0 0.00140954365144 +Gb24_1 ns24 0 ni1 0 0.00143738824198 +Gb26_1 ns26 0 ni1 0 0.00195509948718 +Gb28_1 ns28 0 ni1 0 0.00214523225089 +Gb30_1 ns30 0 ni1 0 0.00226502913593 +Gb32_1 ns32 0 ni1 0 0.00262212784602 +Gb34_1 ns34 0 ni1 0 0.00283256092591 +Gb36_1 ns36 0 ni1 0 0.00342430968348 +Gb38_2 ns38 0 ni2 0 3.81082426726e-009 +Gb39_2 ns39 0 ni2 0 6.11224784432e-008 +Gb40_2 ns40 0 ni2 0 1.34224814785e-007 +Gb41_2 ns41 0 ni2 0 2.07086834559e-006 +Gb42_2 ns42 0 ni2 0 8.06599209385e-006 +Gb44_2 ns44 0 ni2 0 1.27239047456e-005 +Gb45_2 ns45 0 ni2 0 3.83676935832e-005 +Gb46_2 ns46 0 ni2 0 5.60347777266e-005 +Gb48_2 ns48 0 ni2 0 0.000403922917936 +Gb49_2 ns49 0 ni2 0 0.000781359893234 +Gb51_2 ns51 0 ni2 0 0.000825076994629 +Gb53_2 ns53 0 ni2 0 0.000801692955072 +Gb55_2 ns55 0 ni2 0 0.000991341915889 +Gb57_2 ns57 0 ni2 0 0.00131656815235 +Gb59_2 ns59 0 ni2 0 0.00140954365144 +Gb61_2 ns61 0 ni2 0 0.00143738824198 +Gb63_2 ns63 0 ni2 0 0.00195509948718 +Gb65_2 ns65 0 ni2 0 0.00214523225089 +Gb67_2 ns67 0 ni2 0 0.00226502913593 +Gb69_2 ns69 0 ni2 0 0.00262212784602 +Gb71_2 ns71 0 ni2 0 0.00283256092591 +Gb73_2 ns73 0 ni2 0 0.00342430968348 +Gb75_3 ns75 0 ni3 0 3.81082426726e-009 +Gb76_3 ns76 0 ni3 0 6.11224784432e-008 +Gb77_3 ns77 0 ni3 0 1.34224814785e-007 +Gb78_3 ns78 0 ni3 0 2.07086834559e-006 +Gb79_3 ns79 0 ni3 0 8.06599209385e-006 +Gb81_3 ns81 0 ni3 0 1.27239047456e-005 +Gb82_3 ns82 0 ni3 0 3.83676935832e-005 +Gb83_3 ns83 0 ni3 0 5.60347777266e-005 +Gb85_3 ns85 0 ni3 0 0.000403922917936 +Gb86_3 ns86 0 ni3 0 0.000781359893234 +Gb88_3 ns88 0 ni3 0 0.000825076994629 +Gb90_3 ns90 0 ni3 0 0.000801692955072 +Gb92_3 ns92 0 ni3 0 0.000991341915889 +Gb94_3 ns94 0 ni3 0 0.00131656815235 +Gb96_3 ns96 0 ni3 0 0.00140954365144 +Gb98_3 ns98 0 ni3 0 0.00143738824198 +Gb100_3 ns100 0 ni3 0 0.00195509948718 +Gb102_3 ns102 0 ni3 0 0.00214523225089 +Gb104_3 ns104 0 ni3 0 0.00226502913593 +Gb106_3 ns106 0 ni3 0 0.00262212784602 +Gb108_3 ns108 0 ni3 0 0.00283256092591 +Gb110_3 ns110 0 ni3 0 0.00342430968348 +Gb112_4 ns112 0 ni4 0 3.81082426726e-009 +Gb113_4 ns113 0 ni4 0 6.11224784432e-008 +Gb114_4 ns114 0 ni4 0 1.34224814785e-007 +Gb115_4 ns115 0 ni4 0 2.07086834559e-006 +Gb116_4 ns116 0 ni4 0 8.06599209385e-006 +Gb118_4 ns118 0 ni4 0 1.27239047456e-005 +Gb119_4 ns119 0 ni4 0 3.83676935832e-005 +Gb120_4 ns120 0 ni4 0 5.60347777266e-005 +Gb122_4 ns122 0 ni4 0 0.000403922917936 +Gb123_4 ns123 0 ni4 0 0.000781359893234 +Gb125_4 ns125 0 ni4 0 0.000825076994629 +Gb127_4 ns127 0 ni4 0 0.000801692955072 +Gb129_4 ns129 0 ni4 0 0.000991341915889 +Gb131_4 ns131 0 ni4 0 0.00131656815235 +Gb133_4 ns133 0 ni4 0 0.00140954365144 +Gb135_4 ns135 0 ni4 0 0.00143738824198 +Gb137_4 ns137 0 ni4 0 0.00195509948718 +Gb139_4 ns139 0 ni4 0 0.00214523225089 +Gb141_4 ns141 0 ni4 0 0.00226502913593 +Gb143_4 ns143 0 ni4 0 0.00262212784602 +Gb145_4 ns145 0 ni4 0 0.00283256092591 +Gb147_4 ns147 0 ni4 0 0.00342430968348 +Gb149_5 ns149 0 ni5 0 3.81082426726e-009 +Gb150_5 ns150 0 ni5 0 6.11224784432e-008 +Gb151_5 ns151 0 ni5 0 1.34224814785e-007 +Gb152_5 ns152 0 ni5 0 2.07086834559e-006 +Gb153_5 ns153 0 ni5 0 8.06599209385e-006 +Gb155_5 ns155 0 ni5 0 1.27239047456e-005 +Gb156_5 ns156 0 ni5 0 3.83676935832e-005 +Gb157_5 ns157 0 ni5 0 5.60347777266e-005 +Gb159_5 ns159 0 ni5 0 0.000403922917936 +Gb160_5 ns160 0 ni5 0 0.000781359893234 +Gb162_5 ns162 0 ni5 0 0.000825076994629 +Gb164_5 ns164 0 ni5 0 0.000801692955072 +Gb166_5 ns166 0 ni5 0 0.000991341915889 +Gb168_5 ns168 0 ni5 0 0.00131656815235 +Gb170_5 ns170 0 ni5 0 0.00140954365144 +Gb172_5 ns172 0 ni5 0 0.00143738824198 +Gb174_5 ns174 0 ni5 0 0.00195509948718 +Gb176_5 ns176 0 ni5 0 0.00214523225089 +Gb178_5 ns178 0 ni5 0 0.00226502913593 +Gb180_5 ns180 0 ni5 0 0.00262212784602 +Gb182_5 ns182 0 ni5 0 0.00283256092591 +Gb184_5 ns184 0 ni5 0 0.00342430968348 +Gb186_6 ns186 0 ni6 0 3.81082426726e-009 +Gb187_6 ns187 0 ni6 0 6.11224784432e-008 +Gb188_6 ns188 0 ni6 0 1.34224814785e-007 +Gb189_6 ns189 0 ni6 0 2.07086834559e-006 +Gb190_6 ns190 0 ni6 0 8.06599209385e-006 +Gb192_6 ns192 0 ni6 0 1.27239047456e-005 +Gb193_6 ns193 0 ni6 0 3.83676935832e-005 +Gb194_6 ns194 0 ni6 0 5.60347777266e-005 +Gb196_6 ns196 0 ni6 0 0.000403922917936 +Gb197_6 ns197 0 ni6 0 0.000781359893234 +Gb199_6 ns199 0 ni6 0 0.000825076994629 +Gb201_6 ns201 0 ni6 0 0.000801692955072 +Gb203_6 ns203 0 ni6 0 0.000991341915889 +Gb205_6 ns205 0 ni6 0 0.00131656815235 +Gb207_6 ns207 0 ni6 0 0.00140954365144 +Gb209_6 ns209 0 ni6 0 0.00143738824198 +Gb211_6 ns211 0 ni6 0 0.00195509948718 +Gb213_6 ns213 0 ni6 0 0.00214523225089 +Gb215_6 ns215 0 ni6 0 0.00226502913593 +Gb217_6 ns217 0 ni6 0 0.00262212784602 +Gb219_6 ns219 0 ni6 0 0.00283256092591 +Gb221_6 ns221 0 ni6 0 0.00342430968348 + +Gc1_1 0 n2 ns1 0 -0.00268792802339 +Gc1_2 0 n2 ns2 0 0.00671366569136 +Gc1_3 0 n2 ns3 0 0.00032391817683 +Gc1_4 0 n2 ns4 0 -6.56353922054e-005 +Gc1_5 0 n2 ns5 0 -1.1118850257e-007 +Gc1_6 0 n2 ns6 0 9.76400208191e-008 +Gc1_7 0 n2 ns7 0 -7.98144541697e-005 +Gc1_8 0 n2 ns8 0 0.00301899578807 +Gc1_9 0 n2 ns9 0 0.00924630689709 +Gc1_10 0 n2 ns10 0 0.0148235837462 +Gc1_11 0 n2 ns11 0 -0.00268813007828 +Gc1_12 0 n2 ns12 0 0.00114256205737 +Gc1_13 0 n2 ns13 0 0.000999021353099 +Gc1_14 0 n2 ns14 0 0.00405001826403 +Gc1_15 0 n2 ns15 0 0.00164398567597 +Gc1_16 0 n2 ns16 0 -9.34259066281e-007 +Gc1_17 0 n2 ns17 0 -1.72614091976e-006 +Gc1_18 0 n2 ns18 0 2.92573043656e-008 +Gc1_19 0 n2 ns19 0 3.86775973054e-006 +Gc1_20 0 n2 ns20 0 -0.0304145364827 +Gc1_21 0 n2 ns21 0 0.0110979600399 +Gc1_22 0 n2 ns22 0 7.86107796528e-006 +Gc1_23 0 n2 ns23 0 0.000242551373302 +Gc1_24 0 n2 ns24 0 -3.34457130796e-006 +Gc1_25 0 n2 ns25 0 -9.65238957685e-007 +Gc1_26 0 n2 ns26 0 -7.91036616312e-006 +Gc1_27 0 n2 ns27 0 -1.34127097283e-006 +Gc1_28 0 n2 ns28 0 0.00476226479876 +Gc1_29 0 n2 ns29 0 0.00524725708637 +Gc1_30 0 n2 ns30 0 -0.00228803174176 +Gc1_31 0 n2 ns31 0 0.00110759276833 +Gc1_32 0 n2 ns32 0 2.16159474558e-005 +Gc1_33 0 n2 ns33 0 4.65092954895e-005 +Gc1_34 0 n2 ns34 0 0.00653382407595 +Gc1_35 0 n2 ns35 0 -0.00373479153037 +Gc1_36 0 n2 ns36 0 -0.00060158633485 +Gc1_37 0 n2 ns37 0 0.00125947060143 +Gc1_38 0 n2 ns38 0 -0.00300520733361 +Gc1_39 0 n2 ns39 0 0.0066359732532 +Gc1_40 0 n2 ns40 0 0.000362183824274 +Gc1_41 0 n2 ns41 0 -7.07319188315e-005 +Gc1_42 0 n2 ns42 0 -7.03700310341e-008 +Gc1_43 0 n2 ns43 0 -5.01616014745e-007 +Gc1_44 0 n2 ns44 0 -0.000156699581679 +Gc1_45 0 n2 ns45 0 -0.001682747332 +Gc1_46 0 n2 ns46 0 -0.00442279404381 +Gc1_47 0 n2 ns47 0 -0.00780597772885 +Gc1_48 0 n2 ns48 0 0.000153971046865 +Gc1_49 0 n2 ns49 0 -0.000346529633733 +Gc1_50 0 n2 ns50 0 -0.00114553752917 +Gc1_51 0 n2 ns51 0 -0.00255296082326 +Gc1_52 0 n2 ns52 0 0.000220730475541 +Gc1_53 0 n2 ns53 0 -2.18487511926e-006 +Gc1_54 0 n2 ns54 0 1.53704525761e-007 +Gc1_55 0 n2 ns55 0 9.25503635633e-007 +Gc1_56 0 n2 ns56 0 6.01749839765e-007 +Gc1_57 0 n2 ns57 0 0.000894840172896 +Gc1_58 0 n2 ns58 0 -7.17821174688e-005 +Gc1_59 0 n2 ns59 0 -8.79995806712e-005 +Gc1_60 0 n2 ns60 0 0.000349186163994 +Gc1_61 0 n2 ns61 0 5.2399387606e-007 +Gc1_62 0 n2 ns62 0 -1.05465961387e-006 +Gc1_63 0 n2 ns63 0 -1.68912830935e-007 +Gc1_64 0 n2 ns64 0 1.88966552652e-006 +Gc1_65 0 n2 ns65 0 -0.00101339774713 +Gc1_66 0 n2 ns66 0 0.00176240460199 +Gc1_67 0 n2 ns67 0 0.000805383827027 +Gc1_68 0 n2 ns68 0 -0.00116685044405 +Gc1_69 0 n2 ns69 0 -9.19048099285e-006 +Gc1_70 0 n2 ns70 0 -4.35210445062e-006 +Gc1_71 0 n2 ns71 0 -0.000399234283178 +Gc1_72 0 n2 ns72 0 0.000602569776437 +Gc1_73 0 n2 ns73 0 0.000429482257978 +Gc1_74 0 n2 ns74 0 0.00114627454589 +Gc1_75 0 n2 ns75 0 -0.00297563091288 +Gc1_76 0 n2 ns76 0 0.00661318808099 +Gc1_77 0 n2 ns77 0 0.000371613447976 +Gc1_78 0 n2 ns78 0 -7.00616128473e-005 +Gc1_79 0 n2 ns79 0 -1.35901328978e-007 +Gc1_80 0 n2 ns80 0 -5.24325454604e-007 +Gc1_81 0 n2 ns81 0 -0.000167524072503 +Gc1_82 0 n2 ns82 0 -0.000613297165699 +Gc1_83 0 n2 ns83 0 -0.00560834132187 +Gc1_84 0 n2 ns84 0 -0.0069653566938 +Gc1_85 0 n2 ns85 0 0.000287258846565 +Gc1_86 0 n2 ns86 0 -0.000553693092188 +Gc1_87 0 n2 ns87 0 -0.00112038858341 +Gc1_88 0 n2 ns88 0 -0.00210594473599 +Gc1_89 0 n2 ns89 0 0.000168452972916 +Gc1_90 0 n2 ns90 0 -1.39673287315e-006 +Gc1_91 0 n2 ns91 0 -7.28523538727e-007 +Gc1_92 0 n2 ns92 0 1.16407641976e-007 +Gc1_93 0 n2 ns93 0 9.77164472015e-007 +Gc1_94 0 n2 ns94 0 0.0023263846639 +Gc1_95 0 n2 ns95 0 0.000520960663766 +Gc1_96 0 n2 ns96 0 -6.13586566756e-005 +Gc1_97 0 n2 ns97 0 0.000241359723582 +Gc1_98 0 n2 ns98 0 -4.72534592029e-007 +Gc1_99 0 n2 ns99 0 -6.23224221574e-007 +Gc1_100 0 n2 ns100 0 -3.41844133705e-006 +Gc1_101 0 n2 ns101 0 2.308581875e-006 +Gc1_102 0 n2 ns102 0 -0.000730542916641 +Gc1_103 0 n2 ns103 0 0.000527528360772 +Gc1_104 0 n2 ns104 0 0.000542875742674 +Gc1_105 0 n2 ns105 0 -0.000496561740724 +Gc1_106 0 n2 ns106 0 -7.26111233952e-006 +Gc1_107 0 n2 ns107 0 -5.02446377323e-006 +Gc1_108 0 n2 ns108 0 -0.000432760416925 +Gc1_109 0 n2 ns109 0 0.00109808985573 +Gc1_110 0 n2 ns110 0 0.000203132876631 +Gc1_111 0 n2 ns111 0 0.00118594860676 +Gc1_112 0 n2 ns112 0 0.00294934771636 +Gc1_113 0 n2 ns113 0 -0.00660703424956 +Gc1_114 0 n2 ns114 0 -0.00037338417768 +Gc1_115 0 n2 ns115 0 7.07762921095e-005 +Gc1_116 0 n2 ns116 0 1.76052725183e-007 +Gc1_117 0 n2 ns117 0 7.30223496784e-007 +Gc1_118 0 n2 ns118 0 0.000169174943827 +Gc1_119 0 n2 ns119 0 0.000665732982467 +Gc1_120 0 n2 ns120 0 0.00565829805658 +Gc1_121 0 n2 ns121 0 0.00677801542963 +Gc1_122 0 n2 ns122 0 -8.70739854449e-006 +Gc1_123 0 n2 ns123 0 -0.000549369291487 +Gc1_124 0 n2 ns124 0 -0.000618258962289 +Gc1_125 0 n2 ns125 0 -0.00132606110426 +Gc1_126 0 n2 ns126 0 0.000510017286132 +Gc1_127 0 n2 ns127 0 -1.22663225527e-006 +Gc1_128 0 n2 ns128 0 -2.75505987862e-007 +Gc1_129 0 n2 ns129 0 2.12259740702e-007 +Gc1_130 0 n2 ns130 0 5.05921742189e-007 +Gc1_131 0 n2 ns131 0 0.00183728851338 +Gc1_132 0 n2 ns132 0 0.000265874734433 +Gc1_133 0 n2 ns133 0 0.000116525477943 +Gc1_134 0 n2 ns134 0 -8.69382103369e-005 +Gc1_135 0 n2 ns135 0 -2.69067249012e-006 +Gc1_136 0 n2 ns136 0 -1.53852746359e-007 +Gc1_137 0 n2 ns137 0 -2.89299331247e-006 +Gc1_138 0 n2 ns138 0 3.84191519068e-006 +Gc1_139 0 n2 ns139 0 0.00022856628352 +Gc1_140 0 n2 ns140 0 -7.17731529906e-005 +Gc1_141 0 n2 ns141 0 -0.00115574728922 +Gc1_142 0 n2 ns142 0 6.58415539011e-005 +Gc1_143 0 n2 ns143 0 -2.32859531808e-006 +Gc1_144 0 n2 ns144 0 -6.07917188929e-006 +Gc1_145 0 n2 ns145 0 0.00152645300362 +Gc1_146 0 n2 ns146 0 0.00175988493554 +Gc1_147 0 n2 ns147 0 0.000366304696634 +Gc1_148 0 n2 ns148 0 0.000478716307208 +Gc1_149 0 n2 ns149 0 0.0029609096314 +Gc1_150 0 n2 ns150 0 -0.00662927535332 +Gc1_151 0 n2 ns151 0 -0.000363573171887 +Gc1_152 0 n2 ns152 0 7.11243975991e-005 +Gc1_153 0 n2 ns153 0 1.33138965737e-007 +Gc1_154 0 n2 ns154 0 7.17048386968e-007 +Gc1_155 0 n2 ns155 0 0.000160438210333 +Gc1_156 0 n2 ns156 0 0.00174378488298 +Gc1_157 0 n2 ns157 0 0.00440774153721 +Gc1_158 0 n2 ns158 0 0.00736467541946 +Gc1_159 0 n2 ns159 0 -0.000288970452394 +Gc1_160 0 n2 ns160 0 -0.000257568338819 +Gc1_161 0 n2 ns161 0 -0.00142863926715 +Gc1_162 0 n2 ns162 0 -0.00276043712414 +Gc1_163 0 n2 ns163 0 -0.000842502684506 +Gc1_164 0 n2 ns164 0 -2.29908153835e-006 +Gc1_165 0 n2 ns165 0 1.15485474791e-007 +Gc1_166 0 n2 ns166 0 1.43360867903e-006 +Gc1_167 0 n2 ns167 0 1.1455167488e-008 +Gc1_168 0 n2 ns168 0 0.00236863766034 +Gc1_169 0 n2 ns169 0 -0.00301934583119 +Gc1_170 0 n2 ns170 0 0.000111518998779 +Gc1_171 0 n2 ns171 0 -1.57703462929e-005 +Gc1_172 0 n2 ns172 0 7.833017454e-007 +Gc1_173 0 n2 ns173 0 -2.6570478735e-007 +Gc1_174 0 n2 ns174 0 4.09149547351e-006 +Gc1_175 0 n2 ns175 0 3.67650593241e-006 +Gc1_176 0 n2 ns176 0 3.54115457345e-005 +Gc1_177 0 n2 ns177 0 -0.00119479357704 +Gc1_178 0 n2 ns178 0 -0.00115551574658 +Gc1_179 0 n2 ns179 0 0.000838984694159 +Gc1_180 0 n2 ns180 0 -2.98273542374e-006 +Gc1_181 0 n2 ns181 0 1.58097970246e-006 +Gc1_182 0 n2 ns182 0 0.00130336402075 +Gc1_183 0 n2 ns183 0 0.00147446322322 +Gc1_184 0 n2 ns184 0 0.000131865305283 +Gc1_185 0 n2 ns185 0 0.00107708268847 +Gc1_186 0 n2 ns186 0 0.00305284300486 +Gc1_187 0 n2 ns187 0 -0.00648684587219 +Gc1_188 0 n2 ns188 0 -0.000462732734491 +Gc1_189 0 n2 ns189 0 2.53170267516e-005 +Gc1_190 0 n2 ns190 0 -2.19236179053e-009 +Gc1_191 0 n2 ns191 0 -4.29734185224e-007 +Gc1_192 0 n2 ns192 0 7.69696633792e-005 +Gc1_193 0 n2 ns193 0 -0.00278808208043 +Gc1_194 0 n2 ns194 0 -0.00943322468666 +Gc1_195 0 n2 ns195 0 -0.0159332789091 +Gc1_196 0 n2 ns196 0 0.00158645343886 +Gc1_197 0 n2 ns197 0 0.000854571600485 +Gc1_198 0 n2 ns198 0 0.00140817786386 +Gc1_199 0 n2 ns199 0 0.00434740356592 +Gc1_200 0 n2 ns200 0 0.000983282489614 +Gc1_201 0 n2 ns201 0 -1.16534948113e-006 +Gc1_202 0 n2 ns202 0 5.62602872217e-008 +Gc1_203 0 n2 ns203 0 1.47776876153e-006 +Gc1_204 0 n2 ns204 0 4.61747968633e-007 +Gc1_205 0 n2 ns205 0 0.00246412725228 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0.000362754014766 +Gc2_4 0 n4 ns4 0 -7.09830260591e-005 +Gc2_5 0 n4 ns5 0 -5.31865263292e-008 +Gc2_6 0 n4 ns6 0 -4.94171437314e-007 +Gc2_7 0 n4 ns7 0 -0.000156502149753 +Gc2_8 0 n4 ns8 0 -0.00166803277287 +Gc2_9 0 n4 ns9 0 -0.00442872923564 +Gc2_10 0 n4 ns10 0 -0.00786652421124 +Gc2_11 0 n4 ns11 0 0.000157342758723 +Gc2_12 0 n4 ns12 0 -0.000339223221253 +Gc2_13 0 n4 ns13 0 -0.00117270920175 +Gc2_14 0 n4 ns14 0 -0.00256610429671 +Gc2_15 0 n4 ns15 0 0.000259042188648 +Gc2_16 0 n4 ns16 0 -2.46814705601e-006 +Gc2_17 0 n4 ns17 0 8.51029533054e-008 +Gc2_18 0 n4 ns18 0 1.08068590646e-006 +Gc2_19 0 n4 ns19 0 7.80167692148e-007 +Gc2_20 0 n4 ns20 0 0.000917552440801 +Gc2_21 0 n4 ns21 0 -2.88614813546e-005 +Gc2_22 0 n4 ns22 0 -8.91186414378e-005 +Gc2_23 0 n4 ns23 0 0.000351357245326 +Gc2_24 0 n4 ns24 0 5.68132055888e-007 +Gc2_25 0 n4 ns25 0 -1.12051409698e-006 +Gc2_26 0 n4 ns26 0 3.01196422744e-007 +Gc2_27 0 n4 ns27 0 1.98246329955e-006 +Gc2_28 0 n4 ns28 0 -0.000989774172418 +Gc2_29 0 n4 ns29 0 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-0.000160084872409 +Gc2_82 0 n4 ns82 0 -0.000898917260765 +Gc2_83 0 n4 ns83 0 -0.0052872120744 +Gc2_84 0 n4 ns84 0 -0.00701019395599 +Gc2_85 0 n4 ns85 0 0.000303794208283 +Gc2_86 0 n4 ns86 0 -0.000443259135174 +Gc2_87 0 n4 ns87 0 -0.000173160240584 +Gc2_88 0 n4 ns88 0 -0.00231126524693 +Gc2_89 0 n4 ns89 0 -0.000731910610443 +Gc2_90 0 n4 ns90 0 -5.05854515308e-007 +Gc2_91 0 n4 ns91 0 -6.28084635588e-008 +Gc2_92 0 n4 ns92 0 4.22763998224e-007 +Gc2_93 0 n4 ns93 0 6.43587507362e-008 +Gc2_94 0 n4 ns94 0 0.00177286119348 +Gc2_95 0 n4 ns95 0 0.000630837029105 +Gc2_96 0 n4 ns96 0 -6.0477565394e-005 +Gc2_97 0 n4 ns97 0 0.000215789541545 +Gc2_98 0 n4 ns98 0 -2.03519385791e-007 +Gc2_99 0 n4 ns99 0 -9.48522624732e-008 +Gc2_100 0 n4 ns100 0 -8.34272871004e-007 +Gc2_101 0 n4 ns101 0 -4.29954702225e-008 +Gc2_102 0 n4 ns102 0 -0.00161177109055 +Gc2_103 0 n4 ns103 0 0.00159601744156 +Gc2_104 0 n4 ns104 0 0.00170133280046 +Gc2_105 0 n4 ns105 0 -0.00119762759949 +Gc2_106 0 n4 ns106 0 -5.69103870658e-006 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0.00304461076358 +Gc2_132 0 n4 ns132 0 -0.00144198293266 +Gc2_133 0 n4 ns133 0 9.39210939334e-005 +Gc2_134 0 n4 ns134 0 -6.17477031697e-005 +Gc2_135 0 n4 ns135 0 7.83369233805e-007 +Gc2_136 0 n4 ns136 0 1.68914508912e-008 +Gc2_137 0 n4 ns137 0 2.05469184967e-006 +Gc2_138 0 n4 ns138 0 3.06996547905e-006 +Gc2_139 0 n4 ns139 0 -0.00064661716482 +Gc2_140 0 n4 ns140 0 -0.00124929831939 +Gc2_141 0 n4 ns141 0 -0.000318188540117 +Gc2_142 0 n4 ns142 0 0.000295960658603 +Gc2_143 0 n4 ns143 0 -1.29742339425e-005 +Gc2_144 0 n4 ns144 0 -1.54736477173e-006 +Gc2_145 0 n4 ns145 0 0.00016989694549 +Gc2_146 0 n4 ns146 0 0.00109442273044 +Gc2_147 0 n4 ns147 0 0.000353612893946 +Gc2_148 0 n4 ns148 0 0.00135137725649 +Gc2_149 0 n4 ns149 0 0.0029997515931 +Gc2_150 0 n4 ns150 0 -0.00656802492625 +Gc2_151 0 n4 ns151 0 -0.000437960630836 +Gc2_152 0 n4 ns152 0 2.78617369076e-005 +Gc2_153 0 n4 ns153 0 -7.87712342506e-009 +Gc2_154 0 n4 ns154 0 -1.13221825504e-007 +Gc2_155 0 n4 ns155 0 8.01940058249e-005 +Gc2_156 0 n4 ns156 0 -0.00310569153 +Gc2_157 0 n4 ns157 0 -0.00908089822859 +Gc2_158 0 n4 ns158 0 -0.0163304935856 +Gc2_159 0 n4 ns159 0 0.00151223689395 +Gc2_160 0 n4 ns160 0 0.000514648948761 +Gc2_161 0 n4 ns161 0 0.00115586977867 +Gc2_162 0 n4 ns162 0 0.00471947692742 +Gc2_163 0 n4 ns163 0 0.00109823546139 +Gc2_164 0 n4 ns164 0 -1.69411885778e-006 +Gc2_165 0 n4 ns165 0 9.32097620007e-007 +Gc2_166 0 n4 ns166 0 1.70870916885e-006 +Gc2_167 0 n4 ns167 0 -8.40720394036e-007 +Gc2_168 0 n4 ns168 0 0.00339148861924 +Gc2_169 0 n4 ns169 0 -0.000923289029514 +Gc2_170 0 n4 ns170 0 0.000109514080607 +Gc2_171 0 n4 ns171 0 -9.95463682869e-006 +Gc2_172 0 n4 ns172 0 1.18320647153e-006 +Gc2_173 0 n4 ns173 0 -5.84579838916e-007 +Gc2_174 0 n4 ns174 0 9.34404678432e-006 +Gc2_175 0 n4 ns175 0 2.95296590213e-006 +Gc2_176 0 n4 ns176 0 -0.00042197901829 +Gc2_177 0 n4 ns177 0 -0.00980424454653 +Gc2_178 0 n4 ns178 0 0.0042035521713 +Gc2_179 0 n4 ns179 0 0.00194243399564 +Gc2_180 0 n4 ns180 0 1.23040675582e-005 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0.00178111665854 +Gc2_206 0 n4 ns206 0 0.00136755142014 +Gc2_207 0 n4 ns207 0 7.35758943573e-005 +Gc2_208 0 n4 ns208 0 5.22660312924e-005 +Gc2_209 0 n4 ns209 0 4.86634278903e-008 +Gc2_210 0 n4 ns210 0 -7.79234874914e-007 +Gc2_211 0 n4 ns211 0 3.37540401962e-006 +Gc2_212 0 n4 ns212 0 1.85378696697e-006 +Gc2_213 0 n4 ns213 0 -0.000918474857453 +Gc2_214 0 n4 ns214 0 -0.000185956702633 +Gc2_215 0 n4 ns215 0 -0.00020242575034 +Gc2_216 0 n4 ns216 0 0.000500658745882 +Gc2_217 0 n4 ns217 0 -2.12596211441e-007 +Gc2_218 0 n4 ns218 0 -1.26677874269e-005 +Gc2_219 0 n4 ns219 0 0.000840249039577 +Gc2_220 0 n4 ns220 0 0.00147712515613 +Gc2_221 0 n4 ns221 0 0.000585210387501 +Gc2_222 0 n4 ns222 0 0.000590257646079 +Gd2_1 0 n4 ni1 0 -0.000100042133626 +Gd2_2 0 n4 ni2 0 -1.34950853209e-005 +Gd2_3 0 n4 ni3 0 -9.51505371057e-005 +Gd2_4 0 n4 ni4 0 0.000298793967482 +Gd2_5 0 n4 ni5 0 0.00133837435337 +Gd2_6 0 n4 ni6 0 0.000308358888514 +Gc3_1 0 n6 ns1 0 -0.00298776865331 +Gc3_2 0 n6 ns2 0 0.00661583197094 +Gc3_3 0 n6 ns3 0 0.000371653825861 +Gc3_4 0 n6 ns4 0 -6.9957265851e-005 +Gc3_5 0 n6 ns5 0 -1.29014781083e-007 +Gc3_6 0 n6 ns6 0 -5.22755556679e-007 +Gc3_7 0 n6 ns7 0 -0.000166860189958 +Gc3_8 0 n6 ns8 0 -0.000631235387595 +Gc3_9 0 n6 ns9 0 -0.00559511503724 +Gc3_10 0 n6 ns10 0 -0.006918311839 +Gc3_11 0 n6 ns11 0 0.000287985342253 +Gc3_12 0 n6 ns12 0 -0.000551651907351 +Gc3_13 0 n6 ns13 0 -0.0011129853858 +Gc3_14 0 n6 ns14 0 -0.00210766451038 +Gc3_15 0 n6 ns15 0 0.000161024840109 +Gc3_16 0 n6 ns16 0 -1.36012682759e-006 +Gc3_17 0 n6 ns17 0 -7.52045537084e-007 +Gc3_18 0 n6 ns18 0 1.26528565415e-007 +Gc3_19 0 n6 ns19 0 1.00517121505e-006 +Gc3_20 0 n6 ns20 0 0.00231768011717 +Gc3_21 0 n6 ns21 0 0.000516970759275 +Gc3_22 0 n6 ns22 0 -6.13400063837e-005 +Gc3_23 0 n6 ns23 0 0.000241118797671 +Gc3_24 0 n6 ns24 0 -5.28797565827e-007 +Gc3_25 0 n6 ns25 0 -5.91237755172e-007 +Gc3_26 0 n6 ns26 0 -3.14909249817e-006 +Gc3_27 0 n6 ns27 0 2.37311603204e-006 +Gc3_28 0 n6 ns28 0 -0.000730504567042 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+Gc4_180 0 n8 ns180 0 1.85000495622e-006 +Gc4_181 0 n8 ns181 0 6.31644960464e-006 +Gc4_182 0 n8 ns182 0 0.00165764988512 +Gc4_183 0 n8 ns183 0 0.00130147617115 +Gc4_184 0 n8 ns184 0 0.000504461571029 +Gc4_185 0 n8 ns185 0 0.00059518024076 +Gc4_186 0 n8 ns186 0 -0.00294173585503 +Gc4_187 0 n8 ns187 0 0.00660870209585 +Gc4_188 0 n8 ns188 0 0.000373850297195 +Gc4_189 0 n8 ns189 0 -6.89957972185e-005 +Gc4_190 0 n8 ns190 0 -2.34439581925e-007 +Gc4_191 0 n8 ns191 0 -5.74871755031e-007 +Gc4_192 0 n8 ns192 0 -0.000179120397691 +Gc4_193 0 n8 ns193 0 -0.000525253443308 +Gc4_194 0 n8 ns194 0 -0.00569409295924 +Gc4_195 0 n8 ns195 0 -0.00733511902694 +Gc4_196 0 n8 ns196 0 0.000295417245165 +Gc4_197 0 n8 ns197 0 -0.000784966763659 +Gc4_198 0 n8 ns198 0 -0.000947504250436 +Gc4_199 0 n8 ns199 0 -0.0014807915361 +Gc4_200 0 n8 ns200 0 -0.000298343640802 +Gc4_201 0 n8 ns201 0 -1.1157490807e-006 +Gc4_202 0 n8 ns202 0 -1.45983626524e-007 +Gc4_203 0 n8 ns203 0 5.75750282166e-007 +Gc4_204 0 n8 ns204 0 3.01584391508e-007 +Gc4_205 0 n8 ns205 0 0.00290536020147 +Gc4_206 0 n8 ns206 0 -0.00233582812718 +Gc4_207 0 n8 ns207 0 -3.5166243399e-005 +Gc4_208 0 n8 ns208 0 -4.28639773304e-005 +Gc4_209 0 n8 ns209 0 -1.33597376317e-006 +Gc4_210 0 n8 ns210 0 8.18988652191e-007 +Gc4_211 0 n8 ns211 0 -5.90501168511e-006 +Gc4_212 0 n8 ns212 0 4.12353533905e-006 +Gc4_213 0 n8 ns213 0 -8.83688855225e-005 +Gc4_214 0 n8 ns214 0 -0.000559576920155 +Gc4_215 0 n8 ns215 0 0.000377524644783 +Gc4_216 0 n8 ns216 0 -0.000375193254767 +Gc4_217 0 n8 ns217 0 -4.81456961851e-006 +Gc4_218 0 n8 ns218 0 9.69950617722e-006 +Gc4_219 0 n8 ns219 0 0.000196618693147 +Gc4_220 0 n8 ns220 0 0.00127601427316 +Gc4_221 0 n8 ns221 0 0.000505720368659 +Gc4_222 0 n8 ns222 0 0.000786287332371 +Gd4_1 0 n8 ni1 0 0.000520942067136 +Gd4_2 0 n8 ni2 0 0.00030923385615 +Gd4_3 0 n8 ni3 0 0.00133231652848 +Gd4_4 0 n8 ni4 0 -0.00249847086094 +Gd4_5 0 n8 ni5 0 0.000898910364352 +Gd4_6 0 n8 ni6 0 0.00064354656373 +Gc5_1 0 n10 ns1 0 0.0029468402715 +Gc5_2 0 n10 ns2 0 -0.00662902354546 +Gc5_3 0 n10 ns3 0 -0.000365776917515 +Gc5_4 0 n10 ns4 0 7.13802426282e-005 +Gc5_5 0 n10 ns5 0 7.88369501908e-008 +Gc5_6 0 n10 ns6 0 6.7005941842e-007 +Gc5_7 0 n10 ns7 0 0.00016086630808 +Gc5_8 0 n10 ns8 0 0.00165424362665 +Gc5_9 0 n10 ns9 0 0.00445357111929 +Gc5_10 0 n10 ns10 0 0.00774039618468 +Gc5_11 0 n10 ns11 0 -0.000257330598421 +Gc5_12 0 n10 ns12 0 -0.000307609401124 +Gc5_13 0 n10 ns13 0 -0.00143320285875 +Gc5_14 0 n10 ns14 0 -0.00269057164911 +Gc5_15 0 n10 ns15 0 -0.000830861755725 +Gc5_16 0 n10 ns16 0 -2.27694652272e-006 +Gc5_17 0 n10 ns17 0 3.57253355336e-007 +Gc5_18 0 n10 ns18 0 1.61990241e-006 +Gc5_19 0 n10 ns19 0 -9.62058186607e-008 +Gc5_20 0 n10 ns20 0 0.00229352835423 +Gc5_21 0 n10 ns21 0 -0.00303241846918 +Gc5_22 0 n10 ns22 0 0.000112983409162 +Gc5_23 0 n10 ns23 0 -1.19897396263e-005 +Gc5_24 0 n10 ns24 0 7.14791086525e-007 +Gc5_25 0 n10 ns25 0 -9.49436606922e-008 +Gc5_26 0 n10 ns26 0 2.02057067205e-006 +Gc5_27 0 n10 ns27 0 2.832468164e-006 +Gc5_28 0 n10 ns28 0 3.52953210187e-005 +Gc5_29 0 n10 ns29 0 -0.00119912674907 +Gc5_30 0 n10 ns30 0 -0.00116725270522 +Gc5_31 0 n10 ns31 0 0.000863586123898 +Gc5_32 0 n10 ns32 0 -1.90456648262e-006 +Gc5_33 0 n10 ns33 0 2.80027714123e-006 +Gc5_34 0 n10 ns34 0 0.00132847349344 +Gc5_35 0 n10 ns35 0 0.00146790300179 +Gc5_36 0 n10 ns36 0 0.000139204508198 +Gc5_37 0 n10 ns37 0 0.00107048610699 +Gc5_38 0 n10 ns38 0 0.00297129842896 +Gc5_39 0 n10 ns39 0 -0.00656356484334 +Gc5_40 0 n10 ns40 0 -0.000437974390939 +Gc5_41 0 n10 ns41 0 2.74087042715e-005 +Gc5_42 0 n10 ns42 0 8.15426020688e-008 +Gc5_43 0 n10 ns43 0 -6.2109337565e-008 +Gc5_44 0 n10 ns44 0 8.67914100901e-005 +Gc5_45 0 n10 ns45 0 -0.00303726676546 +Gc5_46 0 n10 ns46 0 -0.00911857674302 +Gc5_47 0 n10 ns47 0 -0.0166815470555 +Gc5_48 0 n10 ns48 0 0.00147590745255 +Gc5_49 0 n10 ns49 0 0.000447778752943 +Gc5_50 0 n10 ns50 0 0.00118555714205 +Gc5_51 0 n10 ns51 0 0.00482809330295 +Gc5_52 0 n10 ns52 0 0.00107199318161 +Gc5_53 0 n10 ns53 0 -1.37376618687e-006 +Gc5_54 0 n10 ns54 0 1.20178693727e-006 +Gc5_55 0 n10 ns55 0 1.82018646931e-006 +Gc5_56 0 n10 ns56 0 -1.15601200646e-006 +Gc5_57 0 n10 ns57 0 0.00318876079528 +Gc5_58 0 n10 ns58 0 -0.00110870835546 +Gc5_59 0 n10 ns59 0 0.000113021080979 +Gc5_60 0 n10 ns60 0 -7.4350257332e-006 +Gc5_61 0 n10 ns61 0 1.22147339368e-006 +Gc5_62 0 n10 ns62 0 -4.63049215379e-007 +Gc5_63 0 n10 ns63 0 6.39809059294e-006 +Gc5_64 0 n10 ns64 0 1.39704791178e-006 +Gc5_65 0 n10 ns65 0 -0.000458578854924 +Gc5_66 0 n10 ns66 0 -0.00987695283334 +Gc5_67 0 n10 ns67 0 0.0041693688699 +Gc5_68 0 n10 ns68 0 0.0019889988654 +Gc5_69 0 n10 ns69 0 1.24094811815e-005 +Gc5_70 0 n10 ns70 0 -1.23562646716e-005 +Gc5_71 0 n10 ns71 0 -0.00367529020672 +Gc5_72 0 n10 ns72 0 -0.00125085317912 +Gc5_73 0 n10 ns73 0 0.00127364911 +Gc5_74 0 n10 ns74 0 -0.00103470212128 +Gc5_75 0 n10 ns75 0 0.00290012942201 +Gc5_76 0 n10 ns76 0 -0.00658535093366 +Gc5_77 0 n10 ns77 0 -0.000373773245775 +Gc5_78 0 n10 ns78 0 6.9071395737e-005 +Gc5_79 0 n10 ns79 0 1.36738450107e-007 +Gc5_80 0 n10 ns80 0 3.02971642278e-007 +Gc5_81 0 n10 ns81 0 0.000168009612184 +Gc5_82 0 n10 ns82 0 0.000816021321284 +Gc5_83 0 n10 ns83 0 0.00539461555215 +Gc5_84 0 n10 ns84 0 0.0074855362205 +Gc5_85 0 n10 ns85 0 4.01543176861e-005 +Gc5_86 0 n10 ns86 0 -0.000393193291108 +Gc5_87 0 n10 ns87 0 0.000326905842697 +Gc5_88 0 n10 ns88 0 -0.00138274565517 +Gc5_89 0 n10 ns89 0 -0.000416898076211 +Gc5_90 0 n10 ns90 0 -4.37524318318e-007 +Gc5_91 0 n10 ns91 0 4.03470621708e-007 +Gc5_92 0 n10 ns92 0 4.62494598189e-007 +Gc5_93 0 n10 ns93 0 -5.65184787966e-007 +Gc5_94 0 n10 ns94 0 0.00179426712675 +Gc5_95 0 n10 ns95 0 0.000221580827412 +Gc5_96 0 n10 ns96 0 8.78364254969e-005 +Gc5_97 0 n10 ns97 0 -2.44103860779e-005 +Gc5_98 0 n10 ns98 0 5.73402138859e-007 +Gc5_99 0 n10 ns99 0 -1.97226795332e-007 +Gc5_100 0 n10 ns100 0 3.01777674173e-006 +Gc5_101 0 n10 ns101 0 4.31387925307e-006 +Gc5_102 0 n10 ns102 0 0.000545105060397 +Gc5_103 0 n10 ns103 0 -0.000121831281308 +Gc5_104 0 n10 ns104 0 -0.00120329042238 +Gc5_105 0 n10 ns105 0 -0.000641931960811 +Gc5_106 0 n10 ns106 0 -5.07268794348e-006 +Gc5_107 0 n10 ns107 0 -2.13097756555e-006 +Gc5_108 0 n10 ns108 0 0.00118432258227 +Gc5_109 0 n10 ns109 0 0.000972545094252 +Gc5_110 0 n10 ns110 0 0.000454781699837 +Gc5_111 0 n10 ns111 0 0.000334930221783 +Gc5_112 0 n10 ns112 0 -0.00290312522029 +Gc5_113 0 n10 ns113 0 0.00658221896865 +Gc5_114 0 n10 ns114 0 0.000376179717445 +Gc5_115 0 n10 ns115 0 -6.82679528097e-005 +Gc5_116 0 n10 ns116 0 -2.07222520394e-007 +Gc5_117 0 n10 ns117 0 -5.2219788614e-007 +Gc5_118 0 n10 ns118 0 -0.000174774588343 +Gc5_119 0 n10 ns119 0 -0.000722810318987 +Gc5_120 0 n10 ns120 0 -0.00543355689537 +Gc5_121 0 n10 ns121 0 -0.00777978594688 +Gc5_122 0 n10 ns122 0 0.000297157063124 +Gc5_123 0 n10 ns123 0 -0.000528764796158 +Gc5_124 0 n10 ns124 0 -6.03469162124e-005 +Gc5_125 0 n10 ns125 0 -0.00146436053752 +Gc5_126 0 n10 ns126 0 -0.00109505691059 +Gc5_127 0 n10 ns127 0 -8.68535122449e-007 +Gc5_128 0 n10 ns128 0 5.4248814541e-008 +Gc5_129 0 n10 ns129 0 9.62873943814e-007 +Gc5_130 0 n10 ns130 0 -4.61889270433e-008 +Gc5_131 0 n10 ns131 0 0.00198273573679 +Gc5_132 0 n10 ns132 0 -0.00337281366599 +Gc5_133 0 n10 ns133 0 -8.81617575162e-005 +Gc5_134 0 n10 ns134 0 -1.95801291615e-005 +Gc5_135 0 n10 ns135 0 -4.24066385727e-007 +Gc5_136 0 n10 ns136 0 1.02278204757e-006 +Gc5_137 0 n10 ns137 0 -1.5774508289e-006 +Gc5_138 0 n10 ns138 0 2.88434407153e-009 +Gc5_139 0 n10 ns139 0 0.000192900714586 +Gc5_140 0 n10 ns140 0 -0.000910626990018 +Gc5_141 0 n10 ns141 0 -0.000699900639022 +Gc5_142 0 n10 ns142 0 0.000241635457449 +Gc5_143 0 n10 ns143 0 1.50379459917e-006 +Gc5_144 0 n10 ns144 0 5.99638663486e-006 +Gc5_145 0 n10 ns145 0 0.00173317905552 +Gc5_146 0 n10 ns146 0 0.00125787448802 +Gc5_147 0 n10 ns147 0 0.000511289371277 +Gc5_148 0 n10 ns148 0 0.000587025992792 +Gc5_149 0 n10 ns149 0 -0.00283483297852 +Gc5_150 0 n10 ns150 0 0.00672040787131 +Gc5_151 0 n10 ns151 0 0.000318670415057 +Gc5_152 0 n10 ns152 0 -6.83987522124e-005 +Gc5_153 0 n10 ns153 0 -1.05271472581e-007 +Gc5_154 0 n10 ns154 0 -2.18537538362e-007 +Gc5_155 0 n10 ns155 0 -6.78549035681e-005 +Gc5_156 0 n10 ns156 0 0.00330598311243 +Gc5_157 0 n10 ns157 0 0.00902231837297 +Gc5_158 0 n10 ns158 0 0.0152803382844 +Gc5_159 0 n10 ns159 0 -0.00242911872119 +Gc5_160 0 n10 ns160 0 0.000625791525108 +Gc5_161 0 n10 ns161 0 0.00080310910928 +Gc5_162 0 n10 ns162 0 0.00369595132075 +Gc5_163 0 n10 ns163 0 0.00246510293246 +Gc5_164 0 n10 ns164 0 1.4919423547e-007 +Gc5_165 0 n10 ns165 0 -1.25835680881e-006 +Gc5_166 0 n10 ns166 0 -7.95208438768e-007 +Gc5_167 0 n10 ns167 0 2.69881240643e-006 +Gc5_168 0 n10 ns168 0 -0.0345648704663 +Gc5_169 0 n10 ns169 0 0.0171202712683 +Gc5_170 0 n10 ns170 0 4.19814231819e-005 +Gc5_171 0 n10 ns171 0 -0.00014992689389 +Gc5_172 0 n10 ns172 0 -4.50825655615e-006 +Gc5_173 0 n10 ns173 0 -1.21542747611e-006 +Gc5_174 0 n10 ns174 0 -7.20039697411e-006 +Gc5_175 0 n10 ns175 0 -1.12330736064e-006 +Gc5_176 0 n10 ns176 0 0.00242440965741 +Gc5_177 0 n10 ns177 0 0.012415743436 +Gc5_178 0 n10 ns178 0 -0.00160718508196 +Gc5_179 0 n10 ns179 0 -0.00357155937164 +Gc5_180 0 n10 ns180 0 3.58263787148e-006 +Gc5_181 0 n10 ns181 0 3.9179924376e-005 +Gc5_182 0 n10 ns182 0 0.00419380409842 +Gc5_183 0 n10 ns183 0 -0.00755051676157 +Gc5_184 0 n10 ns184 0 -0.000702132542158 +Gc5_185 0 n10 ns185 0 0.00196457125956 +Gc5_186 0 n10 ns186 0 -0.00293670866676 +Gc5_187 0 n10 ns187 0 0.00662745175366 +Gc5_188 0 n10 ns188 0 0.000366696240862 +Gc5_189 0 n10 ns189 0 -6.96715358522e-005 +Gc5_190 0 n10 ns190 0 -1.74592215335e-007 +Gc5_191 0 n10 ns191 0 -5.48921498397e-007 +Gc5_192 0 n10 ns192 0 -0.000168843368296 +Gc5_193 0 n10 ns193 0 -0.00155782377827 +Gc5_194 0 n10 ns194 0 -0.00450842859867 +Gc5_195 0 n10 ns195 0 -0.0083695612303 +Gc5_196 0 n10 ns196 0 5.21572399705e-006 +Gc5_197 0 n10 ns197 0 -0.000302354988067 +Gc5_198 0 n10 ns198 0 -0.00121804484924 +Gc5_199 0 n10 ns199 0 -0.00209705209949 +Gc5_200 0 n10 ns200 0 -0.000222675591225 +Gc5_201 0 n10 ns201 0 -1.60915685371e-006 +Gc5_202 0 n10 ns202 0 3.63882448573e-007 +Gc5_203 0 n10 ns203 0 1.15375022643e-006 +Gc5_204 0 n10 ns204 0 -2.28019740194e-008 +Gc5_205 0 n10 ns205 0 0.00202363264168 +Gc5_206 0 n10 ns206 0 -0.00370050460675 +Gc5_207 0 n10 ns207 0 -3.28780365371e-005 +Gc5_208 0 n10 ns208 0 -2.93469782172e-005 +Gc5_209 0 n10 ns209 0 -5.38293490756e-007 +Gc5_210 0 n10 ns210 0 1.03250272062e-006 +Gc5_211 0 n10 ns211 0 -2.1692154925e-006 +Gc5_212 0 n10 ns212 0 2.82038100066e-006 +Gc5_213 0 n10 ns213 0 -0.000192273479624 +Gc5_214 0 n10 ns214 0 8.98447210353e-005 +Gc5_215 0 n10 ns215 0 0.000485628891009 +Gc5_216 0 n10 ns216 0 -0.000286609736088 +Gc5_217 0 n10 ns217 0 -4.48498915412e-006 +Gc5_218 0 n10 ns218 0 8.04517249413e-006 +Gc5_219 0 n10 ns219 0 0.000663835581085 +Gc5_220 0 n10 ns220 0 0.00159764600834 +Gc5_221 0 n10 ns221 0 0.000401531743916 +Gc5_222 0 n10 ns222 0 0.00078357017795 +Gd5_1 0 n10 ni1 0 0.000423009773219 +Gd5_2 0 n10 ni2 0 0.00131580138291 +Gd5_3 0 n10 ni3 0 0.000521645556102 +Gd5_4 0 n10 ni4 0 0.000886122987743 +Gd5_5 0 n10 ni5 0 -0.00217851467332 +Gd5_6 0 n10 ni6 0 0.000606583600707 +Gc6_1 0 n12 ns1 0 0.00309749134675 +Gc6_2 0 n12 ns2 0 -0.0065021419275 +Gc6_3 0 n12 ns3 0 -0.000458686303527 +Gc6_4 0 n12 ns4 0 2.57271941744e-005 +Gc6_5 0 n12 ns5 0 -4.98140408333e-008 +Gc6_6 0 n12 ns6 0 -4.40529838498e-007 +Gc6_7 0 n12 ns7 0 7.02761923173e-005 +Gc6_8 0 n12 ns8 0 -0.00262397324 +Gc6_9 0 n12 ns9 0 -0.00952108072881 +Gc6_10 0 n12 ns10 0 -0.0165577663593 +Gc6_11 0 n12 ns11 0 0.00155528846018 +Gc6_12 0 n12 ns12 0 0.000828923625742 +Gc6_13 0 n12 ns13 0 0.00140592068709 +Gc6_14 0 n12 ns14 0 0.00439551811246 +Gc6_15 0 n12 ns15 0 0.000991478372611 +Gc6_16 0 n12 ns16 0 -1.25721351485e-006 +Gc6_17 0 n12 ns17 0 6.08468047205e-008 +Gc6_18 0 n12 ns18 0 1.62203461844e-006 +Gc6_19 0 n12 ns19 0 4.57409293536e-007 +Gc6_20 0 n12 ns20 0 0.00236008205061 +Gc6_21 0 n12 ns21 0 -0.00049477333047 +Gc6_22 0 n12 ns22 0 5.40727671564e-005 +Gc6_23 0 n12 ns23 0 1.08287847838e-006 +Gc6_24 0 n12 ns24 0 -4.17981566204e-007 +Gc6_25 0 n12 ns25 0 2.40946755159e-007 +Gc6_26 0 n12 ns26 0 -4.27684502801e-007 +Gc6_27 0 n12 ns27 0 2.42204182433e-006 +Gc6_28 0 n12 ns28 0 0.000329382971079 +Gc6_29 0 n12 ns29 0 -0.00604177805838 +Gc6_30 0 n12 ns30 0 0.0039038890115 +Gc6_31 0 n12 ns31 0 -0.00161626719475 +Gc6_32 0 n12 ns32 0 -5.71111650843e-006 +Gc6_33 0 n12 ns33 0 -3.62154730435e-006 +Gc6_34 0 n12 ns34 0 -0.00260253717081 +Gc6_35 0 n12 ns35 0 -0.00259147152073 +Gc6_36 0 n12 ns36 0 0.000645297704453 +Gc6_37 0 n12 ns37 0 -0.00198631032977 +Gc6_38 0 n12 ns38 0 0.00296727425326 +Gc6_39 0 n12 ns39 0 -0.00663359484461 +Gc6_40 0 n12 ns40 0 -0.000363541247597 +Gc6_41 0 n12 ns41 0 7.07383000826e-005 +Gc6_42 0 n12 ns42 0 8.32910776927e-008 +Gc6_43 0 n12 ns43 0 2.96060704331e-007 +Gc6_44 0 n12 ns44 0 0.000161765255162 +Gc6_45 0 n12 ns45 0 0.00164619775623 +Gc6_46 0 n12 ns46 0 0.00450095408694 +Gc6_47 0 n12 ns47 0 0.00807746901688 +Gc6_48 0 n12 ns48 0 0.000127897471625 +Gc6_49 0 n12 ns49 0 -0.000318638528196 +Gc6_50 0 n12 ns50 0 -0.000632113135945 +Gc6_51 0 n12 ns51 0 -0.00190651989148 +Gc6_52 0 n12 ns52 0 0.000554119886285 +Gc6_53 0 n12 ns53 0 -1.41903137264e-006 +Gc6_54 0 n12 ns54 0 8.30046409062e-007 +Gc6_55 0 n12 ns55 0 4.28034579579e-007 +Gc6_56 0 n12 ns56 0 -2.73422766657e-007 +Gc6_57 0 n12 ns57 0 0.00176087382963 +Gc6_58 0 n12 ns58 0 0.00134722860751 +Gc6_59 0 n12 ns59 0 7.34869950257e-005 +Gc6_60 0 n12 ns60 0 5.43791175e-005 +Gc6_61 0 n12 ns61 0 6.56771102148e-008 +Gc6_62 0 n12 ns62 0 -8.74042700748e-007 +Gc6_63 0 n12 ns63 0 3.37986307027e-006 +Gc6_64 0 n12 ns64 0 1.25569494429e-006 +Gc6_65 0 n12 ns65 0 -0.000906438772553 +Gc6_66 0 n12 ns66 0 -0.000158427879555 +Gc6_67 0 n12 ns67 0 -0.000203903475373 +Gc6_68 0 n12 ns68 0 0.000484407071736 +Gc6_69 0 n12 ns69 0 7.10290790722e-008 +Gc6_70 0 n12 ns70 0 -1.22315829901e-005 +Gc6_71 0 n12 ns71 0 0.000839184106003 +Gc6_72 0 n12 ns72 0 0.00148040039888 +Gc6_73 0 n12 ns73 0 0.000587795891145 +Gc6_74 0 n12 ns74 0 0.000592204615358 +Gc6_75 0 n12 ns75 0 0.0029270103139 +Gc6_76 0 n12 ns76 0 -0.00661021513179 +Gc6_77 0 n12 ns77 0 -0.000371710147636 +Gc6_78 0 n12 ns78 0 7.01088394661e-005 +Gc6_79 0 n12 ns79 0 1.46774136817e-007 +Gc6_80 0 n12 ns80 0 3.25161859416e-007 +Gc6_81 0 n12 ns81 0 0.000171574506208 +Gc6_82 0 n12 ns82 0 0.000585293127714 +Gc6_83 0 n12 ns83 0 0.00562384112686 +Gc6_84 0 n12 ns84 0 0.00702249079803 +Gc6_85 0 n12 ns85 0 -0.000112452559249 +Gc6_86 0 n12 ns86 0 -0.000742135053029 +Gc6_87 0 n12 ns87 0 -0.00120877328873 +Gc6_88 0 n12 ns88 0 -0.00241638430813 +Gc6_89 0 n12 ns89 0 -0.000932310356342 +Gc6_90 0 n12 ns90 0 -1.00293850189e-006 +Gc6_91 0 n12 ns91 0 2.36810332839e-009 +Gc6_92 0 n12 ns92 0 3.72357199879e-007 +Gc6_93 0 n12 ns93 0 7.50059186632e-008 +Gc6_94 0 n12 ns94 0 0.0035674751265 +Gc6_95 0 n12 ns95 0 -0.000851945636237 +Gc6_96 0 n12 ns96 0 4.93670613042e-005 +Gc6_97 0 n12 ns97 0 3.07187619558e-005 +Gc6_98 0 n12 ns98 0 2.36146923973e-008 +Gc6_99 0 n12 ns99 0 -3.15583018835e-007 +Gc6_100 0 n12 ns100 0 -1.36138338841e-006 +Gc6_101 0 n12 ns101 0 1.43967395328e-006 +Gc6_102 0 n12 ns102 0 -0.00106828124566 +Gc6_103 0 n12 ns103 0 -0.00141402099031 +Gc6_104 0 n12 ns104 0 0.000352447305369 +Gc6_105 0 n12 ns105 0 0.000771400891795 +Gc6_106 0 n12 ns106 0 -1.93494479466e-006 +Gc6_107 0 n12 ns107 0 -5.04828279776e-006 +Gc6_108 0 n12 ns108 0 -6.83916658977e-005 +Gc6_109 0 n12 ns109 0 0.00149115333871 +Gc6_110 0 n12 ns110 0 0.000122553415797 +Gc6_111 0 n12 ns111 0 0.00127567928813 +Gc6_112 0 n12 ns112 0 -0.0029235924809 +Gc6_113 0 n12 ns113 0 0.00660732316943 +Gc6_114 0 n12 ns114 0 0.000372278718493 +Gc6_115 0 n12 ns115 0 -6.90915219099e-005 +Gc6_116 0 n12 ns116 0 -2.41331883684e-007 +Gc6_117 0 n12 ns117 0 -5.6895961134e-007 +Gc6_118 0 n12 ns118 0 -0.000178454027777 +Gc6_119 0 n12 ns119 0 -0.00049702201941 +Gc6_120 0 n12 ns120 0 -0.0057103878726 +Gc6_121 0 n12 ns121 0 -0.00745966985199 +Gc6_122 0 n12 ns122 0 0.000297880178664 +Gc6_123 0 n12 ns123 0 -0.000811476309969 +Gc6_124 0 n12 ns124 0 -0.000957608178246 +Gc6_125 0 n12 ns125 0 -0.00144480942385 +Gc6_126 0 n12 ns126 0 -0.000279565977978 +Gc6_127 0 n12 ns127 0 -1.20062356603e-006 +Gc6_128 0 n12 ns128 0 -4.43367974477e-008 +Gc6_129 0 n12 ns129 0 6.99654237499e-007 +Gc6_130 0 n12 ns130 0 3.05211329188e-007 +Gc6_131 0 n12 ns131 0 0.00286009536334 +Gc6_132 0 n12 ns132 0 -0.00234457323949 +Gc6_133 0 n12 ns133 0 -3.42832261802e-005 +Gc6_134 0 n12 ns134 0 -4.15768050854e-005 +Gc6_135 0 n12 ns135 0 -1.18882175792e-006 +Gc6_136 0 n12 ns136 0 9.1723859091e-007 +Gc6_137 0 n12 ns137 0 -6.4413390635e-006 +Gc6_138 0 n12 ns138 0 4.03539126296e-006 +Gc6_139 0 n12 ns139 0 -7.99548180088e-005 +Gc6_140 0 n12 ns140 0 -0.00057893006708 +Gc6_141 0 n12 ns141 0 0.000358160625997 +Gc6_142 0 n12 ns142 0 -0.000375502168369 +Gc6_143 0 n12 ns143 0 -4.73137578866e-006 +Gc6_144 0 n12 ns144 0 1.01516049299e-005 +Gc6_145 0 n12 ns145 0 0.000186545978418 +Gc6_146 0 n12 ns146 0 0.00124174440761 +Gc6_147 0 n12 ns147 0 0.000515687032956 +Gc6_148 0 n12 ns148 0 0.000789347544659 +Gc6_149 0 n12 ns149 0 -0.00294474450944 +Gc6_150 0 n12 ns150 0 0.00663004236942 +Gc6_151 0 n12 ns151 0 0.000363699564844 +Gc6_152 0 n12 ns152 0 -6.94242537678e-005 +Gc6_153 0 n12 ns153 0 -2.06758790258e-007 +Gc6_154 0 n12 ns154 0 -5.58994515685e-007 +Gc6_155 0 n12 ns155 0 -0.000171608722592 +Gc6_156 0 n12 ns156 0 -0.00152484313414 +Gc6_157 0 n12 ns157 0 -0.00452532684213 +Gc6_158 0 n12 ns158 0 -0.00848619181877 +Gc6_159 0 n12 ns159 0 2.07454916293e-005 +Gc6_160 0 n12 ns160 0 -0.000261195980311 +Gc6_161 0 n12 ns161 0 -0.00123401974596 +Gc6_162 0 n12 ns162 0 -0.00216264112761 +Gc6_163 0 n12 ns163 0 -0.000201126205033 +Gc6_164 0 n12 ns164 0 -1.71636797655e-006 +Gc6_165 0 n12 ns165 0 2.17287701393e-007 +Gc6_166 0 n12 ns166 0 1.09260358151e-006 +Gc6_167 0 n12 ns167 0 9.05452623108e-008 +Gc6_168 0 n12 ns168 0 0.00217040598751 +Gc6_169 0 n12 ns169 0 -0.00355361307382 +Gc6_170 0 n12 ns170 0 -3.20972668856e-005 +Gc6_171 0 n12 ns171 0 -3.08293508408e-005 +Gc6_172 0 n12 ns172 0 -5.72362167984e-007 +Gc6_173 0 n12 ns173 0 8.15335236406e-007 +Gc6_174 0 n12 ns174 0 1.32580505994e-007 +Gc6_175 0 n12 ns175 0 4.39421152803e-006 +Gc6_176 0 n12 ns176 0 -0.00015065594878 +Gc6_177 0 n12 ns177 0 4.97974216044e-005 +Gc6_178 0 n12 ns178 0 0.000465118422123 +Gc6_179 0 n12 ns179 0 -0.000318900549413 +Gc6_180 0 n12 ns180 0 -4.545059681e-006 +Gc6_181 0 n12 ns181 0 7.7159467749e-006 +Gc6_182 0 n12 ns182 0 0.000602820739564 +Gc6_183 0 n12 ns183 0 0.00160631944494 +Gc6_184 0 n12 ns184 0 0.000395407951801 +Gc6_185 0 n12 ns185 0 0.000800349267486 +Gc6_186 0 n12 ns186 0 -0.00285107417447 +Gc6_187 0 n12 ns187 0 0.00674263089184 +Gc6_188 0 n12 ns188 0 0.000312348898728 +Gc6_189 0 n12 ns189 0 -6.71343201416e-005 +Gc6_190 0 n12 ns190 0 -2.95219601241e-007 +Gc6_191 0 n12 ns191 0 -6.95478717425e-007 +Gc6_192 0 n12 ns192 0 -8.07947839604e-005 +Gc6_193 0 n12 ns193 0 0.00314750127257 +Gc6_194 0 n12 ns194 0 0.00930861828804 +Gc6_195 0 n12 ns195 0 0.0143705181532 +Gc6_196 0 n12 ns196 0 -0.00372822258373 +Gc6_197 0 n12 ns197 0 0.000726059506204 +Gc6_198 0 n12 ns198 0 0.00113547996705 +Gc6_199 0 n12 ns199 0 0.00440618092298 +Gc6_200 0 n12 ns200 0 0.00217086462782 +Gc6_201 0 n12 ns201 0 -3.10096973155e-007 +Gc6_202 0 n12 ns202 0 -1.28002188771e-006 +Gc6_203 0 n12 ns203 0 1.4957241454e-007 +Gc6_204 0 n12 ns204 0 2.71975920701e-006 +Gc6_205 0 n12 ns205 0 -0.0404173183399 +Gc6_206 0 n12 ns206 0 0.00980808869458 +Gc6_207 0 n12 ns207 0 3.09339494028e-006 +Gc6_208 0 n12 ns208 0 -0.000105495759184 +Gc6_209 0 n12 ns209 0 -3.47921408224e-006 +Gc6_210 0 n12 ns210 0 2.02542815962e-006 +Gc6_211 0 n12 ns211 0 -1.42435607649e-005 +Gc6_212 0 n12 ns212 0 -9.71852587167e-007 +Gc6_213 0 n12 ns213 0 0.00251284645196 +Gc6_214 0 n12 ns214 0 0.00679920779061 +Gc6_215 0 n12 ns215 0 -0.0056822336905 +Gc6_216 0 n12 ns216 0 0.00182928556637 +Gc6_217 0 n12 ns217 0 2.24016383156e-005 +Gc6_218 0 n12 ns218 0 8.56144168814e-005 +Gc6_219 0 n12 ns219 0 0.00608580303026 +Gc6_220 0 n12 ns220 0 -0.00822633862839 +Gc6_221 0 n12 ns221 0 0.000425730409579 +Gc6_222 0 n12 ns222 0 0.00321286283332 +Gd6_1 0 n12 ni1 0 0.00131582666905 +Gd6_2 0 n12 ni2 0 0.000310041430214 +Gd6_3 0 n12 ni3 0 0.000192997310747 +Gd6_4 0 n12 ni4 0 0.000635765774884 +Gd6_5 0 n12 ni5 0 0.000605605151176 +Gd6_6 0 n12 ni6 0 -0.00319059345921 +.ends + + + +.subckt 744833011180 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 110720257.968 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 43380028.7804 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 8073946.0048 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 490997.258555 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 62739.3561743 +Ca6 ns6 0 1e-012 +Ca7 ns7 0 1e-012 +Ra6 ns6 0 39582.1187874 +Ra7 ns7 0 39582.1187874 +Ga6 ns6 0 ns7 0 -5.02529097822e-007 +Ga7 ns7 0 ns6 0 5.02529097822e-007 +Ca8 ns8 0 1e-012 +Ra8 ns8 0 8453.95577812 +Ca9 ns9 0 1e-012 +Ra9 ns9 0 2096.31980233 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 5977.22591084 +Ra11 ns11 0 5977.22591084 +Ga10 ns10 0 ns11 0 -0.000589510225523 +Ga11 ns11 0 ns10 0 0.000589510225523 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 5114.32579992 +Ra13 ns13 0 5114.32579992 +Ga12 ns12 0 ns13 0 -0.000598446214329 +Ga13 ns13 0 ns12 0 0.000598446214329 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 30257.9249524 +Ra15 ns15 0 30257.9249524 +Ga14 ns14 0 ns15 0 -0.000766023617865 +Ga15 ns15 0 ns14 0 0.000766023617865 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 3744.79930494 +Ra17 ns17 0 3744.79930494 +Ga16 ns16 0 ns17 0 -0.000866926568527 +Ga17 ns17 0 ns16 0 0.000866926568527 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 24407.1977282 +Ra19 ns19 0 24407.1977282 +Ga18 ns18 0 ns19 0 -0.000991984034964 +Ga19 ns19 0 ns18 0 0.000991984034964 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 1474.49779657 +Ra21 ns21 0 1474.49779657 +Ga20 ns20 0 ns21 0 -0.000762283488535 +Ga21 ns21 0 ns20 0 0.000762283488535 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 3010.3231964 +Ra23 ns23 0 3010.3231964 +Ga22 ns22 0 ns23 0 -0.0014536831743 +Ga23 ns23 0 ns22 0 0.0014536831743 +Ca24 ns24 0 1e-012 +Ra24 ns24 0 110720257.968 +Ca25 ns25 0 1e-012 +Ra25 ns25 0 43380028.7804 +Ca26 ns26 0 1e-012 +Ra26 ns26 0 8073946.0048 +Ca27 ns27 0 1e-012 +Ra27 ns27 0 490997.258555 +Ca28 ns28 0 1e-012 +Ra28 ns28 0 62739.3561743 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 39582.1187874 +Ra30 ns30 0 39582.1187874 +Ga29 ns29 0 ns30 0 -5.02529097822e-007 +Ga30 ns30 0 ns29 0 5.02529097822e-007 +Ca31 ns31 0 1e-012 +Ra31 ns31 0 8453.95577812 +Ca32 ns32 0 1e-012 +Ra32 ns32 0 2096.31980233 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 5977.22591084 +Ra34 ns34 0 5977.22591084 +Ga33 ns33 0 ns34 0 -0.000589510225523 +Ga34 ns34 0 ns33 0 0.000589510225523 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 5114.32579992 +Ra36 ns36 0 5114.32579992 +Ga35 ns35 0 ns36 0 -0.000598446214329 +Ga36 ns36 0 ns35 0 0.000598446214329 +Ca37 ns37 0 1e-012 +Ca38 ns38 0 1e-012 +Ra37 ns37 0 30257.9249524 +Ra38 ns38 0 30257.9249524 +Ga37 ns37 0 ns38 0 -0.000766023617865 +Ga38 ns38 0 ns37 0 0.000766023617865 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 3744.79930494 +Ra40 ns40 0 3744.79930494 +Ga39 ns39 0 ns40 0 -0.000866926568527 +Ga40 ns40 0 ns39 0 0.000866926568527 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 24407.1977282 +Ra42 ns42 0 24407.1977282 +Ga41 ns41 0 ns42 0 -0.000991984034964 +Ga42 ns42 0 ns41 0 0.000991984034964 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 1474.49779657 +Ra44 ns44 0 1474.49779657 +Ga43 ns43 0 ns44 0 -0.000762283488535 +Ga44 ns44 0 ns43 0 0.000762283488535 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 3010.3231964 +Ra46 ns46 0 3010.3231964 +Ga45 ns45 0 ns46 0 -0.0014536831743 +Ga46 ns46 0 ns45 0 0.0014536831743 +Ca47 ns47 0 1e-012 +Ra47 ns47 0 110720257.968 +Ca48 ns48 0 1e-012 +Ra48 ns48 0 43380028.7804 +Ca49 ns49 0 1e-012 +Ra49 ns49 0 8073946.0048 +Ca50 ns50 0 1e-012 +Ra50 ns50 0 490997.258555 +Ca51 ns51 0 1e-012 +Ra51 ns51 0 62739.3561743 +Ca52 ns52 0 1e-012 +Ca53 ns53 0 1e-012 +Ra52 ns52 0 39582.1187874 +Ra53 ns53 0 39582.1187874 +Ga52 ns52 0 ns53 0 -5.02529097822e-007 +Ga53 ns53 0 ns52 0 5.02529097822e-007 +Ca54 ns54 0 1e-012 +Ra54 ns54 0 8453.95577812 +Ca55 ns55 0 1e-012 +Ra55 ns55 0 2096.31980233 +Ca56 ns56 0 1e-012 +Ca57 ns57 0 1e-012 +Ra56 ns56 0 5977.22591084 +Ra57 ns57 0 5977.22591084 +Ga56 ns56 0 ns57 0 -0.000589510225523 +Ga57 ns57 0 ns56 0 0.000589510225523 +Ca58 ns58 0 1e-012 +Ca59 ns59 0 1e-012 +Ra58 ns58 0 5114.32579992 +Ra59 ns59 0 5114.32579992 +Ga58 ns58 0 ns59 0 -0.000598446214329 +Ga59 ns59 0 ns58 0 0.000598446214329 +Ca60 ns60 0 1e-012 +Ca61 ns61 0 1e-012 +Ra60 ns60 0 30257.9249524 +Ra61 ns61 0 30257.9249524 +Ga60 ns60 0 ns61 0 -0.000766023617865 +Ga61 ns61 0 ns60 0 0.000766023617865 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 3744.79930494 +Ra63 ns63 0 3744.79930494 +Ga62 ns62 0 ns63 0 -0.000866926568527 +Ga63 ns63 0 ns62 0 0.000866926568527 +Ca64 ns64 0 1e-012 +Ca65 ns65 0 1e-012 +Ra64 ns64 0 24407.1977282 +Ra65 ns65 0 24407.1977282 +Ga64 ns64 0 ns65 0 -0.000991984034964 +Ga65 ns65 0 ns64 0 0.000991984034964 +Ca66 ns66 0 1e-012 +Ca67 ns67 0 1e-012 +Ra66 ns66 0 1474.49779657 +Ra67 ns67 0 1474.49779657 +Ga66 ns66 0 ns67 0 -0.000762283488535 +Ga67 ns67 0 ns66 0 0.000762283488535 +Ca68 ns68 0 1e-012 +Ca69 ns69 0 1e-012 +Ra68 ns68 0 3010.3231964 +Ra69 ns69 0 3010.3231964 +Ga68 ns68 0 ns69 0 -0.0014536831743 +Ga69 ns69 0 ns68 0 0.0014536831743 +Ca70 ns70 0 1e-012 +Ra70 ns70 0 110720257.968 +Ca71 ns71 0 1e-012 +Ra71 ns71 0 43380028.7804 +Ca72 ns72 0 1e-012 +Ra72 ns72 0 8073946.0048 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 490997.258555 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 62739.3561743 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 39582.1187874 +Ra76 ns76 0 39582.1187874 +Ga75 ns75 0 ns76 0 -5.02529097822e-007 +Ga76 ns76 0 ns75 0 5.02529097822e-007 +Ca77 ns77 0 1e-012 +Ra77 ns77 0 8453.95577812 +Ca78 ns78 0 1e-012 +Ra78 ns78 0 2096.31980233 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 5977.22591084 +Ra80 ns80 0 5977.22591084 +Ga79 ns79 0 ns80 0 -0.000589510225523 +Ga80 ns80 0 ns79 0 0.000589510225523 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 5114.32579992 +Ra82 ns82 0 5114.32579992 +Ga81 ns81 0 ns82 0 -0.000598446214329 +Ga82 ns82 0 ns81 0 0.000598446214329 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 30257.9249524 +Ra84 ns84 0 30257.9249524 +Ga83 ns83 0 ns84 0 -0.000766023617865 +Ga84 ns84 0 ns83 0 0.000766023617865 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 3744.79930494 +Ra86 ns86 0 3744.79930494 +Ga85 ns85 0 ns86 0 -0.000866926568527 +Ga86 ns86 0 ns85 0 0.000866926568527 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 24407.1977282 +Ra88 ns88 0 24407.1977282 +Ga87 ns87 0 ns88 0 -0.000991984034964 +Ga88 ns88 0 ns87 0 0.000991984034964 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 1474.49779657 +Ra90 ns90 0 1474.49779657 +Ga89 ns89 0 ns90 0 -0.000762283488535 +Ga90 ns90 0 ns89 0 0.000762283488535 +Ca91 ns91 0 1e-012 +Ca92 ns92 0 1e-012 +Ra91 ns91 0 3010.3231964 +Ra92 ns92 0 3010.3231964 +Ga91 ns91 0 ns92 0 -0.0014536831743 +Ga92 ns92 0 ns91 0 0.0014536831743 +Ca93 ns93 0 1e-012 +Ra93 ns93 0 110720257.968 +Ca94 ns94 0 1e-012 +Ra94 ns94 0 43380028.7804 +Ca95 ns95 0 1e-012 +Ra95 ns95 0 8073946.0048 +Ca96 ns96 0 1e-012 +Ra96 ns96 0 490997.258555 +Ca97 ns97 0 1e-012 +Ra97 ns97 0 62739.3561743 +Ca98 ns98 0 1e-012 +Ca99 ns99 0 1e-012 +Ra98 ns98 0 39582.1187874 +Ra99 ns99 0 39582.1187874 +Ga98 ns98 0 ns99 0 -5.02529097822e-007 +Ga99 ns99 0 ns98 0 5.02529097822e-007 +Ca100 ns100 0 1e-012 +Ra100 ns100 0 8453.95577812 +Ca101 ns101 0 1e-012 +Ra101 ns101 0 2096.31980233 +Ca102 ns102 0 1e-012 +Ca103 ns103 0 1e-012 +Ra102 ns102 0 5977.22591084 +Ra103 ns103 0 5977.22591084 +Ga102 ns102 0 ns103 0 -0.000589510225523 +Ga103 ns103 0 ns102 0 0.000589510225523 +Ca104 ns104 0 1e-012 +Ca105 ns105 0 1e-012 +Ra104 ns104 0 5114.32579992 +Ra105 ns105 0 5114.32579992 +Ga104 ns104 0 ns105 0 -0.000598446214329 +Ga105 ns105 0 ns104 0 0.000598446214329 +Ca106 ns106 0 1e-012 +Ca107 ns107 0 1e-012 +Ra106 ns106 0 30257.9249524 +Ra107 ns107 0 30257.9249524 +Ga106 ns106 0 ns107 0 -0.000766023617865 +Ga107 ns107 0 ns106 0 0.000766023617865 +Ca108 ns108 0 1e-012 +Ca109 ns109 0 1e-012 +Ra108 ns108 0 3744.79930494 +Ra109 ns109 0 3744.79930494 +Ga108 ns108 0 ns109 0 -0.000866926568527 +Ga109 ns109 0 ns108 0 0.000866926568527 +Ca110 ns110 0 1e-012 +Ca111 ns111 0 1e-012 +Ra110 ns110 0 24407.1977282 +Ra111 ns111 0 24407.1977282 +Ga110 ns110 0 ns111 0 -0.000991984034964 +Ga111 ns111 0 ns110 0 0.000991984034964 +Ca112 ns112 0 1e-012 +Ca113 ns113 0 1e-012 +Ra112 ns112 0 1474.49779657 +Ra113 ns113 0 1474.49779657 +Ga112 ns112 0 ns113 0 -0.000762283488535 +Ga113 ns113 0 ns112 0 0.000762283488535 +Ca114 ns114 0 1e-012 +Ca115 ns115 0 1e-012 +Ra114 ns114 0 3010.3231964 +Ra115 ns115 0 3010.3231964 +Ga114 ns114 0 ns115 0 -0.0014536831743 +Ga115 ns115 0 ns114 0 0.0014536831743 +Ca116 ns116 0 1e-012 +Ra116 ns116 0 110720257.968 +Ca117 ns117 0 1e-012 +Ra117 ns117 0 43380028.7804 +Ca118 ns118 0 1e-012 +Ra118 ns118 0 8073946.0048 +Ca119 ns119 0 1e-012 +Ra119 ns119 0 490997.258555 +Ca120 ns120 0 1e-012 +Ra120 ns120 0 62739.3561743 +Ca121 ns121 0 1e-012 +Ca122 ns122 0 1e-012 +Ra121 ns121 0 39582.1187874 +Ra122 ns122 0 39582.1187874 +Ga121 ns121 0 ns122 0 -5.02529097822e-007 +Ga122 ns122 0 ns121 0 5.02529097822e-007 +Ca123 ns123 0 1e-012 +Ra123 ns123 0 8453.95577812 +Ca124 ns124 0 1e-012 +Ra124 ns124 0 2096.31980233 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 5977.22591084 +Ra126 ns126 0 5977.22591084 +Ga125 ns125 0 ns126 0 -0.000589510225523 +Ga126 ns126 0 ns125 0 0.000589510225523 +Ca127 ns127 0 1e-012 +Ca128 ns128 0 1e-012 +Ra127 ns127 0 5114.32579992 +Ra128 ns128 0 5114.32579992 +Ga127 ns127 0 ns128 0 -0.000598446214329 +Ga128 ns128 0 ns127 0 0.000598446214329 +Ca129 ns129 0 1e-012 +Ca130 ns130 0 1e-012 +Ra129 ns129 0 30257.9249524 +Ra130 ns130 0 30257.9249524 +Ga129 ns129 0 ns130 0 -0.000766023617865 +Ga130 ns130 0 ns129 0 0.000766023617865 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 3744.79930494 +Ra132 ns132 0 3744.79930494 +Ga131 ns131 0 ns132 0 -0.000866926568527 +Ga132 ns132 0 ns131 0 0.000866926568527 +Ca133 ns133 0 1e-012 +Ca134 ns134 0 1e-012 +Ra133 ns133 0 24407.1977282 +Ra134 ns134 0 24407.1977282 +Ga133 ns133 0 ns134 0 -0.000991984034964 +Ga134 ns134 0 ns133 0 0.000991984034964 +Ca135 ns135 0 1e-012 +Ca136 ns136 0 1e-012 +Ra135 ns135 0 1474.49779657 +Ra136 ns136 0 1474.49779657 +Ga135 ns135 0 ns136 0 -0.000762283488535 +Ga136 ns136 0 ns135 0 0.000762283488535 +Ca137 ns137 0 1e-012 +Ca138 ns138 0 1e-012 +Ra137 ns137 0 3010.3231964 +Ra138 ns138 0 3010.3231964 +Ga137 ns137 0 ns138 0 -0.0014536831743 +Ga138 ns138 0 ns137 0 0.0014536831743 + +Gb1_1 ns1 0 ni1 0 9.03177086425e-009 +Gb2_1 ns2 0 ni1 0 2.3052082447e-008 +Gb3_1 ns3 0 ni1 0 1.23855175574e-007 +Gb4_1 ns4 0 ni1 0 2.03667124933e-006 +Gb5_1 ns5 0 ni1 0 1.59389585896e-005 +Gb6_1 ns6 0 ni1 0 2.52739289646e-005 +Gb8_1 ns8 0 ni1 0 0.000118287820075 +Gb9_1 ns9 0 ni1 0 0.000477026453162 +Gb10_1 ns10 0 ni1 0 0.000636990073143 +Gb12_1 ns12 0 ni1 0 0.000662331096003 +Gb14_1 ns14 0 ni1 0 0.000767449486636 +Gb16_1 ns16 0 ni1 0 0.000949181243781 +Gb18_1 ns18 0 ni1 0 0.000993676265309 +Gb20_1 ns20 0 ni1 0 0.00136566949146 +Gb22_1 ns22 0 ni1 0 0.00152959404731 +Gb24_2 ns24 0 ni2 0 9.03177086425e-009 +Gb25_2 ns25 0 ni2 0 2.3052082447e-008 +Gb26_2 ns26 0 ni2 0 1.23855175574e-007 +Gb27_2 ns27 0 ni2 0 2.03667124933e-006 +Gb28_2 ns28 0 ni2 0 1.59389585896e-005 +Gb29_2 ns29 0 ni2 0 2.52739289646e-005 +Gb31_2 ns31 0 ni2 0 0.000118287820075 +Gb32_2 ns32 0 ni2 0 0.000477026453162 +Gb33_2 ns33 0 ni2 0 0.000636990073143 +Gb35_2 ns35 0 ni2 0 0.000662331096003 +Gb37_2 ns37 0 ni2 0 0.000767449486636 +Gb39_2 ns39 0 ni2 0 0.000949181243781 +Gb41_2 ns41 0 ni2 0 0.000993676265309 +Gb43_2 ns43 0 ni2 0 0.00136566949146 +Gb45_2 ns45 0 ni2 0 0.00152959404731 +Gb47_3 ns47 0 ni3 0 9.03177086425e-009 +Gb48_3 ns48 0 ni3 0 2.3052082447e-008 +Gb49_3 ns49 0 ni3 0 1.23855175574e-007 +Gb50_3 ns50 0 ni3 0 2.03667124933e-006 +Gb51_3 ns51 0 ni3 0 1.59389585896e-005 +Gb52_3 ns52 0 ni3 0 2.52739289646e-005 +Gb54_3 ns54 0 ni3 0 0.000118287820075 +Gb55_3 ns55 0 ni3 0 0.000477026453162 +Gb56_3 ns56 0 ni3 0 0.000636990073143 +Gb58_3 ns58 0 ni3 0 0.000662331096003 +Gb60_3 ns60 0 ni3 0 0.000767449486636 +Gb62_3 ns62 0 ni3 0 0.000949181243781 +Gb64_3 ns64 0 ni3 0 0.000993676265309 +Gb66_3 ns66 0 ni3 0 0.00136566949146 +Gb68_3 ns68 0 ni3 0 0.00152959404731 +Gb70_4 ns70 0 ni4 0 9.03177086425e-009 +Gb71_4 ns71 0 ni4 0 2.3052082447e-008 +Gb72_4 ns72 0 ni4 0 1.23855175574e-007 +Gb73_4 ns73 0 ni4 0 2.03667124933e-006 +Gb74_4 ns74 0 ni4 0 1.59389585896e-005 +Gb75_4 ns75 0 ni4 0 2.52739289646e-005 +Gb77_4 ns77 0 ni4 0 0.000118287820075 +Gb78_4 ns78 0 ni4 0 0.000477026453162 +Gb79_4 ns79 0 ni4 0 0.000636990073143 +Gb81_4 ns81 0 ni4 0 0.000662331096003 +Gb83_4 ns83 0 ni4 0 0.000767449486636 +Gb85_4 ns85 0 ni4 0 0.000949181243781 +Gb87_4 ns87 0 ni4 0 0.000993676265309 +Gb89_4 ns89 0 ni4 0 0.00136566949146 +Gb91_4 ns91 0 ni4 0 0.00152959404731 +Gb93_5 ns93 0 ni5 0 9.03177086425e-009 +Gb94_5 ns94 0 ni5 0 2.3052082447e-008 +Gb95_5 ns95 0 ni5 0 1.23855175574e-007 +Gb96_5 ns96 0 ni5 0 2.03667124933e-006 +Gb97_5 ns97 0 ni5 0 1.59389585896e-005 +Gb98_5 ns98 0 ni5 0 2.52739289646e-005 +Gb100_5 ns100 0 ni5 0 0.000118287820075 +Gb101_5 ns101 0 ni5 0 0.000477026453162 +Gb102_5 ns102 0 ni5 0 0.000636990073143 +Gb104_5 ns104 0 ni5 0 0.000662331096003 +Gb106_5 ns106 0 ni5 0 0.000767449486636 +Gb108_5 ns108 0 ni5 0 0.000949181243781 +Gb110_5 ns110 0 ni5 0 0.000993676265309 +Gb112_5 ns112 0 ni5 0 0.00136566949146 +Gb114_5 ns114 0 ni5 0 0.00152959404731 +Gb116_6 ns116 0 ni6 0 9.03177086425e-009 +Gb117_6 ns117 0 ni6 0 2.3052082447e-008 +Gb118_6 ns118 0 ni6 0 1.23855175574e-007 +Gb119_6 ns119 0 ni6 0 2.03667124933e-006 +Gb120_6 ns120 0 ni6 0 1.59389585896e-005 +Gb121_6 ns121 0 ni6 0 2.52739289646e-005 +Gb123_6 ns123 0 ni6 0 0.000118287820075 +Gb124_6 ns124 0 ni6 0 0.000477026453162 +Gb125_6 ns125 0 ni6 0 0.000636990073143 +Gb127_6 ns127 0 ni6 0 0.000662331096003 +Gb129_6 ns129 0 ni6 0 0.000767449486636 +Gb131_6 ns131 0 ni6 0 0.000949181243781 +Gb133_6 ns133 0 ni6 0 0.000993676265309 +Gb135_6 ns135 0 ni6 0 0.00136566949146 +Gb137_6 ns137 0 ni6 0 0.00152959404731 + +Gc1_1 0 n2 ns1 0 -0.0138878968458 +Gc1_2 0 n2 ns2 0 0.0136025473327 +Gc1_3 0 n2 ns3 0 0.000327721332268 +Gc1_4 0 n2 ns4 0 -0.000115335969328 +Gc1_5 0 n2 ns5 0 0.00168574992189 +Gc1_6 0 n2 ns6 0 0.0125629138641 +Gc1_7 0 n2 ns7 0 0.0102774063395 +Gc1_8 0 n2 ns8 0 -0.000461694350055 +Gc1_9 0 n2 ns9 0 -0.00224221413645 +Gc1_10 0 n2 ns10 0 0.0031528070499 +Gc1_11 0 n2 ns11 0 -0.00845477583125 +Gc1_12 0 n2 ns12 0 0.00792140616265 +Gc1_13 0 n2 ns13 0 0.00517076930047 +Gc1_14 0 n2 ns14 0 -7.10393276363e-006 +Gc1_15 0 n2 ns15 0 -6.99978463414e-006 +Gc1_16 0 n2 ns16 0 0.00174913455937 +Gc1_17 0 n2 ns17 0 -0.00424760769192 +Gc1_18 0 n2 ns18 0 6.05279157663e-007 +Gc1_19 0 n2 ns19 0 -4.56432827077e-006 +Gc1_20 0 n2 ns20 0 -0.00874909439419 +Gc1_21 0 n2 ns21 0 0.0205662136956 +Gc1_22 0 n2 ns22 0 0.00352907190472 +Gc1_23 0 n2 ns23 0 0.00162833719018 +Gc1_24 0 n2 ns24 0 -0.0138188601103 +Gc1_25 0 n2 ns25 0 0.0135151551271 +Gc1_26 0 n2 ns26 0 0.000341271168139 +Gc1_27 0 n2 ns27 0 -0.000160384768195 +Gc1_28 0 n2 ns28 0 0.000751650012858 +Gc1_29 0 n2 ns29 0 -0.00800135654083 +Gc1_30 0 n2 ns30 0 -0.0156914583295 +Gc1_31 0 n2 ns31 0 -0.000131638769231 +Gc1_32 0 n2 ns32 0 0.000463522411897 +Gc1_33 0 n2 ns33 0 -0.00204987753408 +Gc1_34 0 n2 ns34 0 0.00503023438493 +Gc1_35 0 n2 ns35 0 -0.00364152624689 +Gc1_36 0 n2 ns36 0 -0.00386529029217 +Gc1_37 0 n2 ns37 0 -7.43570939249e-009 +Gc1_38 0 n2 ns38 0 -1.64383818314e-006 +Gc1_39 0 n2 ns39 0 0.00236838801841 +Gc1_40 0 n2 ns40 0 -0.00421070901143 +Gc1_41 0 n2 ns41 0 -1.43255289266e-006 +Gc1_42 0 n2 ns42 0 -7.19888506752e-008 +Gc1_43 0 n2 ns43 0 0.000409704453798 +Gc1_44 0 n2 ns44 0 0.00226948336451 +Gc1_45 0 n2 ns45 0 -0.000421743975991 +Gc1_46 0 n2 ns46 0 0.000531867024914 +Gc1_47 0 n2 ns47 0 -0.0139124223215 +Gc1_48 0 n2 ns48 0 0.0135660107796 +Gc1_49 0 n2 ns49 0 0.000320433430703 +Gc1_50 0 n2 ns50 0 -0.000121035710968 +Gc1_51 0 n2 ns51 0 -0.000677401969538 +Gc1_52 0 n2 ns52 0 -0.00544683286371 +Gc1_53 0 n2 ns53 0 0.0439341818463 +Gc1_54 0 n2 ns54 0 0.000183496527633 +Gc1_55 0 n2 ns55 0 -0.00102169240883 +Gc1_56 0 n2 ns56 0 -0.000892001674104 +Gc1_57 0 n2 ns57 0 0.00294901177238 +Gc1_58 0 n2 ns58 0 -0.00421161915064 +Gc1_59 0 n2 ns59 0 -0.00101621441522 +Gc1_60 0 n2 ns60 0 -5.10739133765e-006 +Gc1_61 0 n2 ns61 0 1.94498303909e-006 +Gc1_62 0 n2 ns62 0 0.00127778536304 +Gc1_63 0 n2 ns63 0 -0.00301810215033 +Gc1_64 0 n2 ns64 0 -2.87226902536e-006 +Gc1_65 0 n2 ns65 0 5.54760688988e-007 +Gc1_66 0 n2 ns66 0 0.000446846291763 +Gc1_67 0 n2 ns67 0 -0.000627918179947 +Gc1_68 0 n2 ns68 0 -0.000143413425524 +Gc1_69 0 n2 ns69 0 0.000323744293795 +Gc1_70 0 n2 ns70 0 0.0139281396328 +Gc1_71 0 n2 ns71 0 -0.0135938278711 +Gc1_72 0 n2 ns72 0 -0.000312215686181 +Gc1_73 0 n2 ns73 0 0.000113542841388 +Gc1_74 0 n2 ns74 0 0.000723279586226 +Gc1_75 0 n2 ns75 0 0.00540714393503 +Gc1_76 0 n2 ns76 0 -0.0433374587444 +Gc1_77 0 n2 ns77 0 -0.000135401979997 +Gc1_78 0 n2 ns78 0 0.00127401330684 +Gc1_79 0 n2 ns79 0 -0.000271128891096 +Gc1_80 0 n2 ns80 0 3.53740900482e-005 +Gc1_81 0 n2 ns81 0 0.000715960088864 +Gc1_82 0 n2 ns82 0 -0.00109973636918 +Gc1_83 0 n2 ns83 0 -8.03301048965e-007 +Gc1_84 0 n2 ns84 0 -8.23630193741e-006 +Gc1_85 0 n2 ns85 0 -0.00156339661079 +Gc1_86 0 n2 ns86 0 0.00290970841464 +Gc1_87 0 n2 ns87 0 2.81908083464e-006 +Gc1_88 0 n2 ns88 0 -3.05463638251e-006 +Gc1_89 0 n2 ns89 0 0.00227460991876 +Gc1_90 0 n2 ns90 0 -0.000155817579638 +Gc1_91 0 n2 ns91 0 -0.000965101203457 +Gc1_92 0 n2 ns92 0 0.00143725928213 +Gc1_93 0 n2 ns93 0 0.0138189425635 +Gc1_94 0 n2 ns94 0 -0.0135313183601 +Gc1_95 0 n2 ns95 0 -0.000334248348498 +Gc1_96 0 n2 ns96 0 0.000154235976868 +Gc1_97 0 n2 ns97 0 -0.00071620794775 +Gc1_98 0 n2 ns98 0 0.00793128877446 +Gc1_99 0 n2 ns99 0 0.0158512053317 +Gc1_100 0 n2 ns100 0 0.000195332610536 +Gc1_101 0 n2 ns101 0 -0.00049954724522 +Gc1_102 0 n2 ns102 0 0.000447083927383 +Gc1_103 0 n2 ns103 0 0.000114842478321 +Gc1_104 0 n2 ns104 0 -0.000541285004282 +Gc1_105 0 n2 ns105 0 0.000375915794262 +Gc1_106 0 n2 ns106 0 7.51280218179e-007 +Gc1_107 0 n2 ns107 0 -3.66650147901e-006 +Gc1_108 0 n2 ns108 0 -0.00139476069429 +Gc1_109 0 n2 ns109 0 0.00414863038017 +Gc1_110 0 n2 ns110 0 1.32984235424e-006 +Gc1_111 0 n2 ns111 0 -9.71842335665e-007 +Gc1_112 0 n2 ns112 0 0.00161069530419 +Gc1_113 0 n2 ns113 0 -0.00510735736918 +Gc1_114 0 n2 ns114 0 -0.000271434532702 +Gc1_115 0 n2 ns115 0 0.00165867844052 +Gc1_116 0 n2 ns116 0 0.013779898399 +Gc1_117 0 n2 ns117 0 -0.0134403637465 +Gc1_118 0 n2 ns118 0 -0.000390319134675 +Gc1_119 0 n2 ns119 0 6.00888615589e-005 +Gc1_120 0 n2 ns120 0 -0.00167885447576 +Gc1_121 0 n2 ns121 0 -0.0126007845543 +Gc1_122 0 n2 ns122 0 -0.0116067609011 +Gc1_123 0 n2 ns123 0 0.000459353267982 +Gc1_124 0 n2 ns124 0 0.000272408763632 +Gc1_125 0 n2 ns125 0 -0.000461064556549 +Gc1_126 0 n2 ns126 0 0.000995148456631 +Gc1_127 0 n2 ns127 0 -0.00050119890265 +Gc1_128 0 n2 ns128 0 -0.00119922307877 +Gc1_129 0 n2 ns129 0 -3.9968316055e-007 +Gc1_130 0 n2 ns130 0 -6.90310265582e-006 +Gc1_131 0 n2 ns131 0 -0.0020479233389 +Gc1_132 0 n2 ns132 0 0.00257709401406 +Gc1_133 0 n2 ns133 0 2.88300257198e-006 +Gc1_134 0 n2 ns134 0 -3.75381740482e-006 +Gc1_135 0 n2 ns135 0 -0.00117360902064 +Gc1_136 0 n2 ns136 0 -0.000958702626964 +Gc1_137 0 n2 ns137 0 -0.00163863623528 +Gc1_138 0 n2 ns138 0 -0.00160009077051 +Gd1_1 0 n2 ni1 0 0.000329585439421 +Gd1_2 0 n2 ni2 0 -0.000621892654618 +Gd1_3 0 n2 ni3 0 -0.000781322601945 +Gd1_4 0 n2 ni4 0 -4.31853200295e-005 +Gd1_5 0 n2 ni5 0 -0.000208519768572 +Gd1_6 0 n2 ni6 0 -0.00215431261322 +Gc2_1 0 n4 ns1 0 -0.0138399852177 +Gc2_2 0 n4 ns2 0 0.0135278690787 +Gc2_3 0 n4 ns3 0 0.000338581517954 +Gc2_4 0 n4 ns4 0 -0.000159548797174 +Gc2_5 0 n4 ns5 0 0.000756718865222 +Gc2_6 0 n4 ns6 0 -0.00799856847107 +Gc2_7 0 n4 ns7 0 -0.0154260370323 +Gc2_8 0 n4 ns8 0 -0.000133078023046 +Gc2_9 0 n4 ns9 0 0.000452980381513 +Gc2_10 0 n4 ns10 0 -0.00205195417607 +Gc2_11 0 n4 ns11 0 0.00500055460729 +Gc2_12 0 n4 ns12 0 -0.00363003963261 +Gc2_13 0 n4 ns13 0 -0.00382325802589 +Gc2_14 0 n4 ns14 0 -5.66675568384e-008 +Gc2_15 0 n4 ns15 0 -1.52577717411e-006 +Gc2_16 0 n4 ns16 0 0.00236194839304 +Gc2_17 0 n4 ns17 0 -0.00419496208507 +Gc2_18 0 n4 ns18 0 -1.47976747648e-006 +Gc2_19 0 n4 ns19 0 -1.16243021361e-007 +Gc2_20 0 n4 ns20 0 0.000405879274282 +Gc2_21 0 n4 ns21 0 0.00222895142426 +Gc2_22 0 n4 ns22 0 -0.00042079316058 +Gc2_23 0 n4 ns23 0 0.000532578517631 +Gc2_24 0 n4 ns24 0 -0.0140805839379 +Gc2_25 0 n4 ns25 0 0.0137254674874 +Gc2_26 0 n4 ns26 0 0.000321310990122 +Gc2_27 0 n4 ns27 0 -7.90404870382e-005 +Gc2_28 0 n4 ns28 0 0.000551996052597 +Gc2_29 0 n4 ns29 0 0.0144895621442 +Gc2_30 0 n4 ns30 0 0.0492645385363 +Gc2_31 0 n4 ns31 0 -8.33425598382e-005 +Gc2_32 0 n4 ns32 0 -0.00555326157526 +Gc2_33 0 n4 ns33 0 0.00424358352823 +Gc2_34 0 n4 ns34 0 -0.00661054868177 +Gc2_35 0 n4 ns35 0 0.0059225048446 +Gc2_36 0 n4 ns36 0 0.00338870434159 +Gc2_37 0 n4 ns37 0 1.14254665223e-006 +Gc2_38 0 n4 ns38 0 -3.94339115288e-006 +Gc2_39 0 n4 ns39 0 0.00329309980747 +Gc2_40 0 n4 ns40 0 -0.00602497470137 +Gc2_41 0 n4 ns41 0 -4.06144535377e-007 +Gc2_42 0 n4 ns42 0 -4.44844099123e-007 +Gc2_43 0 n4 ns43 0 -0.0134042766302 +Gc2_44 0 n4 ns44 0 0.0181970070443 +Gc2_45 0 n4 ns45 0 0.00444137840204 +Gc2_46 0 n4 ns46 0 -8.79838628671e-006 +Gc2_47 0 n4 ns47 0 -0.0138215133911 +Gc2_48 0 n4 ns48 0 0.01355670588 +Gc2_49 0 n4 ns49 0 0.00030490818054 +Gc2_50 0 n4 ns50 0 -0.000149837039814 +Gc2_51 0 n4 ns51 0 0.000401170283023 +Gc2_52 0 n4 ns52 0 -0.00728718794333 +Gc2_53 0 n4 ns53 0 0.00314101547717 +Gc2_54 0 n4 ns54 0 -0.000114826085136 +Gc2_55 0 n4 ns55 0 0.000784701306905 +Gc2_56 0 n4 ns56 0 -0.00340394809432 +Gc2_57 0 n4 ns57 0 0.00154605218918 +Gc2_58 0 n4 ns58 0 -0.00186480439291 +Gc2_59 0 n4 ns59 0 0.00016518458065 +Gc2_60 0 n4 ns60 0 -7.28204146149e-007 +Gc2_61 0 n4 ns61 0 -1.19560251691e-006 +Gc2_62 0 n4 ns62 0 0.00173164052704 +Gc2_63 0 n4 ns63 0 -0.00445790424787 +Gc2_64 0 n4 ns64 0 -1.31505049262e-006 +Gc2_65 0 n4 ns65 0 7.62755118536e-007 +Gc2_66 0 n4 ns66 0 0.000420865307643 +Gc2_67 0 n4 ns67 0 0.00253955500002 +Gc2_68 0 n4 ns68 0 -0.000399486367847 +Gc2_69 0 n4 ns69 0 0.000316137643091 +Gc2_70 0 n4 ns70 0 0.0137482958421 +Gc2_71 0 n4 ns71 0 -0.0135171709939 +Gc2_72 0 n4 ns72 0 -0.000306201694442 +Gc2_73 0 n4 ns73 0 0.000150789844972 +Gc2_74 0 n4 ns74 0 -0.000388704119936 +Gc2_75 0 n4 ns75 0 0.00724542313657 +Gc2_76 0 n4 ns76 0 -0.0029209816507 +Gc2_77 0 n4 ns77 0 0.000122927206487 +Gc2_78 0 n4 ns78 0 -0.000176728057468 +Gc2_79 0 n4 ns79 0 0.00041230110908 +Gc2_80 0 n4 ns80 0 0.000277123952674 +Gc2_81 0 n4 ns81 0 -0.000377223999785 +Gc2_82 0 n4 ns82 0 0.000178844235685 +Gc2_83 0 n4 ns83 0 -9.92316202154e-007 +Gc2_84 0 n4 ns84 0 -2.38737914699e-006 +Gc2_85 0 n4 ns85 0 -0.00198090431064 +Gc2_86 0 n4 ns86 0 0.00452541960729 +Gc2_87 0 n4 ns87 0 1.14358097496e-006 +Gc2_88 0 n4 ns88 0 -7.59972758343e-007 +Gc2_89 0 n4 ns89 0 0.00327887703211 +Gc2_90 0 n4 ns90 0 -0.0040102808948 +Gc2_91 0 n4 ns91 0 -0.00131359160403 +Gc2_92 0 n4 ns92 0 0.00158552630972 +Gc2_93 0 n4 ns93 0 0.0138612094388 +Gc2_94 0 n4 ns94 0 -0.0134464662598 +Gc2_95 0 n4 ns95 0 -0.000402621311844 +Gc2_96 0 n4 ns96 0 3.4111926216e-005 +Gc2_97 0 n4 ns97 0 -0.000607898255882 +Gc2_98 0 n4 ns98 0 -0.0145213345587 +Gc2_99 0 n4 ns99 0 -0.0523905470617 +Gc2_100 0 n4 ns100 0 0.000178168505901 +Gc2_101 0 n4 ns101 0 0.00199325946153 +Gc2_102 0 n4 ns102 0 -0.000138492404818 +Gc2_103 0 n4 ns103 0 0.00146340839194 +Gc2_104 0 n4 ns104 0 -0.000186555104812 +Gc2_105 0 n4 ns105 0 -0.00153668943724 +Gc2_106 0 n4 ns106 0 6.46164699381e-007 +Gc2_107 0 n4 ns107 0 -6.28884992786e-006 +Gc2_108 0 n4 ns108 0 -0.00159677757384 +Gc2_109 0 n4 ns109 0 0.00446373253777 +Gc2_110 0 n4 ns110 0 3.79002458752e-006 +Gc2_111 0 n4 ns111 0 -4.74802508714e-006 +Gc2_112 0 n4 ns112 0 -0.00202595226893 +Gc2_113 0 n4 ns113 0 -0.00379875969536 +Gc2_114 0 n4 ns114 0 -0.00106575418499 +Gc2_115 0 n4 ns115 0 0.000123694398199 +Gc2_116 0 n4 ns116 0 0.0138387463786 +Gc2_117 0 n4 ns117 0 -0.0135247636751 +Gc2_118 0 n4 ns118 0 -0.000339908912277 +Gc2_119 0 n4 ns119 0 0.000158950540834 +Gc2_120 0 n4 ns120 0 -0.000759736869938 +Gc2_121 0 n4 ns121 0 0.00797415482194 +Gc2_122 0 n4 ns122 0 0.0146169735661 +Gc2_123 0 n4 ns123 0 0.000197456200973 +Gc2_124 0 n4 ns124 0 -0.000459830181555 +Gc2_125 0 n4 ns125 0 0.000632656278084 +Gc2_126 0 n4 ns126 0 -0.00112880512228 +Gc2_127 0 n4 ns127 0 0.000653346476006 +Gc2_128 0 n4 ns128 0 0.00069729961578 +Gc2_129 0 n4 ns129 0 2.42047198023e-006 +Gc2_130 0 n4 ns130 0 -3.38041318599e-006 +Gc2_131 0 n4 ns131 0 -0.0024762005928 +Gc2_132 0 n4 ns132 0 0.00428470126975 +Gc2_133 0 n4 ns133 0 1.75199455977e-006 +Gc2_134 0 n4 ns134 0 5.66887482277e-007 +Gc2_135 0 n4 ns135 0 0.0017355210563 +Gc2_136 0 n4 ns136 0 -0.0034537471284 +Gc2_137 0 n4 ns137 0 -0.00108140147263 +Gc2_138 0 n4 ns138 0 0.00108270746737 +Gd2_1 0 n4 ni1 0 -0.000622829839573 +Gd2_2 0 n4 ni2 0 -0.000652224639801 +Gd2_3 0 n4 ni3 0 -0.000623789837925 +Gd2_4 0 n4 ni4 0 -0.000211740825808 +Gd2_5 0 n4 ni5 0 -0.00196533678788 +Gd2_6 0 n4 ni6 0 -0.00040071192654 +Gc3_1 0 n6 ns1 0 -0.0138934660186 +Gc3_2 0 n6 ns2 0 0.0135602483463 +Gc3_3 0 n6 ns3 0 0.000320305788768 +Gc3_4 0 n6 ns4 0 -0.000120875672925 +Gc3_5 0 n6 ns5 0 -0.000666613978655 +Gc3_6 0 n6 ns6 0 -0.00544704380758 +Gc3_7 0 n6 ns7 0 0.0443020771066 +Gc3_8 0 n6 ns8 0 0.000180685593823 +Gc3_9 0 n6 ns9 0 -0.00102813064332 +Gc3_10 0 n6 ns10 0 -0.000881080889743 +Gc3_11 0 n6 ns11 0 0.00292665709315 +Gc3_12 0 n6 ns12 0 -0.00421583180196 +Gc3_13 0 n6 ns13 0 -0.000986809091623 +Gc3_14 0 n6 ns14 0 -4.94972630485e-006 +Gc3_15 0 n6 ns15 0 2.11635279537e-006 +Gc3_16 0 n6 ns16 0 0.00127559506932 +Gc3_17 0 n6 ns17 0 -0.00300690640942 +Gc3_18 0 n6 ns18 0 -2.78568269325e-006 +Gc3_19 0 n6 ns19 0 5.12567085162e-007 +Gc3_20 0 n6 ns20 0 0.000436243214104 +Gc3_21 0 n6 ns21 0 -0.000658461565592 +Gc3_22 0 n6 ns22 0 -0.000141457061688 +Gc3_23 0 n6 ns23 0 0.000322933075539 +Gc3_24 0 n6 ns24 0 -0.0138379264785 +Gc3_25 0 n6 ns25 0 0.0135675680146 +Gc3_26 0 n6 ns26 0 0.000302488169155 +Gc3_27 0 n6 ns27 0 -0.000149307120572 +Gc3_28 0 n6 ns28 0 0.000399496138393 +Gc3_29 0 n6 ns29 0 -0.0072830394707 +Gc3_30 0 n6 ns30 0 0.00308983154215 +Gc3_31 0 n6 ns31 0 -0.000121556665911 +Gc3_32 0 n6 ns32 0 0.000815637264042 +Gc3_33 0 n6 ns33 0 -0.0034973811414 +Gc3_34 0 n6 ns34 0 0.00150176839026 +Gc3_35 0 n6 ns35 0 -0.00173393826653 +Gc3_36 0 n6 ns36 0 0.000215218243706 +Gc3_37 0 n6 ns37 0 3.67473788398e-007 +Gc3_38 0 n6 ns38 0 -1.44752481285e-006 +Gc3_39 0 n6 ns39 0 0.00172601935484 +Gc3_40 0 n6 ns40 0 -0.0044447149334 +Gc3_41 0 n6 ns41 0 -1.53024564616e-006 +Gc3_42 0 n6 ns42 0 7.90402545583e-007 +Gc3_43 0 n6 ns43 0 0.000423434983158 +Gc3_44 0 n6 ns44 0 0.00253224406064 +Gc3_45 0 n6 ns45 0 -0.000386045086105 +Gc3_46 0 n6 ns46 0 0.000327799148767 +Gc3_47 0 n6 ns47 0 -0.0138732519401 +Gc3_48 0 n6 ns48 0 0.0136107423661 +Gc3_49 0 n6 ns49 0 0.0003321177915 +Gc3_50 0 n6 ns50 0 -0.000107011090901 +Gc3_51 0 n6 ns51 0 0.00181564671517 +Gc3_52 0 n6 ns52 0 0.0119369485552 +Gc3_53 0 n6 ns53 0 -0.0145575076823 +Gc3_54 0 n6 ns54 0 -0.000429178142273 +Gc3_55 0 n6 ns55 0 -0.00284807509563 +Gc3_56 0 n6 ns56 0 0.0041931619414 +Gc3_57 0 n6 ns57 0 -0.00439069406575 +Gc3_58 0 n6 ns58 0 0.00665022927508 +Gc3_59 0 n6 ns59 0 0.000687308134617 +Gc3_60 0 n6 ns60 0 -4.2698800952e-006 +Gc3_61 0 n6 ns61 0 2.29155212075e-006 +Gc3_62 0 n6 ns62 0 0.000685778867356 +Gc3_63 0 n6 ns63 0 -0.00430099884221 +Gc3_64 0 n6 ns64 0 -1.85609873453e-006 +Gc3_65 0 n6 ns65 0 -1.76197038682e-006 +Gc3_66 0 n6 ns66 0 -0.00665768330709 +Gc3_67 0 n6 ns67 0 0.0213197658944 +Gc3_68 0 n6 ns68 0 0.0035584403076 +Gc3_69 0 n6 ns69 0 0.00182504778792 +Gc3_70 0 n6 ns70 0 0.0137186313267 +Gc3_71 0 n6 ns71 0 -0.0133629362195 +Gc3_72 0 n6 ns72 0 -0.000410832806299 +Gc3_73 0 n6 ns73 0 6.47345111072e-005 +Gc3_74 0 n6 ns74 0 -0.00200064269879 +Gc3_75 0 n6 ns75 0 -0.0119386810955 +Gc3_76 0 n6 ns76 0 0.00742350210785 +Gc3_77 0 n6 ns77 0 0.000555413393002 +Gc3_78 0 n6 ns78 0 0.000186925007298 +Gc3_79 0 n6 ns79 0 6.67500855848e-005 +Gc3_80 0 n6 ns80 0 0.00044331385786 +Gc3_81 0 n6 ns81 0 -0.000608746523682 +Gc3_82 0 n6 ns82 0 -0.000308789966841 +Gc3_83 0 n6 ns83 0 -4.2702304836e-006 +Gc3_84 0 n6 ns84 0 -4.68678707692e-006 +Gc3_85 0 n6 ns85 0 -0.00119766643081 +Gc3_86 0 n6 ns86 0 0.00311693397247 +Gc3_87 0 n6 ns87 0 7.53670334129e-008 +Gc3_88 0 n6 ns88 0 -3.64114439004e-006 +Gc3_89 0 n6 ns89 0 -0.00228385182013 +Gc3_90 0 n6 ns90 0 -0.00418629840455 +Gc3_91 0 n6 ns91 0 -0.000714800484118 +Gc3_92 0 n6 ns92 0 0.000122762677486 +Gc3_93 0 n6 ns93 0 0.0138752118253 +Gc3_94 0 n6 ns94 0 -0.0135802341801 +Gc3_95 0 n6 ns95 0 -0.000302349037129 +Gc3_96 0 n6 ns96 0 0.000152042381181 +Gc3_97 0 n6 ns97 0 -0.000419627798731 +Gc3_98 0 n6 ns98 0 0.00730963784641 +Gc3_99 0 n6 ns99 0 -0.00322398728645 +Gc3_100 0 n6 ns100 0 0.000124334464943 +Gc3_101 0 n6 ns101 0 -0.000144031073353 +Gc3_102 0 n6 ns102 0 1.43144256279e-005 +Gc3_103 0 n6 ns103 0 -0.000464441084879 +Gc3_104 0 n6 ns104 0 0.000481119400785 +Gc3_105 0 n6 ns105 0 -0.00062392549882 +Gc3_106 0 n6 ns106 0 -1.72768083947e-007 +Gc3_107 0 n6 ns107 0 -4.54396932563e-006 +Gc3_108 0 n6 ns108 0 -0.00070447915269 +Gc3_109 0 n6 ns109 0 0.00405434250889 +Gc3_110 0 n6 ns110 0 1.59281873008e-006 +Gc3_111 0 n6 ns111 0 -1.4728858281e-006 +Gc3_112 0 n6 ns112 0 0.000598881307028 +Gc3_113 0 n6 ns113 0 -0.00265729840307 +Gc3_114 0 n6 ns114 0 -0.00112682095513 +Gc3_115 0 n6 ns115 0 0.000763331598028 +Gc3_116 0 n6 ns116 0 0.0139000186528 +Gc3_117 0 n6 ns117 0 -0.0135667526888 +Gc3_118 0 n6 ns118 0 -0.000318220285579 +Gc3_119 0 n6 ns119 0 0.000118242119509 +Gc3_120 0 n6 ns120 0 0.000682641265327 +Gc3_121 0 n6 ns121 0 0.00539981076366 +Gc3_122 0 n6 ns122 0 -0.044110921998 +Gc3_123 0 n6 ns123 0 -0.00014903838372 +Gc3_124 0 n6 ns124 0 0.00127616791528 +Gc3_125 0 n6 ns125 0 -0.000201561823146 +Gc3_126 0 n6 ns126 0 0.000804779687509 +Gc3_127 0 n6 ns127 0 -0.000203868381635 +Gc3_128 0 n6 ns128 0 -0.000498012927 +Gc3_129 0 n6 ns129 0 -2.18663825884e-006 +Gc3_130 0 n6 ns130 0 -5.23045767174e-006 +Gc3_131 0 n6 ns131 0 -0.00164913562627 +Gc3_132 0 n6 ns132 0 0.00302581881959 +Gc3_133 0 n6 ns133 0 8.38028784879e-007 +Gc3_134 0 n6 ns134 0 -1.75808804474e-006 +Gc3_135 0 n6 ns135 0 0.00265127382005 +Gc3_136 0 n6 ns136 0 -0.00122256565897 +Gc3_137 0 n6 ns137 0 -0.00123143997797 +Gc3_138 0 n6 ns138 0 0.00111537450841 +Gd3_1 0 n6 ni1 0 -0.000783538978432 +Gd3_2 0 n6 ni2 0 -0.000599914414618 +Gd3_3 0 n6 ni3 0 0.000678047039896 +Gd3_4 0 n6 ni4 0 -0.0019508948172 +Gd3_5 0 n6 ni5 0 -0.000432381574609 +Gd3_6 0 n6 ni6 0 -0.000224145412599 +Gc4_1 0 n8 ns1 0 0.0138900562631 +Gc4_2 0 n8 ns2 0 -0.0135667644209 +Gc4_3 0 n8 ns3 0 -0.000315260507845 +Gc4_4 0 n8 ns4 0 0.000116539012134 +Gc4_5 0 n8 ns5 0 0.000699769866399 +Gc4_6 0 n8 ns6 0 0.00543272086244 +Gc4_7 0 n8 ns7 0 -0.0434893498603 +Gc4_8 0 n8 ns8 0 -0.000143693167211 +Gc4_9 0 n8 ns9 0 0.00133901188014 +Gc4_10 0 n8 ns10 0 -0.000282546856115 +Gc4_11 0 n8 ns11 0 7.30812579042e-005 +Gc4_12 0 n8 ns12 0 0.000721161251985 +Gc4_13 0 n8 ns13 0 -0.00116228080788 +Gc4_14 0 n8 ns14 0 -9.10698225138e-007 +Gc4_15 0 n8 ns15 0 -8.47880832894e-006 +Gc4_16 0 n8 ns16 0 -0.00155928177757 +Gc4_17 0 n8 ns17 0 0.00289067922812 +Gc4_18 0 n8 ns18 0 2.905588964e-006 +Gc4_19 0 n8 ns19 0 -2.79830631526e-006 +Gc4_20 0 n8 ns20 0 0.00231814841427 +Gc4_21 0 n8 ns21 0 -4.28032371707e-005 +Gc4_22 0 n8 ns22 0 -0.000974459135047 +Gc4_23 0 n8 ns23 0 0.00144741503061 +Gc4_24 0 n8 ns24 0 0.0137857950935 +Gc4_25 0 n8 ns25 0 -0.0135291711005 +Gc4_26 0 n8 ns26 0 -0.000311143332735 +Gc4_27 0 n8 ns27 0 0.000150540175553 +Gc4_28 0 n8 ns28 0 -0.000398728058195 +Gc4_29 0 n8 ns29 0 0.00725700456271 +Gc4_30 0 n8 ns30 0 -0.00291115768862 +Gc4_31 0 n8 ns31 0 0.000115800196698 +Gc4_32 0 n8 ns32 0 -0.000189139727213 +Gc4_33 0 n8 ns33 0 0.00033252166365 +Gc4_34 0 n8 ns34 0 0.000369169806987 +Gc4_35 0 n8 ns35 0 -0.000233848632289 +Gc4_36 0 n8 ns36 0 3.29224047254e-005 +Gc4_37 0 n8 ns37 0 2.14374988525e-006 +Gc4_38 0 n8 ns38 0 -2.85081486548e-006 +Gc4_39 0 n8 ns39 0 -0.00183756468047 +Gc4_40 0 n8 ns40 0 0.00458384569443 +Gc4_41 0 n8 ns41 0 1.21678637291e-006 +Gc4_42 0 n8 ns42 0 -3.89278885262e-007 +Gc4_43 0 n8 ns43 0 0.00291839894627 +Gc4_44 0 n8 ns44 0 -0.00418839521434 +Gc4_45 0 n8 ns45 0 -0.00124162285848 +Gc4_46 0 n8 ns46 0 0.0015444976837 +Gc4_47 0 n8 ns47 0 0.0137573230906 +Gc4_48 0 n8 ns48 0 -0.0133981686229 +Gc4_49 0 n8 ns49 0 -0.000405603271141 +Gc4_50 0 n8 ns50 0 6.31051414154e-005 +Gc4_51 0 n8 ns51 0 -0.00197705154885 +Gc4_52 0 n8 ns52 0 -0.0119825552286 +Gc4_53 0 n8 ns53 0 0.00705000480046 +Gc4_54 0 n8 ns54 0 0.000567902084189 +Gc4_55 0 n8 ns55 0 0.000165648094485 +Gc4_56 0 n8 ns56 0 6.19723941144e-005 +Gc4_57 0 n8 ns57 0 0.000447021741238 +Gc4_58 0 n8 ns58 0 -0.000603566791275 +Gc4_59 0 n8 ns59 0 -0.000312852737048 +Gc4_60 0 n8 ns60 0 -4.42862164553e-006 +Gc4_61 0 n8 ns61 0 -4.92250710996e-006 +Gc4_62 0 n8 ns62 0 -0.00119152949462 +Gc4_63 0 n8 ns63 0 0.00311925890033 +Gc4_64 0 n8 ns64 0 8.46502516796e-008 +Gc4_65 0 n8 ns65 0 -3.5364874725e-006 +Gc4_66 0 n8 ns66 0 -0.00230666513547 +Gc4_67 0 n8 ns67 0 -0.00421029347103 +Gc4_68 0 n8 ns68 0 -0.000713882539738 +Gc4_69 0 n8 ns69 0 0.000121323575113 +Gc4_70 0 n8 ns70 0 -0.0139843270024 +Gc4_71 0 n8 ns71 0 0.0136516966547 +Gc4_72 0 n8 ns72 0 0.00033548916141 +Gc4_73 0 n8 ns73 0 -0.000120099156334 +Gc4_74 0 n8 ns74 0 0.00182322362002 +Gc4_75 0 n8 ns75 0 0.0117825352033 +Gc4_76 0 n8 ns76 0 -0.0168120582778 +Gc4_77 0 n8 ns77 0 -0.000218315157058 +Gc4_78 0 n8 ns78 0 -0.0061453079473 +Gc4_79 0 n8 ns79 0 -0.0016443851219 +Gc4_80 0 n8 ns80 0 -0.000187973474951 +Gc4_81 0 n8 ns81 0 0.00263650556252 +Gc4_82 0 n8 ns82 0 9.06794597913e-005 +Gc4_83 0 n8 ns83 0 8.62896109387e-006 +Gc4_84 0 n8 ns84 0 -6.019888114e-007 +Gc4_85 0 n8 ns85 0 0.00195355029065 +Gc4_86 0 n8 ns86 0 -0.00265783499121 +Gc4_87 0 n8 ns87 0 1.56821176021e-006 +Gc4_88 0 n8 ns88 0 3.94578254054e-006 +Gc4_89 0 n8 ns89 0 0.000540275845145 +Gc4_90 0 n8 ns90 0 0.0252675695188 +Gc4_91 0 n8 ns91 0 -0.00231861175454 +Gc4_92 0 n8 ns92 0 -0.00726094228916 +Gc4_93 0 n8 ns93 0 -0.0138123197483 +Gc4_94 0 n8 ns94 0 0.0135401692673 +Gc4_95 0 n8 ns95 0 0.00030947499156 +Gc4_96 0 n8 ns96 0 -0.000151942039345 +Gc4_97 0 n8 ns97 0 0.000402031384487 +Gc4_98 0 n8 ns98 0 -0.00724706834988 +Gc4_99 0 n8 ns99 0 0.00318170069832 +Gc4_100 0 n8 ns100 0 -0.000165222266126 +Gc4_101 0 n8 ns101 0 0.00134993848735 +Gc4_102 0 n8 ns102 0 0.000167135270851 +Gc4_103 0 n8 ns103 0 0.000382625179115 +Gc4_104 0 n8 ns104 0 -0.000384935954011 +Gc4_105 0 n8 ns105 0 -0.000623921813975 +Gc4_106 0 n8 ns106 0 1.66287968374e-006 +Gc4_107 0 n8 ns107 0 -1.07007024679e-006 +Gc4_108 0 n8 ns108 0 0.000789635637716 +Gc4_109 0 n8 ns109 0 -0.00470561205034 +Gc4_110 0 n8 ns110 0 3.80651813064e-006 +Gc4_111 0 n8 ns111 0 -1.68094258594e-006 +Gc4_112 0 n8 ns112 0 -0.00656911814416 +Gc4_113 0 n8 ns113 0 -0.000824749455406 +Gc4_114 0 n8 ns114 0 0.00365846134645 +Gc4_115 0 n8 ns115 0 0.00255246359162 +Gc4_116 0 n8 ns116 0 -0.013884598199 +Gc4_117 0 n8 ns117 0 0.0135655543036 +Gc4_118 0 n8 ns118 0 0.000314166432692 +Gc4_119 0 n8 ns119 0 -0.000113517287984 +Gc4_120 0 n8 ns120 0 -0.000725520360216 +Gc4_121 0 n8 ns121 0 -0.00535678201497 +Gc4_122 0 n8 ns122 0 0.0436314005547 +Gc4_123 0 n8 ns123 0 8.79077278233e-005 +Gc4_124 0 n8 ns124 0 0.000233295016264 +Gc4_125 0 n8 ns125 0 0.00037836738202 +Gc4_126 0 n8 ns126 0 2.89314900724e-005 +Gc4_127 0 n8 ns127 0 -0.000636150366778 +Gc4_128 0 n8 ns128 0 -5.38065424785e-006 +Gc4_129 0 n8 ns129 0 1.28050868874e-006 +Gc4_130 0 n8 ns130 0 -2.4252213199e-006 +Gc4_131 0 n8 ns131 0 0.0016098082762 +Gc4_132 0 n8 ns132 0 -0.00363333727105 +Gc4_133 0 n8 ns133 0 2.84908541767e-006 +Gc4_134 0 n8 ns134 0 -3.74422267152e-006 +Gc4_135 0 n8 ns135 0 -0.00606063558277 +Gc4_136 0 n8 ns136 0 -0.00337421189713 +Gc4_137 0 n8 ns137 0 0.00304541328699 +Gc4_138 0 n8 ns138 0 0.00350148002732 +Gd4_1 0 n8 ni1 0 -2.62695152059e-005 +Gd4_2 0 n8 ni2 0 -0.000249410772164 +Gd4_3 0 n8 ni3 0 -0.00196154970166 +Gd4_4 0 n8 ni4 0 -0.000137063369212 +Gd4_5 0 n8 ni5 0 -0.000826445568914 +Gd4_6 0 n8 ni6 0 -0.000900589660442 +Gc5_1 0 n10 ns1 0 0.013826134066 +Gc5_2 0 n10 ns2 0 -0.0135256362818 +Gc5_3 0 n10 ns3 0 -0.000335370696824 +Gc5_4 0 n10 ns4 0 0.000155009777607 +Gc5_5 0 n10 ns5 0 -0.000718025071746 +Gc5_6 0 n10 ns6 0 0.00794372446293 +Gc5_7 0 n10 ns7 0 0.016093107443 +Gc5_8 0 n10 ns8 0 0.000184681680483 +Gc5_9 0 n10 ns9 0 -0.000446407396098 +Gc5_10 0 n10 ns10 0 0.000431853933317 +Gc5_11 0 n10 ns11 0 0.000128384020725 +Gc5_12 0 n10 ns12 0 -0.000519968300814 +Gc5_13 0 n10 ns13 0 0.000351857110447 +Gc5_14 0 n10 ns14 0 6.73573148999e-007 +Gc5_15 0 n10 ns15 0 -3.69010595522e-006 +Gc5_16 0 n10 ns16 0 -0.00139309651655 +Gc5_17 0 n10 ns17 0 0.00413656548684 +Gc5_18 0 n10 ns18 0 1.35569141925e-006 +Gc5_19 0 n10 ns19 0 -1.02556694568e-006 +Gc5_20 0 n10 ns20 0 0.00161367531763 +Gc5_21 0 n10 ns21 0 -0.00503871005346 +Gc5_22 0 n10 ns22 0 -0.000277535165397 +Gc5_23 0 n10 ns23 0 0.00166081221518 +Gc5_24 0 n10 ns24 0 0.0138631948582 +Gc5_25 0 n10 ns25 0 -0.0134644535105 +Gc5_26 0 n10 ns26 0 -0.00039785650938 +Gc5_27 0 n10 ns27 0 3.32204841568e-005 +Gc5_28 0 n10 ns28 0 -0.000601390569261 +Gc5_29 0 n10 ns29 0 -0.0145495231018 +Gc5_30 0 n10 ns30 0 -0.0529567090724 +Gc5_31 0 n10 ns31 0 0.000190023400966 +Gc5_32 0 n10 ns32 0 0.00195854919609 +Gc5_33 0 n10 ns33 0 -0.000148107831462 +Gc5_34 0 n10 ns34 0 0.00146119185891 +Gc5_35 0 n10 ns35 0 -0.000171644271862 +Gc5_36 0 n10 ns36 0 -0.00152712506749 +Gc5_37 0 n10 ns37 0 6.57370137254e-007 +Gc5_38 0 n10 ns38 0 -6.24667076864e-006 +Gc5_39 0 n10 ns39 0 -0.00159252606601 +Gc5_40 0 n10 ns40 0 0.00448007075737 +Gc5_41 0 n10 ns41 0 3.77253777634e-006 +Gc5_42 0 n10 ns42 0 -4.70971951753e-006 +Gc5_43 0 n10 ns43 0 -0.00205606511321 +Gc5_44 0 n10 ns44 0 -0.0038617654021 +Gc5_45 0 n10 ns45 0 -0.0010587505818 +Gc5_46 0 n10 ns46 0 0.000120309306912 +Gc5_47 0 n10 ns47 0 0.0138502561152 +Gc5_48 0 n10 ns48 0 -0.0135673428119 +Gc5_49 0 n10 ns49 0 -0.000306950763955 +Gc5_50 0 n10 ns50 0 0.000151003895765 +Gc5_51 0 n10 ns51 0 -0.000401489239224 +Gc5_52 0 n10 ns52 0 0.00729893840523 +Gc5_53 0 n10 ns53 0 -0.00321982204225 +Gc5_54 0 n10 ns54 0 0.000114637260723 +Gc5_55 0 n10 ns55 0 -0.000140826507171 +Gc5_56 0 n10 ns56 0 3.02145899267e-006 +Gc5_57 0 n10 ns57 0 -0.00045930465353 +Gc5_58 0 n10 ns58 0 0.000502403683008 +Gc5_59 0 n10 ns59 0 -0.000630341645794 +Gc5_60 0 n10 ns60 0 3.78733028176e-009 +Gc5_61 0 n10 ns61 0 -4.04840380414e-006 +Gc5_62 0 n10 ns62 0 -0.000697044746495 +Gc5_63 0 n10 ns63 0 0.00408059002775 +Gc5_64 0 n10 ns64 0 1.40924580098e-006 +Gc5_65 0 n10 ns65 0 -6.95630080463e-007 +Gc5_66 0 n10 ns66 0 0.000588598279452 +Gc5_67 0 n10 ns67 0 -0.00270449641614 +Gc5_68 0 n10 ns68 0 -0.00112383326906 +Gc5_69 0 n10 ns69 0 0.000778296810676 +Gc5_70 0 n10 ns70 0 -0.0137902369126 +Gc5_71 0 n10 ns71 0 0.0135341968254 +Gc5_72 0 n10 ns72 0 0.000308406948967 +Gc5_73 0 n10 ns73 0 -0.000151881974101 +Gc5_74 0 n10 ns74 0 0.000389793355482 +Gc5_75 0 n10 ns75 0 -0.00722732651982 +Gc5_76 0 n10 ns76 0 0.0035804632839 +Gc5_77 0 n10 ns77 0 -0.000168793200066 +Gc5_78 0 n10 ns78 0 0.00151457221378 +Gc5_79 0 n10 ns79 0 0.000308703363937 +Gc5_80 0 n10 ns80 0 0.000296274057712 +Gc5_81 0 n10 ns81 0 -0.000641972686353 +Gc5_82 0 n10 ns82 0 -0.000490763859628 +Gc5_83 0 n10 ns83 0 -1.03095661083e-006 +Gc5_84 0 n10 ns84 0 -4.81227186226e-007 +Gc5_85 0 n10 ns85 0 0.000598233757458 +Gc5_86 0 n10 ns86 0 -0.00474760076994 +Gc5_87 0 n10 ns87 0 9.54451463267e-007 +Gc5_88 0 n10 ns88 0 -2.83077196335e-006 +Gc5_89 0 n10 ns89 0 -0.00573752631758 +Gc5_90 0 n10 ns90 0 -0.000418057025876 +Gc5_91 0 n10 ns91 0 0.00352375485504 +Gc5_92 0 n10 ns92 0 0.0027440153545 +Gc5_93 0 n10 ns93 0 -0.0140474668258 +Gc5_94 0 n10 ns94 0 0.0137184651562 +Gc5_95 0 n10 ns95 0 0.000317557494417 +Gc5_96 0 n10 ns96 0 -8.76336329082e-005 +Gc5_97 0 n10 ns97 0 0.000549035875721 +Gc5_98 0 n10 ns98 0 0.0143746495674 +Gc5_99 0 n10 ns99 0 0.0472970886166 +Gc5_100 0 n10 ns100 0 5.96302382538e-005 +Gc5_101 0 n10 ns101 0 -0.00723752013234 +Gc5_102 0 n10 ns102 0 -0.00122510495761 +Gc5_103 0 n10 ns103 0 -0.00113497827792 +Gc5_104 0 n10 ns104 0 0.00195804121572 +Gc5_105 0 n10 ns105 0 0.0016006514146 +Gc5_106 0 n10 ns106 0 7.01411966022e-006 +Gc5_107 0 n10 ns107 0 5.93628554475e-006 +Gc5_108 0 n10 ns108 0 0.000628338083255 +Gc5_109 0 n10 ns109 0 -0.00357132405857 +Gc5_110 0 n10 ns110 0 -3.49000917283e-006 +Gc5_111 0 n10 ns111 0 6.10859983737e-006 +Gc5_112 0 n10 ns112 0 0.00532616474663 +Gc5_113 0 n10 ns113 0 0.0271276226113 +Gc5_114 0 n10 ns114 0 -0.00387853323067 +Gc5_115 0 n10 ns115 0 -0.00624236895936 +Gc5_116 0 n10 ns116 0 -0.013813044548 +Gc5_117 0 n10 ns117 0 0.0135194322361 +Gc5_118 0 n10 ns118 0 0.000335335160514 +Gc5_119 0 n10 ns119 0 -0.000153574303344 +Gc5_120 0 n10 ns120 0 0.000714346091698 +Gc5_121 0 n10 ns121 0 -0.00790445941067 +Gc5_122 0 n10 ns122 0 -0.0152437089279 +Gc5_123 0 n10 ns123 0 -0.000238113667444 +Gc5_124 0 n10 ns124 0 0.0016066577741 +Gc5_125 0 n10 ns125 0 -5.58259511084e-005 +Gc5_126 0 n10 ns126 0 0.00055079314154 +Gc5_127 0 n10 ns127 0 4.80100482831e-006 +Gc5_128 0 n10 ns128 0 -0.000844879106887 +Gc5_129 0 n10 ns129 0 1.96076118238e-006 +Gc5_130 0 n10 ns130 0 -9.1960060033e-007 +Gc5_131 0 n10 ns131 0 0.00171795397206 +Gc5_132 0 n10 ns132 0 -0.00450694483309 +Gc5_133 0 n10 ns133 0 4.08369514414e-006 +Gc5_134 0 n10 ns134 0 -3.80595562747e-007 +Gc5_135 0 n10 ns135 0 -0.00650713988335 +Gc5_136 0 n10 ns136 0 -0.00190834518491 +Gc5_137 0 n10 ns137 0 0.00389097443937 +Gc5_138 0 n10 ns138 0 0.00366818411685 +Gd5_1 0 n10 ni1 0 -0.000205662743793 +Gd5_2 0 n10 ni2 0 -0.0019743272074 +Gd5_3 0 n10 ni3 0 -0.000430298053634 +Gd5_4 0 n10 ni4 0 -0.000660928273311 +Gd5_5 0 n10 ni5 0 -3.16141331192e-005 +Gd5_6 0 n10 ni6 0 -0.000349073498796 +Gc6_1 0 n12 ns1 0 0.0137897872117 +Gc6_2 0 n12 ns2 0 -0.0134426797651 +Gc6_3 0 n12 ns3 0 -0.000388715654993 +Gc6_4 0 n12 ns4 0 5.84835503617e-005 +Gc6_5 0 n12 ns5 0 -0.00166255430729 +Gc6_6 0 n12 ns6 0 -0.0126329011396 +Gc6_7 0 n12 ns7 0 -0.0118729434633 +Gc6_8 0 n12 ns8 0 0.00047474082354 +Gc6_9 0 n12 ns9 0 0.000224362287811 +Gc6_10 0 n12 ns10 0 -0.000458191300497 +Gc6_11 0 n12 ns11 0 0.00097937393333 +Gc6_12 0 n12 ns12 0 -0.000509179888466 +Gc6_13 0 n12 ns13 0 -0.00117189836925 +Gc6_14 0 n12 ns14 0 -5.22077927388e-007 +Gc6_15 0 n12 ns15 0 -6.82131438036e-006 +Gc6_16 0 n12 ns16 0 -0.00205255158119 +Gc6_17 0 n12 ns17 0 0.00258714308925 +Gc6_18 0 n12 ns18 0 2.88973360217e-006 +Gc6_19 0 n12 ns19 0 -3.67170207874e-006 +Gc6_20 0 n12 ns20 0 -0.0011693719875 +Gc6_21 0 n12 ns21 0 -0.00101884014228 +Gc6_22 0 n12 ns22 0 -0.00163206786313 +Gc6_23 0 n12 ns23 0 -0.00159952760406 +Gc6_24 0 n12 ns24 0 0.0138014402114 +Gc6_25 0 n12 ns25 0 -0.0135097953667 +Gc6_26 0 n12 ns26 0 -0.000341985362542 +Gc6_27 0 n12 ns27 0 0.000159726339159 +Gc6_28 0 n12 ns28 0 -0.000753332032077 +Gc6_29 0 n12 ns29 0 0.0079878786804 +Gc6_30 0 n12 ns30 0 0.0151765755039 +Gc6_31 0 n12 ns31 0 0.000187273634844 +Gc6_32 0 n12 ns32 0 -0.000441679096963 +Gc6_33 0 n12 ns33 0 0.000624780209206 +Gc6_34 0 n12 ns34 0 -0.00113510315644 +Gc6_35 0 n12 ns35 0 0.000669752240882 +Gc6_36 0 n12 ns36 0 0.000705736345919 +Gc6_37 0 n12 ns37 0 2.43211664219e-006 +Gc6_38 0 n12 ns38 0 -3.36756103449e-006 +Gc6_39 0 n12 ns39 0 -0.00247858544636 +Gc6_40 0 n12 ns40 0 0.00429280452029 +Gc6_41 0 n12 ns41 0 1.68441893703e-006 +Gc6_42 0 n12 ns42 0 5.72978292857e-007 +Gc6_43 0 n12 ns43 0 0.00173507338475 +Gc6_44 0 n12 ns44 0 -0.00345427615409 +Gc6_45 0 n12 ns45 0 -0.00108223382871 +Gc6_46 0 n12 ns46 0 0.00108578558087 +Gc6_47 0 n12 ns47 0 0.0139160578673 +Gc6_48 0 n12 ns48 0 -0.0135729906658 +Gc6_49 0 n12 ns49 0 -0.000319670503806 +Gc6_50 0 n12 ns50 0 0.00012011832221 +Gc6_51 0 n12 ns51 0 0.000676134364704 +Gc6_52 0 n12 ns52 0 0.00541939653706 +Gc6_53 0 n12 ns53 0 -0.043850858662 +Gc6_54 0 n12 ns54 0 -0.000158072352968 +Gc6_55 0 n12 ns55 0 0.00129992771933 +Gc6_56 0 n12 ns56 0 -0.000212225607527 +Gc6_57 0 n12 ns57 0 0.000811023987577 +Gc6_58 0 n12 ns58 0 -0.000189678315834 +Gc6_59 0 n12 ns59 0 -0.00050834418071 +Gc6_60 0 n12 ns60 0 -2.22025128242e-006 +Gc6_61 0 n12 ns61 0 -5.27753992792e-006 +Gc6_62 0 n12 ns62 0 -0.00164994064584 +Gc6_63 0 n12 ns63 0 0.00303040836365 +Gc6_64 0 n12 ns64 0 7.98484704805e-007 +Gc6_65 0 n12 ns65 0 -1.79283581619e-006 +Gc6_66 0 n12 ns66 0 0.00265954588436 +Gc6_67 0 n12 ns67 0 -0.0012027494405 +Gc6_68 0 n12 ns68 0 -0.00123388361694 +Gc6_69 0 n12 ns69 0 0.00111844978993 +Gc6_70 0 n12 ns70 0 -0.013936992016 +Gc6_71 0 n12 ns71 0 0.0136003845412 +Gc6_72 0 n12 ns72 0 0.000312919741187 +Gc6_73 0 n12 ns73 0 -0.000112967351355 +Gc6_74 0 n12 ns74 0 -0.000720446305759 +Gc6_75 0 n12 ns75 0 -0.00536036912872 +Gc6_76 0 n12 ns76 0 0.0437133374451 +Gc6_77 0 n12 ns77 0 9.03656302935e-005 +Gc6_78 0 n12 ns78 0 0.00021533013637 +Gc6_79 0 n12 ns79 0 0.000385973607112 +Gc6_80 0 n12 ns80 0 4.61349831893e-006 +Gc6_81 0 n12 ns81 0 -0.000646020160566 +Gc6_82 0 n12 ns82 0 3.24260654813e-005 +Gc6_83 0 n12 ns83 0 1.06405706345e-006 +Gc6_84 0 n12 ns84 0 -2.26823186193e-006 +Gc6_85 0 n12 ns85 0 0.00160268993691 +Gc6_86 0 n12 ns86 0 -0.00363166925154 +Gc6_87 0 n12 ns87 0 2.97111269538e-006 +Gc6_88 0 n12 ns88 0 -3.86647511931e-006 +Gc6_89 0 n12 ns89 0 -0.00605143249978 +Gc6_90 0 n12 ns90 0 -0.00340518559484 +Gc6_91 0 n12 ns91 0 0.00304924295465 +Gc6_92 0 n12 ns92 0 0.0035050554026 +Gc6_93 0 n12 ns93 0 -0.0138135732583 +Gc6_94 0 n12 ns94 0 0.013531093724 +Gc6_95 0 n12 ns95 0 0.000335140602551 +Gc6_96 0 n12 ns96 0 -0.000154307938338 +Gc6_97 0 n12 ns97 0 0.000732076983844 +Gc6_98 0 n12 ns98 0 -0.00791685645109 +Gc6_99 0 n12 ns99 0 -0.0149774101512 +Gc6_100 0 n12 ns100 0 -0.000235978230589 +Gc6_101 0 n12 ns101 0 0.00161283276163 +Gc6_102 0 n12 ns102 0 -4.92769625353e-005 +Gc6_103 0 n12 ns103 0 0.000550121406898 +Gc6_104 0 n12 ns104 0 -6.63840829892e-006 +Gc6_105 0 n12 ns105 0 -0.000844314204502 +Gc6_106 0 n12 ns106 0 1.92034747688e-006 +Gc6_107 0 n12 ns107 0 -8.86557250293e-007 +Gc6_108 0 n12 ns108 0 0.00171144990385 +Gc6_109 0 n12 ns109 0 -0.00451321846033 +Gc6_110 0 n12 ns110 0 3.99127927138e-006 +Gc6_111 0 n12 ns111 0 -5.55646173089e-007 +Gc6_112 0 n12 ns112 0 -0.00648154573765 +Gc6_113 0 n12 ns113 0 -0.00188515819781 +Gc6_114 0 n12 ns114 0 0.00388724286364 +Gc6_115 0 n12 ns115 0 0.00367194148988 +Gc6_116 0 n12 ns116 0 -0.0139204497781 +Gc6_117 0 n12 ns117 0 0.0136244377605 +Gc6_118 0 n12 ns118 0 0.000324420131292 +Gc6_119 0 n12 ns119 0 -0.000117342881109 +Gc6_120 0 n12 ns120 0 0.00152155424653 +Gc6_121 0 n12 ns121 0 0.01250237847 +Gc6_122 0 n12 ns122 0 0.0048020262502 +Gc6_123 0 n12 ns123 0 -0.000236853286457 +Gc6_124 0 n12 ns124 0 -0.00501569499195 +Gc6_125 0 n12 ns125 0 -0.000769970857568 +Gc6_126 0 n12 ns126 0 -0.000302427364751 +Gc6_127 0 n12 ns127 0 0.0013571713869 +Gc6_128 0 n12 ns128 0 0.000111131025782 +Gc6_129 0 n12 ns129 0 3.55884019837e-006 +Gc6_130 0 n12 ns130 0 1.5010689269e-006 +Gc6_131 0 n12 ns131 0 0.0019118293183 +Gc6_132 0 n12 ns132 0 -0.00252278259317 +Gc6_133 0 n12 ns133 0 -1.05285797501e-006 +Gc6_134 0 n12 ns134 0 2.13729990795e-006 +Gc6_135 0 n12 ns135 0 0.00307527043131 +Gc6_136 0 n12 ns136 0 0.0255320473493 +Gc6_137 0 n12 ns137 0 -0.00174554314726 +Gc6_138 0 n12 ns138 0 -0.00508429494473 +Gd6_1 0 n12 ni1 0 -0.00215444473935 +Gd6_2 0 n12 ni2 0 -0.000398225722482 +Gd6_3 0 n12 ni3 0 -0.000219787286558 +Gd6_4 0 n12 ni4 0 -0.000898913278124 +Gd6_5 0 n12 ni5 0 -0.000344102374112 +Gd6_6 0 n12 ni6 0 0.000684257408001 +.ends + + + + +.subckt 744833027110 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ca2 ns2 0 1e-012 +Ra1 ns1 0 78142251.6175 +Ra2 ns2 0 78142251.6175 +Ga1 ns1 0 ns2 0 -1.66834166576e-008 +Ga2 ns2 0 ns1 0 1.66834166576e-008 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 769217.989359 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 213757.299735 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 116453.788775 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 92674.7610812 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 21153.3122152 +Ra8 ns8 0 21153.3122152 +Ga7 ns7 0 ns8 0 -0.000249222437267 +Ga8 ns8 0 ns7 0 0.000249222437267 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 21872.5448188 +Ra10 ns10 0 21872.5448188 +Ga9 ns9 0 ns10 0 -0.000251926123887 +Ga10 ns10 0 ns9 0 0.000251926123887 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 15766.275449 +Ra12 ns12 0 15766.275449 +Ga11 ns11 0 ns12 0 -0.00033383883354 +Ga12 ns12 0 ns11 0 0.00033383883354 +Ca13 ns13 0 1e-012 +Ra13 ns13 0 2833.99868867 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 11409.8248173 +Ra15 ns15 0 11409.8248173 +Ga14 ns14 0 ns15 0 -0.000738150036542 +Ga15 ns15 0 ns14 0 0.000738150036542 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 1505.49511141 +Ra17 ns17 0 1505.49511141 +Ga16 ns16 0 ns17 0 -0.000680702432689 +Ga17 ns17 0 ns16 0 0.000680702432689 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 78142251.6175 +Ra19 ns19 0 78142251.6175 +Ga18 ns18 0 ns19 0 -1.66834166576e-008 +Ga19 ns19 0 ns18 0 1.66834166576e-008 +Ca20 ns20 0 1e-012 +Ra20 ns20 0 769217.989359 +Ca21 ns21 0 1e-012 +Ra21 ns21 0 213757.299735 +Ca22 ns22 0 1e-012 +Ra22 ns22 0 116453.788775 +Ca23 ns23 0 1e-012 +Ra23 ns23 0 92674.7610812 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 21153.3122152 +Ra25 ns25 0 21153.3122152 +Ga24 ns24 0 ns25 0 -0.000249222437267 +Ga25 ns25 0 ns24 0 0.000249222437267 +Ca26 ns26 0 1e-012 +Ca27 ns27 0 1e-012 +Ra26 ns26 0 21872.5448188 +Ra27 ns27 0 21872.5448188 +Ga26 ns26 0 ns27 0 -0.000251926123887 +Ga27 ns27 0 ns26 0 0.000251926123887 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 15766.275449 +Ra29 ns29 0 15766.275449 +Ga28 ns28 0 ns29 0 -0.00033383883354 +Ga29 ns29 0 ns28 0 0.00033383883354 +Ca30 ns30 0 1e-012 +Ra30 ns30 0 2833.99868867 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 11409.8248173 +Ra32 ns32 0 11409.8248173 +Ga31 ns31 0 ns32 0 -0.000738150036542 +Ga32 ns32 0 ns31 0 0.000738150036542 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 1505.49511141 +Ra34 ns34 0 1505.49511141 +Ga33 ns33 0 ns34 0 -0.000680702432689 +Ga34 ns34 0 ns33 0 0.000680702432689 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 78142251.6175 +Ra36 ns36 0 78142251.6175 +Ga35 ns35 0 ns36 0 -1.66834166576e-008 +Ga36 ns36 0 ns35 0 1.66834166576e-008 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 769217.989359 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 213757.299735 +Ca39 ns39 0 1e-012 +Ra39 ns39 0 116453.788775 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 92674.7610812 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 21153.3122152 +Ra42 ns42 0 21153.3122152 +Ga41 ns41 0 ns42 0 -0.000249222437267 +Ga42 ns42 0 ns41 0 0.000249222437267 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 21872.5448188 +Ra44 ns44 0 21872.5448188 +Ga43 ns43 0 ns44 0 -0.000251926123887 +Ga44 ns44 0 ns43 0 0.000251926123887 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 15766.275449 +Ra46 ns46 0 15766.275449 +Ga45 ns45 0 ns46 0 -0.00033383883354 +Ga46 ns46 0 ns45 0 0.00033383883354 +Ca47 ns47 0 1e-012 +Ra47 ns47 0 2833.99868867 +Ca48 ns48 0 1e-012 +Ca49 ns49 0 1e-012 +Ra48 ns48 0 11409.8248173 +Ra49 ns49 0 11409.8248173 +Ga48 ns48 0 ns49 0 -0.000738150036542 +Ga49 ns49 0 ns48 0 0.000738150036542 +Ca50 ns50 0 1e-012 +Ca51 ns51 0 1e-012 +Ra50 ns50 0 1505.49511141 +Ra51 ns51 0 1505.49511141 +Ga50 ns50 0 ns51 0 -0.000680702432689 +Ga51 ns51 0 ns50 0 0.000680702432689 +Ca52 ns52 0 1e-012 +Ca53 ns53 0 1e-012 +Ra52 ns52 0 78142251.6175 +Ra53 ns53 0 78142251.6175 +Ga52 ns52 0 ns53 0 -1.66834166576e-008 +Ga53 ns53 0 ns52 0 1.66834166576e-008 +Ca54 ns54 0 1e-012 +Ra54 ns54 0 769217.989359 +Ca55 ns55 0 1e-012 +Ra55 ns55 0 213757.299735 +Ca56 ns56 0 1e-012 +Ra56 ns56 0 116453.788775 +Ca57 ns57 0 1e-012 +Ra57 ns57 0 92674.7610812 +Ca58 ns58 0 1e-012 +Ca59 ns59 0 1e-012 +Ra58 ns58 0 21153.3122152 +Ra59 ns59 0 21153.3122152 +Ga58 ns58 0 ns59 0 -0.000249222437267 +Ga59 ns59 0 ns58 0 0.000249222437267 +Ca60 ns60 0 1e-012 +Ca61 ns61 0 1e-012 +Ra60 ns60 0 21872.5448188 +Ra61 ns61 0 21872.5448188 +Ga60 ns60 0 ns61 0 -0.000251926123887 +Ga61 ns61 0 ns60 0 0.000251926123887 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 15766.275449 +Ra63 ns63 0 15766.275449 +Ga62 ns62 0 ns63 0 -0.00033383883354 +Ga63 ns63 0 ns62 0 0.00033383883354 +Ca64 ns64 0 1e-012 +Ra64 ns64 0 2833.99868867 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 11409.8248173 +Ra66 ns66 0 11409.8248173 +Ga65 ns65 0 ns66 0 -0.000738150036542 +Ga66 ns66 0 ns65 0 0.000738150036542 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 1505.49511141 +Ra68 ns68 0 1505.49511141 +Ga67 ns67 0 ns68 0 -0.000680702432689 +Ga68 ns68 0 ns67 0 0.000680702432689 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 78142251.6175 +Ra70 ns70 0 78142251.6175 +Ga69 ns69 0 ns70 0 -1.66834166576e-008 +Ga70 ns70 0 ns69 0 1.66834166576e-008 +Ca71 ns71 0 1e-012 +Ra71 ns71 0 769217.989359 +Ca72 ns72 0 1e-012 +Ra72 ns72 0 213757.299735 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 116453.788775 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 92674.7610812 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 21153.3122152 +Ra76 ns76 0 21153.3122152 +Ga75 ns75 0 ns76 0 -0.000249222437267 +Ga76 ns76 0 ns75 0 0.000249222437267 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 21872.5448188 +Ra78 ns78 0 21872.5448188 +Ga77 ns77 0 ns78 0 -0.000251926123887 +Ga78 ns78 0 ns77 0 0.000251926123887 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 15766.275449 +Ra80 ns80 0 15766.275449 +Ga79 ns79 0 ns80 0 -0.00033383883354 +Ga80 ns80 0 ns79 0 0.00033383883354 +Ca81 ns81 0 1e-012 +Ra81 ns81 0 2833.99868867 +Ca82 ns82 0 1e-012 +Ca83 ns83 0 1e-012 +Ra82 ns82 0 11409.8248173 +Ra83 ns83 0 11409.8248173 +Ga82 ns82 0 ns83 0 -0.000738150036542 +Ga83 ns83 0 ns82 0 0.000738150036542 +Ca84 ns84 0 1e-012 +Ca85 ns85 0 1e-012 +Ra84 ns84 0 1505.49511141 +Ra85 ns85 0 1505.49511141 +Ga84 ns84 0 ns85 0 -0.000680702432689 +Ga85 ns85 0 ns84 0 0.000680702432689 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 78142251.6175 +Ra87 ns87 0 78142251.6175 +Ga86 ns86 0 ns87 0 -1.66834166576e-008 +Ga87 ns87 0 ns86 0 1.66834166576e-008 +Ca88 ns88 0 1e-012 +Ra88 ns88 0 769217.989359 +Ca89 ns89 0 1e-012 +Ra89 ns89 0 213757.299735 +Ca90 ns90 0 1e-012 +Ra90 ns90 0 116453.788775 +Ca91 ns91 0 1e-012 +Ra91 ns91 0 92674.7610812 +Ca92 ns92 0 1e-012 +Ca93 ns93 0 1e-012 +Ra92 ns92 0 21153.3122152 +Ra93 ns93 0 21153.3122152 +Ga92 ns92 0 ns93 0 -0.000249222437267 +Ga93 ns93 0 ns92 0 0.000249222437267 +Ca94 ns94 0 1e-012 +Ca95 ns95 0 1e-012 +Ra94 ns94 0 21872.5448188 +Ra95 ns95 0 21872.5448188 +Ga94 ns94 0 ns95 0 -0.000251926123887 +Ga95 ns95 0 ns94 0 0.000251926123887 +Ca96 ns96 0 1e-012 +Ca97 ns97 0 1e-012 +Ra96 ns96 0 15766.275449 +Ra97 ns97 0 15766.275449 +Ga96 ns96 0 ns97 0 -0.00033383883354 +Ga97 ns97 0 ns96 0 0.00033383883354 +Ca98 ns98 0 1e-012 +Ra98 ns98 0 2833.99868867 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 11409.8248173 +Ra100 ns100 0 11409.8248173 +Ga99 ns99 0 ns100 0 -0.000738150036542 +Ga100 ns100 0 ns99 0 0.000738150036542 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 1505.49511141 +Ra102 ns102 0 1505.49511141 +Ga101 ns101 0 ns102 0 -0.000680702432689 +Ga102 ns102 0 ns101 0 0.000680702432689 + +Gb1_1 ns1 0 ni1 0 2.64996113133e-008 +Gb3_1 ns3 0 ni1 0 1.30002159834e-006 +Gb4_1 ns4 0 ni1 0 4.6782028087e-006 +Gb5_1 ns5 0 ni1 0 8.58709716976e-006 +Gb6_1 ns6 0 ni1 0 1.07904243651e-005 +Gb7_1 ns7 0 ni1 0 0.000258189621699 +Gb9_1 ns9 0 ni1 0 0.000260223259052 +Gb11_1 ns11 0 ni1 0 0.000345889329633 +Gb13_1 ns13 0 ni1 0 0.000352858314295 +Gb14_1 ns14 0 ni1 0 0.000748556361932 +Gb16_1 ns16 0 ni1 0 0.00132886507764 +Gb18_2 ns18 0 ni2 0 2.64996113133e-008 +Gb20_2 ns20 0 ni2 0 1.30002159834e-006 +Gb21_2 ns21 0 ni2 0 4.6782028087e-006 +Gb22_2 ns22 0 ni2 0 8.58709716976e-006 +Gb23_2 ns23 0 ni2 0 1.07904243651e-005 +Gb24_2 ns24 0 ni2 0 0.000258189621699 +Gb26_2 ns26 0 ni2 0 0.000260223259052 +Gb28_2 ns28 0 ni2 0 0.000345889329633 +Gb30_2 ns30 0 ni2 0 0.000352858314295 +Gb31_2 ns31 0 ni2 0 0.000748556361932 +Gb33_2 ns33 0 ni2 0 0.00132886507764 +Gb35_3 ns35 0 ni3 0 2.64996113133e-008 +Gb37_3 ns37 0 ni3 0 1.30002159834e-006 +Gb38_3 ns38 0 ni3 0 4.6782028087e-006 +Gb39_3 ns39 0 ni3 0 8.58709716976e-006 +Gb40_3 ns40 0 ni3 0 1.07904243651e-005 +Gb41_3 ns41 0 ni3 0 0.000258189621699 +Gb43_3 ns43 0 ni3 0 0.000260223259052 +Gb45_3 ns45 0 ni3 0 0.000345889329633 +Gb47_3 ns47 0 ni3 0 0.000352858314295 +Gb48_3 ns48 0 ni3 0 0.000748556361932 +Gb50_3 ns50 0 ni3 0 0.00132886507764 +Gb52_4 ns52 0 ni4 0 2.64996113133e-008 +Gb54_4 ns54 0 ni4 0 1.30002159834e-006 +Gb55_4 ns55 0 ni4 0 4.6782028087e-006 +Gb56_4 ns56 0 ni4 0 8.58709716976e-006 +Gb57_4 ns57 0 ni4 0 1.07904243651e-005 +Gb58_4 ns58 0 ni4 0 0.000258189621699 +Gb60_4 ns60 0 ni4 0 0.000260223259052 +Gb62_4 ns62 0 ni4 0 0.000345889329633 +Gb64_4 ns64 0 ni4 0 0.000352858314295 +Gb65_4 ns65 0 ni4 0 0.000748556361932 +Gb67_4 ns67 0 ni4 0 0.00132886507764 +Gb69_5 ns69 0 ni5 0 2.64996113133e-008 +Gb71_5 ns71 0 ni5 0 1.30002159834e-006 +Gb72_5 ns72 0 ni5 0 4.6782028087e-006 +Gb73_5 ns73 0 ni5 0 8.58709716976e-006 +Gb74_5 ns74 0 ni5 0 1.07904243651e-005 +Gb75_5 ns75 0 ni5 0 0.000258189621699 +Gb77_5 ns77 0 ni5 0 0.000260223259052 +Gb79_5 ns79 0 ni5 0 0.000345889329633 +Gb81_5 ns81 0 ni5 0 0.000352858314295 +Gb82_5 ns82 0 ni5 0 0.000748556361932 +Gb84_5 ns84 0 ni5 0 0.00132886507764 +Gb86_6 ns86 0 ni6 0 2.64996113133e-008 +Gb88_6 ns88 0 ni6 0 1.30002159834e-006 +Gb89_6 ns89 0 ni6 0 4.6782028087e-006 +Gb90_6 ns90 0 ni6 0 8.58709716976e-006 +Gb91_6 ns91 0 ni6 0 1.07904243651e-005 +Gb92_6 ns92 0 ni6 0 0.000258189621699 +Gb94_6 ns94 0 ni6 0 0.000260223259052 +Gb96_6 ns96 0 ni6 0 0.000345889329633 +Gb98_6 ns98 0 ni6 0 0.000352858314295 +Gb99_6 ns99 0 ni6 0 0.000748556361932 +Gb101_6 ns101 0 ni6 0 0.00132886507764 + +Gc1_1 0 n2 ns1 0 0.00398247960479 +Gc1_2 0 n2 ns2 0 0.0028110556956 +Gc1_3 0 n2 ns3 0 9.70717078617e-005 +Gc1_4 0 n2 ns4 0 -9.71454320808e-006 +Gc1_5 0 n2 ns5 0 0.00990137308477 +Gc1_6 0 n2 ns6 0 0.00364425453404 +Gc1_7 0 n2 ns7 0 0.00488693606487 +Gc1_8 0 n2 ns8 0 -0.000988534367098 +Gc1_9 0 n2 ns9 0 0.00149263805931 +Gc1_10 0 n2 ns10 0 -5.51197391794e-005 +Gc1_11 0 n2 ns11 0 0.00190165883609 +Gc1_12 0 n2 ns12 0 -0.00085743539859 +Gc1_13 0 n2 ns13 0 -0.00215826456985 +Gc1_14 0 n2 ns14 0 0.00343878093896 +Gc1_15 0 n2 ns15 0 -0.00272463403887 +Gc1_16 0 n2 ns16 0 -0.0060227359702 +Gc1_17 0 n2 ns17 0 0.0192842507617 +Gc1_18 0 n2 ns18 0 0.00392760559385 +Gc1_19 0 n2 ns19 0 0.00264957302204 +Gc1_20 0 n2 ns20 0 -5.34652661276e-005 +Gc1_21 0 n2 ns21 0 -8.20353077211e-005 +Gc1_22 0 n2 ns22 0 -0.00570623710892 +Gc1_23 0 n2 ns23 0 -0.00102066085083 +Gc1_24 0 n2 ns24 0 -0.00362645876533 +Gc1_25 0 n2 ns25 0 0.00148890188691 +Gc1_26 0 n2 ns26 0 0.000709875129776 +Gc1_27 0 n2 ns27 0 -0.00122646638764 +Gc1_28 0 n2 ns28 0 0.00182414881775 +Gc1_29 0 n2 ns29 0 -0.000821863936519 +Gc1_30 0 n2 ns30 0 0.000222031838851 +Gc1_31 0 n2 ns31 0 -0.000874118325251 +Gc1_32 0 n2 ns32 0 0.000772428410568 +Gc1_33 0 n2 ns33 0 0.00103473769582 +Gc1_34 0 n2 ns34 0 0.000144291891677 +Gc1_35 0 n2 ns35 0 0.00390515758577 +Gc1_36 0 n2 ns36 0 0.00262795769656 +Gc1_37 0 n2 ns37 0 -5.34269272515e-005 +Gc1_38 0 n2 ns38 0 -7.980125373e-005 +Gc1_39 0 n2 ns39 0 -0.00353973863688 +Gc1_40 0 n2 ns40 0 -0.00320003494651 +Gc1_41 0 n2 ns41 0 -0.00139346235858 +Gc1_42 0 n2 ns42 0 -1.66787964754e-005 +Gc1_43 0 n2 ns43 0 -0.00165230449655 +Gc1_44 0 n2 ns44 0 0.000512181361313 +Gc1_45 0 n2 ns45 0 0.00209481950445 +Gc1_46 0 n2 ns46 0 -0.00109802105309 +Gc1_47 0 n2 ns47 0 -0.000108029801164 +Gc1_48 0 n2 ns48 0 -0.00061422019667 +Gc1_49 0 n2 ns49 0 0.000356722670569 +Gc1_50 0 n2 ns50 0 -0.000765964642295 +Gc1_51 0 n2 ns51 0 -0.000560668609528 +Gc1_52 0 n2 ns52 0 -0.00390422860886 +Gc1_53 0 n2 ns53 0 -0.00261323041574 +Gc1_54 0 n2 ns54 0 5.13868829301e-005 +Gc1_55 0 n2 ns55 0 0.000104193245353 +Gc1_56 0 n2 ns56 0 0.00342662259718 +Gc1_57 0 n2 ns57 0 0.00328273310621 +Gc1_58 0 n2 ns58 0 0.000967513183309 +Gc1_59 0 n2 ns59 0 2.9069960747e-005 +Gc1_60 0 n2 ns60 0 0.00064945350123 +Gc1_61 0 n2 ns61 0 -0.000407871988666 +Gc1_62 0 n2 ns62 0 -0.00186610781648 +Gc1_63 0 n2 ns63 0 0.00099681101134 +Gc1_64 0 n2 ns64 0 -0.000219269948269 +Gc1_65 0 n2 ns65 0 -0.000604250051844 +Gc1_66 0 n2 ns66 0 0.000804684934454 +Gc1_67 0 n2 ns67 0 -0.00190773601615 +Gc1_68 0 n2 ns68 0 -0.00265426315884 +Gc1_69 0 n2 ns69 0 -0.00392288948266 +Gc1_70 0 n2 ns70 0 -0.00264086253067 +Gc1_71 0 n2 ns71 0 4.91859221786e-005 +Gc1_72 0 n2 ns72 0 0.000107738305844 +Gc1_73 0 n2 ns73 0 0.00558342977718 +Gc1_74 0 n2 ns74 0 0.00110219081806 +Gc1_75 0 n2 ns75 0 0.0013484584603 +Gc1_76 0 n2 ns76 0 -0.000498984026061 +Gc1_77 0 n2 ns77 0 -0.000470814285184 +Gc1_78 0 n2 ns78 0 0.000457712394562 +Gc1_79 0 n2 ns79 0 -0.00179445800481 +Gc1_80 0 n2 ns80 0 0.00083063908639 +Gc1_81 0 n2 ns81 0 -0.000341404978406 +Gc1_82 0 n2 ns82 0 -0.00068545290702 +Gc1_83 0 n2 ns83 0 0.000647694417573 +Gc1_84 0 n2 ns84 0 -0.00137197331074 +Gc1_85 0 n2 ns85 0 -0.00246199814337 +Gc1_86 0 n2 ns86 0 -0.00393400292269 +Gc1_87 0 n2 ns87 0 -0.00297964793791 +Gc1_88 0 n2 ns88 0 -0.000173819864017 +Gc1_89 0 n2 ns89 0 4.96515607787e-005 +Gc1_90 0 n2 ns90 0 -0.00993348120874 +Gc1_91 0 n2 ns91 0 -0.00362970199276 +Gc1_92 0 n2 ns92 0 -0.00223951008233 +Gc1_93 0 n2 ns93 0 0.000839144033196 +Gc1_94 0 n2 ns94 0 -0.000763860636453 +Gc1_95 0 n2 ns95 0 -8.89413783241e-005 +Gc1_96 0 n2 ns96 0 -0.00195369752777 +Gc1_97 0 n2 ns97 0 0.000937945642007 +Gc1_98 0 n2 ns98 0 0.000509097416475 +Gc1_99 0 n2 ns99 0 -0.000843821960868 +Gc1_100 0 n2 ns100 0 0.00019621430609 +Gc1_101 0 n2 ns101 0 -0.000405386420882 +Gc1_102 0 n2 ns102 0 -0.00282125304567 +Gd1_1 0 n2 ni1 0 -0.000412387184648 +Gd1_2 0 n2 ni2 0 0.000303824974108 +Gd1_3 0 n2 ni3 0 -0.000560794717506 +Gd1_4 0 n2 ni4 0 -0.000704656982778 +Gd1_5 0 n2 ni5 0 -0.000668141597861 +Gd1_6 0 n2 ni6 0 -0.00037790696577 +Gc2_1 0 n4 ns1 0 0.00392048470721 +Gc2_2 0 n4 ns2 0 0.00264630580843 +Gc2_3 0 n4 ns3 0 -5.11510845543e-005 +Gc2_4 0 n4 ns4 0 -8.39707482918e-005 +Gc2_5 0 n4 ns5 0 -0.00571222584299 +Gc2_6 0 n4 ns6 0 -0.00101257869923 +Gc2_7 0 n4 ns7 0 -0.00363105249379 +Gc2_8 0 n4 ns8 0 0.00148056943684 +Gc2_9 0 n4 ns9 0 0.000715615240827 +Gc2_10 0 n4 ns10 0 -0.00121875147865 +Gc2_11 0 n4 ns11 0 0.00182316292406 +Gc2_12 0 n4 ns12 0 -0.000822127812371 +Gc2_13 0 n4 ns13 0 0.000221048867359 +Gc2_14 0 n4 ns14 0 -0.000875455809896 +Gc2_15 0 n4 ns15 0 0.000772626237553 +Gc2_16 0 n4 ns16 0 0.00104391321254 +Gc2_17 0 n4 ns17 0 0.000148069945179 +Gc2_18 0 n4 ns18 0 0.00397938338139 +Gc2_19 0 n4 ns19 0 0.00281606700457 +Gc2_20 0 n4 ns20 0 9.30244830268e-005 +Gc2_21 0 n4 ns21 0 6.59750891948e-005 +Gc2_22 0 n4 ns22 0 0.00709720875737 +Gc2_23 0 n4 ns23 0 0.00638655361102 +Gc2_24 0 n4 ns24 0 0.000689164300656 +Gc2_25 0 n4 ns25 0 -0.000737381163895 +Gc2_26 0 n4 ns26 0 0.00537898130289 +Gc2_27 0 n4 ns27 0 1.44918896797e-005 +Gc2_28 0 n4 ns28 0 0.00177422040858 +Gc2_29 0 n4 ns29 0 -0.000772025017713 +Gc2_30 0 n4 ns30 0 -0.00294618282144 +Gc2_31 0 n4 ns31 0 0.00423127380897 +Gc2_32 0 n4 ns32 0 -0.00441532527427 +Gc2_33 0 n4 ns33 0 -0.013469109672 +Gc2_34 0 n4 ns34 0 0.0163482613639 +Gc2_35 0 n4 ns35 0 0.00389755308698 +Gc2_36 0 n4 ns36 0 0.00262597316525 +Gc2_37 0 n4 ns37 0 -5.5539757058e-005 +Gc2_38 0 n4 ns38 0 -5.9170928551e-005 +Gc2_39 0 n4 ns39 0 -0.00100984949486 +Gc2_40 0 n4 ns40 0 -0.00575290561509 +Gc2_41 0 n4 ns41 0 0.0022234793386 +Gc2_42 0 n4 ns42 0 0.000128150829046 +Gc2_43 0 n4 ns43 0 -0.00515089488599 +Gc2_44 0 n4 ns44 0 0.000372817358704 +Gc2_45 0 n4 ns45 0 0.00203709084332 +Gc2_46 0 n4 ns46 0 -0.00106589714244 +Gc2_47 0 n4 ns47 0 -3.4838634082e-005 +Gc2_48 0 n4 ns48 0 -0.000785975179458 +Gc2_49 0 n4 ns49 0 0.000947254407704 +Gc2_50 0 n4 ns50 0 0.000828816658493 +Gc2_51 0 n4 ns51 0 -0.000423057822907 +Gc2_52 0 n4 ns52 0 -0.00389944560106 +Gc2_53 0 n4 ns53 0 -0.0026168238012 +Gc2_54 0 n4 ns54 0 5.10043045029e-005 +Gc2_55 0 n4 ns55 0 9.67483482237e-005 +Gc2_56 0 n4 ns56 0 0.000844881241232 +Gc2_57 0 n4 ns57 0 0.00586565878738 +Gc2_58 0 n4 ns58 0 -0.00101855174521 +Gc2_59 0 n4 ns59 0 0.000397922357523 +Gc2_60 0 n4 ns60 0 0.00186131285027 +Gc2_61 0 n4 ns61 0 -0.000580906337368 +Gc2_62 0 n4 ns62 0 -0.00182183780727 +Gc2_63 0 n4 ns63 0 0.000953967077947 +Gc2_64 0 n4 ns64 0 -0.000219166102795 +Gc2_65 0 n4 ns65 0 -0.000845745457689 +Gc2_66 0 n4 ns66 0 0.000828964841241 +Gc2_67 0 n4 ns67 0 -0.000365383662208 +Gc2_68 0 n4 ns68 0 -0.00202833924296 +Gc2_69 0 n4 ns69 0 -0.00392251484291 +Gc2_70 0 n4 ns70 0 -0.0029657619367 +Gc2_71 0 n4 ns71 0 -0.000178640776866 +Gc2_72 0 n4 ns72 0 0.000116118164594 +Gc2_73 0 n4 ns73 0 -0.00754493934321 +Gc2_74 0 n4 ns74 0 -0.00606765700333 +Gc2_75 0 n4 ns75 0 9.19830481082e-005 +Gc2_76 0 n4 ns76 0 0.000469976085894 +Gc2_77 0 n4 ns77 0 -0.00284547384875 +Gc2_78 0 n4 ns78 0 7.58516158139e-005 +Gc2_79 0 n4 ns79 0 -0.00174056508564 +Gc2_80 0 n4 ns80 0 0.000796415423704 +Gc2_81 0 n4 ns81 0 0.000587021550766 +Gc2_82 0 n4 ns82 0 -0.00108105640217 +Gc2_83 0 n4 ns83 0 0.000353258708676 +Gc2_84 0 n4 ns84 0 0.000850063305546 +Gc2_85 0 n4 ns85 0 -0.00179807888111 +Gc2_86 0 n4 ns86 0 -0.00392895451189 +Gc2_87 0 n4 ns87 0 -0.00265064397144 +Gc2_88 0 n4 ns88 0 5.33767535406e-005 +Gc2_89 0 n4 ns89 0 9.54197055764e-005 +Gc2_90 0 n4 ns90 0 0.00562518795524 +Gc2_91 0 n4 ns91 0 0.00108597194093 +Gc2_92 0 n4 ns92 0 0.00173163162226 +Gc2_93 0 n4 ns93 0 -0.000507712884227 +Gc2_94 0 n4 ns94 0 -0.000157004201268 +Gc2_95 0 n4 ns95 0 0.000237390802572 +Gc2_96 0 n4 ns96 0 -0.00190136096292 +Gc2_97 0 n4 ns97 0 0.000887926566944 +Gc2_98 0 n4 ns98 0 -0.000409760027391 +Gc2_99 0 n4 ns99 0 -0.000688178867501 +Gc2_100 0 n4 ns100 0 0.00131476015428 +Gc2_101 0 n4 ns101 0 -0.000801792169592 +Gc2_102 0 n4 ns102 0 -0.00289736919068 +Gd2_1 0 n4 ni1 0 0.000308830540475 +Gd2_2 0 n4 ni2 0 -0.00426025935981 +Gd2_3 0 n4 ni3 0 0.000318726752807 +Gd2_4 0 n4 ni4 0 -0.00018643433167 +Gd2_5 0 n4 ni5 0 0.000179012288031 +Gd2_6 0 n4 ni6 0 -0.00011760935165 +Gc3_1 0 n6 ns1 0 0.00390301315773 +Gc3_2 0 n6 ns2 0 0.00262319194855 +Gc3_3 0 n6 ns3 0 -5.31063969282e-005 +Gc3_4 0 n6 ns4 0 -7.73747560985e-005 +Gc3_5 0 n6 ns5 0 -0.00355005845065 +Gc3_6 0 n6 ns6 0 -0.00319040415585 +Gc3_7 0 n6 ns7 0 -0.00138133153322 +Gc3_8 0 n6 ns8 0 -1.65517552956e-005 +Gc3_9 0 n6 ns9 0 -0.0016625599328 +Gc3_10 0 n6 ns10 0 0.000511888793062 +Gc3_11 0 n6 ns11 0 0.002093489324 +Gc3_12 0 n6 ns12 0 -0.00109852235542 +Gc3_13 0 n6 ns13 0 -0.000105845469139 +Gc3_14 0 n6 ns14 0 -0.000614524947482 +Gc3_15 0 n6 ns15 0 0.000358503257686 +Gc3_16 0 n6 ns16 0 -0.0007515996331 +Gc3_17 0 n6 ns17 0 -0.000554473028829 +Gc3_18 0 n6 ns18 0 0.00389635046173 +Gc3_19 0 n6 ns19 0 0.00262253560206 +Gc3_20 0 n6 ns20 0 -5.57492704467e-005 +Gc3_21 0 n6 ns21 0 -5.32255309222e-005 +Gc3_22 0 n6 ns22 0 -0.00103077637885 +Gc3_23 0 n6 ns23 0 -0.00573555465595 +Gc3_24 0 n6 ns24 0 0.00221806634035 +Gc3_25 0 n6 ns25 0 0.000122117034306 +Gc3_26 0 n6 ns26 0 -0.0051440109382 +Gc3_27 0 n6 ns27 0 0.000378657965924 +Gc3_28 0 n6 ns28 0 0.00203552526071 +Gc3_29 0 n6 ns29 0 -0.00106621151824 +Gc3_30 0 n6 ns30 0 -3.68694064759e-005 +Gc3_31 0 n6 ns31 0 -0.000785793316351 +Gc3_32 0 n6 ns32 0 0.00094778372545 +Gc3_33 0 n6 ns33 0 0.000833374579376 +Gc3_34 0 n6 ns34 0 -0.000423474463885 +Gc3_35 0 n6 ns35 0 0.00396576996233 +Gc3_36 0 n6 ns36 0 0.00281509340397 +Gc3_37 0 n6 ns37 0 9.42832709323e-005 +Gc3_38 0 n6 ns38 0 4.46470858008e-005 +Gc3_39 0 n6 ns39 0 0.00500473993717 +Gc3_40 0 n6 ns40 0 0.00852240736143 +Gc3_41 0 n6 ns41 0 -0.00106842377724 +Gc3_42 0 n6 ns42 0 0.000644469648375 +Gc3_43 0 n6 ns43 0 0.00622331449432 +Gc3_44 0 n6 ns44 0 -0.00153192664168 +Gc3_45 0 n6 ns45 0 0.00231031128762 +Gc3_46 0 n6 ns46 0 -0.00136251025177 +Gc3_47 0 n6 ns47 0 -0.00204924726222 +Gc3_48 0 n6 ns48 0 0.00248237897708 +Gc3_49 0 n6 ns49 0 -0.00207707901911 +Gc3_50 0 n6 ns50 0 -0.00164059152574 +Gc3_51 0 n6 ns51 0 0.022185652005 +Gc3_52 0 n6 ns52 0 -0.00391032002799 +Gc3_53 0 n6 ns53 0 -0.00295795790027 +Gc3_54 0 n6 ns54 0 -0.000177117078977 +Gc3_55 0 n6 ns55 0 0.000110171322415 +Gc3_56 0 n6 ns56 0 -0.00533745395916 +Gc3_57 0 n6 ns57 0 -0.00829381635246 +Gc3_58 0 n6 ns58 0 0.000393450979328 +Gc3_59 0 n6 ns59 0 -0.000134320550403 +Gc3_60 0 n6 ns60 0 -0.00255198657078 +Gc3_61 0 n6 ns61 0 0.00069093383025 +Gc3_62 0 n6 ns62 0 -0.0020600516889 +Gc3_63 0 n6 ns63 0 0.00125185715036 +Gc3_64 0 n6 ns64 0 0.000473657761924 +Gc3_65 0 n6 ns65 0 -0.000449588158208 +Gc3_66 0 n6 ns66 0 0.000108070153438 +Gc3_67 0 n6 ns67 0 -0.0033232341505 +Gc3_68 0 n6 ns68 0 -0.00446326009246 +Gc3_69 0 n6 ns69 0 -0.00390141501994 +Gc3_70 0 n6 ns70 0 -0.00262169206557 +Gc3_71 0 n6 ns71 0 5.50848655817e-005 +Gc3_72 0 n6 ns72 0 7.20934299766e-005 +Gc3_73 0 n6 ns73 0 0.000940553814465 +Gc3_74 0 n6 ns74 0 0.00580860150566 +Gc3_75 0 n6 ns75 0 -0.000925422921178 +Gc3_76 0 n6 ns76 0 0.000251292264868 +Gc3_77 0 n6 ns77 0 0.00259875830666 +Gc3_78 0 n6 ns78 0 -0.000663044838142 +Gc3_79 0 n6 ns79 0 -0.00199977795362 +Gc3_80 0 n6 ns80 0 0.00107215368425 +Gc3_81 0 n6 ns81 0 -0.000260241635449 +Gc3_82 0 n6 ns82 0 -0.000401253422067 +Gc3_83 0 n6 ns83 0 0.000395930763658 +Gc3_84 0 n6 ns84 0 -0.00292687537009 +Gc3_85 0 n6 ns85 0 -0.00286129628012 +Gc3_86 0 n6 ns86 0 -0.00390357176851 +Gc3_87 0 n6 ns87 0 -0.00262535199988 +Gc3_88 0 n6 ns88 0 5.33917526564e-005 +Gc3_89 0 n6 ns89 0 9.75862788237e-005 +Gc3_90 0 n6 ns90 0 0.00343227448903 +Gc3_91 0 n6 ns91 0 0.00327329130778 +Gc3_92 0 n6 ns92 0 0.000840003540342 +Gc3_93 0 n6 ns93 0 0.000105421025189 +Gc3_94 0 n6 ns94 0 0.000373283982341 +Gc3_95 0 n6 ns95 0 -0.000348643365706 +Gc3_96 0 n6 ns96 0 -0.00215900539989 +Gc3_97 0 n6 ns97 0 0.00118750202097 +Gc3_98 0 n6 ns98 0 -0.000382192491035 +Gc3_99 0 n6 ns99 0 -0.000566093666027 +Gc3_100 0 n6 ns100 0 0.000166614716632 +Gc3_101 0 n6 ns101 0 -0.00227050385421 +Gc3_102 0 n6 ns102 0 -0.00258294119394 +Gd3_1 0 n6 ni1 0 -0.000551438851488 +Gd3_2 0 n6 ni2 0 0.000321801356486 +Gd3_3 0 n6 ni3 0 0.000507678947606 +Gd3_4 0 n6 ni4 0 -0.00147539793347 +Gd3_5 0 n6 ni5 0 -0.00116569755637 +Gd3_6 0 n6 ni6 0 -0.00111919961874 +Gc4_1 0 n8 ns1 0 -0.00390643081018 +Gc4_2 0 n8 ns2 0 -0.00261358044453 +Gc4_3 0 n8 ns3 0 5.00660435601e-005 +Gc4_4 0 n8 ns4 0 0.000111891614351 +Gc4_5 0 n8 ns5 0 0.00340224423768 +Gc4_6 0 n8 ns6 0 0.00330075853258 +Gc4_7 0 n8 ns7 0 0.000969351240458 +Gc4_8 0 n8 ns8 0 1.36828394384e-005 +Gc4_9 0 n8 ns9 0 0.000648830720501 +Gc4_10 0 n8 ns10 0 -0.000393136758872 +Gc4_11 0 n8 ns11 0 -0.00186610033271 +Gc4_12 0 n8 ns12 0 0.000998444437031 +Gc4_13 0 n8 ns13 0 -0.000215350550378 +Gc4_14 0 n8 ns14 0 -0.000605070358771 +Gc4_15 0 n8 ns15 0 0.00080431221552 +Gc4_16 0 n8 ns16 0 -0.00191191092134 +Gc4_17 0 n8 ns17 0 -0.00265096974961 +Gc4_18 0 n8 ns18 0 -0.00390171215955 +Gc4_19 0 n8 ns19 0 -0.00261931664603 +Gc4_20 0 n8 ns20 0 4.94112545474e-005 +Gc4_21 0 n8 ns21 0 0.000106076790435 +Gc4_22 0 n8 ns22 0 0.000816022753405 +Gc4_23 0 n8 ns23 0 0.00588651356513 +Gc4_24 0 n8 ns24 0 -0.00101673908053 +Gc4_25 0 n8 ns25 0 0.000388696686297 +Gc4_26 0 n8 ns26 0 0.00186038125207 +Gc4_27 0 n8 ns27 0 -0.0005728643543 +Gc4_28 0 n8 ns28 0 -0.0018211212889 +Gc4_29 0 n8 ns29 0 0.000954783731949 +Gc4_30 0 n8 ns30 0 -0.000207803105903 +Gc4_31 0 n8 ns31 0 -0.000849013322718 +Gc4_32 0 n8 ns32 0 0.000832540907137 +Gc4_33 0 n8 ns33 0 -0.000338887972085 +Gc4_34 0 n8 ns34 0 -0.00200982859347 +Gc4_35 0 n8 ns35 0 -0.00390981396055 +Gc4_36 0 n8 ns36 0 -0.00294591122222 +Gc4_37 0 n8 ns37 0 -0.000172958399298 +Gc4_38 0 n8 ns38 0 8.46986749265e-005 +Gc4_39 0 n8 ns39 0 -0.00525149865014 +Gc4_40 0 n8 ns40 0 -0.00836158711552 +Gc4_41 0 n8 ns41 0 0.000368043489223 +Gc4_42 0 n8 ns42 0 -0.000140840814917 +Gc4_43 0 n8 ns43 0 -0.00252736970697 +Gc4_44 0 n8 ns44 0 0.000696264804752 +Gc4_45 0 n8 ns45 0 -0.00205959972888 +Gc4_46 0 n8 ns46 0 0.00125269592719 +Gc4_47 0 n8 ns47 0 0.000485142331474 +Gc4_48 0 n8 ns48 0 -0.000449038120339 +Gc4_49 0 n8 ns49 0 0.000111845860698 +Gc4_50 0 n8 ns50 0 -0.00330653216804 +Gc4_51 0 n8 ns51 0 -0.00445196610967 +Gc4_52 0 n8 ns52 0 0.00396762961633 +Gc4_53 0 n8 ns53 0 0.00279578048394 +Gc4_54 0 n8 ns54 0 9.17364020586e-005 +Gc4_55 0 n8 ns55 0 2.09664975043e-005 +Gc4_56 0 n8 ns56 0 0.00503684846892 +Gc4_57 0 n8 ns57 0 0.00844606591318 +Gc4_58 0 n8 ns58 0 0.000158979840951 +Gc4_59 0 n8 ns59 0 0.000496170611697 +Gc4_60 0 n8 ns60 0 0.000723282570361 +Gc4_61 0 n8 ns61 0 -0.000750287287609 +Gc4_62 0 n8 ns62 0 0.00178826690049 +Gc4_63 0 n8 ns63 0 -0.00114801716929 +Gc4_64 0 n8 ns64 0 -0.00286587613212 +Gc4_65 0 n8 ns65 0 0.000999086792704 +Gc4_66 0 n8 ns66 0 -0.000928341890146 +Gc4_67 0 n8 ns67 0 0.0145873124892 +Gc4_68 0 n8 ns68 0 0.0277530780483 +Gc4_69 0 n8 ns69 0 0.00389989553261 +Gc4_70 0 n8 ns70 0 0.00261571870846 +Gc4_71 0 n8 ns71 0 -5.17826765129e-005 +Gc4_72 0 n8 ns72 0 -7.25709592534e-005 +Gc4_73 0 n8 ns73 0 -0.000968414578453 +Gc4_74 0 n8 ns74 0 -0.00575443756672 +Gc4_75 0 n8 ns75 0 0.00029641489996 +Gc4_76 0 n8 ns76 0 3.24696850201e-006 +Gc4_77 0 n8 ns77 0 -0.000877239651816 +Gc4_78 0 n8 ns78 0 0.00017202411504 +Gc4_79 0 n8 ns79 0 0.00177946320261 +Gc4_80 0 n8 ns80 0 -0.000989214308953 +Gc4_81 0 n8 ns81 0 4.74078539091e-007 +Gc4_82 0 n8 ns82 0 0.000262053530318 +Gc4_83 0 n8 ns83 0 -0.000300287755812 +Gc4_84 0 n8 ns84 0 -0.00888625791929 +Gc4_85 0 n8 ns85 0 -0.00392790557743 +Gc4_86 0 n8 ns86 0 0.00390590480238 +Gc4_87 0 n8 ns87 0 0.00262677902834 +Gc4_88 0 n8 ns88 0 -5.02160973428e-005 +Gc4_89 0 n8 ns89 0 -8.81301139201e-005 +Gc4_90 0 n8 ns90 0 -0.00351088380522 +Gc4_91 0 n8 ns91 0 -0.00318918661962 +Gc4_92 0 n8 ns92 0 -0.000606060396838 +Gc4_93 0 n8 ns93 0 0.000221084819996 +Gc4_94 0 n8 ns94 0 -0.000101391209868 +Gc4_95 0 n8 ns95 0 -1.98516310885e-005 +Gc4_96 0 n8 ns96 0 0.00191622849398 +Gc4_97 0 n8 ns97 0 -0.00109413363961 +Gc4_98 0 n8 ns98 0 3.61152118911e-005 +Gc4_99 0 n8 ns99 0 0.000261697776881 +Gc4_100 0 n8 ns100 0 -0.000371787042851 +Gc4_101 0 n8 ns101 0 -0.00911842032299 +Gc4_102 0 n8 ns102 0 -0.00380046286169 +Gd4_1 0 n8 ni1 0 -0.000708728433177 +Gd4_2 0 n8 ni2 0 -0.000171033871397 +Gd4_3 0 n8 ni3 0 -0.00146322880098 +Gd4_4 0 n8 ni4 0 0.00685947438617 +Gd4_5 0 n8 ni5 0 -0.00361408845304 +Gd4_6 0 n8 ni6 0 -0.00377764969653 +Gc5_1 0 n10 ns1 0 -0.00392989528906 +Gc5_2 0 n10 ns2 0 -0.0026410597581 +Gc5_3 0 n10 ns3 0 5.00428767954e-005 +Gc5_4 0 n10 ns4 0 0.00010849093946 +Gc5_5 0 n10 ns5 0 0.00557643675892 +Gc5_6 0 n10 ns6 0 0.00110739207983 +Gc5_7 0 n10 ns7 0 0.00134879791064 +Gc5_8 0 n10 ns8 0 -0.000508299861183 +Gc5_9 0 n10 ns9 0 -0.000469960578845 +Gc5_10 0 n10 ns10 0 0.000465949442814 +Gc5_11 0 n10 ns11 0 -0.00179432217989 +Gc5_12 0 n10 ns12 0 0.000831838198894 +Gc5_13 0 n10 ns13 0 -0.000331400300829 +Gc5_14 0 n10 ns14 0 -0.000686989970915 +Gc5_15 0 n10 ns15 0 0.000651012616678 +Gc5_16 0 n10 ns16 0 -0.00134988902164 +Gc5_17 0 n10 ns17 0 -0.00244805716897 +Gc5_18 0 n10 ns18 0 -0.00392514221774 +Gc5_19 0 n10 ns19 0 -0.0029560754735 +Gc5_20 0 n10 ns20 0 -0.000174522945197 +Gc5_21 0 n10 ns21 0 9.04874507374e-005 +Gc5_22 0 n10 ns22 0 -0.00745462488069 +Gc5_23 0 n10 ns23 0 -0.00613746744868 +Gc5_24 0 n10 ns24 0 6.25192854141e-005 +Gc5_25 0 n10 ns25 0 0.000467258026642 +Gc5_26 0 n10 ns26 0 -0.00281869918929 +Gc5_27 0 n10 ns27 0 7.72454429015e-005 +Gc5_28 0 n10 ns28 0 -0.00174021240934 +Gc5_29 0 n10 ns29 0 0.000797283241702 +Gc5_30 0 n10 ns30 0 0.000597964237416 +Gc5_31 0 n10 ns31 0 -0.00108629000999 +Gc5_32 0 n10 ns32 0 0.000358751307443 +Gc5_33 0 n10 ns33 0 0.000895390385928 +Gc5_34 0 n10 ns34 0 -0.00177674219879 +Gc5_35 0 n10 ns35 0 -0.00390001733705 +Gc5_36 0 n10 ns36 0 -0.00261906151116 +Gc5_37 0 n10 ns37 0 5.16735872133e-005 +Gc5_38 0 n10 ns38 0 9.18807287274e-005 +Gc5_39 0 n10 ns39 0 0.000879434648972 +Gc5_40 0 n10 ns40 0 0.00585601238305 +Gc5_41 0 n10 ns41 0 -0.000930958386058 +Gc5_42 0 n10 ns42 0 0.000239794574287 +Gc5_43 0 n10 ns43 0 0.00260722033259 +Gc5_44 0 n10 ns44 0 -0.000653306607343 +Gc5_45 0 n10 ns45 0 -0.00200057922051 +Gc5_46 0 n10 ns46 0 0.00107380950459 +Gc5_47 0 n10 ns47 0 -0.000248820385256 +Gc5_48 0 n10 ns48 0 -0.000404133437692 +Gc5_49 0 n10 ns49 0 0.000399645421425 +Gc5_50 0 n10 ns50 0 -0.00290064458254 +Gc5_51 0 n10 ns51 0 -0.00284377615453 +Gc5_52 0 n10 ns52 0 0.0039039308066 +Gc5_53 0 n10 ns53 0 0.00260988422708 +Gc5_54 0 n10 ns54 0 -5.34183279733e-005 +Gc5_55 0 n10 ns55 0 -6.83840165464e-005 +Gc5_56 0 n10 ns56 0 -0.000973396045303 +Gc5_57 0 n10 ns57 0 -0.00575339204004 +Gc5_58 0 n10 ns58 0 0.000302568671547 +Gc5_59 0 n10 ns59 0 -1.17903364681e-006 +Gc5_60 0 n10 ns60 0 -0.000882990682922 +Gc5_61 0 n10 ns61 0 0.000176439765531 +Gc5_62 0 n10 ns62 0 0.00178033425252 +Gc5_63 0 n10 ns63 0 -0.000989330974953 +Gc5_64 0 n10 ns64 0 7.22766230437e-006 +Gc5_65 0 n10 ns65 0 0.000261179154662 +Gc5_66 0 n10 ns66 0 -0.000299823929532 +Gc5_67 0 n10 ns67 0 -0.00888074240486 +Gc5_68 0 n10 ns68 0 -0.00391947564861 +Gc5_69 0 n10 ns69 0 0.00398010502343 +Gc5_70 0 n10 ns70 0 0.00279979458653 +Gc5_71 0 n10 ns71 0 9.39651679057e-005 +Gc5_72 0 n10 ns72 0 1.05254402347e-005 +Gc5_73 0 n10 ns73 0 0.00724771533336 +Gc5_74 0 n10 ns74 0 0.00622906733063 +Gc5_75 0 n10 ns75 0 0.000158626799084 +Gc5_76 0 n10 ns76 0 0.00037642577982 +Gc5_77 0 n10 ns77 0 0.001064217582 +Gc5_78 0 n10 ns78 0 -0.000655558204203 +Gc5_79 0 n10 ns79 0 0.00164857061048 +Gc5_80 0 n10 ns80 0 -0.000823277606031 +Gc5_81 0 n10 ns81 0 -0.00270165069149 +Gc5_82 0 n10 ns82 0 0.00103629968097 +Gc5_83 0 n10 ns83 0 -0.000758783189292 +Gc5_84 0 n10 ns84 0 0.0129451278251 +Gc5_85 0 n10 ns85 0 0.0268535261318 +Gc5_86 0 n10 ns86 0 0.00392410118284 +Gc5_87 0 n10 ns87 0 0.00264954190592 +Gc5_88 0 n10 ns88 0 -4.90987375894e-005 +Gc5_89 0 n10 ns89 0 -8.51507771409e-005 +Gc5_90 0 n10 ns90 0 -0.00569638828969 +Gc5_91 0 n10 ns91 0 -0.000998420729346 +Gc5_92 0 n10 ns92 0 -0.000691473748546 +Gc5_93 0 n10 ns93 0 0.000443144119823 +Gc5_94 0 n10 ns94 0 0.00014008367566 +Gc5_95 0 n10 ns95 0 -0.000348506002202 +Gc5_96 0 n10 ns96 0 0.00184739130592 +Gc5_97 0 n10 ns97 0 -0.000924028148842 +Gc5_98 0 n10 ns98 0 6.99091336454e-005 +Gc5_99 0 n10 ns99 0 0.000388866745319 +Gc5_100 0 n10 ns100 0 -0.000300862126223 +Gc5_101 0 n10 ns101 0 -0.00959417623022 +Gc5_102 0 n10 ns102 0 -0.0041812603301 +Gd5_1 0 n10 ni1 0 -0.00065396783097 +Gd5_2 0 n10 ni2 0 0.000205798143124 +Gd5_3 0 n10 ni3 0 -0.00114898909309 +Gd5_4 0 n10 ni4 0 -0.00361089448055 +Gd5_5 0 n10 ni5 0 0.00586248923198 +Gd5_6 0 n10 ni6 0 -0.00391540357803 +Gc6_1 0 n12 ns1 0 -0.00393176971649 +Gc6_2 0 n12 ns2 0 -0.00298271773605 +Gc6_3 0 n12 ns3 0 -0.000171734467872 +Gc6_4 0 n12 ns4 0 3.55973439268e-005 +Gc6_5 0 n12 ns5 0 -0.00987667945595 +Gc6_6 0 n12 ns6 0 -0.00367633067221 +Gc6_7 0 n12 ns7 0 -0.00226292338666 +Gc6_8 0 n12 ns8 0 0.000822694042121 +Gc6_9 0 n12 ns9 0 -0.000740471960424 +Gc6_10 0 n12 ns10 0 -7.60192364142e-005 +Gc6_11 0 n12 ns11 0 -0.00195178526643 +Gc6_12 0 n12 ns12 0 0.000938986111094 +Gc6_13 0 n12 ns13 0 0.000522480511629 +Gc6_14 0 n12 ns14 0 -0.000845033252427 +Gc6_15 0 n12 ns15 0 0.000200225159748 +Gc6_16 0 n12 ns16 0 -0.000372389282007 +Gc6_17 0 n12 ns17 0 -0.0028004857715 +Gc6_18 0 n12 ns18 0 -0.00392139959382 +Gc6_19 0 n12 ns19 0 -0.00265038233597 +Gc6_20 0 n12 ns20 0 4.85060465952e-005 +Gc6_21 0 n12 ns21 0 0.000116881451011 +Gc6_22 0 n12 ns22 0 0.00556557386845 +Gc6_23 0 n12 ns23 0 0.00113013500731 +Gc6_24 0 n12 ns24 0 0.00172486712654 +Gc6_25 0 n12 ns25 0 -0.000519913155647 +Gc6_26 0 n12 ns26 0 -0.000147874940027 +Gc6_27 0 n12 ns27 0 0.00024763112277 +Gc6_28 0 n12 ns28 0 -0.00190169733016 +Gc6_29 0 n12 ns29 0 0.000889245875587 +Gc6_30 0 n12 ns30 0 -0.000403212868876 +Gc6_31 0 n12 ns31 0 -0.000688323105799 +Gc6_32 0 n12 ns32 0 0.00131757210314 +Gc6_33 0 n12 ns33 0 -0.000789647288891 +Gc6_34 0 n12 ns34 0 -0.00288886449856 +Gc6_35 0 n12 ns35 0 -0.00390321494329 +Gc6_36 0 n12 ns36 0 -0.00262275164755 +Gc6_37 0 n12 ns37 0 5.00708519682e-005 +Gc6_38 0 n12 ns38 0 0.00011567991444 +Gc6_39 0 n12 ns39 0 0.00338001716432 +Gc6_40 0 n12 ns40 0 0.00331288644021 +Gc6_41 0 n12 ns41 0 0.000840494082442 +Gc6_42 0 n12 ns42 0 9.26244746186e-005 +Gc6_43 0 n12 ns43 0 0.000374359032193 +Gc6_44 0 n12 ns44 0 -0.000337588142642 +Gc6_45 0 n12 ns45 0 -0.00215920672058 +Gc6_46 0 n12 ns46 0 0.00118915020617 +Gc6_47 0 n12 ns47 0 -0.000372182347953 +Gc6_48 0 n12 ns48 0 -0.000568887767056 +Gc6_49 0 n12 ns49 0 0.000169142305111 +Gc6_50 0 n12 ns50 0 -0.00224393812507 +Gc6_51 0 n12 ns51 0 -0.00256590250897 +Gc6_52 0 n12 ns52 0 0.00391083246264 +Gc6_53 0 n12 ns53 0 0.00262218309021 +Gc6_54 0 n12 ns54 0 -5.2190956107e-005 +Gc6_55 0 n12 ns55 0 -8.29167667891e-005 +Gc6_56 0 n12 ns56 0 -0.00351488553098 +Gc6_57 0 n12 ns57 0 -0.0031892830617 +Gc6_58 0 n12 ns58 0 -0.000600306676147 +Gc6_59 0 n12 ns59 0 0.00021587915483 +Gc6_60 0 n12 ns60 0 -0.000106243275088 +Gc6_61 0 n12 ns61 0 -1.43432950014e-005 +Gc6_62 0 n12 ns62 0 0.00191626126837 +Gc6_63 0 n12 ns63 0 -0.00109385147297 +Gc6_64 0 n12 ns64 0 4.43445807851e-005 +Gc6_65 0 n12 ns65 0 0.00025907631517 +Gc6_66 0 n12 ns66 0 -0.000371097643294 +Gc6_67 0 n12 ns67 0 -0.0091055920376 +Gc6_68 0 n12 ns68 0 -0.00378801036707 +Gc6_69 0 n12 ns69 0 0.00393286820568 +Gc6_70 0 n12 ns70 0 0.00264879512121 +Gc6_71 0 n12 ns71 0 -5.27952050848e-005 +Gc6_72 0 n12 ns72 0 -7.59088593138e-005 +Gc6_73 0 n12 ns73 0 -0.00571055427278 +Gc6_74 0 n12 ns74 0 -0.000991841357523 +Gc6_75 0 n12 ns75 0 -0.00068689622063 +Gc6_76 0 n12 ns76 0 0.000440319369841 +Gc6_77 0 n12 ns77 0 0.000135806316493 +Gc6_78 0 n12 ns78 0 -0.000345488023743 +Gc6_79 0 n12 ns79 0 0.00184714486396 +Gc6_80 0 n12 ns80 0 -0.00092351316395 +Gc6_81 0 n12 ns81 0 7.19328943473e-005 +Gc6_82 0 n12 ns82 0 0.000386672761301 +Gc6_83 0 n12 ns83 0 -0.000300369868961 +Gc6_84 0 n12 ns84 0 -0.00958716201513 +Gc6_85 0 n12 ns85 0 -0.00417717177721 +Gc6_86 0 n12 ns86 0 0.00398497409904 +Gc6_87 0 n12 ns87 0 0.00282091752732 +Gc6_88 0 n12 ns88 0 8.84230800701e-005 +Gc6_89 0 n12 ns89 0 3.68136263438e-005 +Gc6_90 0 n12 ns90 0 0.00968737429746 +Gc6_91 0 n12 ns91 0 0.00376727056409 +Gc6_92 0 n12 ns92 0 0.00131351589556 +Gc6_93 0 n12 ns93 0 -7.37217070876e-005 +Gc6_94 0 n12 ns94 0 5.88655290914e-005 +Gc6_95 0 n12 ns95 0 -0.000337878797409 +Gc6_96 0 n12 ns96 0 0.00195727767836 +Gc6_97 0 n12 ns97 0 -0.00102414450744 +Gc6_98 0 n12 ns98 0 -0.00258969030042 +Gc6_99 0 n12 ns99 0 0.000961734594223 +Gc6_100 0 n12 ns100 0 -0.00098399594007 +Gc6_101 0 n12 ns101 0 0.0124740335168 +Gc6_102 0 n12 ns102 0 0.0275001711235 +Gd6_1 0 n12 ni1 0 -0.000355392881955 +Gd6_2 0 n12 ni2 0 -0.000108590139182 +Gd6_3 0 n12 ni3 0 -0.00110190827607 +Gd6_4 0 n12 ni4 0 -0.00377117766446 +Gd6_5 0 n12 ni5 0 -0.00391216075928 +Gd6_6 0 n12 ni6 0 0.00550848807921 +.ends + + + + +.subckt 744833052100 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ca2 ns2 0 1e-012 +Ra1 ns1 0 3585.43634301 +Ra2 ns2 0 3585.43634301 +Ga1 ns1 0 ns2 0 -0.000459429215964 +Ga2 ns2 0 ns1 0 0.000459429215964 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 2510.12252977 +Ca4 ns4 0 1e-012 +Ca5 ns5 0 1e-012 +Ra4 ns4 0 187190.790845 +Ra5 ns5 0 187190.790845 +Ga4 ns4 0 ns5 0 -0.000287692890348 +Ga5 ns5 0 ns4 0 0.000287692890348 +Ca6 ns6 0 1e-012 +Ca7 ns7 0 1e-012 +Ra6 ns6 0 30992.4817434 +Ra7 ns7 0 30992.4817434 +Ga6 ns6 0 ns7 0 -0.00024157017528 +Ga7 ns7 0 ns6 0 0.00024157017528 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 36739.2101294 +Ra9 ns9 0 36739.2101294 +Ga8 ns8 0 ns9 0 -0.000191846748352 +Ga9 ns9 0 ns8 0 0.000191846748352 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 37288.2844594 +Ra11 ns11 0 37288.2844594 +Ga10 ns10 0 ns11 0 -0.000183341128367 +Ga11 ns11 0 ns10 0 0.000183341128367 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 162152.731673 +Ra13 ns13 0 162152.731673 +Ga12 ns12 0 ns13 0 -2.45005262475e-005 +Ga13 ns13 0 ns12 0 2.45005262475e-005 +Ca14 ns14 0 1e-012 +Ra14 ns14 0 138029.726403 +Ca15 ns15 0 1e-012 +Ra15 ns15 0 183954.067888 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 413085.353113 +Ra17 ns17 0 413085.353113 +Ga16 ns16 0 ns17 0 -3.17051228078e-006 +Ga17 ns17 0 ns16 0 3.17051228078e-006 +Ca18 ns18 0 1e-012 +Ra18 ns18 0 729804.836139 +Ca19 ns19 0 1e-012 +Ra19 ns19 0 4934731.06052 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 74339016.1265 +Ra21 ns21 0 74339016.1265 +Ga20 ns20 0 ns21 0 -2.24810155777e-008 +Ga21 ns21 0 ns20 0 2.24810155777e-008 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 3585.43634301 +Ra23 ns23 0 3585.43634301 +Ga22 ns22 0 ns23 0 -0.000459429215964 +Ga23 ns23 0 ns22 0 0.000459429215964 +Ca24 ns24 0 1e-012 +Ra24 ns24 0 2510.12252977 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 187190.790845 +Ra26 ns26 0 187190.790845 +Ga25 ns25 0 ns26 0 -0.000287692890348 +Ga26 ns26 0 ns25 0 0.000287692890348 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 30992.4817434 +Ra28 ns28 0 30992.4817434 +Ga27 ns27 0 ns28 0 -0.00024157017528 +Ga28 ns28 0 ns27 0 0.00024157017528 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 36739.2101294 +Ra30 ns30 0 36739.2101294 +Ga29 ns29 0 ns30 0 -0.000191846748352 +Ga30 ns30 0 ns29 0 0.000191846748352 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 37288.2844594 +Ra32 ns32 0 37288.2844594 +Ga31 ns31 0 ns32 0 -0.000183341128367 +Ga32 ns32 0 ns31 0 0.000183341128367 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 162152.731673 +Ra34 ns34 0 162152.731673 +Ga33 ns33 0 ns34 0 -2.45005262475e-005 +Ga34 ns34 0 ns33 0 2.45005262475e-005 +Ca35 ns35 0 1e-012 +Ra35 ns35 0 138029.726403 +Ca36 ns36 0 1e-012 +Ra36 ns36 0 183954.067888 +Ca37 ns37 0 1e-012 +Ca38 ns38 0 1e-012 +Ra37 ns37 0 413085.353113 +Ra38 ns38 0 413085.353113 +Ga37 ns37 0 ns38 0 -3.17051228078e-006 +Ga38 ns38 0 ns37 0 3.17051228078e-006 +Ca39 ns39 0 1e-012 +Ra39 ns39 0 729804.836139 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 4934731.06052 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 74339016.1265 +Ra42 ns42 0 74339016.1265 +Ga41 ns41 0 ns42 0 -2.24810155777e-008 +Ga42 ns42 0 ns41 0 2.24810155777e-008 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 3585.43634301 +Ra44 ns44 0 3585.43634301 +Ga43 ns43 0 ns44 0 -0.000459429215964 +Ga44 ns44 0 ns43 0 0.000459429215964 +Ca45 ns45 0 1e-012 +Ra45 ns45 0 2510.12252977 +Ca46 ns46 0 1e-012 +Ca47 ns47 0 1e-012 +Ra46 ns46 0 187190.790845 +Ra47 ns47 0 187190.790845 +Ga46 ns46 0 ns47 0 -0.000287692890348 +Ga47 ns47 0 ns46 0 0.000287692890348 +Ca48 ns48 0 1e-012 +Ca49 ns49 0 1e-012 +Ra48 ns48 0 30992.4817434 +Ra49 ns49 0 30992.4817434 +Ga48 ns48 0 ns49 0 -0.00024157017528 +Ga49 ns49 0 ns48 0 0.00024157017528 +Ca50 ns50 0 1e-012 +Ca51 ns51 0 1e-012 +Ra50 ns50 0 36739.2101294 +Ra51 ns51 0 36739.2101294 +Ga50 ns50 0 ns51 0 -0.000191846748352 +Ga51 ns51 0 ns50 0 0.000191846748352 +Ca52 ns52 0 1e-012 +Ca53 ns53 0 1e-012 +Ra52 ns52 0 37288.2844594 +Ra53 ns53 0 37288.2844594 +Ga52 ns52 0 ns53 0 -0.000183341128367 +Ga53 ns53 0 ns52 0 0.000183341128367 +Ca54 ns54 0 1e-012 +Ca55 ns55 0 1e-012 +Ra54 ns54 0 162152.731673 +Ra55 ns55 0 162152.731673 +Ga54 ns54 0 ns55 0 -2.45005262475e-005 +Ga55 ns55 0 ns54 0 2.45005262475e-005 +Ca56 ns56 0 1e-012 +Ra56 ns56 0 138029.726403 +Ca57 ns57 0 1e-012 +Ra57 ns57 0 183954.067888 +Ca58 ns58 0 1e-012 +Ca59 ns59 0 1e-012 +Ra58 ns58 0 413085.353113 +Ra59 ns59 0 413085.353113 +Ga58 ns58 0 ns59 0 -3.17051228078e-006 +Ga59 ns59 0 ns58 0 3.17051228078e-006 +Ca60 ns60 0 1e-012 +Ra60 ns60 0 729804.836139 +Ca61 ns61 0 1e-012 +Ra61 ns61 0 4934731.06052 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 74339016.1265 +Ra63 ns63 0 74339016.1265 +Ga62 ns62 0 ns63 0 -2.24810155777e-008 +Ga63 ns63 0 ns62 0 2.24810155777e-008 +Ca64 ns64 0 1e-012 +Ca65 ns65 0 1e-012 +Ra64 ns64 0 3585.43634301 +Ra65 ns65 0 3585.43634301 +Ga64 ns64 0 ns65 0 -0.000459429215964 +Ga65 ns65 0 ns64 0 0.000459429215964 +Ca66 ns66 0 1e-012 +Ra66 ns66 0 2510.12252977 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 187190.790845 +Ra68 ns68 0 187190.790845 +Ga67 ns67 0 ns68 0 -0.000287692890348 +Ga68 ns68 0 ns67 0 0.000287692890348 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 30992.4817434 +Ra70 ns70 0 30992.4817434 +Ga69 ns69 0 ns70 0 -0.00024157017528 +Ga70 ns70 0 ns69 0 0.00024157017528 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 36739.2101294 +Ra72 ns72 0 36739.2101294 +Ga71 ns71 0 ns72 0 -0.000191846748352 +Ga72 ns72 0 ns71 0 0.000191846748352 +Ca73 ns73 0 1e-012 +Ca74 ns74 0 1e-012 +Ra73 ns73 0 37288.2844594 +Ra74 ns74 0 37288.2844594 +Ga73 ns73 0 ns74 0 -0.000183341128367 +Ga74 ns74 0 ns73 0 0.000183341128367 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 162152.731673 +Ra76 ns76 0 162152.731673 +Ga75 ns75 0 ns76 0 -2.45005262475e-005 +Ga76 ns76 0 ns75 0 2.45005262475e-005 +Ca77 ns77 0 1e-012 +Ra77 ns77 0 138029.726403 +Ca78 ns78 0 1e-012 +Ra78 ns78 0 183954.067888 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 413085.353113 +Ra80 ns80 0 413085.353113 +Ga79 ns79 0 ns80 0 -3.17051228078e-006 +Ga80 ns80 0 ns79 0 3.17051228078e-006 +Ca81 ns81 0 1e-012 +Ra81 ns81 0 729804.836139 +Ca82 ns82 0 1e-012 +Ra82 ns82 0 4934731.06052 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 74339016.1265 +Ra84 ns84 0 74339016.1265 +Ga83 ns83 0 ns84 0 -2.24810155777e-008 +Ga84 ns84 0 ns83 0 2.24810155777e-008 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 3585.43634301 +Ra86 ns86 0 3585.43634301 +Ga85 ns85 0 ns86 0 -0.000459429215964 +Ga86 ns86 0 ns85 0 0.000459429215964 +Ca87 ns87 0 1e-012 +Ra87 ns87 0 2510.12252977 +Ca88 ns88 0 1e-012 +Ca89 ns89 0 1e-012 +Ra88 ns88 0 187190.790845 +Ra89 ns89 0 187190.790845 +Ga88 ns88 0 ns89 0 -0.000287692890348 +Ga89 ns89 0 ns88 0 0.000287692890348 +Ca90 ns90 0 1e-012 +Ca91 ns91 0 1e-012 +Ra90 ns90 0 30992.4817434 +Ra91 ns91 0 30992.4817434 +Ga90 ns90 0 ns91 0 -0.00024157017528 +Ga91 ns91 0 ns90 0 0.00024157017528 +Ca92 ns92 0 1e-012 +Ca93 ns93 0 1e-012 +Ra92 ns92 0 36739.2101294 +Ra93 ns93 0 36739.2101294 +Ga92 ns92 0 ns93 0 -0.000191846748352 +Ga93 ns93 0 ns92 0 0.000191846748352 +Ca94 ns94 0 1e-012 +Ca95 ns95 0 1e-012 +Ra94 ns94 0 37288.2844594 +Ra95 ns95 0 37288.2844594 +Ga94 ns94 0 ns95 0 -0.000183341128367 +Ga95 ns95 0 ns94 0 0.000183341128367 +Ca96 ns96 0 1e-012 +Ca97 ns97 0 1e-012 +Ra96 ns96 0 162152.731673 +Ra97 ns97 0 162152.731673 +Ga96 ns96 0 ns97 0 -2.45005262475e-005 +Ga97 ns97 0 ns96 0 2.45005262475e-005 +Ca98 ns98 0 1e-012 +Ra98 ns98 0 138029.726403 +Ca99 ns99 0 1e-012 +Ra99 ns99 0 183954.067888 +Ca100 ns100 0 1e-012 +Ca101 ns101 0 1e-012 +Ra100 ns100 0 413085.353113 +Ra101 ns101 0 413085.353113 +Ga100 ns100 0 ns101 0 -3.17051228078e-006 +Ga101 ns101 0 ns100 0 3.17051228078e-006 +Ca102 ns102 0 1e-012 +Ra102 ns102 0 729804.836139 +Ca103 ns103 0 1e-012 +Ra103 ns103 0 4934731.06052 +Ca104 ns104 0 1e-012 +Ca105 ns105 0 1e-012 +Ra104 ns104 0 74339016.1265 +Ra105 ns105 0 74339016.1265 +Ga104 ns104 0 ns105 0 -2.24810155777e-008 +Ga105 ns105 0 ns104 0 2.24810155777e-008 +Ca106 ns106 0 1e-012 +Ca107 ns107 0 1e-012 +Ra106 ns106 0 3585.43634301 +Ra107 ns107 0 3585.43634301 +Ga106 ns106 0 ns107 0 -0.000459429215964 +Ga107 ns107 0 ns106 0 0.000459429215964 +Ca108 ns108 0 1e-012 +Ra108 ns108 0 2510.12252977 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 187190.790845 +Ra110 ns110 0 187190.790845 +Ga109 ns109 0 ns110 0 -0.000287692890348 +Ga110 ns110 0 ns109 0 0.000287692890348 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 30992.4817434 +Ra112 ns112 0 30992.4817434 +Ga111 ns111 0 ns112 0 -0.00024157017528 +Ga112 ns112 0 ns111 0 0.00024157017528 +Ca113 ns113 0 1e-012 +Ca114 ns114 0 1e-012 +Ra113 ns113 0 36739.2101294 +Ra114 ns114 0 36739.2101294 +Ga113 ns113 0 ns114 0 -0.000191846748352 +Ga114 ns114 0 ns113 0 0.000191846748352 +Ca115 ns115 0 1e-012 +Ca116 ns116 0 1e-012 +Ra115 ns115 0 37288.2844594 +Ra116 ns116 0 37288.2844594 +Ga115 ns115 0 ns116 0 -0.000183341128367 +Ga116 ns116 0 ns115 0 0.000183341128367 +Ca117 ns117 0 1e-012 +Ca118 ns118 0 1e-012 +Ra117 ns117 0 162152.731673 +Ra118 ns118 0 162152.731673 +Ga117 ns117 0 ns118 0 -2.45005262475e-005 +Ga118 ns118 0 ns117 0 2.45005262475e-005 +Ca119 ns119 0 1e-012 +Ra119 ns119 0 138029.726403 +Ca120 ns120 0 1e-012 +Ra120 ns120 0 183954.067888 +Ca121 ns121 0 1e-012 +Ca122 ns122 0 1e-012 +Ra121 ns121 0 413085.353113 +Ra122 ns122 0 413085.353113 +Ga121 ns121 0 ns122 0 -3.17051228078e-006 +Ga122 ns122 0 ns121 0 3.17051228078e-006 +Ca123 ns123 0 1e-012 +Ra123 ns123 0 729804.836139 +Ca124 ns124 0 1e-012 +Ra124 ns124 0 4934731.06052 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 74339016.1265 +Ra126 ns126 0 74339016.1265 +Ga125 ns125 0 ns126 0 -2.24810155777e-008 +Ga126 ns126 0 ns125 0 2.24810155777e-008 + +Gb1_1 ns1 0 ni1 0 -0.000628744965715 +Gb3_1 ns3 0 ni1 0 -0.000398386926591 +Gb4_1 ns4 0 ni1 0 -0.000287792088119 +Gb6_1 ns6 0 ni1 0 -0.000245879844892 +Gb8_1 ns8 0 ni1 0 -0.000195708514109 +Gb10_1 ns10 0 ni1 0 -0.000187263920485 +Gb12_1 ns12 0 ni1 0 -2.60528276457e-005 +Gb14_1 ns14 0 ni1 0 -7.24481621505e-006 +Gb15_1 ns15 0 ni1 0 -5.43613963792e-006 +Gb16_1 ns16 0 ni1 0 -5.0188910333e-006 +Gb18_1 ns18 0 ni1 0 -1.37022934144e-006 +Gb19_1 ns19 0 ni1 0 -2.02645288616e-007 +Gb20_1 ns20 0 ni1 0 -3.05301736366e-008 +Gb22_2 ns22 0 ni2 0 -0.000628744965715 +Gb24_2 ns24 0 ni2 0 -0.000398386926591 +Gb25_2 ns25 0 ni2 0 -0.000287792088119 +Gb27_2 ns27 0 ni2 0 -0.000245879844892 +Gb29_2 ns29 0 ni2 0 -0.000195708514109 +Gb31_2 ns31 0 ni2 0 -0.000187263920485 +Gb33_2 ns33 0 ni2 0 -2.60528276457e-005 +Gb35_2 ns35 0 ni2 0 -7.24481621505e-006 +Gb36_2 ns36 0 ni2 0 -5.43613963792e-006 +Gb37_2 ns37 0 ni2 0 -5.0188910333e-006 +Gb39_2 ns39 0 ni2 0 -1.37022934144e-006 +Gb40_2 ns40 0 ni2 0 -2.02645288616e-007 +Gb41_2 ns41 0 ni2 0 -3.05301736366e-008 +Gb43_3 ns43 0 ni3 0 -0.000628744965715 +Gb45_3 ns45 0 ni3 0 -0.000398386926591 +Gb46_3 ns46 0 ni3 0 -0.000287792088119 +Gb48_3 ns48 0 ni3 0 -0.000245879844892 +Gb50_3 ns50 0 ni3 0 -0.000195708514109 +Gb52_3 ns52 0 ni3 0 -0.000187263920485 +Gb54_3 ns54 0 ni3 0 -2.60528276457e-005 +Gb56_3 ns56 0 ni3 0 -7.24481621505e-006 +Gb57_3 ns57 0 ni3 0 -5.43613963792e-006 +Gb58_3 ns58 0 ni3 0 -5.0188910333e-006 +Gb60_3 ns60 0 ni3 0 -1.37022934144e-006 +Gb61_3 ns61 0 ni3 0 -2.02645288616e-007 +Gb62_3 ns62 0 ni3 0 -3.05301736366e-008 +Gb64_4 ns64 0 ni4 0 -0.000628744965715 +Gb66_4 ns66 0 ni4 0 -0.000398386926591 +Gb67_4 ns67 0 ni4 0 -0.000287792088119 +Gb69_4 ns69 0 ni4 0 -0.000245879844892 +Gb71_4 ns71 0 ni4 0 -0.000195708514109 +Gb73_4 ns73 0 ni4 0 -0.000187263920485 +Gb75_4 ns75 0 ni4 0 -2.60528276457e-005 +Gb77_4 ns77 0 ni4 0 -7.24481621505e-006 +Gb78_4 ns78 0 ni4 0 -5.43613963792e-006 +Gb79_4 ns79 0 ni4 0 -5.0188910333e-006 +Gb81_4 ns81 0 ni4 0 -1.37022934144e-006 +Gb82_4 ns82 0 ni4 0 -2.02645288616e-007 +Gb83_4 ns83 0 ni4 0 -3.05301736366e-008 +Gb85_5 ns85 0 ni5 0 -0.000628744965715 +Gb87_5 ns87 0 ni5 0 -0.000398386926591 +Gb88_5 ns88 0 ni5 0 -0.000287792088119 +Gb90_5 ns90 0 ni5 0 -0.000245879844892 +Gb92_5 ns92 0 ni5 0 -0.000195708514109 +Gb94_5 ns94 0 ni5 0 -0.000187263920485 +Gb96_5 ns96 0 ni5 0 -2.60528276457e-005 +Gb98_5 ns98 0 ni5 0 -7.24481621505e-006 +Gb99_5 ns99 0 ni5 0 -5.43613963792e-006 +Gb100_5 ns100 0 ni5 0 -5.0188910333e-006 +Gb102_5 ns102 0 ni5 0 -1.37022934144e-006 +Gb103_5 ns103 0 ni5 0 -2.02645288616e-007 +Gb104_5 ns104 0 ni5 0 -3.05301736366e-008 +Gb106_6 ns106 0 ni6 0 -0.000628744965715 +Gb108_6 ns108 0 ni6 0 -0.000398386926591 +Gb109_6 ns109 0 ni6 0 -0.000287792088119 +Gb111_6 ns111 0 ni6 0 -0.000245879844892 +Gb113_6 ns113 0 ni6 0 -0.000195708514109 +Gb115_6 ns115 0 ni6 0 -0.000187263920485 +Gb117_6 ns117 0 ni6 0 -2.60528276457e-005 +Gb119_6 ns119 0 ni6 0 -7.24481621505e-006 +Gb120_6 ns120 0 ni6 0 -5.43613963792e-006 +Gb121_6 ns121 0 ni6 0 -5.0188910333e-006 +Gb123_6 ns123 0 ni6 0 -1.37022934144e-006 +Gb124_6 ns124 0 ni6 0 -2.02645288616e-007 +Gb125_6 ns125 0 ni6 0 -3.05301736366e-008 + +Gc1_1 0 n2 ns1 0 -0.0100487740814 +Gc1_2 0 n2 ns2 0 -0.0112196357119 +Gc1_3 0 n2 ns3 0 0.0167674687566 +Gc1_4 0 n2 ns4 0 6.05370572453e-007 +Gc1_5 0 n2 ns5 0 5.68201760626e-007 +Gc1_6 0 n2 ns6 0 -0.000654926657836 +Gc1_7 0 n2 ns7 0 0.000879951888928 +Gc1_8 0 n2 ns8 0 3.85413052195e-006 +Gc1_9 0 n2 ns9 0 0.000246589835023 +Gc1_10 0 n2 ns10 0 -0.00183175447587 +Gc1_11 0 n2 ns11 0 0.00116492059428 +Gc1_12 0 n2 ns12 0 -2.29482467003e-006 +Gc1_13 0 n2 ns13 0 -2.91929905405e-006 +Gc1_14 0 n2 ns14 0 -0.00429664291596 +Gc1_15 0 n2 ns15 0 -0.00917832815946 +Gc1_16 0 n2 ns16 0 1.07060767259e-005 +Gc1_17 0 n2 ns17 0 -3.05214109212e-005 +Gc1_18 0 n2 ns18 0 -0.000212739501777 +Gc1_19 0 n2 ns19 0 -9.14765414437e-005 +Gc1_20 0 n2 ns20 0 -0.00158716781764 +Gc1_21 0 n2 ns21 0 -0.0004146566682 +Gc1_22 0 n2 ns22 0 0.00112348734198 +Gc1_23 0 n2 ns23 0 0.0010278349488 +Gc1_24 0 n2 ns24 0 -0.00020462056941 +Gc1_25 0 n2 ns25 0 1.19979480965e-006 +Gc1_26 0 n2 ns26 0 4.46855808009e-007 +Gc1_27 0 n2 ns27 0 -0.000851773027187 +Gc1_28 0 n2 ns28 0 0.00112238342533 +Gc1_29 0 n2 ns29 0 -0.00019822763598 +Gc1_30 0 n2 ns30 0 0.000451249064257 +Gc1_31 0 n2 ns31 0 0.000899264304536 +Gc1_32 0 n2 ns32 0 -0.000868513716285 +Gc1_33 0 n2 ns33 0 -1.22930216543e-007 +Gc1_34 0 n2 ns34 0 -3.51407602526e-006 +Gc1_35 0 n2 ns35 0 0.00278403960597 +Gc1_36 0 n2 ns36 0 0.00394883896078 +Gc1_37 0 n2 ns37 0 3.42276003127e-006 +Gc1_38 0 n2 ns38 0 1.16981873845e-006 +Gc1_39 0 n2 ns39 0 0.000115913388572 +Gc1_40 0 n2 ns40 0 2.58539545044e-005 +Gc1_41 0 n2 ns41 0 -0.00157986090467 +Gc1_42 0 n2 ns42 0 -0.000414439879992 +Gc1_43 0 n2 ns43 0 0.000757993334988 +Gc1_44 0 n2 ns44 0 0.000991298929354 +Gc1_45 0 n2 ns45 0 -0.000124364606217 +Gc1_46 0 n2 ns46 0 1.11086979921e-006 +Gc1_47 0 n2 ns47 0 4.94421937554e-007 +Gc1_48 0 n2 ns48 0 -0.000699632576247 +Gc1_49 0 n2 ns49 0 0.00109125080302 +Gc1_50 0 n2 ns50 0 0.000417028345728 +Gc1_51 0 n2 ns51 0 -0.000461679795486 +Gc1_52 0 n2 ns52 0 0.000105939607036 +Gc1_53 0 n2 ns53 0 2.14515233258e-006 +Gc1_54 0 n2 ns54 0 -9.31044854933e-008 +Gc1_55 0 n2 ns55 0 -3.42896570239e-006 +Gc1_56 0 n2 ns56 0 0.00169447967125 +Gc1_57 0 n2 ns57 0 0.00501216934744 +Gc1_58 0 n2 ns58 0 -3.05003073779e-006 +Gc1_59 0 n2 ns59 0 -1.26664243443e-006 +Gc1_60 0 n2 ns60 0 0.000120872102437 +Gc1_61 0 n2 ns61 0 2.62207688306e-005 +Gc1_62 0 n2 ns62 0 -0.00158630969029 +Gc1_63 0 n2 ns63 0 -0.000410266058305 +Gc1_64 0 n2 ns64 0 0.00157039336796 +Gc1_65 0 n2 ns65 0 0.00157266801646 +Gc1_66 0 n2 ns66 0 -0.000281189556723 +Gc1_67 0 n2 ns67 0 8.64743951046e-007 +Gc1_68 0 n2 ns68 0 6.38290645795e-007 +Gc1_69 0 n2 ns69 0 0.000793311668848 +Gc1_70 0 n2 ns70 0 -0.0011568192917 +Gc1_71 0 n2 ns71 0 -0.000498452311316 +Gc1_72 0 n2 ns72 0 0.000744278993472 +Gc1_73 0 n2 ns73 0 -0.000542532321753 +Gc1_74 0 n2 ns74 0 1.60943203705e-007 +Gc1_75 0 n2 ns75 0 -4.63480615138e-006 +Gc1_76 0 n2 ns76 0 1.17327627153e-006 +Gc1_77 0 n2 ns77 0 -0.00181861449665 +Gc1_78 0 n2 ns78 0 -0.0049155119156 +Gc1_79 0 n2 ns79 0 1.21668668458e-005 +Gc1_80 0 n2 ns80 0 9.33881842486e-006 +Gc1_81 0 n2 ns81 0 -0.000122952654465 +Gc1_82 0 n2 ns82 0 -2.46876402315e-005 +Gc1_83 0 n2 ns83 0 0.00158732810931 +Gc1_84 0 n2 ns84 0 0.00040828615337 +Gc1_85 0 n2 ns85 0 0.00201148704877 +Gc1_86 0 n2 ns86 0 0.00204314288992 +Gc1_87 0 n2 ns87 0 0.000223200864934 +Gc1_88 0 n2 ns88 0 7.89660305514e-007 +Gc1_89 0 n2 ns89 0 5.53921346944e-007 +Gc1_90 0 n2 ns90 0 0.000934317828832 +Gc1_91 0 n2 ns91 0 -0.00108412860782 +Gc1_92 0 n2 ns92 0 0.000527739820931 +Gc1_93 0 n2 ns93 0 -0.000601154073538 +Gc1_94 0 n2 ns94 0 -0.00148460138811 +Gc1_95 0 n2 ns95 0 0.00107565520479 +Gc1_96 0 n2 ns96 0 -5.40136559784e-006 +Gc1_97 0 n2 ns97 0 1.08381291662e-006 +Gc1_98 0 n2 ns98 0 -0.00293064271221 +Gc1_99 0 n2 ns99 0 -0.003825642925 +Gc1_100 0 n2 ns100 0 8.38502603989e-006 +Gc1_101 0 n2 ns101 0 8.37863888963e-006 +Gc1_102 0 n2 ns102 0 -0.000116136402945 +Gc1_103 0 n2 ns103 0 -2.47271089134e-005 +Gc1_104 0 n2 ns104 0 0.00158121681034 +Gc1_105 0 n2 ns105 0 0.000410354584407 +Gc1_106 0 n2 ns106 0 0.0120082710445 +Gc1_107 0 n2 ns107 0 0.00259708621607 +Gc1_108 0 n2 ns108 0 -0.00587018439056 +Gc1_109 0 n2 ns109 0 6.716523552e-007 +Gc1_110 0 n2 ns110 0 8.0263776266e-007 +Gc1_111 0 n2 ns111 0 0.000647685568565 +Gc1_112 0 n2 ns112 0 -0.00080071593984 +Gc1_113 0 n2 ns113 0 0.000162324603218 +Gc1_114 0 n2 ns114 0 -0.000293211000044 +Gc1_115 0 n2 ns115 0 0.00259165327131 +Gc1_116 0 n2 ns116 0 -0.00164637194678 +Gc1_117 0 n2 ns117 0 -2.60486325187e-006 +Gc1_118 0 n2 ns118 0 -2.1268956972e-006 +Gc1_119 0 n2 ns119 0 0.00432257874134 +Gc1_120 0 n2 ns120 0 0.00915710887587 +Gc1_121 0 n2 ns121 0 -1.06691388815e-005 +Gc1_122 0 n2 ns122 0 -1.60479763848e-005 +Gc1_123 0 n2 ns123 0 0.00020358611912 +Gc1_124 0 n2 ns124 0 9.44879446901e-005 +Gc1_125 0 n2 ns125 0 0.00158895253394 +Gc1_126 0 n2 ns126 0 0.000412870019882 +Gd1_1 0 n2 ni1 0 0.00114463549377 +Gd1_2 0 n2 ni2 0 0.00102260186966 +Gd1_3 0 n2 ni3 0 0.00108180126162 +Gd1_4 0 n2 ni4 0 0.000787658281495 +Gd1_5 0 n2 ni5 0 0.00027530816533 +Gd1_6 0 n2 ni6 0 -0.0024864375604 +Gc2_1 0 n4 ns1 0 0.00111325883879 +Gc2_2 0 n4 ns2 0 0.00101814357689 +Gc2_3 0 n4 ns3 0 -0.000218474843647 +Gc2_4 0 n4 ns4 0 1.19307056231e-006 +Gc2_5 0 n4 ns5 0 4.33109208575e-007 +Gc2_6 0 n4 ns6 0 -0.000851401313264 +Gc2_7 0 n4 ns7 0 0.00112166804638 +Gc2_8 0 n4 ns8 0 -0.000198336485124 +Gc2_9 0 n4 ns9 0 0.000449422789941 +Gc2_10 0 n4 ns10 0 0.000898496597794 +Gc2_11 0 n4 ns11 0 -0.000866387430122 +Gc2_12 0 n4 ns12 0 -1.69741622897e-007 +Gc2_13 0 n4 ns13 0 -3.18407975754e-006 +Gc2_14 0 n4 ns14 0 0.00278369611661 +Gc2_15 0 n4 ns15 0 0.00394855805691 +Gc2_16 0 n4 ns16 0 3.35065346414e-006 +Gc2_17 0 n4 ns17 0 1.26315312502e-006 +Gc2_18 0 n4 ns18 0 0.000115628107293 +Gc2_19 0 n4 ns19 0 2.64425757003e-005 +Gc2_20 0 n4 ns20 0 -0.00158235810686 +Gc2_21 0 n4 ns21 0 -0.000411831240637 +Gc2_22 0 n4 ns22 0 -0.00982474419548 +Gc2_23 0 n4 ns23 0 -0.011933856924 +Gc2_24 0 n4 ns24 0 0.0157878428029 +Gc2_25 0 n4 ns25 0 9.29788175242e-007 +Gc2_26 0 n4 ns26 0 3.57889499862e-007 +Gc2_27 0 n4 ns27 0 -0.00111762960402 +Gc2_28 0 n4 ns28 0 0.00139239268175 +Gc2_29 0 n4 ns29 0 -0.000768045067027 +Gc2_30 0 n4 ns30 0 0.000569317220593 +Gc2_31 0 n4 ns31 0 -0.000572160245679 +Gc2_32 0 n4 ns32 0 0.000468035988696 +Gc2_33 0 n4 ns33 0 -5.0758779335e-006 +Gc2_34 0 n4 ns34 0 2.28203503541e-006 +Gc2_35 0 n4 ns35 0 -0.0055453512158 +Gc2_36 0 n4 ns36 0 -0.00803410092753 +Gc2_37 0 n4 ns37 0 4.26658449306e-005 +Gc2_38 0 n4 ns38 0 -7.30693160776e-005 +Gc2_39 0 n4 ns39 0 -0.000168701374525 +Gc2_40 0 n4 ns40 0 -0.000100496075043 +Gc2_41 0 n4 ns41 0 -0.00157155961161 +Gc2_42 0 n4 ns42 0 -0.000412746307874 +Gc2_43 0 n4 ns43 0 0.000715015143173 +Gc2_44 0 n4 ns44 0 0.00112433429049 +Gc2_45 0 n4 ns45 0 -7.95337155632e-005 +Gc2_46 0 n4 ns46 0 1.26323013887e-006 +Gc2_47 0 n4 ns47 0 4.56315104962e-007 +Gc2_48 0 n4 ns48 0 -0.000922763010981 +Gc2_49 0 n4 ns49 0 0.00136905797666 +Gc2_50 0 n4 ns50 0 0.00107112252387 +Gc2_51 0 n4 ns51 0 -0.00067428887241 +Gc2_52 0 n4 ns52 0 -0.000155656784465 +Gc2_53 0 n4 ns53 0 -8.32781552234e-005 +Gc2_54 0 n4 ns54 0 2.90893690524e-007 +Gc2_55 0 n4 ns55 0 -3.91114665981e-006 +Gc2_56 0 n4 ns56 0 0.00325281980202 +Gc2_57 0 n4 ns57 0 0.00346342844939 +Gc2_58 0 n4 ns58 0 6.94876633589e-006 +Gc2_59 0 n4 ns59 0 -1.67514901425e-006 +Gc2_60 0 n4 ns60 0 0.000122266367483 +Gc2_61 0 n4 ns61 0 2.66402919338e-005 +Gc2_62 0 n4 ns62 0 -0.0015956448118 +Gc2_63 0 n4 ns63 0 -0.000418306301517 +Gc2_64 0 n4 ns64 0 0.00211402852088 +Gc2_65 0 n4 ns65 0 0.00184775187064 +Gc2_66 0 n4 ns66 0 1.95876893174e-005 +Gc2_67 0 n4 ns67 0 9.10586242235e-007 +Gc2_68 0 n4 ns68 0 6.95785467081e-007 +Gc2_69 0 n4 ns69 0 0.00103775793664 +Gc2_70 0 n4 ns70 0 -0.00145772905781 +Gc2_71 0 n4 ns71 0 -0.00148769526298 +Gc2_72 0 n4 ns72 0 0.00101944767405 +Gc2_73 0 n4 ns73 0 0.000295952449459 +Gc2_74 0 n4 ns74 0 -9.90647240199e-005 +Gc2_75 0 n4 ns75 0 -5.6144522369e-006 +Gc2_76 0 n4 ns76 0 9.69812533883e-007 +Gc2_77 0 n4 ns77 0 -0.00340597110192 +Gc2_78 0 n4 ns78 0 -0.00334741172212 +Gc2_79 0 n4 ns79 0 1.2449105725e-005 +Gc2_80 0 n4 ns80 0 1.0144892251e-005 +Gc2_81 0 n4 ns81 0 -0.000116708833535 +Gc2_82 0 n4 ns82 0 -2.68347571454e-005 +Gc2_83 0 n4 ns83 0 0.00159742492219 +Gc2_84 0 n4 ns84 0 0.000414420836345 +Gc2_85 0 n4 ns85 0 0.0122114858203 +Gc2_86 0 n4 ns86 0 0.00357365631376 +Gc2_87 0 n4 ns87 0 -0.00461181251716 +Gc2_88 0 n4 ns88 0 9.0536502516e-007 +Gc2_89 0 n4 ns89 0 8.98932637129e-007 +Gc2_90 0 n4 ns90 0 0.00121016033499 +Gc2_91 0 n4 ns91 0 -0.00136511033709 +Gc2_92 0 n4 ns92 0 0.00145908189446 +Gc2_93 0 n4 ns93 0 -0.000799528321569 +Gc2_94 0 n4 ns94 0 0.000694117596782 +Gc2_95 0 n4 ns95 0 -0.000753464580204 +Gc2_96 0 n4 ns96 0 -2.60774531703e-006 +Gc2_97 0 n4 ns97 0 -1.69491789786e-006 +Gc2_98 0 n4 ns98 0 0.00602033704413 +Gc2_99 0 n4 ns99 0 0.00735414481139 +Gc2_100 0 n4 ns100 0 3.21963648476e-005 +Gc2_101 0 n4 ns101 0 -5.63926493721e-005 +Gc2_102 0 n4 ns102 0 0.000243145068946 +Gc2_103 0 n4 ns103 0 8.96224415877e-005 +Gc2_104 0 n4 ns104 0 0.00157466229179 +Gc2_105 0 n4 ns105 0 0.000409762435562 +Gc2_106 0 n4 ns106 0 0.00166870693668 +Gc2_107 0 n4 ns107 0 0.00177451297868 +Gc2_108 0 n4 ns108 0 -1.97158837473e-005 +Gc2_109 0 n4 ns109 0 9.28179984674e-007 +Gc2_110 0 n4 ns110 0 6.4443756196e-007 +Gc2_111 0 n4 ns111 0 0.000841024640333 +Gc2_112 0 n4 ns112 0 -0.00100491598268 +Gc2_113 0 n4 ns113 0 0.000373870334886 +Gc2_114 0 n4 ns114 0 -0.0004933961128 +Gc2_115 0 n4 ns115 0 -0.00146216698406 +Gc2_116 0 n4 ns116 0 0.00105222388448 +Gc2_117 0 n4 ns117 0 -5.25499259068e-006 +Gc2_118 0 n4 ns118 0 1.21949081357e-006 +Gc2_119 0 n4 ns119 0 -0.00290480554757 +Gc2_120 0 n4 ns120 0 -0.00385969192908 +Gc2_121 0 n4 ns121 0 6.79753550801e-006 +Gc2_122 0 n4 ns122 0 7.16526995772e-006 +Gc2_123 0 n4 ns123 0 -0.000114291665506 +Gc2_124 0 n4 ns124 0 -2.64914552798e-005 +Gc2_125 0 n4 ns125 0 0.00158180779136 +Gc2_126 0 n4 ns126 0 0.000413770373173 +Gd2_1 0 n4 ni1 0 0.00103262690539 +Gd2_2 0 n4 ni2 0 0.00141155481399 +Gd2_3 0 n4 ni3 0 0.00113215460901 +Gd2_4 0 n4 ni4 0 0.000306514940537 +Gd2_5 0 n4 ni5 0 -0.00305700800989 +Gd2_6 0 n4 ni6 0 0.000658242167747 +Gc3_1 0 n6 ns1 0 0.00074562820688 +Gc3_2 0 n6 ns2 0 0.000980297831186 +Gc3_3 0 n6 ns3 0 -0.000141322603902 +Gc3_4 0 n6 ns4 0 1.10856989598e-006 +Gc3_5 0 n6 ns5 0 4.78119478786e-007 +Gc3_6 0 n6 ns6 0 -0.000699325914613 +Gc3_7 0 n6 ns7 0 0.00109046794145 +Gc3_8 0 n6 ns8 0 0.000416478512471 +Gc3_9 0 n6 ns9 0 -0.000462827821092 +Gc3_10 0 n6 ns10 0 0.0001055759656 +Gc3_11 0 n6 ns11 0 3.58680272396e-006 +Gc3_12 0 n6 ns12 0 -9.38034634872e-008 +Gc3_13 0 n6 ns13 0 -3.11678886881e-006 +Gc3_14 0 n6 ns14 0 0.00169756469561 +Gc3_15 0 n6 ns15 0 0.00500839786421 +Gc3_16 0 n6 ns16 0 -3.20352118839e-006 +Gc3_17 0 n6 ns17 0 -1.57312259358e-006 +Gc3_18 0 n6 ns18 0 0.000120560708685 +Gc3_19 0 n6 ns19 0 2.67938625129e-005 +Gc3_20 0 n6 ns20 0 -0.00158914324444 +Gc3_21 0 n6 ns21 0 -0.00041170443064 +Gc3_22 0 n6 ns22 0 0.000704952880256 +Gc3_23 0 n6 ns23 0 0.00111663272288 +Gc3_24 0 n6 ns24 0 -9.20120861047e-005 +Gc3_25 0 n6 ns25 0 1.26308982929e-006 +Gc3_26 0 n6 ns26 0 4.51754789712e-007 +Gc3_27 0 n6 ns27 0 -0.00092213697194 +Gc3_28 0 n6 ns28 0 0.00136826860735 +Gc3_29 0 n6 ns29 0 0.00107144865005 +Gc3_30 0 n6 ns30 0 -0.000675254915825 +Gc3_31 0 n6 ns31 0 -0.000156732537743 +Gc3_32 0 n6 ns32 0 -8.21639422914e-005 +Gc3_33 0 n6 ns33 0 1.78078838197e-007 +Gc3_34 0 n6 ns34 0 -3.39301595404e-006 +Gc3_35 0 n6 ns35 0 0.00327133498525 +Gc3_36 0 n6 ns36 0 0.00343951386118 +Gc3_37 0 n6 ns37 0 7.75397888796e-006 +Gc3_38 0 n6 ns38 0 -4.54557074754e-006 +Gc3_39 0 n6 ns39 0 0.000123763995409 +Gc3_40 0 n6 ns40 0 2.70571308832e-005 +Gc3_41 0 n6 ns41 0 -0.00159853821903 +Gc3_42 0 n6 ns42 0 -0.00041934951021 +Gc3_43 0 n6 ns43 0 -0.00861835238883 +Gc3_44 0 n6 ns44 0 -0.0100870667394 +Gc3_45 0 n6 ns45 0 0.0180396791949 +Gc3_46 0 n6 ns46 0 6.21746020259e-007 +Gc3_47 0 n6 ns47 0 8.53892772745e-007 +Gc3_48 0 n6 ns48 0 -0.000749108145585 +Gc3_49 0 n6 ns49 0 0.00130361541543 +Gc3_50 0 n6 ns50 0 -0.00102937214844 +Gc3_51 0 n6 ns51 0 0.000854685650346 +Gc3_52 0 n6 ns52 0 -5.24894476957e-005 +Gc3_53 0 n6 ns53 0 -5.22739099319e-005 +Gc3_54 0 n6 ns54 0 -4.33453704069e-006 +Gc3_55 0 n6 ns55 0 3.03801236881e-006 +Gc3_56 0 n6 ns56 0 -0.00453838671518 +Gc3_57 0 n6 ns57 0 -0.00897135957262 +Gc3_58 0 n6 ns58 0 2.58228954736e-005 +Gc3_59 0 n6 ns59 0 -6.18243578537e-005 +Gc3_60 0 n6 ns60 0 -0.000193270919886 +Gc3_61 0 n6 ns61 0 -9.65814946442e-005 +Gc3_62 0 n6 ns62 0 -0.00158129210836 +Gc3_63 0 n6 ns63 0 -0.000402158686002 +Gc3_64 0 n6 ns64 0 0.0119185670128 +Gc3_65 0 n6 ns65 0 0.00169425173658 +Gc3_66 0 n6 ns66 0 -0.00744514434734 +Gc3_67 0 n6 ns67 0 8.92332798537e-007 +Gc3_68 0 n6 ns68 0 3.49203624087e-007 +Gc3_69 0 n6 ns69 0 0.000846146194091 +Gc3_70 0 n6 ns70 0 -0.00140884927951 +Gc3_71 0 n6 ns71 0 0.00183181072751 +Gc3_72 0 n6 ns72 0 -0.0012319941976 +Gc3_73 0 n6 ns73 0 -7.40594634765e-005 +Gc3_74 0 n6 ns74 0 -7.85343147878e-006 +Gc3_75 0 n6 ns75 0 -3.13255400893e-006 +Gc3_76 0 n6 ns76 0 -1.57910805684e-006 +Gc3_77 0 n6 ns77 0 0.00491325619609 +Gc3_78 0 n6 ns78 0 0.0084844385453 +Gc3_79 0 n6 ns79 0 5.96638560789e-006 +Gc3_80 0 n6 ns80 0 -4.30280011347e-005 +Gc3_81 0 n6 ns81 0 0.000226302609891 +Gc3_82 0 n6 ns82 0 9.4343349746e-005 +Gc3_83 0 n6 ns83 0 0.00157906903987 +Gc3_84 0 n6 ns84 0 0.000409747001686 +Gc3_85 0 n6 ns85 0 0.00134107655703 +Gc3_86 0 n6 ns86 0 0.00156653641545 +Gc3_87 0 n6 ns87 0 -4.6841485107e-005 +Gc3_88 0 n6 ns88 0 9.82712923166e-007 +Gc3_89 0 n6 ns89 0 7.06410988677e-007 +Gc3_90 0 n6 ns90 0 0.00101302192192 +Gc3_91 0 n6 ns91 0 -0.00132652721397 +Gc3_92 0 n6 ns92 0 -0.00152369738662 +Gc3_93 0 n6 ns93 0 0.000999960780685 +Gc3_94 0 n6 ns94 0 0.000133821057323 +Gc3_95 0 n6 ns95 0 9.95276130835e-007 +Gc3_96 0 n6 ns96 0 -5.44566537408e-006 +Gc3_97 0 n6 ns97 0 1.31961119146e-006 +Gc3_98 0 n6 ns98 0 -0.00336173993106 +Gc3_99 0 n6 ns99 0 -0.00340704795352 +Gc3_100 0 n6 ns100 0 1.2049628032e-005 +Gc3_101 0 n6 ns101 0 5.30174433568e-006 +Gc3_102 0 n6 ns102 0 -0.000112754464285 +Gc3_103 0 n6 ns103 0 -2.91307486636e-005 +Gc3_104 0 n6 ns104 0 0.00159921806954 +Gc3_105 0 n6 ns105 0 0.00042240485984 +Gc3_106 0 n6 ns106 0 0.00142926629676 +Gc3_107 0 n6 ns107 0 0.00192719350748 +Gc3_108 0 n6 ns108 0 0.000335699476078 +Gc3_109 0 n6 ns109 0 8.73678943558e-007 +Gc3_110 0 n6 ns110 0 5.70265124745e-007 +Gc3_111 0 n6 ns111 0 0.000697098941048 +Gc3_112 0 n6 ns112 0 -0.000977796727187 +Gc3_113 0 n6 ns113 0 -0.000334449144857 +Gc3_114 0 n6 ns114 0 0.000608040212361 +Gc3_115 0 n6 ns115 0 -0.000243919497991 +Gc3_116 0 n6 ns116 0 -0.000137551755072 +Gc3_117 0 n6 ns117 0 -5.20405378457e-006 +Gc3_118 0 n6 ns118 0 1.23377646596e-006 +Gc3_119 0 n6 ns119 0 -0.00182431988345 +Gc3_120 0 n6 ns120 0 -0.00490265044399 +Gc3_121 0 n6 ns121 0 1.08084073114e-005 +Gc3_122 0 n6 ns122 0 1.16754643684e-005 +Gc3_123 0 n6 ns123 0 -0.000122590436731 +Gc3_124 0 n6 ns124 0 -2.62135443171e-005 +Gc3_125 0 n6 ns125 0 0.00158870403181 +Gc3_126 0 n6 ns126 0 0.000414549038994 +Gd3_1 0 n6 ni1 0 0.00109491073898 +Gd3_2 0 n6 ni2 0 0.00114227453102 +Gd3_3 0 n6 ni3 0 -0.000150440784117 +Gd3_4 0 n6 ni4 0 -0.00153209761543 +Gd3_5 0 n6 ni5 0 0.000810868610441 +Gd3_6 0 n6 ni6 0 0.000457496224527 +Gc4_1 0 n8 ns1 0 0.00155225208913 +Gc4_2 0 n8 ns2 0 0.00155638453981 +Gc4_3 0 n8 ns3 0 -0.000307509241853 +Gc4_4 0 n8 ns4 0 8.60586458375e-007 +Gc4_5 0 n8 ns5 0 6.54885079818e-007 +Gc4_6 0 n8 ns6 0 0.000793364295535 +Gc4_7 0 n8 ns7 0 -0.00115734775535 +Gc4_8 0 n8 ns8 0 -0.000500104336009 +Gc4_9 0 n8 ns9 0 0.000743633891998 +Gc4_10 0 n8 ns10 0 -0.000542069236707 +Gc4_11 0 n8 ns11 0 1.32073048503e-006 +Gc4_12 0 n8 ns12 0 -4.6282762477e-006 +Gc4_13 0 n8 ns13 0 1.77231765044e-006 +Gc4_14 0 n8 ns14 0 -0.00179521912159 +Gc4_15 0 n8 ns15 0 -0.00494147912345 +Gc4_16 0 n8 ns16 0 1.283239537e-005 +Gc4_17 0 n8 ns17 0 6.77013153316e-006 +Gc4_18 0 n8 ns18 0 -0.000121078768125 +Gc4_19 0 n8 ns19 0 -2.43976809654e-005 +Gc4_20 0 n8 ns20 0 0.00158670309138 +Gc4_21 0 n8 ns21 0 0.000407273558475 +Gc4_22 0 n8 ns22 0 0.00209228869335 +Gc4_23 0 n8 ns23 0 0.00182962961644 +Gc4_24 0 n8 ns24 0 -8.94004888617e-006 +Gc4_25 0 n8 ns25 0 9.04845510916e-007 +Gc4_26 0 n8 ns26 0 7.28302676386e-007 +Gc4_27 0 n8 ns27 0 0.00103778935581 +Gc4_28 0 n8 ns28 0 -0.00145804828298 +Gc4_29 0 n8 ns29 0 -0.00148956702983 +Gc4_30 0 n8 ns30 0 0.00101899484753 +Gc4_31 0 n8 ns31 0 0.000296927131028 +Gc4_32 0 n8 ns32 0 -9.8072825494e-005 +Gc4_33 0 n8 ns33 0 -5.70532278144e-006 +Gc4_34 0 n8 ns34 0 1.78566913394e-006 +Gc4_35 0 n8 ns35 0 -0.003368634189 +Gc4_36 0 n8 ns36 0 -0.00339088079867 +Gc4_37 0 n8 ns37 0 1.36081339288e-005 +Gc4_38 0 n8 ns38 0 5.54298879763e-006 +Gc4_39 0 n8 ns39 0 -0.000113143162144 +Gc4_40 0 n8 ns40 0 -2.70104174941e-005 +Gc4_41 0 n8 ns41 0 0.00159724980407 +Gc4_42 0 n8 ns42 0 0.000414313454412 +Gc4_43 0 n8 ns43 0 0.0119450465686 +Gc4_44 0 n8 ns44 0 0.00169963160531 +Gc4_45 0 n8 ns45 0 -0.00743475334765 +Gc4_46 0 n8 ns46 0 8.55202068809e-007 +Gc4_47 0 n8 ns47 0 3.61442447981e-007 +Gc4_48 0 n8 ns48 0 0.000846581609621 +Gc4_49 0 n8 ns49 0 -0.00140997837249 +Gc4_50 0 n8 ns50 0 0.0018308025097 +Gc4_51 0 n8 ns51 0 -0.00123505448709 +Gc4_52 0 n8 ns52 0 -7.22208852942e-005 +Gc4_53 0 n8 ns53 0 -5.13100997701e-006 +Gc4_54 0 n8 ns54 0 -2.94788421159e-006 +Gc4_55 0 n8 ns55 0 -3.2565141837e-006 +Gc4_56 0 n8 ns56 0 0.00488886794632 +Gc4_57 0 n8 ns57 0 0.00851154876577 +Gc4_58 0 n8 ns58 0 5.11229523701e-006 +Gc4_59 0 n8 ns59 0 -4.1104846208e-005 +Gc4_60 0 n8 ns60 0 0.000223871716895 +Gc4_61 0 n8 ns61 0 9.33368962094e-005 +Gc4_62 0 n8 ns62 0 0.00158507716283 +Gc4_63 0 n8 ns63 0 0.000413454912065 +Gc4_64 0 n8 ns64 0 -0.0126833254536 +Gc4_65 0 n8 ns65 0 -0.0123598713643 +Gc4_66 0 n8 ns66 0 0.0159865133644 +Gc4_67 0 n8 ns67 0 1.14178664882e-006 +Gc4_68 0 n8 ns68 0 1.15338065538e-006 +Gc4_69 0 n8 ns69 0 -0.000867384880575 +Gc4_70 0 n8 ns70 0 0.00153907553054 +Gc4_71 0 n8 ns71 0 -0.00265827716275 +Gc4_72 0 n8 ns72 0 0.00178051305999 +Gc4_73 0 n8 ns73 0 -0.000100743777073 +Gc4_74 0 n8 ns74 0 -0.000113401915195 +Gc4_75 0 n8 ns75 0 1.28196310371e-007 +Gc4_76 0 n8 ns76 0 2.00103176948e-006 +Gc4_77 0 n8 ns77 0 -0.00456536097274 +Gc4_78 0 n8 ns78 0 -0.00900610940589 +Gc4_79 0 n8 ns79 0 2.59721359177e-005 +Gc4_80 0 n8 ns80 0 -6.24654018504e-005 +Gc4_81 0 n8 ns81 0 -0.000190704237614 +Gc4_82 0 n8 ns82 0 -9.22093929062e-005 +Gc4_83 0 n8 ns83 0 -0.00159385007958 +Gc4_84 0 n8 ns84 0 -0.000425597823576 +Gc4_85 0 n8 ns85 0 0.00248295274276 +Gc4_86 0 n8 ns86 0 0.00228707544648 +Gc4_87 0 n8 ns87 0 0.000828187371931 +Gc4_88 0 n8 ns88 0 8.53917043719e-007 +Gc4_89 0 n8 ns89 0 4.87917532205e-007 +Gc4_90 0 n8 ns90 0 -0.00104766929605 +Gc4_91 0 n8 ns91 0 0.00145330648153 +Gc4_92 0 n8 ns92 0 0.00254343155335 +Gc4_93 0 n8 ns93 0 -0.0013618481164 +Gc4_94 0 n8 ns94 0 -0.000556794924551 +Gc4_95 0 n8 ns95 0 1.80318185683e-006 +Gc4_96 0 n8 ns96 0 -1.11982495562e-006 +Gc4_97 0 n8 ns97 0 -3.04521676743e-006 +Gc4_98 0 n8 ns98 0 0.00324052082692 +Gc4_99 0 n8 ns99 0 0.00350834898339 +Gc4_100 0 n8 ns100 0 6.75671879926e-006 +Gc4_101 0 n8 ns101 0 6.81714181589e-007 +Gc4_102 0 n8 ns102 0 0.00012060756415 +Gc4_103 0 n8 ns103 0 2.52499868004e-005 +Gc4_104 0 n8 ns104 0 -0.00159623523683 +Gc4_105 0 n8 ns105 0 -0.000414777168365 +Gc4_106 0 n8 ns106 0 0.00258673756671 +Gc4_107 0 n8 ns107 0 0.00209151989704 +Gc4_108 0 n8 ns108 0 0.000716569851332 +Gc4_109 0 n8 ns109 0 8.12898429798e-007 +Gc4_110 0 n8 ns110 0 5.36174998607e-007 +Gc4_111 0 n8 ns111 0 -0.000708070847847 +Gc4_112 0 n8 ns112 0 0.0010740923802 +Gc4_113 0 n8 ns113 0 0.00071865088562 +Gc4_114 0 n8 ns114 0 -0.000852612466359 +Gc4_115 0 n8 ns115 0 0.000690336374995 +Gc4_116 0 n8 ns116 0 -7.56609321674e-005 +Gc4_117 0 n8 ns117 0 -1.32550255557e-006 +Gc4_118 0 n8 ns118 0 -2.7170940893e-006 +Gc4_119 0 n8 ns119 0 0.00167144610357 +Gc4_120 0 n8 ns120 0 0.00506728910156 +Gc4_121 0 n8 ns121 0 -3.02128297183e-006 +Gc4_122 0 n8 ns122 0 1.30574491074e-006 +Gc4_123 0 n8 ns123 0 0.000118571433748 +Gc4_124 0 n8 ns124 0 2.50771077973e-005 +Gc4_125 0 n8 ns125 0 -0.00158750782292 +Gc4_126 0 n8 ns126 0 -0.000409593082247 +Gd4_1 0 n8 ni1 0 0.000808644691298 +Gd4_2 0 n8 ni2 0 0.000330086940859 +Gd4_3 0 n8 ni3 0 -0.00155483702557 +Gd4_4 0 n8 ni4 0 0.00350008070767 +Gd4_5 0 n8 ni5 0 -0.000366390514959 +Gd4_6 0 n8 ni6 0 -0.000410176287613 +Gc5_1 0 n10 ns1 0 0.00198933681172 +Gc5_2 0 n10 ns2 0 0.00202199342134 +Gc5_3 0 n10 ns3 0 0.000190958045853 +Gc5_4 0 n10 ns4 0 7.7720463194e-007 +Gc5_5 0 n10 ns5 0 5.68971723445e-007 +Gc5_6 0 n10 ns6 0 0.000933823131453 +Gc5_7 0 n10 ns7 0 -0.00108463023029 +Gc5_8 0 n10 ns8 0 0.000525249043412 +Gc5_9 0 n10 ns9 0 -0.00060197433945 +Gc5_10 0 n10 ns10 0 -0.00148327207637 +Gc5_11 0 n10 ns11 0 0.00107738310782 +Gc5_12 0 n10 ns12 0 -5.36973626464e-006 +Gc5_13 0 n10 ns13 0 1.62239140207e-006 +Gc5_14 0 n10 ns14 0 -0.00290547866651 +Gc5_15 0 n10 ns15 0 -0.00385343191717 +Gc5_16 0 n10 ns16 0 9.11212096218e-006 +Gc5_17 0 n10 ns17 0 5.67939272451e-006 +Gc5_18 0 n10 ns18 0 -0.000114023397745 +Gc5_19 0 n10 ns19 0 -2.46366242226e-005 +Gc5_20 0 n10 ns20 0 0.00157991218719 +Gc5_21 0 n10 ns21 0 0.000406639664713 +Gc5_22 0 n10 ns22 0 0.0122299101728 +Gc5_23 0 n10 ns23 0 0.0035728557115 +Gc5_24 0 n10 ns24 0 -0.00461222422715 +Gc5_25 0 n10 ns25 0 8.82154358123e-007 +Gc5_26 0 n10 ns26 0 9.00489565082e-007 +Gc5_27 0 n10 ns27 0 0.00121055129182 +Gc5_28 0 n10 ns28 0 -0.00136619009635 +Gc5_29 0 n10 ns29 0 0.00145910266258 +Gc5_30 0 n10 ns30 0 -0.000803013791041 +Gc5_31 0 n10 ns31 0 0.000694553649007 +Gc5_32 0 n10 ns32 0 -0.000750960631001 +Gc5_33 0 n10 ns33 0 -2.33038838452e-006 +Gc5_34 0 n10 ns34 0 -3.37628892544e-006 +Gc5_35 0 n10 ns35 0 0.00599442560655 +Gc5_36 0 n10 ns36 0 0.00738343083619 +Gc5_37 0 n10 ns37 0 3.13104422183e-005 +Gc5_38 0 n10 ns38 0 -5.3640618446e-005 +Gc5_39 0 n10 ns39 0 0.000240755732367 +Gc5_40 0 n10 ns40 0 8.9079211504e-005 +Gc5_41 0 n10 ns41 0 0.00157874060709 +Gc5_42 0 n10 ns42 0 0.000408115933213 +Gc5_43 0 n10 ns43 0 0.00132508469201 +Gc5_44 0 n10 ns44 0 0.00155797050869 +Gc5_45 0 n10 ns45 0 -6.05350479954e-005 +Gc5_46 0 n10 ns46 0 9.591644453e-007 +Gc5_47 0 n10 ns47 0 7.50278031141e-007 +Gc5_48 0 n10 ns48 0 0.00101369889533 +Gc5_49 0 n10 ns49 0 -0.00132709522323 +Gc5_50 0 n10 ns50 0 -0.00152657655183 +Gc5_51 0 n10 ns51 0 0.00100135905037 +Gc5_52 0 n10 ns52 0 0.000135774352503 +Gc5_53 0 n10 ns53 0 8.77874538643e-007 +Gc5_54 0 n10 ns54 0 -5.61718865033e-006 +Gc5_55 0 n10 ns55 0 1.72820871089e-006 +Gc5_56 0 n10 ns56 0 -0.00337506034125 +Gc5_57 0 n10 ns57 0 -0.00339110099475 +Gc5_58 0 n10 ns58 0 1.21532033252e-005 +Gc5_59 0 n10 ns59 0 8.42716371947e-006 +Gc5_60 0 n10 ns60 0 -0.000112848173739 +Gc5_61 0 n10 ns61 0 -2.89802710666e-005 +Gc5_62 0 n10 ns62 0 0.00159892616096 +Gc5_63 0 n10 ns63 0 0.000420297787024 +Gc5_64 0 n10 ns64 0 0.00247888210927 +Gc5_65 0 n10 ns65 0 0.00227797657178 +Gc5_66 0 n10 ns66 0 0.000817849397039 +Gc5_67 0 n10 ns67 0 8.4169239324e-007 +Gc5_68 0 n10 ns68 0 4.72175563654e-007 +Gc5_69 0 n10 ns69 0 -0.00104832299328 +Gc5_70 0 n10 ns70 0 0.0014529931766 +Gc5_71 0 n10 ns71 0 0.00254272832017 +Gc5_72 0 n10 ns72 0 -0.00136367726415 +Gc5_73 0 n10 ns73 0 -0.000556980945374 +Gc5_74 0 n10 ns74 0 4.25726952958e-006 +Gc5_75 0 n10 ns75 0 -1.12691428928e-006 +Gc5_76 0 n10 ns76 0 -3.37545154404e-006 +Gc5_77 0 n10 ns77 0 0.00321878359832 +Gc5_78 0 n10 ns78 0 0.00353663682891 +Gc5_79 0 n10 ns79 0 5.56186437573e-006 +Gc5_80 0 n10 ns80 0 4.19344821109e-006 +Gc5_81 0 n10 ns81 0 0.000118166918612 +Gc5_82 0 n10 ns82 0 2.61536774669e-005 +Gc5_83 0 n10 ns83 0 -0.0015990759481 +Gc5_84 0 n10 ns84 0 -0.000417258083898 +Gc5_85 0 n10 ns85 0 -0.0129657649875 +Gc5_86 0 n10 ns86 0 -0.0147604899471 +Gc5_87 0 n10 ns87 0 0.0125483281926 +Gc5_88 0 n10 ns88 0 1.39867768678e-006 +Gc5_89 0 n10 ns89 0 6.10419633608e-007 +Gc5_90 0 n10 ns90 0 -0.00121786005722 +Gc5_91 0 n10 ns91 0 0.00135575669976 +Gc5_92 0 n10 ns92 0 -0.00210986761749 +Gc5_93 0 n10 ns93 0 0.00112432631291 +Gc5_94 0 n10 ns94 0 -0.00119407122313 +Gc5_95 0 n10 ns95 0 0.000932207444841 +Gc5_96 0 n10 ns96 0 -9.7996154064e-007 +Gc5_97 0 n10 ns97 0 1.42140821714e-006 +Gc5_98 0 n10 ns98 0 -0.00558450292414 +Gc5_99 0 n10 ns99 0 -0.00805298916427 +Gc5_100 0 n10 ns100 0 4.00048477372e-005 +Gc5_101 0 n10 ns101 0 -7.40329787736e-005 +Gc5_102 0 n10 ns102 0 -0.000169276398621 +Gc5_103 0 n10 ns103 0 -9.69535749508e-005 +Gc5_104 0 n10 ns104 0 -0.00157968058233 +Gc5_105 0 n10 ns105 0 -0.000404329248358 +Gc5_106 0 n10 ns106 0 0.00264136318342 +Gc5_107 0 n10 ns107 0 0.00227440170682 +Gc5_108 0 n10 ns108 0 0.00100186018914 +Gc5_109 0 n10 ns109 0 8.60305695933e-007 +Gc5_110 0 n10 ns110 0 4.70307473586e-007 +Gc5_111 0 n10 ns111 0 -0.000833939880164 +Gc5_112 0 n10 ns112 0 0.00100196916494 +Gc5_113 0 n10 ns113 0 -0.000440790422701 +Gc5_114 0 n10 ns114 0 0.000763461595034 +Gc5_115 0 n10 ns115 0 0.00211177967669 +Gc5_116 0 n10 ns116 0 -0.00155537952404 +Gc5_117 0 n10 ns117 0 -1.19986931348e-006 +Gc5_118 0 n10 ns118 0 -2.61716280253e-006 +Gc5_119 0 n10 ns119 0 0.00277228230224 +Gc5_120 0 n10 ns120 0 0.0039888493764 +Gc5_121 0 n10 ns121 0 3.33156757294e-006 +Gc5_122 0 n10 ns122 0 2.76985185219e-006 +Gc5_123 0 n10 ns123 0 0.000113313378795 +Gc5_124 0 n10 ns124 0 2.46208475401e-005 +Gc5_125 0 n10 ns125 0 -0.00157998140562 +Gc5_126 0 n10 ns126 0 -0.000407276636791 +Gd5_1 0 n10 ni1 0 0.00030020013256 +Gd5_2 0 n10 ni2 0 -0.00307082309044 +Gd5_3 0 n10 ni3 0 0.000827388010201 +Gd5_4 0 n10 ni4 0 -0.000362135073214 +Gd5_5 0 n10 ni5 0 0.00505954842392 +Gd5_6 0 n10 ni6 0 -0.000524254722336 +Gc6_1 0 n12 ns1 0 0.0120332372002 +Gc6_2 0 n12 ns2 0 0.00262410639618 +Gc6_3 0 n12 ns3 0 -0.00583028287891 +Gc6_4 0 n12 ns4 0 6.98769385013e-007 +Gc6_5 0 n12 ns5 0 7.81026826498e-007 +Gc6_6 0 n12 ns6 0 0.000648457858122 +Gc6_7 0 n12 ns7 0 -0.000800965568843 +Gc6_8 0 n12 ns8 0 0.000160087585496 +Gc6_9 0 n12 ns9 0 -0.000294505644027 +Gc6_10 0 n12 ns10 0 0.00259500977374 +Gc6_11 0 n12 ns11 0 -0.00164432433395 +Gc6_12 0 n12 ns12 0 -2.77509580688e-006 +Gc6_13 0 n12 ns13 0 -2.81456538774e-006 +Gc6_14 0 n12 ns14 0 0.0042927654984 +Gc6_15 0 n12 ns15 0 0.00919209818214 +Gc6_16 0 n12 ns16 0 -1.18550259692e-005 +Gc6_17 0 n12 ns17 0 -1.18366095318e-005 +Gc6_18 0 n12 ns18 0 0.000200551805491 +Gc6_19 0 n12 ns19 0 9.52656170838e-005 +Gc6_20 0 n12 ns20 0 0.00158594628879 +Gc6_21 0 n12 ns21 0 0.000411351309421 +Gc6_22 0 n12 ns22 0 0.00165651949956 +Gc6_23 0 n12 ns23 0 0.001765315977 +Gc6_24 0 n12 ns24 0 -3.56561431526e-005 +Gc6_25 0 n12 ns25 0 9.1218384593e-007 +Gc6_26 0 n12 ns26 0 6.71496994177e-007 +Gc6_27 0 n12 ns27 0 0.000841459248087 +Gc6_28 0 n12 ns28 0 -0.00100543312979 +Gc6_29 0 n12 ns29 0 0.000373495862238 +Gc6_30 0 n12 ns30 0 -0.000494066843947 +Gc6_31 0 n12 ns31 0 -0.00146285870969 +Gc6_32 0 n12 ns32 0 0.00105339453714 +Gc6_33 0 n12 ns33 0 -5.36380052074e-006 +Gc6_34 0 n12 ns34 0 1.83759316012e-006 +Gc6_35 0 n12 ns35 0 -0.00290422786858 +Gc6_36 0 n12 ns36 0 -0.00386036734424 +Gc6_37 0 n12 ns37 0 6.9090922403e-006 +Gc6_38 0 n12 ns38 0 7.94237202422e-006 +Gc6_39 0 n12 ns39 0 -0.000113716516872 +Gc6_40 0 n12 ns40 0 -2.67179239684e-005 +Gc6_41 0 n12 ns41 0 0.00158130552681 +Gc6_42 0 n12 ns42 0 0.000415862911052 +Gc6_43 0 n12 ns43 0 0.00141212055219 +Gc6_44 0 n12 ns44 0 0.00191823821086 +Gc6_45 0 n12 ns45 0 0.000319853080899 +Gc6_46 0 n12 ns46 0 8.61445826018e-007 +Gc6_47 0 n12 ns47 0 6.18199490412e-007 +Gc6_48 0 n12 ns48 0 0.000697749940982 +Gc6_49 0 n12 ns49 0 -0.000978243399401 +Gc6_50 0 n12 ns50 0 -0.000335985532372 +Gc6_51 0 n12 ns51 0 0.000608864302815 +Gc6_52 0 n12 ns52 0 -0.000243072421446 +Gc6_53 0 n12 ns53 0 -0.000137579428639 +Gc6_54 0 n12 ns54 0 -5.39190774432e-006 +Gc6_55 0 n12 ns55 0 1.89399406028e-006 +Gc6_56 0 n12 ns56 0 -0.00182191636942 +Gc6_57 0 n12 ns57 0 -0.00490624716602 +Gc6_58 0 n12 ns58 0 1.11521577528e-005 +Gc6_59 0 n12 ns59 0 1.20112482905e-005 +Gc6_60 0 n12 ns60 0 -0.000121701059494 +Gc6_61 0 n12 ns61 0 -2.61650425159e-005 +Gc6_62 0 n12 ns62 0 0.00158722573768 +Gc6_63 0 n12 ns63 0 0.000410827356617 +Gc6_64 0 n12 ns64 0 0.00257930756394 +Gc6_65 0 n12 ns65 0 0.00207960043543 +Gc6_66 0 n12 ns66 0 0.000701144908238 +Gc6_67 0 n12 ns67 0 8.03052698036e-007 +Gc6_68 0 n12 ns68 0 5.28966444417e-007 +Gc6_69 0 n12 ns69 0 -0.00070884078615 +Gc6_70 0 n12 ns70 0 0.00107373411934 +Gc6_71 0 n12 ns71 0 0.000717800514372 +Gc6_72 0 n12 ns72 0 -0.00085413358718 +Gc6_73 0 n12 ns73 0 0.000690342002791 +Gc6_74 0 n12 ns74 0 -7.34282113498e-005 +Gc6_75 0 n12 ns75 0 -1.31191929682e-006 +Gc6_76 0 n12 ns76 0 -2.84159779275e-006 +Gc6_77 0 n12 ns77 0 0.00167004957686 +Gc6_78 0 n12 ns78 0 0.00506972617672 +Gc6_79 0 n12 ns79 0 -2.6336468109e-006 +Gc6_80 0 n12 ns80 0 2.03724141662e-006 +Gc6_81 0 n12 ns81 0 0.000118687110345 +Gc6_82 0 n12 ns82 0 2.55053888876e-005 +Gc6_83 0 n12 ns83 0 -0.00158915264344 +Gc6_84 0 n12 ns84 0 -0.000410241381818 +Gc6_85 0 n12 ns85 0 0.0026336304727 +Gc6_86 0 n12 ns86 0 0.00226221281358 +Gc6_87 0 n12 ns87 0 0.000987186109756 +Gc6_88 0 n12 ns88 0 8.4081885325e-007 +Gc6_89 0 n12 ns89 0 4.57777090295e-007 +Gc6_90 0 n12 ns90 0 -0.000834840324345 +Gc6_91 0 n12 ns91 0 0.00100146178176 +Gc6_92 0 n12 ns92 0 -0.000443381299557 +Gc6_93 0 n12 ns93 0 0.000762154630277 +Gc6_94 0 n12 ns94 0 0.00211343163896 +Gc6_95 0 n12 ns95 0 -0.00155276500031 +Gc6_96 0 n12 ns96 0 -1.20996583108e-006 +Gc6_97 0 n12 ns97 0 -2.82140106581e-006 +Gc6_98 0 n12 ns98 0 0.00276330782901 +Gc6_99 0 n12 ns99 0 0.00400068348146 +Gc6_100 0 n12 ns100 0 3.11943759847e-006 +Gc6_101 0 n12 ns101 0 4.4324976446e-006 +Gc6_102 0 n12 ns102 0 0.000112522300315 +Gc6_103 0 n12 ns103 0 2.56180905949e-005 +Gc6_104 0 n12 ns104 0 -0.00158327823983 +Gc6_105 0 n12 ns105 0 -0.000413154336801 +Gc6_106 0 n12 ns106 0 -0.0127635008859 +Gc6_107 0 n12 ns107 0 -0.0138990799639 +Gc6_108 0 n12 ns108 0 0.0136510526191 +Gc6_109 0 n12 ns109 0 1.20045447717e-006 +Gc6_110 0 n12 ns110 0 7.48563077041e-007 +Gc6_111 0 n12 ns111 0 -0.000574442966349 +Gc6_112 0 n12 ns112 0 0.000745799512069 +Gc6_113 0 n12 ns113 0 -4.80505973526e-005 +Gc6_114 0 n12 ns114 0 0.000379503324329 +Gc6_115 0 n12 ns115 0 -0.00397866229368 +Gc6_116 0 n12 ns116 0 0.00207574355897 +Gc6_117 0 n12 ns117 0 -2.86307415605e-007 +Gc6_118 0 n12 ns118 0 9.57136976055e-007 +Gc6_119 0 n12 ns119 0 -0.00414883406701 +Gc6_120 0 n12 ns120 0 -0.00939590394174 +Gc6_121 0 n12 ns121 0 1.01156494203e-005 +Gc6_122 0 n12 ns122 0 -4.8219425039e-005 +Gc6_123 0 n12 ns123 0 -0.000203388785048 +Gc6_124 0 n12 ns124 0 -9.00859338194e-005 +Gc6_125 0 n12 ns125 0 -0.00159013871357 +Gc6_126 0 n12 ns126 0 -0.000409389740189 +Gd6_1 0 n12 ni1 0 -0.00251381766267 +Gd6_2 0 n12 ni2 0 0.000672995560122 +Gd6_3 0 n12 ni3 0 0.000475981024286 +Gd6_4 0 n12 ni4 0 -0.000401698638393 +Gd6_5 0 n12 ni5 0 -0.000515974115439 +Gd6_6 0 n12 ni6 0 0.00450143791381 +.ends + + + + +.subckt 744833084075 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 2600.15260032 +Ca2 ns2 0 1e-012 +Ca3 ns3 0 1e-012 +Ra2 ns2 0 12488.2002142 +Ra3 ns3 0 12488.2002142 +Ga2 ns2 0 ns3 0 -0.000382923537159 +Ga3 ns3 0 ns2 0 0.000382923537159 +Ca4 ns4 0 1e-012 +Ca5 ns5 0 1e-012 +Ra4 ns4 0 5401.25591576 +Ra5 ns5 0 5401.25591576 +Ga4 ns4 0 ns5 0 -0.000307369478146 +Ga5 ns5 0 ns4 0 0.000307369478146 +Ca6 ns6 0 1e-012 +Ca7 ns7 0 1e-012 +Ra6 ns6 0 68089.7532469 +Ra7 ns7 0 68089.7532469 +Ga6 ns6 0 ns7 0 -0.000240771559902 +Ga7 ns7 0 ns6 0 0.000240771559902 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 62478.3975911 +Ra9 ns9 0 62478.3975911 +Ga8 ns8 0 ns9 0 -0.000175090240354 +Ga9 ns9 0 ns8 0 0.000175090240354 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 71863.8646749 +Ra11 ns11 0 71863.8646749 +Ga10 ns10 0 ns11 0 -0.000142243725148 +Ga11 ns11 0 ns10 0 0.000142243725148 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 71376.542734 +Ra13 ns13 0 71376.542734 +Ga12 ns12 0 ns13 0 -0.000130143645314 +Ga13 ns13 0 ns12 0 0.000130143645314 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 287513.122552 +Ra15 ns15 0 287513.122552 +Ga14 ns14 0 ns15 0 -1.59775243036e-005 +Ga15 ns15 0 ns14 0 1.59775243036e-005 +Ca16 ns16 0 1e-012 +Ra16 ns16 0 214521.935161 +Ca17 ns17 0 1e-012 +Ra17 ns17 0 315470.828552 +Ca18 ns18 0 1e-012 +Ra18 ns18 0 1127473.16043 +Ca19 ns19 0 1e-012 +Ra19 ns19 0 4243356.81091 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 76212827.9948 +Ra21 ns21 0 76212827.9948 +Ga20 ns20 0 ns21 0 -2.17110042069e-008 +Ga21 ns21 0 ns20 0 2.17110042069e-008 +Ca22 ns22 0 1e-012 +Ra22 ns22 0 2600.15260032 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 12488.2002142 +Ra24 ns24 0 12488.2002142 +Ga23 ns23 0 ns24 0 -0.000382923537159 +Ga24 ns24 0 ns23 0 0.000382923537159 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 5401.25591576 +Ra26 ns26 0 5401.25591576 +Ga25 ns25 0 ns26 0 -0.000307369478146 +Ga26 ns26 0 ns25 0 0.000307369478146 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 68089.7532469 +Ra28 ns28 0 68089.7532469 +Ga27 ns27 0 ns28 0 -0.000240771559902 +Ga28 ns28 0 ns27 0 0.000240771559902 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 62478.3975911 +Ra30 ns30 0 62478.3975911 +Ga29 ns29 0 ns30 0 -0.000175090240354 +Ga30 ns30 0 ns29 0 0.000175090240354 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 71863.8646749 +Ra32 ns32 0 71863.8646749 +Ga31 ns31 0 ns32 0 -0.000142243725148 +Ga32 ns32 0 ns31 0 0.000142243725148 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 71376.542734 +Ra34 ns34 0 71376.542734 +Ga33 ns33 0 ns34 0 -0.000130143645314 +Ga34 ns34 0 ns33 0 0.000130143645314 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 287513.122552 +Ra36 ns36 0 287513.122552 +Ga35 ns35 0 ns36 0 -1.59775243036e-005 +Ga36 ns36 0 ns35 0 1.59775243036e-005 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 214521.935161 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 315470.828552 +Ca39 ns39 0 1e-012 +Ra39 ns39 0 1127473.16043 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 4243356.81091 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 76212827.9948 +Ra42 ns42 0 76212827.9948 +Ga41 ns41 0 ns42 0 -2.17110042069e-008 +Ga42 ns42 0 ns41 0 2.17110042069e-008 +Ca43 ns43 0 1e-012 +Ra43 ns43 0 2600.15260032 +Ca44 ns44 0 1e-012 +Ca45 ns45 0 1e-012 +Ra44 ns44 0 12488.2002142 +Ra45 ns45 0 12488.2002142 +Ga44 ns44 0 ns45 0 -0.000382923537159 +Ga45 ns45 0 ns44 0 0.000382923537159 +Ca46 ns46 0 1e-012 +Ca47 ns47 0 1e-012 +Ra46 ns46 0 5401.25591576 +Ra47 ns47 0 5401.25591576 +Ga46 ns46 0 ns47 0 -0.000307369478146 +Ga47 ns47 0 ns46 0 0.000307369478146 +Ca48 ns48 0 1e-012 +Ca49 ns49 0 1e-012 +Ra48 ns48 0 68089.7532469 +Ra49 ns49 0 68089.7532469 +Ga48 ns48 0 ns49 0 -0.000240771559902 +Ga49 ns49 0 ns48 0 0.000240771559902 +Ca50 ns50 0 1e-012 +Ca51 ns51 0 1e-012 +Ra50 ns50 0 62478.3975911 +Ra51 ns51 0 62478.3975911 +Ga50 ns50 0 ns51 0 -0.000175090240354 +Ga51 ns51 0 ns50 0 0.000175090240354 +Ca52 ns52 0 1e-012 +Ca53 ns53 0 1e-012 +Ra52 ns52 0 71863.8646749 +Ra53 ns53 0 71863.8646749 +Ga52 ns52 0 ns53 0 -0.000142243725148 +Ga53 ns53 0 ns52 0 0.000142243725148 +Ca54 ns54 0 1e-012 +Ca55 ns55 0 1e-012 +Ra54 ns54 0 71376.542734 +Ra55 ns55 0 71376.542734 +Ga54 ns54 0 ns55 0 -0.000130143645314 +Ga55 ns55 0 ns54 0 0.000130143645314 +Ca56 ns56 0 1e-012 +Ca57 ns57 0 1e-012 +Ra56 ns56 0 287513.122552 +Ra57 ns57 0 287513.122552 +Ga56 ns56 0 ns57 0 -1.59775243036e-005 +Ga57 ns57 0 ns56 0 1.59775243036e-005 +Ca58 ns58 0 1e-012 +Ra58 ns58 0 214521.935161 +Ca59 ns59 0 1e-012 +Ra59 ns59 0 315470.828552 +Ca60 ns60 0 1e-012 +Ra60 ns60 0 1127473.16043 +Ca61 ns61 0 1e-012 +Ra61 ns61 0 4243356.81091 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 76212827.9948 +Ra63 ns63 0 76212827.9948 +Ga62 ns62 0 ns63 0 -2.17110042069e-008 +Ga63 ns63 0 ns62 0 2.17110042069e-008 +Ca64 ns64 0 1e-012 +Ra64 ns64 0 2600.15260032 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 12488.2002142 +Ra66 ns66 0 12488.2002142 +Ga65 ns65 0 ns66 0 -0.000382923537159 +Ga66 ns66 0 ns65 0 0.000382923537159 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 5401.25591576 +Ra68 ns68 0 5401.25591576 +Ga67 ns67 0 ns68 0 -0.000307369478146 +Ga68 ns68 0 ns67 0 0.000307369478146 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 68089.7532469 +Ra70 ns70 0 68089.7532469 +Ga69 ns69 0 ns70 0 -0.000240771559902 +Ga70 ns70 0 ns69 0 0.000240771559902 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 62478.3975911 +Ra72 ns72 0 62478.3975911 +Ga71 ns71 0 ns72 0 -0.000175090240354 +Ga72 ns72 0 ns71 0 0.000175090240354 +Ca73 ns73 0 1e-012 +Ca74 ns74 0 1e-012 +Ra73 ns73 0 71863.8646749 +Ra74 ns74 0 71863.8646749 +Ga73 ns73 0 ns74 0 -0.000142243725148 +Ga74 ns74 0 ns73 0 0.000142243725148 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 71376.542734 +Ra76 ns76 0 71376.542734 +Ga75 ns75 0 ns76 0 -0.000130143645314 +Ga76 ns76 0 ns75 0 0.000130143645314 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 287513.122552 +Ra78 ns78 0 287513.122552 +Ga77 ns77 0 ns78 0 -1.59775243036e-005 +Ga78 ns78 0 ns77 0 1.59775243036e-005 +Ca79 ns79 0 1e-012 +Ra79 ns79 0 214521.935161 +Ca80 ns80 0 1e-012 +Ra80 ns80 0 315470.828552 +Ca81 ns81 0 1e-012 +Ra81 ns81 0 1127473.16043 +Ca82 ns82 0 1e-012 +Ra82 ns82 0 4243356.81091 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 76212827.9948 +Ra84 ns84 0 76212827.9948 +Ga83 ns83 0 ns84 0 -2.17110042069e-008 +Ga84 ns84 0 ns83 0 2.17110042069e-008 +Ca85 ns85 0 1e-012 +Ra85 ns85 0 2600.15260032 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 12488.2002142 +Ra87 ns87 0 12488.2002142 +Ga86 ns86 0 ns87 0 -0.000382923537159 +Ga87 ns87 0 ns86 0 0.000382923537159 +Ca88 ns88 0 1e-012 +Ca89 ns89 0 1e-012 +Ra88 ns88 0 5401.25591576 +Ra89 ns89 0 5401.25591576 +Ga88 ns88 0 ns89 0 -0.000307369478146 +Ga89 ns89 0 ns88 0 0.000307369478146 +Ca90 ns90 0 1e-012 +Ca91 ns91 0 1e-012 +Ra90 ns90 0 68089.7532469 +Ra91 ns91 0 68089.7532469 +Ga90 ns90 0 ns91 0 -0.000240771559902 +Ga91 ns91 0 ns90 0 0.000240771559902 +Ca92 ns92 0 1e-012 +Ca93 ns93 0 1e-012 +Ra92 ns92 0 62478.3975911 +Ra93 ns93 0 62478.3975911 +Ga92 ns92 0 ns93 0 -0.000175090240354 +Ga93 ns93 0 ns92 0 0.000175090240354 +Ca94 ns94 0 1e-012 +Ca95 ns95 0 1e-012 +Ra94 ns94 0 71863.8646749 +Ra95 ns95 0 71863.8646749 +Ga94 ns94 0 ns95 0 -0.000142243725148 +Ga95 ns95 0 ns94 0 0.000142243725148 +Ca96 ns96 0 1e-012 +Ca97 ns97 0 1e-012 +Ra96 ns96 0 71376.542734 +Ra97 ns97 0 71376.542734 +Ga96 ns96 0 ns97 0 -0.000130143645314 +Ga97 ns97 0 ns96 0 0.000130143645314 +Ca98 ns98 0 1e-012 +Ca99 ns99 0 1e-012 +Ra98 ns98 0 287513.122552 +Ra99 ns99 0 287513.122552 +Ga98 ns98 0 ns99 0 -1.59775243036e-005 +Ga99 ns99 0 ns98 0 1.59775243036e-005 +Ca100 ns100 0 1e-012 +Ra100 ns100 0 214521.935161 +Ca101 ns101 0 1e-012 +Ra101 ns101 0 315470.828552 +Ca102 ns102 0 1e-012 +Ra102 ns102 0 1127473.16043 +Ca103 ns103 0 1e-012 +Ra103 ns103 0 4243356.81091 +Ca104 ns104 0 1e-012 +Ca105 ns105 0 1e-012 +Ra104 ns104 0 76212827.9948 +Ra105 ns105 0 76212827.9948 +Ga104 ns104 0 ns105 0 -2.17110042069e-008 +Ga105 ns105 0 ns104 0 2.17110042069e-008 +Ca106 ns106 0 1e-012 +Ra106 ns106 0 2600.15260032 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 12488.2002142 +Ra108 ns108 0 12488.2002142 +Ga107 ns107 0 ns108 0 -0.000382923537159 +Ga108 ns108 0 ns107 0 0.000382923537159 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 5401.25591576 +Ra110 ns110 0 5401.25591576 +Ga109 ns109 0 ns110 0 -0.000307369478146 +Ga110 ns110 0 ns109 0 0.000307369478146 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 68089.7532469 +Ra112 ns112 0 68089.7532469 +Ga111 ns111 0 ns112 0 -0.000240771559902 +Ga112 ns112 0 ns111 0 0.000240771559902 +Ca113 ns113 0 1e-012 +Ca114 ns114 0 1e-012 +Ra113 ns113 0 62478.3975911 +Ra114 ns114 0 62478.3975911 +Ga113 ns113 0 ns114 0 -0.000175090240354 +Ga114 ns114 0 ns113 0 0.000175090240354 +Ca115 ns115 0 1e-012 +Ca116 ns116 0 1e-012 +Ra115 ns115 0 71863.8646749 +Ra116 ns116 0 71863.8646749 +Ga115 ns115 0 ns116 0 -0.000142243725148 +Ga116 ns116 0 ns115 0 0.000142243725148 +Ca117 ns117 0 1e-012 +Ca118 ns118 0 1e-012 +Ra117 ns117 0 71376.542734 +Ra118 ns118 0 71376.542734 +Ga117 ns117 0 ns118 0 -0.000130143645314 +Ga118 ns118 0 ns117 0 0.000130143645314 +Ca119 ns119 0 1e-012 +Ca120 ns120 0 1e-012 +Ra119 ns119 0 287513.122552 +Ra120 ns120 0 287513.122552 +Ga119 ns119 0 ns120 0 -1.59775243036e-005 +Ga120 ns120 0 ns119 0 1.59775243036e-005 +Ca121 ns121 0 1e-012 +Ra121 ns121 0 214521.935161 +Ca122 ns122 0 1e-012 +Ra122 ns122 0 315470.828552 +Ca123 ns123 0 1e-012 +Ra123 ns123 0 1127473.16043 +Ca124 ns124 0 1e-012 +Ra124 ns124 0 4243356.81091 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 76212827.9948 +Ra126 ns126 0 76212827.9948 +Ga125 ns125 0 ns126 0 -2.17110042069e-008 +Ga126 ns126 0 ns125 0 2.17110042069e-008 + +Gb1_1 ns1 0 ni1 0 -0.000384592811928 +Gb2_1 ns2 0 ni1 0 -0.000399668655934 +Gb4_1 ns4 0 ni1 0 -0.000418888705102 +Gb6_1 ns6 0 ni1 0 -0.000241667401641 +Gb8_1 ns8 0 ni1 0 -0.000176553354793 +Gb10_1 ns10 0 ni1 0 -0.00014360499976 +Gb12_1 ns12 0 ni1 0 -0.000131651869901 +Gb14_1 ns14 0 ni1 0 -1.67346625249e-005 +Gb16_1 ns16 0 ni1 0 -4.66152796566e-006 +Gb17_1 ns17 0 ni1 0 -3.1698651967e-006 +Gb18_1 ns18 0 ni1 0 -8.86939073224e-007 +Gb19_1 ns19 0 ni1 0 -2.35662482454e-007 +Gb20_1 ns20 0 ni1 0 -2.96408352535e-008 +Gb22_2 ns22 0 ni2 0 -0.000384592811928 +Gb23_2 ns23 0 ni2 0 -0.000399668655934 +Gb25_2 ns25 0 ni2 0 -0.000418888705102 +Gb27_2 ns27 0 ni2 0 -0.000241667401641 +Gb29_2 ns29 0 ni2 0 -0.000176553354793 +Gb31_2 ns31 0 ni2 0 -0.00014360499976 +Gb33_2 ns33 0 ni2 0 -0.000131651869901 +Gb35_2 ns35 0 ni2 0 -1.67346625249e-005 +Gb37_2 ns37 0 ni2 0 -4.66152796566e-006 +Gb38_2 ns38 0 ni2 0 -3.1698651967e-006 +Gb39_2 ns39 0 ni2 0 -8.86939073224e-007 +Gb40_2 ns40 0 ni2 0 -2.35662482454e-007 +Gb41_2 ns41 0 ni2 0 -2.96408352535e-008 +Gb43_3 ns43 0 ni3 0 -0.000384592811928 +Gb44_3 ns44 0 ni3 0 -0.000399668655934 +Gb46_3 ns46 0 ni3 0 -0.000418888705102 +Gb48_3 ns48 0 ni3 0 -0.000241667401641 +Gb50_3 ns50 0 ni3 0 -0.000176553354793 +Gb52_3 ns52 0 ni3 0 -0.00014360499976 +Gb54_3 ns54 0 ni3 0 -0.000131651869901 +Gb56_3 ns56 0 ni3 0 -1.67346625249e-005 +Gb58_3 ns58 0 ni3 0 -4.66152796566e-006 +Gb59_3 ns59 0 ni3 0 -3.1698651967e-006 +Gb60_3 ns60 0 ni3 0 -8.86939073224e-007 +Gb61_3 ns61 0 ni3 0 -2.35662482454e-007 +Gb62_3 ns62 0 ni3 0 -2.96408352535e-008 +Gb64_4 ns64 0 ni4 0 -0.000384592811928 +Gb65_4 ns65 0 ni4 0 -0.000399668655934 +Gb67_4 ns67 0 ni4 0 -0.000418888705102 +Gb69_4 ns69 0 ni4 0 -0.000241667401641 +Gb71_4 ns71 0 ni4 0 -0.000176553354793 +Gb73_4 ns73 0 ni4 0 -0.00014360499976 +Gb75_4 ns75 0 ni4 0 -0.000131651869901 +Gb77_4 ns77 0 ni4 0 -1.67346625249e-005 +Gb79_4 ns79 0 ni4 0 -4.66152796566e-006 +Gb80_4 ns80 0 ni4 0 -3.1698651967e-006 +Gb81_4 ns81 0 ni4 0 -8.86939073224e-007 +Gb82_4 ns82 0 ni4 0 -2.35662482454e-007 +Gb83_4 ns83 0 ni4 0 -2.96408352535e-008 +Gb85_5 ns85 0 ni5 0 -0.000384592811928 +Gb86_5 ns86 0 ni5 0 -0.000399668655934 +Gb88_5 ns88 0 ni5 0 -0.000418888705102 +Gb90_5 ns90 0 ni5 0 -0.000241667401641 +Gb92_5 ns92 0 ni5 0 -0.000176553354793 +Gb94_5 ns94 0 ni5 0 -0.00014360499976 +Gb96_5 ns96 0 ni5 0 -0.000131651869901 +Gb98_5 ns98 0 ni5 0 -1.67346625249e-005 +Gb100_5 ns100 0 ni5 0 -4.66152796566e-006 +Gb101_5 ns101 0 ni5 0 -3.1698651967e-006 +Gb102_5 ns102 0 ni5 0 -8.86939073224e-007 +Gb103_5 ns103 0 ni5 0 -2.35662482454e-007 +Gb104_5 ns104 0 ni5 0 -2.96408352535e-008 +Gb106_6 ns106 0 ni6 0 -0.000384592811928 +Gb107_6 ns107 0 ni6 0 -0.000399668655934 +Gb109_6 ns109 0 ni6 0 -0.000418888705102 +Gb111_6 ns111 0 ni6 0 -0.000241667401641 +Gb113_6 ns113 0 ni6 0 -0.000176553354793 +Gb115_6 ns115 0 ni6 0 -0.00014360499976 +Gb117_6 ns117 0 ni6 0 -0.000131651869901 +Gb119_6 ns119 0 ni6 0 -1.67346625249e-005 +Gb121_6 ns121 0 ni6 0 -4.66152796566e-006 +Gb122_6 ns122 0 ni6 0 -3.1698651967e-006 +Gb123_6 ns123 0 ni6 0 -8.86939073224e-007 +Gb124_6 ns124 0 ni6 0 -2.35662482454e-007 +Gb125_6 ns125 0 ni6 0 -2.96408352535e-008 + +Gc1_1 0 n2 ns1 0 0.0228499509814 +Gc1_2 0 n2 ns2 0 -0.00170530715259 +Gc1_3 0 n2 ns3 0 0.00178150629536 +Gc1_4 0 n2 ns4 0 -0.0037853596656 +Gc1_5 0 n2 ns5 0 -0.00617613732843 +Gc1_6 0 n2 ns6 0 -3.60353633641e-006 +Gc1_7 0 n2 ns7 0 -6.54755879846e-006 +Gc1_8 0 n2 ns8 0 -0.00042493215181 +Gc1_9 0 n2 ns9 0 0.000510028151388 +Gc1_10 0 n2 ns10 0 3.72523302314e-005 +Gc1_11 0 n2 ns11 0 2.82007790938e-005 +Gc1_12 0 n2 ns12 0 -0.00120979406245 +Gc1_13 0 n2 ns13 0 0.000859842114375 +Gc1_14 0 n2 ns14 0 8.78650389323e-007 +Gc1_15 0 n2 ns15 0 5.64530348323e-006 +Gc1_16 0 n2 ns16 0 -0.00471176989196 +Gc1_17 0 n2 ns17 0 -0.00848637270816 +Gc1_18 0 n2 ns18 0 -0.000248030066382 +Gc1_19 0 n2 ns19 0 -0.000138473429435 +Gc1_20 0 n2 ns20 0 -0.00100693497139 +Gc1_21 0 n2 ns21 0 -0.000288991560741 +Gc1_22 0 n2 ns22 0 -5.31413260811e-005 +Gc1_23 0 n2 ns23 0 -0.000340748661526 +Gc1_24 0 n2 ns24 0 0.00168226585433 +Gc1_25 0 n2 ns25 0 0.00209813647391 +Gc1_26 0 n2 ns26 0 0.000241110928619 +Gc1_27 0 n2 ns27 0 -5.77391992227e-006 +Gc1_28 0 n2 ns28 0 -6.38839358171e-006 +Gc1_29 0 n2 ns29 0 -0.000583767369911 +Gc1_30 0 n2 ns30 0 0.000694705266804 +Gc1_31 0 n2 ns31 0 -2.84542164825e-006 +Gc1_32 0 n2 ns32 0 0.000175610956266 +Gc1_33 0 n2 ns33 0 0.000429077069837 +Gc1_34 0 n2 ns34 0 -0.000428984349959 +Gc1_35 0 n2 ns35 0 4.87016007571e-006 +Gc1_36 0 n2 ns36 0 -2.38824330348e-006 +Gc1_37 0 n2 ns37 0 0.00308278063841 +Gc1_38 0 n2 ns38 0 0.00355711351987 +Gc1_39 0 n2 ns39 0 0.000113406611992 +Gc1_40 0 n2 ns40 0 7.06985620663e-005 +Gc1_41 0 n2 ns41 0 -0.00101459737248 +Gc1_42 0 n2 ns42 0 -0.000307165696129 +Gc1_43 0 n2 ns43 0 0.000333909261879 +Gc1_44 0 n2 ns44 0 -0.000177740320789 +Gc1_45 0 n2 ns45 0 0.00156031274892 +Gc1_46 0 n2 ns46 0 0.0020908644383 +Gc1_47 0 n2 ns47 0 0.000478980014225 +Gc1_48 0 n2 ns48 0 -5.61270602404e-006 +Gc1_49 0 n2 ns49 0 -6.27827579448e-006 +Gc1_50 0 n2 ns50 0 -0.000390745617416 +Gc1_51 0 n2 ns51 0 0.000577384157185 +Gc1_52 0 n2 ns52 0 3.86815236765e-005 +Gc1_53 0 n2 ns53 0 -0.000160178668768 +Gc1_54 0 n2 ns54 0 0.000115168174945 +Gc1_55 0 n2 ns55 0 -2.21206501822e-005 +Gc1_56 0 n2 ns56 0 3.80292505421e-006 +Gc1_57 0 n2 ns57 0 -2.69023971969e-006 +Gc1_58 0 n2 ns58 0 0.00187092081893 +Gc1_59 0 n2 ns59 0 0.00472371670101 +Gc1_60 0 n2 ns60 0 0.000139657037866 +Gc1_61 0 n2 ns61 0 6.01027254752e-005 +Gc1_62 0 n2 ns62 0 -0.0010068209424 +Gc1_63 0 n2 ns63 0 -0.00029162312181 +Gc1_64 0 n2 ns64 0 -0.000898372567657 +Gc1_65 0 n2 ns65 0 0.000149636041096 +Gc1_66 0 n2 ns66 0 0.000118115171575 +Gc1_67 0 n2 ns67 0 0.000671908134317 +Gc1_68 0 n2 ns68 0 0.00102208757906 +Gc1_69 0 n2 ns69 0 -5.14339215377e-006 +Gc1_70 0 n2 ns70 0 -5.49265554088e-006 +Gc1_71 0 n2 ns71 0 0.000444782497651 +Gc1_72 0 n2 ns72 0 -0.000662435374932 +Gc1_73 0 n2 ns73 0 -6.05134350367e-005 +Gc1_74 0 n2 ns74 0 0.000256020918112 +Gc1_75 0 n2 ns75 0 -0.000527486240166 +Gc1_76 0 n2 ns76 0 0.000162081244839 +Gc1_77 0 n2 ns77 0 -2.71383690556e-006 +Gc1_78 0 n2 ns78 0 8.3343744222e-007 +Gc1_79 0 n2 ns79 0 -0.00183242224472 +Gc1_80 0 n2 ns80 0 -0.00478138192238 +Gc1_81 0 n2 ns81 0 -0.000126637937764 +Gc1_82 0 n2 ns82 0 -6.23359656866e-005 +Gc1_83 0 n2 ns83 0 0.0010087842992 +Gc1_84 0 n2 ns84 0 0.000289222407383 +Gc1_85 0 n2 ns85 0 -0.000313605948044 +Gc1_86 0 n2 ns86 0 8.5339942683e-005 +Gc1_87 0 n2 ns87 0 7.00605444755e-005 +Gc1_88 0 n2 ns88 0 0.000938218855462 +Gc1_89 0 n2 ns89 0 0.00146849369624 +Gc1_90 0 n2 ns90 0 -5.69018059086e-006 +Gc1_91 0 n2 ns91 0 -4.87955577779e-006 +Gc1_92 0 n2 ns92 0 0.000646441556927 +Gc1_93 0 n2 ns93 0 -0.000725264792862 +Gc1_94 0 n2 ns94 0 6.09585470517e-005 +Gc1_95 0 n2 ns95 0 -0.000317478888954 +Gc1_96 0 n2 ns96 0 -0.000761859292962 +Gc1_97 0 n2 ns97 0 0.000630694418648 +Gc1_98 0 n2 ns98 0 -3.9719584735e-006 +Gc1_99 0 n2 ns99 0 5.01430173901e-007 +Gc1_100 0 n2 ns100 0 -0.00305179484979 +Gc1_101 0 n2 ns101 0 -0.00360369040473 +Gc1_102 0 n2 ns102 0 -0.000100843703526 +Gc1_103 0 n2 ns103 0 -7.32836432019e-005 +Gc1_104 0 n2 ns104 0 0.00101651470192 +Gc1_105 0 n2 ns105 0 0.000303075291619 +Gc1_106 0 n2 ns106 0 -0.00792177073079 +Gc1_107 0 n2 ns107 0 0.00237266649102 +Gc1_108 0 n2 ns108 0 -0.00418327208744 +Gc1_109 0 n2 ns109 0 0.00492252910711 +Gc1_110 0 n2 ns110 0 0.00329096453758 +Gc1_111 0 n2 ns111 0 -5.04981682175e-006 +Gc1_112 0 n2 ns112 0 -6.92437677121e-006 +Gc1_113 0 n2 ns113 0 0.000381925223471 +Gc1_114 0 n2 ns114 0 -0.000457191758766 +Gc1_115 0 n2 ns115 0 -1.85519802262e-005 +Gc1_116 0 n2 ns116 0 -5.65737469082e-005 +Gc1_117 0 n2 ns117 0 0.00189104999327 +Gc1_118 0 n2 ns118 0 -0.00123377241077 +Gc1_119 0 n2 ns119 0 5.75449173899e-006 +Gc1_120 0 n2 ns120 0 4.01404144798e-006 +Gc1_121 0 n2 ns121 0 0.00483158747548 +Gc1_122 0 n2 ns122 0 0.00845022219727 +Gc1_123 0 n2 ns123 0 0.000244151708302 +Gc1_124 0 n2 ns124 0 0.000142982268733 +Gc1_125 0 n2 ns125 0 0.00100746888915 +Gc1_126 0 n2 ns126 0 0.000287010435445 +Gd1_1 0 n2 ni1 0 -0.00280672776615 +Gd1_2 0 n2 ni2 0 0.00104682864575 +Gd1_3 0 n2 ni3 0 0.0007372169939 +Gd1_4 0 n2 ni4 0 0.00153698387463 +Gd1_5 0 n2 ni5 0 0.00105431981186 +Gd1_6 0 n2 ni6 0 0.00125411386545 +Gc2_1 0 n4 ns1 0 -8.30808328804e-005 +Gc2_2 0 n4 ns2 0 -0.000336503102426 +Gc2_3 0 n4 ns3 0 0.00167025897483 +Gc2_4 0 n4 ns4 0 0.00207396871729 +Gc2_5 0 n4 ns5 0 0.000228691274574 +Gc2_6 0 n4 ns6 0 -5.74101515349e-006 +Gc2_7 0 n4 ns7 0 -6.34594438626e-006 +Gc2_8 0 n4 ns8 0 -0.000583784681926 +Gc2_9 0 n4 ns9 0 0.000694216656842 +Gc2_10 0 n4 ns10 0 -3.12032289759e-006 +Gc2_11 0 n4 ns11 0 0.000175465828705 +Gc2_12 0 n4 ns12 0 0.000428984388335 +Gc2_13 0 n4 ns13 0 -0.000428260504944 +Gc2_14 0 n4 ns14 0 4.71471281462e-006 +Gc2_15 0 n4 ns15 0 -2.24571777726e-006 +Gc2_16 0 n4 ns16 0 0.0030816739401 +Gc2_17 0 n4 ns17 0 0.00355709570245 +Gc2_18 0 n4 ns18 0 0.000112674120918 +Gc2_19 0 n4 ns19 0 7.19142578279e-005 +Gc2_20 0 n4 ns20 0 -0.00101782250543 +Gc2_21 0 n4 ns21 0 -0.000308472795502 +Gc2_22 0 n4 ns22 0 0.0218869750633 +Gc2_23 0 n4 ns23 0 -0.00173641082152 +Gc2_24 0 n4 ns24 0 0.00105262121519 +Gc2_25 0 n4 ns25 0 -0.00536908944159 +Gc2_26 0 n4 ns26 0 -0.00622316941489 +Gc2_27 0 n4 ns27 0 -4.84143611992e-006 +Gc2_28 0 n4 ns28 0 -6.342139365e-006 +Gc2_29 0 n4 ns29 0 -0.000795332163768 +Gc2_30 0 n4 ns30 0 0.000937993894489 +Gc2_31 0 n4 ns31 0 -0.000489131478567 +Gc2_32 0 n4 ns32 0 0.000573125517634 +Gc2_33 0 n4 ns33 0 -0.00017252087907 +Gc2_34 0 n4 ns34 0 0.000186830483196 +Gc2_35 0 n4 ns35 0 -5.03030373833e-007 +Gc2_36 0 n4 ns36 0 1.01760949296e-005 +Gc2_37 0 n4 ns37 0 -0.00509434502702 +Gc2_38 0 n4 ns38 0 -0.00810274971471 +Gc2_39 0 n4 ns39 0 -0.000246352557544 +Gc2_40 0 n4 ns40 0 -0.000142379350777 +Gc2_41 0 n4 ns41 0 -0.00101138315599 +Gc2_42 0 n4 ns42 0 -0.000286737253767 +Gc2_43 0 n4 ns43 0 0.000107338984208 +Gc2_44 0 n4 ns44 0 -0.000257233352507 +Gc2_45 0 n4 ns45 0 0.00145169384723 +Gc2_46 0 n4 ns46 0 0.00205477252518 +Gc2_47 0 n4 ns47 0 0.000450152864536 +Gc2_48 0 n4 ns48 0 -5.48166035215e-006 +Gc2_49 0 n4 ns49 0 -6.76344413276e-006 +Gc2_50 0 n4 ns50 0 -0.000533880236298 +Gc2_51 0 n4 ns51 0 0.000782466942571 +Gc2_52 0 n4 ns52 0 0.000460579110315 +Gc2_53 0 n4 ns53 0 -0.000453601716073 +Gc2_54 0 n4 ns54 0 -5.94758942864e-005 +Gc2_55 0 n4 ns55 0 8.20126916846e-006 +Gc2_56 0 n4 ns56 0 3.99053435454e-006 +Gc2_57 0 n4 ns57 0 -3.51478455257e-006 +Gc2_58 0 n4 ns58 0 0.00231243440645 +Gc2_59 0 n4 ns59 0 0.00428133336843 +Gc2_60 0 n4 ns60 0 0.000145835147981 +Gc2_61 0 n4 ns61 0 6.17934168336e-005 +Gc2_62 0 n4 ns62 0 -0.00100207587111 +Gc2_63 0 n4 ns63 0 -0.000291488107199 +Gc2_64 0 n4 ns64 0 -0.00031112170923 +Gc2_65 0 n4 ns65 0 0.00012432765815 +Gc2_66 0 n4 ns66 0 0.000185647254129 +Gc2_67 0 n4 ns67 0 0.00057090544851 +Gc2_68 0 n4 ns68 0 0.00117957612146 +Gc2_69 0 n4 ns69 0 -5.14744433455e-006 +Gc2_70 0 n4 ns70 0 -4.94510583262e-006 +Gc2_71 0 n4 ns71 0 0.000602908093172 +Gc2_72 0 n4 ns72 0 -0.000890797866434 +Gc2_73 0 n4 ns73 0 -0.00085010272981 +Gc2_74 0 n4 ns74 0 0.000739625660165 +Gc2_75 0 n4 ns75 0 0.000190826463586 +Gc2_76 0 n4 ns76 0 -9.94310661447e-005 +Gc2_77 0 n4 ns77 0 -3.67330118711e-006 +Gc2_78 0 n4 ns78 0 1.0556931228e-006 +Gc2_79 0 n4 ns79 0 -0.00228456291025 +Gc2_80 0 n4 ns80 0 -0.00432382102348 +Gc2_81 0 n4 ns81 0 -0.000134068110714 +Gc2_82 0 n4 ns82 0 -6.43410921723e-005 +Gc2_83 0 n4 ns83 0 0.00100468116533 +Gc2_84 0 n4 ns84 0 0.000288417162173 +Gc2_85 0 n4 ns85 0 -0.00685340255488 +Gc2_86 0 n4 ns86 0 0.00229986522018 +Gc2_87 0 n4 ns87 0 -0.00259768177081 +Gc2_88 0 n4 ns88 0 0.00832003992739 +Gc2_89 0 n4 ns89 0 0.00347280087967 +Gc2_90 0 n4 ns90 0 -4.9165368427e-006 +Gc2_91 0 n4 ns91 0 -6.5855269005e-006 +Gc2_92 0 n4 ns92 0 0.000883701586514 +Gc2_93 0 n4 ns93 0 -0.000975904085022 +Gc2_94 0 n4 ns94 0 0.000951465623373 +Gc2_95 0 n4 ns95 0 -0.000896445270734 +Gc2_96 0 n4 ns96 0 0.000250451051286 +Gc2_97 0 n4 ns97 0 -0.000309050904188 +Gc2_98 0 n4 ns98 0 6.01295089772e-006 +Gc2_99 0 n4 ns99 0 6.46021826511e-006 +Gc2_100 0 n4 ns100 0 0.00532154240132 +Gc2_101 0 n4 ns101 0 0.00795341328677 +Gc2_102 0 n4 ns102 0 0.000260666014805 +Gc2_103 0 n4 ns103 0 0.000143259517578 +Gc2_104 0 n4 ns104 0 0.00100199396674 +Gc2_105 0 n4 ns105 0 0.000286485270628 +Gc2_106 0 n4 ns106 0 -0.000611393795003 +Gc2_107 0 n4 ns107 0 0.000273386921835 +Gc2_108 0 n4 ns108 0 -0.000627249859555 +Gc2_109 0 n4 ns109 0 -0.000466909157641 +Gc2_110 0 n4 ns110 0 0.00141474055887 +Gc2_111 0 n4 ns111 0 -4.08859401655e-006 +Gc2_112 0 n4 ns112 0 -6.45344198543e-006 +Gc2_113 0 n4 ns113 0 0.0005134997665 +Gc2_114 0 n4 ns114 0 -0.000613058757875 +Gc2_115 0 n4 ns115 0 -6.50812520432e-006 +Gc2_116 0 n4 ns116 0 -0.000217734322007 +Gc2_117 0 n4 ns117 0 -0.000718351136383 +Gc2_118 0 n4 ns118 0 0.000607525836859 +Gc2_119 0 n4 ns119 0 -3.48609789774e-006 +Gc2_120 0 n4 ns120 0 -7.92134513941e-007 +Gc2_121 0 n4 ns121 0 -0.00305179940584 +Gc2_122 0 n4 ns122 0 -0.00361128698807 +Gc2_123 0 n4 ns123 0 -9.97153590979e-005 +Gc2_124 0 n4 ns124 0 -7.52229111105e-005 +Gc2_125 0 n4 ns125 0 0.00101707064654 +Gc2_126 0 n4 ns126 0 0.00030937277032 +Gd2_1 0 n4 ni1 0 0.00106633082545 +Gd2_2 0 n4 ni2 0 -0.00136591216331 +Gd2_3 0 n4 ni3 0 0.000789674675323 +Gd2_4 0 n4 ni4 0 0.0012244394262 +Gd2_5 0 n4 ni5 0 -0.000489862655362 +Gd2_6 0 n4 ni6 0 0.00161429164909 +Gc3_1 0 n6 ns1 0 0.000305909168234 +Gc3_2 0 n6 ns2 0 -0.000173363855128 +Gc3_3 0 n6 ns3 0 0.0015521770839 +Gc3_4 0 n6 ns4 0 0.00207296839627 +Gc3_5 0 n6 ns5 0 0.000464516230194 +Gc3_6 0 n6 ns6 0 -5.6503980843e-006 +Gc3_7 0 n6 ns7 0 -6.22176448473e-006 +Gc3_8 0 n6 ns8 0 -0.000390841446555 +Gc3_9 0 n6 ns9 0 0.000576904759487 +Gc3_10 0 n6 ns10 0 3.84826563251e-005 +Gc3_11 0 n6 ns11 0 -0.000160051818175 +Gc3_12 0 n6 ns12 0 0.000115103183538 +Gc3_13 0 n6 ns13 0 -2.1808760774e-005 +Gc3_14 0 n6 ns14 0 3.73881926613e-006 +Gc3_15 0 n6 ns15 0 -2.55227386142e-006 +Gc3_16 0 n6 ns16 0 0.00187022745968 +Gc3_17 0 n6 ns17 0 0.00472358280852 +Gc3_18 0 n6 ns18 0 0.000138882054132 +Gc3_19 0 n6 ns19 0 6.08782634769e-005 +Gc3_20 0 n6 ns20 0 -0.00100949491917 +Gc3_21 0 n6 ns21 0 -0.00029241854847 +Gc3_22 0 n6 ns22 0 7.61411500572e-005 +Gc3_23 0 n6 ns23 0 -0.000252039353803 +Gc3_24 0 n6 ns24 0 0.00144073153853 +Gc3_25 0 n6 ns25 0 0.00203221007246 +Gc3_26 0 n6 ns26 0 0.000435522686182 +Gc3_27 0 n6 ns27 0 -5.46289465444e-006 +Gc3_28 0 n6 ns28 0 -6.71450597798e-006 +Gc3_29 0 n6 ns29 0 -0.000533985689262 +Gc3_30 0 n6 ns30 0 0.000781659081613 +Gc3_31 0 n6 ns31 0 0.00046033081195 +Gc3_32 0 n6 ns32 0 -0.000452999752968 +Gc3_33 0 n6 ns33 0 -5.95330199217e-005 +Gc3_34 0 n6 ns34 0 8.24850770809e-006 +Gc3_35 0 n6 ns35 0 3.91303353121e-006 +Gc3_36 0 n6 ns36 0 -3.18704454804e-006 +Gc3_37 0 n6 ns37 0 0.00231304576716 +Gc3_38 0 n6 ns38 0 0.00428008193289 +Gc3_39 0 n6 ns39 0 0.00014505529581 +Gc3_40 0 n6 ns40 0 6.26093107371e-005 +Gc3_41 0 n6 ns41 0 -0.0010047131693 +Gc3_42 0 n6 ns42 0 -0.000289012399609 +Gc3_43 0 n6 ns43 0 0.0224680366056 +Gc3_44 0 n6 ns44 0 -0.00241825099092 +Gc3_45 0 n6 ns45 0 0.00122198407999 +Gc3_46 0 n6 ns46 0 -0.00464998553104 +Gc3_47 0 n6 ns47 0 -0.00496573861025 +Gc3_48 0 n6 ns48 0 -4.94656944141e-006 +Gc3_49 0 n6 ns49 0 -6.13369134582e-006 +Gc3_50 0 n6 ns50 0 -0.000343858877795 +Gc3_51 0 n6 ns51 0 0.000638227623975 +Gc3_52 0 n6 ns52 0 -0.000378292175401 +Gc3_53 0 n6 ns53 0 0.000314292198702 +Gc3_54 0 n6 ns54 0 -2.69625459562e-005 +Gc3_55 0 n6 ns55 0 -1.4618441913e-005 +Gc3_56 0 n6 ns56 0 5.22367102747e-008 +Gc3_57 0 n6 ns57 0 1.18759404912e-005 +Gc3_58 0 n6 ns58 0 -0.00388160408965 +Gc3_59 0 n6 ns59 0 -0.00925901022256 +Gc3_60 0 n6 ns60 0 -0.000262249244794 +Gc3_61 0 n6 ns61 0 -0.000136769861959 +Gc3_62 0 n6 ns62 0 -0.0010093221369 +Gc3_63 0 n6 ns63 0 -0.000292024586466 +Gc3_64 0 n6 ns64 0 -0.00810617368719 +Gc3_65 0 n6 ns65 0 0.0024086954059 +Gc3_66 0 n6 ns66 0 -0.0025233366951 +Gc3_67 0 n6 ns67 0 0.00725068636798 +Gc3_68 0 n6 ns68 0 0.00167484945493 +Gc3_69 0 n6 ns69 0 -5.18557404172e-006 +Gc3_70 0 n6 ns70 0 -6.89535972641e-006 +Gc3_71 0 n6 ns71 0 0.000400609539068 +Gc3_72 0 n6 ns72 0 -0.000733887573896 +Gc3_73 0 n6 ns73 0 0.000764243977871 +Gc3_74 0 n6 ns74 0 -0.000568357153619 +Gc3_75 0 n6 ns75 0 2.73122917803e-005 +Gc3_76 0 n6 ns76 0 -2.21576482285e-006 +Gc3_77 0 n6 ns77 0 5.26088767581e-006 +Gc3_78 0 n6 ns78 0 7.92652694017e-006 +Gc3_79 0 n6 ns79 0 0.0041497960105 +Gc3_80 0 n6 ns80 0 0.00906478515233 +Gc3_81 0 n6 ns81 0 0.000290016936243 +Gc3_82 0 n6 ns82 0 0.000130710495405 +Gc3_83 0 n6 ns83 0 0.0010060981596 +Gc3_84 0 n6 ns84 0 0.000294535176094 +Gc3_85 0 n6 ns85 0 -0.000111126548952 +Gc3_86 0 n6 ns86 0 0.000331024976978 +Gc3_87 0 n6 ns87 0 -0.000324788592701 +Gc3_88 0 n6 ns88 0 -7.96145148083e-005 +Gc3_89 0 n6 ns89 0 0.00143056497292 +Gc3_90 0 n6 ns90 0 -4.19816826915e-006 +Gc3_91 0 n6 ns91 0 -5.77722960412e-006 +Gc3_92 0 n6 ns92 0 0.000595193457196 +Gc3_93 0 n6 ns93 0 -0.000814358408893 +Gc3_94 0 n6 ns94 0 -0.000808830122616 +Gc3_95 0 n6 ns95 0 0.000638034046866 +Gc3_96 0 n6 ns96 0 7.13870213576e-005 +Gc3_97 0 n6 ns97 0 -1.89627510856e-005 +Gc3_98 0 n6 ns98 0 -3.20322237186e-006 +Gc3_99 0 n6 ns99 0 4.62917840188e-007 +Gc3_100 0 n6 ns100 0 -0.00227859598496 +Gc3_101 0 n6 ns101 0 -0.00433751307514 +Gc3_102 0 n6 ns102 0 -0.000132830849558 +Gc3_103 0 n6 ns103 0 -6.59570990097e-005 +Gc3_104 0 n6 ns104 0 0.0010055529516 +Gc3_105 0 n6 ns105 0 0.000291859650385 +Gc3_106 0 n6 ns106 0 -0.000536388236096 +Gc3_107 0 n6 ns107 0 0.000417350011971 +Gc3_108 0 n6 ns108 0 -0.000286351316105 +Gc3_109 0 n6 ns109 0 0.000328150178475 +Gc3_110 0 n6 ns110 0 0.00132858524975 +Gc3_111 0 n6 ns111 0 -5.2487614452e-006 +Gc3_112 0 n6 ns112 0 -5.20495268507e-006 +Gc3_113 0 n6 ns113 0 0.000346427053746 +Gc3_114 0 n6 ns114 0 -0.000512565796893 +Gc3_115 0 n6 ns115 0 -4.99724031583e-006 +Gc3_116 0 n6 ns116 0 0.0001569990955 +Gc3_117 0 n6 ns117 0 -0.000203421457252 +Gc3_118 0 n6 ns118 0 1.33192137353e-005 +Gc3_119 0 n6 ns119 0 -3.20796471254e-006 +Gc3_120 0 n6 ns120 0 -1.38167697212e-007 +Gc3_121 0 n6 ns121 0 -0.00184452388386 +Gc3_122 0 n6 ns122 0 -0.00476636168279 +Gc3_123 0 n6 ns123 0 -0.000128095095871 +Gc3_124 0 n6 ns124 0 -6.34410168436e-005 +Gc3_125 0 n6 ns125 0 0.00100929852474 +Gc3_126 0 n6 ns126 0 0.000294238089897 +Gd3_1 0 n6 ni1 0 0.000752497103696 +Gd3_2 0 n6 ni2 0 0.000807472868009 +Gd3_3 0 n6 ni3 0 -0.00168458536905 +Gd3_4 0 n6 ni4 0 0.000667972953542 +Gd3_5 0 n6 ni5 0 0.00118273655059 +Gd3_6 0 n6 ni6 0 0.00109699106147 +Gc4_1 0 n8 ns1 0 -0.000907715939428 +Gc4_2 0 n8 ns2 0 0.000149052397348 +Gc4_3 0 n8 ns3 0 0.000111726227128 +Gc4_4 0 n8 ns4 0 0.00066130637703 +Gc4_5 0 n8 ns5 0 0.00102282687906 +Gc4_6 0 n8 ns6 0 -5.15808369483e-006 +Gc4_7 0 n8 ns7 0 -5.48112355042e-006 +Gc4_8 0 n8 ns8 0 0.000444885072635 +Gc4_9 0 n8 ns9 0 -0.00066231858883 +Gc4_10 0 n8 ns10 0 -6.09347875756e-005 +Gc4_11 0 n8 ns11 0 0.000256088883104 +Gc4_12 0 n8 ns12 0 -0.000527374089946 +Gc4_13 0 n8 ns13 0 0.000162097689207 +Gc4_14 0 n8 ns14 0 -2.77598203976e-006 +Gc4_15 0 n8 ns15 0 7.03044409328e-007 +Gc4_16 0 n8 ns16 0 -0.00183236489338 +Gc4_17 0 n8 ns17 0 -0.00478043546927 +Gc4_18 0 n8 ns18 0 -0.000126626201058 +Gc4_19 0 n8 ns19 0 -6.20486673343e-005 +Gc4_20 0 n8 ns20 0 0.00100790191976 +Gc4_21 0 n8 ns21 0 0.000290769097355 +Gc4_22 0 n8 ns22 0 -0.000326249032337 +Gc4_23 0 n8 ns23 0 0.000126586534997 +Gc4_24 0 n8 ns24 0 0.000178355520715 +Gc4_25 0 n8 ns25 0 0.000557148456248 +Gc4_26 0 n8 ns26 0 0.00117545999937 +Gc4_27 0 n8 ns27 0 -5.13694011926e-006 +Gc4_28 0 n8 ns28 0 -4.90434283008e-006 +Gc4_29 0 n8 ns29 0 0.000603121409867 +Gc4_30 0 n8 ns30 0 -0.000890719563937 +Gc4_31 0 n8 ns31 0 -0.000850364990738 +Gc4_32 0 n8 ns32 0 0.000739159488367 +Gc4_33 0 n8 ns33 0 0.000190825157731 +Gc4_34 0 n8 ns34 0 -9.912458215e-005 +Gc4_35 0 n8 ns35 0 -3.68151424698e-006 +Gc4_36 0 n8 ns36 0 1.08675980056e-006 +Gc4_37 0 n8 ns37 0 -0.00228258402823 +Gc4_38 0 n8 ns38 0 -0.00432449581924 +Gc4_39 0 n8 ns39 0 -0.000134106810415 +Gc4_40 0 n8 ns40 0 -6.36105441401e-005 +Gc4_41 0 n8 ns41 0 0.00100320143441 +Gc4_42 0 n8 ns42 0 0.000284475855182 +Gc4_43 0 n8 ns43 0 -0.00817256731627 +Gc4_44 0 n8 ns44 0 0.00242213702756 +Gc4_45 0 n8 ns45 0 -0.00255198344928 +Gc4_46 0 n8 ns46 0 0.00720727549624 +Gc4_47 0 n8 ns47 0 0.00165088380844 +Gc4_48 0 n8 ns48 0 -4.96526774314e-006 +Gc4_49 0 n8 ns49 0 -7.02534276481e-006 +Gc4_50 0 n8 ns50 0 0.000400927547281 +Gc4_51 0 n8 ns51 0 -0.000734512120724 +Gc4_52 0 n8 ns52 0 0.000764558507454 +Gc4_53 0 n8 ns53 0 -0.000569160017546 +Gc4_54 0 n8 ns54 0 2.67688854904e-005 +Gc4_55 0 n8 ns55 0 -1.93067743068e-006 +Gc4_56 0 n8 ns56 0 5.93086984232e-006 +Gc4_57 0 n8 ns57 0 7.78985989314e-006 +Gc4_58 0 n8 ns58 0 0.0041546405315 +Gc4_59 0 n8 ns59 0 0.00905934132354 +Gc4_60 0 n8 ns60 0 0.000291657036036 +Gc4_61 0 n8 ns61 0 0.000128685653068 +Gc4_62 0 n8 ns62 0 0.00101218760594 +Gc4_63 0 n8 ns63 0 0.00029613597311 +Gc4_64 0 n8 ns64 0 0.0216668492595 +Gc4_65 0 n8 ns65 0 -0.00326856670073 +Gc4_66 0 n8 ns66 0 0.00143996345174 +Gc4_67 0 n8 ns67 0 -0.00641913410787 +Gc4_68 0 n8 ns68 0 -0.00595564587606 +Gc4_69 0 n8 ns69 0 -4.10228107531e-006 +Gc4_70 0 n8 ns70 0 -7.27280775774e-006 +Gc4_71 0 n8 ns71 0 -0.000417278496372 +Gc4_72 0 n8 ns72 0 0.000798769317222 +Gc4_73 0 n8 ns73 0 -0.00138887792858 +Gc4_74 0 n8 ns74 0 0.000905630707934 +Gc4_75 0 n8 ns75 0 -0.000210799559959 +Gc4_76 0 n8 ns76 0 -1.26930359047e-005 +Gc4_77 0 n8 ns77 0 -4.40537194763e-008 +Gc4_78 0 n8 ns78 0 1.24504688476e-005 +Gc4_79 0 n8 ns79 0 -0.00393745125204 +Gc4_80 0 n8 ns80 0 -0.00924152853799 +Gc4_81 0 n8 ns81 0 -0.000273693608989 +Gc4_82 0 n8 ns82 0 -0.000127760399706 +Gc4_83 0 n8 ns83 0 -0.0010213047252 +Gc4_84 0 n8 ns84 0 -0.000305635450685 +Gc4_85 0 n8 ns85 0 0.000594714205443 +Gc4_86 0 n8 ns86 0 0.000368822496011 +Gc4_87 0 n8 ns87 0 0.000984683703733 +Gc4_88 0 n8 ns88 0 0.00262376646032 +Gc4_89 0 n8 ns89 0 0.00116193505946 +Gc4_90 0 n8 ns90 0 -5.41838042515e-006 +Gc4_91 0 n8 ns91 0 -6.23790966584e-006 +Gc4_92 0 n8 ns92 0 -0.000643207083833 +Gc4_93 0 n8 ns93 0 0.00089326909824 +Gc4_94 0 n8 ns94 0 0.00154498819104 +Gc4_95 0 n8 ns95 0 -0.00109567782791 +Gc4_96 0 n8 ns96 0 -0.000346054892166 +Gc4_97 0 n8 ns97 0 0.000129091043853 +Gc4_98 0 n8 ns98 0 3.19728279296e-006 +Gc4_99 0 n8 ns99 0 -4.06712546616e-006 +Gc4_100 0 n8 ns100 0 0.00230900253782 +Gc4_101 0 n8 ns101 0 0.00430629939767 +Gc4_102 0 n8 ns102 0 0.000145262908944 +Gc4_103 0 n8 ns103 0 6.02658257185e-005 +Gc4_104 0 n8 ns104 0 -0.0010029862188 +Gc4_105 0 n8 ns105 0 -0.000286611891082 +Gc4_106 0 n8 ns106 0 0.000888316600806 +Gc4_107 0 n8 ns107 0 0.000521357055188 +Gc4_108 0 n8 ns108 0 0.000877965564159 +Gc4_109 0 n8 ns109 0 0.00247671354686 +Gc4_110 0 n8 ns110 0 0.00129304649649 +Gc4_111 0 n8 ns111 0 -5.20470982142e-006 +Gc4_112 0 n8 ns112 0 -5.9677270369e-006 +Gc4_113 0 n8 ns113 0 -0.000369419365812 +Gc4_114 0 n8 ns114 0 0.000555711247542 +Gc4_115 0 n8 ns115 0 4.66688111124e-005 +Gc4_116 0 n8 ns116 0 -0.000316167900005 +Gc4_117 0 n8 ns117 0 0.000792654544098 +Gc4_118 0 n8 ns118 0 -0.000212144676636 +Gc4_119 0 n8 ns119 0 2.95506031261e-006 +Gc4_120 0 n8 ns120 0 -2.82793137938e-006 +Gc4_121 0 n8 ns121 0 0.00186978425418 +Gc4_122 0 n8 ns122 0 0.0047454677199 +Gc4_123 0 n8 ns123 0 0.00013900220821 +Gc4_124 0 n8 ns124 0 5.88095396122e-005 +Gc4_125 0 n8 ns125 0 -0.0010072215218 +Gc4_126 0 n8 ns126 0 -0.000289983622611 +Gd4_1 0 n8 ni1 0 0.00154786721333 +Gd4_2 0 n8 ni2 0 0.00123598561463 +Gd4_3 0 n8 ni3 0 0.000703204365801 +Gd4_4 0 n8 ni4 0 0.00050582315805 +Gd4_5 0 n8 ni5 0 -0.000423745753501 +Gd4_6 0 n8 ni6 0 -0.00052835349753 +Gc5_1 0 n10 ns1 0 -0.000323338525814 +Gc5_2 0 n10 ns2 0 8.53403843416e-005 +Gc5_3 0 n10 ns3 0 6.21186154378e-005 +Gc5_4 0 n10 ns4 0 0.000923535539274 +Gc5_5 0 n10 ns5 0 0.00146957913998 +Gc5_6 0 n10 ns6 0 -5.67729026241e-006 +Gc5_7 0 n10 ns7 0 -4.8442772054e-006 +Gc5_8 0 n10 ns8 0 0.000646602692735 +Gc5_9 0 n10 ns9 0 -0.000725113016821 +Gc5_10 0 n10 ns10 0 6.08890114431e-005 +Gc5_11 0 n10 ns11 0 -0.000317293094947 +Gc5_12 0 n10 ns12 0 -0.000761776253031 +Gc5_13 0 n10 ns13 0 0.000630667425153 +Gc5_14 0 n10 ns14 0 -4.08984159452e-006 +Gc5_15 0 n10 ns15 0 3.27925589019e-007 +Gc5_16 0 n10 ns16 0 -0.00305317255798 +Gc5_17 0 n10 ns17 0 -0.00360157870769 +Gc5_18 0 n10 ns18 0 -0.00010152066615 +Gc5_19 0 n10 ns19 0 -7.22642809244e-005 +Gc5_20 0 n10 ns20 0 0.00101532424615 +Gc5_21 0 n10 ns21 0 0.000300498215864 +Gc5_22 0 n10 ns22 0 -0.0068922132886 +Gc5_23 0 n10 ns23 0 0.00230460993755 +Gc5_24 0 n10 ns24 0 -0.0026211011289 +Gc5_25 0 n10 ns25 0 0.00829366160418 +Gc5_26 0 n10 ns26 0 0.00346908910357 +Gc5_27 0 n10 ns27 0 -4.74153502352e-006 +Gc5_28 0 n10 ns28 0 -6.70565684333e-006 +Gc5_29 0 n10 ns29 0 0.000884413300207 +Gc5_30 0 n10 ns30 0 -0.000976599203428 +Gc5_31 0 n10 ns31 0 0.000952013268506 +Gc5_32 0 n10 ns32 0 -0.000897240551243 +Gc5_33 0 n10 ns33 0 0.000250234596366 +Gc5_34 0 n10 ns34 0 -0.000309251233824 +Gc5_35 0 n10 ns35 0 6.63926953036e-006 +Gc5_36 0 n10 ns36 0 6.27087676538e-006 +Gc5_37 0 n10 ns37 0 0.00532339771495 +Gc5_38 0 n10 ns38 0 0.00795255612072 +Gc5_39 0 n10 ns39 0 0.000261000777043 +Gc5_40 0 n10 ns40 0 0.00014156167967 +Gc5_41 0 n10 ns41 0 0.00100729182721 +Gc5_42 0 n10 ns42 0 0.000285693397478 +Gc5_43 0 n10 ns43 0 -0.000141948233369 +Gc5_44 0 n10 ns44 0 0.000337039245387 +Gc5_45 0 n10 ns45 0 -0.000338309606828 +Gc5_46 0 n10 ns46 0 -0.000107081794418 +Gc5_47 0 n10 ns47 0 0.00141959107626 +Gc5_48 0 n10 ns48 0 -4.16000232072e-006 +Gc5_49 0 n10 ns49 0 -5.72365166228e-006 +Gc5_50 0 n10 ns50 0 0.000595332579268 +Gc5_51 0 n10 ns51 0 -0.000814822786179 +Gc5_52 0 n10 ns52 0 -0.000809386930463 +Gc5_53 0 n10 ns53 0 0.000638304977317 +Gc5_54 0 n10 ns54 0 7.1454498066e-005 +Gc5_55 0 n10 ns55 0 -1.87069747138e-005 +Gc5_56 0 n10 ns56 0 -3.41582040696e-006 +Gc5_57 0 n10 ns57 0 4.04163302581e-007 +Gc5_58 0 n10 ns58 0 -0.0022784702998 +Gc5_59 0 n10 ns59 0 -0.00433881536961 +Gc5_60 0 n10 ns60 0 -0.000132518914468 +Gc5_61 0 n10 ns61 0 -6.59550241669e-005 +Gc5_62 0 n10 ns62 0 0.00100413971423 +Gc5_63 0 n10 ns63 0 0.000291083177397 +Gc5_64 0 n10 ns64 0 0.000598001797693 +Gc5_65 0 n10 ns65 0 0.000368427909357 +Gc5_66 0 n10 ns66 0 0.00098619565876 +Gc5_67 0 n10 ns67 0 0.00262673211907 +Gc5_68 0 n10 ns68 0 0.00116254434459 +Gc5_69 0 n10 ns69 0 -5.44780348714e-006 +Gc5_70 0 n10 ns70 0 -6.1518689738e-006 +Gc5_71 0 n10 ns71 0 -0.000643050453853 +Gc5_72 0 n10 ns72 0 0.000893058425428 +Gc5_73 0 n10 ns73 0 0.00154484120532 +Gc5_74 0 n10 ns74 0 -0.00109587449833 +Gc5_75 0 n10 ns75 0 -0.000346258224043 +Gc5_76 0 n10 ns76 0 0.000129212790817 +Gc5_77 0 n10 ns77 0 3.02998412616e-006 +Gc5_78 0 n10 ns78 0 -4.2237139721e-006 +Gc5_79 0 n10 ns79 0 0.00230808893947 +Gc5_80 0 n10 ns80 0 0.00430761019895 +Gc5_81 0 n10 ns81 0 0.000145133880501 +Gc5_82 0 n10 ns82 0 6.06406974406e-005 +Gc5_83 0 n10 ns83 0 -0.00100448281649 +Gc5_84 0 n10 ns84 0 -0.00028921428402 +Gc5_85 0 n10 ns85 0 0.0194355691828 +Gc5_86 0 n10 ns86 0 -0.00334545848509 +Gc5_87 0 n10 ns87 0 0.00200632710333 +Gc5_88 0 n10 ns88 0 -0.00715038805938 +Gc5_89 0 n10 ns89 0 -0.00837839333092 +Gc5_90 0 n10 ns90 0 -4.9044557451e-006 +Gc5_91 0 n10 ns91 0 -6.87013324437e-006 +Gc5_92 0 n10 ns92 0 -0.000932929853712 +Gc5_93 0 n10 ns93 0 0.000970911866683 +Gc5_94 0 n10 ns94 0 -0.00167567004165 +Gc5_95 0 n10 ns95 0 0.00126836552109 +Gc5_96 0 n10 ns96 0 -0.000476312801212 +Gc5_97 0 n10 ns97 0 0.00044234808911 +Gc5_98 0 n10 ns98 0 -7.01792689148e-007 +Gc5_99 0 n10 ns99 0 1.11407842959e-005 +Gc5_100 0 n10 ns100 0 -0.00515479016383 +Gc5_101 0 n10 ns101 0 -0.00808722578987 +Gc5_102 0 n10 ns102 0 -0.00025636486131 +Gc5_103 0 n10 ns103 0 -0.000134980027678 +Gc5_104 0 n10 ns104 0 -0.00101987156411 +Gc5_105 0 n10 ns105 0 -0.000293697572431 +Gc5_106 0 n10 ns106 0 0.000845295512395 +Gc5_107 0 n10 ns107 0 0.000573272777575 +Gc5_108 0 n10 ns108 0 0.000901996038174 +Gc5_109 0 n10 ns109 0 0.00232623748947 +Gc5_110 0 n10 ns110 0 0.00114866984449 +Gc5_111 0 n10 ns111 0 -4.84888311812e-006 +Gc5_112 0 n10 ns112 0 -6.38254050804e-006 +Gc5_113 0 n10 ns113 0 -0.000542877063283 +Gc5_114 0 n10 ns114 0 0.000609291907913 +Gc5_115 0 n10 ns115 0 -5.69622710047e-006 +Gc5_116 0 n10 ns116 0 0.000331633408853 +Gc5_117 0 n10 ns117 0 0.00118952208893 +Gc5_118 0 n10 ns118 0 -0.000907845953235 +Gc5_119 0 n10 ns119 0 4.05477101123e-006 +Gc5_120 0 n10 ns120 0 -2.33627657378e-006 +Gc5_121 0 n10 ns121 0 0.00309165863712 +Gc5_122 0 n10 ns122 0 0.00357266316415 +Gc5_123 0 n10 ns123 0 0.000113859729863 +Gc5_124 0 n10 ns124 0 6.903484436e-005 +Gc5_125 0 n10 ns125 0 -0.00101441900267 +Gc5_126 0 n10 ns126 0 -0.000299600323303 +Gd5_1 0 n10 ni1 0 0.00106690594853 +Gd5_2 0 n10 ni2 0 -0.000465529901725 +Gd5_3 0 n10 ni3 0 0.00120517392834 +Gd5_4 0 n10 ni4 0 -0.000426629078772 +Gd5_5 0 n10 ni5 0 0.00248159691606 +Gd5_6 0 n10 ni6 0 -0.000572090999791 +Gc6_1 0 n12 ns1 0 -0.00796629751969 +Gc6_2 0 n12 ns2 0 0.00237519753979 +Gc6_3 0 n12 ns3 0 -0.00419658078266 +Gc6_4 0 n12 ns4 0 0.00489761714407 +Gc6_5 0 n12 ns5 0 0.00327201683143 +Gc6_6 0 n12 ns6 0 -5.14583240537e-006 +Gc6_7 0 n12 ns7 0 -6.5983790567e-006 +Gc6_8 0 n12 ns8 0 0.000381391006431 +Gc6_9 0 n12 ns9 0 -0.000457307412616 +Gc6_10 0 n12 ns10 0 -1.96797568878e-005 +Gc6_11 0 n12 ns11 0 -5.69646628972e-005 +Gc6_12 0 n12 ns12 0 0.00189131986207 +Gc6_13 0 n12 ns13 0 -0.00123254067476 +Gc6_14 0 n12 ns14 0 5.80039425347e-006 +Gc6_15 0 n12 ns15 0 4.09948299539e-006 +Gc6_16 0 n12 ns16 0 0.00483325564431 +Gc6_17 0 n12 ns17 0 0.00844814314336 +Gc6_18 0 n12 ns18 0 0.000243324096337 +Gc6_19 0 n12 ns19 0 0.000143685813779 +Gc6_20 0 n12 ns20 0 0.00100561905127 +Gc6_21 0 n12 ns21 0 0.000283599653814 +Gc6_22 0 n12 ns22 0 -0.000640315536073 +Gc6_23 0 n12 ns23 0 0.000278861616699 +Gc6_24 0 n12 ns24 0 -0.000640164894751 +Gc6_25 0 n12 ns25 0 -0.000492861682131 +Gc6_26 0 n12 ns26 0 0.00140493256523 +Gc6_27 0 n12 ns27 0 -4.04680942267e-006 +Gc6_28 0 n12 ns28 0 -6.40365788306e-006 +Gc6_29 0 n12 ns29 0 0.00051367935792 +Gc6_30 0 n12 ns30 0 -0.000613202478756 +Gc6_31 0 n12 ns31 0 -6.58874868128e-006 +Gc6_32 0 n12 ns32 0 -0.000217937644978 +Gc6_33 0 n12 ns33 0 -0.000718629896553 +Gc6_34 0 n12 ns34 0 0.000607934637605 +Gc6_35 0 n12 ns35 0 -3.70494038674e-006 +Gc6_36 0 n12 ns36 0 -7.6122401693e-007 +Gc6_37 0 n12 ns37 0 -0.00305079984077 +Gc6_38 0 n12 ns38 0 -0.00361378786257 +Gc6_39 0 n12 ns39 0 -9.92160053308e-005 +Gc6_40 0 n12 ns40 0 -7.48171491502e-005 +Gc6_41 0 n12 ns41 0 0.00101532553008 +Gc6_42 0 n12 ns42 0 0.000306677398204 +Gc6_43 0 n12 ns43 0 -0.000566333976922 +Gc6_44 0 n12 ns44 0 0.000423255673601 +Gc6_45 0 n12 ns45 0 -0.000299457721311 +Gc6_46 0 n12 ns46 0 0.000303744587685 +Gc6_47 0 n12 ns47 0 0.00131828357063 +Gc6_48 0 n12 ns48 0 -5.19867240037e-006 +Gc6_49 0 n12 ns49 0 -5.16699171733e-006 +Gc6_50 0 n12 ns50 0 0.000346668569975 +Gc6_51 0 n12 ns51 0 -0.000512816327816 +Gc6_52 0 n12 ns52 0 -5.17640505952e-006 +Gc6_53 0 n12 ns53 0 0.00015675671629 +Gc6_54 0 n12 ns54 0 -0.000203809641956 +Gc6_55 0 n12 ns55 0 1.35302799014e-005 +Gc6_56 0 n12 ns56 0 -3.41813554075e-006 +Gc6_57 0 n12 ns57 0 -9.13928117835e-008 +Gc6_58 0 n12 ns58 0 -0.00184488346941 +Gc6_59 0 n12 ns59 0 -0.00476702450972 +Gc6_60 0 n12 ns60 0 -0.00012825369647 +Gc6_61 0 n12 ns61 0 -6.29834468734e-005 +Gc6_62 0 n12 ns62 0 0.00100742912797 +Gc6_63 0 n12 ns63 0 0.000290656606231 +Gc6_64 0 n12 ns64 0 0.000884835093105 +Gc6_65 0 n12 ns65 0 0.000522547043782 +Gc6_66 0 n12 ns66 0 0.000877277713217 +Gc6_67 0 n12 ns67 0 0.00247578635585 +Gc6_68 0 n12 ns68 0 0.00129032501293 +Gc6_69 0 n12 ns69 0 -5.20837789411e-006 +Gc6_70 0 n12 ns70 0 -5.89361122775e-006 +Gc6_71 0 n12 ns71 0 -0.000369347867063 +Gc6_72 0 n12 ns72 0 0.000555382946724 +Gc6_73 0 n12 ns73 0 4.67246613866e-005 +Gc6_74 0 n12 ns74 0 -0.000316150927618 +Gc6_75 0 n12 ns75 0 0.000792264308925 +Gc6_76 0 n12 ns76 0 -0.000212145602091 +Gc6_77 0 n12 ns77 0 2.91411686975e-006 +Gc6_78 0 n12 ns78 0 -2.90703816881e-006 +Gc6_79 0 n12 ns79 0 0.00186965106494 +Gc6_80 0 n12 ns80 0 0.00474625972825 +Gc6_81 0 n12 ns81 0 0.00013875764607 +Gc6_82 0 n12 ns82 0 5.94334353151e-005 +Gc6_83 0 n12 ns83 0 -0.00100924225257 +Gc6_84 0 n12 ns84 0 -0.000291786021488 +Gc6_85 0 n12 ns85 0 0.000840345191131 +Gc6_86 0 n12 ns86 0 0.00057422909192 +Gc6_87 0 n12 ns87 0 0.000900712445203 +Gc6_88 0 n12 ns88 0 0.00232332210116 +Gc6_89 0 n12 ns89 0 0.00114547958032 +Gc6_90 0 n12 ns90 0 -4.86008867001e-006 +Gc6_91 0 n12 ns91 0 -6.30894374777e-006 +Gc6_92 0 n12 ns92 0 -0.000542864025308 +Gc6_93 0 n12 ns93 0 0.000608966748239 +Gc6_94 0 n12 ns94 0 -5.9600949493e-006 +Gc6_95 0 n12 ns95 0 0.000331581281616 +Gc6_96 0 n12 ns96 0 0.00118932922739 +Gc6_97 0 n12 ns97 0 -0.000907541713382 +Gc6_98 0 n12 ns98 0 4.0041434184e-006 +Gc6_99 0 n12 ns99 0 -2.47135911298e-006 +Gc6_100 0 n12 ns100 0 0.00309051680772 +Gc6_101 0 n12 ns101 0 0.00357404187719 +Gc6_102 0 n12 ns102 0 0.000113479515832 +Gc6_103 0 n12 ns103 0 6.99596430084e-005 +Gc6_104 0 n12 ns104 0 -0.0010167956447 +Gc6_105 0 n12 ns105 0 -0.000303741158972 +Gc6_106 0 n12 ns106 0 0.021214389203 +Gc6_107 0 n12 ns107 0 -0.00387942892913 +Gc6_108 0 n12 ns108 0 0.00436324098457 +Gc6_109 0 n12 ns109 0 -0.00257484577488 +Gc6_110 0 n12 ns110 0 -0.00813633729168 +Gc6_111 0 n12 ns111 0 -5.85018916922e-006 +Gc6_112 0 n12 ns112 0 -5.43313134345e-006 +Gc6_113 0 n12 ns113 0 -0.000311006763071 +Gc6_114 0 n12 ns114 0 0.00037554932198 +Gc6_115 0 n12 ns115 0 5.53754046995e-005 +Gc6_116 0 n12 ns116 0 3.06690512801e-005 +Gc6_117 0 n12 ns117 0 -0.00303378343337 +Gc6_118 0 n12 ns118 0 0.00170414979818 +Gc6_119 0 n12 ns119 0 -8.2808605327e-007 +Gc6_120 0 n12 ns120 0 5.04870109461e-006 +Gc6_121 0 n12 ns121 0 -0.00471550675111 +Gc6_122 0 n12 ns122 0 -0.0085339712868 +Gc6_123 0 n12 ns123 0 -0.000243864823899 +Gc6_124 0 n12 ns124 0 -0.000137361830727 +Gc6_125 0 n12 ns125 0 -0.00100846367184 +Gc6_126 0 n12 ns126 0 -0.000281586838389 +Gd6_1 0 n12 ni1 0 0.00128196451757 +Gd6_2 0 n12 ni2 0 0.00163557773456 +Gd6_3 0 n12 ni3 0 0.00111712236553 +Gd6_4 0 n12 ni4 0 -0.000528258290957 +Gd6_5 0 n12 ni5 0 -0.000569837918649 +Gd6_6 0 n12 ni6 0 0.000126916272432 +.ends + + + + +.subckt 744833120060 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 40091822.3831 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 1292645.52696 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 396092.534628 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 193993.6029 +Ca5 ns5 0 1e-012 +Ca6 ns6 0 1e-012 +Ra5 ns5 0 1375916.53676 +Ra6 ns6 0 1375916.53676 +Ga5 ns5 0 ns6 0 -7.49960699534e-006 +Ga6 ns6 0 ns5 0 7.49960699534e-006 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 665010.776245 +Ra8 ns8 0 665010.776245 +Ga7 ns7 0 ns8 0 -4.02809094819e-005 +Ga8 ns8 0 ns7 0 4.02809094819e-005 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 129553.00642 +Ra10 ns10 0 129553.00642 +Ga9 ns9 0 ns10 0 -9.25335219066e-005 +Ga10 ns10 0 ns9 0 9.25335219066e-005 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 141458.760316 +Ra12 ns12 0 141458.760316 +Ga11 ns11 0 ns12 0 -9.59845636843e-005 +Ga12 ns12 0 ns11 0 9.59845636843e-005 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 114497.830147 +Ra14 ns14 0 114497.830147 +Ga13 ns13 0 ns14 0 -0.000121273871768 +Ga14 ns14 0 ns13 0 0.000121273871768 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 17496.4734332 +Ra16 ns16 0 17496.4734332 +Ga15 ns15 0 ns16 0 -0.000281929900368 +Ga16 ns16 0 ns15 0 0.000281929900368 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 2726.20185013 +Ra18 ns18 0 2726.20185013 +Ga17 ns17 0 ns18 0 -0.000160249796977 +Ga18 ns18 0 ns17 0 0.000160249796977 +Ca19 ns19 0 1e-012 +Ra19 ns19 0 40091822.3831 +Ca20 ns20 0 1e-012 +Ra20 ns20 0 1292645.52696 +Ca21 ns21 0 1e-012 +Ra21 ns21 0 396092.534628 +Ca22 ns22 0 1e-012 +Ra22 ns22 0 193993.6029 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 1375916.53676 +Ra24 ns24 0 1375916.53676 +Ga23 ns23 0 ns24 0 -7.49960699534e-006 +Ga24 ns24 0 ns23 0 7.49960699534e-006 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 665010.776245 +Ra26 ns26 0 665010.776245 +Ga25 ns25 0 ns26 0 -4.02809094819e-005 +Ga26 ns26 0 ns25 0 4.02809094819e-005 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 129553.00642 +Ra28 ns28 0 129553.00642 +Ga27 ns27 0 ns28 0 -9.25335219066e-005 +Ga28 ns28 0 ns27 0 9.25335219066e-005 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 141458.760316 +Ra30 ns30 0 141458.760316 +Ga29 ns29 0 ns30 0 -9.59845636843e-005 +Ga30 ns30 0 ns29 0 9.59845636843e-005 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 114497.830147 +Ra32 ns32 0 114497.830147 +Ga31 ns31 0 ns32 0 -0.000121273871768 +Ga32 ns32 0 ns31 0 0.000121273871768 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 17496.4734332 +Ra34 ns34 0 17496.4734332 +Ga33 ns33 0 ns34 0 -0.000281929900368 +Ga34 ns34 0 ns33 0 0.000281929900368 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 2726.20185013 +Ra36 ns36 0 2726.20185013 +Ga35 ns35 0 ns36 0 -0.000160249796977 +Ga36 ns36 0 ns35 0 0.000160249796977 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 40091822.3831 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 1292645.52696 +Ca39 ns39 0 1e-012 +Ra39 ns39 0 396092.534628 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 193993.6029 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 1375916.53676 +Ra42 ns42 0 1375916.53676 +Ga41 ns41 0 ns42 0 -7.49960699534e-006 +Ga42 ns42 0 ns41 0 7.49960699534e-006 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 665010.776245 +Ra44 ns44 0 665010.776245 +Ga43 ns43 0 ns44 0 -4.02809094819e-005 +Ga44 ns44 0 ns43 0 4.02809094819e-005 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 129553.00642 +Ra46 ns46 0 129553.00642 +Ga45 ns45 0 ns46 0 -9.25335219066e-005 +Ga46 ns46 0 ns45 0 9.25335219066e-005 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 141458.760316 +Ra48 ns48 0 141458.760316 +Ga47 ns47 0 ns48 0 -9.59845636843e-005 +Ga48 ns48 0 ns47 0 9.59845636843e-005 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 114497.830147 +Ra50 ns50 0 114497.830147 +Ga49 ns49 0 ns50 0 -0.000121273871768 +Ga50 ns50 0 ns49 0 0.000121273871768 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 17496.4734332 +Ra52 ns52 0 17496.4734332 +Ga51 ns51 0 ns52 0 -0.000281929900368 +Ga52 ns52 0 ns51 0 0.000281929900368 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 2726.20185013 +Ra54 ns54 0 2726.20185013 +Ga53 ns53 0 ns54 0 -0.000160249796977 +Ga54 ns54 0 ns53 0 0.000160249796977 +Ca55 ns55 0 1e-012 +Ra55 ns55 0 40091822.3831 +Ca56 ns56 0 1e-012 +Ra56 ns56 0 1292645.52696 +Ca57 ns57 0 1e-012 +Ra57 ns57 0 396092.534628 +Ca58 ns58 0 1e-012 +Ra58 ns58 0 193993.6029 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 1375916.53676 +Ra60 ns60 0 1375916.53676 +Ga59 ns59 0 ns60 0 -7.49960699534e-006 +Ga60 ns60 0 ns59 0 7.49960699534e-006 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 665010.776245 +Ra62 ns62 0 665010.776245 +Ga61 ns61 0 ns62 0 -4.02809094819e-005 +Ga62 ns62 0 ns61 0 4.02809094819e-005 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 129553.00642 +Ra64 ns64 0 129553.00642 +Ga63 ns63 0 ns64 0 -9.25335219066e-005 +Ga64 ns64 0 ns63 0 9.25335219066e-005 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 141458.760316 +Ra66 ns66 0 141458.760316 +Ga65 ns65 0 ns66 0 -9.59845636843e-005 +Ga66 ns66 0 ns65 0 9.59845636843e-005 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 114497.830147 +Ra68 ns68 0 114497.830147 +Ga67 ns67 0 ns68 0 -0.000121273871768 +Ga68 ns68 0 ns67 0 0.000121273871768 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 17496.4734332 +Ra70 ns70 0 17496.4734332 +Ga69 ns69 0 ns70 0 -0.000281929900368 +Ga70 ns70 0 ns69 0 0.000281929900368 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 2726.20185013 +Ra72 ns72 0 2726.20185013 +Ga71 ns71 0 ns72 0 -0.000160249796977 +Ga72 ns72 0 ns71 0 0.000160249796977 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 40091822.3831 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 1292645.52696 +Ca75 ns75 0 1e-012 +Ra75 ns75 0 396092.534628 +Ca76 ns76 0 1e-012 +Ra76 ns76 0 193993.6029 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 1375916.53676 +Ra78 ns78 0 1375916.53676 +Ga77 ns77 0 ns78 0 -7.49960699534e-006 +Ga78 ns78 0 ns77 0 7.49960699534e-006 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 665010.776245 +Ra80 ns80 0 665010.776245 +Ga79 ns79 0 ns80 0 -4.02809094819e-005 +Ga80 ns80 0 ns79 0 4.02809094819e-005 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 129553.00642 +Ra82 ns82 0 129553.00642 +Ga81 ns81 0 ns82 0 -9.25335219066e-005 +Ga82 ns82 0 ns81 0 9.25335219066e-005 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 141458.760316 +Ra84 ns84 0 141458.760316 +Ga83 ns83 0 ns84 0 -9.59845636843e-005 +Ga84 ns84 0 ns83 0 9.59845636843e-005 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 114497.830147 +Ra86 ns86 0 114497.830147 +Ga85 ns85 0 ns86 0 -0.000121273871768 +Ga86 ns86 0 ns85 0 0.000121273871768 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 17496.4734332 +Ra88 ns88 0 17496.4734332 +Ga87 ns87 0 ns88 0 -0.000281929900368 +Ga88 ns88 0 ns87 0 0.000281929900368 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 2726.20185013 +Ra90 ns90 0 2726.20185013 +Ga89 ns89 0 ns90 0 -0.000160249796977 +Ga90 ns90 0 ns89 0 0.000160249796977 +Ca91 ns91 0 1e-012 +Ra91 ns91 0 40091822.3831 +Ca92 ns92 0 1e-012 +Ra92 ns92 0 1292645.52696 +Ca93 ns93 0 1e-012 +Ra93 ns93 0 396092.534628 +Ca94 ns94 0 1e-012 +Ra94 ns94 0 193993.6029 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 1375916.53676 +Ra96 ns96 0 1375916.53676 +Ga95 ns95 0 ns96 0 -7.49960699534e-006 +Ga96 ns96 0 ns95 0 7.49960699534e-006 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 665010.776245 +Ra98 ns98 0 665010.776245 +Ga97 ns97 0 ns98 0 -4.02809094819e-005 +Ga98 ns98 0 ns97 0 4.02809094819e-005 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 129553.00642 +Ra100 ns100 0 129553.00642 +Ga99 ns99 0 ns100 0 -9.25335219066e-005 +Ga100 ns100 0 ns99 0 9.25335219066e-005 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 141458.760316 +Ra102 ns102 0 141458.760316 +Ga101 ns101 0 ns102 0 -9.59845636843e-005 +Ga102 ns102 0 ns101 0 9.59845636843e-005 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 114497.830147 +Ra104 ns104 0 114497.830147 +Ga103 ns103 0 ns104 0 -0.000121273871768 +Ga104 ns104 0 ns103 0 0.000121273871768 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 17496.4734332 +Ra106 ns106 0 17496.4734332 +Ga105 ns105 0 ns106 0 -0.000281929900368 +Ga106 ns106 0 ns105 0 0.000281929900368 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 2726.20185013 +Ra108 ns108 0 2726.20185013 +Ga107 ns107 0 ns108 0 -0.000160249796977 +Ga108 ns108 0 ns107 0 0.000160249796977 + +Gb1_1 ns1 0 ni1 0 2.49427424487e-008 +Gb2_1 ns2 0 ni1 0 7.73607287647e-007 +Gb3_1 ns3 0 ni1 0 2.52466257901e-006 +Gb4_1 ns4 0 ni1 0 5.15480915376e-006 +Gb5_1 ns5 0 ni1 0 7.57004017808e-006 +Gb7_1 ns7 0 ni1 0 4.03370457278e-005 +Gb9_1 ns9 0 ni1 0 9.31774033612e-005 +Gb11_1 ns11 0 ni1 0 9.65052053364e-005 +Gb13_1 ns13 0 ni1 0 0.000121902853807 +Gb15_1 ns15 0 ni1 0 0.000293516548512 +Gb17_1 ns17 0 ni1 0 0.000436819553212 +Gb19_2 ns19 0 ni2 0 2.49427424487e-008 +Gb20_2 ns20 0 ni2 0 7.73607287647e-007 +Gb21_2 ns21 0 ni2 0 2.52466257901e-006 +Gb22_2 ns22 0 ni2 0 5.15480915376e-006 +Gb23_2 ns23 0 ni2 0 7.57004017808e-006 +Gb25_2 ns25 0 ni2 0 4.03370457278e-005 +Gb27_2 ns27 0 ni2 0 9.31774033612e-005 +Gb29_2 ns29 0 ni2 0 9.65052053364e-005 +Gb31_2 ns31 0 ni2 0 0.000121902853807 +Gb33_2 ns33 0 ni2 0 0.000293516548512 +Gb35_2 ns35 0 ni2 0 0.000436819553212 +Gb37_3 ns37 0 ni3 0 2.49427424487e-008 +Gb38_3 ns38 0 ni3 0 7.73607287647e-007 +Gb39_3 ns39 0 ni3 0 2.52466257901e-006 +Gb40_3 ns40 0 ni3 0 5.15480915376e-006 +Gb41_3 ns41 0 ni3 0 7.57004017808e-006 +Gb43_3 ns43 0 ni3 0 4.03370457278e-005 +Gb45_3 ns45 0 ni3 0 9.31774033612e-005 +Gb47_3 ns47 0 ni3 0 9.65052053364e-005 +Gb49_3 ns49 0 ni3 0 0.000121902853807 +Gb51_3 ns51 0 ni3 0 0.000293516548512 +Gb53_3 ns53 0 ni3 0 0.000436819553212 +Gb55_4 ns55 0 ni4 0 2.49427424487e-008 +Gb56_4 ns56 0 ni4 0 7.73607287647e-007 +Gb57_4 ns57 0 ni4 0 2.52466257901e-006 +Gb58_4 ns58 0 ni4 0 5.15480915376e-006 +Gb59_4 ns59 0 ni4 0 7.57004017808e-006 +Gb61_4 ns61 0 ni4 0 4.03370457278e-005 +Gb63_4 ns63 0 ni4 0 9.31774033612e-005 +Gb65_4 ns65 0 ni4 0 9.65052053364e-005 +Gb67_4 ns67 0 ni4 0 0.000121902853807 +Gb69_4 ns69 0 ni4 0 0.000293516548512 +Gb71_4 ns71 0 ni4 0 0.000436819553212 +Gb73_5 ns73 0 ni5 0 2.49427424487e-008 +Gb74_5 ns74 0 ni5 0 7.73607287647e-007 +Gb75_5 ns75 0 ni5 0 2.52466257901e-006 +Gb76_5 ns76 0 ni5 0 5.15480915376e-006 +Gb77_5 ns77 0 ni5 0 7.57004017808e-006 +Gb79_5 ns79 0 ni5 0 4.03370457278e-005 +Gb81_5 ns81 0 ni5 0 9.31774033612e-005 +Gb83_5 ns83 0 ni5 0 9.65052053364e-005 +Gb85_5 ns85 0 ni5 0 0.000121902853807 +Gb87_5 ns87 0 ni5 0 0.000293516548512 +Gb89_5 ns89 0 ni5 0 0.000436819553212 +Gb91_6 ns91 0 ni6 0 2.49427424487e-008 +Gb92_6 ns92 0 ni6 0 7.73607287647e-007 +Gb93_6 ns93 0 ni6 0 2.52466257901e-006 +Gb94_6 ns94 0 ni6 0 5.15480915376e-006 +Gb95_6 ns95 0 ni6 0 7.57004017808e-006 +Gb97_6 ns97 0 ni6 0 4.03370457278e-005 +Gb99_6 ns99 0 ni6 0 9.31774033612e-005 +Gb101_6 ns101 0 ni6 0 9.65052053364e-005 +Gb103_6 ns103 0 ni6 0 0.000121902853807 +Gb105_6 ns105 0 ni6 0 0.000293516548512 +Gb107_6 ns107 0 ni6 0 0.000436819553212 + +Gc1_1 0 n2 ns1 0 0.00114403953526 +Gc1_2 0 n2 ns2 0 0.000767402752756 +Gc1_3 0 n2 ns3 0 0.0120400908242 +Gc1_4 0 n2 ns4 0 0.000611999647566 +Gc1_5 0 n2 ns5 0 1.40596038565e-006 +Gc1_6 0 n2 ns6 0 -3.31657086792e-006 +Gc1_7 0 n2 ns7 0 7.72896484095e-007 +Gc1_8 0 n2 ns8 0 2.15546162694e-007 +Gc1_9 0 n2 ns9 0 0.00069804091898 +Gc1_10 0 n2 ns10 0 -0.000608504182236 +Gc1_11 0 n2 ns11 0 8.09930495444e-005 +Gc1_12 0 n2 ns12 0 -4.63993142232e-005 +Gc1_13 0 n2 ns13 0 0.000516186920636 +Gc1_14 0 n2 ns14 0 -0.000553541642529 +Gc1_15 0 n2 ns15 0 0.00174949935122 +Gc1_16 0 n2 ns16 0 -0.00125030684763 +Gc1_17 0 n2 ns17 0 -0.000234934963802 +Gc1_18 0 n2 ns18 0 0.0514625959576 +Gc1_19 0 n2 ns19 0 0.00099545217229 +Gc1_20 0 n2 ns20 0 -0.000429716121586 +Gc1_21 0 n2 ns21 0 -0.00586574477384 +Gc1_22 0 n2 ns22 0 -0.000471747376122 +Gc1_23 0 n2 ns23 0 8.82723516529e-007 +Gc1_24 0 n2 ns24 0 -1.60535606005e-006 +Gc1_25 0 n2 ns25 0 2.4030120171e-007 +Gc1_26 0 n2 ns26 0 -1.44846692031e-007 +Gc1_27 0 n2 ns27 0 -0.000268741776404 +Gc1_28 0 n2 ns28 0 0.000199874567162 +Gc1_29 0 n2 ns29 0 -0.000129163912396 +Gc1_30 0 n2 ns30 0 9.96367245399e-005 +Gc1_31 0 n2 ns31 0 0.0004494495067 +Gc1_32 0 n2 ns32 0 -0.000540465961542 +Gc1_33 0 n2 ns33 0 -9.30966682888e-006 +Gc1_34 0 n2 ns34 0 -0.000292078128579 +Gc1_35 0 n2 ns35 0 0.00140803663759 +Gc1_36 0 n2 ns36 0 -0.000827236111303 +Gc1_37 0 n2 ns37 0 0.000992997880036 +Gc1_38 0 n2 ns38 0 -0.000442582440198 +Gc1_39 0 n2 ns39 0 -0.00591528899742 +Gc1_40 0 n2 ns40 0 -0.000388291635876 +Gc1_41 0 n2 ns41 0 8.43421426864e-008 +Gc1_42 0 n2 ns42 0 -1.2523479157e-006 +Gc1_43 0 n2 ns43 0 3.42008311622e-007 +Gc1_44 0 n2 ns44 0 -2.63895081075e-007 +Gc1_45 0 n2 ns45 0 -0.00040396837287 +Gc1_46 0 n2 ns46 0 0.000241441764464 +Gc1_47 0 n2 ns47 0 0.000176171426877 +Gc1_48 0 n2 ns48 0 -0.000137032195768 +Gc1_49 0 n2 ns49 0 0.00044866202429 +Gc1_50 0 n2 ns50 0 -0.000414453844108 +Gc1_51 0 n2 ns51 0 0.000147787791291 +Gc1_52 0 n2 ns52 0 -0.000424545850034 +Gc1_53 0 n2 ns53 0 -0.000126453787593 +Gc1_54 0 n2 ns54 0 -0.00275060275843 +Gc1_55 0 n2 ns55 0 -0.000984930346287 +Gc1_56 0 n2 ns56 0 0.000434139518391 +Gc1_57 0 n2 ns57 0 0.0059374840578 +Gc1_58 0 n2 ns58 0 0.000370789318629 +Gc1_59 0 n2 ns59 0 3.85587087304e-007 +Gc1_60 0 n2 ns60 0 1.23962678446e-006 +Gc1_61 0 n2 ns61 0 -3.3238383761e-007 +Gc1_62 0 n2 ns62 0 -2.52764964293e-007 +Gc1_63 0 n2 ns63 0 0.000752118651544 +Gc1_64 0 n2 ns64 0 -0.000417516361343 +Gc1_65 0 n2 ns65 0 -0.000216259518441 +Gc1_66 0 n2 ns66 0 0.000170508938674 +Gc1_67 0 n2 ns67 0 -0.000486177516625 +Gc1_68 0 n2 ns68 0 0.000436138173882 +Gc1_69 0 n2 ns69 0 -0.000808171990827 +Gc1_70 0 n2 ns70 0 9.3245741628e-005 +Gc1_71 0 n2 ns71 0 0.0013671746412 +Gc1_72 0 n2 ns72 0 -0.000925470355713 +Gc1_73 0 n2 ns73 0 -0.00098921383087 +Gc1_74 0 n2 ns74 0 0.000420995710624 +Gc1_75 0 n2 ns75 0 0.00588319276284 +Gc1_76 0 n2 ns76 0 0.000457743607513 +Gc1_77 0 n2 ns77 0 -4.29369747924e-007 +Gc1_78 0 n2 ns78 0 1.66875213947e-006 +Gc1_79 0 n2 ns79 0 -2.20989723207e-007 +Gc1_80 0 n2 ns80 0 -3.43110491093e-007 +Gc1_81 0 n2 ns81 0 0.000280573587777 +Gc1_82 0 n2 ns82 0 -0.000233565727468 +Gc1_83 0 n2 ns83 0 0.000223333163293 +Gc1_84 0 n2 ns84 0 -0.000151183544011 +Gc1_85 0 n2 ns85 0 -0.000372137490942 +Gc1_86 0 n2 ns86 0 0.000520389475055 +Gc1_87 0 n2 ns87 0 -0.000242784588188 +Gc1_88 0 n2 ns88 0 -0.000221198704414 +Gc1_89 0 n2 ns89 0 -0.00083520209634 +Gc1_90 0 n2 ns90 0 -0.00417671804759 +Gc1_91 0 n2 ns91 0 -0.00112672501242 +Gc1_92 0 n2 ns92 0 -0.000859784227459 +Gc1_93 0 n2 ns93 0 -0.0119534822033 +Gc1_94 0 n2 ns94 0 -0.000721404694217 +Gc1_95 0 n2 ns95 0 2.02357245283e-007 +Gc1_96 0 n2 ns96 0 -1.05914690154e-006 +Gc1_97 0 n2 ns97 0 -1.20166736943e-007 +Gc1_98 0 n2 ns98 0 -8.40873055688e-007 +Gc1_99 0 n2 ns99 0 -0.00110710606021 +Gc1_100 0 n2 ns100 0 0.00079849750864 +Gc1_101 0 n2 ns101 0 -9.0945986139e-005 +Gc1_102 0 n2 ns102 0 5.02994278551e-005 +Gc1_103 0 n2 ns103 0 -0.000554075802938 +Gc1_104 0 n2 ns104 0 0.000536440552846 +Gc1_105 0 n2 ns105 0 -0.00146438080166 +Gc1_106 0 n2 ns106 0 0.00219737800573 +Gc1_107 0 n2 ns107 0 -0.0170759812799 +Gc1_108 0 n2 ns108 0 -0.044674474021 +Gd1_1 0 n2 ni1 0 0.000363024969325 +Gd1_2 0 n2 ni2 0 0.00213969694788 +Gd1_3 0 n2 ni3 0 0.00171127908679 +Gd1_4 0 n2 ni4 0 0.00147943438476 +Gd1_5 0 n2 ni5 0 0.00120072492711 +Gd1_6 0 n2 ni6 0 -0.00185993771922 +Gc2_1 0 n4 ns1 0 0.000992084062668 +Gc2_2 0 n4 ns2 0 -0.000428854876701 +Gc2_3 0 n4 ns3 0 -0.00586610442468 +Gc2_4 0 n4 ns4 0 -0.000471518867852 +Gc2_5 0 n4 ns5 0 9.78810486251e-007 +Gc2_6 0 n4 ns6 0 -1.61996359454e-006 +Gc2_7 0 n4 ns7 0 2.30947835448e-007 +Gc2_8 0 n4 ns8 0 -1.43344426105e-007 +Gc2_9 0 n4 ns9 0 -0.000268496528041 +Gc2_10 0 n4 ns10 0 0.000199748683456 +Gc2_11 0 n4 ns11 0 -0.000129310733932 +Gc2_12 0 n4 ns12 0 9.96126830572e-005 +Gc2_13 0 n4 ns13 0 0.000449454045944 +Gc2_14 0 n4 ns14 0 -0.000540196236957 +Gc2_15 0 n4 ns15 0 -8.34040204435e-006 +Gc2_16 0 n4 ns16 0 -0.000294984224098 +Gc2_17 0 n4 ns17 0 0.00139202052812 +Gc2_18 0 n4 ns18 0 -0.000843023749493 +Gc2_19 0 n4 ns19 0 0.0011379498736 +Gc2_20 0 n4 ns20 0 0.000741017607575 +Gc2_21 0 n4 ns21 0 0.0119007883219 +Gc2_22 0 n4 ns22 0 0.000771822673277 +Gc2_23 0 n4 ns23 0 -1.26445239456e-006 +Gc2_24 0 n4 ns24 0 -2.54488889034e-006 +Gc2_25 0 n4 ns25 0 8.38422969842e-007 +Gc2_26 0 n4 ns26 0 7.11369917519e-007 +Gc2_27 0 n4 ns27 0 7.4069933929e-005 +Gc2_28 0 n4 ns28 0 -8.38725617986e-005 +Gc2_29 0 n4 ns29 0 0.00033651075268 +Gc2_30 0 n4 ns30 0 -0.000233139511698 +Gc2_31 0 n4 ns31 0 0.000396533601764 +Gc2_32 0 n4 ns32 0 -0.000526120230003 +Gc2_33 0 n4 ns33 0 0.000178719111111 +Gc2_34 0 n4 ns34 0 -0.000404203026384 +Gc2_35 0 n4 ns35 0 0.00624339117334 +Gc2_36 0 n4 ns36 0 0.0587076918963 +Gc2_37 0 n4 ns37 0 0.000982728493688 +Gc2_38 0 n4 ns38 0 -0.000408964061201 +Gc2_39 0 n4 ns39 0 -0.00576210577865 +Gc2_40 0 n4 ns40 0 -0.000576055981015 +Gc2_41 0 n4 ns41 0 1.96354503662e-006 +Gc2_42 0 n4 ns42 0 -1.97448527375e-006 +Gc2_43 0 n4 ns43 0 5.73065679712e-008 +Gc2_44 0 n4 ns44 0 -1.40027530716e-007 +Gc2_45 0 n4 ns45 0 0.000133113104062 +Gc2_46 0 n4 ns46 0 -9.16441240223e-005 +Gc2_47 0 n4 ns47 0 -0.000392561213965 +Gc2_48 0 n4 ns48 0 0.00028759750794 +Gc2_49 0 n4 ns49 0 0.000394025728465 +Gc2_50 0 n4 ns50 0 -0.000408027700845 +Gc2_51 0 n4 ns51 0 0.000169918345476 +Gc2_52 0 n4 ns52 0 -0.000285612613205 +Gc2_53 0 n4 ns53 0 0.00134066495694 +Gc2_54 0 n4 ns54 0 -0.000887590732591 +Gc2_55 0 n4 ns55 0 -0.000979534004085 +Gc2_56 0 n4 ns56 0 0.000401965188423 +Gc2_57 0 n4 ns57 0 0.00578070135128 +Gc2_58 0 n4 ns58 0 0.000560274818138 +Gc2_59 0 n4 ns59 0 -1.71064377937e-006 +Gc2_60 0 n4 ns60 0 1.91137644182e-006 +Gc2_61 0 n4 ns61 0 -5.52537314488e-008 +Gc2_62 0 n4 ns62 0 -3.10391319828e-007 +Gc2_63 0 n4 ns63 0 -0.000276334172807 +Gc2_64 0 n4 ns64 0 0.00014538442245 +Gc2_65 0 n4 ns65 0 0.000531914376014 +Gc2_66 0 n4 ns66 0 -0.00037266182518 +Gc2_67 0 n4 ns67 0 -0.000427164734201 +Gc2_68 0 n4 ns68 0 0.000429997940476 +Gc2_69 0 n4 ns69 0 -0.000575276908442 +Gc2_70 0 n4 ns70 0 -0.000328695043262 +Gc2_71 0 n4 ns71 0 0.00105782454485 +Gc2_72 0 n4 ns72 0 -0.000320419097855 +Gc2_73 0 n4 ns73 0 -0.00112508068302 +Gc2_74 0 n4 ns74 0 -0.000825154646685 +Gc2_75 0 n4 ns75 0 -0.0118267053946 +Gc2_76 0 n4 ns76 0 -0.000870740890941 +Gc2_77 0 n4 ns77 0 2.24979977024e-006 +Gc2_78 0 n4 ns78 0 -1.00848791195e-006 +Gc2_79 0 n4 ns79 0 -5.30644344804e-007 +Gc2_80 0 n4 ns80 0 -1.11723889719e-006 +Gc2_81 0 n4 ns81 0 -0.000104869706821 +Gc2_82 0 n4 ns82 0 8.12096280867e-005 +Gc2_83 0 n4 ns83 0 -0.000500386489431 +Gc2_84 0 n4 ns84 0 0.000334729397351 +Gc2_85 0 n4 ns85 0 -0.000325811588063 +Gc2_86 0 n4 ns86 0 0.0005020328818 +Gc2_87 0 n4 ns87 0 -0.000370148759324 +Gc2_88 0 n4 ns88 0 0.00172401039251 +Gc2_89 0 n4 ns89 0 -0.0270426035197 +Gc2_90 0 n4 ns90 0 -0.0581059408758 +Gc2_91 0 n4 ns91 0 -0.00099284020358 +Gc2_92 0 n4 ns92 0 0.000421516846337 +Gc2_93 0 n4 ns93 0 0.00589602425511 +Gc2_94 0 n4 ns94 0 0.000447574496817 +Gc2_95 0 n4 ns95 0 -2.9753657741e-007 +Gc2_96 0 n4 ns96 0 1.3286300935e-006 +Gc2_97 0 n4 ns97 0 -2.10678392072e-007 +Gc2_98 0 n4 ns98 0 -3.71599279158e-007 +Gc2_99 0 n4 ns99 0 0.000395133463275 +Gc2_100 0 n4 ns100 0 -0.000271267301703 +Gc2_101 0 n4 ns101 0 0.000202468884082 +Gc2_102 0 n4 ns102 0 -0.000128486869959 +Gc2_103 0 n4 ns103 0 -0.000484293531771 +Gc2_104 0 n4 ns104 0 0.000527630586728 +Gc2_105 0 n4 ns105 0 -6.0245184763e-005 +Gc2_106 0 n4 ns106 0 -0.00034015819153 +Gc2_107 0 n4 ns107 0 0.00122779920815 +Gc2_108 0 n4 ns108 0 -0.00100248151473 +Gd2_1 0 n4 ni1 0 0.00213352922136 +Gd2_2 0 n4 ni2 0 0.00210331631586 +Gd2_3 0 n4 ni3 0 0.00212787484538 +Gd2_4 0 n4 ni4 0 0.00133604930616 +Gd2_5 0 n4 ni5 0 -0.00472067927393 +Gd2_6 0 n4 ni6 0 0.0020429563752 +Gc3_1 0 n6 ns1 0 0.000988489823016 +Gc3_2 0 n6 ns2 0 -0.000441694233697 +Gc3_3 0 n6 ns3 0 -0.00591527045452 +Gc3_4 0 n6 ns4 0 -0.00038826806242 +Gc3_5 0 n6 ns5 0 1.59217087762e-007 +Gc3_6 0 n6 ns6 0 -1.24138886727e-006 +Gc3_7 0 n6 ns7 0 3.37893969701e-007 +Gc3_8 0 n6 ns8 0 -2.59304744192e-007 +Gc3_9 0 n6 ns9 0 -0.000403584762712 +Gc3_10 0 n6 ns10 0 0.000241100863701 +Gc3_11 0 n6 ns11 0 0.000175966782707 +Gc3_12 0 n6 ns12 0 -0.000136707728251 +Gc3_13 0 n6 ns13 0 0.000448575160645 +Gc3_14 0 n6 ns14 0 -0.000414129907816 +Gc3_15 0 n6 ns15 0 0.000148398372867 +Gc3_16 0 n6 ns16 0 -0.000428442556626 +Gc3_17 0 n6 ns17 0 -0.000149214136917 +Gc3_18 0 n6 ns18 0 -0.00277251038289 +Gc3_19 0 n6 ns19 0 0.000985622220488 +Gc3_20 0 n6 ns20 0 -0.000408537614907 +Gc3_21 0 n6 ns21 0 -0.00576209017949 +Gc3_22 0 n6 ns22 0 -0.000576020840855 +Gc3_23 0 n6 ns23 0 2.02127397329e-006 +Gc3_24 0 n6 ns24 0 -1.94443231897e-006 +Gc3_25 0 n6 ns25 0 5.24496901599e-008 +Gc3_26 0 n6 ns26 0 -1.4082600664e-007 +Gc3_27 0 n6 ns27 0 0.000133123717253 +Gc3_28 0 n6 ns28 0 -9.15370286489e-005 +Gc3_29 0 n6 ns29 0 -0.000392436339512 +Gc3_30 0 n6 ns30 0 0.00028744764578 +Gc3_31 0 n6 ns31 0 0.000393795765053 +Gc3_32 0 n6 ns32 0 -0.000407745644737 +Gc3_33 0 n6 ns33 0 0.000170072382829 +Gc3_34 0 n6 ns34 0 -0.000286467760652 +Gc3_35 0 n6 ns35 0 0.00133764899827 +Gc3_36 0 n6 ns36 0 -0.00089047062756 +Gc3_37 0 n6 ns37 0 0.00113004820205 +Gc3_38 0 n6 ns38 0 0.000759139322985 +Gc3_39 0 n6 ns39 0 0.0118730388653 +Gc3_40 0 n6 ns40 0 0.000736405418215 +Gc3_41 0 n6 ns41 0 7.68881117648e-008 +Gc3_42 0 n6 ns42 0 -1.4016538108e-006 +Gc3_43 0 n6 ns43 0 2.28542518549e-007 +Gc3_44 0 n6 ns44 0 -2.30773419647e-007 +Gc3_45 0 n6 ns45 0 0.000196533546545 +Gc3_46 0 n6 ns46 0 -7.42977077795e-005 +Gc3_47 0 n6 ns47 0 0.000532225449389 +Gc3_48 0 n6 ns48 0 -0.00035798527853 +Gc3_49 0 n6 ns49 0 0.000388096768325 +Gc3_50 0 n6 ns50 0 -0.000305135871248 +Gc3_51 0 n6 ns51 0 0.00188512254829 +Gc3_52 0 n6 ns52 0 -0.000690304394386 +Gc3_53 0 n6 ns53 0 -0.0135628489907 +Gc3_54 0 n6 ns54 0 0.0284613255165 +Gc3_55 0 n6 ns55 0 -0.00111756797961 +Gc3_56 0 n6 ns56 0 -0.000842145453102 +Gc3_57 0 n6 ns57 0 -0.0118015873441 +Gc3_58 0 n6 ns58 0 -0.00083306011591 +Gc3_59 0 n6 ns59 0 7.83011478732e-007 +Gc3_60 0 n6 ns60 0 -2.10657243291e-006 +Gc3_61 0 n6 ns61 0 7.8026548557e-008 +Gc3_62 0 n6 ns62 0 -2.52328790179e-007 +Gc3_63 0 n6 ns63 0 -0.000404952971542 +Gc3_64 0 n6 ns64 0 0.000121597596206 +Gc3_65 0 n6 ns65 0 -0.000684023891143 +Gc3_66 0 n6 ns66 0 0.000445565534203 +Gc3_67 0 n6 ns67 0 -0.000420223338533 +Gc3_68 0 n6 ns68 0 0.000317446367245 +Gc3_69 0 n6 ns69 0 -0.00288133537432 +Gc3_70 0 n6 ns70 0 0.00222297090976 +Gc3_71 0 n6 ns71 0 -0.00349084302778 +Gc3_72 0 n6 ns72 0 -0.0212327685439 +Gc3_73 0 n6 ns73 0 -0.00098555550306 +Gc3_74 0 n6 ns74 0 0.000403740396786 +Gc3_75 0 n6 ns75 0 0.00578675476575 +Gc3_76 0 n6 ns76 0 0.000558028897208 +Gc3_77 0 n6 ns77 0 -1.72069552636e-006 +Gc3_78 0 n6 ns78 0 1.72178846065e-006 +Gc3_79 0 n6 ns79 0 -2.28826149756e-008 +Gc3_80 0 n6 ns80 0 -3.87593170148e-007 +Gc3_81 0 n6 ns81 0 -0.000161049468594 +Gc3_82 0 n6 ns82 0 0.000103967940852 +Gc3_83 0 n6 ns83 0 0.00063789061327 +Gc3_84 0 n6 ns84 0 -0.000422322187083 +Gc3_85 0 n6 ns85 0 -0.000330231530341 +Gc3_86 0 n6 ns86 0 0.000395041522773 +Gc3_87 0 n6 ns87 0 6.57221066564e-005 +Gc3_88 0 n6 ns88 0 -0.000419989049242 +Gc3_89 0 n6 ns89 0 -0.000444415292202 +Gc3_90 0 n6 ns90 0 -0.00339233302546 +Gc3_91 0 n6 ns91 0 -0.000991939073918 +Gc3_92 0 n6 ns92 0 0.000435596352073 +Gc3_93 0 n6 ns93 0 0.00593756279399 +Gc3_94 0 n6 ns94 0 0.000368133851631 +Gc3_95 0 n6 ns95 0 6.23003224277e-007 +Gc3_96 0 n6 ns96 0 1.0682669589e-006 +Gc3_97 0 n6 ns97 0 -3.54383931133e-007 +Gc3_98 0 n6 ns98 0 -3.10954894605e-007 +Gc3_99 0 n6 ns99 0 0.00059427393207 +Gc3_100 0 n6 ns100 0 -0.000315776083847 +Gc3_101 0 n6 ns101 0 -0.000238496291634 +Gc3_102 0 n6 ns102 0 0.000164947484792 +Gc3_103 0 n6 ns103 0 -0.0004777255081 +Gc3_104 0 n6 ns104 0 0.000397550178101 +Gc3_105 0 n6 ns105 0 -5.81861658132e-005 +Gc3_106 0 n6 ns106 0 -0.000322361298872 +Gc3_107 0 n6 ns107 0 0.000782033394567 +Gc3_108 0 n6 ns108 0 -0.00183165161396 +Gd3_1 0 n6 ni1 0 0.00170174251346 +Gd3_2 0 n6 ni2 0 0.0021267764178 +Gd3_3 0 n6 ni3 0 -0.00398522806304 +Gd3_4 0 n6 ni4 0 0.00174949094525 +Gd3_5 0 n6 ni5 0 0.0015524836987 +Gd3_6 0 n6 ni6 0 0.0017836514408 +Gc4_1 0 n8 ns1 0 -0.000991283289749 +Gc4_2 0 n8 ns2 0 0.000434191977069 +Gc4_3 0 n8 ns3 0 0.00593773946032 +Gc4_4 0 n8 ns4 0 0.000370519125981 +Gc4_5 0 n8 ns5 0 3.47385470063e-007 +Gc4_6 0 n8 ns6 0 1.21721312058e-006 +Gc4_7 0 n8 ns7 0 -3.58724549818e-007 +Gc4_8 0 n8 ns8 0 -2.53262317258e-007 +Gc4_9 0 n8 ns9 0 0.000752507219119 +Gc4_10 0 n8 ns10 0 -0.000417740876474 +Gc4_11 0 n8 ns11 0 -0.000216397778126 +Gc4_12 0 n8 ns12 0 0.000170626660871 +Gc4_13 0 n8 ns13 0 -0.000486342462976 +Gc4_14 0 n8 ns14 0 0.000436406189542 +Gc4_15 0 n8 ns15 0 -0.000807234134397 +Gc4_16 0 n8 ns16 0 8.99524869426e-005 +Gc4_17 0 n8 ns17 0 0.00134456616872 +Gc4_18 0 n8 ns18 0 -0.000950298887431 +Gc4_19 0 n8 ns19 0 -0.000984481631361 +Gc4_20 0 n8 ns20 0 0.000401667122959 +Gc4_21 0 n8 ns21 0 0.00578091628502 +Gc4_22 0 n8 ns22 0 0.000559730256601 +Gc4_23 0 n8 ns23 0 -1.72521663309e-006 +Gc4_24 0 n8 ns24 0 1.85917595537e-006 +Gc4_25 0 n8 ns25 0 -9.19844640069e-008 +Gc4_26 0 n8 ns26 0 -3.11943143481e-007 +Gc4_27 0 n8 ns27 0 -0.000276087222555 +Gc4_28 0 n8 ns28 0 0.000145459470911 +Gc4_29 0 n8 ns29 0 0.000531839508979 +Gc4_30 0 n8 ns30 0 -0.000372749953345 +Gc4_31 0 n8 ns31 0 -0.000427290238978 +Gc4_32 0 n8 ns32 0 0.000430288212227 +Gc4_33 0 n8 ns33 0 -0.000573476216558 +Gc4_34 0 n8 ns34 0 -0.000332073458941 +Gc4_35 0 n8 ns35 0 0.00103300427148 +Gc4_36 0 n8 ns36 0 -0.000349061966391 +Gc4_37 0 n8 ns37 0 -0.00111744491319 +Gc4_38 0 n8 ns38 0 -0.000840903669131 +Gc4_39 0 n8 ns39 0 -0.0118018025143 +Gc4_40 0 n8 ns40 0 -0.000833335533497 +Gc4_41 0 n8 ns41 0 6.85627006432e-007 +Gc4_42 0 n8 ns42 0 -2.21752981809e-006 +Gc4_43 0 n8 ns43 0 1.10620046916e-007 +Gc4_44 0 n8 ns44 0 -2.55691938429e-007 +Gc4_45 0 n8 ns45 0 -0.000405146786249 +Gc4_46 0 n8 ns46 0 0.000121737449209 +Gc4_47 0 n8 ns47 0 -0.000684319393008 +Gc4_48 0 n8 ns48 0 0.000446085112325 +Gc4_49 0 n8 ns49 0 -0.000420478250521 +Gc4_50 0 n8 ns50 0 0.000317736566386 +Gc4_51 0 n8 ns51 0 -0.00289222278444 +Gc4_52 0 n8 ns52 0 0.0022081427413 +Gc4_53 0 n8 ns53 0 -0.00361389535608 +Gc4_54 0 n8 ns54 0 -0.0213307973093 +Gc4_55 0 n8 ns55 0 0.00113507751816 +Gc4_56 0 n8 ns56 0 0.000752963434312 +Gc4_57 0 n8 ns57 0 0.0119081754686 +Gc4_58 0 n8 ns58 0 0.000733248542476 +Gc4_59 0 n8 ns59 0 7.63803684334e-007 +Gc4_60 0 n8 ns60 0 -2.23373285466e-006 +Gc4_61 0 n8 ns61 0 3.66185820834e-007 +Gc4_62 0 n8 ns62 0 -6.17116734369e-007 +Gc4_63 0 n8 ns63 0 0.000739249375558 +Gc4_64 0 n8 ns64 0 -0.000207559257342 +Gc4_65 0 n8 ns65 0 0.000926169707075 +Gc4_66 0 n8 ns66 0 -0.000578139917036 +Gc4_67 0 n8 ns67 0 0.000460508084902 +Gc4_68 0 n8 ns68 0 -0.000345412568804 +Gc4_69 0 n8 ns69 0 0.00527173210168 +Gc4_70 0 n8 ns70 0 -0.00200701917561 +Gc4_71 0 n8 ns71 0 -0.0147365721449 +Gc4_72 0 n8 ns72 0 0.0252136284401 +Gc4_73 0 n8 ns73 0 0.000984625189923 +Gc4_74 0 n8 ns74 0 -0.000407931765002 +Gc4_75 0 n8 ns75 0 -0.00577959187847 +Gc4_76 0 n8 ns76 0 -0.000577653663835 +Gc4_77 0 n8 ns77 0 2.17339807502e-006 +Gc4_78 0 n8 ns78 0 -1.91730474442e-006 +Gc4_79 0 n8 ns79 0 -2.16860493336e-008 +Gc4_80 0 n8 ns80 0 -1.45611027419e-007 +Gc4_81 0 n8 ns81 0 0.000293447644722 +Gc4_82 0 n8 ns82 0 -0.000179792078285 +Gc4_83 0 n8 ns83 0 -0.000827774363694 +Gc4_84 0 n8 ns84 0 0.000536217350702 +Gc4_85 0 n8 ns85 0 0.000365144755198 +Gc4_86 0 n8 ns86 0 -0.000427104504092 +Gc4_87 0 n8 ns87 0 -0.000888633237646 +Gc4_88 0 n8 ns88 0 0.000280312813943 +Gc4_89 0 n8 ns89 0 0.000140858332206 +Gc4_90 0 n8 ns90 0 -0.00297477825971 +Gc4_91 0 n8 ns91 0 0.000987593138543 +Gc4_92 0 n8 ns92 0 -0.000440871356303 +Gc4_93 0 n8 ns93 0 -0.00593278279245 +Gc4_94 0 n8 ns94 0 -0.00038573754751 +Gc4_95 0 n8 ns95 0 8.91194478786e-008 +Gc4_96 0 n8 ns96 0 -1.19463576364e-006 +Gc4_97 0 n8 ns97 0 2.97364070314e-007 +Gc4_98 0 n8 ns98 0 -2.09541813163e-007 +Gc4_99 0 n8 ns99 0 -0.00115096422108 +Gc4_100 0 n8 ns100 0 0.000521000570174 +Gc4_101 0 n8 ns101 0 0.000325322892693 +Gc4_102 0 n8 ns102 0 -0.000214681797906 +Gc4_103 0 n8 ns103 0 0.000524503082171 +Gc4_104 0 n8 ns104 0 -0.000428172195009 +Gc4_105 0 n8 ns105 0 -0.000616511471054 +Gc4_106 0 n8 ns106 0 -0.000178867180374 +Gc4_107 0 n8 ns107 0 -0.000119573825739 +Gc4_108 0 n8 ns108 0 -0.0026206205725 +Gd4_1 0 n8 ni1 0 0.00147089642862 +Gd4_2 0 n8 ni2 0 0.00132698972981 +Gd4_3 0 n8 ni3 0 0.00168074972685 +Gd4_4 0 n8 ni4 0 -0.00123105260367 +Gd4_5 0 n8 ni5 0 0.000876959537033 +Gd4_6 0 n8 ni6 0 0.00101058194907 +Gc5_1 0 n10 ns1 0 -0.000992915101684 +Gc5_2 0 n10 ns2 0 0.000421450917771 +Gc5_3 0 n10 ns3 0 0.00588298522536 +Gc5_4 0 n10 ns4 0 0.00045731322135 +Gc5_5 0 n10 ns5 0 -4.5880633061e-007 +Gc5_6 0 n10 ns6 0 1.62096887936e-006 +Gc5_7 0 n10 ns7 0 -2.52671186752e-007 +Gc5_8 0 n10 ns8 0 -3.49609144946e-007 +Gc5_9 0 n10 ns9 0 0.000280790451487 +Gc5_10 0 n10 ns10 0 -0.00023361973817 +Gc5_11 0 n10 ns11 0 0.000223194135247 +Gc5_12 0 n10 ns12 0 -0.000151196555103 +Gc5_13 0 n10 ns13 0 -0.000372214702427 +Gc5_14 0 n10 ns14 0 0.000520586703968 +Gc5_15 0 n10 ns15 0 -0.000242282866933 +Gc5_16 0 n10 ns16 0 -0.000223215548765 +Gc5_17 0 n10 ns17 0 -0.00085229041813 +Gc5_18 0 n10 ns18 0 -0.00419541171869 +Gc5_19 0 n10 ns19 0 -0.00112591406396 +Gc5_20 0 n10 ns20 0 -0.000824697894282 +Gc5_21 0 n10 ns21 0 -0.0118254050525 +Gc5_22 0 n10 ns22 0 -0.000871677810236 +Gc5_23 0 n10 ns23 0 2.19869568861e-006 +Gc5_24 0 n10 ns24 0 -1.16525894661e-006 +Gc5_25 0 n10 ns25 0 -5.2340716574e-007 +Gc5_26 0 n10 ns26 0 -1.12838153774e-006 +Gc5_27 0 n10 ns27 0 -0.000104754600874 +Gc5_28 0 n10 ns28 0 8.16279246018e-005 +Gc5_29 0 n10 ns29 0 -0.000500766935876 +Gc5_30 0 n10 ns30 0 0.000334824932152 +Gc5_31 0 n10 ns31 0 -0.000325752667209 +Gc5_32 0 n10 ns32 0 0.000502309191599 +Gc5_33 0 n10 ns33 0 -0.000374112186981 +Gc5_34 0 n10 ns34 0 0.00170771461972 +Gc5_35 0 n10 ns35 0 -0.0271833814137 +Gc5_36 0 n10 ns36 0 -0.0582351369569 +Gc5_37 0 n10 ns37 0 -0.000979788430379 +Gc5_38 0 n10 ns38 0 0.000403480809489 +Gc5_39 0 n10 ns39 0 0.0057882389214 +Gc5_40 0 n10 ns40 0 0.000557570776445 +Gc5_41 0 n10 ns41 0 -1.62655285754e-006 +Gc5_42 0 n10 ns42 0 1.65880883395e-006 +Gc5_43 0 n10 ns43 0 -5.78440431615e-008 +Gc5_44 0 n10 ns44 0 -3.95400800436e-007 +Gc5_45 0 n10 ns45 0 -0.000160751339614 +Gc5_46 0 n10 ns46 0 0.000103939192619 +Gc5_47 0 n10 ns47 0 0.000637872279166 +Gc5_48 0 n10 ns48 0 -0.000422336413638 +Gc5_49 0 n10 ns49 0 -0.00033027902583 +Gc5_50 0 n10 ns50 0 0.000395248319462 +Gc5_51 0 n10 ns51 0 6.98026629643e-005 +Gc5_52 0 n10 ns52 0 -0.000422654272605 +Gc5_53 0 n10 ns53 0 -0.000466500683741 +Gc5_54 0 n10 ns54 0 -0.00342299244812 +Gc5_55 0 n10 ns55 0 0.000983258456139 +Gc5_56 0 n10 ns56 0 -0.000408316118202 +Gc5_57 0 n10 ns57 0 -0.00578036726589 +Gc5_58 0 n10 ns58 0 -0.000577886731537 +Gc5_59 0 n10 ns59 0 2.15433096495e-006 +Gc5_60 0 n10 ns60 0 -1.88220621516e-006 +Gc5_61 0 n10 ns61 0 -2.52404733256e-008 +Gc5_62 0 n10 ns62 0 -1.46461067495e-007 +Gc5_63 0 n10 ns63 0 0.000293460273368 +Gc5_64 0 n10 ns64 0 -0.000179734886517 +Gc5_65 0 n10 ns65 0 -0.000827570627315 +Gc5_66 0 n10 ns66 0 0.000536170640489 +Gc5_67 0 n10 ns67 0 0.000364935078916 +Gc5_68 0 n10 ns68 0 -0.000426778210669 +Gc5_69 0 n10 ns69 0 -0.000885771007504 +Gc5_70 0 n10 ns70 0 0.000277524426858 +Gc5_71 0 n10 ns71 0 0.000126999998161 +Gc5_72 0 n10 ns72 0 -0.00299219237427 +Gc5_73 0 n10 ns73 0 0.00114362674544 +Gc5_74 0 n10 ns74 0 0.00073461161255 +Gc5_75 0 n10 ns75 0 0.0119410439321 +Gc5_76 0 n10 ns76 0 0.00076609254524 +Gc5_77 0 n10 ns77 0 -7.6292670002e-007 +Gc5_78 0 n10 ns78 0 -3.50136803067e-006 +Gc5_79 0 n10 ns79 0 1.02271340868e-006 +Gc5_80 0 n10 ns80 0 3.60974446357e-007 +Gc5_81 0 n10 ns81 0 9.41205539611e-005 +Gc5_82 0 n10 ns82 0 -9.51619204023e-005 +Gc5_83 0 n10 ns83 0 0.000810007267975 +Gc5_84 0 n10 ns84 0 -0.00049420472136 +Gc5_85 0 n10 ns85 0 0.00026905683595 +Gc5_86 0 n10 ns86 0 -0.000486539658972 +Gc5_87 0 n10 ns87 0 0.00138260061698 +Gc5_88 0 n10 ns88 0 -0.00132753998577 +Gc5_89 0 n10 ns89 0 0.01239572645 +Gc5_90 0 n10 ns90 0 0.069645743067 +Gc5_91 0 n10 ns91 0 0.000991222809392 +Gc5_92 0 n10 ns92 0 -0.000428021200932 +Gc5_93 0 n10 ns93 0 -0.00588452277568 +Gc5_94 0 n10 ns94 0 -0.00046966559444 +Gc5_95 0 n10 ns95 0 9.35612569693e-007 +Gc5_96 0 n10 ns96 0 -1.52518161502e-006 +Gc5_97 0 n10 ns97 0 1.77567373578e-007 +Gc5_98 0 n10 ns98 0 -1.16392542353e-007 +Gc5_99 0 n10 ns99 0 -0.000447671306387 +Gc5_100 0 n10 ns100 0 0.00030254649767 +Gc5_101 0 n10 ns101 0 -0.00030642486294 +Gc5_102 0 n10 ns102 0 0.000183615292897 +Gc5_103 0 n10 ns103 0 0.000411324074905 +Gc5_104 0 n10 ns104 0 -0.000521250787126 +Gc5_105 0 n10 ns105 0 -0.000473271684986 +Gc5_106 0 n10 ns106 0 7.04010566154e-006 +Gc5_107 0 n10 ns107 0 0.000176034263806 +Gc5_108 0 n10 ns108 0 -0.00332252580262 +Gd5_1 0 n10 ni1 0 0.00119354005171 +Gd5_2 0 n10 ni2 0 -0.00479059010934 +Gd5_3 0 n10 ni3 0 0.00154685198578 +Gd5_4 0 n10 ni4 0 0.000873667371215 +Gd5_5 0 n10 ni5 0 0.00494027067004 +Gd5_6 0 n10 ni6 0 0.00135061066574 +Gc6_1 0 n12 ns1 0 -0.0011263984707 +Gc6_2 0 n12 ns2 0 -0.000857746979362 +Gc6_3 0 n12 ns3 0 -0.0119556506726 +Gc6_4 0 n12 ns4 0 -0.000721406246428 +Gc6_5 0 n12 ns5 0 2.53919619085e-007 +Gc6_6 0 n12 ns6 0 -1.07084195153e-006 +Gc6_7 0 n12 ns7 0 -1.59612780424e-007 +Gc6_8 0 n12 ns8 0 -8.56480471093e-007 +Gc6_9 0 n12 ns9 0 -0.00110675125943 +Gc6_10 0 n12 ns10 0 0.000798715280265 +Gc6_11 0 n12 ns11 0 -9.13926768538e-005 +Gc6_12 0 n12 ns12 0 5.05662763967e-005 +Gc6_13 0 n12 ns13 0 -0.000554095963961 +Gc6_14 0 n12 ns14 0 0.00053662954653 +Gc6_15 0 n12 ns15 0 -0.00146318282164 +Gc6_16 0 n12 ns16 0 0.00218343333619 +Gc6_17 0 n12 ns17 0 -0.0171579477275 +Gc6_18 0 n12 ns18 0 -0.0447547747815 +Gc6_19 0 n12 ns19 0 -0.000989479391902 +Gc6_20 0 n12 ns20 0 0.000420905468323 +Gc6_21 0 n12 ns21 0 0.00589741276483 +Gc6_22 0 n12 ns22 0 0.000447278046443 +Gc6_23 0 n12 ns23 0 -1.97646385753e-007 +Gc6_24 0 n12 ns24 0 1.26506209931e-006 +Gc6_25 0 n12 ns25 0 -2.45830264813e-007 +Gc6_26 0 n12 ns26 0 -3.71681845865e-007 +Gc6_27 0 n12 ns27 0 0.000395615867612 +Gc6_28 0 n12 ns28 0 -0.000271457341284 +Gc6_29 0 n12 ns29 0 0.00020210331653 +Gc6_30 0 n12 ns30 0 -0.00012832169228 +Gc6_31 0 n12 ns31 0 -0.000484268179605 +Gc6_32 0 n12 ns32 0 0.000527756383755 +Gc6_33 0 n12 ns33 0 -5.75818123915e-005 +Gc6_34 0 n12 ns34 0 -0.000340869188335 +Gc6_35 0 n12 ns35 0 0.00121928474476 +Gc6_36 0 n12 ns36 0 -0.00101779651723 +Gc6_37 0 n12 ns37 0 -0.000985150355912 +Gc6_38 0 n12 ns38 0 0.000434417018826 +Gc6_39 0 n12 ns39 0 0.00593969410261 +Gc6_40 0 n12 ns40 0 0.000367468616592 +Gc6_41 0 n12 ns41 0 7.09326495285e-007 +Gc6_42 0 n12 ns42 0 1.01785020507e-006 +Gc6_43 0 n12 ns43 0 -3.9040996976e-007 +Gc6_44 0 n12 ns44 0 -3.0490614059e-007 +Gc6_45 0 n12 ns45 0 0.000594772881034 +Gc6_46 0 n12 ns46 0 -0.000316433106123 +Gc6_47 0 n12 ns47 0 -0.000238694318408 +Gc6_48 0 n12 ns48 0 0.00016556099663 +Gc6_49 0 n12 ns49 0 -0.00047769189777 +Gc6_50 0 n12 ns50 0 0.000397816825354 +Gc6_51 0 n12 ns51 0 -5.38159913074e-005 +Gc6_52 0 n12 ns52 0 -0.000328244084135 +Gc6_53 0 n12 ns53 0 0.000737926379474 +Gc6_54 0 n12 ns54 0 -0.00188251749393 +Gc6_55 0 n12 ns55 0 0.000993131342449 +Gc6_56 0 n12 ns56 0 -0.000441068628454 +Gc6_57 0 n12 ns57 0 -0.0059338972708 +Gc6_58 0 n12 ns58 0 -0.000385542051556 +Gc6_59 0 n12 ns59 0 7.62241910894e-008 +Gc6_60 0 n12 ns60 0 -1.19080902255e-006 +Gc6_61 0 n12 ns61 0 2.88078567546e-007 +Gc6_62 0 n12 ns62 0 -2.07069502152e-007 +Gc6_63 0 n12 ns63 0 -0.0011505042789 +Gc6_64 0 n12 ns64 0 0.000521077811246 +Gc6_65 0 n12 ns65 0 0.000325126462024 +Gc6_66 0 n12 ns66 0 -0.000214715816435 +Gc6_67 0 n12 ns67 0 0.000524194832941 +Gc6_68 0 n12 ns68 0 -0.000427876003736 +Gc6_69 0 n12 ns69 0 -0.000614723653326 +Gc6_70 0 n12 ns70 0 -0.000180126107126 +Gc6_71 0 n12 ns71 0 -0.000125435917354 +Gc6_72 0 n12 ns72 0 -0.00262926176876 +Gc6_73 0 n12 ns73 0 0.000994988465606 +Gc6_74 0 n12 ns74 0 -0.000427539671374 +Gc6_75 0 n12 ns75 0 -0.00588609027302 +Gc6_76 0 n12 ns76 0 -0.000469562011407 +Gc6_77 0 n12 ns77 0 9.32662342399e-007 +Gc6_78 0 n12 ns78 0 -1.53731129955e-006 +Gc6_79 0 n12 ns79 0 1.65820968674e-007 +Gc6_80 0 n12 ns80 0 -1.26553145203e-007 +Gc6_81 0 n12 ns81 0 -0.000447529315811 +Gc6_82 0 n12 ns82 0 0.000302336053616 +Gc6_83 0 n12 ns83 0 -0.000306397460545 +Gc6_84 0 n12 ns84 0 0.000183724384943 +Gc6_85 0 n12 ns85 0 0.000411199882416 +Gc6_86 0 n12 ns86 0 -0.000520965074329 +Gc6_87 0 n12 ns87 0 -0.000472103690886 +Gc6_88 0 n12 ns88 0 4.0160281635e-006 +Gc6_89 0 n12 ns89 0 0.00016097843425 +Gc6_90 0 n12 ns90 0 -0.00333723463386 +Gc6_91 0 n12 ns91 0 0.00114341863039 +Gc6_92 0 n12 ns92 0 0.000762625120103 +Gc6_93 0 n12 ns93 0 0.0120817101549 +Gc6_94 0 n12 ns94 0 0.00059781228233 +Gc6_95 0 n12 ns95 0 8.88507247206e-007 +Gc6_96 0 n12 ns96 0 -4.09599052308e-006 +Gc6_97 0 n12 ns97 0 7.21314316067e-007 +Gc6_98 0 n12 ns98 0 2.82603071266e-007 +Gc6_99 0 n12 ns99 0 0.00166796827297 +Gc6_100 0 n12 ns100 0 -0.00105329617015 +Gc6_101 0 n12 ns101 0 0.000152537696915 +Gc6_102 0 n12 ns102 0 -7.18214308844e-005 +Gc6_103 0 n12 ns103 0 0.000599112108952 +Gc6_104 0 n12 ns104 0 -0.00053040412886 +Gc6_105 0 n12 ns105 0 0.00207974186042 +Gc6_106 0 n12 ns106 0 -0.00124949423949 +Gc6_107 0 n12 ns107 0 -0.000533884073017 +Gc6_108 0 n12 ns108 0 0.0512696326889 +Gd6_1 0 n12 ni1 0 -0.00189333041546 +Gd6_2 0 n12 ni2 0 0.00204199974394 +Gd6_3 0 n12 ni3 0 0.00176806078888 +Gd6_4 0 n12 ni4 0 0.00100970662242 +Gd6_5 0 n12 ni5 0 0.00134491698275 +Gd6_6 0 n12 ni6 0 0.000786766578813 +.ends diff --git a/spice/copy/sub/Contrib/Wurth/WE-TPBHV.lib b/spice/copy/sub/Contrib/Wurth/WE-TPBHV.lib new file mode 100755 index 0000000..105915d --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-TPBHV.lib @@ -0,0 +1,34431 @@ + +.subckt 744835021220 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 53470373.653 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 3064028.86216 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 524560.804073 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 121434.060612 +Ca5 ns5 0 1e-012 +Ca6 ns6 0 1e-012 +Ra5 ns5 0 93676.1683439 +Ra6 ns6 0 93676.1683439 +Ga5 ns5 0 ns6 0 -1.32406937189e-006 +Ga6 ns6 0 ns5 0 1.32406937189e-006 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 2568604.28548 +Ra8 ns8 0 2568604.28548 +Ga7 ns7 0 ns8 0 -1.93606942641e-005 +Ga8 ns8 0 ns7 0 1.93606942641e-005 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 59402.4965533 +Ra10 ns10 0 59402.4965533 +Ga9 ns9 0 ns10 0 -2.44034588029e-005 +Ga10 ns10 0 ns9 0 2.44034588029e-005 +Ca11 ns11 0 1e-012 +Ra11 ns11 0 15532.7073519 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 280068.055244 +Ra13 ns13 0 280068.055244 +Ga12 ns12 0 ns13 0 -0.000214391214058 +Ga13 ns13 0 ns12 0 0.000214391214058 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 16510.382539 +Ra15 ns15 0 16510.382539 +Ga14 ns14 0 ns15 0 -0.000273347495029 +Ga15 ns15 0 ns14 0 0.000273347495029 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 15646.4252602 +Ra17 ns17 0 15646.4252602 +Ga16 ns16 0 ns17 0 -0.000282732902545 +Ga17 ns17 0 ns16 0 0.000282732902545 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 14240.9568277 +Ra19 ns19 0 14240.9568277 +Ga18 ns18 0 ns19 0 -0.000346840691063 +Ga19 ns19 0 ns18 0 0.000346840691063 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 49616.7443209 +Ra21 ns21 0 49616.7443209 +Ga20 ns20 0 ns21 0 -0.000361423329675 +Ga21 ns21 0 ns20 0 0.000361423329675 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 84397.2184576 +Ra23 ns23 0 84397.2184576 +Ga22 ns22 0 ns23 0 -0.000441479446341 +Ga23 ns23 0 ns22 0 0.000441479446341 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 11905.9943737 +Ra25 ns25 0 11905.9943737 +Ga24 ns24 0 ns25 0 -0.000599425845674 +Ga25 ns25 0 ns24 0 0.000599425845674 +Ca26 ns26 0 1e-012 +Ca27 ns27 0 1e-012 +Ra26 ns26 0 6516.40141978 +Ra27 ns27 0 6516.40141978 +Ga26 ns26 0 ns27 0 -0.000882524520416 +Ga27 ns27 0 ns26 0 0.000882524520416 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 1199.27832416 +Ra29 ns29 0 1199.27832416 +Ga28 ns28 0 ns29 0 -0.000574235418143 +Ga29 ns29 0 ns28 0 0.000574235418143 +Ca30 ns30 0 1e-012 +Ra30 ns30 0 53470373.653 +Ca31 ns31 0 1e-012 +Ra31 ns31 0 3064028.86216 +Ca32 ns32 0 1e-012 +Ra32 ns32 0 524560.804073 +Ca33 ns33 0 1e-012 +Ra33 ns33 0 121434.060612 +Ca34 ns34 0 1e-012 +Ca35 ns35 0 1e-012 +Ra34 ns34 0 93676.1683439 +Ra35 ns35 0 93676.1683439 +Ga34 ns34 0 ns35 0 -1.32406937189e-006 +Ga35 ns35 0 ns34 0 1.32406937189e-006 +Ca36 ns36 0 1e-012 +Ca37 ns37 0 1e-012 +Ra36 ns36 0 2568604.28548 +Ra37 ns37 0 2568604.28548 +Ga36 ns36 0 ns37 0 -1.93606942641e-005 +Ga37 ns37 0 ns36 0 1.93606942641e-005 +Ca38 ns38 0 1e-012 +Ca39 ns39 0 1e-012 +Ra38 ns38 0 59402.4965533 +Ra39 ns39 0 59402.4965533 +Ga38 ns38 0 ns39 0 -2.44034588029e-005 +Ga39 ns39 0 ns38 0 2.44034588029e-005 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 15532.7073519 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 280068.055244 +Ra42 ns42 0 280068.055244 +Ga41 ns41 0 ns42 0 -0.000214391214058 +Ga42 ns42 0 ns41 0 0.000214391214058 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 16510.382539 +Ra44 ns44 0 16510.382539 +Ga43 ns43 0 ns44 0 -0.000273347495029 +Ga44 ns44 0 ns43 0 0.000273347495029 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 15646.4252602 +Ra46 ns46 0 15646.4252602 +Ga45 ns45 0 ns46 0 -0.000282732902545 +Ga46 ns46 0 ns45 0 0.000282732902545 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 14240.9568277 +Ra48 ns48 0 14240.9568277 +Ga47 ns47 0 ns48 0 -0.000346840691063 +Ga48 ns48 0 ns47 0 0.000346840691063 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 49616.7443209 +Ra50 ns50 0 49616.7443209 +Ga49 ns49 0 ns50 0 -0.000361423329675 +Ga50 ns50 0 ns49 0 0.000361423329675 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 84397.2184576 +Ra52 ns52 0 84397.2184576 +Ga51 ns51 0 ns52 0 -0.000441479446341 +Ga52 ns52 0 ns51 0 0.000441479446341 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 11905.9943737 +Ra54 ns54 0 11905.9943737 +Ga53 ns53 0 ns54 0 -0.000599425845674 +Ga54 ns54 0 ns53 0 0.000599425845674 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 6516.40141978 +Ra56 ns56 0 6516.40141978 +Ga55 ns55 0 ns56 0 -0.000882524520416 +Ga56 ns56 0 ns55 0 0.000882524520416 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 1199.27832416 +Ra58 ns58 0 1199.27832416 +Ga57 ns57 0 ns58 0 -0.000574235418143 +Ga58 ns58 0 ns57 0 0.000574235418143 +Ca59 ns59 0 1e-012 +Ra59 ns59 0 53470373.653 +Ca60 ns60 0 1e-012 +Ra60 ns60 0 3064028.86216 +Ca61 ns61 0 1e-012 +Ra61 ns61 0 524560.804073 +Ca62 ns62 0 1e-012 +Ra62 ns62 0 121434.060612 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 93676.1683439 +Ra64 ns64 0 93676.1683439 +Ga63 ns63 0 ns64 0 -1.32406937189e-006 +Ga64 ns64 0 ns63 0 1.32406937189e-006 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 2568604.28548 +Ra66 ns66 0 2568604.28548 +Ga65 ns65 0 ns66 0 -1.93606942641e-005 +Ga66 ns66 0 ns65 0 1.93606942641e-005 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 59402.4965533 +Ra68 ns68 0 59402.4965533 +Ga67 ns67 0 ns68 0 -2.44034588029e-005 +Ga68 ns68 0 ns67 0 2.44034588029e-005 +Ca69 ns69 0 1e-012 +Ra69 ns69 0 15532.7073519 +Ca70 ns70 0 1e-012 +Ca71 ns71 0 1e-012 +Ra70 ns70 0 280068.055244 +Ra71 ns71 0 280068.055244 +Ga70 ns70 0 ns71 0 -0.000214391214058 +Ga71 ns71 0 ns70 0 0.000214391214058 +Ca72 ns72 0 1e-012 +Ca73 ns73 0 1e-012 +Ra72 ns72 0 16510.382539 +Ra73 ns73 0 16510.382539 +Ga72 ns72 0 ns73 0 -0.000273347495029 +Ga73 ns73 0 ns72 0 0.000273347495029 +Ca74 ns74 0 1e-012 +Ca75 ns75 0 1e-012 +Ra74 ns74 0 15646.4252602 +Ra75 ns75 0 15646.4252602 +Ga74 ns74 0 ns75 0 -0.000282732902545 +Ga75 ns75 0 ns74 0 0.000282732902545 +Ca76 ns76 0 1e-012 +Ca77 ns77 0 1e-012 +Ra76 ns76 0 14240.9568277 +Ra77 ns77 0 14240.9568277 +Ga76 ns76 0 ns77 0 -0.000346840691063 +Ga77 ns77 0 ns76 0 0.000346840691063 +Ca78 ns78 0 1e-012 +Ca79 ns79 0 1e-012 +Ra78 ns78 0 49616.7443209 +Ra79 ns79 0 49616.7443209 +Ga78 ns78 0 ns79 0 -0.000361423329675 +Ga79 ns79 0 ns78 0 0.000361423329675 +Ca80 ns80 0 1e-012 +Ca81 ns81 0 1e-012 +Ra80 ns80 0 84397.2184576 +Ra81 ns81 0 84397.2184576 +Ga80 ns80 0 ns81 0 -0.000441479446341 +Ga81 ns81 0 ns80 0 0.000441479446341 +Ca82 ns82 0 1e-012 +Ca83 ns83 0 1e-012 +Ra82 ns82 0 11905.9943737 +Ra83 ns83 0 11905.9943737 +Ga82 ns82 0 ns83 0 -0.000599425845674 +Ga83 ns83 0 ns82 0 0.000599425845674 +Ca84 ns84 0 1e-012 +Ca85 ns85 0 1e-012 +Ra84 ns84 0 6516.40141978 +Ra85 ns85 0 6516.40141978 +Ga84 ns84 0 ns85 0 -0.000882524520416 +Ga85 ns85 0 ns84 0 0.000882524520416 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 1199.27832416 +Ra87 ns87 0 1199.27832416 +Ga86 ns86 0 ns87 0 -0.000574235418143 +Ga87 ns87 0 ns86 0 0.000574235418143 +Ca88 ns88 0 1e-012 +Ra88 ns88 0 53470373.653 +Ca89 ns89 0 1e-012 +Ra89 ns89 0 3064028.86216 +Ca90 ns90 0 1e-012 +Ra90 ns90 0 524560.804073 +Ca91 ns91 0 1e-012 +Ra91 ns91 0 121434.060612 +Ca92 ns92 0 1e-012 +Ca93 ns93 0 1e-012 +Ra92 ns92 0 93676.1683439 +Ra93 ns93 0 93676.1683439 +Ga92 ns92 0 ns93 0 -1.32406937189e-006 +Ga93 ns93 0 ns92 0 1.32406937189e-006 +Ca94 ns94 0 1e-012 +Ca95 ns95 0 1e-012 +Ra94 ns94 0 2568604.28548 +Ra95 ns95 0 2568604.28548 +Ga94 ns94 0 ns95 0 -1.93606942641e-005 +Ga95 ns95 0 ns94 0 1.93606942641e-005 +Ca96 ns96 0 1e-012 +Ca97 ns97 0 1e-012 +Ra96 ns96 0 59402.4965533 +Ra97 ns97 0 59402.4965533 +Ga96 ns96 0 ns97 0 -2.44034588029e-005 +Ga97 ns97 0 ns96 0 2.44034588029e-005 +Ca98 ns98 0 1e-012 +Ra98 ns98 0 15532.7073519 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 280068.055244 +Ra100 ns100 0 280068.055244 +Ga99 ns99 0 ns100 0 -0.000214391214058 +Ga100 ns100 0 ns99 0 0.000214391214058 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 16510.382539 +Ra102 ns102 0 16510.382539 +Ga101 ns101 0 ns102 0 -0.000273347495029 +Ga102 ns102 0 ns101 0 0.000273347495029 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 15646.4252602 +Ra104 ns104 0 15646.4252602 +Ga103 ns103 0 ns104 0 -0.000282732902545 +Ga104 ns104 0 ns103 0 0.000282732902545 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 14240.9568277 +Ra106 ns106 0 14240.9568277 +Ga105 ns105 0 ns106 0 -0.000346840691063 +Ga106 ns106 0 ns105 0 0.000346840691063 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 49616.7443209 +Ra108 ns108 0 49616.7443209 +Ga107 ns107 0 ns108 0 -0.000361423329675 +Ga108 ns108 0 ns107 0 0.000361423329675 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 84397.2184576 +Ra110 ns110 0 84397.2184576 +Ga109 ns109 0 ns110 0 -0.000441479446341 +Ga110 ns110 0 ns109 0 0.000441479446341 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 11905.9943737 +Ra112 ns112 0 11905.9943737 +Ga111 ns111 0 ns112 0 -0.000599425845674 +Ga112 ns112 0 ns111 0 0.000599425845674 +Ca113 ns113 0 1e-012 +Ca114 ns114 0 1e-012 +Ra113 ns113 0 6516.40141978 +Ra114 ns114 0 6516.40141978 +Ga113 ns113 0 ns114 0 -0.000882524520416 +Ga114 ns114 0 ns113 0 0.000882524520416 +Ca115 ns115 0 1e-012 +Ca116 ns116 0 1e-012 +Ra115 ns115 0 1199.27832416 +Ra116 ns116 0 1199.27832416 +Ga115 ns115 0 ns116 0 -0.000574235418143 +Ga116 ns116 0 ns115 0 0.000574235418143 +Ca117 ns117 0 1e-012 +Ra117 ns117 0 53470373.653 +Ca118 ns118 0 1e-012 +Ra118 ns118 0 3064028.86216 +Ca119 ns119 0 1e-012 +Ra119 ns119 0 524560.804073 +Ca120 ns120 0 1e-012 +Ra120 ns120 0 121434.060612 +Ca121 ns121 0 1e-012 +Ca122 ns122 0 1e-012 +Ra121 ns121 0 93676.1683439 +Ra122 ns122 0 93676.1683439 +Ga121 ns121 0 ns122 0 -1.32406937189e-006 +Ga122 ns122 0 ns121 0 1.32406937189e-006 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 2568604.28548 +Ra124 ns124 0 2568604.28548 +Ga123 ns123 0 ns124 0 -1.93606942641e-005 +Ga124 ns124 0 ns123 0 1.93606942641e-005 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 59402.4965533 +Ra126 ns126 0 59402.4965533 +Ga125 ns125 0 ns126 0 -2.44034588029e-005 +Ga126 ns126 0 ns125 0 2.44034588029e-005 +Ca127 ns127 0 1e-012 +Ra127 ns127 0 15532.7073519 +Ca128 ns128 0 1e-012 +Ca129 ns129 0 1e-012 +Ra128 ns128 0 280068.055244 +Ra129 ns129 0 280068.055244 +Ga128 ns128 0 ns129 0 -0.000214391214058 +Ga129 ns129 0 ns128 0 0.000214391214058 +Ca130 ns130 0 1e-012 +Ca131 ns131 0 1e-012 +Ra130 ns130 0 16510.382539 +Ra131 ns131 0 16510.382539 +Ga130 ns130 0 ns131 0 -0.000273347495029 +Ga131 ns131 0 ns130 0 0.000273347495029 +Ca132 ns132 0 1e-012 +Ca133 ns133 0 1e-012 +Ra132 ns132 0 15646.4252602 +Ra133 ns133 0 15646.4252602 +Ga132 ns132 0 ns133 0 -0.000282732902545 +Ga133 ns133 0 ns132 0 0.000282732902545 +Ca134 ns134 0 1e-012 +Ca135 ns135 0 1e-012 +Ra134 ns134 0 14240.9568277 +Ra135 ns135 0 14240.9568277 +Ga134 ns134 0 ns135 0 -0.000346840691063 +Ga135 ns135 0 ns134 0 0.000346840691063 +Ca136 ns136 0 1e-012 +Ca137 ns137 0 1e-012 +Ra136 ns136 0 49616.7443209 +Ra137 ns137 0 49616.7443209 +Ga136 ns136 0 ns137 0 -0.000361423329675 +Ga137 ns137 0 ns136 0 0.000361423329675 +Ca138 ns138 0 1e-012 +Ca139 ns139 0 1e-012 +Ra138 ns138 0 84397.2184576 +Ra139 ns139 0 84397.2184576 +Ga138 ns138 0 ns139 0 -0.000441479446341 +Ga139 ns139 0 ns138 0 0.000441479446341 +Ca140 ns140 0 1e-012 +Ca141 ns141 0 1e-012 +Ra140 ns140 0 11905.9943737 +Ra141 ns141 0 11905.9943737 +Ga140 ns140 0 ns141 0 -0.000599425845674 +Ga141 ns141 0 ns140 0 0.000599425845674 +Ca142 ns142 0 1e-012 +Ca143 ns143 0 1e-012 +Ra142 ns142 0 6516.40141978 +Ra143 ns143 0 6516.40141978 +Ga142 ns142 0 ns143 0 -0.000882524520416 +Ga143 ns143 0 ns142 0 0.000882524520416 +Ca144 ns144 0 1e-012 +Ca145 ns145 0 1e-012 +Ra144 ns144 0 1199.27832416 +Ra145 ns145 0 1199.27832416 +Ga144 ns144 0 ns145 0 -0.000574235418143 +Ga145 ns145 0 ns144 0 0.000574235418143 +Ca146 ns146 0 1e-012 +Ra146 ns146 0 53470373.653 +Ca147 ns147 0 1e-012 +Ra147 ns147 0 3064028.86216 +Ca148 ns148 0 1e-012 +Ra148 ns148 0 524560.804073 +Ca149 ns149 0 1e-012 +Ra149 ns149 0 121434.060612 +Ca150 ns150 0 1e-012 +Ca151 ns151 0 1e-012 +Ra150 ns150 0 93676.1683439 +Ra151 ns151 0 93676.1683439 +Ga150 ns150 0 ns151 0 -1.32406937189e-006 +Ga151 ns151 0 ns150 0 1.32406937189e-006 +Ca152 ns152 0 1e-012 +Ca153 ns153 0 1e-012 +Ra152 ns152 0 2568604.28548 +Ra153 ns153 0 2568604.28548 +Ga152 ns152 0 ns153 0 -1.93606942641e-005 +Ga153 ns153 0 ns152 0 1.93606942641e-005 +Ca154 ns154 0 1e-012 +Ca155 ns155 0 1e-012 +Ra154 ns154 0 59402.4965533 +Ra155 ns155 0 59402.4965533 +Ga154 ns154 0 ns155 0 -2.44034588029e-005 +Ga155 ns155 0 ns154 0 2.44034588029e-005 +Ca156 ns156 0 1e-012 +Ra156 ns156 0 15532.7073519 +Ca157 ns157 0 1e-012 +Ca158 ns158 0 1e-012 +Ra157 ns157 0 280068.055244 +Ra158 ns158 0 280068.055244 +Ga157 ns157 0 ns158 0 -0.000214391214058 +Ga158 ns158 0 ns157 0 0.000214391214058 +Ca159 ns159 0 1e-012 +Ca160 ns160 0 1e-012 +Ra159 ns159 0 16510.382539 +Ra160 ns160 0 16510.382539 +Ga159 ns159 0 ns160 0 -0.000273347495029 +Ga160 ns160 0 ns159 0 0.000273347495029 +Ca161 ns161 0 1e-012 +Ca162 ns162 0 1e-012 +Ra161 ns161 0 15646.4252602 +Ra162 ns162 0 15646.4252602 +Ga161 ns161 0 ns162 0 -0.000282732902545 +Ga162 ns162 0 ns161 0 0.000282732902545 +Ca163 ns163 0 1e-012 +Ca164 ns164 0 1e-012 +Ra163 ns163 0 14240.9568277 +Ra164 ns164 0 14240.9568277 +Ga163 ns163 0 ns164 0 -0.000346840691063 +Ga164 ns164 0 ns163 0 0.000346840691063 +Ca165 ns165 0 1e-012 +Ca166 ns166 0 1e-012 +Ra165 ns165 0 49616.7443209 +Ra166 ns166 0 49616.7443209 +Ga165 ns165 0 ns166 0 -0.000361423329675 +Ga166 ns166 0 ns165 0 0.000361423329675 +Ca167 ns167 0 1e-012 +Ca168 ns168 0 1e-012 +Ra167 ns167 0 84397.2184576 +Ra168 ns168 0 84397.2184576 +Ga167 ns167 0 ns168 0 -0.000441479446341 +Ga168 ns168 0 ns167 0 0.000441479446341 +Ca169 ns169 0 1e-012 +Ca170 ns170 0 1e-012 +Ra169 ns169 0 11905.9943737 +Ra170 ns170 0 11905.9943737 +Ga169 ns169 0 ns170 0 -0.000599425845674 +Ga170 ns170 0 ns169 0 0.000599425845674 +Ca171 ns171 0 1e-012 +Ca172 ns172 0 1e-012 +Ra171 ns171 0 6516.40141978 +Ra172 ns172 0 6516.40141978 +Ga171 ns171 0 ns172 0 -0.000882524520416 +Ga172 ns172 0 ns171 0 0.000882524520416 +Ca173 ns173 0 1e-012 +Ca174 ns174 0 1e-012 +Ra173 ns173 0 1199.27832416 +Ra174 ns174 0 1199.27832416 +Ga173 ns173 0 ns174 0 -0.000574235418143 +Ga174 ns174 0 ns173 0 0.000574235418143 + +Gb1_1 ns1 0 ni1 0 1.87019452396e-008 +Gb2_1 ns2 0 ni1 0 3.26367682873e-007 +Gb3_1 ns3 0 ni1 0 1.90635669352e-006 +Gb4_1 ns4 0 ni1 0 8.23492185766e-006 +Gb5_1 ns5 0 ni1 0 1.08393029726e-005 +Gb7_1 ns7 0 ni1 0 1.93685228743e-005 +Gb9_1 ns9 0 ni1 0 3.60163195781e-005 +Gb11_1 ns11 0 ni1 0 6.43802768794e-005 +Gb12_1 ns12 0 ni1 0 0.000214450679666 +Gb14_1 ns14 0 ni1 0 0.000286768054782 +Gb16_1 ns16 0 ni1 0 0.000297180425343 +Gb18_1 ns18 0 ni1 0 0.000361057155974 +Gb20_1 ns20 0 ni1 0 0.000362547228687 +Gb22_1 ns22 0 ni1 0 0.000441797450825 +Gb24_1 ns24 0 ni1 0 0.00061119467296 +Gb26_1 ns26 0 ni1 0 0.000909208927653 +Gb28_1 ns28 0 ni1 0 0.00122929240728 +Gb30_2 ns30 0 ni2 0 1.87019452396e-008 +Gb31_2 ns31 0 ni2 0 3.26367682873e-007 +Gb32_2 ns32 0 ni2 0 1.90635669352e-006 +Gb33_2 ns33 0 ni2 0 8.23492185766e-006 +Gb34_2 ns34 0 ni2 0 1.08393029726e-005 +Gb36_2 ns36 0 ni2 0 1.93685228743e-005 +Gb38_2 ns38 0 ni2 0 3.60163195781e-005 +Gb40_2 ns40 0 ni2 0 6.43802768794e-005 +Gb41_2 ns41 0 ni2 0 0.000214450679666 +Gb43_2 ns43 0 ni2 0 0.000286768054782 +Gb45_2 ns45 0 ni2 0 0.000297180425343 +Gb47_2 ns47 0 ni2 0 0.000361057155974 +Gb49_2 ns49 0 ni2 0 0.000362547228687 +Gb51_2 ns51 0 ni2 0 0.000441797450825 +Gb53_2 ns53 0 ni2 0 0.00061119467296 +Gb55_2 ns55 0 ni2 0 0.000909208927653 +Gb57_2 ns57 0 ni2 0 0.00122929240728 +Gb59_3 ns59 0 ni3 0 1.87019452396e-008 +Gb60_3 ns60 0 ni3 0 3.26367682873e-007 +Gb61_3 ns61 0 ni3 0 1.90635669352e-006 +Gb62_3 ns62 0 ni3 0 8.23492185766e-006 +Gb63_3 ns63 0 ni3 0 1.08393029726e-005 +Gb65_3 ns65 0 ni3 0 1.93685228743e-005 +Gb67_3 ns67 0 ni3 0 3.60163195781e-005 +Gb69_3 ns69 0 ni3 0 6.43802768794e-005 +Gb70_3 ns70 0 ni3 0 0.000214450679666 +Gb72_3 ns72 0 ni3 0 0.000286768054782 +Gb74_3 ns74 0 ni3 0 0.000297180425343 +Gb76_3 ns76 0 ni3 0 0.000361057155974 +Gb78_3 ns78 0 ni3 0 0.000362547228687 +Gb80_3 ns80 0 ni3 0 0.000441797450825 +Gb82_3 ns82 0 ni3 0 0.00061119467296 +Gb84_3 ns84 0 ni3 0 0.000909208927653 +Gb86_3 ns86 0 ni3 0 0.00122929240728 +Gb88_4 ns88 0 ni4 0 1.87019452396e-008 +Gb89_4 ns89 0 ni4 0 3.26367682873e-007 +Gb90_4 ns90 0 ni4 0 1.90635669352e-006 +Gb91_4 ns91 0 ni4 0 8.23492185766e-006 +Gb92_4 ns92 0 ni4 0 1.08393029726e-005 +Gb94_4 ns94 0 ni4 0 1.93685228743e-005 +Gb96_4 ns96 0 ni4 0 3.60163195781e-005 +Gb98_4 ns98 0 ni4 0 6.43802768794e-005 +Gb99_4 ns99 0 ni4 0 0.000214450679666 +Gb101_4 ns101 0 ni4 0 0.000286768054782 +Gb103_4 ns103 0 ni4 0 0.000297180425343 +Gb105_4 ns105 0 ni4 0 0.000361057155974 +Gb107_4 ns107 0 ni4 0 0.000362547228687 +Gb109_4 ns109 0 ni4 0 0.000441797450825 +Gb111_4 ns111 0 ni4 0 0.00061119467296 +Gb113_4 ns113 0 ni4 0 0.000909208927653 +Gb115_4 ns115 0 ni4 0 0.00122929240728 +Gb117_5 ns117 0 ni5 0 1.87019452396e-008 +Gb118_5 ns118 0 ni5 0 3.26367682873e-007 +Gb119_5 ns119 0 ni5 0 1.90635669352e-006 +Gb120_5 ns120 0 ni5 0 8.23492185766e-006 +Gb121_5 ns121 0 ni5 0 1.08393029726e-005 +Gb123_5 ns123 0 ni5 0 1.93685228743e-005 +Gb125_5 ns125 0 ni5 0 3.60163195781e-005 +Gb127_5 ns127 0 ni5 0 6.43802768794e-005 +Gb128_5 ns128 0 ni5 0 0.000214450679666 +Gb130_5 ns130 0 ni5 0 0.000286768054782 +Gb132_5 ns132 0 ni5 0 0.000297180425343 +Gb134_5 ns134 0 ni5 0 0.000361057155974 +Gb136_5 ns136 0 ni5 0 0.000362547228687 +Gb138_5 ns138 0 ni5 0 0.000441797450825 +Gb140_5 ns140 0 ni5 0 0.00061119467296 +Gb142_5 ns142 0 ni5 0 0.000909208927653 +Gb144_5 ns144 0 ni5 0 0.00122929240728 +Gb146_6 ns146 0 ni6 0 1.87019452396e-008 +Gb147_6 ns147 0 ni6 0 3.26367682873e-007 +Gb148_6 ns148 0 ni6 0 1.90635669352e-006 +Gb149_6 ns149 0 ni6 0 8.23492185766e-006 +Gb150_6 ns150 0 ni6 0 1.08393029726e-005 +Gb152_6 ns152 0 ni6 0 1.93685228743e-005 +Gb154_6 ns154 0 ni6 0 3.60163195781e-005 +Gb156_6 ns156 0 ni6 0 6.43802768794e-005 +Gb157_6 ns157 0 ni6 0 0.000214450679666 +Gb159_6 ns159 0 ni6 0 0.000286768054782 +Gb161_6 ns161 0 ni6 0 0.000297180425343 +Gb163_6 ns163 0 ni6 0 0.000361057155974 +Gb165_6 ns165 0 ni6 0 0.000362547228687 +Gb167_6 ns167 0 ni6 0 0.000441797450825 +Gb169_6 ns169 0 ni6 0 0.00061119467296 +Gb171_6 ns171 0 ni6 0 0.000909208927653 +Gb173_6 ns173 0 ni6 0 0.00122929240728 + +Gc1_1 0 n2 ns1 0 0.0066092899161 +Gc1_2 0 n2 ns2 0 2.2689510828e-005 +Gc1_3 0 n2 ns3 0 2.64067923118e-005 +Gc1_4 0 n2 ns4 0 0.00315888739439 +Gc1_5 0 n2 ns5 0 0.0113728864294 +Gc1_6 0 n2 ns6 0 0.00658946302068 +Gc1_7 0 n2 ns7 0 4.28279983207e-007 +Gc1_8 0 n2 ns8 0 2.35202015471e-007 +Gc1_9 0 n2 ns9 0 6.59051939484e-005 +Gc1_10 0 n2 ns10 0 3.77803508203e-005 +Gc1_11 0 n2 ns11 0 -0.000559712345936 +Gc1_12 0 n2 ns12 0 3.63704886744e-007 +Gc1_13 0 n2 ns13 0 8.40882277674e-007 +Gc1_14 0 n2 ns14 0 0.00193640715455 +Gc1_15 0 n2 ns15 0 0.00122443246614 +Gc1_16 0 n2 ns16 0 0.00140908991257 +Gc1_17 0 n2 ns17 0 -0.0013006971855 +Gc1_18 0 n2 ns18 0 0.00171197902755 +Gc1_19 0 n2 ns19 0 -0.00128045471814 +Gc1_20 0 n2 ns20 0 3.74202528596e-006 +Gc1_21 0 n2 ns21 0 4.16389482949e-006 +Gc1_22 0 n2 ns22 0 -5.90182663012e-007 +Gc1_23 0 n2 ns23 0 -6.13926430348e-007 +Gc1_24 0 n2 ns24 0 7.17812448533e-005 +Gc1_25 0 n2 ns25 0 9.70000939347e-005 +Gc1_26 0 n2 ns26 0 0.00294645987455 +Gc1_27 0 n2 ns27 0 0.000781248067944 +Gc1_28 0 n2 ns28 0 0.00568045793805 +Gc1_29 0 n2 ns29 0 0.03654904912 +Gc1_30 0 n2 ns30 0 0.00654782982601 +Gc1_31 0 n2 ns31 0 -1.27895791387e-005 +Gc1_32 0 n2 ns32 0 -4.4286261626e-005 +Gc1_33 0 n2 ns33 0 -0.00267130059662 +Gc1_34 0 n2 ns34 0 -0.00499107927456 +Gc1_35 0 n2 ns35 0 -0.00603227987973 +Gc1_36 0 n2 ns36 0 -1.11614791395e-007 +Gc1_37 0 n2 ns37 0 6.94098508449e-008 +Gc1_38 0 n2 ns38 0 -1.88296929798e-006 +Gc1_39 0 n2 ns39 0 -2.93447593567e-005 +Gc1_40 0 n2 ns40 0 3.11048741475e-005 +Gc1_41 0 n2 ns41 0 7.25171213348e-008 +Gc1_42 0 n2 ns42 0 6.2454800338e-007 +Gc1_43 0 n2 ns43 0 -0.000110063298035 +Gc1_44 0 n2 ns44 0 -0.000641855155093 +Gc1_45 0 n2 ns45 0 -0.00226838508262 +Gc1_46 0 n2 ns46 0 0.00105047011471 +Gc1_47 0 n2 ns47 0 0.00194888477207 +Gc1_48 0 n2 ns48 0 -0.0010313365206 +Gc1_49 0 n2 ns49 0 -1.74786179823e-006 +Gc1_50 0 n2 ns50 0 -3.56973733221e-006 +Gc1_51 0 n2 ns51 0 5.71969827323e-007 +Gc1_52 0 n2 ns52 0 9.01684834135e-007 +Gc1_53 0 n2 ns53 0 9.66643677198e-006 +Gc1_54 0 n2 ns54 0 -8.50288625411e-006 +Gc1_55 0 n2 ns55 0 -0.000416777408288 +Gc1_56 0 n2 ns56 0 0.000420473470059 +Gc1_57 0 n2 ns57 0 -0.0012314346518 +Gc1_58 0 n2 ns58 0 -0.00097043823712 +Gc1_59 0 n2 ns59 0 0.0065564887268 +Gc1_60 0 n2 ns60 0 -1.14817315156e-005 +Gc1_61 0 n2 ns61 0 -5.1771186841e-005 +Gc1_62 0 n2 ns62 0 -0.00238423714608 +Gc1_63 0 n2 ns63 0 -0.00492797862129 +Gc1_64 0 n2 ns64 0 -0.00366981301927 +Gc1_65 0 n2 ns65 0 -2.1136821331e-008 +Gc1_66 0 n2 ns66 0 5.14819379145e-008 +Gc1_67 0 n2 ns67 0 6.95579097895e-006 +Gc1_68 0 n2 ns68 0 -1.5065331129e-005 +Gc1_69 0 n2 ns69 0 -7.81306034879e-006 +Gc1_70 0 n2 ns70 0 3.83464237785e-007 +Gc1_71 0 n2 ns71 0 3.43171128857e-007 +Gc1_72 0 n2 ns72 0 -0.00266057105637 +Gc1_73 0 n2 ns73 0 -1.18680574391e-005 +Gc1_74 0 n2 ns74 0 0.000702625337976 +Gc1_75 0 n2 ns75 0 0.00028502460881 +Gc1_76 0 n2 ns76 0 0.00156969462388 +Gc1_77 0 n2 ns77 0 -0.000914408757038 +Gc1_78 0 n2 ns78 0 -4.2667047571e-007 +Gc1_79 0 n2 ns79 0 -1.57222530239e-006 +Gc1_80 0 n2 ns80 0 3.71407798113e-007 +Gc1_81 0 n2 ns81 0 6.49735690442e-007 +Gc1_82 0 n2 ns82 0 9.12150688576e-006 +Gc1_83 0 n2 ns83 0 -2.15304886776e-006 +Gc1_84 0 n2 ns84 0 -0.000393565887319 +Gc1_85 0 n2 ns85 0 0.000569131679629 +Gc1_86 0 n2 ns86 0 -0.00122019128862 +Gc1_87 0 n2 ns87 0 -0.00111248050206 +Gc1_88 0 n2 ns88 0 -0.00661038969336 +Gc1_89 0 n2 ns89 0 -3.21250420044e-005 +Gc1_90 0 n2 ns90 0 -1.2454810323e-005 +Gc1_91 0 n2 ns91 0 -0.00183450954138 +Gc1_92 0 n2 ns92 0 -0.0116853766698 +Gc1_93 0 n2 ns93 0 -0.00132962719323 +Gc1_94 0 n2 ns94 0 2.91188218304e-007 +Gc1_95 0 n2 ns95 0 -6.23981632969e-009 +Gc1_96 0 n2 ns96 0 3.75507870788e-005 +Gc1_97 0 n2 ns97 0 7.74747069934e-005 +Gc1_98 0 n2 ns98 0 1.98574605904e-005 +Gc1_99 0 n2 ns99 0 1.38018202923e-006 +Gc1_100 0 n2 ns100 0 3.59360535226e-008 +Gc1_101 0 n2 ns101 0 -0.000966367168291 +Gc1_102 0 n2 ns102 0 -0.000656585709685 +Gc1_103 0 n2 ns103 0 -0.00119034708734 +Gc1_104 0 n2 ns104 0 0.000830627397011 +Gc1_105 0 n2 ns105 0 -0.001602403518 +Gc1_106 0 n2 ns106 0 0.00106682612257 +Gc1_107 0 n2 ns107 0 -1.71149763578e-006 +Gc1_108 0 n2 ns108 0 1.98924139335e-006 +Gc1_109 0 n2 ns109 0 1.53849624598e-006 +Gc1_110 0 n2 ns110 0 4.33890899436e-007 +Gc1_111 0 n2 ns111 0 -3.18368761127e-005 +Gc1_112 0 n2 ns112 0 -5.96085170444e-005 +Gc1_113 0 n2 ns113 0 -0.000270509023668 +Gc1_114 0 n2 ns114 0 -0.00234649823516 +Gc1_115 0 n2 ns115 0 -0.00927076380842 +Gc1_116 0 n2 ns116 0 -0.00593289773683 +Gc1_117 0 n2 ns117 0 -0.00655102383693 +Gc1_118 0 n2 ns118 0 1.18011923958e-005 +Gc1_119 0 n2 ns119 0 4.8110723928e-005 +Gc1_120 0 n2 ns120 0 0.00239402504242 +Gc1_121 0 n2 ns121 0 0.00510953362208 +Gc1_122 0 n2 ns122 0 0.00520886324526 +Gc1_123 0 n2 ns123 0 3.57718111582e-008 +Gc1_124 0 n2 ns124 0 -5.11175295917e-008 +Gc1_125 0 n2 ns125 0 -4.94149238431e-006 +Gc1_126 0 n2 ns126 0 1.30793226695e-005 +Gc1_127 0 n2 ns127 0 1.44262734344e-005 +Gc1_128 0 n2 ns128 0 2.12432251872e-007 +Gc1_129 0 n2 ns129 0 -9.54686460435e-007 +Gc1_130 0 n2 ns130 0 3.69225806756e-005 +Gc1_131 0 n2 ns131 0 0.00041883347039 +Gc1_132 0 n2 ns132 0 0.00155708913887 +Gc1_133 0 n2 ns133 0 -0.000749938049577 +Gc1_134 0 n2 ns134 0 -0.00188079745212 +Gc1_135 0 n2 ns135 0 0.00106205445984 +Gc1_136 0 n2 ns136 0 1.74752522275e-006 +Gc1_137 0 n2 ns137 0 3.50980043305e-006 +Gc1_138 0 n2 ns138 0 -7.37601196796e-007 +Gc1_139 0 n2 ns139 0 -8.10902302023e-007 +Gc1_140 0 n2 ns140 0 -1.07989066162e-005 +Gc1_141 0 n2 ns141 0 2.08210904072e-005 +Gc1_142 0 n2 ns142 0 -0.000616834676577 +Gc1_143 0 n2 ns143 0 0.000690851968976 +Gc1_144 0 n2 ns144 0 0.000108971225143 +Gc1_145 0 n2 ns145 0 -0.00141977727449 +Gc1_146 0 n2 ns146 0 -0.00655981971548 +Gc1_147 0 n2 ns147 0 1.04079164024e-005 +Gc1_148 0 n2 ns148 0 5.697330855e-005 +Gc1_149 0 n2 ns149 0 0.00202467436185 +Gc1_150 0 n2 ns150 0 0.00509621961519 +Gc1_151 0 n2 ns151 0 0.00260773562289 +Gc1_152 0 n2 ns152 0 -7.2124125005e-008 +Gc1_153 0 n2 ns153 0 -3.21766425472e-008 +Gc1_154 0 n2 ns154 0 -1.63259993712e-005 +Gc1_155 0 n2 ns155 0 -4.92175974112e-006 +Gc1_156 0 n2 ns156 0 6.75301392267e-005 +Gc1_157 0 n2 ns157 0 3.17253038836e-007 +Gc1_158 0 n2 ns158 0 -8.88951358441e-007 +Gc1_159 0 n2 ns159 0 0.00184323340426 +Gc1_160 0 n2 ns160 0 -0.000115450690691 +Gc1_161 0 n2 ns161 0 -0.000365454627385 +Gc1_162 0 n2 ns162 0 -0.000210027386296 +Gc1_163 0 n2 ns163 0 -0.00158678889745 +Gc1_164 0 n2 ns164 0 0.000954327970358 +Gc1_165 0 n2 ns165 0 1.64746016734e-006 +Gc1_166 0 n2 ns166 0 1.84471292107e-006 +Gc1_167 0 n2 ns167 0 -9.18727181969e-007 +Gc1_168 0 n2 ns168 0 -5.00405810895e-007 +Gc1_169 0 n2 ns169 0 -1.80783670207e-006 +Gc1_170 0 n2 ns170 0 2.84140668092e-005 +Gc1_171 0 n2 ns171 0 -0.000507712992056 +Gc1_172 0 n2 ns172 0 0.00140531790732 +Gc1_173 0 n2 ns173 0 -4.64905184799e-005 +Gc1_174 0 n2 ns174 0 -0.00246543556283 +Gd1_1 0 n2 ni1 0 0.00248262695343 +Gd1_2 0 n2 ni2 0 -0.000852433167688 +Gd1_3 0 n2 ni3 0 -0.000847052470189 +Gd1_4 0 n2 ni4 0 -0.00501072190415 +Gd1_5 0 n2 ni5 0 -0.000192194906679 +Gd1_6 0 n2 ni6 0 -0.00018650051049 +Gc2_1 0 n4 ns1 0 0.00654007274212 +Gc2_2 0 n4 ns2 0 -1.12334369036e-005 +Gc2_3 0 n4 ns3 0 -5.26034517023e-005 +Gc2_4 0 n4 ns4 0 -0.00228600399026 +Gc2_5 0 n4 ns5 0 -0.00519624601406 +Gc2_6 0 n4 ns6 0 -0.00496516130371 +Gc2_7 0 n4 ns7 0 8.58242335239e-009 +Gc2_8 0 n4 ns8 0 7.12601202757e-008 +Gc2_9 0 n4 ns9 0 6.43537088535e-006 +Gc2_10 0 n4 ns10 0 -1.43598367687e-005 +Gc2_11 0 n4 ns11 0 -1.34263999086e-005 +Gc2_12 0 n4 ns12 0 1.38591383911e-007 +Gc2_13 0 n4 ns13 0 4.80895860315e-007 +Gc2_14 0 n4 ns14 0 -4.60035627962e-005 +Gc2_15 0 n4 ns15 0 -0.000705629246462 +Gc2_16 0 n4 ns16 0 -0.00231586977516 +Gc2_17 0 n4 ns17 0 0.00114688440237 +Gc2_18 0 n4 ns18 0 0.0019258742067 +Gc2_19 0 n4 ns19 0 -0.00103454909957 +Gc2_20 0 n4 ns20 0 -7.21140368669e-007 +Gc2_21 0 n4 ns21 0 -3.32875512223e-006 +Gc2_22 0 n4 ns22 0 4.43537546595e-007 +Gc2_23 0 n4 ns23 0 8.35657536588e-007 +Gc2_24 0 n4 ns24 0 1.16099144572e-005 +Gc2_25 0 n4 ns25 0 -8.73354405586e-006 +Gc2_26 0 n4 ns26 0 -0.000374588547182 +Gc2_27 0 n4 ns27 0 0.000400908809783 +Gc2_28 0 n4 ns28 0 -0.00145272012583 +Gc2_29 0 n4 ns29 0 -0.00122159833621 +Gc2_30 0 n4 ns30 0 0.00660844730604 +Gc2_31 0 n4 ns31 0 1.7734113137e-005 +Gc2_32 0 n4 ns32 0 3.86484880968e-005 +Gc2_33 0 n4 ns33 0 0.00245826632687 +Gc2_34 0 n4 ns34 0 0.0117101986119 +Gc2_35 0 n4 ns35 0 0.00356154358118 +Gc2_36 0 n4 ns36 0 2.97994988559e-007 +Gc2_37 0 n4 ns37 0 1.04476705062e-007 +Gc2_38 0 n4 ns38 0 4.29989279827e-005 +Gc2_39 0 n4 ns39 0 6.93783963014e-006 +Gc2_40 0 n4 ns40 0 -0.000483874692048 +Gc2_41 0 n4 ns41 0 5.2263101475e-009 +Gc2_42 0 n4 ns42 0 1.01838813014e-006 +Gc2_43 0 n4 ns43 0 0.000389066754738 +Gc2_44 0 n4 ns44 0 0.000164421878335 +Gc2_45 0 n4 ns45 0 0.00430622589981 +Gc2_46 0 n4 ns46 0 -0.0013395293904 +Gc2_47 0 n4 ns47 0 0.00214742912561 +Gc2_48 0 n4 ns48 0 -0.000992103278411 +Gc2_49 0 n4 ns49 0 -5.16989300208e-007 +Gc2_50 0 n4 ns50 0 -9.50532339231e-007 +Gc2_51 0 n4 ns51 0 1.80367199116e-007 +Gc2_52 0 n4 ns52 0 2.96133056099e-007 +Gc2_53 0 n4 ns53 0 6.25671120719e-005 +Gc2_54 0 n4 ns54 0 5.4137090025e-005 +Gc2_55 0 n4 ns55 0 0.00316217041032 +Gc2_56 0 n4 ns56 0 0.00016165324929 +Gc2_57 0 n4 ns57 0 0.00288454863751 +Gc2_58 0 n4 ns58 0 0.0373134264514 +Gc2_59 0 n4 ns59 0 0.00656583725132 +Gc2_60 0 n4 ns60 0 -9.85447504356e-006 +Gc2_61 0 n4 ns61 0 -6.18367000326e-005 +Gc2_62 0 n4 ns62 0 -0.00218213861345 +Gc2_63 0 n4 ns63 0 -0.0049683859738 +Gc2_64 0 n4 ns64 0 -0.00251034189482 +Gc2_65 0 n4 ns65 0 3.91532594014e-008 +Gc2_66 0 n4 ns66 0 4.92352814319e-008 +Gc2_67 0 n4 ns67 0 1.21811440446e-005 +Gc2_68 0 n4 ns68 0 -3.50337030636e-006 +Gc2_69 0 n4 ns69 0 -4.84000108642e-005 +Gc2_70 0 n4 ns70 0 3.33054148521e-007 +Gc2_71 0 n4 ns71 0 3.00807659135e-007 +Gc2_72 0 n4 ns72 0 -0.000664932679013 +Gc2_73 0 n4 ns73 0 0.00112848183467 +Gc2_74 0 n4 ns74 0 -0.00154438143256 +Gc2_75 0 n4 ns75 0 -0.000887686816833 +Gc2_76 0 n4 ns76 0 0.00172436232561 +Gc2_77 0 n4 ns77 0 -0.000828756505606 +Gc2_78 0 n4 ns78 0 5.22466841431e-007 +Gc2_79 0 n4 ns79 0 -2.58281180459e-006 +Gc2_80 0 n4 ns80 0 3.4968280464e-007 +Gc2_81 0 n4 ns81 0 7.5401752884e-007 +Gc2_82 0 n4 ns82 0 9.06864085391e-006 +Gc2_83 0 n4 ns83 0 -6.4392990579e-006 +Gc2_84 0 n4 ns84 0 -0.000364759597856 +Gc2_85 0 n4 ns85 0 0.000274569971958 +Gc2_86 0 n4 ns86 0 -0.00193575558354 +Gc2_87 0 n4 ns87 0 -0.00143406947879 +Gc2_88 0 n4 ns88 0 -0.00654243600983 +Gc2_89 0 n4 ns89 0 1.12230043045e-005 +Gc2_90 0 n4 ns90 0 4.77068328829e-005 +Gc2_91 0 n4 ns91 0 0.00236420207227 +Gc2_92 0 n4 ns92 0 0.00512410544802 +Gc2_93 0 n4 ns93 0 0.005066465183 +Gc2_94 0 n4 ns94 0 9.03822717111e-009 +Gc2_95 0 n4 ns95 0 -6.9845615045e-008 +Gc2_96 0 n4 ns96 0 -9.44232835135e-006 +Gc2_97 0 n4 ns97 0 1.17377309735e-005 +Gc2_98 0 n4 ns98 0 2.74086273378e-005 +Gc2_99 0 n4 ns99 0 3.03685650478e-007 +Gc2_100 0 n4 ns100 0 -9.14258791431e-007 +Gc2_101 0 n4 ns101 0 0.000110996853942 +Gc2_102 0 n4 ns102 0 0.000315220662166 +Gc2_103 0 n4 ns103 0 0.00168956037242 +Gc2_104 0 n4 ns104 0 -0.000707124027483 +Gc2_105 0 n4 ns105 0 -0.00177886475396 +Gc2_106 0 n4 ns106 0 0.00092309827067 +Gc2_107 0 n4 ns107 0 1.1673869745e-006 +Gc2_108 0 n4 ns108 0 3.32788656705e-006 +Gc2_109 0 n4 ns109 0 -4.6436859102e-007 +Gc2_110 0 n4 ns110 0 -6.99328585671e-007 +Gc2_111 0 n4 ns111 0 -1.66482638528e-005 +Gc2_112 0 n4 ns112 0 1.30571642248e-005 +Gc2_113 0 n4 ns113 0 -0.000555194048036 +Gc2_114 0 n4 ns114 0 0.000669896513713 +Gc2_115 0 n4 ns115 0 -0.00116918213314 +Gc2_116 0 n4 ns116 0 -0.00203019399495 +Gc2_117 0 n4 ns117 0 -0.00658984058792 +Gc2_118 0 n4 ns118 0 -3.25849820513e-005 +Gc2_119 0 n4 ns119 0 3.26310731749e-006 +Gc2_120 0 n4 ns120 0 -0.00269180127049 +Gc2_121 0 n4 ns121 0 -0.0112297271986 +Gc2_122 0 n4 ns122 0 -0.00282077402339 +Gc2_123 0 n4 ns123 0 1.18703444964e-007 +Gc2_124 0 n4 ns124 0 -1.35068113147e-008 +Gc2_125 0 n4 ns125 0 1.99812877594e-005 +Gc2_126 0 n4 ns126 0 2.94209938517e-005 +Gc2_127 0 n4 ns127 0 0.000139923596749 +Gc2_128 0 n4 ns128 0 8.79402830487e-007 +Gc2_129 0 n4 ns129 0 3.8479967014e-007 +Gc2_130 0 n4 ns130 0 -0.000390771407817 +Gc2_131 0 n4 ns131 0 0.000160898654709 +Gc2_132 0 n4 ns132 0 -0.00292966184635 +Gc2_133 0 n4 ns133 0 0.00080689285805 +Gc2_134 0 n4 ns134 0 -0.00202930447999 +Gc2_135 0 n4 ns135 0 0.00103137546958 +Gc2_136 0 n4 ns136 0 -2.34983489886e-006 +Gc2_137 0 n4 ns137 0 2.55450304724e-006 +Gc2_138 0 n4 ns138 0 1.6303175924e-006 +Gc2_139 0 n4 ns139 0 6.80146210634e-008 +Gc2_140 0 n4 ns140 0 -5.46226615179e-005 +Gc2_141 0 n4 ns141 0 -5.54523385373e-005 +Gc2_142 0 n4 ns142 0 -0.000657380014889 +Gc2_143 0 n4 ns143 0 -0.00160522402702 +Gc2_144 0 n4 ns144 0 -0.00842002548034 +Gc2_145 0 n4 ns145 0 -0.00741748662202 +Gc2_146 0 n4 ns146 0 -0.00656918618343 +Gc2_147 0 n4 ns147 0 8.53221521144e-006 +Gc2_148 0 n4 ns148 0 6.81530045313e-005 +Gc2_149 0 n4 ns149 0 0.00177936075877 +Gc2_150 0 n4 ns150 0 0.00515355372572 +Gc2_151 0 n4 ns151 0 0.00134009729207 +Gc2_152 0 n4 ns152 0 -1.39643053332e-007 +Gc2_153 0 n4 ns153 0 -3.86917479217e-008 +Gc2_154 0 n4 ns154 0 -2.19577647715e-005 +Gc2_155 0 n4 ns155 0 -1.78753194437e-005 +Gc2_156 0 n4 ns156 0 0.000109566954227 +Gc2_157 0 n4 ns157 0 2.55493847852e-007 +Gc2_158 0 n4 ns158 0 -7.17432373032e-007 +Gc2_159 0 n4 ns159 0 0.000336598677524 +Gc2_160 0 n4 ns160 0 -0.000812961855485 +Gc2_161 0 n4 ns161 0 0.00102235921076 +Gc2_162 0 n4 ns162 0 0.000684514231853 +Gc2_163 0 n4 ns163 0 -0.00173197903509 +Gc2_164 0 n4 ns164 0 0.00088067741833 +Gc2_165 0 n4 ns165 0 2.96084931551e-007 +Gc2_166 0 n4 ns166 0 1.93540888386e-006 +Gc2_167 0 n4 ns167 0 -6.30366084142e-007 +Gc2_168 0 n4 ns168 0 -3.84544444159e-007 +Gc2_169 0 n4 ns169 0 -1.40526448653e-006 +Gc2_170 0 n4 ns170 0 3.16347303302e-005 +Gc2_171 0 n4 ns171 0 -0.000740383703934 +Gc2_172 0 n4 ns172 0 0.00082391084512 +Gc2_173 0 n4 ns173 0 0.000468132731839 +Gc2_174 0 n4 ns174 0 -0.00125016591196 +Gd2_1 0 n4 ni1 0 -0.000918472812112 +Gd2_2 0 n4 ni2 0 0.00118526866842 +Gd2_3 0 n4 ni3 0 -0.00116307878152 +Gd2_4 0 n4 ni4 0 -0.000735114878269 +Gd2_5 0 n4 ni5 0 -0.00511663837138 +Gd2_6 0 n4 ni6 0 -0.000114891271867 +Gc3_1 0 n6 ns1 0 0.00654877583362 +Gc3_2 0 n6 ns2 0 -9.82995985442e-006 +Gc3_3 0 n6 ns3 0 -5.9548101652e-005 +Gc3_4 0 n6 ns4 0 -0.00204417259396 +Gc3_5 0 n6 ns5 0 -0.00511121037729 +Gc3_6 0 n6 ns6 0 -0.00273600505431 +Gc3_7 0 n6 ns7 0 9.2723272527e-008 +Gc3_8 0 n6 ns8 0 6.24434732677e-008 +Gc3_9 0 n6 ns9 0 1.35871913021e-005 +Gc3_10 0 n6 ns10 0 -2.36907583536e-006 +Gc3_11 0 n6 ns11 0 -4.40687946929e-005 +Gc3_12 0 n6 ns12 0 4.62715222124e-007 +Gc3_13 0 n6 ns13 0 1.95501642467e-007 +Gc3_14 0 n6 ns14 0 -0.00260128953997 +Gc3_15 0 n6 ns15 0 -6.08077587874e-005 +Gc3_16 0 n6 ns16 0 0.000653243694914 +Gc3_17 0 n6 ns17 0 0.000362656472094 +Gc3_18 0 n6 ns18 0 0.00155182345721 +Gc3_19 0 n6 ns19 0 -0.000920656634655 +Gc3_20 0 n6 ns20 0 4.71809140753e-007 +Gc3_21 0 n6 ns21 0 -1.28753380209e-006 +Gc3_22 0 n6 ns22 0 2.96353316177e-007 +Gc3_23 0 n6 ns23 0 5.94911695677e-007 +Gc3_24 0 n6 ns24 0 1.16757012728e-005 +Gc3_25 0 n6 ns25 0 -1.69539364648e-006 +Gc3_26 0 n6 ns26 0 -0.000364197876465 +Gc3_27 0 n6 ns27 0 0.000571951008085 +Gc3_28 0 n6 ns28 0 -0.00131768321326 +Gc3_29 0 n6 ns29 0 -0.00127740125116 +Gc3_30 0 n6 ns30 0 0.00656046169265 +Gc3_31 0 n6 ns31 0 -8.58388925881e-006 +Gc3_32 0 n6 ns32 0 -6.86762140625e-005 +Gc3_33 0 n6 ns33 0 -0.00186261856351 +Gc3_34 0 n6 ns34 0 -0.00513946472351 +Gc3_35 0 n6 ns35 0 -0.00162717374178 +Gc3_36 0 n6 ns36 0 1.40487023382e-007 +Gc3_37 0 n6 ns37 0 6.05752028477e-008 +Gc3_38 0 n6 ns38 0 1.90217881445e-005 +Gc3_39 0 n6 ns39 0 8.52692654013e-006 +Gc3_40 0 n6 ns40 0 -8.44883714095e-005 +Gc3_41 0 n6 ns41 0 3.8401998878e-007 +Gc3_42 0 n6 ns42 0 1.93645929967e-007 +Gc3_43 0 n6 ns43 0 -0.000606520969421 +Gc3_44 0 n6 ns44 0 0.00108012744236 +Gc3_45 0 n6 ns45 0 -0.00159322306954 +Gc3_46 0 n6 ns46 0 -0.000811522889381 +Gc3_47 0 n6 ns47 0 0.00170686654964 +Gc3_48 0 n6 ns48 0 -0.000834718050684 +Gc3_49 0 n6 ns49 0 1.22653926592e-006 +Gc3_50 0 n6 ns50 0 -2.29439958819e-006 +Gc3_51 0 n6 ns51 0 2.17116790731e-007 +Gc3_52 0 n6 ns52 0 6.89953655009e-007 +Gc3_53 0 n6 ns53 0 1.04207818949e-005 +Gc3_54 0 n6 ns54 0 -6.80323100807e-006 +Gc3_55 0 n6 ns55 0 -0.000322805950757 +Gc3_56 0 n6 ns56 0 0.000284021948559 +Gc3_57 0 n6 ns57 0 -0.00200156754029 +Gc3_58 0 n6 ns58 0 -0.00159871551561 +Gc3_59 0 n6 ns59 0 0.00661501202533 +Gc3_60 0 n6 ns60 0 2.17868271898e-005 +Gc3_61 0 n6 ns61 0 3.16374582636e-005 +Gc3_62 0 n6 ns62 0 0.00319414631716 +Gc3_63 0 n6 ns63 0 0.0111069281359 +Gc3_64 0 n6 ns64 0 0.00429903608039 +Gc3_65 0 n6 ns65 0 4.72643758352e-007 +Gc3_66 0 n6 ns66 0 1.26418529585e-007 +Gc3_67 0 n6 ns67 0 5.37101610074e-005 +Gc3_68 0 n6 ns68 0 3.74556347813e-005 +Gc3_69 0 n6 ns69 0 -0.000604516024561 +Gc3_70 0 n6 ns70 0 3.88416138093e-007 +Gc3_71 0 n6 ns71 0 6.66226528475e-007 +Gc3_72 0 n6 ns72 0 0.0037575030938 +Gc3_73 0 n6 ns73 0 -0.00140437149642 +Gc3_74 0 n6 ns74 0 0.00102344399545 +Gc3_75 0 n6 ns75 0 0.000493136107386 +Gc3_76 0 n6 ns76 0 0.00139131156943 +Gc3_77 0 n6 ns77 0 -0.000733113310636 +Gc3_78 0 n6 ns78 0 6.44822821003e-007 +Gc3_79 0 n6 ns79 0 -1.49386358999e-006 +Gc3_80 0 n6 ns80 0 -7.58599709875e-007 +Gc3_81 0 n6 ns81 0 4.29704975442e-007 +Gc3_82 0 n6 ns82 0 8.9910338101e-005 +Gc3_83 0 n6 ns83 0 4.24696863768e-005 +Gc3_84 0 n6 ns84 0 0.00299696726425 +Gc3_85 0 n6 ns85 0 3.52486261281e-006 +Gc3_86 0 n6 ns86 0 0.0051170763388 +Gc3_87 0 n6 ns87 0 0.038892170466 +Gc3_88 0 n6 ns88 0 -0.00655179122522 +Gc3_89 0 n6 ns89 0 9.94042337583e-006 +Gc3_90 0 n6 ns90 0 5.46342662664e-005 +Gc3_91 0 n6 ns91 0 0.00211497688393 +Gc3_92 0 n6 ns92 0 0.00503997693834 +Gc3_93 0 n6 ns93 0 0.00282640686372 +Gc3_94 0 n6 ns94 0 -7.31585753869e-008 +Gc3_95 0 n6 ns95 0 -6.80838232221e-008 +Gc3_96 0 n6 ns96 0 -1.6454862552e-005 +Gc3_97 0 n6 ns97 0 -6.68574780792e-007 +Gc3_98 0 n6 ns98 0 5.77019530155e-005 +Gc3_99 0 n6 ns99 0 2.97078319719e-007 +Gc3_100 0 n6 ns100 0 -7.84140250237e-007 +Gc3_101 0 n6 ns101 0 0.00142507962182 +Gc3_102 0 n6 ns102 0 7.2097464337e-005 +Gc3_103 0 n6 ns103 0 -0.00045116369243 +Gc3_104 0 n6 ns104 0 -0.000187572568707 +Gc3_105 0 n6 ns105 0 -0.00143511547672 +Gc3_106 0 n6 ns106 0 0.000851426918929 +Gc3_107 0 n6 ns107 0 -1.36912413823e-006 +Gc3_108 0 n6 ns108 0 1.60313463756e-006 +Gc3_109 0 n6 ns109 0 -1.04816487281e-006 +Gc3_110 0 n6 ns110 0 -1.04886527496e-006 +Gc3_111 0 n6 ns111 0 -8.0315677853e-006 +Gc3_112 0 n6 ns112 0 1.78352758855e-005 +Gc3_113 0 n6 ns113 0 -0.000539846704182 +Gc3_114 0 n6 ns114 0 0.000655364233187 +Gc3_115 0 n6 ns115 0 -0.000788319468627 +Gc3_116 0 n6 ns116 0 -0.00210052295817 +Gc3_117 0 n6 ns117 0 -0.00656180276976 +Gc3_118 0 n6 ns118 0 8.54266210639e-006 +Gc3_119 0 n6 ns119 0 6.32678775631e-005 +Gc3_120 0 n6 ns120 0 0.00199151423814 +Gc3_121 0 n6 ns121 0 0.00504439947613 +Gc3_122 0 n6 ns122 0 0.00188282459896 +Gc3_123 0 n6 ns123 0 -1.14026737641e-007 +Gc3_124 0 n6 ns124 0 -5.84976185595e-008 +Gc3_125 0 n6 ns125 0 -2.03222744734e-005 +Gc3_126 0 n6 ns126 0 -8.92156166991e-006 +Gc3_127 0 n6 ns127 0 8.97861696684e-005 +Gc3_128 0 n6 ns128 0 2.27743777256e-007 +Gc3_129 0 n6 ns129 0 -7.38452347773e-007 +Gc3_130 0 n6 ns130 0 0.00045441850344 +Gc3_131 0 n6 ns131 0 -0.000925926413816 +Gc3_132 0 n6 ns132 0 0.00125447534819 +Gc3_133 0 n6 ns133 0 0.000588048767761 +Gc3_134 0 n6 ns134 0 -0.00165237534113 +Gc3_135 0 n6 ns135 0 0.000893836291824 +Gc3_136 0 n6 ns136 0 -1.39297285626e-006 +Gc3_137 0 n6 ns137 0 2.66024304389e-006 +Gc3_138 0 n6 ns138 0 -8.00277060736e-007 +Gc3_139 0 n6 ns139 0 -7.32222243945e-007 +Gc3_140 0 n6 ns140 0 -7.2763343532e-006 +Gc3_141 0 n6 ns141 0 2.25767182204e-005 +Gc3_142 0 n6 ns142 0 -0.000433968950208 +Gc3_143 0 n6 ns143 0 0.000731152956492 +Gc3_144 0 n6 ns144 0 -0.00106239390796 +Gc3_145 0 n6 ns145 0 -0.00216202099351 +Gc3_146 0 n6 ns146 0 -0.0065998981036 +Gc3_147 0 n6 ns147 0 -3.64680655531e-005 +Gc3_148 0 n6 ns148 0 7.68660802436e-006 +Gc3_149 0 n6 ns149 0 -0.00319401422312 +Gc3_150 0 n6 ns150 0 -0.010745011545 +Gc3_151 0 n6 ns151 0 -0.00287690968702 +Gc3_152 0 n6 ns152 0 3.14563799805e-009 +Gc3_153 0 n6 ns153 0 -1.19413579077e-008 +Gc3_154 0 n6 ns154 0 1.27930011156e-005 +Gc3_155 0 n6 ns155 0 8.66917966108e-006 +Gc3_156 0 n6 ns156 0 0.000225742301804 +Gc3_157 0 n6 ns157 0 9.88031564539e-007 +Gc3_158 0 n6 ns158 0 4.4936994293e-007 +Gc3_159 0 n6 ns159 0 -0.00273023448608 +Gc3_160 0 n6 ns160 0 0.00124547758465 +Gc3_161 0 n6 ns161 0 -0.000475781348236 +Gc3_162 0 n6 ns162 0 -0.000519443541304 +Gc3_163 0 n6 ns163 0 -0.00136731624109 +Gc3_164 0 n6 ns164 0 0.000809383244023 +Gc3_165 0 n6 ns165 0 -3.91825105911e-006 +Gc3_166 0 n6 ns166 0 2.93620835527e-006 +Gc3_167 0 n6 ns167 0 1.51374145803e-006 +Gc3_168 0 n6 ns168 0 -3.86854190052e-007 +Gc3_169 0 n6 ns169 0 -5.43373147956e-005 +Gc3_170 0 n6 ns170 0 -3.29254893679e-005 +Gc3_171 0 n6 ns171 0 -0.000539615617754 +Gc3_172 0 n6 ns172 0 -0.00170572373728 +Gc3_173 0 n6 ns173 0 -0.00784432250667 +Gc3_174 0 n6 ns174 0 -0.0060979044298 +Gd3_1 0 n6 ni1 0 -0.000864134471809 +Gd3_2 0 n6 ni2 0 -0.00115197614632 +Gd3_3 0 n6 ni3 0 0.00169581424972 +Gd3_4 0 n6 ni4 0 -0.000627009791825 +Gd3_5 0 n6 ni5 0 -0.00057299230166 +Gd3_6 0 n6 ni6 0 -0.00462275924945 +Gc4_1 0 n8 ns1 0 -0.00661935603375 +Gc4_2 0 n8 ns2 0 -2.9157044366e-005 +Gc4_3 0 n8 ns3 0 -2.60401351849e-005 +Gc4_4 0 n8 ns4 0 -0.00142035338812 +Gc4_5 0 n8 ns5 0 -0.0119432623749 +Gc4_6 0 n8 ns6 0 -0.000305194939189 +Gc4_7 0 n8 ns7 0 5.49993131445e-007 +Gc4_8 0 n8 ns8 0 5.29347742888e-008 +Gc4_9 0 n8 ns9 0 4.51379897976e-005 +Gc4_10 0 n8 ns10 0 8.19413672443e-005 +Gc4_11 0 n8 ns11 0 -6.43202530426e-006 +Gc4_12 0 n8 ns12 0 1.47116879008e-006 +Gc4_13 0 n8 ns13 0 -1.30874443125e-007 +Gc4_14 0 n8 ns14 0 -0.000840341189241 +Gc4_15 0 n8 ns15 0 -0.000677165405683 +Gc4_16 0 n8 ns16 0 -0.00133012236336 +Gc4_17 0 n8 ns17 0 0.00089531279406 +Gc4_18 0 n8 ns18 0 -0.00161855691073 +Gc4_19 0 n8 ns19 0 0.00103263659073 +Gc4_20 0 n8 ns20 0 -4.55012244455e-007 +Gc4_21 0 n8 ns21 0 3.207610817e-006 +Gc4_22 0 n8 ns22 0 1.42574007507e-006 +Gc4_23 0 n8 ns23 0 2.18139199582e-007 +Gc4_24 0 n8 ns24 0 -2.42478162206e-005 +Gc4_25 0 n8 ns25 0 -5.00998892232e-005 +Gc4_26 0 n8 ns26 0 -0.000250057413873 +Gc4_27 0 n8 ns27 0 -0.00209097939107 +Gc4_28 0 n8 ns28 0 -0.00826151722019 +Gc4_29 0 n8 ns29 0 -0.00566083830821 +Gc4_30 0 n8 ns30 0 -0.00654631821036 +Gc4_31 0 n8 ns31 0 1.25190635957e-005 +Gc4_32 0 n8 ns32 0 4.03579000786e-005 +Gc4_33 0 n8 ns33 0 0.00272686033825 +Gc4_34 0 n8 ns34 0 0.00494483798911 +Gc4_35 0 n8 ns35 0 0.00611021800561 +Gc4_36 0 n8 ns36 0 3.99304953337e-008 +Gc4_37 0 n8 ns37 0 -1.03422395329e-007 +Gc4_38 0 n8 ns38 0 -1.83985179566e-006 +Gc4_39 0 n8 ns39 0 3.22756688355e-005 +Gc4_40 0 n8 ns40 0 -2.0263779387e-005 +Gc4_41 0 n8 ns41 0 3.66087329912e-007 +Gc4_42 0 n8 ns42 0 -1.08567040036e-006 +Gc4_43 0 n8 ns43 0 0.000160173466799 +Gc4_44 0 n8 ns44 0 0.000239560085267 +Gc4_45 0 n8 ns45 0 0.00166177613633 +Gc4_46 0 n8 ns46 0 -0.000602170263463 +Gc4_47 0 n8 ns47 0 -0.0017971226411 +Gc4_48 0 n8 ns48 0 0.000924319173881 +Gc4_49 0 n8 ns49 0 2.09809004478e-006 +Gc4_50 0 n8 ns50 0 3.24451952703e-006 +Gc4_51 0 n8 ns51 0 -5.67044582371e-007 +Gc4_52 0 n8 ns52 0 -7.23730536424e-007 +Gc4_53 0 n8 ns53 0 -1.74279740873e-005 +Gc4_54 0 n8 ns54 0 9.38226566834e-006 +Gc4_55 0 n8 ns55 0 -0.000520817708248 +Gc4_56 0 n8 ns56 0 0.000547042309352 +Gc4_57 0 n8 ns57 0 -0.00182249338773 +Gc4_58 0 n8 ns58 0 -0.0024245498871 +Gc4_59 0 n8 ns59 0 -0.00655444055198 +Gc4_60 0 n8 ns60 0 1.10816869337e-005 +Gc4_61 0 n8 ns61 0 4.82230892983e-005 +Gc4_62 0 n8 ns62 0 0.0024205233767 +Gc4_63 0 n8 ns63 0 0.0048870821874 +Gc4_64 0 n8 ns64 0 0.00369609475451 +Gc4_65 0 n8 ns65 0 -6.43623458731e-008 +Gc4_66 0 n8 ns66 0 -9.85040585935e-008 +Gc4_67 0 n8 ns67 0 -1.08539967157e-005 +Gc4_68 0 n8 ns68 0 1.65938469654e-005 +Gc4_69 0 n8 ns69 0 1.92640197547e-005 +Gc4_70 0 n8 ns70 0 3.42469157849e-007 +Gc4_71 0 n8 ns71 0 -9.41185303177e-007 +Gc4_72 0 n8 ns72 0 0.00145402835678 +Gc4_73 0 n8 ns73 0 6.60446622679e-007 +Gc4_74 0 n8 ns74 0 -0.000456894508342 +Gc4_75 0 n8 ns75 0 -9.40750445754e-005 +Gc4_76 0 n8 ns76 0 -0.00144999620163 +Gc4_77 0 n8 ns77 0 0.000854386825313 +Gc4_78 0 n8 ns78 0 -3.36052802435e-007 +Gc4_79 0 n8 ns79 0 1.44113502754e-006 +Gc4_80 0 n8 ns80 0 -9.85809365562e-007 +Gc4_81 0 n8 ns81 0 -8.40998791682e-007 +Gc4_82 0 n8 ns82 0 -7.65354047787e-006 +Gc4_83 0 n8 ns83 0 1.27161581193e-005 +Gc4_84 0 n8 ns84 0 -0.00050395731326 +Gc4_85 0 n8 ns85 0 0.000525627999515 +Gc4_86 0 n8 ns86 0 -0.00147290713106 +Gc4_87 0 n8 ns87 0 -0.00249173038053 +Gc4_88 0 n8 ns88 0 0.00658629838527 +Gc4_89 0 n8 ns89 0 2.42809306037e-005 +Gc4_90 0 n8 ns90 0 -1.54924714269e-007 +Gc4_91 0 n8 ns91 0 0.00387673624565 +Gc4_92 0 n8 ns92 0 0.0109184742736 +Gc4_93 0 n8 ns93 0 0.00835760129991 +Gc4_94 0 n8 ns94 0 3.15626498621e-007 +Gc4_95 0 n8 ns95 0 9.41813305728e-008 +Gc4_96 0 n8 ns96 0 7.53047309472e-005 +Gc4_97 0 n8 ns97 0 6.36585470442e-005 +Gc4_98 0 n8 ns98 0 -0.000624252315511 +Gc4_99 0 n8 ns99 0 1.5470503257e-007 +Gc4_100 0 n8 ns100 0 4.03343299475e-007 +Gc4_101 0 n8 ns101 0 0.000751123531494 +Gc4_102 0 n8 ns102 0 0.0003522906111 +Gc4_103 0 n8 ns103 0 0.000639781343684 +Gc4_104 0 n8 ns104 0 -0.000342848995999 +Gc4_105 0 n8 ns105 0 0.00138721643733 +Gc4_106 0 n8 ns106 0 -0.000958734883284 +Gc4_107 0 n8 ns107 0 2.97977463302e-006 +Gc4_108 0 n8 ns108 0 8.95735320212e-007 +Gc4_109 0 n8 ns109 0 -1.44096019306e-006 +Gc4_110 0 n8 ns110 0 -1.16911447713e-006 +Gc4_111 0 n8 ns111 0 5.91020629162e-005 +Gc4_112 0 n8 ns112 0 5.63111605714e-005 +Gc4_113 0 n8 ns113 0 0.00239511260744 +Gc4_114 0 n8 ns114 0 0.000810562219815 +Gc4_115 0 n8 ns115 0 0.0129552359623 +Gc4_116 0 n8 ns116 0 0.0430960066706 +Gc4_117 0 n8 ns117 0 0.00655003449331 +Gc4_118 0 n8 ns118 0 -1.14651489608e-005 +Gc4_119 0 n8 ns119 0 -4.35707545803e-005 +Gc4_120 0 n8 ns120 0 -0.00249938900406 +Gc4_121 0 n8 ns121 0 -0.00504047188827 +Gc4_122 0 n8 ns122 0 -0.00544633362465 +Gc4_123 0 n8 ns123 0 2.62304464995e-008 +Gc4_124 0 n8 ns124 0 1.0242078471e-007 +Gc4_125 0 n8 ns125 0 5.39280921633e-006 +Gc4_126 0 n8 ns126 0 -1.8800347225e-005 +Gc4_127 0 n8 ns127 0 -4.07664749265e-006 +Gc4_128 0 n8 ns128 0 4.15837855136e-008 +Gc4_129 0 n8 ns129 0 8.38079435185e-007 +Gc4_130 0 n8 ns130 0 -0.000108508873842 +Gc4_131 0 n8 ns131 0 -0.000140597742 +Gc4_132 0 n8 ns132 0 -0.00112316575397 +Gc4_133 0 n8 ns133 0 0.000436746515481 +Gc4_134 0 n8 ns134 0 0.00173070662277 +Gc4_135 0 n8 ns135 0 -0.000942363994662 +Gc4_136 0 n8 ns136 0 -2.77594243753e-006 +Gc4_137 0 n8 ns137 0 -2.63181417954e-006 +Gc4_138 0 n8 ns138 0 2.43461587302e-007 +Gc4_139 0 n8 ns139 0 5.19029023417e-007 +Gc4_140 0 n8 ns140 0 2.12198271061e-005 +Gc4_141 0 n8 ns141 0 1.41083801409e-005 +Gc4_142 0 n8 ns142 0 -0.000143464734767 +Gc4_143 0 n8 ns143 0 0.000508040479835 +Gc4_144 0 n8 ns144 0 -0.00413058959571 +Gc4_145 0 n8 ns145 0 -0.00402163445861 +Gc4_146 0 n8 ns146 0 0.00655843454693 +Gc4_147 0 n8 ns147 0 -9.95767397207e-006 +Gc4_148 0 n8 ns148 0 -5.26869027407e-005 +Gc4_149 0 n8 ns149 0 -0.00210464889448 +Gc4_150 0 n8 ns150 0 -0.00503794728743 +Gc4_151 0 n8 ns151 0 -0.00278632473295 +Gc4_152 0 n8 ns152 0 1.44034008144e-007 +Gc4_153 0 n8 ns153 0 9.04884969056e-008 +Gc4_154 0 n8 ns154 0 1.58120522557e-005 +Gc4_155 0 n8 ns155 0 1.76386812489e-007 +Gc4_156 0 n8 ns156 0 -5.18163403655e-005 +Gc4_157 0 n8 ns157 0 3.72247011152e-007 +Gc4_158 0 n8 ns158 0 5.76125821844e-007 +Gc4_159 0 n8 ns159 0 -0.00103627530594 +Gc4_160 0 n8 ns160 0 -1.05646016323e-005 +Gc4_161 0 n8 ns161 0 0.000293754514836 +Gc4_162 0 n8 ns162 0 0.000186603057562 +Gc4_163 0 n8 ns163 0 0.00142096154108 +Gc4_164 0 n8 ns164 0 -0.000849872534369 +Gc4_165 0 n8 ns165 0 -1.06485553281e-006 +Gc4_166 0 n8 ns166 0 -1.69462383664e-006 +Gc4_167 0 n8 ns167 0 -1.89657603083e-008 +Gc4_168 0 n8 ns168 0 1.01493131613e-007 +Gc4_169 0 n8 ns169 0 2.68399231513e-005 +Gc4_170 0 n8 ns170 0 2.99277050834e-005 +Gc4_171 0 n8 ns171 0 -7.63409614502e-005 +Gc4_172 0 n8 ns172 0 0.000952784876263 +Gc4_173 0 n8 ns173 0 -0.00483255175348 +Gc4_174 0 n8 ns174 0 -0.00510469838193 +Gd4_1 0 n8 ni1 0 -0.0044740587263 +Gd4_2 0 n8 ni2 0 -0.00103060655993 +Gd4_3 0 n8 ni3 0 -0.000937860296935 +Gd4_4 0 n8 ni4 0 0.00418944581273 +Gd4_5 0 n8 ni5 0 -0.001464062462 +Gd4_6 0 n8 ni6 0 -0.00179209937781 +Gc5_1 0 n10 ns1 0 -0.00653789704045 +Gc5_2 0 n10 ns2 0 9.9343064388e-006 +Gc5_3 0 n10 ns3 0 5.67824577986e-005 +Gc5_4 0 n10 ns4 0 0.00199271689871 +Gc5_5 0 n10 ns5 0 0.00532933994365 +Gc5_6 0 n10 ns6 0 0.00410475640631 +Gc5_7 0 n10 ns7 0 -1.37006028863e-007 +Gc5_8 0 n10 ns8 0 -1.01439054346e-007 +Gc5_9 0 n10 ns9 0 -1.43701451746e-005 +Gc5_10 0 n10 ns10 0 4.55201674106e-007 +Gc5_11 0 n10 ns11 0 5.63555934401e-005 +Gc5_12 0 n10 ns12 0 1.18823875735e-007 +Gc5_13 0 n10 ns13 0 -8.50081590461e-007 +Gc5_14 0 n10 ns14 0 -5.96795566272e-005 +Gc5_15 0 n10 ns15 0 0.000455741515972 +Gc5_16 0 n10 ns16 0 0.00165507499978 +Gc5_17 0 n10 ns17 0 -0.000826710045862 +Gc5_18 0 n10 ns18 0 -0.00185648919695 +Gc5_19 0 n10 ns19 0 0.00107818606743 +Gc5_20 0 n10 ns20 0 6.31873781767e-007 +Gc5_21 0 n10 ns21 0 2.71286155491e-006 +Gc5_22 0 n10 ns22 0 -5.43882306958e-007 +Gc5_23 0 n10 ns23 0 -6.33091412948e-007 +Gc5_24 0 n10 ns24 0 -1.41577770661e-005 +Gc5_25 0 n10 ns25 0 1.50841875475e-005 +Gc5_26 0 n10 ns26 0 -0.000639379159769 +Gc5_27 0 n10 ns27 0 0.000569138021838 +Gc5_28 0 n10 ns28 0 -0.000301933931908 +Gc5_29 0 n10 ns29 0 -0.00143511354101 +Gc5_30 0 n10 ns30 0 -0.00660357088991 +Gc5_31 0 n10 ns31 0 -2.87126522566e-005 +Gc5_32 0 n10 ns32 0 -1.46707441771e-005 +Gc5_33 0 n10 ns33 0 -0.00184328755225 +Gc5_34 0 n10 ns34 0 -0.0116805351162 +Gc5_35 0 n10 ns35 0 -0.000429204559759 +Gc5_36 0 n10 ns36 0 4.18135134919e-007 +Gc5_37 0 n10 ns37 0 2.49068185516e-008 +Gc5_38 0 n10 ns38 0 4.13699394005e-005 +Gc5_39 0 n10 ns39 0 6.28624453471e-005 +Gc5_40 0 n10 ns40 0 4.09313139369e-005 +Gc5_41 0 n10 ns41 0 1.09385457912e-006 +Gc5_42 0 n10 ns42 0 3.93682947329e-008 +Gc5_43 0 n10 ns43 0 -0.000203239018633 +Gc5_44 0 n10 ns44 0 4.91658612395e-005 +Gc5_45 0 n10 ns45 0 -0.00310470530437 +Gc5_46 0 n10 ns46 0 0.000999391236546 +Gc5_47 0 n10 ns47 0 -0.00207089299626 +Gc5_48 0 n10 ns48 0 0.00100035253648 +Gc5_49 0 n10 ns49 0 -2.70200790277e-007 +Gc5_50 0 n10 ns50 0 3.90800186021e-006 +Gc5_51 0 n10 ns51 0 1.33240759491e-006 +Gc5_52 0 n10 ns52 0 -2.20106903496e-007 +Gc5_53 0 n10 ns53 0 -4.93331575552e-005 +Gc5_54 0 n10 ns54 0 -5.25684574611e-005 +Gc5_55 0 n10 ns55 0 -0.00057634389303 +Gc5_56 0 n10 ns56 0 -0.00151411838165 +Gc5_57 0 n10 ns57 0 -0.00829148343972 +Gc5_58 0 n10 ns58 0 -0.00769153668391 +Gc5_59 0 n10 ns59 0 -0.00656465438326 +Gc5_60 0 n10 ns60 0 9.49618880408e-006 +Gc5_61 0 n10 ns61 0 5.84554766817e-005 +Gc5_62 0 n10 ns62 0 0.00221079890008 +Gc5_63 0 n10 ns63 0 0.00493821138947 +Gc5_64 0 n10 ns64 0 0.00251250389301 +Gc5_65 0 n10 ns65 0 -1.23548541236e-007 +Gc5_66 0 n10 ns66 0 -9.27709340689e-008 +Gc5_67 0 n10 ns67 0 -1.58031869598e-005 +Gc5_68 0 n10 ns68 0 5.13132230598e-006 +Gc5_69 0 n10 ns69 0 6.01499404784e-005 +Gc5_70 0 n10 ns70 0 2.66980140959e-007 +Gc5_71 0 n10 ns71 0 -8.56688748273e-007 +Gc5_72 0 n10 ns72 0 0.000473056665584 +Gc5_73 0 n10 ns73 0 -0.000971587351615 +Gc5_74 0 n10 ns74 0 0.00125226865231 +Gc5_75 0 n10 ns75 0 0.000647378084243 +Gc5_76 0 n10 ns76 0 -0.0016597487886 +Gc5_77 0 n10 ns77 0 0.000898470822046 +Gc5_78 0 n10 ns78 0 -1.08973296791e-006 +Gc5_79 0 n10 ns79 0 2.43872793885e-006 +Gc5_80 0 n10 ns80 0 -8.33959277859e-007 +Gc5_81 0 n10 ns81 0 -7.06640054141e-007 +Gc5_82 0 n10 ns82 0 -7.55852689665e-006 +Gc5_83 0 n10 ns83 0 1.75380863236e-005 +Gc5_84 0 n10 ns84 0 -0.000403423494802 +Gc5_85 0 n10 ns85 0 0.000606796654645 +Gc5_86 0 n10 ns86 0 -0.00168496493202 +Gc5_87 0 n10 ns87 0 -0.00249441613894 +Gc5_88 0 n10 ns88 0 0.00653996415742 +Gc5_89 0 n10 ns89 0 -9.94072594081e-006 +Gc5_90 0 n10 ns90 0 -5.01362786262e-005 +Gc5_91 0 n10 ns91 0 -0.00213090861149 +Gc5_92 0 n10 ns92 0 -0.00522611214472 +Gc5_93 0 n10 ns93 0 -0.00438024989832 +Gc5_94 0 n10 ns94 0 1.09864553594e-007 +Gc5_95 0 n10 ns95 0 1.11119575266e-007 +Gc5_96 0 n10 ns96 0 1.49311196105e-005 +Gc5_97 0 n10 ns97 0 -1.06290179272e-006 +Gc5_98 0 n10 ns98 0 -5.26881653052e-005 +Gc5_99 0 n10 ns99 0 1.18853583859e-007 +Gc5_100 0 n10 ns100 0 7.07070062569e-007 +Gc5_101 0 n10 ns101 0 -3.85877392246e-005 +Gc5_102 0 n10 ns102 0 -0.000197741411362 +Gc5_103 0 n10 ns103 0 -0.00118254201265 +Gc5_104 0 n10 ns104 0 0.000528159219194 +Gc5_105 0 n10 ns105 0 0.00171061855514 +Gc5_106 0 n10 ns106 0 -0.000949102692945 +Gc5_107 0 n10 ns107 0 -1.78846004832e-006 +Gc5_108 0 n10 ns108 0 -2.28951847214e-006 +Gc5_109 0 n10 ns109 0 1.19758113648e-007 +Gc5_110 0 n10 ns110 0 4.26264536797e-007 +Gc5_111 0 n10 ns111 0 2.32677665843e-005 +Gc5_112 0 n10 ns112 0 1.50087458258e-005 +Gc5_113 0 n10 ns113 0 -0.000108339857128 +Gc5_114 0 n10 ns114 0 0.000502479833684 +Gc5_115 0 n10 ns115 0 -0.00429360968879 +Gc5_116 0 n10 ns116 0 -0.00424421937442 +Gc5_117 0 n10 ns117 0 0.00659585224678 +Gc5_118 0 n10 ns118 0 1.77747795503e-005 +Gc5_119 0 n10 ns119 0 2.79200974317e-005 +Gc5_120 0 n10 ns120 0 0.00236467029441 +Gc5_121 0 n10 ns121 0 0.0116507158993 +Gc5_122 0 n10 ns122 0 0.00301325461771 +Gc5_123 0 n10 ns123 0 1.52967881244e-007 +Gc5_124 0 n10 ns124 0 1.41984644672e-007 +Gc5_125 0 n10 ns125 0 2.64852310024e-005 +Gc5_126 0 n10 ns126 0 -1.65542745386e-005 +Gc5_127 0 n10 ns127 0 -0.000417023527264 +Gc5_128 0 n10 ns128 0 -2.83138040728e-007 +Gc5_129 0 n10 ns129 0 1.06990725489e-006 +Gc5_130 0 n10 ns130 0 -1.8625531766e-005 +Gc5_131 0 n10 ns131 0 8.66498703969e-005 +Gc5_132 0 n10 ns132 0 0.00232722926999 +Gc5_133 0 n10 ns133 0 -0.00097268411754 +Gc5_134 0 n10 ns134 0 0.00202407271114 +Gc5_135 0 n10 ns135 0 -0.000998883952134 +Gc5_136 0 n10 ns136 0 -2.30607015211e-006 +Gc5_137 0 n10 ns137 0 -3.40420967549e-006 +Gc5_138 0 n10 ns138 0 3.80257021386e-007 +Gc5_139 0 n10 ns139 0 7.03264081404e-007 +Gc5_140 0 n10 ns140 0 5.68158109308e-005 +Gc5_141 0 n10 ns141 0 1.47690500311e-005 +Gc5_142 0 n10 ns142 0 0.00238629448812 +Gc5_143 0 n10 ns143 0 0.000320884297481 +Gc5_144 0 n10 ns144 0 0.0120257266957 +Gc5_145 0 n10 ns145 0 0.0454670577211 +Gc5_146 0 n10 ns146 0 0.00656856010793 +Gc5_147 0 n10 ns147 0 -8.27911685813e-006 +Gc5_148 0 n10 ns148 0 -6.35116247229e-005 +Gc5_149 0 n10 ns149 0 -0.00187177052101 +Gc5_150 0 n10 ns150 0 -0.00509228619822 +Gc5_151 0 n10 ns151 0 -0.00153876217847 +Gc5_152 0 n10 ns152 0 2.10266531117e-007 +Gc5_153 0 n10 ns153 0 8.8640519051e-008 +Gc5_154 0 n10 ns154 0 2.21701546067e-005 +Gc5_155 0 n10 ns155 0 1.29756941438e-005 +Gc5_156 0 n10 ns156 0 -9.7093891586e-005 +Gc5_157 0 n10 ns157 0 3.22486280845e-007 +Gc5_158 0 n10 ns158 0 4.2203623741e-007 +Gc5_159 0 n10 ns159 0 -0.000232807196339 +Gc5_160 0 n10 ns160 0 0.000614914118394 +Gc5_161 0 n10 ns161 0 -0.00081443165599 +Gc5_162 0 n10 ns162 0 -0.00038611915593 +Gc5_163 0 n10 ns163 0 0.0016248895886 +Gc5_164 0 n10 ns164 0 -0.000921075105072 +Gc5_165 0 n10 ns165 0 6.37565489191e-007 +Gc5_166 0 n10 ns166 0 -1.4471192707e-006 +Gc5_167 0 n10 ns167 0 -1.63132195888e-007 +Gc5_168 0 n10 ns168 0 2.33135083218e-007 +Gc5_169 0 n10 ns169 0 2.60344026242e-005 +Gc5_170 0 n10 ns170 0 2.92828750984e-005 +Gc5_171 0 n10 ns171 0 -5.66085759545e-005 +Gc5_172 0 n10 ns172 0 0.000506576116325 +Gc5_173 0 n10 ns173 0 -0.00535737987772 +Gc5_174 0 n10 ns174 0 -0.00500350650268 +Gd5_1 0 n10 ni1 0 -0.000428172694497 +Gd5_2 0 n10 ni2 0 -0.00496619859982 +Gd5_3 0 n10 ni3 0 -0.000859054773247 +Gd5_4 0 n10 ni4 0 -0.00150756710755 +Gd5_5 0 n10 ni5 0 0.00360113608662 +Gd5_6 0 n10 ni6 0 -0.00198793491318 +Gc6_1 0 n12 ns1 0 -0.00654686719405 +Gc6_2 0 n12 ns2 0 8.67141837382e-006 +Gc6_3 0 n12 ns3 0 6.32216768544e-005 +Gc6_4 0 n12 ns4 0 0.00178451970964 +Gc6_5 0 n12 ns5 0 0.00523464429179 +Gc6_6 0 n12 ns6 0 0.00196866139445 +Gc6_7 0 n12 ns7 0 -2.07376536109e-007 +Gc6_8 0 n12 ns8 0 -8.3991114267e-008 +Gc6_9 0 n12 ns9 0 -2.15013458874e-005 +Gc6_10 0 n12 ns10 0 -1.01806526772e-005 +Gc6_11 0 n12 ns11 0 8.71573514733e-005 +Gc6_12 0 n12 ns12 0 2.45377738013e-007 +Gc6_13 0 n12 ns13 0 -8.41711405273e-007 +Gc6_14 0 n12 ns14 0 0.00177232101436 +Gc6_15 0 n12 ns15 0 -0.000107188566659 +Gc6_16 0 n12 ns16 0 -0.000283784765455 +Gc6_17 0 n12 ns17 0 -0.000243178649998 +Gc6_18 0 n12 ns18 0 -0.00157519796061 +Gc6_19 0 n12 ns19 0 0.000971895486207 +Gc6_20 0 n12 ns20 0 1.1332276836e-006 +Gc6_21 0 n12 ns21 0 8.77582738005e-007 +Gc6_22 0 n12 ns22 0 -7.7427041447e-007 +Gc6_23 0 n12 ns23 0 -2.7618892326e-007 +Gc6_24 0 n12 ns24 0 -2.42581975406e-007 +Gc6_25 0 n12 ns25 0 2.38697357483e-005 +Gc6_26 0 n12 ns26 0 -0.000518753656556 +Gc6_27 0 n12 ns27 0 0.00129850103867 +Gc6_28 0 n12 ns28 0 -0.000502273102646 +Gc6_29 0 n12 ns29 0 -0.00258880539643 +Gc6_30 0 n12 ns30 0 -0.0065584020435 +Gc6_31 0 n12 ns31 0 7.41802818205e-006 +Gc6_32 0 n12 ns32 0 7.18569581229e-005 +Gc6_33 0 n12 ns33 0 0.00162077535535 +Gc6_34 0 n12 ns34 0 0.00524474573547 +Gc6_35 0 n12 ns35 0 0.000911376613989 +Gc6_36 0 n12 ns36 0 -2.59238655409e-007 +Gc6_37 0 n12 ns37 0 -7.68927832599e-008 +Gc6_38 0 n12 ns38 0 -2.66128252924e-005 +Gc6_39 0 n12 ns39 0 -2.02274957777e-005 +Gc6_40 0 n12 ns40 0 0.000124387102702 +Gc6_41 0 n12 ns41 0 2.12108455915e-007 +Gc6_42 0 n12 ns42 0 -6.94510230679e-007 +Gc6_43 0 n12 ns43 0 0.000282875353457 +Gc6_44 0 n12 ns44 0 -0.000814922037813 +Gc6_45 0 n12 ns45 0 0.00108645596547 +Gc6_46 0 n12 ns46 0 0.000667927409791 +Gc6_47 0 n12 ns47 0 -0.00172177084011 +Gc6_48 0 n12 ns48 0 0.000893671789741 +Gc6_49 0 n12 ns49 0 -1.31201777225e-007 +Gc6_50 0 n12 ns50 0 1.37492760782e-006 +Gc6_51 0 n12 ns51 0 -5.50170418912e-007 +Gc6_52 0 n12 ns52 0 -2.6281572159e-007 +Gc6_53 0 n12 ns53 0 -5.11541877294e-006 +Gc6_54 0 n12 ns54 0 2.60825845384e-005 +Gc6_55 0 n12 ns55 0 -0.000746850560463 +Gc6_56 0 n12 ns56 0 0.000683052357986 +Gc6_57 0 n12 ns57 0 -9.14822697432e-005 +Gc6_58 0 n12 ns58 0 -0.00140739274939 +Gc6_59 0 n12 ns59 0 -0.00661395653372 +Gc6_60 0 n12 ns60 0 -3.30083206697e-005 +Gc6_61 0 n12 ns61 0 -6.84725246754e-006 +Gc6_62 0 n12 ns62 0 -0.00259332048376 +Gc6_63 0 n12 ns63 0 -0.0110724565319 +Gc6_64 0 n12 ns64 0 -0.001212512078 +Gc6_65 0 n12 ns65 0 2.42304455869e-007 +Gc6_66 0 n12 ns66 0 3.95218585119e-008 +Gc6_67 0 n12 ns67 0 2.78655907402e-005 +Gc6_68 0 n12 ns68 0 3.01360344005e-005 +Gc6_69 0 n12 ns69 0 0.000159920487868 +Gc6_70 0 n12 ns70 0 1.1252827629e-006 +Gc6_71 0 n12 ns71 0 1.90189646505e-007 +Gc6_72 0 n12 ns72 0 -0.00259119386114 +Gc6_73 0 n12 ns73 0 0.0011626312334 +Gc6_74 0 n12 ns74 0 -0.000606555718753 +Gc6_75 0 n12 ns75 0 -0.000378414048296 +Gc6_76 0 n12 ns76 0 -0.00139820208542 +Gc6_77 0 n12 ns77 0 0.000785585242664 +Gc6_78 0 n12 ns78 0 -2.23768775634e-006 +Gc6_79 0 n12 ns79 0 3.8732021274e-006 +Gc6_80 0 n12 ns80 0 1.3694734804e-006 +Gc6_81 0 n12 ns81 0 -5.13728282736e-007 +Gc6_82 0 n12 ns82 0 -4.8472477172e-005 +Gc6_83 0 n12 ns83 0 -2.97584207609e-005 +Gc6_84 0 n12 ns84 0 -0.000485252983806 +Gc6_85 0 n12 ns85 0 -0.0015974152995 +Gc6_86 0 n12 ns86 0 -0.00757790501 +Gc6_87 0 n12 ns87 0 -0.00622518909109 +Gc6_88 0 n12 ns88 0 0.00654945764987 +Gc6_89 0 n12 ns89 0 -8.54717234194e-006 +Gc6_90 0 n12 ns90 0 -5.76651694194e-005 +Gc6_91 0 n12 ns91 0 -0.00186237603434 +Gc6_92 0 n12 ns92 0 -0.00515933601496 +Gc6_93 0 n12 ns93 0 -0.00208494377629 +Gc6_94 0 n12 ns94 0 1.95162671315e-007 +Gc6_95 0 n12 ns95 0 9.90069400218e-008 +Gc6_96 0 n12 ns96 0 2.21861416024e-005 +Gc6_97 0 n12 ns97 0 1.22984386269e-005 +Gc6_98 0 n12 ns98 0 -8.33278907918e-005 +Gc6_99 0 n12 ns99 0 4.30188427027e-007 +Gc6_100 0 n12 ns100 0 5.05856326967e-007 +Gc6_101 0 n12 ns101 0 -0.000987279613118 +Gc6_102 0 n12 ns102 0 -4.28131734068e-005 +Gc6_103 0 n12 ns103 0 0.000247701228445 +Gc6_104 0 n12 ns104 0 0.000242123526371 +Gc6_105 0 n12 ns105 0 0.00140894649964 +Gc6_106 0 n12 ns106 0 -0.000857715704975 +Gc6_107 0 n12 ns107 0 -4.02834493204e-007 +Gc6_108 0 n12 ns108 0 -1.35695178421e-006 +Gc6_109 0 n12 ns109 0 -9.37488066285e-008 +Gc6_110 0 n12 ns110 0 6.57705513105e-009 +Gc6_111 0 n12 ns111 0 2.86626051961e-005 +Gc6_112 0 n12 ns112 0 3.14766048061e-005 +Gc6_113 0 n12 ns113 0 -5.47473885965e-005 +Gc6_114 0 n12 ns114 0 0.000978067258305 +Gc6_115 0 n12 ns115 0 -0.00481120796141 +Gc6_116 0 n12 ns116 0 -0.00519639449642 +Gc6_117 0 n12 ns117 0 0.0065595981155 +Gc6_118 0 n12 ns118 0 -7.41189737925e-006 +Gc6_119 0 n12 ns119 0 -6.54329916661e-005 +Gc6_120 0 n12 ns120 0 -0.00177740609644 +Gc6_121 0 n12 ns121 0 -0.00513813751607 +Gc6_122 0 n12 ns122 0 -0.00126135198345 +Gc6_123 0 n12 ns123 0 2.20225807549e-007 +Gc6_124 0 n12 ns124 0 9.02944917206e-008 +Gc6_125 0 n12 ns125 0 2.46761447449e-005 +Gc6_126 0 n12 ns126 0 1.83970487453e-005 +Gc6_127 0 n12 ns127 0 -0.000109092516424 +Gc6_128 0 n12 ns128 0 3.53625977349e-007 +Gc6_129 0 n12 ns129 0 3.74646628145e-007 +Gc6_130 0 n12 ns130 0 -0.00020860250898 +Gc6_131 0 n12 ns131 0 0.000606041153262 +Gc6_132 0 n12 ns132 0 -0.000839377721772 +Gc6_133 0 n12 ns133 0 -0.00036767600545 +Gc6_134 0 n12 ns134 0 0.00162144513576 +Gc6_135 0 n12 ns135 0 -0.000926089827496 +Gc6_136 0 n12 ns136 0 9.36343326623e-007 +Gc6_137 0 n12 ns137 0 -1.23384568374e-006 +Gc6_138 0 n12 ns138 0 -1.93827325915e-007 +Gc6_139 0 n12 ns139 0 2.15547336166e-007 +Gc6_140 0 n12 ns140 0 2.73651746403e-005 +Gc6_141 0 n12 ns141 0 2.99692036691e-005 +Gc6_142 0 n12 ns142 0 -5.04657588923e-005 +Gc6_143 0 n12 ns143 0 0.000517211660872 +Gc6_144 0 n12 ns144 0 -0.00534831253567 +Gc6_145 0 n12 ns145 0 -0.0050335501205 +Gc6_146 0 n12 ns146 0 0.00660419603385 +Gc6_147 0 n12 ns147 0 2.34500696088e-005 +Gc6_148 0 n12 ns148 0 7.68849294951e-006 +Gc6_149 0 n12 ns149 0 0.00384387315189 +Gc6_150 0 n12 ns150 0 0.0106583543588 +Gc6_151 0 n12 ns151 0 0.00585948958294 +Gc6_152 0 n12 ns152 0 5.90234799299e-007 +Gc6_153 0 n12 ns153 0 1.29115381678e-007 +Gc6_154 0 n12 ns154 0 5.36433507022e-005 +Gc6_155 0 n12 ns155 0 4.66349100501e-005 +Gc6_156 0 n12 ns156 0 -0.000630038728024 +Gc6_157 0 n12 ns157 0 1.94155538e-007 +Gc6_158 0 n12 ns158 0 5.14641084718e-007 +Gc6_159 0 n12 ns159 0 0.00161576095592 +Gc6_160 0 n12 ns160 0 -0.000850436445958 +Gc6_161 0 n12 ns161 0 0.000580465611353 +Gc6_162 0 n12 ns162 0 0.000217627328972 +Gc6_163 0 n12 ns163 0 0.00140102688756 +Gc6_164 0 n12 ns164 0 -0.000759536685073 +Gc6_165 0 n12 ns165 0 -4.7906127457e-007 +Gc6_166 0 n12 ns166 0 -3.93972578266e-006 +Gc6_167 0 n12 ns167 0 2.83653495693e-007 +Gc6_168 0 n12 ns168 0 8.07316479873e-007 +Gc6_169 0 n12 ns169 0 4.32551790076e-005 +Gc6_170 0 n12 ns170 0 8.3527110974e-006 +Gc6_171 0 n12 ns171 0 0.0018887335116 +Gc6_172 0 n12 ns172 0 -0.000631214582908 +Gc6_173 0 n12 ns173 0 0.0133134852789 +Gc6_174 0 n12 ns174 0 0.0477738876148 +Gd6_1 0 n12 ni1 0 -0.000430613521014 +Gd6_2 0 n12 ni2 0 -0.000408266529117 +Gd6_3 0 n12 ni3 0 -0.0044303120728 +Gd6_4 0 n12 ni4 0 -0.00175741302334 +Gd6_5 0 n12 ni5 0 -0.00197742248958 +Gd6_6 0 n12 ni6 0 0.00337767145015 +.ends + +.subckt 744835034160 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 77213136.7445 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 1734728.75874 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 274682.273568 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 141385.594693 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 124408.774731 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 9695.38335251 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 186799.140083 +Ra8 ns8 0 186799.140083 +Ga7 ns7 0 ns8 0 -0.000220031228384 +Ga8 ns8 0 ns7 0 0.000220031228384 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 18905.464824 +Ra10 ns10 0 18905.464824 +Ga9 ns9 0 ns10 0 -0.000223102659344 +Ga10 ns10 0 ns9 0 0.000223102659344 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 21918.0164216 +Ra12 ns12 0 21918.0164216 +Ga11 ns11 0 ns12 0 -0.000225608963046 +Ga12 ns12 0 ns11 0 0.000225608963046 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 17638.8014066 +Ra14 ns14 0 17638.8014066 +Ga13 ns13 0 ns14 0 -0.000278732896707 +Ga14 ns14 0 ns13 0 0.000278732896707 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 4859.98516324 +Ra16 ns16 0 4859.98516324 +Ga15 ns15 0 ns16 0 -0.000585480963545 +Ga16 ns16 0 ns15 0 0.000585480963545 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 1754.03387431 +Ra18 ns18 0 1754.03387431 +Ga17 ns17 0 ns18 0 -0.000528555261685 +Ga18 ns18 0 ns17 0 0.000528555261685 +Ca19 ns19 0 1e-012 +Ca20 ns20 0 1e-012 +Ra19 ns19 0 10492.0859211 +Ra20 ns20 0 10492.0859211 +Ga19 ns19 0 ns20 0 -0.00078326448425 +Ga20 ns20 0 ns19 0 0.00078326448425 +Ca21 ns21 0 1e-012 +Ra21 ns21 0 77213136.7445 +Ca22 ns22 0 1e-012 +Ra22 ns22 0 1734728.75874 +Ca23 ns23 0 1e-012 +Ra23 ns23 0 274682.273568 +Ca24 ns24 0 1e-012 +Ra24 ns24 0 141385.594693 +Ca25 ns25 0 1e-012 +Ra25 ns25 0 124408.774731 +Ca26 ns26 0 1e-012 +Ra26 ns26 0 9695.38335251 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 186799.140083 +Ra28 ns28 0 186799.140083 +Ga27 ns27 0 ns28 0 -0.000220031228384 +Ga28 ns28 0 ns27 0 0.000220031228384 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 18905.464824 +Ra30 ns30 0 18905.464824 +Ga29 ns29 0 ns30 0 -0.000223102659344 +Ga30 ns30 0 ns29 0 0.000223102659344 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 21918.0164216 +Ra32 ns32 0 21918.0164216 +Ga31 ns31 0 ns32 0 -0.000225608963046 +Ga32 ns32 0 ns31 0 0.000225608963046 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 17638.8014066 +Ra34 ns34 0 17638.8014066 +Ga33 ns33 0 ns34 0 -0.000278732896707 +Ga34 ns34 0 ns33 0 0.000278732896707 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 4859.98516324 +Ra36 ns36 0 4859.98516324 +Ga35 ns35 0 ns36 0 -0.000585480963545 +Ga36 ns36 0 ns35 0 0.000585480963545 +Ca37 ns37 0 1e-012 +Ca38 ns38 0 1e-012 +Ra37 ns37 0 1754.03387431 +Ra38 ns38 0 1754.03387431 +Ga37 ns37 0 ns38 0 -0.000528555261685 +Ga38 ns38 0 ns37 0 0.000528555261685 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 10492.0859211 +Ra40 ns40 0 10492.0859211 +Ga39 ns39 0 ns40 0 -0.00078326448425 +Ga40 ns40 0 ns39 0 0.00078326448425 +Ca41 ns41 0 1e-012 +Ra41 ns41 0 77213136.7445 +Ca42 ns42 0 1e-012 +Ra42 ns42 0 1734728.75874 +Ca43 ns43 0 1e-012 +Ra43 ns43 0 274682.273568 +Ca44 ns44 0 1e-012 +Ra44 ns44 0 141385.594693 +Ca45 ns45 0 1e-012 +Ra45 ns45 0 124408.774731 +Ca46 ns46 0 1e-012 +Ra46 ns46 0 9695.38335251 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 186799.140083 +Ra48 ns48 0 186799.140083 +Ga47 ns47 0 ns48 0 -0.000220031228384 +Ga48 ns48 0 ns47 0 0.000220031228384 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 18905.464824 +Ra50 ns50 0 18905.464824 +Ga49 ns49 0 ns50 0 -0.000223102659344 +Ga50 ns50 0 ns49 0 0.000223102659344 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 21918.0164216 +Ra52 ns52 0 21918.0164216 +Ga51 ns51 0 ns52 0 -0.000225608963046 +Ga52 ns52 0 ns51 0 0.000225608963046 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 17638.8014066 +Ra54 ns54 0 17638.8014066 +Ga53 ns53 0 ns54 0 -0.000278732896707 +Ga54 ns54 0 ns53 0 0.000278732896707 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 4859.98516324 +Ra56 ns56 0 4859.98516324 +Ga55 ns55 0 ns56 0 -0.000585480963545 +Ga56 ns56 0 ns55 0 0.000585480963545 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 1754.03387431 +Ra58 ns58 0 1754.03387431 +Ga57 ns57 0 ns58 0 -0.000528555261685 +Ga58 ns58 0 ns57 0 0.000528555261685 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 10492.0859211 +Ra60 ns60 0 10492.0859211 +Ga59 ns59 0 ns60 0 -0.00078326448425 +Ga60 ns60 0 ns59 0 0.00078326448425 +Ca61 ns61 0 1e-012 +Ra61 ns61 0 77213136.7445 +Ca62 ns62 0 1e-012 +Ra62 ns62 0 1734728.75874 +Ca63 ns63 0 1e-012 +Ra63 ns63 0 274682.273568 +Ca64 ns64 0 1e-012 +Ra64 ns64 0 141385.594693 +Ca65 ns65 0 1e-012 +Ra65 ns65 0 124408.774731 +Ca66 ns66 0 1e-012 +Ra66 ns66 0 9695.38335251 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 186799.140083 +Ra68 ns68 0 186799.140083 +Ga67 ns67 0 ns68 0 -0.000220031228384 +Ga68 ns68 0 ns67 0 0.000220031228384 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 18905.464824 +Ra70 ns70 0 18905.464824 +Ga69 ns69 0 ns70 0 -0.000223102659344 +Ga70 ns70 0 ns69 0 0.000223102659344 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 21918.0164216 +Ra72 ns72 0 21918.0164216 +Ga71 ns71 0 ns72 0 -0.000225608963046 +Ga72 ns72 0 ns71 0 0.000225608963046 +Ca73 ns73 0 1e-012 +Ca74 ns74 0 1e-012 +Ra73 ns73 0 17638.8014066 +Ra74 ns74 0 17638.8014066 +Ga73 ns73 0 ns74 0 -0.000278732896707 +Ga74 ns74 0 ns73 0 0.000278732896707 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 4859.98516324 +Ra76 ns76 0 4859.98516324 +Ga75 ns75 0 ns76 0 -0.000585480963545 +Ga76 ns76 0 ns75 0 0.000585480963545 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 1754.03387431 +Ra78 ns78 0 1754.03387431 +Ga77 ns77 0 ns78 0 -0.000528555261685 +Ga78 ns78 0 ns77 0 0.000528555261685 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 10492.0859211 +Ra80 ns80 0 10492.0859211 +Ga79 ns79 0 ns80 0 -0.00078326448425 +Ga80 ns80 0 ns79 0 0.00078326448425 +Ca81 ns81 0 1e-012 +Ra81 ns81 0 77213136.7445 +Ca82 ns82 0 1e-012 +Ra82 ns82 0 1734728.75874 +Ca83 ns83 0 1e-012 +Ra83 ns83 0 274682.273568 +Ca84 ns84 0 1e-012 +Ra84 ns84 0 141385.594693 +Ca85 ns85 0 1e-012 +Ra85 ns85 0 124408.774731 +Ca86 ns86 0 1e-012 +Ra86 ns86 0 9695.38335251 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 186799.140083 +Ra88 ns88 0 186799.140083 +Ga87 ns87 0 ns88 0 -0.000220031228384 +Ga88 ns88 0 ns87 0 0.000220031228384 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 18905.464824 +Ra90 ns90 0 18905.464824 +Ga89 ns89 0 ns90 0 -0.000223102659344 +Ga90 ns90 0 ns89 0 0.000223102659344 +Ca91 ns91 0 1e-012 +Ca92 ns92 0 1e-012 +Ra91 ns91 0 21918.0164216 +Ra92 ns92 0 21918.0164216 +Ga91 ns91 0 ns92 0 -0.000225608963046 +Ga92 ns92 0 ns91 0 0.000225608963046 +Ca93 ns93 0 1e-012 +Ca94 ns94 0 1e-012 +Ra93 ns93 0 17638.8014066 +Ra94 ns94 0 17638.8014066 +Ga93 ns93 0 ns94 0 -0.000278732896707 +Ga94 ns94 0 ns93 0 0.000278732896707 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 4859.98516324 +Ra96 ns96 0 4859.98516324 +Ga95 ns95 0 ns96 0 -0.000585480963545 +Ga96 ns96 0 ns95 0 0.000585480963545 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 1754.03387431 +Ra98 ns98 0 1754.03387431 +Ga97 ns97 0 ns98 0 -0.000528555261685 +Ga98 ns98 0 ns97 0 0.000528555261685 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 10492.0859211 +Ra100 ns100 0 10492.0859211 +Ga99 ns99 0 ns100 0 -0.00078326448425 +Ga100 ns100 0 ns99 0 0.00078326448425 +Ca101 ns101 0 1e-012 +Ra101 ns101 0 77213136.7445 +Ca102 ns102 0 1e-012 +Ra102 ns102 0 1734728.75874 +Ca103 ns103 0 1e-012 +Ra103 ns103 0 274682.273568 +Ca104 ns104 0 1e-012 +Ra104 ns104 0 141385.594693 +Ca105 ns105 0 1e-012 +Ra105 ns105 0 124408.774731 +Ca106 ns106 0 1e-012 +Ra106 ns106 0 9695.38335251 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 186799.140083 +Ra108 ns108 0 186799.140083 +Ga107 ns107 0 ns108 0 -0.000220031228384 +Ga108 ns108 0 ns107 0 0.000220031228384 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 18905.464824 +Ra110 ns110 0 18905.464824 +Ga109 ns109 0 ns110 0 -0.000223102659344 +Ga110 ns110 0 ns109 0 0.000223102659344 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 21918.0164216 +Ra112 ns112 0 21918.0164216 +Ga111 ns111 0 ns112 0 -0.000225608963046 +Ga112 ns112 0 ns111 0 0.000225608963046 +Ca113 ns113 0 1e-012 +Ca114 ns114 0 1e-012 +Ra113 ns113 0 17638.8014066 +Ra114 ns114 0 17638.8014066 +Ga113 ns113 0 ns114 0 -0.000278732896707 +Ga114 ns114 0 ns113 0 0.000278732896707 +Ca115 ns115 0 1e-012 +Ca116 ns116 0 1e-012 +Ra115 ns115 0 4859.98516324 +Ra116 ns116 0 4859.98516324 +Ga115 ns115 0 ns116 0 -0.000585480963545 +Ga116 ns116 0 ns115 0 0.000585480963545 +Ca117 ns117 0 1e-012 +Ca118 ns118 0 1e-012 +Ra117 ns117 0 1754.03387431 +Ra118 ns118 0 1754.03387431 +Ga117 ns117 0 ns118 0 -0.000528555261685 +Ga118 ns118 0 ns117 0 0.000528555261685 +Ca119 ns119 0 1e-012 +Ca120 ns120 0 1e-012 +Ra119 ns119 0 10492.0859211 +Ra120 ns120 0 10492.0859211 +Ga119 ns119 0 ns120 0 -0.00078326448425 +Ga120 ns120 0 ns119 0 0.00078326448425 + +Gb1_1 ns1 0 ni1 0 1.29511640397e-008 +Gb2_1 ns2 0 ni1 0 5.7645899681e-007 +Gb3_1 ns3 0 ni1 0 3.64056983733e-006 +Gb4_1 ns4 0 ni1 0 7.07285634135e-006 +Gb5_1 ns5 0 ni1 0 8.03801823596e-006 +Gb6_1 ns6 0 ni1 0 0.000103141873162 +Gb7_1 ns7 0 ni1 0 0.000220161474845 +Gb9_1 ns9 0 ni1 0 0.000235643323388 +Gb11_1 ns11 0 ni1 0 0.000234835551607 +Gb13_1 ns13 0 ni1 0 0.000290264073499 +Gb15_1 ns15 0 ni1 0 0.000657794122568 +Gb17_1 ns17 0 ni1 0 0.00106014002649 +Gb19_1 ns19 0 ni1 0 0.000794862077909 +Gb21_2 ns21 0 ni2 0 1.29511640397e-008 +Gb22_2 ns22 0 ni2 0 5.7645899681e-007 +Gb23_2 ns23 0 ni2 0 3.64056983733e-006 +Gb24_2 ns24 0 ni2 0 7.07285634135e-006 +Gb25_2 ns25 0 ni2 0 8.03801823596e-006 +Gb26_2 ns26 0 ni2 0 0.000103141873162 +Gb27_2 ns27 0 ni2 0 0.000220161474845 +Gb29_2 ns29 0 ni2 0 0.000235643323388 +Gb31_2 ns31 0 ni2 0 0.000234835551607 +Gb33_2 ns33 0 ni2 0 0.000290264073499 +Gb35_2 ns35 0 ni2 0 0.000657794122568 +Gb37_2 ns37 0 ni2 0 0.00106014002649 +Gb39_2 ns39 0 ni2 0 0.000794862077909 +Gb41_3 ns41 0 ni3 0 1.29511640397e-008 +Gb42_3 ns42 0 ni3 0 5.7645899681e-007 +Gb43_3 ns43 0 ni3 0 3.64056983733e-006 +Gb44_3 ns44 0 ni3 0 7.07285634135e-006 +Gb45_3 ns45 0 ni3 0 8.03801823596e-006 +Gb46_3 ns46 0 ni3 0 0.000103141873162 +Gb47_3 ns47 0 ni3 0 0.000220161474845 +Gb49_3 ns49 0 ni3 0 0.000235643323388 +Gb51_3 ns51 0 ni3 0 0.000234835551607 +Gb53_3 ns53 0 ni3 0 0.000290264073499 +Gb55_3 ns55 0 ni3 0 0.000657794122568 +Gb57_3 ns57 0 ni3 0 0.00106014002649 +Gb59_3 ns59 0 ni3 0 0.000794862077909 +Gb61_4 ns61 0 ni4 0 1.29511640397e-008 +Gb62_4 ns62 0 ni4 0 5.7645899681e-007 +Gb63_4 ns63 0 ni4 0 3.64056983733e-006 +Gb64_4 ns64 0 ni4 0 7.07285634135e-006 +Gb65_4 ns65 0 ni4 0 8.03801823596e-006 +Gb66_4 ns66 0 ni4 0 0.000103141873162 +Gb67_4 ns67 0 ni4 0 0.000220161474845 +Gb69_4 ns69 0 ni4 0 0.000235643323388 +Gb71_4 ns71 0 ni4 0 0.000234835551607 +Gb73_4 ns73 0 ni4 0 0.000290264073499 +Gb75_4 ns75 0 ni4 0 0.000657794122568 +Gb77_4 ns77 0 ni4 0 0.00106014002649 +Gb79_4 ns79 0 ni4 0 0.000794862077909 +Gb81_5 ns81 0 ni5 0 1.29511640397e-008 +Gb82_5 ns82 0 ni5 0 5.7645899681e-007 +Gb83_5 ns83 0 ni5 0 3.64056983733e-006 +Gb84_5 ns84 0 ni5 0 7.07285634135e-006 +Gb85_5 ns85 0 ni5 0 8.03801823596e-006 +Gb86_5 ns86 0 ni5 0 0.000103141873162 +Gb87_5 ns87 0 ni5 0 0.000220161474845 +Gb89_5 ns89 0 ni5 0 0.000235643323388 +Gb91_5 ns91 0 ni5 0 0.000234835551607 +Gb93_5 ns93 0 ni5 0 0.000290264073499 +Gb95_5 ns95 0 ni5 0 0.000657794122568 +Gb97_5 ns97 0 ni5 0 0.00106014002649 +Gb99_5 ns99 0 ni5 0 0.000794862077909 +Gb101_6 ns101 0 ni6 0 1.29511640397e-008 +Gb102_6 ns102 0 ni6 0 5.7645899681e-007 +Gb103_6 ns103 0 ni6 0 3.64056983733e-006 +Gb104_6 ns104 0 ni6 0 7.07285634135e-006 +Gb105_6 ns105 0 ni6 0 8.03801823596e-006 +Gb106_6 ns106 0 ni6 0 0.000103141873162 +Gb107_6 ns107 0 ni6 0 0.000220161474845 +Gb109_6 ns109 0 ni6 0 0.000235643323388 +Gb111_6 ns111 0 ni6 0 0.000234835551607 +Gb113_6 ns113 0 ni6 0 0.000290264073499 +Gb115_6 ns115 0 ni6 0 0.000657794122568 +Gb117_6 ns117 0 ni6 0 0.00106014002649 +Gb119_6 ns119 0 ni6 0 0.000794862077909 + +Gc1_1 0 n2 ns1 0 0.00643295230051 +Gc1_2 0 n2 ns2 0 5.17928939234e-005 +Gc1_3 0 n2 ns3 0 0.000154831532817 +Gc1_4 0 n2 ns4 0 0.00674208460434 +Gc1_5 0 n2 ns5 0 0.00652844824227 +Gc1_6 0 n2 ns6 0 -0.000355681048424 +Gc1_7 0 n2 ns7 0 8.54993457742e-007 +Gc1_8 0 n2 ns8 0 -9.97552398558e-007 +Gc1_9 0 n2 ns9 0 0.00175955721654 +Gc1_10 0 n2 ns10 0 0.000919211449613 +Gc1_11 0 n2 ns11 0 0.00257976321755 +Gc1_12 0 n2 ns12 0 -0.00101548939474 +Gc1_13 0 n2 ns13 0 0.00161645689249 +Gc1_14 0 n2 ns14 0 -0.000937882728397 +Gc1_15 0 n2 ns15 0 -0.000856427281921 +Gc1_16 0 n2 ns16 0 0.000365137946677 +Gc1_17 0 n2 ns17 0 -0.00427859273073 +Gc1_18 0 n2 ns18 0 0.0236536083615 +Gc1_19 0 n2 ns19 0 0.00134855558649 +Gc1_20 0 n2 ns20 0 -0.00237594930141 +Gc1_21 0 n2 ns21 0 0.00631430288751 +Gc1_22 0 n2 ns22 0 -3.91888881306e-005 +Gc1_23 0 n2 ns23 0 -0.000206142081343 +Gc1_24 0 n2 ns24 0 -0.00128875914841 +Gc1_25 0 n2 ns25 0 -0.00533538335559 +Gc1_26 0 n2 ns26 0 -6.42115338177e-006 +Gc1_27 0 n2 ns27 0 5.59358762127e-007 +Gc1_28 0 n2 ns28 0 -5.54679552176e-007 +Gc1_29 0 n2 ns29 0 -0.0016437389958 +Gc1_30 0 n2 ns30 0 -0.000546294247295 +Gc1_31 0 n2 ns31 0 -0.000465895880655 +Gc1_32 0 n2 ns32 0 0.00078459452161 +Gc1_33 0 n2 ns33 0 0.00185617297772 +Gc1_34 0 n2 ns34 0 -0.000894969143025 +Gc1_35 0 n2 ns35 0 -0.00017158995135 +Gc1_36 0 n2 ns36 0 -7.56206476773e-005 +Gc1_37 0 n2 ns37 0 -0.000500399876493 +Gc1_38 0 n2 ns38 0 -0.00015744019867 +Gc1_39 0 n2 ns39 0 -0.000389700343275 +Gc1_40 0 n2 ns40 0 0.000351158110388 +Gc1_41 0 n2 ns41 0 0.00632740604051 +Gc1_42 0 n2 ns42 0 -3.87414675906e-005 +Gc1_43 0 n2 ns43 0 -0.000303417246751 +Gc1_44 0 n2 ns44 0 -0.00435601844519 +Gc1_45 0 n2 ns45 0 -0.00212806234371 +Gc1_46 0 n2 ns46 0 -1.41734736898e-006 +Gc1_47 0 n2 ns47 0 4.28778010091e-007 +Gc1_48 0 n2 ns48 0 -4.78882215053e-007 +Gc1_49 0 n2 ns49 0 -8.25981139197e-005 +Gc1_50 0 n2 ns50 0 -0.000100071056366 +Gc1_51 0 n2 ns51 0 -0.00214706183366 +Gc1_52 0 n2 ns52 0 0.000510602876436 +Gc1_53 0 n2 ns53 0 0.00186378018869 +Gc1_54 0 n2 ns54 0 -0.000953739757546 +Gc1_55 0 n2 ns55 0 1.65494607741e-005 +Gc1_56 0 n2 ns56 0 2.09528605639e-005 +Gc1_57 0 n2 ns57 0 0.000761008002135 +Gc1_58 0 n2 ns58 0 -0.000312172257164 +Gc1_59 0 n2 ns59 0 -0.000289952931265 +Gc1_60 0 n2 ns60 0 0.00101339245991 +Gc1_61 0 n2 ns61 0 -0.00637846931282 +Gc1_62 0 n2 ns62 0 -4.83162847912e-005 +Gc1_63 0 n2 ns63 0 -0.000151505352203 +Gc1_64 0 n2 ns64 0 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-0.000174270958573 +Gc2_16 0 n4 ns16 0 -8.00560361008e-005 +Gc2_17 0 n4 ns17 0 -0.000495363885316 +Gc2_18 0 n4 ns18 0 -0.000148113618935 +Gc2_19 0 n4 ns19 0 -0.000387422660539 +Gc2_20 0 n4 ns20 0 0.00035028367529 +Gc2_21 0 n4 ns21 0 0.00643524924606 +Gc2_22 0 n4 ns22 0 4.68070754124e-005 +Gc2_23 0 n4 ns23 0 0.00018381374189 +Gc2_24 0 n4 ns24 0 0.00864175614803 +Gc2_25 0 n4 ns25 0 0.00469700685871 +Gc2_26 0 n4 ns26 0 -0.000361509345573 +Gc2_27 0 n4 ns27 0 3.85909589798e-007 +Gc2_28 0 n4 ns28 0 -2.75131638982e-007 +Gc2_29 0 n4 ns29 0 0.00476822032295 +Gc2_30 0 n4 ns30 0 -0.0007716700362 +Gc2_31 0 n4 ns31 0 0.000299393819859 +Gc2_32 0 n4 ns32 0 -0.000635251701238 +Gc2_33 0 n4 ns33 0 0.00201779160781 +Gc2_34 0 n4 ns34 0 -0.00081540492263 +Gc2_35 0 n4 ns35 0 -0.000247352078224 +Gc2_36 0 n4 ns36 0 0.00072303633497 +Gc2_37 0 n4 ns37 0 0.00363099252325 +Gc2_38 0 n4 ns38 0 0.02859659554 +Gc2_39 0 n4 ns39 0 0.00117165761118 +Gc2_40 0 n4 ns40 0 -0.00111386312424 +Gc2_41 0 n4 ns41 0 0.00633108912794 +Gc2_42 0 n4 ns42 0 -3.36229553353e-005 +Gc2_43 0 n4 ns43 0 -0.000316786347378 +Gc2_44 0 n4 ns44 0 -0.00615263930949 +Gc2_45 0 n4 ns45 0 -0.000341392965663 +Gc2_46 0 n4 ns46 0 -6.21374943998e-006 +Gc2_47 0 n4 ns47 0 7.75534421195e-007 +Gc2_48 0 n4 ns48 0 -4.74849836006e-007 +Gc2_49 0 n4 ns49 0 -0.00220483658896 +Gc2_50 0 n4 ns50 0 0.000481555675768 +Gc2_51 0 n4 ns51 0 -0.000163991139305 +Gc2_52 0 n4 ns52 0 -0.000335739184138 +Gc2_53 0 n4 ns53 0 0.00207788095233 +Gc2_54 0 n4 ns54 0 -0.000886688922861 +Gc2_55 0 n4 ns55 0 -0.000147775866634 +Gc2_56 0 n4 ns56 0 -2.79658863901e-005 +Gc2_57 0 n4 ns57 0 -6.48639460615e-005 +Gc2_58 0 n4 ns58 0 3.1274887364e-005 +Gc2_59 0 n4 ns59 0 -0.00046373739847 +Gc2_60 0 n4 ns60 0 0.000474706052374 +Gc2_61 0 n4 ns61 0 -0.00631591269529 +Gc2_62 0 n4 ns62 0 3.83525541139e-005 +Gc2_63 0 n4 ns63 0 0.000211796998141 +Gc2_64 0 n4 ns64 0 0.00126159654987 +Gc2_65 0 n4 ns65 0 0.00535928588772 +Gc2_66 0 n4 ns66 0 3.34337814098e-006 +Gc2_67 0 n4 ns67 0 2.94833892159e-007 +Gc2_68 0 n4 ns68 0 -3.20672403113e-007 +Gc2_69 0 n4 ns69 0 0.00146768944252 +Gc2_70 0 n4 ns70 0 0.000365992421654 +Gc2_71 0 n4 ns71 0 0.000327954034752 +Gc2_72 0 n4 ns72 0 -0.000606575479934 +Gc2_73 0 n4 ns73 0 -0.00176145817025 +Gc2_74 0 n4 ns74 0 0.000841146994877 +Gc2_75 0 n4 ns75 0 -0.000250055818267 +Gc2_76 0 n4 ns76 0 -0.000203581923538 +Gc2_77 0 n4 ns77 0 -0.00208446458962 +Gc2_78 0 n4 ns78 0 -0.00138829443757 +Gc2_79 0 n4 ns79 0 -0.000311582622206 +Gc2_80 0 n4 ns80 0 -3.98907511186e-005 +Gc2_81 0 n4 ns81 0 -0.00637239940187 +Gc2_82 0 n4 ns82 0 -4.43581983291e-005 +Gc2_83 0 n4 ns83 0 -0.000163989457863 +Gc2_84 0 n4 ns84 0 -0.00876155037776 +Gc2_85 0 n4 ns85 0 -0.00457956924906 +Gc2_86 0 n4 ns86 0 0.000171238774988 +Gc2_87 0 n4 ns87 0 7.82021943451e-007 +Gc2_88 0 n4 ns88 0 -1.73557892511e-007 +Gc2_89 0 n4 ns89 0 -0.00353452435245 +Gc2_90 0 n4 ns90 0 0.000823422100919 +Gc2_91 0 n4 ns91 0 -0.000414403822256 +Gc2_92 0 n4 ns92 0 0.000550013025867 +Gc2_93 0 n4 ns93 0 -0.00216431445115 +Gc2_94 0 n4 ns94 0 0.000915240844932 +Gc2_95 0 n4 ns95 0 -0.000641477146201 +Gc2_96 0 n4 ns96 0 -0.000122942047432 +Gc2_97 0 n4 ns97 0 -0.00380733932019 +Gc2_98 0 n4 ns98 0 -0.00649075462229 +Gc2_99 0 n4 ns99 0 -0.000429601823742 +Gc2_100 0 n4 ns100 0 0.000998696935974 +Gc2_101 0 n4 ns101 0 -0.00633595648163 +Gc2_102 0 n4 ns102 0 3.31416951723e-005 +Gc2_103 0 n4 ns103 0 0.000323203537262 +Gc2_104 0 n4 ns104 0 0.00607895769273 +Gc2_105 0 n4 ns105 0 0.000400126245759 +Gc2_106 0 n4 ns106 0 7.29552891752e-006 +Gc2_107 0 n4 ns107 0 3.71884006036e-007 +Gc2_108 0 n4 ns108 0 -2.94631388904e-007 +Gc2_109 0 n4 ns109 0 0.00149899111845 +Gc2_110 0 n4 ns110 0 -0.000275605927106 +Gc2_111 0 n4 ns111 0 0.000100203297908 +Gc2_112 0 n4 ns112 0 0.000241156758073 +Gc2_113 0 n4 ns113 0 -0.00190875175125 +Gc2_114 0 n4 ns114 0 0.000804435880229 +Gc2_115 0 n4 ns115 0 -0.000242062329229 +Gc2_116 0 n4 ns116 0 -0.000222448576711 +Gc2_117 0 n4 ns117 0 -0.00177438225868 +Gc2_118 0 n4 ns118 0 -0.00125422050255 +Gc2_119 0 n4 ns119 0 -0.000383734313609 +Gc2_120 0 n4 ns120 0 -0.000152038338209 +Gd2_1 0 n4 ni1 0 -0.000452548528344 +Gd2_2 0 n4 ni2 0 0.00126157834409 +Gd2_3 0 n4 ni3 0 -0.00028886079985 +Gd2_4 0 n4 ni4 0 -0.00095783278142 +Gd2_5 0 n4 ni5 0 -0.00268808255199 +Gd2_6 0 n4 ni6 0 -0.000907706277711 +Gc3_1 0 n6 ns1 0 0.00632819170334 +Gc3_2 0 n6 ns2 0 -3.89142769612e-005 +Gc3_3 0 n6 ns3 0 -0.000302186259964 +Gc3_4 0 n6 ns4 0 -0.00436449415591 +Gc3_5 0 n6 ns5 0 -0.00212020451578 +Gc3_6 0 n6 ns6 0 -7.84500680313e-007 +Gc3_7 0 n6 ns7 0 4.28824508845e-007 +Gc3_8 0 n6 ns8 0 -4.79437006751e-007 +Gc3_9 0 n6 ns9 0 -8.17421491352e-005 +Gc3_10 0 n6 ns10 0 -0.000101444138167 +Gc3_11 0 n6 ns11 0 -0.00214713233825 +Gc3_12 0 n6 ns12 0 0.000511946467765 +Gc3_13 0 n6 ns13 0 0.00186338084094 +Gc3_14 0 n6 ns14 0 -0.000953684767942 +Gc3_15 0 n6 ns15 0 1.57688339184e-005 +Gc3_16 0 n6 ns16 0 2.45148324305e-005 +Gc3_17 0 n6 ns17 0 0.000776483001941 +Gc3_18 0 n6 ns18 0 -0.000310840044509 +Gc3_19 0 n6 ns19 0 -0.000290645941643 +Gc3_20 0 n6 ns20 0 0.00101613912318 +Gc3_21 0 n6 ns21 0 0.00633192117894 +Gc3_22 0 n6 ns22 0 -3.3759777804e-005 +Gc3_23 0 n6 ns23 0 -0.000315947033556 +Gc3_24 0 n6 ns24 0 -0.00616086329838 +Gc3_25 0 n6 ns25 0 -0.000333451905531 +Gc3_26 0 n6 ns26 0 -5.69536489102e-006 +Gc3_27 0 n6 ns27 0 7.72588004058e-007 +Gc3_28 0 n6 ns28 0 -4.53945389939e-007 +Gc3_29 0 n6 ns29 0 -0.00221014131584 +Gc3_30 0 n6 ns30 0 0.000495585707369 +Gc3_31 0 n6 ns31 0 -0.000162253330947 +Gc3_32 0 n6 ns32 0 -0.000347585545803 +Gc3_33 0 n6 ns33 0 0.00207737321559 +Gc3_34 0 n6 ns34 0 -0.000889987165554 +Gc3_35 0 n6 ns35 0 -0.000178214926215 +Gc3_36 0 n6 ns36 0 -4.25513366367e-005 +Gc3_37 0 n6 ns37 0 -4.83495479292e-005 +Gc3_38 0 n6 ns38 0 7.34259403697e-005 +Gc3_39 0 n6 ns39 0 -0.00045809055111 +Gc3_40 0 n6 ns40 0 0.000457937057121 +Gc3_41 0 n6 ns41 0 0.00646293782317 +Gc3_42 0 n6 ns42 0 4.91492653602e-005 +Gc3_43 0 n6 ns43 0 0.000240617186802 +Gc3_44 0 n6 ns44 0 0.0118285461373 +Gc3_45 0 n6 ns45 0 0.00135464946746 +Gc3_46 0 n6 ns46 0 -0.000372867233978 +Gc3_47 0 n6 ns47 0 8.87982273248e-007 +Gc3_48 0 n6 ns48 0 -4.74423895224e-007 +Gc3_49 0 n6 ns49 0 0.00218604818719 +Gc3_50 0 n6 ns50 0 0.000129906807416 +Gc3_51 0 n6 ns51 0 0.00195941863218 +Gc3_52 0 n6 ns52 0 -0.000285890778362 +Gc3_53 0 n6 ns53 0 0.002047871556 +Gc3_54 0 n6 ns54 0 -0.000957225597778 +Gc3_55 0 n6 ns55 0 -0.00146931855624 +Gc3_56 0 n6 ns56 0 0.000817461947332 +Gc3_57 0 n6 ns57 0 -0.00356582804286 +Gc3_58 0 n6 ns58 0 0.0251338688171 +Gc3_59 0 n6 ns59 0 0.000711858977574 +Gc3_60 0 n6 ns60 0 -0.00328895030622 +Gc3_61 0 n6 ns61 0 -0.00633035500179 +Gc3_62 0 n6 ns62 0 3.81735755499e-005 +Gc3_63 0 n6 ns63 0 0.000305274310492 +Gc3_64 0 n6 ns64 0 0.00434656872518 +Gc3_65 0 n6 ns65 0 0.00213140586725 +Gc3_66 0 n6 ns66 0 1.9487748493e-005 +Gc3_67 0 n6 ns67 0 6.68193555083e-007 +Gc3_68 0 n6 ns68 0 -1.66268748681e-007 +Gc3_69 0 n6 ns69 0 -9.39112314589e-005 +Gc3_70 0 n6 ns70 0 0.000124082341938 +Gc3_71 0 n6 ns71 0 0.0014515710001 +Gc3_72 0 n6 ns72 0 -0.000445407174638 +Gc3_73 0 n6 ns73 0 -0.00177087827481 +Gc3_74 0 n6 ns74 0 0.000892993120952 +Gc3_75 0 n6 ns75 0 -0.000127477823918 +Gc3_76 0 n6 ns76 0 -7.27650628584e-005 +Gc3_77 0 n6 ns77 0 -0.000135737041754 +Gc3_78 0 n6 ns78 0 -0.00103263549364 +Gc3_79 0 n6 ns79 0 -0.000348640485278 +Gc3_80 0 n6 ns80 0 0.000574242637102 +Gc3_81 0 n6 ns81 0 -0.00633553629137 +Gc3_82 0 n6 ns82 0 3.30717539627e-005 +Gc3_83 0 n6 ns83 0 0.000322101350301 +Gc3_84 0 n6 ns84 0 0.00612248806324 +Gc3_85 0 n6 ns85 0 0.000368305798654 +Gc3_86 0 n6 ns86 0 9.54586698039e-006 +Gc3_87 0 n6 ns87 0 3.01037633004e-007 +Gc3_88 0 n6 ns88 0 -4.21937180803e-008 +Gc3_89 0 n6 ns89 0 0.0018180364617 +Gc3_90 0 n6 ns90 0 -0.000398949161261 +Gc3_91 0 n6 ns91 0 0.000186714517648 +Gc3_92 0 n6 ns92 0 0.000180207765774 +Gc3_93 0 n6 ns93 0 -0.00220214017072 +Gc3_94 0 n6 ns94 0 0.000960804382015 +Gc3_95 0 n6 ns95 0 -9.4379232831e-005 +Gc3_96 0 n6 ns96 0 -0.000161495072191 +Gc3_97 0 n6 ns97 0 -0.000440303351929 +Gc3_98 0 n6 ns98 0 -0.00157225726444 +Gc3_99 0 n6 ns99 0 -6.90922347396e-005 +Gc3_100 0 n6 ns100 0 0.000790863061941 +Gc3_101 0 n6 ns101 0 -0.0064053091616 +Gc3_102 0 n6 ns102 0 -4.52986829526e-005 +Gc3_103 0 n6 ns103 0 -0.000230367335993 +Gc3_104 0 n6 ns104 0 -0.0118711019236 +Gc3_105 0 n6 ns105 0 -0.00130467928465 +Gc3_106 0 n6 ns106 0 0.000199229379165 +Gc3_107 0 n6 ns107 0 8.0427795946e-007 +Gc3_108 0 n6 ns108 0 -2.84067791677e-007 +Gc3_109 0 n6 ns109 0 -0.00132625791084 +Gc3_110 0 n6 ns110 0 -0.000182338691125 +Gc3_111 0 n6 ns111 0 -0.00151646342065 +Gc3_112 0 n6 ns112 0 0.000355026741647 +Gc3_113 0 n6 ns113 0 -0.00189074873353 +Gc3_114 0 n6 ns114 0 0.0008958609257 +Gc3_115 0 n6 ns115 0 -0.000257267712806 +Gc3_116 0 n6 ns116 0 -0.000109297776531 +Gc3_117 0 n6 ns117 0 0.00040678172256 +Gc3_118 0 n6 ns118 0 -0.00183599422309 +Gc3_119 0 n6 ns119 0 -0.000550772703822 +Gc3_120 0 n6 ns120 0 0.000519149348268 +Gd3_1 0 n6 ni1 0 0.000242242498508 +Gd3_2 0 n6 ni2 0 -0.000289314189922 +Gd3_3 0 n6 ni3 0 -0.00261351522055 +Gd3_4 0 n6 ni4 0 -0.00019352817137 +Gd3_5 0 n6 ni5 0 -0.000123101350683 +Gd3_6 0 n6 ni6 0 -0.000504319461285 +Gc4_1 0 n8 ns1 0 -0.00637777011885 +Gc4_2 0 n8 ns2 0 -4.88600227642e-005 +Gc4_3 0 n8 ns3 0 -0.000146589593367 +Gc4_4 0 n8 ns4 0 -0.00679045738868 +Gc4_5 0 n8 ns5 0 -0.00648478072837 +Gc4_6 0 n8 ns6 0 0.000155162495155 +Gc4_7 0 n8 ns7 0 7.8874372048e-007 +Gc4_8 0 n8 ns8 0 -9.6432505276e-008 +Gc4_9 0 n8 ns9 0 -0.00102951907423 +Gc4_10 0 n8 ns10 0 -0.000777392597846 +Gc4_11 0 n8 ns11 0 -0.00200444757235 +Gc4_12 0 n8 ns12 0 0.000931395612156 +Gc4_13 0 n8 ns13 0 -0.00155385888772 +Gc4_14 0 n8 ns14 0 0.000930720195076 +Gc4_15 0 n8 ns15 0 -0.000312778240776 +Gc4_16 0 n8 ns16 0 -0.000178216776633 +Gc4_17 0 n8 ns17 0 -0.000435867948286 +Gc4_18 0 n8 ns18 0 -0.00216554647076 +Gc4_19 0 n8 ns19 0 -0.000565529867514 +Gc4_20 0 n8 ns20 0 0.000395171852895 +Gc4_21 0 n8 ns21 0 -0.00631905225393 +Gc4_22 0 n8 ns22 0 3.85213842098e-005 +Gc4_23 0 n8 ns23 0 0.000210943013851 +Gc4_24 0 n8 ns24 0 0.00125785974063 +Gc4_25 0 n8 ns25 0 0.00536438206224 +Gc4_26 0 n8 ns26 0 2.60505105258e-006 +Gc4_27 0 n8 ns27 0 2.94819878886e-007 +Gc4_28 0 n8 ns28 0 -3.29606871437e-007 +Gc4_29 0 n8 ns29 0 0.00146516441561 +Gc4_30 0 n8 ns30 0 0.000367008473469 +Gc4_31 0 n8 ns31 0 0.00033012770245 +Gc4_32 0 n8 ns32 0 -0.00060772142073 +Gc4_33 0 n8 ns33 0 -0.00176176207913 +Gc4_34 0 n8 ns34 0 0.000841358582982 +Gc4_35 0 n8 ns35 0 -0.000251002580669 +Gc4_36 0 n8 ns36 0 -0.000200443245333 +Gc4_37 0 n8 ns37 0 -0.00207519728574 +Gc4_38 0 n8 ns38 0 -0.00138803769925 +Gc4_39 0 n8 ns39 0 -0.000313937230308 +Gc4_40 0 n8 ns40 0 -3.81611220894e-005 +Gc4_41 0 n8 ns41 0 -0.00633212959878 +Gc4_42 0 n8 ns42 0 3.84673332079e-005 +Gc4_43 0 n8 ns43 0 0.000303798793434 +Gc4_44 0 n8 ns44 0 0.00435048289231 +Gc4_45 0 n8 ns45 0 0.00212954204392 +Gc4_46 0 n8 ns46 0 1.87954624096e-005 +Gc4_47 0 n8 ns47 0 6.4601558189e-007 +Gc4_48 0 n8 ns48 0 -1.80835423943e-007 +Gc4_49 0 n8 ns49 0 -9.61240105564e-005 +Gc4_50 0 n8 ns50 0 0.000123044320914 +Gc4_51 0 n8 ns51 0 0.00145343971649 +Gc4_52 0 n8 ns52 0 -0.000444689242104 +Gc4_53 0 n8 ns53 0 -0.00177059529258 +Gc4_54 0 n8 ns54 0 0.000892883628106 +Gc4_55 0 n8 ns55 0 -0.000122736707163 +Gc4_56 0 n8 ns56 0 -6.99120424998e-005 +Gc4_57 0 n8 ns57 0 -0.00012860196506 +Gc4_58 0 n8 ns58 0 -0.00103786730778 +Gc4_59 0 n8 ns59 0 -0.00034960309421 +Gc4_60 0 n8 ns60 0 0.000580118741427 +Gc4_61 0 n8 ns61 0 0.00640517313047 +Gc4_62 0 n8 ns62 0 5.10033031701e-005 +Gc4_63 0 n8 ns63 0 0.000150810172866 +Gc4_64 0 n8 ns64 0 0.00674138635832 +Gc4_65 0 n8 ns65 0 0.00651528381508 +Gc4_66 0 n8 ns66 0 -0.000340760585978 +Gc4_67 0 n8 ns67 0 8.47700179259e-007 +Gc4_68 0 n8 ns68 0 3.04747663025e-007 +Gc4_69 0 n8 ns69 0 0.00116932124044 +Gc4_70 0 n8 ns70 0 0.000515925827095 +Gc4_71 0 n8 ns71 0 0.00114191590242 +Gc4_72 0 n8 ns72 0 -0.000636689213317 +Gc4_73 0 n8 ns73 0 0.00145037679366 +Gc4_74 0 n8 ns74 0 -0.000845966020863 +Gc4_75 0 n8 ns75 0 -0.000659424695107 +Gc4_76 0 n8 ns76 0 0.000809238880834 +Gc4_77 0 n8 ns77 0 0.00579391326439 +Gc4_78 0 n8 ns78 0 0.0270180356997 +Gc4_79 0 n8 ns79 0 0.000905051309672 +Gc4_80 0 n8 ns80 0 0.000336417708676 +Gc4_81 0 n8 ns81 0 0.00632164710561 +Gc4_82 0 n8 ns82 0 -3.81429065661e-005 +Gc4_83 0 n8 ns83 0 -0.000207251941452 +Gc4_84 0 n8 ns84 0 -0.00127529963436 +Gc4_85 0 n8 ns85 0 -0.00533617772504 +Gc4_86 0 n8 ns86 0 3.83793825229e-007 +Gc4_87 0 n8 ns87 0 4.56433690955e-007 +Gc4_88 0 n8 ns88 0 1.84749486538e-007 +Gc4_89 0 n8 ns89 0 -0.00116123203784 +Gc4_90 0 n8 ns90 0 -0.000147143218006 +Gc4_91 0 n8 ns91 0 -0.000204294658591 +Gc4_92 0 n8 ns92 0 0.000413492914768 +Gc4_93 0 n8 ns93 0 0.00185196905842 +Gc4_94 0 n8 ns94 0 -0.000938332286506 +Gc4_95 0 n8 ns95 0 -0.000311725927815 +Gc4_96 0 n8 ns96 0 -0.000101042192775 +Gc4_97 0 n8 ns97 0 -0.00319843806839 +Gc4_98 0 n8 ns98 0 -0.00110219880252 +Gc4_99 0 n8 ns99 0 -0.000367205736359 +Gc4_100 0 n8 ns100 0 -0.000365631199983 +Gc4_101 0 n8 ns101 0 0.00633620651757 +Gc4_102 0 n8 ns102 0 -3.78752724498e-005 +Gc4_103 0 n8 ns103 0 -0.000303260138964 +Gc4_104 0 n8 ns104 0 -0.00433644502518 +Gc4_105 0 n8 ns105 0 -0.00213318188604 +Gc4_106 0 n8 ns106 0 1.13935340649e-006 +Gc4_107 0 n8 ns107 0 2.52408703545e-007 +Gc4_108 0 n8 ns108 0 1.13668467358e-007 +Gc4_109 0 n8 ns109 0 -1.92737561841e-005 +Gc4_110 0 n8 ns110 0 -2.15357262942e-005 +Gc4_111 0 n8 ns111 0 -0.00100485549451 +Gc4_112 0 n8 ns112 0 0.000325535083141 +Gc4_113 0 n8 ns113 0 0.0016257058897 +Gc4_114 0 n8 ns114 0 -0.000836946595897 +Gc4_115 0 n8 ns115 0 -0.000313627569943 +Gc4_116 0 n8 ns116 0 -0.000140852990022 +Gc4_117 0 n8 ns117 0 -0.00349958384617 +Gc4_118 0 n8 ns118 0 -0.00140914791944 +Gc4_119 0 n8 ns119 0 -0.000307458409379 +Gc4_120 0 n8 ns120 0 -0.000312637566 +Gd4_1 0 n8 ni1 0 -0.000901016004347 +Gd4_2 0 n8 ni2 0 -0.000955019109061 +Gd4_3 0 n8 ni3 0 -0.000188879501246 +Gd4_4 0 n8 ni4 0 0.00103060555513 +Gd4_5 0 n8 ni5 0 -0.00138316531218 +Gd4_6 0 n8 ni6 0 -0.0014366130787 +Gc5_1 0 n10 ns1 0 -0.00631798989921 +Gc5_2 0 n10 ns2 0 3.83767328876e-005 +Gc5_3 0 n10 ns3 0 0.000215784757525 +Gc5_4 0 n10 ns4 0 0.00120776239787 +Gc5_5 0 n10 ns5 0 0.00540118336219 +Gc5_6 0 n10 ns6 0 2.59343099663e-006 +Gc5_7 0 n10 ns7 0 1.30562294539e-007 +Gc5_8 0 n10 ns8 0 -3.4020978207e-007 +Gc5_9 0 n10 ns9 0 0.00133428311 +Gc5_10 0 n10 ns10 0 0.000414908842017 +Gc5_11 0 n10 ns11 0 0.000227119520966 +Gc5_12 0 n10 ns12 0 -0.00064422414842 +Gc5_13 0 n10 ns13 0 -0.00196699199148 +Gc5_14 0 n10 ns14 0 0.000969911547788 +Gc5_15 0 n10 ns15 0 -0.000153357142923 +Gc5_16 0 n10 ns16 0 -9.9755868616e-005 +Gc5_17 0 n10 ns17 0 -0.000588562875776 +Gc5_18 0 n10 ns18 0 -0.000960324888907 +Gc5_19 0 n10 ns19 0 -0.00045323864609 +Gc5_20 0 n10 ns20 0 0.00026905685291 +Gc5_21 0 n10 ns21 0 -0.0063725887173 +Gc5_22 0 n10 ns22 0 -4.35824024888e-005 +Gc5_23 0 n10 ns23 0 -0.000170135327126 +Gc5_24 0 n10 ns24 0 -0.00873318805036 +Gc5_25 0 n10 ns25 0 -0.00460311631505 +Gc5_26 0 n10 ns26 0 0.00017154975335 +Gc5_27 0 n10 ns27 0 7.80912420592e-007 +Gc5_28 0 n10 ns28 0 -1.89651246082e-007 +Gc5_29 0 n10 ns29 0 -0.00353310258488 +Gc5_30 0 n10 ns30 0 0.000822420178198 +Gc5_31 0 n10 ns31 0 -0.000416103023101 +Gc5_32 0 n10 ns32 0 0.00055109621116 +Gc5_33 0 n10 ns33 0 -0.00216488985463 +Gc5_34 0 n10 ns34 0 0.000915604697103 +Gc5_35 0 n10 ns35 0 -0.000643977725426 +Gc5_36 0 n10 ns36 0 -0.00011915629741 +Gc5_37 0 n10 ns37 0 -0.0037984609128 +Gc5_38 0 n10 ns38 0 -0.00648666963559 +Gc5_39 0 n10 ns39 0 -0.000433879254389 +Gc5_40 0 n10 ns40 0 0.000999314506197 +Gc5_41 0 n10 ns41 0 -0.00633583578572 +Gc5_42 0 n10 ns42 0 3.31976897318e-005 +Gc5_43 0 n10 ns43 0 0.000319957946155 +Gc5_44 0 n10 ns44 0 0.00613289246367 +Gc5_45 0 n10 ns45 0 0.000360097722118 +Gc5_46 0 n10 ns46 0 1.17247669745e-005 +Gc5_47 0 n10 ns47 0 2.53272014768e-007 +Gc5_48 0 n10 ns48 0 -4.37120364183e-008 +Gc5_49 0 n10 ns49 0 0.00179105292774 +Gc5_50 0 n10 ns50 0 -0.000392468891779 +Gc5_51 0 n10 ns51 0 0.000205177546081 +Gc5_52 0 n10 ns52 0 0.000170944165338 +Gc5_53 0 n10 ns53 0 -0.0021984792368 +Gc5_54 0 n10 ns54 0 0.000956219173417 +Gc5_55 0 n10 ns55 0 -0.000132785642077 +Gc5_56 0 n10 ns56 0 -0.000173763543712 +Gc5_57 0 n10 ns57 0 -0.000380250858025 +Gc5_58 0 n10 ns58 0 -0.00149623069396 +Gc5_59 0 n10 ns59 0 -7.35446745697e-005 +Gc5_60 0 n10 ns60 0 0.000777648960617 +Gc5_61 0 n10 ns61 0 0.00631871794253 +Gc5_62 0 n10 ns62 0 -3.76594987548e-005 +Gc5_63 0 n10 ns63 0 -0.000208608401421 +Gc5_64 0 n10 ns64 0 -0.00127593423372 +Gc5_65 0 n10 ns65 0 -0.00533494945187 +Gc5_66 0 n10 ns66 0 -5.59462448891e-007 +Gc5_67 0 n10 ns67 0 4.73787586048e-007 +Gc5_68 0 n10 ns68 0 1.79066862719e-007 +Gc5_69 0 n10 ns69 0 -0.00115626136562 +Gc5_70 0 n10 ns70 0 -0.000146545532075 +Gc5_71 0 n10 ns71 0 -0.000208055020858 +Gc5_72 0 n10 ns72 0 0.00041391790182 +Gc5_73 0 n10 ns73 0 0.00185124876684 +Gc5_74 0 n10 ns74 0 -0.000937752162464 +Gc5_75 0 n10 ns75 0 -0.000307064323094 +Gc5_76 0 n10 ns76 0 -9.98023947692e-005 +Gc5_77 0 n10 ns77 0 -0.00321259727321 +Gc5_78 0 n10 ns78 0 -0.00111554683536 +Gc5_79 0 n10 ns79 0 -0.000365702808475 +Gc5_80 0 n10 ns80 0 -0.000365175617682 +Gc5_81 0 n10 ns81 0 0.00641451955072 +Gc5_82 0 n10 ns82 0 4.51957789827e-005 +Gc5_83 0 n10 ns83 0 0.000184951496163 +Gc5_84 0 n10 ns84 0 0.00857114319998 +Gc5_85 0 n10 ns85 0 0.00474117098695 +Gc5_86 0 n10 ns86 0 -0.000384710579273 +Gc5_87 0 n10 ns87 0 6.87144916265e-007 +Gc5_88 0 n10 ns88 0 3.97455613579e-007 +Gc5_89 0 n10 ns89 0 0.00323342388531 +Gc5_90 0 n10 ns90 0 -0.000801874796044 +Gc5_91 0 n10 ns91 0 4.56649442725e-006 +Gc5_92 0 n10 ns92 0 -0.000400124998349 +Gc5_93 0 n10 ns93 0 0.00225319203376 +Gc5_94 0 n10 ns94 0 -0.000973716826188 +Gc5_95 0 n10 ns95 0 -0.000327742202322 +Gc5_96 0 n10 ns96 0 0.000753528210626 +Gc5_97 0 n10 ns97 0 0.0080614783401 +Gc5_98 0 n10 ns98 0 0.0308847691976 +Gc5_99 0 n10 ns99 0 0.000810048120983 +Gc5_100 0 n10 ns100 0 -0.000663783474875 +Gc5_101 0 n10 ns101 0 0.00634105166854 +Gc5_102 0 n10 ns102 0 -3.30207608868e-005 +Gc5_103 0 n10 ns103 0 -0.000316138846323 +Gc5_104 0 n10 ns104 0 -0.00613580882513 +Gc5_105 0 n10 ns105 0 -0.000345443683507 +Gc5_106 0 n10 ns106 0 -7.57293698178e-007 +Gc5_107 0 n10 ns107 0 3.54555523705e-007 +Gc5_108 0 n10 ns108 0 2.74380944757e-008 +Gc5_109 0 n10 ns109 0 -0.0012323815082 +Gc5_110 0 n10 ns110 0 0.000343022580993 +Gc5_111 0 n10 ns111 0 -0.000149934846684 +Gc5_112 0 n10 ns112 0 -0.000213585181128 +Gc5_113 0 n10 ns113 0 0.00201146265437 +Gc5_114 0 n10 ns114 0 -0.000901001137449 +Gc5_115 0 n10 ns115 0 -0.000284189130453 +Gc5_116 0 n10 ns116 0 -0.000105695157234 +Gc5_117 0 n10 ns117 0 -0.00354991718194 +Gc5_118 0 n10 ns118 0 -0.00118631086851 +Gc5_119 0 n10 ns119 0 -0.000297883706745 +Gc5_120 0 n10 ns120 0 -0.000360430678327 +Gd5_1 0 n10 ni1 0 -0.000493300450772 +Gd5_2 0 n10 ni2 0 -0.00268926450932 +Gd5_3 0 n10 ni3 0 -0.000114476323313 +Gd5_4 0 n10 ni4 0 -0.00138705152261 +Gd5_5 0 n10 ni5 0 0.00255019494294 +Gd5_6 0 n10 ni6 0 -0.00149194979011 +Gc6_1 0 n12 ns1 0 -0.006331372802 +Gc6_2 0 n12 ns2 0 3.85030388062e-005 +Gc6_3 0 n12 ns3 0 0.000306730980133 +Gc6_4 0 n12 ns4 0 0.00432118843028 +Gc6_5 0 n12 ns5 0 0.00215372650131 +Gc6_6 0 n12 ns6 0 1.96442929241e-005 +Gc6_7 0 n12 ns7 0 4.58523660786e-007 +Gc6_8 0 n12 ns8 0 -5.9570191934e-007 +Gc6_9 0 n12 ns9 0 7.90239915893e-005 +Gc6_10 0 n12 ns10 0 7.02296838013e-005 +Gc6_11 0 n12 ns11 0 0.00153578232739 +Gc6_12 0 n12 ns12 0 -0.000457057227153 +Gc6_13 0 n12 ns13 0 -0.00170855261105 +Gc6_14 0 n12 ns14 0 0.000865588704267 +Gc6_15 0 n12 ns15 0 -0.000171408164534 +Gc6_16 0 n12 ns16 0 -8.97657452841e-005 +Gc6_17 0 n12 ns17 0 -0.000985726164471 +Gc6_18 0 n12 ns18 0 -0.0013344734375 +Gc6_19 0 n12 ns19 0 -0.00033972220083 +Gc6_20 0 n12 ns20 0 0.000513499146913 +Gc6_21 0 n12 ns21 0 -0.00633489358391 +Gc6_22 0 n12 ns22 0 3.31124797046e-005 +Gc6_23 0 n12 ns23 0 0.000323830059874 +Gc6_24 0 n12 ns24 0 0.00608235428831 +Gc6_25 0 n12 ns25 0 0.000396872504841 +Gc6_26 0 n12 ns26 0 4.96275703688e-006 +Gc6_27 0 n12 ns27 0 4.12430416981e-007 +Gc6_28 0 n12 ns28 0 -2.37609318959e-007 +Gc6_29 0 n12 ns29 0 0.00149954133768 +Gc6_30 0 n12 ns30 0 -0.000263903697052 +Gc6_31 0 n12 ns31 0 9.72986063335e-005 +Gc6_32 0 n12 ns32 0 0.000232402423907 +Gc6_33 0 n12 ns33 0 -0.00190891535606 +Gc6_34 0 n12 ns34 0 0.000802483938051 +Gc6_35 0 n12 ns35 0 -0.000268293619793 +Gc6_36 0 n12 ns36 0 -0.000262833048561 +Gc6_37 0 n12 ns37 0 -0.00186042084527 +Gc6_38 0 n12 ns38 0 -0.0012300324023 +Gc6_39 0 n12 ns39 0 -0.000361690847287 +Gc6_40 0 n12 ns40 0 -0.000187166523779 +Gc6_41 0 n12 ns41 0 -0.00640552379485 +Gc6_42 0 n12 ns42 0 -4.46019194474e-005 +Gc6_43 0 n12 ns43 0 -0.000236763857689 +Gc6_44 0 n12 ns44 0 -0.011840526879 +Gc6_45 0 n12 ns45 0 -0.00133065596991 +Gc6_46 0 n12 ns46 0 0.000200908230847 +Gc6_47 0 n12 ns47 0 8.08359523126e-007 +Gc6_48 0 n12 ns48 0 -3.10112885285e-007 +Gc6_49 0 n12 ns49 0 -0.001324273489 +Gc6_50 0 n12 ns50 0 -0.000186103891378 +Gc6_51 0 n12 ns51 0 -0.00151809405501 +Gc6_52 0 n12 ns52 0 0.000358157718776 +Gc6_53 0 n12 ns53 0 -0.00189072467792 +Gc6_54 0 n12 ns54 0 0.000896199150557 +Gc6_55 0 n12 ns55 0 -0.000256150799364 +Gc6_56 0 n12 ns56 0 -0.000108026754893 +Gc6_57 0 n12 ns57 0 0.000416633794764 +Gc6_58 0 n12 ns58 0 -0.00183124596285 +Gc6_59 0 n12 ns59 0 -0.000553907526221 +Gc6_60 0 n12 ns60 0 0.000522464306259 +Gc6_61 0 n12 ns61 0 0.00633281288629 +Gc6_62 0 n12 ns62 0 -3.7354883869e-005 +Gc6_63 0 n12 ns63 0 -0.00030513389221 +Gc6_64 0 n12 ns64 0 -0.0043337010984 +Gc6_65 0 n12 ns65 0 -0.00213441591074 +Gc6_66 0 n12 ns66 0 -6.8622197091e-007 +Gc6_67 0 n12 ns67 0 2.70082478186e-007 +Gc6_68 0 n12 ns68 0 1.3434082159e-007 +Gc6_69 0 n12 ns69 0 -9.49834094885e-006 +Gc6_70 0 n12 ns70 0 -1.74524808739e-005 +Gc6_71 0 n12 ns71 0 -0.00101298482323 +Gc6_72 0 n12 ns72 0 0.000324258297047 +Gc6_73 0 n12 ns73 0 0.00162446044151 +Gc6_74 0 n12 ns74 0 -0.000836934575674 +Gc6_75 0 n12 ns75 0 -0.000307826852782 +Gc6_76 0 n12 ns76 0 -0.000141121717602 +Gc6_77 0 n12 ns77 0 -0.00353354727191 +Gc6_78 0 n12 ns78 0 -0.00142943539405 +Gc6_79 0 n12 ns79 0 -0.000305178938415 +Gc6_80 0 n12 ns80 0 -0.000316849855901 +Gc6_81 0 n12 ns81 0 0.00633798935674 +Gc6_82 0 n12 ns82 0 -3.24373376053e-005 +Gc6_83 0 n12 ns83 0 -0.000318027905412 +Gc6_84 0 n12 ns84 0 -0.00613460463419 +Gc6_85 0 n12 ns85 0 -0.000345603970796 +Gc6_86 0 n12 ns86 0 -2.6378663221e-006 +Gc6_87 0 n12 ns87 0 3.54421186312e-007 +Gc6_88 0 n12 ns88 0 5.26699364853e-008 +Gc6_89 0 n12 ns89 0 -0.00122645919293 +Gc6_90 0 n12 ns90 0 0.000348147905285 +Gc6_91 0 n12 ns91 0 -0.000154949182145 +Gc6_92 0 n12 ns92 0 -0.000216197406689 +Gc6_93 0 n12 ns93 0 0.00201076419996 +Gc6_94 0 n12 ns94 0 -0.000901022694573 +Gc6_95 0 n12 ns95 0 -0.000275581320239 +Gc6_96 0 n12 ns96 0 -9.77245275526e-005 +Gc6_97 0 n12 ns97 0 -0.00356310229304 +Gc6_98 0 n12 ns98 0 -0.00121095927748 +Gc6_99 0 n12 ns99 0 -0.000298769041869 +Gc6_100 0 n12 ns100 0 -0.000357968981607 +Gc6_101 0 n12 ns101 0 0.00644308583264 +Gc6_102 0 n12 ns102 0 4.69338745783e-005 +Gc6_103 0 n12 ns103 0 0.000241663949873 +Gc6_104 0 n12 ns104 0 0.0117518656978 +Gc6_105 0 n12 ns105 0 0.00139752329079 +Gc6_106 0 n12 ns106 0 -0.000370119258524 +Gc6_107 0 n12 ns107 0 7.65117476179e-007 +Gc6_108 0 n12 ns108 0 6.95799919521e-009 +Gc6_109 0 n12 ns109 0 0.00117133946512 +Gc6_110 0 n12 ns110 0 5.98139390386e-005 +Gc6_111 0 n12 ns111 0 0.000899847514982 +Gc6_112 0 n12 ns112 0 -0.000209315040011 +Gc6_113 0 n12 ns113 0 0.00172865571515 +Gc6_114 0 n12 ns114 0 -0.000790099520326 +Gc6_115 0 n12 ns115 0 -0.000587448698577 +Gc6_116 0 n12 ns116 0 0.000897708242499 +Gc6_117 0 n12 ns117 0 0.00628158044004 +Gc6_118 0 n12 ns118 0 0.0269182569902 +Gc6_119 0 n12 ns119 0 0.000881267015957 +Gc6_120 0 n12 ns120 0 0.000474825885693 +Gd6_1 0 n12 ni1 0 -0.000533367062059 +Gd6_2 0 n12 ni2 0 -0.000950801427957 +Gd6_3 0 n12 ni3 0 -0.000501750982893 +Gd6_4 0 n12 ni4 0 -0.00144902457524 +Gd6_5 0 n12 ni5 0 -0.00149376971334 +Gd6_6 0 n12 ni6 0 0.00134577250485 +.ends + +.subckt 744835050135 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 116799204.166 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 3396288.43854 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 792452.836323 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 251419.371424 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 193588.00389 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 75965.2379493 +Ca7 ns7 0 1e-012 +Ra7 ns7 0 17411.2623248 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 47301.3531499 +Ra9 ns9 0 47301.3531499 +Ga8 ns8 0 ns9 0 -0.000131182228368 +Ga9 ns9 0 ns8 0 0.000131182228368 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 46745.4034733 +Ra11 ns11 0 46745.4034733 +Ga10 ns10 0 ns11 0 -0.000137668373643 +Ga11 ns11 0 ns10 0 0.000137668373643 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 39346.2337271 +Ra13 ns13 0 39346.2337271 +Ga12 ns12 0 ns13 0 -0.00016724898973 +Ga13 ns13 0 ns12 0 0.00016724898973 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 223507.758571 +Ra15 ns15 0 223507.758571 +Ga14 ns14 0 ns15 0 -0.000214808332661 +Ga15 ns15 0 ns14 0 0.000214808332661 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 17569.9179665 +Ra17 ns17 0 17569.9179665 +Ga16 ns16 0 ns17 0 -0.00048534634387 +Ga17 ns17 0 ns16 0 0.00048534634387 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 15103.4403441 +Ra19 ns19 0 15103.4403441 +Ga18 ns18 0 ns19 0 -0.000496216226097 +Ga19 ns19 0 ns18 0 0.000496216226097 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 10986.4696349 +Ra21 ns21 0 10986.4696349 +Ga20 ns20 0 ns21 0 -0.000546895847416 +Ga21 ns21 0 ns20 0 0.000546895847416 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 7018.56851802 +Ra23 ns23 0 7018.56851802 +Ga22 ns22 0 ns23 0 -0.000564437160335 +Ga23 ns23 0 ns22 0 0.000564437160335 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 1504.86264583 +Ra25 ns25 0 1504.86264583 +Ga24 ns24 0 ns25 0 -0.000369030043378 +Ga25 ns25 0 ns24 0 0.000369030043378 +Ca26 ns26 0 1e-012 +Ca27 ns27 0 1e-012 +Ra26 ns26 0 6682.98102094 +Ra27 ns27 0 6682.98102094 +Ga26 ns26 0 ns27 0 -0.000816527879121 +Ga27 ns27 0 ns26 0 0.000816527879121 +Ca28 ns28 0 1e-012 +Ra28 ns28 0 116799204.166 +Ca29 ns29 0 1e-012 +Ra29 ns29 0 3396288.43854 +Ca30 ns30 0 1e-012 +Ra30 ns30 0 792452.836323 +Ca31 ns31 0 1e-012 +Ra31 ns31 0 251419.371424 +Ca32 ns32 0 1e-012 +Ra32 ns32 0 193588.00389 +Ca33 ns33 0 1e-012 +Ra33 ns33 0 75965.2379493 +Ca34 ns34 0 1e-012 +Ra34 ns34 0 17411.2623248 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 47301.3531499 +Ra36 ns36 0 47301.3531499 +Ga35 ns35 0 ns36 0 -0.000131182228368 +Ga36 ns36 0 ns35 0 0.000131182228368 +Ca37 ns37 0 1e-012 +Ca38 ns38 0 1e-012 +Ra37 ns37 0 46745.4034733 +Ra38 ns38 0 46745.4034733 +Ga37 ns37 0 ns38 0 -0.000137668373643 +Ga38 ns38 0 ns37 0 0.000137668373643 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 39346.2337271 +Ra40 ns40 0 39346.2337271 +Ga39 ns39 0 ns40 0 -0.00016724898973 +Ga40 ns40 0 ns39 0 0.00016724898973 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 223507.758571 +Ra42 ns42 0 223507.758571 +Ga41 ns41 0 ns42 0 -0.000214808332661 +Ga42 ns42 0 ns41 0 0.000214808332661 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 17569.9179665 +Ra44 ns44 0 17569.9179665 +Ga43 ns43 0 ns44 0 -0.00048534634387 +Ga44 ns44 0 ns43 0 0.00048534634387 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 15103.4403441 +Ra46 ns46 0 15103.4403441 +Ga45 ns45 0 ns46 0 -0.000496216226097 +Ga46 ns46 0 ns45 0 0.000496216226097 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 10986.4696349 +Ra48 ns48 0 10986.4696349 +Ga47 ns47 0 ns48 0 -0.000546895847416 +Ga48 ns48 0 ns47 0 0.000546895847416 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 7018.56851802 +Ra50 ns50 0 7018.56851802 +Ga49 ns49 0 ns50 0 -0.000564437160335 +Ga50 ns50 0 ns49 0 0.000564437160335 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 1504.86264583 +Ra52 ns52 0 1504.86264583 +Ga51 ns51 0 ns52 0 -0.000369030043378 +Ga52 ns52 0 ns51 0 0.000369030043378 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 6682.98102094 +Ra54 ns54 0 6682.98102094 +Ga53 ns53 0 ns54 0 -0.000816527879121 +Ga54 ns54 0 ns53 0 0.000816527879121 +Ca55 ns55 0 1e-012 +Ra55 ns55 0 116799204.166 +Ca56 ns56 0 1e-012 +Ra56 ns56 0 3396288.43854 +Ca57 ns57 0 1e-012 +Ra57 ns57 0 792452.836323 +Ca58 ns58 0 1e-012 +Ra58 ns58 0 251419.371424 +Ca59 ns59 0 1e-012 +Ra59 ns59 0 193588.00389 +Ca60 ns60 0 1e-012 +Ra60 ns60 0 75965.2379493 +Ca61 ns61 0 1e-012 +Ra61 ns61 0 17411.2623248 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 47301.3531499 +Ra63 ns63 0 47301.3531499 +Ga62 ns62 0 ns63 0 -0.000131182228368 +Ga63 ns63 0 ns62 0 0.000131182228368 +Ca64 ns64 0 1e-012 +Ca65 ns65 0 1e-012 +Ra64 ns64 0 46745.4034733 +Ra65 ns65 0 46745.4034733 +Ga64 ns64 0 ns65 0 -0.000137668373643 +Ga65 ns65 0 ns64 0 0.000137668373643 +Ca66 ns66 0 1e-012 +Ca67 ns67 0 1e-012 +Ra66 ns66 0 39346.2337271 +Ra67 ns67 0 39346.2337271 +Ga66 ns66 0 ns67 0 -0.00016724898973 +Ga67 ns67 0 ns66 0 0.00016724898973 +Ca68 ns68 0 1e-012 +Ca69 ns69 0 1e-012 +Ra68 ns68 0 223507.758571 +Ra69 ns69 0 223507.758571 +Ga68 ns68 0 ns69 0 -0.000214808332661 +Ga69 ns69 0 ns68 0 0.000214808332661 +Ca70 ns70 0 1e-012 +Ca71 ns71 0 1e-012 +Ra70 ns70 0 17569.9179665 +Ra71 ns71 0 17569.9179665 +Ga70 ns70 0 ns71 0 -0.00048534634387 +Ga71 ns71 0 ns70 0 0.00048534634387 +Ca72 ns72 0 1e-012 +Ca73 ns73 0 1e-012 +Ra72 ns72 0 15103.4403441 +Ra73 ns73 0 15103.4403441 +Ga72 ns72 0 ns73 0 -0.000496216226097 +Ga73 ns73 0 ns72 0 0.000496216226097 +Ca74 ns74 0 1e-012 +Ca75 ns75 0 1e-012 +Ra74 ns74 0 10986.4696349 +Ra75 ns75 0 10986.4696349 +Ga74 ns74 0 ns75 0 -0.000546895847416 +Ga75 ns75 0 ns74 0 0.000546895847416 +Ca76 ns76 0 1e-012 +Ca77 ns77 0 1e-012 +Ra76 ns76 0 7018.56851802 +Ra77 ns77 0 7018.56851802 +Ga76 ns76 0 ns77 0 -0.000564437160335 +Ga77 ns77 0 ns76 0 0.000564437160335 +Ca78 ns78 0 1e-012 +Ca79 ns79 0 1e-012 +Ra78 ns78 0 1504.86264583 +Ra79 ns79 0 1504.86264583 +Ga78 ns78 0 ns79 0 -0.000369030043378 +Ga79 ns79 0 ns78 0 0.000369030043378 +Ca80 ns80 0 1e-012 +Ca81 ns81 0 1e-012 +Ra80 ns80 0 6682.98102094 +Ra81 ns81 0 6682.98102094 +Ga80 ns80 0 ns81 0 -0.000816527879121 +Ga81 ns81 0 ns80 0 0.000816527879121 +Ca82 ns82 0 1e-012 +Ra82 ns82 0 116799204.166 +Ca83 ns83 0 1e-012 +Ra83 ns83 0 3396288.43854 +Ca84 ns84 0 1e-012 +Ra84 ns84 0 792452.836323 +Ca85 ns85 0 1e-012 +Ra85 ns85 0 251419.371424 +Ca86 ns86 0 1e-012 +Ra86 ns86 0 193588.00389 +Ca87 ns87 0 1e-012 +Ra87 ns87 0 75965.2379493 +Ca88 ns88 0 1e-012 +Ra88 ns88 0 17411.2623248 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 47301.3531499 +Ra90 ns90 0 47301.3531499 +Ga89 ns89 0 ns90 0 -0.000131182228368 +Ga90 ns90 0 ns89 0 0.000131182228368 +Ca91 ns91 0 1e-012 +Ca92 ns92 0 1e-012 +Ra91 ns91 0 46745.4034733 +Ra92 ns92 0 46745.4034733 +Ga91 ns91 0 ns92 0 -0.000137668373643 +Ga92 ns92 0 ns91 0 0.000137668373643 +Ca93 ns93 0 1e-012 +Ca94 ns94 0 1e-012 +Ra93 ns93 0 39346.2337271 +Ra94 ns94 0 39346.2337271 +Ga93 ns93 0 ns94 0 -0.00016724898973 +Ga94 ns94 0 ns93 0 0.00016724898973 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 223507.758571 +Ra96 ns96 0 223507.758571 +Ga95 ns95 0 ns96 0 -0.000214808332661 +Ga96 ns96 0 ns95 0 0.000214808332661 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 17569.9179665 +Ra98 ns98 0 17569.9179665 +Ga97 ns97 0 ns98 0 -0.00048534634387 +Ga98 ns98 0 ns97 0 0.00048534634387 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 15103.4403441 +Ra100 ns100 0 15103.4403441 +Ga99 ns99 0 ns100 0 -0.000496216226097 +Ga100 ns100 0 ns99 0 0.000496216226097 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 10986.4696349 +Ra102 ns102 0 10986.4696349 +Ga101 ns101 0 ns102 0 -0.000546895847416 +Ga102 ns102 0 ns101 0 0.000546895847416 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 7018.56851802 +Ra104 ns104 0 7018.56851802 +Ga103 ns103 0 ns104 0 -0.000564437160335 +Ga104 ns104 0 ns103 0 0.000564437160335 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 1504.86264583 +Ra106 ns106 0 1504.86264583 +Ga105 ns105 0 ns106 0 -0.000369030043378 +Ga106 ns106 0 ns105 0 0.000369030043378 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 6682.98102094 +Ra108 ns108 0 6682.98102094 +Ga107 ns107 0 ns108 0 -0.000816527879121 +Ga108 ns108 0 ns107 0 0.000816527879121 +Ca109 ns109 0 1e-012 +Ra109 ns109 0 116799204.166 +Ca110 ns110 0 1e-012 +Ra110 ns110 0 3396288.43854 +Ca111 ns111 0 1e-012 +Ra111 ns111 0 792452.836323 +Ca112 ns112 0 1e-012 +Ra112 ns112 0 251419.371424 +Ca113 ns113 0 1e-012 +Ra113 ns113 0 193588.00389 +Ca114 ns114 0 1e-012 +Ra114 ns114 0 75965.2379493 +Ca115 ns115 0 1e-012 +Ra115 ns115 0 17411.2623248 +Ca116 ns116 0 1e-012 +Ca117 ns117 0 1e-012 +Ra116 ns116 0 47301.3531499 +Ra117 ns117 0 47301.3531499 +Ga116 ns116 0 ns117 0 -0.000131182228368 +Ga117 ns117 0 ns116 0 0.000131182228368 +Ca118 ns118 0 1e-012 +Ca119 ns119 0 1e-012 +Ra118 ns118 0 46745.4034733 +Ra119 ns119 0 46745.4034733 +Ga118 ns118 0 ns119 0 -0.000137668373643 +Ga119 ns119 0 ns118 0 0.000137668373643 +Ca120 ns120 0 1e-012 +Ca121 ns121 0 1e-012 +Ra120 ns120 0 39346.2337271 +Ra121 ns121 0 39346.2337271 +Ga120 ns120 0 ns121 0 -0.00016724898973 +Ga121 ns121 0 ns120 0 0.00016724898973 +Ca122 ns122 0 1e-012 +Ca123 ns123 0 1e-012 +Ra122 ns122 0 223507.758571 +Ra123 ns123 0 223507.758571 +Ga122 ns122 0 ns123 0 -0.000214808332661 +Ga123 ns123 0 ns122 0 0.000214808332661 +Ca124 ns124 0 1e-012 +Ca125 ns125 0 1e-012 +Ra124 ns124 0 17569.9179665 +Ra125 ns125 0 17569.9179665 +Ga124 ns124 0 ns125 0 -0.00048534634387 +Ga125 ns125 0 ns124 0 0.00048534634387 +Ca126 ns126 0 1e-012 +Ca127 ns127 0 1e-012 +Ra126 ns126 0 15103.4403441 +Ra127 ns127 0 15103.4403441 +Ga126 ns126 0 ns127 0 -0.000496216226097 +Ga127 ns127 0 ns126 0 0.000496216226097 +Ca128 ns128 0 1e-012 +Ca129 ns129 0 1e-012 +Ra128 ns128 0 10986.4696349 +Ra129 ns129 0 10986.4696349 +Ga128 ns128 0 ns129 0 -0.000546895847416 +Ga129 ns129 0 ns128 0 0.000546895847416 +Ca130 ns130 0 1e-012 +Ca131 ns131 0 1e-012 +Ra130 ns130 0 7018.56851802 +Ra131 ns131 0 7018.56851802 +Ga130 ns130 0 ns131 0 -0.000564437160335 +Ga131 ns131 0 ns130 0 0.000564437160335 +Ca132 ns132 0 1e-012 +Ca133 ns133 0 1e-012 +Ra132 ns132 0 1504.86264583 +Ra133 ns133 0 1504.86264583 +Ga132 ns132 0 ns133 0 -0.000369030043378 +Ga133 ns133 0 ns132 0 0.000369030043378 +Ca134 ns134 0 1e-012 +Ca135 ns135 0 1e-012 +Ra134 ns134 0 6682.98102094 +Ra135 ns135 0 6682.98102094 +Ga134 ns134 0 ns135 0 -0.000816527879121 +Ga135 ns135 0 ns134 0 0.000816527879121 +Ca136 ns136 0 1e-012 +Ra136 ns136 0 116799204.166 +Ca137 ns137 0 1e-012 +Ra137 ns137 0 3396288.43854 +Ca138 ns138 0 1e-012 +Ra138 ns138 0 792452.836323 +Ca139 ns139 0 1e-012 +Ra139 ns139 0 251419.371424 +Ca140 ns140 0 1e-012 +Ra140 ns140 0 193588.00389 +Ca141 ns141 0 1e-012 +Ra141 ns141 0 75965.2379493 +Ca142 ns142 0 1e-012 +Ra142 ns142 0 17411.2623248 +Ca143 ns143 0 1e-012 +Ca144 ns144 0 1e-012 +Ra143 ns143 0 47301.3531499 +Ra144 ns144 0 47301.3531499 +Ga143 ns143 0 ns144 0 -0.000131182228368 +Ga144 ns144 0 ns143 0 0.000131182228368 +Ca145 ns145 0 1e-012 +Ca146 ns146 0 1e-012 +Ra145 ns145 0 46745.4034733 +Ra146 ns146 0 46745.4034733 +Ga145 ns145 0 ns146 0 -0.000137668373643 +Ga146 ns146 0 ns145 0 0.000137668373643 +Ca147 ns147 0 1e-012 +Ca148 ns148 0 1e-012 +Ra147 ns147 0 39346.2337271 +Ra148 ns148 0 39346.2337271 +Ga147 ns147 0 ns148 0 -0.00016724898973 +Ga148 ns148 0 ns147 0 0.00016724898973 +Ca149 ns149 0 1e-012 +Ca150 ns150 0 1e-012 +Ra149 ns149 0 223507.758571 +Ra150 ns150 0 223507.758571 +Ga149 ns149 0 ns150 0 -0.000214808332661 +Ga150 ns150 0 ns149 0 0.000214808332661 +Ca151 ns151 0 1e-012 +Ca152 ns152 0 1e-012 +Ra151 ns151 0 17569.9179665 +Ra152 ns152 0 17569.9179665 +Ga151 ns151 0 ns152 0 -0.00048534634387 +Ga152 ns152 0 ns151 0 0.00048534634387 +Ca153 ns153 0 1e-012 +Ca154 ns154 0 1e-012 +Ra153 ns153 0 15103.4403441 +Ra154 ns154 0 15103.4403441 +Ga153 ns153 0 ns154 0 -0.000496216226097 +Ga154 ns154 0 ns153 0 0.000496216226097 +Ca155 ns155 0 1e-012 +Ca156 ns156 0 1e-012 +Ra155 ns155 0 10986.4696349 +Ra156 ns156 0 10986.4696349 +Ga155 ns155 0 ns156 0 -0.000546895847416 +Ga156 ns156 0 ns155 0 0.000546895847416 +Ca157 ns157 0 1e-012 +Ca158 ns158 0 1e-012 +Ra157 ns157 0 7018.56851802 +Ra158 ns158 0 7018.56851802 +Ga157 ns157 0 ns158 0 -0.000564437160335 +Ga158 ns158 0 ns157 0 0.000564437160335 +Ca159 ns159 0 1e-012 +Ca160 ns160 0 1e-012 +Ra159 ns159 0 1504.86264583 +Ra160 ns160 0 1504.86264583 +Ga159 ns159 0 ns160 0 -0.000369030043378 +Ga160 ns160 0 ns159 0 0.000369030043378 +Ca161 ns161 0 1e-012 +Ca162 ns162 0 1e-012 +Ra161 ns161 0 6682.98102094 +Ra162 ns162 0 6682.98102094 +Ga161 ns161 0 ns162 0 -0.000816527879121 +Ga162 ns162 0 ns161 0 0.000816527879121 + +Gb1_1 ns1 0 ni1 0 8.56170217204e-009 +Gb2_1 ns2 0 ni1 0 2.94439067263e-007 +Gb3_1 ns3 0 ni1 0 1.26190475214e-006 +Gb4_1 ns4 0 ni1 0 3.97741826469e-006 +Gb5_1 ns5 0 ni1 0 5.16560933479e-006 +Gb6_1 ns6 0 ni1 0 1.31639158515e-005 +Gb7_1 ns7 0 ni1 0 5.74340895762e-005 +Gb8_1 ns8 0 ni1 0 0.000134589273343 +Gb10_1 ns10 0 ni1 0 0.000140992580132 +Gb12_1 ns12 0 ni1 0 0.000171111148844 +Gb14_1 ns14 0 ni1 0 0.00021490152145 +Gb16_1 ns16 0 ni1 0 0.000492020690686 +Gb18_1 ns18 0 ni1 0 0.000505050630376 +Gb20_1 ns20 0 ni1 0 0.000562044676118 +Gb22_1 ns22 0 ni1 0 0.000600402760651 +Gb24_1 ns24 0 ni1 0 0.000869449444039 +Gb26_1 ns26 0 ni1 0 0.000843949209849 +Gb28_2 ns28 0 ni2 0 8.56170217204e-009 +Gb29_2 ns29 0 ni2 0 2.94439067263e-007 +Gb30_2 ns30 0 ni2 0 1.26190475214e-006 +Gb31_2 ns31 0 ni2 0 3.97741826469e-006 +Gb32_2 ns32 0 ni2 0 5.16560933479e-006 +Gb33_2 ns33 0 ni2 0 1.31639158515e-005 +Gb34_2 ns34 0 ni2 0 5.74340895762e-005 +Gb35_2 ns35 0 ni2 0 0.000134589273343 +Gb37_2 ns37 0 ni2 0 0.000140992580132 +Gb39_2 ns39 0 ni2 0 0.000171111148844 +Gb41_2 ns41 0 ni2 0 0.00021490152145 +Gb43_2 ns43 0 ni2 0 0.000492020690686 +Gb45_2 ns45 0 ni2 0 0.000505050630376 +Gb47_2 ns47 0 ni2 0 0.000562044676118 +Gb49_2 ns49 0 ni2 0 0.000600402760651 +Gb51_2 ns51 0 ni2 0 0.000869449444039 +Gb53_2 ns53 0 ni2 0 0.000843949209849 +Gb55_3 ns55 0 ni3 0 8.56170217204e-009 +Gb56_3 ns56 0 ni3 0 2.94439067263e-007 +Gb57_3 ns57 0 ni3 0 1.26190475214e-006 +Gb58_3 ns58 0 ni3 0 3.97741826469e-006 +Gb59_3 ns59 0 ni3 0 5.16560933479e-006 +Gb60_3 ns60 0 ni3 0 1.31639158515e-005 +Gb61_3 ns61 0 ni3 0 5.74340895762e-005 +Gb62_3 ns62 0 ni3 0 0.000134589273343 +Gb64_3 ns64 0 ni3 0 0.000140992580132 +Gb66_3 ns66 0 ni3 0 0.000171111148844 +Gb68_3 ns68 0 ni3 0 0.00021490152145 +Gb70_3 ns70 0 ni3 0 0.000492020690686 +Gb72_3 ns72 0 ni3 0 0.000505050630376 +Gb74_3 ns74 0 ni3 0 0.000562044676118 +Gb76_3 ns76 0 ni3 0 0.000600402760651 +Gb78_3 ns78 0 ni3 0 0.000869449444039 +Gb80_3 ns80 0 ni3 0 0.000843949209849 +Gb82_4 ns82 0 ni4 0 8.56170217204e-009 +Gb83_4 ns83 0 ni4 0 2.94439067263e-007 +Gb84_4 ns84 0 ni4 0 1.26190475214e-006 +Gb85_4 ns85 0 ni4 0 3.97741826469e-006 +Gb86_4 ns86 0 ni4 0 5.16560933479e-006 +Gb87_4 ns87 0 ni4 0 1.31639158515e-005 +Gb88_4 ns88 0 ni4 0 5.74340895762e-005 +Gb89_4 ns89 0 ni4 0 0.000134589273343 +Gb91_4 ns91 0 ni4 0 0.000140992580132 +Gb93_4 ns93 0 ni4 0 0.000171111148844 +Gb95_4 ns95 0 ni4 0 0.00021490152145 +Gb97_4 ns97 0 ni4 0 0.000492020690686 +Gb99_4 ns99 0 ni4 0 0.000505050630376 +Gb101_4 ns101 0 ni4 0 0.000562044676118 +Gb103_4 ns103 0 ni4 0 0.000600402760651 +Gb105_4 ns105 0 ni4 0 0.000869449444039 +Gb107_4 ns107 0 ni4 0 0.000843949209849 +Gb109_5 ns109 0 ni5 0 8.56170217204e-009 +Gb110_5 ns110 0 ni5 0 2.94439067263e-007 +Gb111_5 ns111 0 ni5 0 1.26190475214e-006 +Gb112_5 ns112 0 ni5 0 3.97741826469e-006 +Gb113_5 ns113 0 ni5 0 5.16560933479e-006 +Gb114_5 ns114 0 ni5 0 1.31639158515e-005 +Gb115_5 ns115 0 ni5 0 5.74340895762e-005 +Gb116_5 ns116 0 ni5 0 0.000134589273343 +Gb118_5 ns118 0 ni5 0 0.000140992580132 +Gb120_5 ns120 0 ni5 0 0.000171111148844 +Gb122_5 ns122 0 ni5 0 0.00021490152145 +Gb124_5 ns124 0 ni5 0 0.000492020690686 +Gb126_5 ns126 0 ni5 0 0.000505050630376 +Gb128_5 ns128 0 ni5 0 0.000562044676118 +Gb130_5 ns130 0 ni5 0 0.000600402760651 +Gb132_5 ns132 0 ni5 0 0.000869449444039 +Gb134_5 ns134 0 ni5 0 0.000843949209849 +Gb136_6 ns136 0 ni6 0 8.56170217204e-009 +Gb137_6 ns137 0 ni6 0 2.94439067263e-007 +Gb138_6 ns138 0 ni6 0 1.26190475214e-006 +Gb139_6 ns139 0 ni6 0 3.97741826469e-006 +Gb140_6 ns140 0 ni6 0 5.16560933479e-006 +Gb141_6 ns141 0 ni6 0 1.31639158515e-005 +Gb142_6 ns142 0 ni6 0 5.74340895762e-005 +Gb143_6 ns143 0 ni6 0 0.000134589273343 +Gb145_6 ns145 0 ni6 0 0.000140992580132 +Gb147_6 ns147 0 ni6 0 0.000171111148844 +Gb149_6 ns149 0 ni6 0 0.00021490152145 +Gb151_6 ns151 0 ni6 0 0.000492020690686 +Gb153_6 ns153 0 ni6 0 0.000505050630376 +Gb155_6 ns155 0 ni6 0 0.000562044676118 +Gb157_6 ns157 0 ni6 0 0.000600402760651 +Gb159_6 ns159 0 ni6 0 0.000869449444039 +Gb161_6 ns161 0 ni6 0 0.000843949209849 + +Gc1_1 0 n2 ns1 0 0.00662711870674 +Gc1_2 0 n2 ns2 0 7.58557222411e-005 +Gc1_3 0 n2 ns3 0 0.000133722807538 +Gc1_4 0 n2 ns4 0 0.00878821687164 +Gc1_5 0 n2 ns5 0 0.00450700782757 +Gc1_6 0 n2 ns6 0 1.29903684807e-005 +Gc1_7 0 n2 ns7 0 -0.000145301712065 +Gc1_8 0 n2 ns8 0 0.000645712118197 +Gc1_9 0 n2 ns9 0 -0.000398068286027 +Gc1_10 0 n2 ns10 0 0.00242752236837 +Gc1_11 0 n2 ns11 0 -8.16957433713e-005 +Gc1_12 0 n2 ns12 0 0.0020756709085 +Gc1_13 0 n2 ns13 0 -0.000342674357402 +Gc1_14 0 n2 ns14 0 1.19203208028e-007 +Gc1_15 0 n2 ns15 0 -2.9758120796e-008 +Gc1_16 0 n2 ns16 0 0.000173508385523 +Gc1_17 0 n2 ns17 0 0.000105353707283 +Gc1_18 0 n2 ns18 0 -0.000467264089008 +Gc1_19 0 n2 ns19 0 -3.97803590461e-005 +Gc1_20 0 n2 ns20 0 0.00515887167589 +Gc1_21 0 n2 ns21 0 -0.00700542399197 +Gc1_22 0 n2 ns22 0 -0.000201977285657 +Gc1_23 0 n2 ns23 0 0.00424157974792 +Gc1_24 0 n2 ns24 0 -0.0125775447539 +Gc1_25 0 n2 ns25 0 0.0233585422912 +Gc1_26 0 n2 ns26 0 0.00242169825501 +Gc1_27 0 n2 ns27 0 0.00263988473789 +Gc1_28 0 n2 ns28 0 0.00653126093977 +Gc1_29 0 n2 ns29 0 -2.70063366857e-005 +Gc1_30 0 n2 ns30 0 -0.000101748338123 +Gc1_31 0 n2 ns31 0 -0.00547441243598 +Gc1_32 0 n2 ns32 0 -0.0011526202634 +Gc1_33 0 n2 ns33 0 -3.79916551706e-005 +Gc1_34 0 n2 ns34 0 1.7597763417e-006 +Gc1_35 0 n2 ns35 0 -0.00170415713622 +Gc1_36 0 n2 ns36 0 0.000530761602857 +Gc1_37 0 n2 ns37 0 5.55571028039e-005 +Gc1_38 0 n2 ns38 0 -0.000597992018122 +Gc1_39 0 n2 ns39 0 0.00153932473905 +Gc1_40 0 n2 ns40 0 -0.000288120489352 +Gc1_41 0 n2 ns41 0 4.7471606378e-008 +Gc1_42 0 n2 ns42 0 -1.12615228118e-007 +Gc1_43 0 n2 ns43 0 -6.5246400183e-005 +Gc1_44 0 n2 ns44 0 4.99491857676e-005 +Gc1_45 0 n2 ns45 0 -0.000156936593904 +Gc1_46 0 n2 ns46 0 -0.000552516052449 +Gc1_47 0 n2 ns47 0 -0.000145301377231 +Gc1_48 0 n2 ns48 0 0.00109154521541 +Gc1_49 0 n2 ns49 0 -0.000135267849645 +Gc1_50 0 n2 ns50 0 9.11403771753e-005 +Gc1_51 0 n2 ns51 0 0.000688425587501 +Gc1_52 0 n2 ns52 0 -3.81445871854e-006 +Gc1_53 0 n2 ns53 0 -0.000434415994669 +Gc1_54 0 n2 ns54 0 0.000111580561265 +Gc1_55 0 n2 ns55 0 0.0065053713645 +Gc1_56 0 n2 ns56 0 -3.17800864408e-005 +Gc1_57 0 n2 ns57 0 -6.71225765036e-005 +Gc1_58 0 n2 ns58 0 -0.00349393676607 +Gc1_59 0 n2 ns59 0 -0.00318097190619 +Gc1_60 0 n2 ns60 0 -1.30022566501e-005 +Gc1_61 0 n2 ns61 0 -9.04840983463e-006 +Gc1_62 0 n2 ns62 0 0.000619311465736 +Gc1_63 0 n2 ns63 0 5.05080378682e-005 +Gc1_64 0 n2 ns64 0 -0.00244059561521 +Gc1_65 0 n2 ns65 0 0.000126826947664 +Gc1_66 0 n2 ns66 0 0.00166225761043 +Gc1_67 0 n2 ns67 0 -0.000452095501346 +Gc1_68 0 n2 ns68 0 1.04286037217e-007 +Gc1_69 0 n2 ns69 0 -1.50162564212e-007 +Gc1_70 0 n2 ns70 0 -0.00017717818371 +Gc1_71 0 n2 ns71 0 0.000117687443599 +Gc1_72 0 n2 ns72 0 -0.000387366585649 +Gc1_73 0 n2 ns73 0 0.000253031271236 +Gc1_74 0 n2 ns74 0 -0.0002277240819 +Gc1_75 0 n2 ns75 0 0.0001574229361 +Gc1_76 0 n2 ns76 0 0.000198529909781 +Gc1_77 0 n2 ns77 0 8.34082486626e-005 +Gc1_78 0 n2 ns78 0 0.000515680936848 +Gc1_79 0 n2 ns79 0 -0.000307756131525 +Gc1_80 0 n2 ns80 0 -0.000287525582051 +Gc1_81 0 n2 ns81 0 0.00015337927013 +Gc1_82 0 n2 ns82 0 -0.00660088655784 +Gc1_83 0 n2 ns83 0 -8.19225258933e-005 +Gc1_84 0 n2 ns84 0 -0.000112412886098 +Gc1_85 0 n2 ns85 0 -0.00888624876597 +Gc1_86 0 n2 ns86 0 -0.0043956062865 +Gc1_87 0 n2 ns87 0 -4.05730210117e-005 +Gc1_88 0 n2 ns88 0 6.48013802447e-005 +Gc1_89 0 n2 ns89 0 -0.000521191389339 +Gc1_90 0 n2 ns90 0 0.000335042441445 +Gc1_91 0 n2 ns91 0 -0.00194069202555 +Gc1_92 0 n2 ns92 0 0.000121168426465 +Gc1_93 0 n2 ns93 0 -0.00205627654195 +Gc1_94 0 n2 ns94 0 0.000370168495972 +Gc1_95 0 n2 ns95 0 1.45328516727e-007 +Gc1_96 0 n2 ns96 0 -2.77885525056e-007 +Gc1_97 0 n2 ns97 0 -6.98424995024e-005 +Gc1_98 0 n2 ns98 0 4.00708882616e-005 +Gc1_99 0 n2 ns99 0 0.000379542253176 +Gc1_100 0 n2 ns100 0 -0.000232113835143 +Gc1_101 0 n2 ns101 0 -0.00283671963264 +Gc1_102 0 n2 ns102 0 0.00446146363206 +Gc1_103 0 n2 ns103 0 -0.00025910229064 +Gc1_104 0 n2 ns104 0 -0.00221302071095 +Gc1_105 0 n2 ns105 0 -0.00172363122823 +Gc1_106 0 n2 ns106 0 -0.00502855876789 +Gc1_107 0 n2 ns107 0 7.36399077048e-005 +Gc1_108 0 n2 ns108 0 -0.00175298407582 +Gc1_109 0 n2 ns109 0 -0.00653613350339 +Gc1_110 0 n2 ns110 0 2.61258870335e-005 +Gc1_111 0 n2 ns111 0 0.000102352856215 +Gc1_112 0 n2 ns112 0 0.00546876234133 +Gc1_113 0 n2 ns113 0 0.0011453925742 +Gc1_114 0 n2 ns114 0 4.39290052381e-005 +Gc1_115 0 n2 ns115 0 3.1973627421e-006 +Gc1_116 0 n2 ns116 0 0.00138441995992 +Gc1_117 0 n2 ns117 0 -0.00044215388026 +Gc1_118 0 n2 ns118 0 -0.000118701024348 +Gc1_119 0 n2 ns119 0 0.00051492934569 +Gc1_120 0 n2 ns120 0 -0.00155230875044 +Gc1_121 0 n2 ns121 0 0.000294728801355 +Gc1_122 0 n2 ns122 0 2.6310887071e-007 +Gc1_123 0 n2 ns123 0 -2.86594001036e-007 +Gc1_124 0 n2 ns124 0 4.1022002874e-006 +Gc1_125 0 n2 ns125 0 0.00010746567818 +Gc1_126 0 n2 ns126 0 0.000172828908886 +Gc1_127 0 n2 ns127 0 -0.000176219339624 +Gc1_128 0 n2 ns128 0 -0.000201070836931 +Gc1_129 0 n2 ns129 0 -0.000259362197929 +Gc1_130 0 n2 ns130 0 -0.00024776543093 +Gc1_131 0 n2 ns131 0 0.00057249720686 +Gc1_132 0 n2 ns132 0 0.000718141804375 +Gc1_133 0 n2 ns133 0 -0.000554321955707 +Gc1_134 0 n2 ns134 0 -0.00116987957361 +Gc1_135 0 n2 ns135 0 0.000691445172782 +Gc1_136 0 n2 ns136 0 -0.00651224795201 +Gc1_137 0 n2 ns137 0 3.10841704253e-005 +Gc1_138 0 n2 ns138 0 6.6998089632e-005 +Gc1_139 0 n2 ns139 0 0.00350233732182 +Gc1_140 0 n2 ns140 0 0.00316250373084 +Gc1_141 0 n2 ns141 0 2.23213299621e-005 +Gc1_142 0 n2 ns142 0 9.26642345208e-006 +Gc1_143 0 n2 ns143 0 -0.000385097679129 +Gc1_144 0 n2 ns144 0 -7.14631224581e-005 +Gc1_145 0 n2 ns145 0 0.00194353245386 +Gc1_146 0 n2 ns146 0 -7.52566188133e-005 +Gc1_147 0 n2 ns147 0 -0.0016014627914 +Gc1_148 0 n2 ns148 0 0.000410121648989 +Gc1_149 0 n2 ns149 0 2.45729486304e-007 +Gc1_150 0 n2 ns150 0 -2.79259962143e-007 +Gc1_151 0 n2 ns151 0 2.32289212274e-005 +Gc1_152 0 n2 ns152 0 8.817928168e-005 +Gc1_153 0 n2 ns153 0 0.000179640492335 +Gc1_154 0 n2 ns154 0 -0.000300157047334 +Gc1_155 0 n2 ns155 0 -0.000326253982597 +Gc1_156 0 n2 ns156 0 0.000581460940102 +Gc1_157 0 n2 ns157 0 -0.000283667992368 +Gc1_158 0 n2 ns158 0 0.000119278968048 +Gc1_159 0 n2 ns159 0 0.000223337273157 +Gc1_160 0 n2 ns160 0 -0.00116078589955 +Gc1_161 0 n2 ns161 0 -0.00101570526683 +Gc1_162 0 n2 ns162 0 0.000463950309823 +Gd1_1 0 n2 ni1 0 -0.00260376483851 +Gd1_2 0 n2 ni2 0 -0.000115658168634 +Gd1_3 0 n2 ni3 0 -0.000117968565364 +Gd1_4 0 n2 ni4 0 -0.00140453756614 +Gd1_5 0 n2 ni5 0 -0.000422531943357 +Gd1_6 0 n2 ni6 0 -0.000459524210242 +Gc2_1 0 n4 ns1 0 0.00651890143613 +Gc2_2 0 n4 ns2 0 -2.61702877635e-005 +Gc2_3 0 n4 ns3 0 -0.000103394205914 +Gc2_4 0 n4 ns4 0 -0.00546456315977 +Gc2_5 0 n4 ns5 0 -0.00116240435582 +Gc2_6 0 n4 ns6 0 -3.54796009014e-005 +Gc2_7 0 n4 ns7 0 1.37279171507e-006 +Gc2_8 0 n4 ns8 0 -0.00170151492405 +Gc2_9 0 n4 ns9 0 0.000530510382055 +Gc2_10 0 n4 ns10 0 5.40980337586e-005 +Gc2_11 0 n4 ns11 0 -0.000597231287834 +Gc2_12 0 n4 ns12 0 0.00153781181435 +Gc2_13 0 n4 ns13 0 -0.00028803935806 +Gc2_14 0 n4 ns14 0 5.55889116361e-008 +Gc2_15 0 n4 ns15 0 -1.0435116203e-007 +Gc2_16 0 n4 ns16 0 -6.77185786526e-005 +Gc2_17 0 n4 ns17 0 5.37824422331e-005 +Gc2_18 0 n4 ns18 0 -0.000156915174837 +Gc2_19 0 n4 ns19 0 -0.000560641191006 +Gc2_20 0 n4 ns20 0 -0.000139576004607 +Gc2_21 0 n4 ns21 0 0.00108302209864 +Gc2_22 0 n4 ns22 0 -0.000132234908683 +Gc2_23 0 n4 ns23 0 0.00011487068979 +Gc2_24 0 n4 ns24 0 0.000750610370876 +Gc2_25 0 n4 ns25 0 1.55982892602e-005 +Gc2_26 0 n4 ns26 0 -0.000439464602138 +Gc2_27 0 n4 ns27 0 0.000127338287327 +Gc2_28 0 n4 ns28 0 0.00661308992071 +Gc2_29 0 n4 ns29 0 8.12128844563e-005 +Gc2_30 0 n4 ns30 0 0.000130044229437 +Gc2_31 0 n4 ns31 0 0.00906558699196 +Gc2_32 0 n4 ns32 0 0.00421533913219 +Gc2_33 0 n4 ns33 0 1.75042183077e-005 +Gc2_34 0 n4 ns34 0 -0.000148018684053 +Gc2_35 0 n4 ns35 0 0.00409798220015 +Gc2_36 0 n4 ns36 0 -0.000164581267309 +Gc2_37 0 n4 ns37 0 -0.000129314031979 +Gc2_38 0 n4 ns38 0 2.21608533202e-005 +Gc2_39 0 n4 ns39 0 0.00113516153954 +Gc2_40 0 n4 ns40 0 -0.000228814791724 +Gc2_41 0 n4 ns41 0 1.56667198482e-007 +Gc2_42 0 n4 ns42 0 -1.07724955724e-007 +Gc2_43 0 n4 ns43 0 0.00144318397367 +Gc2_44 0 n4 ns44 0 -0.00178520455408 +Gc2_45 0 n4 ns45 0 0.00253058270284 +Gc2_46 0 n4 ns46 0 -0.00138425365022 +Gc2_47 0 n4 ns47 0 0.00121407850049 +Gc2_48 0 n4 ns48 0 -0.00033365763353 +Gc2_49 0 n4 ns49 0 -0.00142526247498 +Gc2_50 0 n4 ns50 0 0.00257462668724 +Gc2_51 0 n4 ns51 0 -0.0129361185361 +Gc2_52 0 n4 ns52 0 0.0195548049577 +Gc2_53 0 n4 ns53 0 0.0009295334764 +Gc2_54 0 n4 ns54 0 0.00251767223163 +Gc2_55 0 n4 ns55 0 0.00650169805218 +Gc2_56 0 n4 ns56 0 -3.46238209817e-005 +Gc2_57 0 n4 ns57 0 -6.6975843806e-005 +Gc2_58 0 n4 ns58 0 -0.00389808930597 +Gc2_59 0 n4 ns59 0 -0.0027685476443 +Gc2_60 0 n4 ns60 0 -1.52851761547e-005 +Gc2_61 0 n4 ns61 0 -7.8998336862e-006 +Gc2_62 0 n4 ns62 0 -0.00125255016516 +Gc2_63 0 n4 ns63 0 -0.000459539594429 +Gc2_64 0 n4 ns64 0 -5.72388592235e-005 +Gc2_65 0 n4 ns65 0 0.000538064416653 +Gc2_66 0 n4 ns66 0 0.00122152629711 +Gc2_67 0 n4 ns67 0 -0.000359558443062 +Gc2_68 0 n4 ns68 0 -6.37659167795e-009 +Gc2_69 0 n4 ns69 0 -1.3521534031e-007 +Gc2_70 0 n4 ns70 0 -0.000977217068376 +Gc2_71 0 n4 ns71 0 -8.50851776189e-005 +Gc2_72 0 n4 ns72 0 0.000232167400123 +Gc2_73 0 n4 ns73 0 0.000648749434644 +Gc2_74 0 n4 ns74 0 8.23520034623e-005 +Gc2_75 0 n4 ns75 0 -0.000248792018492 +Gc2_76 0 n4 ns76 0 0.000112214566318 +Gc2_77 0 n4 ns77 0 0.00032558966509 +Gc2_78 0 n4 ns78 0 0.000690541830562 +Gc2_79 0 n4 ns79 0 -0.000184558724929 +Gc2_80 0 n4 ns80 0 -0.000224484863171 +Gc2_81 0 n4 ns81 0 0.000123473613382 +Gc2_82 0 n4 ns82 0 -0.00652085602057 +Gc2_83 0 n4 ns83 0 2.57831773669e-005 +Gc2_84 0 n4 ns84 0 0.000102121446915 +Gc2_85 0 n4 ns85 0 0.00548487865306 +Gc2_86 0 n4 ns86 0 0.00113602036023 +Gc2_87 0 n4 ns87 0 4.55536549615e-005 +Gc2_88 0 n4 ns88 0 -3.23130695234e-006 +Gc2_89 0 n4 ns89 0 0.00145408488448 +Gc2_90 0 n4 ns90 0 -0.000449056357177 +Gc2_91 0 n4 ns91 0 -4.61297361954e-005 +Gc2_92 0 n4 ns92 0 0.000479500589506 +Gc2_93 0 n4 ns93 0 -0.00151951319618 +Gc2_94 0 n4 ns94 0 0.000305086067456 +Gc2_95 0 n4 ns95 0 1.90113128126e-007 +Gc2_96 0 n4 ns96 0 -1.68845468138e-007 +Gc2_97 0 n4 ns97 0 -4.39753788943e-005 +Gc2_98 0 n4 ns98 0 0.000662968978073 +Gc2_99 0 n4 ns99 0 -0.000617396267632 +Gc2_100 0 n4 ns100 0 0.000141929995169 +Gc2_101 0 n4 ns101 0 0.00025606815479 +Gc2_102 0 n4 ns102 0 -0.000906877432704 +Gc2_103 0 n4 ns103 0 -7.30173212459e-005 +Gc2_104 0 n4 ns104 0 0.000353736769708 +Gc2_105 0 n4 ns105 0 -0.000242800427883 +Gc2_106 0 n4 ns106 0 -0.00110603262619 +Gc2_107 0 n4 ns107 0 -0.000698689953653 +Gc2_108 0 n4 ns108 0 0.000189610765186 +Gc2_109 0 n4 ns109 0 -0.00660674955165 +Gc2_110 0 n4 ns110 0 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0 n4 ns135 0 -0.00130198689413 +Gc2_136 0 n4 ns136 0 -0.00650892198186 +Gc2_137 0 n4 ns137 0 3.41270289343e-005 +Gc2_138 0 n4 ns138 0 6.68016632541e-005 +Gc2_139 0 n4 ns139 0 0.00390180469553 +Gc2_140 0 n4 ns140 0 0.002749499881 +Gc2_141 0 n4 ns141 0 2.56407114677e-005 +Gc2_142 0 n4 ns142 0 8.05928297998e-006 +Gc2_143 0 n4 ns143 0 0.000767456241209 +Gc2_144 0 n4 ns144 0 0.000385356261894 +Gc2_145 0 n4 ns145 0 4.200764874e-005 +Gc2_146 0 n4 ns146 0 -0.000429889127197 +Gc2_147 0 n4 ns147 0 -0.00117936483572 +Gc2_148 0 n4 ns148 0 0.000326048010385 +Gc2_149 0 n4 ns149 0 1.98455022085e-007 +Gc2_150 0 n4 ns150 0 -3.04543868748e-007 +Gc2_151 0 n4 ns151 0 3.23653432792e-005 +Gc2_152 0 n4 ns152 0 0.000473352294702 +Gc2_153 0 n4 ns153 0 -0.000479495060981 +Gc2_154 0 n4 ns154 0 -0.000383152094646 +Gc2_155 0 n4 ns155 0 0.000215827300723 +Gc2_156 0 n4 ns156 0 -0.000314661843455 +Gc2_157 0 n4 ns157 0 -7.95891879317e-005 +Gc2_158 0 n4 ns158 0 0.000528706658598 +Gc2_159 0 n4 ns159 0 0.000930572879001 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ns29 0 2.70769736361e-005 +Gc4_30 0 n8 ns30 0 0.000100693679721 +Gc4_31 0 n8 ns31 0 0.00548207280748 +Gc4_32 0 n8 ns32 0 0.00114378323917 +Gc4_33 0 n8 ns33 0 4.2507612942e-005 +Gc4_34 0 n8 ns34 0 -6.47975024398e-006 +Gc4_35 0 n8 ns35 0 0.00145414486098 +Gc4_36 0 n8 ns36 0 -0.000447560593051 +Gc4_37 0 n8 ns37 0 -4.85524110376e-005 +Gc4_38 0 n8 ns38 0 0.000479644967103 +Gc4_39 0 n8 ns39 0 -0.00151789267068 +Gc4_40 0 n8 ns40 0 0.000303924378566 +Gc4_41 0 n8 ns41 0 1.76845142042e-007 +Gc4_42 0 n8 ns42 0 -1.68706184304e-007 +Gc4_43 0 n8 ns43 0 -4.20685880255e-005 +Gc4_44 0 n8 ns44 0 0.000657035379742 +Gc4_45 0 n8 ns45 0 -0.000614287786712 +Gc4_46 0 n8 ns46 0 0.000153325785435 +Gc4_47 0 n8 ns47 0 0.000242138504793 +Gc4_48 0 n8 ns48 0 -0.000887124884472 +Gc4_49 0 n8 ns49 0 -6.79936833328e-005 +Gc4_50 0 n8 ns50 0 0.000294152497388 +Gc4_51 0 n8 ns51 0 -0.000442845500991 +Gc4_52 0 n8 ns52 0 -0.00122366893045 +Gc4_53 0 n8 ns53 0 -0.000670093610164 +Gc4_54 0 n8 ns54 0 0.000152241698557 +Gc4_55 0 n8 ns55 0 -0.00650432884062 +Gc4_56 0 n8 ns56 0 3.17335377775e-005 +Gc4_57 0 n8 ns57 0 6.62730393713e-005 +Gc4_58 0 n8 ns58 0 0.00349938086527 +Gc4_59 0 n8 ns59 0 0.00317083139522 +Gc4_60 0 n8 ns60 0 1.81661036243e-005 +Gc4_61 0 n8 ns61 0 5.81577864746e-006 +Gc4_62 0 n8 ns62 0 -0.000511491768851 +Gc4_63 0 n8 ns63 0 -3.94466032646e-005 +Gc4_64 0 n8 ns64 0 0.00190950478823 +Gc4_65 0 n8 ns65 0 -0.00013178048159 +Gc4_66 0 n8 ns66 0 -0.00163749787448 +Gc4_67 0 n8 ns67 0 0.00046712998088 +Gc4_68 0 n8 ns68 0 2.99143124599e-007 +Gc4_69 0 n8 ns69 0 -2.96503573446e-007 +Gc4_70 0 n8 ns70 0 -1.13829812556e-005 +Gc4_71 0 n8 ns71 0 7.62200570745e-005 +Gc4_72 0 n8 ns72 0 -0.000538188113047 +Gc4_73 0 n8 ns73 0 0.0002095128011 +Gc4_74 0 n8 ns74 0 0.00025446119492 +Gc4_75 0 n8 ns75 0 -0.000405785716609 +Gc4_76 0 n8 ns76 0 -2.72767662791e-005 +Gc4_77 0 n8 ns77 0 0.000457102790254 +Gc4_78 0 n8 ns78 0 0.000823607206321 +Gc4_79 0 n8 ns79 0 -0.000663574809561 +Gc4_80 0 n8 ns80 0 -0.000785649684761 +Gc4_81 0 n8 ns81 0 0.000677225097829 +Gc4_82 0 n8 ns82 0 0.0065651054102 +Gc4_83 0 n8 ns83 0 7.46329851801e-005 +Gc4_84 0 n8 ns84 0 0.000136803183796 +Gc4_85 0 n8 ns85 0 0.00873894261313 +Gc4_86 0 n8 ns86 0 0.00454572189149 +Gc4_87 0 n8 ns87 0 -2.53740110914e-006 +Gc4_88 0 n8 ns88 0 -0.000125965641306 +Gc4_89 0 n8 ns89 0 0.000456063412895 +Gc4_90 0 n8 ns90 0 -0.000269684156369 +Gc4_91 0 n8 ns91 0 0.00150741301763 +Gc4_92 0 n8 ns92 0 -0.000130849174842 +Gc4_93 0 n8 ns93 0 0.00202240331974 +Gc4_94 0 n8 ns94 0 -0.000402341218882 +Gc4_95 0 n8 ns95 0 6.63524045699e-007 +Gc4_96 0 n8 ns96 0 -4.8138763576e-007 +Gc4_97 0 n8 ns97 0 9.12147588714e-005 +Gc4_98 0 n8 ns98 0 0.000114817983345 +Gc4_99 0 n8 ns99 0 -0.000341651836708 +Gc4_100 0 n8 ns100 0 -0.000499724651431 +Gc4_101 0 n8 ns101 0 0.00185517486937 +Gc4_102 0 n8 ns102 0 -0.00367042326404 +Gc4_103 0 n8 ns103 0 0.00140850541477 +Gc4_104 0 n8 ns104 0 0.00359518933041 +Gc4_105 0 n8 ns105 0 -0.0032006770844 +Gc4_106 0 n8 ns106 0 0.0329303730584 +Gc4_107 0 n8 ns107 0 0.00298808420596 +Gc4_108 0 n8 ns108 0 0.00192198767163 +Gc4_109 0 n8 ns109 0 0.00653641579559 +Gc4_110 0 n8 ns110 0 -2.55098526164e-005 +Gc4_111 0 n8 ns111 0 -0.000102845992432 +Gc4_112 0 n8 ns112 0 -0.00545720541209 +Gc4_113 0 n8 ns113 0 -0.00115918723258 +Gc4_114 0 n8 ns114 0 -3.6638038702e-005 +Gc4_115 0 n8 ns115 0 2.3505386095e-007 +Gc4_116 0 n8 ns116 0 -0.00116956713605 +Gc4_117 0 n8 ns117 0 0.000382362943356 +Gc4_118 0 n8 ns118 0 7.97661386308e-005 +Gc4_119 0 n8 ns119 0 -0.000415476711994 +Gc4_120 0 n8 ns120 0 0.00152654452744 +Gc4_121 0 n8 ns121 0 -0.000316734824972 +Gc4_122 0 n8 ns122 0 3.38093307232e-007 +Gc4_123 0 n8 ns123 0 -1.4509601774e-007 +Gc4_124 0 n8 ns124 0 -9.24767516737e-005 +Gc4_125 0 n8 ns125 0 -0.000222367188103 +Gc4_126 0 n8 ns126 0 0.00052448751806 +Gc4_127 0 n8 ns127 0 -0.000448173484578 +Gc4_128 0 n8 ns128 0 0.000728239982274 +Gc4_129 0 n8 ns129 0 0.000191442058156 +Gc4_130 0 n8 ns130 0 -0.00103857281398 +Gc4_131 0 n8 ns131 0 0.000482067379359 +Gc4_132 0 n8 ns132 0 -0.00296112545814 +Gc4_133 0 n8 ns133 0 -0.00388707641164 +Gc4_134 0 n8 ns134 0 -0.00124320517046 +Gc4_135 0 n8 ns135 0 0.000486923261479 +Gc4_136 0 n8 ns136 0 0.00651143061852 +Gc4_137 0 n8 ns137 0 -3.02970834142e-005 +Gc4_138 0 n8 ns138 0 -6.80830621699e-005 +Gc4_139 0 n8 ns139 0 -0.00348233576246 +Gc4_140 0 n8 ns140 0 -0.00318278184444 +Gc4_141 0 n8 ns141 0 -1.19871508272e-005 +Gc4_142 0 n8 ns142 0 -9.81268945466e-006 +Gc4_143 0 n8 ns143 0 0.000332301121868 +Gc4_144 0 n8 ns144 0 6.77387065444e-005 +Gc4_145 0 n8 ns145 0 -0.00154310613734 +Gc4_146 0 n8 ns146 0 8.54557209625e-005 +Gc4_147 0 n8 ns147 0 0.00157228958732 +Gc4_148 0 n8 ns148 0 -0.000431911287725 +Gc4_149 0 n8 ns149 0 5.08451996107e-007 +Gc4_150 0 n8 ns150 0 -2.7451226401e-007 +Gc4_151 0 n8 ns151 0 -3.98945559061e-005 +Gc4_152 0 n8 ns152 0 -2.62541981426e-005 +Gc4_153 0 n8 ns153 0 0.000316425015235 +Gc4_154 0 n8 ns154 0 -0.000299059973187 +Gc4_155 0 n8 ns155 0 0.000603305801562 +Gc4_156 0 n8 ns156 0 -0.000383348980803 +Gc4_157 0 n8 ns157 0 -0.000598144458993 +Gc4_158 0 n8 ns158 0 0.000617112217681 +Gc4_159 0 n8 ns159 0 -0.00209365265126 +Gc4_160 0 n8 ns160 0 -0.00387458973429 +Gc4_161 0 n8 ns161 0 -0.00125144822661 +Gc4_162 0 n8 ns162 0 0.00111536302146 +Gd4_1 0 n8 ni1 0 -0.00122701458065 +Gd4_2 0 n8 ni2 0 -0.000491794243038 +Gd4_3 0 n8 ni3 0 -0.000164372624532 +Gd4_4 0 n8 ni4 0 -0.000303133465015 +Gd4_5 0 n8 ni5 0 -0.00135846056084 +Gd4_6 0 n8 ni6 0 -0.00104268756262 +Gc5_1 0 n10 ns1 0 -0.00652835414658 +Gc5_2 0 n10 ns2 0 2.67356372755e-005 +Gc5_3 0 n10 ns3 0 0.000101588094208 +Gc5_4 0 n10 ns4 0 0.00546766223102 +Gc5_5 0 n10 ns5 0 0.00114977019973 +Gc5_6 0 n10 ns6 0 4.12521983282e-005 +Gc5_7 0 n10 ns7 0 -1.0619372194e-006 +Gc5_8 0 n10 ns8 0 0.00138273723931 +Gc5_9 0 n10 ns9 0 -0.000439399845082 +Gc5_10 0 n10 ns10 0 -0.000120597253747 +Gc5_11 0 n10 ns11 0 0.000513561572977 +Gc5_12 0 n10 ns12 0 -0.0015489013812 +Gc5_13 0 n10 ns13 0 0.000293187348185 +Gc5_14 0 n10 ns14 0 2.49719172604e-007 +Gc5_15 0 n10 ns15 0 -2.94251892751e-007 +Gc5_16 0 n10 ns16 0 8.28557987804e-006 +Gc5_17 0 n10 ns17 0 9.93695433919e-005 +Gc5_18 0 n10 ns18 0 0.000172441347993 +Gc5_19 0 n10 ns19 0 -0.000156977519089 +Gc5_20 0 n10 ns20 0 -0.000220849019345 +Gc5_21 0 n10 ns21 0 -0.00023934384317 +Gc5_22 0 n10 ns22 0 -0.000238434825627 +Gc5_23 0 n10 ns23 0 0.000496954206746 +Gc5_24 0 n10 ns24 0 0.000446603096002 +Gc5_25 0 n10 ns25 0 -0.00070653304477 +Gc5_26 0 n10 ns26 0 -0.00113347713347 +Gc5_27 0 n10 ns27 0 0.000637353425745 +Gc5_28 0 n10 ns28 0 -0.00661117363249 +Gc5_29 0 n10 ns29 0 -8.63418075809e-005 +Gc5_30 0 n10 ns30 0 -0.000109659266529 +Gc5_31 0 n10 ns31 0 -0.0091328371341 +Gc5_32 0 n10 ns32 0 -0.00413812720504 +Gc5_33 0 n10 ns33 0 -3.24627132718e-005 +Gc5_34 0 n10 ns34 0 8.26258079578e-005 +Gc5_35 0 n10 ns35 0 -0.00330451251735 +Gc5_36 0 n10 ns36 0 0.00016304912608 +Gc5_37 0 n10 ns37 0 9.91891318038e-005 +Gc5_38 0 n10 ns38 0 1.14680801797e-005 +Gc5_39 0 n10 ns39 0 -0.00114552275703 +Gc5_40 0 n10 ns40 0 0.000235686611372 +Gc5_41 0 n10 ns41 0 1.74830176556e-007 +Gc5_42 0 n10 ns42 0 -2.46197541291e-007 +Gc5_43 0 n10 ns43 0 -0.000500847510181 +Gc5_44 0 n10 ns44 0 0.000998664330556 +Gc5_45 0 n10 ns45 0 -0.00128011985723 +Gc5_46 0 n10 ns46 0 0.000319021663384 +Gc5_47 0 n10 ns47 0 -0.000177399772933 +Gc5_48 0 n10 ns48 0 4.18474229056e-005 +Gc5_49 0 n10 ns49 0 0.000116756516987 +Gc5_50 0 n10 ns50 0 -0.000780255606343 +Gc5_51 0 n10 ns51 0 -0.00158078017028 +Gc5_52 0 n10 ns52 0 -0.00258555757664 +Gc5_53 0 n10 ns53 0 0.000353003654476 +Gc5_54 0 n10 ns54 0 -0.00123912500433 +Gc5_55 0 n10 ns55 0 -0.00650323496088 +Gc5_56 0 n10 ns56 0 3.4853948357e-005 +Gc5_57 0 n10 ns57 0 6.58477102324e-005 +Gc5_58 0 n10 ns58 0 0.00390470647855 +Gc5_59 0 n10 ns59 0 0.00276100533818 +Gc5_60 0 n10 ns60 0 1.8893771043e-005 +Gc5_61 0 n10 ns61 0 6.07927752523e-006 +Gc5_62 0 n10 ns62 0 0.00102502590757 +Gc5_63 0 n10 ns63 0 0.000365956775519 +Gc5_64 0 n10 ns64 0 0.000102287785716 +Gc5_65 0 n10 ns65 0 -0.000459855809971 +Gc5_66 0 n10 ns66 0 -0.00123335524708 +Gc5_67 0 n10 ns67 0 0.00036302593408 +Gc5_68 0 n10 ns68 0 1.82176316517e-007 +Gc5_69 0 n10 ns69 0 -2.84461100874e-007 +Gc5_70 0 n10 ns70 0 6.72403366151e-005 +Gc5_71 0 n10 ns71 0 0.000169853025086 +Gc5_72 0 n10 ns72 0 -0.000570753183609 +Gc5_73 0 n10 ns73 0 0.000216094161241 +Gc5_74 0 n10 ns74 0 0.00014643787136 +Gc5_75 0 n10 ns75 0 -8.39153728302e-005 +Gc5_76 0 n10 ns76 0 -0.000180243888442 +Gc5_77 0 n10 ns77 0 0.000245495157984 +Gc5_78 0 n10 ns78 0 0.000329813880858 +Gc5_79 0 n10 ns79 0 -0.0010186990495 +Gc5_80 0 n10 ns80 0 -0.000783702590756 +Gc5_81 0 n10 ns81 0 0.000288799755238 +Gc5_82 0 n10 ns82 0 0.00653014376662 +Gc5_83 0 n10 ns83 0 -2.60339070553e-005 +Gc5_84 0 n10 ns84 0 -0.000101301379024 +Gc5_85 0 n10 ns85 0 -0.00547005108221 +Gc5_86 0 n10 ns86 0 -0.00114494496726 +Gc5_87 0 n10 ns87 0 -3.95898396817e-005 +Gc5_88 0 n10 ns88 0 1.70275198149e-006 +Gc5_89 0 n10 ns89 0 -0.00116947145993 +Gc5_90 0 n10 ns90 0 0.000381518035226 +Gc5_91 0 n10 ns91 0 8.00536493266e-005 +Gc5_92 0 n10 ns92 0 -0.000414770359483 +Gc5_93 0 n10 ns93 0 0.00152634518708 +Gc5_94 0 n10 ns94 0 -0.000316654417962 +Gc5_95 0 n10 ns95 0 3.46591779453e-007 +Gc5_96 0 n10 ns96 0 -1.30181799149e-007 +Gc5_97 0 n10 ns97 0 -9.22223055084e-005 +Gc5_98 0 n10 ns98 0 -0.000226121156272 +Gc5_99 0 n10 ns99 0 0.00052693560468 +Gc5_100 0 n10 ns100 0 -0.000441655040061 +Gc5_101 0 n10 ns101 0 0.000721997090887 +Gc5_102 0 n10 ns102 0 0.000194166573781 +Gc5_103 0 n10 ns103 0 -0.00103532373932 +Gc5_104 0 n10 ns104 0 0.000477451812298 +Gc5_105 0 n10 ns105 0 -0.00293461985903 +Gc5_106 0 n10 ns106 0 -0.003864487004 +Gc5_107 0 n10 ns107 0 -0.00124621420245 +Gc5_108 0 n10 ns108 0 0.000492563471674 +Gc5_109 0 n10 ns109 0 0.00659355029743 +Gc5_110 0 n10 ns110 0 8.2274131924e-005 +Gc5_111 0 n10 ns111 0 0.000123755580973 +Gc5_112 0 n10 ns112 0 0.00907949020979 +Gc5_113 0 n10 ns113 0 0.00416870681467 +Gc5_114 0 n10 ns114 0 3.63180380554e-005 +Gc5_115 0 n10 ns115 0 -0.000124787749917 +Gc5_116 0 n10 ns116 0 0.00267229888947 +Gc5_117 0 n10 ns117 0 -0.000152919685304 +Gc5_118 0 n10 ns118 0 -8.10281121391e-005 +Gc5_119 0 n10 ns119 0 -3.45353679861e-005 +Gc5_120 0 n10 ns120 0 0.00115720345777 +Gc5_121 0 n10 ns121 0 -0.000247778869586 +Gc5_122 0 n10 ns122 0 6.29666740036e-007 +Gc5_123 0 n10 ns123 0 -3.86644921142e-007 +Gc5_124 0 n10 ns124 0 0.000152524769323 +Gc5_125 0 n10 ns125 0 -0.000296593642373 +Gc5_126 0 n10 ns126 0 0.000627025387792 +Gc5_127 0 n10 ns127 0 -0.000734165786969 +Gc5_128 0 n10 ns128 0 0.00036784397196 +Gc5_129 0 n10 ns129 0 -0.000599043458 +Gc5_130 0 n10 ns130 0 0.000672868033039 +Gc5_131 0 n10 ns131 0 0.00242773838612 +Gc5_132 0 n10 ns132 0 -0.00319936358608 +Gc5_133 0 n10 ns133 0 0.0312595663227 +Gc5_134 0 n10 ns134 0 0.00273808249796 +Gc5_135 0 n10 ns135 0 0.00149130009597 +Gc5_136 0 n10 ns136 0 0.0065104173664 +Gc5_137 0 n10 ns137 0 -3.36979288956e-005 +Gc5_138 0 n10 ns138 0 -6.72858778069e-005 +Gc5_139 0 n10 ns139 0 -0.00388826159259 +Gc5_140 0 n10 ns140 0 -0.00276564315193 +Gc5_141 0 n10 ns141 0 -1.67174898489e-005 +Gc5_142 0 n10 ns142 0 -6.76023580344e-006 +Gc5_143 0 n10 ns143 0 -0.000616346122564 +Gc5_144 0 n10 ns144 0 -0.000300323601724 +Gc5_145 0 n10 ns145 0 -9.86229154532e-005 +Gc5_146 0 n10 ns146 0 0.000367606121798 +Gc5_147 0 n10 ns147 0 0.00118538759042 +Gc5_148 0 n10 ns148 0 -0.000335603927413 +Gc5_149 0 n10 ns149 0 4.9140974412e-007 +Gc5_150 0 n10 ns150 0 -3.29290727628e-007 +Gc5_151 0 n10 ns151 0 -3.97949117269e-005 +Gc5_152 0 n10 ns152 0 -0.00012502713315 +Gc5_153 0 n10 ns153 0 0.000534130265421 +Gc5_154 0 n10 ns154 0 -0.000350683457788 +Gc5_155 0 n10 ns155 0 0.000428778915467 +Gc5_156 0 n10 ns156 0 0.000101133455358 +Gc5_157 0 n10 ns157 0 -0.000833561927025 +Gc5_158 0 n10 ns158 0 0.000395286677923 +Gc5_159 0 n10 ns159 0 -0.00226151418462 +Gc5_160 0 n10 ns160 0 -0.00369177011839 +Gc5_161 0 n10 ns161 0 -0.00121416955067 +Gc5_162 0 n10 ns162 0 0.000766436455447 +Gd5_1 0 n10 ni1 0 -0.000508643255086 +Gd5_2 0 n10 ni2 0 -0.000879782225212 +Gd5_3 0 n10 ni3 0 -0.000285042261379 +Gd5_4 0 n10 ni4 0 -0.00135047721036 +Gd5_5 0 n10 ni5 0 -0.000932552783586 +Gd5_6 0 n10 ni6 0 -0.00111364167486 +Gc6_1 0 n12 ns1 0 -0.00650413624632 +Gc6_2 0 n12 ns2 0 3.13895803012e-005 +Gc6_3 0 n12 ns3 0 6.69767152947e-005 +Gc6_4 0 n12 ns4 0 0.00349789367033 +Gc6_5 0 n12 ns5 0 0.00317061942506 +Gc6_6 0 n12 ns6 0 1.87720111695e-005 +Gc6_7 0 n12 ns7 0 5.28272869431e-006 +Gc6_8 0 n12 ns8 0 -0.000382652765367 +Gc6_9 0 n12 ns9 0 -7.04801274385e-005 +Gc6_10 0 n12 ns10 0 0.00193735640801 +Gc6_11 0 n12 ns11 0 -7.41832075993e-005 +Gc6_12 0 n12 ns12 0 -0.00159838575357 +Gc6_13 0 n12 ns13 0 0.000408402394616 +Gc6_14 0 n12 ns14 0 2.34485072912e-007 +Gc6_15 0 n12 ns15 0 -2.76778574195e-007 +Gc6_16 0 n12 ns16 0 3.51686812278e-005 +Gc6_17 0 n12 ns17 0 7.14551501731e-005 +Gc6_18 0 n12 ns18 0 0.000169723901966 +Gc6_19 0 n12 ns19 0 -0.000260977970419 +Gc6_20 0 n12 ns20 0 -0.000362772487634 +Gc6_21 0 n12 ns21 0 0.000594014954373 +Gc6_22 0 n12 ns22 0 -0.00024847551752 +Gc6_23 0 n12 ns23 0 3.21244494588e-005 +Gc6_24 0 n12 ns24 0 -6.92965846375e-005 +Gc6_25 0 n12 ns25 0 -0.00133165524989 +Gc6_26 0 n12 ns26 0 -0.000976024982291 +Gc6_27 0 n12 ns27 0 0.00041326543091 +Gc6_28 0 n12 ns28 0 -0.00652161958794 +Gc6_29 0 n12 ns29 0 3.45321907166e-005 +Gc6_30 0 n12 ns30 0 6.66148924153e-005 +Gc6_31 0 n12 ns31 0 0.0038975706502 +Gc6_32 0 n12 ns32 0 0.00275771003735 +Gc6_33 0 n12 ns33 0 2.17402221535e-005 +Gc6_34 0 n12 ns34 0 5.1502956249e-006 +Gc6_35 0 n12 ns35 0 0.000766445902044 +Gc6_36 0 n12 ns36 0 0.000385097354304 +Gc6_37 0 n12 ns37 0 4.1218364034e-005 +Gc6_38 0 n12 ns38 0 -0.000428645594129 +Gc6_39 0 n12 ns39 0 -0.00117735103539 +Gc6_40 0 n12 ns40 0 0.000324938236057 +Gc6_41 0 n12 ns41 0 1.93590757236e-007 +Gc6_42 0 n12 ns42 0 -2.99625857378e-007 +Gc6_43 0 n12 ns43 0 3.76197768416e-005 +Gc6_44 0 n12 ns44 0 0.000473605705009 +Gc6_45 0 n12 ns45 0 -0.00048391582981 +Gc6_46 0 n12 ns46 0 -0.000379853216597 +Gc6_47 0 n12 ns47 0 0.000208499462591 +Gc6_48 0 n12 ns48 0 -0.000301956775538 +Gc6_49 0 n12 ns49 0 -7.78565560822e-005 +Gc6_50 0 n12 ns50 0 0.000485980705942 +Gc6_51 0 n12 ns51 0 0.000759167042526 +Gc6_52 0 n12 ns52 0 -0.000457791357559 +Gc6_53 0 n12 ns53 0 -0.000759188559448 +Gc6_54 0 n12 ns54 0 0.000544443217647 +Gc6_55 0 n12 ns55 0 -0.00655717182523 +Gc6_56 0 n12 ns56 0 -8.46793305851e-005 +Gc6_57 0 n12 ns57 0 -8.51238327573e-005 +Gc6_58 0 n12 ns58 0 -0.00717521234925 +Gc6_59 0 n12 ns59 0 -0.0060981110342 +Gc6_60 0 n12 ns60 0 -8.68205622916e-006 +Gc6_61 0 n12 ns61 0 4.55324090603e-005 +Gc6_62 0 n12 ns62 0 -0.000132763539819 +Gc6_63 0 n12 ns63 0 -0.000214249827043 +Gc6_64 0 n12 ns64 0 -0.00194533453208 +Gc6_65 0 n12 ns65 0 0.000101689415454 +Gc6_66 0 n12 ns66 0 -0.00127090081699 +Gc6_67 0 n12 ns67 0 0.000455322906555 +Gc6_68 0 n12 ns68 0 1.44343547539e-007 +Gc6_69 0 n12 ns69 0 -2.22435375937e-007 +Gc6_70 0 n12 ns70 0 -0.000386542325598 +Gc6_71 0 n12 ns71 0 -8.38036374417e-005 +Gc6_72 0 n12 ns72 0 -0.000821657499662 +Gc6_73 0 n12 ns73 0 0.000975843033928 +Gc6_74 0 n12 ns74 0 -0.000119655140454 +Gc6_75 0 n12 ns75 0 0.000167561306313 +Gc6_76 0 n12 ns76 0 -0.000212902062971 +Gc6_77 0 n12 ns77 0 -0.000889989975942 +Gc6_78 0 n12 ns78 0 -0.00311141651766 +Gc6_79 0 n12 ns79 0 -0.00287414339972 +Gc6_80 0 n12 ns80 0 0.000446436185519 +Gc6_81 0 n12 ns81 0 -0.00163650921224 +Gc6_82 0 n12 ns82 0 0.00650490101491 +Gc6_83 0 n12 ns83 0 -3.0761741869e-005 +Gc6_84 0 n12 ns84 0 -6.68375091372e-005 +Gc6_85 0 n12 ns85 0 -0.00349308749769 +Gc6_86 0 n12 ns86 0 -0.00317088347218 +Gc6_87 0 n12 ns87 0 -1.42564446265e-005 +Gc6_88 0 n12 ns88 0 -8.93604817208e-006 +Gc6_89 0 n12 ns89 0 0.000332121033708 +Gc6_90 0 n12 ns90 0 6.77080867499e-005 +Gc6_91 0 n12 ns91 0 -0.00154303988266 +Gc6_92 0 n12 ns92 0 8.52794675237e-005 +Gc6_93 0 n12 ns93 0 0.00157252295915 +Gc6_94 0 n12 ns94 0 -0.000431959591555 +Gc6_95 0 n12 ns95 0 5.23598487258e-007 +Gc6_96 0 n12 ns96 0 -2.72011295127e-007 +Gc6_97 0 n12 ns97 0 -4.02809910723e-005 +Gc6_98 0 n12 ns98 0 -3.31144411756e-005 +Gc6_99 0 n12 ns99 0 0.000322420016048 +Gc6_100 0 n12 ns100 0 -0.000287060466048 +Gc6_101 0 n12 ns101 0 0.000592442477648 +Gc6_102 0 n12 ns102 0 -0.000375564359789 +Gc6_103 0 n12 ns103 0 -0.000597852236638 +Gc6_104 0 n12 ns104 0 0.000598320603654 +Gc6_105 0 n12 ns105 0 -0.00210443734456 +Gc6_106 0 n12 ns106 0 -0.00386522471657 +Gc6_107 0 n12 ns107 0 -0.00125006083703 +Gc6_108 0 n12 ns108 0 0.00111135450746 +Gc6_109 0 n12 ns109 0 0.00651788488571 +Gc6_110 0 n12 ns110 0 -3.42265971474e-005 +Gc6_111 0 n12 ns111 0 -6.59366489154e-005 +Gc6_112 0 n12 ns112 0 -0.00389996858674 +Gc6_113 0 n12 ns113 0 -0.00275273741819 +Gc6_114 0 n12 ns114 0 -1.92039159638e-005 +Gc6_115 0 n12 ns115 0 -5.92415506439e-006 +Gc6_116 0 n12 ns116 0 -0.000616747066973 +Gc6_117 0 n12 ns117 0 -0.00030072129689 +Gc6_118 0 n12 ns118 0 -9.81058420441e-005 +Gc6_119 0 n12 ns119 0 0.000367838609733 +Gc6_120 0 n12 ns120 0 0.00118552365504 +Gc6_121 0 n12 ns121 0 -0.00033556006017 +Gc6_122 0 n12 ns122 0 4.91266003983e-007 +Gc6_123 0 n12 ns123 0 -3.21442079548e-007 +Gc6_124 0 n12 ns124 0 -3.7581102954e-005 +Gc6_125 0 n12 ns125 0 -0.000123389968529 +Gc6_126 0 n12 ns126 0 0.000530368388116 +Gc6_127 0 n12 ns127 0 -0.000352886607878 +Gc6_128 0 n12 ns128 0 0.000433334802323 +Gc6_129 0 n12 ns129 0 9.92952418768e-005 +Gc6_130 0 n12 ns130 0 -0.000841167899988 +Gc6_131 0 n12 ns131 0 0.000399800302948 +Gc6_132 0 n12 ns132 0 -0.00225670161142 +Gc6_133 0 n12 ns133 0 -0.00367919205314 +Gc6_134 0 n12 ns134 0 -0.00121713819625 +Gc6_135 0 n12 ns135 0 0.00076267227435 +Gc6_136 0 n12 ns136 0 0.00654068177088 +Gc6_137 0 n12 ns137 0 8.02225538868e-005 +Gc6_138 0 n12 ns138 0 9.86254519609e-005 +Gc6_139 0 n12 ns139 0 0.00713539884689 +Gc6_140 0 n12 ns140 0 0.00611297039238 +Gc6_141 0 n12 ns141 0 1.83892472468e-005 +Gc6_142 0 n12 ns142 0 -0.000106096475862 +Gc6_143 0 n12 ns143 0 6.57307160149e-005 +Gc6_144 0 n12 ns144 0 0.000156402871294 +Gc6_145 0 n12 ns145 0 0.00155098131121 +Gc6_146 0 n12 ns146 0 -7.04009469596e-005 +Gc6_147 0 n12 ns147 0 0.00122432576335 +Gc6_148 0 n12 ns148 0 -0.000425441903665 +Gc6_149 0 n12 ns149 0 5.93080356122e-007 +Gc6_150 0 n12 ns150 0 -3.72685853981e-007 +Gc6_151 0 n12 ns151 0 0.000119393634149 +Gc6_152 0 n12 ns152 0 0.000172906776471 +Gc6_153 0 n12 ns153 0 0.000194690749547 +Gc6_154 0 n12 ns154 0 -0.000654516366593 +Gc6_155 0 n12 ns155 0 0.000252234433165 +Gc6_156 0 n12 ns156 0 -0.000733474619995 +Gc6_157 0 n12 ns157 0 0.000958300707295 +Gc6_158 0 n12 ns158 0 0.00220474487607 +Gc6_159 0 n12 ns159 0 -0.0036999740883 +Gc6_160 0 n12 ns160 0 0.0303203204604 +Gc6_161 0 n12 ns161 0 0.00294876964691 +Gc6_162 0 n12 ns162 0 0.00114259771383 +Gd6_1 0 n12 ni1 0 -0.000548433437393 +Gd6_2 0 n12 ni2 0 -0.000162312266416 +Gd6_3 0 n12 ni3 0 -0.0011706502443 +Gd6_4 0 n12 ni4 0 -0.00104873146911 +Gd6_5 0 n12 ni5 0 -0.00111552449718 +Gd6_6 0 n12 ni6 0 -0.00100434554271 +.ends + + +.subckt 744835090095 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 234980401.203 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 3686375.32141 +Ca3 ns3 0 1e-012 +Ca4 ns4 0 1e-012 +Ra3 ns3 0 860822.458334 +Ra4 ns4 0 860822.458334 +Ga3 ns3 0 ns4 0 -6.52058706256e-007 +Ga4 ns4 0 ns3 0 6.52058706256e-007 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 501550.229785 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 369596.750398 +Ca7 ns7 0 1e-012 +Ra7 ns7 0 113166.288146 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 1052511.07871 +Ra9 ns9 0 1052511.07871 +Ga8 ns8 0 ns9 0 -1.92482479923e-005 +Ga9 ns9 0 ns8 0 1.92482479923e-005 +Ca10 ns10 0 1e-012 +Ra10 ns10 0 15945.9215037 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 99686.9047432 +Ra12 ns12 0 99686.9047432 +Ga11 ns11 0 ns12 0 8.23637568024e-005 +Ga12 ns12 0 ns11 0 -8.23637568024e-005 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 93866.819083 +Ra14 ns14 0 93866.819083 +Ga13 ns13 0 ns14 0 9.32385492882e-005 +Ga14 ns14 0 ns13 0 -9.32385492882e-005 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 80166.9541859 +Ra16 ns16 0 80166.9541859 +Ga15 ns15 0 ns16 0 0.000111704482203 +Ga16 ns16 0 ns15 0 -0.000111704482203 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 298584.146077 +Ra18 ns18 0 298584.146077 +Ga17 ns17 0 ns18 0 -0.000219173848946 +Ga18 ns18 0 ns17 0 0.000219173848946 +Ca19 ns19 0 1e-012 +Ca20 ns20 0 1e-012 +Ra19 ns19 0 31192.5022213 +Ra20 ns20 0 31192.5022213 +Ga19 ns19 0 ns20 0 -0.000318970158623 +Ga20 ns20 0 ns19 0 0.000318970158623 +Ca21 ns21 0 1e-012 +Ca22 ns22 0 1e-012 +Ra21 ns21 0 21769.1303288 +Ra22 ns22 0 21769.1303288 +Ga21 ns21 0 ns22 0 -0.000370728609904 +Ga22 ns22 0 ns21 0 0.000370728609904 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 39022.7928598 +Ra24 ns24 0 39022.7928598 +Ga23 ns23 0 ns24 0 -0.000405563076664 +Ga24 ns24 0 ns23 0 0.000405563076664 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 2139.64850026 +Ra26 ns26 0 2139.64850026 +Ga25 ns25 0 ns26 0 0.000217240575825 +Ga26 ns26 0 ns25 0 -0.000217240575825 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 33525.361311 +Ra28 ns28 0 33525.361311 +Ga27 ns27 0 ns28 0 0.000551177197672 +Ga28 ns28 0 ns27 0 -0.000551177197672 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 10899.5342598 +Ra30 ns30 0 10899.5342598 +Ga29 ns29 0 ns30 0 0.000580254710465 +Ga30 ns30 0 ns29 0 -0.000580254710465 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 10542.0213763 +Ra32 ns32 0 10542.0213763 +Ga31 ns31 0 ns32 0 0.000626215063344 +Ga32 ns32 0 ns31 0 -0.000626215063344 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 3956.67929269 +Ra34 ns34 0 3956.67929269 +Ga33 ns33 0 ns34 0 0.000583367859299 +Ga34 ns34 0 ns33 0 -0.000583367859299 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 12877.6101262 +Ra36 ns36 0 12877.6101262 +Ga35 ns35 0 ns36 0 0.000723077147846 +Ga36 ns36 0 ns35 0 -0.000723077147846 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 234980401.203 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 3686375.32141 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 860822.458334 +Ra40 ns40 0 860822.458334 +Ga39 ns39 0 ns40 0 -6.52058706256e-007 +Ga40 ns40 0 ns39 0 6.52058706256e-007 +Ca41 ns41 0 1e-012 +Ra41 ns41 0 501550.229785 +Ca42 ns42 0 1e-012 +Ra42 ns42 0 369596.750398 +Ca43 ns43 0 1e-012 +Ra43 ns43 0 113166.288146 +Ca44 ns44 0 1e-012 +Ca45 ns45 0 1e-012 +Ra44 ns44 0 1052511.07871 +Ra45 ns45 0 1052511.07871 +Ga44 ns44 0 ns45 0 -1.92482479923e-005 +Ga45 ns45 0 ns44 0 1.92482479923e-005 +Ca46 ns46 0 1e-012 +Ra46 ns46 0 15945.9215037 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 99686.9047432 +Ra48 ns48 0 99686.9047432 +Ga47 ns47 0 ns48 0 8.23637568024e-005 +Ga48 ns48 0 ns47 0 -8.23637568024e-005 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 93866.819083 +Ra50 ns50 0 93866.819083 +Ga49 ns49 0 ns50 0 9.32385492882e-005 +Ga50 ns50 0 ns49 0 -9.32385492882e-005 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 80166.9541859 +Ra52 ns52 0 80166.9541859 +Ga51 ns51 0 ns52 0 0.000111704482203 +Ga52 ns52 0 ns51 0 -0.000111704482203 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 298584.146077 +Ra54 ns54 0 298584.146077 +Ga53 ns53 0 ns54 0 -0.000219173848946 +Ga54 ns54 0 ns53 0 0.000219173848946 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 31192.5022213 +Ra56 ns56 0 31192.5022213 +Ga55 ns55 0 ns56 0 -0.000318970158623 +Ga56 ns56 0 ns55 0 0.000318970158623 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 21769.1303288 +Ra58 ns58 0 21769.1303288 +Ga57 ns57 0 ns58 0 -0.000370728609904 +Ga58 ns58 0 ns57 0 0.000370728609904 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 39022.7928598 +Ra60 ns60 0 39022.7928598 +Ga59 ns59 0 ns60 0 -0.000405563076664 +Ga60 ns60 0 ns59 0 0.000405563076664 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 2139.64850026 +Ra62 ns62 0 2139.64850026 +Ga61 ns61 0 ns62 0 0.000217240575825 +Ga62 ns62 0 ns61 0 -0.000217240575825 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 33525.361311 +Ra64 ns64 0 33525.361311 +Ga63 ns63 0 ns64 0 0.000551177197672 +Ga64 ns64 0 ns63 0 -0.000551177197672 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 10899.5342598 +Ra66 ns66 0 10899.5342598 +Ga65 ns65 0 ns66 0 0.000580254710465 +Ga66 ns66 0 ns65 0 -0.000580254710465 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 10542.0213763 +Ra68 ns68 0 10542.0213763 +Ga67 ns67 0 ns68 0 0.000626215063344 +Ga68 ns68 0 ns67 0 -0.000626215063344 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 3956.67929269 +Ra70 ns70 0 3956.67929269 +Ga69 ns69 0 ns70 0 0.000583367859299 +Ga70 ns70 0 ns69 0 -0.000583367859299 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 12877.6101262 +Ra72 ns72 0 12877.6101262 +Ga71 ns71 0 ns72 0 0.000723077147846 +Ga72 ns72 0 ns71 0 -0.000723077147846 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 234980401.203 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 3686375.32141 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 860822.458334 +Ra76 ns76 0 860822.458334 +Ga75 ns75 0 ns76 0 -6.52058706256e-007 +Ga76 ns76 0 ns75 0 6.52058706256e-007 +Ca77 ns77 0 1e-012 +Ra77 ns77 0 501550.229785 +Ca78 ns78 0 1e-012 +Ra78 ns78 0 369596.750398 +Ca79 ns79 0 1e-012 +Ra79 ns79 0 113166.288146 +Ca80 ns80 0 1e-012 +Ca81 ns81 0 1e-012 +Ra80 ns80 0 1052511.07871 +Ra81 ns81 0 1052511.07871 +Ga80 ns80 0 ns81 0 -1.92482479923e-005 +Ga81 ns81 0 ns80 0 1.92482479923e-005 +Ca82 ns82 0 1e-012 +Ra82 ns82 0 15945.9215037 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 99686.9047432 +Ra84 ns84 0 99686.9047432 +Ga83 ns83 0 ns84 0 8.23637568024e-005 +Ga84 ns84 0 ns83 0 -8.23637568024e-005 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 93866.819083 +Ra86 ns86 0 93866.819083 +Ga85 ns85 0 ns86 0 9.32385492882e-005 +Ga86 ns86 0 ns85 0 -9.32385492882e-005 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 80166.9541859 +Ra88 ns88 0 80166.9541859 +Ga87 ns87 0 ns88 0 0.000111704482203 +Ga88 ns88 0 ns87 0 -0.000111704482203 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 298584.146077 +Ra90 ns90 0 298584.146077 +Ga89 ns89 0 ns90 0 -0.000219173848946 +Ga90 ns90 0 ns89 0 0.000219173848946 +Ca91 ns91 0 1e-012 +Ca92 ns92 0 1e-012 +Ra91 ns91 0 31192.5022213 +Ra92 ns92 0 31192.5022213 +Ga91 ns91 0 ns92 0 -0.000318970158623 +Ga92 ns92 0 ns91 0 0.000318970158623 +Ca93 ns93 0 1e-012 +Ca94 ns94 0 1e-012 +Ra93 ns93 0 21769.1303288 +Ra94 ns94 0 21769.1303288 +Ga93 ns93 0 ns94 0 -0.000370728609904 +Ga94 ns94 0 ns93 0 0.000370728609904 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 39022.7928598 +Ra96 ns96 0 39022.7928598 +Ga95 ns95 0 ns96 0 -0.000405563076664 +Ga96 ns96 0 ns95 0 0.000405563076664 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 2139.64850026 +Ra98 ns98 0 2139.64850026 +Ga97 ns97 0 ns98 0 0.000217240575825 +Ga98 ns98 0 ns97 0 -0.000217240575825 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 33525.361311 +Ra100 ns100 0 33525.361311 +Ga99 ns99 0 ns100 0 0.000551177197672 +Ga100 ns100 0 ns99 0 -0.000551177197672 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 10899.5342598 +Ra102 ns102 0 10899.5342598 +Ga101 ns101 0 ns102 0 0.000580254710465 +Ga102 ns102 0 ns101 0 -0.000580254710465 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 10542.0213763 +Ra104 ns104 0 10542.0213763 +Ga103 ns103 0 ns104 0 0.000626215063344 +Ga104 ns104 0 ns103 0 -0.000626215063344 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 3956.67929269 +Ra106 ns106 0 3956.67929269 +Ga105 ns105 0 ns106 0 0.000583367859299 +Ga106 ns106 0 ns105 0 -0.000583367859299 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 12877.6101262 +Ra108 ns108 0 12877.6101262 +Ga107 ns107 0 ns108 0 0.000723077147846 +Ga108 ns108 0 ns107 0 -0.000723077147846 +Ca109 ns109 0 1e-012 +Ra109 ns109 0 234980401.203 +Ca110 ns110 0 1e-012 +Ra110 ns110 0 3686375.32141 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 860822.458334 +Ra112 ns112 0 860822.458334 +Ga111 ns111 0 ns112 0 -6.52058706256e-007 +Ga112 ns112 0 ns111 0 6.52058706256e-007 +Ca113 ns113 0 1e-012 +Ra113 ns113 0 501550.229785 +Ca114 ns114 0 1e-012 +Ra114 ns114 0 369596.750398 +Ca115 ns115 0 1e-012 +Ra115 ns115 0 113166.288146 +Ca116 ns116 0 1e-012 +Ca117 ns117 0 1e-012 +Ra116 ns116 0 1052511.07871 +Ra117 ns117 0 1052511.07871 +Ga116 ns116 0 ns117 0 -1.92482479923e-005 +Ga117 ns117 0 ns116 0 1.92482479923e-005 +Ca118 ns118 0 1e-012 +Ra118 ns118 0 15945.9215037 +Ca119 ns119 0 1e-012 +Ca120 ns120 0 1e-012 +Ra119 ns119 0 99686.9047432 +Ra120 ns120 0 99686.9047432 +Ga119 ns119 0 ns120 0 8.23637568024e-005 +Ga120 ns120 0 ns119 0 -8.23637568024e-005 +Ca121 ns121 0 1e-012 +Ca122 ns122 0 1e-012 +Ra121 ns121 0 93866.819083 +Ra122 ns122 0 93866.819083 +Ga121 ns121 0 ns122 0 9.32385492882e-005 +Ga122 ns122 0 ns121 0 -9.32385492882e-005 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 80166.9541859 +Ra124 ns124 0 80166.9541859 +Ga123 ns123 0 ns124 0 0.000111704482203 +Ga124 ns124 0 ns123 0 -0.000111704482203 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 298584.146077 +Ra126 ns126 0 298584.146077 +Ga125 ns125 0 ns126 0 -0.000219173848946 +Ga126 ns126 0 ns125 0 0.000219173848946 +Ca127 ns127 0 1e-012 +Ca128 ns128 0 1e-012 +Ra127 ns127 0 31192.5022213 +Ra128 ns128 0 31192.5022213 +Ga127 ns127 0 ns128 0 -0.000318970158623 +Ga128 ns128 0 ns127 0 0.000318970158623 +Ca129 ns129 0 1e-012 +Ca130 ns130 0 1e-012 +Ra129 ns129 0 21769.1303288 +Ra130 ns130 0 21769.1303288 +Ga129 ns129 0 ns130 0 -0.000370728609904 +Ga130 ns130 0 ns129 0 0.000370728609904 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 39022.7928598 +Ra132 ns132 0 39022.7928598 +Ga131 ns131 0 ns132 0 -0.000405563076664 +Ga132 ns132 0 ns131 0 0.000405563076664 +Ca133 ns133 0 1e-012 +Ca134 ns134 0 1e-012 +Ra133 ns133 0 2139.64850026 +Ra134 ns134 0 2139.64850026 +Ga133 ns133 0 ns134 0 0.000217240575825 +Ga134 ns134 0 ns133 0 -0.000217240575825 +Ca135 ns135 0 1e-012 +Ca136 ns136 0 1e-012 +Ra135 ns135 0 33525.361311 +Ra136 ns136 0 33525.361311 +Ga135 ns135 0 ns136 0 0.000551177197672 +Ga136 ns136 0 ns135 0 -0.000551177197672 +Ca137 ns137 0 1e-012 +Ca138 ns138 0 1e-012 +Ra137 ns137 0 10899.5342598 +Ra138 ns138 0 10899.5342598 +Ga137 ns137 0 ns138 0 0.000580254710465 +Ga138 ns138 0 ns137 0 -0.000580254710465 +Ca139 ns139 0 1e-012 +Ca140 ns140 0 1e-012 +Ra139 ns139 0 10542.0213763 +Ra140 ns140 0 10542.0213763 +Ga139 ns139 0 ns140 0 0.000626215063344 +Ga140 ns140 0 ns139 0 -0.000626215063344 +Ca141 ns141 0 1e-012 +Ca142 ns142 0 1e-012 +Ra141 ns141 0 3956.67929269 +Ra142 ns142 0 3956.67929269 +Ga141 ns141 0 ns142 0 0.000583367859299 +Ga142 ns142 0 ns141 0 -0.000583367859299 +Ca143 ns143 0 1e-012 +Ca144 ns144 0 1e-012 +Ra143 ns143 0 12877.6101262 +Ra144 ns144 0 12877.6101262 +Ga143 ns143 0 ns144 0 0.000723077147846 +Ga144 ns144 0 ns143 0 -0.000723077147846 +Ca145 ns145 0 1e-012 +Ra145 ns145 0 234980401.203 +Ca146 ns146 0 1e-012 +Ra146 ns146 0 3686375.32141 +Ca147 ns147 0 1e-012 +Ca148 ns148 0 1e-012 +Ra147 ns147 0 860822.458334 +Ra148 ns148 0 860822.458334 +Ga147 ns147 0 ns148 0 -6.52058706256e-007 +Ga148 ns148 0 ns147 0 6.52058706256e-007 +Ca149 ns149 0 1e-012 +Ra149 ns149 0 501550.229785 +Ca150 ns150 0 1e-012 +Ra150 ns150 0 369596.750398 +Ca151 ns151 0 1e-012 +Ra151 ns151 0 113166.288146 +Ca152 ns152 0 1e-012 +Ca153 ns153 0 1e-012 +Ra152 ns152 0 1052511.07871 +Ra153 ns153 0 1052511.07871 +Ga152 ns152 0 ns153 0 -1.92482479923e-005 +Ga153 ns153 0 ns152 0 1.92482479923e-005 +Ca154 ns154 0 1e-012 +Ra154 ns154 0 15945.9215037 +Ca155 ns155 0 1e-012 +Ca156 ns156 0 1e-012 +Ra155 ns155 0 99686.9047432 +Ra156 ns156 0 99686.9047432 +Ga155 ns155 0 ns156 0 8.23637568024e-005 +Ga156 ns156 0 ns155 0 -8.23637568024e-005 +Ca157 ns157 0 1e-012 +Ca158 ns158 0 1e-012 +Ra157 ns157 0 93866.819083 +Ra158 ns158 0 93866.819083 +Ga157 ns157 0 ns158 0 9.32385492882e-005 +Ga158 ns158 0 ns157 0 -9.32385492882e-005 +Ca159 ns159 0 1e-012 +Ca160 ns160 0 1e-012 +Ra159 ns159 0 80166.9541859 +Ra160 ns160 0 80166.9541859 +Ga159 ns159 0 ns160 0 0.000111704482203 +Ga160 ns160 0 ns159 0 -0.000111704482203 +Ca161 ns161 0 1e-012 +Ca162 ns162 0 1e-012 +Ra161 ns161 0 298584.146077 +Ra162 ns162 0 298584.146077 +Ga161 ns161 0 ns162 0 -0.000219173848946 +Ga162 ns162 0 ns161 0 0.000219173848946 +Ca163 ns163 0 1e-012 +Ca164 ns164 0 1e-012 +Ra163 ns163 0 31192.5022213 +Ra164 ns164 0 31192.5022213 +Ga163 ns163 0 ns164 0 -0.000318970158623 +Ga164 ns164 0 ns163 0 0.000318970158623 +Ca165 ns165 0 1e-012 +Ca166 ns166 0 1e-012 +Ra165 ns165 0 21769.1303288 +Ra166 ns166 0 21769.1303288 +Ga165 ns165 0 ns166 0 -0.000370728609904 +Ga166 ns166 0 ns165 0 0.000370728609904 +Ca167 ns167 0 1e-012 +Ca168 ns168 0 1e-012 +Ra167 ns167 0 39022.7928598 +Ra168 ns168 0 39022.7928598 +Ga167 ns167 0 ns168 0 -0.000405563076664 +Ga168 ns168 0 ns167 0 0.000405563076664 +Ca169 ns169 0 1e-012 +Ca170 ns170 0 1e-012 +Ra169 ns169 0 2139.64850026 +Ra170 ns170 0 2139.64850026 +Ga169 ns169 0 ns170 0 0.000217240575825 +Ga170 ns170 0 ns169 0 -0.000217240575825 +Ca171 ns171 0 1e-012 +Ca172 ns172 0 1e-012 +Ra171 ns171 0 33525.361311 +Ra172 ns172 0 33525.361311 +Ga171 ns171 0 ns172 0 0.000551177197672 +Ga172 ns172 0 ns171 0 -0.000551177197672 +Ca173 ns173 0 1e-012 +Ca174 ns174 0 1e-012 +Ra173 ns173 0 10899.5342598 +Ra174 ns174 0 10899.5342598 +Ga173 ns173 0 ns174 0 0.000580254710465 +Ga174 ns174 0 ns173 0 -0.000580254710465 +Ca175 ns175 0 1e-012 +Ca176 ns176 0 1e-012 +Ra175 ns175 0 10542.0213763 +Ra176 ns176 0 10542.0213763 +Ga175 ns175 0 ns176 0 0.000626215063344 +Ga176 ns176 0 ns175 0 -0.000626215063344 +Ca177 ns177 0 1e-012 +Ca178 ns178 0 1e-012 +Ra177 ns177 0 3956.67929269 +Ra178 ns178 0 3956.67929269 +Ga177 ns177 0 ns178 0 0.000583367859299 +Ga178 ns178 0 ns177 0 -0.000583367859299 +Ca179 ns179 0 1e-012 +Ca180 ns180 0 1e-012 +Ra179 ns179 0 12877.6101262 +Ra180 ns180 0 12877.6101262 +Ga179 ns179 0 ns180 0 0.000723077147846 +Ga180 ns180 0 ns179 0 -0.000723077147846 +Ca181 ns181 0 1e-012 +Ra181 ns181 0 234980401.203 +Ca182 ns182 0 1e-012 +Ra182 ns182 0 3686375.32141 +Ca183 ns183 0 1e-012 +Ca184 ns184 0 1e-012 +Ra183 ns183 0 860822.458334 +Ra184 ns184 0 860822.458334 +Ga183 ns183 0 ns184 0 -6.52058706256e-007 +Ga184 ns184 0 ns183 0 6.52058706256e-007 +Ca185 ns185 0 1e-012 +Ra185 ns185 0 501550.229785 +Ca186 ns186 0 1e-012 +Ra186 ns186 0 369596.750398 +Ca187 ns187 0 1e-012 +Ra187 ns187 0 113166.288146 +Ca188 ns188 0 1e-012 +Ca189 ns189 0 1e-012 +Ra188 ns188 0 1052511.07871 +Ra189 ns189 0 1052511.07871 +Ga188 ns188 0 ns189 0 -1.92482479923e-005 +Ga189 ns189 0 ns188 0 1.92482479923e-005 +Ca190 ns190 0 1e-012 +Ra190 ns190 0 15945.9215037 +Ca191 ns191 0 1e-012 +Ca192 ns192 0 1e-012 +Ra191 ns191 0 99686.9047432 +Ra192 ns192 0 99686.9047432 +Ga191 ns191 0 ns192 0 8.23637568024e-005 +Ga192 ns192 0 ns191 0 -8.23637568024e-005 +Ca193 ns193 0 1e-012 +Ca194 ns194 0 1e-012 +Ra193 ns193 0 93866.819083 +Ra194 ns194 0 93866.819083 +Ga193 ns193 0 ns194 0 9.32385492882e-005 +Ga194 ns194 0 ns193 0 -9.32385492882e-005 +Ca195 ns195 0 1e-012 +Ca196 ns196 0 1e-012 +Ra195 ns195 0 80166.9541859 +Ra196 ns196 0 80166.9541859 +Ga195 ns195 0 ns196 0 0.000111704482203 +Ga196 ns196 0 ns195 0 -0.000111704482203 +Ca197 ns197 0 1e-012 +Ca198 ns198 0 1e-012 +Ra197 ns197 0 298584.146077 +Ra198 ns198 0 298584.146077 +Ga197 ns197 0 ns198 0 -0.000219173848946 +Ga198 ns198 0 ns197 0 0.000219173848946 +Ca199 ns199 0 1e-012 +Ca200 ns200 0 1e-012 +Ra199 ns199 0 31192.5022213 +Ra200 ns200 0 31192.5022213 +Ga199 ns199 0 ns200 0 -0.000318970158623 +Ga200 ns200 0 ns199 0 0.000318970158623 +Ca201 ns201 0 1e-012 +Ca202 ns202 0 1e-012 +Ra201 ns201 0 21769.1303288 +Ra202 ns202 0 21769.1303288 +Ga201 ns201 0 ns202 0 -0.000370728609904 +Ga202 ns202 0 ns201 0 0.000370728609904 +Ca203 ns203 0 1e-012 +Ca204 ns204 0 1e-012 +Ra203 ns203 0 39022.7928598 +Ra204 ns204 0 39022.7928598 +Ga203 ns203 0 ns204 0 -0.000405563076664 +Ga204 ns204 0 ns203 0 0.000405563076664 +Ca205 ns205 0 1e-012 +Ca206 ns206 0 1e-012 +Ra205 ns205 0 2139.64850026 +Ra206 ns206 0 2139.64850026 +Ga205 ns205 0 ns206 0 0.000217240575825 +Ga206 ns206 0 ns205 0 -0.000217240575825 +Ca207 ns207 0 1e-012 +Ca208 ns208 0 1e-012 +Ra207 ns207 0 33525.361311 +Ra208 ns208 0 33525.361311 +Ga207 ns207 0 ns208 0 0.000551177197672 +Ga208 ns208 0 ns207 0 -0.000551177197672 +Ca209 ns209 0 1e-012 +Ca210 ns210 0 1e-012 +Ra209 ns209 0 10899.5342598 +Ra210 ns210 0 10899.5342598 +Ga209 ns209 0 ns210 0 0.000580254710465 +Ga210 ns210 0 ns209 0 -0.000580254710465 +Ca211 ns211 0 1e-012 +Ca212 ns212 0 1e-012 +Ra211 ns211 0 10542.0213763 +Ra212 ns212 0 10542.0213763 +Ga211 ns211 0 ns212 0 0.000626215063344 +Ga212 ns212 0 ns211 0 -0.000626215063344 +Ca213 ns213 0 1e-012 +Ca214 ns214 0 1e-012 +Ra213 ns213 0 3956.67929269 +Ra214 ns214 0 3956.67929269 +Ga213 ns213 0 ns214 0 0.000583367859299 +Ga214 ns214 0 ns213 0 -0.000583367859299 +Ca215 ns215 0 1e-012 +Ca216 ns216 0 1e-012 +Ra215 ns215 0 12877.6101262 +Ra216 ns216 0 12877.6101262 +Ga215 ns215 0 ns216 0 0.000723077147846 +Ga216 ns216 0 ns215 0 -0.000723077147846 + +Gb1_1 ns1 0 ni1 0 4.25567406847e-009 +Gb2_1 ns2 0 ni1 0 2.71269177121e-007 +Gb3_1 ns3 0 ni1 0 1.52768470067e-006 +Gb5_1 ns5 0 ni1 0 1.99381824713e-006 +Gb6_1 ns6 0 ni1 0 2.7056514943e-006 +Gb7_1 ns7 0 ni1 0 8.83655385699e-006 +Gb8_1 ns8 0 ni1 0 1.92951461133e-005 +Gb10_1 ns10 0 ni1 0 6.27119605328e-005 +Gb11_1 ns11 0 ni1 0 8.35855216612e-005 +Gb13_1 ns13 0 ni1 0 9.445580071e-005 +Gb15_1 ns15 0 ni1 0 0.000113097442163 +Gb17_1 ns17 0 ni1 0 0.000219225026294 +Gb19_1 ns19 0 ni1 0 0.000322192336535 +Gb21_1 ns21 0 ni1 0 0.00037642056858 +Gb23_1 ns23 0 ni1 0 0.000407182293063 +Gb25_1 ns25 0 ni1 0 0.000568343918174 +Gb27_1 ns27 0 ni1 0 0.000552791414325 +Gb29_1 ns29 0 ni1 0 0.000594761304036 +Gb31_1 ns31 0 ni1 0 0.000640584134811 +Gb33_1 ns33 0 ni1 0 0.000692863240992 +Gb35_1 ns35 0 ni1 0 0.000731416740126 +Gb37_2 ns37 0 ni2 0 4.25567406847e-009 +Gb38_2 ns38 0 ni2 0 2.71269177121e-007 +Gb39_2 ns39 0 ni2 0 1.52768470067e-006 +Gb41_2 ns41 0 ni2 0 1.99381824713e-006 +Gb42_2 ns42 0 ni2 0 2.7056514943e-006 +Gb43_2 ns43 0 ni2 0 8.83655385699e-006 +Gb44_2 ns44 0 ni2 0 1.92951461133e-005 +Gb46_2 ns46 0 ni2 0 6.27119605328e-005 +Gb47_2 ns47 0 ni2 0 8.35855216612e-005 +Gb49_2 ns49 0 ni2 0 9.445580071e-005 +Gb51_2 ns51 0 ni2 0 0.000113097442163 +Gb53_2 ns53 0 ni2 0 0.000219225026294 +Gb55_2 ns55 0 ni2 0 0.000322192336535 +Gb57_2 ns57 0 ni2 0 0.00037642056858 +Gb59_2 ns59 0 ni2 0 0.000407182293063 +Gb61_2 ns61 0 ni2 0 0.000568343918174 +Gb63_2 ns63 0 ni2 0 0.000552791414325 +Gb65_2 ns65 0 ni2 0 0.000594761304036 +Gb67_2 ns67 0 ni2 0 0.000640584134811 +Gb69_2 ns69 0 ni2 0 0.000692863240992 +Gb71_2 ns71 0 ni2 0 0.000731416740126 +Gb73_3 ns73 0 ni3 0 4.25567406847e-009 +Gb74_3 ns74 0 ni3 0 2.71269177121e-007 +Gb75_3 ns75 0 ni3 0 1.52768470067e-006 +Gb77_3 ns77 0 ni3 0 1.99381824713e-006 +Gb78_3 ns78 0 ni3 0 2.7056514943e-006 +Gb79_3 ns79 0 ni3 0 8.83655385699e-006 +Gb80_3 ns80 0 ni3 0 1.92951461133e-005 +Gb82_3 ns82 0 ni3 0 6.27119605328e-005 +Gb83_3 ns83 0 ni3 0 8.35855216612e-005 +Gb85_3 ns85 0 ni3 0 9.445580071e-005 +Gb87_3 ns87 0 ni3 0 0.000113097442163 +Gb89_3 ns89 0 ni3 0 0.000219225026294 +Gb91_3 ns91 0 ni3 0 0.000322192336535 +Gb93_3 ns93 0 ni3 0 0.00037642056858 +Gb95_3 ns95 0 ni3 0 0.000407182293063 +Gb97_3 ns97 0 ni3 0 0.000568343918174 +Gb99_3 ns99 0 ni3 0 0.000552791414325 +Gb101_3 ns101 0 ni3 0 0.000594761304036 +Gb103_3 ns103 0 ni3 0 0.000640584134811 +Gb105_3 ns105 0 ni3 0 0.000692863240992 +Gb107_3 ns107 0 ni3 0 0.000731416740126 +Gb109_4 ns109 0 ni4 0 4.25567406847e-009 +Gb110_4 ns110 0 ni4 0 2.71269177121e-007 +Gb111_4 ns111 0 ni4 0 1.52768470067e-006 +Gb113_4 ns113 0 ni4 0 1.99381824713e-006 +Gb114_4 ns114 0 ni4 0 2.7056514943e-006 +Gb115_4 ns115 0 ni4 0 8.83655385699e-006 +Gb116_4 ns116 0 ni4 0 1.92951461133e-005 +Gb118_4 ns118 0 ni4 0 6.27119605328e-005 +Gb119_4 ns119 0 ni4 0 8.35855216612e-005 +Gb121_4 ns121 0 ni4 0 9.445580071e-005 +Gb123_4 ns123 0 ni4 0 0.000113097442163 +Gb125_4 ns125 0 ni4 0 0.000219225026294 +Gb127_4 ns127 0 ni4 0 0.000322192336535 +Gb129_4 ns129 0 ni4 0 0.00037642056858 +Gb131_4 ns131 0 ni4 0 0.000407182293063 +Gb133_4 ns133 0 ni4 0 0.000568343918174 +Gb135_4 ns135 0 ni4 0 0.000552791414325 +Gb137_4 ns137 0 ni4 0 0.000594761304036 +Gb139_4 ns139 0 ni4 0 0.000640584134811 +Gb141_4 ns141 0 ni4 0 0.000692863240992 +Gb143_4 ns143 0 ni4 0 0.000731416740126 +Gb145_5 ns145 0 ni5 0 4.25567406847e-009 +Gb146_5 ns146 0 ni5 0 2.71269177121e-007 +Gb147_5 ns147 0 ni5 0 1.52768470067e-006 +Gb149_5 ns149 0 ni5 0 1.99381824713e-006 +Gb150_5 ns150 0 ni5 0 2.7056514943e-006 +Gb151_5 ns151 0 ni5 0 8.83655385699e-006 +Gb152_5 ns152 0 ni5 0 1.92951461133e-005 +Gb154_5 ns154 0 ni5 0 6.27119605328e-005 +Gb155_5 ns155 0 ni5 0 8.35855216612e-005 +Gb157_5 ns157 0 ni5 0 9.445580071e-005 +Gb159_5 ns159 0 ni5 0 0.000113097442163 +Gb161_5 ns161 0 ni5 0 0.000219225026294 +Gb163_5 ns163 0 ni5 0 0.000322192336535 +Gb165_5 ns165 0 ni5 0 0.00037642056858 +Gb167_5 ns167 0 ni5 0 0.000407182293063 +Gb169_5 ns169 0 ni5 0 0.000568343918174 +Gb171_5 ns171 0 ni5 0 0.000552791414325 +Gb173_5 ns173 0 ni5 0 0.000594761304036 +Gb175_5 ns175 0 ni5 0 0.000640584134811 +Gb177_5 ns177 0 ni5 0 0.000692863240992 +Gb179_5 ns179 0 ni5 0 0.000731416740126 +Gb181_6 ns181 0 ni6 0 4.25567406847e-009 +Gb182_6 ns182 0 ni6 0 2.71269177121e-007 +Gb183_6 ns183 0 ni6 0 1.52768470067e-006 +Gb185_6 ns185 0 ni6 0 1.99381824713e-006 +Gb186_6 ns186 0 ni6 0 2.7056514943e-006 +Gb187_6 ns187 0 ni6 0 8.83655385699e-006 +Gb188_6 ns188 0 ni6 0 1.92951461133e-005 +Gb190_6 ns190 0 ni6 0 6.27119605328e-005 +Gb191_6 ns191 0 ni6 0 8.35855216612e-005 +Gb193_6 ns193 0 ni6 0 9.445580071e-005 +Gb195_6 ns195 0 ni6 0 0.000113097442163 +Gb197_6 ns197 0 ni6 0 0.000219225026294 +Gb199_6 ns199 0 ni6 0 0.000322192336535 +Gb201_6 ns201 0 ni6 0 0.00037642056858 +Gb203_6 ns203 0 ni6 0 0.000407182293063 +Gb205_6 ns205 0 ni6 0 0.000568343918174 +Gb207_6 ns207 0 ni6 0 0.000552791414325 +Gb209_6 ns209 0 ni6 0 0.000594761304036 +Gb211_6 ns211 0 ni6 0 0.000640584134811 +Gb213_6 ns213 0 ni6 0 0.000692863240992 +Gb215_6 ns215 0 ni6 0 0.000731416740126 + +Gc1_1 0 n2 ns1 0 0.00637361219658 +Gc1_2 0 n2 ns2 0 0.000152560737479 +Gc1_3 0 n2 ns3 0 -0.000248148741404 +Gc1_4 0 n2 ns4 0 -1.87137091691e-005 +Gc1_5 0 n2 ns5 0 0.00698731941562 +Gc1_6 0 n2 ns6 0 0.00622107175532 +Gc1_7 0 n2 ns7 0 5.75084031134e-005 +Gc1_8 0 n2 ns8 0 -1.05588987835e-006 +Gc1_9 0 n2 ns9 0 -5.98411823371e-007 +Gc1_10 0 n2 ns10 0 -0.000250519048293 +Gc1_11 0 n2 ns11 0 -9.48570016845e-007 +Gc1_12 0 n2 ns12 0 -2.12476102785e-005 +Gc1_13 0 n2 ns13 0 0.00120466018079 +Gc1_14 0 n2 ns14 0 0.000291721877554 +Gc1_15 0 n2 ns15 0 0.00135756058471 +Gc1_16 0 n2 ns16 0 0.000757240769775 +Gc1_17 0 n2 ns17 0 5.65096528065e-007 +Gc1_18 0 n2 ns18 0 2.76255774711e-007 +Gc1_19 0 n2 ns19 0 -6.83989719636e-007 +Gc1_20 0 n2 ns20 0 -2.67688982794e-005 +Gc1_21 0 n2 ns21 0 6.13410014972e-005 +Gc1_22 0 n2 ns22 0 -5.01848027111e-005 +Gc1_23 0 n2 ns23 0 8.91857477548e-005 +Gc1_24 0 n2 ns24 0 -0.000107900156229 +Gc1_25 0 n2 ns25 0 -0.0254168450931 +Gc1_26 0 n2 ns26 0 -0.0275143658016 +Gc1_27 0 n2 ns27 0 8.94407791508e-006 +Gc1_28 0 n2 ns28 0 -3.62465502256e-006 +Gc1_29 0 n2 ns29 0 -9.76781605161e-005 +Gc1_30 0 n2 ns30 0 -0.000222112032292 +Gc1_31 0 n2 ns31 0 -0.00241728819137 +Gc1_32 0 n2 ns32 0 0.00269611432739 +Gc1_33 0 n2 ns33 0 0.0135559998419 +Gc1_34 0 n2 ns34 0 0.0094073411538 +Gc1_35 0 n2 ns35 0 -0.0010336629319 +Gc1_36 0 n2 ns36 0 -0.00249055350302 +Gc1_37 0 n2 ns37 0 0.00612690465432 +Gc1_38 0 n2 ns38 0 -7.30231806349e-005 +Gc1_39 0 n2 ns39 0 0.000102968365101 +Gc1_40 0 n2 ns40 0 2.0724598309e-006 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0.00044848770982 +Gc1_67 0 n2 ns67 0 0.000672398011738 +Gc1_68 0 n2 ns68 0 -0.00124742898077 +Gc1_69 0 n2 ns69 0 -0.00162474486537 +Gc1_70 0 n2 ns70 0 0.000750507922749 +Gc1_71 0 n2 ns71 0 -3.02464375143e-005 +Gc1_72 0 n2 ns72 0 0.000919787810224 +Gc1_73 0 n2 ns73 0 0.00611687297013 +Gc1_74 0 n2 ns74 0 -8.01008056059e-005 +Gc1_75 0 n2 ns75 0 0.000109179431985 +Gc1_76 0 n2 ns76 0 1.51168429538e-005 +Gc1_77 0 n2 ns77 0 -0.00396468227039 +Gc1_78 0 n2 ns78 0 -0.00263265754628 +Gc1_79 0 n2 ns79 0 -3.08298587777e-005 +Gc1_80 0 n2 ns80 0 1.54740178343e-007 +Gc1_81 0 n2 ns81 0 4.26336911797e-007 +Gc1_82 0 n2 ns82 0 -5.99261019517e-006 +Gc1_83 0 n2 ns83 0 -0.00016261243704 +Gc1_84 0 n2 ns84 0 4.44343536201e-005 +Gc1_85 0 n2 ns85 0 -0.000457868314519 +Gc1_86 0 n2 ns86 0 -0.000154072582739 +Gc1_87 0 n2 ns87 0 0.00071124312164 +Gc1_88 0 n2 ns88 0 0.00030159667742 +Gc1_89 0 n2 ns89 0 3.88561526864e-007 +Gc1_90 0 n2 ns90 0 -3.66192476702e-008 +Gc1_91 0 n2 ns91 0 -3.0368197154e-005 +Gc1_92 0 n2 ns92 0 0.000158703625038 +Gc1_93 0 n2 ns93 0 5.40308550075e-005 +Gc1_94 0 n2 ns94 0 -6.30975483822e-005 +Gc1_95 0 n2 ns95 0 -4.39197475012e-005 +Gc1_96 0 n2 ns96 0 0.000125568974086 +Gc1_97 0 n2 ns97 0 0.000970387021346 +Gc1_98 0 n2 ns98 0 -0.000417022676439 +Gc1_99 0 n2 ns99 0 9.48030987703e-006 +Gc1_100 0 n2 ns100 0 1.68779845943e-006 +Gc1_101 0 n2 ns101 0 -0.00116226542431 +Gc1_102 0 n2 ns102 0 -0.0009035571994 +Gc1_103 0 n2 ns103 0 0.00244532178168 +Gc1_104 0 n2 ns104 0 -0.000461138062645 +Gc1_105 0 n2 ns105 0 -0.00229778264343 +Gc1_106 0 n2 ns106 0 0.000860271057341 +Gc1_107 0 n2 ns107 0 -0.000914934707046 +Gc1_108 0 n2 ns108 0 0.000305246342179 +Gc1_109 0 n2 ns109 0 -0.00636907247221 +Gc1_110 0 n2 ns110 0 -0.000153808567906 +Gc1_111 0 n2 ns111 0 0.000234476202623 +Gc1_112 0 n2 ns112 0 1.80214440471e-005 +Gc1_113 0 n2 ns113 0 -0.0069379350964 +Gc1_114 0 n2 ns114 0 -0.00625146385581 +Gc1_115 0 n2 ns115 0 -5.4909302483e-005 +Gc1_116 0 n2 ns116 0 6.38473635873e-007 +Gc1_117 0 n2 ns117 0 9.36103633821e-007 +Gc1_118 0 n2 ns118 0 8.84454030796e-005 +Gc1_119 0 n2 ns119 0 7.56059010196e-006 +Gc1_120 0 n2 ns120 0 2.96350250932e-006 +Gc1_121 0 n2 ns121 0 -0.00109106734755 +Gc1_122 0 n2 ns122 0 -0.000263898855078 +Gc1_123 0 n2 ns123 0 -0.001352680726 +Gc1_124 0 n2 ns124 0 -0.000733934651212 +Gc1_125 0 n2 ns125 0 1.98196013568e-007 +Gc1_126 0 n2 ns126 0 -5.93491455656e-007 +Gc1_127 0 n2 ns127 0 -1.71432366187e-006 +Gc1_128 0 n2 ns128 0 1.5684922483e-005 +Gc1_129 0 n2 ns129 0 -3.42135933563e-005 +Gc1_130 0 n2 ns130 0 1.9846187001e-005 +Gc1_131 0 n2 ns131 0 9.39219949228e-005 +Gc1_132 0 n2 ns132 0 -0.000152769416309 +Gc1_133 0 n2 ns133 0 0.0056644305049 +Gc1_134 0 n2 ns134 0 0.0228179898293 +Gc1_135 0 n2 ns135 0 -1.3264149778e-005 +Gc1_136 0 n2 ns136 0 -3.12449114016e-006 +Gc1_137 0 n2 ns137 0 0.000539412664894 +Gc1_138 0 n2 ns138 0 0.000676074821088 +Gc1_139 0 n2 ns139 0 0.00301518212948 +Gc1_140 0 n2 ns140 0 -0.000111779530892 +Gc1_141 0 n2 ns141 0 -0.00994221773021 +Gc1_142 0 n2 ns142 0 -0.0143863291463 +Gc1_143 0 n2 ns143 0 -0.00153171219005 +Gc1_144 0 n2 ns144 0 -3.68364601194e-005 +Gc1_145 0 n2 ns145 0 -0.00614883335149 +Gc1_146 0 n2 ns146 0 7.2853008993e-005 +Gc1_147 0 n2 ns147 0 -0.000105917393946 +Gc1_148 0 n2 ns148 0 2.71834062931e-006 +Gc1_149 0 n2 ns149 0 0.00307610861322 +Gc1_150 0 n2 ns150 0 0.00352771827629 +Gc1_151 0 n2 ns151 0 4.25082380008e-005 +Gc1_152 0 n2 ns152 0 9.13293723519e-008 +Gc1_153 0 n2 ns153 0 -4.33376208364e-007 +Gc1_154 0 n2 ns154 0 3.83656346458e-006 +Gc1_155 0 n2 ns155 0 -5.93491956102e-005 +Gc1_156 0 n2 ns156 0 1.75375001917e-005 +Gc1_157 0 n2 ns157 0 0.00122047609913 +Gc1_158 0 n2 ns158 0 0.000290240242177 +Gc1_159 0 n2 ns159 0 -0.0012349745626 +Gc1_160 0 n2 ns160 0 -0.000549858929277 +Gc1_161 0 n2 ns161 0 2.14888649034e-007 +Gc1_162 0 n2 ns162 0 -2.8896128632e-007 +Gc1_163 0 n2 ns163 0 -1.74354898261e-006 +Gc1_164 0 n2 ns164 0 -2.42969808695e-005 +Gc1_165 0 n2 ns165 0 9.77337441266e-005 +Gc1_166 0 n2 ns166 0 -0.000177528423552 +Gc1_167 0 n2 ns167 0 -4.1030812679e-006 +Gc1_168 0 n2 ns168 0 -3.43149863515e-008 +Gc1_169 0 n2 ns169 0 0.000253361106553 +Gc1_170 0 n2 ns170 0 0.00117189672146 +Gc1_171 0 n2 ns171 0 -8.54003177846e-006 +Gc1_172 0 n2 ns172 0 -2.71679653879e-006 +Gc1_173 0 n2 ns173 0 0.000860904108153 +Gc1_174 0 n2 ns174 0 5.51305481359e-005 +Gc1_175 0 n2 ns175 0 -0.00180700233418 +Gc1_176 0 n2 ns176 0 -0.000121939396277 +Gc1_177 0 n2 ns177 0 -0.00220207832875 +Gc1_178 0 n2 ns178 0 -0.000728485597524 +Gc1_179 0 n2 ns179 0 0.00132989152619 +Gc1_180 0 n2 ns180 0 0.000652836498266 +Gc1_181 0 n2 ns181 0 -0.00614667679944 +Gc1_182 0 n2 ns182 0 7.89924344867e-005 +Gc1_183 0 n2 ns183 0 -0.000124198961472 +Gc1_184 0 n2 ns184 0 -3.96622722657e-006 +Gc1_185 0 n2 ns185 0 0.00403550737749 +Gc1_186 0 n2 ns186 0 0.00257209752714 +Gc1_187 0 n2 ns187 0 4.09076615409e-005 +Gc1_188 0 n2 ns188 0 1.05148086622e-007 +Gc1_189 0 n2 ns189 0 -4.23204303674e-007 +Gc1_190 0 n2 ns190 0 4.99659534951e-006 +Gc1_191 0 n2 ns191 0 0.000149740688274 +Gc1_192 0 n2 ns192 0 -4.1904049678e-005 +Gc1_193 0 n2 ns193 0 0.000486773486177 +Gc1_194 0 n2 ns194 0 0.00015330786579 +Gc1_195 0 n2 ns195 0 -0.00076432700893 +Gc1_196 0 n2 ns196 0 -0.000320006787563 +Gc1_197 0 n2 ns197 0 2.1161456214e-007 +Gc1_198 0 n2 ns198 0 -1.40788619635e-007 +Gc1_199 0 n2 ns199 0 2.19733771424e-005 +Gc1_200 0 n2 ns200 0 -0.000130697125202 +Gc1_201 0 n2 ns201 0 5.34293377615e-008 +Gc1_202 0 n2 ns202 0 2.29583247494e-005 +Gc1_203 0 n2 ns203 0 -2.00098423223e-005 +Gc1_204 0 n2 ns204 0 1.15695728084e-005 +Gc1_205 0 n2 ns205 0 -0.000495763684591 +Gc1_206 0 n2 ns206 0 0.00126240171586 +Gc1_207 0 n2 ns207 0 -4.13229455892e-006 +Gc1_208 0 n2 ns208 0 -4.43761544326e-006 +Gc1_209 0 n2 ns209 0 0.000308581034786 +Gc1_210 0 n2 ns210 0 0.000374374105266 +Gc1_211 0 n2 ns211 0 -0.00123806200666 +Gc1_212 0 n2 ns212 0 -0.00060457498806 +Gc1_213 0 n2 ns213 0 -0.00145652803195 +Gc1_214 0 n2 ns214 0 -0.000196935312199 +Gc1_215 0 n2 ns215 0 0.000856917567772 +Gc1_216 0 n2 ns216 0 0.000773938539658 +Gd1_1 0 n2 ni1 0 -0.00243943208532 +Gd1_2 0 n2 ni2 0 -0.000744346598569 +Gd1_3 0 n2 ni3 0 -0.000473868118316 +Gd1_4 0 n2 ni4 0 -0.00276198449897 +Gd1_5 0 n2 ni5 0 -0.000202417041964 +Gd1_6 0 n2 ni6 0 -0.000241684316663 +Gc2_1 0 n4 ns1 0 0.00613145559704 +Gc2_2 0 n4 ns2 0 -7.28113958036e-005 +Gc2_3 0 n4 ns3 0 0.000105582311356 +Gc2_4 0 n4 ns4 0 1.14243830634e-006 +Gc2_5 0 n4 ns5 0 -0.00306239705577 +Gc2_6 0 n4 ns6 0 -0.00354774926124 +Gc2_7 0 n4 ns7 0 -3.63901758392e-005 +Gc2_8 0 n4 ns8 0 1.3010429067e-007 +Gc2_9 0 n4 ns9 0 4.40676776519e-007 +Gc2_10 0 n4 ns10 0 2.92183405284e-006 +Gc2_11 0 n4 ns11 0 6.72828943772e-005 +Gc2_12 0 n4 ns12 0 -1.94977478132e-005 +Gc2_13 0 n4 ns13 0 -0.00139148159706 +Gc2_14 0 n4 ns14 0 -0.000317837232293 +Gc2_15 0 n4 ns15 0 0.00127919745267 +Gc2_16 0 n4 ns16 0 0.000552795605117 +Gc2_17 0 n4 ns17 0 2.65197386244e-007 +Gc2_18 0 n4 ns18 0 -1.17050585936e-007 +Gc2_19 0 n4 ns19 0 5.77472890958e-006 +Gc2_20 0 n4 ns20 0 1.29473346864e-005 +Gc2_21 0 n4 ns21 0 -0.000198946220022 +Gc2_22 0 n4 ns22 0 0.000253154636671 +Gc2_23 0 n4 ns23 0 -7.35419827793e-005 +Gc2_24 0 n4 ns24 0 9.10808132093e-005 +Gc2_25 0 n4 ns25 0 -0.000212462161686 +Gc2_26 0 n4 ns26 0 -0.000529855315457 +Gc2_27 0 n4 ns27 0 6.3101037673e-006 +Gc2_28 0 n4 ns28 0 -6.31904790289e-006 +Gc2_29 0 n4 ns29 0 -0.000823126488292 +Gc2_30 0 n4 ns30 0 0.0004436771 +Gc2_31 0 n4 ns31 0 0.000653557737623 +Gc2_32 0 n4 ns32 0 -0.00127610748747 +Gc2_33 0 n4 ns33 0 -0.0015575642577 +Gc2_34 0 n4 ns34 0 0.000707145375198 +Gc2_35 0 n4 ns35 0 -6.22175389836e-005 +Gc2_36 0 n4 ns36 0 0.000911219143565 +Gc2_37 0 n4 ns37 0 0.0063783406279 +Gc2_38 0 n4 ns38 0 0.000150260628796 +Gc2_39 0 n4 ns39 0 -0.000198643723746 +Gc2_40 0 n4 ns40 0 -2.10101738342e-005 +Gc2_41 0 n4 ns41 0 0.00673699820409 +Gc2_42 0 n4 ns42 0 0.00642423708937 +Gc2_43 0 n4 ns43 0 4.08979298773e-005 +Gc2_44 0 n4 ns44 0 -1.27447138419e-006 +Gc2_45 0 n4 ns45 0 -9.03833469389e-007 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0 n4 ns72 0 -0.000512310090088 +Gc2_73 0 n4 ns73 0 0.00629269080747 +Gc2_74 0 n4 ns74 0 -7.20336818464e-005 +Gc2_75 0 n4 ns75 0 0.000123562901261 +Gc2_76 0 n4 ns76 0 -1.84138097183e-005 +Gc2_77 0 n4 ns77 0 -0.00392442429359 +Gc2_78 0 n4 ns78 0 -0.00271249390532 +Gc2_79 0 n4 ns79 0 -3.36833111007e-005 +Gc2_80 0 n4 ns80 0 1.14659839036e-008 +Gc2_81 0 n4 ns81 0 3.36953962867e-007 +Gc2_82 0 n4 ns82 0 8.81256543381e-006 +Gc2_83 0 n4 ns83 0 -0.00118130337845 +Gc2_84 0 n4 ns84 0 -0.000139360782014 +Gc2_85 0 n4 ns85 0 0.000529952269209 +Gc2_86 0 n4 ns86 0 0.000169154961022 +Gc2_87 0 n4 ns87 0 0.000665639848615 +Gc2_88 0 n4 ns88 0 0.000200771465512 +Gc2_89 0 n4 ns89 0 3.14463924305e-007 +Gc2_90 0 n4 ns90 0 -2.43543233507e-007 +Gc2_91 0 n4 ns91 0 6.28707402818e-005 +Gc2_92 0 n4 ns92 0 -0.000227439362956 +Gc2_93 0 n4 ns93 0 -0.000338427698624 +Gc2_94 0 n4 ns94 0 0.000863081459358 +Gc2_95 0 n4 ns95 0 5.24078088006e-005 +Gc2_96 0 n4 ns96 0 -9.81830486807e-005 +Gc2_97 0 n4 ns97 0 -0.00190575606258 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n4 ni5 0 -0.00243524902505 +Gd2_6 0 n4 ni6 0 0.000139075083101 +Gc3_1 0 n6 ns1 0 0.00612004041786 +Gc3_2 0 n6 ns2 0 -7.93018830635e-005 +Gc3_3 0 n6 ns3 0 0.000121344991222 +Gc3_4 0 n6 ns4 0 8.39480892844e-006 +Gc3_5 0 n6 ns5 0 -0.00401584453058 +Gc3_6 0 n6 ns6 0 -0.0025939092182 +Gc3_7 0 n6 ns7 0 -3.59473560422e-005 +Gc3_8 0 n6 ns8 0 1.21413940345e-007 +Gc3_9 0 n6 ns9 0 4.34459819066e-007 +Gc3_10 0 n6 ns10 0 6.34514485667e-006 +Gc3_11 0 n6 ns11 0 -0.000162631342964 +Gc3_12 0 n6 ns12 0 4.64481418365e-005 +Gc3_13 0 n6 ns13 0 -0.000455298081254 +Gc3_14 0 n6 ns14 0 -0.00015405475315 +Gc3_15 0 n6 ns15 0 0.000711410241064 +Gc3_16 0 n6 ns16 0 0.000300398426338 +Gc3_17 0 n6 ns17 0 3.32610451496e-007 +Gc3_18 0 n6 ns18 0 -3.97736061715e-008 +Gc3_19 0 n6 ns19 0 -2.94923574264e-005 +Gc3_20 0 n6 ns20 0 0.000159319774494 +Gc3_21 0 n6 ns21 0 5.49246177045e-005 +Gc3_22 0 n6 ns22 0 -5.98680518874e-005 +Gc3_23 0 n6 ns23 0 -4.4469146468e-005 +Gc3_24 0 n6 ns24 0 0.000125841515546 +Gc3_25 0 n6 ns25 0 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n8 ns4 0 2.31477281542e-005 +Gc4_5 0 n8 ns5 0 -0.00688360598883 +Gc4_6 0 n8 ns6 0 -0.00629561574017 +Gc4_7 0 n8 ns7 0 -4.93095449473e-005 +Gc4_8 0 n8 ns8 0 6.16061662772e-007 +Gc4_9 0 n8 ns9 0 9.21560259959e-007 +Gc4_10 0 n8 ns10 0 8.50107084624e-005 +Gc4_11 0 n8 ns11 0 7.45632017521e-006 +Gc4_12 0 n8 ns12 0 1.99245560255e-006 +Gc4_13 0 n8 ns13 0 -0.0010912671185 +Gc4_14 0 n8 ns14 0 -0.000263314793921 +Gc4_15 0 n8 ns15 0 -0.00135224607994 +Gc4_16 0 n8 ns16 0 -0.000732979472497 +Gc4_17 0 n8 ns17 0 2.18886905036e-007 +Gc4_18 0 n8 ns18 0 -5.94291487344e-007 +Gc4_19 0 n8 ns19 0 -1.89613704464e-006 +Gc4_20 0 n8 ns20 0 1.49707451763e-005 +Gc4_21 0 n8 ns21 0 -3.29215053663e-005 +Gc4_22 0 n8 ns22 0 1.78991010718e-005 +Gc4_23 0 n8 ns23 0 9.44833581108e-005 +Gc4_24 0 n8 ns24 0 -0.000152623639744 +Gc4_25 0 n8 ns25 0 0.0057809287945 +Gc4_26 0 n8 ns26 0 0.0228575035173 +Gc4_27 0 n8 ns27 0 -1.30537678188e-005 +Gc4_28 0 n8 ns28 0 -2.93635566189e-006 +Gc4_29 0 n8 ns29 0 0.000561160730795 +Gc4_30 0 n8 ns30 0 0.000657140680316 +Gc4_31 0 n8 ns31 0 0.0029746289663 +Gc4_32 0 n8 ns32 0 -0.000169756098738 +Gc4_33 0 n8 ns33 0 -0.00973116705088 +Gc4_34 0 n8 ns34 0 -0.0144063038714 +Gc4_35 0 n8 ns35 0 -0.00159049556884 +Gc4_36 0 n8 ns36 0 -6.34563829682e-005 +Gc4_37 0 n8 ns37 0 -0.00613209526979 +Gc4_38 0 n8 ns38 0 7.3684713601e-005 +Gc4_39 0 n8 ns39 0 -7.94738031735e-005 +Gc4_40 0 n8 ns40 0 -1.59460282744e-005 +Gc4_41 0 n8 ns41 0 0.00295511748197 +Gc4_42 0 n8 ns42 0 0.00362516389016 +Gc4_43 0 n8 ns43 0 3.0995142905e-005 +Gc4_44 0 n8 ns44 0 -6.49926024777e-008 +Gc4_45 0 n8 ns45 0 -2.79979200685e-007 +Gc4_46 0 n8 ns46 0 3.10220112658e-005 +Gc4_47 0 n8 ns47 0 -2.57790160335e-005 +Gc4_48 0 n8 ns48 0 2.76674479061e-005 +Gc4_49 0 n8 ns49 0 0.00124650085917 +Gc4_50 0 n8 ns50 0 0.000287050878725 +Gc4_51 0 n8 ns51 0 -0.00126614502511 +Gc4_52 0 n8 ns52 0 -0.00053779607937 +Gc4_53 0 n8 ns53 0 7.68409018923e-008 +Gc4_54 0 n8 ns54 0 -1.90217524454e-007 +Gc4_55 0 n8 ns55 0 -2.76005754369e-006 +Gc4_56 0 n8 ns56 0 1.06432773114e-006 +Gc4_57 0 n8 ns57 0 -0.000128126622065 +Gc4_58 0 n8 ns58 0 0.000272919471583 +Gc4_59 0 n8 ns59 0 -0.000105895596092 +Gc4_60 0 n8 ns60 0 0.00011734799962 +Gc4_61 0 n8 ns61 0 0.000673787857024 +Gc4_62 0 n8 ns62 0 -3.76714437616e-006 +Gc4_63 0 n8 ns63 0 -5.93148474993e-006 +Gc4_64 0 n8 ns64 0 -7.50733175955e-006 +Gc4_65 0 n8 ns65 0 0.000349495535778 +Gc4_66 0 n8 ns66 0 0.000442421144088 +Gc4_67 0 n8 ns67 0 -0.00122814197133 +Gc4_68 0 n8 ns68 0 -0.000184683138119 +Gc4_69 0 n8 ns69 0 -0.000832570656783 +Gc4_70 0 n8 ns70 0 -7.68210948596e-005 +Gc4_71 0 n8 ns71 0 0.000503910829925 +Gc4_72 0 n8 ns72 0 1.57456868482e-005 +Gc4_73 0 n8 ns73 0 -0.00611593039928 +Gc4_74 0 n8 ns74 0 8.09986368152e-005 +Gc4_75 0 n8 ns75 0 -8.29367302628e-005 +Gc4_76 0 n8 ns76 0 -2.95416673489e-005 +Gc4_77 0 n8 ns77 0 0.00385805077784 +Gc4_78 0 n8 ns78 0 0.00270691121206 +Gc4_79 0 n8 ns79 0 2.69163680692e-005 +Gc4_80 0 n8 ns80 0 -1.23533630139e-007 +Gc4_81 0 n8 ns81 0 -2.74855911744e-007 +Gc4_82 0 n8 ns82 0 3.83983439297e-005 +Gc4_83 0 n8 ns83 0 5.59395245556e-005 +Gc4_84 0 n8 ns84 0 -5.07135792978e-005 +Gc4_85 0 n8 ns85 0 0.000412676117409 +Gc4_86 0 n8 ns86 0 0.000139316539667 +Gc4_87 0 n8 ns87 0 -0.000702611848718 +Gc4_88 0 n8 ns88 0 -0.000292699017804 +Gc4_89 0 n8 ns89 0 1.14498894628e-007 +Gc4_90 0 n8 ns90 0 -9.61417109438e-008 +Gc4_91 0 n8 ns91 0 -5.36374677836e-005 +Gc4_92 0 n8 ns92 0 -3.36572490176e-005 +Gc4_93 0 n8 ns93 0 3.39557640891e-005 +Gc4_94 0 n8 ns94 0 -3.71534149635e-005 +Gc4_95 0 n8 ns95 0 -7.01088211401e-005 +Gc4_96 0 n8 ns96 0 0.000166477298351 +Gc4_97 0 n8 ns97 0 0.000778757906944 +Gc4_98 0 n8 ns98 0 -0.000512339549751 +Gc4_99 0 n8 ns99 0 -9.04836507704e-007 +Gc4_100 0 n8 ns100 0 -1.0682792043e-005 +Gc4_101 0 n8 ns101 0 -0.000425723257361 +Gc4_102 0 n8 ns102 0 0.000945273012727 +Gc4_103 0 n8 ns103 0 -0.00110218981425 +Gc4_104 0 n8 ns104 0 -0.00185711964018 +Gc4_105 0 n8 ns105 0 -0.000100784321783 +Gc4_106 0 n8 ns106 0 -0.000184216540183 +Gc4_107 0 n8 ns107 0 0.000300750510868 +Gc4_108 0 n8 ns108 0 0.00078899054764 +Gc4_109 0 n8 ns109 0 0.00628405073277 +Gc4_110 0 n8 ns110 0 0.000157996112179 +Gc4_111 0 n8 ns111 0 -0.000149234768509 +Gc4_112 0 n8 ns112 0 -6.45928649491e-005 +Gc4_113 0 n8 ns113 0 0.00663387020171 +Gc4_114 0 n8 ns114 0 0.00643891877259 +Gc4_115 0 n8 ns115 0 5.34675895589e-005 +Gc4_116 0 n8 ns116 0 -2.39937152775e-006 +Gc4_117 0 n8 ns117 0 8.9540904049e-007 +Gc4_118 0 n8 ns118 0 -0.000157263856894 +Gc4_119 0 n8 ns119 0 -1.64455067303e-005 +Gc4_120 0 n8 ns120 0 4.68669671714e-007 +Gc4_121 0 n8 ns121 0 0.000976554149741 +Gc4_122 0 n8 ns122 0 0.000243253251014 +Gc4_123 0 n8 ns123 0 0.00134433598066 +Gc4_124 0 n8 ns124 0 0.000712968845574 +Gc4_125 0 n8 ns125 0 -5.43468448179e-008 +Gc4_126 0 n8 ns126 0 5.49846060574e-007 +Gc4_127 0 n8 ns127 0 1.33281612225e-005 +Gc4_128 0 n8 ns128 0 -1.26944428093e-005 +Gc4_129 0 n8 ns129 0 7.58703445051e-005 +Gc4_130 0 n8 ns130 0 -3.54048805591e-005 +Gc4_131 0 n8 ns131 0 0.000156404912581 +Gc4_132 0 n8 ns132 0 -0.000181631275117 +Gc4_133 0 n8 ns133 0 -0.0172008160982 +Gc4_134 0 n8 ns134 0 -0.0332141955223 +Gc4_135 0 n8 ns135 0 6.8132092102e-006 +Gc4_136 0 n8 ns136 0 -6.24952222619e-006 +Gc4_137 0 n8 ns137 0 -0.000338332552284 +Gc4_138 0 n8 ns138 0 -0.000766085994604 +Gc4_139 0 n8 ns139 0 -0.0012164475979 +Gc4_140 0 n8 ns140 0 -0.00143550117285 +Gc4_141 0 n8 ns141 0 0.00811894113452 +Gc4_142 0 n8 ns142 0 0.00791139790867 +Gc4_143 0 n8 ns143 0 0.000597120533238 +Gc4_144 0 n8 ns144 0 0.00143762918228 +Gc4_145 0 n8 ns145 0 0.00615537588902 +Gc4_146 0 n8 ns146 0 -7.34758956178e-005 +Gc4_147 0 n8 ns147 0 8.13993834738e-005 +Gc4_148 0 n8 ns148 0 1.18154393518e-005 +Gc4_149 0 n8 ns149 0 -0.00297165593664 +Gc4_150 0 n8 ns150 0 -0.00360281561787 +Gc4_151 0 n8 ns151 0 -3.45063071627e-005 +Gc4_152 0 n8 ns152 0 1.31004980478e-007 +Gc4_153 0 n8 ns153 0 1.31975075626e-007 +Gc4_154 0 n8 ns154 0 -1.64705077281e-005 +Gc4_155 0 n8 ns155 0 2.13629118206e-005 +Gc4_156 0 n8 ns156 0 -2.24109918986e-005 +Gc4_157 0 n8 ns157 0 -0.00109057842813 +Gc4_158 0 n8 ns158 0 -0.000260652578552 +Gc4_159 0 n8 ns159 0 0.001222712479 +Gc4_160 0 n8 ns160 0 0.000534273900902 +Gc4_161 0 n8 ns161 0 2.80490627035e-007 +Gc4_162 0 n8 ns162 0 -1.43696282496e-007 +Gc4_163 0 n8 ns163 0 1.1656275115e-005 +Gc4_164 0 n8 ns164 0 2.78057298645e-006 +Gc4_165 0 n8 ns165 0 6.37437041562e-005 +Gc4_166 0 n8 ns166 0 -0.000174148915342 +Gc4_167 0 n8 ns167 0 -3.59545080222e-006 +Gc4_168 0 n8 ns168 0 4.6423095059e-006 +Gc4_169 0 n8 ns169 0 -0.00167324497507 +Gc4_170 0 n8 ns170 0 0.00146932281807 +Gc4_171 0 n8 ns171 0 -9.77747691679e-007 +Gc4_172 0 n8 ns172 0 -1.43722449631e-007 +Gc4_173 0 n8 ns173 0 -0.000349316697496 +Gc4_174 0 n8 ns174 0 -0.000260987168658 +Gc4_175 0 n8 ns175 0 0.000644651799409 +Gc4_176 0 n8 ns176 0 0.00168816091158 +Gc4_177 0 n8 ns177 0 -0.00115413886734 +Gc4_178 0 n8 ns178 0 8.05853354216e-005 +Gc4_179 0 n8 ns179 0 -0.000521933607918 +Gc4_180 0 n8 ns180 0 -0.00106760670794 +Gc4_181 0 n8 ns181 0 0.00614681761807 +Gc4_182 0 n8 ns182 0 -7.98073145876e-005 +Gc4_183 0 n8 ns183 0 9.6447962871e-005 +Gc4_184 0 n8 ns184 0 2.03204306788e-005 +Gc4_185 0 n8 ns185 0 -0.0039169699018 +Gc4_186 0 n8 ns186 0 -0.00265676407432 +Gc4_187 0 n8 ns187 0 -3.21555886241e-005 +Gc4_188 0 n8 ns188 0 1.45596534891e-007 +Gc4_189 0 n8 ns189 0 1.31217252651e-007 +Gc4_190 0 n8 ns190 0 -1.94497024397e-005 +Gc4_191 0 n8 ns191 0 -5.34522518844e-005 +Gc4_192 0 n8 ns192 0 4.96618690852e-005 +Gc4_193 0 n8 ns193 0 -0.000436390281801 +Gc4_194 0 n8 ns194 0 -0.00013734905871 +Gc4_195 0 n8 ns195 0 0.0007556479211 +Gc4_196 0 n8 ns196 0 0.000310784317384 +Gc4_197 0 n8 ns197 0 2.66096891014e-007 +Gc4_198 0 n8 ns198 0 -4.53677815882e-008 +Gc4_199 0 n8 ns199 0 4.94674056529e-005 +Gc4_200 0 n8 ns200 0 2.69957479721e-005 +Gc4_201 0 n8 ns201 0 1.41014474175e-005 +Gc4_202 0 n8 ns202 0 1.95232723111e-005 +Gc4_203 0 n8 ns203 0 -2.61032886821e-005 +Gc4_204 0 n8 ns204 0 1.7653558212e-005 +Gc4_205 0 n8 ns205 0 -0.0016135682792 +Gc4_206 0 n8 ns206 0 0.00155569347093 +Gc4_207 0 n8 ns207 0 -3.24376677522e-006 +Gc4_208 0 n8 ns208 0 -3.36087767028e-006 +Gc4_209 0 n8 ns209 0 -1.45862461948e-005 +Gc4_210 0 n8 ns210 0 6.86045085597e-006 +Gc4_211 0 n8 ns211 0 8.86653921997e-005 +Gc4_212 0 n8 ns212 0 0.00137205694424 +Gc4_213 0 n8 ns213 0 -0.0019158331919 +Gc4_214 0 n8 ns214 0 -0.000114155384662 +Gc4_215 0 n8 ns215 0 -5.86702507198e-005 +Gc4_216 0 n8 ns216 0 -0.000509505167954 +Gd4_1 0 n8 ni1 0 -0.00266726785039 +Gd4_2 0 n8 ni2 0 -6.34166557665e-005 +Gd4_3 0 n8 ni3 0 -0.000198403086419 +Gd4_4 0 n8 ni4 0 -0.001124864416 +Gd4_5 0 n8 ni5 0 -0.000756436966749 +Gd4_6 0 n8 ni6 0 -0.000904404383837 +Gc5_1 0 n10 ns1 0 -0.00614562507797 +Gc5_2 0 n10 ns2 0 7.27373193481e-005 +Gc5_3 0 n10 ns3 0 -0.000105728628987 +Gc5_4 0 n10 ns4 0 2.61720095142e-006 +Gc5_5 0 n10 ns5 0 0.00307634227464 +Gc5_6 0 n10 ns6 0 0.00352726700201 +Gc5_7 0 n10 ns7 0 4.25034800271e-005 +Gc5_8 0 n10 ns8 0 7.08992891112e-008 +Gc5_9 0 n10 ns9 0 -3.93949261606e-007 +Gc5_10 0 n10 ns10 0 3.30859674828e-006 +Gc5_11 0 n10 ns11 0 -5.86684339571e-005 +Gc5_12 0 n10 ns12 0 1.77098219077e-005 +Gc5_13 0 n10 ns13 0 0.00121973366584 +Gc5_14 0 n10 ns14 0 0.000289465289326 +Gc5_15 0 n10 ns15 0 -0.00123412486286 +Gc5_16 0 n10 ns16 0 -0.000549452710988 +Gc5_17 0 n10 ns17 0 2.25854549905e-007 +Gc5_18 0 n10 ns18 0 -3.12316447324e-007 +Gc5_19 0 n10 ns19 0 -1.85780293378e-006 +Gc5_20 0 n10 ns20 0 -2.39702230398e-005 +Gc5_21 0 n10 ns21 0 9.69449904654e-005 +Gc5_22 0 n10 ns22 0 -0.000176572965797 +Gc5_23 0 n10 ns23 0 -4.29511086765e-006 +Gc5_24 0 n10 ns24 0 2.39373759879e-008 +Gc5_25 0 n10 ns25 0 -4.41216435826e-005 +Gc5_26 0 n10 ns26 0 0.0012297756555 +Gc5_27 0 n10 ns27 0 -8.85747517469e-006 +Gc5_28 0 n10 ns28 0 -2.59787180955e-006 +Gc5_29 0 n10 ns29 0 0.000858878908164 +Gc5_30 0 n10 ns30 0 7.65324200476e-005 +Gc5_31 0 n10 ns31 0 -0.00176596534611 +Gc5_32 0 n10 ns32 0 -8.59298408533e-005 +Gc5_33 0 n10 ns33 0 -0.00241535927082 +Gc5_34 0 n10 ns34 0 -0.000586011491062 +Gc5_35 0 n10 ns35 0 0.00140008943132 +Gc5_36 0 n10 ns36 0 0.00067586544192 +Gc5_37 0 n10 ns37 0 -0.00639645434706 +Gc5_38 0 n10 ns38 0 -0.000149783340258 +Gc5_39 0 n10 ns39 0 0.000208828111161 +Gc5_40 0 n10 ns40 0 -4.13052249293e-006 +Gc5_41 0 n10 ns41 0 -0.00682197997686 +Gc5_42 0 n10 ns42 0 -0.00634432810853 +Gc5_43 0 n10 ns43 0 -5.40872658491e-005 +Gc5_44 0 n10 ns44 0 2.13836833354e-007 +Gc5_45 0 n10 ns45 0 1.06182657478e-006 +Gc5_46 0 n10 ns46 0 8.7565043466e-005 +Gc5_47 0 n10 ns47 0 -0.000412194268544 +Gc5_48 0 n10 ns48 0 -5.20886213434e-005 +Gc5_49 0 n10 ns49 0 -0.00140234866598 +Gc5_50 0 n10 ns50 0 -0.000326013013724 +Gc5_51 0 n10 ns51 0 -0.00114861747948 +Gc5_52 0 n10 ns52 0 -0.000375369429156 +Gc5_53 0 n10 ns53 0 3.56605068586e-007 +Gc5_54 0 n10 ns54 0 -1.78577895126e-007 +Gc5_55 0 n10 ns55 0 -2.35830555483e-006 +Gc5_56 0 n10 ns56 0 3.49440567438e-005 +Gc5_57 0 n10 ns57 0 -0.000786076943427 +Gc5_58 0 n10 ns58 0 0.00277646856228 +Gc5_59 0 n10 ns59 0 8.23445776137e-006 +Gc5_60 0 n10 ns60 0 -1.57157475529e-006 +Gc5_61 0 n10 ns61 0 0.00304692313845 +Gc5_62 0 n10 ns62 0 0.00391343491082 +Gc5_63 0 n10 ns63 0 9.42279957412e-006 +Gc5_64 0 n10 ns64 0 2.16868751062e-006 +Gc5_65 0 n10 ns65 0 -0.000704941477386 +Gc5_66 0 n10 ns66 0 -0.00252548524062 +Gc5_67 0 n10 ns67 0 0.00072217624472 +Gc5_68 0 n10 ns68 0 -0.00098588016861 +Gc5_69 0 n10 ns69 0 -0.00929132406345 +Gc5_70 0 n10 ns70 0 0.00363563491619 +Gc5_71 0 n10 ns71 0 0.0012832752603 +Gc5_72 0 n10 ns72 0 0.000530376373907 +Gc5_73 0 n10 ns73 0 -0.0062877281831 +Gc5_74 0 n10 ns74 0 7.24159092621e-005 +Gc5_75 0 n10 ns75 0 -0.000102932670366 +Gc5_76 0 n10 ns76 0 5.69363604337e-006 +Gc5_77 0 n10 ns77 0 0.00383677993868 +Gc5_78 0 n10 ns78 0 0.00277621613533 +Gc5_79 0 n10 ns79 0 2.94746212622e-005 +Gc5_80 0 n10 ns80 0 -7.00159350961e-008 +Gc5_81 0 n10 ns81 0 -1.30906291202e-007 +Gc5_82 0 n10 ns82 0 1.66827649585e-005 +Gc5_83 0 n10 ns83 0 0.00104008115858 +Gc5_84 0 n10 ns84 0 0.000129313396636 +Gc5_85 0 n10 ns85 0 -0.000460670878086 +Gc5_86 0 n10 ns86 0 -0.000153395072497 +Gc5_87 0 n10 ns87 0 -0.000641088989655 +Gc5_88 0 n10 ns88 0 -0.000202279082138 +Gc5_89 0 n10 ns89 0 2.24244433236e-007 +Gc5_90 0 n10 ns90 0 -4.25460368564e-008 +Gc5_91 0 n10 ns91 0 -0.00017044048638 +Gc5_92 0 n10 ns92 0 0.000344313050877 +Gc5_93 0 n10 ns93 0 0.000140516368002 +Gc5_94 0 n10 ns94 0 -0.00057944358277 +Gc5_95 0 n10 ns95 0 5.4430585109e-006 +Gc5_96 0 n10 ns96 0 -1.40438282882e-006 +Gc5_97 0 n10 ns97 0 0.0029122155569 +Gc5_98 0 n10 ns98 0 -0.000308265610618 +Gc5_99 0 n10 ns99 0 1.30821526737e-006 +Gc5_100 0 n10 ns100 0 -5.9395088902e-007 +Gc5_101 0 n10 ns101 0 -9.93792720114e-005 +Gc5_102 0 n10 ns102 0 0.000899762473279 +Gc5_103 0 n10 ns103 0 -0.000625876379721 +Gc5_104 0 n10 ns104 0 -0.000401770500354 +Gc5_105 0 n10 ns105 0 -0.00122194385311 +Gc5_106 0 n10 ns106 0 -0.00230754235472 +Gc5_107 0 n10 ns107 0 0.000351908242218 +Gc5_108 0 n10 ns108 0 -0.00027542157576 +Gc5_109 0 n10 ns109 0 0.00613213045698 +Gc5_110 0 n10 ns110 0 -7.31734839923e-005 +Gc5_111 0 n10 ns111 0 8.1336225039e-005 +Gc5_112 0 n10 ns112 0 1.10068012358e-005 +Gc5_113 0 n10 ns113 0 -0.00297552805435 +Gc5_114 0 n10 ns114 0 -0.00359931279477 +Gc5_115 0 n10 ns115 0 -3.43963998371e-005 +Gc5_116 0 n10 ns116 0 1.21352545557e-007 +Gc5_117 0 n10 ns117 0 1.18745642089e-007 +Gc5_118 0 n10 ns118 0 -1.49287153489e-005 +Gc5_119 0 n10 ns119 0 2.08017627252e-005 +Gc5_120 0 n10 ns120 0 -2.21374728384e-005 +Gc5_121 0 n10 ns121 0 -0.00109009586174 +Gc5_122 0 n10 ns122 0 -0.000260369758807 +Gc5_123 0 n10 ns123 0 0.00122248496961 +Gc5_124 0 n10 ns124 0 0.000534439085262 +Gc5_125 0 n10 ns125 0 2.66827315153e-007 +Gc5_126 0 n10 ns126 0 -1.18800949097e-007 +Gc5_127 0 n10 ns127 0 1.24710590414e-005 +Gc5_128 0 n10 ns128 0 2.33004267051e-006 +Gc5_129 0 n10 ns129 0 6.66259298658e-005 +Gc5_130 0 n10 ns130 0 -0.000173896303064 +Gc5_131 0 n10 ns131 0 -3.27898927791e-006 +Gc5_132 0 n10 ns132 0 5.32573972964e-006 +Gc5_133 0 n10 ns133 0 -0.0013084095138 +Gc5_134 0 n10 ns134 0 0.00130376546882 +Gc5_135 0 n10 ns135 0 -9.4090662822e-007 +Gc5_136 0 n10 ns136 0 -7.33473700301e-007 +Gc5_137 0 n10 ns137 0 -0.000363728146418 +Gc5_138 0 n10 ns138 0 -0.000260683654484 +Gc5_139 0 n10 ns139 0 0.00062568055891 +Gc5_140 0 n10 ns140 0 0.00168623839803 +Gc5_141 0 n10 ns141 0 -0.00107717356804 +Gc5_142 0 n10 ns142 0 -0.000130268439496 +Gc5_143 0 n10 ns143 0 -0.000565746217988 +Gc5_144 0 n10 ns144 0 -0.00106802054361 +Gc5_145 0 n10 ns145 0 0.00635307100679 +Gc5_146 0 n10 ns146 0 0.000149576078364 +Gc5_147 0 n10 ns147 0 -0.000171327790583 +Gc5_148 0 n10 ns148 0 -3.20738735571e-005 +Gc5_149 0 n10 ns149 0 0.00663500394848 +Gc5_150 0 n10 ns150 0 0.00646860212084 +Gc5_151 0 n10 ns151 0 5.42880195348e-005 +Gc5_152 0 n10 ns152 0 -2.71554182986e-007 +Gc5_153 0 n10 ns153 0 -5.98161901115e-007 +Gc5_154 0 n10 ns154 0 -0.000146456487828 +Gc5_155 0 n10 ns155 0 0.000369329538295 +Gc5_156 0 n10 ns156 0 4.71182116177e-005 +Gc5_157 0 n10 ns157 0 0.0012285608927 +Gc5_158 0 n10 ns158 0 0.00029256118765 +Gc5_159 0 n10 ns159 0 0.00110959202024 +Gc5_160 0 n10 ns160 0 0.00037693061842 +Gc5_161 0 n10 ns161 0 -3.55774046038e-008 +Gc5_162 0 n10 ns162 0 -8.86691004805e-008 +Gc5_163 0 n10 ns163 0 2.38053782959e-005 +Gc5_164 0 n10 ns164 0 -5.59427297497e-005 +Gc5_165 0 n10 ns165 0 0.000237693360586 +Gc5_166 0 n10 ns166 0 -0.00182362042621 +Gc5_167 0 n10 ns167 0 -2.68649334861e-006 +Gc5_168 0 n10 ns168 0 5.92693729316e-006 +Gc5_169 0 n10 ns169 0 -0.0174786199292 +Gc5_170 0 n10 ns170 0 -0.0149044925312 +Gc5_171 0 n10 ns171 0 -6.61815630223e-006 +Gc5_172 0 n10 ns172 0 -1.39786210869e-005 +Gc5_173 0 n10 ns173 0 -0.000252985976735 +Gc5_174 0 n10 ns174 0 0.00222257134867 +Gc5_175 0 n10 ns175 0 0.000622485520018 +Gc5_176 0 n10 ns176 0 -1.43615571017e-005 +Gc5_177 0 n10 ns177 0 0.0116579642165 +Gc5_178 0 n10 ns178 0 -0.00554636987281 +Gc5_179 0 n10 ns179 0 -0.0011135347213 +Gc5_180 0 n10 ns180 0 -0.000613624231615 +Gc5_181 0 n10 ns181 0 0.00630373453533 +Gc5_182 0 n10 ns182 0 -7.19129735657e-005 +Gc5_183 0 n10 ns183 0 0.000107914169696 +Gc5_184 0 n10 ns184 0 -1.19706935275e-005 +Gc5_185 0 n10 ns185 0 -0.00386549472657 +Gc5_186 0 n10 ns186 0 -0.00274503578158 +Gc5_187 0 n10 ns187 0 -3.34502896891e-005 +Gc5_188 0 n10 ns188 0 -9.0556108036e-009 +Gc5_189 0 n10 ns189 0 8.01779818823e-008 +Gc5_190 0 n10 ns190 0 -5.43136173829e-006 +Gc5_191 0 n10 ns191 0 -0.000955848945191 +Gc5_192 0 n10 ns192 0 -0.000118745158431 +Gc5_193 0 n10 ns193 0 0.000492971466634 +Gc5_194 0 n10 ns194 0 0.000153739162411 +Gc5_195 0 n10 ns195 0 0.000688152183114 +Gc5_196 0 n10 ns196 0 0.000215488182404 +Gc5_197 0 n10 ns197 0 2.70349482238e-007 +Gc5_198 0 n10 ns198 0 -2.06060832179e-007 +Gc5_199 0 n10 ns199 0 0.000133676963527 +Gc5_200 0 n10 ns200 0 -0.00027908136522 +Gc5_201 0 n10 ns201 0 0.00011249346432 +Gc5_202 0 n10 ns202 0 0.000132987492892 +Gc5_203 0 n10 ns203 0 -1.60541238271e-006 +Gc5_204 0 n10 ns204 0 -9.39536843057e-007 +Gc5_205 0 n10 ns205 0 -0.00271230544914 +Gc5_206 0 n10 ns206 0 0.00223314419053 +Gc5_207 0 n10 ns207 0 -1.91160139644e-006 +Gc5_208 0 n10 ns208 0 -5.08299336178e-006 +Gc5_209 0 n10 ns209 0 0.000123110811161 +Gc5_210 0 n10 ns210 0 0.000237505727314 +Gc5_211 0 n10 ns211 0 0.0005978535036 +Gc5_212 0 n10 ns212 0 0.000125704997634 +Gc5_213 0 n10 ns213 0 -0.00199803781159 +Gc5_214 0 n10 ns214 0 -7.60400131417e-005 +Gc5_215 0 n10 ns215 0 -0.00139052017766 +Gc5_216 0 n10 ns216 0 0.000314369514348 +Gd5_1 0 n10 ni1 0 -0.000331139648708 +Gd5_2 0 n10 ni2 0 -0.00244683655588 +Gd5_3 0 n10 ni3 0 0.000231847031314 +Gd5_4 0 n10 ni4 0 -0.000656306782143 +Gd5_5 0 n10 ni5 0 -0.000889433230587 +Gd5_6 0 n10 ni6 0 -0.00166331385282 +Gc6_1 0 n12 ns1 0 -0.00612661020515 +Gc6_2 0 n12 ns2 0 7.90352008417e-005 +Gc6_3 0 n12 ns3 0 -0.000121284993642 +Gc6_4 0 n12 ns4 0 -5.26635263553e-006 +Gc6_5 0 n12 ns5 0 0.00402625310282 +Gc6_6 0 n12 ns6 0 0.00257883233923 +Gc6_7 0 n12 ns7 0 4.05579274246e-005 +Gc6_8 0 n12 ns8 0 5.86176983747e-008 +Gc6_9 0 n12 ns9 0 -4.17301393001e-007 +Gc6_10 0 n12 ns10 0 1.94442828911e-006 +Gc6_11 0 n12 ns11 0 0.000149779722182 +Gc6_12 0 n12 ns12 0 -4.20372334145e-005 +Gc6_13 0 n12 ns13 0 0.000485975392463 +Gc6_14 0 n12 ns14 0 0.000152840762597 +Gc6_15 0 n12 ns15 0 -0.000763475563866 +Gc6_16 0 n12 ns16 0 -0.000319391499039 +Gc6_17 0 n12 ns17 0 2.32088704243e-007 +Gc6_18 0 n12 ns18 0 -1.51644759766e-007 +Gc6_19 0 n12 ns19 0 2.16771949253e-005 +Gc6_20 0 n12 ns20 0 -0.000129990287406 +Gc6_21 0 n12 ns21 0 -2.19860851027e-006 +Gc6_22 0 n12 ns22 0 2.36681822433e-005 +Gc6_23 0 n12 ns23 0 -2.03737392832e-005 +Gc6_24 0 n12 ns24 0 1.12422758609e-005 +Gc6_25 0 n12 ns25 0 -0.000891956232838 +Gc6_26 0 n12 ns26 0 0.00140323382802 +Gc6_27 0 n12 ns27 0 -4.62799692043e-006 +Gc6_28 0 n12 ns28 0 -4.06431011754e-006 +Gc6_29 0 n12 ns29 0 0.000330867193351 +Gc6_30 0 n12 ns30 0 0.0003908379342 +Gc6_31 0 n12 ns31 0 -0.00120328672004 +Gc6_32 0 n12 ns32 0 -0.00060417637962 +Gc6_33 0 n12 ns33 0 -0.00161485622193 +Gc6_34 0 n12 ns34 0 4.20559017304e-005 +Gc6_35 0 n12 ns35 0 0.00091763809078 +Gc6_36 0 n12 ns36 0 0.000778965454102 +Gc6_37 0 n12 ns37 0 -0.00628732782165 +Gc6_38 0 n12 ns38 0 7.01780774819e-005 +Gc6_39 0 n12 ns39 0 -0.000142029955219 +Gc6_40 0 n12 ns40 0 2.97962651834e-005 +Gc6_41 0 n12 ns41 0 0.00400464132306 +Gc6_42 0 n12 ns42 0 0.00264648417858 +Gc6_43 0 n12 ns43 0 4.38075697769e-005 +Gc6_44 0 n12 ns44 0 1.11077150831e-007 +Gc6_45 0 n12 ns45 0 -3.03495356789e-007 +Gc6_46 0 n12 ns46 0 -1.42548377965e-005 +Gc6_47 0 n12 ns47 0 0.0010833659732 +Gc6_48 0 n12 ns48 0 0.000126451576826 +Gc6_49 0 n12 ns49 0 -0.000567194443398 +Gc6_50 0 n12 ns50 0 -0.000167784135222 +Gc6_51 0 n12 ns51 0 -0.000713378935853 +Gc6_52 0 n12 ns52 0 -0.000211820542208 +Gc6_53 0 n12 ns53 0 3.04444434687e-007 +Gc6_54 0 n12 ns54 0 4.83799580477e-008 +Gc6_55 0 n12 ns55 0 -4.45553667358e-005 +Gc6_56 0 n12 ns56 0 0.000181173517534 +Gc6_57 0 n12 ns57 0 -0.000145552745438 +Gc6_58 0 n12 ns58 0 -0.000222544398364 +Gc6_59 0 n12 ns59 0 1.99751126911e-005 +Gc6_60 0 n12 ns60 0 -6.03275567764e-006 +Gc6_61 0 n12 ns61 0 0.00116326040654 +Gc6_62 0 n12 ns62 0 0.000316499674619 +Gc6_63 0 n12 ns63 0 2.69419478518e-007 +Gc6_64 0 n12 ns64 0 -2.82441736068e-006 +Gc6_65 0 n12 ns65 0 -7.5702955786e-005 +Gc6_66 0 n12 ns66 0 0.000401678394427 +Gc6_67 0 n12 ns67 0 -0.000142826868901 +Gc6_68 0 n12 ns68 0 -0.000314967374736 +Gc6_69 0 n12 ns69 0 -0.000174796654204 +Gc6_70 0 n12 ns70 0 -0.000707136130037 +Gc6_71 0 n12 ns71 0 -0.000480931824886 +Gc6_72 0 n12 ns72 0 -0.000403747353241 +Gc6_73 0 n12 ns73 0 -0.00641854523267 +Gc6_74 0 n12 ns74 0 -0.00015596532619 +Gc6_75 0 n12 ns75 0 0.000223347155276 +Gc6_76 0 n12 ns76 0 2.46938684529e-006 +Gc6_77 0 n12 ns77 0 -0.00780710992369 +Gc6_78 0 n12 ns78 0 -0.00537746789644 +Gc6_79 0 n12 ns79 0 -4.79010184637e-005 +Gc6_80 0 n12 ns80 0 2.2403592291e-007 +Gc6_81 0 n12 ns81 0 1.07387735123e-006 +Gc6_82 0 n12 ns82 0 8.46467103098e-005 +Gc6_83 0 n12 ns83 0 -0.00269331874279 +Gc6_84 0 n12 ns84 0 -0.000379487530867 +Gc6_85 0 n12 ns85 0 -0.00018044309413 +Gc6_86 0 n12 ns86 0 -8.20611490853e-005 +Gc6_87 0 n12 ns87 0 -0.000393431291902 +Gc6_88 0 n12 ns88 0 -0.00011339754719 +Gc6_89 0 n12 ns89 0 3.79929538429e-007 +Gc6_90 0 n12 ns90 0 -2.41602626517e-007 +Gc6_91 0 n12 ns91 0 -0.00111184723765 +Gc6_92 0 n12 ns92 0 0.00157690236537 +Gc6_93 0 n12 ns93 0 2.98000783567e-005 +Gc6_94 0 n12 ns94 0 4.45800987612e-005 +Gc6_95 0 n12 ns95 0 1.51065117335e-005 +Gc6_96 0 n12 ns96 0 -1.51215886839e-005 +Gc6_97 0 n12 ns97 0 -5.69178280164e-006 +Gc6_98 0 n12 ns98 0 0.00510365677973 +Gc6_99 0 n12 ns99 0 -7.80951468338e-008 +Gc6_100 0 n12 ns100 0 -3.50636330133e-007 +Gc6_101 0 n12 ns101 0 -0.000722038762009 +Gc6_102 0 n12 ns102 0 -0.000778567861568 +Gc6_103 0 n12 ns103 0 0.000630715574921 +Gc6_104 0 n12 ns104 0 0.000307444879914 +Gc6_105 0 n12 ns105 0 -0.00849154871133 +Gc6_106 0 n12 ns106 0 0.000357116488718 +Gc6_107 0 n12 ns107 0 0.000711084213123 +Gc6_108 0 n12 ns108 0 0.000745213728501 +Gc6_109 0 n12 ns109 0 0.00612226539694 +Gc6_110 0 n12 ns110 0 -7.93346035398e-005 +Gc6_111 0 n12 ns111 0 9.67490313587e-005 +Gc6_112 0 n12 ns112 0 2.02503493215e-005 +Gc6_113 0 n12 ns113 0 -0.00391978255311 +Gc6_114 0 n12 ns114 0 -0.00265441498525 +Gc6_115 0 n12 ns115 0 -3.20522335019e-005 +Gc6_116 0 n12 ns116 0 1.59096152713e-007 +Gc6_117 0 n12 ns117 0 1.29039121437e-007 +Gc6_118 0 n12 ns118 0 -1.86361595712e-005 +Gc6_119 0 n12 ns119 0 -5.39380505618e-005 +Gc6_120 0 n12 ns120 0 4.95136548493e-005 +Gc6_121 0 n12 ns121 0 -0.000436328165887 +Gc6_122 0 n12 ns122 0 -0.000136823434727 +Gc6_123 0 n12 ns123 0 0.000755533373236 +Gc6_124 0 n12 ns124 0 0.00031091579562 +Gc6_125 0 n12 ns125 0 2.53184807305e-007 +Gc6_126 0 n12 ns126 0 -1.89826438423e-008 +Gc6_127 0 n12 ns127 0 5.0074284274e-005 +Gc6_128 0 n12 ns128 0 2.65574722145e-005 +Gc6_129 0 n12 ns129 0 1.6341143919e-005 +Gc6_130 0 n12 ns130 0 1.94921535231e-005 +Gc6_131 0 n12 ns131 0 -2.58861987456e-005 +Gc6_132 0 n12 ns132 0 1.81906494534e-005 +Gc6_133 0 n12 ns133 0 -0.00132532300021 +Gc6_134 0 n12 ns134 0 0.00143769880668 +Gc6_135 0 n12 ns135 0 -3.24852540656e-006 +Gc6_136 0 n12 ns136 0 -3.82863954348e-006 +Gc6_137 0 n12 ns137 0 -2.29160752263e-005 +Gc6_138 0 n12 ns138 0 7.64132118432e-006 +Gc6_139 0 n12 ns139 0 7.40909237206e-005 +Gc6_140 0 n12 ns140 0 0.00136067495953 +Gc6_141 0 n12 ns141 0 -0.00183430264876 +Gc6_142 0 n12 ns142 0 -0.000273067352563 +Gc6_143 0 n12 ns143 0 -0.000100033937929 +Gc6_144 0 n12 ns144 0 -0.000514913678281 +Gc6_145 0 n12 ns145 0 0.00627651113452 +Gc6_146 0 n12 ns146 0 -7.00019125196e-005 +Gc6_147 0 n12 ns147 0 0.0001228764834 +Gc6_148 0 n12 ns148 0 -1.81817471574e-005 +Gc6_149 0 n12 ns149 0 -0.0039225169407 +Gc6_150 0 n12 ns150 0 -0.00270582337854 +Gc6_151 0 n12 ns151 0 -3.66612940677e-005 +Gc6_152 0 n12 ns152 0 -3.20149413842e-008 +Gc6_153 0 n12 ns153 0 1.08623619468e-007 +Gc6_154 0 n12 ns154 0 2.63767640632e-006 +Gc6_155 0 n12 ns155 0 -0.000956166083281 +Gc6_156 0 n12 ns156 0 -0.000117198107329 +Gc6_157 0 n12 ns157 0 0.000494530110733 +Gc6_158 0 n12 ns158 0 0.000153986637557 +Gc6_159 0 n12 ns159 0 0.000688533192391 +Gc6_160 0 n12 ns160 0 0.000214981383071 +Gc6_161 0 n12 ns161 0 2.31587460544e-007 +Gc6_162 0 n12 ns162 0 -1.84688097487e-007 +Gc6_163 0 n12 ns163 0 0.000134917824892 +Gc6_164 0 n12 ns164 0 -0.000278988324676 +Gc6_165 0 n12 ns165 0 0.000115478752129 +Gc6_166 0 n12 ns166 0 0.000135086965181 +Gc6_167 0 n12 ns167 0 -1.52812064951e-006 +Gc6_168 0 n12 ns168 0 -1.86018550407e-007 +Gc6_169 0 n12 ns169 0 -0.00225538418386 +Gc6_170 0 n12 ns170 0 0.00191344382585 +Gc6_171 0 n12 ns171 0 -1.9220980942e-006 +Gc6_172 0 n12 ns172 0 -5.74050549883e-006 +Gc6_173 0 n12 ns173 0 9.13761318459e-005 +Gc6_174 0 n12 ns174 0 0.000255670042668 +Gc6_175 0 n12 ns175 0 0.000599209819408 +Gc6_176 0 n12 ns176 0 0.000152594577019 +Gc6_177 0 n12 ns177 0 -0.00205420381182 +Gc6_178 0 n12 ns178 0 -0.000356024374548 +Gc6_179 0 n12 ns179 0 -0.00141708409531 +Gc6_180 0 n12 ns180 0 0.000341243204179 +Gc6_181 0 n12 ns181 0 0.00635128657338 +Gc6_182 0 n12 ns182 0 0.000157383746121 +Gc6_183 0 n12 ns183 0 -0.000163982933678 +Gc6_184 0 n12 ns184 0 -5.21273620132e-005 +Gc6_185 0 n12 ns185 0 0.00752416734057 +Gc6_186 0 n12 ns186 0 0.00557238044594 +Gc6_187 0 n12 ns187 0 3.80119836587e-005 +Gc6_188 0 n12 ns188 0 -5.34415917144e-007 +Gc6_189 0 n12 ns189 0 -1.02286382907e-007 +Gc6_190 0 n12 ns190 0 -0.000111112162938 +Gc6_191 0 n12 ns191 0 0.00248031642052 +Gc6_192 0 n12 ns192 0 0.000358441068266 +Gc6_193 0 n12 ns193 0 0.000199049079045 +Gc6_194 0 n12 ns194 0 7.57391758888e-005 +Gc6_195 0 n12 ns195 0 0.000423625419948 +Gc6_196 0 n12 ns196 0 0.000119972222 +Gc6_197 0 n12 ns197 0 -1.23185814371e-007 +Gc6_198 0 n12 ns198 0 1.04283053358e-007 +Gc6_199 0 n12 ns199 0 0.000883342886428 +Gc6_200 0 n12 ns200 0 -0.00128488439037 +Gc6_201 0 n12 ns201 0 1.31475067241e-005 +Gc6_202 0 n12 ns202 0 2.25830033012e-005 +Gc6_203 0 n12 ns203 0 3.56772604728e-006 +Gc6_204 0 n12 ns204 0 7.36683917019e-006 +Gc6_205 0 n12 ns205 0 -0.0121033699195 +Gc6_206 0 n12 ns206 0 -0.0178679603115 +Gc6_207 0 n12 ns207 0 5.60234058687e-007 +Gc6_208 0 n12 ns208 0 -9.55599551888e-006 +Gc6_209 0 n12 ns209 0 -4.82659167963e-005 +Gc6_210 0 n12 ns210 0 0.000539343636255 +Gc6_211 0 n12 ns211 0 0.000610359145865 +Gc6_212 0 n12 ns212 0 -0.00062712682107 +Gc6_213 0 n12 ns213 0 0.00876037232735 +Gc6_214 0 n12 ns214 0 -0.00449079577737 +Gc6_215 0 n12 ns215 0 8.92311376583e-005 +Gc6_216 0 n12 ns216 0 -0.00120628799588 +Gd6_1 0 n12 ni1 0 -0.000368627166145 +Gd6_2 0 n12 ni2 0 -7.79341086082e-006 +Gd6_3 0 n12 ni3 0 -0.00339616911909 +Gd6_4 0 n12 ni4 0 -0.000817474550071 +Gd6_5 0 n12 ni5 0 -0.00158948935418 +Gd6_6 0 n12 ni6 0 -0.000437993967074 +.ends + +.subckt 744835150072 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 372677161.844 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 8054157.44481 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 2445683.5266 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 817276.540311 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 605191.465212 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 156084.799782 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 200645.407904 +Ra8 ns8 0 200645.407904 +Ga7 ns7 0 ns8 0 5.11682247826e-005 +Ga8 ns8 0 ns7 0 -5.11682247826e-005 +Ca9 ns9 0 1e-012 +Ra9 ns9 0 18802.8685956 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 187680.174303 +Ra11 ns11 0 187680.174303 +Ga10 ns10 0 ns11 0 5.51694914493e-005 +Ga11 ns11 0 ns10 0 -5.51694914493e-005 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 154116.20456 +Ra13 ns13 0 154116.20456 +Ga12 ns12 0 ns13 0 6.5681254163e-005 +Ga13 ns13 0 ns12 0 -6.5681254163e-005 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 74567.3035165 +Ra15 ns15 0 74567.3035165 +Ga14 ns14 0 ns15 0 -0.00020495961627 +Ga15 ns15 0 ns14 0 0.00020495961627 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 69345.8496748 +Ra17 ns17 0 69345.8496748 +Ga16 ns16 0 ns17 0 0.000220027707284 +Ga17 ns17 0 ns16 0 -0.000220027707284 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 68046.113702 +Ra19 ns19 0 68046.113702 +Ga18 ns18 0 ns19 0 0.000230085192609 +Ga19 ns19 0 ns18 0 -0.000230085192609 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 12014.2994221 +Ra21 ns21 0 12014.2994221 +Ga20 ns20 0 ns21 0 0.000351651929893 +Ga21 ns21 0 ns20 0 -0.000351651929893 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 12494.1301865 +Ra23 ns23 0 12494.1301865 +Ga22 ns22 0 ns23 0 0.000427786531933 +Ga23 ns23 0 ns22 0 -0.000427786531933 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 31537.8103832 +Ra25 ns25 0 31537.8103832 +Ga24 ns24 0 ns25 0 0.00043688665921 +Ga25 ns25 0 ns24 0 -0.00043688665921 +Ca26 ns26 0 1e-012 +Ca27 ns27 0 1e-012 +Ra26 ns26 0 7098.06518869 +Ra27 ns27 0 7098.06518869 +Ga26 ns26 0 ns27 0 0.000487638170462 +Ga27 ns27 0 ns26 0 -0.000487638170462 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 34326.8919895 +Ra29 ns29 0 34326.8919895 +Ga28 ns28 0 ns29 0 0.000511847996809 +Ga29 ns29 0 ns28 0 -0.000511847996809 +Ca30 ns30 0 1e-012 +Ca31 ns31 0 1e-012 +Ra30 ns30 0 34798.3438772 +Ra31 ns31 0 34798.3438772 +Ga30 ns30 0 ns31 0 0.00054215406924 +Ga31 ns31 0 ns30 0 -0.00054215406924 +Ca32 ns32 0 1e-012 +Ra32 ns32 0 1658.41579716 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 3301.78849442 +Ra34 ns34 0 3301.78849442 +Ga33 ns33 0 ns34 0 0.000588020380804 +Ga34 ns34 0 ns33 0 -0.000588020380804 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 8392.66045311 +Ra36 ns36 0 8392.66045311 +Ga35 ns35 0 ns36 0 0.000747352084953 +Ga36 ns36 0 ns35 0 -0.000747352084953 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 372677161.844 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 8054157.44481 +Ca39 ns39 0 1e-012 +Ra39 ns39 0 2445683.5266 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 817276.540311 +Ca41 ns41 0 1e-012 +Ra41 ns41 0 605191.465212 +Ca42 ns42 0 1e-012 +Ra42 ns42 0 156084.799782 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 200645.407904 +Ra44 ns44 0 200645.407904 +Ga43 ns43 0 ns44 0 5.11682247826e-005 +Ga44 ns44 0 ns43 0 -5.11682247826e-005 +Ca45 ns45 0 1e-012 +Ra45 ns45 0 18802.8685956 +Ca46 ns46 0 1e-012 +Ca47 ns47 0 1e-012 +Ra46 ns46 0 187680.174303 +Ra47 ns47 0 187680.174303 +Ga46 ns46 0 ns47 0 5.51694914493e-005 +Ga47 ns47 0 ns46 0 -5.51694914493e-005 +Ca48 ns48 0 1e-012 +Ca49 ns49 0 1e-012 +Ra48 ns48 0 154116.20456 +Ra49 ns49 0 154116.20456 +Ga48 ns48 0 ns49 0 6.5681254163e-005 +Ga49 ns49 0 ns48 0 -6.5681254163e-005 +Ca50 ns50 0 1e-012 +Ca51 ns51 0 1e-012 +Ra50 ns50 0 74567.3035165 +Ra51 ns51 0 74567.3035165 +Ga50 ns50 0 ns51 0 -0.00020495961627 +Ga51 ns51 0 ns50 0 0.00020495961627 +Ca52 ns52 0 1e-012 +Ca53 ns53 0 1e-012 +Ra52 ns52 0 69345.8496748 +Ra53 ns53 0 69345.8496748 +Ga52 ns52 0 ns53 0 0.000220027707284 +Ga53 ns53 0 ns52 0 -0.000220027707284 +Ca54 ns54 0 1e-012 +Ca55 ns55 0 1e-012 +Ra54 ns54 0 68046.113702 +Ra55 ns55 0 68046.113702 +Ga54 ns54 0 ns55 0 0.000230085192609 +Ga55 ns55 0 ns54 0 -0.000230085192609 +Ca56 ns56 0 1e-012 +Ca57 ns57 0 1e-012 +Ra56 ns56 0 12014.2994221 +Ra57 ns57 0 12014.2994221 +Ga56 ns56 0 ns57 0 0.000351651929893 +Ga57 ns57 0 ns56 0 -0.000351651929893 +Ca58 ns58 0 1e-012 +Ca59 ns59 0 1e-012 +Ra58 ns58 0 12494.1301865 +Ra59 ns59 0 12494.1301865 +Ga58 ns58 0 ns59 0 0.000427786531933 +Ga59 ns59 0 ns58 0 -0.000427786531933 +Ca60 ns60 0 1e-012 +Ca61 ns61 0 1e-012 +Ra60 ns60 0 31537.8103832 +Ra61 ns61 0 31537.8103832 +Ga60 ns60 0 ns61 0 0.00043688665921 +Ga61 ns61 0 ns60 0 -0.00043688665921 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 7098.06518869 +Ra63 ns63 0 7098.06518869 +Ga62 ns62 0 ns63 0 0.000487638170462 +Ga63 ns63 0 ns62 0 -0.000487638170462 +Ca64 ns64 0 1e-012 +Ca65 ns65 0 1e-012 +Ra64 ns64 0 34326.8919895 +Ra65 ns65 0 34326.8919895 +Ga64 ns64 0 ns65 0 0.000511847996809 +Ga65 ns65 0 ns64 0 -0.000511847996809 +Ca66 ns66 0 1e-012 +Ca67 ns67 0 1e-012 +Ra66 ns66 0 34798.3438772 +Ra67 ns67 0 34798.3438772 +Ga66 ns66 0 ns67 0 0.00054215406924 +Ga67 ns67 0 ns66 0 -0.00054215406924 +Ca68 ns68 0 1e-012 +Ra68 ns68 0 1658.41579716 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 3301.78849442 +Ra70 ns70 0 3301.78849442 +Ga69 ns69 0 ns70 0 0.000588020380804 +Ga70 ns70 0 ns69 0 -0.000588020380804 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 8392.66045311 +Ra72 ns72 0 8392.66045311 +Ga71 ns71 0 ns72 0 0.000747352084953 +Ga72 ns72 0 ns71 0 -0.000747352084953 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 372677161.844 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 8054157.44481 +Ca75 ns75 0 1e-012 +Ra75 ns75 0 2445683.5266 +Ca76 ns76 0 1e-012 +Ra76 ns76 0 817276.540311 +Ca77 ns77 0 1e-012 +Ra77 ns77 0 605191.465212 +Ca78 ns78 0 1e-012 +Ra78 ns78 0 156084.799782 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 200645.407904 +Ra80 ns80 0 200645.407904 +Ga79 ns79 0 ns80 0 5.11682247826e-005 +Ga80 ns80 0 ns79 0 -5.11682247826e-005 +Ca81 ns81 0 1e-012 +Ra81 ns81 0 18802.8685956 +Ca82 ns82 0 1e-012 +Ca83 ns83 0 1e-012 +Ra82 ns82 0 187680.174303 +Ra83 ns83 0 187680.174303 +Ga82 ns82 0 ns83 0 5.51694914493e-005 +Ga83 ns83 0 ns82 0 -5.51694914493e-005 +Ca84 ns84 0 1e-012 +Ca85 ns85 0 1e-012 +Ra84 ns84 0 154116.20456 +Ra85 ns85 0 154116.20456 +Ga84 ns84 0 ns85 0 6.5681254163e-005 +Ga85 ns85 0 ns84 0 -6.5681254163e-005 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 74567.3035165 +Ra87 ns87 0 74567.3035165 +Ga86 ns86 0 ns87 0 -0.00020495961627 +Ga87 ns87 0 ns86 0 0.00020495961627 +Ca88 ns88 0 1e-012 +Ca89 ns89 0 1e-012 +Ra88 ns88 0 69345.8496748 +Ra89 ns89 0 69345.8496748 +Ga88 ns88 0 ns89 0 0.000220027707284 +Ga89 ns89 0 ns88 0 -0.000220027707284 +Ca90 ns90 0 1e-012 +Ca91 ns91 0 1e-012 +Ra90 ns90 0 68046.113702 +Ra91 ns91 0 68046.113702 +Ga90 ns90 0 ns91 0 0.000230085192609 +Ga91 ns91 0 ns90 0 -0.000230085192609 +Ca92 ns92 0 1e-012 +Ca93 ns93 0 1e-012 +Ra92 ns92 0 12014.2994221 +Ra93 ns93 0 12014.2994221 +Ga92 ns92 0 ns93 0 0.000351651929893 +Ga93 ns93 0 ns92 0 -0.000351651929893 +Ca94 ns94 0 1e-012 +Ca95 ns95 0 1e-012 +Ra94 ns94 0 12494.1301865 +Ra95 ns95 0 12494.1301865 +Ga94 ns94 0 ns95 0 0.000427786531933 +Ga95 ns95 0 ns94 0 -0.000427786531933 +Ca96 ns96 0 1e-012 +Ca97 ns97 0 1e-012 +Ra96 ns96 0 31537.8103832 +Ra97 ns97 0 31537.8103832 +Ga96 ns96 0 ns97 0 0.00043688665921 +Ga97 ns97 0 ns96 0 -0.00043688665921 +Ca98 ns98 0 1e-012 +Ca99 ns99 0 1e-012 +Ra98 ns98 0 7098.06518869 +Ra99 ns99 0 7098.06518869 +Ga98 ns98 0 ns99 0 0.000487638170462 +Ga99 ns99 0 ns98 0 -0.000487638170462 +Ca100 ns100 0 1e-012 +Ca101 ns101 0 1e-012 +Ra100 ns100 0 34326.8919895 +Ra101 ns101 0 34326.8919895 +Ga100 ns100 0 ns101 0 0.000511847996809 +Ga101 ns101 0 ns100 0 -0.000511847996809 +Ca102 ns102 0 1e-012 +Ca103 ns103 0 1e-012 +Ra102 ns102 0 34798.3438772 +Ra103 ns103 0 34798.3438772 +Ga102 ns102 0 ns103 0 0.00054215406924 +Ga103 ns103 0 ns102 0 -0.00054215406924 +Ca104 ns104 0 1e-012 +Ra104 ns104 0 1658.41579716 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 3301.78849442 +Ra106 ns106 0 3301.78849442 +Ga105 ns105 0 ns106 0 0.000588020380804 +Ga106 ns106 0 ns105 0 -0.000588020380804 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 8392.66045311 +Ra108 ns108 0 8392.66045311 +Ga107 ns107 0 ns108 0 0.000747352084953 +Ga108 ns108 0 ns107 0 -0.000747352084953 +Ca109 ns109 0 1e-012 +Ra109 ns109 0 372677161.844 +Ca110 ns110 0 1e-012 +Ra110 ns110 0 8054157.44481 +Ca111 ns111 0 1e-012 +Ra111 ns111 0 2445683.5266 +Ca112 ns112 0 1e-012 +Ra112 ns112 0 817276.540311 +Ca113 ns113 0 1e-012 +Ra113 ns113 0 605191.465212 +Ca114 ns114 0 1e-012 +Ra114 ns114 0 156084.799782 +Ca115 ns115 0 1e-012 +Ca116 ns116 0 1e-012 +Ra115 ns115 0 200645.407904 +Ra116 ns116 0 200645.407904 +Ga115 ns115 0 ns116 0 5.11682247826e-005 +Ga116 ns116 0 ns115 0 -5.11682247826e-005 +Ca117 ns117 0 1e-012 +Ra117 ns117 0 18802.8685956 +Ca118 ns118 0 1e-012 +Ca119 ns119 0 1e-012 +Ra118 ns118 0 187680.174303 +Ra119 ns119 0 187680.174303 +Ga118 ns118 0 ns119 0 5.51694914493e-005 +Ga119 ns119 0 ns118 0 -5.51694914493e-005 +Ca120 ns120 0 1e-012 +Ca121 ns121 0 1e-012 +Ra120 ns120 0 154116.20456 +Ra121 ns121 0 154116.20456 +Ga120 ns120 0 ns121 0 6.5681254163e-005 +Ga121 ns121 0 ns120 0 -6.5681254163e-005 +Ca122 ns122 0 1e-012 +Ca123 ns123 0 1e-012 +Ra122 ns122 0 74567.3035165 +Ra123 ns123 0 74567.3035165 +Ga122 ns122 0 ns123 0 -0.00020495961627 +Ga123 ns123 0 ns122 0 0.00020495961627 +Ca124 ns124 0 1e-012 +Ca125 ns125 0 1e-012 +Ra124 ns124 0 69345.8496748 +Ra125 ns125 0 69345.8496748 +Ga124 ns124 0 ns125 0 0.000220027707284 +Ga125 ns125 0 ns124 0 -0.000220027707284 +Ca126 ns126 0 1e-012 +Ca127 ns127 0 1e-012 +Ra126 ns126 0 68046.113702 +Ra127 ns127 0 68046.113702 +Ga126 ns126 0 ns127 0 0.000230085192609 +Ga127 ns127 0 ns126 0 -0.000230085192609 +Ca128 ns128 0 1e-012 +Ca129 ns129 0 1e-012 +Ra128 ns128 0 12014.2994221 +Ra129 ns129 0 12014.2994221 +Ga128 ns128 0 ns129 0 0.000351651929893 +Ga129 ns129 0 ns128 0 -0.000351651929893 +Ca130 ns130 0 1e-012 +Ca131 ns131 0 1e-012 +Ra130 ns130 0 12494.1301865 +Ra131 ns131 0 12494.1301865 +Ga130 ns130 0 ns131 0 0.000427786531933 +Ga131 ns131 0 ns130 0 -0.000427786531933 +Ca132 ns132 0 1e-012 +Ca133 ns133 0 1e-012 +Ra132 ns132 0 31537.8103832 +Ra133 ns133 0 31537.8103832 +Ga132 ns132 0 ns133 0 0.00043688665921 +Ga133 ns133 0 ns132 0 -0.00043688665921 +Ca134 ns134 0 1e-012 +Ca135 ns135 0 1e-012 +Ra134 ns134 0 7098.06518869 +Ra135 ns135 0 7098.06518869 +Ga134 ns134 0 ns135 0 0.000487638170462 +Ga135 ns135 0 ns134 0 -0.000487638170462 +Ca136 ns136 0 1e-012 +Ca137 ns137 0 1e-012 +Ra136 ns136 0 34326.8919895 +Ra137 ns137 0 34326.8919895 +Ga136 ns136 0 ns137 0 0.000511847996809 +Ga137 ns137 0 ns136 0 -0.000511847996809 +Ca138 ns138 0 1e-012 +Ca139 ns139 0 1e-012 +Ra138 ns138 0 34798.3438772 +Ra139 ns139 0 34798.3438772 +Ga138 ns138 0 ns139 0 0.00054215406924 +Ga139 ns139 0 ns138 0 -0.00054215406924 +Ca140 ns140 0 1e-012 +Ra140 ns140 0 1658.41579716 +Ca141 ns141 0 1e-012 +Ca142 ns142 0 1e-012 +Ra141 ns141 0 3301.78849442 +Ra142 ns142 0 3301.78849442 +Ga141 ns141 0 ns142 0 0.000588020380804 +Ga142 ns142 0 ns141 0 -0.000588020380804 +Ca143 ns143 0 1e-012 +Ca144 ns144 0 1e-012 +Ra143 ns143 0 8392.66045311 +Ra144 ns144 0 8392.66045311 +Ga143 ns143 0 ns144 0 0.000747352084953 +Ga144 ns144 0 ns143 0 -0.000747352084953 +Ca145 ns145 0 1e-012 +Ra145 ns145 0 372677161.844 +Ca146 ns146 0 1e-012 +Ra146 ns146 0 8054157.44481 +Ca147 ns147 0 1e-012 +Ra147 ns147 0 2445683.5266 +Ca148 ns148 0 1e-012 +Ra148 ns148 0 817276.540311 +Ca149 ns149 0 1e-012 +Ra149 ns149 0 605191.465212 +Ca150 ns150 0 1e-012 +Ra150 ns150 0 156084.799782 +Ca151 ns151 0 1e-012 +Ca152 ns152 0 1e-012 +Ra151 ns151 0 200645.407904 +Ra152 ns152 0 200645.407904 +Ga151 ns151 0 ns152 0 5.11682247826e-005 +Ga152 ns152 0 ns151 0 -5.11682247826e-005 +Ca153 ns153 0 1e-012 +Ra153 ns153 0 18802.8685956 +Ca154 ns154 0 1e-012 +Ca155 ns155 0 1e-012 +Ra154 ns154 0 187680.174303 +Ra155 ns155 0 187680.174303 +Ga154 ns154 0 ns155 0 5.51694914493e-005 +Ga155 ns155 0 ns154 0 -5.51694914493e-005 +Ca156 ns156 0 1e-012 +Ca157 ns157 0 1e-012 +Ra156 ns156 0 154116.20456 +Ra157 ns157 0 154116.20456 +Ga156 ns156 0 ns157 0 6.5681254163e-005 +Ga157 ns157 0 ns156 0 -6.5681254163e-005 +Ca158 ns158 0 1e-012 +Ca159 ns159 0 1e-012 +Ra158 ns158 0 74567.3035165 +Ra159 ns159 0 74567.3035165 +Ga158 ns158 0 ns159 0 -0.00020495961627 +Ga159 ns159 0 ns158 0 0.00020495961627 +Ca160 ns160 0 1e-012 +Ca161 ns161 0 1e-012 +Ra160 ns160 0 69345.8496748 +Ra161 ns161 0 69345.8496748 +Ga160 ns160 0 ns161 0 0.000220027707284 +Ga161 ns161 0 ns160 0 -0.000220027707284 +Ca162 ns162 0 1e-012 +Ca163 ns163 0 1e-012 +Ra162 ns162 0 68046.113702 +Ra163 ns163 0 68046.113702 +Ga162 ns162 0 ns163 0 0.000230085192609 +Ga163 ns163 0 ns162 0 -0.000230085192609 +Ca164 ns164 0 1e-012 +Ca165 ns165 0 1e-012 +Ra164 ns164 0 12014.2994221 +Ra165 ns165 0 12014.2994221 +Ga164 ns164 0 ns165 0 0.000351651929893 +Ga165 ns165 0 ns164 0 -0.000351651929893 +Ca166 ns166 0 1e-012 +Ca167 ns167 0 1e-012 +Ra166 ns166 0 12494.1301865 +Ra167 ns167 0 12494.1301865 +Ga166 ns166 0 ns167 0 0.000427786531933 +Ga167 ns167 0 ns166 0 -0.000427786531933 +Ca168 ns168 0 1e-012 +Ca169 ns169 0 1e-012 +Ra168 ns168 0 31537.8103832 +Ra169 ns169 0 31537.8103832 +Ga168 ns168 0 ns169 0 0.00043688665921 +Ga169 ns169 0 ns168 0 -0.00043688665921 +Ca170 ns170 0 1e-012 +Ca171 ns171 0 1e-012 +Ra170 ns170 0 7098.06518869 +Ra171 ns171 0 7098.06518869 +Ga170 ns170 0 ns171 0 0.000487638170462 +Ga171 ns171 0 ns170 0 -0.000487638170462 +Ca172 ns172 0 1e-012 +Ca173 ns173 0 1e-012 +Ra172 ns172 0 34326.8919895 +Ra173 ns173 0 34326.8919895 +Ga172 ns172 0 ns173 0 0.000511847996809 +Ga173 ns173 0 ns172 0 -0.000511847996809 +Ca174 ns174 0 1e-012 +Ca175 ns175 0 1e-012 +Ra174 ns174 0 34798.3438772 +Ra175 ns175 0 34798.3438772 +Ga174 ns174 0 ns175 0 0.00054215406924 +Ga175 ns175 0 ns174 0 -0.00054215406924 +Ca176 ns176 0 1e-012 +Ra176 ns176 0 1658.41579716 +Ca177 ns177 0 1e-012 +Ca178 ns178 0 1e-012 +Ra177 ns177 0 3301.78849442 +Ra178 ns178 0 3301.78849442 +Ga177 ns177 0 ns178 0 0.000588020380804 +Ga178 ns178 0 ns177 0 -0.000588020380804 +Ca179 ns179 0 1e-012 +Ca180 ns180 0 1e-012 +Ra179 ns179 0 8392.66045311 +Ra180 ns180 0 8392.66045311 +Ga179 ns179 0 ns180 0 0.000747352084953 +Ga180 ns180 0 ns179 0 -0.000747352084953 +Ca181 ns181 0 1e-012 +Ra181 ns181 0 372677161.844 +Ca182 ns182 0 1e-012 +Ra182 ns182 0 8054157.44481 +Ca183 ns183 0 1e-012 +Ra183 ns183 0 2445683.5266 +Ca184 ns184 0 1e-012 +Ra184 ns184 0 817276.540311 +Ca185 ns185 0 1e-012 +Ra185 ns185 0 605191.465212 +Ca186 ns186 0 1e-012 +Ra186 ns186 0 156084.799782 +Ca187 ns187 0 1e-012 +Ca188 ns188 0 1e-012 +Ra187 ns187 0 200645.407904 +Ra188 ns188 0 200645.407904 +Ga187 ns187 0 ns188 0 5.11682247826e-005 +Ga188 ns188 0 ns187 0 -5.11682247826e-005 +Ca189 ns189 0 1e-012 +Ra189 ns189 0 18802.8685956 +Ca190 ns190 0 1e-012 +Ca191 ns191 0 1e-012 +Ra190 ns190 0 187680.174303 +Ra191 ns191 0 187680.174303 +Ga190 ns190 0 ns191 0 5.51694914493e-005 +Ga191 ns191 0 ns190 0 -5.51694914493e-005 +Ca192 ns192 0 1e-012 +Ca193 ns193 0 1e-012 +Ra192 ns192 0 154116.20456 +Ra193 ns193 0 154116.20456 +Ga192 ns192 0 ns193 0 6.5681254163e-005 +Ga193 ns193 0 ns192 0 -6.5681254163e-005 +Ca194 ns194 0 1e-012 +Ca195 ns195 0 1e-012 +Ra194 ns194 0 74567.3035165 +Ra195 ns195 0 74567.3035165 +Ga194 ns194 0 ns195 0 -0.00020495961627 +Ga195 ns195 0 ns194 0 0.00020495961627 +Ca196 ns196 0 1e-012 +Ca197 ns197 0 1e-012 +Ra196 ns196 0 69345.8496748 +Ra197 ns197 0 69345.8496748 +Ga196 ns196 0 ns197 0 0.000220027707284 +Ga197 ns197 0 ns196 0 -0.000220027707284 +Ca198 ns198 0 1e-012 +Ca199 ns199 0 1e-012 +Ra198 ns198 0 68046.113702 +Ra199 ns199 0 68046.113702 +Ga198 ns198 0 ns199 0 0.000230085192609 +Ga199 ns199 0 ns198 0 -0.000230085192609 +Ca200 ns200 0 1e-012 +Ca201 ns201 0 1e-012 +Ra200 ns200 0 12014.2994221 +Ra201 ns201 0 12014.2994221 +Ga200 ns200 0 ns201 0 0.000351651929893 +Ga201 ns201 0 ns200 0 -0.000351651929893 +Ca202 ns202 0 1e-012 +Ca203 ns203 0 1e-012 +Ra202 ns202 0 12494.1301865 +Ra203 ns203 0 12494.1301865 +Ga202 ns202 0 ns203 0 0.000427786531933 +Ga203 ns203 0 ns202 0 -0.000427786531933 +Ca204 ns204 0 1e-012 +Ca205 ns205 0 1e-012 +Ra204 ns204 0 31537.8103832 +Ra205 ns205 0 31537.8103832 +Ga204 ns204 0 ns205 0 0.00043688665921 +Ga205 ns205 0 ns204 0 -0.00043688665921 +Ca206 ns206 0 1e-012 +Ca207 ns207 0 1e-012 +Ra206 ns206 0 7098.06518869 +Ra207 ns207 0 7098.06518869 +Ga206 ns206 0 ns207 0 0.000487638170462 +Ga207 ns207 0 ns206 0 -0.000487638170462 +Ca208 ns208 0 1e-012 +Ca209 ns209 0 1e-012 +Ra208 ns208 0 34326.8919895 +Ra209 ns209 0 34326.8919895 +Ga208 ns208 0 ns209 0 0.000511847996809 +Ga209 ns209 0 ns208 0 -0.000511847996809 +Ca210 ns210 0 1e-012 +Ca211 ns211 0 1e-012 +Ra210 ns210 0 34798.3438772 +Ra211 ns211 0 34798.3438772 +Ga210 ns210 0 ns211 0 0.00054215406924 +Ga211 ns211 0 ns210 0 -0.00054215406924 +Ca212 ns212 0 1e-012 +Ra212 ns212 0 1658.41579716 +Ca213 ns213 0 1e-012 +Ca214 ns214 0 1e-012 +Ra213 ns213 0 3301.78849442 +Ra214 ns214 0 3301.78849442 +Ga213 ns213 0 ns214 0 0.000588020380804 +Ga214 ns214 0 ns213 0 -0.000588020380804 +Ca215 ns215 0 1e-012 +Ca216 ns216 0 1e-012 +Ra215 ns215 0 8392.66045311 +Ra216 ns216 0 8392.66045311 +Ga215 ns215 0 ns216 0 0.000747352084953 +Ga216 ns216 0 ns215 0 -0.000747352084953 + +Gb1_1 ns1 0 ni1 0 2.68328758074e-009 +Gb2_1 ns2 0 ni1 0 1.24159479977e-007 +Gb3_1 ns3 0 ni1 0 4.08883647096e-007 +Gb4_1 ns4 0 ni1 0 1.22357604884e-006 +Gb5_1 ns5 0 ni1 0 1.65236963421e-006 +Gb6_1 ns6 0 ni1 0 6.4067737627e-006 +Gb7_1 ns7 0 ni1 0 5.16536710887e-005 +Gb9_1 ns9 0 ni1 0 5.31833743832e-005 +Gb10_1 ns10 0 ni1 0 5.56840848627e-005 +Gb12_1 ns12 0 ni1 0 6.63222599539e-005 +Gb14_1 ns14 0 ni1 0 0.000205837091415 +Gb16_1 ns16 0 ni1 0 0.000220972815806 +Gb18_1 ns18 0 ni1 0 0.000231023844754 +Gb20_1 ns20 0 ni1 0 0.000371353012509 +Gb22_1 ns22 0 ni1 0 0.000442761325311 +Gb24_1 ns24 0 ni1 0 0.000439187932206 +Gb26_1 ns26 0 ni1 0 0.000528340788048 +Gb28_1 ns28 0 ni1 0 0.000513506017802 +Gb30_1 ns30 0 ni1 0 0.00054367728045 +Gb32_1 ns32 0 ni1 0 0.00060298509078 +Gb33_1 ns33 0 ni1 0 0.000744014821508 +Gb35_1 ns35 0 ni1 0 0.000766348665947 +Gb37_2 ns37 0 ni2 0 2.68328758074e-009 +Gb38_2 ns38 0 ni2 0 1.24159479977e-007 +Gb39_2 ns39 0 ni2 0 4.08883647096e-007 +Gb40_2 ns40 0 ni2 0 1.22357604884e-006 +Gb41_2 ns41 0 ni2 0 1.65236963421e-006 +Gb42_2 ns42 0 ni2 0 6.4067737627e-006 +Gb43_2 ns43 0 ni2 0 5.16536710887e-005 +Gb45_2 ns45 0 ni2 0 5.31833743832e-005 +Gb46_2 ns46 0 ni2 0 5.56840848627e-005 +Gb48_2 ns48 0 ni2 0 6.63222599539e-005 +Gb50_2 ns50 0 ni2 0 0.000205837091415 +Gb52_2 ns52 0 ni2 0 0.000220972815806 +Gb54_2 ns54 0 ni2 0 0.000231023844754 +Gb56_2 ns56 0 ni2 0 0.000371353012509 +Gb58_2 ns58 0 ni2 0 0.000442761325311 +Gb60_2 ns60 0 ni2 0 0.000439187932206 +Gb62_2 ns62 0 ni2 0 0.000528340788048 +Gb64_2 ns64 0 ni2 0 0.000513506017802 +Gb66_2 ns66 0 ni2 0 0.00054367728045 +Gb68_2 ns68 0 ni2 0 0.00060298509078 +Gb69_2 ns69 0 ni2 0 0.000744014821508 +Gb71_2 ns71 0 ni2 0 0.000766348665947 +Gb73_3 ns73 0 ni3 0 2.68328758074e-009 +Gb74_3 ns74 0 ni3 0 1.24159479977e-007 +Gb75_3 ns75 0 ni3 0 4.08883647096e-007 +Gb76_3 ns76 0 ni3 0 1.22357604884e-006 +Gb77_3 ns77 0 ni3 0 1.65236963421e-006 +Gb78_3 ns78 0 ni3 0 6.4067737627e-006 +Gb79_3 ns79 0 ni3 0 5.16536710887e-005 +Gb81_3 ns81 0 ni3 0 5.31833743832e-005 +Gb82_3 ns82 0 ni3 0 5.56840848627e-005 +Gb84_3 ns84 0 ni3 0 6.63222599539e-005 +Gb86_3 ns86 0 ni3 0 0.000205837091415 +Gb88_3 ns88 0 ni3 0 0.000220972815806 +Gb90_3 ns90 0 ni3 0 0.000231023844754 +Gb92_3 ns92 0 ni3 0 0.000371353012509 +Gb94_3 ns94 0 ni3 0 0.000442761325311 +Gb96_3 ns96 0 ni3 0 0.000439187932206 +Gb98_3 ns98 0 ni3 0 0.000528340788048 +Gb100_3 ns100 0 ni3 0 0.000513506017802 +Gb102_3 ns102 0 ni3 0 0.00054367728045 +Gb104_3 ns104 0 ni3 0 0.00060298509078 +Gb105_3 ns105 0 ni3 0 0.000744014821508 +Gb107_3 ns107 0 ni3 0 0.000766348665947 +Gb109_4 ns109 0 ni4 0 2.68328758074e-009 +Gb110_4 ns110 0 ni4 0 1.24159479977e-007 +Gb111_4 ns111 0 ni4 0 4.08883647096e-007 +Gb112_4 ns112 0 ni4 0 1.22357604884e-006 +Gb113_4 ns113 0 ni4 0 1.65236963421e-006 +Gb114_4 ns114 0 ni4 0 6.4067737627e-006 +Gb115_4 ns115 0 ni4 0 5.16536710887e-005 +Gb117_4 ns117 0 ni4 0 5.31833743832e-005 +Gb118_4 ns118 0 ni4 0 5.56840848627e-005 +Gb120_4 ns120 0 ni4 0 6.63222599539e-005 +Gb122_4 ns122 0 ni4 0 0.000205837091415 +Gb124_4 ns124 0 ni4 0 0.000220972815806 +Gb126_4 ns126 0 ni4 0 0.000231023844754 +Gb128_4 ns128 0 ni4 0 0.000371353012509 +Gb130_4 ns130 0 ni4 0 0.000442761325311 +Gb132_4 ns132 0 ni4 0 0.000439187932206 +Gb134_4 ns134 0 ni4 0 0.000528340788048 +Gb136_4 ns136 0 ni4 0 0.000513506017802 +Gb138_4 ns138 0 ni4 0 0.00054367728045 +Gb140_4 ns140 0 ni4 0 0.00060298509078 +Gb141_4 ns141 0 ni4 0 0.000744014821508 +Gb143_4 ns143 0 ni4 0 0.000766348665947 +Gb145_5 ns145 0 ni5 0 2.68328758074e-009 +Gb146_5 ns146 0 ni5 0 1.24159479977e-007 +Gb147_5 ns147 0 ni5 0 4.08883647096e-007 +Gb148_5 ns148 0 ni5 0 1.22357604884e-006 +Gb149_5 ns149 0 ni5 0 1.65236963421e-006 +Gb150_5 ns150 0 ni5 0 6.4067737627e-006 +Gb151_5 ns151 0 ni5 0 5.16536710887e-005 +Gb153_5 ns153 0 ni5 0 5.31833743832e-005 +Gb154_5 ns154 0 ni5 0 5.56840848627e-005 +Gb156_5 ns156 0 ni5 0 6.63222599539e-005 +Gb158_5 ns158 0 ni5 0 0.000205837091415 +Gb160_5 ns160 0 ni5 0 0.000220972815806 +Gb162_5 ns162 0 ni5 0 0.000231023844754 +Gb164_5 ns164 0 ni5 0 0.000371353012509 +Gb166_5 ns166 0 ni5 0 0.000442761325311 +Gb168_5 ns168 0 ni5 0 0.000439187932206 +Gb170_5 ns170 0 ni5 0 0.000528340788048 +Gb172_5 ns172 0 ni5 0 0.000513506017802 +Gb174_5 ns174 0 ni5 0 0.00054367728045 +Gb176_5 ns176 0 ni5 0 0.00060298509078 +Gb177_5 ns177 0 ni5 0 0.000744014821508 +Gb179_5 ns179 0 ni5 0 0.000766348665947 +Gb181_6 ns181 0 ni6 0 2.68328758074e-009 +Gb182_6 ns182 0 ni6 0 1.24159479977e-007 +Gb183_6 ns183 0 ni6 0 4.08883647096e-007 +Gb184_6 ns184 0 ni6 0 1.22357604884e-006 +Gb185_6 ns185 0 ni6 0 1.65236963421e-006 +Gb186_6 ns186 0 ni6 0 6.4067737627e-006 +Gb187_6 ns187 0 ni6 0 5.16536710887e-005 +Gb189_6 ns189 0 ni6 0 5.31833743832e-005 +Gb190_6 ns190 0 ni6 0 5.56840848627e-005 +Gb192_6 ns192 0 ni6 0 6.63222599539e-005 +Gb194_6 ns194 0 ni6 0 0.000205837091415 +Gb196_6 ns196 0 ni6 0 0.000220972815806 +Gb198_6 ns198 0 ni6 0 0.000231023844754 +Gb200_6 ns200 0 ni6 0 0.000371353012509 +Gb202_6 ns202 0 ni6 0 0.000442761325311 +Gb204_6 ns204 0 ni6 0 0.000439187932206 +Gb206_6 ns206 0 ni6 0 0.000528340788048 +Gb208_6 ns208 0 ni6 0 0.000513506017802 +Gb210_6 ns210 0 ni6 0 0.00054367728045 +Gb212_6 ns212 0 ni6 0 0.00060298509078 +Gb213_6 ns213 0 ni6 0 0.000744014821508 +Gb215_6 ns215 0 ni6 0 0.000766348665947 + +Gc1_1 0 n2 ns1 0 0.00670521642154 +Gc1_2 0 n2 ns2 0 5.61782412152e-005 +Gc1_3 0 n2 ns3 0 0.000472867041487 +Gc1_4 0 n2 ns4 0 0.00830218930506 +Gc1_5 0 n2 ns5 0 0.00454344992675 +Gc1_6 0 n2 ns6 0 7.03722815011e-005 +Gc1_7 0 n2 ns7 0 0.000529871310653 +Gc1_8 0 n2 ns8 0 9.83948026733e-005 +Gc1_9 0 n2 ns9 0 -0.000150763972821 +Gc1_10 0 n2 ns10 0 0.00109405190057 +Gc1_11 0 n2 ns11 0 0.000186633295053 +Gc1_12 0 n2 ns12 0 0.00113888829025 +Gc1_13 0 n2 ns13 0 0.000300979393698 +Gc1_14 0 n2 ns14 0 2.00714811122e-005 +Gc1_15 0 n2 ns15 0 -4.70076607877e-005 +Gc1_16 0 n2 ns16 0 7.87738701693e-005 +Gc1_17 0 n2 ns17 0 6.07776303472e-005 +Gc1_18 0 n2 ns18 0 0.000345259359418 +Gc1_19 0 n2 ns19 0 0.000952135377994 +Gc1_20 0 n2 ns20 0 0.000316189275894 +Gc1_21 0 n2 ns21 0 0.000237182573035 +Gc1_22 0 n2 ns22 0 0.000871834197595 +Gc1_23 0 n2 ns23 0 0.0117340141355 +Gc1_24 0 n2 ns24 0 0.000276827482717 +Gc1_25 0 n2 ns25 0 -3.62815409637e-005 +Gc1_26 0 n2 ns26 0 -0.00125641573316 +Gc1_27 0 n2 ns27 0 -0.00155502187936 +Gc1_28 0 n2 ns28 0 -4.34035928161e-005 +Gc1_29 0 n2 ns29 0 3.27354029194e-005 +Gc1_30 0 n2 ns30 0 0.00043949060356 +Gc1_31 0 n2 ns31 0 0.00119055592384 +Gc1_32 0 n2 ns32 0 -0.0355700084852 +Gc1_33 0 n2 ns33 0 0.021330620967 +Gc1_34 0 n2 ns34 0 -0.0114628798566 +Gc1_35 0 n2 ns35 0 -0.00281957517944 +Gc1_36 0 n2 ns36 0 0.000809391310903 +Gc1_37 0 n2 ns37 0 0.00664355750332 +Gc1_38 0 n2 ns38 0 -2.63407575451e-005 +Gc1_39 0 n2 ns39 0 -0.000217243437372 +Gc1_40 0 n2 ns40 0 -0.00356496089616 +Gc1_41 0 n2 ns41 0 -0.00290107741217 +Gc1_42 0 n2 ns42 0 -3.10165000851e-005 +Gc1_43 0 n2 ns43 0 -0.00104067115165 +Gc1_44 0 n2 ns44 0 -0.000170835088134 +Gc1_45 0 n2 ns45 0 -2.47582716941e-005 +Gc1_46 0 n2 ns46 0 0.000327588990638 +Gc1_47 0 n2 ns47 0 0.000117912370148 +Gc1_48 0 n2 ns48 0 0.000798476629969 +Gc1_49 0 n2 ns49 0 0.000218139285328 +Gc1_50 0 n2 ns50 0 8.98772913213e-005 +Gc1_51 0 n2 ns51 0 -0.000155672660732 +Gc1_52 0 n2 ns52 0 -6.92779065818e-005 +Gc1_53 0 n2 ns53 0 -0.0001237354699 +Gc1_54 0 n2 ns54 0 -3.42078461754e-005 +Gc1_55 0 n2 ns55 0 -0.00015764160215 +Gc1_56 0 n2 ns56 0 0.000599779972052 +Gc1_57 0 n2 ns57 0 0.000362883008539 +Gc1_58 0 n2 ns58 0 -0.000502433175861 +Gc1_59 0 n2 ns59 0 -0.00718845104343 +Gc1_60 0 n2 ns60 0 -0.000267502566921 +Gc1_61 0 n2 ns61 0 0.000754545298154 +Gc1_62 0 n2 ns62 0 -0.00158784770783 +Gc1_63 0 n2 ns63 0 0.00742862959872 +Gc1_64 0 n2 ns64 0 -1.63146052388e-005 +Gc1_65 0 n2 ns65 0 4.59747105984e-005 +Gc1_66 0 n2 ns66 0 3.13293094663e-005 +Gc1_67 0 n2 ns67 0 -0.000363910067161 +Gc1_68 0 n2 ns68 0 -0.00250451108212 +Gc1_69 0 n2 ns69 0 -0.00238134632886 +Gc1_70 0 n2 ns70 0 0.00109080038732 +Gc1_71 0 n2 ns71 0 0.00149500693832 +Gc1_72 0 n2 ns72 0 0.000590673192863 +Gc1_73 0 n2 ns73 0 0.00664044011773 +Gc1_74 0 n2 ns74 0 -2.83721646775e-005 +Gc1_75 0 n2 ns75 0 -0.000256458017187 +Gc1_76 0 n2 ns76 0 -0.0047548531258 +Gc1_77 0 n2 ns77 0 -0.00164447967396 +Gc1_78 0 n2 ns78 0 -5.22225156664e-005 +Gc1_79 0 n2 ns79 0 0.000157147532759 +Gc1_80 0 n2 ns80 0 1.40213406114e-005 +Gc1_81 0 n2 ns81 0 7.85341215835e-005 +Gc1_82 0 n2 ns82 0 -0.00119966064179 +Gc1_83 0 n2 ns83 0 -0.000193009306642 +Gc1_84 0 n2 ns84 0 0.00110982811773 +Gc1_85 0 n2 ns85 0 0.00030670275334 +Gc1_86 0 n2 ns86 0 3.6559913965e-005 +Gc1_87 0 n2 ns87 0 -7.24911430117e-005 +Gc1_88 0 n2 ns88 0 0.000133684831573 +Gc1_89 0 n2 ns89 0 0.000195089396178 +Gc1_90 0 n2 ns90 0 -0.000207281287374 +Gc1_91 0 n2 ns91 0 -0.000505842657906 +Gc1_92 0 n2 ns92 0 -0.00235708039292 +Gc1_93 0 n2 ns93 0 -0.000620047674971 +Gc1_94 0 n2 ns94 0 0.00123372803917 +Gc1_95 0 n2 ns95 0 0.000434723147139 +Gc1_96 0 n2 ns96 0 0.000227531806269 +Gc1_97 0 n2 ns97 0 -2.09951659588e-005 +Gc1_98 0 n2 ns98 0 -0.00136236721568 +Gc1_99 0 n2 ns99 0 0.000104308864676 +Gc1_100 0 n2 ns100 0 -0.000112898189823 +Gc1_101 0 n2 ns101 0 -0.000224301426489 +Gc1_102 0 n2 ns102 0 0.000115009880388 +Gc1_103 0 n2 ns103 0 -6.90498779586e-005 +Gc1_104 0 n2 ns104 0 -0.00495574081809 +Gc1_105 0 n2 ns105 0 -0.000837675888305 +Gc1_106 0 n2 ns106 0 0.00450423686269 +Gc1_107 0 n2 ns107 0 0.000767764897732 +Gc1_108 0 n2 ns108 0 0.000297362403875 +Gc1_109 0 n2 ns109 0 -0.00669528955316 +Gc1_110 0 n2 ns110 0 -5.99705505243e-005 +Gc1_111 0 n2 ns111 0 -0.000466810821366 +Gc1_112 0 n2 ns112 0 -0.00829344576288 +Gc1_113 0 n2 ns113 0 -0.00455096327608 +Gc1_114 0 n2 ns114 0 -6.96312900039e-005 +Gc1_115 0 n2 ns115 0 -0.000497764548671 +Gc1_116 0 n2 ns116 0 -7.95328548525e-005 +Gc1_117 0 n2 ns117 0 0.000140138567464 +Gc1_118 0 n2 ns118 0 -0.00100549471987 +Gc1_119 0 n2 ns119 0 -0.000186437939993 +Gc1_120 0 n2 ns120 0 -0.00112166907034 +Gc1_121 0 n2 ns121 0 -0.000308029285547 +Gc1_122 0 n2 ns122 0 -1.38557001783e-005 +Gc1_123 0 n2 ns123 0 5.60226532592e-005 +Gc1_124 0 n2 ns124 0 -5.59398143106e-005 +Gc1_125 0 n2 ns125 0 -5.98047328132e-005 +Gc1_126 0 n2 ns126 0 -0.00016438599023 +Gc1_127 0 n2 ns127 0 -0.000656043850903 +Gc1_128 0 n2 ns128 0 0.000269834187842 +Gc1_129 0 n2 ns129 0 -0.00039366451718 +Gc1_130 0 n2 ns130 0 0.00349520955782 +Gc1_131 0 n2 ns131 0 -0.00670055477024 +Gc1_132 0 n2 ns132 0 -0.000187065214747 +Gc1_133 0 n2 ns133 0 -0.00015988736643 +Gc1_134 0 n2 ns134 0 -0.00250574965202 +Gc1_135 0 n2 ns135 0 0.000458373282162 +Gc1_136 0 n2 ns136 0 7.69593015932e-005 +Gc1_137 0 n2 ns137 0 4.10736068291e-005 +Gc1_138 0 n2 ns138 0 0.000329279063239 +Gc1_139 0 n2 ns139 0 -0.000402809450651 +Gc1_140 0 n2 ns140 0 0.0210854336914 +Gc1_141 0 n2 ns141 0 -0.0228916885289 +Gc1_142 0 n2 ns142 0 -0.00157108367844 +Gc1_143 0 n2 ns143 0 0.00359279020977 +Gc1_144 0 n2 ns144 0 -0.00189085811047 +Gc1_145 0 n2 ns145 0 -0.00663781055391 +Gc1_146 0 n2 ns146 0 2.10300047584e-005 +Gc1_147 0 n2 ns147 0 0.000223025917802 +Gc1_148 0 n2 ns148 0 0.00354366363553 +Gc1_149 0 n2 ns149 0 0.00291598000104 +Gc1_150 0 n2 ns150 0 2.92090005574e-005 +Gc1_151 0 n2 ns151 0 0.000997330650532 +Gc1_152 0 n2 ns152 0 0.000164962124707 +Gc1_153 0 n2 ns153 0 5.75351378625e-005 +Gc1_154 0 n2 ns154 0 -0.000338999935744 +Gc1_155 0 n2 ns155 0 -0.000117777860128 +Gc1_156 0 n2 ns156 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0 n4 ns211 0 9.73107639749e-005 +Gc2_212 0 n4 ns212 0 0.00136662807422 +Gc2_213 0 n4 ns213 0 0.00172957174021 +Gc2_214 0 n4 ns214 0 -0.00139258204113 +Gc2_215 0 n4 ns215 0 -5.11754764477e-005 +Gc2_216 0 n4 ns216 0 0.00136047246114 +Gd2_1 0 n4 ni1 0 -0.00104968380953 +Gd2_2 0 n4 ni2 0 -0.0051710203856 +Gd2_3 0 n4 ni3 0 -0.000983221710077 +Gd2_4 0 n4 ni4 0 0.00019094466723 +Gd2_5 0 n4 ni5 0 -0.00141905242086 +Gd2_6 0 n4 ni6 0 0.000210666297199 +Gc3_1 0 n6 ns1 0 0.00663939621736 +Gc3_2 0 n6 ns2 0 -2.75854735066e-005 +Gc3_3 0 n6 ns3 0 -0.00025745764925 +Gc3_4 0 n6 ns4 0 -0.00475100555203 +Gc3_5 0 n6 ns5 0 -0.00164714901807 +Gc3_6 0 n6 ns6 0 -5.19388931193e-005 +Gc3_7 0 n6 ns7 0 0.000156709922468 +Gc3_8 0 n6 ns8 0 1.21510345177e-005 +Gc3_9 0 n6 ns9 0 7.28244050777e-005 +Gc3_10 0 n6 ns10 0 -0.00120053542729 +Gc3_11 0 n6 ns11 0 -0.000191539138538 +Gc3_12 0 n6 ns12 0 0.00110912267775 +Gc3_13 0 n6 ns13 0 0.000306997064005 +Gc3_14 0 n6 ns14 0 3.62021204117e-005 +Gc3_15 0 n6 ns15 0 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0 1.77558120827e-005 +Gc4_100 0 n8 ns100 0 -0.000260940809121 +Gc4_101 0 n8 ns101 0 0.00016799493742 +Gc4_102 0 n8 ns102 0 -4.92758706414e-005 +Gc4_103 0 n8 ns103 0 -2.58209497704e-005 +Gc4_104 0 n8 ns104 0 0.00441466572738 +Gc4_105 0 n8 ns105 0 4.3129378575e-005 +Gc4_106 0 n8 ns106 0 -0.00338199894232 +Gc4_107 0 n8 ns107 0 -0.000786763332331 +Gc4_108 0 n8 ns108 0 5.35040312756e-005 +Gc4_109 0 n8 ns109 0 0.00670680507685 +Gc4_110 0 n8 ns110 0 4.67822526885e-005 +Gc4_111 0 n8 ns111 0 0.000479698950104 +Gc4_112 0 n8 ns112 0 0.00831133697355 +Gc4_113 0 n8 ns113 0 0.00451928182534 +Gc4_114 0 n8 ns114 0 8.27555958125e-005 +Gc4_115 0 n8 ns115 0 0.00047365999282 +Gc4_116 0 n8 ns116 0 8.83606632346e-005 +Gc4_117 0 n8 ns117 0 -0.000205563525729 +Gc4_118 0 n8 ns118 0 0.000942292288719 +Gc4_119 0 n8 ns119 0 0.000166631121875 +Gc4_120 0 n8 ns120 0 0.00110717899918 +Gc4_121 0 n8 ns121 0 0.000305443653241 +Gc4_122 0 n8 ns122 0 8.14315557004e-006 +Gc4_123 0 n8 ns123 0 -5.54750653578e-005 +Gc4_124 0 n8 ns124 0 3.70274016482e-005 +Gc4_125 0 n8 ns125 0 5.22013894902e-005 +Gc4_126 0 n8 ns126 0 6.07299316077e-005 +Gc4_127 0 n8 ns127 0 0.000448226743734 +Gc4_128 0 n8 ns128 0 -0.000319131910405 +Gc4_129 0 n8 ns129 0 0.000390189897244 +Gc4_130 0 n8 ns130 0 -0.00395753152226 +Gc4_131 0 n8 ns131 0 0.00297376386621 +Gc4_132 0 n8 ns132 0 4.28379839691e-006 +Gc4_133 0 n8 ns133 0 0.000175003385774 +Gc4_134 0 n8 ns134 0 0.0048139883773 +Gc4_135 0 n8 ns135 0 0.00162041379452 +Gc4_136 0 n8 ns136 0 -1.14719348424e-005 +Gc4_137 0 n8 ns137 0 -8.43174041326e-005 +Gc4_138 0 n8 ns138 0 -0.000230531173428 +Gc4_139 0 n8 ns139 0 -2.522010105e-005 +Gc4_140 0 n8 ns140 0 -0.0439101324734 +Gc4_141 0 n8 ns141 0 0.0266841048634 +Gc4_142 0 n8 ns142 0 0.0013323525443 +Gc4_143 0 n8 ns143 0 -0.00470514593668 +Gc4_144 0 n8 ns144 0 -0.00026209514378 +Gc4_145 0 n8 ns145 0 0.00664024439439 +Gc4_146 0 n8 ns146 0 -2.14162912622e-005 +Gc4_147 0 n8 ns147 0 -0.000220799947646 +Gc4_148 0 n8 ns148 0 -0.00355604303472 +Gc4_149 0 n8 ns149 0 -0.00290247871389 +Gc4_150 0 n8 ns150 0 -3.29558627661e-005 +Gc4_151 0 n8 ns151 0 -0.000947570588165 +Gc4_152 0 n8 ns152 0 -0.000155631662767 +Gc4_153 0 n8 ns153 0 -4.41540711794e-005 +Gc4_154 0 n8 ns154 0 0.000311738608689 +Gc4_155 0 n8 ns155 0 0.000111813315498 +Gc4_156 0 n8 ns156 0 0.00080870004017 +Gc4_157 0 n8 ns157 0 0.000224396480722 +Gc4_158 0 n8 ns158 0 8.02933635883e-005 +Gc4_159 0 n8 ns159 0 -0.000162242965737 +Gc4_160 0 n8 ns160 0 -6.7748148073e-006 +Gc4_161 0 n8 ns161 0 -6.69335997073e-005 +Gc4_162 0 n8 ns162 0 1.07485781281e-005 +Gc4_163 0 n8 ns163 0 -6.69504811571e-005 +Gc4_164 0 n8 ns164 0 6.77408938879e-005 +Gc4_165 0 n8 ns165 0 0.000280540924412 +Gc4_166 0 n8 ns166 0 0.00236076853121 +Gc4_167 0 n8 ns167 0 -0.000131084369385 +Gc4_168 0 n8 ns168 0 -0.000355209158102 +Gc4_169 0 n8 ns169 0 5.3053415062e-005 +Gc4_170 0 n8 ns170 0 -0.0018290430588 +Gc4_171 0 n8 ns171 0 0.00236948661539 +Gc4_172 0 n8 ns172 0 -3.25022257927e-005 +Gc4_173 0 n8 ns173 0 -3.77352429932e-005 +Gc4_174 0 n8 ns174 0 2.62441215781e-005 +Gc4_175 0 n8 ns175 0 0.000168577784916 +Gc4_176 0 n8 ns176 0 0.00230461298406 +Gc4_177 0 n8 ns177 0 -0.00470410991233 +Gc4_178 0 n8 ns178 0 -0.0047882306484 +Gc4_179 0 n8 ns179 0 0.000477834180078 +Gc4_180 0 n8 ns180 0 0.00112836202807 +Gc4_181 0 n8 ns181 0 0.00663740181872 +Gc4_182 0 n8 ns182 0 -2.39006822947e-005 +Gc4_183 0 n8 ns183 0 -0.00025961808798 +Gc4_184 0 n8 ns184 0 -0.00474432002746 +Gc4_185 0 n8 ns185 0 -0.00164784320811 +Gc4_186 0 n8 ns186 0 -5.39865479352e-005 +Gc4_187 0 n8 ns187 0 0.000127825859479 +Gc4_188 0 n8 ns188 0 3.95720004194e-006 +Gc4_189 0 n8 ns189 0 5.94692776142e-005 +Gc4_190 0 n8 ns190 0 -0.00105680352242 +Gc4_191 0 n8 ns191 0 -0.000161817852869 +Gc4_192 0 n8 ns192 0 0.00109403842046 +Gc4_193 0 n8 ns193 0 0.000303422981121 +Gc4_194 0 n8 ns194 0 3.21472482696e-005 +Gc4_195 0 n8 ns195 0 -7.66159176014e-005 +Gc4_196 0 n8 ns196 0 7.28206433864e-005 +Gc4_197 0 n8 ns197 0 0.000118252809801 +Gc4_198 0 n8 ns198 0 -4.42442066205e-005 +Gc4_199 0 n8 ns199 0 -0.000208461491354 +Gc4_200 0 n8 ns200 0 0.00027249664116 +Gc4_201 0 n8 ns201 0 -0.000185821186624 +Gc4_202 0 n8 ns202 0 0.000606634777118 +Gc4_203 0 n8 ns203 0 0.000872542277729 +Gc4_204 0 n8 ns204 0 2.50133720585e-006 +Gc4_205 0 n8 ns205 0 0.000190619648524 +Gc4_206 0 n8 ns206 0 -0.00112131568272 +Gc4_207 0 n8 ns207 0 0.000360054383303 +Gc4_208 0 n8 ns208 0 0.000168414861239 +Gc4_209 0 n8 ns209 0 -5.11985897204e-005 +Gc4_210 0 n8 ns210 0 8.40316032559e-006 +Gc4_211 0 n8 ns211 0 0.000168529132735 +Gc4_212 0 n8 ns212 0 -0.00109039755742 +Gc4_213 0 n8 ns213 0 -0.00445375475264 +Gc4_214 0 n8 ns214 0 -0.000415661809996 +Gc4_215 0 n8 ns215 0 0.000422829068648 +Gc4_216 0 n8 ns216 0 0.000529137054484 +Gd4_1 0 n8 ni1 0 -0.00241183950127 +Gd4_2 0 n8 ni2 0 0.000346637647948 +Gd4_3 0 n8 ni3 0 0.00106876217783 +Gd4_4 0 n8 ni4 0 -0.00292133837239 +Gd4_5 0 n8 ni5 0 -0.00100139460077 +Gd4_6 0 n8 ni6 0 -0.00186255397218 +Gc5_1 0 n10 ns1 0 -0.00663968346268 +Gc5_2 0 n10 ns2 0 2.32928082447e-005 +Gc5_3 0 n10 ns3 0 0.000220905751813 +Gc5_4 0 n10 ns4 0 0.00354798814237 +Gc5_5 0 n10 ns5 0 0.00291321913133 +Gc5_6 0 n10 ns6 0 2.98259786091e-005 +Gc5_7 0 n10 ns7 0 0.000995807015801 +Gc5_8 0 n10 ns8 0 0.000165240210391 +Gc5_9 0 n10 ns9 0 5.70022007585e-005 +Gc5_10 0 n10 ns10 0 -0.00033783224087 +Gc5_11 0 n10 ns11 0 -0.000118022096325 +Gc5_12 0 n10 ns12 0 -0.000819155594822 +Gc5_13 0 n10 ns13 0 -0.000222187839688 +Gc5_14 0 n10 ns14 0 -8.46444536367e-005 +Gc5_15 0 n10 ns15 0 0.000153251072481 +Gc5_16 0 n10 ns16 0 3.4635981976e-005 +Gc5_17 0 n10 ns17 0 8.89552426338e-005 +Gc5_18 0 n10 ns18 0 -1.38104966206e-005 +Gc5_19 0 n10 ns19 0 9.43241492637e-005 +Gc5_20 0 n10 ns20 0 -0.000103942822867 +Gc5_21 0 n10 ns21 0 -0.000398018152595 +Gc5_22 0 n10 ns22 0 -0.00252261650477 +Gc5_23 0 n10 ns23 0 0.00243780340802 +Gc5_24 0 n10 ns24 0 0.000141962715559 +Gc5_25 0 n10 ns25 0 -0.000412682081701 +Gc5_26 0 n10 ns26 0 0.00408811602292 +Gc5_27 0 n10 ns27 0 -0.00410767176791 +Gc5_28 0 n10 ns28 0 6.90326697295e-005 +Gc5_29 0 n10 ns29 0 -2.24234557267e-005 +Gc5_30 0 n10 ns30 0 -0.000370935793673 +Gc5_31 0 n10 ns31 0 -0.000149744790712 +Gc5_32 0 n10 ns32 0 -2.85478188385e-005 +Gc5_33 0 n10 ns33 0 -0.000246848951439 +Gc5_34 0 n10 ns34 0 0.00330792942618 +Gc5_35 0 n10 ns35 0 -0.00173481385401 +Gc5_36 0 n10 ns36 0 -0.00101495466892 +Gc5_37 0 n10 ns37 0 -0.00669566736146 +Gc5_38 0 n10 ns38 0 -6.39582983225e-005 +Gc5_39 0 n10 ns39 0 -0.000422162361149 +Gc5_40 0 n10 ns40 0 -0.00754437176588 +Gc5_41 0 n10 ns41 0 -0.00536139889599 +Gc5_42 0 n10 ns42 0 -4.05711700786e-005 +Gc5_43 0 n10 ns43 0 -0.00194934874944 +Gc5_44 0 n10 ns44 0 -0.000242230547396 +Gc5_45 0 n10 ns45 0 3.80964994479e-005 +Gc5_46 0 n10 ns46 0 -9.41955532358e-005 +Gc5_47 0 n10 ns47 0 -5.06734388744e-005 +Gc5_48 0 n10 ns48 0 -0.000574058687443 +Gc5_49 0 n10 ns49 0 -0.000157669984009 +Gc5_50 0 n10 ns50 0 -0.000369623048675 +Gc5_51 0 n10 ns51 0 0.000497243930525 +Gc5_52 0 n10 ns52 0 -1.36221737106e-005 +Gc5_53 0 n10 ns53 0 -0.000188430286926 +Gc5_54 0 n10 ns54 0 1.18525060249e-005 +Gc5_55 0 n10 ns55 0 -1.41723919975e-005 +Gc5_56 0 n10 ns56 0 -0.000285670479536 +Gc5_57 0 n10 ns57 0 -0.000249318963462 +Gc5_58 0 n10 ns58 0 0.000869783613418 +Gc5_59 0 n10 ns59 0 -0.00310613707763 +Gc5_60 0 n10 ns60 0 0.000905035871371 +Gc5_61 0 n10 ns61 0 0.00113611129344 +Gc5_62 0 n10 ns62 0 -0.00648537604851 +Gc5_63 0 n10 ns63 0 -0.0131168762756 +Gc5_64 0 n10 ns64 0 1.20655058003e-005 +Gc5_65 0 n10 ns65 0 -5.1076543571e-005 +Gc5_66 0 n10 ns66 0 7.08150458672e-005 +Gc5_67 0 n10 ns67 0 6.39572856956e-005 +Gc5_68 0 n10 ns68 0 0.0178744316345 +Gc5_69 0 n10 ns69 0 -0.00835882563011 +Gc5_70 0 n10 ns70 0 0.00323231483872 +Gc5_71 0 n10 ns71 0 -0.00270741418795 +Gc5_72 0 n10 ns72 0 0.000465701567395 +Gc5_73 0 n10 ns73 0 -0.00664104481303 +Gc5_74 0 n10 ns74 0 3.27943583318e-005 +Gc5_75 0 n10 ns75 0 0.000211326752546 +Gc5_76 0 n10 ns76 0 0.00390493632498 +Gc5_77 0 n10 ns77 0 0.00254623489535 +Gc5_78 0 n10 ns78 0 3.61385070779e-005 +Gc5_79 0 n10 ns79 0 0.000284204587482 +Gc5_80 0 n10 ns80 0 -2.72736650532e-005 +Gc5_81 0 n10 ns81 0 1.51393830575e-005 +Gc5_82 0 n10 ns82 0 0.000372044538118 +Gc5_83 0 n10 ns83 0 0.000113689242657 +Gc5_84 0 n10 ns84 0 -0.0007976747828 +Gc5_85 0 n10 ns85 0 -0.000227901636607 +Gc5_86 0 n10 ns86 0 -0.000139407969703 +Gc5_87 0 n10 ns87 0 0.000286709134339 +Gc5_88 0 n10 ns88 0 6.59558465202e-005 +Gc5_89 0 n10 ns89 0 0.00035753588059 +Gc5_90 0 n10 ns90 0 5.35553032456e-006 +Gc5_91 0 n10 ns91 0 -4.97923287314e-005 +Gc5_92 0 n10 ns92 0 0.000112357534701 +Gc5_93 0 n10 ns93 0 0.000514281624826 +Gc5_94 0 n10 ns94 0 -6.97170438376e-005 +Gc5_95 0 n10 ns95 0 0.000251993592137 +Gc5_96 0 n10 ns96 0 0.000169416859341 +Gc5_97 0 n10 ns97 0 -0.000339793810076 +Gc5_98 0 n10 ns98 0 -0.00129136122757 +Gc5_99 0 n10 ns99 0 -0.000944294049255 +Gc5_100 0 n10 ns100 0 -8.33704693042e-005 +Gc5_101 0 n10 ns101 0 0.000200145009621 +Gc5_102 0 n10 ns102 0 -3.03817632522e-006 +Gc5_103 0 n10 ns103 0 4.04574336787e-005 +Gc5_104 0 n10 ns104 0 0.00163465103474 +Gc5_105 0 n10 ns105 0 0.0010569261746 +Gc5_106 0 n10 ns106 0 -0.0011019695612 +Gc5_107 0 n10 ns107 0 -0.000597631205501 +Gc5_108 0 n10 ns108 0 0.00012307284133 +Gc5_109 0 n10 ns109 0 0.00664108117485 +Gc5_110 0 n10 ns110 0 -2.33365414961e-005 +Gc5_111 0 n10 ns111 0 -0.000218483500399 +Gc5_112 0 n10 ns112 0 -0.00356167553872 +Gc5_113 0 n10 ns113 0 -0.00289766936294 +Gc5_114 0 n10 ns114 0 -3.37243784916e-005 +Gc5_115 0 n10 ns115 0 -0.000946929199104 +Gc5_116 0 n10 ns116 0 -0.000155944695054 +Gc5_117 0 n10 ns117 0 -4.24347407731e-005 +Gc5_118 0 n10 ns118 0 0.000311281008864 +Gc5_119 0 n10 ns119 0 0.000111621092942 +Gc5_120 0 n10 ns120 0 0.000808223694384 +Gc5_121 0 n10 ns121 0 0.000224511679369 +Gc5_122 0 n10 ns122 0 8.04006326806e-005 +Gc5_123 0 n10 ns123 0 -0.000162069632268 +Gc5_124 0 n10 ns124 0 -7.00694128491e-006 +Gc5_125 0 n10 ns125 0 -6.72049460598e-005 +Gc5_126 0 n10 ns126 0 1.06002755992e-005 +Gc5_127 0 n10 ns127 0 -6.66990000575e-005 +Gc5_128 0 n10 ns128 0 6.99541283469e-005 +Gc5_129 0 n10 ns129 0 0.000275852901831 +Gc5_130 0 n10 ns130 0 0.00235868885028 +Gc5_131 0 n10 ns131 0 -0.000147527634618 +Gc5_132 0 n10 ns132 0 -0.000355932148155 +Gc5_133 0 n10 ns133 0 5.39939397031e-005 +Gc5_134 0 n10 ns134 0 -0.00187294937312 +Gc5_135 0 n10 ns135 0 0.00239941511257 +Gc5_136 0 n10 ns136 0 -3.23077290691e-005 +Gc5_137 0 n10 ns137 0 -3.79835959244e-005 +Gc5_138 0 n10 ns138 0 2.63416853165e-005 +Gc5_139 0 n10 ns139 0 0.000168635324337 +Gc5_140 0 n10 ns140 0 0.002315136491 +Gc5_141 0 n10 ns141 0 -0.00459659792506 +Gc5_142 0 n10 ns142 0 -0.00480357027426 +Gc5_143 0 n10 ns143 0 0.000460600006712 +Gc5_144 0 n10 ns144 0 0.00111147107884 +Gc5_145 0 n10 ns145 0 0.00671052728921 +Gc5_146 0 n10 ns146 0 4.96934357611e-005 +Gc5_147 0 n10 ns147 0 0.000435936751677 +Gc5_148 0 n10 ns148 0 0.00755626149876 +Gc5_149 0 n10 ns149 0 0.0053275681667 +Gc5_150 0 n10 ns150 0 5.69921008497e-005 +Gc5_151 0 n10 ns151 0 0.00186658638929 +Gc5_152 0 n10 ns152 0 0.000251470260152 +Gc5_153 0 n10 ns153 0 -5.32140810417e-005 +Gc5_154 0 n10 ns154 0 0.000120561876639 +Gc5_155 0 n10 ns155 0 3.69353933539e-005 +Gc5_156 0 n10 ns156 0 0.000592219953068 +Gc5_157 0 n10 ns157 0 0.000152590084827 +Gc5_158 0 n10 ns158 0 0.000352687818481 +Gc5_159 0 n10 ns159 0 -0.000473235053931 +Gc5_160 0 n10 ns160 0 -1.269579793e-005 +Gc5_161 0 n10 ns161 0 0.000131040738689 +Gc5_162 0 n10 ns162 0 -1.02226546478e-005 +Gc5_163 0 n10 ns163 0 1.4078908912e-005 +Gc5_164 0 n10 ns164 0 0.00025545822735 +Gc5_165 0 n10 ns165 0 0.000170668892225 +Gc5_166 0 n10 ns166 0 -0.000721169489584 +Gc5_167 0 n10 ns167 0 0.00102216920951 +Gc5_168 0 n10 ns168 0 -0.000467267087709 +Gc5_169 0 n10 ns169 0 -0.000644766860531 +Gc5_170 0 n10 ns170 0 0.00113046944191 +Gc5_171 0 n10 ns171 0 0.0115810106154 +Gc5_172 0 n10 ns172 0 -3.0506477958e-005 +Gc5_173 0 n10 ns173 0 1.94651908327e-005 +Gc5_174 0 n10 ns174 0 0.000118827480458 +Gc5_175 0 n10 ns175 0 -5.01631095198e-005 +Gc5_176 0 n10 ns176 0 -0.0412084015933 +Gc5_177 0 n10 ns177 0 0.0131187173032 +Gc5_178 0 n10 ns178 0 -0.00653921662784 +Gc5_179 0 n10 ns179 0 0.00363127844563 +Gc5_180 0 n10 ns180 0 0.00266220505239 +Gc5_181 0 n10 ns181 0 0.00663544847578 +Gc5_182 0 n10 ns182 0 -2.80746452304e-005 +Gc5_183 0 n10 ns183 0 -0.000215873782858 +Gc5_184 0 n10 ns184 0 -0.00388572872307 +Gc5_185 0 n10 ns185 0 -0.00255839358521 +Gc5_186 0 n10 ns186 0 -3.27845831741e-005 +Gc5_187 0 n10 ns187 0 -0.000247594986917 +Gc5_188 0 n10 ns188 0 2.85988170826e-005 +Gc5_189 0 n10 ns189 0 -2.39344977342e-005 +Gc5_190 0 n10 ns190 0 -0.000355481123567 +Gc5_191 0 n10 ns191 0 -0.000102370541587 +Gc5_192 0 n10 ns192 0 0.000798555877385 +Gc5_193 0 n10 ns193 0 0.000224115078728 +Gc5_194 0 n10 ns194 0 0.000132469427802 +Gc5_195 0 n10 ns195 0 -0.000270011499066 +Gc5_196 0 n10 ns196 0 -5.58670815368e-005 +Gc5_197 0 n10 ns197 0 -0.000310241731398 +Gc5_198 0 n10 ns198 0 -1.06516187988e-005 +Gc5_199 0 n10 ns199 0 2.26933319214e-005 +Gc5_200 0 n10 ns200 0 8.12628638615e-005 +Gc5_201 0 n10 ns201 0 -0.000274353213131 +Gc5_202 0 n10 ns202 0 0.000251960562745 +Gc5_203 0 n10 ns203 0 -0.000331350954698 +Gc5_204 0 n10 ns204 0 -0.000326247285769 +Gc5_205 0 n10 ns205 0 0.000165552439434 +Gc5_206 0 n10 ns206 0 0.00379039981646 +Gc5_207 0 n10 ns207 0 0.00317929143241 +Gc5_208 0 n10 ns208 0 7.4007051589e-005 +Gc5_209 0 n10 ns209 0 -9.51758755943e-005 +Gc5_210 0 n10 ns210 0 0.000121846148392 +Gc5_211 0 n10 ns211 0 -4.87552286387e-005 +Gc5_212 0 n10 ns212 0 0.00135087553319 +Gc5_213 0 n10 ns213 0 -0.0063760304199 +Gc5_214 0 n10 ns214 0 -6.17231531658e-005 +Gc5_215 0 n10 ns215 0 0.000575511605651 +Gc5_216 0 n10 ns216 0 -0.00265866217451 +Gd5_1 0 n10 ni1 0 -0.000126309749954 +Gd5_2 0 n10 ni2 0 -0.00173293804166 +Gd5_3 0 n10 ni3 0 0.000440547682424 +Gd5_4 0 n10 ni4 0 -0.000972677018512 +Gd5_5 0 n10 ni5 0 -0.0040098896141 +Gd5_6 0 n10 ni6 0 -0.000769680350982 +Gc6_1 0 n12 ns1 0 -0.00663690221638 +Gc6_2 0 n12 ns2 0 2.60172493748e-005 +Gc6_3 0 n12 ns3 0 0.000258828847669 +Gc6_4 0 n12 ns4 0 0.00474228736993 +Gc6_5 0 n12 ns5 0 0.00165286327736 +Gc6_6 0 n12 ns6 0 5.1833401866e-005 +Gc6_7 0 n12 ns7 0 -0.000134992388962 +Gc6_8 0 n12 ns8 0 -5.42646089704e-006 +Gc6_9 0 n12 ns9 0 -5.19239008164e-005 +Gc6_10 0 n12 ns10 0 0.00113997775871 +Gc6_11 0 n12 ns11 0 0.000172790450988 +Gc6_12 0 n12 ns12 0 -0.00110818947948 +Gc6_13 0 n12 ns13 0 -0.0003005685238 +Gc6_14 0 n12 ns14 0 -3.70463301698e-005 +Gc6_15 0 n12 ns15 0 7.02261654086e-005 +Gc6_16 0 n12 ns16 0 -0.000123786646499 +Gc6_17 0 n12 ns17 0 -0.000162441977311 +Gc6_18 0 n12 ns18 0 9.23149438841e-005 +Gc6_19 0 n12 ns19 0 0.000301966283991 +Gc6_20 0 n12 ns20 0 0.00142257223683 +Gc6_21 0 n12 ns21 0 0.000718554576862 +Gc6_22 0 n12 ns22 0 -0.00165712580759 +Gc6_23 0 n12 ns23 0 -0.00115014920086 +Gc6_24 0 n12 ns24 0 -0.000201160397339 +Gc6_25 0 n12 ns25 0 -0.000109990120869 +Gc6_26 0 n12 ns26 0 0.00196798647289 +Gc6_27 0 n12 ns27 0 -0.00133277306052 +Gc6_28 0 n12 ns28 0 4.09041141173e-005 +Gc6_29 0 n12 ns29 0 0.000127848072743 +Gc6_30 0 n12 ns30 0 -0.000349225996186 +Gc6_31 0 n12 ns31 0 -0.000219992353605 +Gc6_32 0 n12 ns32 0 0.00335508177778 +Gc6_33 0 n12 ns33 0 -0.000401124624863 +Gc6_34 0 n12 ns34 0 -0.00136267565696 +Gc6_35 0 n12 ns35 0 -0.00226367311476 +Gc6_36 0 n12 ns36 0 0.000314906874602 +Gc6_37 0 n12 ns37 0 -0.00663471347477 +Gc6_38 0 n12 ns38 0 2.9320712932e-005 +Gc6_39 0 n12 ns39 0 0.000216670378058 +Gc6_40 0 n12 ns40 0 0.00387813667132 +Gc6_41 0 n12 ns41 0 0.00256837355784 +Gc6_42 0 n12 ns42 0 2.95763898112e-005 +Gc6_43 0 n12 ns43 0 0.000259065169741 +Gc6_44 0 n12 ns44 0 -3.10589204832e-005 +Gc6_45 0 n12 ns45 0 3.12202553848e-005 +Gc6_46 0 n12 ns46 0 0.00033869186796 +Gc6_47 0 n12 ns47 0 0.00010724077212 +Gc6_48 0 n12 ns48 0 -0.000776292546917 +Gc6_49 0 n12 ns49 0 -0.000220749360185 +Gc6_50 0 n12 ns50 0 -0.000140344587802 +Gc6_51 0 n12 ns51 0 0.000278499858884 +Gc6_52 0 n12 ns52 0 0.000124808846686 +Gc6_53 0 n12 ns53 0 0.000433795662434 +Gc6_54 0 n12 ns54 0 -5.71757957408e-006 +Gc6_55 0 n12 ns55 0 -4.67147892309e-005 +Gc6_56 0 n12 ns56 0 0.00116896028029 +Gc6_57 0 n12 ns57 0 0.000973830470796 +Gc6_58 0 n12 ns58 0 0.000553695021363 +Gc6_59 0 n12 ns59 0 0.000547813904314 +Gc6_60 0 n12 ns60 0 0.000607991029854 +Gc6_61 0 n12 ns61 0 -0.000334731682807 +Gc6_62 0 n12 ns62 0 -0.00559114207859 +Gc6_63 0 n12 ns63 0 -0.00225576183708 +Gc6_64 0 n12 ns64 0 7.91057236701e-005 +Gc6_65 0 n12 ns65 0 5.5095960551e-005 +Gc6_66 0 n12 ns66 0 6.47915513099e-005 +Gc6_67 0 n12 ns67 0 9.76882758846e-005 +Gc6_68 0 n12 ns68 0 0.0012625844123 +Gc6_69 0 n12 ns69 0 0.00163996254522 +Gc6_70 0 n12 ns70 0 -0.00127730567553 +Gc6_71 0 n12 ns71 0 -2.63024182351e-005 +Gc6_72 0 n12 ns72 0 0.00137017771085 +Gc6_73 0 n12 ns73 0 -0.0066976648405 +Gc6_74 0 n12 ns74 0 -6.73213770938e-005 +Gc6_75 0 n12 ns75 0 -0.000459820658233 +Gc6_76 0 n12 ns76 0 -0.0086510035546 +Gc6_77 0 n12 ns77 0 -0.0041740461427 +Gc6_78 0 n12 ns78 0 -6.4434699167e-005 +Gc6_79 0 n12 ns79 0 -2.88780033172e-005 +Gc6_80 0 n12 ns80 0 3.51207701127e-005 +Gc6_81 0 n12 ns81 0 0.000137515497826 +Gc6_82 0 n12 ns82 0 -0.00125419644772 +Gc6_83 0 n12 ns83 0 -0.000171852459084 +Gc6_84 0 n12 ns84 0 -0.00107681204083 +Gc6_85 0 n12 ns85 0 -0.000323638459411 +Gc6_86 0 n12 ns86 0 -4.36533673597e-005 +Gc6_87 0 n12 ns87 0 0.000154448884195 +Gc6_88 0 n12 ns88 0 -0.000314438759142 +Gc6_89 0 n12 ns89 0 -0.000745791988875 +Gc6_90 0 n12 ns90 0 -5.65157533165e-005 +Gc6_91 0 n12 ns91 0 -0.000160519648975 +Gc6_92 0 n12 ns92 0 -0.00679034511121 +Gc6_93 0 n12 ns93 0 -0.0066603793086 +Gc6_94 0 n12 ns94 0 -0.000167719923309 +Gc6_95 0 n12 ns95 0 -0.000215529958966 +Gc6_96 0 n12 ns96 0 -0.000167958063813 +Gc6_97 0 n12 ns97 0 -9.43440584728e-005 +Gc6_98 0 n12 ns98 0 -0.00115096747175 +Gc6_99 0 n12 ns99 0 -0.00147590466945 +Gc6_100 0 n12 ns100 0 -0.00080213568961 +Gc6_101 0 n12 ns101 0 -0.000249671505622 +Gc6_102 0 n12 ns102 0 -1.69467799649e-005 +Gc6_103 0 n12 ns103 0 3.75140976296e-005 +Gc6_104 0 n12 ns104 0 0.00191423432156 +Gc6_105 0 n12 ns105 0 -0.00643997124299 +Gc6_106 0 n12 ns106 0 0.00858475144783 +Gc6_107 0 n12 ns107 0 0.000243139846767 +Gc6_108 0 n12 ns108 0 0.00127854511106 +Gc6_109 0 n12 ns109 0 0.00663808942027 +Gc6_110 0 n12 ns110 0 -2.57473902064e-005 +Gc6_111 0 n12 ns111 0 -0.000256957008627 +Gc6_112 0 n12 ns112 0 -0.00475359207122 +Gc6_113 0 n12 ns113 0 -0.00163901147923 +Gc6_114 0 n12 ns114 0 -5.5649981442e-005 +Gc6_115 0 n12 ns115 0 0.000128466095224 +Gc6_116 0 n12 ns116 0 4.30084437474e-006 +Gc6_117 0 n12 ns117 0 6.39171922005e-005 +Gc6_118 0 n12 ns118 0 -0.0010564742614 +Gc6_119 0 n12 ns119 0 -0.000162769636438 +Gc6_120 0 n12 ns120 0 0.00109336447477 +Gc6_121 0 n12 ns121 0 0.000303271582497 +Gc6_122 0 n12 ns122 0 3.22244197139e-005 +Gc6_123 0 n12 ns123 0 -7.622032507e-005 +Gc6_124 0 n12 ns124 0 7.21855283168e-005 +Gc6_125 0 n12 ns125 0 0.000117788647305 +Gc6_126 0 n12 ns126 0 -4.44311237073e-005 +Gc6_127 0 n12 ns127 0 -0.000207780631921 +Gc6_128 0 n12 ns128 0 0.000274595520805 +Gc6_129 0 n12 ns129 0 -0.000193987661311 +Gc6_130 0 n12 ns130 0 0.00060589857151 +Gc6_131 0 n12 ns131 0 0.000854438229596 +Gc6_132 0 n12 ns132 0 2.13414319911e-006 +Gc6_133 0 n12 ns133 0 0.000191271098702 +Gc6_134 0 n12 ns134 0 -0.00118670605531 +Gc6_135 0 n12 ns135 0 0.000376244960299 +Gc6_136 0 n12 ns136 0 0.000168771628922 +Gc6_137 0 n12 ns137 0 -5.07775992951e-005 +Gc6_138 0 n12 ns138 0 8.87256205552e-006 +Gc6_139 0 n12 ns139 0 0.00016861414665 +Gc6_140 0 n12 ns140 0 -0.00115694914391 +Gc6_141 0 n12 ns141 0 -0.0043424443309 +Gc6_142 0 n12 ns142 0 -0.000350301266152 +Gc6_143 0 n12 ns143 0 0.000415928665769 +Gc6_144 0 n12 ns144 0 0.000508553716797 +Gc6_145 0 n12 ns145 0 0.00663636617487 +Gc6_146 0 n12 ns146 0 -2.95509619224e-005 +Gc6_147 0 n12 ns147 0 -0.000213851096438 +Gc6_148 0 n12 ns148 0 -0.0038933730385 +Gc6_149 0 n12 ns149 0 -0.0025513665079 +Gc6_150 0 n12 ns150 0 -3.38046502403e-005 +Gc6_151 0 n12 ns151 0 -0.000247525071949 +Gc6_152 0 n12 ns152 0 2.75712572856e-005 +Gc6_153 0 n12 ns153 0 -2.55028626443e-005 +Gc6_154 0 n12 ns154 0 -0.000356209202471 +Gc6_155 0 n12 ns155 0 -0.000101950314043 +Gc6_156 0 n12 ns156 0 0.000798111093068 +Gc6_157 0 n12 ns157 0 0.000224469214962 +Gc6_158 0 n12 ns158 0 0.000132428499602 +Gc6_159 0 n12 ns159 0 -0.000270203519335 +Gc6_160 0 n12 ns160 0 -5.54063403602e-005 +Gc6_161 0 n12 ns161 0 -0.000309900083412 +Gc6_162 0 n12 ns162 0 -1.05363783769e-005 +Gc6_163 0 n12 ns163 0 2.228621196e-005 +Gc6_164 0 n12 ns164 0 7.55130863513e-005 +Gc6_165 0 n12 ns165 0 -0.000270755167423 +Gc6_166 0 n12 ns166 0 0.000241641996584 +Gc6_167 0 n12 ns167 0 -0.000320432259436 +Gc6_168 0 n12 ns168 0 -0.000325478440142 +Gc6_169 0 n12 ns169 0 0.000165530902054 +Gc6_170 0 n12 ns170 0 0.00381708385929 +Gc6_171 0 n12 ns171 0 0.00322393346635 +Gc6_172 0 n12 ns172 0 7.37460252761e-005 +Gc6_173 0 n12 ns173 0 -9.47047077927e-005 +Gc6_174 0 n12 ns174 0 0.000122121515841 +Gc6_175 0 n12 ns175 0 -4.84619253989e-005 +Gc6_176 0 n12 ns176 0 0.00155571444993 +Gc6_177 0 n12 ns177 0 -0.00626603552275 +Gc6_178 0 n12 ns178 0 -0.000272297817468 +Gc6_179 0 n12 ns179 0 0.000534613262877 +Gc6_180 0 n12 ns180 0 -0.00267745840768 +Gc6_181 0 n12 ns181 0 0.00671369743454 +Gc6_182 0 n12 ns182 0 5.17001331653e-005 +Gc6_183 0 n12 ns183 0 0.000475722380005 +Gc6_184 0 n12 ns184 0 0.00865958065652 +Gc6_185 0 n12 ns185 0 0.00414208959066 +Gc6_186 0 n12 ns186 0 8.0065339438e-005 +Gc6_187 0 n12 ns187 0 2.46456696393e-005 +Gc6_188 0 n12 ns188 0 -5.76322299947e-006 +Gc6_189 0 n12 ns189 0 -0.000141594352364 +Gc6_190 0 n12 ns190 0 0.00121495216002 +Gc6_191 0 n12 ns191 0 0.000142492100286 +Gc6_192 0 n12 ns192 0 0.00108055604439 +Gc6_193 0 n12 ns193 0 0.000308753855164 +Gc6_194 0 n12 ns194 0 4.20716844379e-005 +Gc6_195 0 n12 ns195 0 -0.000138778291595 +Gc6_196 0 n12 ns196 0 0.000293028358825 +Gc6_197 0 n12 ns197 0 0.000639121915687 +Gc6_198 0 n12 ns198 0 1.90866078338e-005 +Gc6_199 0 n12 ns199 0 0.000100275576012 +Gc6_200 0 n12 ns200 0 0.00371594755236 +Gc6_201 0 n12 ns201 0 0.00523865889471 +Gc6_202 0 n12 ns202 0 0.000495044535292 +Gc6_203 0 n12 ns203 0 0.000270969073364 +Gc6_204 0 n12 ns204 0 7.90095171669e-005 +Gc6_205 0 n12 ns205 0 0.000162848402854 +Gc6_206 0 n12 ns206 0 0.00220290918501 +Gc6_207 0 n12 ns207 0 0.000709406028091 +Gc6_208 0 n12 ns208 0 0.000415925187717 +Gc6_209 0 n12 ns209 0 0.000249060331917 +Gc6_210 0 n12 ns210 0 0.000126286296914 +Gc6_211 0 n12 ns211 0 -8.22709426951e-006 +Gc6_212 0 n12 ns212 0 -0.0267286442418 +Gc6_213 0 n12 ns213 0 0.00940637771128 +Gc6_214 0 n12 ns214 0 -0.00939277286633 +Gc6_215 0 n12 ns215 0 0.00155673442442 +Gc6_216 0 n12 ns216 0 -0.000459929196871 +Gd6_1 0 n12 ni1 0 0.000299339466599 +Gd6_2 0 n12 ni2 0 0.000159040982099 +Gd6_3 0 n12 ni3 0 -0.00396028304195 +Gd6_4 0 n12 ni4 0 -0.00185255909734 +Gd6_5 0 n12 ni5 0 -0.000681551993014 +Gd6_6 0 n12 ni6 0 -0.00166451427546 +.ends + +*$ +* BEGIN ANSOFT HEADER +* node 1 Port1 +* node 2 Port2 +* node 3 Port3 +* node 4 Port4 +* node 5 Port5 +* node 6 Port6 +* Project: Project10 +* Format: PSpice +* Topckt: s744837002460_2_sp +* Date: Thu May 28 10:03:19 2020 +* Notes: Frequency range: 0 to 1e+009 Hz, 502 points +* : Maximum number of poles: 10000 +* : S-Matrix fitting error tolerance: 0.005 +* : Causality check tolerance: auto +* : Passivity enforcement: off +* : Causality enforcement: off +* : Fitting method: TWA +* : Matrix fitting: By entire matrix +* : Ensure Z-parameter accuracy: on +* : Relative error control: off +* : Common ground option: on +* : Final fitting error: 0.00689383 +* : Final model order: 450 +* END ANSOFT HEADER + +.subckt 744837002460 1 2 3 6 5 4 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 6331587.52368 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 53092.0957602 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 13263.7345565 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 6737.05345859 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 2289.90455735 +Ca6 ns6 0 1e-012 +Ca7 ns7 0 1e-012 +Ra6 ns6 0 18302.104562 +Ra7 ns7 0 18302.104562 +Ga6 ns6 0 ns7 0 0.000617458441383 +Ga7 ns7 0 ns6 0 -0.000617458441383 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 3982.32923659 +Ra9 ns9 0 3982.32923659 +Ga8 ns8 0 ns9 0 0.0011382900548 +Ga9 ns9 0 ns8 0 -0.0011382900548 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 6190.23212565 +Ra11 ns11 0 6190.23212565 +Ga10 ns10 0 ns11 0 0.001275504789 +Ga11 ns11 0 ns10 0 -0.001275504789 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 1028.23945703 +Ra13 ns13 0 1028.23945703 +Ga12 ns12 0 ns13 0 -0.000863059182564 +Ga13 ns13 0 ns12 0 0.000863059182564 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 4245.09858935 +Ra15 ns15 0 4245.09858935 +Ga14 ns14 0 ns15 0 0.00137593972572 +Ga15 ns15 0 ns14 0 -0.00137593972572 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 11532.8477904 +Ra17 ns17 0 11532.8477904 +Ga16 ns16 0 ns17 0 0.00155320169346 +Ga17 ns17 0 ns16 0 -0.00155320169346 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 21758.9645403 +Ra19 ns19 0 21758.9645403 +Ga18 ns18 0 ns19 0 0.00160285125485 +Ga19 ns19 0 ns18 0 -0.00160285125485 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 20309.2225097 +Ra21 ns21 0 20309.2225097 +Ga20 ns20 0 ns21 0 0.00172215743413 +Ga21 ns21 0 ns20 0 -0.00172215743413 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 30981.8030017 +Ra23 ns23 0 30981.8030017 +Ga22 ns22 0 ns23 0 0.0017373931074 +Ga23 ns23 0 ns22 0 -0.0017373931074 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 3317.41037863 +Ra25 ns25 0 3317.41037863 +Ga24 ns24 0 ns25 0 0.0018048307594 +Ga25 ns25 0 ns24 0 -0.0018048307594 +Ca26 ns26 0 1e-012 +Ca27 ns27 0 1e-012 +Ra26 ns26 0 38100.4687103 +Ra27 ns27 0 38100.4687103 +Ga26 ns26 0 ns27 0 0.00184062394811 +Ga27 ns27 0 ns26 0 -0.00184062394811 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 3543.48224398 +Ra29 ns29 0 3543.48224398 +Ga28 ns28 0 ns29 0 0.0020080566871 +Ga29 ns29 0 ns28 0 -0.0020080566871 +Ca30 ns30 0 1e-012 +Ca31 ns31 0 1e-012 +Ra30 ns30 0 14318.3672863 +Ra31 ns31 0 14318.3672863 +Ga30 ns30 0 ns31 0 0.00204184225892 +Ga31 ns31 0 ns30 0 -0.00204184225892 +Ca32 ns32 0 1e-012 +Ca33 ns33 0 1e-012 +Ra32 ns32 0 1102.22650745 +Ra33 ns33 0 1102.22650745 +Ga32 ns32 0 ns33 0 -0.00264690653526 +Ga33 ns33 0 ns32 0 0.00264690653526 +Ca34 ns34 0 1e-012 +Ca35 ns35 0 1e-012 +Ra34 ns34 0 3785.94130957 +Ra35 ns35 0 3785.94130957 +Ga34 ns34 0 ns35 0 -0.00281671550743 +Ga35 ns35 0 ns34 0 0.00281671550743 +Ca36 ns36 0 1e-012 +Ca37 ns37 0 1e-012 +Ra36 ns36 0 15212.9526569 +Ra37 ns37 0 15212.9526569 +Ga36 ns36 0 ns37 0 -0.00324031038854 +Ga37 ns37 0 ns36 0 0.00324031038854 +Ca38 ns38 0 1e-012 +Ca39 ns39 0 1e-012 +Ra38 ns38 0 5619.39695443 +Ra39 ns39 0 5619.39695443 +Ga38 ns38 0 ns39 0 0.00324366276672 +Ga39 ns39 0 ns38 0 -0.00324366276672 +Ca40 ns40 0 1e-012 +Ca41 ns41 0 1e-012 +Ra40 ns40 0 25637.890289 +Ra41 ns41 0 25637.890289 +Ga40 ns40 0 ns41 0 0.00355475462299 +Ga41 ns41 0 ns40 0 -0.00355475462299 +Ca42 ns42 0 1e-012 +Ca43 ns43 0 1e-012 +Ra42 ns42 0 16045.1872042 +Ra43 ns43 0 16045.1872042 +Ga42 ns42 0 ns43 0 0.00366226122782 +Ga43 ns43 0 ns42 0 -0.00366226122782 +Ca44 ns44 0 1e-012 +Ca45 ns45 0 1e-012 +Ra44 ns44 0 21687.7693218 +Ra45 ns45 0 21687.7693218 +Ga44 ns44 0 ns45 0 0.00369099997192 +Ga45 ns45 0 ns44 0 -0.00369099997192 +Ca46 ns46 0 1e-012 +Ca47 ns47 0 1e-012 +Ra46 ns46 0 1228.84909818 +Ra47 ns47 0 1228.84909818 +Ga46 ns46 0 ns47 0 0.00386601696559 +Ga47 ns47 0 ns46 0 -0.00386601696559 +Ca48 ns48 0 1e-012 +Ca49 ns49 0 1e-012 +Ra48 ns48 0 18342.1900173 +Ra49 ns49 0 18342.1900173 +Ga48 ns48 0 ns49 0 0.00399940149645 +Ga49 ns49 0 ns48 0 -0.00399940149645 +Ca50 ns50 0 1e-012 +Ca51 ns51 0 1e-012 +Ra50 ns50 0 11903.4910987 +Ra51 ns51 0 11903.4910987 +Ga50 ns50 0 ns51 0 0.00408976646903 +Ga51 ns51 0 ns50 0 -0.00408976646903 +Ca52 ns52 0 1e-012 +Ca53 ns53 0 1e-012 +Ra52 ns52 0 12692.524621 +Ra53 ns53 0 12692.524621 +Ga52 ns52 0 ns53 0 0.00414513961157 +Ga53 ns53 0 ns52 0 -0.00414513961157 +Ca54 ns54 0 1e-012 +Ca55 ns55 0 1e-012 +Ra54 ns54 0 4344.34411088 +Ra55 ns55 0 4344.34411088 +Ga54 ns54 0 ns55 0 -0.00455794741421 +Ga55 ns55 0 ns54 0 0.00455794741421 +Ca56 ns56 0 1e-012 +Ca57 ns57 0 1e-012 +Ra56 ns56 0 2901.81929778 +Ra57 ns57 0 2901.81929778 +Ga56 ns56 0 ns57 0 0.00481264175409 +Ga57 ns57 0 ns56 0 -0.00481264175409 +Ca58 ns58 0 1e-012 +Ca59 ns59 0 1e-012 +Ra58 ns58 0 5638.39578337 +Ra59 ns59 0 5638.39578337 +Ga58 ns58 0 ns59 0 0.00497765146802 +Ga59 ns59 0 ns58 0 -0.00497765146802 +Ca60 ns60 0 1e-012 +Ca61 ns61 0 1e-012 +Ra60 ns60 0 7990.11670552 +Ra61 ns61 0 7990.11670552 +Ga60 ns60 0 ns61 0 0.00517905842625 +Ga61 ns61 0 ns60 0 -0.00517905842625 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 23719.5240812 +Ra63 ns63 0 23719.5240812 +Ga62 ns62 0 ns63 0 0.0052656494058 +Ga63 ns63 0 ns62 0 -0.0052656494058 +Ca64 ns64 0 1e-012 +Ca65 ns65 0 1e-012 +Ra64 ns64 0 7652.32468773 +Ra65 ns65 0 7652.32468773 +Ga64 ns64 0 ns65 0 0.00541092047714 +Ga65 ns65 0 ns64 0 -0.00541092047714 +Ca66 ns66 0 1e-012 +Ca67 ns67 0 1e-012 +Ra66 ns66 0 4436.51193446 +Ra67 ns67 0 4436.51193446 +Ga66 ns66 0 ns67 0 0.00559439789276 +Ga67 ns67 0 ns66 0 -0.00559439789276 +Ca68 ns68 0 1e-012 +Ca69 ns69 0 1e-012 +Ra68 ns68 0 5143.60957566 +Ra69 ns69 0 5143.60957566 +Ga68 ns68 0 ns69 0 0.00577549992818 +Ga69 ns69 0 ns68 0 -0.00577549992818 +Ca70 ns70 0 1e-012 +Ca71 ns71 0 1e-012 +Ra70 ns70 0 6362.86414534 +Ra71 ns71 0 6362.86414534 +Ga70 ns70 0 ns71 0 0.0059387234503 +Ga71 ns71 0 ns70 0 -0.0059387234503 +Ca72 ns72 0 1e-012 +Ca73 ns73 0 1e-012 +Ra72 ns72 0 3112.32079105 +Ra73 ns73 0 3112.32079105 +Ga72 ns72 0 ns73 0 0.00629316475466 +Ga73 ns73 0 ns72 0 -0.00629316475466 +Ca74 ns74 0 1e-012 +Ca75 ns75 0 1e-012 +Ra74 ns74 0 17627.8949771 +Ra75 ns75 0 17627.8949771 +Ga74 ns74 0 ns75 0 0.00636797928682 +Ga75 ns75 0 ns74 0 -0.00636797928682 +Ca76 ns76 0 1e-012 +Ra76 ns76 0 6331587.52368 +Ca77 ns77 0 1e-012 +Ra77 ns77 0 53092.0957602 +Ca78 ns78 0 1e-012 +Ra78 ns78 0 13263.7345565 +Ca79 ns79 0 1e-012 +Ra79 ns79 0 6737.05345859 +Ca80 ns80 0 1e-012 +Ra80 ns80 0 2289.90455735 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 18302.104562 +Ra82 ns82 0 18302.104562 +Ga81 ns81 0 ns82 0 0.000617458441383 +Ga82 ns82 0 ns81 0 -0.000617458441383 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 3982.32923659 +Ra84 ns84 0 3982.32923659 +Ga83 ns83 0 ns84 0 0.0011382900548 +Ga84 ns84 0 ns83 0 -0.0011382900548 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 6190.23212565 +Ra86 ns86 0 6190.23212565 +Ga85 ns85 0 ns86 0 0.001275504789 +Ga86 ns86 0 ns85 0 -0.001275504789 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 1028.23945703 +Ra88 ns88 0 1028.23945703 +Ga87 ns87 0 ns88 0 -0.000863059182564 +Ga88 ns88 0 ns87 0 0.000863059182564 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 4245.09858935 +Ra90 ns90 0 4245.09858935 +Ga89 ns89 0 ns90 0 0.00137593972572 +Ga90 ns90 0 ns89 0 -0.00137593972572 +Ca91 ns91 0 1e-012 +Ca92 ns92 0 1e-012 +Ra91 ns91 0 11532.8477904 +Ra92 ns92 0 11532.8477904 +Ga91 ns91 0 ns92 0 0.00155320169346 +Ga92 ns92 0 ns91 0 -0.00155320169346 +Ca93 ns93 0 1e-012 +Ca94 ns94 0 1e-012 +Ra93 ns93 0 21758.9645403 +Ra94 ns94 0 21758.9645403 +Ga93 ns93 0 ns94 0 0.00160285125485 +Ga94 ns94 0 ns93 0 -0.00160285125485 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 20309.2225097 +Ra96 ns96 0 20309.2225097 +Ga95 ns95 0 ns96 0 0.00172215743413 +Ga96 ns96 0 ns95 0 -0.00172215743413 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 30981.8030017 +Ra98 ns98 0 30981.8030017 +Ga97 ns97 0 ns98 0 0.0017373931074 +Ga98 ns98 0 ns97 0 -0.0017373931074 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 3317.41037863 +Ra100 ns100 0 3317.41037863 +Ga99 ns99 0 ns100 0 0.0018048307594 +Ga100 ns100 0 ns99 0 -0.0018048307594 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 38100.4687103 +Ra102 ns102 0 38100.4687103 +Ga101 ns101 0 ns102 0 0.00184062394811 +Ga102 ns102 0 ns101 0 -0.00184062394811 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 3543.48224398 +Ra104 ns104 0 3543.48224398 +Ga103 ns103 0 ns104 0 0.0020080566871 +Ga104 ns104 0 ns103 0 -0.0020080566871 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 14318.3672863 +Ra106 ns106 0 14318.3672863 +Ga105 ns105 0 ns106 0 0.00204184225892 +Ga106 ns106 0 ns105 0 -0.00204184225892 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 1102.22650745 +Ra108 ns108 0 1102.22650745 +Ga107 ns107 0 ns108 0 -0.00264690653526 +Ga108 ns108 0 ns107 0 0.00264690653526 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 3785.94130957 +Ra110 ns110 0 3785.94130957 +Ga109 ns109 0 ns110 0 -0.00281671550743 +Ga110 ns110 0 ns109 0 0.00281671550743 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 15212.9526569 +Ra112 ns112 0 15212.9526569 +Ga111 ns111 0 ns112 0 -0.00324031038854 +Ga112 ns112 0 ns111 0 0.00324031038854 +Ca113 ns113 0 1e-012 +Ca114 ns114 0 1e-012 +Ra113 ns113 0 5619.39695443 +Ra114 ns114 0 5619.39695443 +Ga113 ns113 0 ns114 0 0.00324366276672 +Ga114 ns114 0 ns113 0 -0.00324366276672 +Ca115 ns115 0 1e-012 +Ca116 ns116 0 1e-012 +Ra115 ns115 0 25637.890289 +Ra116 ns116 0 25637.890289 +Ga115 ns115 0 ns116 0 0.00355475462299 +Ga116 ns116 0 ns115 0 -0.00355475462299 +Ca117 ns117 0 1e-012 +Ca118 ns118 0 1e-012 +Ra117 ns117 0 16045.1872042 +Ra118 ns118 0 16045.1872042 +Ga117 ns117 0 ns118 0 0.00366226122782 +Ga118 ns118 0 ns117 0 -0.00366226122782 +Ca119 ns119 0 1e-012 +Ca120 ns120 0 1e-012 +Ra119 ns119 0 21687.7693218 +Ra120 ns120 0 21687.7693218 +Ga119 ns119 0 ns120 0 0.00369099997192 +Ga120 ns120 0 ns119 0 -0.00369099997192 +Ca121 ns121 0 1e-012 +Ca122 ns122 0 1e-012 +Ra121 ns121 0 1228.84909818 +Ra122 ns122 0 1228.84909818 +Ga121 ns121 0 ns122 0 0.00386601696559 +Ga122 ns122 0 ns121 0 -0.00386601696559 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 18342.1900173 +Ra124 ns124 0 18342.1900173 +Ga123 ns123 0 ns124 0 0.00399940149645 +Ga124 ns124 0 ns123 0 -0.00399940149645 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 11903.4910987 +Ra126 ns126 0 11903.4910987 +Ga125 ns125 0 ns126 0 0.00408976646903 +Ga126 ns126 0 ns125 0 -0.00408976646903 +Ca127 ns127 0 1e-012 +Ca128 ns128 0 1e-012 +Ra127 ns127 0 12692.524621 +Ra128 ns128 0 12692.524621 +Ga127 ns127 0 ns128 0 0.00414513961157 +Ga128 ns128 0 ns127 0 -0.00414513961157 +Ca129 ns129 0 1e-012 +Ca130 ns130 0 1e-012 +Ra129 ns129 0 4344.34411088 +Ra130 ns130 0 4344.34411088 +Ga129 ns129 0 ns130 0 -0.00455794741421 +Ga130 ns130 0 ns129 0 0.00455794741421 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 2901.81929778 +Ra132 ns132 0 2901.81929778 +Ga131 ns131 0 ns132 0 0.00481264175409 +Ga132 ns132 0 ns131 0 -0.00481264175409 +Ca133 ns133 0 1e-012 +Ca134 ns134 0 1e-012 +Ra133 ns133 0 5638.39578337 +Ra134 ns134 0 5638.39578337 +Ga133 ns133 0 ns134 0 0.00497765146802 +Ga134 ns134 0 ns133 0 -0.00497765146802 +Ca135 ns135 0 1e-012 +Ca136 ns136 0 1e-012 +Ra135 ns135 0 7990.11670552 +Ra136 ns136 0 7990.11670552 +Ga135 ns135 0 ns136 0 0.00517905842625 +Ga136 ns136 0 ns135 0 -0.00517905842625 +Ca137 ns137 0 1e-012 +Ca138 ns138 0 1e-012 +Ra137 ns137 0 23719.5240812 +Ra138 ns138 0 23719.5240812 +Ga137 ns137 0 ns138 0 0.0052656494058 +Ga138 ns138 0 ns137 0 -0.0052656494058 +Ca139 ns139 0 1e-012 +Ca140 ns140 0 1e-012 +Ra139 ns139 0 7652.32468773 +Ra140 ns140 0 7652.32468773 +Ga139 ns139 0 ns140 0 0.00541092047714 +Ga140 ns140 0 ns139 0 -0.00541092047714 +Ca141 ns141 0 1e-012 +Ca142 ns142 0 1e-012 +Ra141 ns141 0 4436.51193446 +Ra142 ns142 0 4436.51193446 +Ga141 ns141 0 ns142 0 0.00559439789276 +Ga142 ns142 0 ns141 0 -0.00559439789276 +Ca143 ns143 0 1e-012 +Ca144 ns144 0 1e-012 +Ra143 ns143 0 5143.60957566 +Ra144 ns144 0 5143.60957566 +Ga143 ns143 0 ns144 0 0.00577549992818 +Ga144 ns144 0 ns143 0 -0.00577549992818 +Ca145 ns145 0 1e-012 +Ca146 ns146 0 1e-012 +Ra145 ns145 0 6362.86414534 +Ra146 ns146 0 6362.86414534 +Ga145 ns145 0 ns146 0 0.0059387234503 +Ga146 ns146 0 ns145 0 -0.0059387234503 +Ca147 ns147 0 1e-012 +Ca148 ns148 0 1e-012 +Ra147 ns147 0 3112.32079105 +Ra148 ns148 0 3112.32079105 +Ga147 ns147 0 ns148 0 0.00629316475466 +Ga148 ns148 0 ns147 0 -0.00629316475466 +Ca149 ns149 0 1e-012 +Ca150 ns150 0 1e-012 +Ra149 ns149 0 17627.8949771 +Ra150 ns150 0 17627.8949771 +Ga149 ns149 0 ns150 0 0.00636797928682 +Ga150 ns150 0 ns149 0 -0.00636797928682 +Ca151 ns151 0 1e-012 +Ra151 ns151 0 6331587.52368 +Ca152 ns152 0 1e-012 +Ra152 ns152 0 53092.0957602 +Ca153 ns153 0 1e-012 +Ra153 ns153 0 13263.7345565 +Ca154 ns154 0 1e-012 +Ra154 ns154 0 6737.05345859 +Ca155 ns155 0 1e-012 +Ra155 ns155 0 2289.90455735 +Ca156 ns156 0 1e-012 +Ca157 ns157 0 1e-012 +Ra156 ns156 0 18302.104562 +Ra157 ns157 0 18302.104562 +Ga156 ns156 0 ns157 0 0.000617458441383 +Ga157 ns157 0 ns156 0 -0.000617458441383 +Ca158 ns158 0 1e-012 +Ca159 ns159 0 1e-012 +Ra158 ns158 0 3982.32923659 +Ra159 ns159 0 3982.32923659 +Ga158 ns158 0 ns159 0 0.0011382900548 +Ga159 ns159 0 ns158 0 -0.0011382900548 +Ca160 ns160 0 1e-012 +Ca161 ns161 0 1e-012 +Ra160 ns160 0 6190.23212565 +Ra161 ns161 0 6190.23212565 +Ga160 ns160 0 ns161 0 0.001275504789 +Ga161 ns161 0 ns160 0 -0.001275504789 +Ca162 ns162 0 1e-012 +Ca163 ns163 0 1e-012 +Ra162 ns162 0 1028.23945703 +Ra163 ns163 0 1028.23945703 +Ga162 ns162 0 ns163 0 -0.000863059182564 +Ga163 ns163 0 ns162 0 0.000863059182564 +Ca164 ns164 0 1e-012 +Ca165 ns165 0 1e-012 +Ra164 ns164 0 4245.09858935 +Ra165 ns165 0 4245.09858935 +Ga164 ns164 0 ns165 0 0.00137593972572 +Ga165 ns165 0 ns164 0 -0.00137593972572 +Ca166 ns166 0 1e-012 +Ca167 ns167 0 1e-012 +Ra166 ns166 0 11532.8477904 +Ra167 ns167 0 11532.8477904 +Ga166 ns166 0 ns167 0 0.00155320169346 +Ga167 ns167 0 ns166 0 -0.00155320169346 +Ca168 ns168 0 1e-012 +Ca169 ns169 0 1e-012 +Ra168 ns168 0 21758.9645403 +Ra169 ns169 0 21758.9645403 +Ga168 ns168 0 ns169 0 0.00160285125485 +Ga169 ns169 0 ns168 0 -0.00160285125485 +Ca170 ns170 0 1e-012 +Ca171 ns171 0 1e-012 +Ra170 ns170 0 20309.2225097 +Ra171 ns171 0 20309.2225097 +Ga170 ns170 0 ns171 0 0.00172215743413 +Ga171 ns171 0 ns170 0 -0.00172215743413 +Ca172 ns172 0 1e-012 +Ca173 ns173 0 1e-012 +Ra172 ns172 0 30981.8030017 +Ra173 ns173 0 30981.8030017 +Ga172 ns172 0 ns173 0 0.0017373931074 +Ga173 ns173 0 ns172 0 -0.0017373931074 +Ca174 ns174 0 1e-012 +Ca175 ns175 0 1e-012 +Ra174 ns174 0 3317.41037863 +Ra175 ns175 0 3317.41037863 +Ga174 ns174 0 ns175 0 0.0018048307594 +Ga175 ns175 0 ns174 0 -0.0018048307594 +Ca176 ns176 0 1e-012 +Ca177 ns177 0 1e-012 +Ra176 ns176 0 38100.4687103 +Ra177 ns177 0 38100.4687103 +Ga176 ns176 0 ns177 0 0.00184062394811 +Ga177 ns177 0 ns176 0 -0.00184062394811 +Ca178 ns178 0 1e-012 +Ca179 ns179 0 1e-012 +Ra178 ns178 0 3543.48224398 +Ra179 ns179 0 3543.48224398 +Ga178 ns178 0 ns179 0 0.0020080566871 +Ga179 ns179 0 ns178 0 -0.0020080566871 +Ca180 ns180 0 1e-012 +Ca181 ns181 0 1e-012 +Ra180 ns180 0 14318.3672863 +Ra181 ns181 0 14318.3672863 +Ga180 ns180 0 ns181 0 0.00204184225892 +Ga181 ns181 0 ns180 0 -0.00204184225892 +Ca182 ns182 0 1e-012 +Ca183 ns183 0 1e-012 +Ra182 ns182 0 1102.22650745 +Ra183 ns183 0 1102.22650745 +Ga182 ns182 0 ns183 0 -0.00264690653526 +Ga183 ns183 0 ns182 0 0.00264690653526 +Ca184 ns184 0 1e-012 +Ca185 ns185 0 1e-012 +Ra184 ns184 0 3785.94130957 +Ra185 ns185 0 3785.94130957 +Ga184 ns184 0 ns185 0 -0.00281671550743 +Ga185 ns185 0 ns184 0 0.00281671550743 +Ca186 ns186 0 1e-012 +Ca187 ns187 0 1e-012 +Ra186 ns186 0 15212.9526569 +Ra187 ns187 0 15212.9526569 +Ga186 ns186 0 ns187 0 -0.00324031038854 +Ga187 ns187 0 ns186 0 0.00324031038854 +Ca188 ns188 0 1e-012 +Ca189 ns189 0 1e-012 +Ra188 ns188 0 5619.39695443 +Ra189 ns189 0 5619.39695443 +Ga188 ns188 0 ns189 0 0.00324366276672 +Ga189 ns189 0 ns188 0 -0.00324366276672 +Ca190 ns190 0 1e-012 +Ca191 ns191 0 1e-012 +Ra190 ns190 0 25637.890289 +Ra191 ns191 0 25637.890289 +Ga190 ns190 0 ns191 0 0.00355475462299 +Ga191 ns191 0 ns190 0 -0.00355475462299 +Ca192 ns192 0 1e-012 +Ca193 ns193 0 1e-012 +Ra192 ns192 0 16045.1872042 +Ra193 ns193 0 16045.1872042 +Ga192 ns192 0 ns193 0 0.00366226122782 +Ga193 ns193 0 ns192 0 -0.00366226122782 +Ca194 ns194 0 1e-012 +Ca195 ns195 0 1e-012 +Ra194 ns194 0 21687.7693218 +Ra195 ns195 0 21687.7693218 +Ga194 ns194 0 ns195 0 0.00369099997192 +Ga195 ns195 0 ns194 0 -0.00369099997192 +Ca196 ns196 0 1e-012 +Ca197 ns197 0 1e-012 +Ra196 ns196 0 1228.84909818 +Ra197 ns197 0 1228.84909818 +Ga196 ns196 0 ns197 0 0.00386601696559 +Ga197 ns197 0 ns196 0 -0.00386601696559 +Ca198 ns198 0 1e-012 +Ca199 ns199 0 1e-012 +Ra198 ns198 0 18342.1900173 +Ra199 ns199 0 18342.1900173 +Ga198 ns198 0 ns199 0 0.00399940149645 +Ga199 ns199 0 ns198 0 -0.00399940149645 +Ca200 ns200 0 1e-012 +Ca201 ns201 0 1e-012 +Ra200 ns200 0 11903.4910987 +Ra201 ns201 0 11903.4910987 +Ga200 ns200 0 ns201 0 0.00408976646903 +Ga201 ns201 0 ns200 0 -0.00408976646903 +Ca202 ns202 0 1e-012 +Ca203 ns203 0 1e-012 +Ra202 ns202 0 12692.524621 +Ra203 ns203 0 12692.524621 +Ga202 ns202 0 ns203 0 0.00414513961157 +Ga203 ns203 0 ns202 0 -0.00414513961157 +Ca204 ns204 0 1e-012 +Ca205 ns205 0 1e-012 +Ra204 ns204 0 4344.34411088 +Ra205 ns205 0 4344.34411088 +Ga204 ns204 0 ns205 0 -0.00455794741421 +Ga205 ns205 0 ns204 0 0.00455794741421 +Ca206 ns206 0 1e-012 +Ca207 ns207 0 1e-012 +Ra206 ns206 0 2901.81929778 +Ra207 ns207 0 2901.81929778 +Ga206 ns206 0 ns207 0 0.00481264175409 +Ga207 ns207 0 ns206 0 -0.00481264175409 +Ca208 ns208 0 1e-012 +Ca209 ns209 0 1e-012 +Ra208 ns208 0 5638.39578337 +Ra209 ns209 0 5638.39578337 +Ga208 ns208 0 ns209 0 0.00497765146802 +Ga209 ns209 0 ns208 0 -0.00497765146802 +Ca210 ns210 0 1e-012 +Ca211 ns211 0 1e-012 +Ra210 ns210 0 7990.11670552 +Ra211 ns211 0 7990.11670552 +Ga210 ns210 0 ns211 0 0.00517905842625 +Ga211 ns211 0 ns210 0 -0.00517905842625 +Ca212 ns212 0 1e-012 +Ca213 ns213 0 1e-012 +Ra212 ns212 0 23719.5240812 +Ra213 ns213 0 23719.5240812 +Ga212 ns212 0 ns213 0 0.0052656494058 +Ga213 ns213 0 ns212 0 -0.0052656494058 +Ca214 ns214 0 1e-012 +Ca215 ns215 0 1e-012 +Ra214 ns214 0 7652.32468773 +Ra215 ns215 0 7652.32468773 +Ga214 ns214 0 ns215 0 0.00541092047714 +Ga215 ns215 0 ns214 0 -0.00541092047714 +Ca216 ns216 0 1e-012 +Ca217 ns217 0 1e-012 +Ra216 ns216 0 4436.51193446 +Ra217 ns217 0 4436.51193446 +Ga216 ns216 0 ns217 0 0.00559439789276 +Ga217 ns217 0 ns216 0 -0.00559439789276 +Ca218 ns218 0 1e-012 +Ca219 ns219 0 1e-012 +Ra218 ns218 0 5143.60957566 +Ra219 ns219 0 5143.60957566 +Ga218 ns218 0 ns219 0 0.00577549992818 +Ga219 ns219 0 ns218 0 -0.00577549992818 +Ca220 ns220 0 1e-012 +Ca221 ns221 0 1e-012 +Ra220 ns220 0 6362.86414534 +Ra221 ns221 0 6362.86414534 +Ga220 ns220 0 ns221 0 0.0059387234503 +Ga221 ns221 0 ns220 0 -0.0059387234503 +Ca222 ns222 0 1e-012 +Ca223 ns223 0 1e-012 +Ra222 ns222 0 3112.32079105 +Ra223 ns223 0 3112.32079105 +Ga222 ns222 0 ns223 0 0.00629316475466 +Ga223 ns223 0 ns222 0 -0.00629316475466 +Ca224 ns224 0 1e-012 +Ca225 ns225 0 1e-012 +Ra224 ns224 0 17627.8949771 +Ra225 ns225 0 17627.8949771 +Ga224 ns224 0 ns225 0 0.00636797928682 +Ga225 ns225 0 ns224 0 -0.00636797928682 +Ca226 ns226 0 1e-012 +Ra226 ns226 0 6331587.52368 +Ca227 ns227 0 1e-012 +Ra227 ns227 0 53092.0957602 +Ca228 ns228 0 1e-012 +Ra228 ns228 0 13263.7345565 +Ca229 ns229 0 1e-012 +Ra229 ns229 0 6737.05345859 +Ca230 ns230 0 1e-012 +Ra230 ns230 0 2289.90455735 +Ca231 ns231 0 1e-012 +Ca232 ns232 0 1e-012 +Ra231 ns231 0 18302.104562 +Ra232 ns232 0 18302.104562 +Ga231 ns231 0 ns232 0 0.000617458441383 +Ga232 ns232 0 ns231 0 -0.000617458441383 +Ca233 ns233 0 1e-012 +Ca234 ns234 0 1e-012 +Ra233 ns233 0 3982.32923659 +Ra234 ns234 0 3982.32923659 +Ga233 ns233 0 ns234 0 0.0011382900548 +Ga234 ns234 0 ns233 0 -0.0011382900548 +Ca235 ns235 0 1e-012 +Ca236 ns236 0 1e-012 +Ra235 ns235 0 6190.23212565 +Ra236 ns236 0 6190.23212565 +Ga235 ns235 0 ns236 0 0.001275504789 +Ga236 ns236 0 ns235 0 -0.001275504789 +Ca237 ns237 0 1e-012 +Ca238 ns238 0 1e-012 +Ra237 ns237 0 1028.23945703 +Ra238 ns238 0 1028.23945703 +Ga237 ns237 0 ns238 0 -0.000863059182564 +Ga238 ns238 0 ns237 0 0.000863059182564 +Ca239 ns239 0 1e-012 +Ca240 ns240 0 1e-012 +Ra239 ns239 0 4245.09858935 +Ra240 ns240 0 4245.09858935 +Ga239 ns239 0 ns240 0 0.00137593972572 +Ga240 ns240 0 ns239 0 -0.00137593972572 +Ca241 ns241 0 1e-012 +Ca242 ns242 0 1e-012 +Ra241 ns241 0 11532.8477904 +Ra242 ns242 0 11532.8477904 +Ga241 ns241 0 ns242 0 0.00155320169346 +Ga242 ns242 0 ns241 0 -0.00155320169346 +Ca243 ns243 0 1e-012 +Ca244 ns244 0 1e-012 +Ra243 ns243 0 21758.9645403 +Ra244 ns244 0 21758.9645403 +Ga243 ns243 0 ns244 0 0.00160285125485 +Ga244 ns244 0 ns243 0 -0.00160285125485 +Ca245 ns245 0 1e-012 +Ca246 ns246 0 1e-012 +Ra245 ns245 0 20309.2225097 +Ra246 ns246 0 20309.2225097 +Ga245 ns245 0 ns246 0 0.00172215743413 +Ga246 ns246 0 ns245 0 -0.00172215743413 +Ca247 ns247 0 1e-012 +Ca248 ns248 0 1e-012 +Ra247 ns247 0 30981.8030017 +Ra248 ns248 0 30981.8030017 +Ga247 ns247 0 ns248 0 0.0017373931074 +Ga248 ns248 0 ns247 0 -0.0017373931074 +Ca249 ns249 0 1e-012 +Ca250 ns250 0 1e-012 +Ra249 ns249 0 3317.41037863 +Ra250 ns250 0 3317.41037863 +Ga249 ns249 0 ns250 0 0.0018048307594 +Ga250 ns250 0 ns249 0 -0.0018048307594 +Ca251 ns251 0 1e-012 +Ca252 ns252 0 1e-012 +Ra251 ns251 0 38100.4687103 +Ra252 ns252 0 38100.4687103 +Ga251 ns251 0 ns252 0 0.00184062394811 +Ga252 ns252 0 ns251 0 -0.00184062394811 +Ca253 ns253 0 1e-012 +Ca254 ns254 0 1e-012 +Ra253 ns253 0 3543.48224398 +Ra254 ns254 0 3543.48224398 +Ga253 ns253 0 ns254 0 0.0020080566871 +Ga254 ns254 0 ns253 0 -0.0020080566871 +Ca255 ns255 0 1e-012 +Ca256 ns256 0 1e-012 +Ra255 ns255 0 14318.3672863 +Ra256 ns256 0 14318.3672863 +Ga255 ns255 0 ns256 0 0.00204184225892 +Ga256 ns256 0 ns255 0 -0.00204184225892 +Ca257 ns257 0 1e-012 +Ca258 ns258 0 1e-012 +Ra257 ns257 0 1102.22650745 +Ra258 ns258 0 1102.22650745 +Ga257 ns257 0 ns258 0 -0.00264690653526 +Ga258 ns258 0 ns257 0 0.00264690653526 +Ca259 ns259 0 1e-012 +Ca260 ns260 0 1e-012 +Ra259 ns259 0 3785.94130957 +Ra260 ns260 0 3785.94130957 +Ga259 ns259 0 ns260 0 -0.00281671550743 +Ga260 ns260 0 ns259 0 0.00281671550743 +Ca261 ns261 0 1e-012 +Ca262 ns262 0 1e-012 +Ra261 ns261 0 15212.9526569 +Ra262 ns262 0 15212.9526569 +Ga261 ns261 0 ns262 0 -0.00324031038854 +Ga262 ns262 0 ns261 0 0.00324031038854 +Ca263 ns263 0 1e-012 +Ca264 ns264 0 1e-012 +Ra263 ns263 0 5619.39695443 +Ra264 ns264 0 5619.39695443 +Ga263 ns263 0 ns264 0 0.00324366276672 +Ga264 ns264 0 ns263 0 -0.00324366276672 +Ca265 ns265 0 1e-012 +Ca266 ns266 0 1e-012 +Ra265 ns265 0 25637.890289 +Ra266 ns266 0 25637.890289 +Ga265 ns265 0 ns266 0 0.00355475462299 +Ga266 ns266 0 ns265 0 -0.00355475462299 +Ca267 ns267 0 1e-012 +Ca268 ns268 0 1e-012 +Ra267 ns267 0 16045.1872042 +Ra268 ns268 0 16045.1872042 +Ga267 ns267 0 ns268 0 0.00366226122782 +Ga268 ns268 0 ns267 0 -0.00366226122782 +Ca269 ns269 0 1e-012 +Ca270 ns270 0 1e-012 +Ra269 ns269 0 21687.7693218 +Ra270 ns270 0 21687.7693218 +Ga269 ns269 0 ns270 0 0.00369099997192 +Ga270 ns270 0 ns269 0 -0.00369099997192 +Ca271 ns271 0 1e-012 +Ca272 ns272 0 1e-012 +Ra271 ns271 0 1228.84909818 +Ra272 ns272 0 1228.84909818 +Ga271 ns271 0 ns272 0 0.00386601696559 +Ga272 ns272 0 ns271 0 -0.00386601696559 +Ca273 ns273 0 1e-012 +Ca274 ns274 0 1e-012 +Ra273 ns273 0 18342.1900173 +Ra274 ns274 0 18342.1900173 +Ga273 ns273 0 ns274 0 0.00399940149645 +Ga274 ns274 0 ns273 0 -0.00399940149645 +Ca275 ns275 0 1e-012 +Ca276 ns276 0 1e-012 +Ra275 ns275 0 11903.4910987 +Ra276 ns276 0 11903.4910987 +Ga275 ns275 0 ns276 0 0.00408976646903 +Ga276 ns276 0 ns275 0 -0.00408976646903 +Ca277 ns277 0 1e-012 +Ca278 ns278 0 1e-012 +Ra277 ns277 0 12692.524621 +Ra278 ns278 0 12692.524621 +Ga277 ns277 0 ns278 0 0.00414513961157 +Ga278 ns278 0 ns277 0 -0.00414513961157 +Ca279 ns279 0 1e-012 +Ca280 ns280 0 1e-012 +Ra279 ns279 0 4344.34411088 +Ra280 ns280 0 4344.34411088 +Ga279 ns279 0 ns280 0 -0.00455794741421 +Ga280 ns280 0 ns279 0 0.00455794741421 +Ca281 ns281 0 1e-012 +Ca282 ns282 0 1e-012 +Ra281 ns281 0 2901.81929778 +Ra282 ns282 0 2901.81929778 +Ga281 ns281 0 ns282 0 0.00481264175409 +Ga282 ns282 0 ns281 0 -0.00481264175409 +Ca283 ns283 0 1e-012 +Ca284 ns284 0 1e-012 +Ra283 ns283 0 5638.39578337 +Ra284 ns284 0 5638.39578337 +Ga283 ns283 0 ns284 0 0.00497765146802 +Ga284 ns284 0 ns283 0 -0.00497765146802 +Ca285 ns285 0 1e-012 +Ca286 ns286 0 1e-012 +Ra285 ns285 0 7990.11670552 +Ra286 ns286 0 7990.11670552 +Ga285 ns285 0 ns286 0 0.00517905842625 +Ga286 ns286 0 ns285 0 -0.00517905842625 +Ca287 ns287 0 1e-012 +Ca288 ns288 0 1e-012 +Ra287 ns287 0 23719.5240812 +Ra288 ns288 0 23719.5240812 +Ga287 ns287 0 ns288 0 0.0052656494058 +Ga288 ns288 0 ns287 0 -0.0052656494058 +Ca289 ns289 0 1e-012 +Ca290 ns290 0 1e-012 +Ra289 ns289 0 7652.32468773 +Ra290 ns290 0 7652.32468773 +Ga289 ns289 0 ns290 0 0.00541092047714 +Ga290 ns290 0 ns289 0 -0.00541092047714 +Ca291 ns291 0 1e-012 +Ca292 ns292 0 1e-012 +Ra291 ns291 0 4436.51193446 +Ra292 ns292 0 4436.51193446 +Ga291 ns291 0 ns292 0 0.00559439789276 +Ga292 ns292 0 ns291 0 -0.00559439789276 +Ca293 ns293 0 1e-012 +Ca294 ns294 0 1e-012 +Ra293 ns293 0 5143.60957566 +Ra294 ns294 0 5143.60957566 +Ga293 ns293 0 ns294 0 0.00577549992818 +Ga294 ns294 0 ns293 0 -0.00577549992818 +Ca295 ns295 0 1e-012 +Ca296 ns296 0 1e-012 +Ra295 ns295 0 6362.86414534 +Ra296 ns296 0 6362.86414534 +Ga295 ns295 0 ns296 0 0.0059387234503 +Ga296 ns296 0 ns295 0 -0.0059387234503 +Ca297 ns297 0 1e-012 +Ca298 ns298 0 1e-012 +Ra297 ns297 0 3112.32079105 +Ra298 ns298 0 3112.32079105 +Ga297 ns297 0 ns298 0 0.00629316475466 +Ga298 ns298 0 ns297 0 -0.00629316475466 +Ca299 ns299 0 1e-012 +Ca300 ns300 0 1e-012 +Ra299 ns299 0 17627.8949771 +Ra300 ns300 0 17627.8949771 +Ga299 ns299 0 ns300 0 0.00636797928682 +Ga300 ns300 0 ns299 0 -0.00636797928682 +Ca301 ns301 0 1e-012 +Ra301 ns301 0 6331587.52368 +Ca302 ns302 0 1e-012 +Ra302 ns302 0 53092.0957602 +Ca303 ns303 0 1e-012 +Ra303 ns303 0 13263.7345565 +Ca304 ns304 0 1e-012 +Ra304 ns304 0 6737.05345859 +Ca305 ns305 0 1e-012 +Ra305 ns305 0 2289.90455735 +Ca306 ns306 0 1e-012 +Ca307 ns307 0 1e-012 +Ra306 ns306 0 18302.104562 +Ra307 ns307 0 18302.104562 +Ga306 ns306 0 ns307 0 0.000617458441383 +Ga307 ns307 0 ns306 0 -0.000617458441383 +Ca308 ns308 0 1e-012 +Ca309 ns309 0 1e-012 +Ra308 ns308 0 3982.32923659 +Ra309 ns309 0 3982.32923659 +Ga308 ns308 0 ns309 0 0.0011382900548 +Ga309 ns309 0 ns308 0 -0.0011382900548 +Ca310 ns310 0 1e-012 +Ca311 ns311 0 1e-012 +Ra310 ns310 0 6190.23212565 +Ra311 ns311 0 6190.23212565 +Ga310 ns310 0 ns311 0 0.001275504789 +Ga311 ns311 0 ns310 0 -0.001275504789 +Ca312 ns312 0 1e-012 +Ca313 ns313 0 1e-012 +Ra312 ns312 0 1028.23945703 +Ra313 ns313 0 1028.23945703 +Ga312 ns312 0 ns313 0 -0.000863059182564 +Ga313 ns313 0 ns312 0 0.000863059182564 +Ca314 ns314 0 1e-012 +Ca315 ns315 0 1e-012 +Ra314 ns314 0 4245.09858935 +Ra315 ns315 0 4245.09858935 +Ga314 ns314 0 ns315 0 0.00137593972572 +Ga315 ns315 0 ns314 0 -0.00137593972572 +Ca316 ns316 0 1e-012 +Ca317 ns317 0 1e-012 +Ra316 ns316 0 11532.8477904 +Ra317 ns317 0 11532.8477904 +Ga316 ns316 0 ns317 0 0.00155320169346 +Ga317 ns317 0 ns316 0 -0.00155320169346 +Ca318 ns318 0 1e-012 +Ca319 ns319 0 1e-012 +Ra318 ns318 0 21758.9645403 +Ra319 ns319 0 21758.9645403 +Ga318 ns318 0 ns319 0 0.00160285125485 +Ga319 ns319 0 ns318 0 -0.00160285125485 +Ca320 ns320 0 1e-012 +Ca321 ns321 0 1e-012 +Ra320 ns320 0 20309.2225097 +Ra321 ns321 0 20309.2225097 +Ga320 ns320 0 ns321 0 0.00172215743413 +Ga321 ns321 0 ns320 0 -0.00172215743413 +Ca322 ns322 0 1e-012 +Ca323 ns323 0 1e-012 +Ra322 ns322 0 30981.8030017 +Ra323 ns323 0 30981.8030017 +Ga322 ns322 0 ns323 0 0.0017373931074 +Ga323 ns323 0 ns322 0 -0.0017373931074 +Ca324 ns324 0 1e-012 +Ca325 ns325 0 1e-012 +Ra324 ns324 0 3317.41037863 +Ra325 ns325 0 3317.41037863 +Ga324 ns324 0 ns325 0 0.0018048307594 +Ga325 ns325 0 ns324 0 -0.0018048307594 +Ca326 ns326 0 1e-012 +Ca327 ns327 0 1e-012 +Ra326 ns326 0 38100.4687103 +Ra327 ns327 0 38100.4687103 +Ga326 ns326 0 ns327 0 0.00184062394811 +Ga327 ns327 0 ns326 0 -0.00184062394811 +Ca328 ns328 0 1e-012 +Ca329 ns329 0 1e-012 +Ra328 ns328 0 3543.48224398 +Ra329 ns329 0 3543.48224398 +Ga328 ns328 0 ns329 0 0.0020080566871 +Ga329 ns329 0 ns328 0 -0.0020080566871 +Ca330 ns330 0 1e-012 +Ca331 ns331 0 1e-012 +Ra330 ns330 0 14318.3672863 +Ra331 ns331 0 14318.3672863 +Ga330 ns330 0 ns331 0 0.00204184225892 +Ga331 ns331 0 ns330 0 -0.00204184225892 +Ca332 ns332 0 1e-012 +Ca333 ns333 0 1e-012 +Ra332 ns332 0 1102.22650745 +Ra333 ns333 0 1102.22650745 +Ga332 ns332 0 ns333 0 -0.00264690653526 +Ga333 ns333 0 ns332 0 0.00264690653526 +Ca334 ns334 0 1e-012 +Ca335 ns335 0 1e-012 +Ra334 ns334 0 3785.94130957 +Ra335 ns335 0 3785.94130957 +Ga334 ns334 0 ns335 0 -0.00281671550743 +Ga335 ns335 0 ns334 0 0.00281671550743 +Ca336 ns336 0 1e-012 +Ca337 ns337 0 1e-012 +Ra336 ns336 0 15212.9526569 +Ra337 ns337 0 15212.9526569 +Ga336 ns336 0 ns337 0 -0.00324031038854 +Ga337 ns337 0 ns336 0 0.00324031038854 +Ca338 ns338 0 1e-012 +Ca339 ns339 0 1e-012 +Ra338 ns338 0 5619.39695443 +Ra339 ns339 0 5619.39695443 +Ga338 ns338 0 ns339 0 0.00324366276672 +Ga339 ns339 0 ns338 0 -0.00324366276672 +Ca340 ns340 0 1e-012 +Ca341 ns341 0 1e-012 +Ra340 ns340 0 25637.890289 +Ra341 ns341 0 25637.890289 +Ga340 ns340 0 ns341 0 0.00355475462299 +Ga341 ns341 0 ns340 0 -0.00355475462299 +Ca342 ns342 0 1e-012 +Ca343 ns343 0 1e-012 +Ra342 ns342 0 16045.1872042 +Ra343 ns343 0 16045.1872042 +Ga342 ns342 0 ns343 0 0.00366226122782 +Ga343 ns343 0 ns342 0 -0.00366226122782 +Ca344 ns344 0 1e-012 +Ca345 ns345 0 1e-012 +Ra344 ns344 0 21687.7693218 +Ra345 ns345 0 21687.7693218 +Ga344 ns344 0 ns345 0 0.00369099997192 +Ga345 ns345 0 ns344 0 -0.00369099997192 +Ca346 ns346 0 1e-012 +Ca347 ns347 0 1e-012 +Ra346 ns346 0 1228.84909818 +Ra347 ns347 0 1228.84909818 +Ga346 ns346 0 ns347 0 0.00386601696559 +Ga347 ns347 0 ns346 0 -0.00386601696559 +Ca348 ns348 0 1e-012 +Ca349 ns349 0 1e-012 +Ra348 ns348 0 18342.1900173 +Ra349 ns349 0 18342.1900173 +Ga348 ns348 0 ns349 0 0.00399940149645 +Ga349 ns349 0 ns348 0 -0.00399940149645 +Ca350 ns350 0 1e-012 +Ca351 ns351 0 1e-012 +Ra350 ns350 0 11903.4910987 +Ra351 ns351 0 11903.4910987 +Ga350 ns350 0 ns351 0 0.00408976646903 +Ga351 ns351 0 ns350 0 -0.00408976646903 +Ca352 ns352 0 1e-012 +Ca353 ns353 0 1e-012 +Ra352 ns352 0 12692.524621 +Ra353 ns353 0 12692.524621 +Ga352 ns352 0 ns353 0 0.00414513961157 +Ga353 ns353 0 ns352 0 -0.00414513961157 +Ca354 ns354 0 1e-012 +Ca355 ns355 0 1e-012 +Ra354 ns354 0 4344.34411088 +Ra355 ns355 0 4344.34411088 +Ga354 ns354 0 ns355 0 -0.00455794741421 +Ga355 ns355 0 ns354 0 0.00455794741421 +Ca356 ns356 0 1e-012 +Ca357 ns357 0 1e-012 +Ra356 ns356 0 2901.81929778 +Ra357 ns357 0 2901.81929778 +Ga356 ns356 0 ns357 0 0.00481264175409 +Ga357 ns357 0 ns356 0 -0.00481264175409 +Ca358 ns358 0 1e-012 +Ca359 ns359 0 1e-012 +Ra358 ns358 0 5638.39578337 +Ra359 ns359 0 5638.39578337 +Ga358 ns358 0 ns359 0 0.00497765146802 +Ga359 ns359 0 ns358 0 -0.00497765146802 +Ca360 ns360 0 1e-012 +Ca361 ns361 0 1e-012 +Ra360 ns360 0 7990.11670552 +Ra361 ns361 0 7990.11670552 +Ga360 ns360 0 ns361 0 0.00517905842625 +Ga361 ns361 0 ns360 0 -0.00517905842625 +Ca362 ns362 0 1e-012 +Ca363 ns363 0 1e-012 +Ra362 ns362 0 23719.5240812 +Ra363 ns363 0 23719.5240812 +Ga362 ns362 0 ns363 0 0.0052656494058 +Ga363 ns363 0 ns362 0 -0.0052656494058 +Ca364 ns364 0 1e-012 +Ca365 ns365 0 1e-012 +Ra364 ns364 0 7652.32468773 +Ra365 ns365 0 7652.32468773 +Ga364 ns364 0 ns365 0 0.00541092047714 +Ga365 ns365 0 ns364 0 -0.00541092047714 +Ca366 ns366 0 1e-012 +Ca367 ns367 0 1e-012 +Ra366 ns366 0 4436.51193446 +Ra367 ns367 0 4436.51193446 +Ga366 ns366 0 ns367 0 0.00559439789276 +Ga367 ns367 0 ns366 0 -0.00559439789276 +Ca368 ns368 0 1e-012 +Ca369 ns369 0 1e-012 +Ra368 ns368 0 5143.60957566 +Ra369 ns369 0 5143.60957566 +Ga368 ns368 0 ns369 0 0.00577549992818 +Ga369 ns369 0 ns368 0 -0.00577549992818 +Ca370 ns370 0 1e-012 +Ca371 ns371 0 1e-012 +Ra370 ns370 0 6362.86414534 +Ra371 ns371 0 6362.86414534 +Ga370 ns370 0 ns371 0 0.0059387234503 +Ga371 ns371 0 ns370 0 -0.0059387234503 +Ca372 ns372 0 1e-012 +Ca373 ns373 0 1e-012 +Ra372 ns372 0 3112.32079105 +Ra373 ns373 0 3112.32079105 +Ga372 ns372 0 ns373 0 0.00629316475466 +Ga373 ns373 0 ns372 0 -0.00629316475466 +Ca374 ns374 0 1e-012 +Ca375 ns375 0 1e-012 +Ra374 ns374 0 17627.8949771 +Ra375 ns375 0 17627.8949771 +Ga374 ns374 0 ns375 0 0.00636797928682 +Ga375 ns375 0 ns374 0 -0.00636797928682 +Ca376 ns376 0 1e-012 +Ra376 ns376 0 6331587.52368 +Ca377 ns377 0 1e-012 +Ra377 ns377 0 53092.0957602 +Ca378 ns378 0 1e-012 +Ra378 ns378 0 13263.7345565 +Ca379 ns379 0 1e-012 +Ra379 ns379 0 6737.05345859 +Ca380 ns380 0 1e-012 +Ra380 ns380 0 2289.90455735 +Ca381 ns381 0 1e-012 +Ca382 ns382 0 1e-012 +Ra381 ns381 0 18302.104562 +Ra382 ns382 0 18302.104562 +Ga381 ns381 0 ns382 0 0.000617458441383 +Ga382 ns382 0 ns381 0 -0.000617458441383 +Ca383 ns383 0 1e-012 +Ca384 ns384 0 1e-012 +Ra383 ns383 0 3982.32923659 +Ra384 ns384 0 3982.32923659 +Ga383 ns383 0 ns384 0 0.0011382900548 +Ga384 ns384 0 ns383 0 -0.0011382900548 +Ca385 ns385 0 1e-012 +Ca386 ns386 0 1e-012 +Ra385 ns385 0 6190.23212565 +Ra386 ns386 0 6190.23212565 +Ga385 ns385 0 ns386 0 0.001275504789 +Ga386 ns386 0 ns385 0 -0.001275504789 +Ca387 ns387 0 1e-012 +Ca388 ns388 0 1e-012 +Ra387 ns387 0 1028.23945703 +Ra388 ns388 0 1028.23945703 +Ga387 ns387 0 ns388 0 -0.000863059182564 +Ga388 ns388 0 ns387 0 0.000863059182564 +Ca389 ns389 0 1e-012 +Ca390 ns390 0 1e-012 +Ra389 ns389 0 4245.09858935 +Ra390 ns390 0 4245.09858935 +Ga389 ns389 0 ns390 0 0.00137593972572 +Ga390 ns390 0 ns389 0 -0.00137593972572 +Ca391 ns391 0 1e-012 +Ca392 ns392 0 1e-012 +Ra391 ns391 0 11532.8477904 +Ra392 ns392 0 11532.8477904 +Ga391 ns391 0 ns392 0 0.00155320169346 +Ga392 ns392 0 ns391 0 -0.00155320169346 +Ca393 ns393 0 1e-012 +Ca394 ns394 0 1e-012 +Ra393 ns393 0 21758.9645403 +Ra394 ns394 0 21758.9645403 +Ga393 ns393 0 ns394 0 0.00160285125485 +Ga394 ns394 0 ns393 0 -0.00160285125485 +Ca395 ns395 0 1e-012 +Ca396 ns396 0 1e-012 +Ra395 ns395 0 20309.2225097 +Ra396 ns396 0 20309.2225097 +Ga395 ns395 0 ns396 0 0.00172215743413 +Ga396 ns396 0 ns395 0 -0.00172215743413 +Ca397 ns397 0 1e-012 +Ca398 ns398 0 1e-012 +Ra397 ns397 0 30981.8030017 +Ra398 ns398 0 30981.8030017 +Ga397 ns397 0 ns398 0 0.0017373931074 +Ga398 ns398 0 ns397 0 -0.0017373931074 +Ca399 ns399 0 1e-012 +Ca400 ns400 0 1e-012 +Ra399 ns399 0 3317.41037863 +Ra400 ns400 0 3317.41037863 +Ga399 ns399 0 ns400 0 0.0018048307594 +Ga400 ns400 0 ns399 0 -0.0018048307594 +Ca401 ns401 0 1e-012 +Ca402 ns402 0 1e-012 +Ra401 ns401 0 38100.4687103 +Ra402 ns402 0 38100.4687103 +Ga401 ns401 0 ns402 0 0.00184062394811 +Ga402 ns402 0 ns401 0 -0.00184062394811 +Ca403 ns403 0 1e-012 +Ca404 ns404 0 1e-012 +Ra403 ns403 0 3543.48224398 +Ra404 ns404 0 3543.48224398 +Ga403 ns403 0 ns404 0 0.0020080566871 +Ga404 ns404 0 ns403 0 -0.0020080566871 +Ca405 ns405 0 1e-012 +Ca406 ns406 0 1e-012 +Ra405 ns405 0 14318.3672863 +Ra406 ns406 0 14318.3672863 +Ga405 ns405 0 ns406 0 0.00204184225892 +Ga406 ns406 0 ns405 0 -0.00204184225892 +Ca407 ns407 0 1e-012 +Ca408 ns408 0 1e-012 +Ra407 ns407 0 1102.22650745 +Ra408 ns408 0 1102.22650745 +Ga407 ns407 0 ns408 0 -0.00264690653526 +Ga408 ns408 0 ns407 0 0.00264690653526 +Ca409 ns409 0 1e-012 +Ca410 ns410 0 1e-012 +Ra409 ns409 0 3785.94130957 +Ra410 ns410 0 3785.94130957 +Ga409 ns409 0 ns410 0 -0.00281671550743 +Ga410 ns410 0 ns409 0 0.00281671550743 +Ca411 ns411 0 1e-012 +Ca412 ns412 0 1e-012 +Ra411 ns411 0 15212.9526569 +Ra412 ns412 0 15212.9526569 +Ga411 ns411 0 ns412 0 -0.00324031038854 +Ga412 ns412 0 ns411 0 0.00324031038854 +Ca413 ns413 0 1e-012 +Ca414 ns414 0 1e-012 +Ra413 ns413 0 5619.39695443 +Ra414 ns414 0 5619.39695443 +Ga413 ns413 0 ns414 0 0.00324366276672 +Ga414 ns414 0 ns413 0 -0.00324366276672 +Ca415 ns415 0 1e-012 +Ca416 ns416 0 1e-012 +Ra415 ns415 0 25637.890289 +Ra416 ns416 0 25637.890289 +Ga415 ns415 0 ns416 0 0.00355475462299 +Ga416 ns416 0 ns415 0 -0.00355475462299 +Ca417 ns417 0 1e-012 +Ca418 ns418 0 1e-012 +Ra417 ns417 0 16045.1872042 +Ra418 ns418 0 16045.1872042 +Ga417 ns417 0 ns418 0 0.00366226122782 +Ga418 ns418 0 ns417 0 -0.00366226122782 +Ca419 ns419 0 1e-012 +Ca420 ns420 0 1e-012 +Ra419 ns419 0 21687.7693218 +Ra420 ns420 0 21687.7693218 +Ga419 ns419 0 ns420 0 0.00369099997192 +Ga420 ns420 0 ns419 0 -0.00369099997192 +Ca421 ns421 0 1e-012 +Ca422 ns422 0 1e-012 +Ra421 ns421 0 1228.84909818 +Ra422 ns422 0 1228.84909818 +Ga421 ns421 0 ns422 0 0.00386601696559 +Ga422 ns422 0 ns421 0 -0.00386601696559 +Ca423 ns423 0 1e-012 +Ca424 ns424 0 1e-012 +Ra423 ns423 0 18342.1900173 +Ra424 ns424 0 18342.1900173 +Ga423 ns423 0 ns424 0 0.00399940149645 +Ga424 ns424 0 ns423 0 -0.00399940149645 +Ca425 ns425 0 1e-012 +Ca426 ns426 0 1e-012 +Ra425 ns425 0 11903.4910987 +Ra426 ns426 0 11903.4910987 +Ga425 ns425 0 ns426 0 0.00408976646903 +Ga426 ns426 0 ns425 0 -0.00408976646903 +Ca427 ns427 0 1e-012 +Ca428 ns428 0 1e-012 +Ra427 ns427 0 12692.524621 +Ra428 ns428 0 12692.524621 +Ga427 ns427 0 ns428 0 0.00414513961157 +Ga428 ns428 0 ns427 0 -0.00414513961157 +Ca429 ns429 0 1e-012 +Ca430 ns430 0 1e-012 +Ra429 ns429 0 4344.34411088 +Ra430 ns430 0 4344.34411088 +Ga429 ns429 0 ns430 0 -0.00455794741421 +Ga430 ns430 0 ns429 0 0.00455794741421 +Ca431 ns431 0 1e-012 +Ca432 ns432 0 1e-012 +Ra431 ns431 0 2901.81929778 +Ra432 ns432 0 2901.81929778 +Ga431 ns431 0 ns432 0 0.00481264175409 +Ga432 ns432 0 ns431 0 -0.00481264175409 +Ca433 ns433 0 1e-012 +Ca434 ns434 0 1e-012 +Ra433 ns433 0 5638.39578337 +Ra434 ns434 0 5638.39578337 +Ga433 ns433 0 ns434 0 0.00497765146802 +Ga434 ns434 0 ns433 0 -0.00497765146802 +Ca435 ns435 0 1e-012 +Ca436 ns436 0 1e-012 +Ra435 ns435 0 7990.11670552 +Ra436 ns436 0 7990.11670552 +Ga435 ns435 0 ns436 0 0.00517905842625 +Ga436 ns436 0 ns435 0 -0.00517905842625 +Ca437 ns437 0 1e-012 +Ca438 ns438 0 1e-012 +Ra437 ns437 0 23719.5240812 +Ra438 ns438 0 23719.5240812 +Ga437 ns437 0 ns438 0 0.0052656494058 +Ga438 ns438 0 ns437 0 -0.0052656494058 +Ca439 ns439 0 1e-012 +Ca440 ns440 0 1e-012 +Ra439 ns439 0 7652.32468773 +Ra440 ns440 0 7652.32468773 +Ga439 ns439 0 ns440 0 0.00541092047714 +Ga440 ns440 0 ns439 0 -0.00541092047714 +Ca441 ns441 0 1e-012 +Ca442 ns442 0 1e-012 +Ra441 ns441 0 4436.51193446 +Ra442 ns442 0 4436.51193446 +Ga441 ns441 0 ns442 0 0.00559439789276 +Ga442 ns442 0 ns441 0 -0.00559439789276 +Ca443 ns443 0 1e-012 +Ca444 ns444 0 1e-012 +Ra443 ns443 0 5143.60957566 +Ra444 ns444 0 5143.60957566 +Ga443 ns443 0 ns444 0 0.00577549992818 +Ga444 ns444 0 ns443 0 -0.00577549992818 +Ca445 ns445 0 1e-012 +Ca446 ns446 0 1e-012 +Ra445 ns445 0 6362.86414534 +Ra446 ns446 0 6362.86414534 +Ga445 ns445 0 ns446 0 0.0059387234503 +Ga446 ns446 0 ns445 0 -0.0059387234503 +Ca447 ns447 0 1e-012 +Ca448 ns448 0 1e-012 +Ra447 ns447 0 3112.32079105 +Ra448 ns448 0 3112.32079105 +Ga447 ns447 0 ns448 0 0.00629316475466 +Ga448 ns448 0 ns447 0 -0.00629316475466 +Ca449 ns449 0 1e-012 +Ca450 ns450 0 1e-012 +Ra449 ns449 0 17627.8949771 +Ra450 ns450 0 17627.8949771 +Ga449 ns449 0 ns450 0 0.00636797928682 +Ga450 ns450 0 ns449 0 -0.00636797928682 + +Gb1_1 ns1 0 ni1 0 1.57938273183e-007 +Gb2_1 ns2 0 ni1 0 1.88351954407e-005 +Gb3_1 ns3 0 ni1 0 7.5393547401e-005 +Gb4_1 ns4 0 ni1 0 0.000148432843252 +Gb5_1 ns5 0 ni1 0 0.000436699423472 +Gb6_1 ns6 0 ni1 0 0.000622293371522 +Gb8_1 ns8 0 ni1 0 0.00119368533126 +Gb10_1 ns10 0 ni1 0 0.00129596471397 +Gb12_1 ns12 0 ni1 0 0.00173844201787 +Gb14_1 ns14 0 ni1 0 0.00141626942917 +Gb16_1 ns16 0 ni1 0 0.00155804229154 +Gb18_1 ns18 0 ni1 0 0.00160416899667 +Gb20_1 ns20 0 ni1 0 0.00172356523281 +Gb22_1 ns22 0 ni1 0 0.00173799274455 +Gb24_1 ns24 0 ni1 0 0.00185517677638 +Gb26_1 ns26 0 ni1 0 0.00184099820887 +Gb28_1 ns28 0 ni1 0 0.00204771767334 +Gb30_1 ns30 0 ni1 0 0.00204423111956 +Gb32_1 ns32 0 ni1 0 0.00295787739292 +Gb34_1 ns34 0 ni1 0 0.00284148455236 +Gb36_1 ns36 0 ni1 0 0.00324164386809 +Gb38_1 ns38 0 ni1 0 0.00325342580249 +Gb40_1 ns40 0 ni1 0 0.00355518260529 +Gb42_1 ns42 0 ni1 0 0.00366332185097 +Gb44_1 ns44 0 ni1 0 0.00369157597683 +Gb46_1 ns46 0 ni1 0 0.00403730977574 +Gb48_1 ns48 0 ni1 0 0.00400014469118 +Gb50_1 ns50 0 ni1 0 0.00409149211931 +Gb52_1 ns52 0 ni1 0 0.0041466371046 +Gb54_1 ns54 0 ni1 0 0.00456957212759 +Gb56_1 ns56 0 ni1 0 0.00483731780947 +Gb58_1 ns58 0 ni1 0 0.00498397070149 +Gb60_1 ns60 0 ni1 0 0.00518208285211 +Gb62_1 ns62 0 ni1 0 0.00526598695425 +Gb64_1 ns64 0 ni1 0 0.00541407651403 +Gb66_1 ns66 0 ni1 0 0.00560347951305 +Gb68_1 ns68 0 ni1 0 0.00578204439733 +Gb70_1 ns70 0 ni1 0 0.0059428825717 +Gb72_1 ns72 0 ni1 0 0.00630956922416 +Gb74_1 ns74 0 ni1 0 0.00636848464284 +Gb76_2 ns76 0 ni2 0 1.57938273183e-007 +Gb77_2 ns77 0 ni2 0 1.88351954407e-005 +Gb78_2 ns78 0 ni2 0 7.5393547401e-005 +Gb79_2 ns79 0 ni2 0 0.000148432843252 +Gb80_2 ns80 0 ni2 0 0.000436699423472 +Gb81_2 ns81 0 ni2 0 0.000622293371522 +Gb83_2 ns83 0 ni2 0 0.00119368533126 +Gb85_2 ns85 0 ni2 0 0.00129596471397 +Gb87_2 ns87 0 ni2 0 0.00173844201787 +Gb89_2 ns89 0 ni2 0 0.00141626942917 +Gb91_2 ns91 0 ni2 0 0.00155804229154 +Gb93_2 ns93 0 ni2 0 0.00160416899667 +Gb95_2 ns95 0 ni2 0 0.00172356523281 +Gb97_2 ns97 0 ni2 0 0.00173799274455 +Gb99_2 ns99 0 ni2 0 0.00185517677638 +Gb101_2 ns101 0 ni2 0 0.00184099820887 +Gb103_2 ns103 0 ni2 0 0.00204771767334 +Gb105_2 ns105 0 ni2 0 0.00204423111956 +Gb107_2 ns107 0 ni2 0 0.00295787739292 +Gb109_2 ns109 0 ni2 0 0.00284148455236 +Gb111_2 ns111 0 ni2 0 0.00324164386809 +Gb113_2 ns113 0 ni2 0 0.00325342580249 +Gb115_2 ns115 0 ni2 0 0.00355518260529 +Gb117_2 ns117 0 ni2 0 0.00366332185097 +Gb119_2 ns119 0 ni2 0 0.00369157597683 +Gb121_2 ns121 0 ni2 0 0.00403730977574 +Gb123_2 ns123 0 ni2 0 0.00400014469118 +Gb125_2 ns125 0 ni2 0 0.00409149211931 +Gb127_2 ns127 0 ni2 0 0.0041466371046 +Gb129_2 ns129 0 ni2 0 0.00456957212759 +Gb131_2 ns131 0 ni2 0 0.00483731780947 +Gb133_2 ns133 0 ni2 0 0.00498397070149 +Gb135_2 ns135 0 ni2 0 0.00518208285211 +Gb137_2 ns137 0 ni2 0 0.00526598695425 +Gb139_2 ns139 0 ni2 0 0.00541407651403 +Gb141_2 ns141 0 ni2 0 0.00560347951305 +Gb143_2 ns143 0 ni2 0 0.00578204439733 +Gb145_2 ns145 0 ni2 0 0.0059428825717 +Gb147_2 ns147 0 ni2 0 0.00630956922416 +Gb149_2 ns149 0 ni2 0 0.00636848464284 +Gb151_3 ns151 0 ni3 0 1.57938273183e-007 +Gb152_3 ns152 0 ni3 0 1.88351954407e-005 +Gb153_3 ns153 0 ni3 0 7.5393547401e-005 +Gb154_3 ns154 0 ni3 0 0.000148432843252 +Gb155_3 ns155 0 ni3 0 0.000436699423472 +Gb156_3 ns156 0 ni3 0 0.000622293371522 +Gb158_3 ns158 0 ni3 0 0.00119368533126 +Gb160_3 ns160 0 ni3 0 0.00129596471397 +Gb162_3 ns162 0 ni3 0 0.00173844201787 +Gb164_3 ns164 0 ni3 0 0.00141626942917 +Gb166_3 ns166 0 ni3 0 0.00155804229154 +Gb168_3 ns168 0 ni3 0 0.00160416899667 +Gb170_3 ns170 0 ni3 0 0.00172356523281 +Gb172_3 ns172 0 ni3 0 0.00173799274455 +Gb174_3 ns174 0 ni3 0 0.00185517677638 +Gb176_3 ns176 0 ni3 0 0.00184099820887 +Gb178_3 ns178 0 ni3 0 0.00204771767334 +Gb180_3 ns180 0 ni3 0 0.00204423111956 +Gb182_3 ns182 0 ni3 0 0.00295787739292 +Gb184_3 ns184 0 ni3 0 0.00284148455236 +Gb186_3 ns186 0 ni3 0 0.00324164386809 +Gb188_3 ns188 0 ni3 0 0.00325342580249 +Gb190_3 ns190 0 ni3 0 0.00355518260529 +Gb192_3 ns192 0 ni3 0 0.00366332185097 +Gb194_3 ns194 0 ni3 0 0.00369157597683 +Gb196_3 ns196 0 ni3 0 0.00403730977574 +Gb198_3 ns198 0 ni3 0 0.00400014469118 +Gb200_3 ns200 0 ni3 0 0.00409149211931 +Gb202_3 ns202 0 ni3 0 0.0041466371046 +Gb204_3 ns204 0 ni3 0 0.00456957212759 +Gb206_3 ns206 0 ni3 0 0.00483731780947 +Gb208_3 ns208 0 ni3 0 0.00498397070149 +Gb210_3 ns210 0 ni3 0 0.00518208285211 +Gb212_3 ns212 0 ni3 0 0.00526598695425 +Gb214_3 ns214 0 ni3 0 0.00541407651403 +Gb216_3 ns216 0 ni3 0 0.00560347951305 +Gb218_3 ns218 0 ni3 0 0.00578204439733 +Gb220_3 ns220 0 ni3 0 0.0059428825717 +Gb222_3 ns222 0 ni3 0 0.00630956922416 +Gb224_3 ns224 0 ni3 0 0.00636848464284 +Gb226_4 ns226 0 ni4 0 1.57938273183e-007 +Gb227_4 ns227 0 ni4 0 1.88351954407e-005 +Gb228_4 ns228 0 ni4 0 7.5393547401e-005 +Gb229_4 ns229 0 ni4 0 0.000148432843252 +Gb230_4 ns230 0 ni4 0 0.000436699423472 +Gb231_4 ns231 0 ni4 0 0.000622293371522 +Gb233_4 ns233 0 ni4 0 0.00119368533126 +Gb235_4 ns235 0 ni4 0 0.00129596471397 +Gb237_4 ns237 0 ni4 0 0.00173844201787 +Gb239_4 ns239 0 ni4 0 0.00141626942917 +Gb241_4 ns241 0 ni4 0 0.00155804229154 +Gb243_4 ns243 0 ni4 0 0.00160416899667 +Gb245_4 ns245 0 ni4 0 0.00172356523281 +Gb247_4 ns247 0 ni4 0 0.00173799274455 +Gb249_4 ns249 0 ni4 0 0.00185517677638 +Gb251_4 ns251 0 ni4 0 0.00184099820887 +Gb253_4 ns253 0 ni4 0 0.00204771767334 +Gb255_4 ns255 0 ni4 0 0.00204423111956 +Gb257_4 ns257 0 ni4 0 0.00295787739292 +Gb259_4 ns259 0 ni4 0 0.00284148455236 +Gb261_4 ns261 0 ni4 0 0.00324164386809 +Gb263_4 ns263 0 ni4 0 0.00325342580249 +Gb265_4 ns265 0 ni4 0 0.00355518260529 +Gb267_4 ns267 0 ni4 0 0.00366332185097 +Gb269_4 ns269 0 ni4 0 0.00369157597683 +Gb271_4 ns271 0 ni4 0 0.00403730977574 +Gb273_4 ns273 0 ni4 0 0.00400014469118 +Gb275_4 ns275 0 ni4 0 0.00409149211931 +Gb277_4 ns277 0 ni4 0 0.0041466371046 +Gb279_4 ns279 0 ni4 0 0.00456957212759 +Gb281_4 ns281 0 ni4 0 0.00483731780947 +Gb283_4 ns283 0 ni4 0 0.00498397070149 +Gb285_4 ns285 0 ni4 0 0.00518208285211 +Gb287_4 ns287 0 ni4 0 0.00526598695425 +Gb289_4 ns289 0 ni4 0 0.00541407651403 +Gb291_4 ns291 0 ni4 0 0.00560347951305 +Gb293_4 ns293 0 ni4 0 0.00578204439733 +Gb295_4 ns295 0 ni4 0 0.0059428825717 +Gb297_4 ns297 0 ni4 0 0.00630956922416 +Gb299_4 ns299 0 ni4 0 0.00636848464284 +Gb301_5 ns301 0 ni5 0 1.57938273183e-007 +Gb302_5 ns302 0 ni5 0 1.88351954407e-005 +Gb303_5 ns303 0 ni5 0 7.5393547401e-005 +Gb304_5 ns304 0 ni5 0 0.000148432843252 +Gb305_5 ns305 0 ni5 0 0.000436699423472 +Gb306_5 ns306 0 ni5 0 0.000622293371522 +Gb308_5 ns308 0 ni5 0 0.00119368533126 +Gb310_5 ns310 0 ni5 0 0.00129596471397 +Gb312_5 ns312 0 ni5 0 0.00173844201787 +Gb314_5 ns314 0 ni5 0 0.00141626942917 +Gb316_5 ns316 0 ni5 0 0.00155804229154 +Gb318_5 ns318 0 ni5 0 0.00160416899667 +Gb320_5 ns320 0 ni5 0 0.00172356523281 +Gb322_5 ns322 0 ni5 0 0.00173799274455 +Gb324_5 ns324 0 ni5 0 0.00185517677638 +Gb326_5 ns326 0 ni5 0 0.00184099820887 +Gb328_5 ns328 0 ni5 0 0.00204771767334 +Gb330_5 ns330 0 ni5 0 0.00204423111956 +Gb332_5 ns332 0 ni5 0 0.00295787739292 +Gb334_5 ns334 0 ni5 0 0.00284148455236 +Gb336_5 ns336 0 ni5 0 0.00324164386809 +Gb338_5 ns338 0 ni5 0 0.00325342580249 +Gb340_5 ns340 0 ni5 0 0.00355518260529 +Gb342_5 ns342 0 ni5 0 0.00366332185097 +Gb344_5 ns344 0 ni5 0 0.00369157597683 +Gb346_5 ns346 0 ni5 0 0.00403730977574 +Gb348_5 ns348 0 ni5 0 0.00400014469118 +Gb350_5 ns350 0 ni5 0 0.00409149211931 +Gb352_5 ns352 0 ni5 0 0.0041466371046 +Gb354_5 ns354 0 ni5 0 0.00456957212759 +Gb356_5 ns356 0 ni5 0 0.00483731780947 +Gb358_5 ns358 0 ni5 0 0.00498397070149 +Gb360_5 ns360 0 ni5 0 0.00518208285211 +Gb362_5 ns362 0 ni5 0 0.00526598695425 +Gb364_5 ns364 0 ni5 0 0.00541407651403 +Gb366_5 ns366 0 ni5 0 0.00560347951305 +Gb368_5 ns368 0 ni5 0 0.00578204439733 +Gb370_5 ns370 0 ni5 0 0.0059428825717 +Gb372_5 ns372 0 ni5 0 0.00630956922416 +Gb374_5 ns374 0 ni5 0 0.00636848464284 +Gb376_6 ns376 0 ni6 0 1.57938273183e-007 +Gb377_6 ns377 0 ni6 0 1.88351954407e-005 +Gb378_6 ns378 0 ni6 0 7.5393547401e-005 +Gb379_6 ns379 0 ni6 0 0.000148432843252 +Gb380_6 ns380 0 ni6 0 0.000436699423472 +Gb381_6 ns381 0 ni6 0 0.000622293371522 +Gb383_6 ns383 0 ni6 0 0.00119368533126 +Gb385_6 ns385 0 ni6 0 0.00129596471397 +Gb387_6 ns387 0 ni6 0 0.00173844201787 +Gb389_6 ns389 0 ni6 0 0.00141626942917 +Gb391_6 ns391 0 ni6 0 0.00155804229154 +Gb393_6 ns393 0 ni6 0 0.00160416899667 +Gb395_6 ns395 0 ni6 0 0.00172356523281 +Gb397_6 ns397 0 ni6 0 0.00173799274455 +Gb399_6 ns399 0 ni6 0 0.00185517677638 +Gb401_6 ns401 0 ni6 0 0.00184099820887 +Gb403_6 ns403 0 ni6 0 0.00204771767334 +Gb405_6 ns405 0 ni6 0 0.00204423111956 +Gb407_6 ns407 0 ni6 0 0.00295787739292 +Gb409_6 ns409 0 ni6 0 0.00284148455236 +Gb411_6 ns411 0 ni6 0 0.00324164386809 +Gb413_6 ns413 0 ni6 0 0.00325342580249 +Gb415_6 ns415 0 ni6 0 0.00355518260529 +Gb417_6 ns417 0 ni6 0 0.00366332185097 +Gb419_6 ns419 0 ni6 0 0.00369157597683 +Gb421_6 ns421 0 ni6 0 0.00403730977574 +Gb423_6 ns423 0 ni6 0 0.00400014469118 +Gb425_6 ns425 0 ni6 0 0.00409149211931 +Gb427_6 ns427 0 ni6 0 0.0041466371046 +Gb429_6 ns429 0 ni6 0 0.00456957212759 +Gb431_6 ns431 0 ni6 0 0.00483731780947 +Gb433_6 ns433 0 ni6 0 0.00498397070149 +Gb435_6 ns435 0 ni6 0 0.00518208285211 +Gb437_6 ns437 0 ni6 0 0.00526598695425 +Gb439_6 ns439 0 ni6 0 0.00541407651403 +Gb441_6 ns441 0 ni6 0 0.00560347951305 +Gb443_6 ns443 0 ni6 0 0.00578204439733 +Gb445_6 ns445 0 ni6 0 0.0059428825717 +Gb447_6 ns447 0 ni6 0 0.00630956922416 +Gb449_6 ns449 0 ni6 0 0.00636848464284 + +Gc1_1 0 n2 ns1 0 0.00644995774267 +Gc1_2 0 n2 ns2 0 0.000621200196124 +Gc1_3 0 n2 ns3 0 0.0074612980903 +Gc1_4 0 n2 ns4 0 0.00886268542163 +Gc1_5 0 n2 ns5 0 -0.00212925695911 +Gc1_6 0 n2 ns6 0 2.80532988527e-005 +Gc1_7 0 n2 ns7 0 3.18985205458e-006 +Gc1_8 0 n2 ns8 0 0.00127630331446 +Gc1_9 0 n2 ns9 0 0.0100256173986 +Gc1_10 0 n2 ns10 0 -0.000591033306042 +Gc1_11 0 n2 ns11 0 -7.01890668201e-005 +Gc1_12 0 n2 ns12 0 0.0127817034211 +Gc1_13 0 n2 ns13 0 0.048717993951 +Gc1_14 0 n2 ns14 0 -0.00161326525046 +Gc1_15 0 n2 ns15 0 2.97460399122e-005 +Gc1_16 0 n2 ns16 0 8.76949867681e-005 +Gc1_17 0 n2 ns17 0 -0.000137816347815 +Gc1_18 0 n2 ns18 0 6.78034677642e-005 +Gc1_19 0 n2 ns19 0 5.03845699147e-005 +Gc1_20 0 n2 ns20 0 9.95978071397e-005 +Gc1_21 0 n2 ns21 0 2.20814039052e-006 +Gc1_22 0 n2 ns22 0 2.72945224027e-006 +Gc1_23 0 n2 ns23 0 5.04802537415e-005 +Gc1_24 0 n2 ns24 0 -6.03145282076e-005 +Gc1_25 0 n2 ns25 0 -0.00451746456358 +Gc1_26 0 n2 ns26 0 -9.77069732532e-005 +Gc1_27 0 n2 ns27 0 0.000132232542075 +Gc1_28 0 n2 ns28 0 -0.000920352130415 +Gc1_29 0 n2 ns29 0 -0.000580284826696 +Gc1_30 0 n2 ns30 0 2.40245656585e-005 +Gc1_31 0 n2 ns31 0 3.20654763582e-005 +Gc1_32 0 n2 ns32 0 0.00386992601995 +Gc1_33 0 n2 ns33 0 -0.0137980115307 +Gc1_34 0 n2 ns34 0 -1.2663299604e-005 +Gc1_35 0 n2 ns35 0 5.46579934003e-005 +Gc1_36 0 n2 ns36 0 -2.85134616264e-006 +Gc1_37 0 n2 ns37 0 -1.65302116532e-006 +Gc1_38 0 n2 ns38 0 -1.51479729243e-005 +Gc1_39 0 n2 ns39 0 -2.98931460936e-005 +Gc1_40 0 n2 ns40 0 4.57147698561e-006 +Gc1_41 0 n2 ns41 0 3.60721912627e-006 +Gc1_42 0 n2 ns42 0 1.74210209009e-005 +Gc1_43 0 n2 ns43 0 5.82740830779e-005 +Gc1_44 0 n2 ns44 0 5.1729094829e-005 +Gc1_45 0 n2 ns45 0 5.25369992182e-005 +Gc1_46 0 n2 ns46 0 -0.00432272768755 +Gc1_47 0 n2 ns47 0 -0.0112260703257 +Gc1_48 0 n2 ns48 0 1.81368940155e-006 +Gc1_49 0 n2 ns49 0 -1.99196575346e-005 +Gc1_50 0 n2 ns50 0 -2.84061757064e-005 +Gc1_51 0 n2 ns51 0 0.000296876924615 +Gc1_52 0 n2 ns52 0 -8.73456325166e-006 +Gc1_53 0 n2 ns53 0 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0.00390304181602 +Gc5_4 0 n10 ns4 0 0.00401761537121 +Gc5_5 0 n10 ns5 0 -0.000170454280105 +Gc5_6 0 n10 ns6 0 1.45806594958e-005 +Gc5_7 0 n10 ns7 0 1.03064083531e-005 +Gc5_8 0 n10 ns8 0 0.000158414392669 +Gc5_9 0 n10 ns9 0 -0.000314822033393 +Gc5_10 0 n10 ns10 0 0.000126499481895 +Gc5_11 0 n10 ns11 0 3.56533618301e-005 +Gc5_12 0 n10 ns12 0 -0.00596129160769 +Gc5_13 0 n10 ns13 0 -0.00468392659652 +Gc5_14 0 n10 ns14 0 0.000743240279254 +Gc5_15 0 n10 ns15 0 -0.00059279980639 +Gc5_16 0 n10 ns16 0 6.99160126634e-005 +Gc5_17 0 n10 ns17 0 -4.7458500759e-005 +Gc5_18 0 n10 ns18 0 -0.000206038795953 +Gc5_19 0 n10 ns19 0 0.000115398936772 +Gc5_20 0 n10 ns20 0 -1.59506912273e-005 +Gc5_21 0 n10 ns21 0 6.15279483178e-005 +Gc5_22 0 n10 ns22 0 -2.05722867279e-005 +Gc5_23 0 n10 ns23 0 -3.07028329782e-005 +Gc5_24 0 n10 ns24 0 0.00192557583911 +Gc5_25 0 n10 ns25 0 0.00179551131869 +Gc5_26 0 n10 ns26 0 -3.64027999228e-005 +Gc5_27 0 n10 ns27 0 -3.51409712424e-005 +Gc5_28 0 n10 ns28 0 0.000214343231436 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n10 ns437 0 -1.38577796509e-006 +Gc5_438 0 n10 ns438 0 -2.42398741166e-006 +Gc5_439 0 n10 ns439 0 -5.77695389788e-006 +Gc5_440 0 n10 ns440 0 2.92091446828e-005 +Gc5_441 0 n10 ns441 0 4.6460596293e-005 +Gc5_442 0 n10 ns442 0 0.000181704735287 +Gc5_443 0 n10 ns443 0 5.72711582636e-005 +Gc5_444 0 n10 ns444 0 3.76996187375e-005 +Gc5_445 0 n10 ns445 0 9.40452980983e-005 +Gc5_446 0 n10 ns446 0 -0.000112118509282 +Gc5_447 0 n10 ns447 0 -8.61355755924e-005 +Gc5_448 0 n10 ns448 0 0.000164733661153 +Gc5_449 0 n10 ns449 0 1.17923073741e-005 +Gc5_450 0 n10 ns450 0 1.55824110817e-006 +Gd5_1 0 n10 ni1 0 -0.000207109174224 +Gd5_2 0 n10 ni2 0 -9.5647722289e-006 +Gd5_3 0 n10 ni3 0 -0.000169410565725 +Gd5_4 0 n10 ni4 0 -6.0412618434e-005 +Gd5_5 0 n10 ni5 0 -0.000630270275353 +Gd5_6 0 n10 ni6 0 0.000163470590169 +Gc6_1 0 n12 ns1 0 -0.00645406094231 +Gc6_2 0 n12 ns2 0 -0.000648027965587 +Gc6_3 0 n12 ns3 0 -0.00743915347405 +Gc6_4 0 n12 ns4 0 -0.00877123541701 +Gc6_5 0 n12 ns5 0 0.000355062542054 +Gc6_6 0 n12 ns6 0 8.77532491775e-006 +Gc6_7 0 n12 ns7 0 6.51392902254e-006 +Gc6_8 0 n12 ns8 0 -0.000407834885909 +Gc6_9 0 n12 ns9 0 -0.000385511897744 +Gc6_10 0 n12 ns10 0 0.000107475926273 +Gc6_11 0 n12 ns11 0 -0.000205997293954 +Gc6_12 0 n12 ns12 0 0.00152573623692 +Gc6_13 0 n12 ns13 0 -0.00388257119473 +Gc6_14 0 n12 ns14 0 -0.000591636879808 +Gc6_15 0 n12 ns15 0 -0.00116295717368 +Gc6_16 0 n12 ns16 0 -5.80018407917e-005 +Gc6_17 0 n12 ns17 0 -7.12739139499e-005 +Gc6_18 0 n12 ns18 0 -4.26958685959e-005 +Gc6_19 0 n12 ns19 0 -6.75320067222e-005 +Gc6_20 0 n12 ns20 0 -0.000123397207458 +Gc6_21 0 n12 ns21 0 3.67599622749e-005 +Gc6_22 0 n12 ns22 0 -3.43676650297e-005 +Gc6_23 0 n12 ns23 0 -9.75633775124e-006 +Gc6_24 0 n12 ns24 0 0.00117787949441 +Gc6_25 0 n12 ns25 0 0.00156594726827 +Gc6_26 0 n12 ns26 0 0.000149699478733 +Gc6_27 0 n12 ns27 0 -3.47875070336e-005 +Gc6_28 0 n12 ns28 0 0.000198302146613 +Gc6_29 0 n12 ns29 0 5.61691561531e-005 +Gc6_30 0 n12 ns30 0 1.91741059743e-005 +Gc6_31 0 n12 ns31 0 -9.85122985169e-005 +Gc6_32 0 n12 ns32 0 -0.00174838583855 +Gc6_33 0 n12 ns33 0 0.00195999144329 +Gc6_34 0 n12 ns34 0 -6.15020289488e-006 +Gc6_35 0 n12 ns35 0 1.44105524599e-005 +Gc6_36 0 n12 ns36 0 -6.5759787672e-006 +Gc6_37 0 n12 ns37 0 7.59039360951e-006 +Gc6_38 0 n12 ns38 0 3.5849936845e-005 +Gc6_39 0 n12 ns39 0 -2.1370541969e-006 +Gc6_40 0 n12 ns40 0 1.98877661438e-006 +Gc6_41 0 n12 ns41 0 3.81498180034e-006 +Gc6_42 0 n12 ns42 0 -2.80542824148e-005 +Gc6_43 0 n12 ns43 0 3.98603570801e-005 +Gc6_44 0 n12 ns44 0 -2.14367230521e-005 +Gc6_45 0 n12 ns45 0 6.87363305584e-005 +Gc6_46 0 n12 ns46 0 0.00328974636337 +Gc6_47 0 n12 ns47 0 0.00237732043758 +Gc6_48 0 n12 ns48 0 4.05358653092e-006 +Gc6_49 0 n12 ns49 0 -5.00009268587e-006 +Gc6_50 0 n12 ns50 0 -1.89098906466e-006 +Gc6_51 0 n12 ns51 0 -0.000175841685486 +Gc6_52 0 n12 ns52 0 -4.42956582699e-005 +Gc6_53 0 n12 ns53 0 -1.64042906052e-005 +Gc6_54 0 n12 ns54 0 3.54219645102e-005 +Gc6_55 0 n12 ns55 0 0.000274186526032 +Gc6_56 0 n12 ns56 0 -0.00129305508758 +Gc6_57 0 n12 ns57 0 -0.00221977451961 +Gc6_58 0 n12 ns58 0 -0.000163531814333 +Gc6_59 0 n12 ns59 0 1.85095354265e-005 +Gc6_60 0 n12 ns60 0 -0.000314258076941 +Gc6_61 0 n12 ns61 0 0.000224332841359 +Gc6_62 0 n12 ns62 0 -1.00118254871e-006 +Gc6_63 0 n12 ns63 0 -4.93779614851e-006 +Gc6_64 0 n12 ns64 0 7.05332337359e-005 +Gc6_65 0 n12 ns65 0 3.88428286739e-005 +Gc6_66 0 n12 ns66 0 0.000146511714021 +Gc6_67 0 n12 ns67 0 0.000344528954931 +Gc6_68 0 n12 ns68 0 8.96835195035e-005 +Gc6_69 0 n12 ns69 0 0.000153871246975 +Gc6_70 0 n12 ns70 0 0.000282688260803 +Gc6_71 0 n12 ns71 0 -0.000188166616761 +Gc6_72 0 n12 ns72 0 -0.000360403235807 +Gc6_73 0 n12 ns73 0 8.15561008236e-005 +Gc6_74 0 n12 ns74 0 -1.71343957153e-006 +Gc6_75 0 n12 ns75 0 6.99938757975e-006 +Gc6_76 0 n12 ns76 0 -0.006372205619 +Gc6_77 0 n12 ns77 0 8.09241657383e-005 +Gc6_78 0 n12 ns78 0 0.0039041484557 +Gc6_79 0 n12 ns79 0 0.00411544345365 +Gc6_80 0 n12 ns80 0 -0.000126023995215 +Gc6_81 0 n12 ns81 0 5.71853206564e-006 +Gc6_82 0 n12 ns82 0 2.13853240654e-006 +Gc6_83 0 n12 ns83 0 0.00025027315533 +Gc6_84 0 n12 ns84 0 0.000637768399549 +Gc6_85 0 n12 ns85 0 -6.37474412127e-005 +Gc6_86 0 n12 ns86 0 -0.000152315065452 +Gc6_87 0 n12 ns87 0 -0.00547702731087 +Gc6_88 0 n12 ns88 0 -0.00144540096775 +Gc6_89 0 n12 ns89 0 -0.000375584547753 +Gc6_90 0 n12 ns90 0 -0.000172428065024 +Gc6_91 0 n12 ns91 0 5.48588408035e-005 +Gc6_92 0 n12 ns92 0 2.81939918927e-005 +Gc6_93 0 n12 ns93 0 -1.90306833743e-005 +Gc6_94 0 n12 ns94 0 -2.77286225349e-005 +Gc6_95 0 n12 ns95 0 -4.7850251006e-005 +Gc6_96 0 n12 ns96 0 0.000190539335894 +Gc6_97 0 n12 ns97 0 0.000124096771196 +Gc6_98 0 n12 ns98 0 -0.000113467792791 +Gc6_99 0 n12 ns99 0 0.00134714130076 +Gc6_100 0 n12 ns100 0 0.000758936216554 +Gc6_101 0 n12 ns101 0 -5.13862794038e-006 +Gc6_102 0 n12 ns102 0 -7.75656566294e-006 +Gc6_103 0 n12 ns103 0 -9.36085645673e-005 +Gc6_104 0 n12 ns104 0 -0.000138966839578 +Gc6_105 0 n12 ns105 0 -5.23669928401e-006 +Gc6_106 0 n12 ns106 0 -3.86504716765e-005 +Gc6_107 0 n12 ns107 0 0.00180344519526 +Gc6_108 0 n12 ns108 0 0.000167636962659 +Gc6_109 0 n12 ns109 0 -7.64856727391e-006 +Gc6_110 0 n12 ns110 0 4.16733035357e-006 +Gc6_111 0 n12 ns111 0 7.87320640808e-007 +Gc6_112 0 n12 ns112 0 -1.65180875454e-006 +Gc6_113 0 n12 ns113 0 -1.27407094569e-005 +Gc6_114 0 n12 ns114 0 -2.57299798786e-005 +Gc6_115 0 n12 ns115 0 3.92152349294e-006 +Gc6_116 0 n12 ns116 0 -9.82991668323e-007 +Gc6_117 0 n12 ns117 0 1.96019016502e-006 +Gc6_118 0 n12 ns118 0 -9.43340216576e-005 +Gc6_119 0 n12 ns119 0 -1.5167389429e-005 +Gc6_120 0 n12 ns120 0 -7.26840628612e-006 +Gc6_121 0 n12 ns121 0 -0.000995456702223 +Gc6_122 0 n12 ns122 0 0.00154084958941 +Gc6_123 0 n12 ns123 0 -2.79377930181e-005 +Gc6_124 0 n12 ns124 0 -1.48874958669e-005 +Gc6_125 0 n12 ns125 0 -6.35511059377e-006 +Gc6_126 0 n12 ns126 0 -1.6962227631e-005 +Gc6_127 0 n12 ns127 0 8.12032850755e-007 +Gc6_128 0 n12 ns128 0 -1.48777777018e-005 +Gc6_129 0 n12 ns129 0 3.77141094145e-005 +Gc6_130 0 n12 ns130 0 6.04024363016e-005 +Gc6_131 0 n12 ns131 0 4.88707727227e-005 +Gc6_132 0 n12 ns132 0 2.60426824474e-005 +Gc6_133 0 n12 ns133 0 -1.08213159264e-005 +Gc6_134 0 n12 ns134 0 6.38241263171e-005 +Gc6_135 0 n12 ns135 0 0.000148193876173 +Gc6_136 0 n12 ns136 0 4.89508618806e-005 +Gc6_137 0 n12 ns137 0 -7.6100608142e-006 +Gc6_138 0 n12 ns138 0 -4.54736790852e-006 +Gc6_139 0 n12 ns139 0 6.35777347404e-005 +Gc6_140 0 n12 ns140 0 -1.72895042231e-005 +Gc6_141 0 n12 ns141 0 0.000226394789039 +Gc6_142 0 n12 ns142 0 -0.000227361913287 +Gc6_143 0 n12 ns143 0 2.53357677204e-005 +Gc6_144 0 n12 ns144 0 -9.81860692866e-005 +Gc6_145 0 n12 ns145 0 -6.50483650637e-005 +Gc6_146 0 n12 ns146 0 -0.000180371860115 +Gc6_147 0 n12 ns147 0 0.000218489905467 +Gc6_148 0 n12 ns148 0 0.000236401236879 +Gc6_149 0 n12 ns149 0 4.38593739335e-006 +Gc6_150 0 n12 ns150 0 -1.14314581172e-005 +Gc6_151 0 n12 ns151 0 -0.00637174039933 +Gc6_152 0 n12 ns152 0 7.06871155923e-005 +Gc6_153 0 n12 ns153 0 0.0036166499838 +Gc6_154 0 n12 ns154 0 0.00431620054274 +Gc6_155 0 n12 ns155 0 4.32050476668e-005 +Gc6_156 0 n12 ns156 0 6.24283405379e-006 +Gc6_157 0 n12 ns157 0 -2.13035269689e-006 +Gc6_158 0 n12 ns158 0 0.000171674427852 +Gc6_159 0 n12 ns159 0 0.000136358409639 +Gc6_160 0 n12 ns160 0 2.40132033072e-005 +Gc6_161 0 n12 ns161 0 0.000349893633322 +Gc6_162 0 n12 ns162 0 -0.00404396341502 +Gc6_163 0 n12 ns163 0 -0.00648591923701 +Gc6_164 0 n12 ns164 0 0.000842981003458 +Gc6_165 0 n12 ns165 0 -5.05613628039e-005 +Gc6_166 0 n12 ns166 0 8.88479705726e-005 +Gc6_167 0 n12 ns167 0 -6.47729018205e-005 +Gc6_168 0 n12 ns168 0 -7.15636828257e-005 +Gc6_169 0 n12 ns169 0 -3.40437759059e-005 +Gc6_170 0 n12 ns170 0 -0.000101554808196 +Gc6_171 0 n12 ns171 0 7.828477701e-005 +Gc6_172 0 n12 ns172 0 -5.97758620461e-005 +Gc6_173 0 n12 ns173 0 1.85239900501e-008 +Gc6_174 0 n12 ns174 0 0.00546102150884 +Gc6_175 0 n12 ns175 0 0.00255633990565 +Gc6_176 0 n12 ns176 0 -5.39976397552e-005 +Gc6_177 0 n12 ns177 0 -1.45886840692e-005 +Gc6_178 0 n12 ns178 0 0.00044002313627 +Gc6_179 0 n12 ns179 0 -0.000420196994737 +Gc6_180 0 n12 ns180 0 0.000419662677045 +Gc6_181 0 n12 ns181 0 -0.000491366803919 +Gc6_182 0 n12 ns182 0 0.00342559300318 +Gc6_183 0 n12 ns183 0 0.00628848370011 +Gc6_184 0 n12 ns184 0 -5.31539375583e-005 +Gc6_185 0 n12 ns185 0 7.02098857388e-005 +Gc6_186 0 n12 ns186 0 -2.32791974678e-006 +Gc6_187 0 n12 ns187 0 2.31773351841e-006 +Gc6_188 0 n12 ns188 0 3.96008218368e-005 +Gc6_189 0 n12 ns189 0 -2.37927382382e-005 +Gc6_190 0 n12 ns190 0 -1.22085198949e-005 +Gc6_191 0 n12 ns191 0 -1.60589560589e-005 +Gc6_192 0 n12 ns192 0 -7.00721379198e-006 +Gc6_193 0 n12 ns193 0 2.30570592151e-005 +Gc6_194 0 n12 ns194 0 2.34049406118e-005 +Gc6_195 0 n12 ns195 0 -2.58148197989e-006 +Gc6_196 0 n12 ns196 0 -0.00428478265807 +Gc6_197 0 n12 ns197 0 -0.00130121904776 +Gc6_198 0 n12 ns198 0 1.65536263875e-007 +Gc6_199 0 n12 ns199 0 -4.02577737219e-006 +Gc6_200 0 n12 ns200 0 -2.14803015935e-005 +Gc6_201 0 n12 ns201 0 1.2633351179e-005 +Gc6_202 0 n12 ns202 0 4.00623814701e-005 +Gc6_203 0 n12 ns203 0 8.79366305242e-005 +Gc6_204 0 n12 ns204 0 7.91817701585e-005 +Gc6_205 0 n12 ns205 0 3.48204896231e-006 +Gc6_206 0 n12 ns206 0 0.000319086299082 +Gc6_207 0 n12 ns207 0 0.000522580148487 +Gc6_208 0 n12 ns208 0 0.000187619904823 +Gc6_209 0 n12 ns209 0 4.36961649624e-005 +Gc6_210 0 n12 ns210 0 1.11917613348e-005 +Gc6_211 0 n12 ns211 0 -4.52275579703e-005 +Gc6_212 0 n12 ns212 0 6.53377918429e-006 +Gc6_213 0 n12 ns213 0 5.97475092323e-006 +Gc6_214 0 n12 ns214 0 -4.21369459736e-005 +Gc6_215 0 n12 ns215 0 2.88251841568e-005 +Gc6_216 0 n12 ns216 0 -0.000153140839379 +Gc6_217 0 n12 ns217 0 6.98965226206e-006 +Gc6_218 0 n12 ns218 0 -1.72131631097e-005 +Gc6_219 0 n12 ns219 0 3.38833329035e-005 +Gc6_220 0 n12 ns220 0 1.06030146535e-005 +Gc6_221 0 n12 ns221 0 5.74880293815e-005 +Gc6_222 0 n12 ns222 0 9.36221853565e-005 +Gc6_223 0 n12 ns223 0 0.000147681703295 +Gc6_224 0 n12 ns224 0 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ns272 0 -0.00574997055311 +Gc6_273 0 n12 ns273 0 3.33201877438e-006 +Gc6_274 0 n12 ns274 0 4.68928106009e-006 +Gc6_275 0 n12 ns275 0 -4.86355846497e-005 +Gc6_276 0 n12 ns276 0 -3.89240894812e-006 +Gc6_277 0 n12 ns277 0 -6.95644561956e-006 +Gc6_278 0 n12 ns278 0 0.000159660582656 +Gc6_279 0 n12 ns279 0 0.00016737687907 +Gc6_280 0 n12 ns280 0 -4.4851497488e-005 +Gc6_281 0 n12 ns281 0 -1.47202463578e-005 +Gc6_282 0 n12 ns282 0 0.000431539580677 +Gc6_283 0 n12 ns283 0 -4.88760808605e-006 +Gc6_284 0 n12 ns284 0 9.33800036308e-005 +Gc6_285 0 n12 ns285 0 -2.16408992731e-005 +Gc6_286 0 n12 ns286 0 2.12400472313e-005 +Gc6_287 0 n12 ns287 0 1.36490901438e-005 +Gc6_288 0 n12 ns288 0 -1.04998899391e-007 +Gc6_289 0 n12 ns289 0 -1.1102378816e-005 +Gc6_290 0 n12 ns290 0 1.24482046885e-006 +Gc6_291 0 n12 ns291 0 -6.65666052327e-005 +Gc6_292 0 n12 ns292 0 8.09113669268e-005 +Gc6_293 0 n12 ns293 0 -5.77260786847e-006 +Gc6_294 0 n12 ns294 0 6.28201097971e-005 +Gc6_295 0 n12 ns295 0 -6.50580237899e-005 +Gc6_296 0 n12 ns296 0 -7.1390908542e-005 +Gc6_297 0 n12 ns297 0 2.34684057163e-006 +Gc6_298 0 n12 ns298 0 0.00021712867823 +Gc6_299 0 n12 ns299 0 1.76080488625e-005 +Gc6_300 0 n12 ns300 0 -4.17514659738e-006 +Gc6_301 0 n12 ns301 0 0.0063791218403 +Gc6_302 0 n12 ns302 0 -8.4029941868e-005 +Gc6_303 0 n12 ns303 0 -0.00388644303103 +Gc6_304 0 n12 ns304 0 -0.00407375171946 +Gc6_305 0 n12 ns305 0 0.000324422494767 +Gc6_306 0 n12 ns306 0 5.69406925265e-006 +Gc6_307 0 n12 ns307 0 4.69732150907e-006 +Gc6_308 0 n12 ns308 0 7.52321518093e-005 +Gc6_309 0 n12 ns309 0 0.000252922197117 +Gc6_310 0 n12 ns310 0 4.5469360288e-005 +Gc6_311 0 n12 ns311 0 0.000192165261875 +Gc6_312 0 n12 ns312 0 -0.00339100075176 +Gc6_313 0 n12 ns313 0 -0.00440464889206 +Gc6_314 0 n12 ns314 0 0.000713258502069 +Gc6_315 0 n12 ns315 0 7.26327310527e-005 +Gc6_316 0 n12 ns316 0 -3.83822886133e-005 +Gc6_317 0 n12 ns317 0 3.63972132192e-005 +Gc6_318 0 n12 ns318 0 0.000168250697917 +Gc6_319 0 n12 ns319 0 -8.65716214129e-006 +Gc6_320 0 n12 ns320 0 -1.49392517264e-005 +Gc6_321 0 n12 ns321 0 -0.000146664649011 +Gc6_322 0 n12 ns322 0 9.67964879836e-005 +Gc6_323 0 n12 ns323 0 9.58523047611e-005 +Gc6_324 0 n12 ns324 0 -0.000699955471035 +Gc6_325 0 n12 ns325 0 -0.00284884012415 +Gc6_326 0 n12 ns326 0 2.36841517402e-006 +Gc6_327 0 n12 ns327 0 4.64026921583e-005 +Gc6_328 0 n12 ns328 0 -0.0012209832632 +Gc6_329 0 n12 ns329 0 -0.000978801164029 +Gc6_330 0 n12 ns330 0 -0.000182512404171 +Gc6_331 0 n12 ns331 0 0.000162663847063 +Gc6_332 0 n12 ns332 0 0.00883135211687 +Gc6_333 0 n12 ns333 0 -0.0070805049992 +Gc6_334 0 n12 ns334 0 -3.27958509258e-005 +Gc6_335 0 n12 ns335 0 4.05862678993e-005 +Gc6_336 0 n12 ns336 0 -1.01332729842e-005 +Gc6_337 0 n12 ns337 0 -7.07971587212e-006 +Gc6_338 0 n12 ns338 0 3.55529922164e-005 +Gc6_339 0 n12 ns339 0 -5.7377930537e-005 +Gc6_340 0 n12 ns340 0 5.48271318296e-006 +Gc6_341 0 n12 ns341 0 4.17518176109e-006 +Gc6_342 0 n12 ns342 0 7.02567772828e-005 +Gc6_343 0 n12 ns343 0 -6.67167097394e-006 +Gc6_344 0 n12 ns344 0 3.99736525117e-005 +Gc6_345 0 n12 ns345 0 -1.25092779549e-005 +Gc6_346 0 n12 ns346 0 -0.0033075166728 +Gc6_347 0 n12 ns347 0 -0.00584502269979 +Gc6_348 0 n12 ns348 0 1.25513670829e-005 +Gc6_349 0 n12 ns349 0 2.52663387197e-005 +Gc6_350 0 n12 ns350 0 -3.69113489367e-005 +Gc6_351 0 n12 ns351 0 4.8258275442e-005 +Gc6_352 0 n12 ns352 0 9.71531758768e-006 +Gc6_353 0 n12 ns353 0 -6.02685666507e-005 +Gc6_354 0 n12 ns354 0 6.78917516211e-005 +Gc6_355 0 n12 ns355 0 -0.000120227072681 +Gc6_356 0 n12 ns356 0 -8.64023284131e-005 +Gc6_357 0 n12 ns357 0 0.000294163857677 +Gc6_358 0 n12 ns358 0 -0.000109218795938 +Gc6_359 0 n12 ns359 0 6.59405542415e-005 +Gc6_360 0 n12 ns360 0 -1.69047430265e-005 +Gc6_361 0 n12 ns361 0 0.000100170260511 +Gc6_362 0 n12 ns362 0 -1.80925345053e-006 +Gc6_363 0 n12 ns363 0 -2.24973398131e-006 +Gc6_364 0 n12 ns364 0 -5.09504689268e-006 +Gc6_365 0 n12 ns365 0 2.58926414553e-005 +Gc6_366 0 n12 ns366 0 4.41569300909e-005 +Gc6_367 0 n12 ns367 0 0.000163669203533 +Gc6_368 0 n12 ns368 0 4.80130790528e-005 +Gc6_369 0 n12 ns369 0 3.03806498801e-005 +Gc6_370 0 n12 ns370 0 8.96482632629e-005 +Gc6_371 0 n12 ns371 0 -0.000113300511807 +Gc6_372 0 n12 ns372 0 -0.000110163854856 +Gc6_373 0 n12 ns373 0 0.000151398320606 +Gc6_374 0 n12 ns374 0 1.03756383106e-005 +Gc6_375 0 n12 ns375 0 4.32468245638e-006 +Gc6_376 0 n12 ns376 0 0.00645904595582 +Gc6_377 0 n12 ns377 0 0.000621391391188 +Gc6_378 0 n12 ns378 0 0.00733566782631 +Gc6_379 0 n12 ns379 0 0.00898275720659 +Gc6_380 0 n12 ns380 0 -0.00365889178581 +Gc6_381 0 n12 ns381 0 1.25705794348e-005 +Gc6_382 0 n12 ns382 0 2.05178580828e-006 +Gc6_383 0 n12 ns383 0 0.000147170248435 +Gc6_384 0 n12 ns384 0 -0.000526626529279 +Gc6_385 0 n12 ns385 0 -7.08125613297e-005 +Gc6_386 0 n12 ns386 0 -0.000221102424573 +Gc6_387 0 n12 ns387 0 0.0160672576774 +Gc6_388 0 n12 ns388 0 0.0460098231828 +Gc6_389 0 n12 ns389 0 -0.000521600309255 +Gc6_390 0 n12 ns390 0 0.000466154518665 +Gc6_391 0 n12 ns391 0 -0.000117239859056 +Gc6_392 0 n12 ns392 0 7.30989022451e-005 +Gc6_393 0 n12 ns393 0 -1.1537541296e-005 +Gc6_394 0 n12 ns394 0 7.71696712516e-005 +Gc6_395 0 n12 ns395 0 0.000116281531514 +Gc6_396 0 n12 ns396 0 -0.000236194438421 +Gc6_397 0 n12 ns397 0 -0.000141662066129 +Gc6_398 0 n12 ns398 0 -4.12285380125e-006 +Gc6_399 0 n12 ns399 0 -0.00127329013454 +Gc6_400 0 n12 ns400 0 0.00129932354852 +Gc6_401 0 n12 ns401 0 -0.000130826403973 +Gc6_402 0 n12 ns402 0 -6.79480683011e-005 +Gc6_403 0 n12 ns403 0 0.000729948711561 +Gc6_404 0 n12 ns404 0 -0.000869958642925 +Gc6_405 0 n12 ns405 0 -0.000214848490319 +Gc6_406 0 n12 ns406 0 0.000181770110721 +Gc6_407 0 n12 ns407 0 -0.0180848386322 +Gc6_408 0 n12 ns408 0 -0.00898699709448 +Gc6_409 0 n12 ns409 0 -3.58900909558e-006 +Gc6_410 0 n12 ns410 0 3.93027126284e-006 +Gc6_411 0 n12 ns411 0 6.66912252349e-006 +Gc6_412 0 n12 ns412 0 6.72949606031e-006 +Gc6_413 0 n12 ns413 0 -3.23095417977e-005 +Gc6_414 0 n12 ns414 0 -1.78046154179e-005 +Gc6_415 0 n12 ns415 0 1.03405518935e-006 +Gc6_416 0 n12 ns416 0 6.96169600741e-006 +Gc6_417 0 n12 ns417 0 -3.59574181264e-005 +Gc6_418 0 n12 ns418 0 1.96773362297e-005 +Gc6_419 0 n12 ns419 0 -6.39711194024e-005 +Gc6_420 0 n12 ns420 0 1.3443812397e-005 +Gc6_421 0 n12 ns421 0 0.00676639084401 +Gc6_422 0 n12 ns422 0 0.00216745917601 +Gc6_423 0 n12 ns423 0 1.13106079421e-005 +Gc6_424 0 n12 ns424 0 -3.82978510455e-006 +Gc6_425 0 n12 ns425 0 -3.2773661687e-005 +Gc6_426 0 n12 ns426 0 5.90195143332e-005 +Gc6_427 0 n12 ns427 0 4.12209162048e-005 +Gc6_428 0 n12 ns428 0 -7.02533021021e-005 +Gc6_429 0 n12 ns429 0 3.51356893189e-005 +Gc6_430 0 n12 ns430 0 -3.37499751323e-005 +Gc6_431 0 n12 ns431 0 0.000111789458547 +Gc6_432 0 n12 ns432 0 0.000756878557636 +Gc6_433 0 n12 ns433 0 0.000111943798615 +Gc6_434 0 n12 ns434 0 7.08739079528e-005 +Gc6_435 0 n12 ns435 0 0.000159189989983 +Gc6_436 0 n12 ns436 0 -0.000454871208681 +Gc6_437 0 n12 ns437 0 -4.53604697232e-006 +Gc6_438 0 n12 ns438 0 5.26170475412e-006 +Gc6_439 0 n12 ns439 0 -9.03720924596e-005 +Gc6_440 0 n12 ns440 0 -8.10887294268e-005 +Gc6_441 0 n12 ns441 0 -0.000221522473626 +Gc6_442 0 n12 ns442 0 -0.000705785333902 +Gc6_443 0 n12 ns443 0 -0.000151218651557 +Gc6_444 0 n12 ns444 0 -0.000436738555834 +Gc6_445 0 n12 ns445 0 -0.000131230035516 +Gc6_446 0 n12 ns446 0 0.000788921496592 +Gc6_447 0 n12 ns447 0 0.00131908820671 +Gc6_448 0 n12 ns448 0 -0.000912763699059 +Gc6_449 0 n12 ns449 0 3.55897526787e-005 +Gc6_450 0 n12 ns450 0 -6.95038791696e-005 +Gd6_1 0 n12 ni1 0 0.000162761513184 +Gd6_2 0 n12 ni2 0 -1.9993064183e-005 +Gd6_3 0 n12 ni3 0 0.000125694359353 +Gd6_4 0 n12 ni4 0 0.000375083396516 +Gd6_5 0 n12 ni5 0 0.000219586025833 +Gd6_6 0 n12 ni6 0 0.000394028882586 +.ends + + +.subckt 744837006400 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 20559286.3048 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 9285144.58453 +Ca3 ns3 0 1e-012 +Ca4 ns4 0 1e-012 +Ra3 ns3 0 352539453.948 +Ra4 ns4 0 352539453.948 +Ga3 ns3 0 ns4 0 5.56297979207e-007 +Ga4 ns4 0 ns3 0 -5.56297979207e-007 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 979183.600565 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 214434.86522 +Ca7 ns7 0 1e-012 +Ra7 ns7 0 74365.7712357 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 1609829.19467 +Ra9 ns9 0 1609829.19467 +Ga8 ns8 0 ns9 0 1.59275450809e-005 +Ga9 ns9 0 ns8 0 -1.59275450809e-005 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 3029138.22563 +Ra11 ns11 0 3029138.22563 +Ga10 ns10 0 ns11 0 1.921630072e-005 +Ga11 ns11 0 ns10 0 -1.921630072e-005 +Ca12 ns12 0 1e-012 +Ra12 ns12 0 35425.2148101 +Ca13 ns13 0 1e-012 +Ra13 ns13 0 22706.766394 +Ca14 ns14 0 1e-012 +Ra14 ns14 0 10168.0001641 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 285361.668899 +Ra16 ns16 0 285361.668899 +Ga15 ns15 0 ns16 0 0.000213615228399 +Ga16 ns16 0 ns15 0 -0.000213615228399 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 39812.6183749 +Ra18 ns18 0 39812.6183749 +Ga17 ns17 0 ns18 0 -0.000280785203622 +Ga18 ns18 0 ns17 0 0.000280785203622 +Ca19 ns19 0 1e-012 +Ca20 ns20 0 1e-012 +Ra19 ns19 0 14286.3867865 +Ra20 ns20 0 14286.3867865 +Ga19 ns19 0 ns20 0 0.00040393302129 +Ga20 ns20 0 ns19 0 -0.00040393302129 +Ca21 ns21 0 1e-012 +Ca22 ns22 0 1e-012 +Ra21 ns21 0 27778.9174105 +Ra22 ns22 0 27778.9174105 +Ga21 ns21 0 ns22 0 0.000464951480933 +Ga22 ns22 0 ns21 0 -0.000464951480933 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 2338.76241595 +Ra24 ns24 0 2338.76241595 +Ga23 ns23 0 ns24 0 0.000308288775945 +Ga24 ns24 0 ns23 0 -0.000308288775945 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 4561.10737382 +Ra26 ns26 0 4561.10737382 +Ga25 ns25 0 ns26 0 0.000505848852909 +Ga26 ns26 0 ns25 0 -0.000505848852909 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 7262.24557758 +Ra28 ns28 0 7262.24557758 +Ga27 ns27 0 ns28 0 0.000645927620813 +Ga28 ns28 0 ns27 0 -0.000645927620813 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 6275.57561854 +Ra30 ns30 0 6275.57561854 +Ga29 ns29 0 ns30 0 0.000769982291801 +Ga30 ns30 0 ns29 0 -0.000769982291801 +Ca31 ns31 0 1e-012 +Ra31 ns31 0 20559286.3048 +Ca32 ns32 0 1e-012 +Ra32 ns32 0 9285144.58453 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 352539453.948 +Ra34 ns34 0 352539453.948 +Ga33 ns33 0 ns34 0 5.56297979207e-007 +Ga34 ns34 0 ns33 0 -5.56297979207e-007 +Ca35 ns35 0 1e-012 +Ra35 ns35 0 979183.600565 +Ca36 ns36 0 1e-012 +Ra36 ns36 0 214434.86522 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 74365.7712357 +Ca38 ns38 0 1e-012 +Ca39 ns39 0 1e-012 +Ra38 ns38 0 1609829.19467 +Ra39 ns39 0 1609829.19467 +Ga38 ns38 0 ns39 0 1.59275450809e-005 +Ga39 ns39 0 ns38 0 -1.59275450809e-005 +Ca40 ns40 0 1e-012 +Ca41 ns41 0 1e-012 +Ra40 ns40 0 3029138.22563 +Ra41 ns41 0 3029138.22563 +Ga40 ns40 0 ns41 0 1.921630072e-005 +Ga41 ns41 0 ns40 0 -1.921630072e-005 +Ca42 ns42 0 1e-012 +Ra42 ns42 0 35425.2148101 +Ca43 ns43 0 1e-012 +Ra43 ns43 0 22706.766394 +Ca44 ns44 0 1e-012 +Ra44 ns44 0 10168.0001641 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 285361.668899 +Ra46 ns46 0 285361.668899 +Ga45 ns45 0 ns46 0 0.000213615228399 +Ga46 ns46 0 ns45 0 -0.000213615228399 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 39812.6183749 +Ra48 ns48 0 39812.6183749 +Ga47 ns47 0 ns48 0 -0.000280785203622 +Ga48 ns48 0 ns47 0 0.000280785203622 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 14286.3867865 +Ra50 ns50 0 14286.3867865 +Ga49 ns49 0 ns50 0 0.00040393302129 +Ga50 ns50 0 ns49 0 -0.00040393302129 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 27778.9174105 +Ra52 ns52 0 27778.9174105 +Ga51 ns51 0 ns52 0 0.000464951480933 +Ga52 ns52 0 ns51 0 -0.000464951480933 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 2338.76241595 +Ra54 ns54 0 2338.76241595 +Ga53 ns53 0 ns54 0 0.000308288775945 +Ga54 ns54 0 ns53 0 -0.000308288775945 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 4561.10737382 +Ra56 ns56 0 4561.10737382 +Ga55 ns55 0 ns56 0 0.000505848852909 +Ga56 ns56 0 ns55 0 -0.000505848852909 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 7262.24557758 +Ra58 ns58 0 7262.24557758 +Ga57 ns57 0 ns58 0 0.000645927620813 +Ga58 ns58 0 ns57 0 -0.000645927620813 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 6275.57561854 +Ra60 ns60 0 6275.57561854 +Ga59 ns59 0 ns60 0 0.000769982291801 +Ga60 ns60 0 ns59 0 -0.000769982291801 +Ca61 ns61 0 1e-012 +Ra61 ns61 0 20559286.3048 +Ca62 ns62 0 1e-012 +Ra62 ns62 0 9285144.58453 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 352539453.948 +Ra64 ns64 0 352539453.948 +Ga63 ns63 0 ns64 0 5.56297979207e-007 +Ga64 ns64 0 ns63 0 -5.56297979207e-007 +Ca65 ns65 0 1e-012 +Ra65 ns65 0 979183.600565 +Ca66 ns66 0 1e-012 +Ra66 ns66 0 214434.86522 +Ca67 ns67 0 1e-012 +Ra67 ns67 0 74365.7712357 +Ca68 ns68 0 1e-012 +Ca69 ns69 0 1e-012 +Ra68 ns68 0 1609829.19467 +Ra69 ns69 0 1609829.19467 +Ga68 ns68 0 ns69 0 1.59275450809e-005 +Ga69 ns69 0 ns68 0 -1.59275450809e-005 +Ca70 ns70 0 1e-012 +Ca71 ns71 0 1e-012 +Ra70 ns70 0 3029138.22563 +Ra71 ns71 0 3029138.22563 +Ga70 ns70 0 ns71 0 1.921630072e-005 +Ga71 ns71 0 ns70 0 -1.921630072e-005 +Ca72 ns72 0 1e-012 +Ra72 ns72 0 35425.2148101 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 22706.766394 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 10168.0001641 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 285361.668899 +Ra76 ns76 0 285361.668899 +Ga75 ns75 0 ns76 0 0.000213615228399 +Ga76 ns76 0 ns75 0 -0.000213615228399 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 39812.6183749 +Ra78 ns78 0 39812.6183749 +Ga77 ns77 0 ns78 0 -0.000280785203622 +Ga78 ns78 0 ns77 0 0.000280785203622 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 14286.3867865 +Ra80 ns80 0 14286.3867865 +Ga79 ns79 0 ns80 0 0.00040393302129 +Ga80 ns80 0 ns79 0 -0.00040393302129 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 27778.9174105 +Ra82 ns82 0 27778.9174105 +Ga81 ns81 0 ns82 0 0.000464951480933 +Ga82 ns82 0 ns81 0 -0.000464951480933 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 2338.76241595 +Ra84 ns84 0 2338.76241595 +Ga83 ns83 0 ns84 0 0.000308288775945 +Ga84 ns84 0 ns83 0 -0.000308288775945 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 4561.10737382 +Ra86 ns86 0 4561.10737382 +Ga85 ns85 0 ns86 0 0.000505848852909 +Ga86 ns86 0 ns85 0 -0.000505848852909 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 7262.24557758 +Ra88 ns88 0 7262.24557758 +Ga87 ns87 0 ns88 0 0.000645927620813 +Ga88 ns88 0 ns87 0 -0.000645927620813 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 6275.57561854 +Ra90 ns90 0 6275.57561854 +Ga89 ns89 0 ns90 0 0.000769982291801 +Ga90 ns90 0 ns89 0 -0.000769982291801 +Ca91 ns91 0 1e-012 +Ra91 ns91 0 20559286.3048 +Ca92 ns92 0 1e-012 +Ra92 ns92 0 9285144.58453 +Ca93 ns93 0 1e-012 +Ca94 ns94 0 1e-012 +Ra93 ns93 0 352539453.948 +Ra94 ns94 0 352539453.948 +Ga93 ns93 0 ns94 0 5.56297979207e-007 +Ga94 ns94 0 ns93 0 -5.56297979207e-007 +Ca95 ns95 0 1e-012 +Ra95 ns95 0 979183.600565 +Ca96 ns96 0 1e-012 +Ra96 ns96 0 214434.86522 +Ca97 ns97 0 1e-012 +Ra97 ns97 0 74365.7712357 +Ca98 ns98 0 1e-012 +Ca99 ns99 0 1e-012 +Ra98 ns98 0 1609829.19467 +Ra99 ns99 0 1609829.19467 +Ga98 ns98 0 ns99 0 1.59275450809e-005 +Ga99 ns99 0 ns98 0 -1.59275450809e-005 +Ca100 ns100 0 1e-012 +Ca101 ns101 0 1e-012 +Ra100 ns100 0 3029138.22563 +Ra101 ns101 0 3029138.22563 +Ga100 ns100 0 ns101 0 1.921630072e-005 +Ga101 ns101 0 ns100 0 -1.921630072e-005 +Ca102 ns102 0 1e-012 +Ra102 ns102 0 35425.2148101 +Ca103 ns103 0 1e-012 +Ra103 ns103 0 22706.766394 +Ca104 ns104 0 1e-012 +Ra104 ns104 0 10168.0001641 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 285361.668899 +Ra106 ns106 0 285361.668899 +Ga105 ns105 0 ns106 0 0.000213615228399 +Ga106 ns106 0 ns105 0 -0.000213615228399 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 39812.6183749 +Ra108 ns108 0 39812.6183749 +Ga107 ns107 0 ns108 0 -0.000280785203622 +Ga108 ns108 0 ns107 0 0.000280785203622 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 14286.3867865 +Ra110 ns110 0 14286.3867865 +Ga109 ns109 0 ns110 0 0.00040393302129 +Ga110 ns110 0 ns109 0 -0.00040393302129 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 27778.9174105 +Ra112 ns112 0 27778.9174105 +Ga111 ns111 0 ns112 0 0.000464951480933 +Ga112 ns112 0 ns111 0 -0.000464951480933 +Ca113 ns113 0 1e-012 +Ca114 ns114 0 1e-012 +Ra113 ns113 0 2338.76241595 +Ra114 ns114 0 2338.76241595 +Ga113 ns113 0 ns114 0 0.000308288775945 +Ga114 ns114 0 ns113 0 -0.000308288775945 +Ca115 ns115 0 1e-012 +Ca116 ns116 0 1e-012 +Ra115 ns115 0 4561.10737382 +Ra116 ns116 0 4561.10737382 +Ga115 ns115 0 ns116 0 0.000505848852909 +Ga116 ns116 0 ns115 0 -0.000505848852909 +Ca117 ns117 0 1e-012 +Ca118 ns118 0 1e-012 +Ra117 ns117 0 7262.24557758 +Ra118 ns118 0 7262.24557758 +Ga117 ns117 0 ns118 0 0.000645927620813 +Ga118 ns118 0 ns117 0 -0.000645927620813 +Ca119 ns119 0 1e-012 +Ca120 ns120 0 1e-012 +Ra119 ns119 0 6275.57561854 +Ra120 ns120 0 6275.57561854 +Ga119 ns119 0 ns120 0 0.000769982291801 +Ga120 ns120 0 ns119 0 -0.000769982291801 +Ca121 ns121 0 1e-012 +Ra121 ns121 0 20559286.3048 +Ca122 ns122 0 1e-012 +Ra122 ns122 0 9285144.58453 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 352539453.948 +Ra124 ns124 0 352539453.948 +Ga123 ns123 0 ns124 0 5.56297979207e-007 +Ga124 ns124 0 ns123 0 -5.56297979207e-007 +Ca125 ns125 0 1e-012 +Ra125 ns125 0 979183.600565 +Ca126 ns126 0 1e-012 +Ra126 ns126 0 214434.86522 +Ca127 ns127 0 1e-012 +Ra127 ns127 0 74365.7712357 +Ca128 ns128 0 1e-012 +Ca129 ns129 0 1e-012 +Ra128 ns128 0 1609829.19467 +Ra129 ns129 0 1609829.19467 +Ga128 ns128 0 ns129 0 1.59275450809e-005 +Ga129 ns129 0 ns128 0 -1.59275450809e-005 +Ca130 ns130 0 1e-012 +Ca131 ns131 0 1e-012 +Ra130 ns130 0 3029138.22563 +Ra131 ns131 0 3029138.22563 +Ga130 ns130 0 ns131 0 1.921630072e-005 +Ga131 ns131 0 ns130 0 -1.921630072e-005 +Ca132 ns132 0 1e-012 +Ra132 ns132 0 35425.2148101 +Ca133 ns133 0 1e-012 +Ra133 ns133 0 22706.766394 +Ca134 ns134 0 1e-012 +Ra134 ns134 0 10168.0001641 +Ca135 ns135 0 1e-012 +Ca136 ns136 0 1e-012 +Ra135 ns135 0 285361.668899 +Ra136 ns136 0 285361.668899 +Ga135 ns135 0 ns136 0 0.000213615228399 +Ga136 ns136 0 ns135 0 -0.000213615228399 +Ca137 ns137 0 1e-012 +Ca138 ns138 0 1e-012 +Ra137 ns137 0 39812.6183749 +Ra138 ns138 0 39812.6183749 +Ga137 ns137 0 ns138 0 -0.000280785203622 +Ga138 ns138 0 ns137 0 0.000280785203622 +Ca139 ns139 0 1e-012 +Ca140 ns140 0 1e-012 +Ra139 ns139 0 14286.3867865 +Ra140 ns140 0 14286.3867865 +Ga139 ns139 0 ns140 0 0.00040393302129 +Ga140 ns140 0 ns139 0 -0.00040393302129 +Ca141 ns141 0 1e-012 +Ca142 ns142 0 1e-012 +Ra141 ns141 0 27778.9174105 +Ra142 ns142 0 27778.9174105 +Ga141 ns141 0 ns142 0 0.000464951480933 +Ga142 ns142 0 ns141 0 -0.000464951480933 +Ca143 ns143 0 1e-012 +Ca144 ns144 0 1e-012 +Ra143 ns143 0 2338.76241595 +Ra144 ns144 0 2338.76241595 +Ga143 ns143 0 ns144 0 0.000308288775945 +Ga144 ns144 0 ns143 0 -0.000308288775945 +Ca145 ns145 0 1e-012 +Ca146 ns146 0 1e-012 +Ra145 ns145 0 4561.10737382 +Ra146 ns146 0 4561.10737382 +Ga145 ns145 0 ns146 0 0.000505848852909 +Ga146 ns146 0 ns145 0 -0.000505848852909 +Ca147 ns147 0 1e-012 +Ca148 ns148 0 1e-012 +Ra147 ns147 0 7262.24557758 +Ra148 ns148 0 7262.24557758 +Ga147 ns147 0 ns148 0 0.000645927620813 +Ga148 ns148 0 ns147 0 -0.000645927620813 +Ca149 ns149 0 1e-012 +Ca150 ns150 0 1e-012 +Ra149 ns149 0 6275.57561854 +Ra150 ns150 0 6275.57561854 +Ga149 ns149 0 ns150 0 0.000769982291801 +Ga150 ns150 0 ns149 0 -0.000769982291801 +Ca151 ns151 0 1e-012 +Ra151 ns151 0 20559286.3048 +Ca152 ns152 0 1e-012 +Ra152 ns152 0 9285144.58453 +Ca153 ns153 0 1e-012 +Ca154 ns154 0 1e-012 +Ra153 ns153 0 352539453.948 +Ra154 ns154 0 352539453.948 +Ga153 ns153 0 ns154 0 5.56297979207e-007 +Ga154 ns154 0 ns153 0 -5.56297979207e-007 +Ca155 ns155 0 1e-012 +Ra155 ns155 0 979183.600565 +Ca156 ns156 0 1e-012 +Ra156 ns156 0 214434.86522 +Ca157 ns157 0 1e-012 +Ra157 ns157 0 74365.7712357 +Ca158 ns158 0 1e-012 +Ca159 ns159 0 1e-012 +Ra158 ns158 0 1609829.19467 +Ra159 ns159 0 1609829.19467 +Ga158 ns158 0 ns159 0 1.59275450809e-005 +Ga159 ns159 0 ns158 0 -1.59275450809e-005 +Ca160 ns160 0 1e-012 +Ca161 ns161 0 1e-012 +Ra160 ns160 0 3029138.22563 +Ra161 ns161 0 3029138.22563 +Ga160 ns160 0 ns161 0 1.921630072e-005 +Ga161 ns161 0 ns160 0 -1.921630072e-005 +Ca162 ns162 0 1e-012 +Ra162 ns162 0 35425.2148101 +Ca163 ns163 0 1e-012 +Ra163 ns163 0 22706.766394 +Ca164 ns164 0 1e-012 +Ra164 ns164 0 10168.0001641 +Ca165 ns165 0 1e-012 +Ca166 ns166 0 1e-012 +Ra165 ns165 0 285361.668899 +Ra166 ns166 0 285361.668899 +Ga165 ns165 0 ns166 0 0.000213615228399 +Ga166 ns166 0 ns165 0 -0.000213615228399 +Ca167 ns167 0 1e-012 +Ca168 ns168 0 1e-012 +Ra167 ns167 0 39812.6183749 +Ra168 ns168 0 39812.6183749 +Ga167 ns167 0 ns168 0 -0.000280785203622 +Ga168 ns168 0 ns167 0 0.000280785203622 +Ca169 ns169 0 1e-012 +Ca170 ns170 0 1e-012 +Ra169 ns169 0 14286.3867865 +Ra170 ns170 0 14286.3867865 +Ga169 ns169 0 ns170 0 0.00040393302129 +Ga170 ns170 0 ns169 0 -0.00040393302129 +Ca171 ns171 0 1e-012 +Ca172 ns172 0 1e-012 +Ra171 ns171 0 27778.9174105 +Ra172 ns172 0 27778.9174105 +Ga171 ns171 0 ns172 0 0.000464951480933 +Ga172 ns172 0 ns171 0 -0.000464951480933 +Ca173 ns173 0 1e-012 +Ca174 ns174 0 1e-012 +Ra173 ns173 0 2338.76241595 +Ra174 ns174 0 2338.76241595 +Ga173 ns173 0 ns174 0 0.000308288775945 +Ga174 ns174 0 ns173 0 -0.000308288775945 +Ca175 ns175 0 1e-012 +Ca176 ns176 0 1e-012 +Ra175 ns175 0 4561.10737382 +Ra176 ns176 0 4561.10737382 +Ga175 ns175 0 ns176 0 0.000505848852909 +Ga176 ns176 0 ns175 0 -0.000505848852909 +Ca177 ns177 0 1e-012 +Ca178 ns178 0 1e-012 +Ra177 ns177 0 7262.24557758 +Ra178 ns178 0 7262.24557758 +Ga177 ns177 0 ns178 0 0.000645927620813 +Ga178 ns178 0 ns177 0 -0.000645927620813 +Ca179 ns179 0 1e-012 +Ca180 ns180 0 1e-012 +Ra179 ns179 0 6275.57561854 +Ra180 ns180 0 6275.57561854 +Ga179 ns179 0 ns180 0 0.000769982291801 +Ga180 ns180 0 ns179 0 -0.000769982291801 + +Gb1_1 ns1 0 ni1 0 4.86398207202e-008 +Gb2_1 ns2 0 ni1 0 1.07698915283e-007 +Gb3_1 ns3 0 ni1 0 5.56312442829e-007 +Gb5_1 ns5 0 ni1 0 1.02125893389e-006 +Gb6_1 ns6 0 ni1 0 4.66342075004e-006 +Gb7_1 ns7 0 ni1 0 1.34470467176e-005 +Gb8_1 ns8 0 ni1 0 1.59517716302e-005 +Gb10_1 ns10 0 ni1 0 1.92219721429e-005 +Gb12_1 ns12 0 ni1 0 2.822848091e-005 +Gb13_1 ns13 0 ni1 0 4.40397361143e-005 +Gb14_1 ns14 0 ni1 0 9.83477560844e-005 +Gb15_1 ns15 0 ni1 0 0.000213672716308 +Gb17_1 ns17 0 ni1 0 0.000283032106496 +Gb19_1 ns19 0 ni1 0 0.000416062603272 +Gb21_1 ns21 0 ni1 0 0.000467738639848 +Gb23_1 ns23 0 ni1 0 0.00064985715084 +Gb25_1 ns25 0 ni1 0 0.000600874019177 +Gb27_1 ns27 0 ni1 0 0.000675282093443 +Gb29_1 ns29 0 ni1 0 0.000802959366546 +Gb31_2 ns31 0 ni2 0 4.86398207202e-008 +Gb32_2 ns32 0 ni2 0 1.07698915283e-007 +Gb33_2 ns33 0 ni2 0 5.56312442829e-007 +Gb35_2 ns35 0 ni2 0 1.02125893389e-006 +Gb36_2 ns36 0 ni2 0 4.66342075004e-006 +Gb37_2 ns37 0 ni2 0 1.34470467176e-005 +Gb38_2 ns38 0 ni2 0 1.59517716302e-005 +Gb40_2 ns40 0 ni2 0 1.92219721429e-005 +Gb42_2 ns42 0 ni2 0 2.822848091e-005 +Gb43_2 ns43 0 ni2 0 4.40397361143e-005 +Gb44_2 ns44 0 ni2 0 9.83477560844e-005 +Gb45_2 ns45 0 ni2 0 0.000213672716308 +Gb47_2 ns47 0 ni2 0 0.000283032106496 +Gb49_2 ns49 0 ni2 0 0.000416062603272 +Gb51_2 ns51 0 ni2 0 0.000467738639848 +Gb53_2 ns53 0 ni2 0 0.00064985715084 +Gb55_2 ns55 0 ni2 0 0.000600874019177 +Gb57_2 ns57 0 ni2 0 0.000675282093443 +Gb59_2 ns59 0 ni2 0 0.000802959366546 +Gb61_3 ns61 0 ni3 0 4.86398207202e-008 +Gb62_3 ns62 0 ni3 0 1.07698915283e-007 +Gb63_3 ns63 0 ni3 0 5.56312442829e-007 +Gb65_3 ns65 0 ni3 0 1.02125893389e-006 +Gb66_3 ns66 0 ni3 0 4.66342075004e-006 +Gb67_3 ns67 0 ni3 0 1.34470467176e-005 +Gb68_3 ns68 0 ni3 0 1.59517716302e-005 +Gb70_3 ns70 0 ni3 0 1.92219721429e-005 +Gb72_3 ns72 0 ni3 0 2.822848091e-005 +Gb73_3 ns73 0 ni3 0 4.40397361143e-005 +Gb74_3 ns74 0 ni3 0 9.83477560844e-005 +Gb75_3 ns75 0 ni3 0 0.000213672716308 +Gb77_3 ns77 0 ni3 0 0.000283032106496 +Gb79_3 ns79 0 ni3 0 0.000416062603272 +Gb81_3 ns81 0 ni3 0 0.000467738639848 +Gb83_3 ns83 0 ni3 0 0.00064985715084 +Gb85_3 ns85 0 ni3 0 0.000600874019177 +Gb87_3 ns87 0 ni3 0 0.000675282093443 +Gb89_3 ns89 0 ni3 0 0.000802959366546 +Gb91_4 ns91 0 ni4 0 4.86398207202e-008 +Gb92_4 ns92 0 ni4 0 1.07698915283e-007 +Gb93_4 ns93 0 ni4 0 5.56312442829e-007 +Gb95_4 ns95 0 ni4 0 1.02125893389e-006 +Gb96_4 ns96 0 ni4 0 4.66342075004e-006 +Gb97_4 ns97 0 ni4 0 1.34470467176e-005 +Gb98_4 ns98 0 ni4 0 1.59517716302e-005 +Gb100_4 ns100 0 ni4 0 1.92219721429e-005 +Gb102_4 ns102 0 ni4 0 2.822848091e-005 +Gb103_4 ns103 0 ni4 0 4.40397361143e-005 +Gb104_4 ns104 0 ni4 0 9.83477560844e-005 +Gb105_4 ns105 0 ni4 0 0.000213672716308 +Gb107_4 ns107 0 ni4 0 0.000283032106496 +Gb109_4 ns109 0 ni4 0 0.000416062603272 +Gb111_4 ns111 0 ni4 0 0.000467738639848 +Gb113_4 ns113 0 ni4 0 0.00064985715084 +Gb115_4 ns115 0 ni4 0 0.000600874019177 +Gb117_4 ns117 0 ni4 0 0.000675282093443 +Gb119_4 ns119 0 ni4 0 0.000802959366546 +Gb121_5 ns121 0 ni5 0 4.86398207202e-008 +Gb122_5 ns122 0 ni5 0 1.07698915283e-007 +Gb123_5 ns123 0 ni5 0 5.56312442829e-007 +Gb125_5 ns125 0 ni5 0 1.02125893389e-006 +Gb126_5 ns126 0 ni5 0 4.66342075004e-006 +Gb127_5 ns127 0 ni5 0 1.34470467176e-005 +Gb128_5 ns128 0 ni5 0 1.59517716302e-005 +Gb130_5 ns130 0 ni5 0 1.92219721429e-005 +Gb132_5 ns132 0 ni5 0 2.822848091e-005 +Gb133_5 ns133 0 ni5 0 4.40397361143e-005 +Gb134_5 ns134 0 ni5 0 9.83477560844e-005 +Gb135_5 ns135 0 ni5 0 0.000213672716308 +Gb137_5 ns137 0 ni5 0 0.000283032106496 +Gb139_5 ns139 0 ni5 0 0.000416062603272 +Gb141_5 ns141 0 ni5 0 0.000467738639848 +Gb143_5 ns143 0 ni5 0 0.00064985715084 +Gb145_5 ns145 0 ni5 0 0.000600874019177 +Gb147_5 ns147 0 ni5 0 0.000675282093443 +Gb149_5 ns149 0 ni5 0 0.000802959366546 +Gb151_6 ns151 0 ni6 0 4.86398207202e-008 +Gb152_6 ns152 0 ni6 0 1.07698915283e-007 +Gb153_6 ns153 0 ni6 0 5.56312442829e-007 +Gb155_6 ns155 0 ni6 0 1.02125893389e-006 +Gb156_6 ns156 0 ni6 0 4.66342075004e-006 +Gb157_6 ns157 0 ni6 0 1.34470467176e-005 +Gb158_6 ns158 0 ni6 0 1.59517716302e-005 +Gb160_6 ns160 0 ni6 0 1.92219721429e-005 +Gb162_6 ns162 0 ni6 0 2.822848091e-005 +Gb163_6 ns163 0 ni6 0 4.40397361143e-005 +Gb164_6 ns164 0 ni6 0 9.83477560844e-005 +Gb165_6 ns165 0 ni6 0 0.000213672716308 +Gb167_6 ns167 0 ni6 0 0.000283032106496 +Gb169_6 ns169 0 ni6 0 0.000416062603272 +Gb171_6 ns171 0 ni6 0 0.000467738639848 +Gb173_6 ns173 0 ni6 0 0.00064985715084 +Gb175_6 ns175 0 ni6 0 0.000600874019177 +Gb177_6 ns177 0 ni6 0 0.000675282093443 +Gb179_6 ns179 0 ni6 0 0.000802959366546 + +Gc1_1 0 n2 ns1 0 0.00644433829459 +Gc1_2 0 n2 ns2 0 0.000102517006412 +Gc1_3 0 n2 ns3 0 -1.37090305858e-008 +Gc1_4 0 n2 ns4 0 -6.63775971995e-008 +Gc1_5 0 n2 ns5 0 2.06048713632e-005 +Gc1_6 0 n2 ns6 0 0.000142890641055 +Gc1_7 0 n2 ns7 0 0.000971003382124 +Gc1_8 0 n2 ns8 0 -5.32242584581e-007 +Gc1_9 0 n2 ns9 0 -1.02803732082e-006 +Gc1_10 0 n2 ns10 0 2.08355750463e-007 +Gc1_11 0 n2 ns11 0 -5.7406459825e-007 +Gc1_12 0 n2 ns12 0 0.00879821344575 +Gc1_13 0 n2 ns13 0 0.00465937446194 +Gc1_14 0 n2 ns14 0 0.00122481526907 +Gc1_15 0 n2 ns15 0 -3.49628182863e-008 +Gc1_16 0 n2 ns16 0 3.38449948934e-007 +Gc1_17 0 n2 ns17 0 -2.59193681487e-006 +Gc1_18 0 n2 ns18 0 -7.63652691887e-007 +Gc1_19 0 n2 ns19 0 2.25622014563e-005 +Gc1_20 0 n2 ns20 0 -1.33033591331e-005 +Gc1_21 0 n2 ns21 0 2.92622414955e-006 +Gc1_22 0 n2 ns22 0 -8.40598274962e-006 +Gc1_23 0 n2 ns23 0 -0.00477388223046 +Gc1_24 0 n2 ns24 0 -0.0310963177816 +Gc1_25 0 n2 ns25 0 0.0143027788747 +Gc1_26 0 n2 ns26 0 0.00518901503079 +Gc1_27 0 n2 ns27 0 -0.00152825849247 +Gc1_28 0 n2 ns28 0 -0.000586780197459 +Gc1_29 0 n2 ns29 0 -0.00450261618366 +Gc1_30 0 n2 ns30 0 -0.00516981910954 +Gc1_31 0 n2 ns31 0 0.00643300046992 +Gc1_32 0 n2 ns32 0 7.73786613411e-005 +Gc1_33 0 n2 ns33 0 1.05519333576e-007 +Gc1_34 0 n2 ns34 0 3.47263866431e-008 +Gc1_35 0 n2 ns35 0 -1.37984655131e-005 +Gc1_36 0 n2 ns36 0 -4.65900743596e-005 +Gc1_37 0 n2 ns37 0 -0.00047187909665 +Gc1_38 0 n2 ns38 0 -2.70114555685e-007 +Gc1_39 0 n2 ns39 0 5.20224241985e-007 +Gc1_40 0 n2 ns40 0 -1.82452573483e-007 +Gc1_41 0 n2 ns41 0 2.20659303852e-007 +Gc1_42 0 n2 ns42 0 -0.00392886037919 +Gc1_43 0 n2 ns43 0 -0.00295627777544 +Gc1_44 0 n2 ns44 0 -0.000574105632742 +Gc1_45 0 n2 ns45 0 2.14881535938e-007 +Gc1_46 0 n2 ns46 0 8.80046091032e-008 +Gc1_47 0 n2 ns47 0 -1.72800280799e-006 +Gc1_48 0 n2 ns48 0 3.23047257116e-006 +Gc1_49 0 n2 ns49 0 2.55822910795e-005 +Gc1_50 0 n2 ns50 0 -3.37080870547e-005 +Gc1_51 0 n2 ns51 0 1.72862907133e-006 +Gc1_52 0 n2 ns52 0 -9.06353448305e-006 +Gc1_53 0 n2 ns53 0 0.0044089957143 +Gc1_54 0 n2 ns54 0 0.00246941916261 +Gc1_55 0 n2 ns55 0 -0.00331901064683 +Gc1_56 0 n2 ns56 0 -0.00607703369916 +Gc1_57 0 n2 ns57 0 -0.000996413351084 +Gc1_58 0 n2 ns58 0 0.000595356080657 +Gc1_59 0 n2 ns59 0 -0.00184168281754 +Gc1_60 0 n2 ns60 0 0.00189637834116 +Gc1_61 0 n2 ns61 0 0.00643888648961 +Gc1_62 0 n2 ns62 0 8.01486595239e-005 +Gc1_63 0 n2 ns63 0 1.17001116435e-007 +Gc1_64 0 n2 ns64 0 3.57187790461e-008 +Gc1_65 0 n2 ns65 0 -1.38067500665e-005 +Gc1_66 0 n2 ns66 0 -3.05426661064e-005 +Gc1_67 0 n2 ns67 0 -0.000487721119468 +Gc1_68 0 n2 ns68 0 -3.02195812508e-007 +Gc1_69 0 n2 ns69 0 4.46193260885e-007 +Gc1_70 0 n2 ns70 0 -1.83089261313e-007 +Gc1_71 0 n2 ns71 0 2.00698262139e-007 +Gc1_72 0 n2 ns72 0 -0.0047752392194 +Gc1_73 0 n2 ns73 0 -0.00198210214027 +Gc1_74 0 n2 ns74 0 -0.000642053796183 +Gc1_75 0 n2 ns75 0 1.98851065846e-007 +Gc1_76 0 n2 ns76 0 9.72476055054e-008 +Gc1_77 0 n2 ns77 0 -2.01532068465e-006 +Gc1_78 0 n2 ns78 0 2.63754413845e-006 +Gc1_79 0 n2 ns79 0 3.01047048165e-005 +Gc1_80 0 n2 ns80 0 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-0.000421382088455 +Gc1_180 0 n2 ns180 0 -0.000803288316996 +Gd1_1 0 n2 ni1 0 -0.000426206471116 +Gd1_2 0 n2 ni2 0 -0.000930147995934 +Gd1_3 0 n2 ni3 0 -0.00154491011556 +Gd1_4 0 n2 ni4 0 -0.00378486529956 +Gd1_5 0 n2 ni5 0 -0.000330930314142 +Gd1_6 0 n2 ni6 0 -0.000275000615275 +Gc2_1 0 n4 ns1 0 0.00642961362704 +Gc2_2 0 n4 ns2 0 7.92132399691e-005 +Gc2_3 0 n4 ns3 0 1.15500014009e-007 +Gc2_4 0 n4 ns4 0 3.51371692372e-008 +Gc2_5 0 n4 ns5 0 -1.50562877994e-005 +Gc2_6 0 n4 ns6 0 -4.18861565853e-005 +Gc2_7 0 n4 ns7 0 -0.000494744328778 +Gc2_8 0 n4 ns8 0 -1.98085992022e-007 +Gc2_9 0 n4 ns9 0 3.0585339392e-007 +Gc2_10 0 n4 ns10 0 -5.66375642141e-008 +Gc2_11 0 n4 ns11 0 1.93663797376e-007 +Gc2_12 0 n4 ns12 0 -0.00387044083571 +Gc2_13 0 n4 ns13 0 -0.00301768073267 +Gc2_14 0 n4 ns14 0 -0.000519072617988 +Gc2_15 0 n4 ns15 0 1.14149814692e-007 +Gc2_16 0 n4 ns16 0 1.34074946868e-007 +Gc2_17 0 n4 ns17 0 -1.26747876767e-006 +Gc2_18 0 n4 ns18 0 2.98208781244e-006 +Gc2_19 0 n4 ns19 0 2.93574100682e-005 +Gc2_20 0 n4 ns20 0 -2.2365792741e-005 +Gc2_21 0 n4 ns21 0 2.85054837694e-006 +Gc2_22 0 n4 ns22 0 -7.6426935602e-006 +Gc2_23 0 n4 ns23 0 0.00568642218157 +Gc2_24 0 n4 ns24 0 0.0026256904739 +Gc2_25 0 n4 ns25 0 -0.00284334569665 +Gc2_26 0 n4 ns26 0 -0.00642999410201 +Gc2_27 0 n4 ns27 0 -0.000740642060281 +Gc2_28 0 n4 ns28 0 0.000368925681545 +Gc2_29 0 n4 ns29 0 -0.00223673367947 +Gc2_30 0 n4 ns30 0 0.00132949868258 +Gc2_31 0 n4 ns31 0 0.00643858220355 +Gc2_32 0 n4 ns32 0 9.46941012157e-005 +Gc2_33 0 n4 ns33 0 -2.68730751873e-008 +Gc2_34 0 n4 ns34 0 -4.61855292875e-008 +Gc2_35 0 n4 ns35 0 2.66187608655e-005 +Gc2_36 0 n4 ns36 0 0.000138916331847 +Gc2_37 0 n4 ns37 0 0.00110421707391 +Gc2_38 0 n4 ns38 0 -3.5986356556e-007 +Gc2_39 0 n4 ns39 0 -5.36855223675e-008 +Gc2_40 0 n4 ns40 0 -1.81265783837e-007 +Gc2_41 0 n4 ns41 0 -4.56576531522e-008 +Gc2_42 0 n4 ns42 0 0.00827943832246 +Gc2_43 0 n4 ns43 0 0.00543052644002 +Gc2_44 0 n4 ns44 0 0.00139177208519 +Gc2_45 0 n4 ns45 0 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ns97 0 0.000476737624903 +Gc2_98 0 n4 ns98 0 3.28825869314e-007 +Gc2_99 0 n4 ns99 0 -4.49507504108e-007 +Gc2_100 0 n4 ns100 0 1.40777253137e-007 +Gc2_101 0 n4 ns101 0 -1.4636635636e-007 +Gc2_102 0 n4 ns102 0 0.00390600171852 +Gc2_103 0 n4 ns103 0 0.00294218983124 +Gc2_104 0 n4 ns104 0 0.000569031379491 +Gc2_105 0 n4 ns105 0 3.32262888756e-007 +Gc2_106 0 n4 ns106 0 2.28703712296e-007 +Gc2_107 0 n4 ns107 0 1.24721870757e-006 +Gc2_108 0 n4 ns108 0 -1.8134414886e-006 +Gc2_109 0 n4 ns109 0 -9.1790535851e-008 +Gc2_110 0 n4 ns110 0 -3.88333627279e-006 +Gc2_111 0 n4 ns111 0 3.57485088463e-006 +Gc2_112 0 n4 ns112 0 -1.20487485411e-007 +Gc2_113 0 n4 ns113 0 -0.00645611517031 +Gc2_114 0 n4 ns114 0 -0.000894985174728 +Gc2_115 0 n4 ns115 0 0.00110066811839 +Gc2_116 0 n4 ns116 0 0.00508970816337 +Gc2_117 0 n4 ns117 0 0.000432320912342 +Gc2_118 0 n4 ns118 0 -0.000516599710178 +Gc2_119 0 n4 ns119 0 -0.000106702079132 +Gc2_120 0 n4 ns120 0 -0.000504101091183 +Gc2_121 0 n4 ns121 0 -0.0064589167153 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0 -0.0154891475598 +Gc2_147 0 n4 ns147 0 0.000413344106427 +Gc2_148 0 n4 ns148 0 0.000628343170278 +Gc2_149 0 n4 ns149 0 0.0019415488853 +Gc2_150 0 n4 ns150 0 0.00471254012417 +Gc2_151 0 n4 ns151 0 -0.00642665316681 +Gc2_152 0 n4 ns152 0 -8.37777014085e-005 +Gc2_153 0 n4 ns153 0 -1.17064932282e-007 +Gc2_154 0 n4 ns154 0 -3.92769000481e-008 +Gc2_155 0 n4 ns155 0 1.70208248841e-005 +Gc2_156 0 n4 ns156 0 4.36255964937e-005 +Gc2_157 0 n4 ns157 0 0.000558821608397 +Gc2_158 0 n4 ns158 0 2.42769830073e-007 +Gc2_159 0 n4 ns159 0 -4.97575431345e-007 +Gc2_160 0 n4 ns160 0 1.95637556948e-007 +Gc2_161 0 n4 ns161 0 -1.21810343103e-007 +Gc2_162 0 n4 ns162 0 0.00415621782201 +Gc2_163 0 n4 ns163 0 0.00256990970946 +Gc2_164 0 n4 ns164 0 0.000717979303714 +Gc2_165 0 n4 ns165 0 4.32835068499e-007 +Gc2_166 0 n4 ns166 0 3.36940985566e-007 +Gc2_167 0 n4 ns167 0 2.0207195868e-006 +Gc2_168 0 n4 ns168 0 -2.80606924153e-006 +Gc2_169 0 n4 ns169 0 -1.16023944692e-005 +Gc2_170 0 n4 ns170 0 -3.22364379897e-007 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0 n8 ns154 0 3.25066829148e-008 +Gc4_155 0 n8 ns155 0 -1.44321493403e-005 +Gc4_156 0 n8 ns156 0 -2.69139974439e-005 +Gc4_157 0 n8 ns157 0 -0.000508268771017 +Gc4_158 0 n8 ns158 0 -1.90914447609e-007 +Gc4_159 0 n8 ns159 0 1.06805469348e-007 +Gc4_160 0 n8 ns160 0 9.90530166182e-009 +Gc4_161 0 n8 ns161 0 2.29639460265e-008 +Gc4_162 0 n8 ns162 0 -0.00464360549148 +Gc4_163 0 n8 ns163 0 -0.0020697396288 +Gc4_164 0 n8 ns164 0 -0.000494332595516 +Gc4_165 0 n8 ns165 0 -3.02958100951e-008 +Gc4_166 0 n8 ns166 0 5.88203694222e-008 +Gc4_167 0 n8 ns167 0 -8.80289171308e-007 +Gc4_168 0 n8 ns168 0 3.17434625799e-006 +Gc4_169 0 n8 ns169 0 3.86904408357e-005 +Gc4_170 0 n8 ns170 0 -7.52541046794e-006 +Gc4_171 0 n8 ns171 0 5.65385978687e-006 +Gc4_172 0 n8 ns172 0 -2.9756113156e-006 +Gc4_173 0 n8 ns173 0 0.00240236771409 +Gc4_174 0 n8 ns174 0 0.00104866739223 +Gc4_175 0 n8 ns175 0 -0.00122428566996 +Gc4_176 0 n8 ns176 0 -0.00250238521781 +Gc4_177 0 n8 ns177 0 -0.000218891645571 +Gc4_178 0 n8 ns178 0 -3.19248552186e-005 +Gc4_179 0 n8 ns179 0 -0.00223805190661 +Gc4_180 0 n8 ns180 0 0.00120571381069 +Gd4_1 0 n8 ni1 0 -0.0012599905972 +Gd4_2 0 n8 ni2 0 -0.00233659478995 +Gd4_3 0 n8 ni3 0 -0.00128711825214 +Gd4_4 0 n8 ni4 0 -0.0013287408703 +Gd4_5 0 n8 ni5 0 -0.000140874783217 +Gd4_6 0 n8 ni6 0 -0.00043543225936 +Gc5_1 0 n10 ns1 0 -0.00644150506803 +Gc5_2 0 n10 ns2 0 -8.16249537193e-005 +Gc5_3 0 n10 ns3 0 -1.15109644133e-007 +Gc5_4 0 n10 ns4 0 -4.31078909521e-008 +Gc5_5 0 n10 ns5 0 1.62910233886e-005 +Gc5_6 0 n10 ns6 0 4.23760714419e-005 +Gc5_7 0 n10 ns7 0 0.000486745247143 +Gc5_8 0 n10 ns8 0 1.43718649825e-007 +Gc5_9 0 n10 ns9 0 -3.57000914595e-007 +Gc5_10 0 n10 ns10 0 1.60566043001e-008 +Gc5_11 0 n10 ns11 0 -1.20533235487e-007 +Gc5_12 0 n10 ns12 0 0.00386857599168 +Gc5_13 0 n10 ns13 0 0.00298699877166 +Gc5_14 0 n10 ns14 0 0.000481346781125 +Gc5_15 0 n10 ns15 0 6.55116070289e-007 +Gc5_16 0 n10 ns16 0 3.56197771303e-007 +Gc5_17 0 n10 ns17 0 8.54604107284e-007 +Gc5_18 0 n10 ns18 0 -3.00155678466e-006 +Gc5_19 0 n10 ns19 0 -3.96874915236e-006 +Gc5_20 0 n10 ns20 0 -8.13631851121e-006 +Gc5_21 0 n10 ns21 0 2.62668557786e-006 +Gc5_22 0 n10 ns22 0 -3.02545261411e-006 +Gc5_23 0 n10 ns23 0 -0.00782612743091 +Gc5_24 0 n10 ns24 0 -0.00132645993493 +Gc5_25 0 n10 ns25 0 -0.000467910889204 +Gc5_26 0 n10 ns26 0 0.00608013887779 +Gc5_27 0 n10 ns27 0 0.000328525396395 +Gc5_28 0 n10 ns28 0 -0.000299655261986 +Gc5_29 0 n10 ns29 0 0.00132536264173 +Gc5_30 0 n10 ns30 0 9.41547893692e-005 +Gc5_31 0 n10 ns31 0 -0.00647944208174 +Gc5_32 0 n10 ns32 0 -8.05076280804e-005 +Gc5_33 0 n10 ns33 0 2.36652637129e-007 +Gc5_34 0 n10 ns34 0 2.06624064046e-007 +Gc5_35 0 n10 ns35 0 -4.05927661769e-005 +Gc5_36 0 n10 ns36 0 -0.000112250052161 +Gc5_37 0 n10 ns37 0 -0.00117980340262 +Gc5_38 0 n10 ns38 0 -4.45930520971e-007 +Gc5_39 0 n10 ns39 0 1.28580225099e-006 +Gc5_40 0 n10 ns40 0 -2.81040591705e-007 +Gc5_41 0 n10 ns41 0 3.80541100748e-007 +Gc5_42 0 n10 ns42 0 -0.00807362191792 +Gc5_43 0 n10 ns43 0 -0.00558880522056 +Gc5_44 0 n10 ns44 0 -0.00132979504066 +Gc5_45 0 n10 ns45 0 1.19002572285e-007 +Gc5_46 0 n10 ns46 0 -5.60912366971e-008 +Gc5_47 0 n10 ns47 0 -6.09108941914e-006 +Gc5_48 0 n10 ns48 0 8.04853383575e-006 +Gc5_49 0 n10 ns49 0 6.00966681055e-005 +Gc5_50 0 n10 ns50 0 -8.34559105319e-005 +Gc5_51 0 n10 ns51 0 4.39298153528e-006 +Gc5_52 0 n10 ns52 0 -1.40617250265e-005 +Gc5_53 0 n10 ns53 0 0.000168504650178 +Gc5_54 0 n10 ns54 0 0.0250071644509 +Gc5_55 0 n10 ns55 0 -0.00911072646703 +Gc5_56 0 n10 ns56 0 -0.0169401037294 +Gc5_57 0 n10 ns57 0 0.00113512699067 +Gc5_58 0 n10 ns58 0 -0.000176829989371 +Gc5_59 0 n10 ns59 0 0.000515797727178 +Gc5_60 0 n10 ns60 0 0.00300078732111 +Gc5_61 0 n10 ns61 0 -0.00644354691544 +Gc5_62 0 n10 ns62 0 -8.27406752592e-005 +Gc5_63 0 n10 ns63 0 -9.63978235144e-008 +Gc5_64 0 n10 ns64 0 -2.37755260848e-008 +Gc5_65 0 n10 ns65 0 1.54858965704e-005 +Gc5_66 0 n10 ns66 0 4.03239658553e-005 +Gc5_67 0 n10 ns67 0 0.000590265040833 +Gc5_68 0 n10 ns68 0 2.3115224667e-007 +Gc5_69 0 n10 ns69 0 -6.32206270709e-008 +Gc5_70 0 n10 ns70 0 4.06435512049e-009 +Gc5_71 0 n10 ns71 0 -7.61715153596e-008 +Gc5_72 0 n10 ns72 0 0.00412806741061 +Gc5_73 0 n10 ns73 0 0.00259940805583 +Gc5_74 0 n10 ns74 0 0.00068953847415 +Gc5_75 0 n10 ns75 0 5.03111924197e-007 +Gc5_76 0 n10 ns76 0 1.53047150073e-007 +Gc5_77 0 n10 ns77 0 1.317305878e-006 +Gc5_78 0 n10 ns78 0 -7.4500515415e-007 +Gc5_79 0 n10 ns79 0 -1.08376439678e-005 +Gc5_80 0 n10 ns80 0 -1.61835362408e-005 +Gc5_81 0 n10 ns81 0 -1.29910663233e-006 +Gc5_82 0 n10 ns82 0 -2.50305983488e-006 +Gc5_83 0 n10 ns83 0 -0.00567547432306 +Gc5_84 0 n10 ns84 0 -0.00221490183921 +Gc5_85 0 n10 ns85 0 -0.000195376994284 +Gc5_86 0 n10 ns86 0 0.00384281341958 +Gc5_87 0 n10 ns87 0 -0.000672249434281 +Gc5_88 0 n10 ns88 0 -5.60974672644e-005 +Gc5_89 0 n10 ns89 0 0.00029935086681 +Gc5_90 0 n10 ns90 0 0.000624504487822 +Gc5_91 0 n10 ns91 0 0.00644189517664 +Gc5_92 0 n10 ns92 0 8.2009916029e-005 +Gc5_93 0 n10 ns93 0 9.80642371637e-008 +Gc5_94 0 n10 ns94 0 3.59971517762e-008 +Gc5_95 0 n10 ns95 0 -1.55814782877e-005 +Gc5_96 0 n10 ns96 0 -4.3657870301e-005 +Gc5_97 0 n10 ns97 0 -0.000476172774306 +Gc5_98 0 n10 ns98 0 -2.60637569517e-007 +Gc5_99 0 n10 ns99 0 4.41297649437e-007 +Gc5_100 0 n10 ns100 0 -1.15154266534e-007 +Gc5_101 0 n10 ns101 0 7.04808845341e-008 +Gc5_102 0 n10 ns102 0 -0.00386402295386 +Gc5_103 0 n10 ns103 0 -0.00296120651483 +Gc5_104 0 n10 ns104 0 -0.000481567595847 +Gc5_105 0 n10 ns105 0 9.63433997613e-008 +Gc5_106 0 n10 ns106 0 6.95661244048e-008 +Gc5_107 0 n10 ns107 0 -9.03765229386e-007 +Gc5_108 0 n10 ns108 0 4.00295031885e-006 +Gc5_109 0 n10 ns109 0 3.72284294893e-005 +Gc5_110 0 n10 ns110 0 -2.13613374551e-005 +Gc5_111 0 n10 ns111 0 4.55809904108e-006 +Gc5_112 0 n10 ns112 0 -7.82021088403e-006 +Gc5_113 0 n10 ns113 0 0.00424494931754 +Gc5_114 0 n10 ns114 0 0.000992134364607 +Gc5_115 0 n10 ns115 0 -0.00127730611568 +Gc5_116 0 n10 ns116 0 -0.00444795548041 +Gc5_117 0 n10 ns117 0 -0.00104023653894 +Gc5_118 0 n10 ns118 0 0.000188469839439 +Gc5_119 0 n10 ns119 0 -0.00257794267125 +Gc5_120 0 n10 ns120 0 0.00149366818979 +Gc5_121 0 n10 ns121 0 0.0064565230311 +Gc5_122 0 n10 ns122 0 0.000100235585805 +Gc5_123 0 n10 ns123 0 3.71249362385e-008 +Gc5_124 0 n10 ns124 0 -1.43538774245e-008 +Gc5_125 0 n10 ns125 0 2.19922653015e-005 +Gc5_126 0 n10 ns126 0 0.000152332981908 +Gc5_127 0 n10 ns127 0 0.00102552779717 +Gc5_128 0 n10 ns128 0 -5.10230087213e-007 +Gc5_129 0 n10 ns129 0 -2.25305604199e-007 +Gc5_130 0 n10 ns130 0 -3.30734924894e-007 +Gc5_131 0 n10 ns131 0 -2.16569396981e-007 +Gc5_132 0 n10 ns132 0 0.00841750773023 +Gc5_133 0 n10 ns133 0 0.00513242083242 +Gc5_134 0 n10 ns134 0 0.00143108079379 +Gc5_135 0 n10 ns135 0 2.29751053376e-007 +Gc5_136 0 n10 ns136 0 2.05078929669e-007 +Gc5_137 0 n10 ns137 0 -5.7526891213e-007 +Gc5_138 0 n10 ns138 0 4.99142368432e-006 +Gc5_139 0 n10 ns139 0 5.2485798669e-005 +Gc5_140 0 n10 ns140 0 1.82929563444e-005 +Gc5_141 0 n10 ns141 0 1.01520034022e-005 +Gc5_142 0 n10 ns142 0 -3.13656163689e-006 +Gc5_143 0 n10 ns143 0 -0.00180713717329 +Gc5_144 0 n10 ns144 0 -0.0400733890511 +Gc5_145 0 n10 ns145 0 0.00609876401088 +Gc5_146 0 n10 ns146 0 0.010354421214 +Gc5_147 0 n10 ns147 0 -0.00107883992069 +Gc5_148 0 n10 ns148 0 -0.000223903477345 +Gc5_149 0 n10 ns149 0 -0.000477459669148 +Gc5_150 0 n10 ns150 0 -0.0051005810207 +Gc5_151 0 n10 ns151 0 0.00644399653769 +Gc5_152 0 n10 ns152 0 8.39253285631e-005 +Gc5_153 0 n10 ns153 0 1.01152389313e-007 +Gc5_154 0 n10 ns154 0 3.4411477624e-008 +Gc5_155 0 n10 ns155 0 -1.64371547462e-005 +Gc5_156 0 n10 ns156 0 -3.91887249802e-005 +Gc5_157 0 n10 ns157 0 -0.000585044997945 +Gc5_158 0 n10 ns158 0 -2.10704996569e-007 +Gc5_159 0 n10 ns159 0 1.50240459634e-007 +Gc5_160 0 n10 ns160 0 -1.19523289025e-010 +Gc5_161 0 n10 ns161 0 2.99200907001e-008 +Gc5_162 0 n10 ns162 0 -0.00406727894241 +Gc5_163 0 n10 ns163 0 -0.00262232376727 +Gc5_164 0 n10 ns164 0 -0.000619528793234 +Gc5_165 0 n10 ns165 0 7.02942971569e-008 +Gc5_166 0 n10 ns166 0 1.30153625453e-007 +Gc5_167 0 n10 ns167 0 -1.39496080105e-006 +Gc5_168 0 n10 ns168 0 3.32728461001e-006 +Gc5_169 0 n10 ns169 0 4.03705305676e-005 +Gc5_170 0 n10 ns170 0 -2.42360128327e-005 +Gc5_171 0 n10 ns171 0 5.34324222238e-006 +Gc5_172 0 n10 ns172 0 -4.33433253124e-006 +Gc5_173 0 n10 ns173 0 0.00265811916762 +Gc5_174 0 n10 ns174 0 0.00144031858352 +Gc5_175 0 n10 ns175 0 -0.000997647990345 +Gc5_176 0 n10 ns176 0 -0.00254114090679 +Gc5_177 0 n10 ns177 0 -0.000320083089602 +Gc5_178 0 n10 ns178 0 -2.32877899025e-005 +Gc5_179 0 n10 ns179 0 -0.00218213751833 +Gc5_180 0 n10 ns180 0 0.00091776397778 +Gd5_1 0 n10 ni1 0 -0.00143627942189 +Gd5_2 0 n10 ni2 0 -0.00257892477982 +Gd5_3 0 n10 ni3 0 -0.00153225228582 +Gd5_4 0 n10 ni4 0 -0.00043702091483 +Gd5_5 0 n10 ni5 0 -0.000564843474931 +Gd5_6 0 n10 ni6 0 -0.000330666811899 +Gc6_1 0 n12 ns1 0 -0.00643366422636 +Gc6_2 0 n12 ns2 0 -8.33690910206e-005 +Gc6_3 0 n12 ns3 0 -1.15710169042e-007 +Gc6_4 0 n12 ns4 0 -4.53151692614e-008 +Gc6_5 0 n12 ns5 0 1.5590889782e-005 +Gc6_6 0 n12 ns6 0 2.83429341248e-005 +Gc6_7 0 n12 ns7 0 0.000495447033855 +Gc6_8 0 n12 ns8 0 1.5125152626e-007 +Gc6_9 0 n12 ns9 0 -3.19625748691e-007 +Gc6_10 0 n12 ns10 0 8.0741666824e-008 +Gc6_11 0 n12 ns11 0 -6.97243532046e-008 +Gc6_12 0 n12 ns12 0 0.00471667631727 +Gc6_13 0 n12 ns13 0 0.00202983098481 +Gc6_14 0 n12 ns14 0 0.000545858493256 +Gc6_15 0 n12 ns15 0 4.4750835212e-007 +Gc6_16 0 n12 ns16 0 2.4390713336e-007 +Gc6_17 0 n12 ns17 0 8.43361528079e-007 +Gc6_18 0 n12 ns18 0 -2.92150698332e-006 +Gc6_19 0 n12 ns19 0 -1.46234422865e-005 +Gc6_20 0 n12 ns20 0 -1.61113143675e-005 +Gc6_21 0 n12 ns21 0 -1.7144241219e-006 +Gc6_22 0 n12 ns22 0 -4.61739534783e-006 +Gc6_23 0 n12 ns23 0 -0.00465395114776 +Gc6_24 0 n12 ns24 0 -0.00128563066927 +Gc6_25 0 n12 ns25 0 0.000395868603059 +Gc6_26 0 n12 ns26 0 0.00331273875523 +Gc6_27 0 n12 ns27 0 -0.000520503783161 +Gc6_28 0 n12 ns28 0 -8.69900254796e-005 +Gc6_29 0 n12 ns29 0 0.000232911861449 +Gc6_30 0 n12 ns30 0 -2.29178711709e-006 +Gc6_31 0 n12 ns31 0 -0.0064267400491 +Gc6_32 0 n12 ns32 0 -8.34190852997e-005 +Gc6_33 0 n12 ns33 0 -1.18065700234e-007 +Gc6_34 0 n12 ns34 0 -4.07173024095e-008 +Gc6_35 0 n12 ns35 0 1.66673204471e-005 +Gc6_36 0 n12 ns36 0 4.22233136839e-005 +Gc6_37 0 n12 ns37 0 0.000569970692251 +Gc6_38 0 n12 ns38 0 1.51915350203e-007 +Gc6_39 0 n12 ns39 0 -2.87190803389e-007 +Gc6_40 0 n12 ns40 0 5.26736227714e-008 +Gc6_41 0 n12 ns41 0 -6.84830837048e-008 +Gc6_42 0 n12 ns42 0 0.00413808573649 +Gc6_43 0 n12 ns43 0 0.00259171890015 +Gc6_44 0 n12 ns44 0 0.000669857549708 +Gc6_45 0 n12 ns45 0 5.49737391804e-007 +Gc6_46 0 n12 ns46 0 2.9518250036e-007 +Gc6_47 0 n12 ns47 0 1.43639681101e-006 +Gc6_48 0 n12 ns48 0 -2.4498510561e-006 +Gc6_49 0 n12 ns49 0 -1.45593872226e-005 +Gc6_50 0 n12 ns50 0 -1.37205162002e-005 +Gc6_51 0 n12 ns51 0 -3.75255354047e-006 +Gc6_52 0 n12 ns52 0 -3.91237658873e-006 +Gc6_53 0 n12 ns53 0 -0.00480198344147 +Gc6_54 0 n12 ns54 0 -0.00184829072323 +Gc6_55 0 n12 ns55 0 -0.000665762755293 +Gc6_56 0 n12 ns56 0 0.0033756863399 +Gc6_57 0 n12 ns57 0 -0.000241589730159 +Gc6_58 0 n12 ns58 0 -9.47145626468e-005 +Gc6_59 0 n12 ns59 0 0.000400140802421 +Gc6_60 0 n12 ns60 0 0.000384857234978 +Gc6_61 0 n12 ns61 0 -0.00648076877762 +Gc6_62 0 n12 ns62 0 -8.13306075022e-005 +Gc6_63 0 n12 ns63 0 2.5522423275e-007 +Gc6_64 0 n12 ns64 0 2.03814803364e-007 +Gc6_65 0 n12 ns65 0 -4.11520732828e-005 +Gc6_66 0 n12 ns66 0 -9.89653690152e-005 +Gc6_67 0 n12 ns67 0 -0.00117898261397 +Gc6_68 0 n12 ns68 0 -6.15230679663e-007 +Gc6_69 0 n12 ns69 0 1.43233825937e-006 +Gc6_70 0 n12 ns70 0 -3.33778309417e-007 +Gc6_71 0 n12 ns71 0 3.86954615181e-007 +Gc6_72 0 n12 ns72 0 -0.00897236746322 +Gc6_73 0 n12 ns73 0 -0.0045896360371 +Gc6_74 0 n12 ns74 0 -0.00145590824272 +Gc6_75 0 n12 ns75 0 2.73797493979e-007 +Gc6_76 0 n12 ns76 0 -1.78033932936e-007 +Gc6_77 0 n12 ns77 0 -5.58821247981e-006 +Gc6_78 0 n12 ns78 0 7.80150801552e-006 +Gc6_79 0 n12 ns79 0 5.67223846651e-005 +Gc6_80 0 n12 ns80 0 -7.8275543757e-005 +Gc6_81 0 n12 ns81 0 4.46386411758e-006 +Gc6_82 0 n12 ns82 0 -1.11690086939e-005 +Gc6_83 0 n12 ns83 0 -0.0135976323544 +Gc6_84 0 n12 ns84 0 0.0268831132521 +Gc6_85 0 n12 ns85 0 -0.00725908165013 +Gc6_86 0 n12 ns86 0 -0.00677368725178 +Gc6_87 0 n12 ns87 0 0.000226310842268 +Gc6_88 0 n12 ns88 0 -0.000721116098225 +Gc6_89 0 n12 ns89 0 0.00512587224297 +Gc6_90 0 n12 ns90 0 0.0024444704243 +Gc6_91 0 n12 ns91 0 0.00643489111193 +Gc6_92 0 n12 ns92 0 8.32422849882e-005 +Gc6_93 0 n12 ns93 0 1.03237988993e-007 +Gc6_94 0 n12 ns94 0 3.68735857494e-008 +Gc6_95 0 n12 ns95 0 -1.49775175094e-005 +Gc6_96 0 n12 ns96 0 -2.8781932562e-005 +Gc6_97 0 n12 ns97 0 -0.000488373494396 +Gc6_98 0 n12 ns98 0 -2.67147062378e-007 +Gc6_99 0 n12 ns99 0 3.76796096647e-007 +Gc6_100 0 n12 ns100 0 -1.2195136275e-007 +Gc6_101 0 n12 ns101 0 6.15689920301e-008 +Gc6_102 0 n12 ns102 0 -0.00470160445212 +Gc6_103 0 n12 ns103 0 -0.00200590115352 +Gc6_104 0 n12 ns104 0 -0.000551743514068 +Gc6_105 0 n12 ns105 0 5.85874470658e-008 +Gc6_106 0 n12 ns106 0 2.61456767345e-008 +Gc6_107 0 n12 ns107 0 -1.50159679073e-006 +Gc6_108 0 n12 ns108 0 3.3354286047e-006 +Gc6_109 0 n12 ns109 0 3.39140185394e-005 +Gc6_110 0 n12 ns110 0 -2.10123619845e-005 +Gc6_111 0 n12 ns111 0 4.2254491241e-006 +Gc6_112 0 n12 ns112 0 -4.91917434805e-006 +Gc6_113 0 n12 ns113 0 0.000911078186822 +Gc6_114 0 n12 ns114 0 0.000859584845671 +Gc6_115 0 n12 ns115 0 -0.00177418515287 +Gc6_116 0 n12 ns116 0 -0.00207195568666 +Gc6_117 0 n12 ns117 0 -0.000506389891071 +Gc6_118 0 n12 ns118 0 0.000233429258454 +Gc6_119 0 n12 ns119 0 -0.00177574943948 +Gc6_120 0 n12 ns120 0 0.00185215357801 +Gc6_121 0 n12 ns121 0 0.00644493863885 +Gc6_122 0 n12 ns122 0 8.31260100008e-005 +Gc6_123 0 n12 ns123 0 9.56345706597e-008 +Gc6_124 0 n12 ns124 0 3.29502529593e-008 +Gc6_125 0 n12 ns125 0 -1.56738265387e-005 +Gc6_126 0 n12 ns126 0 -4.23839060039e-005 +Gc6_127 0 n12 ns127 0 -0.000565611695517 +Gc6_128 0 n12 ns128 0 -2.85873179044e-007 +Gc6_129 0 n12 ns129 0 3.15004018214e-007 +Gc6_130 0 n12 ns130 0 -1.42540355308e-007 +Gc6_131 0 n12 ns131 0 2.69488316699e-008 +Gc6_132 0 n12 ns132 0 -0.00412251640311 +Gc6_133 0 n12 ns133 0 -0.00256267374434 +Gc6_134 0 n12 ns134 0 -0.000669542871236 +Gc6_135 0 n12 ns135 0 1.42233373439e-007 +Gc6_136 0 n12 ns136 0 1.14840481132e-007 +Gc6_137 0 n12 ns137 0 -1.74815022705e-006 +Gc6_138 0 n12 ns138 0 3.28995718209e-006 +Gc6_139 0 n12 ns139 0 3.82178032737e-005 +Gc6_140 0 n12 ns140 0 -3.2192887302e-005 +Gc6_141 0 n12 ns141 0 5.53750180769e-006 +Gc6_142 0 n12 ns142 0 -6.59689290044e-006 +Gc6_143 0 n12 ns143 0 0.00144448198666 +Gc6_144 0 n12 ns144 0 0.00129036240244 +Gc6_145 0 n12 ns145 0 -0.00146224600456 +Gc6_146 0 n12 ns146 0 -0.00219938029521 +Gc6_147 0 n12 ns147 0 -0.000553763756158 +Gc6_148 0 n12 ns148 0 0.000211395759781 +Gc6_149 0 n12 ns149 0 -0.00179298750184 +Gc6_150 0 n12 ns150 0 0.0014355224448 +Gc6_151 0 n12 ns151 0 0.00644119568683 +Gc6_152 0 n12 ns152 0 0.000100247995957 +Gc6_153 0 n12 ns153 0 5.43910501021e-008 +Gc6_154 0 n12 ns154 0 -1.46595052624e-008 +Gc6_155 0 n12 ns155 0 2.264882984e-005 +Gc6_156 0 n12 ns156 0 0.00013663977476 +Gc6_157 0 n12 ns157 0 0.00104005428905 +Gc6_158 0 n12 ns158 0 -4.7417695698e-007 +Gc6_159 0 n12 ns159 0 -1.35461046225e-007 +Gc6_160 0 n12 ns160 0 -1.2507859357e-007 +Gc6_161 0 n12 ns161 0 -1.54050967451e-007 +Gc6_162 0 n12 ns162 0 0.00925658124662 +Gc6_163 0 n12 ns163 0 0.00419562578226 +Gc6_164 0 n12 ns164 0 0.00148842836129 +Gc6_165 0 n12 ns165 0 -4.50255744176e-008 +Gc6_166 0 n12 ns166 0 1.07182069992e-007 +Gc6_167 0 n12 ns167 0 -2.45317911965e-006 +Gc6_168 0 n12 ns168 0 5.3763741472e-006 +Gc6_169 0 n12 ns169 0 4.41181775932e-005 +Gc6_170 0 n12 ns170 0 -1.149654149e-005 +Gc6_171 0 n12 ns171 0 4.96370250581e-006 +Gc6_172 0 n12 ns172 0 -6.54488604774e-006 +Gc6_173 0 n12 ns173 0 0.00857631714081 +Gc6_174 0 n12 ns174 0 -0.0421902517637 +Gc6_175 0 n12 ns175 0 0.00344252548011 +Gc6_176 0 n12 ns176 0 0.00241882284622 +Gc6_177 0 n12 ns177 0 -0.000611560341278 +Gc6_178 0 n12 ns178 0 0.000432061238886 +Gc6_179 0 n12 ns179 0 -0.00408380918919 +Gc6_180 0 n12 ns180 0 -0.0038509659289 +Gd6_1 0 n12 ni1 0 -0.000974786396312 +Gd6_2 0 n12 ni2 0 -0.00124338508572 +Gd6_3 0 n12 ni3 0 -0.00434211957198 +Gd6_4 0 n12 ni4 0 -0.000975165726986 +Gd6_5 0 n12 ni5 0 -0.000768314845117 +Gd6_6 0 n12 ni6 0 0.00039422633377 +.ends + +.subckt 744837010290 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 27767456.1875 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 1086448.80926 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 173075.945043 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 61916.8668344 +Ca5 ns5 0 1e-012 +Ca6 ns6 0 1e-012 +Ra5 ns5 0 1935585.4744 +Ra6 ns6 0 1935585.4744 +Ga5 ns5 0 ns6 0 -1.96199209514e-005 +Ga6 ns6 0 ns5 0 1.96199209514e-005 +Ca7 ns7 0 1e-012 +Ra7 ns7 0 36848.5698895 +Ca8 ns8 0 1e-012 +Ra8 ns8 0 12951.7207087 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 239781.230563 +Ra10 ns10 0 239781.230563 +Ga9 ns9 0 ns10 0 -0.000218019798899 +Ga10 ns10 0 ns9 0 0.000218019798899 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 9945.51779645 +Ra12 ns12 0 9945.51779645 +Ga11 ns11 0 ns12 0 -0.000347360705454 +Ga12 ns12 0 ns11 0 0.000347360705454 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 9518.26104261 +Ra14 ns14 0 9518.26104261 +Ga13 ns13 0 ns14 0 -0.000354397753558 +Ga14 ns14 0 ns13 0 0.000354397753558 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 61721.5713546 +Ra16 ns16 0 61721.5713546 +Ga15 ns15 0 ns16 0 -0.000436657935278 +Ga16 ns16 0 ns15 0 0.000436657935278 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 8933.01063982 +Ra18 ns18 0 8933.01063982 +Ga17 ns17 0 ns18 0 -0.000431286572702 +Ga18 ns18 0 ns17 0 0.000431286572702 +Ca19 ns19 0 1e-012 +Ca20 ns20 0 1e-012 +Ra19 ns19 0 32653.2130611 +Ra20 ns20 0 32653.2130611 +Ga19 ns19 0 ns20 0 -0.000590362495724 +Ga20 ns20 0 ns19 0 0.000590362495724 +Ca21 ns21 0 1e-012 +Ca22 ns22 0 1e-012 +Ra21 ns21 0 45097.2737857 +Ra22 ns22 0 45097.2737857 +Ga21 ns21 0 ns22 0 -0.00059205988634 +Ga22 ns22 0 ns21 0 0.00059205988634 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 26295.7042864 +Ra24 ns24 0 26295.7042864 +Ga23 ns23 0 ns24 0 -0.000672047035468 +Ga24 ns24 0 ns23 0 0.000672047035468 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 1586.86800331 +Ra26 ns26 0 1586.86800331 +Ga25 ns25 0 ns26 0 -0.000349711883279 +Ga26 ns26 0 ns25 0 0.000349711883279 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 2968.12100965 +Ra28 ns28 0 2968.12100965 +Ga27 ns27 0 ns28 0 -0.000701329903676 +Ga28 ns28 0 ns27 0 0.000701329903676 +Ca29 ns29 0 1e-012 +Ra29 ns29 0 27767456.1875 +Ca30 ns30 0 1e-012 +Ra30 ns30 0 1086448.80926 +Ca31 ns31 0 1e-012 +Ra31 ns31 0 173075.945043 +Ca32 ns32 0 1e-012 +Ra32 ns32 0 61916.8668344 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 1935585.4744 +Ra34 ns34 0 1935585.4744 +Ga33 ns33 0 ns34 0 -1.96199209514e-005 +Ga34 ns34 0 ns33 0 1.96199209514e-005 +Ca35 ns35 0 1e-012 +Ra35 ns35 0 36848.5698895 +Ca36 ns36 0 1e-012 +Ra36 ns36 0 12951.7207087 +Ca37 ns37 0 1e-012 +Ca38 ns38 0 1e-012 +Ra37 ns37 0 239781.230563 +Ra38 ns38 0 239781.230563 +Ga37 ns37 0 ns38 0 -0.000218019798899 +Ga38 ns38 0 ns37 0 0.000218019798899 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 9945.51779645 +Ra40 ns40 0 9945.51779645 +Ga39 ns39 0 ns40 0 -0.000347360705454 +Ga40 ns40 0 ns39 0 0.000347360705454 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 9518.26104261 +Ra42 ns42 0 9518.26104261 +Ga41 ns41 0 ns42 0 -0.000354397753558 +Ga42 ns42 0 ns41 0 0.000354397753558 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 61721.5713546 +Ra44 ns44 0 61721.5713546 +Ga43 ns43 0 ns44 0 -0.000436657935278 +Ga44 ns44 0 ns43 0 0.000436657935278 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 8933.01063982 +Ra46 ns46 0 8933.01063982 +Ga45 ns45 0 ns46 0 -0.000431286572702 +Ga46 ns46 0 ns45 0 0.000431286572702 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 32653.2130611 +Ra48 ns48 0 32653.2130611 +Ga47 ns47 0 ns48 0 -0.000590362495724 +Ga48 ns48 0 ns47 0 0.000590362495724 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 45097.2737857 +Ra50 ns50 0 45097.2737857 +Ga49 ns49 0 ns50 0 -0.00059205988634 +Ga50 ns50 0 ns49 0 0.00059205988634 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 26295.7042864 +Ra52 ns52 0 26295.7042864 +Ga51 ns51 0 ns52 0 -0.000672047035468 +Ga52 ns52 0 ns51 0 0.000672047035468 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 1586.86800331 +Ra54 ns54 0 1586.86800331 +Ga53 ns53 0 ns54 0 -0.000349711883279 +Ga54 ns54 0 ns53 0 0.000349711883279 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 2968.12100965 +Ra56 ns56 0 2968.12100965 +Ga55 ns55 0 ns56 0 -0.000701329903676 +Ga56 ns56 0 ns55 0 0.000701329903676 +Ca57 ns57 0 1e-012 +Ra57 ns57 0 27767456.1875 +Ca58 ns58 0 1e-012 +Ra58 ns58 0 1086448.80926 +Ca59 ns59 0 1e-012 +Ra59 ns59 0 173075.945043 +Ca60 ns60 0 1e-012 +Ra60 ns60 0 61916.8668344 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 1935585.4744 +Ra62 ns62 0 1935585.4744 +Ga61 ns61 0 ns62 0 -1.96199209514e-005 +Ga62 ns62 0 ns61 0 1.96199209514e-005 +Ca63 ns63 0 1e-012 +Ra63 ns63 0 36848.5698895 +Ca64 ns64 0 1e-012 +Ra64 ns64 0 12951.7207087 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 239781.230563 +Ra66 ns66 0 239781.230563 +Ga65 ns65 0 ns66 0 -0.000218019798899 +Ga66 ns66 0 ns65 0 0.000218019798899 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 9945.51779645 +Ra68 ns68 0 9945.51779645 +Ga67 ns67 0 ns68 0 -0.000347360705454 +Ga68 ns68 0 ns67 0 0.000347360705454 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 9518.26104261 +Ra70 ns70 0 9518.26104261 +Ga69 ns69 0 ns70 0 -0.000354397753558 +Ga70 ns70 0 ns69 0 0.000354397753558 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 61721.5713546 +Ra72 ns72 0 61721.5713546 +Ga71 ns71 0 ns72 0 -0.000436657935278 +Ga72 ns72 0 ns71 0 0.000436657935278 +Ca73 ns73 0 1e-012 +Ca74 ns74 0 1e-012 +Ra73 ns73 0 8933.01063982 +Ra74 ns74 0 8933.01063982 +Ga73 ns73 0 ns74 0 -0.000431286572702 +Ga74 ns74 0 ns73 0 0.000431286572702 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 32653.2130611 +Ra76 ns76 0 32653.2130611 +Ga75 ns75 0 ns76 0 -0.000590362495724 +Ga76 ns76 0 ns75 0 0.000590362495724 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 45097.2737857 +Ra78 ns78 0 45097.2737857 +Ga77 ns77 0 ns78 0 -0.00059205988634 +Ga78 ns78 0 ns77 0 0.00059205988634 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 26295.7042864 +Ra80 ns80 0 26295.7042864 +Ga79 ns79 0 ns80 0 -0.000672047035468 +Ga80 ns80 0 ns79 0 0.000672047035468 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 1586.86800331 +Ra82 ns82 0 1586.86800331 +Ga81 ns81 0 ns82 0 -0.000349711883279 +Ga82 ns82 0 ns81 0 0.000349711883279 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 2968.12100965 +Ra84 ns84 0 2968.12100965 +Ga83 ns83 0 ns84 0 -0.000701329903676 +Ga84 ns84 0 ns83 0 0.000701329903676 +Ca85 ns85 0 1e-012 +Ra85 ns85 0 27767456.1875 +Ca86 ns86 0 1e-012 +Ra86 ns86 0 1086448.80926 +Ca87 ns87 0 1e-012 +Ra87 ns87 0 173075.945043 +Ca88 ns88 0 1e-012 +Ra88 ns88 0 61916.8668344 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 1935585.4744 +Ra90 ns90 0 1935585.4744 +Ga89 ns89 0 ns90 0 -1.96199209514e-005 +Ga90 ns90 0 ns89 0 1.96199209514e-005 +Ca91 ns91 0 1e-012 +Ra91 ns91 0 36848.5698895 +Ca92 ns92 0 1e-012 +Ra92 ns92 0 12951.7207087 +Ca93 ns93 0 1e-012 +Ca94 ns94 0 1e-012 +Ra93 ns93 0 239781.230563 +Ra94 ns94 0 239781.230563 +Ga93 ns93 0 ns94 0 -0.000218019798899 +Ga94 ns94 0 ns93 0 0.000218019798899 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 9945.51779645 +Ra96 ns96 0 9945.51779645 +Ga95 ns95 0 ns96 0 -0.000347360705454 +Ga96 ns96 0 ns95 0 0.000347360705454 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 9518.26104261 +Ra98 ns98 0 9518.26104261 +Ga97 ns97 0 ns98 0 -0.000354397753558 +Ga98 ns98 0 ns97 0 0.000354397753558 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 61721.5713546 +Ra100 ns100 0 61721.5713546 +Ga99 ns99 0 ns100 0 -0.000436657935278 +Ga100 ns100 0 ns99 0 0.000436657935278 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 8933.01063982 +Ra102 ns102 0 8933.01063982 +Ga101 ns101 0 ns102 0 -0.000431286572702 +Ga102 ns102 0 ns101 0 0.000431286572702 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 32653.2130611 +Ra104 ns104 0 32653.2130611 +Ga103 ns103 0 ns104 0 -0.000590362495724 +Ga104 ns104 0 ns103 0 0.000590362495724 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 45097.2737857 +Ra106 ns106 0 45097.2737857 +Ga105 ns105 0 ns106 0 -0.00059205988634 +Ga106 ns106 0 ns105 0 0.00059205988634 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 26295.7042864 +Ra108 ns108 0 26295.7042864 +Ga107 ns107 0 ns108 0 -0.000672047035468 +Ga108 ns108 0 ns107 0 0.000672047035468 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 1586.86800331 +Ra110 ns110 0 1586.86800331 +Ga109 ns109 0 ns110 0 -0.000349711883279 +Ga110 ns110 0 ns109 0 0.000349711883279 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 2968.12100965 +Ra112 ns112 0 2968.12100965 +Ga111 ns111 0 ns112 0 -0.000701329903676 +Ga112 ns112 0 ns111 0 0.000701329903676 +Ca113 ns113 0 1e-012 +Ra113 ns113 0 27767456.1875 +Ca114 ns114 0 1e-012 +Ra114 ns114 0 1086448.80926 +Ca115 ns115 0 1e-012 +Ra115 ns115 0 173075.945043 +Ca116 ns116 0 1e-012 +Ra116 ns116 0 61916.8668344 +Ca117 ns117 0 1e-012 +Ca118 ns118 0 1e-012 +Ra117 ns117 0 1935585.4744 +Ra118 ns118 0 1935585.4744 +Ga117 ns117 0 ns118 0 -1.96199209514e-005 +Ga118 ns118 0 ns117 0 1.96199209514e-005 +Ca119 ns119 0 1e-012 +Ra119 ns119 0 36848.5698895 +Ca120 ns120 0 1e-012 +Ra120 ns120 0 12951.7207087 +Ca121 ns121 0 1e-012 +Ca122 ns122 0 1e-012 +Ra121 ns121 0 239781.230563 +Ra122 ns122 0 239781.230563 +Ga121 ns121 0 ns122 0 -0.000218019798899 +Ga122 ns122 0 ns121 0 0.000218019798899 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 9945.51779645 +Ra124 ns124 0 9945.51779645 +Ga123 ns123 0 ns124 0 -0.000347360705454 +Ga124 ns124 0 ns123 0 0.000347360705454 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 9518.26104261 +Ra126 ns126 0 9518.26104261 +Ga125 ns125 0 ns126 0 -0.000354397753558 +Ga126 ns126 0 ns125 0 0.000354397753558 +Ca127 ns127 0 1e-012 +Ca128 ns128 0 1e-012 +Ra127 ns127 0 61721.5713546 +Ra128 ns128 0 61721.5713546 +Ga127 ns127 0 ns128 0 -0.000436657935278 +Ga128 ns128 0 ns127 0 0.000436657935278 +Ca129 ns129 0 1e-012 +Ca130 ns130 0 1e-012 +Ra129 ns129 0 8933.01063982 +Ra130 ns130 0 8933.01063982 +Ga129 ns129 0 ns130 0 -0.000431286572702 +Ga130 ns130 0 ns129 0 0.000431286572702 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 32653.2130611 +Ra132 ns132 0 32653.2130611 +Ga131 ns131 0 ns132 0 -0.000590362495724 +Ga132 ns132 0 ns131 0 0.000590362495724 +Ca133 ns133 0 1e-012 +Ca134 ns134 0 1e-012 +Ra133 ns133 0 45097.2737857 +Ra134 ns134 0 45097.2737857 +Ga133 ns133 0 ns134 0 -0.00059205988634 +Ga134 ns134 0 ns133 0 0.00059205988634 +Ca135 ns135 0 1e-012 +Ca136 ns136 0 1e-012 +Ra135 ns135 0 26295.7042864 +Ra136 ns136 0 26295.7042864 +Ga135 ns135 0 ns136 0 -0.000672047035468 +Ga136 ns136 0 ns135 0 0.000672047035468 +Ca137 ns137 0 1e-012 +Ca138 ns138 0 1e-012 +Ra137 ns137 0 1586.86800331 +Ra138 ns138 0 1586.86800331 +Ga137 ns137 0 ns138 0 -0.000349711883279 +Ga138 ns138 0 ns137 0 0.000349711883279 +Ca139 ns139 0 1e-012 +Ca140 ns140 0 1e-012 +Ra139 ns139 0 2968.12100965 +Ra140 ns140 0 2968.12100965 +Ga139 ns139 0 ns140 0 -0.000701329903676 +Ga140 ns140 0 ns139 0 0.000701329903676 +Ca141 ns141 0 1e-012 +Ra141 ns141 0 27767456.1875 +Ca142 ns142 0 1e-012 +Ra142 ns142 0 1086448.80926 +Ca143 ns143 0 1e-012 +Ra143 ns143 0 173075.945043 +Ca144 ns144 0 1e-012 +Ra144 ns144 0 61916.8668344 +Ca145 ns145 0 1e-012 +Ca146 ns146 0 1e-012 +Ra145 ns145 0 1935585.4744 +Ra146 ns146 0 1935585.4744 +Ga145 ns145 0 ns146 0 -1.96199209514e-005 +Ga146 ns146 0 ns145 0 1.96199209514e-005 +Ca147 ns147 0 1e-012 +Ra147 ns147 0 36848.5698895 +Ca148 ns148 0 1e-012 +Ra148 ns148 0 12951.7207087 +Ca149 ns149 0 1e-012 +Ca150 ns150 0 1e-012 +Ra149 ns149 0 239781.230563 +Ra150 ns150 0 239781.230563 +Ga149 ns149 0 ns150 0 -0.000218019798899 +Ga150 ns150 0 ns149 0 0.000218019798899 +Ca151 ns151 0 1e-012 +Ca152 ns152 0 1e-012 +Ra151 ns151 0 9945.51779645 +Ra152 ns152 0 9945.51779645 +Ga151 ns151 0 ns152 0 -0.000347360705454 +Ga152 ns152 0 ns151 0 0.000347360705454 +Ca153 ns153 0 1e-012 +Ca154 ns154 0 1e-012 +Ra153 ns153 0 9518.26104261 +Ra154 ns154 0 9518.26104261 +Ga153 ns153 0 ns154 0 -0.000354397753558 +Ga154 ns154 0 ns153 0 0.000354397753558 +Ca155 ns155 0 1e-012 +Ca156 ns156 0 1e-012 +Ra155 ns155 0 61721.5713546 +Ra156 ns156 0 61721.5713546 +Ga155 ns155 0 ns156 0 -0.000436657935278 +Ga156 ns156 0 ns155 0 0.000436657935278 +Ca157 ns157 0 1e-012 +Ca158 ns158 0 1e-012 +Ra157 ns157 0 8933.01063982 +Ra158 ns158 0 8933.01063982 +Ga157 ns157 0 ns158 0 -0.000431286572702 +Ga158 ns158 0 ns157 0 0.000431286572702 +Ca159 ns159 0 1e-012 +Ca160 ns160 0 1e-012 +Ra159 ns159 0 32653.2130611 +Ra160 ns160 0 32653.2130611 +Ga159 ns159 0 ns160 0 -0.000590362495724 +Ga160 ns160 0 ns159 0 0.000590362495724 +Ca161 ns161 0 1e-012 +Ca162 ns162 0 1e-012 +Ra161 ns161 0 45097.2737857 +Ra162 ns162 0 45097.2737857 +Ga161 ns161 0 ns162 0 -0.00059205988634 +Ga162 ns162 0 ns161 0 0.00059205988634 +Ca163 ns163 0 1e-012 +Ca164 ns164 0 1e-012 +Ra163 ns163 0 26295.7042864 +Ra164 ns164 0 26295.7042864 +Ga163 ns163 0 ns164 0 -0.000672047035468 +Ga164 ns164 0 ns163 0 0.000672047035468 +Ca165 ns165 0 1e-012 +Ca166 ns166 0 1e-012 +Ra165 ns165 0 1586.86800331 +Ra166 ns166 0 1586.86800331 +Ga165 ns165 0 ns166 0 -0.000349711883279 +Ga166 ns166 0 ns165 0 0.000349711883279 +Ca167 ns167 0 1e-012 +Ca168 ns168 0 1e-012 +Ra167 ns167 0 2968.12100965 +Ra168 ns168 0 2968.12100965 +Ga167 ns167 0 ns168 0 -0.000701329903676 +Ga168 ns168 0 ns167 0 0.000701329903676 + +Gb1_1 ns1 0 ni1 0 3.60133817533e-008 +Gb2_1 ns2 0 ni1 0 9.20429928661e-007 +Gb3_1 ns3 0 ni1 0 5.7778104274e-006 +Gb4_1 ns4 0 ni1 0 1.61506880294e-005 +Gb5_1 ns5 0 ni1 0 1.9633525309e-005 +Gb7_1 ns7 0 ni1 0 2.71380952639e-005 +Gb8_1 ns8 0 ni1 0 7.72098180998e-005 +Gb9_1 ns9 0 ni1 0 0.000218099575163 +Gb11_1 ns11 0 ni1 0 0.000376465498411 +Gb13_1 ns13 0 ni1 0 0.000385543146679 +Gb15_1 ns15 0 ni1 0 0.00043725908783 +Gb17_1 ns17 0 ni1 0 0.000460342742185 +Gb19_1 ns19 0 ni1 0 0.000591951149999 +Gb21_1 ns21 0 ni1 0 0.00059289037515 +Gb23_1 ns23 0 ni1 0 0.000674198978232 +Gb25_1 ns25 0 ni1 0 0.000824243556395 +Gb27_1 ns27 0 ni1 0 0.000863180549583 +Gb29_2 ns29 0 ni2 0 3.60133817533e-008 +Gb30_2 ns30 0 ni2 0 9.20429928661e-007 +Gb31_2 ns31 0 ni2 0 5.7778104274e-006 +Gb32_2 ns32 0 ni2 0 1.61506880294e-005 +Gb33_2 ns33 0 ni2 0 1.9633525309e-005 +Gb35_2 ns35 0 ni2 0 2.71380952639e-005 +Gb36_2 ns36 0 ni2 0 7.72098180998e-005 +Gb37_2 ns37 0 ni2 0 0.000218099575163 +Gb39_2 ns39 0 ni2 0 0.000376465498411 +Gb41_2 ns41 0 ni2 0 0.000385543146679 +Gb43_2 ns43 0 ni2 0 0.00043725908783 +Gb45_2 ns45 0 ni2 0 0.000460342742185 +Gb47_2 ns47 0 ni2 0 0.000591951149999 +Gb49_2 ns49 0 ni2 0 0.00059289037515 +Gb51_2 ns51 0 ni2 0 0.000674198978232 +Gb53_2 ns53 0 ni2 0 0.000824243556395 +Gb55_2 ns55 0 ni2 0 0.000863180549583 +Gb57_3 ns57 0 ni3 0 3.60133817533e-008 +Gb58_3 ns58 0 ni3 0 9.20429928661e-007 +Gb59_3 ns59 0 ni3 0 5.7778104274e-006 +Gb60_3 ns60 0 ni3 0 1.61506880294e-005 +Gb61_3 ns61 0 ni3 0 1.9633525309e-005 +Gb63_3 ns63 0 ni3 0 2.71380952639e-005 +Gb64_3 ns64 0 ni3 0 7.72098180998e-005 +Gb65_3 ns65 0 ni3 0 0.000218099575163 +Gb67_3 ns67 0 ni3 0 0.000376465498411 +Gb69_3 ns69 0 ni3 0 0.000385543146679 +Gb71_3 ns71 0 ni3 0 0.00043725908783 +Gb73_3 ns73 0 ni3 0 0.000460342742185 +Gb75_3 ns75 0 ni3 0 0.000591951149999 +Gb77_3 ns77 0 ni3 0 0.00059289037515 +Gb79_3 ns79 0 ni3 0 0.000674198978232 +Gb81_3 ns81 0 ni3 0 0.000824243556395 +Gb83_3 ns83 0 ni3 0 0.000863180549583 +Gb85_4 ns85 0 ni4 0 3.60133817533e-008 +Gb86_4 ns86 0 ni4 0 9.20429928661e-007 +Gb87_4 ns87 0 ni4 0 5.7778104274e-006 +Gb88_4 ns88 0 ni4 0 1.61506880294e-005 +Gb89_4 ns89 0 ni4 0 1.9633525309e-005 +Gb91_4 ns91 0 ni4 0 2.71380952639e-005 +Gb92_4 ns92 0 ni4 0 7.72098180998e-005 +Gb93_4 ns93 0 ni4 0 0.000218099575163 +Gb95_4 ns95 0 ni4 0 0.000376465498411 +Gb97_4 ns97 0 ni4 0 0.000385543146679 +Gb99_4 ns99 0 ni4 0 0.00043725908783 +Gb101_4 ns101 0 ni4 0 0.000460342742185 +Gb103_4 ns103 0 ni4 0 0.000591951149999 +Gb105_4 ns105 0 ni4 0 0.00059289037515 +Gb107_4 ns107 0 ni4 0 0.000674198978232 +Gb109_4 ns109 0 ni4 0 0.000824243556395 +Gb111_4 ns111 0 ni4 0 0.000863180549583 +Gb113_5 ns113 0 ni5 0 3.60133817533e-008 +Gb114_5 ns114 0 ni5 0 9.20429928661e-007 +Gb115_5 ns115 0 ni5 0 5.7778104274e-006 +Gb116_5 ns116 0 ni5 0 1.61506880294e-005 +Gb117_5 ns117 0 ni5 0 1.9633525309e-005 +Gb119_5 ns119 0 ni5 0 2.71380952639e-005 +Gb120_5 ns120 0 ni5 0 7.72098180998e-005 +Gb121_5 ns121 0 ni5 0 0.000218099575163 +Gb123_5 ns123 0 ni5 0 0.000376465498411 +Gb125_5 ns125 0 ni5 0 0.000385543146679 +Gb127_5 ns127 0 ni5 0 0.00043725908783 +Gb129_5 ns129 0 ni5 0 0.000460342742185 +Gb131_5 ns131 0 ni5 0 0.000591951149999 +Gb133_5 ns133 0 ni5 0 0.00059289037515 +Gb135_5 ns135 0 ni5 0 0.000674198978232 +Gb137_5 ns137 0 ni5 0 0.000824243556395 +Gb139_5 ns139 0 ni5 0 0.000863180549583 +Gb141_6 ns141 0 ni6 0 3.60133817533e-008 +Gb142_6 ns142 0 ni6 0 9.20429928661e-007 +Gb143_6 ns143 0 ni6 0 5.7778104274e-006 +Gb144_6 ns144 0 ni6 0 1.61506880294e-005 +Gb145_6 ns145 0 ni6 0 1.9633525309e-005 +Gb147_6 ns147 0 ni6 0 2.71380952639e-005 +Gb148_6 ns148 0 ni6 0 7.72098180998e-005 +Gb149_6 ns149 0 ni6 0 0.000218099575163 +Gb151_6 ns151 0 ni6 0 0.000376465498411 +Gb153_6 ns153 0 ni6 0 0.000385543146679 +Gb155_6 ns155 0 ni6 0 0.00043725908783 +Gb157_6 ns157 0 ni6 0 0.000460342742185 +Gb159_6 ns159 0 ni6 0 0.000591951149999 +Gb161_6 ns161 0 ni6 0 0.00059289037515 +Gb163_6 ns163 0 ni6 0 0.000674198978232 +Gb165_6 ns165 0 ni6 0 0.000824243556395 +Gb167_6 ns167 0 ni6 0 0.000863180549583 + +Gc1_1 0 n2 ns1 0 0.00662563257644 +Gc1_2 0 n2 ns2 0 4.79087325067e-005 +Gc1_3 0 n2 ns3 0 0.000475060033414 +Gc1_4 0 n2 ns4 0 0.00687581563423 +Gc1_5 0 n2 ns5 0 -1.09472765444e-006 +Gc1_6 0 n2 ns6 0 1.20702707148e-006 +Gc1_7 0 n2 ns7 0 0.00715383465198 +Gc1_8 0 n2 ns8 0 0.00104346062703 +Gc1_9 0 n2 ns9 0 1.41358196565e-006 +Gc1_10 0 n2 ns10 0 -1.8001621226e-006 +Gc1_11 0 n2 ns11 0 0.00262506132852 +Gc1_12 0 n2 ns12 0 0.00211567009901 +Gc1_13 0 n2 ns13 0 0.00276128387783 +Gc1_14 0 n2 ns14 0 -0.0142172656972 +Gc1_15 0 n2 ns15 0 4.53584674811e-006 +Gc1_16 0 n2 ns16 0 2.87356066562e-007 +Gc1_17 0 n2 ns17 0 -0.00457461028324 +Gc1_18 0 n2 ns18 0 -0.00048433123017 +Gc1_19 0 n2 ns19 0 0.000194457948089 +Gc1_20 0 n2 ns20 0 -0.000356446144041 +Gc1_21 0 n2 ns21 0 -0.000765536122315 +Gc1_22 0 n2 ns22 0 -0.000316182981989 +Gc1_23 0 n2 ns23 0 -0.000625167330878 +Gc1_24 0 n2 ns24 0 -0.00117457871406 +Gc1_25 0 n2 ns25 0 -0.00130238326825 +Gc1_26 0 n2 ns26 0 0.0886602459425 +Gc1_27 0 n2 ns27 0 0.0129189667058 +Gc1_28 0 n2 ns28 0 -0.00981734785291 +Gc1_29 0 n2 ns29 0 0.00654624815359 +Gc1_30 0 n2 ns30 0 -2.01805530533e-005 +Gc1_31 0 n2 ns31 0 -0.00024792369374 +Gc1_32 0 n2 ns32 0 -0.00321040692931 +Gc1_33 0 n2 ns33 0 -7.32733146798e-008 +Gc1_34 0 n2 ns34 0 -1.89334552136e-007 +Gc1_35 0 n2 ns35 0 -0.00371614987991 +Gc1_36 0 n2 ns36 0 -0.000767630556959 +Gc1_37 0 n2 ns37 0 -1.6346513672e-007 +Gc1_38 0 n2 ns38 0 4.55819779545e-008 +Gc1_39 0 n2 ns39 0 -0.00325064108935 +Gc1_40 0 n2 ns40 0 -0.00166632175336 +Gc1_41 0 n2 ns41 0 0.00178985804345 +Gc1_42 0 n2 ns42 0 0.00832714176291 +Gc1_43 0 n2 ns43 0 -6.19033558167e-006 +Gc1_44 0 n2 ns44 0 -4.33520712924e-006 +Gc1_45 0 n2 ns45 0 -0.00305515216285 +Gc1_46 0 n2 ns46 0 -0.00555270168309 +Gc1_47 0 n2 ns47 0 1.21625547326e-006 +Gc1_48 0 n2 ns48 0 -0.000596852229589 +Gc1_49 0 n2 ns49 0 -4.59150495671e-005 +Gc1_50 0 n2 ns50 0 0.000392017187774 +Gc1_51 0 n2 ns51 0 -0.000119950396663 +Gc1_52 0 n2 ns52 0 -1.97369487544e-005 +Gc1_53 0 n2 ns53 0 -0.00554129091441 +Gc1_54 0 n2 ns54 0 -0.00475316979953 +Gc1_55 0 n2 ns55 0 0.000306001575317 +Gc1_56 0 n2 ns56 0 -0.00360892318738 +Gc1_57 0 n2 ns57 0 0.00654619445302 +Gc1_58 0 n2 ns58 0 -2.0259990545e-005 +Gc1_59 0 n2 ns59 0 -0.000204319252092 +Gc1_60 0 n2 ns60 0 -0.00371812804872 +Gc1_61 0 n2 ns61 0 -2.14554618315e-007 +Gc1_62 0 n2 ns62 0 3.1954147348e-008 +Gc1_63 0 n2 ns63 0 -0.00323259468737 +Gc1_64 0 n2 ns64 0 -0.000546861857034 +Gc1_65 0 n2 ns65 0 5.91515935029e-007 +Gc1_66 0 n2 ns66 0 -2.31278531133e-007 +Gc1_67 0 n2 ns67 0 -0.00284631316218 +Gc1_68 0 n2 ns68 0 0.00421816544271 +Gc1_69 0 n2 ns69 0 0.000547739944828 +Gc1_70 0 n2 ns70 0 0.000574800681115 +Gc1_71 0 n2 ns71 0 -3.69699161734e-007 +Gc1_72 0 n2 ns72 0 9.98060874923e-007 +Gc1_73 0 n2 ns73 0 -0.00152511071262 +Gc1_74 0 n2 ns74 0 -0.00410714193345 +Gc1_75 0 n2 ns75 0 9.27847229208e-005 +Gc1_76 0 n2 ns76 0 -4.15022899215e-005 +Gc1_77 0 n2 ns77 0 -4.41243592141e-005 +Gc1_78 0 n2 ns78 0 -3.87724467651e-005 +Gc1_79 0 n2 ns79 0 4.13511837033e-005 +Gc1_80 0 n2 ns80 0 -3.89219713563e-005 +Gc1_81 0 n2 ns81 0 0.00286791926594 +Gc1_82 0 n2 ns82 0 0.00253459946083 +Gc1_83 0 n2 ns83 0 -0.00370795957419 +Gc1_84 0 n2 ns84 0 -0.00170439024768 +Gc1_85 0 n2 ns85 0 -0.00658604810592 +Gc1_86 0 n2 ns86 0 -4.51751743401e-005 +Gc1_87 0 n2 ns87 0 -0.000491659759745 +Gc1_88 0 n2 ns88 0 -0.00676816299163 +Gc1_89 0 n2 ns89 0 -1.9271656292e-007 +Gc1_90 0 n2 ns90 0 -5.27587810747e-007 +Gc1_91 0 n2 ns91 0 -0.00726012057847 +Gc1_92 0 n2 ns92 0 -0.00101488983244 +Gc1_93 0 n2 ns93 0 -4.44151039838e-007 +Gc1_94 0 n2 ns94 0 1.20710897413e-006 +Gc1_95 0 n2 ns95 0 -0.00156732547182 +Gc1_96 0 n2 ns96 0 -0.00222855166513 +Gc1_97 0 n2 ns97 0 -0.00230530129544 +Gc1_98 0 n2 ns98 0 0.0125825206342 +Gc1_99 0 n2 ns99 0 -3.4242813691e-006 +Gc1_100 0 n2 ns100 0 -5.83140775909e-007 +Gc1_101 0 n2 ns101 0 0.00408467344645 +Gc1_102 0 n2 ns102 0 0.000779724519283 +Gc1_103 0 n2 ns103 0 -0.000111251561902 +Gc1_104 0 n2 ns104 0 0.000318048861851 +Gc1_105 0 n2 ns105 0 0.000622521018806 +Gc1_106 0 n2 ns106 0 0.000184369544138 +Gc1_107 0 n2 ns107 0 0.000637326482976 +Gc1_108 0 n2 ns108 0 0.00111670950764 +Gc1_109 0 n2 ns109 0 -0.00634504203262 +Gc1_110 0 n2 ns110 0 -0.0666055130133 +Gc1_111 0 n2 ns111 0 -0.00590289184439 +Gc1_112 0 n2 ns112 0 0.0163551641319 +Gc1_113 0 n2 ns113 0 -0.00653039164037 +Gc1_114 0 n2 ns114 0 1.97243434316e-005 +Gc1_115 0 n2 ns115 0 0.000250738266922 +Gc1_116 0 n2 ns116 0 0.00317024263756 +Gc1_117 0 n2 ns117 0 1.75241775876e-007 +Gc1_118 0 n2 ns118 0 3.13519701047e-007 +Gc1_119 0 n2 ns119 0 0.00372328874109 +Gc1_120 0 n2 ns120 0 0.000735257923147 +Gc1_121 0 n2 ns121 0 8.57601878071e-007 +Gc1_122 0 n2 ns122 0 -6.7113253418e-007 +Gc1_123 0 n2 ns123 0 0.0023570614307 +Gc1_124 0 n2 ns124 0 0.00118983575809 +Gc1_125 0 n2 ns125 0 -0.00178740546817 +Gc1_126 0 n2 ns126 0 -0.00674906140684 +Gc1_127 0 n2 ns127 0 4.48387257258e-006 +Gc1_128 0 n2 ns128 0 2.55510572528e-006 +Gc1_129 0 n2 ns129 0 0.00339777084047 +Gc1_130 0 n2 ns130 0 0.00530289290666 +Gc1_131 0 n2 ns131 0 -5.11327747784e-005 +Gc1_132 0 n2 ns132 0 0.000629657959056 +Gc1_133 0 n2 ns133 0 0.000136122994856 +Gc1_134 0 n2 ns134 0 -0.00031044358588 +Gc1_135 0 n2 ns135 0 5.88654645627e-005 +Gc1_136 0 n2 ns136 0 9.04792105922e-005 +Gc1_137 0 n2 ns137 0 0.00272346142219 +Gc1_138 0 n2 ns138 0 0.000606630193451 +Gc1_139 0 n2 ns139 0 -0.00516508305258 +Gc1_140 0 n2 ns140 0 0.00234871249308 +Gc1_141 0 n2 ns141 0 -0.00653231904072 +Gc1_142 0 n2 ns142 0 1.98654745685e-005 +Gc1_143 0 n2 ns143 0 0.000206407759718 +Gc1_144 0 n2 ns144 0 0.00367594548571 +Gc1_145 0 n2 ns145 0 3.39243091946e-007 +Gc1_146 0 n2 ns146 0 8.20068118296e-008 +Gc1_147 0 n2 ns147 0 0.00324583486072 +Gc1_148 0 n2 ns148 0 0.000538501863779 +Gc1_149 0 n2 ns149 0 4.02111820852e-007 +Gc1_150 0 n2 ns150 0 -2.48681375949e-007 +Gc1_151 0 n2 ns151 0 0.0023201304687 +Gc1_152 0 n2 ns152 0 -0.00355377053996 +Gc1_153 0 n2 ns153 0 -0.000411682309366 +Gc1_154 0 n2 ns154 0 -0.000659777995746 +Gc1_155 0 n2 ns155 0 2.11796466392e-007 +Gc1_156 0 n2 ns156 0 -1.33773856408e-006 +Gc1_157 0 n2 ns157 0 0.00168956427051 +Gc1_158 0 n2 ns158 0 0.00412008568885 +Gc1_159 0 n2 ns159 0 -0.000103364777197 +Gc1_160 0 n2 ns160 0 6.15724722993e-005 +Gc1_161 0 n2 ns161 0 9.1092359019e-005 +Gc1_162 0 n2 ns162 0 6.23656838641e-005 +Gc1_163 0 n2 ns163 0 -3.99205618983e-005 +Gc1_164 0 n2 ns164 0 -7.54403526386e-006 +Gc1_165 0 n2 ns165 0 -0.00464499416823 +Gc1_166 0 n2 ns166 0 -0.00620093341607 +Gc1_167 0 n2 ns167 0 -0.0018867811432 +Gc1_168 0 n2 ns168 0 0.0013278155462 +Gd1_1 0 n2 ni1 0 0.00253384033478 +Gd1_2 0 n2 ni2 0 -0.00260998490162 +Gd1_3 0 n2 ni3 0 -0.00136695481977 +Gd1_4 0 n2 ni4 0 -0.0035822317417 +Gd1_5 0 n2 ni5 0 -0.000245380798687 +Gd1_6 0 n2 ni6 0 -0.00137497188283 +Gc2_1 0 n4 ns1 0 0.00655854358389 +Gc2_2 0 n4 ns2 0 -2.15696309927e-005 +Gc2_3 0 n4 ns3 0 -0.000244944674 +Gc2_4 0 n4 ns4 0 -0.00322514658856 +Gc2_5 0 n4 ns5 0 5.90935027436e-008 +Gc2_6 0 n4 ns6 0 -1.47139396537e-007 +Gc2_7 0 n4 ns7 0 -0.00369666166325 +Gc2_8 0 n4 ns8 0 -0.000772487221946 +Gc2_9 0 n4 ns9 0 -1.63610057368e-007 +Gc2_10 0 n4 ns10 0 5.16506335071e-008 +Gc2_11 0 n4 ns11 0 -0.00326237091934 +Gc2_12 0 n4 ns12 0 -0.00166566565862 +Gc2_13 0 n4 ns13 0 0.00180738666063 +Gc2_14 0 n4 ns14 0 0.00831843514089 +Gc2_15 0 n4 ns15 0 -6.20407699602e-006 +Gc2_16 0 n4 ns16 0 -4.32415503558e-006 +Gc2_17 0 n4 ns17 0 -0.00305058383218 +Gc2_18 0 n4 ns18 0 -0.0055425175221 +Gc2_19 0 n4 ns19 0 1.1536030734e-006 +Gc2_20 0 n4 ns20 0 -0.000596866874964 +Gc2_21 0 n4 ns21 0 -4.57847918697e-005 +Gc2_22 0 n4 ns22 0 0.000391880820285 +Gc2_23 0 n4 ns23 0 -0.000121340502118 +Gc2_24 0 n4 ns24 0 -2.09941351043e-005 +Gc2_25 0 n4 ns25 0 -0.00541936220141 +Gc2_26 0 n4 ns26 0 -0.00474014897462 +Gc2_27 0 n4 ns27 0 0.000297734684112 +Gc2_28 0 n4 ns28 0 -0.00354037479982 +Gc2_29 0 n4 ns29 0 0.00662316592188 +Gc2_30 0 n4 ns30 0 5.70616041695e-005 +Gc2_31 0 n4 ns31 0 0.000430099944592 +Gc2_32 0 n4 ns32 0 0.0063918500955 +Gc2_33 0 n4 ns33 0 -7.54898465803e-007 +Gc2_34 0 n4 ns34 0 -3.71145028605e-010 +Gc2_35 0 n4 ns35 0 0.00766393921024 +Gc2_36 0 n4 ns36 0 0.0012791065139 +Gc2_37 0 n4 ns37 0 1.01452688036e-006 +Gc2_38 0 n4 ns38 0 -1.11340744468e-006 +Gc2_39 0 n4 ns39 0 -0.00179864844943 +Gc2_40 0 n4 ns40 0 -0.00197189894428 +Gc2_41 0 n4 ns41 0 0.00339938441379 +Gc2_42 0 n4 ns42 0 -0.00852694463174 +Gc2_43 0 n4 ns43 0 1.75769833016e-006 +Gc2_44 0 n4 ns44 0 -2.10381236903e-006 +Gc2_45 0 n4 ns45 0 -0.00108408733984 +Gc2_46 0 n4 ns46 0 -0.00835702859054 +Gc2_47 0 n4 ns47 0 -0.000182006460193 +Gc2_48 0 n4 ns48 0 -0.00121713982203 +Gc2_49 0 n4 ns49 0 0.000214373534825 +Gc2_50 0 n4 ns50 0 -3.4888642088e-006 +Gc2_51 0 n4 ns51 0 0.000163867669904 +Gc2_52 0 n4 ns52 0 -7.28663645476e-005 +Gc2_53 0 n4 ns53 0 -0.0083726693623 +Gc2_54 0 n4 ns54 0 0.0856977154752 +Gc2_55 0 n4 ns55 0 0.0175039348272 +Gc2_56 0 n4 ns56 0 -0.0072717978956 +Gc2_57 0 n4 ns57 0 0.00654849332164 +Gc2_58 0 n4 ns58 0 -2.61199335605e-005 +Gc2_59 0 n4 ns59 0 -0.000156193992882 +Gc2_60 0 n4 ns60 0 -0.00325627313405 +Gc2_61 0 n4 ns61 0 -3.85010237566e-007 +Gc2_62 0 n4 ns62 0 2.81923446831e-007 +Gc2_63 0 n4 ns63 0 -0.00365794022437 +Gc2_64 0 n4 ns64 0 -0.000847935508566 +Gc2_65 0 n4 ns65 0 6.77724912928e-007 +Gc2_66 0 n4 ns66 0 -1.3266538216e-006 +Gc2_67 0 n4 ns67 0 0.00201173368741 +Gc2_68 0 n4 ns68 0 0.0072826664419 +Gc2_69 0 n4 ns69 0 -0.0055120153365 +Gc2_70 0 n4 ns70 0 -0.00237620405708 +Gc2_71 0 n4 ns71 0 6.37113672825e-006 +Gc2_72 0 n4 ns72 0 -1.04911065169e-006 +Gc2_73 0 n4 ns73 0 0.000432079137931 +Gc2_74 0 n4 ns74 0 -0.00467840169702 +Gc2_75 0 n4 ns75 0 0.000197676914169 +Gc2_76 0 n4 ns76 0 -0.000181895900445 +Gc2_77 0 n4 ns77 0 -3.15336880801e-005 +Gc2_78 0 n4 ns78 0 4.10327651526e-005 +Gc2_79 0 n4 ns79 0 4.32746011153e-005 +Gc2_80 0 n4 ns80 0 -5.4115364699e-005 +Gc2_81 0 n4 ns81 0 0.00558502550547 +Gc2_82 0 n4 ns82 0 -0.000124339004122 +Gc2_83 0 n4 ns83 0 -0.00432340235657 +Gc2_84 0 n4 ns84 0 0.00179242284525 +Gc2_85 0 n4 ns85 0 -0.00655572780559 +Gc2_86 0 n4 ns86 0 2.23082547712e-005 +Gc2_87 0 n4 ns87 0 0.000241443067163 +Gc2_88 0 n4 ns88 0 0.00324419143818 +Gc2_89 0 n4 ns89 0 1.18468666177e-007 +Gc2_90 0 n4 ns90 0 1.43147206786e-007 +Gc2_91 0 n4 ns91 0 0.00364679205903 +Gc2_92 0 n4 ns92 0 0.000785882359165 +Gc2_93 0 n4 ns93 0 6.72029108445e-007 +Gc2_94 0 n4 ns94 0 -4.86471872203e-007 +Gc2_95 0 n4 ns95 0 0.00286558580435 +Gc2_96 0 n4 ns96 0 0.000778948938578 +Gc2_97 0 n4 ns97 0 -0.00152195153746 +Gc2_98 0 n4 ns98 0 -0.0066948778422 +Gc2_99 0 n4 ns99 0 4.55291322077e-006 +Gc2_100 0 n4 ns100 0 2.63768652327e-006 +Gc2_101 0 n4 ns101 0 0.00287861867144 +Gc2_102 0 n4 ns102 0 0.00540184989414 +Gc2_103 0 n4 ns103 0 4.92459298244e-005 +Gc2_104 0 n4 ns104 0 0.000461347129857 +Gc2_105 0 n4 ns105 0 6.28943286114e-006 +Gc2_106 0 n4 ns106 0 -0.000311952266607 +Gc2_107 0 n4 ns107 0 6.74838559762e-005 +Gc2_108 0 n4 ns108 0 -2.48876899133e-005 +Gc2_109 0 n4 ns109 0 0.00127615970977 +Gc2_110 0 n4 ns110 0 -0.000694001198382 +Gc2_111 0 n4 ns111 0 -0.00478931724775 +Gc2_112 0 n4 ns112 0 0.00277950867326 +Gc2_113 0 n4 ns113 0 -0.00661104414404 +Gc2_114 0 n4 ns114 0 -4.50977401678e-005 +Gc2_115 0 n4 ns115 0 -0.000452807356167 +Gc2_116 0 n4 ns116 0 -0.0062844455705 +Gc2_117 0 n4 ns117 0 -5.68722041465e-008 +Gc2_118 0 n4 ns118 0 -5.02374993577e-007 +Gc2_119 0 n4 ns119 0 -0.00773148757793 +Gc2_120 0 n4 ns120 0 -0.0012528837153 +Gc2_121 0 n4 ns121 0 -1.28128179852e-007 +Gc2_122 0 n4 ns122 0 5.66159561095e-007 +Gc2_123 0 n4 ns123 0 0.00192635082935 +Gc2_124 0 n4 ns124 0 0.00142830739117 +Gc2_125 0 n4 ns125 0 -0.00254865672312 +Gc2_126 0 n4 ns126 0 0.00726774685861 +Gc2_127 0 n4 ns127 0 -1.6705277403e-006 +Gc2_128 0 n4 ns128 0 1.81743254545e-006 +Gc2_129 0 n4 ns129 0 0.00122936761997 +Gc2_130 0 n4 ns130 0 0.00822666605464 +Gc2_131 0 n4 ns131 0 0.000169257358335 +Gc2_132 0 n4 ns132 0 0.00133432364698 +Gc2_133 0 n4 ns133 0 -0.000199501226609 +Gc2_134 0 n4 ns134 0 -4.71152295222e-005 +Gc2_135 0 n4 ns135 0 -0.000160856340009 +Gc2_136 0 n4 ns136 0 0.000119596249505 +Gc2_137 0 n4 ns137 0 0.00116785144912 +Gc2_138 0 n4 ns138 0 -0.0626416290687 +Gc2_139 0 n4 ns139 0 -0.0101374571843 +Gc2_140 0 n4 ns140 0 0.0136515284268 +Gc2_141 0 n4 ns141 0 -0.00653397758398 +Gc2_142 0 n4 ns142 0 2.48804195884e-005 +Gc2_143 0 n4 ns143 0 0.000162754901451 +Gc2_144 0 n4 ns144 0 0.00318539563375 +Gc2_145 0 n4 ns145 0 4.53845407034e-007 +Gc2_146 0 n4 ns146 0 -1.08617326384e-007 +Gc2_147 0 n4 ns147 0 0.00368464338773 +Gc2_148 0 n4 ns148 0 0.000792063824344 +Gc2_149 0 n4 ns149 0 1.97262780965e-007 +Gc2_150 0 n4 ns150 0 6.64799421655e-007 +Gc2_151 0 n4 ns151 0 -0.0018993289386 +Gc2_152 0 n4 ns152 0 -0.0058358524139 +Gc2_153 0 n4 ns153 0 0.00472985474877 +Gc2_154 0 n4 ns154 0 0.00193665027244 +Gc2_155 0 n4 ns155 0 -6.01947267484e-006 +Gc2_156 0 n4 ns156 0 6.05086732971e-007 +Gc2_157 0 n4 ns157 0 -0.000261557610195 +Gc2_158 0 n4 ns158 0 0.00499422768637 +Gc2_159 0 n4 ns159 0 -0.000197617224762 +Gc2_160 0 n4 ns160 0 0.000228712677517 +Gc2_161 0 n4 ns161 0 2.93686603326e-005 +Gc2_162 0 n4 ns162 0 -6.06892093029e-005 +Gc2_163 0 n4 ns163 0 -8.10920230444e-005 +Gc2_164 0 n4 ns164 0 5.26210656516e-006 +Gc2_165 0 n4 ns165 0 -0.00613682011372 +Gc2_166 0 n4 ns166 0 -0.00356611061545 +Gc2_167 0 n4 ns167 0 -0.00147827392946 +Gc2_168 0 n4 ns168 0 -0.00208817770522 +Gd2_1 0 n4 ni1 0 -0.00256526033453 +Gd2_2 0 n4 ni2 0 0.00258331242687 +Gd2_3 0 n4 ni3 0 -0.000528607293134 +Gd2_4 0 n4 ni4 0 -0.000549392817713 +Gd2_5 0 n4 ni5 0 -0.00323578493957 +Gd2_6 0 n4 ni6 0 -0.00201501915336 +Gc3_1 0 n6 ns1 0 0.00655625319427 +Gc3_2 0 n6 ns2 0 -2.15131987403e-005 +Gc3_3 0 n6 ns3 0 -0.000201504529866 +Gc3_4 0 n6 ns4 0 -0.00373177795137 +Gc3_5 0 n6 ns5 0 -8.89033281088e-008 +Gc3_6 0 n6 ns6 0 7.47144098907e-008 +Gc3_7 0 n6 ns7 0 -0.00321479290964 +Gc3_8 0 n6 ns8 0 -0.00055159627545 +Gc3_9 0 n6 ns9 0 6.03285214107e-007 +Gc3_10 0 n6 ns10 0 -2.27502800827e-007 +Gc3_11 0 n6 ns11 0 -0.00287884867566 +Gc3_12 0 n6 ns12 0 0.00420620279227 +Gc3_13 0 n6 ns13 0 0.000592478868009 +Gc3_14 0 n6 ns14 0 0.000580060403569 +Gc3_15 0 n6 ns15 0 -5.04431678948e-007 +Gc3_16 0 n6 ns16 0 1.01050230309e-006 +Gc3_17 0 n6 ns17 0 -0.00152471883241 +Gc3_18 0 n6 ns18 0 -0.00409534985834 +Gc3_19 0 n6 ns19 0 9.27136665295e-005 +Gc3_20 0 n6 ns20 0 -4.13208070318e-005 +Gc3_21 0 n6 ns21 0 -4.41254154562e-005 +Gc3_22 0 n6 ns22 0 -3.88816750071e-005 +Gc3_23 0 n6 ns23 0 3.9571013692e-005 +Gc3_24 0 n6 ns24 0 -4.01682281218e-005 +Gc3_25 0 n6 ns25 0 0.00297074317701 +Gc3_26 0 n6 ns26 0 0.00252423424431 +Gc3_27 0 n6 ns27 0 -0.00370983477276 +Gc3_28 0 n6 ns28 0 -0.00163819389026 +Gc3_29 0 n6 ns29 0 0.00655581854655 +Gc3_30 0 n6 ns30 0 -2.6964750929e-005 +Gc3_31 0 n6 ns31 0 -0.000153736606498 +Gc3_32 0 n6 ns32 0 -0.00327082911491 +Gc3_33 0 n6 ns33 0 -2.50911511498e-007 +Gc3_34 0 n6 ns34 0 3.26080391906e-007 +Gc3_35 0 n6 ns35 0 -0.0036391578723 +Gc3_36 0 n6 ns36 0 -0.000852424415148 +Gc3_37 0 n6 ns37 0 6.86300641225e-007 +Gc3_38 0 n6 ns38 0 -1.31803118388e-006 +Gc3_39 0 n6 ns39 0 0.00200116171661 +Gc3_40 0 n6 ns40 0 0.00727986952046 +Gc3_41 0 n6 ns41 0 -0.00549518634257 +Gc3_42 0 n6 ns42 0 -0.00237999954319 +Gc3_43 0 n6 ns43 0 6.34597923234e-006 +Gc3_44 0 n6 ns44 0 -1.06383940637e-006 +Gc3_45 0 n6 ns45 0 0.00043417980941 +Gc3_46 0 n6 ns46 0 -0.00467040548384 +Gc3_47 0 n6 ns47 0 0.00019674925403 +Gc3_48 0 n6 ns48 0 -0.000182212036395 +Gc3_49 0 n6 ns49 0 -3.10795472944e-005 +Gc3_50 0 n6 ns50 0 4.11372219771e-005 +Gc3_51 0 n6 ns51 0 4.11186399612e-005 +Gc3_52 0 n6 ns52 0 -5.54401428668e-005 +Gc3_53 0 n6 ns53 0 0.00568601493146 +Gc3_54 0 n6 ns54 0 -0.000127213704914 +Gc3_55 0 n6 ns55 0 -0.00431722249321 +Gc3_56 0 n6 ns56 0 0.00185711812464 +Gc3_57 0 n6 ns57 0 0.00661439505742 +Gc3_58 0 n6 ns58 0 6.31442063324e-005 +Gc3_59 0 n6 ns59 0 0.000352071422906 +Gc3_60 0 n6 ns60 0 0.00704083087263 +Gc3_61 0 n6 ns61 0 -1.63155565598e-007 +Gc3_62 0 n6 ns62 0 -5.70993339066e-007 +Gc3_63 0 n6 ns63 0 0.00675759182874 +Gc3_64 0 n6 ns64 0 0.00128560002001 +Gc3_65 0 n6 ns65 0 -1.18383234968e-007 +Gc3_66 0 n6 ns66 0 7.03296542063e-007 +Gc3_67 0 n6 ns67 0 0.000521404124182 +Gc3_68 0 n6 ns68 0 -0.0159175404179 +Gc3_69 0 n6 ns69 0 0.00713889921787 +Gc3_70 0 n6 ns70 0 0.00293092969392 +Gc3_71 0 n6 ns71 0 -4.83102285224e-006 +Gc3_72 0 n6 ns72 0 -7.04467436897e-006 +Gc3_73 0 n6 ns73 0 0.00313552265846 +Gc3_74 0 n6 ns74 0 -0.00266017296133 +Gc3_75 0 n6 ns75 0 -1.9314192362e-005 +Gc3_76 0 n6 ns76 0 -2.30253033022e-005 +Gc3_77 0 n6 ns77 0 2.50434323122e-005 +Gc3_78 0 n6 ns78 0 5.02927481887e-006 +Gc3_79 0 n6 ns79 0 -1.02600468614e-005 +Gc3_80 0 n6 ns80 0 5.64840101171e-005 +Gc3_81 0 n6 ns81 0 -0.0249793673647 +Gc3_82 0 n6 ns82 0 0.037734875249 +Gc3_83 0 n6 ns83 0 0.0209268626967 +Gc3_84 0 n6 ns84 0 0.00454996417864 +Gc3_85 0 n6 ns85 0 -0.0065526908543 +Gc3_86 0 n6 ns86 0 2.04533514624e-005 +Gc3_87 0 n6 ns87 0 0.000208343439723 +Gc3_88 0 n6 ns88 0 0.00369083328173 +Gc3_89 0 n6 ns89 0 2.70537857663e-007 +Gc3_90 0 n6 ns90 0 -8.32231909847e-008 +Gc3_91 0 n6 ns91 0 0.00322793525604 +Gc3_92 0 n6 ns92 0 0.000535401614681 +Gc3_93 0 n6 ns93 0 3.79413838847e-007 +Gc3_94 0 n6 ns94 0 -2.06856356883e-007 +Gc3_95 0 n6 ns95 0 0.00180681950754 +Gc3_96 0 n6 ns96 0 -0.00285326681875 +Gc3_97 0 n6 ns97 0 -0.000713523736899 +Gc3_98 0 n6 ns98 0 -0.000647565290771 +Gc3_99 0 n6 ns99 0 1.25900321644e-006 +Gc3_100 0 n6 ns100 0 -3.05833147797e-006 +Gc3_101 0 n6 ns101 0 0.00124940589627 +Gc3_102 0 n6 ns102 0 0.00387229402502 +Gc3_103 0 n6 ns103 0 -6.11018181658e-005 +Gc3_104 0 n6 ns104 0 2.38058136977e-005 +Gc3_105 0 n6 ns105 0 3.58815903272e-005 +Gc3_106 0 n6 ns106 0 3.58090701418e-005 +Gc3_107 0 n6 ns107 0 -5.38540267472e-005 +Gc3_108 0 n6 ns108 0 -3.76217075791e-005 +Gc3_109 0 n6 ns109 0 -0.00434716152159 +Gc3_110 0 n6 ns110 0 -0.00400271146311 +Gc3_111 0 n6 ns111 0 -0.00171954449588 +Gc3_112 0 n6 ns112 0 -0.000104284392861 +Gc3_113 0 n6 ns113 0 -0.00655174111935 +Gc3_114 0 n6 ns114 0 2.58302207934e-005 +Gc3_115 0 n6 ns115 0 0.000162015409715 +Gc3_116 0 n6 ns116 0 0.00322597324822 +Gc3_117 0 n6 ns117 0 4.03151890588e-007 +Gc3_118 0 n6 ns118 0 -3.11906794825e-007 +Gc3_119 0 n6 ns119 0 0.00366823532779 +Gc3_120 0 n6 ns120 0 0.000811796022936 +Gc3_121 0 n6 ns121 0 1.68215497708e-007 +Gc3_122 0 n6 ns122 0 7.63815495494e-007 +Gc3_123 0 n6 ns123 0 -0.0018269530764 +Gc3_124 0 n6 ns124 0 -0.00604942563684 +Gc3_125 0 n6 ns125 0 0.00468820388412 +Gc3_126 0 n6 ns126 0 0.00187700187722 +Gc3_127 0 n6 ns127 0 -4.21685147923e-006 +Gc3_128 0 n6 ns128 0 -4.78193833606e-007 +Gc3_129 0 n6 ns129 0 -0.000410513917745 +Gc3_130 0 n6 ns130 0 0.00469389143807 +Gc3_131 0 n6 ns131 0 -0.000190504640192 +Gc3_132 0 n6 ns132 0 0.000170819518391 +Gc3_133 0 n6 ns133 0 2.63754783168e-005 +Gc3_134 0 n6 ns134 0 -2.38822679808e-005 +Gc3_135 0 n6 ns135 0 -3.73552823571e-005 +Gc3_136 0 n6 ns136 0 -2.62735795558e-005 +Gc3_137 0 n6 ns137 0 -0.00743182290851 +Gc3_138 0 n6 ns138 0 -0.00274169412758 +Gc3_139 0 n6 ns139 0 -0.000800314120977 +Gc3_140 0 n6 ns140 0 -0.00276182492556 +Gc3_141 0 n6 ns141 0 -0.00660953064147 +Gc3_142 0 n6 ns142 0 -4.99717959038e-005 +Gc3_143 0 n6 ns143 0 -0.000378547759066 +Gc3_144 0 n6 ns144 0 -0.00690667835166 +Gc3_145 0 n6 ns145 0 -6.2288691363e-007 +Gc3_146 0 n6 ns146 0 1.10874685347e-007 +Gc3_147 0 n6 ns147 0 -0.00684338581756 +Gc3_148 0 n6 ns148 0 -0.00129074512637 +Gc3_149 0 n6 ns149 0 9.82276295874e-007 +Gc3_150 0 n6 ns150 0 -1.09376861716e-006 +Gc3_151 0 n6 ns151 0 -0.000407469182265 +Gc3_152 0 n6 ns152 0 0.0133510960221 +Gc3_153 0 n6 ns153 0 -0.00571023783062 +Gc3_154 0 n6 ns154 0 -0.00279234017065 +Gc3_155 0 n6 ns155 0 4.40330652231e-006 +Gc3_156 0 n6 ns156 0 3.53367992677e-006 +Gc3_157 0 n6 ns157 0 -0.00257964732854 +Gc3_158 0 n6 ns158 0 0.00280876117523 +Gc3_159 0 n6 ns159 0 -1.04630173863e-005 +Gc3_160 0 n6 ns160 0 4.77492181332e-005 +Gc3_161 0 n6 ns161 0 -1.78900335832e-005 +Gc3_162 0 n6 ns162 0 -1.48486382861e-005 +Gc3_163 0 n6 ns163 0 -7.23049256988e-005 +Gc3_164 0 n6 ns164 0 4.53806558902e-005 +Gc3_165 0 n6 ns165 0 0.0170664562608 +Gc3_166 0 n6 ns166 0 -0.0158903536471 +Gc3_167 0 n6 ns167 0 -0.012908294227 +Gc3_168 0 n6 ns168 0 0.00286007103313 +Gd3_1 0 n6 ni1 0 -0.00132563347953 +Gd3_2 0 n6 ni2 0 -0.000484943297481 +Gd3_3 0 n6 ni3 0 0.000420603876253 +Gd3_4 0 n6 ni4 0 -0.00151341976676 +Gd3_5 0 n6 ni5 0 -0.00212746210164 +Gd3_6 0 n6 ni6 0 -0.00124009208755 +Gc4_1 0 n8 ns1 0 -0.00657646253819 +Gc4_2 0 n8 ns2 0 -4.9778964449e-005 +Gc4_3 0 n8 ns3 0 -0.00047801199007 +Gc4_4 0 n8 ns4 0 -0.00685996899678 +Gc4_5 0 n8 ns5 0 5.95028227716e-007 +Gc4_6 0 n8 ns6 0 -3.01727286945e-007 +Gc4_7 0 n8 ns7 0 -0.00715768459816 +Gc4_8 0 n8 ns8 0 -0.00104537837114 +Gc4_9 0 n8 ns9 0 -4.09396437934e-007 +Gc4_10 0 n8 ns10 0 1.2084345724e-006 +Gc4_11 0 n8 ns11 0 -0.0016739406401 +Gc4_12 0 n8 ns12 0 -0.00231712867009 +Gc4_13 0 n8 ns13 0 -0.00214561808388 +Gc4_14 0 n8 ns14 0 0.0126384715547 +Gc4_15 0 n8 ns15 0 -3.63505666898e-006 +Gc4_16 0 n8 ns16 0 -5.96836361095e-007 +Gc4_17 0 n8 ns17 0 0.00408410162343 +Gc4_18 0 n8 ns18 0 0.000814400788838 +Gc4_19 0 n8 ns19 0 -0.000115833148035 +Gc4_20 0 n8 ns20 0 0.000314069882024 +Gc4_21 0 n8 ns21 0 0.000623734807857 +Gc4_22 0 n8 ns22 0 0.000185314998826 +Gc4_23 0 n8 ns23 0 0.000624145722184 +Gc4_24 0 n8 ns24 0 0.00110494974283 +Gc4_25 0 n8 ns25 0 -0.00571008429277 +Gc4_26 0 n8 ns26 0 -0.0665909959996 +Gc4_27 0 n8 ns27 0 -0.00587968545788 +Gc4_28 0 n8 ns28 0 0.0167475923473 +Gc4_29 0 n8 ns29 0 -0.00655118852849 +Gc4_30 0 n8 ns30 0 2.10021245325e-005 +Gc4_31 0 n8 ns31 0 0.000245130963796 +Gc4_32 0 n8 ns32 0 0.0032391023225 +Gc4_33 0 n8 ns33 0 -1.24543095562e-007 +Gc4_34 0 n8 ns34 0 6.72988142163e-008 +Gc4_35 0 n8 ns35 0 0.00365446827011 +Gc4_36 0 n8 ns36 0 0.000780999576547 +Gc4_37 0 n8 ns37 0 8.80568120562e-007 +Gc4_38 0 n8 ns38 0 -5.21453058923e-007 +Gc4_39 0 n8 ns39 0 0.0028203053211 +Gc4_40 0 n8 ns40 0 0.00076771548971 +Gc4_41 0 n8 ns41 0 -0.00146937711532 +Gc4_42 0 n8 ns42 0 -0.0066747082647 +Gc4_43 0 n8 ns43 0 4.40620863764e-006 +Gc4_44 0 n8 ns44 0 2.82088789977e-006 +Gc4_45 0 n8 ns45 0 0.00286483269251 +Gc4_46 0 n8 ns46 0 0.00539773797979 +Gc4_47 0 n8 ns47 0 5.36787511875e-005 +Gc4_48 0 n8 ns48 0 0.000463679388162 +Gc4_49 0 n8 ns49 0 3.37070349692e-006 +Gc4_50 0 n8 ns50 0 -0.00031238486138 +Gc4_51 0 n8 ns51 0 6.93163519695e-005 +Gc4_52 0 n8 ns52 0 -2.06879814977e-005 +Gc4_53 0 n8 ns53 0 0.00106571847017 +Gc4_54 0 n8 ns54 0 -0.000747959940719 +Gc4_55 0 n8 ns55 0 -0.00477020184901 +Gc4_56 0 n8 ns56 0 0.00266171642312 +Gc4_57 0 n8 ns57 0 -0.00655047944691 +Gc4_58 0 n8 ns58 0 2.0516892712e-005 +Gc4_59 0 n8 ns59 0 0.000204553556243 +Gc4_60 0 n8 ns60 0 0.00372479251289 +Gc4_61 0 n8 ns61 0 -2.08898279409e-008 +Gc4_62 0 n8 ns62 0 -1.17405031455e-007 +Gc4_63 0 n8 ns63 0 0.00319161201058 +Gc4_64 0 n8 ns64 0 0.000546320727321 +Gc4_65 0 n8 ns65 0 3.74960727316e-007 +Gc4_66 0 n8 ns66 0 -2.08237350763e-007 +Gc4_67 0 n8 ns67 0 0.00182567054416 +Gc4_68 0 n8 ns68 0 -0.00282484243795 +Gc4_69 0 n8 ns69 0 -0.000744823506645 +Gc4_70 0 n8 ns70 0 -0.000667828949503 +Gc4_71 0 n8 ns71 0 1.35935137467e-006 +Gc4_72 0 n8 ns72 0 -2.94431023512e-006 +Gc4_73 0 n8 ns73 0 0.00124004232614 +Gc4_74 0 n8 ns74 0 0.00385653558518 +Gc4_75 0 n8 ns75 0 -6.0026129423e-005 +Gc4_76 0 n8 ns76 0 2.45694853048e-005 +Gc4_77 0 n8 ns77 0 3.51940913412e-005 +Gc4_78 0 n8 ns78 0 3.55964703162e-005 +Gc4_79 0 n8 ns79 0 -5.01601269307e-005 +Gc4_80 0 n8 ns80 0 -3.43365097045e-005 +Gc4_81 0 n8 ns81 0 -0.00455998186762 +Gc4_82 0 n8 ns82 0 -0.00396592756307 +Gc4_83 0 n8 ns83 0 -0.00171448604132 +Gc4_84 0 n8 ns84 0 -0.000252889712138 +Gc4_85 0 n8 ns85 0 0.00661802284048 +Gc4_86 0 n8 ns86 0 4.59496406841e-005 +Gc4_87 0 n8 ns87 0 0.000476916458909 +Gc4_88 0 n8 ns88 0 0.00681256000333 +Gc4_89 0 n8 ns89 0 -1.34919930879e-006 +Gc4_90 0 n8 ns90 0 1.10889958041e-006 +Gc4_91 0 n8 ns91 0 0.0071011374148 +Gc4_92 0 n8 ns92 0 0.000935864577659 +Gc4_93 0 n8 ns93 0 1.02411508045e-006 +Gc4_94 0 n8 ns94 0 -1.55580597864e-006 +Gc4_95 0 n8 ns95 0 0.000141098591158 +Gc4_96 0 n8 ns96 0 0.00300911946703 +Gc4_97 0 n8 ns97 0 0.00258987124417 +Gc4_98 0 n8 ns98 0 -0.0122685977664 +Gc4_99 0 n8 ns99 0 2.13657268582e-006 +Gc4_100 0 n8 ns100 0 -1.90928090993e-006 +Gc4_101 0 n8 ns101 0 -0.00326912599079 +Gc4_102 0 n8 ns102 0 -0.00100544495992 +Gc4_103 0 n8 ns103 0 2.44199569133e-005 +Gc4_104 0 n8 ns104 0 -0.000232844505462 +Gc4_105 0 n8 ns105 0 -0.000495587206045 +Gc4_106 0 n8 ns106 0 -0.000116370314584 +Gc4_107 0 n8 ns107 0 -0.000759572419869 +Gc4_108 0 n8 ns108 0 -0.000891780912062 +Gc4_109 0 n8 ns109 0 0.00487181101129 +Gc4_110 0 n8 ns110 0 0.0878824101896 +Gc4_111 0 n8 ns111 0 0.00996327844911 +Gc4_112 0 n8 ns112 0 -0.00816954582206 +Gc4_113 0 n8 ns113 0 0.00653545341376 +Gc4_114 0 n8 ns114 0 -1.96996506858e-005 +Gc4_115 0 n8 ns115 0 -0.000248272003615 +Gc4_116 0 n8 ns116 0 -0.0031857701614 +Gc4_117 0 n8 ns117 0 5.25426267139e-008 +Gc4_118 0 n8 ns118 0 -2.20111710015e-007 +Gc4_119 0 n8 ns119 0 -0.00367386054164 +Gc4_120 0 n8 ns120 0 -0.000722440707337 +Gc4_121 0 n8 ns121 0 8.68597493215e-009 +Gc4_122 0 n8 ns122 0 7.80589754727e-008 +Gc4_123 0 n8 ns123 0 -0.00203491796599 +Gc4_124 0 n8 ns124 0 -0.000826021245738 +Gc4_125 0 n8 ns125 0 0.00151128106759 +Gc4_126 0 n8 ns126 0 0.00581930812827 +Gc4_127 0 n8 ns127 0 -3.30570912116e-006 +Gc4_128 0 n8 ns128 0 -3.81656161394e-006 +Gc4_129 0 n8 ns129 0 -0.00321149296676 +Gc4_130 0 n8 ns130 0 -0.00507848624363 +Gc4_131 0 n8 ns131 0 1.33173560988e-005 +Gc4_132 0 n8 ns132 0 -0.000525161211835 +Gc4_133 0 n8 ns133 0 -9.20379620933e-005 +Gc4_134 0 n8 ns134 0 0.000273949624829 +Gc4_135 0 n8 ns135 0 -2.42015684909e-005 +Gc4_136 0 n8 ns136 0 -0.00017426749315 +Gc4_137 0 n8 ns137 0 -0.00621901771089 +Gc4_138 0 n8 ns138 0 -0.00239098684409 +Gc4_139 0 n8 ns139 0 0.000884085105258 +Gc4_140 0 n8 ns140 0 -0.00407593290512 +Gc4_141 0 n8 ns141 0 0.00653679484024 +Gc4_142 0 n8 ns142 0 -1.93220649141e-005 +Gc4_143 0 n8 ns143 0 -0.000207096518664 +Gc4_144 0 n8 ns144 0 -0.00366899648179 +Gc4_145 0 n8 ns145 0 -6.71662922236e-008 +Gc4_146 0 n8 ns146 0 -3.15756955169e-008 +Gc4_147 0 n8 ns147 0 -0.00321689650423 +Gc4_148 0 n8 ns148 0 -0.000508424707675 +Gc4_149 0 n8 ns149 0 4.49038930605e-007 +Gc4_150 0 n8 ns150 0 -1.00948384487e-007 +Gc4_151 0 n8 ns151 0 -0.00137367451212 +Gc4_152 0 n8 ns152 0 0.00208884545504 +Gc4_153 0 n8 ns153 0 0.000496023597955 +Gc4_154 0 n8 ns154 0 0.00108887823064 +Gc4_155 0 n8 ns155 0 6.98198728822e-008 +Gc4_156 0 n8 ns156 0 -1.74923650725e-007 +Gc4_157 0 n8 ns157 0 -0.00145824939578 +Gc4_158 0 n8 ns158 0 -0.00381426305901 +Gc4_159 0 n8 ns159 0 9.44983229783e-005 +Gc4_160 0 n8 ns160 0 -7.35889846256e-005 +Gc4_161 0 n8 ns161 0 -8.42619587559e-005 +Gc4_162 0 n8 ns162 0 -3.18292466457e-005 +Gc4_163 0 n8 ns163 0 4.42495782473e-005 +Gc4_164 0 n8 ns164 0 -6.25239525566e-005 +Gc4_165 0 n8 ns165 0 -0.00109294201703 +Gc4_166 0 n8 ns166 0 0.00047435069498 +Gc4_167 0 n8 ns167 0 -0.0018198257252 +Gc4_168 0 n8 ns168 0 -0.00179240709144 +Gd4_1 0 n8 ni1 0 -0.00331231034563 +Gd4_2 0 n8 ni2 0 -0.000618322851979 +Gd4_3 0 n8 ni3 0 -0.00159682859325 +Gd4_4 0 n8 ni4 0 0.00248270766544 +Gd4_5 0 n8 ni5 0 -0.00211617444222 +Gd4_6 0 n8 ni6 0 -0.00128943852982 +Gc5_1 0 n10 ns1 0 -0.0065613856704 +Gc5_2 0 n10 ns2 0 2.27463016655e-005 +Gc5_3 0 n10 ns3 0 0.000243189808245 +Gc5_4 0 n10 ns4 0 0.00322169525666 +Gc5_5 0 n10 ns5 0 -2.06505233144e-007 +Gc5_6 0 n10 ns6 0 1.46668889819e-007 +Gc5_7 0 n10 ns7 0 0.00366606437236 +Gc5_8 0 n10 ns8 0 0.000747064010866 +Gc5_9 0 n10 ns9 0 8.44615817973e-007 +Gc5_10 0 n10 ns10 0 -6.79856689907e-007 +Gc5_11 0 n10 ns11 0 0.00238460733016 +Gc5_12 0 n10 ns12 0 0.00120424159362 +Gc5_13 0 n10 ns13 0 -0.00182693664968 +Gc5_14 0 n10 ns14 0 -0.00674403633494 +Gc5_15 0 n10 ns15 0 4.50932945249e-006 +Gc5_16 0 n10 ns16 0 2.54460715135e-006 +Gc5_17 0 n10 ns17 0 0.00337578912891 +Gc5_18 0 n10 ns18 0 0.00528331887365 +Gc5_19 0 n10 ns19 0 -4.79349782449e-005 +Gc5_20 0 n10 ns20 0 0.000631219019473 +Gc5_21 0 n10 ns21 0 0.000134017763356 +Gc5_22 0 n10 ns22 0 -0.000310516087238 +Gc5_23 0 n10 ns23 0 6.66001262145e-005 +Gc5_24 0 n10 ns24 0 9.7719805023e-005 +Gc5_25 0 n10 ns25 0 0.00232878423155 +Gc5_26 0 n10 ns26 0 0.000639841780698 +Gc5_27 0 n10 ns27 0 -0.00517001814928 +Gc5_28 0 n10 ns28 0 0.00207343658495 +Gc5_29 0 n10 ns29 0 -0.00658040776454 +Gc5_30 0 n10 ns30 0 -5.26319080386e-005 +Gc5_31 0 n10 ns31 0 -0.000441647788035 +Gc5_32 0 n10 ns32 0 -0.00635558613877 +Gc5_33 0 n10 ns33 0 3.95352321708e-007 +Gc5_34 0 n10 ns34 0 -2.50257052596e-007 +Gc5_35 0 n10 ns35 0 -0.00765718013021 +Gc5_36 0 n10 ns36 0 -0.00127135578735 +Gc5_37 0 n10 ns37 0 -1.11069982832e-007 +Gc5_38 0 n10 ns38 0 5.58546698622e-007 +Gc5_39 0 n10 ns39 0 0.00187551652164 +Gc5_40 0 n10 ns40 0 0.00136150303943 +Gc5_41 0 n10 ns41 0 -0.00246116714005 +Gc5_42 0 n10 ns42 0 0.00731517666291 +Gc5_43 0 n10 ns43 0 -1.79658281113e-006 +Gc5_44 0 n10 ns44 0 1.60524860734e-006 +Gc5_45 0 n10 ns45 0 0.00123227816331 +Gc5_46 0 n10 ns46 0 0.0082523764679 +Gc5_47 0 n10 ns47 0 0.000166405399538 +Gc5_48 0 n10 ns48 0 0.0013323876108 +Gc5_49 0 n10 ns49 0 -0.000197851825151 +Gc5_50 0 n10 ns50 0 -4.73128390943e-005 +Gc5_51 0 n10 ns51 0 -0.000167364808098 +Gc5_52 0 n10 ns52 0 0.00011221711625 +Gc5_53 0 n10 ns53 0 0.00168510838679 +Gc5_54 0 n10 ns54 0 -0.0625782859705 +Gc5_55 0 n10 ns55 0 -0.010174575968 +Gc5_56 0 n10 ns56 0 0.0139445480346 +Gc5_57 0 n10 ns57 0 -0.00655262148 +Gc5_58 0 n10 ns58 0 2.62670719219e-005 +Gc5_59 0 n10 ns59 0 0.000157824368494 +Gc5_60 0 n10 ns60 0 0.00326056202607 +Gc5_61 0 n10 ns61 0 1.19938657616e-007 +Gc5_62 0 n10 ns62 0 -3.53553423545e-007 +Gc5_63 0 n10 ns63 0 0.00363142207379 +Gc5_64 0 n10 ns64 0 0.000822254679597 +Gc5_65 0 n10 ns65 0 1.60413148676e-007 +Gc5_66 0 n10 ns66 0 7.45944943052e-007 +Gc5_67 0 n10 ns67 0 -0.00178802107858 +Gc5_68 0 n10 ns68 0 -0.00602254183773 +Gc5_69 0 n10 ns69 0 0.00463168039638 +Gc5_70 0 n10 ns70 0 0.00186171777019 +Gc5_71 0 n10 ns71 0 -4.57931728189e-006 +Gc5_72 0 n10 ns72 0 -4.69201903806e-007 +Gc5_73 0 n10 ns73 0 -0.000415919137623 +Gc5_74 0 n10 ns74 0 0.00467261270739 +Gc5_75 0 n10 ns75 0 -0.00018892919325 +Gc5_76 0 n10 ns76 0 0.000171091758545 +Gc5_77 0 n10 ns77 0 2.5469439266e-005 +Gc5_78 0 n10 ns78 0 -2.37411246065e-005 +Gc5_79 0 n10 ns79 0 -3.44806947239e-005 +Gc5_80 0 n10 ns80 0 -2.32277745497e-005 +Gc5_81 0 n10 ns81 0 -0.00764652532773 +Gc5_82 0 n10 ns82 0 -0.00271637761837 +Gc5_83 0 n10 ns83 0 -0.000786523984721 +Gc5_84 0 n10 ns84 0 -0.00290345240116 +Gc5_85 0 n10 ns85 0 0.00655827567567 +Gc5_86 0 n10 ns86 0 -2.23132525925e-005 +Gc5_87 0 n10 ns87 0 -0.000240688739069 +Gc5_88 0 n10 ns88 0 -0.00322136065603 +Gc5_89 0 n10 ns89 0 8.79215503466e-008 +Gc5_90 0 n10 ns90 0 -2.05748883827e-007 +Gc5_91 0 n10 ns91 0 -0.00363922941529 +Gc5_92 0 n10 ns92 0 -0.000725314092231 +Gc5_93 0 n10 ns93 0 -9.71111524854e-008 +Gc5_94 0 n10 ns94 0 1.45852551125e-007 +Gc5_95 0 n10 ns95 0 -0.00206274857911 +Gc5_96 0 n10 ns96 0 -0.000819839716533 +Gc5_97 0 n10 ns97 0 0.0015395106929 +Gc5_98 0 n10 ns98 0 0.00581202453928 +Gc5_99 0 n10 ns99 0 -2.95669990525e-006 +Gc5_100 0 n10 ns100 0 -4.12232217877e-006 +Gc5_101 0 n10 ns101 0 -0.00321486859353 +Gc5_102 0 n10 ns102 0 -0.00508343680139 +Gc5_103 0 n10 ns103 0 1.11706165011e-005 +Gc5_104 0 n10 ns104 0 -0.000525093908314 +Gc5_105 0 n10 ns105 0 -9.09017130555e-005 +Gc5_106 0 n10 ns106 0 0.000273463091411 +Gc5_107 0 n10 ns107 0 -2.37739658597e-005 +Gc5_108 0 n10 ns108 0 -0.000173810885964 +Gc5_109 0 n10 ns109 0 -0.00626394048352 +Gc5_110 0 n10 ns110 0 -0.00239031554981 +Gc5_111 0 n10 ns111 0 0.000898492484319 +Gc5_112 0 n10 ns112 0 -0.00409660908467 +Gc5_113 0 n10 ns113 0 0.00660220663946 +Gc5_114 0 n10 ns114 0 5.61136028279e-005 +Gc5_115 0 n10 ns115 0 0.000432316150463 +Gc5_116 0 n10 ns116 0 0.00629696842228 +Gc5_117 0 n10 ns117 0 -3.78457452917e-007 +Gc5_118 0 n10 ns118 0 3.28106937309e-007 +Gc5_119 0 n10 ns119 0 0.00765177611018 +Gc5_120 0 n10 ns120 0 0.00109861355036 +Gc5_121 0 n10 ns121 0 7.86999861018e-007 +Gc5_122 0 n10 ns122 0 -1.11627464477e-006 +Gc5_123 0 n10 ns123 0 -0.00283768609689 +Gc5_124 0 n10 ns124 0 -0.000190653315617 +Gc5_125 0 n10 ns125 0 0.00280228433582 +Gc5_126 0 n10 ns126 0 -0.00742745558914 +Gc5_127 0 n10 ns127 0 1.76719400079e-007 +Gc5_128 0 n10 ns128 0 -2.96596532688e-006 +Gc5_129 0 n10 ns129 0 -0.000961587705403 +Gc5_130 0 n10 ns130 0 -0.00802665979128 +Gc5_131 0 n10 ns131 0 -0.000179584586649 +Gc5_132 0 n10 ns132 0 -0.00141043219124 +Gc5_133 0 n10 ns133 0 0.000182103303959 +Gc5_134 0 n10 ns134 0 5.90296938166e-005 +Gc5_135 0 n10 ns135 0 3.55040579277e-006 +Gc5_136 0 n10 ns136 0 -6.1450217446e-006 +Gc5_137 0 n10 ns137 0 -0.00220494875688 +Gc5_138 0 n10 ns138 0 0.0828173806834 +Gc5_139 0 n10 ns139 0 0.0141560034315 +Gc5_140 0 n10 ns140 0 -0.00454895644744 +Gc5_141 0 n10 ns141 0 0.00653828892257 +Gc5_142 0 n10 ns142 0 -2.43032497085e-005 +Gc5_143 0 n10 ns143 0 -0.000164748505853 +Gc5_144 0 n10 ns144 0 -0.00317984424987 +Gc5_145 0 n10 ns145 0 -1.67239218162e-007 +Gc5_146 0 n10 ns146 0 1.62730369131e-007 +Gc5_147 0 n10 ns147 0 -0.00366628202857 +Gc5_148 0 n10 ns148 0 -0.000745976555273 +Gc5_149 0 n10 ns149 0 5.35226526091e-007 +Gc5_150 0 n10 ns150 0 -9.13739170355e-007 +Gc5_151 0 n10 ns151 0 0.00169264001966 +Gc5_152 0 n10 ns152 0 0.00450522743599 +Gc5_153 0 n10 ns153 0 -0.00395581792311 +Gc5_154 0 n10 ns154 0 -0.00111765392146 +Gc5_155 0 n10 ns155 0 5.18215707692e-006 +Gc5_156 0 n10 ns156 0 -1.46116645355e-006 +Gc5_157 0 n10 ns157 0 0.000166262673833 +Gc5_158 0 n10 ns158 0 -0.00486837576797 +Gc5_159 0 n10 ns159 0 0.000229222746348 +Gc5_160 0 n10 ns160 0 -0.000251441320706 +Gc5_161 0 n10 ns161 0 -4.25776772651e-005 +Gc5_162 0 n10 ns162 0 5.76061287583e-005 +Gc5_163 0 n10 ns163 0 6.43774800774e-005 +Gc5_164 0 n10 ns164 0 -6.10627813877e-005 +Gc5_165 0 n10 ns165 0 0.00108022317515 +Gc5_166 0 n10 ns166 0 -0.000246069410014 +Gc5_167 0 n10 ns167 0 -0.00195478099055 +Gc5_168 0 n10 ns168 0 0.000712391292048 +Gd5_1 0 n10 ni1 0 -0.00040464105338 +Gd5_2 0 n10 ni2 0 -0.00305094361301 +Gd5_3 0 n10 ni3 0 -0.00220766764012 +Gd5_4 0 n10 ni4 0 -0.00212652331045 +Gd5_5 0 n10 ni5 0 0.00213266378452 +Gd5_6 0 n10 ni6 0 -0.000513933910145 +Gc6_1 0 n12 ns1 0 -0.00655982938402 +Gc6_2 0 n12 ns2 0 2.25562079352e-005 +Gc6_3 0 n12 ns3 0 0.000199361449669 +Gc6_4 0 n12 ns4 0 0.00372643560755 +Gc6_5 0 n12 ns5 0 -7.19465602456e-008 +Gc6_6 0 n12 ns6 0 -6.62773408382e-008 +Gc6_7 0 n12 ns7 0 0.00318926240959 +Gc6_8 0 n12 ns8 0 0.000550396177681 +Gc6_9 0 n12 ns9 0 3.96502630849e-007 +Gc6_10 0 n12 ns10 0 -2.61341580868e-007 +Gc6_11 0 n12 ns11 0 0.00235379875963 +Gc6_12 0 n12 ns12 0 -0.00352473744398 +Gc6_13 0 n12 ns13 0 -0.000464080266911 +Gc6_14 0 n12 ns14 0 -0.000673206038193 +Gc6_15 0 n12 ns15 0 2.14564291859e-007 +Gc6_16 0 n12 ns16 0 -1.23542653282e-006 +Gc6_17 0 n12 ns17 0 0.00167541232084 +Gc6_18 0 n12 ns18 0 0.00409624179423 +Gc6_19 0 n12 ns19 0 -0.000100615872824 +Gc6_20 0 n12 ns20 0 6.34123073071e-005 +Gc6_21 0 n12 ns21 0 8.93308122923e-005 +Gc6_22 0 n12 ns22 0 6.17641162405e-005 +Gc6_23 0 n12 ns23 0 -3.40542981954e-005 +Gc6_24 0 n12 ns24 0 -1.84432617696e-006 +Gc6_25 0 n12 ns25 0 -0.00504792977978 +Gc6_26 0 n12 ns26 0 -0.00619867654441 +Gc6_27 0 n12 ns27 0 -0.00186545671028 +Gc6_28 0 n12 ns28 0 0.00107412019216 +Gc6_29 0 n12 ns29 0 -0.00655896978633 +Gc6_30 0 n12 ns30 0 2.74310570323e-005 +Gc6_31 0 n12 ns31 0 0.000155087085706 +Gc6_32 0 n12 ns32 0 0.00323808917308 +Gc6_33 0 n12 ns33 0 3.85328860869e-008 +Gc6_34 0 n12 ns34 0 -2.81600491493e-007 +Gc6_35 0 n12 ns35 0 0.00362682849277 +Gc6_36 0 n12 ns36 0 0.000803142856821 +Gc6_37 0 n12 ns37 0 1.94886277107e-007 +Gc6_38 0 n12 ns38 0 6.58467115935e-007 +Gc6_39 0 n12 ns39 0 -0.00186738367514 +Gc6_40 0 n12 ns40 0 -0.00580928208596 +Gc6_41 0 n12 ns41 0 0.00468217961505 +Gc6_42 0 n12 ns42 0 0.0019275660513 +Gc6_43 0 n12 ns43 0 -5.95854698845e-006 +Gc6_44 0 n12 ns44 0 6.57083751763e-007 +Gc6_45 0 n12 ns45 0 -0.000277449965084 +Gc6_46 0 n12 ns46 0 0.0049727831562 +Gc6_47 0 n12 ns47 0 -0.000194067122861 +Gc6_48 0 n12 ns48 0 0.000229454548396 +Gc6_49 0 n12 ns49 0 2.77423544941e-005 +Gc6_50 0 n12 ns50 0 -6.06026663385e-005 +Gc6_51 0 n12 ns51 0 -7.20601581797e-005 +Gc6_52 0 n12 ns52 0 1.30322219866e-005 +Gc6_53 0 n12 ns53 0 -0.00654170628224 +Gc6_54 0 n12 ns54 0 -0.00354146412404 +Gc6_55 0 n12 ns55 0 -0.00148643928862 +Gc6_56 0 n12 ns56 0 -0.0023617863704 +Gc6_57 0 n12 ns57 0 -0.00658119083475 +Gc6_58 0 n12 ns58 0 -5.69209605924e-005 +Gc6_59 0 n12 ns59 0 -0.000367861252697 +Gc6_60 0 n12 ns60 0 -0.00698188588937 +Gc6_61 0 n12 ns61 0 -8.28940648877e-008 +Gc6_62 0 n12 ns62 0 3.23707549461e-007 +Gc6_63 0 n12 ns63 0 -0.00676314599837 +Gc6_64 0 n12 ns64 0 -0.00131107217926 +Gc6_65 0 n12 ns65 0 9.91538770752e-007 +Gc6_66 0 n12 ns66 0 -1.11003774493e-006 +Gc6_67 0 n12 ns67 0 -0.000433322995794 +Gc6_68 0 n12 ns68 0 0.013268047713 +Gc6_69 0 n12 ns69 0 -0.00565258812221 +Gc6_70 0 n12 ns70 0 -0.00273221318392 +Gc6_71 0 n12 ns71 0 4.35309766846e-006 +Gc6_72 0 n12 ns72 0 3.3971430579e-006 +Gc6_73 0 n12 ns73 0 -0.00256940642436 +Gc6_74 0 n12 ns74 0 0.00282706487592 +Gc6_75 0 n12 ns75 0 -1.47848246118e-005 +Gc6_76 0 n12 ns76 0 4.4037236704e-005 +Gc6_77 0 n12 ns77 0 -1.53878479227e-005 +Gc6_78 0 n12 ns78 0 -1.36896264205e-005 +Gc6_79 0 n12 ns79 0 -8.14701116203e-005 +Gc6_80 0 n12 ns80 0 3.59588139623e-005 +Gc6_81 0 n12 ns81 0 0.0175647148659 +Gc6_82 0 n12 ns82 0 -0.0158910864441 +Gc6_83 0 n12 ns83 0 -0.0128988448552 +Gc6_84 0 n12 ns84 0 0.0031882372702 +Gc6_85 0 n12 ns85 0 0.0065560244572 +Gc6_86 0 n12 ns86 0 -2.03461748233e-005 +Gc6_87 0 n12 ns87 0 -0.000206166596467 +Gc6_88 0 n12 ns88 0 -0.00367409692101 +Gc6_89 0 n12 ns89 0 -6.69925960317e-008 +Gc6_90 0 n12 ns90 0 2.36001724844e-008 +Gc6_91 0 n12 ns91 0 -0.00321208071485 +Gc6_92 0 n12 ns92 0 -0.000506827887369 +Gc6_93 0 n12 ns93 0 4.49678928137e-007 +Gc6_94 0 n12 ns94 0 -1.0816772544e-007 +Gc6_95 0 n12 ns95 0 -0.00136940616727 +Gc6_96 0 n12 ns96 0 0.00208814041038 +Gc6_97 0 n12 ns97 0 0.00048824678821 +Gc6_98 0 n12 ns98 0 0.00109060635919 +Gc6_99 0 n12 ns99 0 5.00791575192e-008 +Gc6_100 0 n12 ns100 0 -1.55391472746e-007 +Gc6_101 0 n12 ns101 0 -0.00145754365517 +Gc6_102 0 n12 ns102 0 -0.00381930259888 +Gc6_103 0 n12 ns103 0 9.4378660792e-005 +Gc6_104 0 n12 ns104 0 -7.40509419229e-005 +Gc6_105 0 n12 ns105 0 -8.41606976904e-005 +Gc6_106 0 n12 ns106 0 -3.15640050912e-005 +Gc6_107 0 n12 ns107 0 4.38603304463e-005 +Gc6_108 0 n12 ns108 0 -6.26453097915e-005 +Gc6_109 0 n12 ns109 0 -0.00108778552223 +Gc6_110 0 n12 ns110 0 0.000488304889814 +Gc6_111 0 n12 ns111 0 -0.00181469057599 +Gc6_112 0 n12 ns112 0 -0.001791989701 +Gc6_113 0 n12 ns113 0 0.00655465739527 +Gc6_114 0 n12 ns114 0 -2.52796559094e-005 +Gc6_115 0 n12 ns115 0 -0.000163349267026 +Gc6_116 0 n12 ns116 0 -0.00318489077823 +Gc6_117 0 n12 ns117 0 -1.70904829451e-007 +Gc6_118 0 n12 ns118 0 2.22780758828e-007 +Gc6_119 0 n12 ns119 0 -0.00366237380909 +Gc6_120 0 n12 ns120 0 -0.000743350356207 +Gc6_121 0 n12 ns121 0 5.2876051629e-007 +Gc6_122 0 n12 ns122 0 -9.16762934895e-007 +Gc6_123 0 n12 ns123 0 0.00169079234183 +Gc6_124 0 n12 ns124 0 0.0044994120148 +Gc6_125 0 n12 ns125 0 -0.00395347983379 +Gc6_126 0 n12 ns126 0 -0.00110983725541 +Gc6_127 0 n12 ns127 0 5.29653666094e-006 +Gc6_128 0 n12 ns128 0 -1.49060916094e-006 +Gc6_129 0 n12 ns129 0 0.000165738177827 +Gc6_130 0 n12 ns130 0 -0.00486678747909 +Gc6_131 0 n12 ns131 0 0.000229596722245 +Gc6_132 0 n12 ns132 0 -0.000251783135099 +Gc6_133 0 n12 ns133 0 -4.26399861217e-005 +Gc6_134 0 n12 ns134 0 5.7718310405e-005 +Gc6_135 0 n12 ns135 0 6.62638478283e-005 +Gc6_136 0 n12 ns136 0 -6.01883973998e-005 +Gc6_137 0 n12 ns137 0 0.00116471867389 +Gc6_138 0 n12 ns138 0 -0.000176800234612 +Gc6_139 0 n12 ns139 0 -0.00199182898319 +Gc6_140 0 n12 ns140 0 0.000724839573818 +Gc6_141 0 n12 ns141 0 0.00659653469582 +Gc6_142 0 n12 ns142 0 6.12790109712e-005 +Gc6_143 0 n12 ns143 0 0.000356837991787 +Gc6_144 0 n12 ns144 0 0.0069046556251 +Gc6_145 0 n12 ns145 0 1.37608384927e-007 +Gc6_146 0 n12 ns146 0 -2.15687109229e-007 +Gc6_147 0 n12 ns147 0 0.00676713290263 +Gc6_148 0 n12 ns148 0 0.00116459569632 +Gc6_149 0 n12 ns149 0 1.67559410726e-007 +Gc6_150 0 n12 ns150 0 4.73646833814e-007 +Gc6_151 0 n12 ns151 0 -0.000522369923793 +Gc6_152 0 n12 ns152 0 -0.0104835546484 +Gc6_153 0 n12 ns153 0 0.00543640528605 +Gc6_154 0 n12 ns154 0 0.00145853628768 +Gc6_155 0 n12 ns155 0 -4.06014019871e-006 +Gc6_156 0 n12 ns156 0 -3.60638815324e-006 +Gc6_157 0 n12 ns157 0 0.00255373853692 +Gc6_158 0 n12 ns158 0 -0.00288089588603 +Gc6_159 0 n12 ns159 0 8.41133990806e-006 +Gc6_160 0 n12 ns160 0 -2.7146314248e-005 +Gc6_161 0 n12 ns161 0 1.26515112408e-005 +Gc6_162 0 n12 ns162 0 -3.19529097514e-006 +Gc6_163 0 n12 ns163 0 -1.14027222063e-005 +Gc6_164 0 n12 ns164 0 1.17398829352e-005 +Gc6_165 0 n12 ns165 0 -0.0170733297891 +Gc6_166 0 n12 ns166 0 0.0386676336628 +Gc6_167 0 n12 ns167 0 0.0169383024628 +Gc6_168 0 n12 ns168 0 0.00505881827976 +Gd6_1 0 n12 ni1 0 -0.00152461211577 +Gd6_2 0 n12 ni2 0 -0.00217909209051 +Gd6_3 0 n12 ni3 0 -0.00103808147787 +Gd6_4 0 n12 ni4 0 -0.00128498344816 +Gd6_5 0 n12 ni5 0 -0.000500095925148 +Gd6_6 0 n12 ni6 0 0.000499817594082 +.ends + +.subckt 744837018220 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 56362389.9171 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 648445.068399 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 132325.203288 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 75380.4927534 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 17395.9525857 +Ca6 ns6 0 1e-012 +Ca7 ns7 0 1e-012 +Ra6 ns6 0 195980.609193 +Ra7 ns7 0 195980.609193 +Ga6 ns6 0 ns7 0 -0.000219832848874 +Ga7 ns7 0 ns6 0 0.000219832848874 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 14674.7861815 +Ra9 ns9 0 14674.7861815 +Ga8 ns8 0 ns9 0 -0.000289029739587 +Ga9 ns9 0 ns8 0 0.000289029739587 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 16300.0081787 +Ra11 ns11 0 16300.0081787 +Ga10 ns10 0 ns11 0 -0.000299317376673 +Ga11 ns11 0 ns10 0 0.000299317376673 +Ca12 ns12 0 1e-012 +Ra12 ns12 0 2850.31311002 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 12073.2782184 +Ra14 ns14 0 12073.2782184 +Ga13 ns13 0 ns14 0 -0.000350780676773 +Ga14 ns14 0 ns13 0 0.000350780676773 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 1761.33499314 +Ra16 ns16 0 1761.33499314 +Ga15 ns15 0 ns16 0 -0.000619871175394 +Ga16 ns16 0 ns15 0 0.000619871175394 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 11287.5812219 +Ra18 ns18 0 11287.5812219 +Ga17 ns17 0 ns18 0 -0.000913328218727 +Ga18 ns18 0 ns17 0 0.000913328218727 +Ca19 ns19 0 1e-012 +Ra19 ns19 0 56362389.9171 +Ca20 ns20 0 1e-012 +Ra20 ns20 0 648445.068399 +Ca21 ns21 0 1e-012 +Ra21 ns21 0 132325.203288 +Ca22 ns22 0 1e-012 +Ra22 ns22 0 75380.4927534 +Ca23 ns23 0 1e-012 +Ra23 ns23 0 17395.9525857 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 195980.609193 +Ra25 ns25 0 195980.609193 +Ga24 ns24 0 ns25 0 -0.000219832848874 +Ga25 ns25 0 ns24 0 0.000219832848874 +Ca26 ns26 0 1e-012 +Ca27 ns27 0 1e-012 +Ra26 ns26 0 14674.7861815 +Ra27 ns27 0 14674.7861815 +Ga26 ns26 0 ns27 0 -0.000289029739587 +Ga27 ns27 0 ns26 0 0.000289029739587 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 16300.0081787 +Ra29 ns29 0 16300.0081787 +Ga28 ns28 0 ns29 0 -0.000299317376673 +Ga29 ns29 0 ns28 0 0.000299317376673 +Ca30 ns30 0 1e-012 +Ra30 ns30 0 2850.31311002 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 12073.2782184 +Ra32 ns32 0 12073.2782184 +Ga31 ns31 0 ns32 0 -0.000350780676773 +Ga32 ns32 0 ns31 0 0.000350780676773 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 1761.33499314 +Ra34 ns34 0 1761.33499314 +Ga33 ns33 0 ns34 0 -0.000619871175394 +Ga34 ns34 0 ns33 0 0.000619871175394 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 11287.5812219 +Ra36 ns36 0 11287.5812219 +Ga35 ns35 0 ns36 0 -0.000913328218727 +Ga36 ns36 0 ns35 0 0.000913328218727 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 56362389.9171 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 648445.068399 +Ca39 ns39 0 1e-012 +Ra39 ns39 0 132325.203288 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 75380.4927534 +Ca41 ns41 0 1e-012 +Ra41 ns41 0 17395.9525857 +Ca42 ns42 0 1e-012 +Ca43 ns43 0 1e-012 +Ra42 ns42 0 195980.609193 +Ra43 ns43 0 195980.609193 +Ga42 ns42 0 ns43 0 -0.000219832848874 +Ga43 ns43 0 ns42 0 0.000219832848874 +Ca44 ns44 0 1e-012 +Ca45 ns45 0 1e-012 +Ra44 ns44 0 14674.7861815 +Ra45 ns45 0 14674.7861815 +Ga44 ns44 0 ns45 0 -0.000289029739587 +Ga45 ns45 0 ns44 0 0.000289029739587 +Ca46 ns46 0 1e-012 +Ca47 ns47 0 1e-012 +Ra46 ns46 0 16300.0081787 +Ra47 ns47 0 16300.0081787 +Ga46 ns46 0 ns47 0 -0.000299317376673 +Ga47 ns47 0 ns46 0 0.000299317376673 +Ca48 ns48 0 1e-012 +Ra48 ns48 0 2850.31311002 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 12073.2782184 +Ra50 ns50 0 12073.2782184 +Ga49 ns49 0 ns50 0 -0.000350780676773 +Ga50 ns50 0 ns49 0 0.000350780676773 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 1761.33499314 +Ra52 ns52 0 1761.33499314 +Ga51 ns51 0 ns52 0 -0.000619871175394 +Ga52 ns52 0 ns51 0 0.000619871175394 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 11287.5812219 +Ra54 ns54 0 11287.5812219 +Ga53 ns53 0 ns54 0 -0.000913328218727 +Ga54 ns54 0 ns53 0 0.000913328218727 +Ca55 ns55 0 1e-012 +Ra55 ns55 0 56362389.9171 +Ca56 ns56 0 1e-012 +Ra56 ns56 0 648445.068399 +Ca57 ns57 0 1e-012 +Ra57 ns57 0 132325.203288 +Ca58 ns58 0 1e-012 +Ra58 ns58 0 75380.4927534 +Ca59 ns59 0 1e-012 +Ra59 ns59 0 17395.9525857 +Ca60 ns60 0 1e-012 +Ca61 ns61 0 1e-012 +Ra60 ns60 0 195980.609193 +Ra61 ns61 0 195980.609193 +Ga60 ns60 0 ns61 0 -0.000219832848874 +Ga61 ns61 0 ns60 0 0.000219832848874 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 14674.7861815 +Ra63 ns63 0 14674.7861815 +Ga62 ns62 0 ns63 0 -0.000289029739587 +Ga63 ns63 0 ns62 0 0.000289029739587 +Ca64 ns64 0 1e-012 +Ca65 ns65 0 1e-012 +Ra64 ns64 0 16300.0081787 +Ra65 ns65 0 16300.0081787 +Ga64 ns64 0 ns65 0 -0.000299317376673 +Ga65 ns65 0 ns64 0 0.000299317376673 +Ca66 ns66 0 1e-012 +Ra66 ns66 0 2850.31311002 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 12073.2782184 +Ra68 ns68 0 12073.2782184 +Ga67 ns67 0 ns68 0 -0.000350780676773 +Ga68 ns68 0 ns67 0 0.000350780676773 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 1761.33499314 +Ra70 ns70 0 1761.33499314 +Ga69 ns69 0 ns70 0 -0.000619871175394 +Ga70 ns70 0 ns69 0 0.000619871175394 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 11287.5812219 +Ra72 ns72 0 11287.5812219 +Ga71 ns71 0 ns72 0 -0.000913328218727 +Ga72 ns72 0 ns71 0 0.000913328218727 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 56362389.9171 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 648445.068399 +Ca75 ns75 0 1e-012 +Ra75 ns75 0 132325.203288 +Ca76 ns76 0 1e-012 +Ra76 ns76 0 75380.4927534 +Ca77 ns77 0 1e-012 +Ra77 ns77 0 17395.9525857 +Ca78 ns78 0 1e-012 +Ca79 ns79 0 1e-012 +Ra78 ns78 0 195980.609193 +Ra79 ns79 0 195980.609193 +Ga78 ns78 0 ns79 0 -0.000219832848874 +Ga79 ns79 0 ns78 0 0.000219832848874 +Ca80 ns80 0 1e-012 +Ca81 ns81 0 1e-012 +Ra80 ns80 0 14674.7861815 +Ra81 ns81 0 14674.7861815 +Ga80 ns80 0 ns81 0 -0.000289029739587 +Ga81 ns81 0 ns80 0 0.000289029739587 +Ca82 ns82 0 1e-012 +Ca83 ns83 0 1e-012 +Ra82 ns82 0 16300.0081787 +Ra83 ns83 0 16300.0081787 +Ga82 ns82 0 ns83 0 -0.000299317376673 +Ga83 ns83 0 ns82 0 0.000299317376673 +Ca84 ns84 0 1e-012 +Ra84 ns84 0 2850.31311002 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 12073.2782184 +Ra86 ns86 0 12073.2782184 +Ga85 ns85 0 ns86 0 -0.000350780676773 +Ga86 ns86 0 ns85 0 0.000350780676773 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 1761.33499314 +Ra88 ns88 0 1761.33499314 +Ga87 ns87 0 ns88 0 -0.000619871175394 +Ga88 ns88 0 ns87 0 0.000619871175394 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 11287.5812219 +Ra90 ns90 0 11287.5812219 +Ga89 ns89 0 ns90 0 -0.000913328218727 +Ga90 ns90 0 ns89 0 0.000913328218727 +Ca91 ns91 0 1e-012 +Ra91 ns91 0 56362389.9171 +Ca92 ns92 0 1e-012 +Ra92 ns92 0 648445.068399 +Ca93 ns93 0 1e-012 +Ra93 ns93 0 132325.203288 +Ca94 ns94 0 1e-012 +Ra94 ns94 0 75380.4927534 +Ca95 ns95 0 1e-012 +Ra95 ns95 0 17395.9525857 +Ca96 ns96 0 1e-012 +Ca97 ns97 0 1e-012 +Ra96 ns96 0 195980.609193 +Ra97 ns97 0 195980.609193 +Ga96 ns96 0 ns97 0 -0.000219832848874 +Ga97 ns97 0 ns96 0 0.000219832848874 +Ca98 ns98 0 1e-012 +Ca99 ns99 0 1e-012 +Ra98 ns98 0 14674.7861815 +Ra99 ns99 0 14674.7861815 +Ga98 ns98 0 ns99 0 -0.000289029739587 +Ga99 ns99 0 ns98 0 0.000289029739587 +Ca100 ns100 0 1e-012 +Ca101 ns101 0 1e-012 +Ra100 ns100 0 16300.0081787 +Ra101 ns101 0 16300.0081787 +Ga100 ns100 0 ns101 0 -0.000299317376673 +Ga101 ns101 0 ns100 0 0.000299317376673 +Ca102 ns102 0 1e-012 +Ra102 ns102 0 2850.31311002 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 12073.2782184 +Ra104 ns104 0 12073.2782184 +Ga103 ns103 0 ns104 0 -0.000350780676773 +Ga104 ns104 0 ns103 0 0.000350780676773 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 1761.33499314 +Ra106 ns106 0 1761.33499314 +Ga105 ns105 0 ns106 0 -0.000619871175394 +Ga106 ns106 0 ns105 0 0.000619871175394 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 11287.5812219 +Ra108 ns108 0 11287.5812219 +Ga107 ns107 0 ns108 0 -0.000913328218727 +Ga108 ns108 0 ns107 0 0.000913328218727 + +Gb1_1 ns1 0 ni1 0 1.77423278443e-008 +Gb2_1 ns2 0 ni1 0 1.5421506751e-006 +Gb3_1 ns3 0 ni1 0 7.55713934423e-006 +Gb4_1 ns4 0 ni1 0 1.32660316147e-005 +Gb5_1 ns5 0 ni1 0 5.74846358701e-005 +Gb6_1 ns6 0 ni1 0 0.000219951284185 +Gb8_1 ns8 0 ni1 0 0.000305095966787 +Gb10_1 ns10 0 ni1 0 0.000311891925892 +Gb12_1 ns12 0 ni1 0 0.000350838648739 +Gb13_1 ns13 0 ni1 0 0.000370338202984 +Gb15_1 ns15 0 ni1 0 0.00113988469082 +Gb17_1 ns17 0 ni1 0 0.000921921743775 +Gb19_2 ns19 0 ni2 0 1.77423278443e-008 +Gb20_2 ns20 0 ni2 0 1.5421506751e-006 +Gb21_2 ns21 0 ni2 0 7.55713934423e-006 +Gb22_2 ns22 0 ni2 0 1.32660316147e-005 +Gb23_2 ns23 0 ni2 0 5.74846358701e-005 +Gb24_2 ns24 0 ni2 0 0.000219951284185 +Gb26_2 ns26 0 ni2 0 0.000305095966787 +Gb28_2 ns28 0 ni2 0 0.000311891925892 +Gb30_2 ns30 0 ni2 0 0.000350838648739 +Gb31_2 ns31 0 ni2 0 0.000370338202984 +Gb33_2 ns33 0 ni2 0 0.00113988469082 +Gb35_2 ns35 0 ni2 0 0.000921921743775 +Gb37_3 ns37 0 ni3 0 1.77423278443e-008 +Gb38_3 ns38 0 ni3 0 1.5421506751e-006 +Gb39_3 ns39 0 ni3 0 7.55713934423e-006 +Gb40_3 ns40 0 ni3 0 1.32660316147e-005 +Gb41_3 ns41 0 ni3 0 5.74846358701e-005 +Gb42_3 ns42 0 ni3 0 0.000219951284185 +Gb44_3 ns44 0 ni3 0 0.000305095966787 +Gb46_3 ns46 0 ni3 0 0.000311891925892 +Gb48_3 ns48 0 ni3 0 0.000350838648739 +Gb49_3 ns49 0 ni3 0 0.000370338202984 +Gb51_3 ns51 0 ni3 0 0.00113988469082 +Gb53_3 ns53 0 ni3 0 0.000921921743775 +Gb55_4 ns55 0 ni4 0 1.77423278443e-008 +Gb56_4 ns56 0 ni4 0 1.5421506751e-006 +Gb57_4 ns57 0 ni4 0 7.55713934423e-006 +Gb58_4 ns58 0 ni4 0 1.32660316147e-005 +Gb59_4 ns59 0 ni4 0 5.74846358701e-005 +Gb60_4 ns60 0 ni4 0 0.000219951284185 +Gb62_4 ns62 0 ni4 0 0.000305095966787 +Gb64_4 ns64 0 ni4 0 0.000311891925892 +Gb66_4 ns66 0 ni4 0 0.000350838648739 +Gb67_4 ns67 0 ni4 0 0.000370338202984 +Gb69_4 ns69 0 ni4 0 0.00113988469082 +Gb71_4 ns71 0 ni4 0 0.000921921743775 +Gb73_5 ns73 0 ni5 0 1.77423278443e-008 +Gb74_5 ns74 0 ni5 0 1.5421506751e-006 +Gb75_5 ns75 0 ni5 0 7.55713934423e-006 +Gb76_5 ns76 0 ni5 0 1.32660316147e-005 +Gb77_5 ns77 0 ni5 0 5.74846358701e-005 +Gb78_5 ns78 0 ni5 0 0.000219951284185 +Gb80_5 ns80 0 ni5 0 0.000305095966787 +Gb82_5 ns82 0 ni5 0 0.000311891925892 +Gb84_5 ns84 0 ni5 0 0.000350838648739 +Gb85_5 ns85 0 ni5 0 0.000370338202984 +Gb87_5 ns87 0 ni5 0 0.00113988469082 +Gb89_5 ns89 0 ni5 0 0.000921921743775 +Gb91_6 ns91 0 ni6 0 1.77423278443e-008 +Gb92_6 ns92 0 ni6 0 1.5421506751e-006 +Gb93_6 ns93 0 ni6 0 7.55713934423e-006 +Gb94_6 ns94 0 ni6 0 1.32660316147e-005 +Gb95_6 ns95 0 ni6 0 5.74846358701e-005 +Gb96_6 ns96 0 ni6 0 0.000219951284185 +Gb98_6 ns98 0 ni6 0 0.000305095966787 +Gb100_6 ns100 0 ni6 0 0.000311891925892 +Gb102_6 ns102 0 ni6 0 0.000350838648739 +Gb103_6 ns103 0 ni6 0 0.000370338202984 +Gb105_6 ns105 0 ni6 0 0.00113988469082 +Gb107_6 ns107 0 ni6 0 0.000921921743775 + +Gc1_1 0 n2 ns1 0 0.00654190386672 +Gc1_2 0 n2 ns2 0 0.000154458487483 +Gc1_3 0 n2 ns3 0 0.00726945768953 +Gc1_4 0 n2 ns4 0 0.00601811035686 +Gc1_5 0 n2 ns5 0 0.000532277582208 +Gc1_6 0 n2 ns6 0 7.00648243038e-007 +Gc1_7 0 n2 ns7 0 -7.98227076422e-007 +Gc1_8 0 n2 ns8 0 0.00625250656969 +Gc1_9 0 n2 ns9 0 -0.000806123674481 +Gc1_10 0 n2 ns10 0 0.000297566467897 +Gc1_11 0 n2 ns11 0 -0.00205113812848 +Gc1_12 0 n2 ns12 0 -0.00345240742776 +Gc1_13 0 n2 ns13 0 0.00161497548916 +Gc1_14 0 n2 ns14 0 -0.00137327574927 +Gc1_15 0 n2 ns15 0 0.00234601557389 +Gc1_16 0 n2 ns16 0 0.0276672690061 +Gc1_17 0 n2 ns17 0 0.00118058557947 +Gc1_18 0 n2 ns18 0 -0.0024531087678 +Gc1_19 0 n2 ns19 0 0.00644011804988 +Gc1_20 0 n2 ns20 0 -7.00384623875e-005 +Gc1_21 0 n2 ns21 0 -0.00335092030962 +Gc1_22 0 n2 ns22 0 -0.00330253131782 +Gc1_23 0 n2 ns23 0 -0.000261644405839 +Gc1_24 0 n2 ns24 0 5.45850155447e-007 +Gc1_25 0 n2 ns25 0 -5.01631076014e-007 +Gc1_26 0 n2 ns26 0 -0.00169204861732 +Gc1_27 0 n2 ns27 0 0.000387294396428 +Gc1_28 0 n2 ns28 0 -0.00103948082363 +Gc1_29 0 n2 ns29 0 0.000887836507353 +Gc1_30 0 n2 ns30 0 -0.000162068921729 +Gc1_31 0 n2 ns31 0 0.00225868435136 +Gc1_32 0 n2 ns32 0 -0.0019230977155 +Gc1_33 0 n2 ns33 0 -0.000975370586532 +Gc1_34 0 n2 ns34 0 -0.000959187404956 +Gc1_35 0 n2 ns35 0 -0.00021982554098 +Gc1_36 0 n2 ns36 0 0.000709860876741 +Gc1_37 0 n2 ns37 0 0.0064374681679 +Gc1_38 0 n2 ns38 0 -8.74043027508e-005 +Gc1_39 0 n2 ns39 0 -0.00392739632711 +Gc1_40 0 n2 ns40 0 -0.00269562617528 +Gc1_41 0 n2 ns41 0 -0.000254491014936 +Gc1_42 0 n2 ns42 0 6.88750813685e-007 +Gc1_43 0 n2 ns43 0 -5.18857797267e-007 +Gc1_44 0 n2 ns44 0 -0.00332370205214 +Gc1_45 0 n2 ns45 0 -0.000391529781912 +Gc1_46 0 n2 ns46 0 0.00104558015622 +Gc1_47 0 n2 ns47 0 0.0013361149256 +Gc1_48 0 n2 ns48 0 -0.000165743236358 +Gc1_49 0 n2 ns49 0 0.00177559441977 +Gc1_50 0 n2 ns50 0 -0.00153037448243 +Gc1_51 0 n2 ns51 0 -0.00105576229744 +Gc1_52 0 n2 ns52 0 -0.00105804020965 +Gc1_53 0 n2 ns53 0 -0.000188521144409 +Gc1_54 0 n2 ns54 0 0.00068797330815 +Gc1_55 0 n2 ns55 0 -0.00654028813411 +Gc1_56 0 n2 ns56 0 -0.00015450554192 +Gc1_57 0 n2 ns57 0 -0.00724330677361 +Gc1_58 0 n2 ns58 0 -0.0060475549328 +Gc1_59 0 n2 ns59 0 -0.000551442811615 +Gc1_60 0 n2 ns60 0 5.24285207626e-007 +Gc1_61 0 n2 ns61 0 -1.5183229357e-007 +Gc1_62 0 n2 ns62 0 -0.00481077832497 +Gc1_63 0 n2 ns63 0 0.000692520434164 +Gc1_64 0 n2 ns64 0 -0.000199752220809 +Gc1_65 0 n2 ns65 0 0.00176811433813 +Gc1_66 0 n2 ns66 0 0.0007770745991 +Gc1_67 0 n2 ns67 0 -0.00168787403759 +Gc1_68 0 n2 ns68 0 0.00151410487288 +Gc1_69 0 n2 ns69 0 -0.0035917852979 +Gc1_70 0 n2 ns70 0 -0.00711100440193 +Gc1_71 0 n2 ns71 0 -0.000120958190147 +Gc1_72 0 n2 ns72 0 0.000492991504626 +Gc1_73 0 n2 ns73 0 -0.00644126215756 +Gc1_74 0 n2 ns74 0 6.8527335903e-005 +Gc1_75 0 n2 ns75 0 0.0033554978599 +Gc1_76 0 n2 ns76 0 0.00327595470321 +Gc1_77 0 n2 ns77 0 0.000292308087642 +Gc1_78 0 n2 ns78 0 4.56230101901e-007 +Gc1_79 0 n2 ns79 0 6.37741962705e-008 +Gc1_80 0 n2 ns80 0 0.000927713688526 +Gc1_81 0 n2 ns81 0 -0.000154311870269 +Gc1_82 0 n2 ns82 0 0.000825787800774 +Gc1_83 0 n2 ns83 0 -0.000888581035635 +Gc1_84 0 n2 ns84 0 -4.52559834271e-005 +Gc1_85 0 n2 ns85 0 -0.00204381698539 +Gc1_86 0 n2 ns86 0 0.00186918154011 +Gc1_87 0 n2 ns87 0 -0.00112917525761 +Gc1_88 0 n2 ns88 0 -0.00154411789103 +Gc1_89 0 n2 ns89 0 -0.000303331090931 +Gc1_90 0 n2 ns90 0 0.000590189343978 +Gc1_91 0 n2 ns91 0 -0.00643943688627 +Gc1_92 0 n2 ns92 0 8.77897534031e-005 +Gc1_93 0 n2 ns93 0 0.00391800924799 +Gc1_94 0 n2 ns94 0 0.00269093450677 +Gc1_95 0 n2 ns95 0 0.000260254756054 +Gc1_96 0 n2 ns96 0 4.03356339667e-007 +Gc1_97 0 n2 ns97 0 -2.52174807505e-007 +Gc1_98 0 n2 ns98 0 0.00264399156067 +Gc1_99 0 n2 ns99 0 0.000228954523035 +Gc1_100 0 n2 ns100 0 -0.000787932135849 +Gc1_101 0 n2 ns101 0 -0.00103413373632 +Gc1_102 0 n2 ns102 0 0.000118329551281 +Gc1_103 0 n2 ns103 0 -0.0018074047761 +Gc1_104 0 n2 ns104 0 0.00156044078036 +Gc1_105 0 n2 ns105 0 -0.00166179670217 +Gc1_106 0 n2 ns106 0 -0.00165329326499 +Gc1_107 0 n2 ns107 0 -0.000181455222034 +Gc1_108 0 n2 ns108 0 0.000692663619842 +Gd1_1 0 n2 ni1 0 0.000388501937604 +Gd1_2 0 n2 ni2 0 -0.000642915180975 +Gd1_3 0 n2 ni3 0 -0.00071084173533 +Gd1_4 0 n2 ni4 0 -0.00216347283914 +Gd1_5 0 n2 ni5 0 -0.000679355852152 +Gd1_6 0 n2 ni6 0 -0.000818494728389 +Gc2_1 0 n4 ns1 0 0.0064404927457 +Gc2_2 0 n4 ns2 0 -7.00861562444e-005 +Gc2_3 0 n4 ns3 0 -0.00335172500551 +Gc2_4 0 n4 ns4 0 -0.00330111332712 +Gc2_5 0 n4 ns5 0 -0.000259405728232 +Gc2_6 0 n4 ns6 0 5.44811884615e-007 +Gc2_7 0 n4 ns7 0 -4.90027009057e-007 +Gc2_8 0 n4 ns8 0 -0.00169451191978 +Gc2_9 0 n4 ns9 0 0.000386952275649 +Gc2_10 0 n4 ns10 0 -0.00103640226859 +Gc2_11 0 n4 ns11 0 0.000885896756605 +Gc2_12 0 n4 ns12 0 -0.000171274491914 +Gc2_13 0 n4 ns13 0 0.00225789764029 +Gc2_14 0 n4 ns14 0 -0.00192101320505 +Gc2_15 0 n4 ns15 0 -0.000978397347468 +Gc2_16 0 n4 ns16 0 -0.000969484340703 +Gc2_17 0 n4 ns17 0 -0.0002157723343 +Gc2_18 0 n4 ns18 0 0.000707706180916 +Gc2_19 0 n4 ns19 0 0.00652998850096 +Gc2_20 0 n4 ns20 0 0.000160506769347 +Gc2_21 0 n4 ns21 0 0.00745220531814 +Gc2_22 0 n4 ns22 0 0.00585954421831 +Gc2_23 0 n4 ns23 0 0.000574509137875 +Gc2_24 0 n4 ns24 0 9.46067900682e-007 +Gc2_25 0 n4 ns25 0 -6.64352445245e-007 +Gc2_26 0 n4 ns26 0 0.00157444997112 +Gc2_27 0 n4 ns27 0 -0.00158820857383 +Gc2_28 0 n4 ns28 0 0.00339513157706 +Gc2_29 0 n4 ns29 0 -0.000915659142185 +Gc2_30 0 n4 ns30 0 -0.00448603753231 +Gc2_31 0 n4 ns31 0 0.00277260388443 +Gc2_32 0 n4 ns32 0 -0.00304996942227 +Gc2_33 0 n4 ns33 0 0.00579491483315 +Gc2_34 0 n4 ns34 0 0.0294818297121 +Gc2_35 0 n4 ns35 0 0.000901942642323 +Gc2_36 0 n4 ns36 0 -0.00202420139841 +Gc2_37 0 n4 ns37 0 0.00643767488425 +Gc2_38 0 n4 ns38 0 -9.16573285621e-005 +Gc2_39 0 n4 ns39 0 -0.00405120045959 +Gc2_40 0 n4 ns40 0 -0.00257207730609 +Gc2_41 0 n4 ns41 0 -0.000260852291698 +Gc2_42 0 n4 ns42 0 5.10138153239e-007 +Gc2_43 0 n4 ns43 0 -4.12332046567e-007 +Gc2_44 0 n4 ns44 0 6.06357701928e-005 +Gc2_45 0 n4 ns45 0 0.00100881832932 +Gc2_46 0 n4 ns46 0 -0.00294580302858 +Gc2_47 0 n4 ns47 0 0.00070728380408 +Gc2_48 0 n4 ns48 0 4.78222340472e-005 +Gc2_49 0 n4 ns49 0 0.00235836852743 +Gc2_50 0 n4 ns50 0 -0.00225638486488 +Gc2_51 0 n4 ns51 0 -0.00079277733329 +Gc2_52 0 n4 ns52 0 -0.000640281603111 +Gc2_53 0 n4 ns53 0 -0.0002573317763 +Gc2_54 0 n4 ns54 0 0.000616715175931 +Gc2_55 0 n4 ns55 0 -0.00643815494087 +Gc2_56 0 n4 ns56 0 6.81852903588e-005 +Gc2_57 0 n4 ns57 0 0.00336552662664 +Gc2_58 0 n4 ns58 0 0.00327630518463 +Gc2_59 0 n4 ns59 0 0.000283344745933 +Gc2_60 0 n4 ns60 0 4.60143954044e-007 +Gc2_61 0 n4 ns61 0 -1.46813615724e-007 +Gc2_62 0 n4 ns62 0 0.00126286175496 +Gc2_63 0 n4 ns63 0 -0.000266134681124 +Gc2_64 0 n4 ns64 0 0.000980626181639 +Gc2_65 0 n4 ns65 0 -0.000897091380801 +Gc2_66 0 n4 ns66 0 3.19314671682e-005 +Gc2_67 0 n4 ns67 0 -0.0022622538191 +Gc2_68 0 n4 ns68 0 0.0019887752681 +Gc2_69 0 n4 ns69 0 -0.00175401125701 +Gc2_70 0 n4 ns70 0 -0.00173258413184 +Gc2_71 0 n4 ns71 0 -0.00025694292757 +Gc2_72 0 n4 ns72 0 0.000490130343515 +Gc2_73 0 n4 ns73 0 -0.00653939140522 +Gc2_74 0 n4 ns74 0 -0.00015642720856 +Gc2_75 0 n4 ns75 0 -0.00742326965497 +Gc2_76 0 n4 ns76 0 -0.00588708300149 +Gc2_77 0 n4 ns77 0 -0.000559307623082 +Gc2_78 0 n4 ns78 0 3.26379899529e-007 +Gc2_79 0 n4 ns79 0 2.49103023629e-007 +Gc2_80 0 n4 ns80 0 -0.00120996918942 +Gc2_81 0 n4 ns81 0 0.00144754358949 +Gc2_82 0 n4 ns82 0 -0.00256301530009 +Gc2_83 0 n4 ns83 0 0.00066588119086 +Gc2_84 0 n4 ns84 0 0.00139514983003 +Gc2_85 0 n4 ns85 0 -0.00254633627483 +Gc2_86 0 n4 ns86 0 0.00295427472676 +Gc2_87 0 n4 ns87 0 -0.0065550472798 +Gc2_88 0 n4 ns88 0 -0.00941476325659 +Gc2_89 0 n4 ns89 0 0.000349776216386 +Gc2_90 0 n4 ns90 0 0.000765361280864 +Gc2_91 0 n4 ns91 0 -0.0064391233931 +Gc2_92 0 n4 ns92 0 9.15449955682e-005 +Gc2_93 0 n4 ns93 0 0.004043144975 +Gc2_94 0 n4 ns94 0 0.0025605434509 +Gc2_95 0 n4 ns95 0 0.000274201550649 +Gc2_96 0 n4 ns96 0 5.69764673309e-007 +Gc2_97 0 n4 ns97 0 -2.38177752502e-007 +Gc2_98 0 n4 ns98 0 -0.00019172673468 +Gc2_99 0 n4 ns99 0 -0.000740027564265 +Gc2_100 0 n4 ns100 0 0.00232107828841 +Gc2_101 0 n4 ns101 0 -0.000689297808436 +Gc2_102 0 n4 ns102 0 -0.000134689901542 +Gc2_103 0 n4 ns103 0 -0.00236858214429 +Gc2_104 0 n4 ns104 0 0.00228485159239 +Gc2_105 0 n4 ns105 0 -0.0015044501268 +Gc2_106 0 n4 ns106 0 -0.00165531553495 +Gc2_107 0 n4 ns107 0 -0.000353605220062 +Gc2_108 0 n4 ns108 0 0.000347173892906 +Gd2_1 0 n4 ni1 0 -0.00064027206834 +Gd2_2 0 n4 ni2 0 0.00143809131357 +Gd2_3 0 n4 ni3 0 -0.000549510919187 +Gd2_4 0 n4 ni4 0 -0.000824389290755 +Gd2_5 0 n4 ni5 0 -0.00314560446906 +Gd2_6 0 n4 ni6 0 -0.000847371905671 +Gc3_1 0 n6 ns1 0 0.0064365294713 +Gc3_2 0 n6 ns2 0 -8.73643474342e-005 +Gc3_3 0 n6 ns3 0 -0.00392805203223 +Gc3_4 0 n6 ns4 0 -0.00269448863333 +Gc3_5 0 n6 ns5 0 -0.00025204857303 +Gc3_6 0 n6 ns6 0 6.86241713198e-007 +Gc3_7 0 n6 ns7 0 -5.03126208202e-007 +Gc3_8 0 n6 ns8 0 -0.0033228149613 +Gc3_9 0 n6 ns9 0 -0.000381495333041 +Gc3_10 0 n6 ns10 0 0.00104154384242 +Gc3_11 0 n6 ns11 0 0.0013267118222 +Gc3_12 0 n6 ns12 0 -0.000173490662406 +Gc3_13 0 n6 ns13 0 0.00177570038791 +Gc3_14 0 n6 ns14 0 -0.00153279760768 +Gc3_15 0 n6 ns15 0 -0.0010312483295 +Gc3_16 0 n6 ns16 0 -0.00106484251014 +Gc3_17 0 n6 ns17 0 -0.000181956259597 +Gc3_18 0 n6 ns18 0 0.000694218585165 +Gc3_19 0 n6 ns19 0 0.00643170881193 +Gc3_20 0 n6 ns20 0 -9.15364392305e-005 +Gc3_21 0 n6 ns21 0 -0.00405210367957 +Gc3_22 0 n6 ns22 0 -0.00257072756957 +Gc3_23 0 n6 ns23 0 -0.000257885286266 +Gc3_24 0 n6 ns24 0 5.07956355975e-007 +Gc3_25 0 n6 ns25 0 -3.94939275814e-007 +Gc3_26 0 n6 ns26 0 6.48031576384e-005 +Gc3_27 0 n6 ns27 0 0.00101778532277 +Gc3_28 0 n6 ns28 0 -0.00295132270822 +Gc3_29 0 n6 ns29 0 0.000701562640715 +Gc3_30 0 n6 ns30 0 1.72156766616e-005 +Gc3_31 0 n6 ns31 0 0.0023550884231 +Gc3_32 0 n6 ns32 0 -0.00225813255598 +Gc3_33 0 n6 ns33 0 -0.00083083476626 +Gc3_34 0 n6 ns34 0 -0.000674636134513 +Gc3_35 0 n6 ns35 0 -0.000253322982709 +Gc3_36 0 n6 ns36 0 0.000602358255257 +Gc3_37 0 n6 ns37 0 0.00652878433241 +Gc3_38 0 n6 ns38 0 0.000179005037297 +Gc3_39 0 n6 ns39 0 0.00800019367371 +Gc3_40 0 n6 ns40 0 0.00527031835203 +Gc3_41 0 n6 ns41 0 0.000542237790216 +Gc3_42 0 n6 ns42 0 8.08974593868e-007 +Gc3_43 0 n6 ns43 0 -6.8709289165e-007 +Gc3_44 0 n6 ns44 0 0.00334130143854 +Gc3_45 0 n6 ns45 0 -0.00140620644438 +Gc3_46 0 n6 ns46 0 0.0026696456581 +Gc3_47 0 n6 ns47 0 -0.00130433975083 +Gc3_48 0 n6 ns48 0 -0.00440431194048 +Gc3_49 0 n6 ns49 0 0.0016720222389 +Gc3_50 0 n6 ns50 0 -0.00192834521838 +Gc3_51 0 n6 ns51 0 0.00469691580982 +Gc3_52 0 n6 ns52 0 0.0281693007686 +Gc3_53 0 n6 ns53 0 0.00109407754558 +Gc3_54 0 n6 ns54 0 -0.00180265005562 +Gc3_55 0 n6 ns55 0 -0.00643610153331 +Gc3_56 0 n6 ns56 0 8.6689791733e-005 +Gc3_57 0 n6 ns57 0 0.00392986237082 +Gc3_58 0 n6 ns58 0 0.00268275867312 +Gc3_59 0 n6 ns59 0 0.000259877362876 +Gc3_60 0 n6 ns60 0 2.90507100869e-007 +Gc3_61 0 n6 ns61 0 1.7127335964e-008 +Gc3_62 0 n6 ns62 0 0.00246563032326 +Gc3_63 0 n6 ns63 0 0.000217599508513 +Gc3_64 0 n6 ns64 0 -0.000897372767691 +Gc3_65 0 n6 ns65 0 -0.00103312328828 +Gc3_66 0 n6 ns66 0 0.000137840552821 +Gc3_67 0 n6 ns67 0 -0.00177312733269 +Gc3_68 0 n6 ns68 0 0.00166851839502 +Gc3_69 0 n6 ns69 0 -0.0014150011215 +Gc3_70 0 n6 ns70 0 -0.00136500260162 +Gc3_71 0 n6 ns71 0 -0.000299466920631 +Gc3_72 0 n6 ns72 0 0.000451035741696 +Gc3_73 0 n6 ns73 0 -0.00643335029158 +Gc3_74 0 n6 ns74 0 9.03214012742e-005 +Gc3_75 0 n6 ns75 0 0.00406151416969 +Gc3_76 0 n6 ns76 0 0.00255227585436 +Gc3_77 0 n6 ns77 0 0.000280021894308 +Gc3_78 0 n6 ns78 0 4.5797821131e-007 +Gc3_79 0 n6 ns79 0 1.54768865738e-007 +Gc3_80 0 n6 ns80 0 -0.000206470014471 +Gc3_81 0 n6 ns81 0 -0.000672489431468 +Gc3_82 0 n6 ns82 0 0.00241080038009 +Gc3_83 0 n6 ns83 0 -0.00091460783087 +Gc3_84 0 n6 ns84 0 -2.4635730621e-005 +Gc3_85 0 n6 ns85 0 -0.00209922524225 +Gc3_86 0 n6 ns86 0 0.00223231005014 +Gc3_87 0 n6 ns87 0 -0.00186949673136 +Gc3_88 0 n6 ns88 0 -0.00156379621907 +Gc3_89 0 n6 ns89 0 -0.000246038310216 +Gc3_90 0 n6 ns90 0 0.000416465004709 +Gc3_91 0 n6 ns91 0 -0.0065354340538 +Gc3_92 0 n6 ns92 0 -0.000173711114095 +Gc3_93 0 n6 ns93 0 -0.00798721098694 +Gc3_94 0 n6 ns94 0 -0.00526741975276 +Gc3_95 0 n6 ns95 0 -0.000576790856945 +Gc3_96 0 n6 ns96 0 2.93316206177e-007 +Gc3_97 0 n6 ns97 0 -2.85343927943e-007 +Gc3_98 0 n6 ns98 0 -0.00247076620485 +Gc3_99 0 n6 ns99 0 0.000809402914217 +Gc3_100 0 n6 ns100 0 -0.00197496234289 +Gc3_101 0 n6 ns101 0 0.00139542557978 +Gc3_102 0 n6 ns102 0 0.0013885087776 +Gc3_103 0 n6 ns103 0 -0.00178396771877 +Gc3_104 0 n6 ns104 0 0.00207751770154 +Gc3_105 0 n6 ns105 0 -0.00451600811557 +Gc3_106 0 n6 ns106 0 -0.00698512199501 +Gc3_107 0 n6 ns107 0 -0.000119715566756 +Gc3_108 0 n6 ns108 0 0.000267592503106 +Gd3_1 0 n6 ni1 0 -0.000691863111761 +Gd3_2 0 n6 ni2 0 -0.000565968990185 +Gd3_3 0 n6 ni3 0 0.000663271690897 +Gd3_4 0 n6 ni4 0 -0.000787406482469 +Gd3_5 0 n6 ni5 0 -0.000922817104825 +Gd3_6 0 n6 ni6 0 -0.00245299970753 +Gc4_1 0 n8 ns1 0 -0.00653976279899 +Gc4_2 0 n8 ns2 0 -0.000154180009127 +Gc4_3 0 n8 ns3 0 -0.00724828690436 +Gc4_4 0 n8 ns4 0 -0.00604928140396 +Gc4_5 0 n8 ns5 0 -0.000539408067411 +Gc4_6 0 n8 ns6 0 5.39976852287e-007 +Gc4_7 0 n8 ns7 0 -1.08372492951e-007 +Gc4_8 0 n8 ns8 0 -0.00481470468041 +Gc4_9 0 n8 ns9 0 0.000734364412596 +Gc4_10 0 n8 ns10 0 -0.000210820257792 +Gc4_11 0 n8 ns11 0 0.00173062253795 +Gc4_12 0 n8 ns12 0 0.000700718913291 +Gc4_13 0 n8 ns13 0 -0.00168235667778 +Gc4_14 0 n8 ns14 0 0.00150036372202 +Gc4_15 0 n8 ns15 0 -0.00359695707111 +Gc4_16 0 n8 ns16 0 -0.00719285558719 +Gc4_17 0 n8 ns17 0 -9.27154189694e-005 +Gc4_18 0 n8 ns18 0 0.000490678741218 +Gc4_19 0 n8 ns19 0 -0.00644350132605 +Gc4_20 0 n8 ns20 0 6.80775369147e-005 +Gc4_21 0 n8 ns21 0 0.00336708099064 +Gc4_22 0 n8 ns22 0 0.00327699387588 +Gc4_23 0 n8 ns23 0 0.000284669873936 +Gc4_24 0 n8 ns24 0 4.8567062447e-007 +Gc4_25 0 n8 ns25 0 -1.3361985699e-007 +Gc4_26 0 n8 ns26 0 0.0012624659157 +Gc4_27 0 n8 ns27 0 -0.000245890323088 +Gc4_28 0 n8 ns28 0 0.000972221809358 +Gc4_29 0 n8 ns29 0 -0.000913498290659 +Gc4_30 0 n8 ns30 0 1.61264254494e-005 +Gc4_31 0 n8 ns31 0 -0.00225973806353 +Gc4_32 0 n8 ns32 0 0.0019829138601 +Gc4_33 0 n8 ns33 0 -0.00174306851148 +Gc4_34 0 n8 ns34 0 -0.00174440372427 +Gc4_35 0 n8 ns35 0 -0.000257983052399 +Gc4_36 0 n8 ns36 0 0.000495055153401 +Gc4_37 0 n8 ns37 0 -0.00644076526764 +Gc4_38 0 n8 ns38 0 8.645328439e-005 +Gc4_39 0 n8 ns39 0 0.00393246625317 +Gc4_40 0 n8 ns40 0 0.00268320046177 +Gc4_41 0 n8 ns41 0 0.000257898843836 +Gc4_42 0 n8 ns42 0 2.93892171173e-007 +Gc4_43 0 n8 ns43 0 1.17909788078e-008 +Gc4_44 0 n8 ns44 0 0.00247859194078 +Gc4_45 0 n8 ns45 0 0.000212500168613 +Gc4_46 0 n8 ns46 0 -0.000903455209766 +Gc4_47 0 n8 ns47 0 -0.0010221813516 +Gc4_48 0 n8 ns48 0 0.000112316099911 +Gc4_49 0 n8 ns49 0 -0.00178090474238 +Gc4_50 0 n8 ns50 0 0.00167155108823 +Gc4_51 0 n8 ns51 0 -0.00149334146327 +Gc4_52 0 n8 ns52 0 -0.00141294793371 +Gc4_53 0 n8 ns53 0 -0.000295554442167 +Gc4_54 0 n8 ns54 0 0.000430961079327 +Gc4_55 0 n8 ns55 0 0.00651439994191 +Gc4_56 0 n8 ns56 0 0.000153209770976 +Gc4_57 0 n8 ns57 0 0.00726235070654 +Gc4_58 0 n8 ns58 0 0.00598629289098 +Gc4_59 0 n8 ns59 0 0.00051982116462 +Gc4_60 0 n8 ns60 0 5.39890382458e-007 +Gc4_61 0 n8 ns61 0 -1.69359060282e-007 +Gc4_62 0 n8 ns62 0 0.00406892424189 +Gc4_63 0 n8 ns63 0 -0.00091389730893 +Gc4_64 0 n8 ns64 0 6.59635426179e-005 +Gc4_65 0 n8 ns65 0 -0.00111963922288 +Gc4_66 0 n8 ns66 0 -0.00407925149234 +Gc4_67 0 n8 ns67 0 0.00163973330594 +Gc4_68 0 n8 ns68 0 -0.00137266224534 +Gc4_69 0 n8 ns69 0 0.00715262842412 +Gc4_70 0 n8 ns70 0 0.0272033346801 +Gc4_71 0 n8 ns71 0 0.00131853538235 +Gc4_72 0 n8 ns72 0 -0.000962941877093 +Gc4_73 0 n8 ns73 0 0.00644558208807 +Gc4_74 0 n8 ns74 0 -6.94346164776e-005 +Gc4_75 0 n8 ns75 0 -0.00334273861234 +Gc4_76 0 n8 ns76 0 -0.0032902969653 +Gc4_77 0 n8 ns77 0 -0.000254257445009 +Gc4_78 0 n8 ns78 0 3.02664819506e-007 +Gc4_79 0 n8 ns79 0 1.0364921341e-007 +Gc4_80 0 n8 ns80 0 -0.00108599387425 +Gc4_81 0 n8 ns81 0 0.000318911310855 +Gc4_82 0 n8 ns82 0 -0.00052434053901 +Gc4_83 0 n8 ns83 0 0.00049796740551 +Gc4_84 0 n8 ns84 0 0.000139757222764 +Gc4_85 0 n8 ns85 0 0.00223195449526 +Gc4_86 0 n8 ns86 0 -0.00190026395789 +Gc4_87 0 n8 ns87 0 -0.00303500219069 +Gc4_88 0 n8 ns88 0 -0.000698926823909 +Gc4_89 0 n8 ns89 0 -0.000272013109389 +Gc4_90 0 n8 ns90 0 0.000203601291327 +Gc4_91 0 n8 ns91 0 0.0064431792127 +Gc4_92 0 n8 ns92 0 -8.67551055118e-005 +Gc4_93 0 n8 ns93 0 -0.00392078221793 +Gc4_94 0 n8 ns94 0 -0.00267857941446 +Gc4_95 0 n8 ns95 0 -0.000256289103698 +Gc4_96 0 n8 ns96 0 3.54435896551e-007 +Gc4_97 0 n8 ns97 0 -2.60318010407e-007 +Gc4_98 0 n8 ns98 0 -0.00208279797587 +Gc4_99 0 n8 ns99 0 -0.000314172682199 +Gc4_100 0 n8 ns100 0 0.000882746515222 +Gc4_101 0 n8 ns101 0 0.00090168389516 +Gc4_102 0 n8 ns102 0 0.000146084423734 +Gc4_103 0 n8 ns103 0 0.00182266927527 +Gc4_104 0 n8 ns104 0 -0.00153372374506 +Gc4_105 0 n8 ns105 0 -0.00331874344704 +Gc4_106 0 n8 ns106 0 -0.000948112320748 +Gc4_107 0 n8 ns107 0 -0.000258720987188 +Gc4_108 0 n8 ns108 0 0.00018501026531 +Gd4_1 0 n8 ni1 0 -0.00214190280768 +Gd4_2 0 n8 ni2 0 -0.000821272335329 +Gd4_3 0 n8 ni3 0 -0.000826191527124 +Gd4_4 0 n8 ni4 0 0.00171421230215 +Gd4_5 0 n8 ni5 0 -0.00128280865498 +Gd4_6 0 n8 ni6 0 -0.00143422278303 +Gc5_1 0 n10 ns1 0 -0.00644473492067 +Gc5_2 0 n10 ns2 0 6.85905287937e-005 +Gc5_3 0 n10 ns3 0 0.00335803473365 +Gc5_4 0 n10 ns4 0 0.00327599158106 +Gc5_5 0 n10 ns5 0 0.000287902232285 +Gc5_6 0 n10 ns6 0 4.43833884898e-007 +Gc5_7 0 n10 ns7 0 2.51884121798e-008 +Gc5_8 0 n10 ns8 0 0.000932908793697 +Gc5_9 0 n10 ns9 0 -0.00016983714894 +Gc5_10 0 n10 ns10 0 0.00082795557682 +Gc5_11 0 n10 ns11 0 -0.000873235627128 +Gc5_12 0 n10 ns12 0 -2.68943121405e-005 +Gc5_13 0 n10 ns13 0 -0.0020459943988 +Gc5_14 0 n10 ns14 0 0.00187194726502 +Gc5_15 0 n10 ns15 0 -0.0011475297602 +Gc5_16 0 n10 ns16 0 -0.00152433421556 +Gc5_17 0 n10 ns17 0 -0.000312294292013 +Gc5_18 0 n10 ns18 0 0.000584809326993 +Gc5_19 0 n10 ns19 0 -0.00653605848246 +Gc5_20 0 n10 ns20 0 -0.000156694814973 +Gc5_21 0 n10 ns21 0 -0.00742713891877 +Gc5_22 0 n10 ns22 0 -0.00588720594083 +Gc5_23 0 n10 ns23 0 -0.000558649266608 +Gc5_24 0 n10 ns24 0 3.20237318236e-007 +Gc5_25 0 n10 ns25 0 2.3056380152e-007 +Gc5_26 0 n10 ns26 0 -0.00121195146355 +Gc5_27 0 n10 ns27 0 0.00145008923673 +Gc5_28 0 n10 ns28 0 -0.00256128434081 +Gc5_29 0 n10 ns29 0 0.000664755228828 +Gc5_30 0 n10 ns30 0 0.00139272310469 +Gc5_31 0 n10 ns31 0 -0.00254886123974 +Gc5_32 0 n10 ns32 0 0.00295297751612 +Gc5_33 0 n10 ns33 0 -0.00654356016875 +Gc5_34 0 n10 ns34 0 -0.00941800666976 +Gc5_35 0 n10 ns35 0 0.000352924730076 +Gc5_36 0 n10 ns36 0 0.000770778759413 +Gc5_37 0 n10 ns37 0 -0.00643962002088 +Gc5_38 0 n10 ns38 0 8.99833348169e-005 +Gc5_39 0 n10 ns39 0 0.0040647888719 +Gc5_40 0 n10 ns40 0 0.00255290836982 +Gc5_41 0 n10 ns41 0 0.000275000529832 +Gc5_42 0 n10 ns42 0 4.49097893431e-007 +Gc5_43 0 n10 ns43 0 1.33422256374e-007 +Gc5_44 0 n10 ns44 0 -0.000203415355097 +Gc5_45 0 n10 ns45 0 -0.000690058729834 +Gc5_46 0 n10 ns46 0 0.00241459602713 +Gc5_47 0 n10 ns47 0 -0.000899641116794 +Gc5_48 0 n10 ns48 0 6.96999678871e-006 +Gc5_49 0 n10 ns49 0 -0.00209898609121 +Gc5_50 0 n10 ns50 0 0.00223644716839 +Gc5_51 0 n10 ns51 0 -0.00186298343823 +Gc5_52 0 n10 ns52 0 -0.00153056719006 +Gc5_53 0 n10 ns53 0 -0.00025254793346 +Gc5_54 0 n10 ns54 0 0.000417677751088 +Gc5_55 0 n10 ns55 0 0.00644271843823 +Gc5_56 0 n10 ns56 0 -6.90408049659e-005 +Gc5_57 0 n10 ns57 0 -0.00334585817896 +Gc5_58 0 n10 ns58 0 -0.00328721973461 +Gc5_59 0 n10 ns59 0 -0.000257120598841 +Gc5_60 0 n10 ns60 0 2.60443081518e-007 +Gc5_61 0 n10 ns61 0 7.30505773583e-008 +Gc5_62 0 n10 ns62 0 -0.00109623838966 +Gc5_63 0 n10 ns63 0 0.000281677968483 +Gc5_64 0 n10 ns64 0 -0.0005011174152 +Gc5_65 0 n10 ns65 0 0.000521062121259 +Gc5_66 0 n10 ns66 0 0.000182053045931 +Gc5_67 0 n10 ns67 0 0.00223425840957 +Gc5_68 0 n10 ns68 0 -0.00188561997309 +Gc5_69 0 n10 ns69 0 -0.00303887417028 +Gc5_70 0 n10 ns70 0 -0.000655727815139 +Gc5_71 0 n10 ns71 0 -0.000275164920233 +Gc5_72 0 n10 ns72 0 0.000199115629282 +Gc5_73 0 n10 ns73 0 0.00651968635887 +Gc5_74 0 n10 ns74 0 0.000156439166519 +Gc5_75 0 n10 ns75 0 0.00743727467382 +Gc5_76 0 n10 ns76 0 0.00583173340553 +Gc5_77 0 n10 ns77 0 0.000600046260742 +Gc5_78 0 n10 ns78 0 1.02810866036e-006 +Gc5_79 0 n10 ns79 0 3.93462370297e-007 +Gc5_80 0 n10 ns80 0 0.000821775653201 +Gc5_81 0 n10 ns81 0 -0.000790919614792 +Gc5_82 0 n10 ns82 0 0.0018945095364 +Gc5_83 0 n10 ns83 0 -0.000927235583771 +Gc5_84 0 n10 ns84 0 -0.00499507369166 +Gc5_85 0 n10 ns85 0 0.00248753679979 +Gc5_86 0 n10 ns86 0 -0.00282954868349 +Gc5_87 0 n10 ns87 0 0.0112291797144 +Gc5_88 0 n10 ns88 0 0.0294820522391 +Gc5_89 0 n10 ns89 0 0.000934055420614 +Gc5_90 0 n10 ns90 0 -0.00116960377511 +Gc5_91 0 n10 ns91 0 0.0064417623267 +Gc5_92 0 n10 ns92 0 -9.12237265622e-005 +Gc5_93 0 n10 ns93 0 -0.00404323794063 +Gc5_94 0 n10 ns94 0 -0.00255820190281 +Gc5_95 0 n10 ns95 0 -0.000261576451876 +Gc5_96 0 n10 ns96 0 2.49990479989e-007 +Gc5_97 0 n10 ns97 0 -1.46302092014e-007 +Gc5_98 0 n10 ns98 0 -5.71370561671e-005 +Gc5_99 0 n10 ns99 0 0.000463810061608 +Gc5_100 0 n10 ns100 0 -0.00160254436243 +Gc5_101 0 n10 ns101 0 0.000692893066835 +Gc5_102 0 n10 ns102 0 0.00035874367876 +Gc5_103 0 n10 ns103 0 0.00223764277813 +Gc5_104 0 n10 ns104 0 -0.00214235818578 +Gc5_105 0 n10 ns105 0 -0.0029006636987 +Gc5_106 0 n10 ns106 0 -0.00049482218081 +Gc5_107 0 n10 ns107 0 -0.000279489810353 +Gc5_108 0 n10 ns108 0 0.000219440238854 +Gd5_1 0 n10 ni1 0 -0.000697519013343 +Gd5_2 0 n10 ni2 0 -0.00314014600661 +Gd5_3 0 n10 ni3 0 -0.000923837466596 +Gd5_4 0 n10 ni4 0 -0.0012830772259 +Gd5_5 0 n10 ni5 0 0.00347931109639 +Gd5_6 0 n10 ni6 0 -0.00123549714507 +Gc6_1 0 n12 ns1 0 -0.00643993674434 +Gc6_2 0 n12 ns2 0 8.76878679085e-005 +Gc6_3 0 n12 ns3 0 0.0039232909504 +Gc6_4 0 n12 ns4 0 0.00268786920045 +Gc6_5 0 n12 ns5 0 0.000257225561375 +Gc6_6 0 n12 ns6 0 4.42704894628e-007 +Gc6_7 0 n12 ns7 0 -2.62182959014e-007 +Gc6_8 0 n12 ns8 0 0.0026577031892 +Gc6_9 0 n12 ns9 0 0.000243495143694 +Gc6_10 0 n12 ns10 0 -0.000805456395465 +Gc6_11 0 n12 ns11 0 -0.00103544757508 +Gc6_12 0 n12 ns12 0 8.96386148367e-005 +Gc6_13 0 n12 ns13 0 -0.00181066054622 +Gc6_14 0 n12 ns14 0 0.00155200303786 +Gc6_15 0 n12 ns15 0 -0.00170683856736 +Gc6_16 0 n12 ns16 0 -0.00169459915628 +Gc6_17 0 n12 ns17 0 -0.000179633627656 +Gc6_18 0 n12 ns18 0 0.000683786008851 +Gc6_19 0 n12 ns19 0 -0.00643476355441 +Gc6_20 0 n12 ns20 0 9.11830569025e-005 +Gc6_21 0 n12 ns21 0 0.0040510978546 +Gc6_22 0 n12 ns22 0 0.00255516642622 +Gc6_23 0 n12 ns23 0 0.000270132991837 +Gc6_24 0 n12 ns24 0 5.99601643922e-007 +Gc6_25 0 n12 ns25 0 -2.36615456042e-007 +Gc6_26 0 n12 ns26 0 -0.000174160580609 +Gc6_27 0 n12 ns27 0 -0.000717928672052 +Gc6_28 0 n12 ns28 0 0.00229667407359 +Gc6_29 0 n12 ns29 0 -0.000696292813531 +Gc6_30 0 n12 ns30 0 -0.000159441198458 +Gc6_31 0 n12 ns31 0 -0.00236919266319 +Gc6_32 0 n12 ns32 0 0.0022724581503 +Gc6_33 0 n12 ns33 0 -0.00157107041398 +Gc6_34 0 n12 ns34 0 -0.00167281795656 +Gc6_35 0 n12 ns35 0 -0.000372311744519 +Gc6_36 0 n12 ns36 0 0.000326249822064 +Gc6_37 0 n12 ns37 0 -0.00653635927342 +Gc6_38 0 n12 ns38 0 -0.000173474531947 +Gc6_39 0 n12 ns39 0 -0.00799333966735 +Gc6_40 0 n12 ns40 0 -0.0052673851056 +Gc6_41 0 n12 ns41 0 -0.000568000882971 +Gc6_42 0 n12 ns42 0 3.05307977803e-007 +Gc6_43 0 n12 ns43 0 -2.56316129215e-007 +Gc6_44 0 n12 ns44 0 -0.00247289196381 +Gc6_45 0 n12 ns45 0 0.000849096588998 +Gc6_46 0 n12 ns46 0 -0.00198459551177 +Gc6_47 0 n12 ns47 0 0.00136430342662 +Gc6_48 0 n12 ns48 0 0.00131661691748 +Gc6_49 0 n12 ns49 0 -0.00178480400281 +Gc6_50 0 n12 ns50 0 0.0020655497987 +Gc6_51 0 n12 ns51 0 -0.0045306057655 +Gc6_52 0 n12 ns52 0 -0.00707192501528 +Gc6_53 0 n12 ns53 0 -9.19832366755e-005 +Gc6_54 0 n12 ns54 0 0.000266247783619 +Gc6_55 0 n12 ns55 0 0.0064394800426 +Gc6_56 0 n12 ns56 0 -8.65025337612e-005 +Gc6_57 0 n12 ns57 0 -0.00392293123286 +Gc6_58 0 n12 ns58 0 -0.0026769049958 +Gc6_59 0 n12 ns59 0 -0.000256039998642 +Gc6_60 0 n12 ns60 0 3.45329513967e-007 +Gc6_61 0 n12 ns61 0 -2.68422474412e-007 +Gc6_62 0 n12 ns62 0 -0.00208460543425 +Gc6_63 0 n12 ns63 0 -0.000313349263344 +Gc6_64 0 n12 ns64 0 0.000884168270549 +Gc6_65 0 n12 ns65 0 0.000898878815235 +Gc6_66 0 n12 ns66 0 0.00015010103225 +Gc6_67 0 n12 ns67 0 0.00182458431053 +Gc6_68 0 n12 ns68 0 -0.00153200853187 +Gc6_69 0 n12 ns69 0 -0.00331756914109 +Gc6_70 0 n12 ns70 0 -0.000944276057394 +Gc6_71 0 n12 ns71 0 -0.000258842231463 +Gc6_72 0 n12 ns72 0 0.000184419316623 +Gc6_73 0 n12 ns73 0 0.00643649879569 +Gc6_74 0 n12 ns74 0 -9.08063258793e-005 +Gc6_75 0 n12 ns75 0 -0.0040449706217 +Gc6_76 0 n12 ns76 0 -0.00255778932509 +Gc6_77 0 n12 ns77 0 -0.000257806150191 +Gc6_78 0 n12 ns78 0 2.91966862113e-007 +Gc6_79 0 n12 ns79 0 -1.16096393746e-007 +Gc6_80 0 n12 ns80 0 -5.46327724301e-005 +Gc6_81 0 n12 ns81 0 0.000497337899186 +Gc6_82 0 n12 ns82 0 -0.00161853170123 +Gc6_83 0 n12 ns83 0 0.000667339352005 +Gc6_84 0 n12 ns84 0 0.000321148764347 +Gc6_85 0 n12 ns85 0 0.00224046269121 +Gc6_86 0 n12 ns86 0 -0.00215181357453 +Gc6_87 0 n12 ns87 0 -0.00290675815236 +Gc6_88 0 n12 ns88 0 -0.000531210954673 +Gc6_89 0 n12 ns89 0 -0.000279216112973 +Gc6_90 0 n12 ns90 0 0.00021975285787 +Gc6_91 0 n12 ns91 0 0.00651441575953 +Gc6_92 0 n12 ns92 0 0.000176688703349 +Gc6_93 0 n12 ns93 0 0.0079593836898 +Gc6_94 0 n12 ns94 0 0.00526645727849 +Gc6_95 0 n12 ns95 0 0.000536788607868 +Gc6_96 0 n12 ns96 0 8.66497692324e-007 +Gc6_97 0 n12 ns97 0 -4.38376301921e-007 +Gc6_98 0 n12 ns98 0 0.002345420622 +Gc6_99 0 n12 ns99 0 -0.000954575243587 +Gc6_100 0 n12 ns100 0 0.00135585471228 +Gc6_101 0 n12 ns101 0 -0.000752532967417 +Gc6_102 0 n12 ns102 0 -0.00464039228837 +Gc6_103 0 n12 ns103 0 0.00168304471289 +Gc6_104 0 n12 ns104 0 -0.00186017145201 +Gc6_105 0 n12 ns105 0 0.00826201371205 +Gc6_106 0 n12 ns106 0 0.0272545620312 +Gc6_107 0 n12 ns107 0 0.00131624342067 +Gc6_108 0 n12 ns108 0 -0.000869639522243 +Gd6_1 0 n12 ni1 0 -0.000845754668306 +Gd6_2 0 n12 ni2 0 -0.00090294379374 +Gd6_3 0 n12 ni3 0 -0.00244072793575 +Gd6_4 0 n12 ni4 0 -0.0014316280297 +Gd6_5 0 n12 ni5 0 -0.00124018041096 +Gd6_6 0 n12 ni6 0 0.00207530737921 +.ends + +.subckt 744838040400 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 93931609.5505 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 858845.625016 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 136719.182038 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 43637.6672568 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 26193.1348512 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 11244.0529794 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 271972.968997 +Ra8 ns8 0 271972.968997 +Ga7 ns7 0 ns8 0 -0.000219174645357 +Ga8 ns8 0 ns7 0 0.000219174645357 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 4905.23762494 +Ra10 ns10 0 4905.23762494 +Ga9 ns9 0 ns10 0 -0.0004706797245 +Ga10 ns10 0 ns9 0 0.0004706797245 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 2288.50204528 +Ra12 ns12 0 2288.50204528 +Ga11 ns11 0 ns12 0 -0.000304254354245 +Ga12 ns12 0 ns11 0 0.000304254354245 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 5681.62963171 +Ra14 ns14 0 5681.62963171 +Ga13 ns13 0 ns14 0 -0.00055531660304 +Ga14 ns14 0 ns13 0 0.00055531660304 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 13808.0586924 +Ra16 ns16 0 13808.0586924 +Ga15 ns15 0 ns16 0 -0.000692146980885 +Ga16 ns16 0 ns15 0 0.000692146980885 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 4855.38630322 +Ra18 ns18 0 4855.38630322 +Ga17 ns17 0 ns18 0 -0.000712989806853 +Ga18 ns18 0 ns17 0 0.000712989806853 +Ca19 ns19 0 1e-012 +Ra19 ns19 0 93931609.5505 +Ca20 ns20 0 1e-012 +Ra20 ns20 0 858845.625016 +Ca21 ns21 0 1e-012 +Ra21 ns21 0 136719.182038 +Ca22 ns22 0 1e-012 +Ra22 ns22 0 43637.6672568 +Ca23 ns23 0 1e-012 +Ra23 ns23 0 26193.1348512 +Ca24 ns24 0 1e-012 +Ra24 ns24 0 11244.0529794 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 271972.968997 +Ra26 ns26 0 271972.968997 +Ga25 ns25 0 ns26 0 -0.000219174645357 +Ga26 ns26 0 ns25 0 0.000219174645357 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 4905.23762494 +Ra28 ns28 0 4905.23762494 +Ga27 ns27 0 ns28 0 -0.0004706797245 +Ga28 ns28 0 ns27 0 0.0004706797245 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 2288.50204528 +Ra30 ns30 0 2288.50204528 +Ga29 ns29 0 ns30 0 -0.000304254354245 +Ga30 ns30 0 ns29 0 0.000304254354245 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 5681.62963171 +Ra32 ns32 0 5681.62963171 +Ga31 ns31 0 ns32 0 -0.00055531660304 +Ga32 ns32 0 ns31 0 0.00055531660304 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 13808.0586924 +Ra34 ns34 0 13808.0586924 +Ga33 ns33 0 ns34 0 -0.000692146980885 +Ga34 ns34 0 ns33 0 0.000692146980885 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 4855.38630322 +Ra36 ns36 0 4855.38630322 +Ga35 ns35 0 ns36 0 -0.000712989806853 +Ga36 ns36 0 ns35 0 0.000712989806853 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 93931609.5505 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 858845.625016 +Ca39 ns39 0 1e-012 +Ra39 ns39 0 136719.182038 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 43637.6672568 +Ca41 ns41 0 1e-012 +Ra41 ns41 0 26193.1348512 +Ca42 ns42 0 1e-012 +Ra42 ns42 0 11244.0529794 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 271972.968997 +Ra44 ns44 0 271972.968997 +Ga43 ns43 0 ns44 0 -0.000219174645357 +Ga44 ns44 0 ns43 0 0.000219174645357 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 4905.23762494 +Ra46 ns46 0 4905.23762494 +Ga45 ns45 0 ns46 0 -0.0004706797245 +Ga46 ns46 0 ns45 0 0.0004706797245 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 2288.50204528 +Ra48 ns48 0 2288.50204528 +Ga47 ns47 0 ns48 0 -0.000304254354245 +Ga48 ns48 0 ns47 0 0.000304254354245 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 5681.62963171 +Ra50 ns50 0 5681.62963171 +Ga49 ns49 0 ns50 0 -0.00055531660304 +Ga50 ns50 0 ns49 0 0.00055531660304 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 13808.0586924 +Ra52 ns52 0 13808.0586924 +Ga51 ns51 0 ns52 0 -0.000692146980885 +Ga52 ns52 0 ns51 0 0.000692146980885 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 4855.38630322 +Ra54 ns54 0 4855.38630322 +Ga53 ns53 0 ns54 0 -0.000712989806853 +Ga54 ns54 0 ns53 0 0.000712989806853 +Ca55 ns55 0 1e-012 +Ra55 ns55 0 93931609.5505 +Ca56 ns56 0 1e-012 +Ra56 ns56 0 858845.625016 +Ca57 ns57 0 1e-012 +Ra57 ns57 0 136719.182038 +Ca58 ns58 0 1e-012 +Ra58 ns58 0 43637.6672568 +Ca59 ns59 0 1e-012 +Ra59 ns59 0 26193.1348512 +Ca60 ns60 0 1e-012 +Ra60 ns60 0 11244.0529794 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 271972.968997 +Ra62 ns62 0 271972.968997 +Ga61 ns61 0 ns62 0 -0.000219174645357 +Ga62 ns62 0 ns61 0 0.000219174645357 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 4905.23762494 +Ra64 ns64 0 4905.23762494 +Ga63 ns63 0 ns64 0 -0.0004706797245 +Ga64 ns64 0 ns63 0 0.0004706797245 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 2288.50204528 +Ra66 ns66 0 2288.50204528 +Ga65 ns65 0 ns66 0 -0.000304254354245 +Ga66 ns66 0 ns65 0 0.000304254354245 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 5681.62963171 +Ra68 ns68 0 5681.62963171 +Ga67 ns67 0 ns68 0 -0.00055531660304 +Ga68 ns68 0 ns67 0 0.00055531660304 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 13808.0586924 +Ra70 ns70 0 13808.0586924 +Ga69 ns69 0 ns70 0 -0.000692146980885 +Ga70 ns70 0 ns69 0 0.000692146980885 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 4855.38630322 +Ra72 ns72 0 4855.38630322 +Ga71 ns71 0 ns72 0 -0.000712989806853 +Ga72 ns72 0 ns71 0 0.000712989806853 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 93931609.5505 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 858845.625016 +Ca75 ns75 0 1e-012 +Ra75 ns75 0 136719.182038 +Ca76 ns76 0 1e-012 +Ra76 ns76 0 43637.6672568 +Ca77 ns77 0 1e-012 +Ra77 ns77 0 26193.1348512 +Ca78 ns78 0 1e-012 +Ra78 ns78 0 11244.0529794 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 271972.968997 +Ra80 ns80 0 271972.968997 +Ga79 ns79 0 ns80 0 -0.000219174645357 +Ga80 ns80 0 ns79 0 0.000219174645357 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 4905.23762494 +Ra82 ns82 0 4905.23762494 +Ga81 ns81 0 ns82 0 -0.0004706797245 +Ga82 ns82 0 ns81 0 0.0004706797245 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 2288.50204528 +Ra84 ns84 0 2288.50204528 +Ga83 ns83 0 ns84 0 -0.000304254354245 +Ga84 ns84 0 ns83 0 0.000304254354245 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 5681.62963171 +Ra86 ns86 0 5681.62963171 +Ga85 ns85 0 ns86 0 -0.00055531660304 +Ga86 ns86 0 ns85 0 0.00055531660304 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 13808.0586924 +Ra88 ns88 0 13808.0586924 +Ga87 ns87 0 ns88 0 -0.000692146980885 +Ga88 ns88 0 ns87 0 0.000692146980885 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 4855.38630322 +Ra90 ns90 0 4855.38630322 +Ga89 ns89 0 ns90 0 -0.000712989806853 +Ga90 ns90 0 ns89 0 0.000712989806853 +Ca91 ns91 0 1e-012 +Ra91 ns91 0 93931609.5505 +Ca92 ns92 0 1e-012 +Ra92 ns92 0 858845.625016 +Ca93 ns93 0 1e-012 +Ra93 ns93 0 136719.182038 +Ca94 ns94 0 1e-012 +Ra94 ns94 0 43637.6672568 +Ca95 ns95 0 1e-012 +Ra95 ns95 0 26193.1348512 +Ca96 ns96 0 1e-012 +Ra96 ns96 0 11244.0529794 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 271972.968997 +Ra98 ns98 0 271972.968997 +Ga97 ns97 0 ns98 0 -0.000219174645357 +Ga98 ns98 0 ns97 0 0.000219174645357 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 4905.23762494 +Ra100 ns100 0 4905.23762494 +Ga99 ns99 0 ns100 0 -0.0004706797245 +Ga100 ns100 0 ns99 0 0.0004706797245 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 2288.50204528 +Ra102 ns102 0 2288.50204528 +Ga101 ns101 0 ns102 0 -0.000304254354245 +Ga102 ns102 0 ns101 0 0.000304254354245 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 5681.62963171 +Ra104 ns104 0 5681.62963171 +Ga103 ns103 0 ns104 0 -0.00055531660304 +Ga104 ns104 0 ns103 0 0.00055531660304 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 13808.0586924 +Ra106 ns106 0 13808.0586924 +Ga105 ns105 0 ns106 0 -0.000692146980885 +Ga106 ns106 0 ns105 0 0.000692146980885 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 4855.38630322 +Ra108 ns108 0 4855.38630322 +Ga107 ns107 0 ns108 0 -0.000712989806853 +Ga108 ns108 0 ns107 0 0.000712989806853 + +Gb1_1 ns1 0 ni1 0 1.06460434862e-008 +Gb2_1 ns2 0 ni1 0 1.16435360544e-006 +Gb3_1 ns3 0 ni1 0 7.31426260084e-006 +Gb4_1 ns4 0 ni1 0 2.291598206e-005 +Gb5_1 ns5 0 ni1 0 3.81779426434e-005 +Gb6_1 ns6 0 ni1 0 8.89359025464e-005 +Gb7_1 ns7 0 ni1 0 0.000219236327322 +Gb9_1 ns9 0 ni1 0 0.000558978444468 +Gb11_1 ns11 0 ni1 0 0.00064881531932 +Gb13_1 ns13 0 ni1 0 0.000611101097504 +Gb15_1 ns15 0 ni1 0 0.000699724663694 +Gb17_1 ns17 0 ni1 0 0.000772483249591 +Gb19_2 ns19 0 ni2 0 1.06460434862e-008 +Gb20_2 ns20 0 ni2 0 1.16435360544e-006 +Gb21_2 ns21 0 ni2 0 7.31426260084e-006 +Gb22_2 ns22 0 ni2 0 2.291598206e-005 +Gb23_2 ns23 0 ni2 0 3.81779426434e-005 +Gb24_2 ns24 0 ni2 0 8.89359025464e-005 +Gb25_2 ns25 0 ni2 0 0.000219236327322 +Gb27_2 ns27 0 ni2 0 0.000558978444468 +Gb29_2 ns29 0 ni2 0 0.00064881531932 +Gb31_2 ns31 0 ni2 0 0.000611101097504 +Gb33_2 ns33 0 ni2 0 0.000699724663694 +Gb35_2 ns35 0 ni2 0 0.000772483249591 +Gb37_3 ns37 0 ni3 0 1.06460434862e-008 +Gb38_3 ns38 0 ni3 0 1.16435360544e-006 +Gb39_3 ns39 0 ni3 0 7.31426260084e-006 +Gb40_3 ns40 0 ni3 0 2.291598206e-005 +Gb41_3 ns41 0 ni3 0 3.81779426434e-005 +Gb42_3 ns42 0 ni3 0 8.89359025464e-005 +Gb43_3 ns43 0 ni3 0 0.000219236327322 +Gb45_3 ns45 0 ni3 0 0.000558978444468 +Gb47_3 ns47 0 ni3 0 0.00064881531932 +Gb49_3 ns49 0 ni3 0 0.000611101097504 +Gb51_3 ns51 0 ni3 0 0.000699724663694 +Gb53_3 ns53 0 ni3 0 0.000772483249591 +Gb55_4 ns55 0 ni4 0 1.06460434862e-008 +Gb56_4 ns56 0 ni4 0 1.16435360544e-006 +Gb57_4 ns57 0 ni4 0 7.31426260084e-006 +Gb58_4 ns58 0 ni4 0 2.291598206e-005 +Gb59_4 ns59 0 ni4 0 3.81779426434e-005 +Gb60_4 ns60 0 ni4 0 8.89359025464e-005 +Gb61_4 ns61 0 ni4 0 0.000219236327322 +Gb63_4 ns63 0 ni4 0 0.000558978444468 +Gb65_4 ns65 0 ni4 0 0.00064881531932 +Gb67_4 ns67 0 ni4 0 0.000611101097504 +Gb69_4 ns69 0 ni4 0 0.000699724663694 +Gb71_4 ns71 0 ni4 0 0.000772483249591 +Gb73_5 ns73 0 ni5 0 1.06460434862e-008 +Gb74_5 ns74 0 ni5 0 1.16435360544e-006 +Gb75_5 ns75 0 ni5 0 7.31426260084e-006 +Gb76_5 ns76 0 ni5 0 2.291598206e-005 +Gb77_5 ns77 0 ni5 0 3.81779426434e-005 +Gb78_5 ns78 0 ni5 0 8.89359025464e-005 +Gb79_5 ns79 0 ni5 0 0.000219236327322 +Gb81_5 ns81 0 ni5 0 0.000558978444468 +Gb83_5 ns83 0 ni5 0 0.00064881531932 +Gb85_5 ns85 0 ni5 0 0.000611101097504 +Gb87_5 ns87 0 ni5 0 0.000699724663694 +Gb89_5 ns89 0 ni5 0 0.000772483249591 +Gb91_6 ns91 0 ni6 0 1.06460434862e-008 +Gb92_6 ns92 0 ni6 0 1.16435360544e-006 +Gb93_6 ns93 0 ni6 0 7.31426260084e-006 +Gb94_6 ns94 0 ni6 0 2.291598206e-005 +Gb95_6 ns95 0 ni6 0 3.81779426434e-005 +Gb96_6 ns96 0 ni6 0 8.89359025464e-005 +Gb97_6 ns97 0 ni6 0 0.000219236327322 +Gb99_6 ns99 0 ni6 0 0.000558978444468 +Gb101_6 ns101 0 ni6 0 0.00064881531932 +Gb103_6 ns103 0 ni6 0 0.000611101097504 +Gb105_6 ns105 0 ni6 0 0.000699724663694 +Gb107_6 ns107 0 ni6 0 0.000772483249591 + +Gc1_1 0 n2 ns1 0 0.00586300405067 +Gc1_2 0 n2 ns2 0 8.06560266674e-005 +Gc1_3 0 n2 ns3 0 0.000378365871188 +Gc1_4 0 n2 ns4 0 0.00633482523381 +Gc1_5 0 n2 ns5 0 0.00788095023465 +Gc1_6 0 n2 ns6 0 0.00154132100708 +Gc1_7 0 n2 ns7 0 2.98598114873e-007 +Gc1_8 0 n2 ns8 0 -1.41886178901e-007 +Gc1_9 0 n2 ns9 0 0.00823725100957 +Gc1_10 0 n2 ns10 0 -0.00451239764801 +Gc1_11 0 n2 ns11 0 -0.00813716746566 +Gc1_12 0 n2 ns12 0 0.0441678944213 +Gc1_13 0 n2 ns13 0 -0.00531889897227 +Gc1_14 0 n2 ns14 0 -0.00862985402365 +Gc1_15 0 n2 ns15 0 0.00191127342388 +Gc1_16 0 n2 ns16 0 0.00296180763087 +Gc1_17 0 n2 ns17 0 -0.00131346945027 +Gc1_18 0 n2 ns18 0 -0.00219726380813 +Gc1_19 0 n2 ns19 0 0.00578751203418 +Gc1_20 0 n2 ns20 0 1.8604044095e-005 +Gc1_21 0 n2 ns21 0 -0.000134038224815 +Gc1_22 0 n2 ns22 0 -0.00285912861944 +Gc1_23 0 n2 ns23 0 -0.00428290177443 +Gc1_24 0 n2 ns24 0 -0.00100102202343 +Gc1_25 0 n2 ns25 0 2.66515514618e-007 +Gc1_26 0 n2 ns26 0 -3.22552780994e-007 +Gc1_27 0 n2 ns27 0 -0.000264878777244 +Gc1_28 0 n2 ns28 0 0.005510482554 +Gc1_29 0 n2 ns29 0 0.00434289337654 +Gc1_30 0 n2 ns30 0 -0.00429442068798 +Gc1_31 0 n2 ns31 0 -0.000735578894043 +Gc1_32 0 n2 ns32 0 0.0025734024242 +Gc1_33 0 n2 ns33 0 -0.000327066102038 +Gc1_34 0 n2 ns34 0 0.00072196275291 +Gc1_35 0 n2 ns35 0 -0.00419211154794 +Gc1_36 0 n2 ns36 0 -0.00404599434019 +Gc1_37 0 n2 ns37 0 0.00578550960847 +Gc1_38 0 n2 ns38 0 1.55701065419e-005 +Gc1_39 0 n2 ns39 0 -0.000114129624346 +Gc1_40 0 n2 ns40 0 -0.003476144486 +Gc1_41 0 n2 ns41 0 -0.00351203463353 +Gc1_42 0 n2 ns42 0 -0.000565891509521 +Gc1_43 0 n2 ns43 0 4.01595076744e-007 +Gc1_44 0 n2 ns44 0 -1.58111161105e-007 +Gc1_45 0 n2 ns45 0 -0.000557708270579 +Gc1_46 0 n2 ns46 0 -0.000625395151475 +Gc1_47 0 n2 ns47 0 0.0050524015312 +Gc1_48 0 n2 ns48 0 -0.00139446565428 +Gc1_49 0 n2 ns49 0 0.00110836967849 +Gc1_50 0 n2 ns50 0 0.00864330094859 +Gc1_51 0 n2 ns51 0 -0.000619738746095 +Gc1_52 0 n2 ns52 0 0.000706629436123 +Gc1_53 0 n2 ns53 0 -0.00467928004397 +Gc1_54 0 n2 ns54 0 -0.00468624613343 +Gc1_55 0 n2 ns55 0 -0.00584090571434 +Gc1_56 0 n2 ns56 0 -7.67716947272e-005 +Gc1_57 0 n2 ns57 0 -0.000390204751707 +Gc1_58 0 n2 ns58 0 -0.00631489325639 +Gc1_59 0 n2 ns59 0 -0.00791058906138 +Gc1_60 0 n2 ns60 0 -0.00147584712714 +Gc1_61 0 n2 ns61 0 3.06628182964e-007 +Gc1_62 0 n2 ns62 0 -2.090184977e-007 +Gc1_63 0 n2 ns63 0 -0.00516645591759 +Gc1_64 0 n2 ns64 0 0.00563948878021 +Gc1_65 0 n2 ns65 0 0.00558869440262 +Gc1_66 0 n2 ns66 0 -0.0275099174678 +Gc1_67 0 n2 ns67 0 0.00489222430226 +Gc1_68 0 n2 ns68 0 0.0083034998055 +Gc1_69 0 n2 ns69 0 -0.00137103179163 +Gc1_70 0 n2 ns70 0 -0.00313086460996 +Gc1_71 0 n2 ns71 0 0.000363289928361 +Gc1_72 0 n2 ns72 0 0.00970643384834 +Gc1_73 0 n2 ns73 0 -0.00579201466772 +Gc1_74 0 n2 ns74 0 -1.67178855814e-005 +Gc1_75 0 n2 ns75 0 0.000124248445879 +Gc1_76 0 n2 ns76 0 0.00290274378866 +Gc1_77 0 n2 ns77 0 0.00413229655853 +Gc1_78 0 n2 ns78 0 0.00112069760308 +Gc1_79 0 n2 ns79 0 1.00297007175e-007 +Gc1_80 0 n2 ns80 0 -2.06632172487e-007 +Gc1_81 0 n2 ns81 0 -0.000130562389232 +Gc1_82 0 n2 ns82 0 -0.00201815679351 +Gc1_83 0 n2 ns83 0 -0.00265132714856 +Gc1_84 0 n2 ns84 0 0.00351001643444 +Gc1_85 0 n2 ns85 0 -0.00225826226644 +Gc1_86 0 n2 ns86 0 -0.00158657016255 +Gc1_87 0 n2 ns87 0 0.000162313533721 +Gc1_88 0 n2 ns88 0 -0.000941708756562 +Gc1_89 0 n2 ns89 0 0.00115211232568 +Gc1_90 0 n2 ns90 0 0.00145601091887 +Gc1_91 0 n2 ns91 0 -0.00579065452624 +Gc1_92 0 n2 ns92 0 -1.54963114358e-005 +Gc1_93 0 n2 ns93 0 0.000117176530818 +Gc1_94 0 n2 ns94 0 0.0034349809793 +Gc1_95 0 n2 ns95 0 0.00352813051251 +Gc1_96 0 n2 ns96 0 0.000542836535018 +Gc1_97 0 n2 ns97 0 4.52734124141e-007 +Gc1_98 0 n2 ns98 0 -1.47608610815e-008 +Gc1_99 0 n2 ns99 0 0.000348153819333 +Gc1_100 0 n2 ns100 0 0.000974136242708 +Gc1_101 0 n2 ns101 0 -0.00579391731081 +Gc1_102 0 n2 ns102 0 -0.000268836854796 +Gc1_103 0 n2 ns103 0 -0.0018653413138 +Gc1_104 0 n2 ns104 0 -0.00539041154588 +Gc1_105 0 n2 ns105 0 0.000420799847059 +Gc1_106 0 n2 ns106 0 -0.000590923442089 +Gc1_107 0 n2 ns107 0 0.000776390474783 +Gc1_108 0 n2 ns108 0 0.00162932646518 +Gd1_1 0 n2 ni1 0 -0.00201073362828 +Gd1_2 0 n2 ni2 0 -0.000741179678104 +Gd1_3 0 n2 ni3 0 -0.000437593985098 +Gd1_4 0 n2 ni4 0 0.00074158502901 +Gd1_5 0 n2 ni5 0 -0.000696762773854 +Gd1_6 0 n2 ni6 0 -0.00132580779559 +Gc2_1 0 n4 ns1 0 0.0057847718349 +Gc2_2 0 n4 ns2 0 1.8394722351e-005 +Gc2_3 0 n4 ns3 0 -0.0001334784329 +Gc2_4 0 n4 ns4 0 -0.00287483421393 +Gc2_5 0 n4 ns5 0 -0.0042579448931 +Gc2_6 0 n4 ns6 0 -0.00100824210256 +Gc2_7 0 n4 ns7 0 2.43822334583e-007 +Gc2_8 0 n4 ns8 0 -3.11887178887e-007 +Gc2_9 0 n4 ns9 0 -0.000313660153713 +Gc2_10 0 n4 ns10 0 0.00549390568886 +Gc2_11 0 n4 ns11 0 0.00432908508279 +Gc2_12 0 n4 ns12 0 -0.00431235723066 +Gc2_13 0 n4 ns13 0 -0.000708886061605 +Gc2_14 0 n4 ns14 0 0.00248746581545 +Gc2_15 0 n4 ns15 0 -0.000342969489852 +Gc2_16 0 n4 ns16 0 0.000703109551228 +Gc2_17 0 n4 ns17 0 -0.00408210655112 +Gc2_18 0 n4 ns18 0 -0.00394679760237 +Gc2_19 0 n4 ns19 0 0.00584359784885 +Gc2_20 0 n4 ns20 0 8.08252699359e-005 +Gc2_21 0 n4 ns21 0 0.000377601254883 +Gc2_22 0 n4 ns22 0 0.00608936682336 +Gc2_23 0 n4 ns23 0 0.00852332867411 +Gc2_24 0 n4 ns24 0 0.00149041643994 +Gc2_25 0 n4 ns25 0 7.93861370591e-007 +Gc2_26 0 n4 ns26 0 -2.44669886664e-007 +Gc2_27 0 n4 ns27 0 0.00133545333376 +Gc2_28 0 n4 ns28 0 -0.00510086997854 +Gc2_29 0 n4 ns29 0 0.00375600180736 +Gc2_30 0 n4 ns30 0 0.0555741988252 +Gc2_31 0 n4 ns31 0 -0.00421604937544 +Gc2_32 0 n4 ns32 0 -0.0126177486699 +Gc2_33 0 n4 ns33 0 0.0010202973832 +Gc2_34 0 n4 ns34 0 0.00186312018579 +Gc2_35 0 n4 ns35 0 0.00177035299188 +Gc2_36 0 n4 ns36 0 0.00296721133339 +Gc2_37 0 n4 ns37 0 0.00578059076089 +Gc2_38 0 n4 ns38 0 1.74032280926e-005 +Gc2_39 0 n4 ns39 0 -0.000114000275651 +Gc2_40 0 n4 ns40 0 -0.00316726602665 +Gc2_41 0 n4 ns41 0 -0.00392007886336 +Gc2_42 0 n4 ns42 0 -0.000529322045413 +Gc2_43 0 n4 ns43 0 3.13352641525e-007 +Gc2_44 0 n4 ns44 0 -2.23887324022e-007 +Gc2_45 0 n4 ns45 0 0.00253517184098 +Gc2_46 0 n4 ns46 0 -0.000979317454451 +Gc2_47 0 n4 ns47 0 0.00789902276874 +Gc2_48 0 n4 ns48 0 -0.0018197304164 +Gc2_49 0 n4 ns49 0 0.000893598105309 +Gc2_50 0 n4 ns50 0 0.0128730203225 +Gc2_51 0 n4 ns51 0 -0.000575720613746 +Gc2_52 0 n4 ns52 0 0.000649250334763 +Gc2_53 0 n4 ns53 0 -0.00812671350923 +Gc2_54 0 n4 ns54 0 -0.00533414284479 +Gc2_55 0 n4 ns55 0 -0.00578201086107 +Gc2_56 0 n4 ns56 0 -1.73529560867e-005 +Gc2_57 0 n4 ns57 0 0.000127909382717 +Gc2_58 0 n4 ns58 0 0.00294529171966 +Gc2_59 0 n4 ns59 0 0.00412188379255 +Gc2_60 0 n4 ns60 0 0.00109026164258 +Gc2_61 0 n4 ns61 0 2.03077152772e-007 +Gc2_62 0 n4 ns62 0 -3.87648785447e-007 +Gc2_63 0 n4 ns63 0 -0.000493157132631 +Gc2_64 0 n4 ns64 0 -0.00224654516883 +Gc2_65 0 n4 ns65 0 -0.00506132807751 +Gc2_66 0 n4 ns66 0 0.00358201125904 +Gc2_67 0 n4 ns67 0 -0.00208877986099 +Gc2_68 0 n4 ns68 0 -0.00353658525483 +Gc2_69 0 n4 ns69 0 0.00045456943046 +Gc2_70 0 n4 ns70 0 -0.000826310000046 +Gc2_71 0 n4 ns71 0 0.00168639230823 +Gc2_72 0 n4 ns72 0 0.00151478802372 +Gc2_73 0 n4 ns73 0 -0.0058394326169 +Gc2_74 0 n4 ns74 0 -7.70687337187e-005 +Gc2_75 0 n4 ns75 0 -0.000367642225819 +Gc2_76 0 n4 ns76 0 -0.00617695618426 +Gc2_77 0 n4 ns77 0 -0.00825348889117 +Gc2_78 0 n4 ns78 0 -0.0018005453888 +Gc2_79 0 n4 ns79 0 7.53947711634e-007 +Gc2_80 0 n4 ns80 0 -2.13006746452e-007 +Gc2_81 0 n4 ns81 0 0.000752971644046 +Gc2_82 0 n4 ns82 0 0.00278755760915 +Gc2_83 0 n4 ns83 0 -0.010454560174 +Gc2_84 0 n4 ns84 0 -0.0416966468246 +Gc2_85 0 n4 ns85 0 0.00782867727145 +Gc2_86 0 n4 ns86 0 0.0115936977078 +Gc2_87 0 n4 ns87 0 -0.000619985211785 +Gc2_88 0 n4 ns88 0 -0.00200017368839 +Gc2_89 0 n4 ns89 0 -0.00232033173833 +Gc2_90 0 n4 ns90 0 0.00701366661136 +Gc2_91 0 n4 ns91 0 -0.00578588623317 +Gc2_92 0 n4 ns92 0 -1.61050382257e-005 +Gc2_93 0 n4 ns93 0 0.0001085605601 +Gc2_94 0 n4 ns94 0 0.0031719898319 +Gc2_95 0 n4 ns95 0 0.00382654431628 +Gc2_96 0 n4 ns96 0 0.000602599165825 +Gc2_97 0 n4 ns97 0 3.61949312512e-007 +Gc2_98 0 n4 ns98 0 -2.03602655909e-007 +Gc2_99 0 n4 ns99 0 -0.00179370173292 +Gc2_100 0 n4 ns100 0 0.00215536044807 +Gc2_101 0 n4 ns101 0 -0.00502739538437 +Gc2_102 0 n4 ns102 0 0.000317654911391 +Gc2_103 0 n4 ns103 0 -0.00265240004041 +Gc2_104 0 n4 ns104 0 -0.00669933721646 +Gc2_105 0 n4 ns105 0 0.000366099918 +Gc2_106 0 n4 ns106 0 -0.000703700840737 +Gc2_107 0 n4 ns107 0 0.00314650593285 +Gc2_108 0 n4 ns108 0 0.00155256975347 +Gd2_1 0 n4 ni1 0 -0.000701869405622 +Gd2_2 0 n4 ni2 0 0.000951131393129 +Gd2_3 0 n4 ni3 0 -0.000247356049259 +Gd2_4 0 n4 ni4 0 -0.00106991048776 +Gd2_5 0 n4 ni5 0 -0.00201221852112 +Gd2_6 0 n4 ni6 0 -0.00106065190602 +Gc3_1 0 n6 ns1 0 0.00578330785383 +Gc3_2 0 n6 ns2 0 1.52703761853e-005 +Gc3_3 0 n6 ns3 0 -0.000113528903271 +Gc3_4 0 n6 ns4 0 -0.00349032930558 +Gc3_5 0 n6 ns5 0 -0.00348882572425 +Gc3_6 0 n6 ns6 0 -0.000573627348486 +Gc3_7 0 n6 ns7 0 3.94450937994e-007 +Gc3_8 0 n6 ns8 0 -1.50357910987e-007 +Gc3_9 0 n6 ns9 0 -0.000516621453815 +Gc3_10 0 n6 ns10 0 -0.000672394250818 +Gc3_11 0 n6 ns11 0 0.00514872232453 +Gc3_12 0 n6 ns12 0 -0.00146010634897 +Gc3_13 0 n6 ns13 0 0.00118298060927 +Gc3_14 0 n6 ns14 0 0.00865657684274 +Gc3_15 0 n6 ns15 0 -0.000619136228555 +Gc3_16 0 n6 ns16 0 0.000685008503128 +Gc3_17 0 n6 ns17 0 -0.00469258526975 +Gc3_18 0 n6 ns18 0 -0.00451438897833 +Gc3_19 0 n6 ns19 0 0.00577884247057 +Gc3_20 0 n6 ns20 0 1.70962556936e-005 +Gc3_21 0 n6 ns21 0 -0.000113401186948 +Gc3_22 0 n6 ns22 0 -0.00318163934983 +Gc3_23 0 n6 ns23 0 -0.00389647260606 +Gc3_24 0 n6 ns24 0 -0.000537910450631 +Gc3_25 0 n6 ns25 0 3.03028800469e-007 +Gc3_26 0 n6 ns26 0 -2.00646638436e-007 +Gc3_27 0 n6 ns27 0 0.00248467486336 +Gc3_28 0 n6 ns28 0 -0.000991603837622 +Gc3_29 0 n6 ns29 0 0.00784311438898 +Gc3_30 0 n6 ns30 0 -0.00184638959396 +Gc3_31 0 n6 ns31 0 0.000906850774877 +Gc3_32 0 n6 ns32 0 0.0127757147869 +Gc3_33 0 n6 ns33 0 -0.00059275120418 +Gc3_34 0 n6 ns34 0 0.000635478700643 +Gc3_35 0 n6 ns35 0 -0.00799949442847 +Gc3_36 0 n6 ns36 0 -0.00526132870748 +Gc3_37 0 n6 ns37 0 0.00584354764576 +Gc3_38 0 n6 ns38 0 8.26485477936e-005 +Gc3_39 0 n6 ns39 0 0.000353699063838 +Gc3_40 0 n6 ns40 0 0.00648657520645 +Gc3_41 0 n6 ns41 0 0.00715439126581 +Gc3_42 0 n6 ns42 0 0.00092609043323 +Gc3_43 0 n6 ns43 0 5.70647733771e-007 +Gc3_44 0 n6 ns44 0 -2.61927605903e-007 +Gc3_45 0 n6 ns45 0 0.000583308030701 +Gc3_46 0 n6 ns46 0 0.00241448525754 +Gc3_47 0 n6 ns47 0 -0.00914419085539 +Gc3_48 0 n6 ns48 0 0.0209498260833 +Gc3_49 0 n6 ns49 0 0.012466819995 +Gc3_50 0 n6 ns50 0 -0.0113805961786 +Gc3_51 0 n6 ns51 0 -0.000646046774841 +Gc3_52 0 n6 ns52 0 -0.000449094888307 +Gc3_53 0 n6 ns53 0 -0.00338416880496 +Gc3_54 0 n6 ns54 0 0.0113066970733 +Gc3_55 0 n6 ns55 0 -0.00578114920392 +Gc3_56 0 n6 ns56 0 -1.57692541749e-005 +Gc3_57 0 n6 ns57 0 0.000118581375464 +Gc3_58 0 n6 ns58 0 0.00348690588562 +Gc3_59 0 n6 ns59 0 0.00345888925526 +Gc3_60 0 n6 ns60 0 0.000564689268206 +Gc3_61 0 n6 ns61 0 4.67425166361e-007 +Gc3_62 0 n6 ns62 0 -1.57457272309e-007 +Gc3_63 0 n6 ns63 0 0.000237136381773 +Gc3_64 0 n6 ns64 0 0.00168192327181 +Gc3_65 0 n6 ns65 0 -0.00521510779657 +Gc3_66 0 n6 ns66 0 0.000703757436757 +Gc3_67 0 n6 ns67 0 -0.00531609675176 +Gc3_68 0 n6 ns68 0 -0.00617910103042 +Gc3_69 0 n6 ns69 0 0.000757181758824 +Gc3_70 0 n6 ns70 0 -0.000458157101537 +Gc3_71 0 n6 ns71 0 0.00333752339342 +Gc3_72 0 n6 ns72 0 0.0010558009849 +Gc3_73 0 n6 ns73 0 -0.00577833807932 +Gc3_74 0 n6 ns74 0 -1.63400115515e-005 +Gc3_75 0 n6 ns75 0 0.000109446481768 +Gc3_76 0 n6 ns76 0 0.00320695514005 +Gc3_77 0 n6 ns77 0 0.00380913684971 +Gc3_78 0 n6 ns78 0 0.000627537581473 +Gc3_79 0 n6 ns79 0 3.3666025156e-007 +Gc3_80 0 n6 ns80 0 -1.98909996312e-007 +Gc3_81 0 n6 ns81 0 -0.00212397368414 +Gc3_82 0 n6 ns82 0 0.0030126029148 +Gc3_83 0 n6 ns83 0 -0.00735730341864 +Gc3_84 0 n6 ns84 0 0.00202428039607 +Gc3_85 0 n6 ns85 0 -0.00574431706539 +Gc3_86 0 n6 ns86 0 -0.0100057956152 +Gc3_87 0 n6 ns87 0 0.000573325105279 +Gc3_88 0 n6 ns88 0 -0.000454647941383 +Gc3_89 0 n6 ns89 0 0.00572190991506 +Gc3_90 0 n6 ns90 0 0.000481126554633 +Gc3_91 0 n6 ns91 0 -0.00584055127177 +Gc3_92 0 n6 ns92 0 -7.62234858814e-005 +Gc3_93 0 n6 ns93 0 -0.000360773521944 +Gc3_94 0 n6 ns94 0 -0.00645156536312 +Gc3_95 0 n6 ns95 0 -0.00708650124569 +Gc3_96 0 n6 ns96 0 -0.00104774762266 +Gc3_97 0 n6 ns97 0 5.64276878273e-007 +Gc3_98 0 n6 ns98 0 -2.62949451093e-007 +Gc3_99 0 n6 ns99 0 0.000535885940881 +Gc3_100 0 n6 ns100 0 -0.000602379150376 +Gc3_101 0 n6 ns101 0 0.0047986662126 +Gc3_102 0 n6 ns102 0 -0.00567820625364 +Gc3_103 0 n6 ns103 0 -0.00727845121727 +Gc3_104 0 n6 ns104 0 0.008305345741 +Gc3_105 0 n6 ns105 0 0.000565443143106 +Gc3_106 0 n6 ns106 0 4.95181526028e-005 +Gc3_107 0 n6 ns107 0 0.00109300576978 +Gc3_108 0 n6 ns108 0 -0.00206015938226 +Gd3_1 0 n6 ni1 0 -0.000374384590136 +Gd3_2 0 n6 ni2 0 -0.000217230463744 +Gd3_3 0 n6 ni3 0 -0.000878664638809 +Gd3_4 0 n6 ni4 0 -0.00126697646583 +Gd3_5 0 n6 ni5 0 -0.0016255513992 +Gd3_6 0 n6 ni6 0 -0.000257270691943 +Gc4_1 0 n8 ns1 0 -0.0058398012179 +Gc4_2 0 n8 ns2 0 -7.7976274014e-005 +Gc4_3 0 n8 ns3 0 -0.000385738342346 +Gc4_4 0 n8 ns4 0 -0.00638839031333 +Gc4_5 0 n8 ns5 0 -0.00780505446709 +Gc4_6 0 n8 ns6 0 -0.00152715640548 +Gc4_7 0 n8 ns7 0 3.28666212846e-007 +Gc4_8 0 n8 ns8 0 -1.82770956765e-007 +Gc4_9 0 n8 ns9 0 -0.0051483371891 +Gc4_10 0 n8 ns10 0 0.00532341975269 +Gc4_11 0 n8 ns11 0 0.0055277324369 +Gc4_12 0 n8 ns12 0 -0.0278139883224 +Gc4_13 0 n8 ns13 0 0.00524502467815 +Gc4_14 0 n8 ns14 0 0.00824509989249 +Gc4_15 0 n8 ns15 0 -0.00139103823842 +Gc4_16 0 n8 ns16 0 -0.0031949982218 +Gc4_17 0 n8 ns17 0 0.000507545815021 +Gc4_18 0 n8 ns18 0 0.010269736819 +Gc4_19 0 n8 ns19 0 -0.00578800531705 +Gc4_20 0 n8 ns20 0 -1.74504812804e-005 +Gc4_21 0 n8 ns21 0 0.00012776442398 +Gc4_22 0 n8 ns22 0 0.00295551376979 +Gc4_23 0 n8 ns23 0 0.00411024102714 +Gc4_24 0 n8 ns24 0 0.00109491618492 +Gc4_25 0 n8 ns25 0 2.09831384481e-007 +Gc4_26 0 n8 ns26 0 -3.89150570637e-007 +Gc4_27 0 n8 ns27 0 -0.000408905464957 +Gc4_28 0 n8 ns28 0 -0.00223138191034 +Gc4_29 0 n8 ns29 0 -0.00497834411767 +Gc4_30 0 n8 ns30 0 0.00358973789533 +Gc4_31 0 n8 ns31 0 -0.00211121283861 +Gc4_32 0 n8 ns32 0 -0.0034217625933 +Gc4_33 0 n8 ns33 0 0.000469672096031 +Gc4_34 0 n8 ns34 0 -0.000811867511265 +Gc4_35 0 n8 ns35 0 0.00155389723998 +Gc4_36 0 n8 ns36 0 0.00145712098806 +Gc4_37 0 n8 ns37 0 -0.00578648844034 +Gc4_38 0 n8 ns38 0 -1.55258766882e-005 +Gc4_39 0 n8 ns39 0 0.000117922600864 +Gc4_40 0 n8 ns40 0 0.00350367394665 +Gc4_41 0 n8 ns41 0 0.00343806696787 +Gc4_42 0 n8 ns42 0 0.000572759549981 +Gc4_43 0 n8 ns43 0 4.79986268418e-007 +Gc4_44 0 n8 ns44 0 -1.69735204564e-007 +Gc4_45 0 n8 ns45 0 0.00020566625242 +Gc4_46 0 n8 ns46 0 0.00172676467827 +Gc4_47 0 n8 ns47 0 -0.0052912324168 +Gc4_48 0 n8 ns48 0 0.000762323598431 +Gc4_49 0 n8 ns49 0 -0.00538314929265 +Gc4_50 0 n8 ns50 0 -0.00619587841766 +Gc4_51 0 n8 ns51 0 0.000756584069282 +Gc4_52 0 n8 ns52 0 -0.000441286746163 +Gc4_53 0 n8 ns53 0 0.00334949859768 +Gc4_54 0 n8 ns54 0 0.000915224473245 +Gc4_55 0 n8 ns55 0 0.00581641588759 +Gc4_56 0 n8 ns56 0 7.84444796844e-005 +Gc4_57 0 n8 ns57 0 0.000379198497519 +Gc4_58 0 n8 ns58 0 0.00632718606813 +Gc4_59 0 n8 ns59 0 0.00770223736112 +Gc4_60 0 n8 ns60 0 0.00130096985879 +Gc4_61 0 n8 ns61 0 2.54503432673e-007 +Gc4_62 0 n8 ns62 0 -2.04812046175e-007 +Gc4_63 0 n8 ns63 0 0.00692831980581 +Gc4_64 0 n8 ns64 0 -0.0037831120367 +Gc4_65 0 n8 ns65 0 -0.00135369142487 +Gc4_66 0 n8 ns66 0 0.0401150213919 +Gc4_67 0 n8 ns67 0 -0.00252376401846 +Gc4_68 0 n8 ns68 0 -0.00304055457867 +Gc4_69 0 n8 ns69 0 0.000823755993616 +Gc4_70 0 n8 ns70 0 0.00241308706568 +Gc4_71 0 n8 ns71 0 -0.0027342922644 +Gc4_72 0 n8 ns72 0 -4.01140906746e-005 +Gc4_73 0 n8 ns73 0 0.00579260690236 +Gc4_74 0 n8 ns74 0 1.98702195672e-005 +Gc4_75 0 n8 ns75 0 -0.000141234745488 +Gc4_76 0 n8 ns76 0 -0.00281484293839 +Gc4_77 0 n8 ns77 0 -0.00427954997849 +Gc4_78 0 n8 ns78 0 -0.00085117862784 +Gc4_79 0 n8 ns79 0 1.29642336305e-007 +Gc4_80 0 n8 ns80 0 -3.77466461366e-007 +Gc4_81 0 n8 ns81 0 0.000979880729514 +Gc4_82 0 n8 ns82 0 0.00469103940969 +Gc4_83 0 n8 ns83 0 0.00375143398771 +Gc4_84 0 n8 ns84 0 -0.00121115985853 +Gc4_85 0 n8 ns85 0 -0.00173559977979 +Gc4_86 0 n8 ns86 0 0.00336276181405 +Gc4_87 0 n8 ns87 0 -0.000178373091404 +Gc4_88 0 n8 ns88 0 0.00123739561092 +Gc4_89 0 n8 ns89 0 -0.00541554224423 +Gc4_90 0 n8 ns90 0 -0.00692090423263 +Gc4_91 0 n8 ns91 0 0.00579242218802 +Gc4_92 0 n8 ns92 0 1.59751279459e-005 +Gc4_93 0 n8 ns93 0 -0.000114767963527 +Gc4_94 0 n8 ns94 0 -0.00348098093928 +Gc4_95 0 n8 ns95 0 -0.00341629742124 +Gc4_96 0 n8 ns96 0 -0.000563804114463 +Gc4_97 0 n8 ns97 0 4.7411925988e-007 +Gc4_98 0 n8 ns98 0 -1.60325147803e-007 +Gc4_99 0 n8 ns99 0 -0.000278411075717 +Gc4_100 0 n8 ns100 0 9.66923641126e-006 +Gc4_101 0 n8 ns101 0 0.00249442536739 +Gc4_102 0 n8 ns102 0 -0.000470555031076 +Gc4_103 0 n8 ns103 0 0.00183033667732 +Gc4_104 0 n8 ns104 0 0.00456209621368 +Gc4_105 0 n8 ns105 0 -0.000192695890074 +Gc4_106 0 n8 ns106 0 0.000480327748906 +Gc4_107 0 n8 ns107 0 -0.00535081931738 +Gc4_108 0 n8 ns108 0 -0.0036504880872 +Gd4_1 0 n8 ni1 0 0.000914045545752 +Gd4_2 0 n8 ni2 0 -0.00108582111759 +Gd4_3 0 n8 ni3 0 -0.00131877825139 +Gd4_4 0 n8 ni4 0 -0.000967269582166 +Gd4_5 0 n8 ni5 0 -0.00101587879295 +Gd4_6 0 n8 ni6 0 -0.000710629289769 +Gc5_1 0 n10 ns1 0 -0.00579209483796 +Gc5_2 0 n10 ns2 0 -1.65482028275e-005 +Gc5_3 0 n10 ns3 0 0.000121978471108 +Gc5_4 0 n10 ns4 0 0.00294064070324 +Gc5_5 0 n10 ns5 0 0.00407800009599 +Gc5_6 0 n10 ns6 0 0.00114668519476 +Gc5_7 0 n10 ns7 0 6.83211740375e-008 +Gc5_8 0 n10 ns8 0 -2.26909451726e-007 +Gc5_9 0 n10 ns9 0 -0.000200197048181 +Gc5_10 0 n10 ns10 0 -0.00184173502857 +Gc5_11 0 n10 ns11 0 -0.00267775183142 +Gc5_12 0 n10 ns12 0 0.00369862390928 +Gc5_13 0 n10 ns13 0 -0.00245636993393 +Gc5_14 0 n10 ns14 0 -0.00165190069387 +Gc5_15 0 n10 ns15 0 0.000165363305495 +Gc5_16 0 n10 ns16 0 -0.00091713298958 +Gc5_17 0 n10 ns17 0 0.00116336210409 +Gc5_18 0 n10 ns18 0 0.00117069603803 +Gc5_19 0 n10 ns19 0 -0.00583574414626 +Gc5_20 0 n10 ns20 0 -7.66612957396e-005 +Gc5_21 0 n10 ns21 0 -0.000367744832517 +Gc5_22 0 n10 ns22 0 -0.00620061758866 +Gc5_23 0 n10 ns23 0 -0.00822376690344 +Gc5_24 0 n10 ns24 0 -0.00181537535935 +Gc5_25 0 n10 ns25 0 7.65347117282e-007 +Gc5_26 0 n10 ns26 0 -2.26782267669e-007 +Gc5_27 0 n10 ns27 0 0.000812332207666 +Gc5_28 0 n10 ns28 0 0.00263504856431 +Gc5_29 0 n10 ns29 0 -0.0104449231996 +Gc5_30 0 n10 ns30 0 -0.0418192257923 +Gc5_31 0 n10 ns31 0 0.00798612704226 +Gc5_32 0 n10 ns32 0 0.0116689182588 +Gc5_33 0 n10 ns33 0 -0.000608487535206 +Gc5_34 0 n10 ns34 0 -0.00201790858766 +Gc5_35 0 n10 ns35 0 -0.00238216833012 +Gc5_36 0 n10 ns36 0 0.00720986337642 +Gc5_37 0 n10 ns37 0 -0.00578132748285 +Gc5_38 0 n10 ns38 0 -1.6520933573e-005 +Gc5_39 0 n10 ns39 0 0.000108424478199 +Gc5_40 0 n10 ns40 0 0.0032324614912 +Gc5_41 0 n10 ns41 0 0.00377379864918 +Gc5_42 0 n10 ns42 0 0.000645132330329 +Gc5_43 0 n10 ns43 0 3.28049940453e-007 +Gc5_44 0 n10 ns44 0 -2.27060899756e-007 +Gc5_45 0 n10 ns45 0 -0.00209646687405 +Gc5_46 0 n10 ns46 0 0.00309058295849 +Gc5_47 0 n10 ns47 0 -0.00731052249189 +Gc5_48 0 n10 ns48 0 0.00211157832061 +Gc5_49 0 n10 ns49 0 -0.00583717211122 +Gc5_50 0 n10 ns50 0 -0.00994781674409 +Gc5_51 0 n10 ns51 0 0.000583553394731 +Gc5_52 0 n10 ns52 0 -0.000430854369283 +Gc5_53 0 n10 ns53 0 0.00563780689288 +Gc5_54 0 n10 ns54 0 0.000318138482725 +Gc5_55 0 n10 ns55 0 0.00578884805061 +Gc5_56 0 n10 ns56 0 2.04236665875e-005 +Gc5_57 0 n10 ns57 0 -0.00014219073333 +Gc5_58 0 n10 ns58 0 -0.00280908834502 +Gc5_59 0 n10 ns59 0 -0.004291150629 +Gc5_60 0 n10 ns60 0 -0.000837128968701 +Gc5_61 0 n10 ns61 0 9.55188660567e-008 +Gc5_62 0 n10 ns62 0 -3.88036539717e-007 +Gc5_63 0 n10 ns63 0 0.000968306882798 +Gc5_64 0 n10 ns64 0 0.00476087292416 +Gc5_65 0 n10 ns65 0 0.00387319228782 +Gc5_66 0 n10 ns66 0 -0.00113443817913 +Gc5_67 0 n10 ns67 0 -0.00177905866666 +Gc5_68 0 n10 ns68 0 0.00334079620093 +Gc5_69 0 n10 ns69 0 -0.000174745238694 +Gc5_70 0 n10 ns70 0 0.00122862106875 +Gc5_71 0 n10 ns71 0 -0.00544101430216 +Gc5_72 0 n10 ns72 0 -0.00691990063372 +Gc5_73 0 n10 ns73 0 0.00582601177381 +Gc5_74 0 n10 ns74 0 7.79049402156e-005 +Gc5_75 0 n10 ns75 0 0.000379762593408 +Gc5_76 0 n10 ns76 0 0.0059892033553 +Gc5_77 0 n10 ns77 0 0.0084955529097 +Gc5_78 0 n10 ns78 0 0.00133846543254 +Gc5_79 0 n10 ns79 0 9.02973779281e-007 +Gc5_80 0 n10 ns80 0 2.20771473938e-008 +Gc5_81 0 n10 ns81 0 0.0021070776977 +Gc5_82 0 n10 ns82 0 -0.00520610979535 +Gc5_83 0 n10 ns83 0 0.0113808358254 +Gc5_84 0 n10 ns84 0 0.0496591547045 +Gc5_85 0 n10 ns85 0 -0.00157268514308 +Gc5_86 0 n10 ns86 0 -0.00473355972088 +Gc5_87 0 n10 ns87 0 0.000685256090291 +Gc5_88 0 n10 ns88 0 0.00114015195036 +Gc5_89 0 n10 ns89 0 -0.000484934723987 +Gc5_90 0 n10 ns90 0 0.0061799915692 +Gc5_91 0 n10 ns91 0 0.00578698687484 +Gc5_92 0 n10 ns92 0 1.81238899209e-005 +Gc5_93 0 n10 ns93 0 -0.000117645235545 +Gc5_94 0 n10 ns94 0 -0.00311352512237 +Gc5_95 0 n10 ns95 0 -0.00389581581168 +Gc5_96 0 n10 ns96 0 -0.000461648999631 +Gc5_97 0 n10 ns97 0 1.40277271869e-007 +Gc5_98 0 n10 ns98 0 -1.75689873507e-007 +Gc5_99 0 n10 ns99 0 0.00180475802715 +Gc5_100 0 n10 ns100 0 0.000512988610809 +Gc5_101 0 n10 ns101 0 0.00463150427303 +Gc5_102 0 n10 ns102 0 0.000246152773828 +Gc5_103 0 n10 ns103 0 0.00061015191358 +Gc5_104 0 n10 ns104 0 0.00602327624445 +Gc5_105 0 n10 ns105 0 -0.000169610686666 +Gc5_106 0 n10 ns106 0 0.000701374782059 +Gc5_107 0 n10 ns107 0 -0.00707636272637 +Gc5_108 0 n10 ns108 0 -0.00430442460306 +Gd5_1 0 n10 ni1 0 -0.000787636669106 +Gd5_2 0 n10 ni2 0 -0.00196416545072 +Gd5_3 0 n10 ni3 0 -0.00167313159846 +Gd5_4 0 n10 ni4 0 -0.0010058177921 +Gd5_5 0 n10 ni5 0 0.00263580504854 +Gd5_6 0 n10 ni6 0 -0.000597165084448 +Gc6_1 0 n12 ns1 0 -0.00578989196443 +Gc6_2 0 n12 ns2 0 -1.51776735722e-005 +Gc6_3 0 n12 ns3 0 0.000115183299339 +Gc6_4 0 n12 ns4 0 0.00346962217783 +Gc6_5 0 n12 ns5 0 0.00348095581153 +Gc6_6 0 n12 ns6 0 0.000559725108899 +Gc6_7 0 n12 ns7 0 4.33805494329e-007 +Gc6_8 0 n12 ns8 0 -3.87789253838e-008 +Gc6_9 0 n12 ns9 0 0.000299763397585 +Gc6_10 0 n12 ns10 0 0.00110396126719 +Gc6_11 0 n12 ns11 0 -0.00589126155265 +Gc6_12 0 n12 ns12 0 -0.000115360735115 +Gc6_13 0 n12 ns13 0 -0.00203864003226 +Gc6_14 0 n12 ns14 0 -0.00540388461004 +Gc6_15 0 n12 ns15 0 0.000430954378139 +Gc6_16 0 n12 ns16 0 -0.000552120313782 +Gc6_17 0 n12 ns17 0 0.000758541505739 +Gc6_18 0 n12 ns18 0 0.00130121679674 +Gc6_19 0 n12 ns19 0 -0.00578600120131 +Gc6_20 0 n12 ns20 0 -1.58346828996e-005 +Gc6_21 0 n12 ns21 0 0.000106267903519 +Gc6_22 0 n12 ns22 0 0.00322058264477 +Gc6_23 0 n12 ns23 0 0.00375644315983 +Gc6_24 0 n12 ns24 0 0.000635711828612 +Gc6_25 0 n12 ns25 0 3.29009724735e-007 +Gc6_26 0 n12 ns26 0 -2.19815087584e-007 +Gc6_27 0 n12 ns27 0 -0.00192315715789 +Gc6_28 0 n12 ns28 0 0.002367407387 +Gc6_29 0 n12 ns29 0 -0.00514779088728 +Gc6_30 0 n12 ns30 0 0.000570553601364 +Gc6_31 0 n12 ns31 0 -0.00290767188539 +Gc6_32 0 n12 ns32 0 -0.00681253791935 +Gc6_33 0 n12 ns33 0 0.00036471066112 +Gc6_34 0 n12 ns34 0 -0.0006678702615 +Gc6_35 0 n12 ns35 0 0.00320621649052 +Gc6_36 0 n12 ns36 0 0.00114582443426 +Gc6_37 0 n12 ns37 0 -0.00583524940852 +Gc6_38 0 n12 ns38 0 -7.64535168754e-005 +Gc6_39 0 n12 ns39 0 -0.000359267702485 +Gc6_40 0 n12 ns40 0 -0.00648488042789 +Gc6_41 0 n12 ns41 0 -0.00704753233827 +Gc6_42 0 n12 ns42 0 -0.00106123524796 +Gc6_43 0 n12 ns43 0 5.79988754832e-007 +Gc6_44 0 n12 ns44 0 -2.54238664546e-007 +Gc6_45 0 n12 ns45 0 0.000499261504254 +Gc6_46 0 n12 ns46 0 -0.000710802353173 +Gc6_47 0 n12 ns47 0 0.00471387284122 +Gc6_48 0 n12 ns48 0 -0.00576682421517 +Gc6_49 0 n12 ns49 0 -0.00716410249264 +Gc6_50 0 n12 ns50 0 0.00824736230815 +Gc6_51 0 n12 ns51 0 0.000551559470553 +Gc6_52 0 n12 ns52 0 2.98313641125e-005 +Gc6_53 0 n12 ns53 0 0.00119188585194 +Gc6_54 0 n12 ns54 0 -0.00189551666094 +Gc6_55 0 n12 ns55 0 0.0057876270808 +Gc6_56 0 n12 ns56 0 1.64072698936e-005 +Gc6_57 0 n12 ns57 0 -0.000115016763741 +Gc6_58 0 n12 ns58 0 -0.00347819082236 +Gc6_59 0 n12 ns59 0 -0.00342435339101 +Gc6_60 0 n12 ns60 0 -0.000554999726465 +Gc6_61 0 n12 ns61 0 4.51999416587e-007 +Gc6_62 0 n12 ns62 0 -1.7557959128e-007 +Gc6_63 0 n12 ns63 0 -0.00027394845639 +Gc6_64 0 n12 ns64 0 3.0469832114e-005 +Gc6_65 0 n12 ns65 0 0.0025476112506 +Gc6_66 0 n12 ns66 0 -0.000442208104257 +Gc6_67 0 n12 ns67 0 0.00181879759838 +Gc6_68 0 n12 ns68 0 0.00456821195987 +Gc6_69 0 n12 ns69 0 -0.000188180689616 +Gc6_70 0 n12 ns70 0 0.000480845601471 +Gc6_71 0 n12 ns71 0 -0.00537354547816 +Gc6_72 0 n12 ns72 0 -0.0036539281166 +Gc6_73 0 n12 ns73 0 0.00578501635146 +Gc6_74 0 n12 ns74 0 1.87138847907e-005 +Gc6_75 0 n12 ns75 0 -0.000118871527505 +Gc6_76 0 n12 ns76 0 -0.00310870689837 +Gc6_77 0 n12 ns77 0 -0.00390622422072 +Gc6_78 0 n12 ns78 0 -0.000448829984991 +Gc6_79 0 n12 ns79 0 1.16818850188e-007 +Gc6_80 0 n12 ns80 0 -1.9364485858e-007 +Gc6_81 0 n12 ns81 0 0.00174824751762 +Gc6_82 0 n12 ns82 0 0.000570840535715 +Gc6_83 0 n12 ns83 0 0.0046681608283 +Gc6_84 0 n12 ns84 0 0.00031654797566 +Gc6_85 0 n12 ns85 0 0.000570513589127 +Gc6_86 0 n12 ns86 0 0.0059448335874 +Gc6_87 0 n12 ns87 0 -0.000174550405069 +Gc6_88 0 n12 ns88 0 0.000688729867393 +Gc6_89 0 n12 ns89 0 -0.00703063005239 +Gc6_90 0 n12 ns90 0 -0.00430294482417 +Gc6_91 0 n12 ns91 0 0.00582512772081 +Gc6_92 0 n12 ns92 0 7.93143352783e-005 +Gc6_93 0 n12 ns93 0 0.00035708020289 +Gc6_94 0 n12 ns94 0 0.00635576907019 +Gc6_95 0 n12 ns95 0 0.00715330815047 +Gc6_96 0 n12 ns96 0 0.000771054957188 +Gc6_97 0 n12 ns97 0 7.60659416992e-007 +Gc6_98 0 n12 ns98 0 -4.73136679908e-008 +Gc6_99 0 n12 ns99 0 0.00183786161598 +Gc6_100 0 n12 ns100 0 -0.00113366565425 +Gc6_101 0 n12 ns101 0 -0.00413291617328 +Gc6_102 0 n12 ns102 0 0.0174266751447 +Gc6_103 0 n12 ns103 0 0.00857619688779 +Gc6_104 0 n12 ns104 0 -0.00267545875983 +Gc6_105 0 n12 ns105 0 -0.000473603562537 +Gc6_106 0 n12 ns106 0 -0.000550756951534 +Gc6_107 0 n12 ns107 0 -0.000383184543649 +Gc6_108 0 n12 ns108 0 0.0124701138144 +Gd6_1 0 n12 ni1 0 -0.00143514682747 +Gd6_2 0 n12 ni2 0 -0.00119690178743 +Gd6_3 0 n12 ni3 0 -0.000214209645216 +Gd6_4 0 n12 ni4 0 -0.000705617070789 +Gd6_5 0 n12 ni5 0 -0.000595354152146 +Gd6_6 0 n12 ni6 0 0.000281014148637 +.ends + +.subckt 744838180160 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 476027131.749 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 4704469.72566 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 733626.5727 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 210078.283552 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 142288.358404 +Ca6 ns6 0 1e-012 +Ca7 ns7 0 1e-012 +Ra6 ns6 0 2928236.14056 +Ra7 ns7 0 2928236.14056 +Ga6 ns6 0 ns7 0 1.82579664235e-005 +Ga7 ns7 0 ns6 0 -1.82579664235e-005 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 2825439.69786 +Ra9 ns9 0 2825439.69786 +Ga8 ns8 0 ns9 0 1.94899201128e-005 +Ga9 ns9 0 ns8 0 -1.94899201128e-005 +Ca10 ns10 0 1e-012 +Ra10 ns10 0 46488.843108 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 4319122.8285 +Ra12 ns12 0 4319122.8285 +Ga11 ns11 0 ns12 0 2.43529279718e-005 +Ga12 ns12 0 ns11 0 -2.43529279718e-005 +Ca13 ns13 0 1e-012 +Ra13 ns13 0 12615.9992094 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 29002.6055911 +Ra15 ns15 0 29002.6055911 +Ga14 ns14 0 ns15 0 -0.000163352208257 +Ga15 ns15 0 ns14 0 0.000163352208257 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 30092.8599283 +Ra17 ns17 0 30092.8599283 +Ga16 ns16 0 ns17 0 0.000173230749945 +Ga17 ns17 0 ns16 0 -0.000173230749945 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 23871.6896782 +Ra19 ns19 0 23871.6896782 +Ga18 ns18 0 ns19 0 0.000204201202841 +Ga19 ns19 0 ns18 0 -0.000204201202841 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 190609.553557 +Ra21 ns21 0 190609.553557 +Ga20 ns20 0 ns21 0 0.000215857549724 +Ga21 ns21 0 ns20 0 -0.000215857549724 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 26296.4202096 +Ra23 ns23 0 26296.4202096 +Ga22 ns22 0 ns23 0 0.000294807361249 +Ga23 ns23 0 ns22 0 -0.000294807361249 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 86023.3829961 +Ra25 ns25 0 86023.3829961 +Ga24 ns24 0 ns25 0 0.000439439884015 +Ga25 ns25 0 ns24 0 -0.000439439884015 +Ca26 ns26 0 1e-012 +Ca27 ns27 0 1e-012 +Ra26 ns26 0 12765.7384055 +Ra27 ns27 0 12765.7384055 +Ga26 ns26 0 ns27 0 0.00057482785604 +Ga27 ns27 0 ns26 0 -0.00057482785604 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 7278.99871562 +Ra29 ns29 0 7278.99871562 +Ga28 ns28 0 ns29 0 0.000568317673258 +Ga29 ns29 0 ns28 0 -0.000568317673258 +Ca30 ns30 0 1e-012 +Ca31 ns31 0 1e-012 +Ra30 ns30 0 12147.347759 +Ra31 ns31 0 12147.347759 +Ga30 ns30 0 ns31 0 -0.00062126172471 +Ga31 ns31 0 ns30 0 0.00062126172471 +Ca32 ns32 0 1e-012 +Ca33 ns33 0 1e-012 +Ra32 ns32 0 1866.7397854 +Ra33 ns33 0 1866.7397854 +Ga32 ns32 0 ns33 0 0.000409050785383 +Ga33 ns33 0 ns32 0 -0.000409050785383 +Ca34 ns34 0 1e-012 +Ca35 ns35 0 1e-012 +Ra34 ns34 0 10881.6746664 +Ra35 ns35 0 10881.6746664 +Ga34 ns34 0 ns35 0 0.00075860717423 +Ga35 ns35 0 ns34 0 -0.00075860717423 +Ca36 ns36 0 1e-012 +Ra36 ns36 0 476027131.749 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 4704469.72566 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 733626.5727 +Ca39 ns39 0 1e-012 +Ra39 ns39 0 210078.283552 +Ca40 ns40 0 1e-012 +Ra40 ns40 0 142288.358404 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 2928236.14056 +Ra42 ns42 0 2928236.14056 +Ga41 ns41 0 ns42 0 1.82579664235e-005 +Ga42 ns42 0 ns41 0 -1.82579664235e-005 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 2825439.69786 +Ra44 ns44 0 2825439.69786 +Ga43 ns43 0 ns44 0 1.94899201128e-005 +Ga44 ns44 0 ns43 0 -1.94899201128e-005 +Ca45 ns45 0 1e-012 +Ra45 ns45 0 46488.843108 +Ca46 ns46 0 1e-012 +Ca47 ns47 0 1e-012 +Ra46 ns46 0 4319122.8285 +Ra47 ns47 0 4319122.8285 +Ga46 ns46 0 ns47 0 2.43529279718e-005 +Ga47 ns47 0 ns46 0 -2.43529279718e-005 +Ca48 ns48 0 1e-012 +Ra48 ns48 0 12615.9992094 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 29002.6055911 +Ra50 ns50 0 29002.6055911 +Ga49 ns49 0 ns50 0 -0.000163352208257 +Ga50 ns50 0 ns49 0 0.000163352208257 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 30092.8599283 +Ra52 ns52 0 30092.8599283 +Ga51 ns51 0 ns52 0 0.000173230749945 +Ga52 ns52 0 ns51 0 -0.000173230749945 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 23871.6896782 +Ra54 ns54 0 23871.6896782 +Ga53 ns53 0 ns54 0 0.000204201202841 +Ga54 ns54 0 ns53 0 -0.000204201202841 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 190609.553557 +Ra56 ns56 0 190609.553557 +Ga55 ns55 0 ns56 0 0.000215857549724 +Ga56 ns56 0 ns55 0 -0.000215857549724 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 26296.4202096 +Ra58 ns58 0 26296.4202096 +Ga57 ns57 0 ns58 0 0.000294807361249 +Ga58 ns58 0 ns57 0 -0.000294807361249 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 86023.3829961 +Ra60 ns60 0 86023.3829961 +Ga59 ns59 0 ns60 0 0.000439439884015 +Ga60 ns60 0 ns59 0 -0.000439439884015 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 12765.7384055 +Ra62 ns62 0 12765.7384055 +Ga61 ns61 0 ns62 0 0.00057482785604 +Ga62 ns62 0 ns61 0 -0.00057482785604 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 7278.99871562 +Ra64 ns64 0 7278.99871562 +Ga63 ns63 0 ns64 0 0.000568317673258 +Ga64 ns64 0 ns63 0 -0.000568317673258 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 12147.347759 +Ra66 ns66 0 12147.347759 +Ga65 ns65 0 ns66 0 -0.00062126172471 +Ga66 ns66 0 ns65 0 0.00062126172471 +Ca67 ns67 0 1e-012 +Ca68 ns68 0 1e-012 +Ra67 ns67 0 1866.7397854 +Ra68 ns68 0 1866.7397854 +Ga67 ns67 0 ns68 0 0.000409050785383 +Ga68 ns68 0 ns67 0 -0.000409050785383 +Ca69 ns69 0 1e-012 +Ca70 ns70 0 1e-012 +Ra69 ns69 0 10881.6746664 +Ra70 ns70 0 10881.6746664 +Ga69 ns69 0 ns70 0 0.00075860717423 +Ga70 ns70 0 ns69 0 -0.00075860717423 +Ca71 ns71 0 1e-012 +Ra71 ns71 0 476027131.749 +Ca72 ns72 0 1e-012 +Ra72 ns72 0 4704469.72566 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 733626.5727 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 210078.283552 +Ca75 ns75 0 1e-012 +Ra75 ns75 0 142288.358404 +Ca76 ns76 0 1e-012 +Ca77 ns77 0 1e-012 +Ra76 ns76 0 2928236.14056 +Ra77 ns77 0 2928236.14056 +Ga76 ns76 0 ns77 0 1.82579664235e-005 +Ga77 ns77 0 ns76 0 -1.82579664235e-005 +Ca78 ns78 0 1e-012 +Ca79 ns79 0 1e-012 +Ra78 ns78 0 2825439.69786 +Ra79 ns79 0 2825439.69786 +Ga78 ns78 0 ns79 0 1.94899201128e-005 +Ga79 ns79 0 ns78 0 -1.94899201128e-005 +Ca80 ns80 0 1e-012 +Ra80 ns80 0 46488.843108 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 4319122.8285 +Ra82 ns82 0 4319122.8285 +Ga81 ns81 0 ns82 0 2.43529279718e-005 +Ga82 ns82 0 ns81 0 -2.43529279718e-005 +Ca83 ns83 0 1e-012 +Ra83 ns83 0 12615.9992094 +Ca84 ns84 0 1e-012 +Ca85 ns85 0 1e-012 +Ra84 ns84 0 29002.6055911 +Ra85 ns85 0 29002.6055911 +Ga84 ns84 0 ns85 0 -0.000163352208257 +Ga85 ns85 0 ns84 0 0.000163352208257 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 30092.8599283 +Ra87 ns87 0 30092.8599283 +Ga86 ns86 0 ns87 0 0.000173230749945 +Ga87 ns87 0 ns86 0 -0.000173230749945 +Ca88 ns88 0 1e-012 +Ca89 ns89 0 1e-012 +Ra88 ns88 0 23871.6896782 +Ra89 ns89 0 23871.6896782 +Ga88 ns88 0 ns89 0 0.000204201202841 +Ga89 ns89 0 ns88 0 -0.000204201202841 +Ca90 ns90 0 1e-012 +Ca91 ns91 0 1e-012 +Ra90 ns90 0 190609.553557 +Ra91 ns91 0 190609.553557 +Ga90 ns90 0 ns91 0 0.000215857549724 +Ga91 ns91 0 ns90 0 -0.000215857549724 +Ca92 ns92 0 1e-012 +Ca93 ns93 0 1e-012 +Ra92 ns92 0 26296.4202096 +Ra93 ns93 0 26296.4202096 +Ga92 ns92 0 ns93 0 0.000294807361249 +Ga93 ns93 0 ns92 0 -0.000294807361249 +Ca94 ns94 0 1e-012 +Ca95 ns95 0 1e-012 +Ra94 ns94 0 86023.3829961 +Ra95 ns95 0 86023.3829961 +Ga94 ns94 0 ns95 0 0.000439439884015 +Ga95 ns95 0 ns94 0 -0.000439439884015 +Ca96 ns96 0 1e-012 +Ca97 ns97 0 1e-012 +Ra96 ns96 0 12765.7384055 +Ra97 ns97 0 12765.7384055 +Ga96 ns96 0 ns97 0 0.00057482785604 +Ga97 ns97 0 ns96 0 -0.00057482785604 +Ca98 ns98 0 1e-012 +Ca99 ns99 0 1e-012 +Ra98 ns98 0 7278.99871562 +Ra99 ns99 0 7278.99871562 +Ga98 ns98 0 ns99 0 0.000568317673258 +Ga99 ns99 0 ns98 0 -0.000568317673258 +Ca100 ns100 0 1e-012 +Ca101 ns101 0 1e-012 +Ra100 ns100 0 12147.347759 +Ra101 ns101 0 12147.347759 +Ga100 ns100 0 ns101 0 -0.00062126172471 +Ga101 ns101 0 ns100 0 0.00062126172471 +Ca102 ns102 0 1e-012 +Ca103 ns103 0 1e-012 +Ra102 ns102 0 1866.7397854 +Ra103 ns103 0 1866.7397854 +Ga102 ns102 0 ns103 0 0.000409050785383 +Ga103 ns103 0 ns102 0 -0.000409050785383 +Ca104 ns104 0 1e-012 +Ca105 ns105 0 1e-012 +Ra104 ns104 0 10881.6746664 +Ra105 ns105 0 10881.6746664 +Ga104 ns104 0 ns105 0 0.00075860717423 +Ga105 ns105 0 ns104 0 -0.00075860717423 +Ca106 ns106 0 1e-012 +Ra106 ns106 0 476027131.749 +Ca107 ns107 0 1e-012 +Ra107 ns107 0 4704469.72566 +Ca108 ns108 0 1e-012 +Ra108 ns108 0 733626.5727 +Ca109 ns109 0 1e-012 +Ra109 ns109 0 210078.283552 +Ca110 ns110 0 1e-012 +Ra110 ns110 0 142288.358404 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 2928236.14056 +Ra112 ns112 0 2928236.14056 +Ga111 ns111 0 ns112 0 1.82579664235e-005 +Ga112 ns112 0 ns111 0 -1.82579664235e-005 +Ca113 ns113 0 1e-012 +Ca114 ns114 0 1e-012 +Ra113 ns113 0 2825439.69786 +Ra114 ns114 0 2825439.69786 +Ga113 ns113 0 ns114 0 1.94899201128e-005 +Ga114 ns114 0 ns113 0 -1.94899201128e-005 +Ca115 ns115 0 1e-012 +Ra115 ns115 0 46488.843108 +Ca116 ns116 0 1e-012 +Ca117 ns117 0 1e-012 +Ra116 ns116 0 4319122.8285 +Ra117 ns117 0 4319122.8285 +Ga116 ns116 0 ns117 0 2.43529279718e-005 +Ga117 ns117 0 ns116 0 -2.43529279718e-005 +Ca118 ns118 0 1e-012 +Ra118 ns118 0 12615.9992094 +Ca119 ns119 0 1e-012 +Ca120 ns120 0 1e-012 +Ra119 ns119 0 29002.6055911 +Ra120 ns120 0 29002.6055911 +Ga119 ns119 0 ns120 0 -0.000163352208257 +Ga120 ns120 0 ns119 0 0.000163352208257 +Ca121 ns121 0 1e-012 +Ca122 ns122 0 1e-012 +Ra121 ns121 0 30092.8599283 +Ra122 ns122 0 30092.8599283 +Ga121 ns121 0 ns122 0 0.000173230749945 +Ga122 ns122 0 ns121 0 -0.000173230749945 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 23871.6896782 +Ra124 ns124 0 23871.6896782 +Ga123 ns123 0 ns124 0 0.000204201202841 +Ga124 ns124 0 ns123 0 -0.000204201202841 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 190609.553557 +Ra126 ns126 0 190609.553557 +Ga125 ns125 0 ns126 0 0.000215857549724 +Ga126 ns126 0 ns125 0 -0.000215857549724 +Ca127 ns127 0 1e-012 +Ca128 ns128 0 1e-012 +Ra127 ns127 0 26296.4202096 +Ra128 ns128 0 26296.4202096 +Ga127 ns127 0 ns128 0 0.000294807361249 +Ga128 ns128 0 ns127 0 -0.000294807361249 +Ca129 ns129 0 1e-012 +Ca130 ns130 0 1e-012 +Ra129 ns129 0 86023.3829961 +Ra130 ns130 0 86023.3829961 +Ga129 ns129 0 ns130 0 0.000439439884015 +Ga130 ns130 0 ns129 0 -0.000439439884015 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 12765.7384055 +Ra132 ns132 0 12765.7384055 +Ga131 ns131 0 ns132 0 0.00057482785604 +Ga132 ns132 0 ns131 0 -0.00057482785604 +Ca133 ns133 0 1e-012 +Ca134 ns134 0 1e-012 +Ra133 ns133 0 7278.99871562 +Ra134 ns134 0 7278.99871562 +Ga133 ns133 0 ns134 0 0.000568317673258 +Ga134 ns134 0 ns133 0 -0.000568317673258 +Ca135 ns135 0 1e-012 +Ca136 ns136 0 1e-012 +Ra135 ns135 0 12147.347759 +Ra136 ns136 0 12147.347759 +Ga135 ns135 0 ns136 0 -0.00062126172471 +Ga136 ns136 0 ns135 0 0.00062126172471 +Ca137 ns137 0 1e-012 +Ca138 ns138 0 1e-012 +Ra137 ns137 0 1866.7397854 +Ra138 ns138 0 1866.7397854 +Ga137 ns137 0 ns138 0 0.000409050785383 +Ga138 ns138 0 ns137 0 -0.000409050785383 +Ca139 ns139 0 1e-012 +Ca140 ns140 0 1e-012 +Ra139 ns139 0 10881.6746664 +Ra140 ns140 0 10881.6746664 +Ga139 ns139 0 ns140 0 0.00075860717423 +Ga140 ns140 0 ns139 0 -0.00075860717423 +Ca141 ns141 0 1e-012 +Ra141 ns141 0 476027131.749 +Ca142 ns142 0 1e-012 +Ra142 ns142 0 4704469.72566 +Ca143 ns143 0 1e-012 +Ra143 ns143 0 733626.5727 +Ca144 ns144 0 1e-012 +Ra144 ns144 0 210078.283552 +Ca145 ns145 0 1e-012 +Ra145 ns145 0 142288.358404 +Ca146 ns146 0 1e-012 +Ca147 ns147 0 1e-012 +Ra146 ns146 0 2928236.14056 +Ra147 ns147 0 2928236.14056 +Ga146 ns146 0 ns147 0 1.82579664235e-005 +Ga147 ns147 0 ns146 0 -1.82579664235e-005 +Ca148 ns148 0 1e-012 +Ca149 ns149 0 1e-012 +Ra148 ns148 0 2825439.69786 +Ra149 ns149 0 2825439.69786 +Ga148 ns148 0 ns149 0 1.94899201128e-005 +Ga149 ns149 0 ns148 0 -1.94899201128e-005 +Ca150 ns150 0 1e-012 +Ra150 ns150 0 46488.843108 +Ca151 ns151 0 1e-012 +Ca152 ns152 0 1e-012 +Ra151 ns151 0 4319122.8285 +Ra152 ns152 0 4319122.8285 +Ga151 ns151 0 ns152 0 2.43529279718e-005 +Ga152 ns152 0 ns151 0 -2.43529279718e-005 +Ca153 ns153 0 1e-012 +Ra153 ns153 0 12615.9992094 +Ca154 ns154 0 1e-012 +Ca155 ns155 0 1e-012 +Ra154 ns154 0 29002.6055911 +Ra155 ns155 0 29002.6055911 +Ga154 ns154 0 ns155 0 -0.000163352208257 +Ga155 ns155 0 ns154 0 0.000163352208257 +Ca156 ns156 0 1e-012 +Ca157 ns157 0 1e-012 +Ra156 ns156 0 30092.8599283 +Ra157 ns157 0 30092.8599283 +Ga156 ns156 0 ns157 0 0.000173230749945 +Ga157 ns157 0 ns156 0 -0.000173230749945 +Ca158 ns158 0 1e-012 +Ca159 ns159 0 1e-012 +Ra158 ns158 0 23871.6896782 +Ra159 ns159 0 23871.6896782 +Ga158 ns158 0 ns159 0 0.000204201202841 +Ga159 ns159 0 ns158 0 -0.000204201202841 +Ca160 ns160 0 1e-012 +Ca161 ns161 0 1e-012 +Ra160 ns160 0 190609.553557 +Ra161 ns161 0 190609.553557 +Ga160 ns160 0 ns161 0 0.000215857549724 +Ga161 ns161 0 ns160 0 -0.000215857549724 +Ca162 ns162 0 1e-012 +Ca163 ns163 0 1e-012 +Ra162 ns162 0 26296.4202096 +Ra163 ns163 0 26296.4202096 +Ga162 ns162 0 ns163 0 0.000294807361249 +Ga163 ns163 0 ns162 0 -0.000294807361249 +Ca164 ns164 0 1e-012 +Ca165 ns165 0 1e-012 +Ra164 ns164 0 86023.3829961 +Ra165 ns165 0 86023.3829961 +Ga164 ns164 0 ns165 0 0.000439439884015 +Ga165 ns165 0 ns164 0 -0.000439439884015 +Ca166 ns166 0 1e-012 +Ca167 ns167 0 1e-012 +Ra166 ns166 0 12765.7384055 +Ra167 ns167 0 12765.7384055 +Ga166 ns166 0 ns167 0 0.00057482785604 +Ga167 ns167 0 ns166 0 -0.00057482785604 +Ca168 ns168 0 1e-012 +Ca169 ns169 0 1e-012 +Ra168 ns168 0 7278.99871562 +Ra169 ns169 0 7278.99871562 +Ga168 ns168 0 ns169 0 0.000568317673258 +Ga169 ns169 0 ns168 0 -0.000568317673258 +Ca170 ns170 0 1e-012 +Ca171 ns171 0 1e-012 +Ra170 ns170 0 12147.347759 +Ra171 ns171 0 12147.347759 +Ga170 ns170 0 ns171 0 -0.00062126172471 +Ga171 ns171 0 ns170 0 0.00062126172471 +Ca172 ns172 0 1e-012 +Ca173 ns173 0 1e-012 +Ra172 ns172 0 1866.7397854 +Ra173 ns173 0 1866.7397854 +Ga172 ns172 0 ns173 0 0.000409050785383 +Ga173 ns173 0 ns172 0 -0.000409050785383 +Ca174 ns174 0 1e-012 +Ca175 ns175 0 1e-012 +Ra174 ns174 0 10881.6746664 +Ra175 ns175 0 10881.6746664 +Ga174 ns174 0 ns175 0 0.00075860717423 +Ga175 ns175 0 ns174 0 -0.00075860717423 +Ca176 ns176 0 1e-012 +Ra176 ns176 0 476027131.749 +Ca177 ns177 0 1e-012 +Ra177 ns177 0 4704469.72566 +Ca178 ns178 0 1e-012 +Ra178 ns178 0 733626.5727 +Ca179 ns179 0 1e-012 +Ra179 ns179 0 210078.283552 +Ca180 ns180 0 1e-012 +Ra180 ns180 0 142288.358404 +Ca181 ns181 0 1e-012 +Ca182 ns182 0 1e-012 +Ra181 ns181 0 2928236.14056 +Ra182 ns182 0 2928236.14056 +Ga181 ns181 0 ns182 0 1.82579664235e-005 +Ga182 ns182 0 ns181 0 -1.82579664235e-005 +Ca183 ns183 0 1e-012 +Ca184 ns184 0 1e-012 +Ra183 ns183 0 2825439.69786 +Ra184 ns184 0 2825439.69786 +Ga183 ns183 0 ns184 0 1.94899201128e-005 +Ga184 ns184 0 ns183 0 -1.94899201128e-005 +Ca185 ns185 0 1e-012 +Ra185 ns185 0 46488.843108 +Ca186 ns186 0 1e-012 +Ca187 ns187 0 1e-012 +Ra186 ns186 0 4319122.8285 +Ra187 ns187 0 4319122.8285 +Ga186 ns186 0 ns187 0 2.43529279718e-005 +Ga187 ns187 0 ns186 0 -2.43529279718e-005 +Ca188 ns188 0 1e-012 +Ra188 ns188 0 12615.9992094 +Ca189 ns189 0 1e-012 +Ca190 ns190 0 1e-012 +Ra189 ns189 0 29002.6055911 +Ra190 ns190 0 29002.6055911 +Ga189 ns189 0 ns190 0 -0.000163352208257 +Ga190 ns190 0 ns189 0 0.000163352208257 +Ca191 ns191 0 1e-012 +Ca192 ns192 0 1e-012 +Ra191 ns191 0 30092.8599283 +Ra192 ns192 0 30092.8599283 +Ga191 ns191 0 ns192 0 0.000173230749945 +Ga192 ns192 0 ns191 0 -0.000173230749945 +Ca193 ns193 0 1e-012 +Ca194 ns194 0 1e-012 +Ra193 ns193 0 23871.6896782 +Ra194 ns194 0 23871.6896782 +Ga193 ns193 0 ns194 0 0.000204201202841 +Ga194 ns194 0 ns193 0 -0.000204201202841 +Ca195 ns195 0 1e-012 +Ca196 ns196 0 1e-012 +Ra195 ns195 0 190609.553557 +Ra196 ns196 0 190609.553557 +Ga195 ns195 0 ns196 0 0.000215857549724 +Ga196 ns196 0 ns195 0 -0.000215857549724 +Ca197 ns197 0 1e-012 +Ca198 ns198 0 1e-012 +Ra197 ns197 0 26296.4202096 +Ra198 ns198 0 26296.4202096 +Ga197 ns197 0 ns198 0 0.000294807361249 +Ga198 ns198 0 ns197 0 -0.000294807361249 +Ca199 ns199 0 1e-012 +Ca200 ns200 0 1e-012 +Ra199 ns199 0 86023.3829961 +Ra200 ns200 0 86023.3829961 +Ga199 ns199 0 ns200 0 0.000439439884015 +Ga200 ns200 0 ns199 0 -0.000439439884015 +Ca201 ns201 0 1e-012 +Ca202 ns202 0 1e-012 +Ra201 ns201 0 12765.7384055 +Ra202 ns202 0 12765.7384055 +Ga201 ns201 0 ns202 0 0.00057482785604 +Ga202 ns202 0 ns201 0 -0.00057482785604 +Ca203 ns203 0 1e-012 +Ca204 ns204 0 1e-012 +Ra203 ns203 0 7278.99871562 +Ra204 ns204 0 7278.99871562 +Ga203 ns203 0 ns204 0 0.000568317673258 +Ga204 ns204 0 ns203 0 -0.000568317673258 +Ca205 ns205 0 1e-012 +Ca206 ns206 0 1e-012 +Ra205 ns205 0 12147.347759 +Ra206 ns206 0 12147.347759 +Ga205 ns205 0 ns206 0 -0.00062126172471 +Ga206 ns206 0 ns205 0 0.00062126172471 +Ca207 ns207 0 1e-012 +Ca208 ns208 0 1e-012 +Ra207 ns207 0 1866.7397854 +Ra208 ns208 0 1866.7397854 +Ga207 ns207 0 ns208 0 0.000409050785383 +Ga208 ns208 0 ns207 0 -0.000409050785383 +Ca209 ns209 0 1e-012 +Ca210 ns210 0 1e-012 +Ra209 ns209 0 10881.6746664 +Ra210 ns210 0 10881.6746664 +Ga209 ns209 0 ns210 0 0.00075860717423 +Ga210 ns210 0 ns209 0 -0.00075860717423 + +Gb1_1 ns1 0 ni1 0 2.10072059617e-009 +Gb2_1 ns2 0 ni1 0 2.12563808105e-007 +Gb3_1 ns3 0 ni1 0 1.36309130178e-006 +Gb4_1 ns4 0 ni1 0 4.76013028616e-006 +Gb5_1 ns5 0 ni1 0 7.02798184767e-006 +Gb6_1 ns6 0 ni1 0 1.82643539895e-005 +Gb8_1 ns8 0 ni1 0 1.94963472542e-005 +Gb10_1 ns10 0 ni1 0 2.15105374353e-005 +Gb11_1 ns11 0 ni1 0 2.43551291627e-005 +Gb13_1 ns13 0 ni1 0 7.92644310925e-005 +Gb14_1 ns14 0 ni1 0 0.000170630022339 +Gb16_1 ns16 0 ni1 0 0.000179605278739 +Gb18_1 ns18 0 ni1 0 0.000212794807761 +Gb20_1 ns20 0 ni1 0 0.000215985059484 +Gb22_1 ns22 0 ni1 0 0.00029971269334 +Gb24_1 ns24 0 ni1 0 0.000439747399856 +Gb26_1 ns26 0 ni1 0 0.00058550291575 +Gb28_1 ns28 0 ni1 0 0.000601527419166 +Gb30_1 ns30 0 ni1 0 0.000632170160318 +Gb32_1 ns32 0 ni1 0 0.000848040953993 +Gb34_1 ns34 0 ni1 0 0.000769739645409 +Gb36_2 ns36 0 ni2 0 2.10072059617e-009 +Gb37_2 ns37 0 ni2 0 2.12563808105e-007 +Gb38_2 ns38 0 ni2 0 1.36309130178e-006 +Gb39_2 ns39 0 ni2 0 4.76013028616e-006 +Gb40_2 ns40 0 ni2 0 7.02798184767e-006 +Gb41_2 ns41 0 ni2 0 1.82643539895e-005 +Gb43_2 ns43 0 ni2 0 1.94963472542e-005 +Gb45_2 ns45 0 ni2 0 2.15105374353e-005 +Gb46_2 ns46 0 ni2 0 2.43551291627e-005 +Gb48_2 ns48 0 ni2 0 7.92644310925e-005 +Gb49_2 ns49 0 ni2 0 0.000170630022339 +Gb51_2 ns51 0 ni2 0 0.000179605278739 +Gb53_2 ns53 0 ni2 0 0.000212794807761 +Gb55_2 ns55 0 ni2 0 0.000215985059484 +Gb57_2 ns57 0 ni2 0 0.00029971269334 +Gb59_2 ns59 0 ni2 0 0.000439747399856 +Gb61_2 ns61 0 ni2 0 0.00058550291575 +Gb63_2 ns63 0 ni2 0 0.000601527419166 +Gb65_2 ns65 0 ni2 0 0.000632170160318 +Gb67_2 ns67 0 ni2 0 0.000848040953993 +Gb69_2 ns69 0 ni2 0 0.000769739645409 +Gb71_3 ns71 0 ni3 0 2.10072059617e-009 +Gb72_3 ns72 0 ni3 0 2.12563808105e-007 +Gb73_3 ns73 0 ni3 0 1.36309130178e-006 +Gb74_3 ns74 0 ni3 0 4.76013028616e-006 +Gb75_3 ns75 0 ni3 0 7.02798184767e-006 +Gb76_3 ns76 0 ni3 0 1.82643539895e-005 +Gb78_3 ns78 0 ni3 0 1.94963472542e-005 +Gb80_3 ns80 0 ni3 0 2.15105374353e-005 +Gb81_3 ns81 0 ni3 0 2.43551291627e-005 +Gb83_3 ns83 0 ni3 0 7.92644310925e-005 +Gb84_3 ns84 0 ni3 0 0.000170630022339 +Gb86_3 ns86 0 ni3 0 0.000179605278739 +Gb88_3 ns88 0 ni3 0 0.000212794807761 +Gb90_3 ns90 0 ni3 0 0.000215985059484 +Gb92_3 ns92 0 ni3 0 0.00029971269334 +Gb94_3 ns94 0 ni3 0 0.000439747399856 +Gb96_3 ns96 0 ni3 0 0.00058550291575 +Gb98_3 ns98 0 ni3 0 0.000601527419166 +Gb100_3 ns100 0 ni3 0 0.000632170160318 +Gb102_3 ns102 0 ni3 0 0.000848040953993 +Gb104_3 ns104 0 ni3 0 0.000769739645409 +Gb106_4 ns106 0 ni4 0 2.10072059617e-009 +Gb107_4 ns107 0 ni4 0 2.12563808105e-007 +Gb108_4 ns108 0 ni4 0 1.36309130178e-006 +Gb109_4 ns109 0 ni4 0 4.76013028616e-006 +Gb110_4 ns110 0 ni4 0 7.02798184767e-006 +Gb111_4 ns111 0 ni4 0 1.82643539895e-005 +Gb113_4 ns113 0 ni4 0 1.94963472542e-005 +Gb115_4 ns115 0 ni4 0 2.15105374353e-005 +Gb116_4 ns116 0 ni4 0 2.43551291627e-005 +Gb118_4 ns118 0 ni4 0 7.92644310925e-005 +Gb119_4 ns119 0 ni4 0 0.000170630022339 +Gb121_4 ns121 0 ni4 0 0.000179605278739 +Gb123_4 ns123 0 ni4 0 0.000212794807761 +Gb125_4 ns125 0 ni4 0 0.000215985059484 +Gb127_4 ns127 0 ni4 0 0.00029971269334 +Gb129_4 ns129 0 ni4 0 0.000439747399856 +Gb131_4 ns131 0 ni4 0 0.00058550291575 +Gb133_4 ns133 0 ni4 0 0.000601527419166 +Gb135_4 ns135 0 ni4 0 0.000632170160318 +Gb137_4 ns137 0 ni4 0 0.000848040953993 +Gb139_4 ns139 0 ni4 0 0.000769739645409 +Gb141_5 ns141 0 ni5 0 2.10072059617e-009 +Gb142_5 ns142 0 ni5 0 2.12563808105e-007 +Gb143_5 ns143 0 ni5 0 1.36309130178e-006 +Gb144_5 ns144 0 ni5 0 4.76013028616e-006 +Gb145_5 ns145 0 ni5 0 7.02798184767e-006 +Gb146_5 ns146 0 ni5 0 1.82643539895e-005 +Gb148_5 ns148 0 ni5 0 1.94963472542e-005 +Gb150_5 ns150 0 ni5 0 2.15105374353e-005 +Gb151_5 ns151 0 ni5 0 2.43551291627e-005 +Gb153_5 ns153 0 ni5 0 7.92644310925e-005 +Gb154_5 ns154 0 ni5 0 0.000170630022339 +Gb156_5 ns156 0 ni5 0 0.000179605278739 +Gb158_5 ns158 0 ni5 0 0.000212794807761 +Gb160_5 ns160 0 ni5 0 0.000215985059484 +Gb162_5 ns162 0 ni5 0 0.00029971269334 +Gb164_5 ns164 0 ni5 0 0.000439747399856 +Gb166_5 ns166 0 ni5 0 0.00058550291575 +Gb168_5 ns168 0 ni5 0 0.000601527419166 +Gb170_5 ns170 0 ni5 0 0.000632170160318 +Gb172_5 ns172 0 ni5 0 0.000848040953993 +Gb174_5 ns174 0 ni5 0 0.000769739645409 +Gb176_6 ns176 0 ni6 0 2.10072059617e-009 +Gb177_6 ns177 0 ni6 0 2.12563808105e-007 +Gb178_6 ns178 0 ni6 0 1.36309130178e-006 +Gb179_6 ns179 0 ni6 0 4.76013028616e-006 +Gb180_6 ns180 0 ni6 0 7.02798184767e-006 +Gb181_6 ns181 0 ni6 0 1.82643539895e-005 +Gb183_6 ns183 0 ni6 0 1.94963472542e-005 +Gb185_6 ns185 0 ni6 0 2.15105374353e-005 +Gb186_6 ns186 0 ni6 0 2.43551291627e-005 +Gb188_6 ns188 0 ni6 0 7.92644310925e-005 +Gb189_6 ns189 0 ni6 0 0.000170630022339 +Gb191_6 ns191 0 ni6 0 0.000179605278739 +Gb193_6 ns193 0 ni6 0 0.000212794807761 +Gb195_6 ns195 0 ni6 0 0.000215985059484 +Gb197_6 ns197 0 ni6 0 0.00029971269334 +Gb199_6 ns199 0 ni6 0 0.000439747399856 +Gb201_6 ns201 0 ni6 0 0.00058550291575 +Gb203_6 ns203 0 ni6 0 0.000601527419166 +Gb205_6 ns205 0 ni6 0 0.000632170160318 +Gb207_6 ns207 0 ni6 0 0.000848040953993 +Gb209_6 ns209 0 ni6 0 0.000769739645409 + +Gc1_1 0 n2 ns1 0 0.00666752268164 +Gc1_2 0 n2 ns2 0 5.09491582664e-005 +Gc1_3 0 n2 ns3 0 0.00022847879478 +Gc1_4 0 n2 ns4 0 0.00601849118123 +Gc1_5 0 n2 ns5 0 0.00694360169056 +Gc1_6 0 n2 ns6 0 -2.96145276417e-007 +Gc1_7 0 n2 ns7 0 -1.23872481107e-007 +Gc1_8 0 n2 ns8 0 -1.85182724628e-007 +Gc1_9 0 n2 ns9 0 1.34999804817e-007 +Gc1_10 0 n2 ns10 0 0.000430255930801 +Gc1_11 0 n2 ns11 0 7.79910572962e-008 +Gc1_12 0 n2 ns12 0 -5.64435748241e-009 +Gc1_13 0 n2 ns13 0 0.000257868812469 +Gc1_14 0 n2 ns14 0 0.00571353024479 +Gc1_15 0 n2 ns15 0 -0.001187770421 +Gc1_16 0 n2 ns16 0 9.33836942506e-005 +Gc1_17 0 n2 ns17 0 0.000429198364197 +Gc1_18 0 n2 ns18 0 0.00163821125273 +Gc1_19 0 n2 ns19 0 0.00034950096952 +Gc1_20 0 n2 ns20 0 4.34413511062e-008 +Gc1_21 0 n2 ns21 0 4.90973769339e-007 +Gc1_22 0 n2 ns22 0 2.9227351824e-006 +Gc1_23 0 n2 ns23 0 9.86249998041e-007 +Gc1_24 0 n2 ns24 0 -1.15607889872e-007 +Gc1_25 0 n2 ns25 0 3.31632441521e-007 +Gc1_26 0 n2 ns26 0 0.00188722822745 +Gc1_27 0 n2 ns27 0 0.00108645087543 +Gc1_28 0 n2 ns28 0 0.0064662451115 +Gc1_29 0 n2 ns29 0 -0.00056553524915 +Gc1_30 0 n2 ns30 0 -0.00243086526793 +Gc1_31 0 n2 ns31 0 -0.00202066225432 +Gc1_32 0 n2 ns32 0 -0.00753315345312 +Gc1_33 0 n2 ns33 0 -0.0269422298809 +Gc1_34 0 n2 ns34 0 -0.00172843573882 +Gc1_35 0 n2 ns35 0 -0.00228097114443 +Gc1_36 0 n2 ns36 0 0.00661274570056 +Gc1_37 0 n2 ns37 0 -2.57320203508e-005 +Gc1_38 0 n2 ns38 0 -7.52216165428e-005 +Gc1_39 0 n2 ns39 0 -0.00257034018477 +Gc1_40 0 n2 ns40 0 -0.0039321284396 +Gc1_41 0 n2 ns41 0 -2.29954337498e-008 +Gc1_42 0 n2 ns42 0 -1.25025803376e-008 +Gc1_43 0 n2 ns43 0 -7.12895433017e-008 +Gc1_44 0 n2 ns44 0 2.07774727602e-008 +Gc1_45 0 n2 ns45 0 -0.000237255016382 +Gc1_46 0 n2 ns46 0 1.79264742384e-009 +Gc1_47 0 n2 ns47 0 -2.1527277466e-009 +Gc1_48 0 n2 ns48 0 -0.000159779232425 +Gc1_49 0 n2 ns49 0 -0.00299362674862 +Gc1_50 0 n2 ns50 0 0.000998474988873 +Gc1_51 0 n2 ns51 0 0.000799519344656 +Gc1_52 0 n2 ns52 0 0.00115666033006 +Gc1_53 0 n2 ns53 0 0.00195337217966 +Gc1_54 0 n2 ns54 0 0.000421885785863 +Gc1_55 0 n2 ns55 0 -3.6638012539e-008 +Gc1_56 0 n2 ns56 0 5.27008545591e-007 +Gc1_57 0 n2 ns57 0 2.6508791673e-006 +Gc1_58 0 n2 ns58 0 -7.01233429009e-007 +Gc1_59 0 n2 ns59 0 -1.40116776149e-007 +Gc1_60 0 n2 ns60 0 4.55860649951e-007 +Gc1_61 0 n2 ns61 0 -9.22171755246e-005 +Gc1_62 0 n2 ns62 0 8.47155827695e-005 +Gc1_63 0 n2 ns63 0 -0.00126019639497 +Gc1_64 0 n2 ns64 0 0.000205694336981 +Gc1_65 0 n2 ns65 0 0.000226764988897 +Gc1_66 0 n2 ns66 0 0.000479863715716 +Gc1_67 0 n2 ns67 0 -0.00103280271097 +Gc1_68 0 n2 ns68 0 0.000927599139777 +Gc1_69 0 n2 ns69 0 0.000467777118995 +Gc1_70 0 n2 ns70 0 0.000161807020684 +Gc1_71 0 n2 ns71 0 0.00661107966511 +Gc1_72 0 n2 ns72 0 -2.68092396845e-005 +Gc1_73 0 n2 ns73 0 -0.000103403973991 +Gc1_74 0 n2 ns74 0 -0.00355068321275 +Gc1_75 0 n2 ns75 0 -0.00287408293101 +Gc1_76 0 n2 ns76 0 8.38136294257e-009 +Gc1_77 0 n2 ns77 0 8.30399237564e-009 +Gc1_78 0 n2 ns78 0 -3.36621010671e-008 +Gc1_79 0 n2 ns79 0 1.31678647373e-008 +Gc1_80 0 n2 ns80 0 -0.000241660406281 +Gc1_81 0 n2 ns81 0 1.36490242975e-008 +Gc1_82 0 n2 ns82 0 1.36597336912e-008 +Gc1_83 0 n2 ns83 0 -0.000146444943576 +Gc1_84 0 n2 ns84 0 -0.00135469820111 +Gc1_85 0 n2 ns85 0 -0.000209884924618 +Gc1_86 0 n2 ns86 0 -0.000891625657107 +Gc1_87 0 n2 ns87 0 -0.000801344428253 +Gc1_88 0 n2 ns88 0 0.00194632196922 +Gc1_89 0 n2 ns89 0 0.00101416306266 +Gc1_90 0 n2 ns90 0 1.35684139213e-007 +Gc1_91 0 n2 ns91 0 5.80087317229e-007 +Gc1_92 0 n2 ns92 0 2.62553676706e-006 +Gc1_93 0 n2 ns93 0 -7.00399241339e-007 +Gc1_94 0 n2 ns94 0 -2.6451207414e-007 +Gc1_95 0 n2 ns95 0 3.93406524128e-007 +Gc1_96 0 n2 ns96 0 -0.000352185974746 +Gc1_97 0 n2 ns97 0 -0.000221171783181 +Gc1_98 0 n2 ns98 0 -0.00149616029391 +Gc1_99 0 n2 ns99 0 0.000283066794966 +Gc1_100 0 n2 ns100 0 0.000589299829413 +Gc1_101 0 n2 ns101 0 0.000131563582421 +Gc1_102 0 n2 ns102 0 -0.000744369197263 +Gc1_103 0 n2 ns103 0 0.000886438839789 +Gc1_104 0 n2 ns104 0 0.000599216762199 +Gc1_105 0 n2 ns105 0 9.08358590928e-007 +Gc1_106 0 n2 ns106 0 -0.00666402116616 +Gc1_107 0 n2 ns107 0 -6.3232811967e-005 +Gc1_108 0 n2 ns108 0 -0.000205309045469 +Gc1_109 0 n2 ns109 0 -0.00609913716426 +Gc1_110 0 n2 ns110 0 -0.00684103848275 +Gc1_111 0 n2 ns111 0 -5.95238935628e-009 +Gc1_112 0 n2 ns112 0 -3.32543130184e-008 +Gc1_113 0 n2 ns113 0 -1.63565245845e-007 +Gc1_114 0 n2 ns114 0 2.76171417218e-009 +Gc1_115 0 n2 ns115 0 -0.000484117270784 +Gc1_116 0 n2 ns116 0 3.32688233639e-008 +Gc1_117 0 n2 ns117 0 -2.17147168497e-008 +Gc1_118 0 n2 ns118 0 -0.000329203813157 +Gc1_119 0 n2 ns119 0 -0.00471466519068 +Gc1_120 0 n2 ns120 0 0.00105676318609 +Gc1_121 0 n2 ns121 0 2.49105363468e-005 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1.0325358787e-007 +Gc1_147 0 n2 ns147 0 1.0536052764e-008 +Gc1_148 0 n2 ns148 0 1.55360869531e-007 +Gc1_149 0 n2 ns149 0 -9.04955377087e-008 +Gc1_150 0 n2 ns150 0 0.000248423840584 +Gc1_151 0 n2 ns151 0 7.85832910382e-009 +Gc1_152 0 n2 ns152 0 1.42986245777e-008 +Gc1_153 0 n2 ns153 0 0.000135704208705 +Gc1_154 0 n2 ns154 0 0.00219845944154 +Gc1_155 0 n2 ns155 0 -0.000859424782843 +Gc1_156 0 n2 ns156 0 -0.000616167954742 +Gc1_157 0 n2 ns157 0 -0.00101168542114 +Gc1_158 0 n2 ns158 0 -0.00192025098034 +Gc1_159 0 n2 ns159 0 -0.00048425100294 +Gc1_160 0 n2 ns160 0 1.49539130114e-007 +Gc1_161 0 n2 ns161 0 5.89938422462e-007 +Gc1_162 0 n2 ns162 0 2.28819991188e-006 +Gc1_163 0 n2 ns163 0 1.10301964122e-006 +Gc1_164 0 n2 ns164 0 -3.88764466436e-007 +Gc1_165 0 n2 ns165 0 1.18741617783e-007 +Gc1_166 0 n2 ns166 0 -0.000188700804078 +Gc1_167 0 n2 ns167 0 -9.02341311162e-005 +Gc1_168 0 n2 ns168 0 -0.000667650842368 +Gc1_169 0 n2 ns169 0 0.000165063112767 +Gc1_170 0 n2 ns170 0 0.000148430078078 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3.96614242828e-007 +Gc1_196 0 n2 ns196 0 4.21095379538e-007 +Gc1_197 0 n2 ns197 0 9.65933548276e-007 +Gc1_198 0 n2 ns198 0 -2.14790313248e-007 +Gc1_199 0 n2 ns199 0 1.06913701257e-008 +Gc1_200 0 n2 ns200 0 1.96679191178e-007 +Gc1_201 0 n2 ns201 0 -0.000261066208937 +Gc1_202 0 n2 ns202 0 -8.24729816312e-005 +Gc1_203 0 n2 ns203 0 -0.000919267560429 +Gc1_204 0 n2 ns204 0 0.000107795276085 +Gc1_205 0 n2 ns205 0 0.000318875304751 +Gc1_206 0 n2 ns206 0 0.000336431296394 +Gc1_207 0 n2 ns207 0 -0.00143223296481 +Gc1_208 0 n2 ns208 0 0.00164918313685 +Gc1_209 0 n2 ns209 0 -3.8751514619e-005 +Gc1_210 0 n2 ns210 0 0.000276031808314 +Gd1_1 0 n2 ni1 0 -0.00243246206311 +Gd1_2 0 n2 ni2 0 -0.000462030032959 +Gd1_3 0 n2 ni3 0 -0.000355967320817 +Gd1_4 0 n2 ni4 0 -0.00161298493588 +Gd1_5 0 n2 ni5 0 -0.000822110366332 +Gd1_6 0 n2 ni6 0 -0.000605773438325 +Gc2_1 0 n4 ns1 0 0.00661043071102 +Gc2_2 0 n4 ns2 0 -2.50201626123e-005 +Gc2_3 0 n4 ns3 0 -7.63806562621e-005 +Gc2_4 0 n4 ns4 0 -0.00256671849197 +Gc2_5 0 n4 ns5 0 -0.00393479865645 +Gc2_6 0 n4 ns6 0 -1.76431703694e-008 +Gc2_7 0 n4 ns7 0 -1.76248709204e-009 +Gc2_8 0 n4 ns8 0 -5.30077321583e-008 +Gc2_9 0 n4 ns9 0 2.89157786228e-008 +Gc2_10 0 n4 ns10 0 -0.000236208881902 +Gc2_11 0 n4 ns11 0 1.76245167287e-009 +Gc2_12 0 n4 ns12 0 3.03128316719e-009 +Gc2_13 0 n4 ns13 0 -0.00015702305052 +Gc2_14 0 n4 ns14 0 -0.0029922076615 +Gc2_15 0 n4 ns15 0 0.00100360646616 +Gc2_16 0 n4 ns16 0 0.000794517858703 +Gc2_17 0 n4 ns17 0 0.00116076873771 +Gc2_18 0 n4 ns18 0 0.00195341137614 +Gc2_19 0 n4 ns19 0 0.000425726687557 +Gc2_20 0 n4 ns20 0 -5.51174778081e-008 +Gc2_21 0 n4 ns21 0 4.66248163998e-007 +Gc2_22 0 n4 ns22 0 2.11591791031e-006 +Gc2_23 0 n4 ns23 0 -2.98710528424e-007 +Gc2_24 0 n4 ns24 0 -3.34783345652e-007 +Gc2_25 0 n4 ns25 0 1.02553636064e-007 +Gc2_26 0 n4 ns26 0 -0.000121947230453 +Gc2_27 0 n4 ns27 0 4.3962623926e-005 +Gc2_28 0 n4 ns28 0 -0.00113395461114 +Gc2_29 0 n4 ns29 0 8.94038097199e-005 +Gc2_30 0 n4 ns30 0 0.000134725659047 +Gc2_31 0 n4 ns31 0 0.000466202379916 +Gc2_32 0 n4 ns32 0 -0.000761127352227 +Gc2_33 0 n4 ns33 0 0.000830942974278 +Gc2_34 0 n4 ns34 0 0.000394036318928 +Gc2_35 0 n4 ns35 0 0.000166136374003 +Gc2_36 0 n4 ns36 0 0.00666254625957 +Gc2_37 0 n4 ns37 0 4.7836570997e-005 +Gc2_38 0 n4 ns38 0 0.000204150952616 +Gc2_39 0 n4 ns39 0 0.00545007488974 +Gc2_40 0 n4 ns40 0 0.0075934502657 +Gc2_41 0 n4 ns41 0 1.22236189278e-007 +Gc2_42 0 n4 ns42 0 -7.49497643608e-008 +Gc2_43 0 n4 ns43 0 -2.89458392081e-007 +Gc2_44 0 n4 ns44 0 1.90421113642e-007 +Gc2_45 0 n4 ns45 0 0.000425628007364 +Gc2_46 0 n4 ns46 0 2.60601941168e-008 +Gc2_47 0 n4 ns47 0 -1.65866084713e-008 +Gc2_48 0 n4 ns48 0 0.000210433938895 +Gc2_49 0 n4 ns49 0 0.00141951449314 +Gc2_50 0 n4 ns50 0 -0.000804094357073 +Gc2_51 0 n4 ns51 0 0.00371332405553 +Gc2_52 0 n4 ns52 0 0.00161278479037 +Gc2_53 0 n4 ns53 0 0.00233694742958 +Gc2_54 0 n4 ns54 0 0.000459129849669 +Gc2_55 0 n4 ns55 0 -1.12231587245e-007 +Gc2_56 0 n4 ns56 0 7.20649153398e-007 +Gc2_57 0 n4 ns57 0 5.1630515367e-006 +Gc2_58 0 n4 ns58 0 -1.43842916363e-006 +Gc2_59 0 n4 ns59 0 -5.76879682917e-008 +Gc2_60 0 n4 ns60 0 4.82433419966e-007 +Gc2_61 0 n4 ns61 0 0.000265108117293 +Gc2_62 0 n4 ns62 0 0.000774493430855 +Gc2_63 0 n4 ns63 0 0.00810803062859 +Gc2_64 0 n4 ns64 0 0.00300006925931 +Gc2_65 0 n4 ns65 0 -0.00113593524931 +Gc2_66 0 n4 ns66 0 -0.00153166354857 +Gc2_67 0 n4 ns67 0 -0.0085859739245 +Gc2_68 0 n4 ns68 0 -0.0309932017529 +Gc2_69 0 n4 ns69 0 -0.00168453113925 +Gc2_70 0 n4 ns70 0 -0.00233899967323 +Gc2_71 0 n4 ns71 0 0.00660977448377 +Gc2_72 0 n4 ns72 0 -2.65912561127e-005 +Gc2_73 0 n4 ns73 0 -7.69164373159e-005 +Gc2_74 0 n4 ns74 0 -0.00293402830645 +Gc2_75 0 n4 ns75 0 -0.00354040401082 +Gc2_76 0 n4 ns76 0 -4.45307691661e-008 +Gc2_77 0 n4 ns77 0 -2.50453281556e-008 +Gc2_78 0 n4 ns78 0 -9.75887472425e-008 +Gc2_79 0 n4 ns79 0 3.06416445772e-008 +Gc2_80 0 n4 ns80 0 -0.00022329119149 +Gc2_81 0 n4 ns81 0 -6.6975615777e-009 +Gc2_82 0 n4 ns82 0 -4.24137409337e-009 +Gc2_83 0 n4 ns83 0 -0.000136773993471 +Gc2_84 0 n4 ns84 0 0.000845905790788 +Gc2_85 0 n4 ns85 0 7.46740895584e-005 +Gc2_86 0 n4 ns86 0 -0.00337989749258 +Gc2_87 0 n4 ns87 0 -0.000702143484331 +Gc2_88 0 n4 ns88 0 0.00235675719385 +Gc2_89 0 n4 ns89 0 0.00118297328491 +Gc2_90 0 n4 ns90 0 1.32533981406e-007 +Gc2_91 0 n4 ns91 0 7.25424814243e-007 +Gc2_92 0 n4 ns92 0 2.83904013869e-006 +Gc2_93 0 n4 ns93 0 -7.33535031817e-007 +Gc2_94 0 n4 ns94 0 -1.02120732575e-007 +Gc2_95 0 n4 ns95 0 7.45343630542e-007 +Gc2_96 0 n4 ns96 0 -1.00981966586e-005 +Gc2_97 0 n4 ns97 0 -0.000177221034166 +Gc2_98 0 n4 ns98 0 -0.00148312331721 +Gc2_99 0 n4 ns99 0 1.3027787055e-005 +Gc2_100 0 n4 ns100 0 0.000110281031733 +Gc2_101 0 n4 ns101 0 0.00039947453453 +Gc2_102 0 n4 ns102 0 -0.000216936580626 +Gc2_103 0 n4 ns103 0 0.000699779795144 +Gc2_104 0 n4 ns104 0 0.000487814446023 +Gc2_105 0 n4 ns105 0 0.000166518263818 +Gc2_106 0 n4 ns106 0 -0.00661114652051 +Gc2_107 0 n4 ns107 0 2.5074756471e-005 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-7.11744509037e-005 +Gc2_133 0 n4 ns133 0 -0.00118769475194 +Gc2_134 0 n4 ns134 0 -0.000315889093358 +Gc2_135 0 n4 ns135 0 4.11743624738e-005 +Gc2_136 0 n4 ns136 0 -6.70523790028e-005 +Gc2_137 0 n4 ns137 0 -0.00138140450996 +Gc2_138 0 n4 ns138 0 0.00160246782501 +Gc2_139 0 n4 ns139 0 -9.87482714569e-005 +Gc2_140 0 n4 ns140 0 0.00028638474748 +Gc2_141 0 n4 ns141 0 -0.00666905852315 +Gc2_142 0 n4 ns142 0 -5.97289975123e-005 +Gc2_143 0 n4 ns143 0 -0.000179213230852 +Gc2_144 0 n4 ns144 0 -0.00552027719833 +Gc2_145 0 n4 ns145 0 -0.007495678601 +Gc2_146 0 n4 ns146 0 -9.82788333424e-008 +Gc2_147 0 n4 ns147 0 -1.61801714687e-008 +Gc2_148 0 n4 ns148 0 -1.88481667906e-007 +Gc2_149 0 n4 ns149 0 5.99167657646e-008 +Gc2_150 0 n4 ns150 0 -0.000463012645534 +Gc2_151 0 n4 ns151 0 -2.71385940821e-009 +Gc2_152 0 n4 ns152 0 -2.54836005805e-008 +Gc2_153 0 n4 ns153 0 -0.000313342672366 +Gc2_154 0 n4 ns154 0 -0.00101674597034 +Gc2_155 0 n4 ns155 0 0.00059330815413 +Gc2_156 0 n4 ns156 0 -0.00304288263489 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ns79 0 -2.43154640406e-008 +Gc4_80 0 n8 ns80 0 0.00025473044951 +Gc4_81 0 n8 ns81 0 1.48480005296e-008 +Gc4_82 0 n8 ns82 0 -2.82962312835e-008 +Gc4_83 0 n8 ns83 0 9.8416875136e-005 +Gc4_84 0 n8 ns84 0 0.00115571407445 +Gc4_85 0 n8 ns85 0 0.000108988325205 +Gc4_86 0 n8 ns86 0 0.000639659257646 +Gc4_87 0 n8 ns87 0 0.000692752150257 +Gc4_88 0 n8 ns88 0 -0.00199742904644 +Gc4_89 0 n8 ns89 0 -0.00114065577516 +Gc4_90 0 n8 ns90 0 6.7568185091e-007 +Gc4_91 0 n8 ns91 0 5.42052469443e-007 +Gc4_92 0 n8 ns92 0 9.57390396553e-007 +Gc4_93 0 n8 ns93 0 -1.87550557962e-006 +Gc4_94 0 n8 ns94 0 -3.29327715329e-007 +Gc4_95 0 n8 ns95 0 6.65670940579e-007 +Gc4_96 0 n8 ns96 0 -4.23833679107e-005 +Gc4_97 0 n8 ns97 0 0.000183080947791 +Gc4_98 0 n8 ns98 0 -0.000387689143787 +Gc4_99 0 n8 ns99 0 -0.000682037552064 +Gc4_100 0 n8 ns100 0 -0.00127575272008 +Gc4_101 0 n8 ns101 0 -0.00016557644374 +Gc4_102 0 n8 ns102 0 -0.00193332123701 +Gc4_103 0 n8 ns103 0 0.00189580292666 +Gc4_104 0 n8 ns104 0 0.000808086137261 +Gc4_105 0 n8 ns105 0 0.000438229172767 +Gc4_106 0 n8 ns106 0 0.00665905348773 +Gc4_107 0 n8 ns107 0 4.3378267741e-005 +Gc4_108 0 n8 ns108 0 0.000234278875379 +Gc4_109 0 n8 ns109 0 0.00599330310435 +Gc4_110 0 n8 ns110 0 0.00694117027883 +Gc4_111 0 n8 ns111 0 8.1210192595e-008 +Gc4_112 0 n8 ns112 0 -2.9481026609e-007 +Gc4_113 0 n8 ns113 0 -6.78438603348e-007 +Gc4_114 0 n8 ns114 0 -2.35711954721e-007 +Gc4_115 0 n8 ns115 0 0.000423307615433 +Gc4_116 0 n8 ns116 0 2.25773415072e-008 +Gc4_117 0 n8 ns117 0 -2.22869322298e-008 +Gc4_118 0 n8 ns118 0 0.000210066973297 +Gc4_119 0 n8 ns119 0 0.00391444790213 +Gc4_120 0 n8 ns120 0 -0.00104580989749 +Gc4_121 0 n8 ns121 0 -3.71237939289e-005 +Gc4_122 0 n8 ns122 0 0.000262370992719 +Gc4_123 0 n8 ns123 0 0.00171864905981 +Gc4_124 0 n8 ns124 0 0.000502257697941 +Gc4_125 0 n8 ns125 0 1.01884517918e-006 +Gc4_126 0 n8 ns126 0 1.98353395517e-007 +Gc4_127 0 n8 ns127 0 -6.12974327105e-007 +Gc4_128 0 n8 ns128 0 -7.63123948536e-007 +Gc4_129 0 n8 ns129 0 6.06319735065e-008 +Gc4_130 0 n8 ns130 0 8.37955872061e-007 +Gc4_131 0 n8 ns131 0 0.0004685878127 +Gc4_132 0 n8 ns132 0 0.000102824434789 +Gc4_133 0 n8 ns133 0 0.00344051623628 +Gc4_134 0 n8 ns134 0 0.000989502732885 +Gc4_135 0 n8 ns135 0 -0.000319884097542 +Gc4_136 0 n8 ns136 0 0.000530300887111 +Gc4_137 0 n8 ns137 0 0.00272878288403 +Gc4_138 0 n8 ns138 0 -0.0320381550744 +Gc4_139 0 n8 ns139 0 0.00103428760913 +Gc4_140 0 n8 ns140 0 -0.00176005773017 +Gc4_141 0 n8 ns141 0 0.00661165549329 +Gc4_142 0 n8 ns142 0 -2.30630317603e-005 +Gc4_143 0 n8 ns143 0 -7.69840205667e-005 +Gc4_144 0 n8 ns144 0 -0.0025605691444 +Gc4_145 0 n8 ns145 0 -0.00392335165487 +Gc4_146 0 n8 ns146 0 -4.00831315173e-008 +Gc4_147 0 n8 ns147 0 1.96743909405e-008 +Gc4_148 0 n8 ns148 0 -4.77673233498e-008 +Gc4_149 0 n8 ns149 0 4.06161475409e-008 +Gc4_150 0 n8 ns150 0 -0.000236391022153 +Gc4_151 0 n8 ns151 0 -8.51889836988e-009 +Gc4_152 0 n8 ns152 0 -7.43453550662e-009 +Gc4_153 0 n8 ns153 0 -0.000138566449343 +Gc4_154 0 n8 ns154 0 -0.00180469249599 +Gc4_155 0 n8 ns155 0 0.000757384508999 +Gc4_156 0 n8 ns156 0 0.000400255631539 +Gc4_157 0 n8 ns157 0 0.000877697275249 +Gc4_158 0 n8 ns158 0 0.00197505216714 +Gc4_159 0 n8 ns159 0 0.00054570866977 +Gc4_160 0 n8 ns160 0 8.85337571844e-007 +Gc4_161 0 n8 ns161 0 4.57118820777e-007 +Gc4_162 0 n8 ns162 0 7.78870298031e-007 +Gc4_163 0 n8 ns163 0 -1.60657065599e-006 +Gc4_164 0 n8 ns164 0 -4.91277622838e-007 +Gc4_165 0 n8 ns165 0 2.75334365283e-007 +Gc4_166 0 n8 ns166 0 0.000147748570323 +Gc4_167 0 n8 ns167 0 0.000243281452849 +Gc4_168 0 n8 ns168 0 0.000523047244158 +Gc4_169 0 n8 ns169 0 0.000331395483418 +Gc4_170 0 n8 ns170 0 0.000163820645263 +Gc4_171 0 n8 ns171 0 -0.000229275874966 +Gc4_172 0 n8 ns172 0 -0.00491032529621 +Gc4_173 0 n8 ns173 0 0.00308134730103 +Gc4_174 0 n8 ns174 0 -0.00139380503917 +Gc4_175 0 n8 ns175 0 -0.00066984993216 +Gc4_176 0 n8 ns176 0 0.00661041529677 +Gc4_177 0 n8 ns177 0 -2.41812180475e-005 +Gc4_178 0 n8 ns178 0 -0.000105295462545 +Gc4_179 0 n8 ns179 0 -0.00353575627003 +Gc4_180 0 n8 ns180 0 -0.00287272161034 +Gc4_181 0 n8 ns181 0 -3.60588313968e-009 +Gc4_182 0 n8 ns182 0 2.08018012988e-008 +Gc4_183 0 n8 ns183 0 -2.39032558069e-008 +Gc4_184 0 n8 ns184 0 2.15644888121e-008 +Gc4_185 0 n8 ns185 0 -0.000238252303608 +Gc4_186 0 n8 ns186 0 2.22747818323e-009 +Gc4_187 0 n8 ns187 0 -9.12763276896e-010 +Gc4_188 0 n8 ns188 0 -0.000134853688385 +Gc4_189 0 n8 ns189 0 -0.000952502121642 +Gc4_190 0 n8 ns190 0 -9.17763287354e-005 +Gc4_191 0 n8 ns191 0 -0.000491443001821 +Gc4_192 0 n8 ns192 0 -0.000547263330741 +Gc4_193 0 n8 ns193 0 0.00189048147033 +Gc4_194 0 n8 ns194 0 0.000977247583039 +Gc4_195 0 n8 ns195 0 9.41177194687e-007 +Gc4_196 0 n8 ns196 0 2.04345114291e-007 +Gc4_197 0 n8 ns197 0 1.66402878885e-007 +Gc4_198 0 n8 ns198 0 -1.2608612891e-006 +Gc4_199 0 n8 ns199 0 -1.44012849455e-008 +Gc4_200 0 n8 ns200 0 4.63446719945e-007 +Gc4_201 0 n8 ns201 0 8.91071923007e-005 +Gc4_202 0 n8 ns202 0 0.000169558076131 +Gc4_203 0 n8 ns203 0 0.000182989136298 +Gc4_204 0 n8 ns204 0 -0.000115578915625 +Gc4_205 0 n8 ns205 0 1.7753445354e-005 +Gc4_206 0 n8 ns206 0 -0.000306536963986 +Gc4_207 0 n8 ns207 0 -0.00385706706767 +Gc4_208 0 n8 ns208 0 0.00257048461133 +Gc4_209 0 n8 ns209 0 -0.00117183174682 +Gc4_210 0 n8 ns210 0 -0.000349884509146 +Gd4_1 0 n8 ni1 0 -0.00144967647057 +Gd4_2 0 n8 ni2 0 -0.000819379860107 +Gd4_3 0 n8 ni3 0 -0.000871701615246 +Gd4_4 0 n8 ni4 0 0.00153998456527 +Gd4_5 0 n8 ni5 0 -0.00200068495598 +Gd4_6 0 n8 ni6 0 -0.00164964367842 +Gc5_1 0 n10 ns1 0 -0.00660988050552 +Gc5_2 0 n10 ns2 0 2.47250766994e-005 +Gc5_3 0 n10 ns3 0 7.63008302627e-005 +Gc5_4 0 n10 ns4 0 0.00256254825542 +Gc5_5 0 n10 ns5 0 0.00392731771829 +Gc5_6 0 n10 ns6 0 2.31477477498e-008 +Gc5_7 0 n10 ns7 0 -1.52472804058e-008 +Gc5_8 0 n10 ns8 0 -1.04234936247e-008 +Gc5_9 0 n10 ns9 0 -5.86071888795e-008 +Gc5_10 0 n10 ns10 0 0.000239554730523 +Gc5_11 0 n10 ns11 0 1.32456930008e-008 +Gc5_12 0 n10 ns12 0 -8.50623417547e-009 +Gc5_13 0 n10 ns13 0 0.000133217103949 +Gc5_14 0 n10 ns14 0 0.00219384193745 +Gc5_15 0 n10 ns15 0 -0.000858422861657 +Gc5_16 0 n10 ns16 0 -0.000613568369602 +Gc5_17 0 n10 ns17 0 -0.00101157672236 +Gc5_18 0 n10 ns18 0 -0.00191604234998 +Gc5_19 0 n10 ns19 0 -0.000483894120625 +Gc5_20 0 n10 ns20 0 1.59232185198e-007 +Gc5_21 0 n10 ns21 0 6.21255373834e-007 +Gc5_22 0 n10 ns22 0 2.48915520008e-006 +Gc5_23 0 n10 ns23 0 8.60787394866e-007 +Gc5_24 0 n10 ns24 0 -3.95373509415e-007 +Gc5_25 0 n10 ns25 0 8.50429215988e-008 +Gc5_26 0 n10 ns26 0 -0.000189363489117 +Gc5_27 0 n10 ns27 0 -6.10018608668e-005 +Gc5_28 0 n10 ns28 0 -0.000777648405011 +Gc5_29 0 n10 ns29 0 0.000179632431238 +Gc5_30 0 n10 ns30 0 0.000188891404312 +Gc5_31 0 n10 ns31 0 0.000112000317097 +Gc5_32 0 n10 ns32 0 -0.00159490046726 +Gc5_33 0 n10 ns33 0 0.00123031387374 +Gc5_34 0 n10 ns34 0 -0.00037245095084 +Gc5_35 0 n10 ns35 0 0.000290202936268 +Gc5_36 0 n10 ns36 0 -0.00666708977109 +Gc5_37 0 n10 ns37 0 -6.38867663393e-005 +Gc5_38 0 n10 ns38 0 -0.000176230541688 +Gc5_39 0 n10 ns39 0 -0.00552188711161 +Gc5_40 0 n10 ns40 0 -0.00750566744074 +Gc5_41 0 n10 ns41 0 2.53594062312e-008 +Gc5_42 0 n10 ns42 0 1.94716120067e-008 +Gc5_43 0 n10 ns43 0 4.41674391525e-008 +Gc5_44 0 n10 ns44 0 -7.20045671386e-009 +Gc5_45 0 n10 ns45 0 -0.000448715526198 +Gc5_46 0 n10 ns46 0 1.84060386238e-009 +Gc5_47 0 n10 ns47 0 1.35229878676e-009 +Gc5_48 0 n10 ns48 0 -0.00031454115272 +Gc5_49 0 n10 ns49 0 -0.00102298862368 +Gc5_50 0 n10 ns50 0 0.000592059464801 +Gc5_51 0 n10 ns51 0 -0.00303014675738 +Gc5_52 0 n10 ns52 0 -0.00154759154632 +Gc5_53 0 n10 ns53 0 -0.00229815610041 +Gc5_54 0 n10 ns54 0 -0.00056181698023 +Gc5_55 0 n10 ns55 0 8.99342166214e-008 +Gc5_56 0 n10 ns56 0 7.8332031475e-007 +Gc5_57 0 n10 ns57 0 4.12194117659e-006 +Gc5_58 0 n10 ns58 0 6.22469768616e-007 +Gc5_59 0 n10 ns59 0 -1.39929808676e-007 +Gc5_60 0 n10 ns60 0 3.94021972769e-007 +Gc5_61 0 n10 ns61 0 3.2738619102e-005 +Gc5_62 0 n10 ns62 0 -0.000468932516703 +Gc5_63 0 n10 ns63 0 -0.00383827845097 +Gc5_64 0 n10 ns64 0 -0.002946302904 +Gc5_65 0 n10 ns65 0 0.000696173675661 +Gc5_66 0 n10 ns66 0 0.000682961422425 +Gc5_67 0 n10 ns67 0 -0.0014723525541 +Gc5_68 0 n10 ns68 0 0.0112349880154 +Gc5_69 0 n10 ns69 0 0.000337418920835 +Gc5_70 0 n10 ns70 0 0.000898292209632 +Gc5_71 0 n10 ns71 0 -0.00661188345352 +Gc5_72 0 n10 ns72 0 2.6968426159e-005 +Gc5_73 0 n10 ns73 0 7.56514702587e-005 +Gc5_74 0 n10 ns74 0 0.00294047217575 +Gc5_75 0 n10 ns75 0 0.00353141047458 +Gc5_76 0 n10 ns76 0 1.97449109166e-008 +Gc5_77 0 n10 ns77 0 -3.65092932455e-008 +Gc5_78 0 n10 ns78 0 1.31957298844e-009 +Gc5_79 0 n10 ns79 0 -2.90037562718e-008 +Gc5_80 0 n10 ns80 0 0.000229986797201 +Gc5_81 0 n10 ns81 0 2.10256074802e-008 +Gc5_82 0 n10 ns82 0 -8.94385737339e-009 +Gc5_83 0 n10 ns83 0 0.000103233292775 +Gc5_84 0 n10 ns84 0 -0.000630537950281 +Gc5_85 0 n10 ns85 0 -6.59353239142e-005 +Gc5_86 0 n10 ns86 0 0.00285995028589 +Gc5_87 0 n10 ns87 0 0.000685956904203 +Gc5_88 0 n10 ns88 0 -0.00230921725622 +Gc5_89 0 n10 ns89 0 -0.00125438392596 +Gc5_90 0 n10 ns90 0 5.15561228034e-007 +Gc5_91 0 n10 ns91 0 4.77345899426e-007 +Gc5_92 0 n10 ns92 0 1.86686624049e-006 +Gc5_93 0 n10 ns93 0 -1.72064558328e-006 +Gc5_94 0 n10 ns94 0 -1.54663047313e-007 +Gc5_95 0 n10 ns95 0 6.94680534795e-007 +Gc5_96 0 n10 ns96 0 -0.000125840216775 +Gc5_97 0 n10 ns97 0 9.25012936278e-005 +Gc5_98 0 n10 ns98 0 -0.000292149078159 +Gc5_99 0 n10 ns99 0 -0.000594035521992 +Gc5_100 0 n10 ns100 0 -0.00134805924835 +Gc5_101 0 n10 ns101 0 -0.000143453127344 +Gc5_102 0 n10 ns102 0 -0.00258549062549 +Gc5_103 0 n10 ns103 0 0.00247528637696 +Gc5_104 0 n10 ns104 0 0.00104941832251 +Gc5_105 0 n10 ns105 0 0.000494461694961 +Gc5_106 0 n10 ns106 0 0.00661076061991 +Gc5_107 0 n10 ns107 0 -2.45926939333e-005 +Gc5_108 0 n10 ns108 0 -7.50535785238e-005 +Gc5_109 0 n10 ns109 0 -0.00256594141618 +Gc5_110 0 n10 ns110 0 -0.00391830241042 +Gc5_111 0 n10 ns111 0 -2.49366579491e-008 +Gc5_112 0 n10 ns112 0 1.51729491258e-008 +Gc5_113 0 n10 ns113 0 -3.2063409635e-008 +Gc5_114 0 n10 ns114 0 2.34620455472e-008 +Gc5_115 0 n10 ns115 0 -0.000235991690589 +Gc5_116 0 n10 ns116 0 -8.55040796664e-009 +Gc5_117 0 n10 ns117 0 -6.6533427502e-009 +Gc5_118 0 n10 ns118 0 -0.000137779703428 +Gc5_119 0 n10 ns119 0 -0.00180409234516 +Gc5_120 0 n10 ns120 0 0.000756217162865 +Gc5_121 0 n10 ns121 0 0.000400876889153 +Gc5_122 0 n10 ns122 0 0.000877046883375 +Gc5_123 0 n10 ns123 0 0.00197399010826 +Gc5_124 0 n10 ns124 0 0.00054443278685 +Gc5_125 0 n10 ns125 0 8.67217920966e-007 +Gc5_126 0 n10 ns126 0 4.50385457421e-007 +Gc5_127 0 n10 ns127 0 6.33070092194e-007 +Gc5_128 0 n10 ns128 0 -1.74209232593e-006 +Gc5_129 0 n10 ns129 0 -4.80846067735e-007 +Gc5_130 0 n10 ns130 0 2.38322799994e-007 +Gc5_131 0 n10 ns131 0 0.000137568292077 +Gc5_132 0 n10 ns132 0 0.000244422823288 +Gc5_133 0 n10 ns133 0 0.000528106380582 +Gc5_134 0 n10 ns134 0 0.000308019269196 +Gc5_135 0 n10 ns135 0 0.000164104752923 +Gc5_136 0 n10 ns136 0 -0.000239830676969 +Gc5_137 0 n10 ns137 0 -0.00487086577687 +Gc5_138 0 n10 ns138 0 0.00307159990312 +Gc5_139 0 n10 ns139 0 -0.0013937685088 +Gc5_140 0 n10 ns140 0 -0.000673846456707 +Gc5_141 0 n10 ns141 0 0.00666867861713 +Gc5_142 0 n10 ns142 0 4.77119795533e-005 +Gc5_143 0 n10 ns143 0 0.000200747763204 +Gc5_144 0 n10 ns144 0 0.00544070376458 +Gc5_145 0 n10 ns145 0 0.007556639166 +Gc5_146 0 n10 ns146 0 5.01585021953e-008 +Gc5_147 0 n10 ns147 0 1.88479623298e-007 +Gc5_148 0 n10 ns148 0 1.65260794724e-007 +Gc5_149 0 n10 ns149 0 -8.85583433198e-008 +Gc5_150 0 n10 ns150 0 0.000440628752879 +Gc5_151 0 n10 ns151 0 7.78742105824e-008 +Gc5_152 0 n10 ns152 0 1.66515122369e-008 +Gc5_153 0 n10 ns153 0 0.000169062465585 +Gc5_154 0 n10 ns154 0 0.0007297509493 +Gc5_155 0 n10 ns155 0 -0.000550037526474 +Gc5_156 0 n10 ns156 0 0.00258703415528 +Gc5_157 0 n10 ns157 0 0.00137768685727 +Gc5_158 0 n10 ns158 0 0.00226603083026 +Gc5_159 0 n10 ns159 0 0.000555924758466 +Gc5_160 0 n10 ns160 0 7.7616907659e-007 +Gc5_161 0 n10 ns161 0 5.97045611605e-007 +Gc5_162 0 n10 ns162 0 3.68340375248e-006 +Gc5_163 0 n10 ns163 0 -2.15720747714e-006 +Gc5_164 0 n10 ns164 0 -4.59310243133e-007 +Gc5_165 0 n10 ns165 0 2.06346251822e-007 +Gc5_166 0 n10 ns166 0 0.000253621015654 +Gc5_167 0 n10 ns167 0 0.000238557891659 +Gc5_168 0 n10 ns168 0 0.00282543572258 +Gc5_169 0 n10 ns169 0 0.0028915616786 +Gc5_170 0 n10 ns170 0 0.000300536550502 +Gc5_171 0 n10 ns171 0 0.000203720654297 +Gc5_172 0 n10 ns172 0 0.00202254876623 +Gc5_173 0 n10 ns173 0 -0.0358758046927 +Gc5_174 0 n10 ns174 0 0.0014172271784 +Gc5_175 0 n10 ns175 0 -0.00135961432629 +Gc5_176 0 n10 ns176 0 0.00660950623335 +Gc5_177 0 n10 ns177 0 -2.42494050928e-005 +Gc5_178 0 n10 ns178 0 -7.8231350611e-005 +Gc5_179 0 n10 ns179 0 -0.00292289107195 +Gc5_180 0 n10 ns180 0 -0.00353358919217 +Gc5_181 0 n10 ns181 0 -5.95523395089e-008 +Gc5_182 0 n10 ns182 0 3.08566421959e-011 +Gc5_183 0 n10 ns183 0 -7.90146023556e-008 +Gc5_184 0 n10 ns184 0 4.41624418138e-008 +Gc5_185 0 n10 ns185 0 -0.000220705733685 +Gc5_186 0 n10 ns186 0 -8.6710550191e-009 +Gc5_187 0 n10 ns187 0 -7.5331251195e-009 +Gc5_188 0 n10 ns188 0 -0.000124125145182 +Gc5_189 0 n10 ns189 0 0.000549217917676 +Gc5_190 0 n10 ns190 0 1.41722646686e-005 +Gc5_191 0 n10 ns191 0 -0.00210894591031 +Gc5_192 0 n10 ns192 0 -0.000496842346528 +Gc5_193 0 n10 ns193 0 0.00219890433548 +Gc5_194 0 n10 ns194 0 0.00106815906849 +Gc5_195 0 n10 ns195 0 7.94441720863e-007 +Gc5_196 0 n10 ns196 0 3.27823483595e-007 +Gc5_197 0 n10 ns197 0 1.92068092356e-006 +Gc5_198 0 n10 ns198 0 -9.93139779912e-007 +Gc5_199 0 n10 ns199 0 -3.45238418945e-008 +Gc5_200 0 n10 ns200 0 4.54955657987e-007 +Gc5_201 0 n10 ns201 0 9.12913924553e-005 +Gc5_202 0 n10 ns202 0 0.000122568058676 +Gc5_203 0 n10 ns203 0 0.000248336711802 +Gc5_204 0 n10 ns204 0 0.000123971636818 +Gc5_205 0 n10 ns205 0 0.000178899512439 +Gc5_206 0 n10 ns206 0 -0.000193941220407 +Gc5_207 0 n10 ns207 0 -0.00422188222381 +Gc5_208 0 n10 ns208 0 0.00284404156083 +Gc5_209 0 n10 ns209 0 -0.00118114697826 +Gc5_210 0 n10 ns210 0 -0.000485502240563 +Gd5_1 0 n10 ni1 0 -0.000926052348786 +Gd5_2 0 n10 ni2 0 -0.00155592086807 +Gd5_3 0 n10 ni3 0 -0.000969177984255 +Gd5_4 0 n10 ni4 0 -0.00198447410767 +Gd5_5 0 n10 ni5 0 0.00124980667085 +Gd5_6 0 n10 ni6 0 -0.00171294855148 +Gc6_1 0 n12 ns1 0 -0.00660817816406 +Gc6_2 0 n12 ns2 0 2.59198704788e-005 +Gc6_3 0 n12 ns3 0 0.000103971324483 +Gc6_4 0 n12 ns4 0 0.0035490869107 +Gc6_5 0 n12 ns5 0 0.0028662947242 +Gc6_6 0 n12 ns6 0 2.21368544989e-009 +Gc6_7 0 n12 ns7 0 -5.05913450259e-008 +Gc6_8 0 n12 ns8 0 -4.46985145281e-008 +Gc6_9 0 n12 ns9 0 -6.96029296294e-008 +Gc6_10 0 n12 ns10 0 0.000249830419647 +Gc6_11 0 n12 ns11 0 1.23121691115e-008 +Gc6_12 0 n12 ns12 0 -1.99578271629e-008 +Gc6_13 0 n12 ns13 0 0.000109936989745 +Gc6_14 0 n12 ns14 0 0.00117974749493 +Gc6_15 0 n12 ns15 0 0.000122999327296 +Gc6_16 0 n12 ns16 0 0.000674011117646 +Gc6_17 0 n12 ns17 0 0.000544607435491 +Gc6_18 0 n12 ns18 0 -0.00187224863909 +Gc6_19 0 n12 ns19 0 -0.000890705492752 +Gc6_20 0 n12 ns20 0 4.18524531966e-007 +Gc6_21 0 n12 ns21 0 4.2725112313e-007 +Gc6_22 0 n12 ns22 0 1.24412791742e-006 +Gc6_23 0 n12 ns23 0 -3.87576026206e-007 +Gc6_24 0 n12 ns24 0 -4.77893680594e-009 +Gc6_25 0 n12 ns25 0 1.90020930633e-007 +Gc6_26 0 n12 ns26 0 -0.000250750877062 +Gc6_27 0 n12 ns27 0 -5.30802850513e-005 +Gc6_28 0 n12 ns28 0 -0.00102858049521 +Gc6_29 0 n12 ns29 0 0.000142123910588 +Gc6_30 0 n12 ns30 0 0.000360553063625 +Gc6_31 0 n12 ns31 0 0.000313044418914 +Gc6_32 0 n12 ns32 0 -0.00167495214867 +Gc6_33 0 n12 ns33 0 0.00168019806777 +Gc6_34 0 n12 ns34 0 1.50670378754e-005 +Gc6_35 0 n12 ns35 0 0.00032709353171 +Gc6_36 0 n12 ns36 0 -0.00660660212943 +Gc6_37 0 n12 ns37 0 2.62774655073e-005 +Gc6_38 0 n12 ns38 0 7.69475433573e-005 +Gc6_39 0 n12 ns39 0 0.002930696564 +Gc6_40 0 n12 ns40 0 0.00353012071446 +Gc6_41 0 n12 ns41 0 4.41259007735e-008 +Gc6_42 0 n12 ns42 0 -1.78698535909e-008 +Gc6_43 0 n12 ns43 0 3.27924747602e-009 +Gc6_44 0 n12 ns44 0 -7.21748403321e-008 +Gc6_45 0 n12 ns45 0 0.000230215362561 +Gc6_46 0 n12 ns46 0 1.71576325325e-008 +Gc6_47 0 n12 ns47 0 -1.20066956494e-008 +Gc6_48 0 n12 ns48 0 0.000100700154206 +Gc6_49 0 n12 ns49 0 -0.00069435548942 +Gc6_50 0 n12 ns50 0 -6.87869697728e-005 +Gc6_51 0 n12 ns51 0 0.00250228377172 +Gc6_52 0 n12 ns52 0 0.000435352735162 +Gc6_53 0 n12 ns53 0 -0.00226280015715 +Gc6_54 0 n12 ns54 0 -0.00103796813174 +Gc6_55 0 n12 ns55 0 4.54198802689e-007 +Gc6_56 0 n12 ns56 0 4.56730371762e-007 +Gc6_57 0 n12 ns57 0 9.55564973191e-007 +Gc6_58 0 n12 ns58 0 -1.08316455001e-006 +Gc6_59 0 n12 ns59 0 8.42955537474e-008 +Gc6_60 0 n12 ns60 0 4.58181396112e-007 +Gc6_61 0 n12 ns61 0 -2.34136639456e-005 +Gc6_62 0 n12 ns62 0 6.6312500601e-006 +Gc6_63 0 n12 ns63 0 -0.00100567362558 +Gc6_64 0 n12 ns64 0 9.58828801233e-005 +Gc6_65 0 n12 ns65 0 7.69610315735e-005 +Gc6_66 0 n12 ns66 0 1.85345845989e-005 +Gc6_67 0 n12 ns67 0 -0.00137231736391 +Gc6_68 0 n12 ns68 0 0.0013090286339 +Gc6_69 0 n12 ns69 0 -4.85504110656e-005 +Gc6_70 0 n12 ns70 0 0.000163852434865 +Gc6_71 0 n12 ns71 0 -0.00666711070496 +Gc6_72 0 n12 ns72 0 -6.50245522251e-005 +Gc6_73 0 n12 ns73 0 -0.000203673873938 +Gc6_74 0 n12 ns74 0 -0.00643442670937 +Gc6_75 0 n12 ns75 0 -0.00642976571139 +Gc6_76 0 n12 ns76 0 6.31146798789e-008 +Gc6_77 0 n12 ns77 0 3.87071497926e-008 +Gc6_78 0 n12 ns78 0 8.45748539863e-008 +Gc6_79 0 n12 ns79 0 -1.68681625517e-008 +Gc6_80 0 n12 ns80 0 -0.000452832555259 +Gc6_81 0 n12 ns81 0 1.2507419699e-008 +Gc6_82 0 n12 ns82 0 9.58284206506e-009 +Gc6_83 0 n12 ns83 0 -0.000276697292605 +Gc6_84 0 n12 ns84 0 -0.000198657927845 +Gc6_85 0 n12 ns85 0 -0.000121068624796 +Gc6_86 0 n12 ns86 0 -0.00214083381434 +Gc6_87 0 n12 ns87 0 3.16462314471e-005 +Gc6_88 0 n12 ns88 0 -0.0020581181058 +Gc6_89 0 n12 ns89 0 -0.00177525973892 +Gc6_90 0 n12 ns90 0 5.07226321529e-007 +Gc6_91 0 n12 ns91 0 7.05182687975e-007 +Gc6_92 0 n12 ns92 0 3.51410619305e-006 +Gc6_93 0 n12 ns93 0 -1.10887105996e-006 +Gc6_94 0 n12 ns94 0 -1.58238796069e-007 +Gc6_95 0 n12 ns95 0 2.72720176756e-007 +Gc6_96 0 n12 ns96 0 -0.000165515630811 +Gc6_97 0 n12 ns97 0 0.000113344437613 +Gc6_98 0 n12 ns98 0 -0.00102256876639 +Gc6_99 0 n12 ns99 0 -0.00114591861308 +Gc6_100 0 n12 ns100 0 -0.000819677978742 +Gc6_101 0 n12 ns101 0 -0.00013595150291 +Gc6_102 0 n12 ns102 0 -0.00509392831969 +Gc6_103 0 n12 ns103 0 0.00793595023355 +Gc6_104 0 n12 ns104 0 0.000401874394891 +Gc6_105 0 n12 ns105 0 0.000890951835744 +Gc6_106 0 n12 ns106 0 0.00660905491427 +Gc6_107 0 n12 ns107 0 -2.56444240833e-005 +Gc6_108 0 n12 ns108 0 -0.000103336247373 +Gc6_109 0 n12 ns109 0 -0.00354202611802 +Gc6_110 0 n12 ns110 0 -0.00286638237591 +Gc6_111 0 n12 ns111 0 1.39766317411e-008 +Gc6_112 0 n12 ns112 0 2.06338469197e-008 +Gc6_113 0 n12 ns113 0 -6.75475023184e-009 +Gc6_114 0 n12 ns114 0 5.28989438854e-011 +Gc6_115 0 n12 ns115 0 -0.000238325501069 +Gc6_116 0 n12 ns116 0 9.90714505497e-009 +Gc6_117 0 n12 ns117 0 1.69628739398e-010 +Gc6_118 0 n12 ns118 0 -0.000133638116877 +Gc6_119 0 n12 ns119 0 -0.00095142332958 +Gc6_120 0 n12 ns120 0 -9.24598415157e-005 +Gc6_121 0 n12 ns121 0 -0.000491275928222 +Gc6_122 0 n12 ns122 0 -0.000547563826411 +Gc6_123 0 n12 ns123 0 0.00188913618348 +Gc6_124 0 n12 ns124 0 0.000976086566843 +Gc6_125 0 n12 ns125 0 9.2833354361e-007 +Gc6_126 0 n12 ns126 0 2.05397295707e-007 +Gc6_127 0 n12 ns127 0 2.82099523981e-008 +Gc6_128 0 n12 ns128 0 -1.32085846587e-006 +Gc6_129 0 n12 ns129 0 1.53244690569e-008 +Gc6_130 0 n12 ns130 0 4.50641598565e-007 +Gc6_131 0 n12 ns131 0 9.28529189049e-005 +Gc6_132 0 n12 ns132 0 0.000168522292199 +Gc6_133 0 n12 ns133 0 0.000209106890596 +Gc6_134 0 n12 ns134 0 -0.000108107850985 +Gc6_135 0 n12 ns135 0 2.24261668201e-005 +Gc6_136 0 n12 ns136 0 -0.000284867999392 +Gc6_137 0 n12 ns137 0 -0.00377417911862 +Gc6_138 0 n12 ns138 0 0.00256888489802 +Gc6_139 0 n12 ns139 0 -0.00118999011364 +Gc6_140 0 n12 ns140 0 -0.000382336150241 +Gc6_141 0 n12 ns141 0 0.00660725561451 +Gc6_142 0 n12 ns142 0 -2.60552071098e-005 +Gc6_143 0 n12 ns143 0 -7.59823482237e-005 +Gc6_144 0 n12 ns144 0 -0.00292936525292 +Gc6_145 0 n12 ns145 0 -0.00352713449898 +Gc6_146 0 n12 ns146 0 -3.92309476762e-008 +Gc6_147 0 n12 ns147 0 4.25190377409e-009 +Gc6_148 0 n12 ns148 0 -4.6686179325e-008 +Gc6_149 0 n12 ns149 0 1.79574821102e-008 +Gc6_150 0 n12 ns150 0 -0.000221015669109 +Gc6_151 0 n12 ns151 0 -1.27022073073e-008 +Gc6_152 0 n12 ns152 0 -1.1826303162e-008 +Gc6_153 0 n12 ns153 0 -0.000121689590964 +Gc6_154 0 n12 ns154 0 0.000547347142323 +Gc6_155 0 n12 ns155 0 1.3870744736e-005 +Gc6_156 0 n12 ns156 0 -0.0021063559064 +Gc6_157 0 n12 ns157 0 -0.000495421610217 +Gc6_158 0 n12 ns158 0 0.00219840382181 +Gc6_159 0 n12 ns159 0 0.00106683662604 +Gc6_160 0 n12 ns160 0 7.72587717684e-007 +Gc6_161 0 n12 ns161 0 3.355340825e-007 +Gc6_162 0 n12 ns162 0 1.95938443558e-006 +Gc6_163 0 n12 ns163 0 -8.95317704898e-007 +Gc6_164 0 n12 ns164 0 -1.37563068516e-008 +Gc6_165 0 n12 ns165 0 3.68526397724e-007 +Gc6_166 0 n12 ns166 0 8.51935192345e-005 +Gc6_167 0 n12 ns167 0 0.000124230474239 +Gc6_168 0 n12 ns168 0 0.000247820205538 +Gc6_169 0 n12 ns169 0 0.000105184625153 +Gc6_170 0 n12 ns170 0 0.00017948271293 +Gc6_171 0 n12 ns171 0 -0.000201903629272 +Gc6_172 0 n12 ns172 0 -0.00417424462406 +Gc6_173 0 n12 ns173 0 0.00282242532088 +Gc6_174 0 n12 ns174 0 -0.00118248676019 +Gc6_175 0 n12 ns175 0 -0.000490735714174 +Gc6_176 0 n12 ns176 0 0.00666904779187 +Gc6_177 0 n12 ns177 0 4.88026719438e-005 +Gc6_178 0 n12 ns178 0 0.000227124133559 +Gc6_179 0 n12 ns179 0 0.00636521125364 +Gc6_180 0 n12 ns180 0 0.00646587538015 +Gc6_181 0 n12 ns181 0 3.16465043576e-008 +Gc6_182 0 n12 ns182 0 1.38263395927e-007 +Gc6_183 0 n12 ns183 0 1.49460172817e-007 +Gc6_184 0 n12 ns184 0 -1.00195171033e-007 +Gc6_185 0 n12 ns185 0 0.000458424144628 +Gc6_186 0 n12 ns186 0 7.97086484132e-008 +Gc6_187 0 n12 ns187 0 1.72420981296e-009 +Gc6_188 0 n12 ns188 0 0.000103950569752 +Gc6_189 0 n12 ns189 0 0.000220132652628 +Gc6_190 0 n12 ns190 0 1.91514615531e-005 +Gc6_191 0 n12 ns191 0 0.00160742098635 +Gc6_192 0 n12 ns192 0 -0.000141319847289 +Gc6_193 0 n12 ns193 0 0.00197800391768 +Gc6_194 0 n12 ns194 0 0.00153837256734 +Gc6_195 0 n12 ns195 0 8.36093483429e-007 +Gc6_196 0 n12 ns196 0 3.62941139347e-007 +Gc6_197 0 n12 ns197 0 2.27985024288e-006 +Gc6_198 0 n12 ns198 0 -1.34012672483e-006 +Gc6_199 0 n12 ns199 0 3.86133842449e-007 +Gc6_200 0 n12 ns200 0 2.11854081832e-007 +Gc6_201 0 n12 ns201 0 0.00014246374598 +Gc6_202 0 n12 ns202 0 -0.00011012210191 +Gc6_203 0 n12 ns203 0 0.00161593471403 +Gc6_204 0 n12 ns204 0 0.000155728979191 +Gc6_205 0 n12 ns205 0 0.00025634776084 +Gc6_206 0 n12 ns206 0 0.000378321581055 +Gc6_207 0 n12 ns207 0 0.00312403702052 +Gc6_208 0 n12 ns208 0 -0.0311240140613 +Gc6_209 0 n12 ns209 0 0.0014297684344 +Gc6_210 0 n12 ns210 0 -0.00128306154334 +Gd6_1 0 n12 ni1 0 -0.00070443336419 +Gd6_2 0 n12 ni2 0 -0.000748280556761 +Gd6_3 0 n12 ni3 0 -0.00240277609336 +Gd6_4 0 n12 ni4 0 -0.00161010083273 +Gd6_5 0 n12 ni5 0 -0.00169459355139 +Gd6_6 0 n12 ni6 0 0.00083948192548 +.ends + +.subckt 744838480095 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 266400082.649 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 3307450.25377 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 673488.076605 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 428850.778852 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 156085.272074 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 29656.4702222 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 82059.7296993 +Ra8 ns8 0 82059.7296993 +Ga7 ns7 0 ns8 0 -7.60582757162e-005 +Ga8 ns8 0 ns7 0 7.60582757162e-005 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 80003.9153299 +Ra10 ns10 0 80003.9153299 +Ga9 ns9 0 ns10 0 -7.72948134509e-005 +Ga10 ns10 0 ns9 0 7.72948134509e-005 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 61586.8898587 +Ra12 ns12 0 61586.8898587 +Ga11 ns11 0 ns12 0 -9.35567933183e-005 +Ga12 ns12 0 ns11 0 9.35567933183e-005 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 217363.859349 +Ra14 ns14 0 217363.859349 +Ga13 ns13 0 ns14 0 -0.000213977180693 +Ga14 ns14 0 ns13 0 0.000213977180693 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 27924.0216967 +Ra16 ns16 0 27924.0216967 +Ga15 ns15 0 ns16 0 -0.000305228798742 +Ga16 ns16 0 ns15 0 0.000305228798742 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 13389.8066242 +Ra18 ns18 0 13389.8066242 +Ga17 ns17 0 ns18 0 -0.000324743439093 +Ga18 ns18 0 ns17 0 0.000324743439093 +Ca19 ns19 0 1e-012 +Ca20 ns20 0 1e-012 +Ra19 ns19 0 36176.1637754 +Ra20 ns20 0 36176.1637754 +Ga19 ns19 0 ns20 0 -0.000338166530519 +Ga20 ns20 0 ns19 0 0.000338166530519 +Ca21 ns21 0 1e-012 +Ca22 ns22 0 1e-012 +Ra21 ns21 0 1986.6754352 +Ra22 ns22 0 1986.6754352 +Ga21 ns21 0 ns22 0 -0.000399482118772 +Ga22 ns22 0 ns21 0 0.000399482118772 +Ca23 ns23 0 1e-012 +Ra23 ns23 0 266400082.649 +Ca24 ns24 0 1e-012 +Ra24 ns24 0 3307450.25377 +Ca25 ns25 0 1e-012 +Ra25 ns25 0 673488.076605 +Ca26 ns26 0 1e-012 +Ra26 ns26 0 428850.778852 +Ca27 ns27 0 1e-012 +Ra27 ns27 0 156085.272074 +Ca28 ns28 0 1e-012 +Ra28 ns28 0 29656.4702222 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 82059.7296993 +Ra30 ns30 0 82059.7296993 +Ga29 ns29 0 ns30 0 -7.60582757162e-005 +Ga30 ns30 0 ns29 0 7.60582757162e-005 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 80003.9153299 +Ra32 ns32 0 80003.9153299 +Ga31 ns31 0 ns32 0 -7.72948134509e-005 +Ga32 ns32 0 ns31 0 7.72948134509e-005 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 61586.8898587 +Ra34 ns34 0 61586.8898587 +Ga33 ns33 0 ns34 0 -9.35567933183e-005 +Ga34 ns34 0 ns33 0 9.35567933183e-005 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 217363.859349 +Ra36 ns36 0 217363.859349 +Ga35 ns35 0 ns36 0 -0.000213977180693 +Ga36 ns36 0 ns35 0 0.000213977180693 +Ca37 ns37 0 1e-012 +Ca38 ns38 0 1e-012 +Ra37 ns37 0 27924.0216967 +Ra38 ns38 0 27924.0216967 +Ga37 ns37 0 ns38 0 -0.000305228798742 +Ga38 ns38 0 ns37 0 0.000305228798742 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 13389.8066242 +Ra40 ns40 0 13389.8066242 +Ga39 ns39 0 ns40 0 -0.000324743439093 +Ga40 ns40 0 ns39 0 0.000324743439093 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 36176.1637754 +Ra42 ns42 0 36176.1637754 +Ga41 ns41 0 ns42 0 -0.000338166530519 +Ga42 ns42 0 ns41 0 0.000338166530519 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 1986.6754352 +Ra44 ns44 0 1986.6754352 +Ga43 ns43 0 ns44 0 -0.000399482118772 +Ga44 ns44 0 ns43 0 0.000399482118772 +Ca45 ns45 0 1e-012 +Ra45 ns45 0 266400082.649 +Ca46 ns46 0 1e-012 +Ra46 ns46 0 3307450.25377 +Ca47 ns47 0 1e-012 +Ra47 ns47 0 673488.076605 +Ca48 ns48 0 1e-012 +Ra48 ns48 0 428850.778852 +Ca49 ns49 0 1e-012 +Ra49 ns49 0 156085.272074 +Ca50 ns50 0 1e-012 +Ra50 ns50 0 29656.4702222 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 82059.7296993 +Ra52 ns52 0 82059.7296993 +Ga51 ns51 0 ns52 0 -7.60582757162e-005 +Ga52 ns52 0 ns51 0 7.60582757162e-005 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 80003.9153299 +Ra54 ns54 0 80003.9153299 +Ga53 ns53 0 ns54 0 -7.72948134509e-005 +Ga54 ns54 0 ns53 0 7.72948134509e-005 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 61586.8898587 +Ra56 ns56 0 61586.8898587 +Ga55 ns55 0 ns56 0 -9.35567933183e-005 +Ga56 ns56 0 ns55 0 9.35567933183e-005 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 217363.859349 +Ra58 ns58 0 217363.859349 +Ga57 ns57 0 ns58 0 -0.000213977180693 +Ga58 ns58 0 ns57 0 0.000213977180693 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 27924.0216967 +Ra60 ns60 0 27924.0216967 +Ga59 ns59 0 ns60 0 -0.000305228798742 +Ga60 ns60 0 ns59 0 0.000305228798742 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 13389.8066242 +Ra62 ns62 0 13389.8066242 +Ga61 ns61 0 ns62 0 -0.000324743439093 +Ga62 ns62 0 ns61 0 0.000324743439093 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 36176.1637754 +Ra64 ns64 0 36176.1637754 +Ga63 ns63 0 ns64 0 -0.000338166530519 +Ga64 ns64 0 ns63 0 0.000338166530519 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 1986.6754352 +Ra66 ns66 0 1986.6754352 +Ga65 ns65 0 ns66 0 -0.000399482118772 +Ga66 ns66 0 ns65 0 0.000399482118772 +Ca67 ns67 0 1e-012 +Ra67 ns67 0 266400082.649 +Ca68 ns68 0 1e-012 +Ra68 ns68 0 3307450.25377 +Ca69 ns69 0 1e-012 +Ra69 ns69 0 673488.076605 +Ca70 ns70 0 1e-012 +Ra70 ns70 0 428850.778852 +Ca71 ns71 0 1e-012 +Ra71 ns71 0 156085.272074 +Ca72 ns72 0 1e-012 +Ra72 ns72 0 29656.4702222 +Ca73 ns73 0 1e-012 +Ca74 ns74 0 1e-012 +Ra73 ns73 0 82059.7296993 +Ra74 ns74 0 82059.7296993 +Ga73 ns73 0 ns74 0 -7.60582757162e-005 +Ga74 ns74 0 ns73 0 7.60582757162e-005 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 80003.9153299 +Ra76 ns76 0 80003.9153299 +Ga75 ns75 0 ns76 0 -7.72948134509e-005 +Ga76 ns76 0 ns75 0 7.72948134509e-005 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 61586.8898587 +Ra78 ns78 0 61586.8898587 +Ga77 ns77 0 ns78 0 -9.35567933183e-005 +Ga78 ns78 0 ns77 0 9.35567933183e-005 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 217363.859349 +Ra80 ns80 0 217363.859349 +Ga79 ns79 0 ns80 0 -0.000213977180693 +Ga80 ns80 0 ns79 0 0.000213977180693 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 27924.0216967 +Ra82 ns82 0 27924.0216967 +Ga81 ns81 0 ns82 0 -0.000305228798742 +Ga82 ns82 0 ns81 0 0.000305228798742 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 13389.8066242 +Ra84 ns84 0 13389.8066242 +Ga83 ns83 0 ns84 0 -0.000324743439093 +Ga84 ns84 0 ns83 0 0.000324743439093 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 36176.1637754 +Ra86 ns86 0 36176.1637754 +Ga85 ns85 0 ns86 0 -0.000338166530519 +Ga86 ns86 0 ns85 0 0.000338166530519 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 1986.6754352 +Ra88 ns88 0 1986.6754352 +Ga87 ns87 0 ns88 0 -0.000399482118772 +Ga88 ns88 0 ns87 0 0.000399482118772 +Ca89 ns89 0 1e-012 +Ra89 ns89 0 266400082.649 +Ca90 ns90 0 1e-012 +Ra90 ns90 0 3307450.25377 +Ca91 ns91 0 1e-012 +Ra91 ns91 0 673488.076605 +Ca92 ns92 0 1e-012 +Ra92 ns92 0 428850.778852 +Ca93 ns93 0 1e-012 +Ra93 ns93 0 156085.272074 +Ca94 ns94 0 1e-012 +Ra94 ns94 0 29656.4702222 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 82059.7296993 +Ra96 ns96 0 82059.7296993 +Ga95 ns95 0 ns96 0 -7.60582757162e-005 +Ga96 ns96 0 ns95 0 7.60582757162e-005 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 80003.9153299 +Ra98 ns98 0 80003.9153299 +Ga97 ns97 0 ns98 0 -7.72948134509e-005 +Ga98 ns98 0 ns97 0 7.72948134509e-005 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 61586.8898587 +Ra100 ns100 0 61586.8898587 +Ga99 ns99 0 ns100 0 -9.35567933183e-005 +Ga100 ns100 0 ns99 0 9.35567933183e-005 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 217363.859349 +Ra102 ns102 0 217363.859349 +Ga101 ns101 0 ns102 0 -0.000213977180693 +Ga102 ns102 0 ns101 0 0.000213977180693 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 27924.0216967 +Ra104 ns104 0 27924.0216967 +Ga103 ns103 0 ns104 0 -0.000305228798742 +Ga104 ns104 0 ns103 0 0.000305228798742 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 13389.8066242 +Ra106 ns106 0 13389.8066242 +Ga105 ns105 0 ns106 0 -0.000324743439093 +Ga106 ns106 0 ns105 0 0.000324743439093 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 36176.1637754 +Ra108 ns108 0 36176.1637754 +Ga107 ns107 0 ns108 0 -0.000338166530519 +Ga108 ns108 0 ns107 0 0.000338166530519 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 1986.6754352 +Ra110 ns110 0 1986.6754352 +Ga109 ns109 0 ns110 0 -0.000399482118772 +Ga110 ns110 0 ns109 0 0.000399482118772 +Ca111 ns111 0 1e-012 +Ra111 ns111 0 266400082.649 +Ca112 ns112 0 1e-012 +Ra112 ns112 0 3307450.25377 +Ca113 ns113 0 1e-012 +Ra113 ns113 0 673488.076605 +Ca114 ns114 0 1e-012 +Ra114 ns114 0 428850.778852 +Ca115 ns115 0 1e-012 +Ra115 ns115 0 156085.272074 +Ca116 ns116 0 1e-012 +Ra116 ns116 0 29656.4702222 +Ca117 ns117 0 1e-012 +Ca118 ns118 0 1e-012 +Ra117 ns117 0 82059.7296993 +Ra118 ns118 0 82059.7296993 +Ga117 ns117 0 ns118 0 -7.60582757162e-005 +Ga118 ns118 0 ns117 0 7.60582757162e-005 +Ca119 ns119 0 1e-012 +Ca120 ns120 0 1e-012 +Ra119 ns119 0 80003.9153299 +Ra120 ns120 0 80003.9153299 +Ga119 ns119 0 ns120 0 -7.72948134509e-005 +Ga120 ns120 0 ns119 0 7.72948134509e-005 +Ca121 ns121 0 1e-012 +Ca122 ns122 0 1e-012 +Ra121 ns121 0 61586.8898587 +Ra122 ns122 0 61586.8898587 +Ga121 ns121 0 ns122 0 -9.35567933183e-005 +Ga122 ns122 0 ns121 0 9.35567933183e-005 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 217363.859349 +Ra124 ns124 0 217363.859349 +Ga123 ns123 0 ns124 0 -0.000213977180693 +Ga124 ns124 0 ns123 0 0.000213977180693 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 27924.0216967 +Ra126 ns126 0 27924.0216967 +Ga125 ns125 0 ns126 0 -0.000305228798742 +Ga126 ns126 0 ns125 0 0.000305228798742 +Ca127 ns127 0 1e-012 +Ca128 ns128 0 1e-012 +Ra127 ns127 0 13389.8066242 +Ra128 ns128 0 13389.8066242 +Ga127 ns127 0 ns128 0 -0.000324743439093 +Ga128 ns128 0 ns127 0 0.000324743439093 +Ca129 ns129 0 1e-012 +Ca130 ns130 0 1e-012 +Ra129 ns129 0 36176.1637754 +Ra130 ns130 0 36176.1637754 +Ga129 ns129 0 ns130 0 -0.000338166530519 +Ga130 ns130 0 ns129 0 0.000338166530519 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 1986.6754352 +Ra132 ns132 0 1986.6754352 +Ga131 ns131 0 ns132 0 -0.000399482118772 +Ga132 ns132 0 ns131 0 0.000399482118772 + +Gb1_1 ns1 0 ni1 0 3.75375258917e-009 +Gb2_1 ns2 0 ni1 0 3.02347706926e-007 +Gb3_1 ns3 0 ni1 0 1.48480728128e-006 +Gb4_1 ns4 0 ni1 0 2.33181341696e-006 +Gb5_1 ns5 0 ni1 0 6.4067543767e-006 +Gb6_1 ns6 0 ni1 0 3.37194545577e-005 +Gb7_1 ns7 0 ni1 0 7.80107861365e-005 +Gb9_1 ns9 0 ni1 0 7.93160966378e-005 +Gb11_1 ns11 0 ni1 0 9.63748396341e-005 +Gb13_1 ns13 0 ni1 0 0.000214076094716 +Gb15_1 ns15 0 ni1 0 0.000309430436033 +Gb17_1 ns17 0 ni1 0 0.000341919002989 +Gb19_1 ns19 0 ni1 0 0.000340426093006 +Gb21_1 ns21 0 ni1 0 0.00082039899598 +Gb23_2 ns23 0 ni2 0 3.75375258917e-009 +Gb24_2 ns24 0 ni2 0 3.02347706926e-007 +Gb25_2 ns25 0 ni2 0 1.48480728128e-006 +Gb26_2 ns26 0 ni2 0 2.33181341696e-006 +Gb27_2 ns27 0 ni2 0 6.4067543767e-006 +Gb28_2 ns28 0 ni2 0 3.37194545577e-005 +Gb29_2 ns29 0 ni2 0 7.80107861365e-005 +Gb31_2 ns31 0 ni2 0 7.93160966378e-005 +Gb33_2 ns33 0 ni2 0 9.63748396341e-005 +Gb35_2 ns35 0 ni2 0 0.000214076094716 +Gb37_2 ns37 0 ni2 0 0.000309430436033 +Gb39_2 ns39 0 ni2 0 0.000341919002989 +Gb41_2 ns41 0 ni2 0 0.000340426093006 +Gb43_2 ns43 0 ni2 0 0.00082039899598 +Gb45_3 ns45 0 ni3 0 3.75375258917e-009 +Gb46_3 ns46 0 ni3 0 3.02347706926e-007 +Gb47_3 ns47 0 ni3 0 1.48480728128e-006 +Gb48_3 ns48 0 ni3 0 2.33181341696e-006 +Gb49_3 ns49 0 ni3 0 6.4067543767e-006 +Gb50_3 ns50 0 ni3 0 3.37194545577e-005 +Gb51_3 ns51 0 ni3 0 7.80107861365e-005 +Gb53_3 ns53 0 ni3 0 7.93160966378e-005 +Gb55_3 ns55 0 ni3 0 9.63748396341e-005 +Gb57_3 ns57 0 ni3 0 0.000214076094716 +Gb59_3 ns59 0 ni3 0 0.000309430436033 +Gb61_3 ns61 0 ni3 0 0.000341919002989 +Gb63_3 ns63 0 ni3 0 0.000340426093006 +Gb65_3 ns65 0 ni3 0 0.00082039899598 +Gb67_4 ns67 0 ni4 0 3.75375258917e-009 +Gb68_4 ns68 0 ni4 0 3.02347706926e-007 +Gb69_4 ns69 0 ni4 0 1.48480728128e-006 +Gb70_4 ns70 0 ni4 0 2.33181341696e-006 +Gb71_4 ns71 0 ni4 0 6.4067543767e-006 +Gb72_4 ns72 0 ni4 0 3.37194545577e-005 +Gb73_4 ns73 0 ni4 0 7.80107861365e-005 +Gb75_4 ns75 0 ni4 0 7.93160966378e-005 +Gb77_4 ns77 0 ni4 0 9.63748396341e-005 +Gb79_4 ns79 0 ni4 0 0.000214076094716 +Gb81_4 ns81 0 ni4 0 0.000309430436033 +Gb83_4 ns83 0 ni4 0 0.000341919002989 +Gb85_4 ns85 0 ni4 0 0.000340426093006 +Gb87_4 ns87 0 ni4 0 0.00082039899598 +Gb89_5 ns89 0 ni5 0 3.75375258917e-009 +Gb90_5 ns90 0 ni5 0 3.02347706926e-007 +Gb91_5 ns91 0 ni5 0 1.48480728128e-006 +Gb92_5 ns92 0 ni5 0 2.33181341696e-006 +Gb93_5 ns93 0 ni5 0 6.4067543767e-006 +Gb94_5 ns94 0 ni5 0 3.37194545577e-005 +Gb95_5 ns95 0 ni5 0 7.80107861365e-005 +Gb97_5 ns97 0 ni5 0 7.93160966378e-005 +Gb99_5 ns99 0 ni5 0 9.63748396341e-005 +Gb101_5 ns101 0 ni5 0 0.000214076094716 +Gb103_5 ns103 0 ni5 0 0.000309430436033 +Gb105_5 ns105 0 ni5 0 0.000341919002989 +Gb107_5 ns107 0 ni5 0 0.000340426093006 +Gb109_5 ns109 0 ni5 0 0.00082039899598 +Gb111_6 ns111 0 ni6 0 3.75375258917e-009 +Gb112_6 ns112 0 ni6 0 3.02347706926e-007 +Gb113_6 ns113 0 ni6 0 1.48480728128e-006 +Gb114_6 ns114 0 ni6 0 2.33181341696e-006 +Gb115_6 ns115 0 ni6 0 6.4067543767e-006 +Gb116_6 ns116 0 ni6 0 3.37194545577e-005 +Gb117_6 ns117 0 ni6 0 7.80107861365e-005 +Gb119_6 ns119 0 ni6 0 7.93160966378e-005 +Gb121_6 ns121 0 ni6 0 9.63748396341e-005 +Gb123_6 ns123 0 ni6 0 0.000214076094716 +Gb125_6 ns125 0 ni6 0 0.000309430436033 +Gb127_6 ns127 0 ni6 0 0.000341919002989 +Gb129_6 ns129 0 ni6 0 0.000340426093006 +Gb131_6 ns131 0 ni6 0 0.00082039899598 + +Gc1_1 0 n2 ns1 0 0.00136151454275 +Gc1_2 0 n2 ns2 0 0.00021310991863 +Gc1_3 0 n2 ns3 0 0.00293786143288 +Gc1_4 0 n2 ns4 0 0.00983327103905 +Gc1_5 0 n2 ns5 0 0.000445228542591 +Gc1_6 0 n2 ns6 0 0.000128765373068 +Gc1_7 0 n2 ns7 0 0.0012413814731 +Gc1_8 0 n2 ns8 0 -0.000237016026421 +Gc1_9 0 n2 ns9 0 0.00188254643189 +Gc1_10 0 n2 ns10 0 -0.000206173800501 +Gc1_11 0 n2 ns11 0 0.00166662950339 +Gc1_12 0 n2 ns12 0 -0.000304150960101 +Gc1_13 0 n2 ns13 0 1.1430461052e-006 +Gc1_14 0 n2 ns14 0 -5.58995801822e-007 +Gc1_15 0 n2 ns15 0 0.00102984979196 +Gc1_16 0 n2 ns16 0 -0.00280170873839 +Gc1_17 0 n2 ns17 0 0.00222487208654 +Gc1_18 0 n2 ns18 0 0.00170847496339 +Gc1_19 0 n2 ns19 0 -0.000329021446256 +Gc1_20 0 n2 ns20 0 -0.000584097949661 +Gc1_21 0 n2 ns21 0 0.00749369757613 +Gc1_22 0 n2 ns22 0 0.0363262979065 +Gc1_23 0 n2 ns23 0 0.001206246524 +Gc1_24 0 n2 ns24 0 -9.94796729568e-005 +Gc1_25 0 n2 ns25 0 -0.001593615502 +Gc1_26 0 n2 ns26 0 -0.0048190535513 +Gc1_27 0 n2 ns27 0 -0.000185627508113 +Gc1_28 0 n2 ns28 0 -0.00011449640769 +Gc1_29 0 n2 ns29 0 0.000177124470451 +Gc1_30 0 n2 ns30 0 -0.000599257824418 +Gc1_31 0 n2 ns31 0 -0.00164544922546 +Gc1_32 0 n2 ns32 0 0.000789864303563 +Gc1_33 0 n2 ns33 0 0.00157365215446 +Gc1_34 0 n2 ns34 0 -0.000416644004401 +Gc1_35 0 n2 ns35 0 1.69242901978e-007 +Gc1_36 0 n2 ns36 0 -6.28377777321e-007 +Gc1_37 0 n2 ns37 0 0.00018706246352 +Gc1_38 0 n2 ns38 0 -0.000163988704553 +Gc1_39 0 n2 ns39 0 -0.000347547822519 +Gc1_40 0 n2 ns40 0 2.20248566287e-005 +Gc1_41 0 n2 ns41 0 -0.000146646544536 +Gc1_42 0 n2 ns42 0 0.000255415777052 +Gc1_43 0 n2 ns43 0 -0.00198984674006 +Gc1_44 0 n2 ns44 0 -0.00193271395256 +Gc1_45 0 n2 ns45 0 0.00119570654914 +Gc1_46 0 n2 ns46 0 -0.000110284729884 +Gc1_47 0 n2 ns47 0 -0.00134057216283 +Gc1_48 0 n2 ns48 0 -0.00502080204166 +Gc1_49 0 n2 ns49 0 -0.000248273609702 +Gc1_50 0 n2 ns50 0 -8.54132327455e-005 +Gc1_51 0 n2 ns51 0 -0.00119913807126 +Gc1_52 0 n2 ns52 0 0.000836707848466 +Gc1_53 0 n2 ns53 0 -0.000351437881008 +Gc1_54 0 n2 ns54 0 -0.000725728401285 +Gc1_55 0 n2 ns55 0 0.0016461640846 +Gc1_56 0 n2 ns56 0 -0.000364662534373 +Gc1_57 0 n2 ns57 0 2.49040962789e-007 +Gc1_58 0 n2 ns58 0 -5.98354423593e-007 +Gc1_59 0 n2 ns59 0 0.000298543995453 +Gc1_60 0 n2 ns60 0 -0.000716002300227 +Gc1_61 0 n2 ns61 0 -0.00100728879429 +Gc1_62 0 n2 ns62 0 0.000106064372779 +Gc1_63 0 n2 ns63 0 0.000268606222257 +Gc1_64 0 n2 ns64 0 0.000573913809684 +Gc1_65 0 n2 ns65 0 -0.00181376340664 +Gc1_66 0 n2 ns66 0 -0.00162990822904 +Gc1_67 0 n2 ns67 0 -0.00131608672766 +Gc1_68 0 n2 ns68 0 -0.000196560590296 +Gc1_69 0 n2 ns69 0 -0.00294045827353 +Gc1_70 0 n2 ns70 0 -0.00983993987592 +Gc1_71 0 n2 ns71 0 -0.000426373427093 +Gc1_72 0 n2 ns72 0 -0.000233639783046 +Gc1_73 0 n2 ns73 0 -0.000926858219527 +Gc1_74 0 n2 ns74 0 0.000176371542988 +Gc1_75 0 n2 ns75 0 -0.00194091152064 +Gc1_76 0 n2 ns76 0 0.000289780958297 +Gc1_77 0 n2 ns77 0 -0.0016708691962 +Gc1_78 0 n2 ns78 0 0.000291147854331 +Gc1_79 0 n2 ns79 0 6.56628369761e-007 +Gc1_80 0 n2 ns80 0 -3.38372450145e-007 +Gc1_81 0 n2 ns81 0 -0.000898765880506 +Gc1_82 0 n2 ns82 0 0.00234726949112 +Gc1_83 0 n2 ns83 0 -0.00184248524398 +Gc1_84 0 n2 ns84 0 -0.000672124531807 +Gc1_85 0 n2 ns85 0 0.000272222127562 +Gc1_86 0 n2 ns86 0 0.000311447292426 +Gc1_87 0 n2 ns87 0 -0.012556091731 +Gc1_88 0 n2 ns88 0 -0.0149437953044 +Gc1_89 0 n2 ns89 0 -0.00122850152721 +Gc1_90 0 n2 ns90 0 9.61199982069e-005 +Gc1_91 0 n2 ns91 0 0.00160184115821 +Gc1_92 0 n2 ns92 0 0.00480067260639 +Gc1_93 0 n2 ns93 0 0.000193544486887 +Gc1_94 0 n2 ns94 0 9.43625432148e-005 +Gc1_95 0 n2 ns95 0 -0.00015630222669 +Gc1_96 0 n2 ns96 0 0.000483811634118 +Gc1_97 0 n2 ns97 0 0.00144694154489 +Gc1_98 0 n2 ns98 0 -0.000650176886967 +Gc1_99 0 n2 ns99 0 -0.00157045949222 +Gc1_100 0 n2 ns100 0 0.000413016913993 +Gc1_101 0 n2 ns101 0 -3.8418795119e-008 +Gc1_102 0 n2 ns102 0 -6.48477058241e-007 +Gc1_103 0 n2 ns103 0 -0.00026577842534 +Gc1_104 0 n2 ns104 0 0.000340724189751 +Gc1_105 0 n2 ns105 0 0.000198509838454 +Gc1_106 0 n2 ns106 0 -0.000552590770958 +Gc1_107 0 n2 ns107 0 0.000207492699652 +Gc1_108 0 n2 ns108 0 -0.000242797895288 +Gc1_109 0 n2 ns109 0 -0.00245301585881 +Gc1_110 0 n2 ns110 0 -0.002063365143 +Gc1_111 0 n2 ns111 0 -0.00122577071298 +Gc1_112 0 n2 ns112 0 0.000107368843756 +Gc1_113 0 n2 ns113 0 0.00134798020809 +Gc1_114 0 n2 ns114 0 0.00500470105204 +Gc1_115 0 n2 ns115 0 0.000254804262632 +Gc1_116 0 n2 ns116 0 7.04763478523e-005 +Gc1_117 0 n2 ns117 0 0.00114990691461 +Gc1_118 0 n2 ns118 0 -0.000843452406075 +Gc1_119 0 n2 ns119 0 0.00033393214887 +Gc1_120 0 n2 ns120 0 0.000754417706771 +Gc1_121 0 n2 ns121 0 -0.00168641554475 +Gc1_122 0 n2 ns122 0 0.00036491520335 +Gc1_123 0 n2 ns123 0 9.57968847436e-008 +Gc1_124 0 n2 ns124 0 -6.21626655406e-007 +Gc1_125 0 n2 ns125 0 -0.000343847194267 +Gc1_126 0 n2 ns126 0 0.000809097292252 +Gc1_127 0 n2 ns127 0 0.000610322485658 +Gc1_128 0 n2 ns128 0 -0.000692497759129 +Gc1_129 0 n2 ns129 0 -0.000105653650503 +Gc1_130 0 n2 ns130 0 -0.00039136195734 +Gc1_131 0 n2 ns131 0 -0.0028632895729 +Gc1_132 0 n2 ns132 0 -0.00259026394122 +Gd1_1 0 n2 ni1 0 0.00275610836046 +Gd1_2 0 n2 ni2 0 -0.000561768660119 +Gd1_3 0 n2 ni3 0 -0.000545175077844 +Gd1_4 0 n2 ni4 0 -0.0050666672563 +Gd1_5 0 n2 ni5 0 -0.000475853812933 +Gd1_6 0 n2 ni6 0 -0.000609509293826 +Gc2_1 0 n4 ns1 0 0.00120110073425 +Gc2_2 0 n4 ns2 0 -0.000100837151108 +Gc2_3 0 n4 ns3 0 -0.00159120896306 +Gc2_4 0 n4 ns4 0 -0.00482068826176 +Gc2_5 0 n4 ns5 0 -0.000185242964505 +Gc2_6 0 n4 ns6 0 -0.000114047247608 +Gc2_7 0 n4 ns7 0 0.000178184599371 +Gc2_8 0 n4 ns8 0 -0.000596934151861 +Gc2_9 0 n4 ns9 0 -0.00164627262071 +Gc2_10 0 n4 ns10 0 0.000786925417911 +Gc2_11 0 n4 ns11 0 0.00157357901887 +Gc2_12 0 n4 ns12 0 -0.000416236423255 +Gc2_13 0 n4 ns13 0 1.60966358142e-007 +Gc2_14 0 n4 ns14 0 -6.10507507386e-007 +Gc2_15 0 n4 ns15 0 0.000186220944162 +Gc2_16 0 n4 ns16 0 -0.000164209420732 +Gc2_17 0 n4 ns17 0 -0.000349278358166 +Gc2_18 0 n4 ns18 0 2.48898830054e-005 +Gc2_19 0 n4 ns19 0 -0.000146691024865 +Gc2_20 0 n4 ns20 0 0.000253313647416 +Gc2_21 0 n4 ns21 0 -0.00197322236068 +Gc2_22 0 n4 ns22 0 -0.00192305098036 +Gc2_23 0 n4 ns23 0 0.00134255813394 +Gc2_24 0 n4 ns24 0 0.000192248206433 +Gc2_25 0 n4 ns25 0 0.00289317002467 +Gc2_26 0 n4 ns26 0 0.00990431222459 +Gc2_27 0 n4 ns27 0 0.000423573695127 +Gc2_28 0 n4 ns28 0 0.000133239173907 +Gc2_29 0 n4 ns29 0 9.99255144932e-005 +Gc2_30 0 n4 ns30 0 0.000905082272527 +Gc2_31 0 n4 ns31 0 0.00274422039223 +Gc2_32 0 n4 ns32 0 -0.00108612573201 +Gc2_33 0 n4 ns33 0 0.00149537347025 +Gc2_34 0 n4 ns34 0 -0.000497842235984 +Gc2_35 0 n4 ns35 0 2.66967271037e-007 +Gc2_36 0 n4 ns36 0 -5.09525165238e-007 +Gc2_37 0 n4 ns37 0 5.78118434944e-005 +Gc2_38 0 n4 ns38 0 2.26472120235e-005 +Gc2_39 0 n4 ns39 0 0.00129187633115 +Gc2_40 0 n4 ns40 0 -0.000744835750745 +Gc2_41 0 n4 ns41 0 0.000605612922532 +Gc2_42 0 n4 ns42 0 -0.000982259817169 +Gc2_43 0 n4 ns43 0 0.0132636962346 +Gc2_44 0 n4 ns44 0 0.0400036073686 +Gc2_45 0 n4 ns45 0 0.00118581374296 +Gc2_46 0 n4 ns46 0 -9.78591089587e-005 +Gc2_47 0 n4 ns47 0 -0.00123741609666 +Gc2_48 0 n4 ns48 0 -0.0051476048825 +Gc2_49 0 n4 ns49 0 -0.000228185996911 +Gc2_50 0 n4 ns50 0 -9.0791064585e-005 +Gc2_51 0 n4 ns51 0 -0.000168675101202 +Gc2_52 0 n4 ns52 0 -0.000408069922966 +Gc2_53 0 n4 ns53 0 -0.00133345522345 +Gc2_54 0 n4 ns54 0 0.000648228955543 +Gc2_55 0 n4 ns55 0 0.00156776977468 +Gc2_56 0 n4 ns56 0 -0.000470777131257 +Gc2_57 0 n4 ns57 0 2.33648325778e-007 +Gc2_58 0 n4 ns58 0 -6.32727985723e-007 +Gc2_59 0 n4 ns59 0 8.2196650033e-005 +Gc2_60 0 n4 ns60 0 -1.96685097418e-005 +Gc2_61 0 n4 ns61 0 -8.1060425284e-005 +Gc2_62 0 n4 ns62 0 0.000153136394116 +Gc2_63 0 n4 ns63 0 -0.000353911408312 +Gc2_64 0 n4 ns64 0 2.33155563324e-005 +Gc2_65 0 n4 ns65 0 -0.00178043779626 +Gc2_66 0 n4 ns66 0 -0.00179786573514 +Gc2_67 0 n4 ns67 0 -0.00120262016875 +Gc2_68 0 n4 ns68 0 9.44160693478e-005 +Gc2_69 0 n4 ns69 0 0.00160858280957 +Gc2_70 0 n4 ns70 0 0.00479916083071 +Gc2_71 0 n4 ns71 0 0.000194837979244 +Gc2_72 0 n4 ns72 0 9.28815698221e-005 +Gc2_73 0 n4 ns73 0 -0.000112354477639 +Gc2_74 0 n4 ns74 0 0.000497541206529 +Gc2_75 0 n4 ns75 0 0.00149432000841 +Gc2_76 0 n4 ns76 0 -0.000671068138374 +Gc2_77 0 n4 ns77 0 -0.00157080578064 +Gc2_78 0 n4 ns78 0 0.000420080077822 +Gc2_79 0 n4 ns79 0 3.24527406056e-008 +Gc2_80 0 n4 ns80 0 -5.65032822481e-007 +Gc2_81 0 n4 ns81 0 -0.000168643008921 +Gc2_82 0 n4 ns82 0 0.000150124327899 +Gc2_83 0 n4 ns83 0 9.29288836507e-005 +Gc2_84 0 n4 ns84 0 -0.000377122979344 +Gc2_85 0 n4 ns85 0 0.00016420421659 +Gc2_86 0 n4 ns86 0 -0.000119762908414 +Gc2_87 0 n4 ns87 0 -0.0026115360033 +Gc2_88 0 n4 ns88 0 -0.00232824493389 +Gc2_89 0 n4 ns89 0 -0.00129946401442 +Gc2_90 0 n4 ns90 0 -0.000191176387287 +Gc2_91 0 n4 ns91 0 -0.00286976709368 +Gc2_92 0 n4 ns92 0 -0.00992035281151 +Gc2_93 0 n4 ns93 0 -0.000415430641696 +Gc2_94 0 n4 ns94 0 -0.00019001471061 +Gc2_95 0 n4 ns95 0 -5.82225655402e-005 +Gc2_96 0 n4 ns96 0 -0.000899718011472 +Gc2_97 0 n4 ns97 0 -0.00252602647122 +Gc2_98 0 n4 ns98 0 0.00109148127748 +Gc2_99 0 n4 ns99 0 -0.00149187111739 +Gc2_100 0 n4 ns100 0 0.000493128151651 +Gc2_101 0 n4 ns101 0 1.24095392067e-007 +Gc2_102 0 n4 ns102 0 -5.46945098782e-007 +Gc2_103 0 n4 ns103 0 -0.000188027575161 +Gc2_104 0 n4 ns104 0 -2.56284726073e-005 +Gc2_105 0 n4 ns105 0 -0.00067241881903 +Gc2_106 0 n4 ns106 0 0.00116073552996 +Gc2_107 0 n4 ns107 0 -0.000487231116617 +Gc2_108 0 n4 ns108 0 0.000725716127433 +Gc2_109 0 n4 ns109 0 -0.0183474768605 +Gc2_110 0 n4 ns110 0 -0.0183463168882 +Gc2_111 0 n4 ns111 0 -0.00121411087797 +Gc2_112 0 n4 ns112 0 9.69286243621e-005 +Gc2_113 0 n4 ns113 0 0.00124482177399 +Gc2_114 0 n4 ns114 0 0.0051270178007 +Gc2_115 0 n4 ns115 0 0.000240413110982 +Gc2_116 0 n4 ns116 0 6.25523997799e-005 +Gc2_117 0 n4 ns117 0 0.000238097233572 +Gc2_118 0 n4 ns118 0 0.000290956429377 +Gc2_119 0 n4 ns119 0 0.0011262121198 +Gc2_120 0 n4 ns120 0 -0.000499380267206 +Gc2_121 0 n4 ns121 0 -0.00161184006739 +Gc2_122 0 n4 ns122 0 0.000468313673093 +Gc2_123 0 n4 ns123 0 2.29074350667e-007 +Gc2_124 0 n4 ns124 0 -5.98466567336e-007 +Gc2_125 0 n4 ns125 0 -8.36089536602e-005 +Gc2_126 0 n4 ns126 0 3.80271862582e-006 +Gc2_127 0 n4 ns127 0 -0.000189778461791 +Gc2_128 0 n4 ns128 0 -0.00044540407815 +Gc2_129 0 n4 ns129 0 0.0003744626351 +Gc2_130 0 n4 ns130 0 -2.1800394017e-005 +Gc2_131 0 n4 ns131 0 -0.00305112315683 +Gc2_132 0 n4 ns132 0 -0.00242492405067 +Gd2_1 0 n4 ni1 0 -0.000553155470508 +Gd2_2 0 n4 ni2 0 0.00523660699477 +Gd2_3 0 n4 ni3 0 -0.000468910361878 +Gd2_4 0 n4 ni4 0 -0.000533659112607 +Gd2_5 0 n4 ni5 0 -0.0075455576023 +Gd2_6 0 n4 ni6 0 -0.000850950969877 +Gc3_1 0 n6 ns1 0 0.00119561606104 +Gc3_2 0 n6 ns2 0 -0.000111288977743 +Gc3_3 0 n6 ns3 0 -0.00133927681218 +Gc3_4 0 n6 ns4 0 -0.00502082783949 +Gc3_5 0 n6 ns5 0 -0.000248259290084 +Gc3_6 0 n6 ns6 0 -8.48546979818e-005 +Gc3_7 0 n6 ns7 0 -0.0011978101672 +Gc3_8 0 n6 ns8 0 0.000836287792984 +Gc3_9 0 n6 ns9 0 -0.000351966814516 +Gc3_10 0 n6 ns10 0 -0.000725587252776 +Gc3_11 0 n6 ns11 0 0.00164545071853 +Gc3_12 0 n6 ns12 0 -0.000364321181428 +Gc3_13 0 n6 ns13 0 2.40008650778e-007 +Gc3_14 0 n6 ns14 0 -5.9229368508e-007 +Gc3_15 0 n6 ns15 0 0.000297949819644 +Gc3_16 0 n6 ns16 0 -0.000714568613735 +Gc3_17 0 n6 ns17 0 -0.0010036332538 +Gc3_18 0 n6 ns18 0 0.000106987675186 +Gc3_19 0 n6 ns19 0 0.000266127785398 +Gc3_20 0 n6 ns20 0 0.000573696335122 +Gc3_21 0 n6 ns21 0 -0.00179988257049 +Gc3_22 0 n6 ns22 0 -0.00162605364416 +Gc3_23 0 n6 ns23 0 0.00118254574346 +Gc3_24 0 n6 ns24 0 -9.9875334791e-005 +Gc3_25 0 n6 ns25 0 -0.00123412282499 +Gc3_26 0 n6 ns26 0 -0.00514980991881 +Gc3_27 0 n6 ns27 0 -0.000227717777853 +Gc3_28 0 n6 ns28 0 -9.0485832388e-005 +Gc3_29 0 n6 ns29 0 -0.000168301759517 +Gc3_30 0 n6 ns30 0 -0.000407355393016 +Gc3_31 0 n6 ns31 0 -0.00133297631265 +Gc3_32 0 n6 ns32 0 0.000647268801789 +Gc3_33 0 n6 ns33 0 0.00156691665419 +Gc3_34 0 n6 ns34 0 -0.000470404425495 +Gc3_35 0 n6 ns35 0 2.43536471495e-007 +Gc3_36 0 n6 ns36 0 -6.40622135772e-007 +Gc3_37 0 n6 ns37 0 8.06098452792e-005 +Gc3_38 0 n6 ns38 0 -2.03658182156e-005 +Gc3_39 0 n6 ns39 0 -8.04248017749e-005 +Gc3_40 0 n6 ns40 0 0.000159353424564 +Gc3_41 0 n6 ns41 0 -0.000354750513306 +Gc3_42 0 n6 ns42 0 2.0895577406e-005 +Gc3_43 0 n6 ns43 0 -0.00176387960896 +Gc3_44 0 n6 ns44 0 -0.00179290236708 +Gc3_45 0 n6 ns45 0 0.00130138531 +Gc3_46 0 n6 ns46 0 0.000210629204639 +Gc3_47 0 n6 ns47 0 0.00258742626062 +Gc3_48 0 n6 ns48 0 0.0101646715029 +Gc3_49 0 n6 ns49 0 0.000492150525024 +Gc3_50 0 n6 ns50 0 0.000120484591329 +Gc3_51 0 n6 ns51 0 0.00153400464885 +Gc3_52 0 n6 ns52 0 -0.000366429561098 +Gc3_53 0 n6 ns53 0 0.00149386912975 +Gc3_54 0 n6 ns54 0 -2.08934889173e-005 +Gc3_55 0 n6 ns55 0 0.0016572466325 +Gc3_56 0 n6 ns56 0 -0.000426676409279 +Gc3_57 0 n6 ns57 0 6.36958027117e-007 +Gc3_58 0 n6 ns58 0 -7.63024388492e-007 +Gc3_59 0 n6 ns59 0 0.000419539822626 +Gc3_60 0 n6 ns60 0 -1.90253790644e-005 +Gc3_61 0 n6 ns61 0 0.00346475019855 +Gc3_62 0 n6 ns62 0 -0.000710430019845 +Gc3_63 0 n6 ns63 0 -0.000796495207019 +Gc3_64 0 n6 ns64 0 -0.00123510323285 +Gc3_65 0 n6 ns65 0 0.0120685674185 +Gc3_66 0 n6 ns66 0 0.0400307102472 +Gc3_67 0 n6 ns67 0 -0.00119341605978 +Gc3_68 0 n6 ns68 0 0.000104772967942 +Gc3_69 0 n6 ns69 0 0.00135561517593 +Gc3_70 0 n6 ns70 0 0.00499946231575 +Gc3_71 0 n6 ns71 0 0.000257238231908 +Gc3_72 0 n6 ns72 0 6.63181420409e-005 +Gc3_73 0 n6 ns73 0 0.00112285317005 +Gc3_74 0 n6 ns74 0 -0.00084385666601 +Gc3_75 0 n6 ns75 0 0.00027781146374 +Gc3_76 0 n6 ns76 0 0.000752055065949 +Gc3_77 0 n6 ns77 0 -0.00164366922328 +Gc3_78 0 n6 ns78 0 0.000370477434637 +Gc3_79 0 n6 ns79 0 1.42812278268e-007 +Gc3_80 0 n6 ns80 0 -6.12471921552e-007 +Gc3_81 0 n6 ns81 0 -0.00025375165999 +Gc3_82 0 n6 ns82 0 0.000621371217262 +Gc3_83 0 n6 ns83 0 0.000426664711405 +Gc3_84 0 n6 ns84 0 -0.000628214613662 +Gc3_85 0 n6 ns85 0 -3.40969558413e-005 +Gc3_86 0 n6 ns86 0 -0.000339050643256 +Gc3_87 0 n6 ns87 0 -0.003233766121 +Gc3_88 0 n6 ns88 0 -0.00267874154409 +Gc3_89 0 n6 ns89 0 -0.00118590042891 +Gc3_90 0 n6 ns90 0 9.95519272812e-005 +Gc3_91 0 n6 ns91 0 0.00124081622779 +Gc3_92 0 n6 ns92 0 0.00513831248646 +Gc3_93 0 n6 ns93 0 0.00023621539559 +Gc3_94 0 n6 ns94 0 6.57749442565e-005 +Gc3_95 0 n6 ns95 0 0.000259833839213 +Gc3_96 0 n6 ns96 0 0.000283677581561 +Gc3_97 0 n6 ns97 0 0.00117839151418 +Gc3_98 0 n6 ns98 0 -0.000491787261313 +Gc3_99 0 n6 ns99 0 -0.00156795454726 +Gc3_100 0 n6 ns100 0 0.000464010999043 +Gc3_101 0 n6 ns101 0 2.68342927385e-007 +Gc3_102 0 n6 ns102 0 -6.06152294316e-007 +Gc3_103 0 n6 ns103 0 -0.000145535573046 +Gc3_104 0 n6 ns104 0 3.5624943064e-005 +Gc3_105 0 n6 ns105 0 -0.000256501398139 +Gc3_106 0 n6 ns106 0 -0.000402330475774 +Gc3_107 0 n6 ns107 0 0.000423306675631 +Gc3_108 0 n6 ns108 0 5.33587655339e-005 +Gc3_109 0 n6 ns109 0 -0.00283490317443 +Gc3_110 0 n6 ns110 0 -0.00253405160882 +Gc3_111 0 n6 ns111 0 -0.0013031294732 +Gc3_112 0 n6 ns112 0 -0.000201617822244 +Gc3_113 0 n6 ns113 0 -0.00257496594041 +Gc3_114 0 n6 ns114 0 -0.0101700808193 +Gc3_115 0 n6 ns115 0 -0.000482543650688 +Gc3_116 0 n6 ns116 0 -0.000186431812082 +Gc3_117 0 n6 ns117 0 -0.00137242500608 +Gc3_118 0 n6 ns118 0 0.000270790609943 +Gc3_119 0 n6 ns119 0 -0.00141935535758 +Gc3_120 0 n6 ns120 0 0.000106886253539 +Gc3_121 0 n6 ns121 0 -0.00169763057841 +Gc3_122 0 n6 ns122 0 0.000425064146302 +Gc3_123 0 n6 ns123 0 2.58693594979e-007 +Gc3_124 0 n6 ns124 0 -4.38885977534e-007 +Gc3_125 0 n6 ns125 0 -0.000476510706345 +Gc3_126 0 n6 ns126 0 6.00707630538e-005 +Gc3_127 0 n6 ns127 0 -0.00239647347189 +Gc3_128 0 n6 ns128 0 0.00121658517462 +Gc3_129 0 n6 ns129 0 0.000578351796301 +Gc3_130 0 n6 ns130 0 0.000805309332848 +Gc3_131 0 n6 ns131 0 -0.016047414021 +Gc3_132 0 n6 ns132 0 -0.017256452982 +Gd3_1 0 n6 ni1 0 -0.000535496776968 +Gd3_2 0 n6 ni2 0 -0.000459288099628 +Gd3_3 0 n6 ni3 0 0.00492344276583 +Gd3_4 0 n6 ni4 0 -0.000877516167884 +Gd3_5 0 n6 ni5 0 -0.000689549509561 +Gd3_6 0 n6 ni6 0 -0.0068896207705 +Gc4_1 0 n8 ns1 0 -0.00131556183464 +Gc4_2 0 n8 ns2 0 -0.000195414549614 +Gc4_3 0 n8 ns3 0 -0.00293948379147 +Gc4_4 0 n8 ns4 0 -0.00984320355725 +Gc4_5 0 n8 ns5 0 -0.000426268829352 +Gc4_6 0 n8 ns6 0 -0.000228153380725 +Gc4_7 0 n8 ns7 0 -0.000937563330876 +Gc4_8 0 n8 ns8 0 0.000169273719303 +Gc4_9 0 n8 ns9 0 -0.00192399437572 +Gc4_10 0 n8 ns10 0 0.00029291425312 +Gc4_11 0 n8 ns11 0 -0.00166793321797 +Gc4_12 0 n8 ns12 0 0.00029130362683 +Gc4_13 0 n8 ns13 0 6.40555787678e-007 +Gc4_14 0 n8 ns14 0 -3.06554385864e-007 +Gc4_15 0 n8 ns15 0 -0.000907060939644 +Gc4_16 0 n8 ns16 0 0.00233621194694 +Gc4_17 0 n8 ns17 0 -0.00186297528962 +Gc4_18 0 n8 ns18 0 -0.000610678092009 +Gc4_19 0 n8 ns19 0 0.000264150071983 +Gc4_20 0 n8 ns20 0 0.000288181266456 +Gc4_21 0 n8 ns21 0 -0.0122342061733 +Gc4_22 0 n8 ns22 0 -0.0148007116847 +Gc4_23 0 n8 ns23 0 -0.00120610441457 +Gc4_24 0 n8 ns24 0 9.25720254658e-005 +Gc4_25 0 n8 ns25 0 0.00161047876373 +Gc4_26 0 n8 ns26 0 0.00479872151084 +Gc4_27 0 n8 ns27 0 0.000195552027481 +Gc4_28 0 n8 ns28 0 9.19877616036e-005 +Gc4_29 0 n8 ns29 0 -0.0001133441766 +Gc4_30 0 n8 ns30 0 0.000499061014479 +Gc4_31 0 n8 ns31 0 0.00149414916003 +Gc4_32 0 n8 ns32 0 -0.000672432286586 +Gc4_33 0 n8 ns33 0 -0.00156951215754 +Gc4_34 0 n8 ns34 0 0.000419435614437 +Gc4_35 0 n8 ns35 0 2.23450603948e-008 +Gc4_36 0 n8 ns36 0 -5.73921399317e-007 +Gc4_37 0 n8 ns37 0 -0.000167625216399 +Gc4_38 0 n8 ns38 0 0.000151731326201 +Gc4_39 0 n8 ns39 0 9.39861457527e-005 +Gc4_40 0 n8 ns40 0 -0.000382119853556 +Gc4_41 0 n8 ns41 0 0.000163241708358 +Gc4_42 0 n8 ns42 0 -0.000118287757811 +Gc4_43 0 n8 ns43 0 -0.00261660210697 +Gc4_44 0 n8 ns44 0 -0.00232691758397 +Gc4_45 0 n8 ns45 0 -0.00119324707242 +Gc4_46 0 n8 ns46 0 0.000103850139693 +Gc4_47 0 n8 ns47 0 0.00135609401157 +Gc4_48 0 n8 ns48 0 0.00500038019303 +Gc4_49 0 n8 ns49 0 0.000258170370314 +Gc4_50 0 n8 ns50 0 6.43880185243e-005 +Gc4_51 0 n8 ns51 0 0.00112014996172 +Gc4_52 0 n8 ns52 0 -0.000839913711214 +Gc4_53 0 n8 ns53 0 0.00027867466986 +Gc4_54 0 n8 ns54 0 0.000748302156182 +Gc4_55 0 n8 ns55 0 -0.00164175302125 +Gc4_56 0 n8 ns56 0 0.000369617519839 +Gc4_57 0 n8 ns57 0 1.34997061384e-007 +Gc4_58 0 n8 ns58 0 -6.13181994019e-007 +Gc4_59 0 n8 ns59 0 -0.0002526579508 +Gc4_60 0 n8 ns60 0 0.000623608642307 +Gc4_61 0 n8 ns61 0 0.000431749338308 +Gc4_62 0 n8 ns62 0 -0.000639545405813 +Gc4_63 0 n8 ns63 0 -3.41726519138e-005 +Gc4_64 0 n8 ns64 0 -0.00033541392989 +Gc4_65 0 n8 ns65 0 -0.00327165786928 +Gc4_66 0 n8 ns66 0 -0.00269038732762 +Gc4_67 0 n8 ns67 0 0.00125913363115 +Gc4_68 0 n8 ns68 0 0.000191921346486 +Gc4_69 0 n8 ns69 0 0.00298876481626 +Gc4_70 0 n8 ns70 0 0.0097661831374 +Gc4_71 0 n8 ns71 0 0.000470732791466 +Gc4_72 0 n8 ns72 0 8.93074610219e-005 +Gc4_73 0 n8 ns73 0 0.0011055480693 +Gc4_74 0 n8 ns74 0 -0.000215142853608 +Gc4_75 0 n8 ns75 0 0.00150953384482 +Gc4_76 0 n8 ns76 0 -0.000173770150452 +Gc4_77 0 n8 ns77 0 0.00162606949063 +Gc4_78 0 n8 ns78 0 -0.000317623845578 +Gc4_79 0 n8 ns79 0 1.10824568667e-006 +Gc4_80 0 n8 ns80 0 -3.74477934361e-007 +Gc4_81 0 n8 ns81 0 0.000669598756023 +Gc4_82 0 n8 ns82 0 -0.00225260002546 +Gc4_83 0 n8 ns83 0 0.00116637072408 +Gc4_84 0 n8 ns84 0 0.00121623854412 +Gc4_85 0 n8 ns85 0 -0.000225343458087 +Gc4_86 0 n8 ns86 0 -0.000364923347449 +Gc4_87 0 n8 ns87 0 0.010643176516 +Gc4_88 0 n8 ns88 0 0.0391476676184 +Gc4_89 0 n8 ns89 0 0.00122685874797 +Gc4_90 0 n8 ns90 0 -9.06968191491e-005 +Gc4_91 0 n8 ns91 0 -0.0016119488052 +Gc4_92 0 n8 ns92 0 -0.00479130907197 +Gc4_93 0 n8 ns93 0 -0.000195832230592 +Gc4_94 0 n8 ns94 0 -9.68277111435e-005 +Gc4_95 0 n8 ns95 0 0.000152875474271 +Gc4_96 0 n8 ns96 0 -0.000508990974907 +Gc4_97 0 n8 ns97 0 -0.00135076151977 +Gc4_98 0 n8 ns98 0 0.000679600873381 +Gc4_99 0 n8 ns99 0 0.00154567409832 +Gc4_100 0 n8 ns100 0 -0.000411206292388 +Gc4_101 0 n8 ns101 0 8.74804140902e-008 +Gc4_102 0 n8 ns102 0 -5.86213960742e-007 +Gc4_103 0 n8 ns103 0 0.000213439057703 +Gc4_104 0 n8 ns104 0 -0.000246558221632 +Gc4_105 0 n8 ns105 0 0.000144250733588 +Gc4_106 0 n8 ns106 0 6.53955387355e-005 +Gc4_107 0 n8 ns107 0 -7.93099225745e-005 +Gc4_108 0 n8 ns108 0 0.000151424897142 +Gc4_109 0 n8 ns109 0 -0.00316501060387 +Gc4_110 0 n8 ns110 0 -0.00303156099813 +Gc4_111 0 n8 ns111 0 0.00121838123172 +Gc4_112 0 n8 ns112 0 -0.00010242814838 +Gc4_113 0 n8 ns113 0 -0.00135620829534 +Gc4_114 0 n8 ns114 0 -0.00499605249142 +Gc4_115 0 n8 ns115 0 -0.000256157550694 +Gc4_116 0 n8 ns116 0 -7.33035263941e-005 +Gc4_117 0 n8 ns117 0 -0.00102103134037 +Gc4_118 0 n8 ns118 0 0.000731391593073 +Gc4_119 0 n8 ns119 0 -0.000301197706314 +Gc4_120 0 n8 ns120 0 -0.000640121434101 +Gc4_121 0 n8 ns121 0 0.00166162693224 +Gc4_122 0 n8 ns122 0 -0.000365124393789 +Gc4_123 0 n8 ns123 0 1.22525078822e-007 +Gc4_124 0 n8 ns124 0 -5.29825774743e-007 +Gc4_125 0 n8 ns125 0 0.000297783806268 +Gc4_126 0 n8 ns126 0 -0.000644349107028 +Gc4_127 0 n8 ns127 0 -0.000146186249229 +Gc4_128 0 n8 ns128 0 0.000214007390921 +Gc4_129 0 n8 ns129 0 9.0851301072e-005 +Gc4_130 0 n8 ns130 0 0.00025966761389 +Gc4_131 0 n8 ns131 0 -0.00326410882741 +Gc4_132 0 n8 ns132 0 -0.00289191113795 +Gd4_1 0 n8 ni1 0 -0.0048821689805 +Gd4_2 0 n8 ni2 0 -0.000537336672415 +Gd4_3 0 n8 ni3 0 -0.000899724737781 +Gd4_4 0 n8 ni4 0 0.0029426354859 +Gd4_5 0 n8 ni5 0 -0.000526804401817 +Gd4_6 0 n8 ni6 0 -0.000600725571633 +Gc5_1 0 n10 ns1 0 -0.00122325090448 +Gc5_2 0 n10 ns2 0 9.48244158265e-005 +Gc5_3 0 n10 ns3 0 0.00160375541743 +Gc5_4 0 n10 ns4 0 0.00479958789823 +Gc5_5 0 n10 ns5 0 0.000193576985031 +Gc5_6 0 n10 ns6 0 9.35360978025e-005 +Gc5_7 0 n10 ns7 0 -0.00016081136315 +Gc5_8 0 n10 ns8 0 0.000485571886636 +Gc5_9 0 n10 ns9 0 0.00145002351013 +Gc5_10 0 n10 ns10 0 -0.000652154796441 +Gc5_11 0 n10 ns11 0 -0.0015684739409 +Gc5_12 0 n10 ns12 0 0.000412489976914 +Gc5_13 0 n10 ns13 0 -5.98649787773e-008 +Gc5_14 0 n10 ns14 0 -6.48012811175e-007 +Gc5_15 0 n10 ns15 0 -0.000265079589824 +Gc5_16 0 n10 ns16 0 0.000343033807173 +Gc5_17 0 n10 ns17 0 0.000203268577135 +Gc5_18 0 n10 ns18 0 -0.000562853583002 +Gc5_19 0 n10 ns19 0 0.000207182695691 +Gc5_20 0 n10 ns20 0 -0.000239833378157 +Gc5_21 0 n10 ns21 0 -0.00248027550195 +Gc5_22 0 n10 ns22 0 -0.00206927269499 +Gc5_23 0 n10 ns23 0 -0.00130405399399 +Gc5_24 0 n10 ns24 0 -0.0001867178742 +Gc5_25 0 n10 ns25 0 -0.00288088453833 +Gc5_26 0 n10 ns26 0 -0.00991038905333 +Gc5_27 0 n10 ns27 0 -0.000417837983223 +Gc5_28 0 n10 ns28 0 -0.000186550750147 +Gc5_29 0 n10 ns29 0 -6.39397599565e-005 +Gc5_30 0 n10 ns30 0 -0.000901473833 +Gc5_31 0 n10 ns31 0 -0.00251826131364 +Gc5_32 0 n10 ns32 0 0.00109139114808 +Gc5_33 0 n10 ns33 0 -0.0014903057318 +Gc5_34 0 n10 ns34 0 0.000493176265244 +Gc5_35 0 n10 ns35 0 1.12692213749e-007 +Gc5_36 0 n10 ns36 0 -5.46138183431e-007 +Gc5_37 0 n10 ns37 0 -0.000190987024066 +Gc5_38 0 n10 ns38 0 -2.73980883063e-005 +Gc5_39 0 n10 ns39 0 -0.000683830176257 +Gc5_40 0 n10 ns40 0 0.0011808415352 +Gc5_41 0 n10 ns41 0 -0.000490605518232 +Gc5_42 0 n10 ns42 0 0.000716324648197 +Gc5_43 0 n10 ns43 0 -0.0182012928403 +Gc5_44 0 n10 ns44 0 -0.0182757887766 +Gc5_45 0 n10 ns45 0 -0.00118805526913 +Gc5_46 0 n10 ns46 0 9.63255506912e-005 +Gc5_47 0 n10 ns47 0 0.00124578426061 +Gc5_48 0 n10 ns48 0 0.0051347677405 +Gc5_49 0 n10 ns49 0 0.000238258354735 +Gc5_50 0 n10 ns50 0 6.32978174932e-005 +Gc5_51 0 n10 ns51 0 0.000259766525402 +Gc5_52 0 n10 ns52 0 0.000287372718402 +Gc5_53 0 n10 ns53 0 0.00117599557682 +Gc5_54 0 n10 ns54 0 -0.000494856084749 +Gc5_55 0 n10 ns55 0 -0.00156580161335 +Gc5_56 0 n10 ns56 0 0.000462591988958 +Gc5_57 0 n10 ns57 0 2.52286911348e-007 +Gc5_58 0 n10 ns58 0 -5.91866727289e-007 +Gc5_59 0 n10 ns59 0 -0.000144785555757 +Gc5_60 0 n10 ns60 0 3.63418720986e-005 +Gc5_61 0 n10 ns61 0 -0.000257554434889 +Gc5_62 0 n10 ns62 0 -0.000405868296788 +Gc5_63 0 n10 ns63 0 0.000423484511973 +Gc5_64 0 n10 ns64 0 5.36762534578e-005 +Gc5_65 0 n10 ns65 0 -0.00284488287117 +Gc5_66 0 n10 ns66 0 -0.00253240818191 +Gc5_67 0 n10 ns67 0 0.00122177705501 +Gc5_68 0 n10 ns68 0 -9.00352916705e-005 +Gc5_69 0 n10 ns69 0 -0.00161359716116 +Gc5_70 0 n10 ns70 0 -0.00479005297275 +Gc5_71 0 n10 ns71 0 -0.000194986356787 +Gc5_72 0 n10 ns72 0 -9.76893696245e-005 +Gc5_73 0 n10 ns73 0 0.000154197094373 +Gc5_74 0 n10 ns74 0 -0.000510323996438 +Gc5_75 0 n10 ns75 0 -0.00135192048907 +Gc5_76 0 n10 ns76 0 0.000681529829119 +Gc5_77 0 n10 ns77 0 0.00154519431204 +Gc5_78 0 n10 ns78 0 -0.000411476956302 +Gc5_79 0 n10 ns79 0 8.99355826439e-008 +Gc5_80 0 n10 ns80 0 -5.86358571855e-007 +Gc5_81 0 n10 ns81 0 0.000211798027119 +Gc5_82 0 n10 ns82 0 -0.000246420484979 +Gc5_83 0 n10 ns83 0 0.000149861799797 +Gc5_84 0 n10 ns84 0 6.85483478354e-005 +Gc5_85 0 n10 ns85 0 -8.07256133866e-005 +Gc5_86 0 n10 ns86 0 0.000150717362788 +Gc5_87 0 n10 ns87 0 -0.00317321799778 +Gc5_88 0 n10 ns88 0 -0.00304213479418 +Gc5_89 0 n10 ns89 0 0.00130778022944 +Gc5_90 0 n10 ns90 0 0.0001839524892 +Gc5_91 0 n10 ns91 0 0.00290422521855 +Gc5_92 0 n10 ns92 0 0.00987249282377 +Gc5_93 0 n10 ns93 0 0.000436439741573 +Gc5_94 0 n10 ns94 0 0.000117089845986 +Gc5_95 0 n10 ns95 0 0.000128781839223 +Gc5_96 0 n10 ns96 0 0.000674484402111 +Gc5_97 0 n10 ns97 0 0.00225215110939 +Gc5_98 0 n10 ns98 0 -0.000837692419171 +Gc5_99 0 n10 ns99 0 0.00145453571548 +Gc5_100 0 n10 ns100 0 -0.000481812449306 +Gc5_101 0 n10 ns101 0 -6.3709138018e-008 +Gc5_102 0 n10 ns102 0 -5.88086169146e-007 +Gc5_103 0 n10 ns103 0 0.000142108036799 +Gc5_104 0 n10 ns104 0 -7.36424085798e-005 +Gc5_105 0 n10 ns105 0 8.38824590899e-005 +Gc5_106 0 n10 ns106 0 -0.000722638847721 +Gc5_107 0 n10 ns107 0 0.000338914092054 +Gc5_108 0 n10 ns108 0 -0.000716441406071 +Gc5_109 0 n10 ns109 0 0.0154686018807 +Gc5_110 0 n10 ns110 0 0.0428346391005 +Gc5_111 0 n10 ns111 0 0.0012168801475 +Gc5_112 0 n10 ns112 0 -9.65920517095e-005 +Gc5_113 0 n10 ns113 0 -0.00123930441227 +Gc5_114 0 n10 ns114 0 -0.00513754100973 +Gc5_115 0 n10 ns115 0 -0.000232202219384 +Gc5_116 0 n10 ns116 0 -8.05131366676e-005 +Gc5_117 0 n10 ns117 0 -0.000178970091388 +Gc5_118 0 n10 ns118 0 -0.000310443229679 +Gc5_119 0 n10 ns119 0 -0.00111274720309 +Gc5_120 0 n10 ns120 0 0.00052583787628 +Gc5_121 0 n10 ns121 0 0.00158030692808 +Gc5_122 0 n10 ns122 0 -0.000463946088028 +Gc5_123 0 n10 ns123 0 2.82195691845e-007 +Gc5_124 0 n10 ns124 0 -6.44212020762e-007 +Gc5_125 0 n10 ns125 0 0.000112962777519 +Gc5_126 0 n10 ns126 0 -5.49226570844e-005 +Gc5_127 0 n10 ns127 0 0.000408265343201 +Gc5_128 0 n10 ns128 0 4.41702498655e-005 +Gc5_129 0 n10 ns129 0 -0.000227317268814 +Gc5_130 0 n10 ns130 0 -4.90364367011e-005 +Gc5_131 0 n10 ns131 0 -0.0029912114192 +Gc5_132 0 n10 ns132 0 -0.00283969498433 +Gd5_1 0 n10 ni1 0 -0.000491802972385 +Gd5_2 0 n10 ni2 0 -0.00746280963934 +Gd5_3 0 n10 ni3 0 -0.000699012801598 +Gd5_4 0 n10 ni4 0 -0.000529092877995 +Gd5_5 0 n10 ni5 0 0.00457549561868 +Gd5_6 0 n10 ni6 0 -0.000441551528521 +Gc6_1 0 n12 ns1 0 -0.00121834350146 +Gc6_2 0 n12 ns2 0 0.000104212908633 +Gc6_3 0 n12 ns3 0 0.00135388601445 +Gc6_4 0 n12 ns4 0 0.0049993247655 +Gc6_5 0 n12 ns5 0 0.000256180985469 +Gc6_6 0 n12 ns6 0 6.85405245036e-005 +Gc6_7 0 n12 ns7 0 0.00114700122563 +Gc6_8 0 n12 ns8 0 -0.000838005520608 +Gc6_9 0 n12 ns9 0 0.000333951803991 +Gc6_10 0 n12 ns10 0 0.000748832391365 +Gc6_11 0 n12 ns11 0 -0.00168327402295 +Gc6_12 0 n12 ns12 0 0.000364198844932 +Gc6_13 0 n12 ns13 0 9.28146656844e-008 +Gc6_14 0 n12 ns14 0 -6.19948857779e-007 +Gc6_15 0 n12 ns15 0 -0.000341654798098 +Gc6_16 0 n12 ns16 0 0.000809366109928 +Gc6_17 0 n12 ns17 0 0.000610032604097 +Gc6_18 0 n12 ns18 0 -0.000703782510009 +Gc6_19 0 n12 ns19 0 -0.000103359509613 +Gc6_20 0 n12 ns20 0 -0.000387500750199 +Gc6_21 0 n12 ns21 0 -0.00290191955887 +Gc6_22 0 n12 ns22 0 -0.00259620537012 +Gc6_23 0 n12 ns23 0 -0.00120453929583 +Gc6_24 0 n12 ns24 0 9.42230914149e-005 +Gc6_25 0 n12 ns25 0 0.00125041877323 +Gc6_26 0 n12 ns26 0 0.00512176311824 +Gc6_27 0 n12 ns27 0 0.000241872099006 +Gc6_28 0 n12 ns28 0 6.0218713639e-005 +Gc6_29 0 n12 ns29 0 0.000236897474582 +Gc6_30 0 n12 ns30 0 0.000291793828409 +Gc6_31 0 n12 ns31 0 0.00112470406758 +Gc6_32 0 n12 ns32 0 -0.0004996678083 +Gc6_33 0 n12 ns33 0 -0.00160884708483 +Gc6_34 0 n12 ns34 0 0.000467139354344 +Gc6_35 0 n12 ns35 0 2.18569430302e-007 +Gc6_36 0 n12 ns36 0 -6.0370196666e-007 +Gc6_37 0 n12 ns37 0 -8.24712336456e-005 +Gc6_38 0 n12 ns38 0 5.25573881599e-006 +Gc6_39 0 n12 ns39 0 -0.0001852286173 +Gc6_40 0 n12 ns40 0 -0.000457577324602 +Gc6_41 0 n12 ns41 0 0.000376051433297 +Gc6_42 0 n12 ns42 0 -1.81082761502e-005 +Gc6_43 0 n12 ns43 0 -0.0031064036653 +Gc6_44 0 n12 ns44 0 -0.00244117054073 +Gc6_45 0 n12 ns45 0 -0.00130100637845 +Gc6_46 0 n12 ns46 0 -0.000194126052103 +Gc6_47 0 n12 ns47 0 -0.00259045115013 +Gc6_48 0 n12 ns48 0 -0.0101563607483 +Gc6_49 0 n12 ns49 0 -0.000486083769452 +Gc6_50 0 n12 ns50 0 -0.000181305408839 +Gc6_51 0 n12 ns51 0 -0.00137797464032 +Gc6_52 0 n12 ns52 0 0.000263547844989 +Gc6_53 0 n12 ns53 0 -0.00140972135953 +Gc6_54 0 n12 ns54 0 0.000112262605851 +Gc6_55 0 n12 ns55 0 -0.00169568518497 +Gc6_56 0 n12 ns56 0 0.000425652857267 +Gc6_57 0 n12 ns57 0 2.40850621282e-007 +Gc6_58 0 n12 ns58 0 -4.36465187655e-007 +Gc6_59 0 n12 ns59 0 -0.000477932600316 +Gc6_60 0 n12 ns60 0 5.80199621522e-005 +Gc6_61 0 n12 ns61 0 -0.00240856905017 +Gc6_62 0 n12 ns62 0 0.00123235244731 +Gc6_63 0 n12 ns63 0 0.000575932960581 +Gc6_64 0 n12 ns64 0 0.000797072174032 +Gc6_65 0 n12 ns65 0 -0.0159130027473 +Gc6_66 0 n12 ns66 0 -0.0171813488807 +Gc6_67 0 n12 ns67 0 0.00121161261746 +Gc6_68 0 n12 ns68 0 -0.000100906893112 +Gc6_69 0 n12 ns69 0 -0.00135963406336 +Gc6_70 0 n12 ns70 0 -0.00499282705825 +Gc6_71 0 n12 ns71 0 -0.000255780486555 +Gc6_72 0 n12 ns72 0 -7.47114286999e-005 +Gc6_73 0 n12 ns73 0 -0.0010158252684 +Gc6_74 0 n12 ns74 0 0.000731088552052 +Gc6_75 0 n12 ns75 0 -0.000306691858753 +Gc6_76 0 n12 ns76 0 -0.000638498184351 +Gc6_77 0 n12 ns77 0 0.00166111945784 +Gc6_78 0 n12 ns78 0 -0.000366173063802 +Gc6_79 0 n12 ns79 0 1.50597001009e-007 +Gc6_80 0 n12 ns80 0 -5.21424157868e-007 +Gc6_81 0 n12 ns81 0 0.000297495212 +Gc6_82 0 n12 ns82 0 -0.000646528469645 +Gc6_83 0 n12 ns83 0 -0.000147312585037 +Gc6_84 0 n12 ns84 0 0.000220140176666 +Gc6_85 0 n12 ns85 0 9.14279029574e-005 +Gc6_86 0 n12 ns86 0 0.00025892358282 +Gc6_87 0 n12 ns87 0 -0.00326424427579 +Gc6_88 0 n12 ns88 0 -0.00289834894519 +Gc6_89 0 n12 ns89 0 0.00120629958519 +Gc6_90 0 n12 ns90 0 -9.5455341168e-005 +Gc6_91 0 n12 ns91 0 -0.00124173705212 +Gc6_92 0 n12 ns92 0 -0.00513539854427 +Gc6_93 0 n12 ns93 0 -0.000231592078495 +Gc6_94 0 n12 ns94 0 -8.14862303139e-005 +Gc6_95 0 n12 ns95 0 -0.000176220256702 +Gc6_96 0 n12 ns96 0 -0.000310995148071 +Gc6_97 0 n12 ns97 0 -0.0011155521059 +Gc6_98 0 n12 ns98 0 0.00052721952396 +Gc6_99 0 n12 ns99 0 0.00157989763132 +Gc6_100 0 n12 ns100 0 -0.000464604345791 +Gc6_101 0 n12 ns101 0 2.83705233236e-007 +Gc6_102 0 n12 ns102 0 -6.43886443695e-007 +Gc6_103 0 n12 ns103 0 0.000112122681835 +Gc6_104 0 n12 ns104 0 -5.51735467757e-005 +Gc6_105 0 n12 ns105 0 0.000411635102161 +Gc6_106 0 n12 ns106 0 4.60137546869e-005 +Gc6_107 0 n12 ns107 0 -0.000227955791075 +Gc6_108 0 n12 ns108 0 -4.91733067168e-005 +Gc6_109 0 n12 ns109 0 -0.00299907529946 +Gc6_110 0 n12 ns110 0 -0.00284841855736 +Gc6_111 0 n12 ns111 0 0.00128003093629 +Gc6_112 0 n12 ns112 0 0.000199356214252 +Gc6_113 0 n12 ns113 0 0.00259843343546 +Gc6_114 0 n12 ns114 0 0.0101336719777 +Gc6_115 0 n12 ns115 0 0.000497652119556 +Gc6_116 0 n12 ns116 0 0.000114389808802 +Gc6_117 0 n12 ns117 0 0.00135553177927 +Gc6_118 0 n12 ns118 0 -0.000372657387962 +Gc6_119 0 n12 ns119 0 0.00124208751897 +Gc6_120 0 n12 ns120 0 4.37425098825e-005 +Gc6_121 0 n12 ns121 0 0.00170562625538 +Gc6_122 0 n12 ns122 0 -0.000422111204895 +Gc6_123 0 n12 ns123 0 3.2694127902e-007 +Gc6_124 0 n12 ns124 0 -6.04361404237e-007 +Gc6_125 0 n12 ns125 0 0.000341691704966 +Gc6_126 0 n12 ns126 0 -0.000188690720857 +Gc6_127 0 n12 ns127 0 0.00160443444827 +Gc6_128 0 n12 ns128 0 -0.000622314423116 +Gc6_129 0 n12 ns129 0 -0.000527683945531 +Gc6_130 0 n12 ns130 0 -0.000679122046042 +Gc6_131 0 n12 ns131 0 0.0139471227872 +Gc6_132 0 n12 ns132 0 0.0417185343349 +Gd6_1 0 n12 ni1 0 -0.00063609968444 +Gd6_2 0 n12 ni2 0 -0.000885720724959 +Gd6_3 0 n12 ni3 0 -0.00681758493959 +Gd6_4 0 n12 ni4 0 -0.000600661148642 +Gd6_5 0 n12 ni5 0 -0.0004441792297 +Gd6_6 0 n12 ni6 0 0.00442989562257 +.ends + +*$ +* BEGIN ANSOFT HEADER +* node 1 Port1 +* node 2 Port2 +* node 3 Port3 +* node 4 Port4 +* node 5 Port5 +* node 6 Port6 +* Project: Project10 +* Format: PSpice +* Topckt: s744839003460_sp +* Date: Wed May 27 09:31:20 2020 +* Notes: Frequency range: 1 to 1e+009 Hz, 502 points +* : Maximum number of poles: 10000 +* : S-Matrix fitting error tolerance: 0.005 +* : Causality check tolerance: auto +* : Passivity enforcement: off +* : Causality enforcement: off +* : Fitting method: TWA +* : Matrix fitting: By entire matrix +* : Ensure Z-parameter accuracy: on +* : Relative error control: off +* : Common ground option: on +* : Final fitting error: 0.00683527 +* : Final model order: 618 +* END ANSOFT HEADER + +.subckt 744839003460 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 75559446.4424 +Ca2 ns2 0 1e-012 +Ca3 ns3 0 1e-012 +Ra2 ns2 0 1429692.02507 +Ra3 ns3 0 1429692.02507 +Ga2 ns2 0 ns3 0 1.86788534433e-006 +Ga3 ns3 0 ns2 0 -1.86788534433e-006 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 246339.394296 +Ca5 ns5 0 1e-012 +Ca6 ns6 0 1e-012 +Ra5 ns5 0 3140698.95851 +Ra6 ns6 0 3140698.95851 +Ga5 ns5 0 ns6 0 7.09906366399e-006 +Ga6 ns6 0 ns5 0 -7.09906366399e-006 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 432178.481825 +Ra8 ns8 0 432178.481825 +Ga7 ns7 0 ns8 0 7.65521128032e-006 +Ga8 ns8 0 ns7 0 -7.65521128032e-006 +Ca9 ns9 0 1e-012 +Ra9 ns9 0 40845.143813 +Ca10 ns10 0 1e-012 +Ra10 ns10 0 15244.7761181 +Ca11 ns11 0 1e-012 +Ra11 ns11 0 8449.43173224 +Ca12 ns12 0 1e-012 +Ra12 ns12 0 3139.44862129 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 11944.9771613 +Ra14 ns14 0 11944.9771613 +Ga13 ns13 0 ns14 0 0.000462180399865 +Ga14 ns14 0 ns13 0 -0.000462180399865 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 42247.4939429 +Ra16 ns16 0 42247.4939429 +Ga15 ns15 0 ns16 0 0.000693426100266 +Ga16 ns16 0 ns15 0 -0.000693426100266 +Ca17 ns17 0 1e-012 +Ca18 ns18 0 1e-012 +Ra17 ns17 0 39755.901208 +Ra18 ns18 0 39755.901208 +Ga17 ns17 0 ns18 0 0.000761257369333 +Ga18 ns18 0 ns17 0 -0.000761257369333 +Ca19 ns19 0 1e-012 +Ca20 ns20 0 1e-012 +Ra19 ns19 0 21711.3623474 +Ra20 ns20 0 21711.3623474 +Ga19 ns19 0 ns20 0 0.000882812596141 +Ga20 ns20 0 ns19 0 -0.000882812596141 +Ca21 ns21 0 1e-012 +Ca22 ns22 0 1e-012 +Ra21 ns21 0 31406.4073875 +Ra22 ns22 0 31406.4073875 +Ga21 ns21 0 ns22 0 0.0010820924882 +Ga22 ns22 0 ns21 0 -0.0010820924882 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 3149.07180722 +Ra24 ns24 0 3149.07180722 +Ga23 ns23 0 ns24 0 0.00121438412928 +Ga24 ns24 0 ns23 0 -0.00121438412928 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 2569.48104963 +Ra26 ns26 0 2569.48104963 +Ga25 ns25 0 ns26 0 -0.00120846241795 +Ga26 ns26 0 ns25 0 0.00120846241795 +Ca27 ns27 0 1e-012 +Ra27 ns27 0 702.418450592 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 25014.2129071 +Ra29 ns29 0 25014.2129071 +Ga28 ns28 0 ns29 0 0.00152233059114 +Ga29 ns29 0 ns28 0 -0.00152233059114 +Ca30 ns30 0 1e-012 +Ca31 ns31 0 1e-012 +Ra30 ns30 0 21774.9640016 +Ra31 ns31 0 21774.9640016 +Ga30 ns30 0 ns31 0 0.0015688651638 +Ga31 ns31 0 ns30 0 -0.0015688651638 +Ca32 ns32 0 1e-012 +Ca33 ns33 0 1e-012 +Ra32 ns32 0 47567.5330282 +Ra33 ns33 0 47567.5330282 +Ga32 ns32 0 ns33 0 0.0015707458645 +Ga33 ns33 0 ns32 0 -0.0015707458645 +Ca34 ns34 0 1e-012 +Ca35 ns35 0 1e-012 +Ra34 ns34 0 2274.03359868 +Ra35 ns35 0 2274.03359868 +Ga34 ns34 0 ns35 0 0.00166266781711 +Ga35 ns35 0 ns34 0 -0.00166266781711 +Ca36 ns36 0 1e-012 +Ca37 ns37 0 1e-012 +Ra36 ns36 0 35760.6903471 +Ra37 ns37 0 35760.6903471 +Ga36 ns36 0 ns37 0 0.00175118644696 +Ga37 ns37 0 ns36 0 -0.00175118644696 +Ca38 ns38 0 1e-012 +Ca39 ns39 0 1e-012 +Ra38 ns38 0 9906.97610596 +Ra39 ns39 0 9906.97610596 +Ga38 ns38 0 ns39 0 0.00180033453419 +Ga39 ns39 0 ns38 0 -0.00180033453419 +Ca40 ns40 0 1e-012 +Ca41 ns41 0 1e-012 +Ra40 ns40 0 22007.8238421 +Ra41 ns41 0 22007.8238421 +Ga40 ns40 0 ns41 0 0.00184449444316 +Ga41 ns41 0 ns40 0 -0.00184449444316 +Ca42 ns42 0 1e-012 +Ca43 ns43 0 1e-012 +Ra42 ns42 0 30910.1944083 +Ra43 ns43 0 30910.1944083 +Ga42 ns42 0 ns43 0 0.0020789191311 +Ga43 ns43 0 ns42 0 -0.0020789191311 +Ca44 ns44 0 1e-012 +Ca45 ns45 0 1e-012 +Ra44 ns44 0 886.057098121 +Ra45 ns45 0 886.057098121 +Ga44 ns44 0 ns45 0 0.0019302292208 +Ga45 ns45 0 ns44 0 -0.0019302292208 +Ca46 ns46 0 1e-012 +Ca47 ns47 0 1e-012 +Ra46 ns46 0 8767.68764418 +Ra47 ns47 0 8767.68764418 +Ga46 ns46 0 ns47 0 0.00230274466816 +Ga47 ns47 0 ns46 0 -0.00230274466816 +Ca48 ns48 0 1e-012 +Ca49 ns49 0 1e-012 +Ra48 ns48 0 16384.2906969 +Ra49 ns49 0 16384.2906969 +Ga48 ns48 0 ns49 0 0.00251233787856 +Ga49 ns49 0 ns48 0 -0.00251233787856 +Ca50 ns50 0 1e-012 +Ca51 ns51 0 1e-012 +Ra50 ns50 0 21503.7896426 +Ra51 ns51 0 21503.7896426 +Ga50 ns50 0 ns51 0 -0.00260344051006 +Ga51 ns51 0 ns50 0 0.00260344051006 +Ca52 ns52 0 1e-012 +Ca53 ns53 0 1e-012 +Ra52 ns52 0 22825.3651304 +Ra53 ns53 0 22825.3651304 +Ga52 ns52 0 ns53 0 0.00267888417896 +Ga53 ns53 0 ns52 0 -0.00267888417896 +Ca54 ns54 0 1e-012 +Ca55 ns55 0 1e-012 +Ra54 ns54 0 7681.03739833 +Ra55 ns55 0 7681.03739833 +Ga54 ns54 0 ns55 0 0.00294208056419 +Ga55 ns55 0 ns54 0 -0.00294208056419 +Ca56 ns56 0 1e-012 +Ca57 ns57 0 1e-012 +Ra56 ns56 0 11078.985173 +Ra57 ns57 0 11078.985173 +Ga56 ns56 0 ns57 0 0.00304930398407 +Ga57 ns57 0 ns56 0 -0.00304930398407 +Ca58 ns58 0 1e-012 +Ca59 ns59 0 1e-012 +Ra58 ns58 0 2600.01630725 +Ra59 ns59 0 2600.01630725 +Ga58 ns58 0 ns59 0 0.00305535236912 +Ga59 ns59 0 ns58 0 -0.00305535236912 +Ca60 ns60 0 1e-012 +Ca61 ns61 0 1e-012 +Ra60 ns60 0 27128.5023176 +Ra61 ns61 0 27128.5023176 +Ga60 ns60 0 ns61 0 0.00332709985629 +Ga61 ns61 0 ns60 0 -0.00332709985629 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 21634.7316013 +Ra63 ns63 0 21634.7316013 +Ga62 ns62 0 ns63 0 0.003450757883 +Ga63 ns63 0 ns62 0 -0.003450757883 +Ca64 ns64 0 1e-012 +Ca65 ns65 0 1e-012 +Ra64 ns64 0 1255.34703842 +Ra65 ns65 0 1255.34703842 +Ga64 ns64 0 ns65 0 0.00337413358794 +Ga65 ns65 0 ns64 0 -0.00337413358794 +Ca66 ns66 0 1e-012 +Ca67 ns67 0 1e-012 +Ra66 ns66 0 16234.7396118 +Ra67 ns67 0 16234.7396118 +Ga66 ns66 0 ns67 0 0.00357951452468 +Ga67 ns67 0 ns66 0 -0.00357951452468 +Ca68 ns68 0 1e-012 +Ca69 ns69 0 1e-012 +Ra68 ns68 0 9432.97056341 +Ra69 ns69 0 9432.97056341 +Ga68 ns68 0 ns69 0 0.00367408923266 +Ga69 ns69 0 ns68 0 -0.00367408923266 +Ca70 ns70 0 1e-012 +Ca71 ns71 0 1e-012 +Ra70 ns70 0 6490.68663673 +Ra71 ns71 0 6490.68663673 +Ga70 ns70 0 ns71 0 0.00373532438761 +Ga71 ns71 0 ns70 0 -0.00373532438761 +Ca72 ns72 0 1e-012 +Ca73 ns73 0 1e-012 +Ra72 ns72 0 9189.9143658 +Ra73 ns73 0 9189.9143658 +Ga72 ns72 0 ns73 0 0.00402784781244 +Ga73 ns73 0 ns72 0 -0.00402784781244 +Ca74 ns74 0 1e-012 +Ca75 ns75 0 1e-012 +Ra74 ns74 0 15134.0602533 +Ra75 ns75 0 15134.0602533 +Ga74 ns74 0 ns75 0 0.00422563870151 +Ga75 ns75 0 ns74 0 -0.00422563870151 +Ca76 ns76 0 1e-012 +Ca77 ns77 0 1e-012 +Ra76 ns76 0 9502.03815934 +Ra77 ns77 0 9502.03815934 +Ga76 ns76 0 ns77 0 0.00438549041759 +Ga77 ns77 0 ns76 0 -0.00438549041759 +Ca78 ns78 0 1e-012 +Ca79 ns79 0 1e-012 +Ra78 ns78 0 1462.27425817 +Ra79 ns79 0 1462.27425817 +Ga78 ns78 0 ns79 0 0.00444962977407 +Ga79 ns79 0 ns78 0 -0.00444962977407 +Ca80 ns80 0 1e-012 +Ca81 ns81 0 1e-012 +Ra80 ns80 0 10431.5635559 +Ra81 ns81 0 10431.5635559 +Ga80 ns80 0 ns81 0 0.00454033573239 +Ga81 ns81 0 ns80 0 -0.00454033573239 +Ca82 ns82 0 1e-012 +Ca83 ns83 0 1e-012 +Ra82 ns82 0 5694.78290457 +Ra83 ns83 0 5694.78290457 +Ga82 ns82 0 ns83 0 0.00485677246494 +Ga83 ns83 0 ns82 0 -0.00485677246494 +Ca84 ns84 0 1e-012 +Ca85 ns85 0 1e-012 +Ra84 ns84 0 6892.95589034 +Ra85 ns85 0 6892.95589034 +Ga84 ns84 0 ns85 0 0.00500916986901 +Ga85 ns85 0 ns84 0 -0.00500916986901 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 9744.756895 +Ra87 ns87 0 9744.756895 +Ga86 ns86 0 ns87 0 0.00507968996011 +Ga87 ns87 0 ns86 0 -0.00507968996011 +Ca88 ns88 0 1e-012 +Ca89 ns89 0 1e-012 +Ra88 ns88 0 5083.8610328 +Ra89 ns89 0 5083.8610328 +Ga88 ns88 0 ns89 0 0.0052027889728 +Ga89 ns89 0 ns88 0 -0.0052027889728 +Ca90 ns90 0 1e-012 +Ca91 ns91 0 1e-012 +Ra90 ns90 0 11932.9415219 +Ra91 ns91 0 11932.9415219 +Ga90 ns90 0 ns91 0 0.00543255424918 +Ga91 ns91 0 ns90 0 -0.00543255424918 +Ca92 ns92 0 1e-012 +Ca93 ns93 0 1e-012 +Ra92 ns92 0 2649.73611698 +Ra93 ns93 0 2649.73611698 +Ga92 ns92 0 ns93 0 0.00572768809984 +Ga93 ns93 0 ns92 0 -0.00572768809984 +Ca94 ns94 0 1e-012 +Ca95 ns95 0 1e-012 +Ra94 ns94 0 6440.79899097 +Ra95 ns95 0 6440.79899097 +Ga94 ns94 0 ns95 0 0.00579138648629 +Ga95 ns95 0 ns94 0 -0.00579138648629 +Ca96 ns96 0 1e-012 +Ca97 ns97 0 1e-012 +Ra96 ns96 0 10718.8612946 +Ra97 ns97 0 10718.8612946 +Ga96 ns96 0 ns97 0 0.00588634989311 +Ga97 ns97 0 ns96 0 -0.00588634989311 +Ca98 ns98 0 1e-012 +Ca99 ns99 0 1e-012 +Ra98 ns98 0 7964.88003957 +Ra99 ns99 0 7964.88003957 +Ga98 ns98 0 ns99 0 0.00596997907625 +Ga99 ns99 0 ns98 0 -0.00596997907625 +Ca100 ns100 0 1e-012 +Ca101 ns101 0 1e-012 +Ra100 ns100 0 2611.74770779 +Ra101 ns101 0 2611.74770779 +Ga100 ns100 0 ns101 0 0.0059811572659 +Ga101 ns101 0 ns100 0 -0.0059811572659 +Ca102 ns102 0 1e-012 +Ca103 ns103 0 1e-012 +Ra102 ns102 0 3029.51710274 +Ra103 ns103 0 3029.51710274 +Ga102 ns102 0 ns103 0 -0.00624522385785 +Ga103 ns103 0 ns102 0 0.00624522385785 +Ca104 ns104 0 1e-012 +Ra104 ns104 0 75559446.4424 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 1429692.02507 +Ra106 ns106 0 1429692.02507 +Ga105 ns105 0 ns106 0 1.86788534433e-006 +Ga106 ns106 0 ns105 0 -1.86788534433e-006 +Ca107 ns107 0 1e-012 +Ra107 ns107 0 246339.394296 +Ca108 ns108 0 1e-012 +Ca109 ns109 0 1e-012 +Ra108 ns108 0 3140698.95851 +Ra109 ns109 0 3140698.95851 +Ga108 ns108 0 ns109 0 7.09906366399e-006 +Ga109 ns109 0 ns108 0 -7.09906366399e-006 +Ca110 ns110 0 1e-012 +Ca111 ns111 0 1e-012 +Ra110 ns110 0 432178.481825 +Ra111 ns111 0 432178.481825 +Ga110 ns110 0 ns111 0 7.65521128032e-006 +Ga111 ns111 0 ns110 0 -7.65521128032e-006 +Ca112 ns112 0 1e-012 +Ra112 ns112 0 40845.143813 +Ca113 ns113 0 1e-012 +Ra113 ns113 0 15244.7761181 +Ca114 ns114 0 1e-012 +Ra114 ns114 0 8449.43173224 +Ca115 ns115 0 1e-012 +Ra115 ns115 0 3139.44862129 +Ca116 ns116 0 1e-012 +Ca117 ns117 0 1e-012 +Ra116 ns116 0 11944.9771613 +Ra117 ns117 0 11944.9771613 +Ga116 ns116 0 ns117 0 0.000462180399865 +Ga117 ns117 0 ns116 0 -0.000462180399865 +Ca118 ns118 0 1e-012 +Ca119 ns119 0 1e-012 +Ra118 ns118 0 42247.4939429 +Ra119 ns119 0 42247.4939429 +Ga118 ns118 0 ns119 0 0.000693426100266 +Ga119 ns119 0 ns118 0 -0.000693426100266 +Ca120 ns120 0 1e-012 +Ca121 ns121 0 1e-012 +Ra120 ns120 0 39755.901208 +Ra121 ns121 0 39755.901208 +Ga120 ns120 0 ns121 0 0.000761257369333 +Ga121 ns121 0 ns120 0 -0.000761257369333 +Ca122 ns122 0 1e-012 +Ca123 ns123 0 1e-012 +Ra122 ns122 0 21711.3623474 +Ra123 ns123 0 21711.3623474 +Ga122 ns122 0 ns123 0 0.000882812596141 +Ga123 ns123 0 ns122 0 -0.000882812596141 +Ca124 ns124 0 1e-012 +Ca125 ns125 0 1e-012 +Ra124 ns124 0 31406.4073875 +Ra125 ns125 0 31406.4073875 +Ga124 ns124 0 ns125 0 0.0010820924882 +Ga125 ns125 0 ns124 0 -0.0010820924882 +Ca126 ns126 0 1e-012 +Ca127 ns127 0 1e-012 +Ra126 ns126 0 3149.07180722 +Ra127 ns127 0 3149.07180722 +Ga126 ns126 0 ns127 0 0.00121438412928 +Ga127 ns127 0 ns126 0 -0.00121438412928 +Ca128 ns128 0 1e-012 +Ca129 ns129 0 1e-012 +Ra128 ns128 0 2569.48104963 +Ra129 ns129 0 2569.48104963 +Ga128 ns128 0 ns129 0 -0.00120846241795 +Ga129 ns129 0 ns128 0 0.00120846241795 +Ca130 ns130 0 1e-012 +Ra130 ns130 0 702.418450592 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 25014.2129071 +Ra132 ns132 0 25014.2129071 +Ga131 ns131 0 ns132 0 0.00152233059114 +Ga132 ns132 0 ns131 0 -0.00152233059114 +Ca133 ns133 0 1e-012 +Ca134 ns134 0 1e-012 +Ra133 ns133 0 21774.9640016 +Ra134 ns134 0 21774.9640016 +Ga133 ns133 0 ns134 0 0.0015688651638 +Ga134 ns134 0 ns133 0 -0.0015688651638 +Ca135 ns135 0 1e-012 +Ca136 ns136 0 1e-012 +Ra135 ns135 0 47567.5330282 +Ra136 ns136 0 47567.5330282 +Ga135 ns135 0 ns136 0 0.0015707458645 +Ga136 ns136 0 ns135 0 -0.0015707458645 +Ca137 ns137 0 1e-012 +Ca138 ns138 0 1e-012 +Ra137 ns137 0 2274.03359868 +Ra138 ns138 0 2274.03359868 +Ga137 ns137 0 ns138 0 0.00166266781711 +Ga138 ns138 0 ns137 0 -0.00166266781711 +Ca139 ns139 0 1e-012 +Ca140 ns140 0 1e-012 +Ra139 ns139 0 35760.6903471 +Ra140 ns140 0 35760.6903471 +Ga139 ns139 0 ns140 0 0.00175118644696 +Ga140 ns140 0 ns139 0 -0.00175118644696 +Ca141 ns141 0 1e-012 +Ca142 ns142 0 1e-012 +Ra141 ns141 0 9906.97610596 +Ra142 ns142 0 9906.97610596 +Ga141 ns141 0 ns142 0 0.00180033453419 +Ga142 ns142 0 ns141 0 -0.00180033453419 +Ca143 ns143 0 1e-012 +Ca144 ns144 0 1e-012 +Ra143 ns143 0 22007.8238421 +Ra144 ns144 0 22007.8238421 +Ga143 ns143 0 ns144 0 0.00184449444316 +Ga144 ns144 0 ns143 0 -0.00184449444316 +Ca145 ns145 0 1e-012 +Ca146 ns146 0 1e-012 +Ra145 ns145 0 30910.1944083 +Ra146 ns146 0 30910.1944083 +Ga145 ns145 0 ns146 0 0.0020789191311 +Ga146 ns146 0 ns145 0 -0.0020789191311 +Ca147 ns147 0 1e-012 +Ca148 ns148 0 1e-012 +Ra147 ns147 0 886.057098121 +Ra148 ns148 0 886.057098121 +Ga147 ns147 0 ns148 0 0.0019302292208 +Ga148 ns148 0 ns147 0 -0.0019302292208 +Ca149 ns149 0 1e-012 +Ca150 ns150 0 1e-012 +Ra149 ns149 0 8767.68764418 +Ra150 ns150 0 8767.68764418 +Ga149 ns149 0 ns150 0 0.00230274466816 +Ga150 ns150 0 ns149 0 -0.00230274466816 +Ca151 ns151 0 1e-012 +Ca152 ns152 0 1e-012 +Ra151 ns151 0 16384.2906969 +Ra152 ns152 0 16384.2906969 +Ga151 ns151 0 ns152 0 0.00251233787856 +Ga152 ns152 0 ns151 0 -0.00251233787856 +Ca153 ns153 0 1e-012 +Ca154 ns154 0 1e-012 +Ra153 ns153 0 21503.7896426 +Ra154 ns154 0 21503.7896426 +Ga153 ns153 0 ns154 0 -0.00260344051006 +Ga154 ns154 0 ns153 0 0.00260344051006 +Ca155 ns155 0 1e-012 +Ca156 ns156 0 1e-012 +Ra155 ns155 0 22825.3651304 +Ra156 ns156 0 22825.3651304 +Ga155 ns155 0 ns156 0 0.00267888417896 +Ga156 ns156 0 ns155 0 -0.00267888417896 +Ca157 ns157 0 1e-012 +Ca158 ns158 0 1e-012 +Ra157 ns157 0 7681.03739833 +Ra158 ns158 0 7681.03739833 +Ga157 ns157 0 ns158 0 0.00294208056419 +Ga158 ns158 0 ns157 0 -0.00294208056419 +Ca159 ns159 0 1e-012 +Ca160 ns160 0 1e-012 +Ra159 ns159 0 11078.985173 +Ra160 ns160 0 11078.985173 +Ga159 ns159 0 ns160 0 0.00304930398407 +Ga160 ns160 0 ns159 0 -0.00304930398407 +Ca161 ns161 0 1e-012 +Ca162 ns162 0 1e-012 +Ra161 ns161 0 2600.01630725 +Ra162 ns162 0 2600.01630725 +Ga161 ns161 0 ns162 0 0.00305535236912 +Ga162 ns162 0 ns161 0 -0.00305535236912 +Ca163 ns163 0 1e-012 +Ca164 ns164 0 1e-012 +Ra163 ns163 0 27128.5023176 +Ra164 ns164 0 27128.5023176 +Ga163 ns163 0 ns164 0 0.00332709985629 +Ga164 ns164 0 ns163 0 -0.00332709985629 +Ca165 ns165 0 1e-012 +Ca166 ns166 0 1e-012 +Ra165 ns165 0 21634.7316013 +Ra166 ns166 0 21634.7316013 +Ga165 ns165 0 ns166 0 0.003450757883 +Ga166 ns166 0 ns165 0 -0.003450757883 +Ca167 ns167 0 1e-012 +Ca168 ns168 0 1e-012 +Ra167 ns167 0 1255.34703842 +Ra168 ns168 0 1255.34703842 +Ga167 ns167 0 ns168 0 0.00337413358794 +Ga168 ns168 0 ns167 0 -0.00337413358794 +Ca169 ns169 0 1e-012 +Ca170 ns170 0 1e-012 +Ra169 ns169 0 16234.7396118 +Ra170 ns170 0 16234.7396118 +Ga169 ns169 0 ns170 0 0.00357951452468 +Ga170 ns170 0 ns169 0 -0.00357951452468 +Ca171 ns171 0 1e-012 +Ca172 ns172 0 1e-012 +Ra171 ns171 0 9432.97056341 +Ra172 ns172 0 9432.97056341 +Ga171 ns171 0 ns172 0 0.00367408923266 +Ga172 ns172 0 ns171 0 -0.00367408923266 +Ca173 ns173 0 1e-012 +Ca174 ns174 0 1e-012 +Ra173 ns173 0 6490.68663673 +Ra174 ns174 0 6490.68663673 +Ga173 ns173 0 ns174 0 0.00373532438761 +Ga174 ns174 0 ns173 0 -0.00373532438761 +Ca175 ns175 0 1e-012 +Ca176 ns176 0 1e-012 +Ra175 ns175 0 9189.9143658 +Ra176 ns176 0 9189.9143658 +Ga175 ns175 0 ns176 0 0.00402784781244 +Ga176 ns176 0 ns175 0 -0.00402784781244 +Ca177 ns177 0 1e-012 +Ca178 ns178 0 1e-012 +Ra177 ns177 0 15134.0602533 +Ra178 ns178 0 15134.0602533 +Ga177 ns177 0 ns178 0 0.00422563870151 +Ga178 ns178 0 ns177 0 -0.00422563870151 +Ca179 ns179 0 1e-012 +Ca180 ns180 0 1e-012 +Ra179 ns179 0 9502.03815934 +Ra180 ns180 0 9502.03815934 +Ga179 ns179 0 ns180 0 0.00438549041759 +Ga180 ns180 0 ns179 0 -0.00438549041759 +Ca181 ns181 0 1e-012 +Ca182 ns182 0 1e-012 +Ra181 ns181 0 1462.27425817 +Ra182 ns182 0 1462.27425817 +Ga181 ns181 0 ns182 0 0.00444962977407 +Ga182 ns182 0 ns181 0 -0.00444962977407 +Ca183 ns183 0 1e-012 +Ca184 ns184 0 1e-012 +Ra183 ns183 0 10431.5635559 +Ra184 ns184 0 10431.5635559 +Ga183 ns183 0 ns184 0 0.00454033573239 +Ga184 ns184 0 ns183 0 -0.00454033573239 +Ca185 ns185 0 1e-012 +Ca186 ns186 0 1e-012 +Ra185 ns185 0 5694.78290457 +Ra186 ns186 0 5694.78290457 +Ga185 ns185 0 ns186 0 0.00485677246494 +Ga186 ns186 0 ns185 0 -0.00485677246494 +Ca187 ns187 0 1e-012 +Ca188 ns188 0 1e-012 +Ra187 ns187 0 6892.95589034 +Ra188 ns188 0 6892.95589034 +Ga187 ns187 0 ns188 0 0.00500916986901 +Ga188 ns188 0 ns187 0 -0.00500916986901 +Ca189 ns189 0 1e-012 +Ca190 ns190 0 1e-012 +Ra189 ns189 0 9744.756895 +Ra190 ns190 0 9744.756895 +Ga189 ns189 0 ns190 0 0.00507968996011 +Ga190 ns190 0 ns189 0 -0.00507968996011 +Ca191 ns191 0 1e-012 +Ca192 ns192 0 1e-012 +Ra191 ns191 0 5083.8610328 +Ra192 ns192 0 5083.8610328 +Ga191 ns191 0 ns192 0 0.0052027889728 +Ga192 ns192 0 ns191 0 -0.0052027889728 +Ca193 ns193 0 1e-012 +Ca194 ns194 0 1e-012 +Ra193 ns193 0 11932.9415219 +Ra194 ns194 0 11932.9415219 +Ga193 ns193 0 ns194 0 0.00543255424918 +Ga194 ns194 0 ns193 0 -0.00543255424918 +Ca195 ns195 0 1e-012 +Ca196 ns196 0 1e-012 +Ra195 ns195 0 2649.73611698 +Ra196 ns196 0 2649.73611698 +Ga195 ns195 0 ns196 0 0.00572768809984 +Ga196 ns196 0 ns195 0 -0.00572768809984 +Ca197 ns197 0 1e-012 +Ca198 ns198 0 1e-012 +Ra197 ns197 0 6440.79899097 +Ra198 ns198 0 6440.79899097 +Ga197 ns197 0 ns198 0 0.00579138648629 +Ga198 ns198 0 ns197 0 -0.00579138648629 +Ca199 ns199 0 1e-012 +Ca200 ns200 0 1e-012 +Ra199 ns199 0 10718.8612946 +Ra200 ns200 0 10718.8612946 +Ga199 ns199 0 ns200 0 0.00588634989311 +Ga200 ns200 0 ns199 0 -0.00588634989311 +Ca201 ns201 0 1e-012 +Ca202 ns202 0 1e-012 +Ra201 ns201 0 7964.88003957 +Ra202 ns202 0 7964.88003957 +Ga201 ns201 0 ns202 0 0.00596997907625 +Ga202 ns202 0 ns201 0 -0.00596997907625 +Ca203 ns203 0 1e-012 +Ca204 ns204 0 1e-012 +Ra203 ns203 0 2611.74770779 +Ra204 ns204 0 2611.74770779 +Ga203 ns203 0 ns204 0 0.0059811572659 +Ga204 ns204 0 ns203 0 -0.0059811572659 +Ca205 ns205 0 1e-012 +Ca206 ns206 0 1e-012 +Ra205 ns205 0 3029.51710274 +Ra206 ns206 0 3029.51710274 +Ga205 ns205 0 ns206 0 -0.00624522385785 +Ga206 ns206 0 ns205 0 0.00624522385785 +Ca207 ns207 0 1e-012 +Ra207 ns207 0 75559446.4424 +Ca208 ns208 0 1e-012 +Ca209 ns209 0 1e-012 +Ra208 ns208 0 1429692.02507 +Ra209 ns209 0 1429692.02507 +Ga208 ns208 0 ns209 0 1.86788534433e-006 +Ga209 ns209 0 ns208 0 -1.86788534433e-006 +Ca210 ns210 0 1e-012 +Ra210 ns210 0 246339.394296 +Ca211 ns211 0 1e-012 +Ca212 ns212 0 1e-012 +Ra211 ns211 0 3140698.95851 +Ra212 ns212 0 3140698.95851 +Ga211 ns211 0 ns212 0 7.09906366399e-006 +Ga212 ns212 0 ns211 0 -7.09906366399e-006 +Ca213 ns213 0 1e-012 +Ca214 ns214 0 1e-012 +Ra213 ns213 0 432178.481825 +Ra214 ns214 0 432178.481825 +Ga213 ns213 0 ns214 0 7.65521128032e-006 +Ga214 ns214 0 ns213 0 -7.65521128032e-006 +Ca215 ns215 0 1e-012 +Ra215 ns215 0 40845.143813 +Ca216 ns216 0 1e-012 +Ra216 ns216 0 15244.7761181 +Ca217 ns217 0 1e-012 +Ra217 ns217 0 8449.43173224 +Ca218 ns218 0 1e-012 +Ra218 ns218 0 3139.44862129 +Ca219 ns219 0 1e-012 +Ca220 ns220 0 1e-012 +Ra219 ns219 0 11944.9771613 +Ra220 ns220 0 11944.9771613 +Ga219 ns219 0 ns220 0 0.000462180399865 +Ga220 ns220 0 ns219 0 -0.000462180399865 +Ca221 ns221 0 1e-012 +Ca222 ns222 0 1e-012 +Ra221 ns221 0 42247.4939429 +Ra222 ns222 0 42247.4939429 +Ga221 ns221 0 ns222 0 0.000693426100266 +Ga222 ns222 0 ns221 0 -0.000693426100266 +Ca223 ns223 0 1e-012 +Ca224 ns224 0 1e-012 +Ra223 ns223 0 39755.901208 +Ra224 ns224 0 39755.901208 +Ga223 ns223 0 ns224 0 0.000761257369333 +Ga224 ns224 0 ns223 0 -0.000761257369333 +Ca225 ns225 0 1e-012 +Ca226 ns226 0 1e-012 +Ra225 ns225 0 21711.3623474 +Ra226 ns226 0 21711.3623474 +Ga225 ns225 0 ns226 0 0.000882812596141 +Ga226 ns226 0 ns225 0 -0.000882812596141 +Ca227 ns227 0 1e-012 +Ca228 ns228 0 1e-012 +Ra227 ns227 0 31406.4073875 +Ra228 ns228 0 31406.4073875 +Ga227 ns227 0 ns228 0 0.0010820924882 +Ga228 ns228 0 ns227 0 -0.0010820924882 +Ca229 ns229 0 1e-012 +Ca230 ns230 0 1e-012 +Ra229 ns229 0 3149.07180722 +Ra230 ns230 0 3149.07180722 +Ga229 ns229 0 ns230 0 0.00121438412928 +Ga230 ns230 0 ns229 0 -0.00121438412928 +Ca231 ns231 0 1e-012 +Ca232 ns232 0 1e-012 +Ra231 ns231 0 2569.48104963 +Ra232 ns232 0 2569.48104963 +Ga231 ns231 0 ns232 0 -0.00120846241795 +Ga232 ns232 0 ns231 0 0.00120846241795 +Ca233 ns233 0 1e-012 +Ra233 ns233 0 702.418450592 +Ca234 ns234 0 1e-012 +Ca235 ns235 0 1e-012 +Ra234 ns234 0 25014.2129071 +Ra235 ns235 0 25014.2129071 +Ga234 ns234 0 ns235 0 0.00152233059114 +Ga235 ns235 0 ns234 0 -0.00152233059114 +Ca236 ns236 0 1e-012 +Ca237 ns237 0 1e-012 +Ra236 ns236 0 21774.9640016 +Ra237 ns237 0 21774.9640016 +Ga236 ns236 0 ns237 0 0.0015688651638 +Ga237 ns237 0 ns236 0 -0.0015688651638 +Ca238 ns238 0 1e-012 +Ca239 ns239 0 1e-012 +Ra238 ns238 0 47567.5330282 +Ra239 ns239 0 47567.5330282 +Ga238 ns238 0 ns239 0 0.0015707458645 +Ga239 ns239 0 ns238 0 -0.0015707458645 +Ca240 ns240 0 1e-012 +Ca241 ns241 0 1e-012 +Ra240 ns240 0 2274.03359868 +Ra241 ns241 0 2274.03359868 +Ga240 ns240 0 ns241 0 0.00166266781711 +Ga241 ns241 0 ns240 0 -0.00166266781711 +Ca242 ns242 0 1e-012 +Ca243 ns243 0 1e-012 +Ra242 ns242 0 35760.6903471 +Ra243 ns243 0 35760.6903471 +Ga242 ns242 0 ns243 0 0.00175118644696 +Ga243 ns243 0 ns242 0 -0.00175118644696 +Ca244 ns244 0 1e-012 +Ca245 ns245 0 1e-012 +Ra244 ns244 0 9906.97610596 +Ra245 ns245 0 9906.97610596 +Ga244 ns244 0 ns245 0 0.00180033453419 +Ga245 ns245 0 ns244 0 -0.00180033453419 +Ca246 ns246 0 1e-012 +Ca247 ns247 0 1e-012 +Ra246 ns246 0 22007.8238421 +Ra247 ns247 0 22007.8238421 +Ga246 ns246 0 ns247 0 0.00184449444316 +Ga247 ns247 0 ns246 0 -0.00184449444316 +Ca248 ns248 0 1e-012 +Ca249 ns249 0 1e-012 +Ra248 ns248 0 30910.1944083 +Ra249 ns249 0 30910.1944083 +Ga248 ns248 0 ns249 0 0.0020789191311 +Ga249 ns249 0 ns248 0 -0.0020789191311 +Ca250 ns250 0 1e-012 +Ca251 ns251 0 1e-012 +Ra250 ns250 0 886.057098121 +Ra251 ns251 0 886.057098121 +Ga250 ns250 0 ns251 0 0.0019302292208 +Ga251 ns251 0 ns250 0 -0.0019302292208 +Ca252 ns252 0 1e-012 +Ca253 ns253 0 1e-012 +Ra252 ns252 0 8767.68764418 +Ra253 ns253 0 8767.68764418 +Ga252 ns252 0 ns253 0 0.00230274466816 +Ga253 ns253 0 ns252 0 -0.00230274466816 +Ca254 ns254 0 1e-012 +Ca255 ns255 0 1e-012 +Ra254 ns254 0 16384.2906969 +Ra255 ns255 0 16384.2906969 +Ga254 ns254 0 ns255 0 0.00251233787856 +Ga255 ns255 0 ns254 0 -0.00251233787856 +Ca256 ns256 0 1e-012 +Ca257 ns257 0 1e-012 +Ra256 ns256 0 21503.7896426 +Ra257 ns257 0 21503.7896426 +Ga256 ns256 0 ns257 0 -0.00260344051006 +Ga257 ns257 0 ns256 0 0.00260344051006 +Ca258 ns258 0 1e-012 +Ca259 ns259 0 1e-012 +Ra258 ns258 0 22825.3651304 +Ra259 ns259 0 22825.3651304 +Ga258 ns258 0 ns259 0 0.00267888417896 +Ga259 ns259 0 ns258 0 -0.00267888417896 +Ca260 ns260 0 1e-012 +Ca261 ns261 0 1e-012 +Ra260 ns260 0 7681.03739833 +Ra261 ns261 0 7681.03739833 +Ga260 ns260 0 ns261 0 0.00294208056419 +Ga261 ns261 0 ns260 0 -0.00294208056419 +Ca262 ns262 0 1e-012 +Ca263 ns263 0 1e-012 +Ra262 ns262 0 11078.985173 +Ra263 ns263 0 11078.985173 +Ga262 ns262 0 ns263 0 0.00304930398407 +Ga263 ns263 0 ns262 0 -0.00304930398407 +Ca264 ns264 0 1e-012 +Ca265 ns265 0 1e-012 +Ra264 ns264 0 2600.01630725 +Ra265 ns265 0 2600.01630725 +Ga264 ns264 0 ns265 0 0.00305535236912 +Ga265 ns265 0 ns264 0 -0.00305535236912 +Ca266 ns266 0 1e-012 +Ca267 ns267 0 1e-012 +Ra266 ns266 0 27128.5023176 +Ra267 ns267 0 27128.5023176 +Ga266 ns266 0 ns267 0 0.00332709985629 +Ga267 ns267 0 ns266 0 -0.00332709985629 +Ca268 ns268 0 1e-012 +Ca269 ns269 0 1e-012 +Ra268 ns268 0 21634.7316013 +Ra269 ns269 0 21634.7316013 +Ga268 ns268 0 ns269 0 0.003450757883 +Ga269 ns269 0 ns268 0 -0.003450757883 +Ca270 ns270 0 1e-012 +Ca271 ns271 0 1e-012 +Ra270 ns270 0 1255.34703842 +Ra271 ns271 0 1255.34703842 +Ga270 ns270 0 ns271 0 0.00337413358794 +Ga271 ns271 0 ns270 0 -0.00337413358794 +Ca272 ns272 0 1e-012 +Ca273 ns273 0 1e-012 +Ra272 ns272 0 16234.7396118 +Ra273 ns273 0 16234.7396118 +Ga272 ns272 0 ns273 0 0.00357951452468 +Ga273 ns273 0 ns272 0 -0.00357951452468 +Ca274 ns274 0 1e-012 +Ca275 ns275 0 1e-012 +Ra274 ns274 0 9432.97056341 +Ra275 ns275 0 9432.97056341 +Ga274 ns274 0 ns275 0 0.00367408923266 +Ga275 ns275 0 ns274 0 -0.00367408923266 +Ca276 ns276 0 1e-012 +Ca277 ns277 0 1e-012 +Ra276 ns276 0 6490.68663673 +Ra277 ns277 0 6490.68663673 +Ga276 ns276 0 ns277 0 0.00373532438761 +Ga277 ns277 0 ns276 0 -0.00373532438761 +Ca278 ns278 0 1e-012 +Ca279 ns279 0 1e-012 +Ra278 ns278 0 9189.9143658 +Ra279 ns279 0 9189.9143658 +Ga278 ns278 0 ns279 0 0.00402784781244 +Ga279 ns279 0 ns278 0 -0.00402784781244 +Ca280 ns280 0 1e-012 +Ca281 ns281 0 1e-012 +Ra280 ns280 0 15134.0602533 +Ra281 ns281 0 15134.0602533 +Ga280 ns280 0 ns281 0 0.00422563870151 +Ga281 ns281 0 ns280 0 -0.00422563870151 +Ca282 ns282 0 1e-012 +Ca283 ns283 0 1e-012 +Ra282 ns282 0 9502.03815934 +Ra283 ns283 0 9502.03815934 +Ga282 ns282 0 ns283 0 0.00438549041759 +Ga283 ns283 0 ns282 0 -0.00438549041759 +Ca284 ns284 0 1e-012 +Ca285 ns285 0 1e-012 +Ra284 ns284 0 1462.27425817 +Ra285 ns285 0 1462.27425817 +Ga284 ns284 0 ns285 0 0.00444962977407 +Ga285 ns285 0 ns284 0 -0.00444962977407 +Ca286 ns286 0 1e-012 +Ca287 ns287 0 1e-012 +Ra286 ns286 0 10431.5635559 +Ra287 ns287 0 10431.5635559 +Ga286 ns286 0 ns287 0 0.00454033573239 +Ga287 ns287 0 ns286 0 -0.00454033573239 +Ca288 ns288 0 1e-012 +Ca289 ns289 0 1e-012 +Ra288 ns288 0 5694.78290457 +Ra289 ns289 0 5694.78290457 +Ga288 ns288 0 ns289 0 0.00485677246494 +Ga289 ns289 0 ns288 0 -0.00485677246494 +Ca290 ns290 0 1e-012 +Ca291 ns291 0 1e-012 +Ra290 ns290 0 6892.95589034 +Ra291 ns291 0 6892.95589034 +Ga290 ns290 0 ns291 0 0.00500916986901 +Ga291 ns291 0 ns290 0 -0.00500916986901 +Ca292 ns292 0 1e-012 +Ca293 ns293 0 1e-012 +Ra292 ns292 0 9744.756895 +Ra293 ns293 0 9744.756895 +Ga292 ns292 0 ns293 0 0.00507968996011 +Ga293 ns293 0 ns292 0 -0.00507968996011 +Ca294 ns294 0 1e-012 +Ca295 ns295 0 1e-012 +Ra294 ns294 0 5083.8610328 +Ra295 ns295 0 5083.8610328 +Ga294 ns294 0 ns295 0 0.0052027889728 +Ga295 ns295 0 ns294 0 -0.0052027889728 +Ca296 ns296 0 1e-012 +Ca297 ns297 0 1e-012 +Ra296 ns296 0 11932.9415219 +Ra297 ns297 0 11932.9415219 +Ga296 ns296 0 ns297 0 0.00543255424918 +Ga297 ns297 0 ns296 0 -0.00543255424918 +Ca298 ns298 0 1e-012 +Ca299 ns299 0 1e-012 +Ra298 ns298 0 2649.73611698 +Ra299 ns299 0 2649.73611698 +Ga298 ns298 0 ns299 0 0.00572768809984 +Ga299 ns299 0 ns298 0 -0.00572768809984 +Ca300 ns300 0 1e-012 +Ca301 ns301 0 1e-012 +Ra300 ns300 0 6440.79899097 +Ra301 ns301 0 6440.79899097 +Ga300 ns300 0 ns301 0 0.00579138648629 +Ga301 ns301 0 ns300 0 -0.00579138648629 +Ca302 ns302 0 1e-012 +Ca303 ns303 0 1e-012 +Ra302 ns302 0 10718.8612946 +Ra303 ns303 0 10718.8612946 +Ga302 ns302 0 ns303 0 0.00588634989311 +Ga303 ns303 0 ns302 0 -0.00588634989311 +Ca304 ns304 0 1e-012 +Ca305 ns305 0 1e-012 +Ra304 ns304 0 7964.88003957 +Ra305 ns305 0 7964.88003957 +Ga304 ns304 0 ns305 0 0.00596997907625 +Ga305 ns305 0 ns304 0 -0.00596997907625 +Ca306 ns306 0 1e-012 +Ca307 ns307 0 1e-012 +Ra306 ns306 0 2611.74770779 +Ra307 ns307 0 2611.74770779 +Ga306 ns306 0 ns307 0 0.0059811572659 +Ga307 ns307 0 ns306 0 -0.0059811572659 +Ca308 ns308 0 1e-012 +Ca309 ns309 0 1e-012 +Ra308 ns308 0 3029.51710274 +Ra309 ns309 0 3029.51710274 +Ga308 ns308 0 ns309 0 -0.00624522385785 +Ga309 ns309 0 ns308 0 0.00624522385785 +Ca310 ns310 0 1e-012 +Ra310 ns310 0 75559446.4424 +Ca311 ns311 0 1e-012 +Ca312 ns312 0 1e-012 +Ra311 ns311 0 1429692.02507 +Ra312 ns312 0 1429692.02507 +Ga311 ns311 0 ns312 0 1.86788534433e-006 +Ga312 ns312 0 ns311 0 -1.86788534433e-006 +Ca313 ns313 0 1e-012 +Ra313 ns313 0 246339.394296 +Ca314 ns314 0 1e-012 +Ca315 ns315 0 1e-012 +Ra314 ns314 0 3140698.95851 +Ra315 ns315 0 3140698.95851 +Ga314 ns314 0 ns315 0 7.09906366399e-006 +Ga315 ns315 0 ns314 0 -7.09906366399e-006 +Ca316 ns316 0 1e-012 +Ca317 ns317 0 1e-012 +Ra316 ns316 0 432178.481825 +Ra317 ns317 0 432178.481825 +Ga316 ns316 0 ns317 0 7.65521128032e-006 +Ga317 ns317 0 ns316 0 -7.65521128032e-006 +Ca318 ns318 0 1e-012 +Ra318 ns318 0 40845.143813 +Ca319 ns319 0 1e-012 +Ra319 ns319 0 15244.7761181 +Ca320 ns320 0 1e-012 +Ra320 ns320 0 8449.43173224 +Ca321 ns321 0 1e-012 +Ra321 ns321 0 3139.44862129 +Ca322 ns322 0 1e-012 +Ca323 ns323 0 1e-012 +Ra322 ns322 0 11944.9771613 +Ra323 ns323 0 11944.9771613 +Ga322 ns322 0 ns323 0 0.000462180399865 +Ga323 ns323 0 ns322 0 -0.000462180399865 +Ca324 ns324 0 1e-012 +Ca325 ns325 0 1e-012 +Ra324 ns324 0 42247.4939429 +Ra325 ns325 0 42247.4939429 +Ga324 ns324 0 ns325 0 0.000693426100266 +Ga325 ns325 0 ns324 0 -0.000693426100266 +Ca326 ns326 0 1e-012 +Ca327 ns327 0 1e-012 +Ra326 ns326 0 39755.901208 +Ra327 ns327 0 39755.901208 +Ga326 ns326 0 ns327 0 0.000761257369333 +Ga327 ns327 0 ns326 0 -0.000761257369333 +Ca328 ns328 0 1e-012 +Ca329 ns329 0 1e-012 +Ra328 ns328 0 21711.3623474 +Ra329 ns329 0 21711.3623474 +Ga328 ns328 0 ns329 0 0.000882812596141 +Ga329 ns329 0 ns328 0 -0.000882812596141 +Ca330 ns330 0 1e-012 +Ca331 ns331 0 1e-012 +Ra330 ns330 0 31406.4073875 +Ra331 ns331 0 31406.4073875 +Ga330 ns330 0 ns331 0 0.0010820924882 +Ga331 ns331 0 ns330 0 -0.0010820924882 +Ca332 ns332 0 1e-012 +Ca333 ns333 0 1e-012 +Ra332 ns332 0 3149.07180722 +Ra333 ns333 0 3149.07180722 +Ga332 ns332 0 ns333 0 0.00121438412928 +Ga333 ns333 0 ns332 0 -0.00121438412928 +Ca334 ns334 0 1e-012 +Ca335 ns335 0 1e-012 +Ra334 ns334 0 2569.48104963 +Ra335 ns335 0 2569.48104963 +Ga334 ns334 0 ns335 0 -0.00120846241795 +Ga335 ns335 0 ns334 0 0.00120846241795 +Ca336 ns336 0 1e-012 +Ra336 ns336 0 702.418450592 +Ca337 ns337 0 1e-012 +Ca338 ns338 0 1e-012 +Ra337 ns337 0 25014.2129071 +Ra338 ns338 0 25014.2129071 +Ga337 ns337 0 ns338 0 0.00152233059114 +Ga338 ns338 0 ns337 0 -0.00152233059114 +Ca339 ns339 0 1e-012 +Ca340 ns340 0 1e-012 +Ra339 ns339 0 21774.9640016 +Ra340 ns340 0 21774.9640016 +Ga339 ns339 0 ns340 0 0.0015688651638 +Ga340 ns340 0 ns339 0 -0.0015688651638 +Ca341 ns341 0 1e-012 +Ca342 ns342 0 1e-012 +Ra341 ns341 0 47567.5330282 +Ra342 ns342 0 47567.5330282 +Ga341 ns341 0 ns342 0 0.0015707458645 +Ga342 ns342 0 ns341 0 -0.0015707458645 +Ca343 ns343 0 1e-012 +Ca344 ns344 0 1e-012 +Ra343 ns343 0 2274.03359868 +Ra344 ns344 0 2274.03359868 +Ga343 ns343 0 ns344 0 0.00166266781711 +Ga344 ns344 0 ns343 0 -0.00166266781711 +Ca345 ns345 0 1e-012 +Ca346 ns346 0 1e-012 +Ra345 ns345 0 35760.6903471 +Ra346 ns346 0 35760.6903471 +Ga345 ns345 0 ns346 0 0.00175118644696 +Ga346 ns346 0 ns345 0 -0.00175118644696 +Ca347 ns347 0 1e-012 +Ca348 ns348 0 1e-012 +Ra347 ns347 0 9906.97610596 +Ra348 ns348 0 9906.97610596 +Ga347 ns347 0 ns348 0 0.00180033453419 +Ga348 ns348 0 ns347 0 -0.00180033453419 +Ca349 ns349 0 1e-012 +Ca350 ns350 0 1e-012 +Ra349 ns349 0 22007.8238421 +Ra350 ns350 0 22007.8238421 +Ga349 ns349 0 ns350 0 0.00184449444316 +Ga350 ns350 0 ns349 0 -0.00184449444316 +Ca351 ns351 0 1e-012 +Ca352 ns352 0 1e-012 +Ra351 ns351 0 30910.1944083 +Ra352 ns352 0 30910.1944083 +Ga351 ns351 0 ns352 0 0.0020789191311 +Ga352 ns352 0 ns351 0 -0.0020789191311 +Ca353 ns353 0 1e-012 +Ca354 ns354 0 1e-012 +Ra353 ns353 0 886.057098121 +Ra354 ns354 0 886.057098121 +Ga353 ns353 0 ns354 0 0.0019302292208 +Ga354 ns354 0 ns353 0 -0.0019302292208 +Ca355 ns355 0 1e-012 +Ca356 ns356 0 1e-012 +Ra355 ns355 0 8767.68764418 +Ra356 ns356 0 8767.68764418 +Ga355 ns355 0 ns356 0 0.00230274466816 +Ga356 ns356 0 ns355 0 -0.00230274466816 +Ca357 ns357 0 1e-012 +Ca358 ns358 0 1e-012 +Ra357 ns357 0 16384.2906969 +Ra358 ns358 0 16384.2906969 +Ga357 ns357 0 ns358 0 0.00251233787856 +Ga358 ns358 0 ns357 0 -0.00251233787856 +Ca359 ns359 0 1e-012 +Ca360 ns360 0 1e-012 +Ra359 ns359 0 21503.7896426 +Ra360 ns360 0 21503.7896426 +Ga359 ns359 0 ns360 0 -0.00260344051006 +Ga360 ns360 0 ns359 0 0.00260344051006 +Ca361 ns361 0 1e-012 +Ca362 ns362 0 1e-012 +Ra361 ns361 0 22825.3651304 +Ra362 ns362 0 22825.3651304 +Ga361 ns361 0 ns362 0 0.00267888417896 +Ga362 ns362 0 ns361 0 -0.00267888417896 +Ca363 ns363 0 1e-012 +Ca364 ns364 0 1e-012 +Ra363 ns363 0 7681.03739833 +Ra364 ns364 0 7681.03739833 +Ga363 ns363 0 ns364 0 0.00294208056419 +Ga364 ns364 0 ns363 0 -0.00294208056419 +Ca365 ns365 0 1e-012 +Ca366 ns366 0 1e-012 +Ra365 ns365 0 11078.985173 +Ra366 ns366 0 11078.985173 +Ga365 ns365 0 ns366 0 0.00304930398407 +Ga366 ns366 0 ns365 0 -0.00304930398407 +Ca367 ns367 0 1e-012 +Ca368 ns368 0 1e-012 +Ra367 ns367 0 2600.01630725 +Ra368 ns368 0 2600.01630725 +Ga367 ns367 0 ns368 0 0.00305535236912 +Ga368 ns368 0 ns367 0 -0.00305535236912 +Ca369 ns369 0 1e-012 +Ca370 ns370 0 1e-012 +Ra369 ns369 0 27128.5023176 +Ra370 ns370 0 27128.5023176 +Ga369 ns369 0 ns370 0 0.00332709985629 +Ga370 ns370 0 ns369 0 -0.00332709985629 +Ca371 ns371 0 1e-012 +Ca372 ns372 0 1e-012 +Ra371 ns371 0 21634.7316013 +Ra372 ns372 0 21634.7316013 +Ga371 ns371 0 ns372 0 0.003450757883 +Ga372 ns372 0 ns371 0 -0.003450757883 +Ca373 ns373 0 1e-012 +Ca374 ns374 0 1e-012 +Ra373 ns373 0 1255.34703842 +Ra374 ns374 0 1255.34703842 +Ga373 ns373 0 ns374 0 0.00337413358794 +Ga374 ns374 0 ns373 0 -0.00337413358794 +Ca375 ns375 0 1e-012 +Ca376 ns376 0 1e-012 +Ra375 ns375 0 16234.7396118 +Ra376 ns376 0 16234.7396118 +Ga375 ns375 0 ns376 0 0.00357951452468 +Ga376 ns376 0 ns375 0 -0.00357951452468 +Ca377 ns377 0 1e-012 +Ca378 ns378 0 1e-012 +Ra377 ns377 0 9432.97056341 +Ra378 ns378 0 9432.97056341 +Ga377 ns377 0 ns378 0 0.00367408923266 +Ga378 ns378 0 ns377 0 -0.00367408923266 +Ca379 ns379 0 1e-012 +Ca380 ns380 0 1e-012 +Ra379 ns379 0 6490.68663673 +Ra380 ns380 0 6490.68663673 +Ga379 ns379 0 ns380 0 0.00373532438761 +Ga380 ns380 0 ns379 0 -0.00373532438761 +Ca381 ns381 0 1e-012 +Ca382 ns382 0 1e-012 +Ra381 ns381 0 9189.9143658 +Ra382 ns382 0 9189.9143658 +Ga381 ns381 0 ns382 0 0.00402784781244 +Ga382 ns382 0 ns381 0 -0.00402784781244 +Ca383 ns383 0 1e-012 +Ca384 ns384 0 1e-012 +Ra383 ns383 0 15134.0602533 +Ra384 ns384 0 15134.0602533 +Ga383 ns383 0 ns384 0 0.00422563870151 +Ga384 ns384 0 ns383 0 -0.00422563870151 +Ca385 ns385 0 1e-012 +Ca386 ns386 0 1e-012 +Ra385 ns385 0 9502.03815934 +Ra386 ns386 0 9502.03815934 +Ga385 ns385 0 ns386 0 0.00438549041759 +Ga386 ns386 0 ns385 0 -0.00438549041759 +Ca387 ns387 0 1e-012 +Ca388 ns388 0 1e-012 +Ra387 ns387 0 1462.27425817 +Ra388 ns388 0 1462.27425817 +Ga387 ns387 0 ns388 0 0.00444962977407 +Ga388 ns388 0 ns387 0 -0.00444962977407 +Ca389 ns389 0 1e-012 +Ca390 ns390 0 1e-012 +Ra389 ns389 0 10431.5635559 +Ra390 ns390 0 10431.5635559 +Ga389 ns389 0 ns390 0 0.00454033573239 +Ga390 ns390 0 ns389 0 -0.00454033573239 +Ca391 ns391 0 1e-012 +Ca392 ns392 0 1e-012 +Ra391 ns391 0 5694.78290457 +Ra392 ns392 0 5694.78290457 +Ga391 ns391 0 ns392 0 0.00485677246494 +Ga392 ns392 0 ns391 0 -0.00485677246494 +Ca393 ns393 0 1e-012 +Ca394 ns394 0 1e-012 +Ra393 ns393 0 6892.95589034 +Ra394 ns394 0 6892.95589034 +Ga393 ns393 0 ns394 0 0.00500916986901 +Ga394 ns394 0 ns393 0 -0.00500916986901 +Ca395 ns395 0 1e-012 +Ca396 ns396 0 1e-012 +Ra395 ns395 0 9744.756895 +Ra396 ns396 0 9744.756895 +Ga395 ns395 0 ns396 0 0.00507968996011 +Ga396 ns396 0 ns395 0 -0.00507968996011 +Ca397 ns397 0 1e-012 +Ca398 ns398 0 1e-012 +Ra397 ns397 0 5083.8610328 +Ra398 ns398 0 5083.8610328 +Ga397 ns397 0 ns398 0 0.0052027889728 +Ga398 ns398 0 ns397 0 -0.0052027889728 +Ca399 ns399 0 1e-012 +Ca400 ns400 0 1e-012 +Ra399 ns399 0 11932.9415219 +Ra400 ns400 0 11932.9415219 +Ga399 ns399 0 ns400 0 0.00543255424918 +Ga400 ns400 0 ns399 0 -0.00543255424918 +Ca401 ns401 0 1e-012 +Ca402 ns402 0 1e-012 +Ra401 ns401 0 2649.73611698 +Ra402 ns402 0 2649.73611698 +Ga401 ns401 0 ns402 0 0.00572768809984 +Ga402 ns402 0 ns401 0 -0.00572768809984 +Ca403 ns403 0 1e-012 +Ca404 ns404 0 1e-012 +Ra403 ns403 0 6440.79899097 +Ra404 ns404 0 6440.79899097 +Ga403 ns403 0 ns404 0 0.00579138648629 +Ga404 ns404 0 ns403 0 -0.00579138648629 +Ca405 ns405 0 1e-012 +Ca406 ns406 0 1e-012 +Ra405 ns405 0 10718.8612946 +Ra406 ns406 0 10718.8612946 +Ga405 ns405 0 ns406 0 0.00588634989311 +Ga406 ns406 0 ns405 0 -0.00588634989311 +Ca407 ns407 0 1e-012 +Ca408 ns408 0 1e-012 +Ra407 ns407 0 7964.88003957 +Ra408 ns408 0 7964.88003957 +Ga407 ns407 0 ns408 0 0.00596997907625 +Ga408 ns408 0 ns407 0 -0.00596997907625 +Ca409 ns409 0 1e-012 +Ca410 ns410 0 1e-012 +Ra409 ns409 0 2611.74770779 +Ra410 ns410 0 2611.74770779 +Ga409 ns409 0 ns410 0 0.0059811572659 +Ga410 ns410 0 ns409 0 -0.0059811572659 +Ca411 ns411 0 1e-012 +Ca412 ns412 0 1e-012 +Ra411 ns411 0 3029.51710274 +Ra412 ns412 0 3029.51710274 +Ga411 ns411 0 ns412 0 -0.00624522385785 +Ga412 ns412 0 ns411 0 0.00624522385785 +Ca413 ns413 0 1e-012 +Ra413 ns413 0 75559446.4424 +Ca414 ns414 0 1e-012 +Ca415 ns415 0 1e-012 +Ra414 ns414 0 1429692.02507 +Ra415 ns415 0 1429692.02507 +Ga414 ns414 0 ns415 0 1.86788534433e-006 +Ga415 ns415 0 ns414 0 -1.86788534433e-006 +Ca416 ns416 0 1e-012 +Ra416 ns416 0 246339.394296 +Ca417 ns417 0 1e-012 +Ca418 ns418 0 1e-012 +Ra417 ns417 0 3140698.95851 +Ra418 ns418 0 3140698.95851 +Ga417 ns417 0 ns418 0 7.09906366399e-006 +Ga418 ns418 0 ns417 0 -7.09906366399e-006 +Ca419 ns419 0 1e-012 +Ca420 ns420 0 1e-012 +Ra419 ns419 0 432178.481825 +Ra420 ns420 0 432178.481825 +Ga419 ns419 0 ns420 0 7.65521128032e-006 +Ga420 ns420 0 ns419 0 -7.65521128032e-006 +Ca421 ns421 0 1e-012 +Ra421 ns421 0 40845.143813 +Ca422 ns422 0 1e-012 +Ra422 ns422 0 15244.7761181 +Ca423 ns423 0 1e-012 +Ra423 ns423 0 8449.43173224 +Ca424 ns424 0 1e-012 +Ra424 ns424 0 3139.44862129 +Ca425 ns425 0 1e-012 +Ca426 ns426 0 1e-012 +Ra425 ns425 0 11944.9771613 +Ra426 ns426 0 11944.9771613 +Ga425 ns425 0 ns426 0 0.000462180399865 +Ga426 ns426 0 ns425 0 -0.000462180399865 +Ca427 ns427 0 1e-012 +Ca428 ns428 0 1e-012 +Ra427 ns427 0 42247.4939429 +Ra428 ns428 0 42247.4939429 +Ga427 ns427 0 ns428 0 0.000693426100266 +Ga428 ns428 0 ns427 0 -0.000693426100266 +Ca429 ns429 0 1e-012 +Ca430 ns430 0 1e-012 +Ra429 ns429 0 39755.901208 +Ra430 ns430 0 39755.901208 +Ga429 ns429 0 ns430 0 0.000761257369333 +Ga430 ns430 0 ns429 0 -0.000761257369333 +Ca431 ns431 0 1e-012 +Ca432 ns432 0 1e-012 +Ra431 ns431 0 21711.3623474 +Ra432 ns432 0 21711.3623474 +Ga431 ns431 0 ns432 0 0.000882812596141 +Ga432 ns432 0 ns431 0 -0.000882812596141 +Ca433 ns433 0 1e-012 +Ca434 ns434 0 1e-012 +Ra433 ns433 0 31406.4073875 +Ra434 ns434 0 31406.4073875 +Ga433 ns433 0 ns434 0 0.0010820924882 +Ga434 ns434 0 ns433 0 -0.0010820924882 +Ca435 ns435 0 1e-012 +Ca436 ns436 0 1e-012 +Ra435 ns435 0 3149.07180722 +Ra436 ns436 0 3149.07180722 +Ga435 ns435 0 ns436 0 0.00121438412928 +Ga436 ns436 0 ns435 0 -0.00121438412928 +Ca437 ns437 0 1e-012 +Ca438 ns438 0 1e-012 +Ra437 ns437 0 2569.48104963 +Ra438 ns438 0 2569.48104963 +Ga437 ns437 0 ns438 0 -0.00120846241795 +Ga438 ns438 0 ns437 0 0.00120846241795 +Ca439 ns439 0 1e-012 +Ra439 ns439 0 702.418450592 +Ca440 ns440 0 1e-012 +Ca441 ns441 0 1e-012 +Ra440 ns440 0 25014.2129071 +Ra441 ns441 0 25014.2129071 +Ga440 ns440 0 ns441 0 0.00152233059114 +Ga441 ns441 0 ns440 0 -0.00152233059114 +Ca442 ns442 0 1e-012 +Ca443 ns443 0 1e-012 +Ra442 ns442 0 21774.9640016 +Ra443 ns443 0 21774.9640016 +Ga442 ns442 0 ns443 0 0.0015688651638 +Ga443 ns443 0 ns442 0 -0.0015688651638 +Ca444 ns444 0 1e-012 +Ca445 ns445 0 1e-012 +Ra444 ns444 0 47567.5330282 +Ra445 ns445 0 47567.5330282 +Ga444 ns444 0 ns445 0 0.0015707458645 +Ga445 ns445 0 ns444 0 -0.0015707458645 +Ca446 ns446 0 1e-012 +Ca447 ns447 0 1e-012 +Ra446 ns446 0 2274.03359868 +Ra447 ns447 0 2274.03359868 +Ga446 ns446 0 ns447 0 0.00166266781711 +Ga447 ns447 0 ns446 0 -0.00166266781711 +Ca448 ns448 0 1e-012 +Ca449 ns449 0 1e-012 +Ra448 ns448 0 35760.6903471 +Ra449 ns449 0 35760.6903471 +Ga448 ns448 0 ns449 0 0.00175118644696 +Ga449 ns449 0 ns448 0 -0.00175118644696 +Ca450 ns450 0 1e-012 +Ca451 ns451 0 1e-012 +Ra450 ns450 0 9906.97610596 +Ra451 ns451 0 9906.97610596 +Ga450 ns450 0 ns451 0 0.00180033453419 +Ga451 ns451 0 ns450 0 -0.00180033453419 +Ca452 ns452 0 1e-012 +Ca453 ns453 0 1e-012 +Ra452 ns452 0 22007.8238421 +Ra453 ns453 0 22007.8238421 +Ga452 ns452 0 ns453 0 0.00184449444316 +Ga453 ns453 0 ns452 0 -0.00184449444316 +Ca454 ns454 0 1e-012 +Ca455 ns455 0 1e-012 +Ra454 ns454 0 30910.1944083 +Ra455 ns455 0 30910.1944083 +Ga454 ns454 0 ns455 0 0.0020789191311 +Ga455 ns455 0 ns454 0 -0.0020789191311 +Ca456 ns456 0 1e-012 +Ca457 ns457 0 1e-012 +Ra456 ns456 0 886.057098121 +Ra457 ns457 0 886.057098121 +Ga456 ns456 0 ns457 0 0.0019302292208 +Ga457 ns457 0 ns456 0 -0.0019302292208 +Ca458 ns458 0 1e-012 +Ca459 ns459 0 1e-012 +Ra458 ns458 0 8767.68764418 +Ra459 ns459 0 8767.68764418 +Ga458 ns458 0 ns459 0 0.00230274466816 +Ga459 ns459 0 ns458 0 -0.00230274466816 +Ca460 ns460 0 1e-012 +Ca461 ns461 0 1e-012 +Ra460 ns460 0 16384.2906969 +Ra461 ns461 0 16384.2906969 +Ga460 ns460 0 ns461 0 0.00251233787856 +Ga461 ns461 0 ns460 0 -0.00251233787856 +Ca462 ns462 0 1e-012 +Ca463 ns463 0 1e-012 +Ra462 ns462 0 21503.7896426 +Ra463 ns463 0 21503.7896426 +Ga462 ns462 0 ns463 0 -0.00260344051006 +Ga463 ns463 0 ns462 0 0.00260344051006 +Ca464 ns464 0 1e-012 +Ca465 ns465 0 1e-012 +Ra464 ns464 0 22825.3651304 +Ra465 ns465 0 22825.3651304 +Ga464 ns464 0 ns465 0 0.00267888417896 +Ga465 ns465 0 ns464 0 -0.00267888417896 +Ca466 ns466 0 1e-012 +Ca467 ns467 0 1e-012 +Ra466 ns466 0 7681.03739833 +Ra467 ns467 0 7681.03739833 +Ga466 ns466 0 ns467 0 0.00294208056419 +Ga467 ns467 0 ns466 0 -0.00294208056419 +Ca468 ns468 0 1e-012 +Ca469 ns469 0 1e-012 +Ra468 ns468 0 11078.985173 +Ra469 ns469 0 11078.985173 +Ga468 ns468 0 ns469 0 0.00304930398407 +Ga469 ns469 0 ns468 0 -0.00304930398407 +Ca470 ns470 0 1e-012 +Ca471 ns471 0 1e-012 +Ra470 ns470 0 2600.01630725 +Ra471 ns471 0 2600.01630725 +Ga470 ns470 0 ns471 0 0.00305535236912 +Ga471 ns471 0 ns470 0 -0.00305535236912 +Ca472 ns472 0 1e-012 +Ca473 ns473 0 1e-012 +Ra472 ns472 0 27128.5023176 +Ra473 ns473 0 27128.5023176 +Ga472 ns472 0 ns473 0 0.00332709985629 +Ga473 ns473 0 ns472 0 -0.00332709985629 +Ca474 ns474 0 1e-012 +Ca475 ns475 0 1e-012 +Ra474 ns474 0 21634.7316013 +Ra475 ns475 0 21634.7316013 +Ga474 ns474 0 ns475 0 0.003450757883 +Ga475 ns475 0 ns474 0 -0.003450757883 +Ca476 ns476 0 1e-012 +Ca477 ns477 0 1e-012 +Ra476 ns476 0 1255.34703842 +Ra477 ns477 0 1255.34703842 +Ga476 ns476 0 ns477 0 0.00337413358794 +Ga477 ns477 0 ns476 0 -0.00337413358794 +Ca478 ns478 0 1e-012 +Ca479 ns479 0 1e-012 +Ra478 ns478 0 16234.7396118 +Ra479 ns479 0 16234.7396118 +Ga478 ns478 0 ns479 0 0.00357951452468 +Ga479 ns479 0 ns478 0 -0.00357951452468 +Ca480 ns480 0 1e-012 +Ca481 ns481 0 1e-012 +Ra480 ns480 0 9432.97056341 +Ra481 ns481 0 9432.97056341 +Ga480 ns480 0 ns481 0 0.00367408923266 +Ga481 ns481 0 ns480 0 -0.00367408923266 +Ca482 ns482 0 1e-012 +Ca483 ns483 0 1e-012 +Ra482 ns482 0 6490.68663673 +Ra483 ns483 0 6490.68663673 +Ga482 ns482 0 ns483 0 0.00373532438761 +Ga483 ns483 0 ns482 0 -0.00373532438761 +Ca484 ns484 0 1e-012 +Ca485 ns485 0 1e-012 +Ra484 ns484 0 9189.9143658 +Ra485 ns485 0 9189.9143658 +Ga484 ns484 0 ns485 0 0.00402784781244 +Ga485 ns485 0 ns484 0 -0.00402784781244 +Ca486 ns486 0 1e-012 +Ca487 ns487 0 1e-012 +Ra486 ns486 0 15134.0602533 +Ra487 ns487 0 15134.0602533 +Ga486 ns486 0 ns487 0 0.00422563870151 +Ga487 ns487 0 ns486 0 -0.00422563870151 +Ca488 ns488 0 1e-012 +Ca489 ns489 0 1e-012 +Ra488 ns488 0 9502.03815934 +Ra489 ns489 0 9502.03815934 +Ga488 ns488 0 ns489 0 0.00438549041759 +Ga489 ns489 0 ns488 0 -0.00438549041759 +Ca490 ns490 0 1e-012 +Ca491 ns491 0 1e-012 +Ra490 ns490 0 1462.27425817 +Ra491 ns491 0 1462.27425817 +Ga490 ns490 0 ns491 0 0.00444962977407 +Ga491 ns491 0 ns490 0 -0.00444962977407 +Ca492 ns492 0 1e-012 +Ca493 ns493 0 1e-012 +Ra492 ns492 0 10431.5635559 +Ra493 ns493 0 10431.5635559 +Ga492 ns492 0 ns493 0 0.00454033573239 +Ga493 ns493 0 ns492 0 -0.00454033573239 +Ca494 ns494 0 1e-012 +Ca495 ns495 0 1e-012 +Ra494 ns494 0 5694.78290457 +Ra495 ns495 0 5694.78290457 +Ga494 ns494 0 ns495 0 0.00485677246494 +Ga495 ns495 0 ns494 0 -0.00485677246494 +Ca496 ns496 0 1e-012 +Ca497 ns497 0 1e-012 +Ra496 ns496 0 6892.95589034 +Ra497 ns497 0 6892.95589034 +Ga496 ns496 0 ns497 0 0.00500916986901 +Ga497 ns497 0 ns496 0 -0.00500916986901 +Ca498 ns498 0 1e-012 +Ca499 ns499 0 1e-012 +Ra498 ns498 0 9744.756895 +Ra499 ns499 0 9744.756895 +Ga498 ns498 0 ns499 0 0.00507968996011 +Ga499 ns499 0 ns498 0 -0.00507968996011 +Ca500 ns500 0 1e-012 +Ca501 ns501 0 1e-012 +Ra500 ns500 0 5083.8610328 +Ra501 ns501 0 5083.8610328 +Ga500 ns500 0 ns501 0 0.0052027889728 +Ga501 ns501 0 ns500 0 -0.0052027889728 +Ca502 ns502 0 1e-012 +Ca503 ns503 0 1e-012 +Ra502 ns502 0 11932.9415219 +Ra503 ns503 0 11932.9415219 +Ga502 ns502 0 ns503 0 0.00543255424918 +Ga503 ns503 0 ns502 0 -0.00543255424918 +Ca504 ns504 0 1e-012 +Ca505 ns505 0 1e-012 +Ra504 ns504 0 2649.73611698 +Ra505 ns505 0 2649.73611698 +Ga504 ns504 0 ns505 0 0.00572768809984 +Ga505 ns505 0 ns504 0 -0.00572768809984 +Ca506 ns506 0 1e-012 +Ca507 ns507 0 1e-012 +Ra506 ns506 0 6440.79899097 +Ra507 ns507 0 6440.79899097 +Ga506 ns506 0 ns507 0 0.00579138648629 +Ga507 ns507 0 ns506 0 -0.00579138648629 +Ca508 ns508 0 1e-012 +Ca509 ns509 0 1e-012 +Ra508 ns508 0 10718.8612946 +Ra509 ns509 0 10718.8612946 +Ga508 ns508 0 ns509 0 0.00588634989311 +Ga509 ns509 0 ns508 0 -0.00588634989311 +Ca510 ns510 0 1e-012 +Ca511 ns511 0 1e-012 +Ra510 ns510 0 7964.88003957 +Ra511 ns511 0 7964.88003957 +Ga510 ns510 0 ns511 0 0.00596997907625 +Ga511 ns511 0 ns510 0 -0.00596997907625 +Ca512 ns512 0 1e-012 +Ca513 ns513 0 1e-012 +Ra512 ns512 0 2611.74770779 +Ra513 ns513 0 2611.74770779 +Ga512 ns512 0 ns513 0 0.0059811572659 +Ga513 ns513 0 ns512 0 -0.0059811572659 +Ca514 ns514 0 1e-012 +Ca515 ns515 0 1e-012 +Ra514 ns514 0 3029.51710274 +Ra515 ns515 0 3029.51710274 +Ga514 ns514 0 ns515 0 -0.00624522385785 +Ga515 ns515 0 ns514 0 0.00624522385785 +Ca516 ns516 0 1e-012 +Ra516 ns516 0 75559446.4424 +Ca517 ns517 0 1e-012 +Ca518 ns518 0 1e-012 +Ra517 ns517 0 1429692.02507 +Ra518 ns518 0 1429692.02507 +Ga517 ns517 0 ns518 0 1.86788534433e-006 +Ga518 ns518 0 ns517 0 -1.86788534433e-006 +Ca519 ns519 0 1e-012 +Ra519 ns519 0 246339.394296 +Ca520 ns520 0 1e-012 +Ca521 ns521 0 1e-012 +Ra520 ns520 0 3140698.95851 +Ra521 ns521 0 3140698.95851 +Ga520 ns520 0 ns521 0 7.09906366399e-006 +Ga521 ns521 0 ns520 0 -7.09906366399e-006 +Ca522 ns522 0 1e-012 +Ca523 ns523 0 1e-012 +Ra522 ns522 0 432178.481825 +Ra523 ns523 0 432178.481825 +Ga522 ns522 0 ns523 0 7.65521128032e-006 +Ga523 ns523 0 ns522 0 -7.65521128032e-006 +Ca524 ns524 0 1e-012 +Ra524 ns524 0 40845.143813 +Ca525 ns525 0 1e-012 +Ra525 ns525 0 15244.7761181 +Ca526 ns526 0 1e-012 +Ra526 ns526 0 8449.43173224 +Ca527 ns527 0 1e-012 +Ra527 ns527 0 3139.44862129 +Ca528 ns528 0 1e-012 +Ca529 ns529 0 1e-012 +Ra528 ns528 0 11944.9771613 +Ra529 ns529 0 11944.9771613 +Ga528 ns528 0 ns529 0 0.000462180399865 +Ga529 ns529 0 ns528 0 -0.000462180399865 +Ca530 ns530 0 1e-012 +Ca531 ns531 0 1e-012 +Ra530 ns530 0 42247.4939429 +Ra531 ns531 0 42247.4939429 +Ga530 ns530 0 ns531 0 0.000693426100266 +Ga531 ns531 0 ns530 0 -0.000693426100266 +Ca532 ns532 0 1e-012 +Ca533 ns533 0 1e-012 +Ra532 ns532 0 39755.901208 +Ra533 ns533 0 39755.901208 +Ga532 ns532 0 ns533 0 0.000761257369333 +Ga533 ns533 0 ns532 0 -0.000761257369333 +Ca534 ns534 0 1e-012 +Ca535 ns535 0 1e-012 +Ra534 ns534 0 21711.3623474 +Ra535 ns535 0 21711.3623474 +Ga534 ns534 0 ns535 0 0.000882812596141 +Ga535 ns535 0 ns534 0 -0.000882812596141 +Ca536 ns536 0 1e-012 +Ca537 ns537 0 1e-012 +Ra536 ns536 0 31406.4073875 +Ra537 ns537 0 31406.4073875 +Ga536 ns536 0 ns537 0 0.0010820924882 +Ga537 ns537 0 ns536 0 -0.0010820924882 +Ca538 ns538 0 1e-012 +Ca539 ns539 0 1e-012 +Ra538 ns538 0 3149.07180722 +Ra539 ns539 0 3149.07180722 +Ga538 ns538 0 ns539 0 0.00121438412928 +Ga539 ns539 0 ns538 0 -0.00121438412928 +Ca540 ns540 0 1e-012 +Ca541 ns541 0 1e-012 +Ra540 ns540 0 2569.48104963 +Ra541 ns541 0 2569.48104963 +Ga540 ns540 0 ns541 0 -0.00120846241795 +Ga541 ns541 0 ns540 0 0.00120846241795 +Ca542 ns542 0 1e-012 +Ra542 ns542 0 702.418450592 +Ca543 ns543 0 1e-012 +Ca544 ns544 0 1e-012 +Ra543 ns543 0 25014.2129071 +Ra544 ns544 0 25014.2129071 +Ga543 ns543 0 ns544 0 0.00152233059114 +Ga544 ns544 0 ns543 0 -0.00152233059114 +Ca545 ns545 0 1e-012 +Ca546 ns546 0 1e-012 +Ra545 ns545 0 21774.9640016 +Ra546 ns546 0 21774.9640016 +Ga545 ns545 0 ns546 0 0.0015688651638 +Ga546 ns546 0 ns545 0 -0.0015688651638 +Ca547 ns547 0 1e-012 +Ca548 ns548 0 1e-012 +Ra547 ns547 0 47567.5330282 +Ra548 ns548 0 47567.5330282 +Ga547 ns547 0 ns548 0 0.0015707458645 +Ga548 ns548 0 ns547 0 -0.0015707458645 +Ca549 ns549 0 1e-012 +Ca550 ns550 0 1e-012 +Ra549 ns549 0 2274.03359868 +Ra550 ns550 0 2274.03359868 +Ga549 ns549 0 ns550 0 0.00166266781711 +Ga550 ns550 0 ns549 0 -0.00166266781711 +Ca551 ns551 0 1e-012 +Ca552 ns552 0 1e-012 +Ra551 ns551 0 35760.6903471 +Ra552 ns552 0 35760.6903471 +Ga551 ns551 0 ns552 0 0.00175118644696 +Ga552 ns552 0 ns551 0 -0.00175118644696 +Ca553 ns553 0 1e-012 +Ca554 ns554 0 1e-012 +Ra553 ns553 0 9906.97610596 +Ra554 ns554 0 9906.97610596 +Ga553 ns553 0 ns554 0 0.00180033453419 +Ga554 ns554 0 ns553 0 -0.00180033453419 +Ca555 ns555 0 1e-012 +Ca556 ns556 0 1e-012 +Ra555 ns555 0 22007.8238421 +Ra556 ns556 0 22007.8238421 +Ga555 ns555 0 ns556 0 0.00184449444316 +Ga556 ns556 0 ns555 0 -0.00184449444316 +Ca557 ns557 0 1e-012 +Ca558 ns558 0 1e-012 +Ra557 ns557 0 30910.1944083 +Ra558 ns558 0 30910.1944083 +Ga557 ns557 0 ns558 0 0.0020789191311 +Ga558 ns558 0 ns557 0 -0.0020789191311 +Ca559 ns559 0 1e-012 +Ca560 ns560 0 1e-012 +Ra559 ns559 0 886.057098121 +Ra560 ns560 0 886.057098121 +Ga559 ns559 0 ns560 0 0.0019302292208 +Ga560 ns560 0 ns559 0 -0.0019302292208 +Ca561 ns561 0 1e-012 +Ca562 ns562 0 1e-012 +Ra561 ns561 0 8767.68764418 +Ra562 ns562 0 8767.68764418 +Ga561 ns561 0 ns562 0 0.00230274466816 +Ga562 ns562 0 ns561 0 -0.00230274466816 +Ca563 ns563 0 1e-012 +Ca564 ns564 0 1e-012 +Ra563 ns563 0 16384.2906969 +Ra564 ns564 0 16384.2906969 +Ga563 ns563 0 ns564 0 0.00251233787856 +Ga564 ns564 0 ns563 0 -0.00251233787856 +Ca565 ns565 0 1e-012 +Ca566 ns566 0 1e-012 +Ra565 ns565 0 21503.7896426 +Ra566 ns566 0 21503.7896426 +Ga565 ns565 0 ns566 0 -0.00260344051006 +Ga566 ns566 0 ns565 0 0.00260344051006 +Ca567 ns567 0 1e-012 +Ca568 ns568 0 1e-012 +Ra567 ns567 0 22825.3651304 +Ra568 ns568 0 22825.3651304 +Ga567 ns567 0 ns568 0 0.00267888417896 +Ga568 ns568 0 ns567 0 -0.00267888417896 +Ca569 ns569 0 1e-012 +Ca570 ns570 0 1e-012 +Ra569 ns569 0 7681.03739833 +Ra570 ns570 0 7681.03739833 +Ga569 ns569 0 ns570 0 0.00294208056419 +Ga570 ns570 0 ns569 0 -0.00294208056419 +Ca571 ns571 0 1e-012 +Ca572 ns572 0 1e-012 +Ra571 ns571 0 11078.985173 +Ra572 ns572 0 11078.985173 +Ga571 ns571 0 ns572 0 0.00304930398407 +Ga572 ns572 0 ns571 0 -0.00304930398407 +Ca573 ns573 0 1e-012 +Ca574 ns574 0 1e-012 +Ra573 ns573 0 2600.01630725 +Ra574 ns574 0 2600.01630725 +Ga573 ns573 0 ns574 0 0.00305535236912 +Ga574 ns574 0 ns573 0 -0.00305535236912 +Ca575 ns575 0 1e-012 +Ca576 ns576 0 1e-012 +Ra575 ns575 0 27128.5023176 +Ra576 ns576 0 27128.5023176 +Ga575 ns575 0 ns576 0 0.00332709985629 +Ga576 ns576 0 ns575 0 -0.00332709985629 +Ca577 ns577 0 1e-012 +Ca578 ns578 0 1e-012 +Ra577 ns577 0 21634.7316013 +Ra578 ns578 0 21634.7316013 +Ga577 ns577 0 ns578 0 0.003450757883 +Ga578 ns578 0 ns577 0 -0.003450757883 +Ca579 ns579 0 1e-012 +Ca580 ns580 0 1e-012 +Ra579 ns579 0 1255.34703842 +Ra580 ns580 0 1255.34703842 +Ga579 ns579 0 ns580 0 0.00337413358794 +Ga580 ns580 0 ns579 0 -0.00337413358794 +Ca581 ns581 0 1e-012 +Ca582 ns582 0 1e-012 +Ra581 ns581 0 16234.7396118 +Ra582 ns582 0 16234.7396118 +Ga581 ns581 0 ns582 0 0.00357951452468 +Ga582 ns582 0 ns581 0 -0.00357951452468 +Ca583 ns583 0 1e-012 +Ca584 ns584 0 1e-012 +Ra583 ns583 0 9432.97056341 +Ra584 ns584 0 9432.97056341 +Ga583 ns583 0 ns584 0 0.00367408923266 +Ga584 ns584 0 ns583 0 -0.00367408923266 +Ca585 ns585 0 1e-012 +Ca586 ns586 0 1e-012 +Ra585 ns585 0 6490.68663673 +Ra586 ns586 0 6490.68663673 +Ga585 ns585 0 ns586 0 0.00373532438761 +Ga586 ns586 0 ns585 0 -0.00373532438761 +Ca587 ns587 0 1e-012 +Ca588 ns588 0 1e-012 +Ra587 ns587 0 9189.9143658 +Ra588 ns588 0 9189.9143658 +Ga587 ns587 0 ns588 0 0.00402784781244 +Ga588 ns588 0 ns587 0 -0.00402784781244 +Ca589 ns589 0 1e-012 +Ca590 ns590 0 1e-012 +Ra589 ns589 0 15134.0602533 +Ra590 ns590 0 15134.0602533 +Ga589 ns589 0 ns590 0 0.00422563870151 +Ga590 ns590 0 ns589 0 -0.00422563870151 +Ca591 ns591 0 1e-012 +Ca592 ns592 0 1e-012 +Ra591 ns591 0 9502.03815934 +Ra592 ns592 0 9502.03815934 +Ga591 ns591 0 ns592 0 0.00438549041759 +Ga592 ns592 0 ns591 0 -0.00438549041759 +Ca593 ns593 0 1e-012 +Ca594 ns594 0 1e-012 +Ra593 ns593 0 1462.27425817 +Ra594 ns594 0 1462.27425817 +Ga593 ns593 0 ns594 0 0.00444962977407 +Ga594 ns594 0 ns593 0 -0.00444962977407 +Ca595 ns595 0 1e-012 +Ca596 ns596 0 1e-012 +Ra595 ns595 0 10431.5635559 +Ra596 ns596 0 10431.5635559 +Ga595 ns595 0 ns596 0 0.00454033573239 +Ga596 ns596 0 ns595 0 -0.00454033573239 +Ca597 ns597 0 1e-012 +Ca598 ns598 0 1e-012 +Ra597 ns597 0 5694.78290457 +Ra598 ns598 0 5694.78290457 +Ga597 ns597 0 ns598 0 0.00485677246494 +Ga598 ns598 0 ns597 0 -0.00485677246494 +Ca599 ns599 0 1e-012 +Ca600 ns600 0 1e-012 +Ra599 ns599 0 6892.95589034 +Ra600 ns600 0 6892.95589034 +Ga599 ns599 0 ns600 0 0.00500916986901 +Ga600 ns600 0 ns599 0 -0.00500916986901 +Ca601 ns601 0 1e-012 +Ca602 ns602 0 1e-012 +Ra601 ns601 0 9744.756895 +Ra602 ns602 0 9744.756895 +Ga601 ns601 0 ns602 0 0.00507968996011 +Ga602 ns602 0 ns601 0 -0.00507968996011 +Ca603 ns603 0 1e-012 +Ca604 ns604 0 1e-012 +Ra603 ns603 0 5083.8610328 +Ra604 ns604 0 5083.8610328 +Ga603 ns603 0 ns604 0 0.0052027889728 +Ga604 ns604 0 ns603 0 -0.0052027889728 +Ca605 ns605 0 1e-012 +Ca606 ns606 0 1e-012 +Ra605 ns605 0 11932.9415219 +Ra606 ns606 0 11932.9415219 +Ga605 ns605 0 ns606 0 0.00543255424918 +Ga606 ns606 0 ns605 0 -0.00543255424918 +Ca607 ns607 0 1e-012 +Ca608 ns608 0 1e-012 +Ra607 ns607 0 2649.73611698 +Ra608 ns608 0 2649.73611698 +Ga607 ns607 0 ns608 0 0.00572768809984 +Ga608 ns608 0 ns607 0 -0.00572768809984 +Ca609 ns609 0 1e-012 +Ca610 ns610 0 1e-012 +Ra609 ns609 0 6440.79899097 +Ra610 ns610 0 6440.79899097 +Ga609 ns609 0 ns610 0 0.00579138648629 +Ga610 ns610 0 ns609 0 -0.00579138648629 +Ca611 ns611 0 1e-012 +Ca612 ns612 0 1e-012 +Ra611 ns611 0 10718.8612946 +Ra612 ns612 0 10718.8612946 +Ga611 ns611 0 ns612 0 0.00588634989311 +Ga612 ns612 0 ns611 0 -0.00588634989311 +Ca613 ns613 0 1e-012 +Ca614 ns614 0 1e-012 +Ra613 ns613 0 7964.88003957 +Ra614 ns614 0 7964.88003957 +Ga613 ns613 0 ns614 0 0.00596997907625 +Ga614 ns614 0 ns613 0 -0.00596997907625 +Ca615 ns615 0 1e-012 +Ca616 ns616 0 1e-012 +Ra615 ns615 0 2611.74770779 +Ra616 ns616 0 2611.74770779 +Ga615 ns615 0 ns616 0 0.0059811572659 +Ga616 ns616 0 ns615 0 -0.0059811572659 +Ca617 ns617 0 1e-012 +Ca618 ns618 0 1e-012 +Ra617 ns617 0 3029.51710274 +Ra618 ns618 0 3029.51710274 +Ga617 ns617 0 ns618 0 -0.00624522385785 +Ga618 ns618 0 ns617 0 0.00624522385785 + +Gb1_1 ns1 0 ni1 0 1.32346125744e-008 +Gb2_1 ns2 0 ni1 0 2.12980301281e-006 +Gb4_1 ns4 0 ni1 0 4.05944003742e-006 +Gb5_1 ns5 0 ni1 0 7.11334425917e-006 +Gb7_1 ns7 0 ni1 0 8.35459664392e-006 +Gb9_1 ns9 0 ni1 0 2.44827146301e-005 +Gb10_1 ns10 0 ni1 0 6.55962404597e-005 +Gb11_1 ns11 0 ni1 0 0.000118351154455 +Gb12_1 ns12 0 ni1 0 0.000318527270432 +Gb13_1 ns13 0 ni1 0 0.000477344541376 +Gb15_1 ns15 0 ni1 0 0.000694234075243 +Gb17_1 ns17 0 ni1 0 0.000762088492302 +Gb19_1 ns19 0 ni1 0 0.000885215615823 +Gb21_1 ns21 0 ni1 0 0.00108302940084 +Gb23_1 ns23 0 ni1 0 0.0012974224943 +Gb25_1 ns25 0 ni1 0 0.00133379847068 +Gb27_1 ns27 0 ni1 0 0.0014236528086 +Gb28_1 ns28 0 ni1 0 0.00152338041719 +Gb30_1 ns30 0 ni1 0 0.00157020947398 +Gb32_1 ns32 0 ni1 0 0.00157102723128 +Gb34_1 ns34 0 ni1 0 0.00177897345171 +Gb36_1 ns36 0 ni1 0 0.00175163298229 +Gb38_1 ns38 0 ni1 0 0.00180599385817 +Gb40_1 ns40 0 ni1 0 0.00184561379971 +Gb42_1 ns42 0 ni1 0 0.0020794225841 +Gb44_1 ns44 0 ni1 0 0.00259011336935 +Gb46_1 ns46 0 ni1 0 0.00230839383077 +Gb48_1 ns48 0 ni1 0 0.00251382062423 +Gb50_1 ns50 0 ni1 0 0.00260427116822 +Gb52_1 ns52 0 ni1 0 0.00267960066972 +Gb54_1 ns54 0 ni1 0 0.00294784166772 +Gb56_1 ns56 0 ni1 0 0.00305197575559 +Gb58_1 ns58 0 ni1 0 0.00310376810668 +Gb60_1 ns60 0 ni1 0 0.00332750825327 +Gb62_1 ns62 0 ni1 0 0.00345137701391 +Gb64_1 ns64 0 ni1 0 0.00356219951633 +Gb66_1 ns66 0 ni1 0 0.00358057447428 +Gb68_1 ns68 0 ni1 0 0.00367714804858 +Gb70_1 ns70 0 ni1 0 0.00374167901941 +Gb72_1 ns72 0 ni1 0 0.00403078751924 +Gb74_1 ns74 0 ni1 0 0.00422667193083 +Gb76_1 ns76 0 ni1 0 0.00438801592294 +Gb78_1 ns78 0 ni1 0 0.0045547335825 +Gb80_1 ns80 0 ni1 0 0.00454235974501 +Gb82_1 ns82 0 ni1 0 0.00486312135632 +Gb84_1 ns84 0 ni1 0 0.0050133715516 +Gb86_1 ns86 0 ni1 0 0.00508176306262 +Gb88_1 ns88 0 ni1 0 0.00521022560748 +Gb90_1 ns90 0 ni1 0 0.00543384695857 +Gb92_1 ns92 0 ni1 0 0.00575255464146 +Gb94_1 ns94 0 ni1 0 0.0057955488302 +Gb96_1 ns96 0 ni1 0 0.00588782851328 +Gb98_1 ns98 0 ni1 0 0.0059726194701 +Gb100_1 ns100 0 ni1 0 0.00600566777511 +Gb102_1 ns102 0 ni1 0 0.00626267023163 +Gb104_2 ns104 0 ni2 0 1.32346125744e-008 +Gb105_2 ns105 0 ni2 0 2.12980301281e-006 +Gb107_2 ns107 0 ni2 0 4.05944003742e-006 +Gb108_2 ns108 0 ni2 0 7.11334425917e-006 +Gb110_2 ns110 0 ni2 0 8.35459664392e-006 +Gb112_2 ns112 0 ni2 0 2.44827146301e-005 +Gb113_2 ns113 0 ni2 0 6.55962404597e-005 +Gb114_2 ns114 0 ni2 0 0.000118351154455 +Gb115_2 ns115 0 ni2 0 0.000318527270432 +Gb116_2 ns116 0 ni2 0 0.000477344541376 +Gb118_2 ns118 0 ni2 0 0.000694234075243 +Gb120_2 ns120 0 ni2 0 0.000762088492302 +Gb122_2 ns122 0 ni2 0 0.000885215615823 +Gb124_2 ns124 0 ni2 0 0.00108302940084 +Gb126_2 ns126 0 ni2 0 0.0012974224943 +Gb128_2 ns128 0 ni2 0 0.00133379847068 +Gb130_2 ns130 0 ni2 0 0.0014236528086 +Gb131_2 ns131 0 ni2 0 0.00152338041719 +Gb133_2 ns133 0 ni2 0 0.00157020947398 +Gb135_2 ns135 0 ni2 0 0.00157102723128 +Gb137_2 ns137 0 ni2 0 0.00177897345171 +Gb139_2 ns139 0 ni2 0 0.00175163298229 +Gb141_2 ns141 0 ni2 0 0.00180599385817 +Gb143_2 ns143 0 ni2 0 0.00184561379971 +Gb145_2 ns145 0 ni2 0 0.0020794225841 +Gb147_2 ns147 0 ni2 0 0.00259011336935 +Gb149_2 ns149 0 ni2 0 0.00230839383077 +Gb151_2 ns151 0 ni2 0 0.00251382062423 +Gb153_2 ns153 0 ni2 0 0.00260427116822 +Gb155_2 ns155 0 ni2 0 0.00267960066972 +Gb157_2 ns157 0 ni2 0 0.00294784166772 +Gb159_2 ns159 0 ni2 0 0.00305197575559 +Gb161_2 ns161 0 ni2 0 0.00310376810668 +Gb163_2 ns163 0 ni2 0 0.00332750825327 +Gb165_2 ns165 0 ni2 0 0.00345137701391 +Gb167_2 ns167 0 ni2 0 0.00356219951633 +Gb169_2 ns169 0 ni2 0 0.00358057447428 +Gb171_2 ns171 0 ni2 0 0.00367714804858 +Gb173_2 ns173 0 ni2 0 0.00374167901941 +Gb175_2 ns175 0 ni2 0 0.00403078751924 +Gb177_2 ns177 0 ni2 0 0.00422667193083 +Gb179_2 ns179 0 ni2 0 0.00438801592294 +Gb181_2 ns181 0 ni2 0 0.0045547335825 +Gb183_2 ns183 0 ni2 0 0.00454235974501 +Gb185_2 ns185 0 ni2 0 0.00486312135632 +Gb187_2 ns187 0 ni2 0 0.0050133715516 +Gb189_2 ns189 0 ni2 0 0.00508176306262 +Gb191_2 ns191 0 ni2 0 0.00521022560748 +Gb193_2 ns193 0 ni2 0 0.00543384695857 +Gb195_2 ns195 0 ni2 0 0.00575255464146 +Gb197_2 ns197 0 ni2 0 0.0057955488302 +Gb199_2 ns199 0 ni2 0 0.00588782851328 +Gb201_2 ns201 0 ni2 0 0.0059726194701 +Gb203_2 ns203 0 ni2 0 0.00600566777511 +Gb205_2 ns205 0 ni2 0 0.00626267023163 +Gb207_3 ns207 0 ni3 0 1.32346125744e-008 +Gb208_3 ns208 0 ni3 0 2.12980301281e-006 +Gb210_3 ns210 0 ni3 0 4.05944003742e-006 +Gb211_3 ns211 0 ni3 0 7.11334425917e-006 +Gb213_3 ns213 0 ni3 0 8.35459664392e-006 +Gb215_3 ns215 0 ni3 0 2.44827146301e-005 +Gb216_3 ns216 0 ni3 0 6.55962404597e-005 +Gb217_3 ns217 0 ni3 0 0.000118351154455 +Gb218_3 ns218 0 ni3 0 0.000318527270432 +Gb219_3 ns219 0 ni3 0 0.000477344541376 +Gb221_3 ns221 0 ni3 0 0.000694234075243 +Gb223_3 ns223 0 ni3 0 0.000762088492302 +Gb225_3 ns225 0 ni3 0 0.000885215615823 +Gb227_3 ns227 0 ni3 0 0.00108302940084 +Gb229_3 ns229 0 ni3 0 0.0012974224943 +Gb231_3 ns231 0 ni3 0 0.00133379847068 +Gb233_3 ns233 0 ni3 0 0.0014236528086 +Gb234_3 ns234 0 ni3 0 0.00152338041719 +Gb236_3 ns236 0 ni3 0 0.00157020947398 +Gb238_3 ns238 0 ni3 0 0.00157102723128 +Gb240_3 ns240 0 ni3 0 0.00177897345171 +Gb242_3 ns242 0 ni3 0 0.00175163298229 +Gb244_3 ns244 0 ni3 0 0.00180599385817 +Gb246_3 ns246 0 ni3 0 0.00184561379971 +Gb248_3 ns248 0 ni3 0 0.0020794225841 +Gb250_3 ns250 0 ni3 0 0.00259011336935 +Gb252_3 ns252 0 ni3 0 0.00230839383077 +Gb254_3 ns254 0 ni3 0 0.00251382062423 +Gb256_3 ns256 0 ni3 0 0.00260427116822 +Gb258_3 ns258 0 ni3 0 0.00267960066972 +Gb260_3 ns260 0 ni3 0 0.00294784166772 +Gb262_3 ns262 0 ni3 0 0.00305197575559 +Gb264_3 ns264 0 ni3 0 0.00310376810668 +Gb266_3 ns266 0 ni3 0 0.00332750825327 +Gb268_3 ns268 0 ni3 0 0.00345137701391 +Gb270_3 ns270 0 ni3 0 0.00356219951633 +Gb272_3 ns272 0 ni3 0 0.00358057447428 +Gb274_3 ns274 0 ni3 0 0.00367714804858 +Gb276_3 ns276 0 ni3 0 0.00374167901941 +Gb278_3 ns278 0 ni3 0 0.00403078751924 +Gb280_3 ns280 0 ni3 0 0.00422667193083 +Gb282_3 ns282 0 ni3 0 0.00438801592294 +Gb284_3 ns284 0 ni3 0 0.0045547335825 +Gb286_3 ns286 0 ni3 0 0.00454235974501 +Gb288_3 ns288 0 ni3 0 0.00486312135632 +Gb290_3 ns290 0 ni3 0 0.0050133715516 +Gb292_3 ns292 0 ni3 0 0.00508176306262 +Gb294_3 ns294 0 ni3 0 0.00521022560748 +Gb296_3 ns296 0 ni3 0 0.00543384695857 +Gb298_3 ns298 0 ni3 0 0.00575255464146 +Gb300_3 ns300 0 ni3 0 0.0057955488302 +Gb302_3 ns302 0 ni3 0 0.00588782851328 +Gb304_3 ns304 0 ni3 0 0.0059726194701 +Gb306_3 ns306 0 ni3 0 0.00600566777511 +Gb308_3 ns308 0 ni3 0 0.00626267023163 +Gb310_4 ns310 0 ni4 0 1.32346125744e-008 +Gb311_4 ns311 0 ni4 0 2.12980301281e-006 +Gb313_4 ns313 0 ni4 0 4.05944003742e-006 +Gb314_4 ns314 0 ni4 0 7.11334425917e-006 +Gb316_4 ns316 0 ni4 0 8.35459664392e-006 +Gb318_4 ns318 0 ni4 0 2.44827146301e-005 +Gb319_4 ns319 0 ni4 0 6.55962404597e-005 +Gb320_4 ns320 0 ni4 0 0.000118351154455 +Gb321_4 ns321 0 ni4 0 0.000318527270432 +Gb322_4 ns322 0 ni4 0 0.000477344541376 +Gb324_4 ns324 0 ni4 0 0.000694234075243 +Gb326_4 ns326 0 ni4 0 0.000762088492302 +Gb328_4 ns328 0 ni4 0 0.000885215615823 +Gb330_4 ns330 0 ni4 0 0.00108302940084 +Gb332_4 ns332 0 ni4 0 0.0012974224943 +Gb334_4 ns334 0 ni4 0 0.00133379847068 +Gb336_4 ns336 0 ni4 0 0.0014236528086 +Gb337_4 ns337 0 ni4 0 0.00152338041719 +Gb339_4 ns339 0 ni4 0 0.00157020947398 +Gb341_4 ns341 0 ni4 0 0.00157102723128 +Gb343_4 ns343 0 ni4 0 0.00177897345171 +Gb345_4 ns345 0 ni4 0 0.00175163298229 +Gb347_4 ns347 0 ni4 0 0.00180599385817 +Gb349_4 ns349 0 ni4 0 0.00184561379971 +Gb351_4 ns351 0 ni4 0 0.0020794225841 +Gb353_4 ns353 0 ni4 0 0.00259011336935 +Gb355_4 ns355 0 ni4 0 0.00230839383077 +Gb357_4 ns357 0 ni4 0 0.00251382062423 +Gb359_4 ns359 0 ni4 0 0.00260427116822 +Gb361_4 ns361 0 ni4 0 0.00267960066972 +Gb363_4 ns363 0 ni4 0 0.00294784166772 +Gb365_4 ns365 0 ni4 0 0.00305197575559 +Gb367_4 ns367 0 ni4 0 0.00310376810668 +Gb369_4 ns369 0 ni4 0 0.00332750825327 +Gb371_4 ns371 0 ni4 0 0.00345137701391 +Gb373_4 ns373 0 ni4 0 0.00356219951633 +Gb375_4 ns375 0 ni4 0 0.00358057447428 +Gb377_4 ns377 0 ni4 0 0.00367714804858 +Gb379_4 ns379 0 ni4 0 0.00374167901941 +Gb381_4 ns381 0 ni4 0 0.00403078751924 +Gb383_4 ns383 0 ni4 0 0.00422667193083 +Gb385_4 ns385 0 ni4 0 0.00438801592294 +Gb387_4 ns387 0 ni4 0 0.0045547335825 +Gb389_4 ns389 0 ni4 0 0.00454235974501 +Gb391_4 ns391 0 ni4 0 0.00486312135632 +Gb393_4 ns393 0 ni4 0 0.0050133715516 +Gb395_4 ns395 0 ni4 0 0.00508176306262 +Gb397_4 ns397 0 ni4 0 0.00521022560748 +Gb399_4 ns399 0 ni4 0 0.00543384695857 +Gb401_4 ns401 0 ni4 0 0.00575255464146 +Gb403_4 ns403 0 ni4 0 0.0057955488302 +Gb405_4 ns405 0 ni4 0 0.00588782851328 +Gb407_4 ns407 0 ni4 0 0.0059726194701 +Gb409_4 ns409 0 ni4 0 0.00600566777511 +Gb411_4 ns411 0 ni4 0 0.00626267023163 +Gb413_5 ns413 0 ni5 0 1.32346125744e-008 +Gb414_5 ns414 0 ni5 0 2.12980301281e-006 +Gb416_5 ns416 0 ni5 0 4.05944003742e-006 +Gb417_5 ns417 0 ni5 0 7.11334425917e-006 +Gb419_5 ns419 0 ni5 0 8.35459664392e-006 +Gb421_5 ns421 0 ni5 0 2.44827146301e-005 +Gb422_5 ns422 0 ni5 0 6.55962404597e-005 +Gb423_5 ns423 0 ni5 0 0.000118351154455 +Gb424_5 ns424 0 ni5 0 0.000318527270432 +Gb425_5 ns425 0 ni5 0 0.000477344541376 +Gb427_5 ns427 0 ni5 0 0.000694234075243 +Gb429_5 ns429 0 ni5 0 0.000762088492302 +Gb431_5 ns431 0 ni5 0 0.000885215615823 +Gb433_5 ns433 0 ni5 0 0.00108302940084 +Gb435_5 ns435 0 ni5 0 0.0012974224943 +Gb437_5 ns437 0 ni5 0 0.00133379847068 +Gb439_5 ns439 0 ni5 0 0.0014236528086 +Gb440_5 ns440 0 ni5 0 0.00152338041719 +Gb442_5 ns442 0 ni5 0 0.00157020947398 +Gb444_5 ns444 0 ni5 0 0.00157102723128 +Gb446_5 ns446 0 ni5 0 0.00177897345171 +Gb448_5 ns448 0 ni5 0 0.00175163298229 +Gb450_5 ns450 0 ni5 0 0.00180599385817 +Gb452_5 ns452 0 ni5 0 0.00184561379971 +Gb454_5 ns454 0 ni5 0 0.0020794225841 +Gb456_5 ns456 0 ni5 0 0.00259011336935 +Gb458_5 ns458 0 ni5 0 0.00230839383077 +Gb460_5 ns460 0 ni5 0 0.00251382062423 +Gb462_5 ns462 0 ni5 0 0.00260427116822 +Gb464_5 ns464 0 ni5 0 0.00267960066972 +Gb466_5 ns466 0 ni5 0 0.00294784166772 +Gb468_5 ns468 0 ni5 0 0.00305197575559 +Gb470_5 ns470 0 ni5 0 0.00310376810668 +Gb472_5 ns472 0 ni5 0 0.00332750825327 +Gb474_5 ns474 0 ni5 0 0.00345137701391 +Gb476_5 ns476 0 ni5 0 0.00356219951633 +Gb478_5 ns478 0 ni5 0 0.00358057447428 +Gb480_5 ns480 0 ni5 0 0.00367714804858 +Gb482_5 ns482 0 ni5 0 0.00374167901941 +Gb484_5 ns484 0 ni5 0 0.00403078751924 +Gb486_5 ns486 0 ni5 0 0.00422667193083 +Gb488_5 ns488 0 ni5 0 0.00438801592294 +Gb490_5 ns490 0 ni5 0 0.0045547335825 +Gb492_5 ns492 0 ni5 0 0.00454235974501 +Gb494_5 ns494 0 ni5 0 0.00486312135632 +Gb496_5 ns496 0 ni5 0 0.0050133715516 +Gb498_5 ns498 0 ni5 0 0.00508176306262 +Gb500_5 ns500 0 ni5 0 0.00521022560748 +Gb502_5 ns502 0 ni5 0 0.00543384695857 +Gb504_5 ns504 0 ni5 0 0.00575255464146 +Gb506_5 ns506 0 ni5 0 0.0057955488302 +Gb508_5 ns508 0 ni5 0 0.00588782851328 +Gb510_5 ns510 0 ni5 0 0.0059726194701 +Gb512_5 ns512 0 ni5 0 0.00600566777511 +Gb514_5 ns514 0 ni5 0 0.00626267023163 +Gb516_6 ns516 0 ni6 0 1.32346125744e-008 +Gb517_6 ns517 0 ni6 0 2.12980301281e-006 +Gb519_6 ns519 0 ni6 0 4.05944003742e-006 +Gb520_6 ns520 0 ni6 0 7.11334425917e-006 +Gb522_6 ns522 0 ni6 0 8.35459664392e-006 +Gb524_6 ns524 0 ni6 0 2.44827146301e-005 +Gb525_6 ns525 0 ni6 0 6.55962404597e-005 +Gb526_6 ns526 0 ni6 0 0.000118351154455 +Gb527_6 ns527 0 ni6 0 0.000318527270432 +Gb528_6 ns528 0 ni6 0 0.000477344541376 +Gb530_6 ns530 0 ni6 0 0.000694234075243 +Gb532_6 ns532 0 ni6 0 0.000762088492302 +Gb534_6 ns534 0 ni6 0 0.000885215615823 +Gb536_6 ns536 0 ni6 0 0.00108302940084 +Gb538_6 ns538 0 ni6 0 0.0012974224943 +Gb540_6 ns540 0 ni6 0 0.00133379847068 +Gb542_6 ns542 0 ni6 0 0.0014236528086 +Gb543_6 ns543 0 ni6 0 0.00152338041719 +Gb545_6 ns545 0 ni6 0 0.00157020947398 +Gb547_6 ns547 0 ni6 0 0.00157102723128 +Gb549_6 ns549 0 ni6 0 0.00177897345171 +Gb551_6 ns551 0 ni6 0 0.00175163298229 +Gb553_6 ns553 0 ni6 0 0.00180599385817 +Gb555_6 ns555 0 ni6 0 0.00184561379971 +Gb557_6 ns557 0 ni6 0 0.0020794225841 +Gb559_6 ns559 0 ni6 0 0.00259011336935 +Gb561_6 ns561 0 ni6 0 0.00230839383077 +Gb563_6 ns563 0 ni6 0 0.00251382062423 +Gb565_6 ns565 0 ni6 0 0.00260427116822 +Gb567_6 ns567 0 ni6 0 0.00267960066972 +Gb569_6 ns569 0 ni6 0 0.00294784166772 +Gb571_6 ns571 0 ni6 0 0.00305197575559 +Gb573_6 ns573 0 ni6 0 0.00310376810668 +Gb575_6 ns575 0 ni6 0 0.00332750825327 +Gb577_6 ns577 0 ni6 0 0.00345137701391 +Gb579_6 ns579 0 ni6 0 0.00356219951633 +Gb581_6 ns581 0 ni6 0 0.00358057447428 +Gb583_6 ns583 0 ni6 0 0.00367714804858 +Gb585_6 ns585 0 ni6 0 0.00374167901941 +Gb587_6 ns587 0 ni6 0 0.00403078751924 +Gb589_6 ns589 0 ni6 0 0.00422667193083 +Gb591_6 ns591 0 ni6 0 0.00438801592294 +Gb593_6 ns593 0 ni6 0 0.0045547335825 +Gb595_6 ns595 0 ni6 0 0.00454235974501 +Gb597_6 ns597 0 ni6 0 0.00486312135632 +Gb599_6 ns599 0 ni6 0 0.0050133715516 +Gb601_6 ns601 0 ni6 0 0.00508176306262 +Gb603_6 ns603 0 ni6 0 0.00521022560748 +Gb605_6 ns605 0 ni6 0 0.00543384695857 +Gb607_6 ns607 0 ni6 0 0.00575255464146 +Gb609_6 ns609 0 ni6 0 0.0057955488302 +Gb611_6 ns611 0 ni6 0 0.00588782851328 +Gb613_6 ns613 0 ni6 0 0.0059726194701 +Gb615_6 ns615 0 ni6 0 0.00600566777511 +Gb617_6 ns617 0 ni6 0 0.00626267023163 + +Gc1_1 0 n2 ns1 0 0.00639599017976 +Gc1_2 0 n2 ns2 0 -1.2784392242e-005 +Gc1_3 0 n2 ns3 0 3.86573394021e-005 +Gc1_4 0 n2 ns4 0 0.00025642568165 +Gc1_5 0 n2 ns5 0 -1.8401455711e-006 +Gc1_6 0 n2 ns6 0 3.42755524346e-007 +Gc1_7 0 n2 ns7 0 1.68329374813e-005 +Gc1_8 0 n2 ns8 0 -1.09653129162e-005 +Gc1_9 0 n2 ns9 0 0.00039905586069 +Gc1_10 0 n2 ns10 0 0.0064754200605 +Gc1_11 0 n2 ns11 0 0.00810205992642 +Gc1_12 0 n2 ns12 0 0.00294012928805 +Gc1_13 0 n2 ns13 0 -6.53634237944e-006 +Gc1_14 0 n2 ns14 0 1.01159812152e-005 +Gc1_15 0 n2 ns15 0 2.35307698575e-006 +Gc1_16 0 n2 ns16 0 -7.06917487133e-007 +Gc1_17 0 n2 ns17 0 -4.07370616037e-007 +Gc1_18 0 n2 ns18 0 2.35814834919e-006 +Gc1_19 0 n2 ns19 0 2.23382612853e-006 +Gc1_20 0 n2 ns20 0 6.15268637826e-006 +Gc1_21 0 n2 ns21 0 -3.51076165686e-006 +Gc1_22 0 n2 ns22 0 3.73445684834e-006 +Gc1_23 0 n2 ns23 0 0.00165334525942 +Gc1_24 0 n2 ns24 0 0.0102050770067 +Gc1_25 0 n2 ns25 0 -0.00354465532258 +Gc1_26 0 n2 ns26 0 -0.0119490380362 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-1.03525681923e-006 +Gc1_53 0 n2 ns53 0 1.29427133601e-006 +Gc1_54 0 n2 ns54 0 2.31700619961e-005 +Gc1_55 0 n2 ns55 0 -8.86783182955e-006 +Gc1_56 0 n2 ns56 0 4.65686429611e-006 +Gc1_57 0 n2 ns57 0 -3.73090999616e-006 +Gc1_58 0 n2 ns58 0 -0.000601337230402 +Gc1_59 0 n2 ns59 0 -0.000650898046767 +Gc1_60 0 n2 ns60 0 1.81295560397e-007 +Gc1_61 0 n2 ns61 0 1.63256069108e-007 +Gc1_62 0 n2 ns62 0 7.18445921875e-005 +Gc1_63 0 n2 ns63 0 6.33374514342e-005 +Gc1_64 0 n2 ns64 0 -0.0145648509533 +Gc1_65 0 n2 ns65 0 0.00286722157962 +Gc1_66 0 n2 ns66 0 -9.11504087362e-006 +Gc1_67 0 n2 ns67 0 1.75975415322e-005 +Gc1_68 0 n2 ns68 0 5.69960419019e-005 +Gc1_69 0 n2 ns69 0 6.94631393911e-006 +Gc1_70 0 n2 ns70 0 -0.00021390648182 +Gc1_71 0 n2 ns71 0 0.000331189209495 +Gc1_72 0 n2 ns72 0 -6.89394244874e-005 +Gc1_73 0 n2 ns73 0 1.97773311744e-005 +Gc1_74 0 n2 ns74 0 -6.69642718289e-007 +Gc1_75 0 n2 ns75 0 -1.07973757957e-006 +Gc1_76 0 n2 ns76 0 4.38149218906e-006 +Gc1_77 0 n2 ns77 0 -5.16162753863e-006 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+Gc4_514 0 n8 ns514 0 0.000479180939735 +Gc4_515 0 n8 ns515 0 0.00019432565159 +Gc4_516 0 n8 ns516 0 0.00645861998988 +Gc4_517 0 n8 ns517 0 5.77629480785e-006 +Gc4_518 0 n8 ns518 0 6.72952878021e-006 +Gc4_519 0 n8 ns519 0 4.13040565127e-005 +Gc4_520 0 n8 ns520 0 1.10229222503e-007 +Gc4_521 0 n8 ns521 0 -1.07974567892e-006 +Gc4_522 0 n8 ns522 0 -1.41888820517e-006 +Gc4_523 0 n8 ns523 0 8.82768348415e-006 +Gc4_524 0 n8 ns524 0 -0.000204215830222 +Gc4_525 0 n8 ns525 0 -0.00335853671257 +Gc4_526 0 n8 ns526 0 -0.00385441395255 +Gc4_527 0 n8 ns527 0 -0.000889077199988 +Gc4_528 0 n8 ns528 0 -5.04217554084e-006 +Gc4_529 0 n8 ns529 0 2.55231777084e-006 +Gc4_530 0 n8 ns530 0 1.44556693979e-006 +Gc4_531 0 n8 ns531 0 -9.92810204887e-007 +Gc4_532 0 n8 ns532 0 -5.11613326985e-007 +Gc4_533 0 n8 ns533 0 1.87688351563e-006 +Gc4_534 0 n8 ns534 0 2.56883283639e-006 +Gc4_535 0 n8 ns535 0 3.14107728442e-006 +Gc4_536 0 n8 ns536 0 -2.71958266701e-007 +Gc4_537 0 n8 ns537 0 1.97633011898e-006 +Gc4_538 0 n8 ns538 0 -0.000447427755937 +Gc4_539 0 n8 ns539 0 0.00103697861763 +Gc4_540 0 n8 ns540 0 3.34451672645e-005 +Gc4_541 0 n8 ns541 0 0.00251003390028 +Gc4_542 0 n8 ns542 0 0.00960853308041 +Gc4_543 0 n8 ns543 0 6.10373447962e-005 +Gc4_544 0 n8 ns544 0 -1.30782781763e-005 +Gc4_545 0 n8 ns545 0 1.97398898544e-005 +Gc4_546 0 n8 ns546 0 -4.94198182524e-005 +Gc4_547 0 n8 ns547 0 1.33929581161e-006 +Gc4_548 0 n8 ns548 0 2.89137968175e-006 +Gc4_549 0 n8 ns549 0 -0.00762679108914 +Gc4_550 0 n8 ns550 0 0.00215294862916 +Gc4_551 0 n8 ns551 0 1.4061409708e-005 +Gc4_552 0 n8 ns552 0 -1.21470719176e-006 +Gc4_553 0 n8 ns553 0 0.00022394135688 +Gc4_554 0 n8 ns554 0 0.000464693801119 +Gc4_555 0 n8 ns555 0 8.34655800535e-005 +Gc4_556 0 n8 ns556 0 -2.18462559125e-005 +Gc4_557 0 n8 ns557 0 -5.89555453166e-007 +Gc4_558 0 n8 ns558 0 -9.03987411069e-008 +Gc4_559 0 n8 ns559 0 0.00997009282685 +Gc4_560 0 n8 ns560 0 -0.0169781186838 +Gc4_561 0 n8 ns561 0 -6.16479547142e-007 +Gc4_562 0 n8 ns562 0 -4.27788498627e-006 +Gc4_563 0 n8 ns563 0 -1.39596470599e-006 +Gc4_564 0 n8 ns564 0 -1.05895880162e-006 +Gc4_565 0 n8 ns565 0 -2.9216569323e-006 +Gc4_566 0 n8 ns566 0 -2.48854813165e-006 +Gc4_567 0 n8 ns567 0 -1.40717407113e-006 +Gc4_568 0 n8 ns568 0 -1.5150647712e-006 +Gc4_569 0 n8 ns569 0 5.86348724466e-005 +Gc4_570 0 n8 ns570 0 -1.02878211838e-005 +Gc4_571 0 n8 ns571 0 1.02841509819e-005 +Gc4_572 0 n8 ns572 0 -1.5570669182e-005 +Gc4_573 0 n8 ns573 0 -0.00079267349263 +Gc4_574 0 n8 ns574 0 -0.000615080038684 +Gc4_575 0 n8 ns575 0 9.7071978205e-007 +Gc4_576 0 n8 ns576 0 5.7778966495e-006 +Gc4_577 0 n8 ns577 0 2.37079070373e-005 +Gc4_578 0 n8 ns578 0 1.04014980739e-005 +Gc4_579 0 n8 ns579 0 -0.0103152087536 +Gc4_580 0 n8 ns580 0 0.00630802610606 +Gc4_581 0 n8 ns581 0 8.21261612968e-005 +Gc4_582 0 n8 ns582 0 4.21233388565e-005 +Gc4_583 0 n8 ns583 0 0.000110186881569 +Gc4_584 0 n8 ns584 0 -0.000103202250463 +Gc4_585 0 n8 ns585 0 0.000105222199509 +Gc4_586 0 n8 ns586 0 -5.94417709266e-005 +Gc4_587 0 n8 ns587 0 -0.000107567158011 +Gc4_588 0 n8 ns588 0 0.000110821672807 +Gc4_589 0 n8 ns589 0 -1.75559932674e-006 +Gc4_590 0 n8 ns590 0 -5.70132117968e-007 +Gc4_591 0 n8 ns591 0 2.16336077806e-006 +Gc4_592 0 n8 ns592 0 -6.91902793706e-006 +Gc4_593 0 n8 ns593 0 0.00300741566283 +Gc4_594 0 n8 ns594 0 0.000941200087165 +Gc4_595 0 n8 ns595 0 2.48081585753e-006 +Gc4_596 0 n8 ns596 0 -8.9412760604e-006 +Gc4_597 0 n8 ns597 0 1.96005163245e-005 +Gc4_598 0 n8 ns598 0 7.96094914532e-005 +Gc4_599 0 n8 ns599 0 7.87489198845e-005 +Gc4_600 0 n8 ns600 0 -0.000114611722499 +Gc4_601 0 n8 ns601 0 -4.5566125372e-005 +Gc4_602 0 n8 ns602 0 -4.9372680505e-005 +Gc4_603 0 n8 ns603 0 -6.69770262863e-005 +Gc4_604 0 n8 ns604 0 -0.000114436151675 +Gc4_605 0 n8 ns605 0 5.55159390203e-006 +Gc4_606 0 n8 ns606 0 3.32705947746e-006 +Gc4_607 0 n8 ns607 0 -0.000683365837853 +Gc4_608 0 n8 ns608 0 -0.00042871349678 +Gc4_609 0 n8 ns609 0 -8.18236130021e-005 +Gc4_610 0 n8 ns610 0 4.6949265478e-005 +Gc4_611 0 n8 ns611 0 -1.21198944185e-005 +Gc4_612 0 n8 ns612 0 2.81686577985e-005 +Gc4_613 0 n8 ns613 0 -0.000101910340447 +Gc4_614 0 n8 ns614 0 2.06984455872e-005 +Gc4_615 0 n8 ns615 0 0.000911305474242 +Gc4_616 0 n8 ns616 0 0.000447060759317 +Gc4_617 0 n8 ns617 0 6.80937051298e-005 +Gc4_618 0 n8 ns618 0 -5.01820844893e-006 +Gd4_1 0 n8 ni1 0 -0.000231074524596 +Gd4_2 0 n8 ni2 0 -8.15592100117e-005 +Gd4_3 0 n8 ni3 0 -0.000506023326846 +Gd4_4 0 n8 ni4 0 -0.000814858171052 +Gd4_5 0 n8 ni5 0 -0.000179335979684 +Gd4_6 0 n8 ni6 0 9.87155962465e-005 +Gc5_1 0 n10 ns1 0 -0.0064503882148 +Gc5_2 0 n10 ns2 0 -2.63845039619e-006 +Gc5_3 0 n10 ns3 0 -1.25654880424e-005 +Gc5_4 0 n10 ns4 0 -5.4023467884e-005 +Gc5_5 0 n10 ns5 0 -1.33397258048e-006 +Gc5_6 0 n10 ns6 0 1.70027935021e-007 +Gc5_7 0 n10 ns7 0 8.83535521651e-006 +Gc5_8 0 n10 ns8 0 -1.61180130592e-006 +Gc5_9 0 n10 ns9 0 0.0001708733259 +Gc5_10 0 n10 ns10 0 0.00284863862592 +Gc5_11 0 n10 ns11 0 0.00443120659357 +Gc5_12 0 n10 ns12 0 0.00130962278313 +Gc5_13 0 n10 ns13 0 3.37719105128e-007 +Gc5_14 0 n10 ns14 0 4.80900181385e-006 +Gc5_15 0 n10 ns15 0 3.80979437712e-007 +Gc5_16 0 n10 ns16 0 -1.84266858933e-007 +Gc5_17 0 n10 ns17 0 8.3928613026e-007 +Gc5_18 0 n10 ns18 0 2.69688919621e-006 +Gc5_19 0 n10 ns19 0 2.72266892965e-006 +Gc5_20 0 n10 ns20 0 3.07506465491e-006 +Gc5_21 0 n10 ns21 0 2.52718073196e-007 +Gc5_22 0 n10 ns22 0 3.42072749461e-006 +Gc5_23 0 n10 ns23 0 0.00199003271781 +Gc5_24 0 n10 ns24 0 0.00113700978748 +Gc5_25 0 n10 ns25 0 -0.00222573136708 +Gc5_26 0 n10 ns26 0 -0.000455560756911 +Gc5_27 0 n10 ns27 0 0.00112206302488 +Gc5_28 0 n10 ns28 0 -9.99265555142e-005 +Gc5_29 0 n10 ns29 0 6.9534728905e-005 +Gc5_30 0 n10 ns30 0 -1.04315029039e-005 +Gc5_31 0 n10 ns31 0 0.00015687217476 +Gc5_32 0 n10 ns32 0 2.67473404685e-006 +Gc5_33 0 n10 ns33 0 6.97518763816e-007 +Gc5_34 0 n10 ns34 0 0.0090578845421 +Gc5_35 0 n10 ns35 0 -0.00452681082313 +Gc5_36 0 n10 ns36 0 -1.88472509167e-005 +Gc5_37 0 n10 ns37 0 1.34773630501e-005 +Gc5_38 0 n10 ns38 0 -0.000238244662716 +Gc5_39 0 n10 ns39 0 2.83422306161e-005 +Gc5_40 0 n10 ns40 0 -1.75317795396e-005 +Gc5_41 0 n10 ns41 0 -0.000172435446422 +Gc5_42 0 n10 ns42 0 -2.35837233396e-007 +Gc5_43 0 n10 ns43 0 4.75590408167e-008 +Gc5_44 0 n10 ns44 0 -0.0140237753871 +Gc5_45 0 n10 ns45 0 -0.000168556385443 +Gc5_46 0 n10 ns46 0 -5.33687474449e-006 +Gc5_47 0 n10 ns47 0 -4.01543543463e-007 +Gc5_48 0 n10 ns48 0 -1.68221868498e-006 +Gc5_49 0 n10 ns49 0 1.62945973824e-006 +Gc5_50 0 n10 ns50 0 3.01699831771e-007 +Gc5_51 0 n10 ns51 0 -2.46463881235e-007 +Gc5_52 0 n10 ns52 0 5.78196313845e-007 +Gc5_53 0 n10 ns53 0 -4.13009439172e-007 +Gc5_54 0 n10 ns54 0 2.90616559322e-006 +Gc5_55 0 n10 ns55 0 4.80358281443e-006 +Gc5_56 0 n10 ns56 0 3.66583483289e-006 +Gc5_57 0 n10 ns57 0 1.44235161102e-006 +Gc5_58 0 n10 ns58 0 -0.000170455286297 +Gc5_59 0 n10 ns59 0 -1.05448670043e-005 +Gc5_60 0 n10 ns60 0 2.1186487153e-006 +Gc5_61 0 n10 ns61 0 1.30345069806e-007 +Gc5_62 0 n10 ns62 0 2.868311228e-005 +Gc5_63 0 n10 ns63 0 -3.68352617194e-005 +Gc5_64 0 n10 ns64 0 -0.000384401871328 +Gc5_65 0 n10 ns65 0 0.0072133078729 +Gc5_66 0 n10 ns66 0 -9.36508352541e-006 +Gc5_67 0 n10 ns67 0 -1.67020550789e-005 +Gc5_68 0 n10 ns68 0 -8.65162453763e-006 +Gc5_69 0 n10 ns69 0 0.000129314755495 +Gc5_70 0 n10 ns70 0 0.000545130789541 +Gc5_71 0 n10 ns71 0 -0.000173253440335 +Gc5_72 0 n10 ns72 0 -7.38886472012e-005 +Gc5_73 0 n10 ns73 0 -2.59071478515e-005 +Gc5_74 0 n10 ns74 0 -1.45133200811e-006 +Gc5_75 0 n10 ns75 0 7.37466175443e-007 +Gc5_76 0 n10 ns76 0 -1.82900924557e-007 +Gc5_77 0 n10 ns77 0 1.8897555789e-007 +Gc5_78 0 n10 ns78 0 0.0030775967145 +Gc5_79 0 n10 ns79 0 -0.00207280794017 +Gc5_80 0 n10 ns80 0 -4.78288021694e-006 +Gc5_81 0 n10 ns81 0 -4.19519147255e-006 +Gc5_82 0 n10 ns82 0 1.40016053417e-005 +Gc5_83 0 n10 ns83 0 0.000152411800903 +Gc5_84 0 n10 ns84 0 0.000100222122773 +Gc5_85 0 n10 ns85 0 -9.40515976192e-005 +Gc5_86 0 n10 ns86 0 3.10529230034e-005 +Gc5_87 0 n10 ns87 0 -0.000132861355679 +Gc5_88 0 n10 ns88 0 -0.000140627039715 +Gc5_89 0 n10 ns89 0 8.9194723095e-005 +Gc5_90 0 n10 ns90 0 2.88601524646e-006 +Gc5_91 0 n10 ns91 0 -1.1948431825e-006 +Gc5_92 0 n10 ns92 0 0.00067428735056 +Gc5_93 0 n10 ns93 0 -0.000780823600102 +Gc5_94 0 n10 ns94 0 2.90874031202e-005 +Gc5_95 0 n10 ns95 0 -0.000135683997748 +Gc5_96 0 n10 ns96 0 2.47109269169e-005 +Gc5_97 0 n10 ns97 0 -5.2350468415e-005 +Gc5_98 0 n10 ns98 0 6.73349297078e-005 +Gc5_99 0 n10 ns99 0 -1.42688392476e-005 +Gc5_100 0 n10 ns100 0 -0.00185284208646 +Gc5_101 0 n10 ns101 0 0.000733863982094 +Gc5_102 0 n10 ns102 0 0.000755896655746 +Gc5_103 0 n10 ns103 0 -0.000189081228775 +Gc5_104 0 n10 ns104 0 -0.00644978558037 +Gc5_105 0 n10 ns105 0 9.2166029935e-006 +Gc5_106 0 n10 ns106 0 -3.46413878311e-005 +Gc5_107 0 n10 ns107 0 -0.00020308052723 +Gc5_108 0 n10 ns108 0 4.86743645992e-007 +Gc5_109 0 n10 ns109 0 4.00985261339e-007 +Gc5_110 0 n10 ns110 0 -4.94427092498e-006 +Gc5_111 0 n10 ns111 0 -7.41868849694e-007 +Gc5_112 0 n10 ns112 0 -0.00050110220704 +Gc5_113 0 n10 ns113 0 -0.00621930918952 +Gc5_114 0 n10 ns114 0 -0.00862422258 +Gc5_115 0 n10 ns115 0 -0.00206841301401 +Gc5_116 0 n10 ns116 0 -3.37917960217e-006 +Gc5_117 0 n10 ns117 0 -1.63142563293e-006 +Gc5_118 0 n10 ns118 0 9.76639436204e-007 +Gc5_119 0 n10 ns119 0 -6.16135601068e-008 +Gc5_120 0 n10 ns120 0 1.67788681425e-006 +Gc5_121 0 n10 ns121 0 3.61543348294e-006 +Gc5_122 0 n10 ns122 0 2.46419536327e-006 +Gc5_123 0 n10 ns123 0 3.93505552189e-006 +Gc5_124 0 n10 ns124 0 3.7236809423e-007 +Gc5_125 0 n10 ns125 0 2.86245211011e-006 +Gc5_126 0 n10 ns126 0 0.00072644707418 +Gc5_127 0 n10 ns127 0 -0.000762934088817 +Gc5_128 0 n10 ns128 0 -0.000403873067924 +Gc5_129 0 n10 ns129 0 0.00462605265431 +Gc5_130 0 n10 ns130 0 0.0135271065206 +Gc5_131 0 n10 ns131 0 -2.31594369567e-006 +Gc5_132 0 n10 ns132 0 4.45415342364e-005 +Gc5_133 0 n10 ns133 0 -6.54804880253e-005 +Gc5_134 0 n10 ns134 0 -0.000170674991095 +Gc5_135 0 n10 ns135 0 4.93042781414e-006 +Gc5_136 0 n10 ns136 0 -8.35928283671e-007 +Gc5_137 0 n10 ns137 0 0.00688482245331 +Gc5_138 0 n10 ns138 0 -0.00421863499053 +Gc5_139 0 n10 ns139 0 -1.50820426792e-005 +Gc5_140 0 n10 ns140 0 -0.000122973072126 +Gc5_141 0 n10 ns141 0 -1.93024785974e-005 +Gc5_142 0 n10 ns142 0 0.000304839411668 +Gc5_143 0 n10 ns143 0 -3.28564920939e-005 +Gc5_144 0 n10 ns144 0 -8.4242035884e-006 +Gc5_145 0 n10 ns145 0 9.60834214018e-008 +Gc5_146 0 n10 ns146 0 3.27155027354e-007 +Gc5_147 0 n10 ns147 0 -0.0150845143471 +Gc5_148 0 n10 ns148 0 0.0086936934796 +Gc5_149 0 n10 ns149 0 -6.35557937382e-006 +Gc5_150 0 n10 ns150 0 1.44809687021e-005 +Gc5_151 0 n10 ns151 0 -3.2964158458e-006 +Gc5_152 0 n10 ns152 0 3.74336998636e-006 +Gc5_153 0 n10 ns153 0 2.34926298239e-006 +Gc5_154 0 n10 ns154 0 -2.31749284592e-006 +Gc5_155 0 n10 ns155 0 1.26487051695e-006 +Gc5_156 0 n10 ns156 0 3.76390564757e-007 +Gc5_157 0 n10 ns157 0 -4.35100448013e-006 +Gc5_158 0 n10 ns158 0 -8.5719299624e-006 +Gc5_159 0 n10 ns159 0 -2.95004282581e-007 +Gc5_160 0 n10 ns160 0 -7.46438691686e-007 +Gc5_161 0 n10 ns161 0 0.000157004046376 +Gc5_162 0 n10 ns162 0 0.000345574282097 +Gc5_163 0 n10 ns163 0 -3.83708807456e-006 +Gc5_164 0 n10 ns164 0 1.88663880527e-005 +Gc5_165 0 n10 ns165 0 -1.49017174083e-005 +Gc5_166 0 n10 ns166 0 8.26197390308e-006 +Gc5_167 0 n10 ns167 0 0.00636247049838 +Gc5_168 0 n10 ns168 0 -0.00642317601197 +Gc5_169 0 n10 ns169 0 -8.199127871e-006 +Gc5_170 0 n10 ns170 0 -1.69770114327e-006 +Gc5_171 0 n10 ns171 0 -8.20844787887e-005 +Gc5_172 0 n10 ns172 0 -0.000203795812535 +Gc5_173 0 n10 ns173 0 -0.000518646279516 +Gc5_174 0 n10 ns174 0 0.000221628429081 +Gc5_175 0 n10 ns175 0 -2.96719908573e-005 +Gc5_176 0 n10 ns176 0 -6.65489111419e-005 +Gc5_177 0 n10 ns177 0 4.08178475226e-007 +Gc5_178 0 n10 ns178 0 -2.46171569301e-007 +Gc5_179 0 n10 ns179 0 1.27861926746e-005 +Gc5_180 0 n10 ns180 0 4.15928530817e-006 +Gc5_181 0 n10 ns181 0 -0.0071715397051 +Gc5_182 0 n10 ns182 0 0.00282917431277 +Gc5_183 0 n10 ns183 0 4.38626773853e-006 +Gc5_184 0 n10 ns184 0 2.60319001634e-006 +Gc5_185 0 n10 ns185 0 0.000359828429478 +Gc5_186 0 n10 ns186 0 8.63893494935e-005 +Gc5_187 0 n10 ns187 0 -1.18003724715e-005 +Gc5_188 0 n10 ns188 0 0.000415648914479 +Gc5_189 0 n10 ns189 0 0.000255585766732 +Gc5_190 0 n10 ns190 0 -3.8583506705e-005 +Gc5_191 0 n10 ns191 0 -0.000426264381648 +Gc5_192 0 n10 ns192 0 0.000327461577191 +Gc5_193 0 n10 ns193 0 3.65001250068e-006 +Gc5_194 0 n10 ns194 0 -2.43915850453e-006 +Gc5_195 0 n10 ns195 0 0.00282232840842 +Gc5_196 0 n10 ns196 0 0.00244924968911 +Gc5_197 0 n10 ns197 0 0.000176879266938 +Gc5_198 0 n10 ns198 0 0.000118240209223 +Gc5_199 0 n10 ns199 0 -6.8060693232e-006 +Gc5_200 0 n10 ns200 0 3.86210252007e-005 +Gc5_201 0 n10 ns201 0 -7.2935954019e-005 +Gc5_202 0 n10 ns202 0 -4.23311818438e-006 +Gc5_203 0 n10 ns203 0 0.00104058724295 +Gc5_204 0 n10 ns204 0 -0.00372560527083 +Gc5_205 0 n10 ns205 0 -0.0010408978126 +Gc5_206 0 n10 ns206 0 -0.00115786330733 +Gc5_207 0 n10 ns207 0 -0.00646560602013 +Gc5_208 0 n10 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n12 ns495 0 1.28700607067e-005 +Gc6_496 0 n12 ns496 0 -0.000132986063632 +Gc6_497 0 n12 ns497 0 -4.74309751169e-005 +Gc6_498 0 n12 ns498 0 -4.1903022602e-005 +Gc6_499 0 n12 ns499 0 6.50094714293e-005 +Gc6_500 0 n12 ns500 0 0.000280713396507 +Gc6_501 0 n12 ns501 0 0.000141423824256 +Gc6_502 0 n12 ns502 0 -7.02169864013e-007 +Gc6_503 0 n12 ns503 0 1.37147674971e-006 +Gc6_504 0 n12 ns504 0 -0.000652672546097 +Gc6_505 0 n12 ns505 0 3.60578026374e-005 +Gc6_506 0 n12 ns506 0 -4.02800042435e-005 +Gc6_507 0 n12 ns507 0 3.97000436216e-005 +Gc6_508 0 n12 ns508 0 -1.04661837404e-005 +Gc6_509 0 n12 ns509 0 9.73762978998e-006 +Gc6_510 0 n12 ns510 0 -2.98874073544e-006 +Gc6_511 0 n12 ns511 0 6.4964917156e-005 +Gc6_512 0 n12 ns512 0 0.00078820897909 +Gc6_513 0 n12 ns513 0 0.000919095440069 +Gc6_514 0 n12 ns514 0 0.000708302022825 +Gc6_515 0 n12 ns515 0 0.000432231841187 +Gc6_516 0 n12 ns516 0 0.00638333189034 +Gc6_517 0 n12 ns517 0 -2.15228293519e-005 +Gc6_518 0 n12 ns518 0 4.60663832048e-005 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+Gc6_543 0 n12 ns543 0 -4.86582244413e-005 +Gc6_544 0 n12 ns544 0 -4.59294531848e-005 +Gc6_545 0 n12 ns545 0 4.19282456724e-005 +Gc6_546 0 n12 ns546 0 1.22573587078e-005 +Gc6_547 0 n12 ns547 0 -5.54952409906e-006 +Gc6_548 0 n12 ns548 0 9.72964056473e-006 +Gc6_549 0 n12 ns549 0 -0.00864116492835 +Gc6_550 0 n12 ns550 0 0.000739292559374 +Gc6_551 0 n12 ns551 0 9.27736565425e-006 +Gc6_552 0 n12 ns552 0 4.86567635473e-006 +Gc6_553 0 n12 ns553 0 -0.000339515356894 +Gc6_554 0 n12 ns554 0 0.000619294256889 +Gc6_555 0 n12 ns555 0 4.4511258895e-005 +Gc6_556 0 n12 ns556 0 -2.5383932019e-006 +Gc6_557 0 n12 ns557 0 1.30284226244e-006 +Gc6_558 0 n12 ns558 0 -7.02017685689e-007 +Gc6_559 0 n12 ns559 0 0.0272612119906 +Gc6_560 0 n12 ns560 0 0.0614801436687 +Gc6_561 0 n12 ns561 0 8.54786378513e-006 +Gc6_562 0 n12 ns562 0 2.48757808526e-006 +Gc6_563 0 n12 ns563 0 -2.56664984492e-006 +Gc6_564 0 n12 ns564 0 1.03019642575e-006 +Gc6_565 0 n12 ns565 0 -3.91501867309e-006 +Gc6_566 0 n12 ns566 0 -2.79875981978e-007 +Gc6_567 0 n12 ns567 0 -1.58491998482e-007 +Gc6_568 0 n12 ns568 0 -1.20483131966e-006 +Gc6_569 0 n12 ns569 0 5.56966539916e-005 +Gc6_570 0 n12 ns570 0 -2.35523403204e-005 +Gc6_571 0 n12 ns571 0 5.46639064812e-006 +Gc6_572 0 n12 ns572 0 -2.31950120804e-005 +Gc6_573 0 n12 ns573 0 -0.000568075304081 +Gc6_574 0 n12 ns574 0 5.89730845658e-005 +Gc6_575 0 n12 ns575 0 -4.47263341069e-006 +Gc6_576 0 n12 ns576 0 8.99761493614e-006 +Gc6_577 0 n12 ns577 0 -9.89443167476e-006 +Gc6_578 0 n12 ns578 0 2.59080922869e-006 +Gc6_579 0 n12 ns579 0 0.0105124731037 +Gc6_580 0 n12 ns580 0 -0.000479046122583 +Gc6_581 0 n12 ns581 0 -4.97643686025e-005 +Gc6_582 0 n12 ns582 0 0.000142969396077 +Gc6_583 0 n12 ns583 0 -3.41203992494e-005 +Gc6_584 0 n12 ns584 0 -0.000193050087507 +Gc6_585 0 n12 ns585 0 -9.11148515423e-005 +Gc6_586 0 n12 ns586 0 -5.1242103604e-005 +Gc6_587 0 n12 ns587 0 0.000163455416579 +Gc6_588 0 n12 ns588 0 -9.19627606445e-005 +Gc6_589 0 n12 ns589 0 -3.86735924295e-006 +Gc6_590 0 n12 ns590 0 -7.86843661761e-007 +Gc6_591 0 n12 ns591 0 4.52754713871e-006 +Gc6_592 0 n12 ns592 0 -1.73828069042e-005 +Gc6_593 0 n12 ns593 0 0.00601328346665 +Gc6_594 0 n12 ns594 0 0.000560059867359 +Gc6_595 0 n12 ns595 0 5.64141376413e-006 +Gc6_596 0 n12 ns596 0 -8.5089560682e-006 +Gc6_597 0 n12 ns597 0 -8.18060101503e-005 +Gc6_598 0 n12 ns598 0 -2.78366529155e-005 +Gc6_599 0 n12 ns599 0 4.59831249583e-005 +Gc6_600 0 n12 ns600 0 -0.000582550990069 +Gc6_601 0 n12 ns601 0 9.33268544266e-005 +Gc6_602 0 n12 ns602 0 -9.51755311973e-005 +Gc6_603 0 n12 ns603 0 8.54280187433e-005 +Gc6_604 0 n12 ns604 0 0.000232747163498 +Gc6_605 0 n12 ns605 0 -9.63300725131e-006 +Gc6_606 0 n12 ns606 0 9.47676606967e-006 +Gc6_607 0 n12 ns607 0 0.00159405736499 +Gc6_608 0 n12 ns608 0 -0.000357789213797 +Gc6_609 0 n12 ns609 0 -5.46028421253e-006 +Gc6_610 0 n12 ns610 0 2.10660818011e-005 +Gc6_611 0 n12 ns611 0 4.59246666184e-006 +Gc6_612 0 n12 ns612 0 -1.85513061116e-005 +Gc6_613 0 n12 ns613 0 0.000148560982047 +Gc6_614 0 n12 ns614 0 0.00060918292163 +Gc6_615 0 n12 ns615 0 0.00153618668577 +Gc6_616 0 n12 ns616 0 -0.00342387952189 +Gc6_617 0 n12 ns617 0 -0.0015438021856 +Gc6_618 0 n12 ns618 0 0.00119346986386 +Gd6_1 0 n12 ni1 0 -0.000328301978188 +Gd6_2 0 n12 ni2 0 -0.000667227373716 +Gd6_3 0 n12 ni3 0 5.03309333038e-005 +Gd6_4 0 n12 ni4 0 0.000121413617697 +Gd6_5 0 n12 ni5 0 -8.38279890069e-005 +Gd6_6 0 n12 ni6 0 -0.00163196199066 +.ends + + +.subckt 744839010400 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 87202806.0148 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 838013.440199 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 58615.9619396 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 30489.203505 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 8910.33404713 +Ca6 ns6 0 1e-012 +Ca7 ns7 0 1e-012 +Ra6 ns6 0 68172.8774626 +Ra7 ns7 0 68172.8774626 +Ga6 ns6 0 ns7 0 -0.000213018298703 +Ga7 ns7 0 ns6 0 0.000213018298703 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 4597.21553545 +Ra9 ns9 0 4597.21553545 +Ga8 ns8 0 ns9 0 -0.000443889661224 +Ga9 ns9 0 ns8 0 0.000443889661224 +Ca10 ns10 0 1e-012 +Ra10 ns10 0 1964.00477465 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 5153.49438366 +Ra12 ns12 0 5153.49438366 +Ga11 ns11 0 ns12 0 -0.000549674760702 +Ga12 ns12 0 ns11 0 0.000549674760702 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 17045.2467627 +Ra14 ns14 0 17045.2467627 +Ga13 ns13 0 ns14 0 -0.000668338491712 +Ga14 ns14 0 ns13 0 0.000668338491712 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 1956.70478282 +Ra16 ns16 0 1956.70478282 +Ga15 ns15 0 ns16 0 -0.000738626319939 +Ga16 ns16 0 ns15 0 0.000738626319939 +Ca17 ns17 0 1e-012 +Ra17 ns17 0 87202806.0148 +Ca18 ns18 0 1e-012 +Ra18 ns18 0 838013.440199 +Ca19 ns19 0 1e-012 +Ra19 ns19 0 58615.9619396 +Ca20 ns20 0 1e-012 +Ra20 ns20 0 30489.203505 +Ca21 ns21 0 1e-012 +Ra21 ns21 0 8910.33404713 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 68172.8774626 +Ra23 ns23 0 68172.8774626 +Ga22 ns22 0 ns23 0 -0.000213018298703 +Ga23 ns23 0 ns22 0 0.000213018298703 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 4597.21553545 +Ra25 ns25 0 4597.21553545 +Ga24 ns24 0 ns25 0 -0.000443889661224 +Ga25 ns25 0 ns24 0 0.000443889661224 +Ca26 ns26 0 1e-012 +Ra26 ns26 0 1964.00477465 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 5153.49438366 +Ra28 ns28 0 5153.49438366 +Ga27 ns27 0 ns28 0 -0.000549674760702 +Ga28 ns28 0 ns27 0 0.000549674760702 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 17045.2467627 +Ra30 ns30 0 17045.2467627 +Ga29 ns29 0 ns30 0 -0.000668338491712 +Ga30 ns30 0 ns29 0 0.000668338491712 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 1956.70478282 +Ra32 ns32 0 1956.70478282 +Ga31 ns31 0 ns32 0 -0.000738626319939 +Ga32 ns32 0 ns31 0 0.000738626319939 +Ca33 ns33 0 1e-012 +Ra33 ns33 0 87202806.0148 +Ca34 ns34 0 1e-012 +Ra34 ns34 0 838013.440199 +Ca35 ns35 0 1e-012 +Ra35 ns35 0 58615.9619396 +Ca36 ns36 0 1e-012 +Ra36 ns36 0 30489.203505 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 8910.33404713 +Ca38 ns38 0 1e-012 +Ca39 ns39 0 1e-012 +Ra38 ns38 0 68172.8774626 +Ra39 ns39 0 68172.8774626 +Ga38 ns38 0 ns39 0 -0.000213018298703 +Ga39 ns39 0 ns38 0 0.000213018298703 +Ca40 ns40 0 1e-012 +Ca41 ns41 0 1e-012 +Ra40 ns40 0 4597.21553545 +Ra41 ns41 0 4597.21553545 +Ga40 ns40 0 ns41 0 -0.000443889661224 +Ga41 ns41 0 ns40 0 0.000443889661224 +Ca42 ns42 0 1e-012 +Ra42 ns42 0 1964.00477465 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 5153.49438366 +Ra44 ns44 0 5153.49438366 +Ga43 ns43 0 ns44 0 -0.000549674760702 +Ga44 ns44 0 ns43 0 0.000549674760702 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 17045.2467627 +Ra46 ns46 0 17045.2467627 +Ga45 ns45 0 ns46 0 -0.000668338491712 +Ga46 ns46 0 ns45 0 0.000668338491712 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 1956.70478282 +Ra48 ns48 0 1956.70478282 +Ga47 ns47 0 ns48 0 -0.000738626319939 +Ga48 ns48 0 ns47 0 0.000738626319939 +Ca49 ns49 0 1e-012 +Ra49 ns49 0 87202806.0148 +Ca50 ns50 0 1e-012 +Ra50 ns50 0 838013.440199 +Ca51 ns51 0 1e-012 +Ra51 ns51 0 58615.9619396 +Ca52 ns52 0 1e-012 +Ra52 ns52 0 30489.203505 +Ca53 ns53 0 1e-012 +Ra53 ns53 0 8910.33404713 +Ca54 ns54 0 1e-012 +Ca55 ns55 0 1e-012 +Ra54 ns54 0 68172.8774626 +Ra55 ns55 0 68172.8774626 +Ga54 ns54 0 ns55 0 -0.000213018298703 +Ga55 ns55 0 ns54 0 0.000213018298703 +Ca56 ns56 0 1e-012 +Ca57 ns57 0 1e-012 +Ra56 ns56 0 4597.21553545 +Ra57 ns57 0 4597.21553545 +Ga56 ns56 0 ns57 0 -0.000443889661224 +Ga57 ns57 0 ns56 0 0.000443889661224 +Ca58 ns58 0 1e-012 +Ra58 ns58 0 1964.00477465 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 5153.49438366 +Ra60 ns60 0 5153.49438366 +Ga59 ns59 0 ns60 0 -0.000549674760702 +Ga60 ns60 0 ns59 0 0.000549674760702 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 17045.2467627 +Ra62 ns62 0 17045.2467627 +Ga61 ns61 0 ns62 0 -0.000668338491712 +Ga62 ns62 0 ns61 0 0.000668338491712 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 1956.70478282 +Ra64 ns64 0 1956.70478282 +Ga63 ns63 0 ns64 0 -0.000738626319939 +Ga64 ns64 0 ns63 0 0.000738626319939 +Ca65 ns65 0 1e-012 +Ra65 ns65 0 87202806.0148 +Ca66 ns66 0 1e-012 +Ra66 ns66 0 838013.440199 +Ca67 ns67 0 1e-012 +Ra67 ns67 0 58615.9619396 +Ca68 ns68 0 1e-012 +Ra68 ns68 0 30489.203505 +Ca69 ns69 0 1e-012 +Ra69 ns69 0 8910.33404713 +Ca70 ns70 0 1e-012 +Ca71 ns71 0 1e-012 +Ra70 ns70 0 68172.8774626 +Ra71 ns71 0 68172.8774626 +Ga70 ns70 0 ns71 0 -0.000213018298703 +Ga71 ns71 0 ns70 0 0.000213018298703 +Ca72 ns72 0 1e-012 +Ca73 ns73 0 1e-012 +Ra72 ns72 0 4597.21553545 +Ra73 ns73 0 4597.21553545 +Ga72 ns72 0 ns73 0 -0.000443889661224 +Ga73 ns73 0 ns72 0 0.000443889661224 +Ca74 ns74 0 1e-012 +Ra74 ns74 0 1964.00477465 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 5153.49438366 +Ra76 ns76 0 5153.49438366 +Ga75 ns75 0 ns76 0 -0.000549674760702 +Ga76 ns76 0 ns75 0 0.000549674760702 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 17045.2467627 +Ra78 ns78 0 17045.2467627 +Ga77 ns77 0 ns78 0 -0.000668338491712 +Ga78 ns78 0 ns77 0 0.000668338491712 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 1956.70478282 +Ra80 ns80 0 1956.70478282 +Ga79 ns79 0 ns80 0 -0.000738626319939 +Ga80 ns80 0 ns79 0 0.000738626319939 +Ca81 ns81 0 1e-012 +Ra81 ns81 0 87202806.0148 +Ca82 ns82 0 1e-012 +Ra82 ns82 0 838013.440199 +Ca83 ns83 0 1e-012 +Ra83 ns83 0 58615.9619396 +Ca84 ns84 0 1e-012 +Ra84 ns84 0 30489.203505 +Ca85 ns85 0 1e-012 +Ra85 ns85 0 8910.33404713 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 68172.8774626 +Ra87 ns87 0 68172.8774626 +Ga86 ns86 0 ns87 0 -0.000213018298703 +Ga87 ns87 0 ns86 0 0.000213018298703 +Ca88 ns88 0 1e-012 +Ca89 ns89 0 1e-012 +Ra88 ns88 0 4597.21553545 +Ra89 ns89 0 4597.21553545 +Ga88 ns88 0 ns89 0 -0.000443889661224 +Ga89 ns89 0 ns88 0 0.000443889661224 +Ca90 ns90 0 1e-012 +Ra90 ns90 0 1964.00477465 +Ca91 ns91 0 1e-012 +Ca92 ns92 0 1e-012 +Ra91 ns91 0 5153.49438366 +Ra92 ns92 0 5153.49438366 +Ga91 ns91 0 ns92 0 -0.000549674760702 +Ga92 ns92 0 ns91 0 0.000549674760702 +Ca93 ns93 0 1e-012 +Ca94 ns94 0 1e-012 +Ra93 ns93 0 17045.2467627 +Ra94 ns94 0 17045.2467627 +Ga93 ns93 0 ns94 0 -0.000668338491712 +Ga94 ns94 0 ns93 0 0.000668338491712 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 1956.70478282 +Ra96 ns96 0 1956.70478282 +Ga95 ns95 0 ns96 0 -0.000738626319939 +Ga96 ns96 0 ns95 0 0.000738626319939 + +Gb1_1 ns1 0 ni1 0 1.14675208941e-008 +Gb2_1 ns2 0 ni1 0 1.19329828381e-006 +Gb3_1 ns3 0 ni1 0 1.7060199422e-005 +Gb4_1 ns4 0 ni1 0 3.27984953702e-005 +Gb5_1 ns5 0 ni1 0 0.000112229237951 +Gb6_1 ns6 0 ni1 0 0.000214028388159 +Gb8_1 ns8 0 ni1 0 0.000550484269721 +Gb10_1 ns10 0 ni1 0 0.000509163731631 +Gb11_1 ns11 0 ni1 0 0.000618174763592 +Gb13_1 ns13 0 ni1 0 0.000673488369703 +Gb15_1 ns15 0 ni1 0 0.00109223637656 +Gb17_2 ns17 0 ni2 0 1.14675208941e-008 +Gb18_2 ns18 0 ni2 0 1.19329828381e-006 +Gb19_2 ns19 0 ni2 0 1.7060199422e-005 +Gb20_2 ns20 0 ni2 0 3.27984953702e-005 +Gb21_2 ns21 0 ni2 0 0.000112229237951 +Gb22_2 ns22 0 ni2 0 0.000214028388159 +Gb24_2 ns24 0 ni2 0 0.000550484269721 +Gb26_2 ns26 0 ni2 0 0.000509163731631 +Gb27_2 ns27 0 ni2 0 0.000618174763592 +Gb29_2 ns29 0 ni2 0 0.000673488369703 +Gb31_2 ns31 0 ni2 0 0.00109223637656 +Gb33_3 ns33 0 ni3 0 1.14675208941e-008 +Gb34_3 ns34 0 ni3 0 1.19329828381e-006 +Gb35_3 ns35 0 ni3 0 1.7060199422e-005 +Gb36_3 ns36 0 ni3 0 3.27984953702e-005 +Gb37_3 ns37 0 ni3 0 0.000112229237951 +Gb38_3 ns38 0 ni3 0 0.000214028388159 +Gb40_3 ns40 0 ni3 0 0.000550484269721 +Gb42_3 ns42 0 ni3 0 0.000509163731631 +Gb43_3 ns43 0 ni3 0 0.000618174763592 +Gb45_3 ns45 0 ni3 0 0.000673488369703 +Gb47_3 ns47 0 ni3 0 0.00109223637656 +Gb49_4 ns49 0 ni4 0 1.14675208941e-008 +Gb50_4 ns50 0 ni4 0 1.19329828381e-006 +Gb51_4 ns51 0 ni4 0 1.7060199422e-005 +Gb52_4 ns52 0 ni4 0 3.27984953702e-005 +Gb53_4 ns53 0 ni4 0 0.000112229237951 +Gb54_4 ns54 0 ni4 0 0.000214028388159 +Gb56_4 ns56 0 ni4 0 0.000550484269721 +Gb58_4 ns58 0 ni4 0 0.000509163731631 +Gb59_4 ns59 0 ni4 0 0.000618174763592 +Gb61_4 ns61 0 ni4 0 0.000673488369703 +Gb63_4 ns63 0 ni4 0 0.00109223637656 +Gb65_5 ns65 0 ni5 0 1.14675208941e-008 +Gb66_5 ns66 0 ni5 0 1.19329828381e-006 +Gb67_5 ns67 0 ni5 0 1.7060199422e-005 +Gb68_5 ns68 0 ni5 0 3.27984953702e-005 +Gb69_5 ns69 0 ni5 0 0.000112229237951 +Gb70_5 ns70 0 ni5 0 0.000214028388159 +Gb72_5 ns72 0 ni5 0 0.000550484269721 +Gb74_5 ns74 0 ni5 0 0.000509163731631 +Gb75_5 ns75 0 ni5 0 0.000618174763592 +Gb77_5 ns77 0 ni5 0 0.000673488369703 +Gb79_5 ns79 0 ni5 0 0.00109223637656 +Gb81_6 ns81 0 ni6 0 1.14675208941e-008 +Gb82_6 ns82 0 ni6 0 1.19329828381e-006 +Gb83_6 ns83 0 ni6 0 1.7060199422e-005 +Gb84_6 ns84 0 ni6 0 3.27984953702e-005 +Gb85_6 ns85 0 ni6 0 0.000112229237951 +Gb86_6 ns86 0 ni6 0 0.000214028388159 +Gb88_6 ns88 0 ni6 0 0.000550484269721 +Gb90_6 ns90 0 ni6 0 0.000509163731631 +Gb91_6 ns91 0 ni6 0 0.000618174763592 +Gb93_6 ns93 0 ni6 0 0.000673488369703 +Gb95_6 ns95 0 ni6 0 0.00109223637656 + +Gc1_1 0 n2 ns1 0 0.00194466740962 +Gc1_2 0 n2 ns2 0 0.000136176781325 +Gc1_3 0 n2 ns3 0 0.00287244660785 +Gc1_4 0 n2 ns4 0 0.0111839887292 +Gc1_5 0 n2 ns5 0 0.00207318745673 +Gc1_6 0 n2 ns6 0 -1.10552760282e-006 +Gc1_7 0 n2 ns7 0 2.25380222255e-006 +Gc1_8 0 n2 ns8 0 0.00717555669818 +Gc1_9 0 n2 ns9 0 -0.00307664149177 +Gc1_10 0 n2 ns10 0 -0.0294411442583 +Gc1_11 0 n2 ns11 0 0.00892186602486 +Gc1_12 0 n2 ns12 0 -0.00569082762578 +Gc1_13 0 n2 ns13 0 -0.000502300147173 +Gc1_14 0 n2 ns14 0 0.000240978294247 +Gc1_15 0 n2 ns15 0 0.00230965810648 +Gc1_16 0 n2 ns16 0 0.0117551565334 +Gc1_17 0 n2 ns17 0 0.00181273420273 +Gc1_18 0 n2 ns18 0 5.13868823089e-005 +Gc1_19 0 n2 ns19 0 -0.00142467791148 +Gc1_20 0 n2 ns20 0 -0.00563138554613 +Gc1_21 0 n2 ns21 0 -0.00067344543034 +Gc1_22 0 n2 ns22 0 1.6460757857e-006 +Gc1_23 0 n2 ns23 0 -2.8865828371e-007 +Gc1_24 0 n2 ns24 0 -0.000753112129945 +Gc1_25 0 n2 ns25 0 2.56421570732e-005 +Gc1_26 0 n2 ns26 0 0.000870566762999 +Gc1_27 0 n2 ns27 0 -0.00250625783205 +Gc1_28 0 n2 ns28 0 0.00261959282332 +Gc1_29 0 n2 ns29 0 7.88946953808e-006 +Gc1_30 0 n2 ns30 0 -0.000457857785365 +Gc1_31 0 n2 ns31 0 -0.000559757402081 +Gc1_32 0 n2 ns32 0 -0.0033379205368 +Gc1_33 0 n2 ns33 0 0.00181482205729 +Gc1_34 0 n2 ns34 0 4.74598285159e-005 +Gc1_35 0 n2 ns35 0 -0.00139120955451 +Gc1_36 0 n2 ns36 0 -0.00561846537429 +Gc1_37 0 n2 ns37 0 -0.00115561205552 +Gc1_38 0 n2 ns38 0 1.41440647168e-006 +Gc1_39 0 n2 ns39 0 8.24001503893e-007 +Gc1_40 0 n2 ns40 0 -0.00115006130002 +Gc1_41 0 n2 ns41 0 0.000594515639342 +Gc1_42 0 n2 ns42 0 0.00279580812674 +Gc1_43 0 n2 ns43 0 -0.00103263483195 +Gc1_44 0 n2 ns44 0 0.00257200342928 +Gc1_45 0 n2 ns45 0 -0.000423371062286 +Gc1_46 0 n2 ns46 0 -0.000293686690633 +Gc1_47 0 n2 ns47 0 -0.00235239190387 +Gc1_48 0 n2 ns48 0 -0.0031253054619 +Gc1_49 0 n2 ns49 0 -0.00188507278582 +Gc1_50 0 n2 ns50 0 -0.000136689959572 +Gc1_51 0 n2 ns51 0 -0.00280245518218 +Gc1_52 0 n2 ns52 0 -0.0112913988563 +Gc1_53 0 n2 ns53 0 -0.00181681958981 +Gc1_54 0 n2 ns54 0 1.16344937575e-006 +Gc1_55 0 n2 ns55 0 -9.29385987588e-007 +Gc1_56 0 n2 ns56 0 -0.00467247524999 +Gc1_57 0 n2 ns57 0 0.00433440231857 +Gc1_58 0 n2 ns58 0 0.01629275353 +Gc1_59 0 n2 ns59 0 -0.00823743048854 +Gc1_60 0 n2 ns60 0 0.00590818840057 +Gc1_61 0 n2 ns61 0 0.00056203932473 +Gc1_62 0 n2 ns62 0 9.49757780431e-005 +Gc1_63 0 n2 ns63 0 0.00140895920964 +Gc1_64 0 n2 ns64 0 -0.000903817466778 +Gc1_65 0 n2 ns65 0 -0.0017874282015 +Gc1_66 0 n2 ns66 0 -5.04777932224e-005 +Gc1_67 0 n2 ns67 0 0.00139917350212 +Gc1_68 0 n2 ns68 0 0.00562339494746 +Gc1_69 0 n2 ns69 0 0.00062246164172 +Gc1_70 0 n2 ns70 0 5.37350036174e-007 +Gc1_71 0 n2 ns71 0 4.48921765236e-008 +Gc1_72 0 n2 ns72 0 9.66166293412e-005 +Gc1_73 0 n2 ns73 0 0.00019685045563 +Gc1_74 0 n2 ns74 0 0.000805289410689 +Gc1_75 0 n2 ns75 0 0.000790675796302 +Gc1_76 0 n2 ns76 0 -0.00204180062166 +Gc1_77 0 n2 ns77 0 4.25187045437e-006 +Gc1_78 0 n2 ns78 0 0.000239287715086 +Gc1_79 0 n2 ns79 0 -0.0027600715481 +Gc1_80 0 n2 ns80 0 0.00291215710081 +Gc1_81 0 n2 ns81 0 -0.00179184540776 +Gc1_82 0 n2 ns82 0 -4.66594589744e-005 +Gc1_83 0 n2 ns83 0 0.0013687627466 +Gc1_84 0 n2 ns84 0 0.00560449430852 +Gc1_85 0 n2 ns85 0 0.00112028156113 +Gc1_86 0 n2 ns86 0 6.42464575584e-007 +Gc1_87 0 n2 ns87 0 -6.24872022941e-007 +Gc1_88 0 n2 ns88 0 0.000461135878954 +Gc1_89 0 n2 ns89 0 -0.000203398559629 +Gc1_90 0 n2 ns90 0 -0.000855317613403 +Gc1_91 0 n2 ns91 0 0.000503270926119 +Gc1_92 0 n2 ns92 0 -0.0027414218474 +Gc1_93 0 n2 ns93 0 0.000277397680353 +Gc1_94 0 n2 ns94 0 0.000116079001448 +Gc1_95 0 n2 ns95 0 -0.00326113205496 +Gc1_96 0 n2 ns96 0 0.00313284038654 +Gd1_1 0 n2 ni1 0 -0.00163432138453 +Gd1_2 0 n2 ni2 0 -0.000791912628427 +Gd1_3 0 n2 ni3 0 -0.0011590289916 +Gd1_4 0 n2 ni4 0 1.53160120031e-006 +Gd1_5 0 n2 ni5 0 -0.000989981468143 +Gd1_6 0 n2 ni6 0 -0.00143997812485 +Gc2_1 0 n4 ns1 0 0.00183955170558 +Gc2_2 0 n4 ns2 0 5.08266072087e-005 +Gc2_3 0 n4 ns3 0 -0.00143317003192 +Gc2_4 0 n4 ns4 0 -0.00561747647812 +Gc2_5 0 n4 ns5 0 -0.000676972254149 +Gc2_6 0 n4 ns6 0 1.65499837425e-006 +Gc2_7 0 n4 ns7 0 -3.04082246794e-007 +Gc2_8 0 n4 ns8 0 -0.000767913156564 +Gc2_9 0 n4 ns9 0 1.18236543063e-005 +Gc2_10 0 n4 ns10 0 0.000923483075744 +Gc2_11 0 n4 ns11 0 -0.00249562976063 +Gc2_12 0 n4 ns12 0 0.00259112666657 +Gc2_13 0 n4 ns13 0 6.86779259587e-006 +Gc2_14 0 n4 ns14 0 -0.000459836089421 +Gc2_15 0 n4 ns15 0 -0.000476502940176 +Gc2_16 0 n4 ns16 0 -0.00323932095262 +Gc2_17 0 n4 ns17 0 0.00192893640479 +Gc2_18 0 n4 ns18 0 0.000141374711691 +Gc2_19 0 n4 ns19 0 0.00271300098543 +Gc2_20 0 n4 ns20 0 0.0110549363398 +Gc2_21 0 n4 ns21 0 0.00177205296703 +Gc2_22 0 n4 ns22 0 -1.37041399724e-006 +Gc2_23 0 n4 ns23 0 8.12657666717e-007 +Gc2_24 0 n4 ns24 0 0.00582584437049 +Gc2_25 0 n4 ns25 0 -0.000485213324136 +Gc2_26 0 n4 ns26 0 -0.0210778617832 +Gc2_27 0 n4 ns27 0 0.0123633198428 +Gc2_28 0 n4 ns28 0 -0.000918745379166 +Gc2_29 0 n4 ns29 0 -0.000746772861547 +Gc2_30 0 n4 ns30 0 0.000112215465102 +Gc2_31 0 n4 ns31 0 -0.0065208472421 +Gc2_32 0 n4 ns32 0 0.00826939530559 +Gc2_33 0 n4 ns33 0 0.00181342151359 +Gc2_34 0 n4 ns34 0 4.54879941957e-005 +Gc2_35 0 n4 ns35 0 -0.00125310452699 +Gc2_36 0 n4 ns36 0 -0.00571334076383 +Gc2_37 0 n4 ns37 0 -0.00110600265242 +Gc2_38 0 n4 ns38 0 1.76551336387e-006 +Gc2_39 0 n4 ns39 0 1.26618098528e-006 +Gc2_40 0 n4 ns40 0 -6.32344280761e-005 +Gc2_41 0 n4 ns41 0 -0.000586486143832 +Gc2_42 0 n4 ns42 0 0.00224824383711 +Gc2_43 0 n4 ns43 0 -0.00093169880737 +Gc2_44 0 n4 ns44 0 0.00563215085629 +Gc2_45 0 n4 ns45 0 -0.000639188353906 +Gc2_46 0 n4 ns46 0 -0.000217200412977 +Gc2_47 0 n4 ns47 0 -0.00332262735884 +Gc2_48 0 n4 ns48 0 -0.00546108665333 +Gc2_49 0 n4 ns49 0 -0.00182665319289 +Gc2_50 0 n4 ns50 0 -4.98512505169e-005 +Gc2_51 0 n4 ns51 0 0.00141585972374 +Gc2_52 0 n4 ns52 0 0.00561950112372 +Gc2_53 0 n4 ns53 0 0.000623944570467 +Gc2_54 0 n4 ns54 0 6.67519595028e-007 +Gc2_55 0 n4 ns55 0 -1.4656203786e-007 +Gc2_56 0 n4 ns56 0 0.000246888198281 +Gc2_57 0 n4 ns57 0 -0.000144231186527 +Gc2_58 0 n4 ns58 0 0.00154714308759 +Gc2_59 0 n4 ns59 0 0.00119630405623 +Gc2_60 0 n4 ns60 0 -0.00307248321315 +Gc2_61 0 n4 ns61 0 4.52531383737e-005 +Gc2_62 0 n4 ns62 0 0.00025923817672 +Gc2_63 0 n4 ns63 0 -0.00277432785181 +Gc2_64 0 n4 ns64 0 0.0051044708958 +Gc2_65 0 n4 ns65 0 -0.00193530965554 +Gc2_66 0 n4 ns66 0 -0.000136685942664 +Gc2_67 0 n4 ns67 0 -0.00265412872147 +Gc2_68 0 n4 ns68 0 -0.0111022037525 +Gc2_69 0 n4 ns69 0 -0.00161341093459 +Gc2_70 0 n4 ns70 0 1.20914619401e-006 +Gc2_71 0 n4 ns71 0 9.19640790715e-008 +Gc2_72 0 n4 ns72 0 -0.00302194134686 +Gc2_73 0 n4 ns73 0 0.00127188858923 +Gc2_74 0 n4 ns74 0 0.00943595058958 +Gc2_75 0 n4 ns75 0 -0.00921433483883 +Gc2_76 0 n4 ns76 0 0.00205970750984 +Gc2_77 0 n4 ns77 0 0.00065137028995 +Gc2_78 0 n4 ns78 0 0.000134290965514 +Gc2_79 0 n4 ns79 0 0.00626874129911 +Gc2_80 0 n4 ns80 0 0.00260454325943 +Gc2_81 0 n4 ns81 0 -0.00179347696859 +Gc2_82 0 n4 ns82 0 -4.45281978026e-005 +Gc2_83 0 n4 ns83 0 0.00122549390629 +Gc2_84 0 n4 ns84 0 0.00569428281631 +Gc2_85 0 n4 ns85 0 0.00104241272539 +Gc2_86 0 n4 ns86 0 6.18849181478e-007 +Gc2_87 0 n4 ns87 0 -1.26009173306e-006 +Gc2_88 0 n4 ns88 0 -0.000440021611089 +Gc2_89 0 n4 ns89 0 0.000627030019307 +Gc2_90 0 n4 ns90 0 -0.000525289451385 +Gc2_91 0 n4 ns91 0 -0.00127742445294 +Gc2_92 0 n4 ns92 0 -0.00491824005739 +Gc2_93 0 n4 ns93 0 0.000611165789979 +Gc2_94 0 n4 ns94 0 9.51281962734e-005 +Gc2_95 0 n4 ns95 0 0.000719794925754 +Gc2_96 0 n4 ns96 0 0.00527812293028 +Gd2_1 0 n4 ni1 0 -0.000739301874335 +Gd2_2 0 n4 ni2 0 -0.00318264525508 +Gd2_3 0 n4 ni3 0 -0.00135858606465 +Gd2_4 0 n4 ni4 0 -0.000867061196114 +Gd2_5 0 n4 ni5 0 0.000877944303092 +Gd2_6 0 n4 ni6 0 -0.000302315780909 +Gc3_1 0 n6 ns1 0 0.00184292107377 +Gc3_2 0 n6 ns2 0 4.67829512553e-005 +Gc3_3 0 n6 ns3 0 -0.00140015024269 +Gc3_4 0 n6 ns4 0 -0.00560407219586 +Gc3_5 0 n6 ns5 0 -0.00115910208499 +Gc3_6 0 n6 ns6 0 1.39043103644e-006 +Gc3_7 0 n6 ns7 0 8.63706017202e-007 +Gc3_8 0 n6 ns8 0 -0.00116422265268 +Gc3_9 0 n6 ns9 0 0.000614327653991 +Gc3_10 0 n6 ns10 0 0.00279904436666 +Gc3_11 0 n6 ns11 0 -0.00105530828879 +Gc3_12 0 n6 ns12 0 0.00254327568813 +Gc3_13 0 n6 ns13 0 -0.000424609848355 +Gc3_14 0 n6 ns14 0 -0.000294723318137 +Gc3_15 0 n6 ns15 0 -0.00227341379808 +Gc3_16 0 n6 ns16 0 -0.00310902232019 +Gc3_17 0 n6 ns17 0 0.00184238986632 +Gc3_18 0 n6 ns18 0 4.48136357381e-005 +Gc3_19 0 n6 ns19 0 -0.00126200215677 +Gc3_20 0 n6 ns20 0 -0.00569940833984 +Gc3_21 0 n6 ns21 0 -0.00110799223828 +Gc3_22 0 n6 ns22 0 1.76627496265e-006 +Gc3_23 0 n6 ns23 0 1.27075652384e-006 +Gc3_24 0 n6 ns24 0 -8.3867357777e-005 +Gc3_25 0 n6 ns25 0 -0.000595616180961 +Gc3_26 0 n6 ns26 0 0.00229002316026 +Gc3_27 0 n6 ns27 0 -0.000927247629389 +Gc3_28 0 n6 ns28 0 0.00559588485804 +Gc3_29 0 n6 ns29 0 -0.000639856938352 +Gc3_30 0 n6 ns30 0 -0.000219663049437 +Gc3_31 0 n6 ns31 0 -0.00322452557316 +Gc3_32 0 n6 ns32 0 -0.00536688109896 +Gc3_33 0 n6 ns33 0 0.00192309188635 +Gc3_34 0 n6 ns34 0 0.0001464491055 +Gc3_35 0 n6 ns35 0 0.00272188869626 +Gc3_36 0 n6 ns36 0 0.0114379523354 +Gc3_37 0 n6 ns37 0 0.00252235719266 +Gc3_38 0 n6 ns38 0 -1.51647081743e-006 +Gc3_39 0 n6 ns39 0 1.0495115359e-006 +Gc3_40 0 n6 ns40 0 0.00559364818918 +Gc3_41 0 n6 ns41 0 -0.0046921980334 +Gc3_42 0 n6 ns42 0 -0.0348884395444 +Gc3_43 0 n6 ns43 0 0.0112652204944 +Gc3_44 0 n6 ns44 0 -0.0158125459237 +Gc3_45 0 n6 ns45 0 0.00116056089387 +Gc3_46 0 n6 ns46 0 0.00326551677716 +Gc3_47 0 n6 ns47 0 0.00477546531515 +Gc3_48 0 n6 ns48 0 0.0168856029934 +Gc3_49 0 n6 ns49 0 -0.00182940089499 +Gc3_50 0 n6 ns50 0 -4.59678650634e-005 +Gc3_51 0 n6 ns51 0 0.00138586653153 +Gc3_52 0 n6 ns52 0 0.00558248671494 +Gc3_53 0 n6 ns53 0 0.00112325215757 +Gc3_54 0 n6 ns54 0 5.06419368262e-007 +Gc3_55 0 n6 ns55 0 -5.61048034592e-007 +Gc3_56 0 n6 ns56 0 8.10372631611e-005 +Gc3_57 0 n6 ns57 0 0.00033320240619 +Gc3_58 0 n6 ns58 0 -0.00139413442198 +Gc3_59 0 n6 ns59 0 -0.00140633392877 +Gc3_60 0 n6 ns60 0 -0.00194560720444 +Gc3_61 0 n6 ns61 0 0.00024994427964 +Gc3_62 0 n6 ns62 0 -0.000246722543151 +Gc3_63 0 n6 ns63 0 -0.00055429918397 +Gc3_64 0 n6 ns64 0 0.00205610253281 +Gc3_65 0 n6 ns65 0 -0.00182813531567 +Gc3_66 0 n6 ns66 0 -4.41146486215e-005 +Gc3_67 0 n6 ns67 0 0.00124728940308 +Gc3_68 0 n6 ns68 0 0.00569082043165 +Gc3_69 0 n6 ns69 0 0.00108238483705 +Gc3_70 0 n6 ns70 0 1.01062092422e-007 +Gc3_71 0 n6 ns71 0 -1.04965879025e-006 +Gc3_72 0 n6 ns72 0 -0.000244508465076 +Gc3_73 0 n6 ns73 0 0.000835584508557 +Gc3_74 0 n6 ns74 0 -0.00131124737258 +Gc3_75 0 n6 ns75 0 -0.000154253990865 +Gc3_76 0 n6 ns76 0 -0.00402248921215 +Gc3_77 0 n6 ns77 0 0.000343231101531 +Gc3_78 0 n6 ns78 0 -6.73483350389e-005 +Gc3_79 0 n6 ns79 0 -0.00152878641808 +Gc3_80 0 n6 ns80 0 0.00321034466381 +Gc3_81 0 n6 ns81 0 -0.0019334870093 +Gc3_82 0 n6 ns82 0 -0.000142774411037 +Gc3_83 0 n6 ns83 0 -0.0026564687011 +Gc3_84 0 n6 ns84 0 -0.011477084185 +Gc3_85 0 n6 ns85 0 -0.00230731984164 +Gc3_86 0 n6 ns86 0 9.64078406122e-007 +Gc3_87 0 n6 ns87 0 5.58895006508e-007 +Gc3_88 0 n6 ns88 0 -0.0037477334857 +Gc3_89 0 n6 ns89 0 0.00543014881941 +Gc3_90 0 n6 ns90 0 0.022490122324 +Gc3_91 0 n6 ns91 0 -0.00946504981536 +Gc3_92 0 n6 ns92 0 0.0131179551535 +Gc3_93 0 n6 ns93 0 -0.000799914250593 +Gc3_94 0 n6 ns94 0 -0.0025220297412 +Gc3_95 0 n6 ns95 0 0.000737290979725 +Gc3_96 0 n6 ns96 0 -0.00198179597441 +Gd3_1 0 n6 ni1 0 -0.00112219283024 +Gd3_2 0 n6 ni2 0 -0.00130269082257 +Gd3_3 0 n6 ni3 0 -0.00103289722298 +Gd3_4 0 n6 ni4 0 -0.000867056889252 +Gd3_5 0 n6 ni5 0 -0.000995148221384 +Gd3_6 0 n6 ni6 0 0.000481197741819 +Gc4_1 0 n8 ns1 0 -0.00185809015262 +Gc4_2 0 n8 ns2 0 -0.00013639528351 +Gc4_3 0 n8 ns3 0 -0.00286590094735 +Gc4_4 0 n8 ns4 0 -0.0112126021326 +Gc4_5 0 n8 ns5 0 -0.00185048298085 +Gc4_6 0 n8 ns6 0 1.18482364168e-006 +Gc4_7 0 n8 ns7 0 -9.24763459868e-007 +Gc4_8 0 n8 ns8 0 -0.0046936586593 +Gc4_9 0 n8 ns9 0 0.00418769095764 +Gc4_10 0 n8 ns10 0 0.0167368997348 +Gc4_11 0 n8 ns11 0 -0.00813595843516 +Gc4_12 0 n8 ns12 0 0.00578599294522 +Gc4_13 0 n8 ns13 0 0.000556356754538 +Gc4_14 0 n8 ns14 0 8.32798050467e-005 +Gc4_15 0 n8 ns15 0 0.00185525129558 +Gc4_16 0 n8 ns16 0 -0.000197518844731 +Gc4_17 0 n8 ns17 0 -0.00181453987927 +Gc4_18 0 n8 ns18 0 -5.07449024639e-005 +Gc4_19 0 n8 ns19 0 0.00143972780184 +Gc4_20 0 n8 ns20 0 0.00559159233429 +Gc4_21 0 n8 ns21 0 0.000638095637457 +Gc4_22 0 n8 ns22 0 6.60127915535e-007 +Gc4_23 0 n8 ns23 0 -1.75452260912e-007 +Gc4_24 0 n8 ns24 0 0.000262507889488 +Gc4_25 0 n8 ns25 0 -0.000111327534732 +Gc4_26 0 n8 ns26 0 0.00139584653589 +Gc4_27 0 n8 ns27 0 0.00117760804619 +Gc4_28 0 n8 ns28 0 -0.00302972766239 +Gc4_29 0 n8 ns29 0 4.76703134955e-005 +Gc4_30 0 n8 ns30 0 0.000263315509107 +Gc4_31 0 n8 ns31 0 -0.00293332721879 +Gc4_32 0 n8 ns32 0 0.00488201193309 +Gc4_33 0 n8 ns33 0 -0.00181569306897 +Gc4_34 0 n8 ns34 0 -4.69635581097e-005 +Gc4_35 0 n8 ns35 0 0.00140950469896 +Gc4_36 0 n8 ns36 0 0.00555539858426 +Gc4_37 0 n8 ns37 0 0.00113441099918 +Gc4_38 0 n8 ns38 0 5.02076895848e-007 +Gc4_39 0 n8 ns39 0 -6.0756108912e-007 +Gc4_40 0 n8 ns40 0 0.000109923463958 +Gc4_41 0 n8 ns41 0 0.000336098950273 +Gc4_42 0 n8 ns42 0 -0.00149079357688 +Gc4_43 0 n8 ns43 0 -0.0013968878627 +Gc4_44 0 n8 ns44 0 -0.00189045938669 +Gc4_45 0 n8 ns45 0 0.000252937072939 +Gc4_46 0 n8 ns46 0 -0.000241813845148 +Gc4_47 0 n8 ns47 0 -0.000729589007103 +Gc4_48 0 n8 ns48 0 0.00189755779466 +Gc4_49 0 n8 ns49 0 0.00190794001785 +Gc4_50 0 n8 ns50 0 0.000134394694016 +Gc4_51 0 n8 ns51 0 0.00285631596527 +Gc4_52 0 n8 ns52 0 0.0110533530468 +Gc4_53 0 n8 ns53 0 0.00190420442686 +Gc4_54 0 n8 ns54 0 -9.15506741638e-007 +Gc4_55 0 n8 ns55 0 1.36445117279e-006 +Gc4_56 0 n8 ns56 0 0.00470030473842 +Gc4_57 0 n8 ns57 0 -0.00297183040935 +Gc4_58 0 n8 ns58 0 -0.0258051769674 +Gc4_59 0 n8 ns59 0 0.00597395256136 +Gc4_60 0 n8 ns60 0 -0.00422541484949 +Gc4_61 0 n8 ns61 0 -0.000619672071921 +Gc4_62 0 n8 ns62 0 -0.000125087615614 +Gc4_63 0 n8 ns63 0 0.00859781005384 +Gc4_64 0 n8 ns64 0 0.0146443492753 +Gc4_65 0 n8 ns65 0 0.00178940455683 +Gc4_66 0 n8 ns66 0 5.1025114079e-005 +Gc4_67 0 n8 ns67 0 -0.00141199074884 +Gc4_68 0 n8 ns68 0 -0.00557454993027 +Gc4_69 0 n8 ns69 0 -0.000601072073695 +Gc4_70 0 n8 ns70 0 1.37221937843e-006 +Gc4_71 0 n8 ns71 0 -3.97047661827e-008 +Gc4_72 0 n8 ns72 0 0.000429237547222 +Gc4_73 0 n8 ns73 0 -7.33837878558e-005 +Gc4_74 0 n8 ns74 0 -0.000815320155482 +Gc4_75 0 n8 ns75 0 9.50255085046e-005 +Gc4_76 0 n8 ns76 0 0.00213191211929 +Gc4_77 0 n8 ns77 0 -9.19646200497e-005 +Gc4_78 0 n8 ns78 0 -0.000214901036125 +Gc4_79 0 n8 ns79 0 -0.00520969824214 +Gc4_80 0 n8 ns80 0 -0.00518056481885 +Gc4_81 0 n8 ns81 0 0.00179345683457 +Gc4_82 0 n8 ns82 0 4.7325526603e-005 +Gc4_83 0 n8 ns83 0 -0.00138167033382 +Gc4_84 0 n8 ns84 0 -0.00553792986581 +Gc4_85 0 n8 ns85 0 -0.00108517498143 +Gc4_86 0 n8 ns86 0 1.60089819244e-006 +Gc4_87 0 n8 ns87 0 1.02955368236e-006 +Gc4_88 0 n8 ns88 0 0.000422387112946 +Gc4_89 0 n8 ns89 0 -0.00010528590563 +Gc4_90 0 n8 ns90 0 0.00115572589668 +Gc4_91 0 n8 ns91 0 0.00118852941275 +Gc4_92 0 n8 ns92 0 0.00175707508226 +Gc4_93 0 n8 ns93 0 -0.000225706218252 +Gc4_94 0 n8 ns94 0 0.000166550637417 +Gc4_95 0 n8 ns95 0 -0.00664626832503 +Gc4_96 0 n8 ns96 0 -0.0040606024956 +Gd4_1 0 n8 ni1 0 0.00034257394785 +Gd4_2 0 n8 ni2 0 -0.000979055833721 +Gd4_3 0 n8 ni3 0 -0.000968701358427 +Gd4_4 0 n8 ni4 0 -0.000323985842042 +Gd4_5 0 n8 ni5 0 -0.00187973237953 +Gd4_6 0 n8 ni6 0 -0.00204905846063 +Gc5_1 0 n10 ns1 0 -0.001846697649 +Gc5_2 0 n10 ns2 0 -4.96998724682e-005 +Gc5_3 0 n10 ns3 0 0.00143261753016 +Gc5_4 0 n10 ns4 0 0.00558245956517 +Gc5_5 0 n10 ns5 0 0.000630777793649 +Gc5_6 0 n10 ns6 0 4.8955033657e-007 +Gc5_7 0 n10 ns7 0 6.82364696863e-008 +Gc5_8 0 n10 ns8 0 0.000151011681839 +Gc5_9 0 n10 ns9 0 0.000234644603037 +Gc5_10 0 n10 ns10 0 0.000635802955179 +Gc5_11 0 n10 ns11 0 0.000772590666758 +Gc5_12 0 n10 ns12 0 -0.00194892927883 +Gc5_13 0 n10 ns13 0 8.97271768462e-006 +Gc5_14 0 n10 ns14 0 0.00024650966284 +Gc5_15 0 n10 ns15 0 -0.00305118841848 +Gc5_16 0 n10 ns16 0 0.00259847489168 +Gc5_17 0 n10 ns17 0 -0.00187029012217 +Gc5_18 0 n10 ns18 0 -0.000137788628677 +Gc5_19 0 n10 ns19 0 -0.00270273970575 +Gc5_20 0 n10 ns20 0 -0.0110479226011 +Gc5_21 0 n10 ns21 0 -0.00162613465101 +Gc5_22 0 n10 ns22 0 1.21590801337e-006 +Gc5_23 0 n10 ns23 0 6.6904116429e-008 +Gc5_24 0 n10 ns24 0 -0.0030590479191 +Gc5_25 0 n10 ns25 0 0.0011889740887 +Gc5_26 0 n10 ns26 0 0.00965885886624 +Gc5_27 0 n10 ns27 0 -0.00916310693603 +Gc5_28 0 n10 ns28 0 0.0019747928047 +Gc5_29 0 n10 ns29 0 0.000645151908104 +Gc5_30 0 n10 ns30 0 0.000125758242854 +Gc5_31 0 n10 ns31 0 0.00657950153361 +Gc5_32 0 n10 ns32 0 0.00300714650547 +Gc5_33 0 n10 ns33 0 -0.00181391761916 +Gc5_34 0 n10 ns34 0 -4.50839724617e-005 +Gc5_35 0 n10 ns35 0 0.00127154487697 +Gc5_36 0 n10 ns36 0 0.00566221286781 +Gc5_37 0 n10 ns37 0 0.00109600636526 +Gc5_38 0 n10 ns38 0 9.3984104594e-008 +Gc5_39 0 n10 ns39 0 -1.0934787012e-006 +Gc5_40 0 n10 ns40 0 -0.000226467274411 +Gc5_41 0 n10 ns41 0 0.000874090458042 +Gc5_42 0 n10 ns42 0 -0.00146650224358 +Gc5_43 0 n10 ns43 0 -0.00017898475665 +Gc5_44 0 n10 ns44 0 -0.00397705133226 +Gc5_45 0 n10 ns45 0 0.0003451414594 +Gc5_46 0 n10 ns46 0 -6.2781492446e-005 +Gc5_47 0 n10 ns47 0 -0.00168918542081 +Gc5_48 0 n10 ns48 0 0.00297441111731 +Gc5_49 0 n10 ns49 0 0.0018329122502 +Gc5_50 0 n10 ns50 0 5.04045530786e-005 +Gc5_51 0 n10 ns51 0 -0.00141369972275 +Gc5_52 0 n10 ns52 0 -0.00557442089394 +Gc5_53 0 n10 ns53 0 -0.000593738202398 +Gc5_54 0 n10 ns54 0 1.37195944987e-006 +Gc5_55 0 n10 ns55 0 -9.52306639624e-008 +Gc5_56 0 n10 ns56 0 0.000413789585165 +Gc5_57 0 n10 ns57 0 -7.64519894289e-005 +Gc5_58 0 n10 ns58 0 -0.000840220035929 +Gc5_59 0 n10 ns59 0 9.5208495874e-005 +Gc5_60 0 n10 ns60 0 0.0021186590487 +Gc5_61 0 n10 ns61 0 -9.21872166536e-005 +Gc5_62 0 n10 ns62 0 -0.000215583702741 +Gc5_63 0 n10 ns63 0 -0.0051789615092 +Gc5_64 0 n10 ns64 0 -0.00517734066764 +Gc5_65 0 n10 ns65 0 0.00188429761001 +Gc5_66 0 n10 ns66 0 0.000140480452973 +Gc5_67 0 n10 ns67 0 0.00266660609013 +Gc5_68 0 n10 ns68 0 0.0109717309705 +Gc5_69 0 n10 ns69 0 0.00161214415368 +Gc5_70 0 n10 ns70 0 -9.26199071739e-007 +Gc5_71 0 n10 ns71 0 3.27383246776e-007 +Gc5_72 0 n10 ns72 0 0.00281405282766 +Gc5_73 0 n10 ns73 0 -0.000389835729126 +Gc5_74 0 n10 ns74 0 -0.0176852860974 +Gc5_75 0 n10 ns75 0 0.00580255188707 +Gc5_76 0 n10 ns76 0 -0.00146396034186 +Gc5_77 0 n10 ns77 0 -0.00062452737721 +Gc5_78 0 n10 ns78 0 -0.000137172990537 +Gc5_79 0 n10 ns79 0 0.00693743464049 +Gc5_80 0 n10 ns80 0 0.0144852046677 +Gc5_81 0 n10 ns81 0 0.00179420234593 +Gc5_82 0 n10 ns82 0 4.51371744146e-005 +Gc5_83 0 n10 ns83 0 -0.00123963566804 +Gc5_84 0 n10 ns84 0 -0.00564023305904 +Gc5_85 0 n10 ns85 0 -0.0010235987254 +Gc5_86 0 n10 ns86 0 1.21330462516e-006 +Gc5_87 0 n10 ns87 0 1.38344122725e-006 +Gc5_88 0 n10 ns88 0 0.000609001304606 +Gc5_89 0 n10 ns89 0 -0.000637021971719 +Gc5_90 0 n10 ns90 0 0.00121770027029 +Gc5_91 0 n10 ns91 0 0.00157522173704 +Gc5_92 0 n10 ns92 0 0.00315083573559 +Gc5_93 0 n10 ns93 0 -0.000365213312999 +Gc5_94 0 n10 ns94 0 -3.54288676572e-005 +Gc5_95 0 n10 ns95 0 -0.00672384274439 +Gc5_96 0 n10 ns96 0 -0.00452947356827 +Gd5_1 0 n10 ni1 0 -0.00116565704415 +Gd5_2 0 n10 ni2 0 0.00108857519152 +Gd5_3 0 n10 ni3 0 -0.00110889909811 +Gd5_4 0 n10 ni4 0 -0.00187182381375 +Gd5_5 0 n10 ni5 0 -6.31307606078e-005 +Gd5_6 0 n10 ni6 0 -0.00191824339396 +Gc6_1 0 n12 ns1 0 -0.00184897591748 +Gc6_2 0 n12 ns2 0 -4.60850118935e-005 +Gc6_3 0 n12 ns3 0 0.00140320287292 +Gc6_4 0 n12 ns4 0 0.00556231491379 +Gc6_5 0 n12 ns5 0 0.00112851329442 +Gc6_6 0 n12 ns6 0 6.28416063517e-007 +Gc6_7 0 n12 ns7 0 -5.8084200288e-007 +Gc6_8 0 n12 ns8 0 0.00052160796382 +Gc6_9 0 n12 ns9 0 -0.000157579952052 +Gc6_10 0 n12 ns10 0 -0.0010342772179 +Gc6_11 0 n12 ns11 0 0.00048016020322 +Gc6_12 0 n12 ns12 0 -0.00263775844619 +Gc6_13 0 n12 ns13 0 0.000281203468007 +Gc6_14 0 n12 ns14 0 0.000125273286425 +Gc6_15 0 n12 ns15 0 -0.00356810237317 +Gc6_16 0 n12 ns16 0 0.00278602833959 +Gc6_17 0 n12 ns17 0 -0.00184913356749 +Gc6_18 0 n12 ns18 0 -4.38235727302e-005 +Gc6_19 0 n12 ns19 0 0.00125972135571 +Gc6_20 0 n12 ns20 0 0.00565256323273 +Gc6_21 0 n12 ns21 0 0.00104995787261 +Gc6_22 0 n12 ns22 0 5.81825220721e-007 +Gc6_23 0 n12 ns23 0 -1.20055651564e-006 +Gc6_24 0 n12 ns24 0 -0.000379798614295 +Gc6_25 0 n12 ns25 0 0.000672997277843 +Gc6_26 0 n12 ns26 0 -0.000708075561022 +Gc6_27 0 n12 ns27 0 -0.00129726305697 +Gc6_28 0 n12 ns28 0 -0.00481333046692 +Gc6_29 0 n12 ns29 0 0.000614601470654 +Gc6_30 0 n12 ns30 0 0.000104003640459 +Gc6_31 0 n12 ns31 0 0.000401152000692 +Gc6_32 0 n12 ns32 0 0.00492554587062 +Gc6_33 0 n12 ns33 0 -0.00187496991245 +Gc6_34 0 n12 ns34 0 -0.000143607173838 +Gc6_35 0 n12 ns35 0 -0.00270617232191 +Gc6_36 0 n12 ns36 0 -0.0114200434578 +Gc6_37 0 n12 ns37 0 -0.00232293730169 +Gc6_38 0 n12 ns38 0 9.8019841055e-007 +Gc6_39 0 n12 ns39 0 4.58009694877e-007 +Gc6_40 0 n12 ns40 0 -0.00377527846012 +Gc6_41 0 n12 ns41 0 0.00528760251585 +Gc6_42 0 n12 ns42 0 0.0227572777598 +Gc6_43 0 n12 ns43 0 -0.00936865244237 +Gc6_44 0 n12 ns44 0 0.0130370939149 +Gc6_45 0 n12 ns45 0 -0.000800850858667 +Gc6_46 0 n12 ns46 0 -0.00252752926019 +Gc6_47 0 n12 ns47 0 0.0010317699454 +Gc6_48 0 n12 ns48 0 -0.0014844205924 +Gc6_49 0 n12 ns49 0 0.00183499389848 +Gc6_50 0 n12 ns50 0 4.66768498108e-005 +Gc6_51 0 n12 ns51 0 -0.00138330492468 +Gc6_52 0 n12 ns52 0 -0.00553782454657 +Gc6_53 0 n12 ns53 0 -0.00107737630205 +Gc6_54 0 n12 ns54 0 1.59733291427e-006 +Gc6_55 0 n12 ns55 0 9.83611541497e-007 +Gc6_56 0 n12 ns56 0 0.000410211941289 +Gc6_57 0 n12 ns57 0 -9.50175612421e-005 +Gc6_58 0 n12 ns58 0 0.00110574852448 +Gc6_59 0 n12 ns59 0 0.00117447535373 +Gc6_60 0 n12 ns60 0 0.00174979739981 +Gc6_61 0 n12 ns61 0 -0.000226829694989 +Gc6_62 0 n12 ns62 0 0.000166473391529 +Gc6_63 0 n12 ns63 0 -0.0066232887195 +Gc6_64 0 n12 ns64 0 -0.00410141660908 +Gc6_65 0 n12 ns65 0 0.00183449588732 +Gc6_66 0 n12 ns66 0 4.44472012026e-005 +Gc6_67 0 n12 ns67 0 -0.00124060698572 +Gc6_68 0 n12 ns68 0 -0.00564154366444 +Gc6_69 0 n12 ns69 0 -0.00101532920502 +Gc6_70 0 n12 ns70 0 1.20816698231e-006 +Gc6_71 0 n12 ns71 0 1.32263264434e-006 +Gc6_72 0 n12 ns72 0 0.000588528571769 +Gc6_73 0 n12 ns73 0 -0.000632695306314 +Gc6_74 0 n12 ns74 0 0.00117959453275 +Gc6_75 0 n12 ns75 0 0.00156849515387 +Gc6_76 0 n12 ns76 0 0.00313257302526 +Gc6_77 0 n12 ns77 0 -0.000365781464274 +Gc6_78 0 n12 ns78 0 -3.65498287395e-005 +Gc6_79 0 n12 ns79 0 -0.00668485056237 +Gc6_80 0 n12 ns80 0 -0.00453925708566 +Gc6_81 0 n12 ns81 0 0.00188143354602 +Gc6_82 0 n12 ns82 0 0.000146141681754 +Gc6_83 0 n12 ns83 0 0.00266768440843 +Gc6_84 0 n12 ns84 0 0.011322718989 +Gc6_85 0 n12 ns85 0 0.00228395050733 +Gc6_86 0 n12 ns86 0 -1.91048428479e-007 +Gc6_87 0 n12 ns87 0 5.59043074168e-007 +Gc6_88 0 n12 ns88 0 0.00384617945674 +Gc6_89 0 n12 ns89 0 -0.00390084499396 +Gc6_90 0 n12 ns90 0 -0.0306367956429 +Gc6_91 0 n12 ns91 0 0.00641525357435 +Gc6_92 0 n12 ns92 0 -0.00986397581419 +Gc6_93 0 n12 ns93 0 0.000400423920706 +Gc6_94 0 n12 ns94 0 0.00206014528348 +Gc6_95 0 n12 ns95 0 0.0119274456924 +Gc6_96 0 n12 ns96 0 0.0157365330919 +Gd6_1 0 n12 ni1 0 -0.00162328253998 +Gd6_2 0 n12 ni2 0 -0.000492039218668 +Gd6_3 0 n12 ni3 0 0.000702375978424 +Gd6_4 0 n12 ni4 0 -0.00205051640558 +Gd6_5 0 n12 ni5 0 -0.00191122187003 +Gd6_6 0 n12 ni6 0 0.000742722822201 +.ends + +.subckt 744839029220 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 109405168.408 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 669600.284845 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 122619.221081 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 78691.8213997 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 16987.3369902 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 5205.20182516 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 18011.8015748 +Ra8 ns8 0 18011.8015748 +Ga7 ns7 0 ns8 0 -0.000263984688525 +Ga8 ns8 0 ns7 0 0.000263984688525 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 16681.0237286 +Ra10 ns10 0 16681.0237286 +Ga9 ns9 0 ns10 0 -0.000279858918947 +Ga10 ns10 0 ns9 0 0.000279858918947 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 13276.3452589 +Ra12 ns12 0 13276.3452589 +Ga11 ns11 0 ns12 0 -0.000328552969858 +Ga12 ns12 0 ns11 0 0.000328552969858 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 1413.07933985 +Ra14 ns14 0 1413.07933985 +Ga13 ns13 0 ns14 0 -0.000596411398295 +Ga14 ns14 0 ns13 0 0.000596411398295 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 6473.92437606 +Ra16 ns16 0 6473.92437606 +Ga15 ns15 0 ns16 0 -0.000929112152694 +Ga16 ns16 0 ns15 0 0.000929112152694 +Ca17 ns17 0 1e-012 +Ra17 ns17 0 109405168.408 +Ca18 ns18 0 1e-012 +Ra18 ns18 0 669600.284845 +Ca19 ns19 0 1e-012 +Ra19 ns19 0 122619.221081 +Ca20 ns20 0 1e-012 +Ra20 ns20 0 78691.8213997 +Ca21 ns21 0 1e-012 +Ra21 ns21 0 16987.3369902 +Ca22 ns22 0 1e-012 +Ra22 ns22 0 5205.20182516 +Ca23 ns23 0 1e-012 +Ca24 ns24 0 1e-012 +Ra23 ns23 0 18011.8015748 +Ra24 ns24 0 18011.8015748 +Ga23 ns23 0 ns24 0 -0.000263984688525 +Ga24 ns24 0 ns23 0 0.000263984688525 +Ca25 ns25 0 1e-012 +Ca26 ns26 0 1e-012 +Ra25 ns25 0 16681.0237286 +Ra26 ns26 0 16681.0237286 +Ga25 ns25 0 ns26 0 -0.000279858918947 +Ga26 ns26 0 ns25 0 0.000279858918947 +Ca27 ns27 0 1e-012 +Ca28 ns28 0 1e-012 +Ra27 ns27 0 13276.3452589 +Ra28 ns28 0 13276.3452589 +Ga27 ns27 0 ns28 0 -0.000328552969858 +Ga28 ns28 0 ns27 0 0.000328552969858 +Ca29 ns29 0 1e-012 +Ca30 ns30 0 1e-012 +Ra29 ns29 0 1413.07933985 +Ra30 ns30 0 1413.07933985 +Ga29 ns29 0 ns30 0 -0.000596411398295 +Ga30 ns30 0 ns29 0 0.000596411398295 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 6473.92437606 +Ra32 ns32 0 6473.92437606 +Ga31 ns31 0 ns32 0 -0.000929112152694 +Ga32 ns32 0 ns31 0 0.000929112152694 +Ca33 ns33 0 1e-012 +Ra33 ns33 0 109405168.408 +Ca34 ns34 0 1e-012 +Ra34 ns34 0 669600.284845 +Ca35 ns35 0 1e-012 +Ra35 ns35 0 122619.221081 +Ca36 ns36 0 1e-012 +Ra36 ns36 0 78691.8213997 +Ca37 ns37 0 1e-012 +Ra37 ns37 0 16987.3369902 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 5205.20182516 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 18011.8015748 +Ra40 ns40 0 18011.8015748 +Ga39 ns39 0 ns40 0 -0.000263984688525 +Ga40 ns40 0 ns39 0 0.000263984688525 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 16681.0237286 +Ra42 ns42 0 16681.0237286 +Ga41 ns41 0 ns42 0 -0.000279858918947 +Ga42 ns42 0 ns41 0 0.000279858918947 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 13276.3452589 +Ra44 ns44 0 13276.3452589 +Ga43 ns43 0 ns44 0 -0.000328552969858 +Ga44 ns44 0 ns43 0 0.000328552969858 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 1413.07933985 +Ra46 ns46 0 1413.07933985 +Ga45 ns45 0 ns46 0 -0.000596411398295 +Ga46 ns46 0 ns45 0 0.000596411398295 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 6473.92437606 +Ra48 ns48 0 6473.92437606 +Ga47 ns47 0 ns48 0 -0.000929112152694 +Ga48 ns48 0 ns47 0 0.000929112152694 +Ca49 ns49 0 1e-012 +Ra49 ns49 0 109405168.408 +Ca50 ns50 0 1e-012 +Ra50 ns50 0 669600.284845 +Ca51 ns51 0 1e-012 +Ra51 ns51 0 122619.221081 +Ca52 ns52 0 1e-012 +Ra52 ns52 0 78691.8213997 +Ca53 ns53 0 1e-012 +Ra53 ns53 0 16987.3369902 +Ca54 ns54 0 1e-012 +Ra54 ns54 0 5205.20182516 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 18011.8015748 +Ra56 ns56 0 18011.8015748 +Ga55 ns55 0 ns56 0 -0.000263984688525 +Ga56 ns56 0 ns55 0 0.000263984688525 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 16681.0237286 +Ra58 ns58 0 16681.0237286 +Ga57 ns57 0 ns58 0 -0.000279858918947 +Ga58 ns58 0 ns57 0 0.000279858918947 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 13276.3452589 +Ra60 ns60 0 13276.3452589 +Ga59 ns59 0 ns60 0 -0.000328552969858 +Ga60 ns60 0 ns59 0 0.000328552969858 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 1413.07933985 +Ra62 ns62 0 1413.07933985 +Ga61 ns61 0 ns62 0 -0.000596411398295 +Ga62 ns62 0 ns61 0 0.000596411398295 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 6473.92437606 +Ra64 ns64 0 6473.92437606 +Ga63 ns63 0 ns64 0 -0.000929112152694 +Ga64 ns64 0 ns63 0 0.000929112152694 +Ca65 ns65 0 1e-012 +Ra65 ns65 0 109405168.408 +Ca66 ns66 0 1e-012 +Ra66 ns66 0 669600.284845 +Ca67 ns67 0 1e-012 +Ra67 ns67 0 122619.221081 +Ca68 ns68 0 1e-012 +Ra68 ns68 0 78691.8213997 +Ca69 ns69 0 1e-012 +Ra69 ns69 0 16987.3369902 +Ca70 ns70 0 1e-012 +Ra70 ns70 0 5205.20182516 +Ca71 ns71 0 1e-012 +Ca72 ns72 0 1e-012 +Ra71 ns71 0 18011.8015748 +Ra72 ns72 0 18011.8015748 +Ga71 ns71 0 ns72 0 -0.000263984688525 +Ga72 ns72 0 ns71 0 0.000263984688525 +Ca73 ns73 0 1e-012 +Ca74 ns74 0 1e-012 +Ra73 ns73 0 16681.0237286 +Ra74 ns74 0 16681.0237286 +Ga73 ns73 0 ns74 0 -0.000279858918947 +Ga74 ns74 0 ns73 0 0.000279858918947 +Ca75 ns75 0 1e-012 +Ca76 ns76 0 1e-012 +Ra75 ns75 0 13276.3452589 +Ra76 ns76 0 13276.3452589 +Ga75 ns75 0 ns76 0 -0.000328552969858 +Ga76 ns76 0 ns75 0 0.000328552969858 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 1413.07933985 +Ra78 ns78 0 1413.07933985 +Ga77 ns77 0 ns78 0 -0.000596411398295 +Ga78 ns78 0 ns77 0 0.000596411398295 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 6473.92437606 +Ra80 ns80 0 6473.92437606 +Ga79 ns79 0 ns80 0 -0.000929112152694 +Ga80 ns80 0 ns79 0 0.000929112152694 +Ca81 ns81 0 1e-012 +Ra81 ns81 0 109405168.408 +Ca82 ns82 0 1e-012 +Ra82 ns82 0 669600.284845 +Ca83 ns83 0 1e-012 +Ra83 ns83 0 122619.221081 +Ca84 ns84 0 1e-012 +Ra84 ns84 0 78691.8213997 +Ca85 ns85 0 1e-012 +Ra85 ns85 0 16987.3369902 +Ca86 ns86 0 1e-012 +Ra86 ns86 0 5205.20182516 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 18011.8015748 +Ra88 ns88 0 18011.8015748 +Ga87 ns87 0 ns88 0 -0.000263984688525 +Ga88 ns88 0 ns87 0 0.000263984688525 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 16681.0237286 +Ra90 ns90 0 16681.0237286 +Ga89 ns89 0 ns90 0 -0.000279858918947 +Ga90 ns90 0 ns89 0 0.000279858918947 +Ca91 ns91 0 1e-012 +Ca92 ns92 0 1e-012 +Ra91 ns91 0 13276.3452589 +Ra92 ns92 0 13276.3452589 +Ga91 ns91 0 ns92 0 -0.000328552969858 +Ga92 ns92 0 ns91 0 0.000328552969858 +Ca93 ns93 0 1e-012 +Ca94 ns94 0 1e-012 +Ra93 ns93 0 1413.07933985 +Ra94 ns94 0 1413.07933985 +Ga93 ns93 0 ns94 0 -0.000596411398295 +Ga94 ns94 0 ns93 0 0.000596411398295 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 6473.92437606 +Ra96 ns96 0 6473.92437606 +Ga95 ns95 0 ns96 0 -0.000929112152694 +Ga96 ns96 0 ns95 0 0.000929112152694 + +Gb1_1 ns1 0 ni1 0 9.14033600562e-009 +Gb2_1 ns2 0 ni1 0 1.49342827749e-006 +Gb3_1 ns3 0 ni1 0 8.15532826894e-006 +Gb4_1 ns4 0 ni1 0 1.27078009152e-005 +Gb5_1 ns5 0 ni1 0 5.88673787171e-005 +Gb6_1 ns6 0 ni1 0 0.000192115509367 +Gb7_1 ns7 0 ni1 0 0.000275661034482 +Gb9_1 ns9 0 ni1 0 0.000292700409823 +Gb11_1 ns11 0 ni1 0 0.000345820790413 +Gb13_1 ns13 0 ni1 0 0.001210315933 +Gb15_1 ns15 0 ni1 0 0.000954792247068 +Gb17_2 ns17 0 ni2 0 9.14033600562e-009 +Gb18_2 ns18 0 ni2 0 1.49342827749e-006 +Gb19_2 ns19 0 ni2 0 8.15532826894e-006 +Gb20_2 ns20 0 ni2 0 1.27078009152e-005 +Gb21_2 ns21 0 ni2 0 5.88673787171e-005 +Gb22_2 ns22 0 ni2 0 0.000192115509367 +Gb23_2 ns23 0 ni2 0 0.000275661034482 +Gb25_2 ns25 0 ni2 0 0.000292700409823 +Gb27_2 ns27 0 ni2 0 0.000345820790413 +Gb29_2 ns29 0 ni2 0 0.001210315933 +Gb31_2 ns31 0 ni2 0 0.000954792247068 +Gb33_3 ns33 0 ni3 0 9.14033600562e-009 +Gb34_3 ns34 0 ni3 0 1.49342827749e-006 +Gb35_3 ns35 0 ni3 0 8.15532826894e-006 +Gb36_3 ns36 0 ni3 0 1.27078009152e-005 +Gb37_3 ns37 0 ni3 0 5.88673787171e-005 +Gb38_3 ns38 0 ni3 0 0.000192115509367 +Gb39_3 ns39 0 ni3 0 0.000275661034482 +Gb41_3 ns41 0 ni3 0 0.000292700409823 +Gb43_3 ns43 0 ni3 0 0.000345820790413 +Gb45_3 ns45 0 ni3 0 0.001210315933 +Gb47_3 ns47 0 ni3 0 0.000954792247068 +Gb49_4 ns49 0 ni4 0 9.14033600562e-009 +Gb50_4 ns50 0 ni4 0 1.49342827749e-006 +Gb51_4 ns51 0 ni4 0 8.15532826894e-006 +Gb52_4 ns52 0 ni4 0 1.27078009152e-005 +Gb53_4 ns53 0 ni4 0 5.88673787171e-005 +Gb54_4 ns54 0 ni4 0 0.000192115509367 +Gb55_4 ns55 0 ni4 0 0.000275661034482 +Gb57_4 ns57 0 ni4 0 0.000292700409823 +Gb59_4 ns59 0 ni4 0 0.000345820790413 +Gb61_4 ns61 0 ni4 0 0.001210315933 +Gb63_4 ns63 0 ni4 0 0.000954792247068 +Gb65_5 ns65 0 ni5 0 9.14033600562e-009 +Gb66_5 ns66 0 ni5 0 1.49342827749e-006 +Gb67_5 ns67 0 ni5 0 8.15532826894e-006 +Gb68_5 ns68 0 ni5 0 1.27078009152e-005 +Gb69_5 ns69 0 ni5 0 5.88673787171e-005 +Gb70_5 ns70 0 ni5 0 0.000192115509367 +Gb71_5 ns71 0 ni5 0 0.000275661034482 +Gb73_5 ns73 0 ni5 0 0.000292700409823 +Gb75_5 ns75 0 ni5 0 0.000345820790413 +Gb77_5 ns77 0 ni5 0 0.001210315933 +Gb79_5 ns79 0 ni5 0 0.000954792247068 +Gb81_6 ns81 0 ni6 0 9.14033600562e-009 +Gb82_6 ns82 0 ni6 0 1.49342827749e-006 +Gb83_6 ns83 0 ni6 0 8.15532826894e-006 +Gb84_6 ns84 0 ni6 0 1.27078009152e-005 +Gb85_6 ns85 0 ni6 0 5.88673787171e-005 +Gb86_6 ns86 0 ni6 0 0.000192115509367 +Gb87_6 ns87 0 ni6 0 0.000275661034482 +Gb89_6 ns89 0 ni6 0 0.000292700409823 +Gb91_6 ns91 0 ni6 0 0.000345820790413 +Gb93_6 ns93 0 ni6 0 0.001210315933 +Gb95_6 ns95 0 ni6 0 0.000954792247068 + +Gc1_1 0 n2 ns1 0 0.00106079727271 +Gc1_2 0 n2 ns2 0 0.00017481165618 +Gc1_3 0 n2 ns3 0 0.00866182245497 +Gc1_4 0 n2 ns4 0 0.00461512494716 +Gc1_5 0 n2 ns5 0 0.00049497891456 +Gc1_6 0 n2 ns6 0 -0.000315016183903 +Gc1_7 0 n2 ns7 0 0.0012061253753 +Gc1_8 0 n2 ns8 0 -0.00074348106096 +Gc1_9 0 n2 ns9 0 0.00423946424488 +Gc1_10 0 n2 ns10 0 -0.00167442948658 +Gc1_11 0 n2 ns11 0 0.00186484965639 +Gc1_12 0 n2 ns12 0 -0.00151083340265 +Gc1_13 0 n2 ns13 0 -0.00173422623208 +Gc1_14 0 n2 ns14 0 0.038297016452 +Gc1_15 0 n2 ns15 0 0.00210765842889 +Gc1_16 0 n2 ns16 0 -0.0068664679201 +Gc1_17 0 n2 ns17 0 0.000927303285244 +Gc1_18 0 n2 ns18 0 -5.2334164481e-005 +Gc1_19 0 n2 ns19 0 -0.00430504997088 +Gc1_20 0 n2 ns20 0 -0.00231320385701 +Gc1_21 0 n2 ns21 0 -0.000279430336156 +Gc1_22 0 n2 ns22 0 -5.4543725011e-005 +Gc1_23 0 n2 ns23 0 0.000845215049568 +Gc1_24 0 n2 ns24 0 -0.000279234543563 +Gc1_25 0 n2 ns25 0 -0.00381626962658 +Gc1_26 0 n2 ns26 0 0.00171659307342 +Gc1_27 0 n2 ns27 0 0.00259000947261 +Gc1_28 0 n2 ns28 0 -0.00197440319228 +Gc1_29 0 n2 ns29 0 -0.000119492077101 +Gc1_30 0 n2 ns30 0 -0.00137590212682 +Gc1_31 0 n2 ns31 0 -0.000334528976032 +Gc1_32 0 n2 ns32 0 0.00143382374867 +Gc1_33 0 n2 ns33 0 0.000927512123867 +Gc1_34 0 n2 ns34 0 -4.00675944389e-005 +Gc1_35 0 n2 ns35 0 -0.00436118934267 +Gc1_36 0 n2 ns36 0 -0.0022935329844 +Gc1_37 0 n2 ns37 0 -0.000208515896548 +Gc1_38 0 n2 ns38 0 -0.000153560309903 +Gc1_39 0 n2 ns39 0 -0.00278199525532 +Gc1_40 0 n2 ns40 0 0.00101188019381 +Gc1_41 0 n2 ns41 0 0.000987945300553 +Gc1_42 0 n2 ns42 0 -0.000369436612214 +Gc1_43 0 n2 ns43 0 0.0014304088743 +Gc1_44 0 n2 ns44 0 -0.0011594797319 +Gc1_45 0 n2 ns45 0 -8.79604385754e-005 +Gc1_46 0 n2 ns46 0 -0.00152357149044 +Gc1_47 0 n2 ns47 0 -0.000378584195055 +Gc1_48 0 n2 ns48 0 0.00152162309395 +Gc1_49 0 n2 ns49 0 -0.00096971880428 +Gc1_50 0 n2 ns50 0 -0.00017132947433 +Gc1_51 0 n2 ns51 0 -0.00866043900187 +Gc1_52 0 n2 ns52 0 -0.00461262270065 +Gc1_53 0 n2 ns53 0 -0.000485568265711 +Gc1_54 0 n2 ns54 0 -0.000181760463972 +Gc1_55 0 n2 ns55 0 -0.000849275035589 +Gc1_56 0 n2 ns56 0 0.000473293475147 +Gc1_57 0 n2 ns57 0 -0.00340586195912 +Gc1_58 0 n2 ns58 0 0.00164940806802 +Gc1_59 0 n2 ns59 0 -0.00191232907834 +Gc1_60 0 n2 ns60 0 0.00157821819163 +Gc1_61 0 n2 ns61 0 -0.00458524055961 +Gc1_62 0 n2 ns62 0 -0.0120613955907 +Gc1_63 0 n2 ns63 0 0.000306584921482 +Gc1_64 0 n2 ns64 0 0.00206794821248 +Gc1_65 0 n2 ns65 0 -0.000923667829854 +Gc1_66 0 n2 ns66 0 5.31048620163e-005 +Gc1_67 0 n2 ns67 0 0.0042967444732 +Gc1_68 0 n2 ns68 0 0.00230542460386 +Gc1_69 0 n2 ns69 0 0.00029536321283 +Gc1_70 0 n2 ns70 0 -7.10723169014e-005 +Gc1_71 0 n2 ns71 0 -0.000676043144843 +Gc1_72 0 n2 ns72 0 0.000170979206349 +Gc1_73 0 n2 ns73 0 0.00290336177765 +Gc1_74 0 n2 ns74 0 -0.00127366907455 +Gc1_75 0 n2 ns75 0 -0.00245621623267 +Gc1_76 0 n2 ns76 0 0.00190429319567 +Gc1_77 0 n2 ns77 0 -0.00113907252403 +Gc1_78 0 n2 ns78 0 -0.0023790798915 +Gc1_79 0 n2 ns79 0 -0.000468605837729 +Gc1_80 0 n2 ns80 0 0.00100622992413 +Gc1_81 0 n2 ns81 0 -0.000925139226445 +Gc1_82 0 n2 ns82 0 4.09210768104e-005 +Gc1_83 0 n2 ns83 0 0.00435719206334 +Gc1_84 0 n2 ns84 0 0.00228685435927 +Gc1_85 0 n2 ns85 0 0.000227604482753 +Gc1_86 0 n2 ns86 0 5.86481304095e-005 +Gc1_87 0 n2 ns87 0 0.00227733146351 +Gc1_88 0 n2 ns88 0 -0.000933652617791 +Gc1_89 0 n2 ns89 0 -0.000645437005372 +Gc1_90 0 n2 ns90 0 0.000395074512398 +Gc1_91 0 n2 ns91 0 -0.00163301014528 +Gc1_92 0 n2 ns92 0 0.00124107006808 +Gc1_93 0 n2 ns93 0 -0.000891432534853 +Gc1_94 0 n2 ns94 0 -0.00279384038611 +Gc1_95 0 n2 ns95 0 -0.000221959118991 +Gc1_96 0 n2 ns96 0 0.00159745450512 +Gd1_1 0 n2 ni1 0 -0.000980904555588 +Gd1_2 0 n2 ni2 0 -0.000368372132936 +Gd1_3 0 n2 ni3 0 -0.000376953763328 +Gd1_4 0 n2 ni4 0 -0.00228470396802 +Gd1_5 0 n2 ni5 0 -0.000816206319449 +Gd1_6 0 n2 ni6 0 -0.000530873752608 +Gc2_1 0 n4 ns1 0 0.000933155863994 +Gc2_2 0 n4 ns2 0 -5.27261468133e-005 +Gc2_3 0 n4 ns3 0 -0.00430487341424 +Gc2_4 0 n4 ns4 0 -0.00231283255151 +Gc2_5 0 n4 ns5 0 -0.000279640272696 +Gc2_6 0 n4 ns6 0 -5.50487036695e-005 +Gc2_7 0 n4 ns7 0 0.000846319704393 +Gc2_8 0 n4 ns8 0 -0.000279963833897 +Gc2_9 0 n4 ns9 0 -0.00381675600556 +Gc2_10 0 n4 ns10 0 0.00171817339002 +Gc2_11 0 n4 ns11 0 0.0025891285961 +Gc2_12 0 n4 ns12 0 -0.00197454642679 +Gc2_13 0 n4 ns13 0 -0.000125344849531 +Gc2_14 0 n4 ns14 0 -0.00137923142352 +Gc2_15 0 n4 ns15 0 -0.000334272987697 +Gc2_16 0 n4 ns16 0 0.00143205344258 +Gc2_17 0 n4 ns17 0 0.00104711673612 +Gc2_18 0 n4 ns18 0 0.000182772485596 +Gc2_19 0 n4 ns19 0 0.0087537407976 +Gc2_20 0 n4 ns20 0 0.00451756480182 +Gc2_21 0 n4 ns21 0 0.000489551212524 +Gc2_22 0 n4 ns22 0 -0.00029542390593 +Gc2_23 0 n4 ns23 0 0.000447224930357 +Gc2_24 0 n4 ns24 0 -0.000436438814733 +Gc2_25 0 n4 ns25 0 0.00356560178303 +Gc2_26 0 n4 ns26 0 -0.00140911748382 +Gc2_27 0 n4 ns27 0 0.00345922795788 +Gc2_28 0 n4 ns28 0 -0.0027230349477 +Gc2_29 0 n4 ns29 0 0.00607224144737 +Gc2_30 0 n4 ns30 0 0.040823987916 +Gc2_31 0 n4 ns31 0 0.00231314892418 +Gc2_32 0 n4 ns32 0 -0.00368348467946 +Gc2_33 0 n4 ns33 0 0.000931442458762 +Gc2_34 0 n4 ns34 0 -5.14597461851e-005 +Gc2_35 0 n4 ns35 0 -0.00448322321018 +Gc2_36 0 n4 ns36 0 -0.0021535980622 +Gc2_37 0 n4 ns37 0 -0.000229464656384 +Gc2_38 0 n4 ns38 0 -0.000101167658208 +Gc2_39 0 n4 ns39 0 -0.00176939552109 +Gc2_40 0 n4 ns40 0 0.000684586945313 +Gc2_41 0 n4 ns41 0 -0.000586302710098 +Gc2_42 0 n4 ns42 0 0.000283791083604 +Gc2_43 0 n4 ns43 0 0.00195050923508 +Gc2_44 0 n4 ns44 0 -0.00152954516796 +Gc2_45 0 n4 ns45 0 -0.000624899146909 +Gc2_46 0 n4 ns46 0 -0.00121646483707 +Gc2_47 0 n4 ns47 0 -0.000481331092166 +Gc2_48 0 n4 ns48 0 0.00105574995907 +Gc2_49 0 n4 ns49 0 -0.000933003942935 +Gc2_50 0 n4 ns50 0 5.205952926e-005 +Gc2_51 0 n4 ns51 0 0.00431119170019 +Gc2_52 0 n4 ns52 0 0.0023011640818 +Gc2_53 0 n4 ns53 0 0.000293969530478 +Gc2_54 0 n4 ns54 0 -4.77388833228e-005 +Gc2_55 0 n4 ns55 0 -0.000610983561098 +Gc2_56 0 n4 ns56 0 0.000125992998948 +Gc2_57 0 n4 ns57 0 0.00325597401939 +Gc2_58 0 n4 ns58 0 -0.00140154251692 +Gc2_59 0 n4 ns59 0 -0.00262811115619 +Gc2_60 0 n4 ns60 0 0.00203751798729 +Gc2_61 0 n4 ns61 0 -0.00310933650452 +Gc2_62 0 n4 ns62 0 -0.00280526305823 +Gc2_63 0 n4 ns63 0 -0.000366784080115 +Gc2_64 0 n4 ns64 0 0.000228583313727 +Gc2_65 0 n4 ns65 0 -0.000977536665211 +Gc2_66 0 n4 ns66 0 -0.000180270069241 +Gc2_67 0 n4 ns67 0 -0.00874624557777 +Gc2_68 0 n4 ns68 0 -0.00450968621257 +Gc2_69 0 n4 ns69 0 -0.000501913564946 +Gc2_70 0 n4 ns70 0 -0.000126335069745 +Gc2_71 0 n4 ns71 0 -0.000411375348012 +Gc2_72 0 n4 ns72 0 0.000193394829778 +Gc2_73 0 n4 ns73 0 -0.00247047835417 +Gc2_74 0 n4 ns74 0 0.00131707677207 +Gc2_75 0 n4 ns75 0 -0.0032571321662 +Gc2_76 0 n4 ns76 0 0.0026753881212 +Gc2_77 0 n4 ns77 0 -0.00782526687418 +Gc2_78 0 n4 ns78 0 -0.0134505585846 +Gc2_79 0 n4 ns79 0 0.000369070670449 +Gc2_80 0 n4 ns80 0 0.00095580280173 +Gc2_81 0 n4 ns81 0 -0.000928409571913 +Gc2_82 0 n4 ns82 0 5.26179623723e-005 +Gc2_83 0 n4 ns83 0 0.00447209156629 +Gc2_84 0 n4 ns84 0 0.00214999298502 +Gc2_85 0 n4 ns85 0 0.000244921873265 +Gc2_86 0 n4 ns86 0 1.04404629539e-006 +Gc2_87 0 n4 ns87 0 0.0014425456 +Gc2_88 0 n4 ns88 0 -0.000642163983913 +Gc2_89 0 n4 ns89 0 0.000405902266418 +Gc2_90 0 n4 ns90 0 -0.000136017649187 +Gc2_91 0 n4 ns91 0 -0.00218689709234 +Gc2_92 0 n4 ns92 0 0.00165201895066 +Gc2_93 0 n4 ns93 0 -0.00175025247855 +Gc2_94 0 n4 ns94 0 -0.00236514367874 +Gc2_95 0 n4 ns95 0 -0.000511289252394 +Gc2_96 0 n4 ns96 0 0.000574035308525 +Gd2_1 0 n4 ni1 0 -0.000370945299115 +Gd2_2 0 n4 ni2 0 0.00226616926263 +Gd2_3 0 n4 ni3 0 -0.000647988252986 +Gd2_4 0 n4 ni4 0 -0.00151463399903 +Gd2_5 0 n4 ni5 0 -0.00369097780703 +Gd2_6 0 n4 ni6 0 -0.00107388976755 +Gc3_1 0 n6 ns1 0 0.000936979624279 +Gc3_2 0 n6 ns2 0 -4.0314209219e-005 +Gc3_3 0 n6 ns3 0 -0.00436085836414 +Gc3_4 0 n6 ns4 0 -0.00229307935147 +Gc3_5 0 n6 ns5 0 -0.000208823093988 +Gc3_6 0 n6 ns6 0 -0.000153537685487 +Gc3_7 0 n6 ns7 0 -0.00278067221904 +Gc3_8 0 n6 ns8 0 0.00100971032583 +Gc3_9 0 n6 ns9 0 0.000988043617788 +Gc3_10 0 n6 ns10 0 -0.00036646538978 +Gc3_11 0 n6 ns11 0 0.0014293141184 +Gc3_12 0 n6 ns12 0 -0.00115924269176 +Gc3_13 0 n6 ns13 0 -0.000101806767769 +Gc3_14 0 n6 ns14 0 -0.00152902705782 +Gc3_15 0 n6 ns15 0 -0.000377523838812 +Gc3_16 0 n6 ns16 0 0.00151681734358 +Gc3_17 0 n6 ns17 0 0.000941360823049 +Gc3_18 0 n6 ns18 0 -5.17129199259e-005 +Gc3_19 0 n6 ns19 0 -0.00448214061861 +Gc3_20 0 n6 ns20 0 -0.00215381851553 +Gc3_21 0 n6 ns21 0 -0.000228878419227 +Gc3_22 0 n6 ns22 0 -0.000103634935597 +Gc3_23 0 n6 ns23 0 -0.00176751410629 +Gc3_24 0 n6 ns24 0 0.000685351351783 +Gc3_25 0 n6 ns25 0 -0.000588725511053 +Gc3_26 0 n6 ns26 0 0.000284207743035 +Gc3_27 0 n6 ns27 0 0.00195009762857 +Gc3_28 0 n6 ns28 0 -0.00153041985501 +Gc3_29 0 n6 ns29 0 -0.000630694139138 +Gc3_30 0 n6 ns30 0 -0.00122175731557 +Gc3_31 0 n6 ns31 0 -0.000480065797268 +Gc3_32 0 n6 ns32 0 0.00105374640841 +Gc3_33 0 n6 ns33 0 0.00102946628645 +Gc3_34 0 n6 ns34 0 0.000170700858074 +Gc3_35 0 n6 ns35 0 0.00878203923141 +Gc3_36 0 n6 ns36 0 0.00450322828415 +Gc3_37 0 n6 ns37 0 0.000422306637399 +Gc3_38 0 n6 ns38 0 -0.000183685240741 +Gc3_39 0 n6 ns39 0 0.00603638025507 +Gc3_40 0 n6 ns40 0 -0.00223809757278 +Gc3_41 0 n6 ns41 0 -6.85807364761e-005 +Gc3_42 0 n6 ns42 0 0.000164132652406 +Gc3_43 0 n6 ns43 0 0.00100957675372 +Gc3_44 0 n6 ns44 0 -0.000866482405666 +Gc3_45 0 n6 ns45 0 0.000870752515813 +Gc3_46 0 n6 ns46 0 0.0355882917161 +Gc3_47 0 n6 ns47 0 0.00269202137612 +Gc3_48 0 n6 ns48 0 -0.00412537351611 +Gc3_49 0 n6 ns49 0 -0.000935804561944 +Gc3_50 0 n6 ns50 0 3.97118108168e-005 +Gc3_51 0 n6 ns51 0 0.00436536367864 +Gc3_52 0 n6 ns52 0 0.00227845944152 +Gc3_53 0 n6 ns53 0 0.000227783997274 +Gc3_54 0 n6 ns54 0 5.66786408971e-005 +Gc3_55 0 n6 ns55 0 0.00198874311233 +Gc3_56 0 n6 ns56 0 -0.000877672577354 +Gc3_57 0 n6 ns57 0 -0.000766672357367 +Gc3_58 0 n6 ns58 0 0.000422776062198 +Gc3_59 0 n6 ns59 0 -0.00146862853528 +Gc3_60 0 n6 ns60 0 0.00117898075116 +Gc3_61 0 n6 ns61 0 -0.00168061335223 +Gc3_62 0 n6 ns62 0 -0.00219204997299 +Gc3_63 0 n6 ns63 0 -0.000489605168036 +Gc3_64 0 n6 ns64 0 0.000651653255882 +Gc3_65 0 n6 ns65 0 -0.000940645946317 +Gc3_66 0 n6 ns66 0 5.16389884227e-005 +Gc3_67 0 n6 ns67 0 0.00448682065682 +Gc3_68 0 n6 ns68 0 0.00214150414774 +Gc3_69 0 n6 ns69 0 0.000242660403275 +Gc3_70 0 n6 ns70 0 2.38817285877e-005 +Gc3_71 0 n6 ns71 0 0.00146156021223 +Gc3_72 0 n6 ns72 0 -0.000653886728772 +Gc3_73 0 n6 ns73 0 0.00046778778355 +Gc3_74 0 n6 ns74 0 -0.0001529141286 +Gc3_75 0 n6 ns75 0 -0.0018400786397 +Gc3_76 0 n6 ns76 0 0.00146733058174 +Gc3_77 0 n6 ns77 0 -0.00199187164614 +Gc3_78 0 n6 ns78 0 -0.00274753795249 +Gc3_79 0 n6 ns79 0 -0.00030137632874 +Gc3_80 0 n6 ns80 0 0.000985003727777 +Gc3_81 0 n6 ns81 0 -0.000985813550463 +Gc3_82 0 n6 ns82 0 -0.000167974688572 +Gc3_83 0 n6 ns83 0 -0.00877250942812 +Gc3_84 0 n6 ns84 0 -0.00450125905499 +Gc3_85 0 n6 ns85 0 -0.000419321730554 +Gc3_86 0 n6 ns86 0 -0.000305218222566 +Gc3_87 0 n6 ns87 0 -0.00490641543678 +Gc3_88 0 n6 ns88 0 0.00174873217459 +Gc3_89 0 n6 ns89 0 0.000233623154462 +Gc3_90 0 n6 ns90 0 6.39707381556e-005 +Gc3_91 0 n6 ns91 0 -0.00121304823106 +Gc3_92 0 n6 ns92 0 0.00100384009942 +Gc3_93 0 n6 ns93 0 -0.00402632633125 +Gc3_94 0 n6 ns94 0 -0.00923808156416 +Gc3_95 0 n6 ns95 0 -0.000139431469729 +Gc3_96 0 n6 ns96 0 0.00102307535088 +Gd3_1 0 n6 ni1 0 -0.000382353587576 +Gd3_2 0 n6 ni2 0 -0.000649583076836 +Gd3_3 0 n6 ni3 0 0.000234282377841 +Gd3_4 0 n6 ni4 0 -0.00100215970032 +Gd3_5 0 n6 ni5 0 -0.00103592742117 +Gd3_6 0 n6 ni6 0 -0.0022223441317 +Gc4_1 0 n8 ns1 0 -0.000966687622792 +Gc4_2 0 n8 ns2 0 -0.000171359339129 +Gc4_3 0 n8 ns3 0 -0.00865823763304 +Gc4_4 0 n8 ns4 0 -0.00461778612819 +Gc4_5 0 n8 ns5 0 -0.000480651379888 +Gc4_6 0 n8 ns6 0 -0.000189236264027 +Gc4_7 0 n8 ns7 0 -0.000846088237675 +Gc4_8 0 n8 ns8 0 0.000474958136834 +Gc4_9 0 n8 ns9 0 -0.00341002893127 +Gc4_10 0 n8 ns10 0 0.00164877963498 +Gc4_11 0 n8 ns11 0 -0.00191092809451 +Gc4_12 0 n8 ns12 0 0.00157694746848 +Gc4_13 0 n8 ns13 0 -0.00460440837916 +Gc4_14 0 n8 ns14 0 -0.0120717527594 +Gc4_15 0 n8 ns15 0 0.000307498070164 +Gc4_16 0 n8 ns16 0 0.00206253757411 +Gc4_17 0 n8 ns17 0 -0.000929241138654 +Gc4_18 0 n8 ns18 0 5.19947886738e-005 +Gc4_19 0 n8 ns19 0 0.00431028989918 +Gc4_20 0 n8 ns20 0 0.00230331874332 +Gc4_21 0 n8 ns21 0 0.000292278874707 +Gc4_22 0 n8 ns22 0 -4.6313176744e-005 +Gc4_23 0 n8 ns23 0 -0.000610920983673 +Gc4_24 0 n8 ns24 0 0.000124319448103 +Gc4_25 0 n8 ns25 0 0.00325717254395 +Gc4_26 0 n8 ns26 0 -0.00139931906758 +Gc4_27 0 n8 ns27 0 -0.00262932164397 +Gc4_28 0 n8 ns28 0 0.002037917846 +Gc4_29 0 n8 ns29 0 -0.00311441173463 +Gc4_30 0 n8 ns30 0 -0.00280490339093 +Gc4_31 0 n8 ns31 0 -0.000369560955176 +Gc4_32 0 n8 ns32 0 0.000227661090053 +Gc4_33 0 n8 ns33 0 -0.000929197387086 +Gc4_34 0 n8 ns34 0 3.95924072509e-005 +Gc4_35 0 n8 ns35 0 0.00436491086402 +Gc4_36 0 n8 ns36 0 0.00228065118531 +Gc4_37 0 n8 ns37 0 0.000225470086209 +Gc4_38 0 n8 ns38 0 6.05036934526e-005 +Gc4_39 0 n8 ns39 0 0.00198840801007 +Gc4_40 0 n8 ns40 0 -0.000877964157294 +Gc4_41 0 n8 ns41 0 -0.000766756571173 +Gc4_42 0 n8 ns42 0 0.000422727071576 +Gc4_43 0 n8 ns43 0 -0.00146786720224 +Gc4_44 0 n8 ns44 0 0.00117872552089 +Gc4_45 0 n8 ns45 0 -0.00166732196923 +Gc4_46 0 n8 ns46 0 -0.00218090633949 +Gc4_47 0 n8 ns47 0 -0.000493320957492 +Gc4_48 0 n8 ns48 0 0.000655969302949 +Gc4_49 0 n8 ns49 0 0.00102069062789 +Gc4_50 0 n8 ns50 0 0.000173083254465 +Gc4_51 0 n8 ns51 0 0.00864731509324 +Gc4_52 0 n8 ns52 0 0.00460098297939 +Gc4_53 0 n8 ns53 0 0.000489803538034 +Gc4_54 0 n8 ns54 0 -0.000449672648193 +Gc4_55 0 n8 ns55 0 0.000659669672951 +Gc4_56 0 n8 ns56 0 -0.000530699955648 +Gc4_57 0 n8 ns57 0 0.00289718137442 +Gc4_58 0 n8 ns58 0 -0.0012226420658 +Gc4_59 0 n8 ns59 0 0.0017978651996 +Gc4_60 0 n8 ns60 0 -0.00151133552514 +Gc4_61 0 n8 ns61 0 0.0110501246734 +Gc4_62 0 n8 ns62 0 0.0405226995576 +Gc4_63 0 n8 ns63 0 0.00194011307939 +Gc4_64 0 n8 ns64 0 -0.00174891796416 +Gc4_65 0 n8 ns65 0 0.000926439352554 +Gc4_66 0 n8 ns66 0 -5.29152952214e-005 +Gc4_67 0 n8 ns67 0 -0.00429324783764 +Gc4_68 0 n8 ns68 0 -0.00230553835019 +Gc4_69 0 n8 ns69 0 -0.000277393739468 +Gc4_70 0 n8 ns70 0 2.06545012959e-006 +Gc4_71 0 n8 ns71 0 0.000481013488563 +Gc4_72 0 n8 ns72 0 -0.000215604990028 +Gc4_73 0 n8 ns73 0 -0.00233432142445 +Gc4_74 0 n8 ns74 0 0.00124005196374 +Gc4_75 0 n8 ns75 0 0.00236197188269 +Gc4_76 0 n8 ns76 0 -0.00187383392352 +Gc4_77 0 n8 ns77 0 -0.0041462571025 +Gc4_78 0 n8 ns78 0 -0.00208324612047 +Gc4_79 0 n8 ns79 0 -0.000287249088385 +Gc4_80 0 n8 ns80 0 5.3421743437e-005 +Gc4_81 0 n8 ns81 0 0.000927183917172 +Gc4_82 0 n8 ns82 0 -4.06095693371e-005 +Gc4_83 0 n8 ns83 0 -0.0043500148061 +Gc4_84 0 n8 ns84 0 -0.00228706082294 +Gc4_85 0 n8 ns85 0 -0.000209611820035 +Gc4_86 0 n8 ns86 0 -0.000115278394854 +Gc4_87 0 n8 ns87 0 -0.00161220451443 +Gc4_88 0 n8 ns88 0 0.000675191949338 +Gc4_89 0 n8 ns89 0 0.000578646732702 +Gc4_90 0 n8 ns90 0 -0.000238270314588 +Gc4_91 0 n8 ns91 0 0.00154988882217 +Gc4_92 0 n8 ns92 0 -0.00120871314432 +Gc4_93 0 n8 ns93 0 -0.00456013738583 +Gc4_94 0 n8 ns94 0 -0.00255711426176 +Gc4_95 0 n8 ns95 0 -0.000271796804055 +Gc4_96 0 n8 ns96 0 6.59853957376e-005 +Gd4_1 0 n8 ni1 0 -0.00229364453933 +Gd4_2 0 n8 ni2 0 -0.0015200752258 +Gd4_3 0 n8 ni3 0 -0.0010001005462 +Gd4_4 0 n8 ni4 0 0.00352995610974 +Gd4_5 0 n8 ni5 0 -0.00183303841966 +Gd4_6 0 n8 ni6 0 -0.002010972636 +Gc5_1 0 n10 ns1 0 -0.00092979322676 +Gc5_2 0 n10 ns2 0 5.32578475971e-005 +Gc5_3 0 n10 ns3 0 0.0042981724035 +Gc5_4 0 n10 ns4 0 0.00230488917556 +Gc5_5 0 n10 ns5 0 0.000293491336004 +Gc5_6 0 n10 ns6 0 -7.05797744952e-005 +Gc5_7 0 n10 ns7 0 -0.000675910465236 +Gc5_8 0 n10 ns8 0 0.000168753957702 +Gc5_9 0 n10 ns9 0 0.00290457319774 +Gc5_10 0 n10 ns10 0 -0.00127050760829 +Gc5_11 0 n10 ns11 0 -0.00245688591483 +Gc5_12 0 n10 ns12 0 0.00190449629632 +Gc5_13 0 n10 ns13 0 -0.00116959757746 +Gc5_14 0 n10 ns14 0 -0.0023849639714 +Gc5_15 0 n10 ns15 0 -0.000471573326004 +Gc5_16 0 n10 ns16 0 0.000996846114378 +Gc5_17 0 n10 ns17 0 -0.000976500916098 +Gc5_18 0 n10 ns18 0 -0.000180344082445 +Gc5_19 0 n10 ns19 0 -0.00874699727718 +Gc5_20 0 n10 ns20 0 -0.00450925839798 +Gc5_21 0 n10 ns21 0 -0.000498091001399 +Gc5_22 0 n10 ns22 0 -0.000135175552101 +Gc5_23 0 n10 ns23 0 -0.000412294937417 +Gc5_24 0 n10 ns24 0 0.000194155593072 +Gc5_25 0 n10 ns25 0 -0.00247059307703 +Gc5_26 0 n10 ns26 0 0.00131656009479 +Gc5_27 0 n10 ns27 0 -0.00325767529644 +Gc5_28 0 n10 ns28 0 0.00267278287772 +Gc5_29 0 n10 ns29 0 -0.00780880154338 +Gc5_30 0 n10 ns30 0 -0.0134532094816 +Gc5_31 0 n10 ns31 0 0.000371347815896 +Gc5_32 0 n10 ns32 0 0.00096169435705 +Gc5_33 0 n10 ns33 0 -0.000932471717425 +Gc5_34 0 n10 ns34 0 5.14470686747e-005 +Gc5_35 0 n10 ns35 0 0.00448664276363 +Gc5_36 0 n10 ns36 0 0.00214378016799 +Gc5_37 0 n10 ns37 0 0.000239226284594 +Gc5_38 0 n10 ns38 0 2.90746585707e-005 +Gc5_39 0 n10 ns39 0 0.00146021497012 +Gc5_40 0 n10 ns40 0 -0.000655745714623 +Gc5_41 0 n10 ns41 0 0.000469982953772 +Gc5_42 0 n10 ns42 0 -0.000151293602361 +Gc5_43 0 n10 ns43 0 -0.00183978901508 +Gc5_44 0 n10 ns44 0 0.00146760277243 +Gc5_45 0 n10 ns45 0 -0.0020018633106 +Gc5_46 0 n10 ns46 0 -0.00273692148303 +Gc5_47 0 n10 ns47 0 -0.000309099063238 +Gc5_48 0 n10 ns48 0 0.00098040812757 +Gc5_49 0 n10 ns49 0 0.000930955713141 +Gc5_50 0 n10 ns50 0 -5.29739916551e-005 +Gc5_51 0 n10 ns51 0 -0.00429540975223 +Gc5_52 0 n10 ns52 0 -0.00230307787302 +Gc5_53 0 n10 ns53 0 -0.000277644000086 +Gc5_54 0 n10 ns54 0 4.78266028379e-006 +Gc5_55 0 n10 ns55 0 0.000479984492905 +Gc5_56 0 n10 ns56 0 -0.000214533007427 +Gc5_57 0 n10 ns57 0 -0.00233378896371 +Gc5_58 0 n10 ns58 0 0.00123745325034 +Gc5_59 0 n10 ns59 0 0.00236318620432 +Gc5_60 0 n10 ns60 0 -0.00187340136103 +Gc5_61 0 n10 ns61 0 -0.00412847456991 +Gc5_62 0 n10 ns62 0 -0.00207662230736 +Gc5_63 0 n10 ns63 0 -0.000283372941702 +Gc5_64 0 n10 ns64 0 5.75355690233e-005 +Gc5_65 0 n10 ns65 0 0.0010767272056 +Gc5_66 0 n10 ns66 0 0.000185025287289 +Gc5_67 0 n10 ns67 0 0.00872941407803 +Gc5_68 0 n10 ns68 0 0.00449616802684 +Gc5_69 0 n10 ns69 0 0.000519562515004 +Gc5_70 0 n10 ns70 0 -0.000598270902977 +Gc5_71 0 n10 ns71 0 0.000420839476763 +Gc5_72 0 n10 ns72 0 -0.000356138205062 +Gc5_73 0 n10 ns73 0 0.0019153022269 +Gc5_74 0 n10 ns74 0 -0.000770400978559 +Gc5_75 0 n10 ns75 0 0.00287530805098 +Gc5_76 0 n10 ns76 0 -0.00244612019389 +Gc5_77 0 n10 ns77 0 0.0113099331761 +Gc5_78 0 n10 ns78 0 0.0416720332928 +Gc5_79 0 n10 ns79 0 0.0016992913085 +Gc5_80 0 n10 ns80 0 -0.0023927670198 +Gc5_81 0 n10 ns81 0 0.000930202207247 +Gc5_82 0 n10 ns82 0 -5.26184628584e-005 +Gc5_83 0 n10 ns83 0 -0.00446766284471 +Gc5_84 0 n10 ns84 0 -0.00214894059538 +Gc5_85 0 n10 ns85 0 -0.000226747344006 +Gc5_86 0 n10 ns86 0 -5.18309269076e-005 +Gc5_87 0 n10 ns87 0 -0.00120374529326 +Gc5_88 0 n10 ns88 0 0.00048935754849 +Gc5_89 0 n10 ns89 0 -0.000218051257838 +Gc5_90 0 n10 ns90 0 0.000182262649684 +Gc5_91 0 n10 ns91 0 0.00197183182516 +Gc5_92 0 n10 ns92 0 -0.00152047885709 +Gc5_93 0 n10 ns93 0 -0.00422406332131 +Gc5_94 0 n10 ns94 0 -0.00238635888746 +Gc5_95 0 n10 ns95 0 -0.000235165871613 +Gc5_96 0 n10 ns96 0 0.000272969682753 +Gd5_1 0 n10 ni1 0 -0.000834617438593 +Gd5_2 0 n10 ni2 0 -0.00368185925885 +Gd5_3 0 n10 ni3 0 -0.00104835408552 +Gd5_4 0 n10 ni4 0 -0.00182046417105 +Gd5_5 0 n10 ni5 0 0.00359182837613 +Gd5_6 0 n10 ni6 0 -0.00187676373576 +Gc6_1 0 n12 ns1 0 -0.000933431640823 +Gc6_2 0 n12 ns2 0 4.1020909321e-005 +Gc6_3 0 n12 ns3 0 0.00435905895297 +Gc6_4 0 n12 ns4 0 0.00228625815208 +Gc6_5 0 n12 ns5 0 0.000225267819775 +Gc6_6 0 n12 ns6 0 6.24921115719e-005 +Gc6_7 0 n12 ns7 0 0.00227412573785 +Gc6_8 0 n12 ns8 0 -0.000933477507537 +Gc6_9 0 n12 ns9 0 -0.000642227018829 +Gc6_10 0 n12 ns10 0 0.000393738748073 +Gc6_11 0 n12 ns11 0 -0.00163181154954 +Gc6_12 0 n12 ns12 0 0.00124136689918 +Gc6_13 0 n12 ns13 0 -0.000898841138072 +Gc6_14 0 n12 ns14 0 -0.00278325979584 +Gc6_15 0 n12 ns15 0 -0.000227325491551 +Gc6_16 0 n12 ns16 0 0.00159322466586 +Gc6_17 0 n12 ns17 0 -0.000936981601715 +Gc6_18 0 n12 ns18 0 5.25440762587e-005 +Gc6_19 0 n12 ns19 0 0.00447530302783 +Gc6_20 0 n12 ns20 0 0.00214802668134 +Gc6_21 0 n12 ns21 0 0.000241806542086 +Gc6_22 0 n12 ns22 0 3.52681547357e-006 +Gc6_23 0 n12 ns23 0 0.00144165242173 +Gc6_24 0 n12 ns24 0 -0.000643659451673 +Gc6_25 0 n12 ns25 0 0.000408076698054 +Gc6_26 0 n12 ns26 0 -0.000133456263891 +Gc6_27 0 n12 ns27 0 -0.00218715027963 +Gc6_28 0 n12 ns28 0 0.00165183350484 +Gc6_29 0 n12 ns29 0 -0.0017854752125 +Gc6_30 0 n12 ns30 0 -0.0023655758165 +Gc6_31 0 n12 ns31 0 -0.000518094867305 +Gc6_32 0 n12 ns32 0 0.000562456908235 +Gc6_33 0 n12 ns33 0 -0.000982741070487 +Gc6_34 0 n12 ns34 0 -0.00016814655215 +Gc6_35 0 n12 ns35 0 -0.00877351229626 +Gc6_36 0 n12 ns36 0 -0.00450235747473 +Gc6_37 0 n12 ns37 0 -0.000414262049636 +Gc6_38 0 n12 ns38 0 -0.000310914828598 +Gc6_39 0 n12 ns39 0 -0.00490644324003 +Gc6_40 0 n12 ns40 0 0.00175470717738 +Gc6_41 0 n12 ns41 0 0.000229821788378 +Gc6_42 0 n12 ns42 0 5.5310490909e-005 +Gc6_43 0 n12 ns43 0 -0.00120969415175 +Gc6_44 0 n12 ns44 0 0.00100139091037 +Gc6_45 0 n12 ns45 0 -0.00397870510272 +Gc6_46 0 n12 ns46 0 -0.00921990986109 +Gc6_47 0 n12 ns47 0 -0.000139906435962 +Gc6_48 0 n12 ns48 0 0.00103599660715 +Gc6_49 0 n12 ns49 0 0.000933746327782 +Gc6_50 0 n12 ns50 0 -4.06891078517e-005 +Gc6_51 0 n12 ns51 0 -0.00435268672175 +Gc6_52 0 n12 ns52 0 -0.00228413920238 +Gc6_53 0 n12 ns53 0 -0.000210636033055 +Gc6_54 0 n12 ns54 0 -0.000107254823719 +Gc6_55 0 n12 ns55 0 -0.0016156678656 +Gc6_56 0 n12 ns56 0 0.000676403501407 +Gc6_57 0 n12 ns57 0 0.000581094516688 +Gc6_58 0 n12 ns58 0 -0.000243998023993 +Gc6_59 0 n12 ns59 0 0.00155365883667 +Gc6_60 0 n12 ns60 0 -0.00120710473654 +Gc6_61 0 n12 ns61 0 -0.00453279557814 +Gc6_62 0 n12 ns62 0 -0.00253185038969 +Gc6_63 0 n12 ns63 0 -0.000274198745704 +Gc6_64 0 n12 ns64 0 6.96245785928e-005 +Gc6_65 0 n12 ns65 0 0.00093745808208 +Gc6_66 0 n12 ns66 0 -5.25537042934e-005 +Gc6_67 0 n12 ns67 0 -0.00447080746146 +Gc6_68 0 n12 ns68 0 -0.00214584228902 +Gc6_69 0 n12 ns69 0 -0.000226881522872 +Gc6_70 0 n12 ns70 0 -5.1174574433e-005 +Gc6_71 0 n12 ns71 0 -0.00120375913046 +Gc6_72 0 n12 ns72 0 0.000488485516145 +Gc6_73 0 n12 ns73 0 -0.000217645452719 +Gc6_74 0 n12 ns74 0 0.000182333921504 +Gc6_75 0 n12 ns75 0 0.00197243174395 +Gc6_76 0 n12 ns76 0 -0.00151934126481 +Gc6_77 0 n12 ns77 0 -0.00423161493776 +Gc6_78 0 n12 ns78 0 -0.00238994822639 +Gc6_79 0 n12 ns79 0 -0.000232532923439 +Gc6_80 0 n12 ns80 0 0.000270197088317 +Gc6_81 0 n12 ns81 0 0.00106778368894 +Gc6_82 0 n12 ns82 0 0.000173220474675 +Gc6_83 0 n12 ns83 0 0.0087556116262 +Gc6_84 0 n12 ns84 0 0.0044909200152 +Gc6_85 0 n12 ns85 0 0.000430053524989 +Gc6_86 0 n12 ns86 0 -0.000318003156683 +Gc6_87 0 n12 ns87 0 0.00403521387105 +Gc6_88 0 n12 ns88 0 -0.0016691156504 +Gc6_89 0 n12 ns89 0 -0.00011706386462 +Gc6_90 0 n12 ns90 0 0.00019738676701 +Gc6_91 0 n12 ns91 0 0.00122601992421 +Gc6_92 0 n12 ns92 0 -0.000984496606514 +Gc6_93 0 n12 ns93 0 0.00812605027003 +Gc6_94 0 n12 ns94 0 0.0376119181675 +Gc6_95 0 n12 ns95 0 0.00241748394277 +Gc6_96 0 n12 ns96 0 -0.00222630746938 +Gd6_1 0 n12 ni1 0 -0.000540403702045 +Gd6_2 0 n12 ni2 0 -0.00109871820832 +Gd6_3 0 n12 ni3 0 -0.00220022577721 +Gd6_4 0 n12 ni4 0 -0.00199814650961 +Gd6_5 0 n12 ni5 0 -0.00187755219432 +Gd6_6 0 n12 ni6 0 0.00281106920123 +.ends + +.subckt 744839047160 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 1727088210.57 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 7103714.06179 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 953612.929831 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 199734.284714 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 133817.33501 +Ca6 ns6 0 1e-012 +Ca7 ns7 0 1e-012 +Ra6 ns6 0 370326.605866 +Ra7 ns7 0 370326.605866 +Ga6 ns6 0 ns7 0 -1.75541417972e-005 +Ga7 ns7 0 ns6 0 1.75541417972e-005 +Ca8 ns8 0 1e-012 +Ra8 ns8 0 26699.5633485 +Ca9 ns9 0 1e-012 +Ca10 ns10 0 1e-012 +Ra9 ns9 0 28101.9525626 +Ra10 ns10 0 28101.9525626 +Ga9 ns9 0 ns10 0 -0.000165314485689 +Ga10 ns10 0 ns9 0 0.000165314485689 +Ca11 ns11 0 1e-012 +Ca12 ns12 0 1e-012 +Ra11 ns11 0 29205.4590942 +Ra12 ns12 0 29205.4590942 +Ga11 ns11 0 ns12 0 -0.000173239424359 +Ga12 ns12 0 ns11 0 0.000173239424359 +Ca13 ns13 0 1e-012 +Ca14 ns14 0 1e-012 +Ra13 ns13 0 22695.1269696 +Ra14 ns14 0 22695.1269696 +Ga13 ns13 0 ns14 0 -0.000205726769373 +Ga14 ns14 0 ns13 0 0.000205726769373 +Ca15 ns15 0 1e-012 +Ca16 ns16 0 1e-012 +Ra15 ns15 0 212838.187979 +Ra16 ns16 0 212838.187979 +Ga15 ns15 0 ns16 0 -0.000220143302746 +Ga16 ns16 0 ns15 0 0.000220143302746 +Ca17 ns17 0 1e-012 +Ra17 ns17 0 3295.78095608 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 4809.10898737 +Ra19 ns19 0 4809.10898737 +Ga18 ns18 0 ns19 0 -0.000445516707242 +Ga19 ns19 0 ns18 0 0.000445516707242 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 2171.56228344 +Ra21 ns21 0 2171.56228344 +Ga20 ns20 0 ns21 0 -0.000482552456633 +Ga21 ns21 0 ns20 0 0.000482552456633 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 9148.86046844 +Ra23 ns23 0 9148.86046844 +Ga22 ns22 0 ns23 0 -0.000662163304225 +Ga23 ns23 0 ns22 0 0.000662163304225 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 15222.8911842 +Ra25 ns25 0 15222.8911842 +Ga24 ns24 0 ns25 0 -0.000741885788813 +Ga25 ns25 0 ns24 0 0.000741885788813 +Ca26 ns26 0 1e-012 +Ra26 ns26 0 1727088210.57 +Ca27 ns27 0 1e-012 +Ra27 ns27 0 7103714.06179 +Ca28 ns28 0 1e-012 +Ra28 ns28 0 953612.929831 +Ca29 ns29 0 1e-012 +Ra29 ns29 0 199734.284714 +Ca30 ns30 0 1e-012 +Ra30 ns30 0 133817.33501 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 370326.605866 +Ra32 ns32 0 370326.605866 +Ga31 ns31 0 ns32 0 -1.75541417972e-005 +Ga32 ns32 0 ns31 0 1.75541417972e-005 +Ca33 ns33 0 1e-012 +Ra33 ns33 0 26699.5633485 +Ca34 ns34 0 1e-012 +Ca35 ns35 0 1e-012 +Ra34 ns34 0 28101.9525626 +Ra35 ns35 0 28101.9525626 +Ga34 ns34 0 ns35 0 -0.000165314485689 +Ga35 ns35 0 ns34 0 0.000165314485689 +Ca36 ns36 0 1e-012 +Ca37 ns37 0 1e-012 +Ra36 ns36 0 29205.4590942 +Ra37 ns37 0 29205.4590942 +Ga36 ns36 0 ns37 0 -0.000173239424359 +Ga37 ns37 0 ns36 0 0.000173239424359 +Ca38 ns38 0 1e-012 +Ca39 ns39 0 1e-012 +Ra38 ns38 0 22695.1269696 +Ra39 ns39 0 22695.1269696 +Ga38 ns38 0 ns39 0 -0.000205726769373 +Ga39 ns39 0 ns38 0 0.000205726769373 +Ca40 ns40 0 1e-012 +Ca41 ns41 0 1e-012 +Ra40 ns40 0 212838.187979 +Ra41 ns41 0 212838.187979 +Ga40 ns40 0 ns41 0 -0.000220143302746 +Ga41 ns41 0 ns40 0 0.000220143302746 +Ca42 ns42 0 1e-012 +Ra42 ns42 0 3295.78095608 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 4809.10898737 +Ra44 ns44 0 4809.10898737 +Ga43 ns43 0 ns44 0 -0.000445516707242 +Ga44 ns44 0 ns43 0 0.000445516707242 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 2171.56228344 +Ra46 ns46 0 2171.56228344 +Ga45 ns45 0 ns46 0 -0.000482552456633 +Ga46 ns46 0 ns45 0 0.000482552456633 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 9148.86046844 +Ra48 ns48 0 9148.86046844 +Ga47 ns47 0 ns48 0 -0.000662163304225 +Ga48 ns48 0 ns47 0 0.000662163304225 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 15222.8911842 +Ra50 ns50 0 15222.8911842 +Ga49 ns49 0 ns50 0 -0.000741885788813 +Ga50 ns50 0 ns49 0 0.000741885788813 +Ca51 ns51 0 1e-012 +Ra51 ns51 0 1727088210.57 +Ca52 ns52 0 1e-012 +Ra52 ns52 0 7103714.06179 +Ca53 ns53 0 1e-012 +Ra53 ns53 0 953612.929831 +Ca54 ns54 0 1e-012 +Ra54 ns54 0 199734.284714 +Ca55 ns55 0 1e-012 +Ra55 ns55 0 133817.33501 +Ca56 ns56 0 1e-012 +Ca57 ns57 0 1e-012 +Ra56 ns56 0 370326.605866 +Ra57 ns57 0 370326.605866 +Ga56 ns56 0 ns57 0 -1.75541417972e-005 +Ga57 ns57 0 ns56 0 1.75541417972e-005 +Ca58 ns58 0 1e-012 +Ra58 ns58 0 26699.5633485 +Ca59 ns59 0 1e-012 +Ca60 ns60 0 1e-012 +Ra59 ns59 0 28101.9525626 +Ra60 ns60 0 28101.9525626 +Ga59 ns59 0 ns60 0 -0.000165314485689 +Ga60 ns60 0 ns59 0 0.000165314485689 +Ca61 ns61 0 1e-012 +Ca62 ns62 0 1e-012 +Ra61 ns61 0 29205.4590942 +Ra62 ns62 0 29205.4590942 +Ga61 ns61 0 ns62 0 -0.000173239424359 +Ga62 ns62 0 ns61 0 0.000173239424359 +Ca63 ns63 0 1e-012 +Ca64 ns64 0 1e-012 +Ra63 ns63 0 22695.1269696 +Ra64 ns64 0 22695.1269696 +Ga63 ns63 0 ns64 0 -0.000205726769373 +Ga64 ns64 0 ns63 0 0.000205726769373 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 212838.187979 +Ra66 ns66 0 212838.187979 +Ga65 ns65 0 ns66 0 -0.000220143302746 +Ga66 ns66 0 ns65 0 0.000220143302746 +Ca67 ns67 0 1e-012 +Ra67 ns67 0 3295.78095608 +Ca68 ns68 0 1e-012 +Ca69 ns69 0 1e-012 +Ra68 ns68 0 4809.10898737 +Ra69 ns69 0 4809.10898737 +Ga68 ns68 0 ns69 0 -0.000445516707242 +Ga69 ns69 0 ns68 0 0.000445516707242 +Ca70 ns70 0 1e-012 +Ca71 ns71 0 1e-012 +Ra70 ns70 0 2171.56228344 +Ra71 ns71 0 2171.56228344 +Ga70 ns70 0 ns71 0 -0.000482552456633 +Ga71 ns71 0 ns70 0 0.000482552456633 +Ca72 ns72 0 1e-012 +Ca73 ns73 0 1e-012 +Ra72 ns72 0 9148.86046844 +Ra73 ns73 0 9148.86046844 +Ga72 ns72 0 ns73 0 -0.000662163304225 +Ga73 ns73 0 ns72 0 0.000662163304225 +Ca74 ns74 0 1e-012 +Ca75 ns75 0 1e-012 +Ra74 ns74 0 15222.8911842 +Ra75 ns75 0 15222.8911842 +Ga74 ns74 0 ns75 0 -0.000741885788813 +Ga75 ns75 0 ns74 0 0.000741885788813 +Ca76 ns76 0 1e-012 +Ra76 ns76 0 1727088210.57 +Ca77 ns77 0 1e-012 +Ra77 ns77 0 7103714.06179 +Ca78 ns78 0 1e-012 +Ra78 ns78 0 953612.929831 +Ca79 ns79 0 1e-012 +Ra79 ns79 0 199734.284714 +Ca80 ns80 0 1e-012 +Ra80 ns80 0 133817.33501 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 370326.605866 +Ra82 ns82 0 370326.605866 +Ga81 ns81 0 ns82 0 -1.75541417972e-005 +Ga82 ns82 0 ns81 0 1.75541417972e-005 +Ca83 ns83 0 1e-012 +Ra83 ns83 0 26699.5633485 +Ca84 ns84 0 1e-012 +Ca85 ns85 0 1e-012 +Ra84 ns84 0 28101.9525626 +Ra85 ns85 0 28101.9525626 +Ga84 ns84 0 ns85 0 -0.000165314485689 +Ga85 ns85 0 ns84 0 0.000165314485689 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 29205.4590942 +Ra87 ns87 0 29205.4590942 +Ga86 ns86 0 ns87 0 -0.000173239424359 +Ga87 ns87 0 ns86 0 0.000173239424359 +Ca88 ns88 0 1e-012 +Ca89 ns89 0 1e-012 +Ra88 ns88 0 22695.1269696 +Ra89 ns89 0 22695.1269696 +Ga88 ns88 0 ns89 0 -0.000205726769373 +Ga89 ns89 0 ns88 0 0.000205726769373 +Ca90 ns90 0 1e-012 +Ca91 ns91 0 1e-012 +Ra90 ns90 0 212838.187979 +Ra91 ns91 0 212838.187979 +Ga90 ns90 0 ns91 0 -0.000220143302746 +Ga91 ns91 0 ns90 0 0.000220143302746 +Ca92 ns92 0 1e-012 +Ra92 ns92 0 3295.78095608 +Ca93 ns93 0 1e-012 +Ca94 ns94 0 1e-012 +Ra93 ns93 0 4809.10898737 +Ra94 ns94 0 4809.10898737 +Ga93 ns93 0 ns94 0 -0.000445516707242 +Ga94 ns94 0 ns93 0 0.000445516707242 +Ca95 ns95 0 1e-012 +Ca96 ns96 0 1e-012 +Ra95 ns95 0 2171.56228344 +Ra96 ns96 0 2171.56228344 +Ga95 ns95 0 ns96 0 -0.000482552456633 +Ga96 ns96 0 ns95 0 0.000482552456633 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 9148.86046844 +Ra98 ns98 0 9148.86046844 +Ga97 ns97 0 ns98 0 -0.000662163304225 +Ga98 ns98 0 ns97 0 0.000662163304225 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 15222.8911842 +Ra100 ns100 0 15222.8911842 +Ga99 ns99 0 ns100 0 -0.000741885788813 +Ga100 ns100 0 ns99 0 0.000741885788813 +Ca101 ns101 0 1e-012 +Ra101 ns101 0 1727088210.57 +Ca102 ns102 0 1e-012 +Ra102 ns102 0 7103714.06179 +Ca103 ns103 0 1e-012 +Ra103 ns103 0 953612.929831 +Ca104 ns104 0 1e-012 +Ra104 ns104 0 199734.284714 +Ca105 ns105 0 1e-012 +Ra105 ns105 0 133817.33501 +Ca106 ns106 0 1e-012 +Ca107 ns107 0 1e-012 +Ra106 ns106 0 370326.605866 +Ra107 ns107 0 370326.605866 +Ga106 ns106 0 ns107 0 -1.75541417972e-005 +Ga107 ns107 0 ns106 0 1.75541417972e-005 +Ca108 ns108 0 1e-012 +Ra108 ns108 0 26699.5633485 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 28101.9525626 +Ra110 ns110 0 28101.9525626 +Ga109 ns109 0 ns110 0 -0.000165314485689 +Ga110 ns110 0 ns109 0 0.000165314485689 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 29205.4590942 +Ra112 ns112 0 29205.4590942 +Ga111 ns111 0 ns112 0 -0.000173239424359 +Ga112 ns112 0 ns111 0 0.000173239424359 +Ca113 ns113 0 1e-012 +Ca114 ns114 0 1e-012 +Ra113 ns113 0 22695.1269696 +Ra114 ns114 0 22695.1269696 +Ga113 ns113 0 ns114 0 -0.000205726769373 +Ga114 ns114 0 ns113 0 0.000205726769373 +Ca115 ns115 0 1e-012 +Ca116 ns116 0 1e-012 +Ra115 ns115 0 212838.187979 +Ra116 ns116 0 212838.187979 +Ga115 ns115 0 ns116 0 -0.000220143302746 +Ga116 ns116 0 ns115 0 0.000220143302746 +Ca117 ns117 0 1e-012 +Ra117 ns117 0 3295.78095608 +Ca118 ns118 0 1e-012 +Ca119 ns119 0 1e-012 +Ra118 ns118 0 4809.10898737 +Ra119 ns119 0 4809.10898737 +Ga118 ns118 0 ns119 0 -0.000445516707242 +Ga119 ns119 0 ns118 0 0.000445516707242 +Ca120 ns120 0 1e-012 +Ca121 ns121 0 1e-012 +Ra120 ns120 0 2171.56228344 +Ra121 ns121 0 2171.56228344 +Ga120 ns120 0 ns121 0 -0.000482552456633 +Ga121 ns121 0 ns120 0 0.000482552456633 +Ca122 ns122 0 1e-012 +Ca123 ns123 0 1e-012 +Ra122 ns122 0 9148.86046844 +Ra123 ns123 0 9148.86046844 +Ga122 ns122 0 ns123 0 -0.000662163304225 +Ga123 ns123 0 ns122 0 0.000662163304225 +Ca124 ns124 0 1e-012 +Ca125 ns125 0 1e-012 +Ra124 ns124 0 15222.8911842 +Ra125 ns125 0 15222.8911842 +Ga124 ns124 0 ns125 0 -0.000741885788813 +Ga125 ns125 0 ns124 0 0.000741885788813 +Ca126 ns126 0 1e-012 +Ra126 ns126 0 1727088210.57 +Ca127 ns127 0 1e-012 +Ra127 ns127 0 7103714.06179 +Ca128 ns128 0 1e-012 +Ra128 ns128 0 953612.929831 +Ca129 ns129 0 1e-012 +Ra129 ns129 0 199734.284714 +Ca130 ns130 0 1e-012 +Ra130 ns130 0 133817.33501 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 370326.605866 +Ra132 ns132 0 370326.605866 +Ga131 ns131 0 ns132 0 -1.75541417972e-005 +Ga132 ns132 0 ns131 0 1.75541417972e-005 +Ca133 ns133 0 1e-012 +Ra133 ns133 0 26699.5633485 +Ca134 ns134 0 1e-012 +Ca135 ns135 0 1e-012 +Ra134 ns134 0 28101.9525626 +Ra135 ns135 0 28101.9525626 +Ga134 ns134 0 ns135 0 -0.000165314485689 +Ga135 ns135 0 ns134 0 0.000165314485689 +Ca136 ns136 0 1e-012 +Ca137 ns137 0 1e-012 +Ra136 ns136 0 29205.4590942 +Ra137 ns137 0 29205.4590942 +Ga136 ns136 0 ns137 0 -0.000173239424359 +Ga137 ns137 0 ns136 0 0.000173239424359 +Ca138 ns138 0 1e-012 +Ca139 ns139 0 1e-012 +Ra138 ns138 0 22695.1269696 +Ra139 ns139 0 22695.1269696 +Ga138 ns138 0 ns139 0 -0.000205726769373 +Ga139 ns139 0 ns138 0 0.000205726769373 +Ca140 ns140 0 1e-012 +Ca141 ns141 0 1e-012 +Ra140 ns140 0 212838.187979 +Ra141 ns141 0 212838.187979 +Ga140 ns140 0 ns141 0 -0.000220143302746 +Ga141 ns141 0 ns140 0 0.000220143302746 +Ca142 ns142 0 1e-012 +Ra142 ns142 0 3295.78095608 +Ca143 ns143 0 1e-012 +Ca144 ns144 0 1e-012 +Ra143 ns143 0 4809.10898737 +Ra144 ns144 0 4809.10898737 +Ga143 ns143 0 ns144 0 -0.000445516707242 +Ga144 ns144 0 ns143 0 0.000445516707242 +Ca145 ns145 0 1e-012 +Ca146 ns146 0 1e-012 +Ra145 ns145 0 2171.56228344 +Ra146 ns146 0 2171.56228344 +Ga145 ns145 0 ns146 0 -0.000482552456633 +Ga146 ns146 0 ns145 0 0.000482552456633 +Ca147 ns147 0 1e-012 +Ca148 ns148 0 1e-012 +Ra147 ns147 0 9148.86046844 +Ra148 ns148 0 9148.86046844 +Ga147 ns147 0 ns148 0 -0.000662163304225 +Ga148 ns148 0 ns147 0 0.000662163304225 +Ca149 ns149 0 1e-012 +Ca150 ns150 0 1e-012 +Ra149 ns149 0 15222.8911842 +Ra150 ns150 0 15222.8911842 +Ga149 ns149 0 ns150 0 -0.000741885788813 +Ga150 ns150 0 ns149 0 0.000741885788813 + +Gb1_1 ns1 0 ni1 0 5.79009221346e-010 +Gb2_1 ns2 0 ni1 0 1.4077143186e-007 +Gb3_1 ns3 0 ni1 0 1.0486434996e-006 +Gb4_1 ns4 0 ni1 0 5.00665171946e-006 +Gb5_1 ns5 0 ni1 0 7.4728733757e-006 +Gb6_1 ns6 0 ni1 0 1.79695265664e-005 +Gb8_1 ns8 0 ni1 0 3.74537960395e-005 +Gb9_1 ns9 0 ni1 0 0.000172974262175 +Gb11_1 ns11 0 ni1 0 0.000180006876498 +Gb13_1 ns13 0 ni1 0 0.000215163986783 +Gb15_1 ns15 0 ni1 0 0.00022024357838 +Gb17_1 ns17 0 ni1 0 0.000303418222669 +Gb18_1 ns18 0 ni1 0 0.00054256921596 +Gb20_1 ns20 0 ni1 0 0.000922003893669 +Gb22_1 ns22 0 ni1 0 0.000680205977402 +Gb24_1 ns24 0 ni1 0 0.000747702381622 +Gb26_2 ns26 0 ni2 0 5.79009221346e-010 +Gb27_2 ns27 0 ni2 0 1.4077143186e-007 +Gb28_2 ns28 0 ni2 0 1.0486434996e-006 +Gb29_2 ns29 0 ni2 0 5.00665171946e-006 +Gb30_2 ns30 0 ni2 0 7.4728733757e-006 +Gb31_2 ns31 0 ni2 0 1.79695265664e-005 +Gb33_2 ns33 0 ni2 0 3.74537960395e-005 +Gb34_2 ns34 0 ni2 0 0.000172974262175 +Gb36_2 ns36 0 ni2 0 0.000180006876498 +Gb38_2 ns38 0 ni2 0 0.000215163986783 +Gb40_2 ns40 0 ni2 0 0.00022024357838 +Gb42_2 ns42 0 ni2 0 0.000303418222669 +Gb43_2 ns43 0 ni2 0 0.00054256921596 +Gb45_2 ns45 0 ni2 0 0.000922003893669 +Gb47_2 ns47 0 ni2 0 0.000680205977402 +Gb49_2 ns49 0 ni2 0 0.000747702381622 +Gb51_3 ns51 0 ni3 0 5.79009221346e-010 +Gb52_3 ns52 0 ni3 0 1.4077143186e-007 +Gb53_3 ns53 0 ni3 0 1.0486434996e-006 +Gb54_3 ns54 0 ni3 0 5.00665171946e-006 +Gb55_3 ns55 0 ni3 0 7.4728733757e-006 +Gb56_3 ns56 0 ni3 0 1.79695265664e-005 +Gb58_3 ns58 0 ni3 0 3.74537960395e-005 +Gb59_3 ns59 0 ni3 0 0.000172974262175 +Gb61_3 ns61 0 ni3 0 0.000180006876498 +Gb63_3 ns63 0 ni3 0 0.000215163986783 +Gb65_3 ns65 0 ni3 0 0.00022024357838 +Gb67_3 ns67 0 ni3 0 0.000303418222669 +Gb68_3 ns68 0 ni3 0 0.00054256921596 +Gb70_3 ns70 0 ni3 0 0.000922003893669 +Gb72_3 ns72 0 ni3 0 0.000680205977402 +Gb74_3 ns74 0 ni3 0 0.000747702381622 +Gb76_4 ns76 0 ni4 0 5.79009221346e-010 +Gb77_4 ns77 0 ni4 0 1.4077143186e-007 +Gb78_4 ns78 0 ni4 0 1.0486434996e-006 +Gb79_4 ns79 0 ni4 0 5.00665171946e-006 +Gb80_4 ns80 0 ni4 0 7.4728733757e-006 +Gb81_4 ns81 0 ni4 0 1.79695265664e-005 +Gb83_4 ns83 0 ni4 0 3.74537960395e-005 +Gb84_4 ns84 0 ni4 0 0.000172974262175 +Gb86_4 ns86 0 ni4 0 0.000180006876498 +Gb88_4 ns88 0 ni4 0 0.000215163986783 +Gb90_4 ns90 0 ni4 0 0.00022024357838 +Gb92_4 ns92 0 ni4 0 0.000303418222669 +Gb93_4 ns93 0 ni4 0 0.00054256921596 +Gb95_4 ns95 0 ni4 0 0.000922003893669 +Gb97_4 ns97 0 ni4 0 0.000680205977402 +Gb99_4 ns99 0 ni4 0 0.000747702381622 +Gb101_5 ns101 0 ni5 0 5.79009221346e-010 +Gb102_5 ns102 0 ni5 0 1.4077143186e-007 +Gb103_5 ns103 0 ni5 0 1.0486434996e-006 +Gb104_5 ns104 0 ni5 0 5.00665171946e-006 +Gb105_5 ns105 0 ni5 0 7.4728733757e-006 +Gb106_5 ns106 0 ni5 0 1.79695265664e-005 +Gb108_5 ns108 0 ni5 0 3.74537960395e-005 +Gb109_5 ns109 0 ni5 0 0.000172974262175 +Gb111_5 ns111 0 ni5 0 0.000180006876498 +Gb113_5 ns113 0 ni5 0 0.000215163986783 +Gb115_5 ns115 0 ni5 0 0.00022024357838 +Gb117_5 ns117 0 ni5 0 0.000303418222669 +Gb118_5 ns118 0 ni5 0 0.00054256921596 +Gb120_5 ns120 0 ni5 0 0.000922003893669 +Gb122_5 ns122 0 ni5 0 0.000680205977402 +Gb124_5 ns124 0 ni5 0 0.000747702381622 +Gb126_6 ns126 0 ni6 0 5.79009221346e-010 +Gb127_6 ns127 0 ni6 0 1.4077143186e-007 +Gb128_6 ns128 0 ni6 0 1.0486434996e-006 +Gb129_6 ns129 0 ni6 0 5.00665171946e-006 +Gb130_6 ns130 0 ni6 0 7.4728733757e-006 +Gb131_6 ns131 0 ni6 0 1.79695265664e-005 +Gb133_6 ns133 0 ni6 0 3.74537960395e-005 +Gb134_6 ns134 0 ni6 0 0.000172974262175 +Gb136_6 ns136 0 ni6 0 0.000180006876498 +Gb138_6 ns138 0 ni6 0 0.000215163986783 +Gb140_6 ns140 0 ni6 0 0.00022024357838 +Gb142_6 ns142 0 ni6 0 0.000303418222669 +Gb143_6 ns143 0 ni6 0 0.00054256921596 +Gb145_6 ns145 0 ni6 0 0.000922003893669 +Gb147_6 ns147 0 ni6 0 0.000680205977402 +Gb149_6 ns149 0 ni6 0 0.000747702381622 + +Gc1_1 0 n2 ns1 0 0.0066659118032 +Gc1_2 0 n2 ns2 0 4.88892962734e-005 +Gc1_3 0 n2 ns3 0 0.000160705968676 +Gc1_4 0 n2 ns4 0 0.00746581663973 +Gc1_5 0 n2 ns5 0 0.00577540012749 +Gc1_6 0 n2 ns6 0 -1.42235798521e-007 +Gc1_7 0 n2 ns7 0 6.03193824138e-007 +Gc1_8 0 n2 ns8 0 0.000224039170665 +Gc1_9 0 n2 ns9 0 0.000324904269616 +Gc1_10 0 n2 ns10 0 -0.000199218557748 +Gc1_11 0 n2 ns11 0 0.00300012390387 +Gc1_12 0 n2 ns12 0 0.000642079734382 +Gc1_13 0 n2 ns13 0 0.00295472106732 +Gc1_14 0 n2 ns14 0 -0.00156044976171 +Gc1_15 0 n2 ns15 0 2.2676425291e-007 +Gc1_16 0 n2 ns16 0 -3.58862434722e-007 +Gc1_17 0 n2 ns17 0 -0.00169122730978 +Gc1_18 0 n2 ns18 0 -0.000278759495662 +Gc1_19 0 n2 ns19 0 -0.000919979819774 +Gc1_20 0 n2 ns20 0 -0.00660115168365 +Gc1_21 0 n2 ns21 0 0.0216609841831 +Gc1_22 0 n2 ns22 0 0.00345941518347 +Gc1_23 0 n2 ns23 0 -6.77713750969e-005 +Gc1_24 0 n2 ns24 0 -0.00260255041954 +Gc1_25 0 n2 ns25 0 -0.00252743399881 +Gc1_26 0 n2 ns26 0 0.00662449975109 +Gc1_27 0 n2 ns27 0 -1.9046311257e-005 +Gc1_28 0 n2 ns28 0 -4.56398948731e-005 +Gc1_29 0 n2 ns29 0 -0.00297260726345 +Gc1_30 0 n2 ns30 0 -0.00371230002257 +Gc1_31 0 n2 ns31 0 -1.68208945962e-006 +Gc1_32 0 n2 ns32 0 -7.24330580468e-007 +Gc1_33 0 n2 ns33 0 -0.00012415264238 +Gc1_34 0 n2 ns34 0 -0.000572600436522 +Gc1_35 0 n2 ns35 0 0.000408765669654 +Gc1_36 0 n2 ns36 0 -0.0022040104046 +Gc1_37 0 n2 ns37 0 1.20854534168e-005 +Gc1_38 0 n2 ns38 0 0.00246530238787 +Gc1_39 0 n2 ns39 0 -0.000851476832849 +Gc1_40 0 n2 ns40 0 7.65595384725e-008 +Gc1_41 0 n2 ns41 0 -2.70763190082e-007 +Gc1_42 0 n2 ns42 0 -0.000722040915914 +Gc1_43 0 n2 ns43 0 0.000360822386378 +Gc1_44 0 n2 ns44 0 0.000117429753468 +Gc1_45 0 n2 ns45 0 -0.00153435508046 +Gc1_46 0 n2 ns46 0 -0.00201032884727 +Gc1_47 0 n2 ns47 0 -0.000590203151442 +Gc1_48 0 n2 ns48 0 0.00023788281249 +Gc1_49 0 n2 ns49 0 0.000391264735482 +Gc1_50 0 n2 ns50 0 0.000377968814085 +Gc1_51 0 n2 ns51 0 0.00662211900946 +Gc1_52 0 n2 ns52 0 -1.72383553638e-005 +Gc1_53 0 n2 ns53 0 -6.86402082951e-005 +Gc1_54 0 n2 ns54 0 -0.00456096286122 +Gc1_55 0 n2 ns55 0 -0.00206071446175 +Gc1_56 0 n2 ns56 0 -8.72950201509e-007 +Gc1_57 0 n2 ns57 0 8.38987287259e-007 +Gc1_58 0 n2 ns58 0 -0.000133090617688 +Gc1_59 0 n2 ns59 0 0.000338454581417 +Gc1_60 0 n2 ns60 0 -6.52249576622e-005 +Gc1_61 0 n2 ns61 0 -0.00271112415713 +Gc1_62 0 n2 ns62 0 0.000525893727432 +Gc1_63 0 n2 ns63 0 0.00223125584645 +Gc1_64 0 n2 ns64 0 -0.000816727417999 +Gc1_65 0 n2 ns65 0 4.10812003463e-007 +Gc1_66 0 n2 ns66 0 -3.64656999205e-007 +Gc1_67 0 n2 ns67 0 -0.000724765755817 +Gc1_68 0 n2 ns68 0 0.000464291022038 +Gc1_69 0 n2 ns69 0 0.000146084879645 +Gc1_70 0 n2 ns70 0 -0.00185398975843 +Gc1_71 0 n2 ns71 0 -0.00237529392881 +Gc1_72 0 n2 ns72 0 -0.000145762428028 +Gc1_73 0 n2 ns73 0 -6.3077306618e-005 +Gc1_74 0 n2 ns74 0 0.000220057728569 +Gc1_75 0 n2 ns75 0 0.000792407522593 +Gc1_76 0 n2 ns76 0 -0.00666637569468 +Gc1_77 0 n2 ns77 0 -5.67079161581e-005 +Gc1_78 0 n2 ns78 0 -0.000149165983074 +Gc1_79 0 n2 ns79 0 -0.00748061648302 +Gc1_80 0 n2 ns80 0 -0.00575522643967 +Gc1_81 0 n2 ns81 0 -2.02679324809e-006 +Gc1_82 0 n2 ns82 0 9.27877359419e-008 +Gc1_83 0 n2 ns83 0 -0.00025972094755 +Gc1_84 0 n2 ns84 0 -0.000171548008028 +Gc1_85 0 n2 ns85 0 0.000145670370673 +Gc1_86 0 n2 ns86 0 -0.0023292910143 +Gc1_87 0 n2 ns87 0 -0.000431619931465 +Gc1_88 0 n2 ns88 0 -0.00277536033941 +Gc1_89 0 n2 ns89 0 0.00139085721697 +Gc1_90 0 n2 ns90 0 6.63496431926e-007 +Gc1_91 0 n2 ns91 0 -4.65696414043e-007 +Gc1_92 0 n2 ns92 0 -0.00100111600336 +Gc1_93 0 n2 ns93 0 0.000591099122751 +Gc1_94 0 n2 ns94 0 0.000255509438954 +Gc1_95 0 n2 ns95 0 -0.00175962794929 +Gc1_96 0 n2 ns96 0 -0.00531842240424 +Gc1_97 0 n2 ns97 0 -0.000997276340869 +Gc1_98 0 n2 ns98 0 -0.000189487079233 +Gc1_99 0 n2 ns99 0 0.00120674380876 +Gc1_100 0 n2 ns100 0 0.000939215112857 +Gc1_101 0 n2 ns101 0 -0.00662002257736 +Gc1_102 0 n2 ns102 0 1.70619872516e-005 +Gc1_103 0 n2 ns103 0 4.63486512521e-005 +Gc1_104 0 n2 ns104 0 0.00296934248786 +Gc1_105 0 n2 ns105 0 0.00370120474941 +Gc1_106 0 n2 ns106 0 1.20694312108e-006 +Gc1_107 0 n2 ns107 0 9.78611875993e-007 +Gc1_108 0 n2 ns108 0 0.000139115749035 +Gc1_109 0 n2 ns109 0 0.000501842473045 +Gc1_110 0 n2 ns110 0 -0.000314390280876 +Gc1_111 0 n2 ns111 0 0.00173134324735 +Gc1_112 0 n2 ns112 0 -0.000133094082942 +Gc1_113 0 n2 ns113 0 -0.00255041833696 +Gc1_114 0 n2 ns114 0 0.000938938700067 +Gc1_115 0 n2 ns115 0 4.00817243689e-007 +Gc1_116 0 n2 ns116 0 -2.65650909379e-007 +Gc1_117 0 n2 ns117 0 -0.000104505021451 +Gc1_118 0 n2 ns118 0 0.000293081252998 +Gc1_119 0 n2 ns119 0 -7.48813794032e-005 +Gc1_120 0 n2 ns120 0 -0.00205042627785 +Gc1_121 0 n2 ns121 0 -0.00146195683755 +Gc1_122 0 n2 ns122 0 -0.000523736757266 +Gc1_123 0 n2 ns123 0 -0.000138744813225 +Gc1_124 0 n2 ns124 0 0.000164103376857 +Gc1_125 0 n2 ns125 0 0.000243721208285 +Gc1_126 0 n2 ns126 0 -0.00661720274007 +Gc1_127 0 n2 ns127 0 1.49258520569e-005 +Gc1_128 0 n2 ns128 0 6.93450551937e-005 +Gc1_129 0 n2 ns129 0 0.00456022442556 +Gc1_130 0 n2 ns130 0 0.00205021908576 +Gc1_131 0 n2 ns131 0 2.75640726168e-007 +Gc1_132 0 n2 ns132 0 -4.53666717665e-007 +Gc1_133 0 n2 ns133 0 0.000152830407717 +Gc1_134 0 n2 ns134 0 -0.000184095573602 +Gc1_135 0 n2 ns135 0 0.00011204748322 +Gc1_136 0 n2 ns136 0 0.0022417963845 +Gc1_137 0 n2 ns137 0 -0.000528510809073 +Gc1_138 0 n2 ns138 0 -0.00232769489535 +Gc1_139 0 n2 ns139 0 0.000834079413101 +Gc1_140 0 n2 ns140 0 5.42775287556e-007 +Gc1_141 0 n2 ns141 0 -2.83715360886e-007 +Gc1_142 0 n2 ns142 0 -0.000564493140232 +Gc1_143 0 n2 ns143 0 0.000429125164476 +Gc1_144 0 n2 ns144 0 0.000181074199711 +Gc1_145 0 n2 ns145 0 -0.00246260544048 +Gc1_146 0 n2 ns146 0 -0.00271405664751 +Gc1_147 0 n2 ns147 0 -0.000609368423608 +Gc1_148 0 n2 ns148 0 0.000114825840726 +Gc1_149 0 n2 ns149 0 0.000423604210326 +Gc1_150 0 n2 ns150 0 0.000315956763529 +Gd1_1 0 n2 ni1 0 -0.00317281508364 +Gd1_2 0 n2 ni2 0 -0.000651249439225 +Gd1_3 0 n2 ni3 0 -0.00062907155011 +Gd1_4 0 n2 ni4 0 -0.000715216708925 +Gd1_5 0 n2 ni5 0 -0.000900102791563 +Gd1_6 0 n2 ni6 0 -0.00095728325432 +Gc2_1 0 n4 ns1 0 0.00662364063291 +Gc2_2 0 n4 ns2 0 -1.82832670784e-005 +Gc2_3 0 n4 ns3 0 -4.63881915111e-005 +Gc2_4 0 n4 ns4 0 -0.00297200810494 +Gc2_5 0 n4 ns5 0 -0.00371279975474 +Gc2_6 0 n4 ns6 0 -1.4936017182e-006 +Gc2_7 0 n4 ns7 0 -7.08123078839e-007 +Gc2_8 0 n4 ns8 0 -0.000122087313979 +Gc2_9 0 n4 ns9 0 -0.00057366684388 +Gc2_10 0 n4 ns10 0 0.000408275196682 +Gc2_11 0 n4 ns11 0 -0.00220127426083 +Gc2_12 0 n4 ns12 0 1.13996940535e-005 +Gc2_13 0 n4 ns13 0 0.00246370771377 +Gc2_14 0 n4 ns14 0 -0.000851187965945 +Gc2_15 0 n4 ns15 0 8.05996600356e-008 +Gc2_16 0 n4 ns16 0 -2.61077929898e-007 +Gc2_17 0 n4 ns17 0 -0.000722035125237 +Gc2_18 0 n4 ns18 0 0.000349920357368 +Gc2_19 0 n4 ns19 0 0.000120081490099 +Gc2_20 0 n4 ns20 0 -0.0014839639098 +Gc2_21 0 n4 ns21 0 -0.00199999376238 +Gc2_22 0 n4 ns22 0 -0.000587005147764 +Gc2_23 0 n4 ns23 0 0.000243839195512 +Gc2_24 0 n4 ns24 0 0.000384190467942 +Gc2_25 0 n4 ns25 0 0.000383202624385 +Gc2_26 0 n4 ns26 0 0.0066645877876 +Gc2_27 0 n4 ns27 0 4.41666261884e-005 +Gc2_28 0 n4 ns28 0 0.00015637880409 +Gc2_29 0 n4 ns29 0 0.00665689583424 +Gc2_30 0 n4 ns30 0 0.00671843120167 +Gc2_31 0 n4 ns31 0 1.36004698384e-006 +Gc2_32 0 n4 ns32 0 -2.22405553886e-008 +Gc2_33 0 n4 ns33 0 0.000263158207212 +Gc2_34 0 n4 ns34 0 0.00429061537588 +Gc2_35 0 n4 ns35 0 -0.001093741483 +Gc2_36 0 n4 ns36 0 0.00143959548458 +Gc2_37 0 n4 ns37 0 -0.000438543155342 +Gc2_38 0 n4 ns38 0 0.00199283225754 +Gc2_39 0 n4 ns39 0 -0.0004020015378 +Gc2_40 0 n4 ns40 0 2.01374421054e-007 +Gc2_41 0 n4 ns41 0 -2.19826244426e-007 +Gc2_42 0 n4 ns42 0 -0.0017811895525 +Gc2_43 0 n4 ns43 0 -0.000381021376067 +Gc2_44 0 n4 ns44 0 -0.000901528493197 +Gc2_45 0 n4 ns45 0 -0.00335149041699 +Gc2_46 0 n4 ns46 0 0.0260952729778 +Gc2_47 0 n4 ns47 0 0.00379257993303 +Gc2_48 0 n4 ns48 0 -0.00402495603191 +Gc2_49 0 n4 ns49 0 -0.00235885796379 +Gc2_50 0 n4 ns50 0 0.000239962536565 +Gc2_51 0 n4 ns51 0 0.00662057358703 +Gc2_52 0 n4 ns52 0 -1.78360812053e-005 +Gc2_53 0 n4 ns53 0 -6.01185902216e-005 +Gc2_54 0 n4 ns54 0 -0.00361981012512 +Gc2_55 0 n4 ns55 0 -0.00303583204026 +Gc2_56 0 n4 ns56 0 -1.20969048217e-006 +Gc2_57 0 n4 ns57 0 7.40207885022e-007 +Gc2_58 0 n4 ns58 0 -0.000163280502285 +Gc2_59 0 n4 ns59 0 -0.00371671280384 +Gc2_60 0 n4 ns60 0 0.000235287108104 +Gc2_61 0 n4 ns61 0 0.00178197994809 +Gc2_62 0 n4 ns62 0 -0.000421641623236 +Gc2_63 0 n4 ns63 0 0.00181719915259 +Gc2_64 0 n4 ns64 0 -0.000374025698866 +Gc2_65 0 n4 ns65 0 4.27266154799e-007 +Gc2_66 0 n4 ns66 0 -3.13646836709e-007 +Gc2_67 0 n4 ns67 0 -0.00095723452542 +Gc2_68 0 n4 ns68 0 0.000597457548473 +Gc2_69 0 n4 ns69 0 0.000113444662958 +Gc2_70 0 n4 ns70 0 -0.00280027437142 +Gc2_71 0 n4 ns71 0 -0.00280213318028 +Gc2_72 0 n4 ns72 0 -0.000213205752909 +Gc2_73 0 n4 ns73 0 -0.000230410273355 +Gc2_74 0 n4 ns74 0 0.000528690803925 +Gc2_75 0 n4 ns75 0 0.000652601727894 +Gc2_76 0 n4 ns76 0 -0.00662484659514 +Gc2_77 0 n4 ns77 0 1.90635093062e-005 +Gc2_78 0 n4 ns78 0 4.48960034675e-005 +Gc2_79 0 n4 ns79 0 0.00298050114659 +Gc2_80 0 n4 ns80 0 0.00370068869595 +Gc2_81 0 n4 ns81 0 1.36372755202e-006 +Gc2_82 0 n4 ns82 0 7.41090410331e-007 +Gc2_83 0 n4 ns83 0 0.000130908286477 +Gc2_84 0 n4 ns84 0 0.000628833117757 +Gc2_85 0 n4 ns85 0 -0.000309704428003 +Gc2_86 0 n4 ns86 0 0.00163753748416 +Gc2_87 0 n4 ns87 0 2.13997965724e-006 +Gc2_88 0 n4 ns88 0 -0.0022831728869 +Gc2_89 0 n4 ns89 0 0.000746967806111 +Gc2_90 0 n4 ns90 0 3.11528688108e-007 +Gc2_91 0 n4 ns91 0 -3.53807012425e-007 +Gc2_92 0 n4 ns92 0 0.000186668441395 +Gc2_93 0 n4 ns93 0 0.000317994000911 +Gc2_94 0 n4 ns94 0 -0.000221582502697 +Gc2_95 0 n4 ns95 0 -0.00202345474833 +Gc2_96 0 n4 ns96 0 -0.00112427485708 +Gc2_97 0 n4 ns97 0 -0.000727845516215 +Gc2_98 0 n4 ns98 0 0.000478294750809 +Gc2_99 0 n4 ns99 0 0.00018366617709 +Gc2_100 0 n4 ns100 0 -0.00028281316573 +Gc2_101 0 n4 ns101 0 -0.00667098772929 +Gc2_102 0 n4 ns102 0 -5.55752566466e-005 +Gc2_103 0 n4 ns103 0 -0.000141574696172 +Gc2_104 0 n4 ns104 0 -0.00667277044769 +Gc2_105 0 n4 ns105 0 -0.00669007968418 +Gc2_106 0 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-0.00112543499483 +Gd3_5 0 n6 ni5 0 -0.00107837481212 +Gd3_6 0 n6 ni6 0 -0.0024860508614 +Gc4_1 0 n8 ns1 0 -0.00666374073482 +Gc4_2 0 n8 ns2 0 -5.46153031547e-005 +Gc4_3 0 n8 ns3 0 -0.000150858124859 +Gc4_4 0 n8 ns4 0 -0.00747532638873 +Gc4_5 0 n8 ns5 0 -0.00576492857572 +Gc4_6 0 n8 ns6 0 -1.98484367237e-006 +Gc4_7 0 n8 ns7 0 9.36626440675e-010 +Gc4_8 0 n8 ns8 0 -0.000257244119646 +Gc4_9 0 n8 ns9 0 -0.000177038139932 +Gc4_10 0 n8 ns10 0 0.00014687021852 +Gc4_11 0 n8 ns11 0 -0.00232452862228 +Gc4_12 0 n8 ns12 0 -0.000435461322202 +Gc4_13 0 n8 ns13 0 -0.00277403890109 +Gc4_14 0 n8 ns14 0 0.00139228443186 +Gc4_15 0 n8 ns15 0 6.33592879634e-007 +Gc4_16 0 n8 ns16 0 -4.58707856452e-007 +Gc4_17 0 n8 ns17 0 -0.00100388348182 +Gc4_18 0 n8 ns18 0 0.000585220399874 +Gc4_19 0 n8 ns19 0 0.000261956093981 +Gc4_20 0 n8 ns20 0 -0.00172139921226 +Gc4_21 0 n8 ns21 0 -0.00532268502616 +Gc4_22 0 n8 ns22 0 -0.000991782865145 +Gc4_23 0 n8 ns23 0 -0.00018353880302 +Gc4_24 0 n8 ns24 0 0.00120034915653 +Gc4_25 0 n8 ns25 0 0.000946536166681 +Gc4_26 0 n8 ns26 0 -0.00662636356762 +Gc4_27 0 n8 ns27 0 1.84955392796e-005 +Gc4_28 0 n8 ns28 0 4.52280520691e-005 +Gc4_29 0 n8 ns29 0 0.0029787755687 +Gc4_30 0 n8 ns30 0 0.00370386144663 +Gc4_31 0 n8 ns31 0 1.44603955615e-006 +Gc4_32 0 n8 ns32 0 8.01803389997e-007 +Gc4_33 0 n8 ns33 0 0.000132329602178 +Gc4_34 0 n8 ns34 0 0.000629334918173 +Gc4_35 0 n8 ns35 0 -0.000302219686899 +Gc4_36 0 n8 ns36 0 0.00163374517201 +Gc4_37 0 n8 ns37 0 -4.55356624289e-006 +Gc4_38 0 n8 ns38 0 -0.0022831899253 +Gc4_39 0 n8 ns39 0 0.000744404339978 +Gc4_40 0 n8 ns40 0 2.8963129684e-007 +Gc4_41 0 n8 ns41 0 -3.26695940936e-007 +Gc4_42 0 n8 ns42 0 0.00016212879727 +Gc4_43 0 n8 ns43 0 0.000298041520496 +Gc4_44 0 n8 ns44 0 -0.000209302848348 +Gc4_45 0 n8 ns45 0 -0.00197092054134 +Gc4_46 0 n8 ns46 0 -0.00114064391907 +Gc4_47 0 n8 ns47 0 -0.000732503349518 +Gc4_48 0 n8 ns48 0 0.000487988189157 +Gc4_49 0 n8 ns49 0 0.000178657333356 +Gc4_50 0 n8 ns50 0 -0.000282830284895 +Gc4_51 0 n8 ns51 0 -0.00662422244748 +Gc4_52 0 n8 ns52 0 1.68145797181e-005 +Gc4_53 0 n8 ns53 0 6.77600107732e-005 +Gc4_54 0 n8 ns54 0 0.00456790439758 +Gc4_55 0 n8 ns55 0 0.00204658731479 +Gc4_56 0 n8 ns56 0 4.3108178367e-007 +Gc4_57 0 n8 ns57 0 -6.30590990334e-007 +Gc4_58 0 n8 ns58 0 0.000150704636489 +Gc4_59 0 n8 ns59 0 -0.000373027323516 +Gc4_60 0 n8 ns60 0 7.87539242203e-005 +Gc4_61 0 n8 ns61 0 0.00198069870132 +Gc4_62 0 n8 ns62 0 -0.000382165400133 +Gc4_63 0 n8 ns63 0 -0.00207354288958 +Gc4_64 0 n8 ns64 0 0.00070467639792 +Gc4_65 0 n8 ns65 0 5.79736871994e-007 +Gc4_66 0 n8 ns66 0 -1.84169232597e-007 +Gc4_67 0 n8 ns67 0 -0.000295349323577 +Gc4_68 0 n8 ns68 0 0.000404276996918 +Gc4_69 0 n8 ns69 0 -0.000144136192103 +Gc4_70 0 n8 ns70 0 -0.00279211891697 +Gc4_71 0 n8 ns71 0 -0.00149063993846 +Gc4_72 0 n8 ns72 0 -0.000585971766567 +Gc4_73 0 n8 ns73 0 -6.2984248923e-005 +Gc4_74 0 n8 ns74 0 0.000180136425843 +Gc4_75 0 n8 ns75 0 -0.000346079815028 +Gc4_76 0 n8 ns76 0 0.00666609551602 +Gc4_77 0 n8 ns77 0 4.17839064964e-005 +Gc4_78 0 n8 ns78 0 0.000164979406562 +Gc4_79 0 n8 ns79 0 0.00743373925385 +Gc4_80 0 n8 ns80 0 0.00578970312794 +Gc4_81 0 n8 ns81 0 5.30844718717e-007 +Gc4_82 0 n8 ns82 0 -9.79634925671e-008 +Gc4_83 0 n8 ns83 0 0.000199071035268 +Gc4_84 0 n8 ns84 0 0.00025242742171 +Gc4_85 0 n8 ns85 0 -0.000184853092457 +Gc4_86 0 n8 ns86 0 0.00170621524986 +Gc4_87 0 n8 ns87 0 0.000457719398578 +Gc4_88 0 n8 ns88 0 0.002504521761 +Gc4_89 0 n8 ns89 0 -0.00122295982091 +Gc4_90 0 n8 ns90 0 9.22853607768e-007 +Gc4_91 0 n8 ns91 0 -6.36182325222e-009 +Gc4_92 0 n8 ns92 0 -0.00132629698747 +Gc4_93 0 n8 ns93 0 -0.000611213737936 +Gc4_94 0 n8 ns94 0 -0.000637238162652 +Gc4_95 0 n8 ns95 0 0.00280562289243 +Gc4_96 0 n8 ns96 0 0.0231867621302 +Gc4_97 0 n8 ns97 0 0.00136702452474 +Gc4_98 0 n8 ns98 0 0.000407774806421 +Gc4_99 0 n8 ns99 0 -0.000142342518304 +Gc4_100 0 n8 ns100 0 0.000506485292182 +Gc4_101 0 n8 ns101 0 0.00662186803059 +Gc4_102 0 n8 ns102 0 -1.59719450209e-005 +Gc4_103 0 n8 ns103 0 -4.74372401343e-005 +Gc4_104 0 n8 ns104 0 -0.00295744686888 +Gc4_105 0 n8 ns105 0 -0.00371501462171 +Gc4_106 0 n8 ns106 0 -1.85655576222e-006 +Gc4_107 0 n8 ns107 0 -6.05598969858e-007 +Gc4_108 0 n8 ns108 0 -0.000114169948087 +Gc4_109 0 n8 ns109 0 -0.000538502712174 +Gc4_110 0 n8 ns110 0 0.000316386256782 +Gc4_111 0 n8 ns111 0 -0.00132676752417 +Gc4_112 0 n8 ns112 0 2.97052136652e-005 +Gc4_113 0 n8 ns113 0 0.00236670652374 +Gc4_114 0 n8 ns114 0 -0.000844282378745 +Gc4_115 0 n8 ns115 0 3.03058850565e-007 +Gc4_116 0 n8 ns116 0 1.38775883192e-007 +Gc4_117 0 n8 ns117 0 -0.000388695065975 +Gc4_118 0 n8 ns118 0 0.000207499952486 +Gc4_119 0 n8 ns119 0 -0.000286982349376 +Gc4_120 0 n8 ns120 0 -0.00455884633631 +Gc4_121 0 n8 ns121 0 -0.001422907432 +Gc4_122 0 n8 ns122 0 0.000276879715115 +Gc4_123 0 n8 ns123 0 -0.000417886951681 +Gc4_124 0 n8 ns124 0 -0.000779157470682 +Gc4_125 0 n8 ns125 0 -0.000220390256757 +Gc4_126 0 n8 ns126 0 0.00661930282429 +Gc4_127 0 n8 ns127 0 -1.40918255528e-005 +Gc4_128 0 n8 ns128 0 -6.99327698526e-005 +Gc4_129 0 n8 ns129 0 -0.00454786783475 +Gc4_130 0 n8 ns130 0 -0.00205967227338 +Gc4_131 0 n8 ns131 0 -7.1678799463e-007 +Gc4_132 0 n8 ns132 0 8.07225955834e-007 +Gc4_133 0 n8 ns133 0 -0.000130753757637 +Gc4_134 0 n8 ns134 0 0.000312284685669 +Gc4_135 0 n8 ns135 0 -2.74727841939e-005 +Gc4_136 0 n8 ns136 0 -0.00175314735525 +Gc4_137 0 n8 ns137 0 0.000361783811469 +Gc4_138 0 n8 ns138 0 0.0021278765801 +Gc4_139 0 n8 ns139 0 -0.000761973685552 +Gc4_140 0 n8 ns140 0 7.61620656758e-007 +Gc4_141 0 n8 ns141 0 7.03690763529e-008 +Gc4_142 0 n8 ns142 0 -0.000309916552312 +Gc4_143 0 n8 ns143 0 0.000307877970876 +Gc4_144 0 n8 ns144 0 -0.000134311561226 +Gc4_145 0 n8 ns145 0 -0.00448561532794 +Gc4_146 0 n8 ns146 0 -0.00184675921618 +Gc4_147 0 n8 ns147 0 0.000455840035766 +Gc4_148 0 n8 ns148 0 -9.64076422688e-005 +Gc4_149 0 n8 ns149 0 -0.000929020539694 +Gc4_150 0 n8 ns150 0 -0.000129228486873 +Gd4_1 0 n8 ni1 0 -0.000697036935294 +Gd4_2 0 n8 ni2 0 -0.000757202128269 +Gd4_3 0 n8 ni3 0 -0.00111690350531 +Gd4_4 0 n8 ni4 0 -9.91868936269e-006 +Gd4_5 0 n8 ni5 0 -0.00191792011791 +Gd4_6 0 n8 ni6 0 -0.00184651589285 +Gc5_1 0 n10 ns1 0 -0.00662108561433 +Gc5_2 0 n10 ns2 0 1.68771916605e-005 +Gc5_3 0 n10 ns3 0 4.68228538945e-005 +Gc5_4 0 n10 ns4 0 0.002970589643 +Gc5_5 0 n10 ns5 0 0.00370046719284 +Gc5_6 0 n10 ns6 0 1.27546838583e-006 +Gc5_7 0 n10 ns7 0 1.00401294524e-006 +Gc5_8 0 n10 ns8 0 0.000140212977668 +Gc5_9 0 n10 ns9 0 0.00050099117224 +Gc5_10 0 n10 ns10 0 -0.00030982947918 +Gc5_11 0 n10 ns11 0 0.00173004761337 +Gc5_12 0 n10 ns12 0 -0.000138177680322 +Gc5_13 0 n10 ns13 0 -0.00254962079858 +Gc5_14 0 n10 ns14 0 0.000938338411777 +Gc5_15 0 n10 ns15 0 3.98209383253e-007 +Gc5_16 0 n10 ns16 0 -2.36101395692e-007 +Gc5_17 0 n10 ns17 0 -0.000120569505625 +Gc5_18 0 n10 ns18 0 0.000289505206337 +Gc5_19 0 n10 ns19 0 -6.99789445973e-005 +Gc5_20 0 n10 ns20 0 -0.00204927637171 +Gc5_21 0 n10 ns21 0 -0.00147908113949 +Gc5_22 0 n10 ns22 0 -0.000524624810176 +Gc5_23 0 n10 ns23 0 -0.000137834229517 +Gc5_24 0 n10 ns24 0 0.000162894075731 +Gc5_25 0 n10 ns25 0 0.000243666986803 +Gc5_26 0 n10 ns26 0 -0.00666858287676 +Gc5_27 0 n10 ns27 0 -5.63264509545e-005 +Gc5_28 0 n10 ns28 0 -0.000141355449803 +Gc5_29 0 n10 ns29 0 -0.00667493335511 +Gc5_30 0 n10 ns30 0 -0.00668837709422 +Gc5_31 0 n10 ns31 0 -2.2755517352e-006 +Gc5_32 0 n10 ns32 0 -1.79113736697e-007 +Gc5_33 0 n10 ns33 0 -0.00029408761441 +Gc5_34 0 n10 ns34 0 -0.00348587187545 +Gc5_35 0 n10 ns35 0 0.00105284600932 +Gc5_36 0 n10 ns36 0 -0.0012256950746 +Gc5_37 0 n10 ns37 0 0.000465433376632 +Gc5_38 0 n10 ns38 0 -0.00209648344604 +Gc5_39 0 n10 ns39 0 0.000458336940002 +Gc5_40 0 n10 ns40 0 4.19607292919e-007 +Gc5_41 0 n10 ns41 0 -2.99294309195e-007 +Gc5_42 0 n10 ns42 0 -0.000837998376835 +Gc5_43 0 n10 ns43 0 0.000469820086427 +Gc5_44 0 n10 ns44 0 0.000201045692111 +Gc5_45 0 n10 ns45 0 -0.00432288302954 +Gc5_46 0 n10 ns46 0 -0.00954257153108 +Gc5_47 0 n10 ns47 0 -0.00128485259914 +Gc5_48 0 n10 ns48 0 0.00278342939565 +Gc5_49 0 n10 ns49 0 0.0012024531758 +Gc5_50 0 n10 ns50 0 -0.000354025450803 +Gc5_51 0 n10 ns51 0 -0.00662255330683 +Gc5_52 0 n10 ns52 0 1.75236834573e-005 +Gc5_53 0 n10 ns53 0 5.91031337222e-005 +Gc5_54 0 n10 ns54 0 0.00363211477885 +Gc5_55 0 n10 ns55 0 0.00302073773157 +Gc5_56 0 n10 ns56 0 7.22029649637e-007 +Gc5_57 0 n10 ns57 0 -4.71653795076e-007 +Gc5_58 0 n10 ns58 0 0.000181561423283 +Gc5_59 0 n10 ns59 0 0.00318948347933 +Gc5_60 0 n10 ns60 0 -0.000250490242135 +Gc5_61 0 n10 ns61 0 -0.00151943246068 +Gc5_62 0 n10 ns62 0 0.000429856292507 +Gc5_63 0 n10 ns63 0 -0.00190887215632 +Gc5_64 0 n10 ns64 0 0.000415859007324 +Gc5_65 0 n10 ns65 0 6.88199973722e-007 +Gc5_66 0 n10 ns66 0 -2.04986917135e-007 +Gc5_67 0 n10 ns67 0 -0.000367693164052 +Gc5_68 0 n10 ns68 0 0.000397824665381 +Gc5_69 0 n10 ns69 0 4.39353140973e-005 +Gc5_70 0 n10 ns70 0 -0.00284796278142 +Gc5_71 0 n10 ns71 0 -0.00210301545714 +Gc5_72 0 n10 ns72 0 -0.000744801696016 +Gc5_73 0 n10 ns73 0 0.000244298080953 +Gc5_74 0 n10 ns74 0 0.000293414510728 +Gc5_75 0 n10 ns75 0 -0.000415922634472 +Gc5_76 0 n10 ns76 0 0.00662227989789 +Gc5_77 0 n10 ns77 0 -1.73648637246e-005 +Gc5_78 0 n10 ns78 0 -4.60223352863e-005 +Gc5_79 0 n10 ns79 0 -0.00296433369552 +Gc5_80 0 n10 ns80 0 -0.0037067405525 +Gc5_81 0 n10 ns81 0 -1.89430975443e-006 +Gc5_82 0 n10 ns82 0 -6.40216125619e-007 +Gc5_83 0 n10 ns83 0 -0.000119261654603 +Gc5_84 0 n10 ns84 0 -0.000540119974168 +Gc5_85 0 n10 ns85 0 0.000298639820288 +Gc5_86 0 n10 ns86 0 -0.00131595887054 +Gc5_87 0 n10 ns87 0 4.52614220555e-005 +Gc5_88 0 n10 ns88 0 0.00236550487622 +Gc5_89 0 n10 ns89 0 -0.000838581381681 +Gc5_90 0 n10 ns90 0 2.93493177183e-007 +Gc5_91 0 n10 ns91 0 9.1544938021e-008 +Gc5_92 0 n10 ns92 0 -0.000304748141792 +Gc5_93 0 n10 ns93 0 0.000232609177502 +Gc5_94 0 n10 ns94 0 -0.000326937520533 +Gc5_95 0 n10 ns95 0 -0.00460448309659 +Gc5_96 0 n10 ns96 0 -0.00131633617677 +Gc5_97 0 n10 ns97 0 0.000280769078005 +Gc5_98 0 n10 ns98 0 -0.000431685134396 +Gc5_99 0 n10 ns99 0 -0.000778372977585 +Gc5_100 0 n10 ns100 0 -0.000219876306652 +Gc5_101 0 n10 ns101 0 0.00666965950764 +Gc5_102 0 n10 ns102 0 4.4799414709e-005 +Gc5_103 0 n10 ns103 0 0.000154999590668 +Gc5_104 0 n10 ns104 0 0.00661864680258 +Gc5_105 0 n10 ns105 0 0.00673435181778 +Gc5_106 0 n10 ns106 0 2.48182433431e-006 +Gc5_107 0 n10 ns107 0 -9.35744713012e-007 +Gc5_108 0 n10 ns108 0 0.000241137511261 +Gc5_109 0 n10 ns109 0 0.00295632001211 +Gc5_110 0 n10 ns110 0 -0.00103175284636 +Gc5_111 0 n10 ns111 0 0.000950851432644 +Gc5_112 0 n10 ns112 0 -0.00034906883695 +Gc5_113 0 n10 ns113 0 0.00212091925675 +Gc5_114 0 n10 ns114 0 -0.000519058102505 +Gc5_115 0 n10 ns115 0 5.7425862787e-007 +Gc5_116 0 n10 ns116 0 -1.28527588308e-007 +Gc5_117 0 n10 ns117 0 -0.0014485429836 +Gc5_118 0 n10 ns118 0 -0.000673946236129 +Gc5_119 0 n10 ns119 0 -0.000644307992852 +Gc5_120 0 n10 ns120 0 0.00690780827889 +Gc5_121 0 n10 ns121 0 0.0280622333605 +Gc5_122 0 n10 ns122 0 0.00139974828944 +Gc5_123 0 n10 ns123 0 -0.00159153516589 +Gc5_124 0 n10 ns124 0 -0.00016103980794 +Gc5_125 0 n10 ns125 0 0.00100828480162 +Gc5_126 0 n10 ns126 0 0.00661767231325 +Gc5_127 0 n10 ns127 0 -1.45180027751e-005 +Gc5_128 0 n10 ns128 0 -6.12493284486e-005 +Gc5_129 0 n10 ns129 0 -0.00361116163849 +Gc5_130 0 n10 ns130 0 -0.00302942007081 +Gc5_131 0 n10 ns131 0 -9.24568798835e-007 +Gc5_132 0 n10 ns132 0 6.93362504452e-007 +Gc5_133 0 n10 ns133 0 -0.000159568057168 +Gc5_134 0 n10 ns134 0 -0.00247571241274 +Gc5_135 0 n10 ns135 0 0.000283033817285 +Gc5_136 0 n10 ns136 0 0.00121773126872 +Gc5_137 0 n10 ns137 0 -0.000404107831158 +Gc5_138 0 n10 ns138 0 0.00192869615951 +Gc5_139 0 n10 ns139 0 -0.000478286406688 +Gc5_140 0 n10 ns140 0 8.95977824311e-007 +Gc5_141 0 n10 ns141 0 1.11242757047e-008 +Gc5_142 0 n10 ns142 0 -0.000655495835568 +Gc5_143 0 n10 ns143 0 0.000442064535572 +Gc5_144 0 n10 ns144 0 0.000157082893834 +Gc5_145 0 n10 ns145 0 -0.00519093739718 +Gc5_146 0 n10 ns146 0 -0.00274214585295 +Gc5_147 0 n10 ns147 0 0.000726451971401 +Gc5_148 0 n10 ns148 0 -0.0005006071729 +Gc5_149 0 n10 ns149 0 -0.000940312244038 +Gc5_150 0 n10 ns150 0 0.000223540372107 +Gd5_1 0 n10 ni1 0 -0.000903928370463 +Gd5_2 0 n10 ni2 0 -0.00188057998789 +Gd5_3 0 n10 ni3 0 -0.00109577291432 +Gd5_4 0 n10 ni4 0 -0.00192341661108 +Gd5_5 0 n10 ni5 0 0.00185530966166 +Gd5_6 0 n10 ni6 0 -0.00204242481389 +Gc6_1 0 n12 ns1 0 -0.00661873439475 +Gc6_2 0 n12 ns2 0 1.5954848597e-005 +Gc6_3 0 n12 ns3 0 6.90089256692e-005 +Gc6_4 0 n12 ns4 0 0.00456312823294 +Gc6_5 0 n12 ns5 0 0.00204784788559 +Gc6_6 0 n12 ns6 0 3.62669208791e-007 +Gc6_7 0 n12 ns7 0 -4.21684364742e-007 +Gc6_8 0 n12 ns8 0 0.000154652788204 +Gc6_9 0 n12 ns9 0 -0.000184721094243 +Gc6_10 0 n12 ns10 0 0.000117278735985 +Gc6_11 0 n12 ns11 0 0.00224054935634 +Gc6_12 0 n12 ns12 0 -0.000534068929406 +Gc6_13 0 n12 ns13 0 -0.00232766301728 +Gc6_14 0 n12 ns14 0 0.000833594545727 +Gc6_15 0 n12 ns15 0 5.46640337569e-007 +Gc6_16 0 n12 ns16 0 -2.69644631736e-007 +Gc6_17 0 n12 ns17 0 -0.000596799561732 +Gc6_18 0 n12 ns18 0 0.000440534073097 +Gc6_19 0 n12 ns19 0 0.000193833471571 +Gc6_20 0 n12 ns20 0 -0.0024943455863 +Gc6_21 0 n12 ns21 0 -0.00278346578003 +Gc6_22 0 n12 ns22 0 -0.000596485866589 +Gc6_23 0 n12 ns23 0 0.000108649187122 +Gc6_24 0 n12 ns24 0 0.000428906573885 +Gc6_25 0 n12 ns25 0 0.000328674994467 +Gc6_26 0 n12 ns26 0 -0.0066169110405 +Gc6_27 0 n12 ns27 0 1.63022421011e-005 +Gc6_28 0 n12 ns28 0 6.07841105738e-005 +Gc6_29 0 n12 ns29 0 0.00361831569194 +Gc6_30 0 n12 ns30 0 0.00302226830027 +Gc6_31 0 n12 ns31 0 7.95352343605e-007 +Gc6_32 0 n12 ns32 0 -3.99029252887e-007 +Gc6_33 0 n12 ns33 0 0.000182160456944 +Gc6_34 0 n12 ns34 0 0.00306961722488 +Gc6_35 0 n12 ns35 0 -0.000197455150051 +Gc6_36 0 n12 ns36 0 -0.00164965876183 +Gc6_37 0 n12 ns37 0 0.0004418049724 +Gc6_38 0 n12 ns38 0 -0.00191279708613 +Gc6_39 0 n12 ns39 0 0.000379610415869 +Gc6_40 0 n12 ns40 0 5.88478505105e-007 +Gc6_41 0 n12 ns41 0 -3.20415687591e-007 +Gc6_42 0 n12 ns42 0 -0.000411967768851 +Gc6_43 0 n12 ns43 0 0.000367860663855 +Gc6_44 0 n12 ns44 0 0.000160594164706 +Gc6_45 0 n12 ns45 0 -0.00201707867991 +Gc6_46 0 n12 ns46 0 -0.00201141833619 +Gc6_47 0 n12 ns47 0 -0.000572372248007 +Gc6_48 0 n12 ns48 0 0.000528846482789 +Gc6_49 0 n12 ns49 0 -0.000152144041873 +Gc6_50 0 n12 ns50 0 -0.000375163714982 +Gc6_51 0 n12 ns51 0 -0.00666942620869 +Gc6_52 0 n12 ns52 0 -5.48793244888e-005 +Gc6_53 0 n12 ns53 0 -0.00016209050502 +Gc6_54 0 n12 ns54 0 -0.0081653959045 +Gc6_55 0 n12 ns55 0 -0.00512948823524 +Gc6_56 0 n12 ns56 0 -1.56434810861e-006 +Gc6_57 0 n12 ns57 0 1.36757108135e-006 +Gc6_58 0 n12 ns58 0 -0.000299578405548 +Gc6_59 0 n12 ns59 0 -0.00284816514841 +Gc6_60 0 n12 ns60 0 6.35290768707e-005 +Gc6_61 0 n12 ns61 0 -0.00180461496842 +Gc6_62 0 n12 ns62 0 0.00140381673445 +Gc6_63 0 n12 ns63 0 -0.00174774483365 +Gc6_64 0 n12 ns64 0 0.000417333700244 +Gc6_65 0 n12 ns65 0 8.92770799256e-007 +Gc6_66 0 n12 ns66 0 -3.98759504526e-007 +Gc6_67 0 n12 ns67 0 -0.00109175446254 +Gc6_68 0 n12 ns68 0 0.000622773943276 +Gc6_69 0 n12 ns69 0 0.000193218808369 +Gc6_70 0 n12 ns70 0 -0.0065355905176 +Gc6_71 0 n12 ns71 0 -0.00956420701828 +Gc6_72 0 n12 ns72 0 -0.00148876276959 +Gc6_73 0 n12 ns73 0 0.00140786829405 +Gc6_74 0 n12 ns74 0 0.00179649738379 +Gc6_75 0 n12 ns75 0 -0.000312870824048 +Gc6_76 0 n12 ns76 0 0.00661987408839 +Gc6_77 0 n12 ns77 0 -1.62935838581e-005 +Gc6_78 0 n12 ns78 0 -6.83685064114e-005 +Gc6_79 0 n12 ns79 0 -0.00455124027029 +Gc6_80 0 n12 ns80 0 -0.00205669999416 +Gc6_81 0 n12 ns81 0 -9.59063468956e-007 +Gc6_82 0 n12 ns82 0 8.49127019876e-007 +Gc6_83 0 n12 ns83 0 -0.00013051360778 +Gc6_84 0 n12 ns84 0 0.000315628641517 +Gc6_85 0 n12 ns85 0 -1.78567322069e-005 +Gc6_86 0 n12 ns86 0 -0.0017628838947 +Gc6_87 0 n12 ns87 0 0.000355390282645 +Gc6_88 0 n12 ns88 0 0.00212960859765 +Gc6_89 0 n12 ns89 0 -0.000767205555044 +Gc6_90 0 n12 ns90 0 7.57703781122e-007 +Gc6_91 0 n12 ns91 0 1.18668212729e-007 +Gc6_92 0 n12 ns92 0 -0.000345002585181 +Gc6_93 0 n12 ns93 0 0.000284622935915 +Gc6_94 0 n12 ns94 0 -0.000119402414695 +Gc6_95 0 n12 ns95 0 -0.00444128909967 +Gc6_96 0 n12 ns96 0 -0.00187211336282 +Gc6_97 0 n12 ns97 0 0.000446678363487 +Gc6_98 0 n12 ns98 0 -8.27070985704e-005 +Gc6_99 0 n12 ns99 0 -0.00093529458733 +Gc6_100 0 n12 ns100 0 -0.00013765846222 +Gc6_101 0 n12 ns101 0 0.00661836051497 +Gc6_102 0 n12 ns102 0 -1.67020786673e-005 +Gc6_103 0 n12 ns103 0 -5.91462892871e-005 +Gc6_104 0 n12 ns104 0 -0.00361955000269 +Gc6_105 0 n12 ns105 0 -0.00301986711549 +Gc6_106 0 n12 ns106 0 -9.15632546396e-007 +Gc6_107 0 n12 ns107 0 6.22124016754e-007 +Gc6_108 0 n12 ns108 0 -0.000165857523056 +Gc6_109 0 n12 ns109 0 -0.00247966393599 +Gc6_110 0 n12 ns110 0 0.000262853182688 +Gc6_111 0 n12 ns111 0 0.00123278380421 +Gc6_112 0 n12 ns112 0 -0.000387693374123 +Gc6_113 0 n12 ns113 0 0.00192765027681 +Gc6_114 0 n12 ns114 0 -0.000470771715464 +Gc6_115 0 n12 ns115 0 8.67508104747e-007 +Gc6_116 0 n12 ns116 0 -3.98448686978e-008 +Gc6_117 0 n12 ns117 0 -0.000541670110136 +Gc6_118 0 n12 ns118 0 0.000455418099466 +Gc6_119 0 n12 ns119 0 0.000109728717511 +Gc6_120 0 n12 ns120 0 -0.00519536364396 +Gc6_121 0 n12 ns121 0 -0.00256647044965 +Gc6_122 0 n12 ns122 0 0.000706191987741 +Gc6_123 0 n12 ns123 0 -0.000495606462744 +Gc6_124 0 n12 ns124 0 -0.00094366932508 +Gc6_125 0 n12 ns125 0 0.000198092991241 +Gc6_126 0 n12 ns126 0 0.00667168729107 +Gc6_127 0 n12 ns127 0 4.28333645344e-005 +Gc6_128 0 n12 ns128 0 0.000175803237406 +Gc6_129 0 n12 ns129 0 0.00811242871207 +Gc6_130 0 n12 ns130 0 0.00516712524278 +Gc6_131 0 n12 ns131 0 1.31795558977e-006 +Gc6_132 0 n12 ns132 0 -2.09083661753e-006 +Gc6_133 0 n12 ns133 0 0.000261001390569 +Gc6_134 0 n12 ns134 0 0.00243056779336 +Gc6_135 0 n12 ns135 0 -9.05529649761e-005 +Gc6_136 0 n12 ns136 0 0.00140605390282 +Gc6_137 0 n12 ns137 0 -0.00118113706617 +Gc6_138 0 n12 ns138 0 0.001733557964 +Gc6_139 0 n12 ns139 0 -0.000473672644831 +Gc6_140 0 n12 ns140 0 9.80037970217e-007 +Gc6_141 0 n12 ns141 0 9.94110085775e-008 +Gc6_142 0 n12 ns142 0 -0.00209928999501 +Gc6_143 0 n12 ns143 0 -0.000580156447664 +Gc6_144 0 n12 ns144 0 -0.000183878997252 +Gc6_145 0 n12 ns145 0 0.0072149887103 +Gc6_146 0 n12 ns146 0 0.026119851012 +Gc6_147 0 n12 ns147 0 0.00182629432427 +Gc6_148 0 n12 ns148 0 -0.00104957906823 +Gc6_149 0 n12 ns149 0 -0.000291999949068 +Gc6_150 0 n12 ns150 0 0.000988830945367 +Gd6_1 0 n12 ni1 0 -0.000960222529049 +Gd6_2 0 n12 ni2 0 -0.000992038823509 +Gd6_3 0 n12 ni3 0 -0.00256079590029 +Gd6_4 0 n12 ni4 0 -0.00184571190142 +Gd6_5 0 n12 ni5 0 -0.00204389832393 +Gd6_6 0 n12 ni6 0 0.00226704157192 +.ends + +.subckt 744839125095 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 43897276.6858 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 2330673.90051 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 510183.568891 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 243949.260632 +Ca5 ns5 0 1e-012 +Ca6 ns6 0 1e-012 +Ra5 ns5 0 184288.334819 +Ra6 ns6 0 184288.334819 +Ga5 ns5 0 ns6 0 -3.53844187338e-006 +Ga6 ns6 0 ns5 0 3.53844187338e-006 +Ca7 ns7 0 1e-012 +Ra7 ns7 0 15111.4832882 +Ca8 ns8 0 1e-012 +Ca9 ns9 0 1e-012 +Ra8 ns8 0 79358.5346432 +Ra9 ns9 0 79358.5346432 +Ga8 ns8 0 ns9 0 -7.36703001896e-005 +Ga9 ns9 0 ns8 0 7.36703001896e-005 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 78226.38243 +Ra11 ns11 0 78226.38243 +Ga10 ns10 0 ns11 0 -7.58876198947e-005 +Ga11 ns11 0 ns10 0 7.58876198947e-005 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 59079.7796397 +Ra13 ns13 0 59079.7796397 +Ga12 ns12 0 ns13 0 -9.09904798674e-005 +Ga13 ns13 0 ns12 0 9.09904798674e-005 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 220212.324327 +Ra15 ns15 0 220212.324327 +Ga14 ns14 0 ns15 0 -0.000213178618357 +Ga15 ns15 0 ns14 0 0.000213178618357 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 25371.1467683 +Ra17 ns17 0 25371.1467683 +Ga16 ns16 0 ns17 0 -0.00029648887346 +Ga17 ns17 0 ns16 0 0.00029648887346 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 19351.8619948 +Ra19 ns19 0 19351.8619948 +Ga18 ns18 0 ns19 0 -0.000303553791331 +Ga19 ns19 0 ns18 0 0.000303553791331 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 25966.6473295 +Ra21 ns21 0 25966.6473295 +Ga20 ns20 0 ns21 0 -0.000331959768194 +Ga21 ns21 0 ns20 0 0.000331959768194 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 1947.54256361 +Ra23 ns23 0 1947.54256361 +Ga22 ns22 0 ns23 0 -0.000457112733885 +Ga23 ns23 0 ns22 0 0.000457112733885 +Ca24 ns24 0 1e-012 +Ra24 ns24 0 43897276.6858 +Ca25 ns25 0 1e-012 +Ra25 ns25 0 2330673.90051 +Ca26 ns26 0 1e-012 +Ra26 ns26 0 510183.568891 +Ca27 ns27 0 1e-012 +Ra27 ns27 0 243949.260632 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 184288.334819 +Ra29 ns29 0 184288.334819 +Ga28 ns28 0 ns29 0 -3.53844187338e-006 +Ga29 ns29 0 ns28 0 3.53844187338e-006 +Ca30 ns30 0 1e-012 +Ra30 ns30 0 15111.4832882 +Ca31 ns31 0 1e-012 +Ca32 ns32 0 1e-012 +Ra31 ns31 0 79358.5346432 +Ra32 ns32 0 79358.5346432 +Ga31 ns31 0 ns32 0 -7.36703001896e-005 +Ga32 ns32 0 ns31 0 7.36703001896e-005 +Ca33 ns33 0 1e-012 +Ca34 ns34 0 1e-012 +Ra33 ns33 0 78226.38243 +Ra34 ns34 0 78226.38243 +Ga33 ns33 0 ns34 0 -7.58876198947e-005 +Ga34 ns34 0 ns33 0 7.58876198947e-005 +Ca35 ns35 0 1e-012 +Ca36 ns36 0 1e-012 +Ra35 ns35 0 59079.7796397 +Ra36 ns36 0 59079.7796397 +Ga35 ns35 0 ns36 0 -9.09904798674e-005 +Ga36 ns36 0 ns35 0 9.09904798674e-005 +Ca37 ns37 0 1e-012 +Ca38 ns38 0 1e-012 +Ra37 ns37 0 220212.324327 +Ra38 ns38 0 220212.324327 +Ga37 ns37 0 ns38 0 -0.000213178618357 +Ga38 ns38 0 ns37 0 0.000213178618357 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 25371.1467683 +Ra40 ns40 0 25371.1467683 +Ga39 ns39 0 ns40 0 -0.00029648887346 +Ga40 ns40 0 ns39 0 0.00029648887346 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 19351.8619948 +Ra42 ns42 0 19351.8619948 +Ga41 ns41 0 ns42 0 -0.000303553791331 +Ga42 ns42 0 ns41 0 0.000303553791331 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 25966.6473295 +Ra44 ns44 0 25966.6473295 +Ga43 ns43 0 ns44 0 -0.000331959768194 +Ga44 ns44 0 ns43 0 0.000331959768194 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 1947.54256361 +Ra46 ns46 0 1947.54256361 +Ga45 ns45 0 ns46 0 -0.000457112733885 +Ga46 ns46 0 ns45 0 0.000457112733885 +Ca47 ns47 0 1e-012 +Ra47 ns47 0 43897276.6858 +Ca48 ns48 0 1e-012 +Ra48 ns48 0 2330673.90051 +Ca49 ns49 0 1e-012 +Ra49 ns49 0 510183.568891 +Ca50 ns50 0 1e-012 +Ra50 ns50 0 243949.260632 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 184288.334819 +Ra52 ns52 0 184288.334819 +Ga51 ns51 0 ns52 0 -3.53844187338e-006 +Ga52 ns52 0 ns51 0 3.53844187338e-006 +Ca53 ns53 0 1e-012 +Ra53 ns53 0 15111.4832882 +Ca54 ns54 0 1e-012 +Ca55 ns55 0 1e-012 +Ra54 ns54 0 79358.5346432 +Ra55 ns55 0 79358.5346432 +Ga54 ns54 0 ns55 0 -7.36703001896e-005 +Ga55 ns55 0 ns54 0 7.36703001896e-005 +Ca56 ns56 0 1e-012 +Ca57 ns57 0 1e-012 +Ra56 ns56 0 78226.38243 +Ra57 ns57 0 78226.38243 +Ga56 ns56 0 ns57 0 -7.58876198947e-005 +Ga57 ns57 0 ns56 0 7.58876198947e-005 +Ca58 ns58 0 1e-012 +Ca59 ns59 0 1e-012 +Ra58 ns58 0 59079.7796397 +Ra59 ns59 0 59079.7796397 +Ga58 ns58 0 ns59 0 -9.09904798674e-005 +Ga59 ns59 0 ns58 0 9.09904798674e-005 +Ca60 ns60 0 1e-012 +Ca61 ns61 0 1e-012 +Ra60 ns60 0 220212.324327 +Ra61 ns61 0 220212.324327 +Ga60 ns60 0 ns61 0 -0.000213178618357 +Ga61 ns61 0 ns60 0 0.000213178618357 +Ca62 ns62 0 1e-012 +Ca63 ns63 0 1e-012 +Ra62 ns62 0 25371.1467683 +Ra63 ns63 0 25371.1467683 +Ga62 ns62 0 ns63 0 -0.00029648887346 +Ga63 ns63 0 ns62 0 0.00029648887346 +Ca64 ns64 0 1e-012 +Ca65 ns65 0 1e-012 +Ra64 ns64 0 19351.8619948 +Ra65 ns65 0 19351.8619948 +Ga64 ns64 0 ns65 0 -0.000303553791331 +Ga65 ns65 0 ns64 0 0.000303553791331 +Ca66 ns66 0 1e-012 +Ca67 ns67 0 1e-012 +Ra66 ns66 0 25966.6473295 +Ra67 ns67 0 25966.6473295 +Ga66 ns66 0 ns67 0 -0.000331959768194 +Ga67 ns67 0 ns66 0 0.000331959768194 +Ca68 ns68 0 1e-012 +Ca69 ns69 0 1e-012 +Ra68 ns68 0 1947.54256361 +Ra69 ns69 0 1947.54256361 +Ga68 ns68 0 ns69 0 -0.000457112733885 +Ga69 ns69 0 ns68 0 0.000457112733885 +Ca70 ns70 0 1e-012 +Ra70 ns70 0 43897276.6858 +Ca71 ns71 0 1e-012 +Ra71 ns71 0 2330673.90051 +Ca72 ns72 0 1e-012 +Ra72 ns72 0 510183.568891 +Ca73 ns73 0 1e-012 +Ra73 ns73 0 243949.260632 +Ca74 ns74 0 1e-012 +Ca75 ns75 0 1e-012 +Ra74 ns74 0 184288.334819 +Ra75 ns75 0 184288.334819 +Ga74 ns74 0 ns75 0 -3.53844187338e-006 +Ga75 ns75 0 ns74 0 3.53844187338e-006 +Ca76 ns76 0 1e-012 +Ra76 ns76 0 15111.4832882 +Ca77 ns77 0 1e-012 +Ca78 ns78 0 1e-012 +Ra77 ns77 0 79358.5346432 +Ra78 ns78 0 79358.5346432 +Ga77 ns77 0 ns78 0 -7.36703001896e-005 +Ga78 ns78 0 ns77 0 7.36703001896e-005 +Ca79 ns79 0 1e-012 +Ca80 ns80 0 1e-012 +Ra79 ns79 0 78226.38243 +Ra80 ns80 0 78226.38243 +Ga79 ns79 0 ns80 0 -7.58876198947e-005 +Ga80 ns80 0 ns79 0 7.58876198947e-005 +Ca81 ns81 0 1e-012 +Ca82 ns82 0 1e-012 +Ra81 ns81 0 59079.7796397 +Ra82 ns82 0 59079.7796397 +Ga81 ns81 0 ns82 0 -9.09904798674e-005 +Ga82 ns82 0 ns81 0 9.09904798674e-005 +Ca83 ns83 0 1e-012 +Ca84 ns84 0 1e-012 +Ra83 ns83 0 220212.324327 +Ra84 ns84 0 220212.324327 +Ga83 ns83 0 ns84 0 -0.000213178618357 +Ga84 ns84 0 ns83 0 0.000213178618357 +Ca85 ns85 0 1e-012 +Ca86 ns86 0 1e-012 +Ra85 ns85 0 25371.1467683 +Ra86 ns86 0 25371.1467683 +Ga85 ns85 0 ns86 0 -0.00029648887346 +Ga86 ns86 0 ns85 0 0.00029648887346 +Ca87 ns87 0 1e-012 +Ca88 ns88 0 1e-012 +Ra87 ns87 0 19351.8619948 +Ra88 ns88 0 19351.8619948 +Ga87 ns87 0 ns88 0 -0.000303553791331 +Ga88 ns88 0 ns87 0 0.000303553791331 +Ca89 ns89 0 1e-012 +Ca90 ns90 0 1e-012 +Ra89 ns89 0 25966.6473295 +Ra90 ns90 0 25966.6473295 +Ga89 ns89 0 ns90 0 -0.000331959768194 +Ga90 ns90 0 ns89 0 0.000331959768194 +Ca91 ns91 0 1e-012 +Ca92 ns92 0 1e-012 +Ra91 ns91 0 1947.54256361 +Ra92 ns92 0 1947.54256361 +Ga91 ns91 0 ns92 0 -0.000457112733885 +Ga92 ns92 0 ns91 0 0.000457112733885 +Ca93 ns93 0 1e-012 +Ra93 ns93 0 43897276.6858 +Ca94 ns94 0 1e-012 +Ra94 ns94 0 2330673.90051 +Ca95 ns95 0 1e-012 +Ra95 ns95 0 510183.568891 +Ca96 ns96 0 1e-012 +Ra96 ns96 0 243949.260632 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 184288.334819 +Ra98 ns98 0 184288.334819 +Ga97 ns97 0 ns98 0 -3.53844187338e-006 +Ga98 ns98 0 ns97 0 3.53844187338e-006 +Ca99 ns99 0 1e-012 +Ra99 ns99 0 15111.4832882 +Ca100 ns100 0 1e-012 +Ca101 ns101 0 1e-012 +Ra100 ns100 0 79358.5346432 +Ra101 ns101 0 79358.5346432 +Ga100 ns100 0 ns101 0 -7.36703001896e-005 +Ga101 ns101 0 ns100 0 7.36703001896e-005 +Ca102 ns102 0 1e-012 +Ca103 ns103 0 1e-012 +Ra102 ns102 0 78226.38243 +Ra103 ns103 0 78226.38243 +Ga102 ns102 0 ns103 0 -7.58876198947e-005 +Ga103 ns103 0 ns102 0 7.58876198947e-005 +Ca104 ns104 0 1e-012 +Ca105 ns105 0 1e-012 +Ra104 ns104 0 59079.7796397 +Ra105 ns105 0 59079.7796397 +Ga104 ns104 0 ns105 0 -9.09904798674e-005 +Ga105 ns105 0 ns104 0 9.09904798674e-005 +Ca106 ns106 0 1e-012 +Ca107 ns107 0 1e-012 +Ra106 ns106 0 220212.324327 +Ra107 ns107 0 220212.324327 +Ga106 ns106 0 ns107 0 -0.000213178618357 +Ga107 ns107 0 ns106 0 0.000213178618357 +Ca108 ns108 0 1e-012 +Ca109 ns109 0 1e-012 +Ra108 ns108 0 25371.1467683 +Ra109 ns109 0 25371.1467683 +Ga108 ns108 0 ns109 0 -0.00029648887346 +Ga109 ns109 0 ns108 0 0.00029648887346 +Ca110 ns110 0 1e-012 +Ca111 ns111 0 1e-012 +Ra110 ns110 0 19351.8619948 +Ra111 ns111 0 19351.8619948 +Ga110 ns110 0 ns111 0 -0.000303553791331 +Ga111 ns111 0 ns110 0 0.000303553791331 +Ca112 ns112 0 1e-012 +Ca113 ns113 0 1e-012 +Ra112 ns112 0 25966.6473295 +Ra113 ns113 0 25966.6473295 +Ga112 ns112 0 ns113 0 -0.000331959768194 +Ga113 ns113 0 ns112 0 0.000331959768194 +Ca114 ns114 0 1e-012 +Ca115 ns115 0 1e-012 +Ra114 ns114 0 1947.54256361 +Ra115 ns115 0 1947.54256361 +Ga114 ns114 0 ns115 0 -0.000457112733885 +Ga115 ns115 0 ns114 0 0.000457112733885 +Ca116 ns116 0 1e-012 +Ra116 ns116 0 43897276.6858 +Ca117 ns117 0 1e-012 +Ra117 ns117 0 2330673.90051 +Ca118 ns118 0 1e-012 +Ra118 ns118 0 510183.568891 +Ca119 ns119 0 1e-012 +Ra119 ns119 0 243949.260632 +Ca120 ns120 0 1e-012 +Ca121 ns121 0 1e-012 +Ra120 ns120 0 184288.334819 +Ra121 ns121 0 184288.334819 +Ga120 ns120 0 ns121 0 -3.53844187338e-006 +Ga121 ns121 0 ns120 0 3.53844187338e-006 +Ca122 ns122 0 1e-012 +Ra122 ns122 0 15111.4832882 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 79358.5346432 +Ra124 ns124 0 79358.5346432 +Ga123 ns123 0 ns124 0 -7.36703001896e-005 +Ga124 ns124 0 ns123 0 7.36703001896e-005 +Ca125 ns125 0 1e-012 +Ca126 ns126 0 1e-012 +Ra125 ns125 0 78226.38243 +Ra126 ns126 0 78226.38243 +Ga125 ns125 0 ns126 0 -7.58876198947e-005 +Ga126 ns126 0 ns125 0 7.58876198947e-005 +Ca127 ns127 0 1e-012 +Ca128 ns128 0 1e-012 +Ra127 ns127 0 59079.7796397 +Ra128 ns128 0 59079.7796397 +Ga127 ns127 0 ns128 0 -9.09904798674e-005 +Ga128 ns128 0 ns127 0 9.09904798674e-005 +Ca129 ns129 0 1e-012 +Ca130 ns130 0 1e-012 +Ra129 ns129 0 220212.324327 +Ra130 ns130 0 220212.324327 +Ga129 ns129 0 ns130 0 -0.000213178618357 +Ga130 ns130 0 ns129 0 0.000213178618357 +Ca131 ns131 0 1e-012 +Ca132 ns132 0 1e-012 +Ra131 ns131 0 25371.1467683 +Ra132 ns132 0 25371.1467683 +Ga131 ns131 0 ns132 0 -0.00029648887346 +Ga132 ns132 0 ns131 0 0.00029648887346 +Ca133 ns133 0 1e-012 +Ca134 ns134 0 1e-012 +Ra133 ns133 0 19351.8619948 +Ra134 ns134 0 19351.8619948 +Ga133 ns133 0 ns134 0 -0.000303553791331 +Ga134 ns134 0 ns133 0 0.000303553791331 +Ca135 ns135 0 1e-012 +Ca136 ns136 0 1e-012 +Ra135 ns135 0 25966.6473295 +Ra136 ns136 0 25966.6473295 +Ga135 ns135 0 ns136 0 -0.000331959768194 +Ga136 ns136 0 ns135 0 0.000331959768194 +Ca137 ns137 0 1e-012 +Ca138 ns138 0 1e-012 +Ra137 ns137 0 1947.54256361 +Ra138 ns138 0 1947.54256361 +Ga137 ns137 0 ns138 0 -0.000457112733885 +Ga138 ns138 0 ns137 0 0.000457112733885 + +Gb1_1 ns1 0 ni1 0 2.27804564542e-008 +Gb2_1 ns2 0 ni1 0 4.29060453193e-007 +Gb3_1 ns3 0 ni1 0 1.96007880492e-006 +Gb4_1 ns4 0 ni1 0 4.09921307985e-006 +Gb5_1 ns5 0 ni1 0 7.73367458827e-006 +Gb7_1 ns7 0 ni1 0 6.61748407438e-005 +Gb8_1 ns8 0 ni1 0 7.58256624813e-005 +Gb10_1 ns10 0 ni1 0 7.80410093117e-005 +Gb12_1 ns12 0 ni1 0 9.41391438116e-005 +Gb14_1 ns14 0 ni1 0 0.000213275351013 +Gb16_1 ns16 0 ni1 0 0.000301728633576 +Gb18_1 ns18 0 ni1 0 0.000312350471902 +Gb20_1 ns20 0 ni1 0 0.000336427455696 +Gb22_1 ns22 0 ni1 0 0.000920410610912 +Gb24_2 ns24 0 ni2 0 2.27804564542e-008 +Gb25_2 ns25 0 ni2 0 4.29060453193e-007 +Gb26_2 ns26 0 ni2 0 1.96007880492e-006 +Gb27_2 ns27 0 ni2 0 4.09921307985e-006 +Gb28_2 ns28 0 ni2 0 7.73367458827e-006 +Gb30_2 ns30 0 ni2 0 6.61748407438e-005 +Gb31_2 ns31 0 ni2 0 7.58256624813e-005 +Gb33_2 ns33 0 ni2 0 7.80410093117e-005 +Gb35_2 ns35 0 ni2 0 9.41391438116e-005 +Gb37_2 ns37 0 ni2 0 0.000213275351013 +Gb39_2 ns39 0 ni2 0 0.000301728633576 +Gb41_2 ns41 0 ni2 0 0.000312350471902 +Gb43_2 ns43 0 ni2 0 0.000336427455696 +Gb45_2 ns45 0 ni2 0 0.000920410610912 +Gb47_3 ns47 0 ni3 0 2.27804564542e-008 +Gb48_3 ns48 0 ni3 0 4.29060453193e-007 +Gb49_3 ns49 0 ni3 0 1.96007880492e-006 +Gb50_3 ns50 0 ni3 0 4.09921307985e-006 +Gb51_3 ns51 0 ni3 0 7.73367458827e-006 +Gb53_3 ns53 0 ni3 0 6.61748407438e-005 +Gb54_3 ns54 0 ni3 0 7.58256624813e-005 +Gb56_3 ns56 0 ni3 0 7.80410093117e-005 +Gb58_3 ns58 0 ni3 0 9.41391438116e-005 +Gb60_3 ns60 0 ni3 0 0.000213275351013 +Gb62_3 ns62 0 ni3 0 0.000301728633576 +Gb64_3 ns64 0 ni3 0 0.000312350471902 +Gb66_3 ns66 0 ni3 0 0.000336427455696 +Gb68_3 ns68 0 ni3 0 0.000920410610912 +Gb70_4 ns70 0 ni4 0 2.27804564542e-008 +Gb71_4 ns71 0 ni4 0 4.29060453193e-007 +Gb72_4 ns72 0 ni4 0 1.96007880492e-006 +Gb73_4 ns73 0 ni4 0 4.09921307985e-006 +Gb74_4 ns74 0 ni4 0 7.73367458827e-006 +Gb76_4 ns76 0 ni4 0 6.61748407438e-005 +Gb77_4 ns77 0 ni4 0 7.58256624813e-005 +Gb79_4 ns79 0 ni4 0 7.80410093117e-005 +Gb81_4 ns81 0 ni4 0 9.41391438116e-005 +Gb83_4 ns83 0 ni4 0 0.000213275351013 +Gb85_4 ns85 0 ni4 0 0.000301728633576 +Gb87_4 ns87 0 ni4 0 0.000312350471902 +Gb89_4 ns89 0 ni4 0 0.000336427455696 +Gb91_4 ns91 0 ni4 0 0.000920410610912 +Gb93_5 ns93 0 ni5 0 2.27804564542e-008 +Gb94_5 ns94 0 ni5 0 4.29060453193e-007 +Gb95_5 ns95 0 ni5 0 1.96007880492e-006 +Gb96_5 ns96 0 ni5 0 4.09921307985e-006 +Gb97_5 ns97 0 ni5 0 7.73367458827e-006 +Gb99_5 ns99 0 ni5 0 6.61748407438e-005 +Gb100_5 ns100 0 ni5 0 7.58256624813e-005 +Gb102_5 ns102 0 ni5 0 7.80410093117e-005 +Gb104_5 ns104 0 ni5 0 9.41391438116e-005 +Gb106_5 ns106 0 ni5 0 0.000213275351013 +Gb108_5 ns108 0 ni5 0 0.000301728633576 +Gb110_5 ns110 0 ni5 0 0.000312350471902 +Gb112_5 ns112 0 ni5 0 0.000336427455696 +Gb114_5 ns114 0 ni5 0 0.000920410610912 +Gb116_6 ns116 0 ni6 0 2.27804564542e-008 +Gb117_6 ns117 0 ni6 0 4.29060453193e-007 +Gb118_6 ns118 0 ni6 0 1.96007880492e-006 +Gb119_6 ns119 0 ni6 0 4.09921307985e-006 +Gb120_6 ns120 0 ni6 0 7.73367458827e-006 +Gb122_6 ns122 0 ni6 0 6.61748407438e-005 +Gb123_6 ns123 0 ni6 0 7.58256624813e-005 +Gb125_6 ns125 0 ni6 0 7.80410093117e-005 +Gb127_6 ns127 0 ni6 0 9.41391438116e-005 +Gb129_6 ns129 0 ni6 0 0.000213275351013 +Gb131_6 ns131 0 ni6 0 0.000301728633576 +Gb133_6 ns133 0 ni6 0 0.000312350471902 +Gb135_6 ns135 0 ni6 0 0.000336427455696 +Gb137_6 ns137 0 ni6 0 0.000920410610912 + +Gc1_1 0 n2 ns1 0 0.000179454590087 +Gc1_2 0 n2 ns2 0 0.000329060156486 +Gc1_3 0 n2 ns3 0 0.0110149650243 +Gc1_4 0 n2 ns4 0 0.00246233986132 +Gc1_5 0 n2 ns5 0 -0.000222269528581 +Gc1_6 0 n2 ns6 0 0.000242630453777 +Gc1_7 0 n2 ns7 0 0.000253287740058 +Gc1_8 0 n2 ns8 0 0.000335722727286 +Gc1_9 0 n2 ns9 0 -0.00019191071248 +Gc1_10 0 n2 ns10 0 0.00225824195007 +Gc1_11 0 n2 ns11 0 7.62256868294e-005 +Gc1_12 0 n2 ns12 0 0.00231767059837 +Gc1_13 0 n2 ns13 0 -0.000428868998948 +Gc1_14 0 n2 ns14 0 6.66728743289e-007 +Gc1_15 0 n2 ns15 0 -2.9218524526e-007 +Gc1_16 0 n2 ns16 0 -8.79163404508e-005 +Gc1_17 0 n2 ns17 0 9.33218627721e-005 +Gc1_18 0 n2 ns18 0 0.000797658401734 +Gc1_19 0 n2 ns19 0 -0.000541029833978 +Gc1_20 0 n2 ns20 0 0.00148560401777 +Gc1_21 0 n2 ns21 0 -0.0019488721187 +Gc1_22 0 n2 ns22 0 0.0149117729305 +Gc1_23 0 n2 ns23 0 0.037143271846 +Gc1_24 0 n2 ns24 0 6.02257328068e-005 +Gc1_25 0 n2 ns25 0 -0.000161718179478 +Gc1_26 0 n2 ns26 0 -0.00545979351151 +Gc1_27 0 n2 ns27 0 -0.00136543684207 +Gc1_28 0 n2 ns28 0 0.000150950212076 +Gc1_29 0 n2 ns29 0 -0.000159328914399 +Gc1_30 0 n2 ns30 0 -0.000119475217315 +Gc1_31 0 n2 ns31 0 -0.00109337871407 +Gc1_32 0 n2 ns32 0 0.00038568426346 +Gc1_33 0 n2 ns33 0 -0.000585584640401 +Gc1_34 0 n2 ns34 0 -0.000311890218261 +Gc1_35 0 n2 ns35 0 0.00176501309864 +Gc1_36 0 n2 ns36 0 -0.000319172014226 +Gc1_37 0 n2 ns37 0 2.7288789406e-007 +Gc1_38 0 n2 ns38 0 -6.54242798872e-007 +Gc1_39 0 n2 ns39 0 0.000388698160399 +Gc1_40 0 n2 ns40 0 -0.000474800882803 +Gc1_41 0 n2 ns41 0 -0.000142749320295 +Gc1_42 0 n2 ns42 0 0.000261334005145 +Gc1_43 0 n2 ns43 0 -0.0004513158076 +Gc1_44 0 n2 ns44 0 0.00041175737092 +Gc1_45 0 n2 ns45 0 -0.00280015021517 +Gc1_46 0 n2 ns46 0 -0.00213825627789 +Gc1_47 0 n2 ns47 0 5.97796298247e-005 +Gc1_48 0 n2 ns48 0 -0.000185106907747 +Gc1_49 0 n2 ns49 0 -0.00551721846194 +Gc1_50 0 n2 ns50 0 -0.00119441800164 +Gc1_51 0 n2 ns51 0 9.11347205276e-005 +Gc1_52 0 n2 ns52 0 -0.000137267674243 +Gc1_53 0 n2 ns53 0 -0.000142973358227 +Gc1_54 0 n2 ns54 0 0.000640044759602 +Gc1_55 0 n2 ns55 0 1.69096249894e-005 +Gc1_56 0 n2 ns56 0 -0.00238360817248 +Gc1_57 0 n2 ns57 0 0.000139696459717 +Gc1_58 0 n2 ns58 0 0.00187673181275 +Gc1_59 0 n2 ns59 0 -0.000386863553608 +Gc1_60 0 n2 ns60 0 3.80156078105e-007 +Gc1_61 0 n2 ns61 0 -5.79671088877e-007 +Gc1_62 0 n2 ns62 0 0.000325135938204 +Gc1_63 0 n2 ns63 0 -0.00022208536063 +Gc1_64 0 n2 ns64 0 -0.000168046227212 +Gc1_65 0 n2 ns65 0 6.19562643935e-005 +Gc1_66 0 n2 ns66 0 -0.000363564453621 +Gc1_67 0 n2 ns67 0 0.000395271564202 +Gc1_68 0 n2 ns68 0 -0.00263415954724 +Gc1_69 0 n2 ns69 0 -0.00212321883305 +Gc1_70 0 n2 ns70 0 -0.000176243329526 +Gc1_71 0 n2 ns71 0 -0.000333239675992 +Gc1_72 0 n2 ns72 0 -0.0109784995056 +Gc1_73 0 n2 ns73 0 -0.00254469242077 +Gc1_74 0 n2 ns74 0 0.000235342338591 +Gc1_75 0 n2 ns75 0 -0.000287812573616 +Gc1_76 0 n2 ns76 0 -0.000341065178396 +Gc1_77 0 n2 ns77 0 -0.000318055105071 +Gc1_78 0 n2 ns78 0 0.000202953959522 +Gc1_79 0 n2 ns79 0 -0.00205789189828 +Gc1_80 0 n2 ns80 0 -8.67194474553e-005 +Gc1_81 0 n2 ns81 0 -0.00227861961023 +Gc1_82 0 n2 ns82 0 0.000417932251225 +Gc1_83 0 n2 ns83 0 3.09504089732e-007 +Gc1_84 0 n2 ns84 0 -4.17991566975e-007 +Gc1_85 0 n2 ns85 0 -0.000238738913864 +Gc1_86 0 n2 ns86 0 -0.00011662262392 +Gc1_87 0 n2 ns87 0 -5.28336659371e-005 +Gc1_88 0 n2 ns88 0 0.000797242561422 +Gc1_89 0 n2 ns89 0 -0.00140555908314 +Gc1_90 0 n2 ns90 0 0.0016751434733 +Gc1_91 0 n2 ns91 0 -0.0143566443461 +Gc1_92 0 n2 ns92 0 -0.0138059464181 +Gc1_93 0 n2 ns93 0 -6.50427457732e-005 +Gc1_94 0 n2 ns94 0 0.00016247484853 +Gc1_95 0 n2 ns95 0 0.00544384940111 +Gc1_96 0 n2 ns96 0 0.00139966211817 +Gc1_97 0 n2 ns97 0 -0.000153786008745 +Gc1_98 0 n2 ns98 0 0.00018297210938 +Gc1_99 0 n2 ns99 0 3.97458793604e-005 +Gc1_100 0 n2 ns100 0 0.00108082873923 +Gc1_101 0 n2 ns101 0 -0.000357798502859 +Gc1_102 0 n2 ns102 0 0.000449999858345 +Gc1_103 0 n2 ns103 0 0.000302473860758 +Gc1_104 0 n2 ns104 0 -0.00181207068646 +Gc1_105 0 n2 ns105 0 0.000312976979306 +Gc1_106 0 n2 ns106 0 3.01401799483e-007 +Gc1_107 0 n2 ns107 0 -6.37804690437e-007 +Gc1_108 0 n2 ns108 0 -0.000255325568234 +Gc1_109 0 n2 ns109 0 0.000558659408243 +Gc1_110 0 n2 ns110 0 -0.000156149777057 +Gc1_111 0 n2 ns111 0 -0.00064460108021 +Gc1_112 0 n2 ns112 0 0.000525362040515 +Gc1_113 0 n2 ns113 0 -0.000300370827845 +Gc1_114 0 n2 ns114 0 -0.00347633269893 +Gc1_115 0 n2 ns115 0 -0.00231934979242 +Gc1_116 0 n2 ns116 0 -6.527069489e-005 +Gc1_117 0 n2 ns117 0 0.000186031416475 +Gc1_118 0 n2 ns118 0 0.00550228321433 +Gc1_119 0 n2 ns119 0 0.00122683020557 +Gc1_120 0 n2 ns120 0 -9.42907703582e-005 +Gc1_121 0 n2 ns121 0 0.000159006140111 +Gc1_122 0 n2 ns122 0 7.30034401282e-005 +Gc1_123 0 n2 ns123 0 -0.000520390499534 +Gc1_124 0 n2 ns124 0 -1.07949420832e-005 +Gc1_125 0 n2 ns125 0 0.00216984671808 +Gc1_126 0 n2 ns126 0 -0.000119607519214 +Gc1_127 0 n2 ns127 0 -0.00188625260602 +Gc1_128 0 n2 ns128 0 0.00037378445755 +Gc1_129 0 n2 ns129 0 3.46626551667e-007 +Gc1_130 0 n2 ns130 0 -5.65648937277e-007 +Gc1_131 0 n2 ns131 0 -0.000256188201372 +Gc1_132 0 n2 ns132 0 0.000336949784788 +Gc1_133 0 n2 ns133 0 -2.97371432136e-005 +Gc1_134 0 n2 ns134 0 -0.000408939586376 +Gc1_135 0 n2 ns135 0 0.000340181695687 +Gc1_136 0 n2 ns136 0 -0.00019968668795 +Gc1_137 0 n2 ns137 0 -0.00296811750662 +Gc1_138 0 n2 ns138 0 -0.00220686577177 +Gd1_1 0 n2 ni1 0 0.00634481883667 +Gd1_2 0 n2 ni2 0 -0.00106057490949 +Gd1_3 0 n2 ni3 0 -0.000956659490064 +Gd1_4 0 n2 ni4 0 -0.00650203739065 +Gd1_5 0 n2 ni5 0 -0.00120507185862 +Gd1_6 0 n2 ni6 0 -0.000877025213216 +Gc2_1 0 n4 ns1 0 6.28409949405e-005 +Gc2_2 0 n4 ns2 0 -0.00016180140441 +Gc2_3 0 n4 ns3 0 -0.00545986721276 +Gc2_4 0 n4 ns4 0 -0.00136282767747 +Gc2_5 0 n4 ns5 0 0.000150125748675 +Gc2_6 0 n4 ns6 0 -0.000158325873866 +Gc2_7 0 n4 ns7 0 -0.000118765845881 +Gc2_8 0 n4 ns8 0 -0.00109209830986 +Gc2_9 0 n4 ns9 0 0.000385373158716 +Gc2_10 0 n4 ns10 0 -0.000585553666622 +Gc2_11 0 n4 ns11 0 -0.000311732093511 +Gc2_12 0 n4 ns12 0 0.00176369906747 +Gc2_13 0 n4 ns13 0 -0.000318696664372 +Gc2_14 0 n4 ns14 0 2.8228603213e-007 +Gc2_15 0 n4 ns15 0 -6.47548947244e-007 +Gc2_16 0 n4 ns16 0 0.000387207992916 +Gc2_17 0 n4 ns17 0 -0.000476374874566 +Gc2_18 0 n4 ns18 0 -0.000140984881374 +Gc2_19 0 n4 ns19 0 0.000266091954952 +Gc2_20 0 n4 ns20 0 -0.000452896891568 +Gc2_21 0 n4 ns21 0 0.0004097665332 +Gc2_22 0 n4 ns22 0 -0.00278607717654 +Gc2_23 0 n4 ns23 0 -0.00213338786344 +Gc2_24 0 n4 ns24 0 0.000169697184144 +Gc2_25 0 n4 ns25 0 0.000317756091958 +Gc2_26 0 n4 ns26 0 0.0109852317666 +Gc2_27 0 n4 ns27 0 0.00257734099 +Gc2_28 0 n4 ns28 0 -0.000253800555153 +Gc2_29 0 n4 ns29 0 0.00026398180232 +Gc2_30 0 n4 ns30 0 0.000237834252196 +Gc2_31 0 n4 ns31 0 0.00352225480823 +Gc2_32 0 n4 ns32 0 -0.000459867590608 +Gc2_33 0 n4 ns33 0 9.32108426308e-005 +Gc2_34 0 n4 ns34 0 0.000207132789817 +Gc2_35 0 n4 ns35 0 0.00135809843656 +Gc2_36 0 n4 ns36 0 -0.00021971853003 +Gc2_37 0 n4 ns37 0 5.87011098774e-007 +Gc2_38 0 n4 ns38 0 -3.09892105768e-007 +Gc2_39 0 n4 ns39 0 0.000681282984867 +Gc2_40 0 n4 ns40 0 -0.00253573406975 +Gc2_41 0 n4 ns41 0 0.00326163171595 +Gc2_42 0 n4 ns42 0 0.000550209767245 +Gc2_43 0 n4 ns43 0 -0.000672430363358 +Gc2_44 0 n4 ns44 0 -0.000293082994571 +Gc2_45 0 n4 ns45 0 0.0108571494931 +Gc2_46 0 n4 ns46 0 0.0348262016659 +Gc2_47 0 n4 ns47 0 5.50588423991e-005 +Gc2_48 0 n4 ns48 0 -0.000168542473609 +Gc2_49 0 n4 ns49 0 -0.00543537626863 +Gc2_50 0 n4 ns50 0 -0.00136512383782 +Gc2_51 0 n4 ns51 0 0.0001367066181 +Gc2_52 0 n4 ns52 0 -0.000160920583173 +Gc2_53 0 n4 ns53 0 -0.00012451876043 +Gc2_54 0 n4 ns54 0 -0.00186163286802 +Gc2_55 0 n4 ns55 0 -5.883829478e-005 +Gc2_56 0 n4 ns56 0 0.000560679455002 +Gc2_57 0 n4 ns57 0 0.000106995223469 +Gc2_58 0 n4 ns58 0 0.0014341691608 +Gc2_59 0 n4 ns59 0 -0.000289388135935 +Gc2_60 0 n4 ns60 0 4.1825775428e-007 +Gc2_61 0 n4 ns61 0 -5.17114189647e-007 +Gc2_62 0 n4 ns62 0 0.000604546642238 +Gc2_63 0 n4 ns63 0 -0.00193285721607 +Gc2_64 0 n4 ns64 0 -0.00157148621904 +Gc2_65 0 n4 ns65 0 0.00205009894198 +Gc2_66 0 n4 ns66 0 0.0005721186007 +Gc2_67 0 n4 ns67 0 2.34577086176e-005 +Gc2_68 0 n4 ns68 0 -0.00230069490905 +Gc2_69 0 n4 ns69 0 -0.0019392234081 +Gc2_70 0 n4 ns70 0 -6.17790153722e-005 +Gc2_71 0 n4 ns71 0 0.00016237384453 +Gc2_72 0 n4 ns72 0 0.0054502059755 +Gc2_73 0 n4 ns73 0 0.00139655041997 +Gc2_74 0 n4 ns74 0 -0.000153425296051 +Gc2_75 0 n4 ns75 0 0.000182297422035 +Gc2_76 0 n4 ns76 0 4.31824052741e-005 +Gc2_77 0 n4 ns77 0 0.00109729654388 +Gc2_78 0 n4 ns78 0 -0.00033678629826 +Gc2_79 0 n4 ns79 0 0.00046800992907 +Gc2_80 0 n4 ns80 0 0.000288516828949 +Gc2_81 0 n4 ns81 0 -0.001747314478 +Gc2_82 0 n4 ns82 0 0.000301657664331 +Gc2_83 0 n4 ns83 0 3.37787646175e-007 +Gc2_84 0 n4 ns84 0 -5.88519367589e-007 +Gc2_85 0 n4 ns85 0 -0.000372561810435 +Gc2_86 0 n4 ns86 0 0.000754293414862 +Gc2_87 0 n4 ns87 0 -0.000145203889072 +Gc2_88 0 n4 ns88 0 -0.000733755892124 +Gc2_89 0 n4 ns89 0 0.000562960251186 +Gc2_90 0 n4 ns90 0 -0.000318602915028 +Gc2_91 0 n4 ns91 0 -0.00317000199649 +Gc2_92 0 n4 ns92 0 -0.00234121459781 +Gc2_93 0 n4 ns93 0 -0.000177079973565 +Gc2_94 0 n4 ns94 0 -0.000318434115325 +Gc2_95 0 n4 ns95 0 -0.0109447407213 +Gc2_96 0 n4 ns96 0 -0.00264598381415 +Gc2_97 0 n4 ns97 0 0.000268288646956 +Gc2_98 0 n4 ns98 0 -0.000295386867606 +Gc2_99 0 n4 ns99 0 -0.000324661027621 +Gc2_100 0 n4 ns100 0 -0.00327953742521 +Gc2_101 0 n4 ns101 0 0.000453656678993 +Gc2_102 0 n4 ns102 0 -9.0933318211e-005 +Gc2_103 0 n4 ns103 0 -0.000194138757353 +Gc2_104 0 n4 ns104 0 -0.00138513776671 +Gc2_105 0 n4 ns105 0 0.000219749662286 +Gc2_106 0 n4 ns106 0 1.5401503498e-007 +Gc2_107 0 n4 ns107 0 -5.02628188808e-007 +Gc2_108 0 n4 ns108 0 -0.000886247932822 +Gc2_109 0 n4 ns109 0 0.00230543165286 +Gc2_110 0 n4 ns110 0 -0.00209503374515 +Gc2_111 0 n4 ns111 0 -0.000210165116155 +Gc2_112 0 n4 ns112 0 0.000271103318975 +Gc2_113 0 n4 ns113 0 0.000280765233517 +Gc2_114 0 n4 ns114 0 -0.0106726086235 +Gc2_115 0 n4 ns115 0 -0.0118187851637 +Gc2_116 0 n4 ns116 0 -6.00101205481e-005 +Gc2_117 0 n4 ns117 0 0.00016947686401 +Gc2_118 0 n4 ns118 0 0.00541854138971 +Gc2_119 0 n4 ns119 0 0.00139980580218 +Gc2_120 0 n4 ns120 0 -0.000139938893742 +Gc2_121 0 n4 ns121 0 0.000184144473873 +Gc2_122 0 n4 ns122 0 5.03892020836e-005 +Gc2_123 0 n4 ns123 0 0.00173561313602 +Gc2_124 0 n4 ns124 0 6.64301432259e-005 +Gc2_125 0 n4 ns125 0 -0.000586973400184 +Gc2_126 0 n4 ns126 0 -9.26709262046e-005 +Gc2_127 0 n4 ns127 0 -0.00144373655585 +Gc2_128 0 n4 ns128 0 0.000277047748512 +Gc2_129 0 n4 ns129 0 2.36226242383e-007 +Gc2_130 0 n4 ns130 0 -6.064563028e-007 +Gc2_131 0 n4 ns131 0 -0.000508544117794 +Gc2_132 0 n4 ns132 0 0.00199219709592 +Gc2_133 0 n4 ns133 0 0.000996486526594 +Gc2_134 0 n4 ns134 0 -0.0023384219511 +Gc2_135 0 n4 ns135 0 -0.000202460798351 +Gc2_136 0 n4 ns136 0 -1.03866318949e-005 +Gc2_137 0 n4 ns137 0 -0.00364632556059 +Gc2_138 0 n4 ns138 0 -0.00235930766756 +Gd2_1 0 n4 ni1 0 -0.00105174951459 +Gd2_2 0 n4 ni2 0 0.00444861469182 +Gd2_3 0 n4 ni3 0 -0.000785745306711 +Gd2_4 0 n4 ni4 0 -0.000950806674492 +Gd2_5 0 n4 ni5 0 -0.00480557707732 +Gd2_6 0 n4 ni6 0 -0.00126807699013 +Gc3_1 0 n6 ns1 0 6.25002458236e-005 +Gc3_2 0 n6 ns2 0 -0.000185228432402 +Gc3_3 0 n6 ns3 0 -0.00551666074913 +Gc3_4 0 n6 ns4 0 -0.00119279403176 +Gc3_5 0 n6 ns5 0 9.07118212046e-005 +Gc3_6 0 n6 ns6 0 -0.000136467497689 +Gc3_7 0 n6 ns7 0 -0.000142049305459 +Gc3_8 0 n6 ns8 0 0.000639240706976 +Gc3_9 0 n6 ns9 0 1.63522665337e-005 +Gc3_10 0 n6 ns10 0 -0.00238126626345 +Gc3_11 0 n6 ns11 0 0.000139792002035 +Gc3_12 0 n6 ns12 0 0.00187542985122 +Gc3_13 0 n6 ns13 0 -0.000386115102454 +Gc3_14 0 n6 ns14 0 3.90706116821e-007 +Gc3_15 0 n6 ns15 0 -5.78704925816e-007 +Gc3_16 0 n6 ns16 0 0.000324834716413 +Gc3_17 0 n6 ns17 0 -0.000222816489304 +Gc3_18 0 n6 ns18 0 -0.000168330091002 +Gc3_19 0 n6 ns19 0 6.38319585954e-005 +Gc3_20 0 n6 ns20 0 -0.000363664497935 +Gc3_21 0 n6 ns21 0 0.000394133825546 +Gc3_22 0 n6 ns22 0 -0.00262356611927 +Gc3_23 0 n6 ns23 0 -0.00211771266 +Gc3_24 0 n6 ns24 0 5.7544237818e-005 +Gc3_25 0 n6 ns25 0 -0.000168800340638 +Gc3_26 0 n6 ns26 0 -0.00543444913022 +Gc3_27 0 n6 ns27 0 -0.00136478933251 +Gc3_28 0 n6 ns28 0 0.00013655339278 +Gc3_29 0 n6 ns29 0 -0.000160835837979 +Gc3_30 0 n6 ns30 0 -0.00012273462761 +Gc3_31 0 n6 ns31 0 -0.00185944693937 +Gc3_32 0 n6 ns32 0 -5.9346884336e-005 +Gc3_33 0 n6 ns33 0 0.000559578671223 +Gc3_34 0 n6 ns34 0 0.000107431878203 +Gc3_35 0 n6 ns35 0 0.0014332756647 +Gc3_36 0 n6 ns36 0 -0.000288935023089 +Gc3_37 0 n6 ns37 0 4.21422401967e-007 +Gc3_38 0 n6 ns38 0 -5.08892124273e-007 +Gc3_39 0 n6 ns39 0 0.000605136503418 +Gc3_40 0 n6 ns40 0 -0.00193455271025 +Gc3_41 0 n6 ns41 0 -0.00157377930697 +Gc3_42 0 n6 ns42 0 0.00205529856367 +Gc3_43 0 n6 ns43 0 0.00057083652435 +Gc3_44 0 n6 ns44 0 2.05337909885e-005 +Gc3_45 0 n6 ns45 0 -0.00227262036787 +Gc3_46 0 n6 ns46 0 -0.00192705949424 +Gc3_47 0 n6 ns47 0 0.000168873042619 +Gc3_48 0 n6 ns48 0 0.000339807340654 +Gc3_49 0 n6 ns49 0 0.0110273547151 +Gc3_50 0 n6 ns50 0 0.00244004179695 +Gc3_51 0 n6 ns51 0 -0.000197646920505 +Gc3_52 0 n6 ns52 0 0.000253548577889 +Gc3_53 0 n6 ns53 0 0.000213078599427 +Gc3_54 0 n6 ns54 0 0.00100684773288 +Gc3_55 0 n6 ns55 0 0.000156004807985 +Gc3_56 0 n6 ns56 0 0.0023604664823 +Gc3_57 0 n6 ns57 0 -0.000403541603802 +Gc3_58 0 n6 ns58 0 0.00153239203417 +Gc3_59 0 n6 ns59 0 -0.000335516561073 +Gc3_60 0 n6 ns60 0 5.29191512386e-007 +Gc3_61 0 n6 ns61 0 -4.28358543319e-007 +Gc3_62 0 n6 ns62 0 0.00131220669073 +Gc3_63 0 n6 ns63 0 -0.000450081312731 +Gc3_64 0 n6 ns64 0 0.00236384887321 +Gc3_65 0 n6 ns65 0 -0.00189927816915 +Gc3_66 0 n6 ns66 0 -0.000739445285093 +Gc3_67 0 n6 ns67 0 -0.0001910184037 +Gc3_68 0 n6 ns68 0 0.0132962945903 +Gc3_69 0 n6 ns69 0 0.0370599078762 +Gc3_70 0 n6 ns70 0 -6.0843599662e-005 +Gc3_71 0 n6 ns71 0 0.000185437370322 +Gc3_72 0 n6 ns72 0 0.00550724365839 +Gc3_73 0 n6 ns73 0 0.0012238612259 +Gc3_74 0 n6 ns74 0 -9.34355683093e-005 +Gc3_75 0 n6 ns75 0 0.000159049111091 +Gc3_76 0 n6 ns76 0 7.09514915206e-005 +Gc3_77 0 n6 ns77 0 -0.000551066340167 +Gc3_78 0 n6 ns78 0 -1.24281401158e-005 +Gc3_79 0 n6 ns79 0 0.00209520996326 +Gc3_80 0 n6 ns80 0 -0.000119939317798 +Gc3_81 0 n6 ns81 0 -0.00185804561258 +Gc3_82 0 n6 ns82 0 0.000369470665149 +Gc3_83 0 n6 ns83 0 3.40468721447e-007 +Gc3_84 0 n6 ns84 0 -5.41095074996e-007 +Gc3_85 0 n6 ns85 0 -0.000312110424613 +Gc3_86 0 n6 ns86 0 0.000444316277393 +Gc3_87 0 n6 ns87 0 -1.56999489717e-005 +Gc3_88 0 n6 ns88 0 -0.000543627769407 +Gc3_89 0 n6 ns89 0 0.000474167860709 +Gc3_90 0 n6 ns90 0 -0.000313809423494 +Gc3_91 0 n6 ns91 0 -0.00301630534184 +Gc3_92 0 n6 ns92 0 -0.00206726804963 +Gc3_93 0 n6 ns93 0 -5.49324708981e-005 +Gc3_94 0 n6 ns94 0 0.000168769178266 +Gc3_95 0 n6 ns95 0 0.00542874965787 +Gc3_96 0 n6 ns96 0 0.00138910091771 +Gc3_97 0 n6 ns97 0 -0.000138263269921 +Gc3_98 0 n6 ns98 0 0.000179092765513 +Gc3_99 0 n6 ns99 0 6.32379131965e-005 +Gc3_100 0 n6 ns100 0 0.00178714266932 +Gc3_101 0 n6 ns101 0 4.98263144683e-005 +Gc3_102 0 n6 ns102 0 -0.000547209111074 +Gc3_103 0 n6 ns103 0 -8.31374320022e-005 +Gc3_104 0 n6 ns104 0 -0.0014720684587 +Gc3_105 0 n6 ns105 0 0.000284849895381 +Gc3_106 0 n6 ns106 0 2.65317408525e-007 +Gc3_107 0 n6 ns107 0 -5.7745872729e-007 +Gc3_108 0 n6 ns108 0 -0.000553769631507 +Gc3_109 0 n6 ns109 0 0.00183498651273 +Gc3_110 0 n6 ns110 0 0.00104779706493 +Gc3_111 0 n6 ns111 0 -0.00211961370323 +Gc3_112 0 n6 ns112 0 -0.000249434072008 +Gc3_113 0 n6 ns113 0 3.36882003162e-005 +Gc3_114 0 n6 ns114 0 -0.00314302813602 +Gc3_115 0 n6 ns115 0 -0.00228158315941 +Gc3_116 0 n6 ns116 0 -0.000177614705823 +Gc3_117 0 n6 ns117 0 -0.000341300038388 +Gc3_118 0 n6 ns118 0 -0.010984233776 +Gc3_119 0 n6 ns119 0 -0.00250943488371 +Gc3_120 0 n6 ns120 0 0.000213945621098 +Gc3_121 0 n6 ns121 0 -0.000283295627779 +Gc3_122 0 n6 ns122 0 -0.000313413911028 +Gc3_123 0 n6 ns123 0 -0.000891590067946 +Gc3_124 0 n6 ns124 0 -0.000137165628194 +Gc3_125 0 n6 ns125 0 -0.00223624791951 +Gc3_126 0 n6 ns126 0 0.000386510665256 +Gc3_127 0 n6 ns127 0 -0.00153401683901 +Gc3_128 0 n6 ns128 0 0.00032809694419 +Gc3_129 0 n6 ns129 0 4.14512867717e-007 +Gc3_130 0 n6 ns130 0 -4.43424229829e-007 +Gc3_131 0 n6 ns131 0 -0.0014524111548 +Gc3_132 0 n6 ns132 0 0.000493978404178 +Gc3_133 0 n6 ns133 0 -0.0013978449632 +Gc3_134 0 n6 ns134 0 0.00189031175264 +Gc3_135 0 n6 ns135 0 0.000385736750296 +Gc3_136 0 n6 ns136 0 0.000154444563668 +Gc3_137 0 n6 ns137 0 -0.0129215827536 +Gc3_138 0 n6 ns138 0 -0.0133535700579 +Gd3_1 0 n6 ni1 0 -0.000950385226456 +Gd3_2 0 n6 ni2 0 -0.000768252387764 +Gd3_3 0 n6 ni3 0 0.00514410604768 +Gd3_4 0 n6 ni4 0 -0.000906963382727 +Gd3_5 0 n6 ni5 0 -0.000919504794856 +Gd3_6 0 n6 ni6 0 -0.00584990532856 +Gc4_1 0 n8 ns1 0 -0.000174346940492 +Gc4_2 0 n8 ns2 0 -0.000333535600263 +Gc4_3 0 n8 ns3 0 -0.0109778888936 +Gc4_4 0 n8 ns4 0 -0.0025455118389 +Gc4_5 0 n8 ns5 0 0.00023751107279 +Gc4_6 0 n8 ns6 0 -0.000284145036811 +Gc4_7 0 n8 ns7 0 -0.00033349320079 +Gc4_8 0 n8 ns8 0 -0.000319725575698 +Gc4_9 0 n8 ns9 0 0.000194780190844 +Gc4_10 0 n8 ns10 0 -0.00204858601471 +Gc4_11 0 n8 ns11 0 -8.12050684607e-005 +Gc4_12 0 n8 ns12 0 -0.00227415081155 +Gc4_13 0 n8 ns13 0 0.000417194799992 +Gc4_14 0 n8 ns14 0 3.07707252289e-007 +Gc4_15 0 n8 ns15 0 -3.77379807531e-007 +Gc4_16 0 n8 ns16 0 -0.000244713057449 +Gc4_17 0 n8 ns17 0 -0.000143051440484 +Gc4_18 0 n8 ns18 0 -5.64532912751e-005 +Gc4_19 0 n8 ns19 0 0.000866573351422 +Gc4_20 0 n8 ns20 0 -0.00142604801096 +Gc4_21 0 n8 ns21 0 0.0016419477326 +Gc4_22 0 n8 ns22 0 -0.0140450594818 +Gc4_23 0 n8 ns23 0 -0.0136826054803 +Gc4_24 0 n8 ns24 0 -5.92610471742e-005 +Gc4_25 0 n8 ns25 0 0.000162248420677 +Gc4_26 0 n8 ns26 0 0.00545076073734 +Gc4_27 0 n8 ns27 0 0.00139742129808 +Gc4_28 0 n8 ns28 0 -0.000153711318726 +Gc4_29 0 n8 ns29 0 0.000181407262386 +Gc4_30 0 n8 ns30 0 4.03134833842e-005 +Gc4_31 0 n8 ns31 0 0.00109386069095 +Gc4_32 0 n8 ns32 0 -0.000334924964292 +Gc4_33 0 n8 ns33 0 0.000468735824048 +Gc4_34 0 n8 ns34 0 0.000286877928688 +Gc4_35 0 n8 ns35 0 -0.00174448345243 +Gc4_36 0 n8 ns36 0 0.000300476905636 +Gc4_37 0 n8 ns37 0 3.12472316704e-007 +Gc4_38 0 n8 ns38 0 -5.98847891687e-007 +Gc4_39 0 n8 ns39 0 -0.000370942389893 +Gc4_40 0 n8 ns40 0 0.000762789705714 +Gc4_41 0 n8 ns41 0 -0.000142378619901 +Gc4_42 0 n8 ns42 0 -0.000754505246135 +Gc4_43 0 n8 ns43 0 0.000565936795252 +Gc4_44 0 n8 ns44 0 -0.000309540692133 +Gc4_45 0 n8 ns45 0 -0.00321422818468 +Gc4_46 0 n8 ns46 0 -0.00235518583613 +Gc4_47 0 n8 ns47 0 -5.86400387956e-005 +Gc4_48 0 n8 ns48 0 0.000185488098694 +Gc4_49 0 n8 ns49 0 0.00550732425647 +Gc4_50 0 n8 ns50 0 0.00122548871885 +Gc4_51 0 n8 ns51 0 -9.40370998532e-005 +Gc4_52 0 n8 ns52 0 0.000158132999301 +Gc4_53 0 n8 ns53 0 6.78180880088e-005 +Gc4_54 0 n8 ns54 0 -0.000551508196115 +Gc4_55 0 n8 ns55 0 -1.02244091596e-005 +Gc4_56 0 n8 ns56 0 0.00209257275473 +Gc4_57 0 n8 ns57 0 -0.000121703639788 +Gc4_58 0 n8 ns58 0 -0.00185490142002 +Gc4_59 0 n8 ns59 0 0.000367928298979 +Gc4_60 0 n8 ns60 0 3.38931690583e-007 +Gc4_61 0 n8 ns61 0 -5.4276778697e-007 +Gc4_62 0 n8 ns62 0 -0.000313072687075 +Gc4_63 0 n8 ns63 0 0.000449216245495 +Gc4_64 0 n8 ns64 0 -1.03267705648e-005 +Gc4_65 0 n8 ns65 0 -0.000554260638901 +Gc4_66 0 n8 ns66 0 0.000474332223525 +Gc4_67 0 n8 ns67 0 -0.000308615889413 +Gc4_68 0 n8 ns68 0 -0.00304426542111 +Gc4_69 0 n8 ns69 0 -0.0020785901215 +Gc4_70 0 n8 ns70 0 0.000153003107653 +Gc4_71 0 n8 ns71 0 0.000330536682289 +Gc4_72 0 n8 ns72 0 0.0109992379223 +Gc4_73 0 n8 ns73 0 0.00249327759276 +Gc4_74 0 n8 ns74 0 -0.000221602802248 +Gc4_75 0 n8 ns75 0 0.000268455292286 +Gc4_76 0 n8 ns76 0 0.000136601905962 +Gc4_77 0 n8 ns77 0 0.000347043712727 +Gc4_78 0 n8 ns78 0 -0.000137206933572 +Gc4_79 0 n8 ns79 0 0.00179569550931 +Gc4_80 0 n8 ns80 0 3.89031571326e-005 +Gc4_81 0 n8 ns81 0 0.00223395084199 +Gc4_82 0 n8 ns82 0 -0.000423893843225 +Gc4_83 0 n8 ns83 0 3.51476337369e-007 +Gc4_84 0 n8 ns84 0 -4.42754651298e-007 +Gc4_85 0 n8 ns85 0 0.000205411711315 +Gc4_86 0 n8 ns86 0 -2.6451927154e-005 +Gc4_87 0 n8 ns87 0 -9.72807555305e-006 +Gc4_88 0 n8 ns88 0 -0.00044032848562 +Gc4_89 0 n8 ns89 0 0.000954430326102 +Gc4_90 0 n8 ns90 0 -0.00150220444617 +Gc4_91 0 n8 ns91 0 0.016455292225 +Gc4_92 0 n8 ns92 0 0.0386301932718 +Gc4_93 0 n8 ns93 0 6.41873700464e-005 +Gc4_94 0 n8 ns94 0 -0.000161581862012 +Gc4_95 0 n8 ns95 0 -0.00544989685535 +Gc4_96 0 n8 ns96 0 -0.0013789855854 +Gc4_97 0 n8 ns97 0 0.000152308806719 +Gc4_98 0 n8 ns98 0 -0.0001687213992 +Gc4_99 0 n8 ns99 0 -7.38504568159e-005 +Gc4_100 0 n8 ns100 0 -0.00098590522384 +Gc4_101 0 n8 ns101 0 0.000331845846591 +Gc4_102 0 n8 ns102 0 -0.000452020494086 +Gc4_103 0 n8 ns103 0 -0.000265391348746 +Gc4_104 0 n8 ns104 0 0.00177213186066 +Gc4_105 0 n8 ns105 0 -0.000314621889349 +Gc4_106 0 n8 ns106 0 3.74030387638e-007 +Gc4_107 0 n8 ns107 0 -5.09838015962e-007 +Gc4_108 0 n8 ns108 0 0.000281568320795 +Gc4_109 0 n8 ns109 0 -0.000567456272807 +Gc4_110 0 n8 ns110 0 0.000290166753411 +Gc4_111 0 n8 ns111 0 0.000321362226695 +Gc4_112 0 n8 ns112 0 -0.000319174375591 +Gc4_113 0 n8 ns113 0 0.00029993249312 +Gc4_114 0 n8 ns114 0 -0.00369992260868 +Gc4_115 0 n8 ns115 0 -0.00292314325093 +Gc4_116 0 n8 ns116 0 6.39843856294e-005 +Gc4_117 0 n8 ns117 0 -0.000184909934132 +Gc4_118 0 n8 ns118 0 -0.00550803846682 +Gc4_119 0 n8 ns119 0 -0.00120482035761 +Gc4_120 0 n8 ns120 0 9.25107895752e-005 +Gc4_121 0 n8 ns121 0 -0.000143855873223 +Gc4_122 0 n8 ns122 0 -0.000107160837581 +Gc4_123 0 n8 ns123 0 0.000531414901016 +Gc4_124 0 n8 ns124 0 2.73324868585e-005 +Gc4_125 0 n8 ns125 0 -0.00200316226735 +Gc4_126 0 n8 ns126 0 0.000114012977671 +Gc4_127 0 n8 ns127 0 0.00184654691294 +Gc4_128 0 n8 ns128 0 -0.000375163040294 +Gc4_129 0 n8 ns129 0 4.51298303054e-007 +Gc4_130 0 n8 ns130 0 -4.5250575938e-007 +Gc4_131 0 n8 ns131 0 0.000257129383442 +Gc4_132 0 n8 ns132 0 -0.000312049237623 +Gc4_133 0 n8 ns133 0 0.00015288115693 +Gc4_134 0 n8 ns134 0 0.000151590465129 +Gc4_135 0 n8 ns135 0 -0.000188748453236 +Gc4_136 0 n8 ns136 0 0.000232989426166 +Gc4_137 0 n8 ns137 0 -0.00378837434423 +Gc4_138 0 n8 ns138 0 -0.00299034684078 +Gd4_1 0 n8 ni1 0 -0.00630061415443 +Gd4_2 0 n8 ni2 0 -0.000979723319335 +Gd4_3 0 n8 ni3 0 -0.00092504142826 +Gd4_4 0 n8 ni4 0 0.00574390103035 +Gd4_5 0 n8 ni5 0 -0.000949317821969 +Gd4_6 0 n8 ni6 0 -0.00102784437665 +Gc5_1 0 n10 ns1 0 -6.82175034668e-005 +Gc5_2 0 n10 ns2 0 0.000163056647158 +Gc5_3 0 n10 ns3 0 0.0054436111705 +Gc5_4 0 n10 ns4 0 0.00140026018821 +Gc5_5 0 n10 ns5 0 -0.000154036916292 +Gc5_6 0 n10 ns6 0 0.000183198291865 +Gc5_7 0 n10 ns7 0 3.47742549616e-005 +Gc5_8 0 n10 ns8 0 0.00107797909024 +Gc5_9 0 n10 ns9 0 -0.00035288815927 +Gc5_10 0 n10 ns10 0 0.000448186364533 +Gc5_11 0 n10 ns11 0 0.000297874641369 +Gc5_12 0 n10 ns12 0 -0.00180746956667 +Gc5_13 0 n10 ns13 0 0.00031132312321 +Gc5_14 0 n10 ns14 0 3.01868213449e-007 +Gc5_15 0 n10 ns15 0 -6.54500406085e-007 +Gc5_16 0 n10 ns16 0 -0.000255045858262 +Gc5_17 0 n10 ns17 0 0.000568987436347 +Gc5_18 0 n10 ns18 0 -0.000148459989117 +Gc5_19 0 n10 ns19 0 -0.000670035056778 +Gc5_20 0 n10 ns20 0 0.000528716206374 +Gc5_21 0 n10 ns21 0 -0.000287861003018 +Gc5_22 0 n10 ns22 0 -0.00354951701832 +Gc5_23 0 n10 ns23 0 -0.0023467021348 +Gc5_24 0 n10 ns24 0 -0.000181016087053 +Gc5_25 0 n10 ns25 0 -0.000318708768704 +Gc5_26 0 n10 ns26 0 -0.010949131897 +Gc5_27 0 n10 ns27 0 -0.00263805574563 +Gc5_28 0 n10 ns28 0 0.000267531877897 +Gc5_29 0 n10 ns29 0 -0.000290507517967 +Gc5_30 0 n10 ns30 0 -0.000320279908909 +Gc5_31 0 n10 ns31 0 -0.00327814818587 +Gc5_32 0 n10 ns32 0 0.000446582072653 +Gc5_33 0 n10 ns33 0 -8.59507849906e-005 +Gc5_34 0 n10 ns34 0 -0.000189626909496 +Gc5_35 0 n10 ns35 0 -0.00138313874799 +Gc5_36 0 n10 ns36 0 0.000220249901352 +Gc5_37 0 n10 ns37 0 1.56453403846e-007 +Gc5_38 0 n10 ns38 0 -4.7755795107e-007 +Gc5_39 0 n10 ns39 0 -0.000884514677333 +Gc5_40 0 n10 ns40 0 0.00228909042373 +Gc5_41 0 n10 ns41 0 -0.00210425834349 +Gc5_42 0 n10 ns42 0 -0.000175574893183 +Gc5_43 0 n10 ns43 0 0.000261161238143 +Gc5_44 0 n10 ns44 0 0.000264711565424 +Gc5_45 0 n10 ns45 0 -0.0104891991377 +Gc5_46 0 n10 ns46 0 -0.0117398915361 +Gc5_47 0 n10 ns47 0 -5.46733581124e-005 +Gc5_48 0 n10 ns48 0 0.000168899414503 +Gc5_49 0 n10 ns49 0 0.00542836429409 +Gc5_50 0 n10 ns50 0 0.00139198760365 +Gc5_51 0 n10 ns51 0 -0.0001391527417 +Gc5_52 0 n10 ns52 0 0.00017896139183 +Gc5_53 0 n10 ns53 0 5.96267801247e-005 +Gc5_54 0 n10 ns54 0 0.00178387611859 +Gc5_55 0 n10 ns55 0 5.2482636414e-005 +Gc5_56 0 n10 ns56 0 -0.000546582023272 +Gc5_57 0 n10 ns57 0 -8.53663982156e-005 +Gc5_58 0 n10 ns58 0 -0.00146965474152 +Gc5_59 0 n10 ns59 0 0.0002834688724 +Gc5_60 0 n10 ns60 0 2.71990758896e-007 +Gc5_61 0 n10 ns61 0 -5.70428060546e-007 +Gc5_62 0 n10 ns62 0 -0.000553706595753 +Gc5_63 0 n10 ns63 0 0.00183636948896 +Gc5_64 0 n10 ns64 0 0.00105007908911 +Gc5_65 0 n10 ns65 0 -0.00212591018424 +Gc5_66 0 n10 ns66 0 -0.00024735508593 +Gc5_67 0 n10 ns67 0 3.79729079201e-005 +Gc5_68 0 n10 ns68 0 -0.00317555054917 +Gc5_69 0 n10 ns69 0 -0.00229512905846 +Gc5_70 0 n10 ns70 0 6.67617896937e-005 +Gc5_71 0 n10 ns71 0 -0.000162377874226 +Gc5_72 0 n10 ns72 0 -0.00544898615845 +Gc5_73 0 n10 ns73 0 -0.00138040408366 +Gc5_74 0 n10 ns74 0 0.000153006904569 +Gc5_75 0 n10 ns75 0 -0.000169898847674 +Gc5_76 0 n10 ns76 0 -7.47740074055e-005 +Gc5_77 0 n10 ns77 0 -0.000985135255897 +Gc5_78 0 n10 ns78 0 0.000331913432088 +Gc5_79 0 n10 ns79 0 -0.000452893913769 +Gc5_80 0 n10 ns80 0 -0.000264906153273 +Gc5_81 0 n10 ns81 0 0.00177185278998 +Gc5_82 0 n10 ns82 0 -0.000315244047376 +Gc5_83 0 n10 ns83 0 3.90573922278e-007 +Gc5_84 0 n10 ns84 0 -5.13634821501e-007 +Gc5_85 0 n10 ns85 0 0.00027942381081 +Gc5_86 0 n10 ns86 0 -0.000573829123109 +Gc5_87 0 n10 ns87 0 0.000291951757389 +Gc5_88 0 n10 ns88 0 0.000335066477311 +Gc5_89 0 n10 ns89 0 -0.000321838346139 +Gc5_90 0 n10 ns90 0 0.000295645916196 +Gc5_91 0 n10 ns91 0 -0.00368518796231 +Gc5_92 0 n10 ns92 0 -0.00292214027407 +Gc5_93 0 n10 ns93 0 0.000166759153931 +Gc5_94 0 n10 ns94 0 0.000318334764486 +Gc5_95 0 n10 ns95 0 0.0109488198798 +Gc5_96 0 n10 ns96 0 0.0026426988283 +Gc5_97 0 n10 ns97 0 -0.000264784471915 +Gc5_98 0 n10 ns98 0 0.000303660042963 +Gc5_99 0 n10 ns99 0 0.000165696906643 +Gc5_100 0 n10 ns100 0 0.00311469733745 +Gc5_101 0 n10 ns101 0 -0.000439242840501 +Gc5_102 0 n10 ns102 0 1.51215847031e-005 +Gc5_103 0 n10 ns103 0 0.000200954478997 +Gc5_104 0 n10 ns104 0 0.00139683255558 +Gc5_105 0 n10 ns105 0 -0.000234172956009 +Gc5_106 0 n10 ns106 0 2.79329441391e-007 +Gc5_107 0 n10 ns107 0 -5.31749077313e-007 +Gc5_108 0 n10 ns108 0 0.00074416357575 +Gc5_109 0 n10 ns109 0 -0.0021630887254 +Gc5_110 0 n10 ns110 0 0.00169148157059 +Gc5_111 0 n10 ns111 0 0.00030989300245 +Gc5_112 0 n10 ns112 0 -0.000293447838678 +Gc5_113 0 n10 ns113 0 -0.000290387258669 +Gc5_114 0 n10 ns114 0 0.0134284960614 +Gc5_115 0 n10 ns115 0 0.0372977583966 +Gc5_116 0 n10 ns116 0 5.97660363604e-005 +Gc5_117 0 n10 ns117 0 -0.000168646314786 +Gc5_118 0 n10 ns118 0 -0.00542540780606 +Gc5_119 0 n10 ns119 0 -0.00137815415476 +Gc5_120 0 n10 ns120 0 0.000138583491032 +Gc5_121 0 n10 ns121 0 -0.000168781603324 +Gc5_122 0 n10 ns122 0 -9.10743235203e-005 +Gc5_123 0 n10 ns123 0 -0.00157427668438 +Gc5_124 0 n10 ns124 0 -4.26089426045e-005 +Gc5_125 0 n10 ns125 0 0.000469579923999 +Gc5_126 0 n10 ns126 0 8.91862763623e-005 +Gc5_127 0 n10 ns127 0 0.00146041442417 +Gc5_128 0 n10 ns128 0 -0.000290390816761 +Gc5_129 0 n10 ns129 0 4.57468368001e-007 +Gc5_130 0 n10 ns130 0 -4.43961853756e-007 +Gc5_131 0 n10 ns131 0 0.000461342515984 +Gc5_132 0 n10 ns132 0 -0.00165210537691 +Gc5_133 0 n10 ns133 0 -0.000595516810334 +Gc5_134 0 n10 ns134 0 0.00166282728227 +Gc5_135 0 n10 ns135 0 0.000233104909739 +Gc5_136 0 n10 ns136 0 4.52544219807e-005 +Gc5_137 0 n10 ns137 0 -0.00358733044469 +Gc5_138 0 n10 ns138 0 -0.00288569318776 +Gd5_1 0 n10 ni1 0 -0.0012525842966 +Gd5_2 0 n10 ni2 0 -0.00468867620029 +Gd5_3 0 n10 ni3 0 -0.000940840061949 +Gd5_4 0 n10 ni4 0 -0.000939594784611 +Gd5_5 0 n10 ni5 0 0.0043204608503 +Gd5_6 0 n10 ni6 0 -0.00096007619323 +Gc6_1 0 n12 ns1 0 -6.66196444605e-005 +Gc6_2 0 n12 ns2 0 0.000186018403841 +Gc6_3 0 n12 ns3 0 0.00550304345009 +Gc6_4 0 n12 ns4 0 0.00122605515731 +Gc6_5 0 n12 ns5 0 -9.41795578138e-005 +Gc6_6 0 n12 ns6 0 0.000158786029426 +Gc6_7 0 n12 ns7 0 6.94558482473e-005 +Gc6_8 0 n12 ns8 0 -0.000521066231771 +Gc6_9 0 n12 ns9 0 -8.71506155299e-006 +Gc6_10 0 n12 ns10 0 0.00216646121022 +Gc6_11 0 n12 ns11 0 -0.000121611367369 +Gc6_12 0 n12 ns12 0 -0.00188181031382 +Gc6_13 0 n12 ns13 0 0.000372652221159 +Gc6_14 0 n12 ns14 0 3.38409997029e-007 +Gc6_15 0 n12 ns15 0 -5.6112682316e-007 +Gc6_16 0 n12 ns16 0 -0.000254734420373 +Gc6_17 0 n12 ns17 0 0.000346320246288 +Gc6_18 0 n12 ns18 0 -2.64920053711e-005 +Gc6_19 0 n12 ns19 0 -0.000432551143949 +Gc6_20 0 n12 ns20 0 0.000345203742547 +Gc6_21 0 n12 ns21 0 -0.000189615054874 +Gc6_22 0 n12 ns22 0 -0.00303368692 +Gc6_23 0 n12 ns23 0 -0.00222677021938 +Gc6_24 0 n12 ns24 0 -6.1532891557e-005 +Gc6_25 0 n12 ns25 0 0.000169595986449 +Gc6_26 0 n12 ns26 0 0.00541940382787 +Gc6_27 0 n12 ns27 0 0.00139904461341 +Gc6_28 0 n12 ns28 0 -0.000139835561454 +Gc6_29 0 n12 ns29 0 0.0001839163727 +Gc6_30 0 n12 ns30 0 4.68553238594e-005 +Gc6_31 0 n12 ns31 0 0.00172998154797 +Gc6_32 0 n12 ns32 0 6.88504892206e-005 +Gc6_33 0 n12 ns33 0 -0.000584368646903 +Gc6_34 0 n12 ns34 0 -9.53211021073e-005 +Gc6_35 0 n12 ns35 0 -0.00144029001131 +Gc6_36 0 n12 ns36 0 0.000275971479901 +Gc6_37 0 n12 ns37 0 2.41331232917e-007 +Gc6_38 0 n12 ns38 0 -6.10048036231e-007 +Gc6_39 0 n12 ns39 0 -0.000509540714524 +Gc6_40 0 n12 ns40 0 0.00199321327676 +Gc6_41 0 n12 ns41 0 0.00100007816345 +Gc6_42 0 n12 ns42 0 -0.00234455129416 +Gc6_43 0 n12 ns43 0 -0.000200462785343 +Gc6_44 0 n12 ns44 0 -6.2024503669e-006 +Gc6_45 0 n12 ns45 0 -0.00367784665836 +Gc6_46 0 n12 ns46 0 -0.00236997643465 +Gc6_47 0 n12 ns47 0 -0.000179541437417 +Gc6_48 0 n12 ns48 0 -0.000341817180813 +Gc6_49 0 n12 ns49 0 -0.0109863250479 +Gc6_50 0 n12 ns50 0 -0.00250645702715 +Gc6_51 0 n12 ns51 0 0.000214480904395 +Gc6_52 0 n12 ns52 0 -0.000280334288579 +Gc6_53 0 n12 ns53 0 -0.000308014758083 +Gc6_54 0 n12 ns54 0 -0.000891407263614 +Gc6_55 0 n12 ns55 0 -0.000141991027107 +Gc6_56 0 n12 ns56 0 -0.00223077090296 +Gc6_57 0 n12 ns57 0 0.000389286624625 +Gc6_58 0 n12 ns58 0 -0.00153168072533 +Gc6_59 0 n12 ns59 0 0.000328318997373 +Gc6_60 0 n12 ns60 0 4.11653752084e-007 +Gc6_61 0 n12 ns61 0 -4.06439034901e-007 +Gc6_62 0 n12 ns62 0 -0.00144981255536 +Gc6_63 0 n12 ns63 0 0.000480333160918 +Gc6_64 0 n12 ns64 0 -0.001409006941 +Gc6_65 0 n12 ns65 0 0.0019214188391 +Gc6_66 0 n12 ns66 0 0.000376499601693 +Gc6_67 0 n12 ns67 0 0.000137983979812 +Gc6_68 0 n12 ns68 0 -0.0127409747242 +Gc6_69 0 n12 ns69 0 -0.0132718502778 +Gc6_70 0 n12 ns70 0 6.46135695896e-005 +Gc6_71 0 n12 ns71 0 -0.000184966588806 +Gc6_72 0 n12 ns72 0 -0.0055083468512 +Gc6_73 0 n12 ns73 0 -0.00120501606204 +Gc6_74 0 n12 ns74 0 9.26373034596e-005 +Gc6_75 0 n12 ns75 0 -0.000145276596063 +Gc6_76 0 n12 ns76 0 -0.00010787108847 +Gc6_77 0 n12 ns77 0 0.000532455870375 +Gc6_78 0 n12 ns78 0 2.79900959202e-005 +Gc6_79 0 n12 ns79 0 -0.00200458867498 +Gc6_80 0 n12 ns80 0 0.000114099813441 +Gc6_81 0 n12 ns81 0 0.00184648798328 +Gc6_82 0 n12 ns82 0 -0.000376016778208 +Gc6_83 0 n12 ns83 0 4.55473899476e-007 +Gc6_84 0 n12 ns84 0 -4.56435548393e-007 +Gc6_85 0 n12 ns85 0 0.000257536135314 +Gc6_86 0 n12 ns86 0 -0.000311327669067 +Gc6_87 0 n12 ns87 0 0.000153519007997 +Gc6_88 0 n12 ns88 0 0.000149825442769 +Gc6_89 0 n12 ns89 0 -0.000189078583767 +Gc6_90 0 n12 ns90 0 0.000234647140703 +Gc6_91 0 n12 ns91 0 -0.00379033796181 +Gc6_92 0 n12 ns92 0 -0.0029937621654 +Gc6_93 0 n12 ns93 0 5.86034511528e-005 +Gc6_94 0 n12 ns94 0 -0.000168497310533 +Gc6_95 0 n12 ns95 0 -0.00542666117647 +Gc6_96 0 n12 ns96 0 -0.0013768974437 +Gc6_97 0 n12 ns97 0 0.000138243842202 +Gc6_98 0 n12 ns98 0 -0.000169630266206 +Gc6_99 0 n12 ns99 0 -9.15046119935e-005 +Gc6_100 0 n12 ns100 0 -0.00157428772242 +Gc6_101 0 n12 ns101 0 -4.34224787978e-005 +Gc6_102 0 n12 ns102 0 0.000469734652034 +Gc6_103 0 n12 ns103 0 9.03775313886e-005 +Gc6_104 0 n12 ns104 0 0.00146008717309 +Gc6_105 0 n12 ns105 0 -0.000290720241628 +Gc6_106 0 n12 ns106 0 4.60724455767e-007 +Gc6_107 0 n12 ns107 0 -4.43288603774e-007 +Gc6_108 0 n12 ns108 0 0.000459797339485 +Gc6_109 0 n12 ns109 0 -0.00165372982612 +Gc6_110 0 n12 ns110 0 -0.00059270079607 +Gc6_111 0 n12 ns111 0 0.00166690593377 +Gc6_112 0 n12 ns112 0 0.000231142543272 +Gc6_113 0 n12 ns113 0 4.43312041562e-005 +Gc6_114 0 n12 ns114 0 -0.00358380905384 +Gc6_115 0 n12 ns115 0 -0.00288715120578 +Gc6_116 0 n12 ns116 0 0.000165896874222 +Gc6_117 0 n12 ns117 0 0.000340273725745 +Gc6_118 0 n12 ns118 0 0.0109897843135 +Gc6_119 0 n12 ns119 0 0.0025037418003 +Gc6_120 0 n12 ns120 0 -0.000209598296637 +Gc6_121 0 n12 ns121 0 0.000290964428186 +Gc6_122 0 n12 ns122 0 0.000157769988742 +Gc6_123 0 n12 ns123 0 0.00085786332604 +Gc6_124 0 n12 ns124 0 0.000123237694901 +Gc6_125 0 n12 ns125 0 0.0020362185277 +Gc6_126 0 n12 ns126 0 -0.000345176118708 +Gc6_127 0 n12 ns127 0 0.00151809340173 +Gc6_128 0 n12 ns128 0 -0.000336641663535 +Gc6_129 0 n12 ns129 0 2.83437911941e-007 +Gc6_130 0 n12 ns130 0 -5.48386075605e-007 +Gc6_131 0 n12 ns131 0 0.00127004029837 +Gc6_132 0 n12 ns132 0 -0.000609115385261 +Gc6_133 0 n12 ns133 0 0.00109912281578 +Gc6_134 0 n12 ns134 0 -0.00147740387385 +Gc6_135 0 n12 ns135 0 -0.000415710857081 +Gc6_136 0 n12 ns136 0 -0.000179131339533 +Gc6_137 0 n12 ns137 0 0.0155416092015 +Gc6_138 0 n12 ns138 0 0.0386527788885 +Gd6_1 0 n12 ni1 0 -0.000921300460906 +Gd6_2 0 n12 ni2 0 -0.00129008661074 +Gd6_3 0 n12 ni3 0 -0.00573686156744 +Gd6_4 0 n12 ni4 0 -0.00102788759645 +Gd6_5 0 n12 ni5 0 -0.000957208871995 +Gd6_6 0 n12 ni6 0 0.00534781292676 +.ends + +.subckt 744839208072 1 2 3 4 5 6 +Vam1 1 n2 dc 0 +Rport1 n2 0 50 +Vam2 2 n4 dc 0 +Rport2 n4 0 50 +Vam3 3 n6 dc 0 +Rport3 n6 0 50 +Vam4 4 n8 dc 0 +Rport4 n8 0 50 +Vam5 5 n10 dc 0 +Rport5 n10 0 50 +Vam6 6 n12 dc 0 +Rport6 n12 0 50 + +Fi1 0 ni1 Vam1 50 +Gi1 0 ni1 1 0 1 +Rt1 ni1 0 1 +Fi2 0 ni2 Vam2 50 +Gi2 0 ni2 2 0 1 +Rt2 ni2 0 1 +Fi3 0 ni3 Vam3 50 +Gi3 0 ni3 3 0 1 +Rt3 ni3 0 1 +Fi4 0 ni4 Vam4 50 +Gi4 0 ni4 4 0 1 +Rt4 ni4 0 1 +Fi5 0 ni5 Vam5 50 +Gi5 0 ni5 5 0 1 +Rt5 ni5 0 1 +Fi6 0 ni6 Vam6 50 +Gi6 0 ni6 6 0 1 +Rt6 ni6 0 1 + +Ca1 ns1 0 1e-012 +Ra1 ns1 0 1285153296.08 +Ca2 ns2 0 1e-012 +Ra2 ns2 0 297889903.174 +Ca3 ns3 0 1e-012 +Ra3 ns3 0 3006167.60729 +Ca4 ns4 0 1e-012 +Ra4 ns4 0 928745.805552 +Ca5 ns5 0 1e-012 +Ra5 ns5 0 642936.910474 +Ca6 ns6 0 1e-012 +Ra6 ns6 0 168091.544894 +Ca7 ns7 0 1e-012 +Ca8 ns8 0 1e-012 +Ra7 ns7 0 4541912.34875 +Ra8 ns8 0 4541912.34875 +Ga7 ns7 0 ns8 0 -1.9368866379e-005 +Ga8 ns8 0 ns7 0 1.9368866379e-005 +Ca9 ns9 0 1e-012 +Ra9 ns9 0 20614.0861881 +Ca10 ns10 0 1e-012 +Ca11 ns11 0 1e-012 +Ra10 ns10 0 147098.94106 +Ra11 ns11 0 147098.94106 +Ga10 ns10 0 ns11 0 -5.3873313541e-005 +Ga11 ns11 0 ns10 0 5.3873313541e-005 +Ca12 ns12 0 1e-012 +Ca13 ns13 0 1e-012 +Ra12 ns12 0 137059.062494 +Ra13 ns13 0 137059.062494 +Ga12 ns12 0 ns13 0 -5.61796182679e-005 +Ga13 ns13 0 ns12 0 5.61796182679e-005 +Ca14 ns14 0 1e-012 +Ca15 ns15 0 1e-012 +Ra14 ns14 0 107286.124839 +Ra15 ns15 0 107286.124839 +Ga14 ns14 0 ns15 0 -6.75905194798e-005 +Ga15 ns15 0 ns14 0 6.75905194798e-005 +Ca16 ns16 0 1e-012 +Ca17 ns17 0 1e-012 +Ra16 ns16 0 40826.9263427 +Ra17 ns17 0 40826.9263427 +Ga16 ns16 0 ns17 0 -0.000199496956253 +Ga17 ns17 0 ns16 0 0.000199496956253 +Ca18 ns18 0 1e-012 +Ca19 ns19 0 1e-012 +Ra18 ns18 0 236317.272026 +Ra19 ns19 0 236317.272026 +Ga18 ns18 0 ns19 0 -0.000212445395998 +Ga19 ns19 0 ns18 0 0.000212445395998 +Ca20 ns20 0 1e-012 +Ca21 ns21 0 1e-012 +Ra20 ns20 0 41263.0408147 +Ra21 ns21 0 41263.0408147 +Ga20 ns20 0 ns21 0 -0.000213710510467 +Ga21 ns21 0 ns20 0 0.000213710510467 +Ca22 ns22 0 1e-012 +Ca23 ns23 0 1e-012 +Ra22 ns22 0 39479.0900285 +Ra23 ns23 0 39479.0900285 +Ga22 ns22 0 ns23 0 -0.000221729151294 +Ga23 ns23 0 ns22 0 0.000221729151294 +Ca24 ns24 0 1e-012 +Ca25 ns25 0 1e-012 +Ra24 ns24 0 30670.8761275 +Ra25 ns25 0 30670.8761275 +Ga24 ns24 0 ns25 0 -0.000330180611828 +Ga25 ns25 0 ns24 0 0.000330180611828 +Ca26 ns26 0 1e-012 +Ca27 ns27 0 1e-012 +Ra26 ns26 0 19693.214347 +Ra27 ns27 0 19693.214347 +Ga26 ns26 0 ns27 0 -0.000389415329596 +Ga27 ns27 0 ns26 0 0.000389415329596 +Ca28 ns28 0 1e-012 +Ca29 ns29 0 1e-012 +Ra28 ns28 0 1688.05455507 +Ra29 ns29 0 1688.05455507 +Ga28 ns28 0 ns29 0 -0.000477398482785 +Ga29 ns29 0 ns28 0 0.000477398482785 +Ca30 ns30 0 1e-012 +Ra30 ns30 0 1285153296.08 +Ca31 ns31 0 1e-012 +Ra31 ns31 0 297889903.174 +Ca32 ns32 0 1e-012 +Ra32 ns32 0 3006167.60729 +Ca33 ns33 0 1e-012 +Ra33 ns33 0 928745.805552 +Ca34 ns34 0 1e-012 +Ra34 ns34 0 642936.910474 +Ca35 ns35 0 1e-012 +Ra35 ns35 0 168091.544894 +Ca36 ns36 0 1e-012 +Ca37 ns37 0 1e-012 +Ra36 ns36 0 4541912.34875 +Ra37 ns37 0 4541912.34875 +Ga36 ns36 0 ns37 0 -1.9368866379e-005 +Ga37 ns37 0 ns36 0 1.9368866379e-005 +Ca38 ns38 0 1e-012 +Ra38 ns38 0 20614.0861881 +Ca39 ns39 0 1e-012 +Ca40 ns40 0 1e-012 +Ra39 ns39 0 147098.94106 +Ra40 ns40 0 147098.94106 +Ga39 ns39 0 ns40 0 -5.3873313541e-005 +Ga40 ns40 0 ns39 0 5.3873313541e-005 +Ca41 ns41 0 1e-012 +Ca42 ns42 0 1e-012 +Ra41 ns41 0 137059.062494 +Ra42 ns42 0 137059.062494 +Ga41 ns41 0 ns42 0 -5.61796182679e-005 +Ga42 ns42 0 ns41 0 5.61796182679e-005 +Ca43 ns43 0 1e-012 +Ca44 ns44 0 1e-012 +Ra43 ns43 0 107286.124839 +Ra44 ns44 0 107286.124839 +Ga43 ns43 0 ns44 0 -6.75905194798e-005 +Ga44 ns44 0 ns43 0 6.75905194798e-005 +Ca45 ns45 0 1e-012 +Ca46 ns46 0 1e-012 +Ra45 ns45 0 40826.9263427 +Ra46 ns46 0 40826.9263427 +Ga45 ns45 0 ns46 0 -0.000199496956253 +Ga46 ns46 0 ns45 0 0.000199496956253 +Ca47 ns47 0 1e-012 +Ca48 ns48 0 1e-012 +Ra47 ns47 0 236317.272026 +Ra48 ns48 0 236317.272026 +Ga47 ns47 0 ns48 0 -0.000212445395998 +Ga48 ns48 0 ns47 0 0.000212445395998 +Ca49 ns49 0 1e-012 +Ca50 ns50 0 1e-012 +Ra49 ns49 0 41263.0408147 +Ra50 ns50 0 41263.0408147 +Ga49 ns49 0 ns50 0 -0.000213710510467 +Ga50 ns50 0 ns49 0 0.000213710510467 +Ca51 ns51 0 1e-012 +Ca52 ns52 0 1e-012 +Ra51 ns51 0 39479.0900285 +Ra52 ns52 0 39479.0900285 +Ga51 ns51 0 ns52 0 -0.000221729151294 +Ga52 ns52 0 ns51 0 0.000221729151294 +Ca53 ns53 0 1e-012 +Ca54 ns54 0 1e-012 +Ra53 ns53 0 30670.8761275 +Ra54 ns54 0 30670.8761275 +Ga53 ns53 0 ns54 0 -0.000330180611828 +Ga54 ns54 0 ns53 0 0.000330180611828 +Ca55 ns55 0 1e-012 +Ca56 ns56 0 1e-012 +Ra55 ns55 0 19693.214347 +Ra56 ns56 0 19693.214347 +Ga55 ns55 0 ns56 0 -0.000389415329596 +Ga56 ns56 0 ns55 0 0.000389415329596 +Ca57 ns57 0 1e-012 +Ca58 ns58 0 1e-012 +Ra57 ns57 0 1688.05455507 +Ra58 ns58 0 1688.05455507 +Ga57 ns57 0 ns58 0 -0.000477398482785 +Ga58 ns58 0 ns57 0 0.000477398482785 +Ca59 ns59 0 1e-012 +Ra59 ns59 0 1285153296.08 +Ca60 ns60 0 1e-012 +Ra60 ns60 0 297889903.174 +Ca61 ns61 0 1e-012 +Ra61 ns61 0 3006167.60729 +Ca62 ns62 0 1e-012 +Ra62 ns62 0 928745.805552 +Ca63 ns63 0 1e-012 +Ra63 ns63 0 642936.910474 +Ca64 ns64 0 1e-012 +Ra64 ns64 0 168091.544894 +Ca65 ns65 0 1e-012 +Ca66 ns66 0 1e-012 +Ra65 ns65 0 4541912.34875 +Ra66 ns66 0 4541912.34875 +Ga65 ns65 0 ns66 0 -1.9368866379e-005 +Ga66 ns66 0 ns65 0 1.9368866379e-005 +Ca67 ns67 0 1e-012 +Ra67 ns67 0 20614.0861881 +Ca68 ns68 0 1e-012 +Ca69 ns69 0 1e-012 +Ra68 ns68 0 147098.94106 +Ra69 ns69 0 147098.94106 +Ga68 ns68 0 ns69 0 -5.3873313541e-005 +Ga69 ns69 0 ns68 0 5.3873313541e-005 +Ca70 ns70 0 1e-012 +Ca71 ns71 0 1e-012 +Ra70 ns70 0 137059.062494 +Ra71 ns71 0 137059.062494 +Ga70 ns70 0 ns71 0 -5.61796182679e-005 +Ga71 ns71 0 ns70 0 5.61796182679e-005 +Ca72 ns72 0 1e-012 +Ca73 ns73 0 1e-012 +Ra72 ns72 0 107286.124839 +Ra73 ns73 0 107286.124839 +Ga72 ns72 0 ns73 0 -6.75905194798e-005 +Ga73 ns73 0 ns72 0 6.75905194798e-005 +Ca74 ns74 0 1e-012 +Ca75 ns75 0 1e-012 +Ra74 ns74 0 40826.9263427 +Ra75 ns75 0 40826.9263427 +Ga74 ns74 0 ns75 0 -0.000199496956253 +Ga75 ns75 0 ns74 0 0.000199496956253 +Ca76 ns76 0 1e-012 +Ca77 ns77 0 1e-012 +Ra76 ns76 0 236317.272026 +Ra77 ns77 0 236317.272026 +Ga76 ns76 0 ns77 0 -0.000212445395998 +Ga77 ns77 0 ns76 0 0.000212445395998 +Ca78 ns78 0 1e-012 +Ca79 ns79 0 1e-012 +Ra78 ns78 0 41263.0408147 +Ra79 ns79 0 41263.0408147 +Ga78 ns78 0 ns79 0 -0.000213710510467 +Ga79 ns79 0 ns78 0 0.000213710510467 +Ca80 ns80 0 1e-012 +Ca81 ns81 0 1e-012 +Ra80 ns80 0 39479.0900285 +Ra81 ns81 0 39479.0900285 +Ga80 ns80 0 ns81 0 -0.000221729151294 +Ga81 ns81 0 ns80 0 0.000221729151294 +Ca82 ns82 0 1e-012 +Ca83 ns83 0 1e-012 +Ra82 ns82 0 30670.8761275 +Ra83 ns83 0 30670.8761275 +Ga82 ns82 0 ns83 0 -0.000330180611828 +Ga83 ns83 0 ns82 0 0.000330180611828 +Ca84 ns84 0 1e-012 +Ca85 ns85 0 1e-012 +Ra84 ns84 0 19693.214347 +Ra85 ns85 0 19693.214347 +Ga84 ns84 0 ns85 0 -0.000389415329596 +Ga85 ns85 0 ns84 0 0.000389415329596 +Ca86 ns86 0 1e-012 +Ca87 ns87 0 1e-012 +Ra86 ns86 0 1688.05455507 +Ra87 ns87 0 1688.05455507 +Ga86 ns86 0 ns87 0 -0.000477398482785 +Ga87 ns87 0 ns86 0 0.000477398482785 +Ca88 ns88 0 1e-012 +Ra88 ns88 0 1285153296.08 +Ca89 ns89 0 1e-012 +Ra89 ns89 0 297889903.174 +Ca90 ns90 0 1e-012 +Ra90 ns90 0 3006167.60729 +Ca91 ns91 0 1e-012 +Ra91 ns91 0 928745.805552 +Ca92 ns92 0 1e-012 +Ra92 ns92 0 642936.910474 +Ca93 ns93 0 1e-012 +Ra93 ns93 0 168091.544894 +Ca94 ns94 0 1e-012 +Ca95 ns95 0 1e-012 +Ra94 ns94 0 4541912.34875 +Ra95 ns95 0 4541912.34875 +Ga94 ns94 0 ns95 0 -1.9368866379e-005 +Ga95 ns95 0 ns94 0 1.9368866379e-005 +Ca96 ns96 0 1e-012 +Ra96 ns96 0 20614.0861881 +Ca97 ns97 0 1e-012 +Ca98 ns98 0 1e-012 +Ra97 ns97 0 147098.94106 +Ra98 ns98 0 147098.94106 +Ga97 ns97 0 ns98 0 -5.3873313541e-005 +Ga98 ns98 0 ns97 0 5.3873313541e-005 +Ca99 ns99 0 1e-012 +Ca100 ns100 0 1e-012 +Ra99 ns99 0 137059.062494 +Ra100 ns100 0 137059.062494 +Ga99 ns99 0 ns100 0 -5.61796182679e-005 +Ga100 ns100 0 ns99 0 5.61796182679e-005 +Ca101 ns101 0 1e-012 +Ca102 ns102 0 1e-012 +Ra101 ns101 0 107286.124839 +Ra102 ns102 0 107286.124839 +Ga101 ns101 0 ns102 0 -6.75905194798e-005 +Ga102 ns102 0 ns101 0 6.75905194798e-005 +Ca103 ns103 0 1e-012 +Ca104 ns104 0 1e-012 +Ra103 ns103 0 40826.9263427 +Ra104 ns104 0 40826.9263427 +Ga103 ns103 0 ns104 0 -0.000199496956253 +Ga104 ns104 0 ns103 0 0.000199496956253 +Ca105 ns105 0 1e-012 +Ca106 ns106 0 1e-012 +Ra105 ns105 0 236317.272026 +Ra106 ns106 0 236317.272026 +Ga105 ns105 0 ns106 0 -0.000212445395998 +Ga106 ns106 0 ns105 0 0.000212445395998 +Ca107 ns107 0 1e-012 +Ca108 ns108 0 1e-012 +Ra107 ns107 0 41263.0408147 +Ra108 ns108 0 41263.0408147 +Ga107 ns107 0 ns108 0 -0.000213710510467 +Ga108 ns108 0 ns107 0 0.000213710510467 +Ca109 ns109 0 1e-012 +Ca110 ns110 0 1e-012 +Ra109 ns109 0 39479.0900285 +Ra110 ns110 0 39479.0900285 +Ga109 ns109 0 ns110 0 -0.000221729151294 +Ga110 ns110 0 ns109 0 0.000221729151294 +Ca111 ns111 0 1e-012 +Ca112 ns112 0 1e-012 +Ra111 ns111 0 30670.8761275 +Ra112 ns112 0 30670.8761275 +Ga111 ns111 0 ns112 0 -0.000330180611828 +Ga112 ns112 0 ns111 0 0.000330180611828 +Ca113 ns113 0 1e-012 +Ca114 ns114 0 1e-012 +Ra113 ns113 0 19693.214347 +Ra114 ns114 0 19693.214347 +Ga113 ns113 0 ns114 0 -0.000389415329596 +Ga114 ns114 0 ns113 0 0.000389415329596 +Ca115 ns115 0 1e-012 +Ca116 ns116 0 1e-012 +Ra115 ns115 0 1688.05455507 +Ra116 ns116 0 1688.05455507 +Ga115 ns115 0 ns116 0 -0.000477398482785 +Ga116 ns116 0 ns115 0 0.000477398482785 +Ca117 ns117 0 1e-012 +Ra117 ns117 0 1285153296.08 +Ca118 ns118 0 1e-012 +Ra118 ns118 0 297889903.174 +Ca119 ns119 0 1e-012 +Ra119 ns119 0 3006167.60729 +Ca120 ns120 0 1e-012 +Ra120 ns120 0 928745.805552 +Ca121 ns121 0 1e-012 +Ra121 ns121 0 642936.910474 +Ca122 ns122 0 1e-012 +Ra122 ns122 0 168091.544894 +Ca123 ns123 0 1e-012 +Ca124 ns124 0 1e-012 +Ra123 ns123 0 4541912.34875 +Ra124 ns124 0 4541912.34875 +Ga123 ns123 0 ns124 0 -1.9368866379e-005 +Ga124 ns124 0 ns123 0 1.9368866379e-005 +Ca125 ns125 0 1e-012 +Ra125 ns125 0 20614.0861881 +Ca126 ns126 0 1e-012 +Ca127 ns127 0 1e-012 +Ra126 ns126 0 147098.94106 +Ra127 ns127 0 147098.94106 +Ga126 ns126 0 ns127 0 -5.3873313541e-005 +Ga127 ns127 0 ns126 0 5.3873313541e-005 +Ca128 ns128 0 1e-012 +Ca129 ns129 0 1e-012 +Ra128 ns128 0 137059.062494 +Ra129 ns129 0 137059.062494 +Ga128 ns128 0 ns129 0 -5.61796182679e-005 +Ga129 ns129 0 ns128 0 5.61796182679e-005 +Ca130 ns130 0 1e-012 +Ca131 ns131 0 1e-012 +Ra130 ns130 0 107286.124839 +Ra131 ns131 0 107286.124839 +Ga130 ns130 0 ns131 0 -6.75905194798e-005 +Ga131 ns131 0 ns130 0 6.75905194798e-005 +Ca132 ns132 0 1e-012 +Ca133 ns133 0 1e-012 +Ra132 ns132 0 40826.9263427 +Ra133 ns133 0 40826.9263427 +Ga132 ns132 0 ns133 0 -0.000199496956253 +Ga133 ns133 0 ns132 0 0.000199496956253 +Ca134 ns134 0 1e-012 +Ca135 ns135 0 1e-012 +Ra134 ns134 0 236317.272026 +Ra135 ns135 0 236317.272026 +Ga134 ns134 0 ns135 0 -0.000212445395998 +Ga135 ns135 0 ns134 0 0.000212445395998 +Ca136 ns136 0 1e-012 +Ca137 ns137 0 1e-012 +Ra136 ns136 0 41263.0408147 +Ra137 ns137 0 41263.0408147 +Ga136 ns136 0 ns137 0 -0.000213710510467 +Ga137 ns137 0 ns136 0 0.000213710510467 +Ca138 ns138 0 1e-012 +Ca139 ns139 0 1e-012 +Ra138 ns138 0 39479.0900285 +Ra139 ns139 0 39479.0900285 +Ga138 ns138 0 ns139 0 -0.000221729151294 +Ga139 ns139 0 ns138 0 0.000221729151294 +Ca140 ns140 0 1e-012 +Ca141 ns141 0 1e-012 +Ra140 ns140 0 30670.8761275 +Ra141 ns141 0 30670.8761275 +Ga140 ns140 0 ns141 0 -0.000330180611828 +Ga141 ns141 0 ns140 0 0.000330180611828 +Ca142 ns142 0 1e-012 +Ca143 ns143 0 1e-012 +Ra142 ns142 0 19693.214347 +Ra143 ns143 0 19693.214347 +Ga142 ns142 0 ns143 0 -0.000389415329596 +Ga143 ns143 0 ns142 0 0.000389415329596 +Ca144 ns144 0 1e-012 +Ca145 ns145 0 1e-012 +Ra144 ns144 0 1688.05455507 +Ra145 ns145 0 1688.05455507 +Ga144 ns144 0 ns145 0 -0.000477398482785 +Ga145 ns145 0 ns144 0 0.000477398482785 +Ca146 ns146 0 1e-012 +Ra146 ns146 0 1285153296.08 +Ca147 ns147 0 1e-012 +Ra147 ns147 0 297889903.174 +Ca148 ns148 0 1e-012 +Ra148 ns148 0 3006167.60729 +Ca149 ns149 0 1e-012 +Ra149 ns149 0 928745.805552 +Ca150 ns150 0 1e-012 +Ra150 ns150 0 642936.910474 +Ca151 ns151 0 1e-012 +Ra151 ns151 0 168091.544894 +Ca152 ns152 0 1e-012 +Ca153 ns153 0 1e-012 +Ra152 ns152 0 4541912.34875 +Ra153 ns153 0 4541912.34875 +Ga152 ns152 0 ns153 0 -1.9368866379e-005 +Ga153 ns153 0 ns152 0 1.9368866379e-005 +Ca154 ns154 0 1e-012 +Ra154 ns154 0 20614.0861881 +Ca155 ns155 0 1e-012 +Ca156 ns156 0 1e-012 +Ra155 ns155 0 147098.94106 +Ra156 ns156 0 147098.94106 +Ga155 ns155 0 ns156 0 -5.3873313541e-005 +Ga156 ns156 0 ns155 0 5.3873313541e-005 +Ca157 ns157 0 1e-012 +Ca158 ns158 0 1e-012 +Ra157 ns157 0 137059.062494 +Ra158 ns158 0 137059.062494 +Ga157 ns157 0 ns158 0 -5.61796182679e-005 +Ga158 ns158 0 ns157 0 5.61796182679e-005 +Ca159 ns159 0 1e-012 +Ca160 ns160 0 1e-012 +Ra159 ns159 0 107286.124839 +Ra160 ns160 0 107286.124839 +Ga159 ns159 0 ns160 0 -6.75905194798e-005 +Ga160 ns160 0 ns159 0 6.75905194798e-005 +Ca161 ns161 0 1e-012 +Ca162 ns162 0 1e-012 +Ra161 ns161 0 40826.9263427 +Ra162 ns162 0 40826.9263427 +Ga161 ns161 0 ns162 0 -0.000199496956253 +Ga162 ns162 0 ns161 0 0.000199496956253 +Ca163 ns163 0 1e-012 +Ca164 ns164 0 1e-012 +Ra163 ns163 0 236317.272026 +Ra164 ns164 0 236317.272026 +Ga163 ns163 0 ns164 0 -0.000212445395998 +Ga164 ns164 0 ns163 0 0.000212445395998 +Ca165 ns165 0 1e-012 +Ca166 ns166 0 1e-012 +Ra165 ns165 0 41263.0408147 +Ra166 ns166 0 41263.0408147 +Ga165 ns165 0 ns166 0 -0.000213710510467 +Ga166 ns166 0 ns165 0 0.000213710510467 +Ca167 ns167 0 1e-012 +Ca168 ns168 0 1e-012 +Ra167 ns167 0 39479.0900285 +Ra168 ns168 0 39479.0900285 +Ga167 ns167 0 ns168 0 -0.000221729151294 +Ga168 ns168 0 ns167 0 0.000221729151294 +Ca169 ns169 0 1e-012 +Ca170 ns170 0 1e-012 +Ra169 ns169 0 30670.8761275 +Ra170 ns170 0 30670.8761275 +Ga169 ns169 0 ns170 0 -0.000330180611828 +Ga170 ns170 0 ns169 0 0.000330180611828 +Ca171 ns171 0 1e-012 +Ca172 ns172 0 1e-012 +Ra171 ns171 0 19693.214347 +Ra172 ns172 0 19693.214347 +Ga171 ns171 0 ns172 0 -0.000389415329596 +Ga172 ns172 0 ns171 0 0.000389415329596 +Ca173 ns173 0 1e-012 +Ca174 ns174 0 1e-012 +Ra173 ns173 0 1688.05455507 +Ra174 ns174 0 1688.05455507 +Ga173 ns173 0 ns174 0 -0.000477398482785 +Ga174 ns174 0 ns173 0 0.000477398482785 + +Gb1_1 ns1 0 ni1 0 7.78117290016e-010 +Gb2_1 ns2 0 ni1 0 3.35694492947e-009 +Gb3_1 ns3 0 ni1 0 3.32649449609e-007 +Gb4_1 ns4 0 ni1 0 1.07672087887e-006 +Gb5_1 ns5 0 ni1 0 1.55536256157e-006 +Gb6_1 ns6 0 ni1 0 5.94913920643e-006 +Gb7_1 ns7 0 ni1 0 1.93713691338e-005 +Gb9_1 ns9 0 ni1 0 4.85105180445e-005 +Gb10_1 ns10 0 ni1 0 5.47311553705e-005 +Gb12_1 ns12 0 ni1 0 5.71271760493e-005 +Gb14_1 ns14 0 ni1 0 6.88758863379e-005 +Gb16_1 ns16 0 ni1 0 0.000202504211944 +Gb18_1 ns18 0 ni1 0 0.000212529683221 +Gb20_1 ns20 0 ni1 0 0.000216458731502 +Gb22_1 ns22 0 ni1 0 0.000224622780889 +Gb24_1 ns24 0 ni1 0 0.000333400168455 +Gb26_1 ns26 0 ni1 0 0.000396036789299 +Gb28_1 ns28 0 ni1 0 0.000977121266886 +Gb30_2 ns30 0 ni2 0 7.78117290016e-010 +Gb31_2 ns31 0 ni2 0 3.35694492947e-009 +Gb32_2 ns32 0 ni2 0 3.32649449609e-007 +Gb33_2 ns33 0 ni2 0 1.07672087887e-006 +Gb34_2 ns34 0 ni2 0 1.55536256157e-006 +Gb35_2 ns35 0 ni2 0 5.94913920643e-006 +Gb36_2 ns36 0 ni2 0 1.93713691338e-005 +Gb38_2 ns38 0 ni2 0 4.85105180445e-005 +Gb39_2 ns39 0 ni2 0 5.47311553705e-005 +Gb41_2 ns41 0 ni2 0 5.71271760493e-005 +Gb43_2 ns43 0 ni2 0 6.88758863379e-005 +Gb45_2 ns45 0 ni2 0 0.000202504211944 +Gb47_2 ns47 0 ni2 0 0.000212529683221 +Gb49_2 ns49 0 ni2 0 0.000216458731502 +Gb51_2 ns51 0 ni2 0 0.000224622780889 +Gb53_2 ns53 0 ni2 0 0.000333400168455 +Gb55_2 ns55 0 ni2 0 0.000396036789299 +Gb57_2 ns57 0 ni2 0 0.000977121266886 +Gb59_3 ns59 0 ni3 0 7.78117290016e-010 +Gb60_3 ns60 0 ni3 0 3.35694492947e-009 +Gb61_3 ns61 0 ni3 0 3.32649449609e-007 +Gb62_3 ns62 0 ni3 0 1.07672087887e-006 +Gb63_3 ns63 0 ni3 0 1.55536256157e-006 +Gb64_3 ns64 0 ni3 0 5.94913920643e-006 +Gb65_3 ns65 0 ni3 0 1.93713691338e-005 +Gb67_3 ns67 0 ni3 0 4.85105180445e-005 +Gb68_3 ns68 0 ni3 0 5.47311553705e-005 +Gb70_3 ns70 0 ni3 0 5.71271760493e-005 +Gb72_3 ns72 0 ni3 0 6.88758863379e-005 +Gb74_3 ns74 0 ni3 0 0.000202504211944 +Gb76_3 ns76 0 ni3 0 0.000212529683221 +Gb78_3 ns78 0 ni3 0 0.000216458731502 +Gb80_3 ns80 0 ni3 0 0.000224622780889 +Gb82_3 ns82 0 ni3 0 0.000333400168455 +Gb84_3 ns84 0 ni3 0 0.000396036789299 +Gb86_3 ns86 0 ni3 0 0.000977121266886 +Gb88_4 ns88 0 ni4 0 7.78117290016e-010 +Gb89_4 ns89 0 ni4 0 3.35694492947e-009 +Gb90_4 ns90 0 ni4 0 3.32649449609e-007 +Gb91_4 ns91 0 ni4 0 1.07672087887e-006 +Gb92_4 ns92 0 ni4 0 1.55536256157e-006 +Gb93_4 ns93 0 ni4 0 5.94913920643e-006 +Gb94_4 ns94 0 ni4 0 1.93713691338e-005 +Gb96_4 ns96 0 ni4 0 4.85105180445e-005 +Gb97_4 ns97 0 ni4 0 5.47311553705e-005 +Gb99_4 ns99 0 ni4 0 5.71271760493e-005 +Gb101_4 ns101 0 ni4 0 6.88758863379e-005 +Gb103_4 ns103 0 ni4 0 0.000202504211944 +Gb105_4 ns105 0 ni4 0 0.000212529683221 +Gb107_4 ns107 0 ni4 0 0.000216458731502 +Gb109_4 ns109 0 ni4 0 0.000224622780889 +Gb111_4 ns111 0 ni4 0 0.000333400168455 +Gb113_4 ns113 0 ni4 0 0.000396036789299 +Gb115_4 ns115 0 ni4 0 0.000977121266886 +Gb117_5 ns117 0 ni5 0 7.78117290016e-010 +Gb118_5 ns118 0 ni5 0 3.35694492947e-009 +Gb119_5 ns119 0 ni5 0 3.32649449609e-007 +Gb120_5 ns120 0 ni5 0 1.07672087887e-006 +Gb121_5 ns121 0 ni5 0 1.55536256157e-006 +Gb122_5 ns122 0 ni5 0 5.94913920643e-006 +Gb123_5 ns123 0 ni5 0 1.93713691338e-005 +Gb125_5 ns125 0 ni5 0 4.85105180445e-005 +Gb126_5 ns126 0 ni5 0 5.47311553705e-005 +Gb128_5 ns128 0 ni5 0 5.71271760493e-005 +Gb130_5 ns130 0 ni5 0 6.88758863379e-005 +Gb132_5 ns132 0 ni5 0 0.000202504211944 +Gb134_5 ns134 0 ni5 0 0.000212529683221 +Gb136_5 ns136 0 ni5 0 0.000216458731502 +Gb138_5 ns138 0 ni5 0 0.000224622780889 +Gb140_5 ns140 0 ni5 0 0.000333400168455 +Gb142_5 ns142 0 ni5 0 0.000396036789299 +Gb144_5 ns144 0 ni5 0 0.000977121266886 +Gb146_6 ns146 0 ni6 0 7.78117290016e-010 +Gb147_6 ns147 0 ni6 0 3.35694492947e-009 +Gb148_6 ns148 0 ni6 0 3.32649449609e-007 +Gb149_6 ns149 0 ni6 0 1.07672087887e-006 +Gb150_6 ns150 0 ni6 0 1.55536256157e-006 +Gb151_6 ns151 0 ni6 0 5.94913920643e-006 +Gb152_6 ns152 0 ni6 0 1.93713691338e-005 +Gb154_6 ns154 0 ni6 0 4.85105180445e-005 +Gb155_6 ns155 0 ni6 0 5.47311553705e-005 +Gb157_6 ns157 0 ni6 0 5.71271760493e-005 +Gb159_6 ns159 0 ni6 0 6.88758863379e-005 +Gb161_6 ns161 0 ni6 0 0.000202504211944 +Gb163_6 ns163 0 ni6 0 0.000212529683221 +Gb165_6 ns165 0 ni6 0 0.000216458731502 +Gb167_6 ns167 0 ni6 0 0.000224622780889 +Gb169_6 ns169 0 ni6 0 0.000333400168455 +Gb171_6 ns171 0 ni6 0 0.000396036789299 +Gb173_6 ns173 0 ni6 0 0.000977121266886 + +Gc1_1 0 n2 ns1 0 0.00652604610017 +Gc1_2 0 n2 ns2 0 6.74972091513e-005 +Gc1_3 0 n2 ns3 0 0.000463780157415 +Gc1_4 0 n2 ns4 0 0.00665592602148 +Gc1_5 0 n2 ns5 0 0.00597422665427 +Gc1_6 0 n2 ns6 0 0.000238216506919 +Gc1_7 0 n2 ns7 0 9.38407853956e-008 +Gc1_8 0 n2 ns8 0 1.70356953976e-007 +Gc1_9 0 n2 ns9 0 7.48433548073e-005 +Gc1_10 0 n2 ns10 0 0.00213463538464 +Gc1_11 0 n2 ns11 0 -9.04645496368e-005 +Gc1_12 0 n2 ns12 0 0.000152958771264 +Gc1_13 0 n2 ns13 0 0.000112636866754 +Gc1_14 0 n2 ns14 0 0.000613829284801 +Gc1_15 0 n2 ns15 0 -6.77304309732e-005 +Gc1_16 0 n2 ns16 0 0.00283873212476 +Gc1_17 0 n2 ns17 0 -0.00121958569113 +Gc1_18 0 n2 ns18 0 -3.77881299338e-008 +Gc1_19 0 n2 ns19 0 1.08715699138e-008 +Gc1_20 0 n2 ns20 0 0.000437051448141 +Gc1_21 0 n2 ns21 0 0.000211196920954 +Gc1_22 0 n2 ns22 0 7.43416049203e-005 +Gc1_23 0 n2 ns23 0 -8.39313682166e-005 +Gc1_24 0 n2 ns24 0 0.00301072015102 +Gc1_25 0 n2 ns25 0 -0.000757143076768 +Gc1_26 0 n2 ns26 0 -0.000490038208991 +Gc1_27 0 n2 ns27 0 0.000119819723199 +Gc1_28 0 n2 ns28 0 -0.00787501442058 +Gc1_29 0 n2 ns29 0 0.0235070379678 +Gc1_30 0 n2 ns30 0 0.00661802803887 +Gc1_31 0 n2 ns31 0 -0.00010524283528 +Gc1_32 0 n2 ns32 0 -0.000265920832537 +Gc1_33 0 n2 ns33 0 -0.00279512402419 +Gc1_34 0 n2 ns34 0 -0.00345713379419 +Gc1_35 0 n2 ns35 0 -0.000108864469725 +Gc1_36 0 n2 ns36 0 6.16413348484e-008 +Gc1_37 0 n2 ns37 0 8.18325005832e-008 +Gc1_38 0 n2 ns38 0 -6.04248122052e-005 +Gc1_39 0 n2 ns39 0 -0.00119597134334 +Gc1_40 0 n2 ns40 0 -7.46702008187e-005 +Gc1_41 0 n2 ns41 0 0.000504070194951 +Gc1_42 0 n2 ns42 0 7.84762763197e-005 +Gc1_43 0 n2 ns43 0 0.000767843909705 +Gc1_44 0 n2 ns44 0 -0.000101181380853 +Gc1_45 0 n2 ns45 0 0.000252865355021 +Gc1_46 0 n2 ns46 0 0.000199064401902 +Gc1_47 0 n2 ns47 0 -2.3302289232e-007 +Gc1_48 0 n2 ns48 0 3.52960693519e-007 +Gc1_49 0 n2 ns49 0 -0.00104196142033 +Gc1_50 0 n2 ns50 0 3.07108384831e-005 +Gc1_51 0 n2 ns51 0 0.000209120865076 +Gc1_52 0 n2 ns52 0 -1.59669029914e-005 +Gc1_53 0 n2 ns53 0 -0.000658330561745 +Gc1_54 0 n2 ns54 0 3.08369066864e-005 +Gc1_55 0 n2 ns55 0 0.000489681312264 +Gc1_56 0 n2 ns56 0 -8.82070762059e-005 +Gc1_57 0 n2 ns57 0 -0.000130479869557 +Gc1_58 0 n2 ns58 0 -0.0004664640974 +Gc1_59 0 n2 ns59 0 0.00662610346635 +Gc1_60 0 n2 ns60 0 -0.000115252986696 +Gc1_61 0 n2 ns61 0 -0.000301231822972 +Gc1_62 0 n2 ns62 0 -0.00374609834711 +Gc1_63 0 n2 ns63 0 -0.00248811591833 +Gc1_64 0 n2 ns64 0 -9.03055126067e-005 +Gc1_65 0 n2 ns65 0 5.31991336967e-008 +Gc1_66 0 n2 ns66 0 7.5956159096e-008 +Gc1_67 0 n2 ns67 0 -4.97171481188e-005 +Gc1_68 0 n2 ns68 0 -0.000510493820525 +Gc1_69 0 n2 ns69 0 0.000133928791602 +Gc1_70 0 n2 ns70 0 -0.000486488813697 +Gc1_71 0 n2 ns71 0 -0.000141558882655 +Gc1_72 0 n2 ns72 0 0.00102140449586 +Gc1_73 0 n2 ns73 0 -9.59047853714e-005 +Gc1_74 0 n2 ns74 0 0.000371341032035 +Gc1_75 0 n2 ns75 0 3.91892009472e-005 +Gc1_76 0 n2 ns76 0 9.61950904937e-008 +Gc1_77 0 n2 ns77 0 2.93906936167e-007 +Gc1_78 0 n2 ns78 0 -0.000508664246891 +Gc1_79 0 n2 ns79 0 -8.35450022278e-005 +Gc1_80 0 n2 ns80 0 -0.000261153946191 +Gc1_81 0 n2 ns81 0 0.00024916222978 +Gc1_82 0 n2 ns82 0 -0.000715957537469 +Gc1_83 0 n2 ns83 0 0.000180228811394 +Gc1_84 0 n2 ns84 0 0.0003487850666 +Gc1_85 0 n2 ns85 0 -0.000101737522783 +Gc1_86 0 n2 ns86 0 0.000186608545537 +Gc1_87 0 n2 ns87 0 -0.000450380162492 +Gc1_88 0 n2 ns88 0 -0.00704687528917 +Gc1_89 0 n2 ns89 0 0.000391522095827 +Gc1_90 0 n2 ns90 0 -0.000593657991312 +Gc1_91 0 n2 ns91 0 -0.00639266246364 +Gc1_92 0 n2 ns92 0 -0.00610238085021 +Gc1_93 0 n2 ns93 0 -0.000195573519064 +Gc1_94 0 n2 ns94 0 2.82371422839e-007 +Gc1_95 0 n2 ns95 0 -4.35205290618e-008 +Gc1_96 0 n2 ns96 0 -0.000180779274643 +Gc1_97 0 n2 ns97 0 -0.00196725447351 +Gc1_98 0 n2 ns98 0 4.45046970237e-005 +Gc1_99 0 n2 ns99 0 -7.82408311582e-005 +Gc1_100 0 n2 ns100 0 -9.3207750496e-005 +Gc1_101 0 n2 ns101 0 -0.000621934928815 +Gc1_102 0 n2 ns102 0 6.66034524991e-005 +Gc1_103 0 n2 ns103 0 -0.00199038104766 +Gc1_104 0 n2 ns104 0 0.000794776902302 +Gc1_105 0 n2 ns105 0 -5.57035505892e-009 +Gc1_106 0 n2 ns106 0 -5.8388557702e-007 +Gc1_107 0 n2 ns107 0 -0.000110427337361 +Gc1_108 0 n2 ns108 0 -0.000198850025973 +Gc1_109 0 n2 ns109 0 -2.87393008819e-005 +Gc1_110 0 n2 ns110 0 9.5884151641e-005 +Gc1_111 0 n2 ns111 0 -0.000736966224187 +Gc1_112 0 n2 ns112 0 0.000150162853557 +Gc1_113 0 n2 ns113 0 -0.000105821962761 +Gc1_114 0 n2 ns114 0 -8.36801987659e-005 +Gc1_115 0 n2 ns115 0 -0.000663346993486 +Gc1_116 0 n2 ns116 0 -0.00282303324068 +Gc1_117 0 n2 ns117 0 -0.00659070211335 +Gc1_118 0 n2 ns118 0 8.30246105895e-005 +Gc1_119 0 n2 ns119 0 0.000259801074922 +Gc1_120 0 n2 ns120 0 0.00280772067811 +Gc1_121 0 n2 ns121 0 0.00344063007678 +Gc1_122 0 n2 ns122 0 0.000108319755921 +Gc1_123 0 n2 ns123 0 -6.66385417221e-008 +Gc1_124 0 n2 ns124 0 -1.98459656427e-008 +Gc1_125 0 n2 ns125 0 8.76369467826e-005 +Gc1_126 0 n2 ns126 0 0.00102426186005 +Gc1_127 0 n2 ns127 0 5.6953582118e-005 +Gc1_128 0 n2 ns128 0 -0.000447833170875 +Gc1_129 0 n2 ns129 0 -6.38148205408e-005 +Gc1_130 0 n2 ns130 0 -0.000765777825425 +Gc1_131 0 n2 ns131 0 0.000103569091954 +Gc1_132 0 n2 ns132 0 -0.000613075903704 +Gc1_133 0 n2 ns133 0 1.00269638656e-005 +Gc1_134 0 n2 ns134 0 5.17273115404e-007 +Gc1_135 0 n2 ns135 0 4.04990129985e-007 +Gc1_136 0 n2 ns136 0 0.000755060380164 +Gc1_137 0 n2 ns137 0 -0.000220642412058 +Gc1_138 0 n2 ns138 0 -4.53290518522e-005 +Gc1_139 0 n2 ns139 0 8.27595384036e-005 +Gc1_140 0 n2 ns140 0 -0.000428248031053 +Gc1_141 0 n2 ns141 0 0.000196106448169 +Gc1_142 0 n2 ns142 0 -0.000129100268852 +Gc1_143 0 n2 ns143 0 3.90664714184e-005 +Gc1_144 0 n2 ns144 0 -0.000513811126051 +Gc1_145 0 n2 ns145 0 -0.000782827205865 +Gc1_146 0 n2 ns146 0 -0.00661642634505 +Gc1_147 0 n2 ns147 0 0.00011157681212 +Gc1_148 0 n2 ns148 0 0.00029255648426 +Gc1_149 0 n2 ns149 0 0.00376511018482 +Gc1_150 0 n2 ns150 0 0.00246567550713 +Gc1_151 0 n2 ns151 0 9.12936517179e-005 +Gc1_152 0 n2 ns152 0 -4.90912706614e-008 +Gc1_153 0 n2 ns153 0 -1.12398330621e-008 +Gc1_154 0 n2 ns154 0 7.98493562234e-005 +Gc1_155 0 n2 ns155 0 0.000472942790796 +Gc1_156 0 n2 ns156 0 -0.000129416784809 +Gc1_157 0 n2 ns157 0 0.000441596592109 +Gc1_158 0 n2 ns158 0 0.000136637905725 +Gc1_159 0 n2 ns159 0 -0.000988379482799 +Gc1_160 0 n2 ns160 0 9.72641849518e-005 +Gc1_161 0 n2 ns161 0 -0.000805046886754 +Gc1_162 0 n2 ns162 0 0.00017563321877 +Gc1_163 0 n2 ns163 0 4.73184264491e-007 +Gc1_164 0 n2 ns164 0 2.92720709507e-007 +Gc1_165 0 n2 ns165 0 0.000384537439117 +Gc1_166 0 n2 ns166 0 -0.00012655372499 +Gc1_167 0 n2 ns167 0 0.000279883498412 +Gc1_168 0 n2 ns168 0 -0.000115960999323 +Gc1_169 0 n2 ns169 0 -0.000284175764339 +Gc1_170 0 n2 ns170 0 9.64714051647e-005 +Gc1_171 0 n2 ns171 0 -0.000117137343195 +Gc1_172 0 n2 ns172 0 2.78958813402e-005 +Gc1_173 0 n2 ns173 0 -0.00101260891914 +Gc1_174 0 n2 ns174 0 -0.00110267088361 +Gd1_1 0 n2 ni1 0 -0.00395766865932 +Gd1_2 0 n2 ni2 0 3.80255674239e-005 +Gd1_3 0 n2 ni3 0 0.00022164283018 +Gd1_4 0 n2 ni4 0 -7.18230546114e-005 +Gd1_5 0 n2 ni5 0 -4.99163208033e-005 +Gd1_6 0 n2 ni6 0 -0.000252919278087 +Gc2_1 0 n4 ns1 0 0.00663631389159 +Gc2_2 0 n4 ns2 0 -0.000124236985783 +Gc2_3 0 n4 ns3 0 -0.000267236436629 +Gc2_4 0 n4 ns4 0 -0.00278876905629 +Gc2_5 0 n4 ns5 0 -0.00346294203828 +Gc2_6 0 n4 ns6 0 -0.000107110592714 +Gc2_7 0 n4 ns7 0 7.42853403054e-008 +Gc2_8 0 n4 ns8 0 8.37471627192e-008 +Gc2_9 0 n4 ns9 0 -6.05237800917e-005 +Gc2_10 0 n4 ns10 0 -0.00119596350847 +Gc2_11 0 n4 ns11 0 -7.43002519748e-005 +Gc2_12 0 n4 ns12 0 0.000504206035645 +Gc2_13 0 n4 ns13 0 7.7751211696e-005 +Gc2_14 0 n4 ns14 0 0.000767830595101 +Gc2_15 0 n4 ns15 0 -0.000100971185141 +Gc2_16 0 n4 ns16 0 0.00025321011851 +Gc2_17 0 n4 ns17 0 0.000199889929877 +Gc2_18 0 n4 ns18 0 -2.11830723877e-007 +Gc2_19 0 n4 ns19 0 3.57532244319e-007 +Gc2_20 0 n4 ns20 0 -0.00104388597836 +Gc2_21 0 n4 ns21 0 3.0789885721e-005 +Gc2_22 0 n4 ns22 0 0.000210249182296 +Gc2_23 0 n4 ns23 0 -1.70299960946e-005 +Gc2_24 0 n4 ns24 0 -0.000657641433668 +Gc2_25 0 n4 ns25 0 3.12181456202e-005 +Gc2_26 0 n4 ns26 0 0.000485959935415 +Gc2_27 0 n4 ns27 0 -8.69400031383e-005 +Gc2_28 0 n4 ns28 0 -9.64322069583e-005 +Gc2_29 0 n4 ns29 0 -0.000450979624157 +Gc2_30 0 n4 ns30 0 0.00656540791323 +Gc2_31 0 n4 ns31 0 2.65121081965e-005 +Gc2_32 0 n4 ns32 0 0.000426053930503 +Gc2_33 0 n4 ns33 0 0.00629198980342 +Gc2_34 0 n4 ns34 0 0.00639762310463 +Gc2_35 0 n4 ns35 0 0.000234800196967 +Gc2_36 0 n4 ns36 0 1.36941846924e-007 +Gc2_37 0 n4 ns37 0 -2.32380958187e-008 +Gc2_38 0 n4 ns38 0 9.2150883802e-005 +Gc2_39 0 n4 ns39 0 0.000635826592611 +Gc2_40 0 n4 ns40 0 0.000123388351957 +Gc2_41 0 n4 ns41 0 0.00145165212074 +Gc2_42 0 n4 ns42 0 -0.00011053976102 +Gc2_43 0 n4 ns43 0 0.000986811589917 +Gc2_44 0 n4 ns44 0 -0.000154543626345 +Gc2_45 0 n4 ns45 0 7.43684998757e-006 +Gc2_46 0 n4 ns46 0 -2.43020567731e-005 +Gc2_47 0 n4 ns47 0 -1.25176966066e-006 +Gc2_48 0 n4 ns48 0 -9.64172285018e-007 +Gc2_49 0 n4 ns49 0 0.00191081236233 +Gc2_50 0 n4 ns50 0 -0.00102170148034 +Gc2_51 0 n4 ns51 0 0.000858965629622 +Gc2_52 0 n4 ns52 0 -0.000392187686949 +Gc2_53 0 n4 ns53 0 0.000169535422559 +Gc2_54 0 n4 ns54 0 4.4006984393e-005 +Gc2_55 0 n4 ns55 0 0.00383141005845 +Gc2_56 0 n4 ns56 0 -0.00172613899496 +Gc2_57 0 n4 ns57 0 -0.00308160861183 +Gc2_58 0 n4 ns58 0 0.028054625283 +Gc2_59 0 n4 ns59 0 0.00659182730071 +Gc2_60 0 n4 ns60 0 -8.41706727077e-005 +Gc2_61 0 n4 ns61 0 -0.000276145775896 +Gc2_62 0 n4 ns62 0 -0.00328964879064 +Gc2_63 0 n4 ns63 0 -0.00299507542742 +Gc2_64 0 n4 ns64 0 -6.55401964338e-005 +Gc2_65 0 n4 ns65 0 9.17077186153e-008 +Gc2_66 0 n4 ns66 0 6.80563423924e-008 +Gc2_67 0 n4 ns67 0 -5.2454788118e-005 +Gc2_68 0 n4 ns68 0 0.00027707644733 +Gc2_69 0 n4 ns69 0 -3.98626240095e-005 +Gc2_70 0 n4 ns70 0 -0.00148851110953 +Gc2_71 0 n4 ns71 0 7.14979248008e-005 +Gc2_72 0 n4 ns72 0 0.00129900013818 +Gc2_73 0 n4 ns73 0 -0.000150436342379 +Gc2_74 0 n4 ns74 0 8.61813049385e-006 +Gc2_75 0 n4 ns75 0 5.25004744177e-005 +Gc2_76 0 n4 ns76 0 5.69816491782e-007 +Gc2_77 0 n4 ns77 0 2.55819385935e-007 +Gc2_78 0 n4 ns78 0 0.000761505937067 +Gc2_79 0 n4 ns79 0 -0.000418021674996 +Gc2_80 0 n4 ns80 0 -0.001148448039 +Gc2_81 0 n4 ns81 0 0.000608143082698 +Gc2_82 0 n4 ns82 0 9.80516588522e-005 +Gc2_83 0 n4 ns83 0 -8.11489764302e-005 +Gc2_84 0 n4 ns84 0 -0.000933290609673 +Gc2_85 0 n4 ns85 0 0.000488052317918 +Gc2_86 0 n4 ns86 0 0.00141718194325 +Gc2_87 0 n4 ns87 0 1.87151285369e-005 +Gc2_88 0 n4 ns88 0 -0.00660474428912 +Gc2_89 0 n4 ns89 0 9.19178312334e-005 +Gc2_90 0 n4 ns90 0 0.000264509015646 +Gc2_91 0 n4 ns91 0 0.00279791206484 +Gc2_92 0 n4 ns92 0 0.00345481662424 +Gc2_93 0 n4 ns93 0 0.000104925861193 +Gc2_94 0 n4 ns94 0 -7.76794845897e-008 +Gc2_95 0 n4 ns95 0 -2.89088357905e-008 +Gc2_96 0 n4 ns96 0 9.15727084832e-005 +Gc2_97 0 n4 ns97 0 0.00108131848488 +Gc2_98 0 n4 ns98 0 5.68573425475e-005 +Gc2_99 0 n4 ns99 0 -0.000406742347819 +Gc2_100 0 n4 ns100 0 -5.81160694571e-005 +Gc2_101 0 n4 ns101 0 -0.000802910473006 +Gc2_102 0 n4 ns102 0 0.000105075103523 +Gc2_103 0 n4 ns103 0 -0.000216874611747 +Gc2_104 0 n4 ns104 0 -9.63465562888e-005 +Gc2_105 0 n4 ns105 0 7.16194581023e-007 +Gc2_106 0 n4 ns106 0 3.96351153086e-007 +Gc2_107 0 n4 ns107 0 0.00040967689789 +Gc2_108 0 n4 ns108 0 -6.48394892954e-005 +Gc2_109 0 n4 ns109 0 -9.8072665831e-005 +Gc2_110 0 n4 ns110 0 9.71236216131e-005 +Gc2_111 0 n4 ns111 0 0.000156401144214 +Gc2_112 0 n4 ns112 0 5.93982998703e-006 +Gc2_113 0 n4 ns113 0 -0.000733898159536 +Gc2_114 0 n4 ns114 0 0.000132614768872 +Gc2_115 0 n4 ns115 0 -0.00170700691 +Gc2_116 0 n4 ns116 0 -0.00153918582531 +Gc2_117 0 n4 ns117 0 -0.00704815528278 +Gc2_118 0 n4 ns118 0 0.000383627711254 +Gc2_119 0 n4 ns119 0 -0.000551142310251 +Gc2_120 0 n4 ns120 0 -0.00600872006899 +Gc2_121 0 n4 ns121 0 -0.00654713189587 +Gc2_122 0 n4 ns122 0 -0.000182862619326 +Gc2_123 0 n4 ns123 0 3.06925763163e-007 +Gc2_124 0 n4 ns124 0 -8.46216863772e-009 +Gc2_125 0 n4 ns125 0 -0.000172823243768 +Gc2_126 0 n4 ns126 0 -0.000560148110878 +Gc2_127 0 n4 ns127 0 -0.000136870641892 +Gc2_128 0 n4 ns128 0 -0.00130372012149 +Gc2_129 0 n4 ns129 0 0.000104289743026 +Gc2_130 0 n4 ns130 0 -0.000961082847116 +Gc2_131 0 n4 ns131 0 0.000150692464801 +Gc2_132 0 n4 ns132 0 -5.50439872812e-005 +Gc2_133 0 n4 ns133 0 -2.36250484426e-005 +Gc2_134 0 n4 ns134 0 6.9010655335e-007 +Gc2_135 0 n4 ns135 0 -2.4606938044e-007 +Gc2_136 0 n4 ns136 0 -0.00140271952685 +Gc2_137 0 n4 ns137 0 0.00080257281374 +Gc2_138 0 n4 ns138 0 -0.000509460238398 +Gc2_139 0 n4 ns139 0 0.000300191238121 +Gc2_140 0 n4 ns140 0 9.54378788408e-005 +Gc2_141 0 n4 ns141 0 -8.81719990716e-006 +Gc2_142 0 n4 ns142 0 -0.00172454610834 +Gc2_143 0 n4 ns143 0 0.000792612482098 +Gc2_144 0 n4 ns144 0 -0.00465029422493 +Gc2_145 0 n4 ns145 0 -0.00701560126073 +Gc2_146 0 n4 ns146 0 -0.0065888769746 +Gc2_147 0 n4 ns147 0 8.71572232935e-005 +Gc2_148 0 n4 ns148 0 0.000267646768324 +Gc2_149 0 n4 ns149 0 0.00330895654398 +Gc2_150 0 n4 ns150 0 0.00297039352472 +Gc2_151 0 n4 ns151 0 6.82119757842e-005 +Gc2_152 0 n4 ns152 0 -9.66201705606e-008 +Gc2_153 0 n4 ns153 0 -1.32560605243e-008 +Gc2_154 0 n4 ns154 0 7.69805798304e-005 +Gc2_155 0 n4 ns155 0 -0.000265565024165 +Gc2_156 0 n4 ns156 0 1.67660245935e-005 +Gc2_157 0 n4 ns157 0 0.00131614614208 +Gc2_158 0 n4 ns158 0 -4.64307919513e-005 +Gc2_159 0 n4 ns159 0 -0.00125860482189 +Gc2_160 0 n4 ns160 0 0.0001489431916 +Gc2_161 0 n4 ns161 0 -0.000101731889174 +Gc2_162 0 n4 ns162 0 -3.78196775893e-005 +Gc2_163 0 n4 ns163 0 3.2438770642e-007 +Gc2_164 0 n4 ns164 0 6.36332106542e-007 +Gc2_165 0 n4 ns165 0 -0.000632804714665 +Gc2_166 0 n4 ns166 0 0.000235636781254 +Gc2_167 0 n4 ns167 0 0.000916245425747 +Gc2_168 0 n4 ns168 0 -0.000367579947512 +Gc2_169 0 n4 ns169 0 6.96557037125e-005 +Gc2_170 0 n4 ns170 0 -2.20192242459e-005 +Gc2_171 0 n4 ns171 0 -0.000677566727264 +Gc2_172 0 n4 ns172 0 0.000273601999155 +Gc2_173 0 n4 ns173 0 -0.00184915450028 +Gc2_174 0 n4 ns174 0 -0.00148725247567 +Gd2_1 0 n4 ni1 0 5.79697469289e-005 +Gd2_2 0 n4 ni2 0 -0.0010844522476 +Gd2_3 0 n4 ni3 0 0.000635702354977 +Gd2_4 0 n4 ni4 0 -0.000613871752178 +Gd2_5 0 n4 ni5 0 -0.0020129708137 +Gd2_6 0 n4 ni6 0 -0.000829667592475 +Gc3_1 0 n6 ns1 0 0.00661324612755 +Gc3_2 0 n6 ns2 0 -0.000103378337148 +Gc3_3 0 n6 ns3 0 -0.000302365174583 +Gc3_4 0 n6 ns4 0 -0.00374111349754 +Gc3_5 0 n6 ns5 0 -0.00249228568949 +Gc3_6 0 n6 ns6 0 -8.89273562853e-005 +Gc3_7 0 n6 ns7 0 6.34245111847e-008 +Gc3_8 0 n6 ns8 0 7.20630897883e-008 +Gc3_9 0 n6 ns9 0 -4.98705986663e-005 +Gc3_10 0 n6 ns10 0 -0.00051072238698 +Gc3_11 0 n6 ns11 0 0.000134033167538 +Gc3_12 0 n6 ns12 0 -0.000485892463389 +Gc3_13 0 n6 ns13 0 -0.000141780488118 +Gc3_14 0 n6 ns14 0 0.00102110957711 +Gc3_15 0 n6 ns15 0 -9.58870114544e-005 +Gc3_16 0 n6 ns16 0 0.000371348092793 +Gc3_17 0 n6 ns17 0 3.9880267467e-005 +Gc3_18 0 n6 ns18 0 1.19530114643e-007 +Gc3_19 0 n6 ns19 0 2.88793441257e-007 +Gc3_20 0 n6 ns20 0 -0.000509878259685 +Gc3_21 0 n6 ns21 0 -8.38389236862e-005 +Gc3_22 0 n6 ns22 0 -0.000260221389087 +Gc3_23 0 n6 ns23 0 0.000248697965803 +Gc3_24 0 n6 ns24 0 -0.000715402939534 +Gc3_25 0 n6 ns25 0 0.000180426103595 +Gc3_26 0 n6 ns26 0 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0 0.000697456264637 +Gc3_79 0 n6 ns79 0 -0.000231649915944 +Gc3_80 0 n6 ns80 0 0.00161709907782 +Gc3_81 0 n6 ns81 0 -0.00110613296229 +Gc3_82 0 n6 ns82 0 5.44735551211e-005 +Gc3_83 0 n6 ns83 0 -0.000126083335599 +Gc3_84 0 n6 ns84 0 0.00290747789646 +Gc3_85 0 n6 ns85 0 -0.00121651254225 +Gc3_86 0 n6 ns86 0 0.00584380708058 +Gc3_87 0 n6 ns87 0 0.0357766041371 +Gc3_88 0 n6 ns88 0 -0.00658537710212 +Gc3_89 0 n6 ns89 0 7.46972595542e-005 +Gc3_90 0 n6 ns90 0 0.000299806856233 +Gc3_91 0 n6 ns91 0 0.00374929605472 +Gc3_92 0 n6 ns92 0 0.00248437343673 +Gc3_93 0 n6 ns93 0 8.70492119978e-005 +Gc3_94 0 n6 ns94 0 -6.38771618613e-008 +Gc3_95 0 n6 ns95 0 -2.31345617361e-008 +Gc3_96 0 n6 ns96 0 8.06982251874e-005 +Gc3_97 0 n6 ns97 0 0.000459075526698 +Gc3_98 0 n6 ns98 0 -0.000135014750624 +Gc3_99 0 n6 ns99 0 0.000418487624918 +Gc3_100 0 n6 ns100 0 0.000141467708742 +Gc3_101 0 n6 ns101 0 -0.00106798221041 +Gc3_102 0 n6 ns102 0 9.78236658217e-005 +Gc3_103 0 n6 ns103 0 -0.000294287610616 +Gc3_104 0 n6 ns104 0 1.60148375444e-005 +Gc3_105 0 n6 ns105 0 9.45632487827e-007 +Gc3_106 0 n6 ns106 0 4.37758314718e-007 +Gc3_107 0 n6 ns107 0 0.000168200619791 +Gc3_108 0 n6 ns108 0 -5.7905213218e-005 +Gc3_109 0 n6 ns109 0 0.000320084357525 +Gc3_110 0 n6 ns110 0 -0.000121982834833 +Gc3_111 0 n6 ns111 0 0.000192027948858 +Gc3_112 0 n6 ns112 0 -1.98085896158e-005 +Gc3_113 0 n6 ns113 0 -0.000664717694766 +Gc3_114 0 n6 ns114 0 0.000127603284466 +Gc3_115 0 n6 ns115 0 -0.00267226123821 +Gc3_116 0 n6 ns116 0 -0.00193530119297 +Gc3_117 0 n6 ns117 0 -0.00662433955314 +Gc3_118 0 n6 ns118 0 0.000118037512949 +Gc3_119 0 n6 ns119 0 0.000270388004646 +Gc3_120 0 n6 ns120 0 0.00330793719977 +Gc3_121 0 n6 ns121 0 0.00297703310344 +Gc3_122 0 n6 ns122 0 6.50480230188e-005 +Gc3_123 0 n6 ns123 0 -9.50795562242e-008 +Gc3_124 0 n6 ns124 0 -1.08486273214e-008 +Gc3_125 0 n6 ns125 0 8.10410035495e-005 +Gc3_126 0 n6 ns126 0 -0.000247622497585 +Gc3_127 0 n6 ns127 0 1.68216668337e-005 +Gc3_128 0 n6 ns128 0 0.00139272554877 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-0.00112480249379 +Gd3_5 0 n6 ni5 0 -0.0013805076446 +Gd3_6 0 n6 ni6 0 -0.00326273862483 +Gc4_1 0 n8 ns1 0 -0.00704502235691 +Gc4_2 0 n8 ns2 0 0.000393569914143 +Gc4_3 0 n8 ns3 0 -0.000604515581036 +Gc4_4 0 n8 ns4 0 -0.00635598168844 +Gc4_5 0 n8 ns5 0 -0.00613671000831 +Gc4_6 0 n8 ns6 0 -0.000189699244503 +Gc4_7 0 n8 ns7 0 3.06422059423e-007 +Gc4_8 0 n8 ns8 0 -4.00234743051e-008 +Gc4_9 0 n8 ns9 0 -0.000183499821854 +Gc4_10 0 n8 ns10 0 -0.00196914591756 +Gc4_11 0 n8 ns11 0 4.48309603163e-005 +Gc4_12 0 n8 ns12 0 -7.74180358405e-005 +Gc4_13 0 n8 ns13 0 -9.36227415828e-005 +Gc4_14 0 n8 ns14 0 -0.000622110411168 +Gc4_15 0 n8 ns15 0 6.67033409581e-005 +Gc4_16 0 n8 ns16 0 -0.00199061867886 +Gc4_17 0 n8 ns17 0 0.000796240945377 +Gc4_18 0 n8 ns18 0 -2.92136613396e-008 +Gc4_19 0 n8 ns19 0 -5.22229385896e-007 +Gc4_20 0 n8 ns20 0 -0.00011024726491 +Gc4_21 0 n8 ns21 0 -0.000200477706118 +Gc4_22 0 n8 ns22 0 -2.88201544679e-005 +Gc4_23 0 n8 ns23 0 9.69962399568e-005 +Gc4_24 0 n8 ns24 0 -0.00073746397234 +Gc4_25 0 n8 ns25 0 0.00014969944241 +Gc4_26 0 n8 ns26 0 -0.000101322362072 +Gc4_27 0 n8 ns27 0 -8.32403439504e-005 +Gc4_28 0 n8 ns28 0 -0.000694866583067 +Gc4_29 0 n8 ns29 0 -0.00284561393778 +Gc4_30 0 n8 ns30 0 -0.00659213647858 +Gc4_31 0 n8 ns31 0 7.65432759277e-005 +Gc4_32 0 n8 ns32 0 0.000269826655867 +Gc4_33 0 n8 ns33 0 0.00278022517912 +Gc4_34 0 n8 ns34 0 0.00347290690443 +Gc4_35 0 n8 ns35 0 0.000101227390398 +Gc4_36 0 n8 ns36 0 -8.24684057176e-008 +Gc4_37 0 n8 ns37 0 -3.38501909384e-008 +Gc4_38 0 n8 ns38 0 9.40464219065e-005 +Gc4_39 0 n8 ns39 0 0.00108305058257 +Gc4_40 0 n8 ns40 0 5.62464086219e-005 +Gc4_41 0 n8 ns41 0 -0.000407547275818 +Gc4_42 0 n8 ns42 0 -5.71163713341e-005 +Gc4_43 0 n8 ns43 0 -0.000803874455129 +Gc4_44 0 n8 ns44 0 0.000105308434176 +Gc4_45 0 n8 ns45 0 -0.000217700212723 +Gc4_46 0 n8 ns46 0 -9.59925488055e-005 +Gc4_47 0 n8 ns47 0 7.35893949239e-007 +Gc4_48 0 n8 ns48 0 4.3759896256e-007 +Gc4_49 0 n8 ns49 0 0.000410182883567 +Gc4_50 0 n8 ns50 0 -6.73270010681e-005 +Gc4_51 0 n8 ns51 0 -9.74916460449e-005 +Gc4_52 0 n8 ns52 0 9.8784216445e-005 +Gc4_53 0 n8 ns53 0 0.000156421393398 +Gc4_54 0 n8 ns54 0 5.90427171853e-006 +Gc4_55 0 n8 ns55 0 -0.000734315839826 +Gc4_56 0 n8 ns56 0 0.000133167532167 +Gc4_57 0 n8 ns57 0 -0.00169922523966 +Gc4_58 0 n8 ns58 0 -0.00153510019737 +Gc4_59 0 n8 ns59 0 -0.0066027933866 +Gc4_60 0 n8 ns60 0 8.93107971122e-005 +Gc4_61 0 n8 ns61 0 0.000305120792364 +Gc4_62 0 n8 ns62 0 0.00372974618172 +Gc4_63 0 n8 ns63 0 0.00250445373107 +Gc4_64 0 n8 ns64 0 8.29832368114e-005 +Gc4_65 0 n8 ns65 0 -6.81427012091e-008 +Gc4_66 0 n8 ns66 0 -3.22386640048e-008 +Gc4_67 0 n8 ns67 0 8.31546844745e-005 +Gc4_68 0 n8 ns68 0 0.000460172662836 +Gc4_69 0 n8 ns69 0 -0.000135490413966 +Gc4_70 0 n8 ns70 0 0.000418223622271 +Gc4_71 0 n8 ns71 0 0.000142317761158 +Gc4_72 0 n8 ns72 0 -0.00106894039798 +Gc4_73 0 n8 ns73 0 9.80679918418e-005 +Gc4_74 0 n8 ns74 0 -0.00029540025384 +Gc4_75 0 n8 ns75 0 1.5770879125e-005 +Gc4_76 0 n8 ns76 0 9.35544987786e-007 +Gc4_77 0 n8 ns77 0 4.6488584466e-007 +Gc4_78 0 n8 ns78 0 0.00017053363371 +Gc4_79 0 n8 ns79 0 -5.94664036339e-005 +Gc4_80 0 n8 ns80 0 0.000319398636277 +Gc4_81 0 n8 ns81 0 -0.000120536279884 +Gc4_82 0 n8 ns82 0 0.000192627930645 +Gc4_83 0 n8 ns83 0 -1.9921835119e-005 +Gc4_84 0 n8 ns84 0 -0.000666076017214 +Gc4_85 0 n8 ns85 0 0.000129028659193 +Gc4_86 0 n8 ns86 0 -0.0026679829133 +Gc4_87 0 n8 ns87 0 -0.00193310450683 +Gc4_88 0 n8 ns88 0 0.00661571462471 +Gc4_89 0 n8 ns89 0 -2.41380801137e-005 +Gc4_90 0 n8 ns90 0 0.000461730820464 +Gc4_91 0 n8 ns91 0 0.00666528693345 +Gc4_92 0 n8 ns92 0 0.00595510273911 +Gc4_93 0 n8 ns93 0 0.00024759102958 +Gc4_94 0 n8 ns94 0 3.3810858583e-008 +Gc4_95 0 n8 ns95 0 5.70308940707e-008 +Gc4_96 0 n8 ns96 0 2.80489776873e-005 +Gc4_97 0 n8 ns97 0 0.0017833220758 +Gc4_98 0 n8 ns98 0 -4.16490457382e-005 +Gc4_99 0 n8 ns99 0 7.73821968183e-005 +Gc4_100 0 n8 ns100 0 8.14453397085e-005 +Gc4_101 0 n8 ns101 0 0.000668744497673 +Gc4_102 0 n8 ns102 0 -6.96112090351e-005 +Gc4_103 0 n8 ns103 0 0.00131857051747 +Gc4_104 0 n8 ns104 0 -0.000602141086248 +Gc4_105 0 n8 ns105 0 -1.15712938062e-007 +Gc4_106 0 n8 ns106 0 7.79155881539e-007 +Gc4_107 0 n8 ns107 0 0.00020070849935 +Gc4_108 0 n8 ns108 0 5.22170880479e-005 +Gc4_109 0 n8 ns109 0 -3.44256226948e-005 +Gc4_110 0 n8 ns110 0 4.81364025845e-005 +Gc4_111 0 n8 ns111 0 0.000124107075854 +Gc4_112 0 n8 ns112 0 -0.000126767567083 +Gc4_113 0 n8 ns113 0 0.00110739314379 +Gc4_114 0 n8 ns114 0 0.000169713255164 +Gc4_115 0 n8 ns115 0 0.00489349766566 +Gc4_116 0 n8 ns116 0 0.0323350584957 +Gc4_117 0 n8 ns117 0 0.00657258574189 +Gc4_118 0 n8 ns118 0 -6.23080823662e-005 +Gc4_119 0 n8 ns119 0 -0.00026235927488 +Gc4_120 0 n8 ns120 0 -0.0028035912779 +Gc4_121 0 n8 ns121 0 -0.00344039909895 +Gc4_122 0 n8 ns122 0 -0.000115481962943 +Gc4_123 0 n8 ns123 0 6.76429125319e-008 +Gc4_124 0 n8 ns124 0 1.10338345815e-007 +Gc4_125 0 n8 ns125 0 -3.25356266836e-005 +Gc4_126 0 n8 ns126 0 -0.000944377482594 +Gc4_127 0 n8 ns127 0 -7.34748237593e-005 +Gc4_128 0 n8 ns128 0 0.000398126021917 +Gc4_129 0 n8 ns129 0 6.7963182435e-005 +Gc4_130 0 n8 ns130 0 0.000803879422107 +Gc4_131 0 n8 ns131 0 -9.31014806214e-005 +Gc4_132 0 n8 ns132 0 0.000398360919029 +Gc4_133 0 n8 ns133 0 4.3373127308e-005 +Gc4_134 0 n8 ns134 0 1.1162193087e-006 +Gc4_135 0 n8 ns135 0 6.38714348256e-007 +Gc4_136 0 n8 ns136 0 -0.000415243533742 +Gc4_137 0 n8 ns137 0 -5.17410925999e-005 +Gc4_138 0 n8 ns138 0 0.000156632036794 +Gc4_139 0 n8 ns139 0 -4.25510485696e-005 +Gc4_140 0 n8 ns140 0 0.000109927380053 +Gc4_141 0 n8 ns141 0 -2.81163397884e-005 +Gc4_142 0 n8 ns142 0 0.000160857594773 +Gc4_143 0 n8 ns143 0 -0.00022661860767 +Gc4_144 0 n8 ns144 0 -0.00460011382287 +Gc4_145 0 n8 ns145 0 -0.00369107031115 +Gc4_146 0 n8 ns146 0 0.00659472371673 +Gc4_147 0 n8 ns147 0 -8.74872027837e-005 +Gc4_148 0 n8 ns148 0 -0.000295053385096 +Gc4_149 0 n8 ns149 0 -0.00376156100513 +Gc4_150 0 n8 ns150 0 -0.00246332195491 +Gc4_151 0 n8 ns151 0 -9.9710157645e-005 +Gc4_152 0 n8 ns152 0 5.09233163775e-008 +Gc4_153 0 n8 ns153 0 1.06060767146e-007 +Gc4_154 0 n8 ns154 0 -2.1354109057e-005 +Gc4_155 0 n8 ns155 0 -0.00044467543501 +Gc4_156 0 n8 ns156 0 9.72131989063e-005 +Gc4_157 0 n8 ns157 0 -0.000341804913647 +Gc4_158 0 n8 ns158 0 -0.000114099852287 +Gc4_159 0 n8 ns159 0 0.00103730111924 +Gc4_160 0 n8 ns160 0 -8.44859414331e-005 +Gc4_161 0 n8 ns161 0 0.000529755753945 +Gc4_162 0 n8 ns162 0 -6.69972440246e-005 +Gc4_163 0 n8 ns163 0 1.27548617321e-006 +Gc4_164 0 n8 ns164 0 1.00450363228e-006 +Gc4_165 0 n8 ns165 0 -0.000256584843598 +Gc4_166 0 n8 ns166 0 -6.43637541102e-005 +Gc4_167 0 n8 ns167 0 -0.000129083907702 +Gc4_168 0 n8 ns168 0 0.000117039058429 +Gc4_169 0 n8 ns169 0 7.48829321014e-005 +Gc4_170 0 n8 ns170 0 -6.13161264884e-006 +Gc4_171 0 n8 ns171 0 8.85354321058e-005 +Gc4_172 0 n8 ns172 0 -0.000200894737225 +Gc4_173 0 n8 ns173 0 -0.00469556484598 +Gc4_174 0 n8 ns174 0 -0.00380042733461 +Gd4_1 0 n8 ni1 0 -8.71874539458e-005 +Gd4_2 0 n8 ni2 0 -0.000608453586654 +Gd4_3 0 n8 ni3 0 -0.00112246445378 +Gd4_4 0 n8 ni4 0 8.63923573968e-006 +Gd4_5 0 n8 ni5 0 -0.00120055891973 +Gd4_6 0 n8 ni6 0 -0.00129179668687 +Gc5_1 0 n10 ns1 0 -0.006607055891 +Gc5_2 0 n10 ns2 0 9.73280188657e-005 +Gc5_3 0 n10 ns3 0 0.000269351638461 +Gc5_4 0 n10 ns4 0 0.00277330385246 +Gc5_5 0 n10 ns5 0 0.00347484143172 +Gc5_6 0 n10 ns6 0 9.92831188396e-005 +Gc5_7 0 n10 ns7 0 -7.53093298509e-008 +Gc5_8 0 n10 ns8 0 -2.63816923829e-008 +Gc5_9 0 n10 ns9 0 9.35470663968e-005 +Gc5_10 0 n10 ns10 0 0.00102702158999 +Gc5_11 0 n10 ns11 0 5.53534331455e-005 +Gc5_12 0 n10 ns12 0 -0.000449334148978 +Gc5_13 0 n10 ns13 0 -6.13074590852e-005 +Gc5_14 0 n10 ns14 0 -0.000767011188986 +Gc5_15 0 n10 ns15 0 0.000104039306561 +Gc5_16 0 n10 ns16 0 -0.000614714566908 +Gc5_17 0 n10 ns17 0 9.77152509447e-006 +Gc5_18 0 n10 ns18 0 5.09377073629e-007 +Gc5_19 0 n10 ns19 0 4.10262680486e-007 +Gc5_20 0 n10 ns20 0 0.000757467971986 +Gc5_21 0 n10 ns21 0 -0.000222975550062 +Gc5_22 0 n10 ns22 0 -4.5514868825e-005 +Gc5_23 0 n10 ns23 0 8.46584364525e-005 +Gc5_24 0 n10 ns24 0 -0.000428679993107 +Gc5_25 0 n10 ns25 0 0.000196503511652 +Gc5_26 0 n10 ns26 0 -0.000129794729174 +Gc5_27 0 n10 ns27 0 3.86234415025e-005 +Gc5_28 0 n10 ns28 0 -0.00049671352669 +Gc5_29 0 n10 ns29 0 -0.000770731937815 +Gc5_30 0 n10 ns30 0 -0.00704358585471 +Gc5_31 0 n10 ns31 0 0.000384937524574 +Gc5_32 0 n10 ns32 0 -0.000565483162173 +Gc5_33 0 n10 ns33 0 -0.00597009820522 +Gc5_34 0 n10 ns34 0 -0.0065810758805 +Gc5_35 0 n10 ns35 0 -0.000177674889022 +Gc5_36 0 n10 ns36 0 3.44821340703e-007 +Gc5_37 0 n10 ns37 0 2.53813992191e-009 +Gc5_38 0 n10 ns38 0 -0.000176560575777 +Gc5_39 0 n10 ns39 0 -0.000560307237272 +Gc5_40 0 n10 ns40 0 -0.000136412628284 +Gc5_41 0 n10 ns41 0 -0.00130654495524 +Gc5_42 0 n10 ns42 0 0.000104483959238 +Gc5_43 0 n10 ns43 0 -0.000962205986604 +Gc5_44 0 n10 ns44 0 0.000150801071444 +Gc5_45 0 n10 ns45 0 -5.57266995625e-005 +Gc5_46 0 n10 ns46 0 -2.41781524235e-005 +Gc5_47 0 n10 ns47 0 6.87679761199e-007 +Gc5_48 0 n10 ns48 0 -2.6103978876e-007 +Gc5_49 0 n10 ns49 0 -0.00140278272748 +Gc5_50 0 n10 ns50 0 0.000802993288456 +Gc5_51 0 n10 ns51 0 -0.000510487206887 +Gc5_52 0 n10 ns52 0 0.000301765794008 +Gc5_53 0 n10 ns53 0 9.27752767189e-005 +Gc5_54 0 n10 ns54 0 -8.01753922473e-006 +Gc5_55 0 n10 ns55 0 -0.00171650225188 +Gc5_56 0 n10 ns56 0 0.000775520912851 +Gc5_57 0 n10 ns57 0 -0.00483752498478 +Gc5_58 0 n10 ns58 0 -0.00707830555219 +Gc5_59 0 n10 ns59 0 -0.00660948894045 +Gc5_60 0 n10 ns60 0 0.000100109182019 +Gc5_61 0 n10 ns61 0 0.000276940209223 +Gc5_62 0 n10 ns62 0 0.00328464264273 +Gc5_63 0 n10 ns63 0 0.00300130257706 +Gc5_64 0 n10 ns64 0 5.98109488104e-005 +Gc5_65 0 n10 ns65 0 -1.03394523945e-007 +Gc5_66 0 n10 ns66 0 -1.78497385917e-008 +Gc5_67 0 n10 ns67 0 8.34684734307e-005 +Gc5_68 0 n10 ns68 0 -0.000246559766257 +Gc5_69 0 n10 ns69 0 1.66651210124e-005 +Gc5_70 0 n10 ns70 0 0.00139234775737 +Gc5_71 0 n10 ns71 0 -4.81997520537e-005 +Gc5_72 0 n10 ns72 0 -0.00129764119608 +Gc5_73 0 n10 ns73 0 0.000150968787834 +Gc5_74 0 n10 ns74 0 -9.91566243325e-005 +Gc5_75 0 n10 ns75 0 -6.91833753372e-006 +Gc5_76 0 n10 ns76 0 4.94765644716e-007 +Gc5_77 0 n10 ns77 0 4.84845164547e-007 +Gc5_78 0 n10 ns78 0 -0.000610814993458 +Gc5_79 0 n10 ns79 0 0.000199256695989 +Gc5_80 0 n10 ns80 0 0.000814884802028 +Gc5_81 0 n10 ns81 0 -0.000347530125867 +Gc5_82 0 n10 ns82 0 0.000135212893639 +Gc5_83 0 n10 ns83 0 -3.21247340939e-005 +Gc5_84 0 n10 ns84 0 -0.000326851720342 +Gc5_85 0 n10 ns85 0 -7.63604158718e-005 +Gc5_86 0 n10 ns86 0 -0.00327422363793 +Gc5_87 0 n10 ns87 0 -0.00208291856691 +Gc5_88 0 n10 ns88 0 0.00658833269683 +Gc5_89 0 n10 ns89 0 -7.80531136296e-005 +Gc5_90 0 n10 ns90 0 -0.000265142406942 +Gc5_91 0 n10 ns91 0 -0.00279483071047 +Gc5_92 0 n10 ns92 0 -0.0034487418015 +Gc5_93 0 n10 ns93 0 -0.000112530104237 +Gc5_94 0 n10 ns94 0 6.58508345553e-008 +Gc5_95 0 n10 ns95 0 1.09782859278e-007 +Gc5_96 0 n10 ns96 0 -3.47470065618e-005 +Gc5_97 0 n10 ns97 0 -0.000945281137834 +Gc5_98 0 n10 ns98 0 -7.25811113383e-005 +Gc5_99 0 n10 ns99 0 0.00039864420502 +Gc5_100 0 n10 ns100 0 6.67517941451e-005 +Gc5_101 0 n10 ns101 0 0.000804209754521 +Gc5_102 0 n10 ns102 0 -9.3283388076e-005 +Gc5_103 0 n10 ns103 0 0.000398489139548 +Gc5_104 0 n10 ns104 0 4.34882556677e-005 +Gc5_105 0 n10 ns105 0 1.12619964579e-006 +Gc5_106 0 n10 ns106 0 5.79376345222e-007 +Gc5_107 0 n10 ns107 0 -0.000415587226183 +Gc5_108 0 n10 ns108 0 -5.173658475e-005 +Gc5_109 0 n10 ns109 0 0.000156911476531 +Gc5_110 0 n10 ns110 0 -4.26787761025e-005 +Gc5_111 0 n10 ns111 0 0.000109485309013 +Gc5_112 0 n10 ns112 0 -2.85609547079e-005 +Gc5_113 0 n10 ns113 0 0.000163568979612 +Gc5_114 0 n10 ns114 0 -0.00022737297371 +Gc5_115 0 n10 ns115 0 -0.00462156006108 +Gc5_116 0 n10 ns116 0 -0.00370269067242 +Gc5_117 0 n10 ns117 0 0.00657646919063 +Gc5_118 0 n10 ns118 0 1.87782021026e-005 +Gc5_119 0 n10 ns119 0 0.000428797172463 +Gc5_120 0 n10 ns120 0 0.00628413070674 +Gc5_121 0 n10 ns121 0 0.00638655579473 +Gc5_122 0 n10 ns122 0 0.000242864509446 +Gc5_123 0 n10 ns123 0 2.52902098461e-007 +Gc5_124 0 n10 ns124 0 7.26948638288e-008 +Gc5_125 0 n10 ns125 0 4.84399506577e-005 +Gc5_126 0 n10 ns126 0 0.000492112049923 +Gc5_127 0 n10 ns127 0 0.000102647983012 +Gc5_128 0 n10 ns128 0 0.00121204507806 +Gc5_129 0 n10 ns129 0 -7.50271552423e-005 +Gc5_130 0 n10 ns130 0 0.000976355376231 +Gc5_131 0 n10 ns131 0 -0.00014845312375 +Gc5_132 0 n10 ns132 0 5.20977886316e-005 +Gc5_133 0 n10 ns133 0 -2.88064346286e-005 +Gc5_134 0 n10 ns134 0 -9.43858538048e-007 +Gc5_135 0 n10 ns135 0 7.50064058791e-007 +Gc5_136 0 n10 ns136 0 0.00119939080703 +Gc5_137 0 n10 ns137 0 -0.000780757632641 +Gc5_138 0 n10 ns138 0 0.000299490337816 +Gc5_139 0 n10 ns139 0 -7.53059643098e-005 +Gc5_140 0 n10 ns140 0 -1.53567896794e-005 +Gc5_141 0 n10 ns141 0 -0.000146626810599 +Gc5_142 0 n10 ns142 0 0.00166954232351 +Gc5_143 0 n10 ns143 0 -0.000336870292008 +Gc5_144 0 n10 ns144 0 0.00785665100283 +Gc5_145 0 n10 ns145 0 0.0357190036984 +Gc5_146 0 n10 ns146 0 0.00660578530566 +Gc5_147 0 n10 ns147 0 -0.000102445398612 +Gc5_148 0 n10 ns148 0 -0.000267410886027 +Gc5_149 0 n10 ns149 0 -0.00331391551713 +Gc5_150 0 n10 ns150 0 -0.00296154087855 +Gc5_151 0 n10 ns151 0 -7.67770074101e-005 +Gc5_152 0 n10 ns152 0 8.3009335191e-008 +Gc5_153 0 n10 ns153 0 9.36612332178e-008 +Gc5_154 0 n10 ns154 0 -2.07221682007e-005 +Gc5_155 0 n10 ns155 0 0.000216315651674 +Gc5_156 0 n10 ns156 0 -3.02611870713e-005 +Gc5_157 0 n10 ns157 0 -0.00118997644303 +Gc5_158 0 n10 ns158 0 4.92160432071e-005 +Gc5_159 0 n10 ns159 0 0.00125862190029 +Gc5_160 0 n10 ns160 0 -0.000134342728724 +Gc5_161 0 n10 ns161 0 0.000149313942746 +Gc5_162 0 n10 ns162 0 6.77841708955e-005 +Gc5_163 0 n10 ns163 0 1.33593896232e-006 +Gc5_164 0 n10 ns164 0 8.6904317535e-007 +Gc5_165 0 n10 ns165 0 0.000383231017525 +Gc5_166 0 n10 ns166 0 -0.000334627875259 +Gc5_167 0 n10 ns167 0 -0.000491649513593 +Gc5_168 0 n10 ns168 0 0.000284334612333 +Gc5_169 0 n10 ns169 0 4.55826873549e-005 +Gc5_170 0 n10 ns170 0 -2.91048094696e-006 +Gc5_171 0 n10 ns171 0 0.000142769704308 +Gc5_172 0 n10 ns172 0 -0.0003042431181 +Gc5_173 0 n10 ns173 0 -0.00419742892477 +Gc5_174 0 n10 ns174 0 -0.00329928748817 +Gd5_1 0 n10 ni1 0 -3.93725497403e-005 +Gd5_2 0 n10 ni2 0 -0.00213794997323 +Gd5_3 0 n10 ni3 0 -0.00137275672019 +Gd5_4 0 n10 ni4 0 -0.00121201577434 +Gd5_5 0 n10 ni5 0 0.00136375006834 +Gd5_6 0 n10 ni6 0 -0.0011259017474 +Gc6_1 0 n12 ns1 0 -0.0066010858859 +Gc6_2 0 n12 ns2 0 9.37289684359e-005 +Gc6_3 0 n12 ns3 0 0.000303719722008 +Gc6_4 0 n12 ns4 0 0.00372743785154 +Gc6_5 0 n12 ns5 0 0.002502680999 +Gc6_6 0 n12 ns6 0 8.15298145719e-005 +Gc6_7 0 n12 ns7 0 -6.31517925767e-008 +Gc6_8 0 n12 ns8 0 -2.65122500971e-008 +Gc6_9 0 n12 ns9 0 8.61922227138e-005 +Gc6_10 0 n12 ns10 0 0.000475364887581 +Gc6_11 0 n12 ns11 0 -0.000131602894143 +Gc6_12 0 n12 ns12 0 0.000440782577396 +Gc6_13 0 n12 ns13 0 0.000139598981756 +Gc6_14 0 n12 ns14 0 -0.000989724706285 +Gc6_15 0 n12 ns15 0 9.79321083928e-005 +Gc6_16 0 n12 ns16 0 -0.000806303409033 +Gc6_17 0 n12 ns17 0 0.000175907836602 +Gc6_18 0 n12 ns18 0 4.53621659084e-007 +Gc6_19 0 n12 ns19 0 3.12594383137e-007 +Gc6_20 0 n12 ns20 0 0.000385688900882 +Gc6_21 0 n12 ns21 0 -0.000128869105113 +Gc6_22 0 n12 ns22 0 0.00028033325307 +Gc6_23 0 n12 ns23 0 -0.000114507806993 +Gc6_24 0 n12 ns24 0 -0.0002840667905 +Gc6_25 0 n12 ns25 0 9.66862314362e-005 +Gc6_26 0 n12 ns26 0 -0.000119528060863 +Gc6_27 0 n12 ns27 0 2.84953865157e-005 +Gc6_28 0 n12 ns28 0 -0.000987801823801 +Gc6_29 0 n12 ns29 0 -0.00108577716521 +Gc6_30 0 n12 ns30 0 -0.00660456861621 +Gc6_31 0 n12 ns31 0 0.000101202498529 +Gc6_32 0 n12 ns32 0 0.000275486664982 +Gc6_33 0 n12 ns33 0 0.00328216804564 +Gc6_34 0 n12 ns34 0 0.0029964874991 +Gc6_35 0 n12 ns35 0 6.13715496406e-005 +Gc6_36 0 n12 ns36 0 -1.01962817553e-007 +Gc6_37 0 n12 ns37 0 -2.33292549313e-008 +Gc6_38 0 n12 ns38 0 8.10308165848e-005 +Gc6_39 0 n12 ns39 0 -0.000264142763388 +Gc6_40 0 n12 ns40 0 1.62142893186e-005 +Gc6_41 0 n12 ns41 0 0.00131557648903 +Gc6_42 0 n12 ns42 0 -4.540353716e-005 +Gc6_43 0 n12 ns43 0 -0.00125948986205 +Gc6_44 0 n12 ns44 0 0.00014952082349 +Gc6_45 0 n12 ns45 0 -0.000103167840675 +Gc6_46 0 n12 ns46 0 -3.85449215447e-005 +Gc6_47 0 n12 ns47 0 2.87789216409e-007 +Gc6_48 0 n12 ns48 0 6.56389296711e-007 +Gc6_49 0 n12 ns49 0 -0.00062919378309 +Gc6_50 0 n12 ns50 0 0.00023375012639 +Gc6_51 0 n12 ns51 0 0.000914999168773 +Gc6_52 0 n12 ns52 0 -0.000365324088455 +Gc6_53 0 n12 ns53 0 6.99374841241e-005 +Gc6_54 0 n12 ns54 0 -2.2026393706e-005 +Gc6_55 0 n12 ns55 0 -0.00067810020393 +Gc6_56 0 n12 ns56 0 0.000274051645814 +Gc6_57 0 n12 ns57 0 -0.00185173709297 +Gc6_58 0 n12 ns58 0 -0.00148543895591 +Gc6_59 0 n12 ns59 0 -0.00704123126302 +Gc6_60 0 n12 ns60 0 0.000381994891732 +Gc6_61 0 n12 ns61 0 -0.000601846058924 +Gc6_62 0 n12 ns62 0 -0.00686349168245 +Gc6_63 0 n12 ns63 0 -0.00567148420318 +Gc6_64 0 n12 ns64 0 -0.000166382748603 +Gc6_65 0 n12 ns65 0 3.34419289995e-007 +Gc6_66 0 n12 ns66 0 1.08109637593e-007 +Gc6_67 0 n12 ns67 0 -0.000117292358428 +Gc6_68 0 n12 ns68 0 -0.000121952201839 +Gc6_69 0 n12 ns69 0 5.39134631526e-007 +Gc6_70 0 n12 ns70 0 -0.00134279472171 +Gc6_71 0 n12 ns71 0 7.48068458871e-005 +Gc6_72 0 n12 ns72 0 -0.00167858120117 +Gc6_73 0 n12 ns73 0 0.000141229371777 +Gc6_74 0 n12 ns74 0 -9.75703697984e-005 +Gc6_75 0 n12 ns75 0 2.51262193884e-005 +Gc6_76 0 n12 ns76 0 1.38142121035e-006 +Gc6_77 0 n12 ns77 0 -2.19841692707e-007 +Gc6_78 0 n12 ns78 0 -0.000482823607852 +Gc6_79 0 n12 ns79 0 0.00010448982753 +Gc6_80 0 n12 ns80 0 -0.00114948092889 +Gc6_81 0 n12 ns81 0 0.0009233220601 +Gc6_82 0 n12 ns82 0 0.000141040559054 +Gc6_83 0 n12 ns83 0 3.57190670229e-005 +Gc6_84 0 n12 ns84 0 -0.00110695752198 +Gc6_85 0 n12 ns85 0 0.000468488048834 +Gc6_86 0 n12 ns86 0 -0.00832241710609 +Gc6_87 0 n12 ns87 0 -0.00948202434181 +Gc6_88 0 n12 ns88 0 0.00658233745009 +Gc6_89 0 n12 ns89 0 -7.4189270843e-005 +Gc6_90 0 n12 ns90 0 -0.000299805631676 +Gc6_91 0 n12 ns91 0 -0.00374840809468 +Gc6_92 0 n12 ns92 0 -0.00247612529141 +Gc6_93 0 n12 ns93 0 -9.55262534455e-005 +Gc6_94 0 n12 ns94 0 5.52961904372e-008 +Gc6_95 0 n12 ns95 0 1.09096305006e-007 +Gc6_96 0 n12 ns96 0 -2.41744304551e-005 +Gc6_97 0 n12 ns97 0 -0.000446031119212 +Gc6_98 0 n12 ns98 0 9.84475704797e-005 +Gc6_99 0 n12 ns99 0 -0.000341150541377 +Gc6_100 0 n12 ns100 0 -0.000115724522047 +Gc6_101 0 n12 ns101 0 0.00103790363453 +Gc6_102 0 n12 ns102 0 -8.4868240759e-005 +Gc6_103 0 n12 ns103 0 0.000530451507003 +Gc6_104 0 n12 ns104 0 -6.6904299438e-005 +Gc6_105 0 n12 ns105 0 1.28807833341e-006 +Gc6_106 0 n12 ns106 0 9.94258613751e-007 +Gc6_107 0 n12 ns107 0 -0.000257478143646 +Gc6_108 0 n12 ns108 0 -6.33320103477e-005 +Gc6_109 0 n12 ns109 0 -0.000129114708466 +Gc6_110 0 n12 ns110 0 0.000116133076672 +Gc6_111 0 n12 ns111 0 7.50626191663e-005 +Gc6_112 0 n12 ns112 0 -5.87280964136e-006 +Gc6_113 0 n12 ns113 0 8.78391963913e-005 +Gc6_114 0 n12 ns114 0 -0.000201266066829 +Gc6_115 0 n12 ns115 0 -0.00470160579939 +Gc6_116 0 n12 ns116 0 -0.00380483608207 +Gc6_117 0 n12 ns117 0 0.00662246759817 +Gc6_118 0 n12 ns118 0 -0.00011867939023 +Gc6_119 0 n12 ns119 0 -0.000270321706619 +Gc6_120 0 n12 ns120 0 -0.00330762077004 +Gc6_121 0 n12 ns121 0 -0.00296663047505 +Gc6_122 0 n12 ns122 0 -7.48427410793e-005 +Gc6_123 0 n12 ns123 0 8.50470538474e-008 +Gc6_124 0 n12 ns124 0 9.93722836033e-008 +Gc6_125 0 n12 ns125 0 -2.29407936729e-005 +Gc6_126 0 n12 ns126 0 0.000215888190064 +Gc6_127 0 n12 ns127 0 -3.00236862641e-005 +Gc6_128 0 n12 ns128 0 -0.00119005498676 +Gc6_129 0 n12 ns129 0 4.90031457723e-005 +Gc6_130 0 n12 ns130 0 0.00125898130984 +Gc6_131 0 n12 ns131 0 -0.000134856972698 +Gc6_132 0 n12 ns132 0 0.000149226074736 +Gc6_133 0 n12 ns133 0 6.74161911744e-005 +Gc6_134 0 n12 ns134 0 1.34919456176e-006 +Gc6_135 0 n12 ns135 0 8.74167233385e-007 +Gc6_136 0 n12 ns136 0 0.000384569961429 +Gc6_137 0 n12 ns137 0 -0.000335235042974 +Gc6_138 0 n12 ns138 0 -0.000492401795186 +Gc6_139 0 n12 ns139 0 0.000285353941156 +Gc6_140 0 n12 ns140 0 4.49789570629e-005 +Gc6_141 0 n12 ns141 0 -3.72688440995e-006 +Gc6_142 0 n12 ns142 0 0.000148169627738 +Gc6_143 0 n12 ns143 0 -0.000304984424176 +Gc6_144 0 n12 ns144 0 -0.0042368882173 +Gc6_145 0 n12 ns145 0 -0.00332167944398 +Gc6_146 0 n12 ns146 0 0.00658865268796 +Gc6_147 0 n12 ns147 0 9.51178267164e-006 +Gc6_148 0 n12 ns148 0 0.000459357435887 +Gc6_149 0 n12 ns149 0 0.00718673157794 +Gc6_150 0 n12 ns150 0 0.00547574768028 +Gc6_151 0 n12 ns151 0 0.000220789287182 +Gc6_152 0 n12 ns152 0 2.76145883515e-007 +Gc6_153 0 n12 ns153 0 -4.29704158865e-009 +Gc6_154 0 n12 ns154 0 9.95675756069e-006 +Gc6_155 0 n12 ns155 0 0.000129709628293 +Gc6_156 0 n12 ns156 0 -3.26887069524e-005 +Gc6_157 0 n12 ns157 0 0.00118161881507 +Gc6_158 0 n12 ns158 0 -2.91123422937e-005 +Gc6_159 0 n12 ns159 0 0.0016375670238 +Gc6_160 0 n12 ns160 0 -0.000130140884885 +Gc6_161 0 n12 ns161 0 0.000130972599513 +Gc6_162 0 n12 ns162 0 -8.52118368406e-005 +Gc6_163 0 n12 ns163 0 -1.32702437062e-006 +Gc6_164 0 n12 ns164 0 1.37206993692e-006 +Gc6_165 0 n12 ns165 0 0.000559047644986 +Gc6_166 0 n12 ns166 0 -0.000265673435919 +Gc6_167 0 n12 ns167 0 0.000809112358547 +Gc6_168 0 n12 ns168 0 -0.000534461365844 +Gc6_169 0 n12 ns169 0 -9.43083163268e-005 +Gc6_170 0 n12 ns170 0 -0.000120994267221 +Gc6_171 0 n12 ns171 0 0.00150724471768 +Gc6_172 0 n12 ns172 0 -0.000371231427557 +Gc6_173 0 n12 ns173 0 0.0103807440616 +Gc6_174 0 n12 ns174 0 0.0380943902059 +Gd6_1 0 n12 ni1 0 -0.000239404009448 +Gd6_2 0 n12 ni2 0 -0.000832289132123 +Gd6_3 0 n12 ni3 0 -0.00338045657996 +Gd6_4 0 n12 ni4 0 -0.00129558416239 +Gd6_5 0 n12 ni5 0 -0.00114617437223 +Gd6_6 0 n12 ni6 0 0.00202572802055 +.ends diff --git a/spice/copy/sub/Contrib/Wurth/WE-UCF.lib b/spice/copy/sub/Contrib/Wurth/WE-UCF.lib new file mode 100755 index 0000000..5494575 --- /dev/null +++ b/spice/copy/sub/Contrib/Wurth/WE-UCF.lib @@ -0,0 +1,471 @@ +************************************************** +* Manufacturer: Wurth Elektronik +* Kinds: SMD Common Mode Line Filter +* Matchcode: WE-UCF +* Library Type: LTspice +* Version: rev18a +* Created/modified by: Fredo Huang +* Date and Time : 2018-01-03 +* Team: eiSos EDA Service +* Contact: libraries@we-online.com +************************************************** +.subckt 1712_744290103_10m 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=4.74617949108858E-11 +.param dC4=1.38462941112749E-09 +.param dL4=4.95096492159064E-06 +.param dR5=17551.318359375 +.param dR6=48996.91015625 +.param Rdc=.920000016689301 +.param L1=1.25834280624986E-02 +.param C1=1.66831947562285E-11 +.param R1=184871.25 +.param L2=0 +.param C2=0 +.param R2=0 +.param L3=0 +.param C3=0 +.param R3=0 +.ends 1712_744290103_10m +***** +***** +.subckt 1712_744290104_100m 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=8.03334274102063E-11 +.param dC4=8.79059403047222E-09 +.param dL4=4.73879190394655E-05 +.param dR5=120012.125 +.param dR6=56807.0703125 +.param Rdc=8.89999961853027 +.param L1=.112887047231197 +.param C1=2.86326101717194E-11 +.param R1=1525863.375 +.param L2=0 +.param C2=0 +.param R2=0 +.param L3=0 +.param C3=0 +.param R3=0 +.ends 1712_744290104_100m +***** +***** +.subckt 1712_744290121_0.12m 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=1.21738964395379E-11 +.param dC4=1.22426535575926E-09 +.param dL4=4.21172146047866E-08 +.param dR5=930.412902832031 +.param dR6=34905 +.param Rdc=.010499999858439 +.param L1=5.51203193026595E-05 +.param C1=7.83036829821171E-11 +.param R1=422.040466308594 +.param L2=6.53777169645764E-05 +.param C2=1.38247234840461E-11 +.param R2=1372.61340332031 +.param L3=7.43812597647775E-06 +.param C3=1.92659451760113E-12 +.param R3=693.999389648438 +.ends 1712_744290121_0.12m +***** +***** +.subckt 1712_744290130_13u 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=4.57795390138016E-12 +.param dC4=1.81477521898898E-09 +.param dL4=6.44908704217073E-09 +.param dR5=207.256896972656 +.param dR6=58693.20703125 +.param Rdc=2.70000007003546E-03 +.param L1=9.41628786677029E-06 +.param C1=1.43379502715035E-10 +.param R1=133.131927490234 +.param L2=2.81386269307404E-06 +.param C2=2.45268730455703E-13 +.param R2=107.987922668457 +.param L3=7.5519661635326E-09 +.param C3=2.99107028207957E-12 +.param R3=134.344955444336 +.ends 1712_744290130_13u +***** +***** +.subckt 1712_744290152_1.5m 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=2.64873695893231E-11 +.param dC4=1.1000000389727E-11 +.param dL4=7.46307364352106E-07 +.param dR5=9895.32421875 +.param dR6=26414.25390625 +.param Rdc=.119999997317791 +.param L1=1.89211196266115E-03 +.param C1=8.06618747489773E-12 +.param R1=24879.861328125 +.param L2=0 +.param C2=0 +.param R2=0 +.param L3=0 +.param C3=0 +.param R3=0 +.ends 1712_744290152_1.5m +***** +***** +.subckt 1712_744290283_28m 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=4.49225240339857E-11 +.param dC4=1.37190958593436E-09 +.param dL4=1.26334916785709E-05 +.param dR5=36557.671875 +.param dR6=47479.15625 +.param Rdc=2.79999995231628 +.param L1=3.25118005275726E-02 +.param C1=1.92766549250711E-11 +.param R1=428658.96875 +.param L2=0 +.param C2=0 +.param R2=0 +.param L3=0 +.param C3=0 +.param R3=0 +.ends 1712_744290283_28m +***** +***** +.subckt 1712_744290321_0.32m 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=1.42225406798979E-11 +.param dC4=1.01491937076759E-09 +.param dL4=1.37159545943177E-07 +.param dR5=2605.998046875 +.param dR6=49426.28125 +.param Rdc=.028999999165535 +.param L1=2.65387789113447E-04 +.param C1=6.81724555279262E-12 +.param R1=2490.7373046875 +.param L2=1.1344288213877E-04 +.param C2=9.37875818673994E-12 +.param R2=3506.99365234375 +.param L3=1.68796032085083E-05 +.param C3=3.19853084990163E-12 +.param R3=1128.4638671875 +.ends 1712_744290321_0.32m +***** +***** +.subckt 1712_744290472_4.7m 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=2.96738154881293E-11 +.param dC4=1.02935437951146E-09 +.param dL4=2.51910887527629E-06 +.param dR5=8836.4130859375 +.param dR6=40508.046875 +.param Rdc=.519999980926514 +.param L1=5.89522439986467E-03 +.param C1=1.05513132953039E-11 +.param R1=67842.5 +.param L2=0 +.param C2=0 +.param R2=0 +.param L3=0 +.param C3=0 +.param R3=0 +.ends 1712_744290472_4.7m +***** +***** +.subckt 1712_744290473_47m 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=3.7521298568155E-11 +.param dC4=1.20230003730626E-09 +.param dL4=2.11652914003935E-05 +.param dR5=127700.953125 +.param dR6=48777.77734375 +.param Rdc=4 +.param L1=5.58203496038914E-02 +.param C1=1.57894721602991E-11 +.param R1=759816.5625 +.param L2=0 +.param C2=0 +.param R2=0 +.param L3=0 +.param C3=0 +.param R3=0 +.ends 1712_744290473_47m +***** +***** +.subckt 1712_744290560_56u 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=1.36055021415782E-11 +.param dC4=7.28196183907848E-11 +.param dL4=1.54179193856407E-08 +.param dR5=296.977081298828 +.param dR6=43570.71484375 +.param Rdc=4.69999993219972E-03 +.param L1=3.52823190041818E-05 +.param C1=6.85353510054831E-11 +.param R1=297.650543212891 +.param L2=2.31806388910627E-05 +.param C2=1.97330138340668E-11 +.param R2=503.99951171875 +.param L3=9.9998067071283E-07 +.param C3=2.16720500052781E-12 +.param R3=245.140625 +.ends 1712_744290560_56u +***** +***** +.subckt 1712_744290683_68m 1 2 3 4 +R1 N001 1 {Rdc} +R6 N007 2 {Rdc} +R8 N003 N001 {dR6} +C6 N002 N001 {dC4} +L15 N006 N001 {dL4} +L16 N007 N008 {dL4} +C7 N006 N008 {ck} +R9 N003 N002 {dR5} +R10 N009 N012 {dR5} +C8 N012 N007 {dC4} +R11 N009 N007 {dR6} +L17 N003 N006 {dL4} +L18 N008 N009 {dL4} +L9 N004 N003 {L1} Rpar={R1} Cpar={C1} +L10 N005 N004 {L2} Rpar={R2} Cpar={C2} +L11 4 N005 {L3} Rpar={R3} Cpar={C3} +L12 N010 N009 {L1} Rpar={R1} Cpar={C1} +L13 N011 N010 {L2} Rpar={R2} Cpar={C2} +L14 3 N011 {L3} Rpar={R3} Cpar={C3} +K1 L15 L16 L17 L18 0.9999 +K2 L9 L12 1 +K3 L10 L13 1 +K4 L11 L14 1 +.param ck=5.82679945959619E-11 +.param dC4=2.60948063157684E-09 +.param dL4=3.05886605929118E-05 +.param dR5=102559.84375 +.param dR6=58554.0703125 +.param Rdc=5 +.param L1=7.82001689076424E-02 +.param C1=2.37045088419263E-11 +.param R1=1450485.875 +.param L2=0 +.param C2=0 +.param R2=0 +.param L3=0 +.param C3=0 +.param R3=0 +.ends 1712_744290683_68m diff --git a/spice/copy/sub/ISO16750-2.lib b/spice/copy/sub/ISO16750-2.lib new file mode 100755 index 0000000..db0c309 --- /dev/null +++ b/spice/copy/sub/ISO16750-2.lib @@ -0,0 +1,255 @@ +* Copyright (c) 2017 Linear Technology Corporation. All rights reserved. +* Author: Dan Eddleman +* +* Automotive Transient Models (ISO-16750-2) +*************************************************************** + +*.subckt 4-2_12V_DirectCurrentSupplyVoltageMinimum + - +*.param Usmin = 6 +*V1 + - {Usmin} +*.ends 4-2_12V_DirectCurrentSupplyVoltageMinimum + +*.subckt 4-2_24V_DirectCurrentSupplyVoltageMinimum + - +*.param Usmin = 10 +*V1 + - {Usmin} +*.ends 4-2_24V_DirectCurrentSupplyVoltageMinimum + +*.subckt 4-2_12V_DirectCurrentSupplyVoltageMaximum + - +*.param Usmin = 16 +*V1 + - {Usmin} +*.ends 4-2_12V_DirectCurrentSupplyVoltageMaximum + +*.subckt 4-2_24V_DirectCurrentSupplyVoltageMaximum + - +*.param Usmin = 32 +*V1 + - {Usmin} +*.ends 4-2_24V_DirectCurrentSupplyVoltageMaximum + +*.subckt 4-3_12V_Overvoltage + - +*.param Usmax = 24 +*V1 + - {Usmax} +*.ends 4-3_12V_Overvoltage + +*.subckt 4-3_24V_Overvoltage + - +*.param Usmax = 36 +*V1 + - {Usmax} +*.ends 4-3_24V_Overvoltage + +.subckt 4-4_12V_SuperimposedAlternatingVoltage + - +.param Umax = 16 +.param Upp=4 +.param Ri=50m +A1 N001 N004 0 0 0 0 N002 0 MODULATOR mark=25k space=0 +V1 N005 - PWL(0 0 10u {Umax-(Upp/2)}) Rser=1m +B1 N001 0 V=2e-3*exp(v(t1)/9.654) +V2 N004 0 PWL(0 0 1u 0 +1u {Upp/2}) Rser=1m +R1 + N003 {Ri} +E1 N003 N005 N002 0 1 +V3 t1 0 PWL(0 0 60 60 120 0 180 60 240 0 300 60 360 0 420 60 480 0 540 60 600 0) Rser=1m +.ends 4-4_12V_SuperimposedAlternatingVoltage + +.subckt 4-4_24V_SuperimposedAlternatingVoltage + - +.param Umax = 32 +.param Upp=10 +.param Ri=50m +A1 N001 N004 0 0 0 0 N002 0 MODULATOR mark=25k space=0 +V1 N005 - PWL(0 0 10u {Umax-(Upp/2)}) Rser=1m +B1 N001 0 V=2e-3*exp(v(t1)/9.654) +V2 N004 0 PWL(0 0 1u 0 +1u {Upp/2}) Rser=1m +R1 + N003 {Ri} +E1 N003 N005 N002 0 1 +V3 t1 0 PWL(0 0 60 60 120 0 180 60 240 0 300 60 360 0 420 60 480 0 540 60 600 0) Rser=1m +.ends 4-4_24V_SuperimposedAlternatingVoltage + +.subckt 4-5_12V_SlowDecreaseAndIncreaseOfSupplyVoltage + - +.param Usmin = 6 +.param t0=1m +V1 + - PWL(0 0 {t0} 0 +1u {Usmin} {Usmin*60/0.5} 0 {2*Usmin*60/0.5} {Usmin}) +.ends 4-5_12V_SlowDecreaseAndIncreaseOfSupplyVoltage + +.subckt 4-5_24V_SlowDecreaseAndIncreaseOfSupplyVoltage + - +.param Usmin = 10 +.param t0=1m +V1 + - PWL(0 0 {t0} 0 +1u {Usmin} {Usmin*60/0.5} 0 {2*Usmin*60/0.5} {Usmin}) +.ends 4-5_24V_SlowDecreaseAndIncreaseOfSupplyVoltage + +.subckt 4-6-1_12V_MomentaryDropInSupplyVoltage + - +.param Usmin = 6 +V2 + - PWL(0 0 +1u {Usmin} 10 {Usmin} +1m 4.5 10.1 4.5 +1m {Usmin}) +.ends 4-6-1_12V_MomentaryDropInSupplyVoltage + +.subckt 4-6-1_24V_MomentaryDropInSupplyVoltage + - +.param Usmin = 10 +V2 + - PWL(0 0 +1u {Usmin} 10 {Usmin} +1m 9 10.1 9 +1m {Usmin}) +.ends 4-6-1_24V_MomentaryDropInSupplyVoltage + +.subckt 4-6-2_12V_ResetBehaviourAtVoltageDrop + - +.param Usmin = 6 +V1 + - PWL(0 0 +1u {Usmin} 20 {Usmin} +1m {Usmin*0.95} +5 {Usmin*0.95} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.90} +5 {Usmin*0.90} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.85} +5 {Usmin*0.85} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.8} +5 {Usmin*0.8} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.75} +5 {Usmin*0.75} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.7} +5 {Usmin*0.7} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.65} +5 {Usmin*0.65} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.6} +5 {Usmin*0.6} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.55} +5 {Usmin*0.55} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.5} +5 {Usmin*0.5} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.45} +5 {Usmin*0.45} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.4} +5 {Usmin*0.4} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.35} +5 {Usmin*0.35} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.3} +5 {Usmin*0.3} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.25} +5 {Usmin*0.25} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.2} +5 {Usmin*0.2} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.15} +5 {Usmin*0.15} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.1} +5 {Usmin*0.1} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.05} +5 {Usmin*0.05} +1m {Usmin} +10 {Usmin} +1m {Usmin*0} +5 {Usmin*0} +1m {Usmin} +40 {Usmin}) +.ends 4-6-2_12V_ResetBehaviourAtVoltageDrop + +.subckt 4-6-2_24V_ResetBehaviourAtVoltageDrop + - +.param Usmin = 10 +V1 + - PWL(0 0 +1u {Usmin} 20 {Usmin} +1m {Usmin*0.95} +5 {Usmin*0.95} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.90} +5 {Usmin*0.90} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.85} +5 {Usmin*0.85} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.8} +5 {Usmin*0.8} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.75} +5 {Usmin*0.75} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.7} +5 {Usmin*0.7} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.65} +5 {Usmin*0.65} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.6} +5 {Usmin*0.6} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.55} +5 {Usmin*0.55} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.5} +5 {Usmin*0.5} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.45} +5 {Usmin*0.45} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.4} +5 {Usmin*0.4} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.35} +5 {Usmin*0.35} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.3} +5 {Usmin*0.3} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.25} +5 {Usmin*0.25} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.2} +5 {Usmin*0.2} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.15} +5 {Usmin*0.15} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.1} +5 {Usmin*0.1} +1m {Usmin} +10 {Usmin} +1m {Usmin*0.05} +5 {Usmin*0.05} +1m {Usmin} +10 {Usmin} +1m {Usmin*0} +5 {Usmin*0} +1m {Usmin} +40 {Usmin}) +.ends 4-6-2_24V_ResetBehaviourAtVoltageDrop + +.subckt 4-6-3_12V_StartingProfile + - +.param Ub = 13.5 +.param Us6 = 6 +.param Us = 6.5 +.param tf = 5m +.param t6 = 15m +.param t7 = 50m +.param t8 = 10000m +.param tr = 100m +.param Ri = 10m +.param t0 = 1 +R1 + - {Ri} +I3 - + PWL(0 0 +1u {Ub/Ri} {t0} {Ub/Ri} {t0+tf} {Us6/Ri} {t0+tf+t6} {Us6/Ri} {t0+tf+t6+t7} {(Us+1)/Ri} {t0+tf+t6+t7+t8} {(Us+1)/Ri} {t0+tf+t6+t7+t8+tr} {Ub/Ri}) +I1 - + SINE(0 {1/Ri} 2 {t0+tf+t6+t7} 0 180 {t8*2}) +.ends 4-6-3_12V_StartingProfile + +.subckt 4-6-3_24V_StartingProfile + - +.param Ub = 27 +.param Us6 = 6 +.param Us = 10 +.param tf = 10m +.param t6 = 50m +.param t7 = 50m +.param t8 = 1000m +.param tr = 40m +.param Ri = 10m +.param t0 = 1 +R1 + - {Ri} +I3 - + PWL(0 0 +1u {Ub/Ri} {t0} {Ub/Ri} {t0+tf} {Us6/Ri} {t0+tf+t6} {Us6/Ri} {t0+tf+t6+t7} {(Us+1)/Ri} {t0+tf+t6+t7+t8} {(Us+1)/Ri} {t0+tf+t6+t7+t8+tr} {Ub/Ri}) +I1 - + SINE(0 {1/Ri} 2 {t0+tf+t6+t7} 0 180 {t8*2}) +.ends 4-6-3_24V_StartingProfile + +.subckt 4-6-4_12V_LoadDumpWithoutSuppressionTestA + - +.param Ua=14 +.param Us=101 +.param UsClamp={Us} +.param Ri=0.5 +.param t0=1 +.param Creservoir=0.15 Rshunt=1.55 +L1 N004 N005 2m +D1 N007 + Dideal +V2 N007 - PWL(0 0 1m {Ua}) +R1 N005 - {Rshunt} +D2 N006 + Dideal +C1 N003 - {Creservoir} +R2 N003 N002 100 +V3 N002 - PWL(0 0 1m {Us}) +S1 N004 N003 N001 0 Sideal +V4 N001 0 PULSE(0 1 {t0} +1n +1n 1 60 10) +R3 N006 N005 {Ri} +D3 + N008 Dideal +V5 N008 - PWL(0 0 1m {Usclamp}) +.model Sideal SW(Ron=1m Roff=100MEG Vt=0.5 Vh=-0.1) +.model Dideal D(Ron=1m Roff=1MEG Vfwd=1m epsilon=10m) +.ic V(n003)={Us} +.ends 4-6-4_12V_LoadDumpWithoutSuppressionTestA + + +.subckt 4-6-4_24V_LoadDumpWithoutSuppressionTestA + - +.param Ua=28 +.param Us=202 +.param UsClamp={Us} +.param Ri=1 +.param t0=1 +.param Creservoir=0.15 Rshunt=1.55 +L1 N004 N005 2m +D1 N007 + Dideal +V2 N007 - PWL(0 0 1m {Ua}) +R1 N005 - {Rshunt} +D2 N006 + Dideal +C1 N003 - {Creservoir} +R2 N003 N002 100 +V3 N002 - PWL(0 0 1m {Us}) +S1 N004 N003 N001 0 Sideal +V4 N001 0 PULSE(0 1 {t0} +1n +1n 1 60 10) +R3 N006 N005 {Ri} +D3 + N008 Dideal +V5 N008 - PWL(0 0 1m {Usclamp}) +.model Sideal SW(Ron=1m Roff=100MEG Vt=0.5 Vh=-0.1) +.model Dideal D(Ron=1m Roff=1MEG Vfwd=1m epsilon=10m) +.ic V(n003)={Us} +.ends 4-6-4_24V_LoadDumpWithoutSuppressionTestA + +.subckt 4-6-4_12V_LoadDumpWithSuppressionTestB + - +.param Ua=14 +.param Us=101 +.param UsClamp=35 +.param Ri=0.5 +.param t0=1 +.param Creservoir=0.15 Rshunt=1.55 +L1 N004 N005 2m +D1 N007 + Dideal +V2 N007 - PWL(0 0 1m {Ua}) +R1 N005 - {Rshunt} +D2 N006 + Dideal +C1 N003 - {Creservoir} +R2 N003 N002 100 +V3 N002 - PWL(0 0 1m {Us}) +S1 N004 N003 N001 0 Sideal +V4 N001 0 PULSE(0 1 {t0} +1n +1n 1 60 10) +R3 N006 N005 {Ri} +D3 + N008 Dideal +V5 N008 - PWL(0 0 1m {Usclamp}) +.model Sideal SW(Ron=1m Roff=100MEG Vt=0.5 Vh=-0.1) +.model Dideal D(Ron=1m Roff=1MEG Vfwd=1m epsilon=10m) +.ic V(n003)={Us} +.ends 4-6-4_12V_LoadDumpWithSuppressionTestB + +.subckt 4-6-4_24V_LoadDumpWithSuppressionTestB + - +.param Ua=28 +.param Us=202 +.param UsClamp=58 +.param Ri=1 +.param t0=1 +.param Creservoir=0.15 Rshunt=1.55 +L1 N004 N005 2m +D1 N007 + Dideal +V2 N007 - PWL(0 0 1m {Ua}) +R1 N005 - {Rshunt} +D2 N006 + Dideal +C1 N003 - {Creservoir} +R2 N003 N002 100 +V3 N002 - PWL(0 0 1m {Us}) +S1 N004 N003 N001 0 Sideal +V4 N001 0 PULSE(0 1 {t0} +1n +1n 1 60 10) +R3 N006 N005 {Ri} +D3 + N008 Dideal +V5 N008 - PWL(0 0 1m {Usclamp}) +.model Sideal SW(Ron=1m Roff=100MEG Vt=0.5 Vh=-0.1) +.model Dideal D(Ron=1m Roff=1MEG Vfwd=1m epsilon=10m) +.ic V(n003)={Us} +.ends 4-6-4_24V_LoadDumpWithSuppressionTestB + +.subckt 4-7_12V_ReversedVoltageCase2 + - +V1 + - PWL(0 0 1m {Ua} 100m {Ua} +1u {-1*Ua}) +.param Ua=14 +.ends 4-7_12V_ReversedVoltageCase2 + +.subckt 4-9-1_12V_SingleLineInterruption + - +V3 N002 0 PWL(0 -1 {t0} -1 +1u 1 +10 1 +1u -1) +.param Ua=14 +.param t0=1 +V2 N001 - PWL(0 0 1u {Ua}) +S1 N001 + N002 0 SHORT +.model SHORT SW(Ron=1m Roff=10MEG Vt=0 Vh=-.5) +.ends 4-9-1_12V_SingleLineInterruption + + +.subckt 4-7_24V_ReversedVoltageCase2 + - +V1 + - PWL(0 0 1m {Ua} 100m {Ua} +1u {-1*Ua}) +.param Ua=28 +.ends 4-7_24V_ReversedVoltageCase2 + +.subckt 4-9-1_24V_SingleLineInterruption + - +.param Ua=28 +.param t0=1 +V2 N001 - PWL(0 0 1u {Ua}) +S1 N001 + N002 0 SHORT +V3 N002 0 PWL(0 -1 {t0} -1 +1u 1 +10 1 +1u -1) +.model SHORT SW(Ron=1m Roff=10MEG Vt=0 Vh=-.5) +.ends 4-9-1_24V_SingleLineInterruption \ No newline at end of file diff --git a/spice/copy/sub/ISO7637-2.lib b/spice/copy/sub/ISO7637-2.lib new file mode 100755 index 0000000..e064dc5 --- /dev/null +++ b/spice/copy/sub/ISO7637-2.lib @@ -0,0 +1,148 @@ +* Copyright (c) 2017 Linear Technology Corporation. All rights reserved. +* Author: Dan Eddleman +* +* Automotive Transient Models (ISO-7637-2) +*************************************************************** + +.subckt Pulse1_12V + - +.param Ua = 13.5 +.param Us = -150 +.param Ri = 10 +.param td = 2m +.param tr = 1u +.param t1 = 0.5 +.param t2 = 200m +.param t3 = 50us +.param t0 = 1m +R2 + - {Ri} +I1 - + EXP(0 {Us/Ri} {t0+t3} {tr/2.2} {t0+t3+(5*tr)} {td/2.305} {t1}) +I2 - + PULSE({Ua/Ri} 0 {t0} 1u 1u {t2} {t1}) +.ends Pulse1_12V + +.subckt Pulse1_24V + - +.param Ua = 27 +.param Us = -600 +.param Ri = 50 +.param td = 1m +.param tr = 3u +.param t1 = 0.5 +.param t2 = 200m +.param t3 = 50us +.param t0 = 1m +R2 + - {Ri} +I1 - + EXP(0 {Us/Ri} {t0+t3} {tr/2.2} {t0+t3+(5*tr)} {td/2.305} {t1}) +I2 - + PULSE({Ua/Ri} 0 {t0} 1u 1u {t2} {t1}) +.ends Pulse1_24V + +.subckt Pulse2a_12V + - +.param Ua = 13.5 +.param Us = 112 +.param Ri = 2 +.param td = 50u +.param tr = 1u +.param t1 = 0.2 +.param t0 = 1m +R1 + - {Ri} +I3 - + EXP({Ua/Ri} {(Ua+Us)/Ri} {t0} {tr/2.2} {t0+(2*tr)} {td/2.305} {t1}) +.ends Pulse2a_12V + + +.subckt Pulse2a_24V + - +.param Ua = 27 +.param Us = 112 +.param Ri = 2 +.param td = 50u +.param tr = 1u +.param t1 = 0.2 +.param t0 = 1m +R1 + - {Ri} +I3 - + EXP({Ua/Ri} {(Ua+Us)/Ri} {t0} {tr/2.2} {t0+(2*tr)} {td/2.305} {t1}) +.ends Pulse2a_24V + +.subckt Pulse2b_12V + - +.param Ua = 13.5 +.param Us = 10 +.param Ri = 0.05 +.param td = 0.2 +.param tr = 1m +.param t12 = 1m +.param t6=1m +.param t0 = 1m +.param ton=1 +.param trep = 5 +R1 + - {Ri} +I3 - + EXP(0 {Us/Ri} {t0+t12+t6} {tr/2.2} {t0+t12+(2*tr)} {td/2.305} {trep}) +I1 - + PULSE({Ua/Ri} 0 {t0} {t12} {t12} {trep-ton} {trep}) +.ends Pulse2b_12V + +.subckt Pulse2b_24V + - +.param Ua = 27 +.param Us = 20 +.param Ri = 0.05 +.param td = 0.2 +.param tr = 1m +.param t12 = 1m +.param t6=1m +.param t0 = 1m +.param ton=1 +.param trep = 5 +R1 + - {Ri} +I3 - + EXP(0 {Us/Ri} {t0+t12+t6} {tr/2.2} {t0+t12+(2*tr)} {td/2.305} {trep}) +I1 - + PULSE({Ua/Ri} 0 {t0} {t12} {t12} {trep-ton} {trep}) +.ends Pulse2b_24V + +.subckt Pulse3a_12V + - +.param Ua = 13.5V +.param Us = -220V +.param Ri = 50 +.param td = 150ns +.param tr = 5ns +.param t1 = 100u +.param t4 = 10ms +.param t5 = 90ms +.param t0 = 1ms +R2 + - {Ri} +I1 - + EXP({Ua/Ri} {(Us+Ua)/Ri} {t0} {tr/2.2} {t0+(2*tr)} {td/2.305} {t1} {t4/t1} {(t4+t5)}) +.ends Pulse3a_12V + +.subckt Pulse3a_24V + - +.param Ua = 27V +.param Us = -300V +.param Ri = 50 +.param td = 150ns +.param tr = 5ns +.param t1 = 100u +.param t4 = 10ms +.param t5 = 90ms +.param t0 = 1ms +R2 + - {Ri} +I1 - + EXP({Ua/Ri} {(Us+Ua)/Ri} {t0} {tr/2.2} {t0+(2*tr)} {td/2.305} {t1} {t4/t1} {(t4+t5)}) +.ends Pulse3a_24V + +.subckt Pulse3b_12V + - +.param Ua = 13.5 +.param Us = 150 +.param Ri = 50 +.param td = 150n +.param tr = 5n +.param t1 = 100u +.param t4 = 10m +.param t5 = 90m +.param t0 = 1m +R1 + - {Ri} +I2 - + EXP({Ua/Ri} {(Us+Ua)/Ri} {t0} {tr/2.2} {t0+(2*tr)} {td/2.305} {t1} {t4/t1} {(t4+t5)}) +.ends Pulse3b_12V + +.subckt Pulse3b_24V + - +.param Ua = 27 +.param Us = 300 +.param Ri = 50 +.param td = 150n +.param tr = 5n +.param t1 = 100u +.param t4 = 10m +.param t5 = 90m +.param t0 = 1m +R1 + - {Ri} +I2 - + EXP({Ua/Ri} {(Us+Ua)/Ri} {t0} {tr/2.2} {t0+(2*tr)} {td/2.305} {t1} {t4/t1} {(t4+t5)}) +.ends Pulse3b_24V diff --git a/spice/copy/sub/LT1021-10.sub b/spice/copy/sub/LT1021-10.sub new file mode 100755 index 0000000..b76ff5a Binary files /dev/null and b/spice/copy/sub/LT1021-10.sub differ diff --git a/spice/copy/sub/LT1021-5.sub b/spice/copy/sub/LT1021-5.sub new file mode 100755 index 0000000..ae6ffd5 Binary files /dev/null and b/spice/copy/sub/LT1021-5.sub differ diff --git a/spice/copy/sub/LT1021-7.sub b/spice/copy/sub/LT1021-7.sub new file mode 100755 index 0000000..43e29ba Binary files /dev/null and b/spice/copy/sub/LT1021-7.sub differ diff --git a/spice/copy/sub/LT1026.sub b/spice/copy/sub/LT1026.sub new file mode 100755 index 0000000..79a9fa7 Binary files /dev/null and b/spice/copy/sub/LT1026.sub differ diff --git a/spice/copy/sub/LT1054.sub b/spice/copy/sub/LT1054.sub new file mode 100755 index 0000000..8889617 Binary files /dev/null and b/spice/copy/sub/LT1054.sub differ diff --git a/spice/copy/sub/LT1054L.sub b/spice/copy/sub/LT1054L.sub new file mode 100755 index 0000000..1e09e3f Binary files /dev/null and b/spice/copy/sub/LT1054L.sub differ diff --git a/spice/copy/sub/LT1070.sub b/spice/copy/sub/LT1070.sub new file mode 100755 index 0000000..c36b3c7 Binary files /dev/null and b/spice/copy/sub/LT1070.sub differ diff --git a/spice/copy/sub/LT1071.sub b/spice/copy/sub/LT1071.sub new file mode 100755 index 0000000..f13a0ab Binary files /dev/null and b/spice/copy/sub/LT1071.sub differ diff --git a/spice/copy/sub/LT1072.sub b/spice/copy/sub/LT1072.sub new file mode 100755 index 0000000..b36fc1b Binary files /dev/null and b/spice/copy/sub/LT1072.sub differ diff --git a/spice/copy/sub/LT1073.sub b/spice/copy/sub/LT1073.sub new file mode 100755 index 0000000..3197f34 Binary files /dev/null and b/spice/copy/sub/LT1073.sub differ diff --git a/spice/copy/sub/LT1074.sub b/spice/copy/sub/LT1074.sub new file mode 100755 index 0000000..f7793cf Binary files /dev/null and b/spice/copy/sub/LT1074.sub differ diff --git a/spice/copy/sub/LT1076-5.sub b/spice/copy/sub/LT1076-5.sub new file mode 100755 index 0000000..a1f35fc Binary files /dev/null and b/spice/copy/sub/LT1076-5.sub differ diff --git a/spice/copy/sub/LT1076.sub b/spice/copy/sub/LT1076.sub new file mode 100755 index 0000000..796e1a1 Binary files /dev/null and b/spice/copy/sub/LT1076.sub differ diff --git a/spice/copy/sub/LT1082.sub b/spice/copy/sub/LT1082.sub new file mode 100755 index 0000000..54984cb Binary files /dev/null and b/spice/copy/sub/LT1082.sub differ diff --git a/spice/copy/sub/LT1083.lib b/spice/copy/sub/LT1083.lib new file mode 100755 index 0000000..35134e5 --- /dev/null +++ b/spice/copy/sub/LT1083.lib @@ -0,0 +1,485 @@ +* Copyright © Linear Technology Corp. 2012. All rights reserved. +* +.subckt LT1083-12 1 2 3 +Q1 N003 2 N006 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 N006 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +R8 2 N006 242 +R9 N006 1 2.074K +D2 3 2 2mA +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=3K) +.ends LT1083-12 +* +.subckt LT1083-5 1 2 3 +Q1 N003 2 N006 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 N006 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +R8 2 N006 242 +R9 N006 1 730 +D2 3 2 2mA +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=3K) +.ends LT1083-5 +* +.subckt LT1083 1 2 3 +Q1 N003 2 1 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 1 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=3K) +.ends LT1083 +* +.subckt LT1084-12 1 2 3 +Q1 N003 2 N006 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 N006 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +R8 2 N006 242 +R9 N006 1 2.076K +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=2K) +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.ends LT1084-12 +* +.subckt LT1084-3.3 1 2 3 +Q1 N003 2 N006 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 N006 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +R8 2 N006 242 +R9 N006 1 397 +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=2K) +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.ends LT1084-3.3 +* +.subckt LT1084-5 1 2 3 +Q1 N003 2 N006 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 N006 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +R8 2 N006 242 +R9 N006 1 725 +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=2K) +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.ends LT1084-5 +* +.subckt LT1084 1 2 3 +Q1 N003 2 1 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 1 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=2K) +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.ends LT1084 +* +.subckt LT1085-12 1 2 3 +Q1 N003 2 N006 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 N006 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +R2 2 N006 242 +R8 N006 1 2.076K +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=1.2K) +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.ends LT1085-12 +* +.subckt LT1085-3.3 1 2 3 +Q1 N003 2 N006 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 N006 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +R2 2 N006 242 +R8 N006 1 397 +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=1.2K) +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.ends LT1085-3.3 +* +.subckt LT1085-3.6 1 2 3 +Q1 N003 2 N006 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 N006 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +R2 2 N006 242 +R8 N006 1 455 +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=1.2K) +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.ends LT1085-3.6 +* +.subckt LT1085-5 1 2 3 +Q1 N003 2 N006 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 N006 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +R2 2 N006 242 +R8 N006 1 725 +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=1.2K) +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.ends LT1085-5 +* +.subckt LT1085 1 2 3 +Q1 N003 2 1 0 N temp=27 +Q3 3 N002 2 0 NP +I2 3 N003 55µ +Q7 3 N003 N004 0 NA +Q12 2 N004 N002 0 PA +I1 N004 2 100µ +D1 N002 3 D +G1 N002 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N002 100K +G3 3 N002 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N002 1 1Meg +C3 3 N004 500p Rser=5K +D3 N003 3 D +R7 3 N003 150Meg +D2 3 2 2mA +.model D D(Ron=1 Roff=1T) +.model N NPN(BF=125 Cjc=40p Re=9.87K) +.model NA NPN(BF=125) +.model PA PNP(BF=80) +.model NP NPN(BF=1.2K) +.model 2mA D(Ron=250 Roff=100 Ilimit=2m) +.ends LT1085 +* +.subckt LT1086-12 1 2 3 +Q1 N002 2 N001 0 N temp=27 +R2 N001 N005 9.87K +Q3 3 N007 2 0 NP +I2 3 N002 55µ +Q7 3 N002 N006 0 NA +Q12 2 N006 N007 0 PA +I1 N006 2 100µ +D1 N007 3 D +G1 N007 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N007 100K +G3 3 N007 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N007 N005 1Meg +I4 3 2 1.5m load +C3 3 N006 500p Rser=5K +D3 N002 3 D +R7 3 N002 150Meg +R8 2 N005 242 +R5 1 N005 2.075K +.model N NPN(BF=125 Cjc=40p) +.model NP NPN(BF=600) +.model D D(Ron=1 Roff=1T) +.model PA PNP(BF=80) +.model NA NPN(BF=125) +.ends LT1086-12 +* +.subckt LT1086-2.85 1 2 3 +Q1 N002 2 N001 0 N temp=27 +R2 N001 N005 9.87K +Q3 3 N007 2 0 NP +I2 3 N002 55µ +Q7 3 N002 N006 0 NA +Q12 2 N006 N007 0 PA +I1 N006 2 100µ +D1 N007 3 D +G1 N007 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N007 100K +G3 3 N007 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N007 N005 1Meg +I4 3 2 1.5m load +C3 3 N006 500p Rser=5K +D3 N002 3 D +R7 3 N002 150Meg +R8 2 N005 242 +R5 1 N005 310.1 +.model N NPN(BF=125 Cjc=40p) +.model NP NPN(BF=600) +.model D D(Ron=1 Roff=1T) +.model PA PNP(BF=80) +.model NA NPN(BF=125) +.ends LT1086-2.85 +* +.subckt LT1086-3.3 1 2 3 +Q1 N002 2 N001 0 N temp=27 +R2 N001 N005 9.87K +Q3 3 N007 2 0 NP +I2 3 N002 55µ +Q7 3 N002 N006 0 NA +Q12 2 N006 N007 0 PA +I1 N006 2 100µ +D1 N007 3 D +G1 N007 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N007 100K +G3 3 N007 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N007 N005 1Meg +I4 3 2 1.5m load +C3 3 N006 500p Rser=5K +D3 N002 3 D +R7 3 N002 150Meg +R8 2 N005 242 +R5 1 N005 397 +.model N NPN(BF=125 Cjc=40p) +.model NP NPN(BF=600) +.model D D(Ron=1 Roff=1T) +.model PA PNP(BF=80) +.model NA NPN(BF=125) +.ends LT1086-3.3 +* +.subckt LT1086-3.6 1 2 3 +Q1 N002 2 N001 0 N temp=27 +R2 N001 N005 9.87K +Q3 3 N007 2 0 NP +I2 3 N002 55µ +Q7 3 N002 N006 0 NA +Q12 2 N006 N007 0 PA +I1 N006 2 100µ +D1 N007 3 D +G1 N007 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N007 100K +G3 3 N007 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N007 N005 1Meg +I4 3 2 1.5m load +C3 3 N006 500p Rser=5K +D3 N002 3 D +R7 3 N002 150Meg +R8 2 N005 242 +R5 1 N005 455 +.model N NPN(BF=125 Cjc=40p) +.model NP NPN(BF=600) +.model D D(Ron=1 Roff=1T) +.model PA PNP(BF=80) +.model NA NPN(BF=125) +.ends LT1086-3.6 +* +.subckt LT1086-5 1 2 3 +Q1 N002 2 N001 0 N temp=27 +R2 N001 N005 9.87K +Q3 3 N007 2 0 NP +I2 3 N002 55µ +Q7 3 N002 N006 0 NA +Q12 2 N006 N007 0 PA +I1 N006 2 100µ +D1 N007 3 D +G1 N007 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N007 100K +G3 3 N007 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N007 N005 1Meg +I4 3 2 1.5m load +C3 3 N006 500p Rser=5K +D3 N002 3 D +R7 3 N002 150Meg +R8 2 N005 242 +R5 1 N005 725 +.model N NPN(BF=125 Cjc=40p) +.model NP NPN(BF=600) +.model D D(Ron=1 Roff=1T) +.model PA PNP(BF=80) +.model NA NPN(BF=125) +.ends LT1086-5 +* +.subckt LT1086 1 2 3 +Q1 N002 2 N001 0 N temp=27 +R2 N001 1 9.87K +Q3 3 N007 2 0 NP +I2 3 N002 55µ +Q7 3 N002 N006 0 NA +Q12 2 N006 N007 0 PA +I1 N006 2 100µ +D1 N007 3 D +G1 N007 3 3 2 table( 10 0 20 2.8m 35 3m) +R3 3 N007 100K +G3 3 N007 3 2 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N007 1 1Meg +I4 3 2 2m load +C3 3 N006 500p Rser=5K +D3 N002 3 D +R7 3 N002 150Meg +.model N NPN(BF=125 Cjc=40p) +.model NP NPN(BF=600) +.model D D(Ron=1 Roff=1T) +.model PA PNP(BF=80) +.model NA NPN(BF=125) +.ends LT1086 +* +.subckt LT1086H 1 2 3 +Q1 N002 3 N001 0 N temp=27 +R2 N001 2 9.87K +Q3 1 N007 3 0 NP +I2 1 N002 55µ +Q7 1 N002 N006 0 NA +Q12 3 N006 N007 0 PA +I1 N006 3 100µ +D1 N007 1 D +G1 N007 1 1 3 table( 10 0 20 2.8m 35 3m) +R3 1 N007 100K +G3 1 N007 1 3 table(0.95,0m 0.969,0.5m 1,1m 1.06,1.5m 1.16,2m 1.34,2.5m 1.64,3m) +R4 N007 2 1Meg +I4 1 3 2m load +C3 1 N006 500p Rser=5K +D3 N002 1 D +R7 1 N002 150Meg +.model N NPN(BF=125 Cjc=40p) +.model NP NPN(BF=300) +.model D D(Ron=1 Roff=1T) +.model PA PNP(BF=80) +.model NA NPN(BF=125) +.ends LT1086H diff --git a/spice/copy/sub/LT1103.sub b/spice/copy/sub/LT1103.sub new file mode 100755 index 0000000..59a9547 Binary files /dev/null and b/spice/copy/sub/LT1103.sub differ diff --git a/spice/copy/sub/LT1105.sub b/spice/copy/sub/LT1105.sub new file mode 100755 index 0000000..a8b317d Binary files /dev/null and b/spice/copy/sub/LT1105.sub differ diff --git a/spice/copy/sub/LT1106.sub b/spice/copy/sub/LT1106.sub new file mode 100755 index 0000000..556bebe Binary files /dev/null and b/spice/copy/sub/LT1106.sub differ diff --git a/spice/copy/sub/LT1107.sub b/spice/copy/sub/LT1107.sub new file mode 100755 index 0000000..6588760 Binary files /dev/null and b/spice/copy/sub/LT1107.sub differ diff --git a/spice/copy/sub/LT1108.sub b/spice/copy/sub/LT1108.sub new file mode 100755 index 0000000..7952229 Binary files /dev/null and b/spice/copy/sub/LT1108.sub differ diff --git a/spice/copy/sub/LT1109.sub b/spice/copy/sub/LT1109.sub new file mode 100755 index 0000000..4c7b6f4 Binary files /dev/null and b/spice/copy/sub/LT1109.sub differ diff --git a/spice/copy/sub/LT1109A.sub b/spice/copy/sub/LT1109A.sub new file mode 100755 index 0000000..a4ad9e8 Binary files /dev/null and b/spice/copy/sub/LT1109A.sub differ diff --git a/spice/copy/sub/LT1110.sub b/spice/copy/sub/LT1110.sub new file mode 100755 index 0000000..4bb741a Binary files /dev/null and b/spice/copy/sub/LT1110.sub differ diff --git a/spice/copy/sub/LT1111.sub b/spice/copy/sub/LT1111.sub new file mode 100755 index 0000000..6716ed7 Binary files /dev/null and b/spice/copy/sub/LT1111.sub differ diff --git a/spice/copy/sub/LT1117.lib b/spice/copy/sub/LT1117.lib new file mode 100755 index 0000000..4fdd25d --- /dev/null +++ b/spice/copy/sub/LT1117.lib @@ -0,0 +1,91 @@ +* Copyright © Linear Technology Corp. 2012. All rights reserved. +* +.subckt LT1117-2.85 1 2 3 +C4 3 COM 10p +C5 2 COM 5p +M1 N001 N005 2 2 Q temp=27 +D1 3 2 IM +D2 3 N001 DO +G2 3 N005 3 2 13n +D3 3 COM 55uA +G1 N005 2 2 N004 100µ +C1 2 N005 50p Rpar=10K noiseless +C3 N001 3 10p +C2 2 N004 5n +A1 2 COM 2 2 2 2 N004 2 OTA g=100u Iout=10u Ref=1.259 Vhigh=10 Vlow=-10 +D5 N004 2 10K +R1 2 COM 250 noiseless +R2 COM 1 313 noiseless +.model Q VDMOS(Vto=0 Kp=800K) +.model IM D(Ron=100 Vfwd=.6 epsilon=.2 Ilimit=1.7m noiseless) +.model DO D(Ron=.1 epsilon=.07 Vfwd=.95 Ilimit=.95 noiseless) +.model 55uA D(Ron=10K Roff=10K Ilimit=55u noiseless) +.model 10K D(Ron=1 Roff=10K Vfwd=3m Vrev=3m epsilon=100m revepsilon=100m noiseless) +.ends LT1117-2.85 +* +.subckt LT1117-3.3 1 2 3 +C4 3 COM 10p +C5 2 COM 5p +M1 N001 N005 2 2 Q temp=27 +D1 3 2 IM +D2 3 N001 DO +G2 3 N005 3 2 13n +D3 3 COM 55uA +G1 N005 2 2 N004 100µ +C1 2 N005 50p Rpar=10K noiseless +C3 N001 3 10p +C2 2 N004 5n +A1 2 COM 2 2 2 2 N004 2 OTA g=100u Iout=10u Ref=1.259 Vhigh=10 Vlow=-10 +D5 N004 2 10K +R1 2 COM 250 noiseless +R2 COM 1 401 noiseless +.model Q VDMOS(Vto=0 Kp=800K) +.model IM D(Ron=100 Vfwd=.6 epsilon=.2 Ilimit=1.7m noiseless) +.model DO D(Ron=.1 epsilon=.07 Vfwd=.95 Ilimit=.95 noiseless) +.model 55uA D(Ron=10K Roff=10K Ilimit=55u noiseless) +.model 10K D(Ron=1 Roff=10K Vfwd=3m Vrev=3m epsilon=100m revepsilon=100m noiseless) +.ends LT1117-3.3 +* +.subckt LT1117-5 1 2 3 +C4 3 COM 10p +C5 2 COM 5p +M1 N001 N005 2 2 Q temp=27 +D1 3 2 IM +D2 3 N001 DO +G2 3 N005 3 2 13n +D3 3 COM 55uA +G1 N005 2 2 N004 100µ +C1 2 N005 50p Rpar=10K noiseless +C3 N001 3 10p +C2 2 N004 5n +A1 2 COM 2 2 2 2 N004 2 OTA g=100u Iout=10u Ref=1.259 Vhigh=10 Vlow=-10 +D5 N004 2 10K +R1 2 COM 250 noiseless +R2 COM 1 735 noiseless +.model Q VDMOS(Vto=0 Kp=800K) +.model IM D(Ron=100 Vfwd=.6 epsilon=.2 Ilimit=1.7m noiseless) +.model DO D(Ron=.1 epsilon=.07 Vfwd=.95 Ilimit=.95 noiseless) +.model 55uA D(Ron=10K Roff=10K Ilimit=55u noiseless) +.model 10K D(Ron=1 Roff=10K Vfwd=3m Vrev=3m epsilon=100m revepsilon=100m noiseless) +.ends LT1117-5 +* +.subckt LT1117 1 2 3 +C4 3 1 10p +C5 2 1 5p +M1 N001 N005 2 2 Q temp=27 +D1 3 2 IM +D2 3 N001 DO +G2 3 N005 3 2 13n +D3 3 1 55uA +G1 N005 2 2 N004 100µ +C1 2 N005 50p Rpar=10K noiseless +C3 N001 3 10p +C2 2 N004 5n +A1 2 1 2 2 2 2 N004 2 OTA g=100u Iout=10u Ref=1.259 Vhigh=10 Vlow=-10 +D5 N004 2 10K +.model Q VDMOS(Vto=0 Kp=800K) +.model IM D(Ron=100 Vfwd=.6 epsilon=.2 Ilimit=1.7m noiseless) +.model DO D(Ron=.1 epsilon=.07 Vfwd=.95 Ilimit=.95 noiseless) +.model 55uA D(Ron=10K Roff=10K Ilimit=55u noiseless) +.model 10K D(Ron=1 Roff=10K Vfwd=3m Vrev=3m epsilon=100m revepsilon=100m noiseless) +.ends LT1117 diff --git a/spice/copy/sub/LT1118.lib b/spice/copy/sub/LT1118.lib new file mode 100755 index 0000000..c354814 --- /dev/null +++ b/spice/copy/sub/LT1118.lib @@ -0,0 +1,164 @@ +* Copyright © Linear Technology Corp. 2012. All rights reserved. +* +.subckt LT1118-2.5 1 2 3 4 5 6 +C4 5 1 10p +C5 6 1 50p +M1 N005 N008 6 6 Q temp=27 +D2 5 N005 DO +G2 5 N008 5 6 .5µ +G1 N008 6 6 N007 100µ +C1 6 N008 .1p Rpar=10K noiseless +C3 N005 5 10p +C2 6 N007 50p Rpar=2Meg Rser=30K +A1 4 1 6 6 6 6 N007 6 OTA g=50u Iout=10u Ref=1.225 Vhigh=1 Vlow=-1 +A2 5 1 1 1 1 1 N004 1 SCHMITT Vt=2 Vh=1m +A3 3 1 1 1 1 1 N002 1 SCHMITT Vt=1.4 Vh=1m +C6 3 1 1p +A4 1 N002 1 N004 1 1 N003 1 AND tau=1u +D4 3 1 1uA m=.1 +S1 6 N008 1 N003 SD +S2 6 N007 1 N003 SD +D1 1 6 S +S3 N009 1 1 N003 SD +G3 1 N009 6 N007 100µ +C7 N009 1 .1p Rpar=10K noiseless +M2 6 N009 1 1 Q temp=27 +D5 6 5 S +D6 N009 1 L +D7 4 1 1uA m=.35 +D3 5 1 1uA +S4 5 1 N003 1 600uA +D8 6 N007 L N=3 +D9 N007 6 L N=3 +R3 6 4 51.4K +C9 4 1 .5p Rpar=50K +.model Q VDMOS(Vto=2m Kp=100) +.model DO D(Ron=.25 epsilon=.1 Vfwd=.8 Ilimit=1.2 noiseless) +.model 1uA D(Ron=50K Roff=50K Ilimit=1u noiseless) +.model SD SW(Ron=100 Roff=1G Vt=-.5 Vh=-.4) +.model S D(Ron=1 epsilon=2) +.model L D(Ron=100 Vfwd=110m epsilon=24m) +.model 600uA SW(Ron=50 Roff=1G Vt=.5 Vh=-.4 Ilimit=600u level=2) +.ends LT1118-2.5 +* +.subckt LT1118-2.85 1 2 3 4 5 6 +C4 5 1 10p +C5 6 1 50p +M1 N005 N008 6 6 Q temp=27 +D2 5 N005 DO +G2 5 N008 5 6 .5µ +G1 N008 6 6 N007 100µ +C1 6 N008 .1p Rpar=10K noiseless +C3 N005 5 10p +C2 6 N007 50p Rpar=2Meg Rser=30K +A1 4 1 6 6 6 6 N007 6 OTA g=50u Iout=10u Ref=1.225 Vhigh=1 Vlow=-1 +A2 5 1 1 1 1 1 N004 1 SCHMITT Vt=2 Vh=1m +A3 3 1 1 1 1 1 N002 1 SCHMITT Vt=1.4 Vh=1m +C6 3 1 1p +A4 1 N002 1 N004 1 1 N003 1 AND tau=1u +D4 3 1 1uA m=.1 +S1 6 N008 1 N003 SD +S2 6 N007 1 N003 SD +D1 1 6 S +S3 N009 1 1 N003 SD +G3 1 N009 6 N007 100µ +C7 N009 1 .1p Rpar=10K noiseless +M2 6 N009 1 1 Q temp=27 +D5 6 5 S +D6 N009 1 L +D7 4 1 1uA m=.35 +D3 5 1 1uA +S4 5 1 N003 1 600uA +D8 6 N007 L N=3 +D9 N007 6 L N=3 +R3 6 4 65.39K +C9 4 1 .5p Rpar=50K +.model Q VDMOS(Vto=2m Kp=100) +.model DO D(Ron=.25 epsilon=.1 Vfwd=.8 Ilimit=1.2 noiseless) +.model 1uA D(Ron=50K Roff=50K Ilimit=1u noiseless) +.model SD SW(Ron=100 Roff=1G Vt=-.5 Vh=-.4) +.model S D(Ron=1 epsilon=2) +.model L D(Ron=100 Vfwd=110m epsilon=24m) +.model 600uA SW(Ron=50 Roff=1G Vt=.5 Vh=-.4 Ilimit=600u level=2) +.ends LT1118-2.85 +* +.subckt LT1118-5 1 2 3 4 5 6 +C4 5 1 10p +C5 6 1 50p +M1 N005 N008 6 6 Q temp=27 +D2 5 N005 DO +G2 5 N008 5 6 .5µ +G1 N008 6 6 N007 100µ +C1 6 N008 .1p Rpar=10K noiseless +C3 N005 5 10p +C2 6 N007 50p Rpar=2Meg Rser=30K +A1 4 1 6 6 6 6 N007 6 OTA g=50u Iout=10u Ref=1.225 Vhigh=1 Vlow=-1 +A2 5 1 1 1 1 1 N004 1 SCHMITT Vt=2 Vh=1m +A3 3 1 1 1 1 1 N002 1 SCHMITT Vt=1.4 Vh=1m +C6 3 1 1p +A4 1 N002 1 N004 1 1 N003 1 AND tau=1u +D4 3 1 1uA m=.1 +S1 6 N008 1 N003 SD +S2 6 N007 1 N003 SD +D1 1 6 S +S3 N009 1 1 N003 SD +G3 1 N009 6 N007 100µ +C7 N009 1 .1p Rpar=10K noiseless +M2 6 N009 1 1 Q temp=27 +D5 6 5 S +D6 N009 1 L +D7 4 1 1uA m=.35 +D3 5 1 1uA +S4 5 1 N003 1 600uA +D8 6 N007 L N=3 +D9 N007 6 L N=3 +R3 6 4 151.9K +C9 4 1 .5p Rpar=50K +.model Q VDMOS(Vto=2m Kp=100) +.model DO D(Ron=.25 epsilon=.1 Vfwd=.8 Ilimit=1.2 noiseless) +.model 1uA D(Ron=50K Roff=50K Ilimit=1u noiseless) +.model SD SW(Ron=100 Roff=1G Vt=-.5 Vh=-.4) +.model S D(Ron=1 epsilon=2) +.model L D(Ron=100 Vfwd=110m epsilon=24m) +.model 600uA SW(Ron=50 Roff=1G Vt=.5 Vh=-.4 Ilimit=600u level=2) +.ends LT1118-5 +* +.subckt LT1118 1 2 3 4 5 6 +C4 5 1 10p +C5 6 1 50p +M1 N005 N008 6 6 Q temp=27 +D2 5 N005 DO +G2 5 N008 5 6 .5µ +G1 N008 6 6 N007 100µ +C1 6 N008 .1p Rpar=10K noiseless +C3 N005 5 10p +C2 6 N007 50p Rpar=2Meg Rser=30K +A1 4 1 6 6 6 6 N007 6 OTA g=50u Iout=10u Ref=1.225 Vhigh=1 Vlow=-1 +A2 5 1 1 1 1 1 N004 1 SCHMITT Vt=2 Vh=1m +A3 3 1 1 1 1 1 N002 1 SCHMITT Vt=1.4 Vh=1m +C6 3 1 1p +A4 1 N002 1 N004 1 1 N003 1 AND tau=1u +D4 3 1 1uA m=.1 +S1 6 N008 1 N003 SD +S2 6 N007 1 N003 SD +D1 1 6 S +S3 N010 1 1 N003 SD +G3 1 N010 6 N007 100µ +C7 N010 1 .1p Rpar=10K noiseless +M2 6 N010 1 1 Q temp=27 +D5 6 5 S +D6 N010 1 L +D7 4 1 1uA m=.35 +D3 5 1 1uA +S4 5 1 N003 1 600uA +D8 6 N007 L N=3 +D9 N007 6 L N=3 +C9 4 1 .5p +.model Q VDMOS(Vto=2m Kp=100) +.model DO D(Ron=.25 epsilon=.1 Vfwd=.8 Ilimit=1.2 noiseless) +.model 1uA D(Ron=50K Roff=50K Ilimit=1u noiseless) +.model SD SW(Ron=100 Roff=1G Vt=-.5 Vh=-.4) +.model S D(Ron=1 epsilon=2) +.model L D(Ron=100 Vfwd=110m epsilon=24m) +.model 600uA SW(Ron=50 Roff=1G Vt=.5 Vh=-.4 Ilimit=600u level=2) +.ends LT1118 diff --git a/spice/copy/sub/LT1121.lib b/spice/copy/sub/LT1121.lib new file mode 100755 index 0000000..962f480 --- /dev/null +++ b/spice/copy/sub/LT1121.lib @@ -0,0 +1,125 @@ +* Copyright © Linear Technology Corp. 2017. All rights reserved. +* +.subckt LT1121-3.3 1 2 3 4 5 6 7 8 +Q1 N9 N1 8 0 PN +Q2 N1 N2 3 0 NA +Q3 N2 N3 N5 0 NP temp=27 +C1 N2 N3 20p Rser=300K +Q4 N3 N3 N4 0 NP 10 temp=27 +R3 N5 3 2.4K +C2 1 N3 20p Rser=20K +Q5 1 1 N6 0 FB temp=27 +R6 N4 N6 81K +I1 8 5 6µ load +G2 8 N3 N8 3 7µ +G1 8 N2 N8 3 7µ +R1 8 N1 150K +R8 N9 1 1.1 +D3 0 N10 F +G3 0 N10 1 N9 10m +Q7 N3 N1 N9 0 P 10m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +G5 N10 0 N8 3 table(0 3m 1 0) +D2 5 3 A +D4 3 5 B +I2 0 N10 3m +C4 8 N2 50p Rser=.1G +C8 8 N3 500p Rser=.1G Rpar=3G +R4 N4 3 2K +A1 5 3 3 3 3 3 N8 3 SCHMITT vt=.95 vh=1m trise=2u +A2 N10 0 N2 N2 N2 N2 3 N2 VARISTOR +.model PN PNP(BF=25 Cje=500p Cjc=500p) +.model NA NPN(BF=150K Cje=1p Cjc=1p Re=40) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.6) +.model B D(Ron=2 Vrev=7.5 Vfwd=.6) +.ends LT1121-3.3 +* +.subckt LT1121-5 1 2 3 4 5 6 7 8 +Q1 N9 N1 8 0 PN +Q2 N1 N2 3 0 NA +Q3 N2 N3 N5 0 NP temp=27 +C1 N2 N3 20p Rser=300K +Q4 N3 N3 N4 0 NP 10 temp=27 +R3 N5 3 2.4K +C2 1 N3 20p Rser=20K +Q5 1 1 N6 0 FB temp=27 +R6 N4 N6 135.5K +I1 8 5 6µ load +G2 8 N3 N8 3 7µ +G1 8 N2 N8 3 7µ +R1 8 N1 150K +R8 N9 1 1.1 +D3 0 N10 F +G3 0 N10 1 N9 10m +Q7 N3 N1 N9 0 P 10m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +G5 N10 0 N8 3 table(0 3m 1 0) +D2 5 3 A +D4 3 5 B +I2 0 N10 3m +C4 8 N2 50p Rser=.1G +C8 8 N3 500p Rser=.1G Rpar=3G +R4 N4 3 2K +A1 5 3 3 3 3 3 N8 3 SCHMITT vt=.95 vh=1m trise=2u +A2 N10 0 N2 N2 N2 N2 3 N2 VARISTOR +.model PN PNP(BF=25 Cje=500p Cjc=500p) +.model NA NPN(BF=150K Cje=1p Cjc=1p Re=40) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.6) +.model B D(Ron=2 Vrev=7.5 Vfwd=.6) +.ends LT1121-5 +* +.subckt LT1121 1 2 3 4 5 6 7 8 +Q1 N9 N1 8 0 PN +Q2 N1 N2 3 0 NA +Q3 N2 N3 N5 0 NP temp=27 +C1 N2 N3 20p Rser=300K +Q4 N3 N3 N4 0 NP 10 temp=27 +R3 N5 3 2.4K +C2 1 N3 20p Rser=20K +Q5 1 2 N6 0 FB temp=27 +R6 N4 N6 95.4K +I1 8 5 6µ load +G2 8 N3 N8 3 7µ +G1 8 N2 N8 3 7µ +R1 8 N1 150K +R8 N9 1 1.1 +D3 0 N10 F +G3 0 N10 1 N9 10m +Q7 N3 N1 N9 0 P 10m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +G5 N10 0 N8 3 table(0 3m 1 0) +D2 5 3 A +D4 3 5 B +I2 0 N10 3m +C4 8 N2 50p Rser=.1G +C6 2 3 10p +C8 8 N3 500p Rser=.1G Rpar=3G +R4 N4 3 2K +A1 5 3 3 3 3 3 N8 3 SCHMITT vt=.95 vh=1m trise=2u +A2 N10 0 N2 N2 N2 N2 3 N2 VARISTOR +.model PN PNP(BF=25 Cje=500p Cjc=500p) +.model NA NPN(BF=150K Cje=1p Cjc=1p Re=40) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.6) +.model B D(Ron=2 Vrev=7.5 Vfwd=.6) +.ends LT1121 diff --git a/spice/copy/sub/LT1129.lib b/spice/copy/sub/LT1129.lib new file mode 100755 index 0000000..2d96689 --- /dev/null +++ b/spice/copy/sub/LT1129.lib @@ -0,0 +1,127 @@ +* Copyright © Linear Technology Corp. 2004. All rights reserved. +* +.subckt LT1129-3.3 1 2 3 4 5 +Q1 N009 N001 5 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N006 0 NP temp=27 +C1 N002 N003 20p Rser=200K +Q4 N003 N003 N005 0 NP 10 temp=27 +R2 N005 3 2K +R3 N006 3 2.4K +C2 1 N003 20p Rser=2K +Q5 1 2 N007 0 FB temp=27 +R6 N007 N005 80.9K +I1 5 4 6µ load +G2 5 N003 N008 3 7µ +G1 5 N002 N008 3 7µ +R1 5 N001 37K +R8 N009 1 .23 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 5 1 X +C5 1 3 10p +C7 5 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 4 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 4 3 A +D4 3 4 B +I2 0 N010 3m +C4 5 N002 5p Rser=.4G +C6 2 3 1p +C8 5 N003 500p Rser=.27G Rpar=3G +.model PN PNP(BF=25 Cje=500p Cjc=500p tf=100n) +.model NA NPN(BF=1Meg Cje=1p Cjc=1p Re=10) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.6) +.model B D(Ron=2 Vrev=7.5 Vfwd=.6) +.ends LT1129-3.3 +* +.subckt LT1129-5 1 2 3 4 5 +Q1 N009 N001 5 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N006 0 NP temp=27 +C1 N002 N003 20p Rser=200K +Q4 N003 N003 N005 0 NP 10 temp=27 +R2 N005 3 2K +R3 N006 3 2.4K +C2 1 N003 20p Rser=2K +Q5 1 2 N007 0 FB temp=27 +R6 N007 N005 135.1K +I1 5 4 6µ load +G2 5 N003 N008 3 7µ +G1 5 N002 N008 3 7µ +R1 5 N001 37K +R8 N009 1 .23 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 5 1 X +C5 1 3 10p +C7 5 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 4 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 4 3 A +D4 3 4 B +I2 0 N010 3m +C4 5 N002 5p Rser=.4G +C6 2 3 1p +C8 5 N003 500p Rser=.27G Rpar=3G +.model PN PNP(BF=25 Cje=500p Cjc=500p tf=100n) +.model NA NPN(BF=1Meg Cje=1p Cjc=1p Re=10) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.6) +.model B D(Ron=2 Vrev=7.5 Vfwd=.6) +.ends LT1129-5 +* +.subckt LT1129 1 2 3 4 5 +Q1 N009 N001 5 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N006 0 NP temp=27 +C1 N002 N003 20p Rser=200K +Q4 N003 N003 N005 0 NP 10 temp=27 +R2 N005 3 2K +R3 N006 3 2.4K +C2 1 N003 20p Rser=2K +Q5 1 2 N007 0 FB temp=27 +R6 N007 N005 95.2K +I1 5 4 6µ load +G2 5 N003 N008 3 7µ +G1 5 N002 N008 3 7µ +R1 5 N001 37K +R8 N009 1 .23 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 5 1 X +C5 1 3 10p +C7 5 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 4 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 4 3 A +D4 3 4 B +I2 0 N010 3m +C4 5 N002 5p Rser=.4G +C6 2 3 1p +C8 5 N003 500p Rser=.27G Rpar=3G +.model PN PNP(BF=25 Cje=500p Cjc=500p tf=100n) +.model NA NPN(BF=1Meg Cje=1p Cjc=1p Re=10) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.6) +.model B D(Ron=2 Vrev=7.5 Vfwd=.6) +.ends LT1129 diff --git a/spice/copy/sub/LT1158.sub b/spice/copy/sub/LT1158.sub new file mode 100755 index 0000000..5fb034b Binary files /dev/null and b/spice/copy/sub/LT1158.sub differ diff --git a/spice/copy/sub/LT1160.sub b/spice/copy/sub/LT1160.sub new file mode 100755 index 0000000..a7fdc22 Binary files /dev/null and b/spice/copy/sub/LT1160.sub differ diff --git a/spice/copy/sub/LT1161.sub b/spice/copy/sub/LT1161.sub new file mode 100755 index 0000000..0f74037 Binary files /dev/null and b/spice/copy/sub/LT1161.sub differ diff --git a/spice/copy/sub/LT1170.sub b/spice/copy/sub/LT1170.sub new file mode 100755 index 0000000..1be679f Binary files /dev/null and b/spice/copy/sub/LT1170.sub differ diff --git a/spice/copy/sub/LT1171.sub b/spice/copy/sub/LT1171.sub new file mode 100755 index 0000000..f23e626 Binary files /dev/null and b/spice/copy/sub/LT1171.sub differ diff --git a/spice/copy/sub/LT1172.sub b/spice/copy/sub/LT1172.sub new file mode 100755 index 0000000..07bfa57 Binary files /dev/null and b/spice/copy/sub/LT1172.sub differ diff --git a/spice/copy/sub/LT1173.sub b/spice/copy/sub/LT1173.sub new file mode 100755 index 0000000..265cc02 Binary files /dev/null and b/spice/copy/sub/LT1173.sub differ diff --git a/spice/copy/sub/LT1175.lib b/spice/copy/sub/LT1175.lib new file mode 100755 index 0000000..840ed9e --- /dev/null +++ b/spice/copy/sub/LT1175.lib @@ -0,0 +1,83 @@ +* Copyright © Linear Technology Corp. 2012. All rights reserved. +* +.subckt LT1175-5 1 2 3 4 5 6 7 +C4 1 5 10p +C5 3 5 5p +M1 N004 N009 3 3 Q temp=27 +D3 5 1 10uA +G1 N009 3 3 N008 100µ +C1 3 N009 1p Rpar=10K noiseless +C3 N004 1 10p Rpar=2.5 +C2 3 N008 250p Rser=500 Cpar=100p noiseless +A1 4 5 3 3 3 3 N008 3 OTA g=76u Iout=20u Ref=-5 Vhigh=10 Vlow=-10 +D5 3 N008 200K +C9 2 5 10p +C10 7 5 10p +D6 5 4 10uA m=1.2 +C11 4 5 1p +D7 6 1 1uA +D8 6 5 3uA +A2 6 5 5 5 5 5 N001 5 SCHMITT Vt=1.65 Vh=1m Vhigh=2 Rout=10K +A3 6 5 5 5 5 N001 5 5 SCHMITT Vt=-1.65 Vh=1m Vhigh=2 Rout=10K Cout=100p +S1 3 N008 5 N001 SD +S2 1 5 N001 5 IQ +G2 N009 3 3 1 12n +C6 N004 2 10p Rpar=2.5 +C7 N004 7 20p Rpar=1.25 +G4 N009 3 N006 N004 .5 Vto=.25 dir=-1 +B1 1 N006 I=1m/ max(13.5,V(3,1)) Rpar=10K +C12 N006 1 10p +G3 1 5 1 N004 4.16m +G5 1 5 2 N004 4.16m +G6 1 5 7 N004 8.32m +D1 5 3 10uA m=.1 +S4 3 N009 5 N001 SD +.model Q VDMOS(Vto=0 Kp=100 Vto=-10m pchan) +.model 10uA D(Ron=100K Roff=100K Ilimit=10u noiseless) +.model 200K D(Ron=100 Roff=200K Vfwd=.15 Vrev=0 epsilon=.1 revepsilon=.1 noiseless) +.model 1uA D(Ron=100K epsilon=.5 Ilimit=1u noiseless Vrev=8.5 revepsilon=.5 Vfwd=2) +.model 3uA D(Ron=100K epsilon=.5 Ilimit=3u noiseless Vfwd=1 noiseless) +.model SD SW(Ron=1K Roff=1G Vt=-.5 Vh=-.4 noiseless) +.model IQ SW(Ron=2K Roff=1G Vt=.5 Vh=-.4 Ilimit=35u level=2 noiseless) +.ends LT1175-5 +* +.subckt LT1175 1 2 3 4 5 6 7 +C4 1 5 10p +C5 3 5 5p +M1 N004 N008 3 3 Q temp=27 +D3 5 1 10uA +G1 N008 3 3 N007 100µ +C1 3 N008 1p Rpar=10K noiseless +C3 N004 1 10p Rpar=2.5 +C2 3 N007 250p Rser=500 Cpar=100p noiseless +A1 4 5 3 3 3 3 N007 3 OTA g=100u Iout=20u Ref=-3.8 Vhigh=10 Vlow=-10 +D5 3 N007 200K +C9 2 5 10p +C10 7 5 10p +D6 5 4 10uA m=7.5m +C11 4 5 1p +D7 6 1 1uA +D8 6 5 3uA +A2 6 5 5 5 5 5 N001 5 SCHMITT Vt=1.65 Vh=1m Vhigh=2 Rout=10K +A3 6 5 5 5 5 N001 5 5 SCHMITT Vt=-1.65 Vh=1m Vhigh=2 Rout=10K Cout=100p +S1 3 N007 5 N001 SD +S2 1 5 N001 5 IQ +G2 N008 3 3 1 12n +C6 N004 2 10p Rpar=2.5 +C7 N004 7 20p Rpar=1.25 +G4 N008 3 N006 N004 .5 Vto=.25 dir=-1 +B1 1 N006 I=1m/ max(13.5,V(3,1)) Rpar=10K +C12 N006 1 10p +G3 1 5 1 N004 4.16m +G5 1 5 2 N004 4.16m +G6 1 5 7 N004 8.32m +D1 5 3 10uA m=.1 +S4 3 N008 5 N001 SD +.model Q VDMOS(Vto=0 Kp=100 Vto=-10m pchan) +.model 10uA D(Ron=100K Roff=100K Ilimit=10u noiseless) +.model 200K D(Ron=100 Roff=200K Vfwd=.15 Vrev=0 epsilon=.1 revepsilon=.1 noiseless) +.model 1uA D(Ron=100K epsilon=.5 Ilimit=1u noiseless Vrev=8.5 revepsilon=.5 Vfwd=2) +.model 3uA D(Ron=100K epsilon=.5 Ilimit=3u noiseless Vfwd=1 noiseless) +.model SD SW(Ron=1K Roff=1G Vt=-.5 Vh=-.4 noiseless) +.model IQ SW(Ron=2K Roff=1G Vt=.5 Vh=-.4 Ilimit=35u level=2 noiseless) +.ends LT1175 diff --git a/spice/copy/sub/LT1176.sub b/spice/copy/sub/LT1176.sub new file mode 100755 index 0000000..e6e4e00 Binary files /dev/null and b/spice/copy/sub/LT1176.sub differ diff --git a/spice/copy/sub/LT1182.sub b/spice/copy/sub/LT1182.sub new file mode 100755 index 0000000..d537061 Binary files /dev/null and b/spice/copy/sub/LT1182.sub differ diff --git a/spice/copy/sub/LT1183.sub b/spice/copy/sub/LT1183.sub new file mode 100755 index 0000000..3b0743a Binary files /dev/null and b/spice/copy/sub/LT1183.sub differ diff --git a/spice/copy/sub/LT1184.sub b/spice/copy/sub/LT1184.sub new file mode 100755 index 0000000..0be725f Binary files /dev/null and b/spice/copy/sub/LT1184.sub differ diff --git a/spice/copy/sub/LT1184F.sub b/spice/copy/sub/LT1184F.sub new file mode 100755 index 0000000..25561cc Binary files /dev/null and b/spice/copy/sub/LT1184F.sub differ diff --git a/spice/copy/sub/LT1185.lib b/spice/copy/sub/LT1185.lib new file mode 100755 index 0000000..572d8f0 --- /dev/null +++ b/spice/copy/sub/LT1185.lib @@ -0,0 +1,33 @@ +* Copyright © Linear Technology Corp. 2012. All rights reserved. +* +.subckt LT1185 1 2 3 4 5 +C4 3 1 10p +C5 2 1 1p +C1 5 1 10p +M1 N009 1 5 5 R temp=27 +D1 N009 3 1uA +A1 N004 1 N007 3 3 3 N008 3 OTA g=1m Ref=0 Iout=100u Cout=1.2n Rout=350K Vhigh=1 Vlow=-1 +R3 N010 3 .055 +A2 N010 N011 3 3 3 3 N008 3 OTA Isrc=.1u Isink=-1m asym g=10m Ref=.2 Vhigh=100 Vlow=-100 +A3 N010 N009 3 3 3 3 N008 3 OTA Isrc=.1u Isink=-1m asym g=50m Ref=-7m Vhigh=100 Vlow=-100 +C2 N011 3 10p Rpar=4.2K noiseless +B1 N011 3 I=1/13K +1m/min(-13,V(3,2)) +C3 N009 3 10p Rpar=360 noiseless +A4 N009 3 3 3 3 3 N007 3 SCHMITT Vt=195u Vh=10u trise=1u +D2 1 N005 Q1 +D3 1 3 Q2 +G2 1 N004 5 2 100µ +C6 N004 1 20p Rpar=10K Rser=5K +C9 4 3 5p +R6 4 N005 70m +D4 2 3 B +M2 N005 N008 N010 N010 Q temp=27 +G1 1 3 N010 3 .44 +G3 1 3 N008 3 4m Vto=0 dir=1 +.model R VDMOS(Vto=2.39 Kp=50 pchan) +.model 1uA D(Ron=50K Roff=50K Ilimit=2u noiseless) +.model Q VDMOS(Vto=0 Kp=50 lambda=.3) +.model Q1 D(Ron=1K epsilon=2 Ilimit=2.1m noiseless) +.model Q2 D(Ron=15K Vfwd=19 epsilon=2 noiseless) +.model B D(Ron=1.5Meg Roff=1.5Meg Ilimit=.7u) +.ends LT1185 diff --git a/spice/copy/sub/LT1186F.sub b/spice/copy/sub/LT1186F.sub new file mode 100755 index 0000000..b6e66c9 Binary files /dev/null and b/spice/copy/sub/LT1186F.sub differ diff --git a/spice/copy/sub/LT1241.sub b/spice/copy/sub/LT1241.sub new file mode 100755 index 0000000..2cef216 Binary files /dev/null and b/spice/copy/sub/LT1241.sub differ diff --git a/spice/copy/sub/LT1242.sub b/spice/copy/sub/LT1242.sub new file mode 100755 index 0000000..4ecfd6d Binary files /dev/null and b/spice/copy/sub/LT1242.sub differ diff --git a/spice/copy/sub/LT1243.sub b/spice/copy/sub/LT1243.sub new file mode 100755 index 0000000..6685e58 Binary files /dev/null and b/spice/copy/sub/LT1243.sub differ diff --git a/spice/copy/sub/LT1244.sub b/spice/copy/sub/LT1244.sub new file mode 100755 index 0000000..8ef5832 Binary files /dev/null and b/spice/copy/sub/LT1244.sub differ diff --git a/spice/copy/sub/LT1245.sub b/spice/copy/sub/LT1245.sub new file mode 100755 index 0000000..595c567 Binary files /dev/null and b/spice/copy/sub/LT1245.sub differ diff --git a/spice/copy/sub/LT1246.sub b/spice/copy/sub/LT1246.sub new file mode 100755 index 0000000..7df3433 Binary files /dev/null and b/spice/copy/sub/LT1246.sub differ diff --git a/spice/copy/sub/LT1247.sub b/spice/copy/sub/LT1247.sub new file mode 100755 index 0000000..46004a1 Binary files /dev/null and b/spice/copy/sub/LT1247.sub differ diff --git a/spice/copy/sub/LT1248.sub b/spice/copy/sub/LT1248.sub new file mode 100755 index 0000000..5638c2a Binary files /dev/null and b/spice/copy/sub/LT1248.sub differ diff --git a/spice/copy/sub/LT1249.sub b/spice/copy/sub/LT1249.sub new file mode 100755 index 0000000..6c711b2 Binary files /dev/null and b/spice/copy/sub/LT1249.sub differ diff --git a/spice/copy/sub/LT1268.sub b/spice/copy/sub/LT1268.sub new file mode 100755 index 0000000..9c3cec5 Binary files /dev/null and b/spice/copy/sub/LT1268.sub differ diff --git a/spice/copy/sub/LT1269.sub b/spice/copy/sub/LT1269.sub new file mode 100755 index 0000000..4e206c8 Binary files /dev/null and b/spice/copy/sub/LT1269.sub differ diff --git a/spice/copy/sub/LT1270.sub b/spice/copy/sub/LT1270.sub new file mode 100755 index 0000000..65fa1a5 Binary files /dev/null and b/spice/copy/sub/LT1270.sub differ diff --git a/spice/copy/sub/LT1270A.sub b/spice/copy/sub/LT1270A.sub new file mode 100755 index 0000000..1d0be7f Binary files /dev/null and b/spice/copy/sub/LT1270A.sub differ diff --git a/spice/copy/sub/LT1271.sub b/spice/copy/sub/LT1271.sub new file mode 100755 index 0000000..a25ef8a Binary files /dev/null and b/spice/copy/sub/LT1271.sub differ diff --git a/spice/copy/sub/LT1300.sub b/spice/copy/sub/LT1300.sub new file mode 100755 index 0000000..47b1214 Binary files /dev/null and b/spice/copy/sub/LT1300.sub differ diff --git a/spice/copy/sub/LT1301.sub b/spice/copy/sub/LT1301.sub new file mode 100755 index 0000000..2b9d2f0 Binary files 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0000000..1272079 Binary files /dev/null and b/spice/copy/sub/LT1376.sub differ diff --git a/spice/copy/sub/LT1377.sub b/spice/copy/sub/LT1377.sub new file mode 100755 index 0000000..c8a7c1d Binary files /dev/null and b/spice/copy/sub/LT1377.sub differ diff --git a/spice/copy/sub/LT1389.lib b/spice/copy/sub/LT1389.lib new file mode 100755 index 0000000..d20de5b --- /dev/null +++ b/spice/copy/sub/LT1389.lib @@ -0,0 +1,85 @@ +* Copyright © Linear Technology Corp. 2016. All rights reserved. +* +.subckt LT1389-1.25 1 2 +C3 1 2 10p Rpar=8Meg noiseless +R1 1 N002 3Meg tc = 0 -.60u 2n 80p noiseless +D1 2 1 Y +R3 N002 2 3Meg noiseless +A1 N002 2 2 2 2 2 N003 2 OTA G=100u Iout=1u Ref=.624715543 en=252n enk=10 Vhigh=0 Vlow=-800m +G1 2 G 2 N003 .1µ +C1 N003 N002 20p Rser=30Meg Rpar=3.54G noiseless +B1 1 2 I=Max((.5+.5*tanh((V(1,2)-500m)/50m))*20m*(V(G,2))**3.5,0) +C4 G 2 3p Rpar=10Meg noiseless +C6 G 2 q=uplim(2p*X,200f,10f) +D2 2 N003 DLIM +C2 1 N004 10p +C7 N004 2 1p Rpar=10k noiseless +S1 N002 1 N004 2 SLS +C5 1 G 500f +.model Y D(Is=5e-12 N=1.2 Rs=6 noiseless) +.model DLIM D(Ron=1k Roff=1T vfwd=600m epsilon=100m noiseless) +.model SLS SW(Ron=3Meg Roff=1T vt=100u vh=-10u noiseless) +.ends LT1389-1.25 +* +.subckt LT1389-2.5 1 2 +C3 1 2 10p Rpar=10.435Meg noiseless +R1 1 N002 6Meg tc = 0 -.60u -2n 40p noiseless +D1 2 1 Y +R3 N002 2 6Meg noiseless +A1 N002 2 2 2 2 2 N003 2 OTA G=100u Iout=1u Ref=1.24912357 en=505n enk=10 Vhigh=0 Vlow=-800m +G1 2 G 2 N003 .1µ +C1 N003 N002 20p Rser=60Meg Rpar=4.4G noiseless +B1 1 2 I=Max((.5+.5*tanh((V(1,2)-500m)/50m))*20m*(V(G,2))**3.4,0) +C4 G 2 3p Rpar=10Meg noiseless +C6 G 2 q=uplim(3p*X,200f,10f) +D2 2 N003 DLIM +C2 1 N004 10p +C7 N004 2 1p Rpar=10k noiseless +S1 N002 1 N004 2 SLS +C5 1 G 100f +.model Y D(Is=5e-12 N=1.2 Rs=6 noiseless) +.model DLIM D(Ron=1k Roff=1T vfwd=600m epsilon=100m noiseless) +.model SLS SW(Ron=3Meg Roff=1T vt=100u vh=-10u noiseless) +.ends LT1389-2.5 +* +.subckt LT1389-4.096 1 2 +C3 1 2 10p Rpar=12Meg noiseless +R1 1 N002 TTC 12Meg tc = 0 -.55u -1.5n 70p noiseless +D1 2 1 Y +R3 N002 2 12Meg noiseless +A1 N002 2 2 2 2 2 N003 2 OTA G=100u Iout=1u Ref=2.04795028 en=807n enk=10 Vhigh=0 Vlow=-5.5 +G1 2 G 2 N003 .1µ +C1 N003 N002 2p Rser=3.5G Rpar=80G noiseless +B1 1 2 I=Max((.5+.5*tanh((V(1,2)-500m)/50m))*80u*(V(G,2))**2.2,0) +C4 G 2 3p Rpar=10Meg noiseless +C6 G 2 q=uplim(3p*X,200f,10f) +D2 2 N003 DLIM +C2 1 N004 10p +C7 N004 2 1p Rpar=25k noiseless +S1 N002 1 N004 2 SLS +.model Y D(Is=5e-12 N=1.2 Rs=6 noiseless) +.model DLIM D(Ron=1k Roff=1T vfwd=5 epsilon=100m noiseless) +.model SLS SW(Ron=2Meg Roff=1T vt=100u vh=-10u noiseless) +.model TTC R(tnom=40) +.ends LT1389-4.096 +* +.subckt LT1389-5 1 2 +C3 1 2 10p Rpar=12Meg noiseless +R1 1 N002 TTC 12Meg tc = 0 -1.05u -3.8n 100p noiseless +D1 2 1 Y +R3 N002 2 12Meg noiseless +A1 N002 2 2 2 2 2 N003 2 OTA G=100u Iout=1u Ref=2.499934 en=1.01u enk=10 Vhigh=0 Vlow=-5.5 +G1 2 G 2 N003 .1µ +C1 N003 N002 2p Rser=3.5G Rpar=52G noiseless +B1 1 2 I=Max((.5+.5*tanh((V(1,2)-500m)/50m))*80u*(V(G,2))**2.2,0) +C4 G 2 3p Rpar=10Meg noiseless +C6 G 2 q=uplim(3p*X,200f,10f) +D2 2 N003 DLIM +C2 1 N004 10p +C7 N004 2 1p Rpar=25k noiseless +S1 N002 1 N004 2 SLS +.model Y D(Is=5e-12 N=1.2 Rs=6 noiseless) +.model DLIM D(Ron=1k Roff=1T vfwd=5 epsilon=100m noiseless) +.model SLS SW(Ron=2Meg Roff=1T vt=100u vh=-10u noiseless) +.model TTC R(tnom=40) +.ends LT1389-5 diff --git a/spice/copy/sub/LT1424-5.sub b/spice/copy/sub/LT1424-5.sub new file mode 100755 index 0000000..cfdad3b Binary files /dev/null and b/spice/copy/sub/LT1424-5.sub differ diff --git a/spice/copy/sub/LT1424-9.sub b/spice/copy/sub/LT1424-9.sub new file mode 100755 index 0000000..616f77f Binary files /dev/null and b/spice/copy/sub/LT1424-9.sub differ diff --git a/spice/copy/sub/LT1425.sub b/spice/copy/sub/LT1425.sub new file mode 100755 index 0000000..c50a522 Binary files /dev/null and b/spice/copy/sub/LT1425.sub differ diff --git a/spice/copy/sub/LT1431.sub b/spice/copy/sub/LT1431.sub new file mode 100755 index 0000000..ed1538e Binary files /dev/null and b/spice/copy/sub/LT1431.sub differ diff --git a/spice/copy/sub/LT1432-3.3.sub b/spice/copy/sub/LT1432-3.3.sub new file mode 100755 index 0000000..b4d88c1 Binary files /dev/null and b/spice/copy/sub/LT1432-3.3.sub differ diff --git a/spice/copy/sub/LT1432.sub b/spice/copy/sub/LT1432.sub new file mode 100755 index 0000000..2f5df2f Binary files /dev/null and b/spice/copy/sub/LT1432.sub differ diff --git a/spice/copy/sub/LT1461.lib b/spice/copy/sub/LT1461.lib new file mode 100755 index 0000000..a6f39b5 --- /dev/null +++ b/spice/copy/sub/LT1461.lib @@ -0,0 +1,409 @@ +* Copyright © Analog Devices, Inc. 2019. All rights reserved. +* +.subckt LT1461-2.5 1 2 3 4 +R3 VBG 1 310K noiseless +R4 4 VBG 299.71637K noiseless +C2 4 N011 30p +C3 2 N011 500f +Q1 N009 N011 1 0 NPN1 Temp=27 +G1 4 N009 XB0 0 10µ +G2 4 N011 XB0 0 10µ +D3 N011 1 DBGRS +R1 XB0 0 100K noiseless +B1 0 XB0 I=dnlim(2.66e-6*(V(4,VBG)-.66),10n,150n)*V(ON,1) +Q2 1 X1N N003 0 PNP1 Temp=27 +Q3 X1N N010 1 0 NPN2 Temp=27 +R2 N004 N003 1K noiseless +C1 N009 X1N 4p Rser=50Meg noiseless +A1 1 N009 ON 1 1 1 N010 1 OTA g=.55m iout=2m ref=580m Rout=1k Cout=1p vlow=300m vhigh=1 +M1 4 N008 1 1 Ndrn Temp=27 +S1 1 N008 2 X1N Sdrn +A2 N009 1 ON 1 1 1 N008 1 OTA g=100u iout=15u ref=550m Cout=1p vlow=0 vhigh=1e308 +C4 4 N009 1p Rpar=100G noiseless +C7 4 N011 1p +Bstart1 2 N009 I=dnlim(2u*(1.1-V(4,VBG)),0,.1u)*V(ON,1) +D5 N011 4 DLIM1 +C8 N009 1 1p +C11 4 1 1p +C13 X1N 1 1p +C10 N009 X1N 6p Rser=800k noiseless +C16 VBG 1 .1p +C6 VBG N011 1p +C5 2 X1N 1p +C9 2 N004 1p +C12 N004 4 1p +S2 N009 1 1 N012 SGLIT1 +S3 1 N009 N012 1 SGLIT2 +D1 2 X1N DBIAS +D4 2 N004 DBIAS +D2 2 3 DBIAS +C14 2 3 1p +D7 3 1 DSHT +A3 3 1 1 1 1 1 N005 1 SCHMITT vt=2.3 vh=0 trise=10u +A4 2 1 1 1 1 1 N002 1 SCHMITT vt=2.3 vh=0 trise=500u tfall=20u +A5 N002 1 1 1 N005 _ON ON 1 AND trise=40u +D8 2 1 DBURN +Q4 4B N004 2 0 PNPPass Temp=27 +R5 4B 4 5 noiseless +A6 XB0 0 0 0 0 0 0 0 OTA g=0 in=1p ink=1.3 +C19 N009 N013 1p Rser=6Meg noiseless +C20 2 N012 400f Rser=10Meg noiseless +C21 N012 1 250f Rpar=50Meg noiseless +D9 N013 1 DLIMX +G4 1 N013 N012 1 100µ +G6 0 N014 1 N015 1m +L1 N014 0 2m Rser=1 noiseless +G7 1 XRR N014 0 15m +R8 XRR 1 1K noiseless +C18 N004 XRR 800f +C22 2 N015 40f +C23 N015 1 40f Rpar=1Meg noiseless +C24 N004 1 100f +C25 2 N012 150f Rser=1Meg noiseless +D10 XRR 1 DLIMX +D11 N012 1 DBICLMP +C15 N013 1 4p Rser=100k Rpar=10Meg noiseless +B2 VBG 4 I=25n*dnlim((V(4B,4)-150m),0,10m)**1.2 +G3 1 N012 _ON 1 10n +.model PNPPass PNP(IS=3.6e-16 BF=100 BR=1 ISC=1.5e-9 NC=1.9 IKF=14m TF=10n ITF=20m XTF=40 noiseless) +.model PNP1 PNP(IS=1e-16 Rb=100 BF=100 TF=10n noiseless) +.model NPN1 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=100 noiseless) +.model NPN2 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=350 noiseless) +.model DBGRS D(Ron=71k Roff=1G vfwd= 400m epsilon=200m noiseless) +.model DLIM1 D(Ron=1k Roff=100G vfwd=1 epsilon=500m noiseless) +.model DLIMX D(Ron=10 Roff=500k vfwd=1 epsilon=300m vrev=1 revepsilon=300m noiseless) +.model SGLIT1 SW(Ron=700k Roff=1G vt=300m vh=-100m noiseless) +.model SGLIT2 SW(Ron=500k Roff=1G vt=120m vh=-80m noiseless) +.model DBICLMP D(Ron=1k Roff=200Meg vfwd=1 epsilon=400m vrev=1 revepsilon=400m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=1 epsilon=500m ilimit=26.8u noiseless) +.model Dbias D(Ron=10 Roff=100Meg vfwd=300m epsilon=200m ilimit=500n noiseless) +.model Ndrn VDMOS(Kp=30u vto=2) +.model Sdrn SW(Ron=1k Roff=1Meg vt=560m vh=-100m noiseless) +.model DSHT D(Ron=100k Roff=1G vfwd=2.5 epsilon=500m noiseless) +.ends LT1461-2.5 +* +.subckt LT1461-3.3 1 2 3 4 +R3 VBG 1 505.06932K noiseless +R4 4 VBG 299.7K noiseless +C2 4 N011 30p +C3 2 N011 500f +Q1 N009 N011 1 0 NPN1 Temp=27 +G1 4 N009 XB0 0 10µ +G2 4 N011 XB0 0 10µ +D3 N011 1 DBGRS +R1 XB0 0 100K noiseless +B1 0 XB0 I=dnlim(2.66e-6*(V(4,VBG)-.66),10n,150n)*V(ON,1) +Q2 1 X1N N003 0 PNP1 Temp=27 +Q3 X1N N010 1 0 NPN2 Temp=27 +R2 N004 N003 1K noiseless +C1 N009 X1N 4p Rser=50Meg noiseless +A1 1 N009 ON 1 1 1 N010 1 OTA g=.55m iout=2m ref=580m Rout=1k Cout=1p vlow=300m vhigh=1 +M1 4 N008 1 1 Ndrn Temp=27 +S1 1 N008 2 X1N Sdrn +A2 N009 1 ON 1 1 1 N008 1 OTA g=100u iout=15u ref=550m Cout=1p vlow=0 vhigh=1e308 +C4 4 N009 1p Rpar=100G noiseless +C7 4 N011 1p +Bstart1 2 N009 I=dnlim(2u*(1.1-V(4,VBG)),0,.1u)*V(ON,1) +D5 N011 4 DLIM1 +C8 N009 1 1p +C11 4 1 1p +C13 X1N 1 1p +C10 N009 X1N 6p Rser=800k noiseless +C16 VBG 1 .1p +C6 VBG N011 1p +C5 2 X1N 1p +C9 2 N004 1p +C12 N004 4 1p +S2 N009 1 1 N012 SGLIT1 +S3 1 N009 N012 1 SGLIT2 +D1 2 X1N DBIAS +D4 2 N004 DBIAS +D2 2 3 DBIAS +C14 2 3 1p +D7 3 1 DSHT +A3 3 1 1 1 1 1 N005 1 SCHMITT vt=2.3 vh=0 trise=10u +A4 2 1 1 1 1 1 N002 1 SCHMITT vt=2.3 vh=0 trise=500u tfall=20u +A5 N002 1 1 1 N005 _ON ON 1 AND trise=40u +D8 2 1 DBURN +Q4 4B N004 2 0 PNPPass Temp=27 +R5 4B 4 5 noiseless +A6 XB0 0 0 0 0 0 0 0 OTA g=0 in=1p ink=1.3 +C19 N009 N013 1p Rser=6Meg noiseless +C20 2 N012 400f Rser=10Meg noiseless +C21 N012 1 250f Rpar=50Meg noiseless +D9 N013 1 DLIMX +G4 1 N013 N012 1 100µ +G6 0 N014 1 N015 1m +L1 N014 0 3.5m Rser=1 noiseless +G7 1 XRR N014 0 15m +R8 XRR 1 1K noiseless +C18 N004 XRR 800f +C22 2 N015 40f +C23 N015 1 40f Rpar=1Meg noiseless +C24 N004 1 100f +C25 2 N012 150f Rser=4.6Meg noiseless +D10 XRR 1 DLIMX +D11 N012 1 DBICLMP +C15 N013 1 5.4p Rser=60.6k Rpar=10Meg noiseless +B2 VBG 4 I=25n*dnlim((V(4B,4)-105m),0,10m)**1.2 +G3 1 N012 _ON 1 10n +.model PNPPass PNP(IS=3.6e-16 BF=100 BR=1 ISC=1.5e-9 NC=1.9 IKF=14m TF=10n ITF=20m XTF=40 noiseless) +.model PNP1 PNP(IS=1e-16 Rb=100 BF=100 TF=10n noiseless) +.model NPN1 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=100 noiseless) +.model NPN2 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=178 noiseless) +.model DBGRS D(Ron=71k Roff=1G vfwd= 400m epsilon=200m noiseless) +.model DLIM1 D(Ron=1k Roff=100G vfwd=1 epsilon=500m noiseless) +.model DLIMX D(Ron=10 Roff=500k vfwd=1 epsilon=300m vrev=1 revepsilon=300m noiseless) +.model SGLIT1 SW(Ron=700k Roff=1G vt=300m vh=-100m noiseless) +.model SGLIT2 SW(Ron=500k Roff=1G vt=120m vh=-80m noiseless) +.model DBICLMP D(Ron=1k Roff=200Meg vfwd=1 epsilon=400m vrev=1 revepsilon=400m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=1 epsilon=500m ilimit=26.8u noiseless) +.model Dbias D(Ron=10 Roff=100Meg vfwd=300m epsilon=200m ilimit=500n noiseless) +.model Ndrn VDMOS(Kp=30u vto=2) +.model Sdrn SW(Ron=1k Roff=1Meg vt=560m vh=-100m noiseless) +.model DSHT D(Ron=100k Roff=1G vfwd=2.5 epsilon=500m noiseless) +.ends LT1461-3.3 +* +.subckt LT1461-3 1 2 3 4 +R3 VBG 1 431.90805K noiseless +R4 4 VBG 299.7K noiseless +C2 4 N011 30p +C3 2 N011 500f +Q1 N009 N011 1 0 NPN1 Temp=27 +G1 4 N009 XB0 0 10µ +G2 4 N011 XB0 0 10µ +D3 N011 1 DBGRS +R1 XB0 0 100K noiseless +B1 0 XB0 I=dnlim(2.66e-6*(V(4,VBG)-.66),10n,150n)*V(ON,1) +Q2 1 X1N N003 0 PNP1 Temp=27 +Q3 X1N N010 1 0 NPN2 Temp=27 +R2 N004 N003 1K noiseless +C1 N009 X1N 4p Rser=50Meg noiseless +A1 1 N009 ON 1 1 1 N010 1 OTA g=.55m iout=2m ref=580m Rout=1k Cout=1p vlow=300m vhigh=1 +M1 4 N008 1 1 Ndrn Temp=27 +S1 1 N008 2 X1N Sdrn +A2 N009 1 ON 1 1 1 N008 1 OTA g=100u iout=15u ref=550m Cout=1p vlow=0 vhigh=1e308 +C4 4 N009 1p Rpar=100G noiseless +C7 4 N011 1p +Bstart1 2 N009 I=dnlim(2u*(1.1-V(4,VBG)),0,.1u)*V(ON,1) +D5 N011 4 DLIM1 +C8 N009 1 1p +C11 4 1 1p +C13 X1N 1 1p +C10 N009 X1N 6p Rser=800k noiseless +C16 VBG 1 .1p +C6 VBG N011 1p +C5 2 X1N 1p +C9 2 N004 1p +C12 N004 4 1p +S2 N009 1 1 N012 SGLIT1 +S3 1 N009 N012 1 SGLIT2 +D1 2 X1N DBIAS +D4 2 N004 DBIAS +D2 2 3 DBIAS +C14 2 3 1p +D7 3 1 DSHT +A3 3 1 1 1 1 1 N005 1 SCHMITT vt=2.3 vh=0 trise=10u +A4 2 1 1 1 1 1 N002 1 SCHMITT vt=2.3 vh=0 trise=500u tfall=20u +A5 N002 1 1 1 N005 _ON ON 1 AND trise=40u +D8 2 1 DBURN +Q4 4B N004 2 0 PNPPass Temp=27 +R5 4B 4 5 noiseless +A6 XB0 0 0 0 0 0 0 0 OTA g=0 in=1p ink=1.3 +C19 N009 N013 1p Rser=6Meg noiseless +C20 2 N012 400f Rser=10Meg noiseless +C21 N012 1 250f Rpar=50Meg noiseless +D9 N013 1 DLIMX +G4 1 N013 N012 1 100µ +G6 0 N014 1 N015 1m +L1 N014 0 2.8m Rser=1 noiseless +G7 1 XRR N014 0 15m +R8 XRR 1 1K noiseless +C18 N004 XRR 800f +C22 2 N015 40f +C23 N015 1 40f Rpar=1Meg noiseless +C24 N004 1 100f +C25 2 N012 150f Rser=2.5Meg noiseless +D10 XRR 1 DLIMX +D11 N012 1 DBICLMP +C15 N013 1 4.8p Rser=73k Rpar=10Meg noiseless +B2 VBG 4 I=25n*dnlim((V(4B,4)-122m),0,10m)**1.2 +G3 1 N012 _ON 1 10n +.model PNPPass PNP(IS=3.6e-16 BF=100 BR=1 ISC=1.5e-9 NC=1.9 IKF=14m TF=10n ITF=20m XTF=40 noiseless) +.model PNP1 PNP(IS=1e-16 Rb=100 BF=100 TF=10n noiseless) +.model NPN1 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=100 noiseless) +.model NPN2 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=221 noiseless) +.model DBGRS D(Ron=71k Roff=1G vfwd= 400m epsilon=200m noiseless) +.model DLIM1 D(Ron=1k Roff=100G vfwd=1 epsilon=500m noiseless) +.model DLIMX D(Ron=10 Roff=500k vfwd=1 epsilon=300m vrev=1 revepsilon=300m noiseless) +.model SGLIT1 SW(Ron=700k Roff=1G vt=300m vh=-100m noiseless) +.model SGLIT2 SW(Ron=500k Roff=1G vt=120m vh=-80m noiseless) +.model DBICLMP D(Ron=1k Roff=200Meg vfwd=1 epsilon=400m vrev=1 revepsilon=400m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=1 epsilon=500m ilimit=26.8u noiseless) +.model Dbias D(Ron=10 Roff=100Meg vfwd=300m epsilon=200m ilimit=500n noiseless) +.model Ndrn VDMOS(Kp=30u vto=2) +.model Sdrn SW(Ron=1k Roff=1Meg vt=560m vh=-100m noiseless) +.model DSHT D(Ron=100k Roff=1G vfwd=2.5 epsilon=500m noiseless) +.ends LT1461-3 +* +.subckt LT1461-4.096 1 2 3 4 +R3 VBG 1 699.13929K noiseless +R4 4 VBG 299.7K noiseless +C2 4 N011 30p +C3 2 N011 500f +Q1 N009 N011 1 0 NPN1 Temp=27 +G1 4 N009 XB0 0 10µ +G2 4 N011 XB0 0 10µ +D3 N011 1 DBGRS +R1 XB0 0 100K noiseless +B1 0 XB0 I=dnlim(2.66e-6*(V(4,VBG)-.66),10n,150n)*V(ON,1) +Q2 1 X1N N003 0 PNP1 Temp=27 +Q3 X1N N010 1 0 NPN2 Temp=27 +R2 N004 N003 1K noiseless +C1 N009 X1N 4p Rser=50Meg noiseless +A1 1 N009 ON 1 1 1 N010 1 OTA g=.55m iout=2m ref=580m Rout=1k Cout=1p vlow=300m vhigh=1 +M1 4 N008 1 1 Ndrn Temp=27 +S1 1 N008 2 X1N Sdrn +A2 N009 1 ON 1 1 1 N008 1 OTA g=100u iout=15u ref=550m Cout=1p vlow=0 vhigh=1e308 +C4 4 N009 1p Rpar=100G noiseless +C7 4 N011 1p +Bstart1 2 N009 I=dnlim(2u*(1.1-V(4,VBG)),0,.1u)*V(ON,1) +D5 N011 4 DLIM1 +C8 N009 1 1p +C11 4 1 1p +C13 X1N 1 1p +C10 N009 X1N 6p Rser=800k noiseless +C16 VBG 1 .1p +C6 VBG N011 1p +C5 2 X1N 1p +C9 2 N004 1p +C12 N004 4 1p +S3 1 N009 N012 1 SGLIT2 +D1 2 X1N DBIAS +D4 2 N004 DBIAS +D2 2 3 DBIAS +C14 2 3 1p +D7 3 1 DSHT +A3 3 1 1 1 1 1 N005 1 SCHMITT vt=2.3 vh=0 trise=10u +A4 2 1 1 1 1 1 N002 1 SCHMITT vt=2.3 vh=0 trise=500u tfall=20u +A5 N002 1 1 1 N005 _ON ON 1 AND trise=40u +D8 2 1 DBURN +Q4 4B N004 2 0 PNPPass Temp=27 +R5 4B 4 5 noiseless +A6 XB0 0 0 0 0 0 0 0 OTA g=0 in=1p ink=1.3 +C19 N009 N013 1p Rser=6Meg noiseless +C20 2 N012 400f Rser=10Meg noiseless +C21 N012 1 250f Rpar=50Meg noiseless +D9 N013 1 DLIMX +G4 1 N013 N012 1 100µ +G6 0 N014 1 N015 1m +L1 N014 0 6.3m Rser=1 noiseless +G7 1 XRR N014 0 15m +R8 XRR 1 1K noiseless +C18 N004 XRR 800f +C22 2 N015 40f +C23 N015 1 40f Rpar=1Meg noiseless +C24 N004 1 100f +C25 2 N012 150f Rser=19Meg noiseless +D10 XRR 1 DLIMX +D11 N012 1 DBICLMP +C15 N013 1 7.2p Rser=37k Rpar=10Meg noiseless +B2 VBG 4 I=25n*dnlim((V(4B,4)-61m),0,10m)**1.2 +G3 1 N012 _ON 1 10n +.model PNPPass PNP(IS=3.6e-16 BF=100 BR=1 ISC=1.5e-9 NC=1.9 IKF=14m TF=10n ITF=20m XTF=40 noiseless) +.model PNP1 PNP(IS=1e-16 Rb=100 BF=100 TF=10n noiseless) +.model NPN1 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=100 noiseless) +.model NPN2 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=122 noiseless) +.model DBGRS D(Ron=71k Roff=1G vfwd= 400m epsilon=200m noiseless) +.model DLIM1 D(Ron=1k Roff=100G vfwd=1 epsilon=500m noiseless) +.model DLIMX D(Ron=10 Roff=500k vfwd=1 epsilon=300m vrev=1 revepsilon=300m noiseless) +.model SGLIT2 SW(Ron=500k Roff=1G vt=120m vh=-80m noiseless) +.model DBICLMP D(Ron=1k Roff=200Meg vfwd=1 epsilon=400m vrev=1 revepsilon=400m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=1 epsilon=500m ilimit=26.8u noiseless) +.model Dbias D(Ron=10 Roff=100Meg vfwd=300m epsilon=200m ilimit=500n noiseless) +.model Ndrn VDMOS(Kp=30u vto=2) +.model Sdrn SW(Ron=1k Roff=1Meg vt=560m vh=-100m noiseless) +.model DSHT D(Ron=100k Roff=1G vfwd=2.5 epsilon=500m noiseless) +.ends LT1461-4.096 +* +.subckt LT1461-5 1 2 3 4 +R3 VBG 1 919.5878K noiseless +C2 4 N012 30p +C3 2 N012 500f +Q1 N009 N012 1 0 NPN1 Temp=27 +G1 4 N009 XB0 0 10µ +G2 4 N012 XB0 0 10µ +D3 N012 1 DBGRS +R1 XB0 0 100K noiseless +B1 0 XB0 I=dnlim(2.66e-6*(V(4,VBG)-.66),10n,150n)*V(ON,1) +Q2 1 X1N N003 0 PNP1 Temp=27 +Q3 X1N N011 1 0 NPN2 Temp=27 +R2 N004 N003 1K noiseless +C1 N009 X1N 4p Rser=50Meg noiseless +A1 1 N009 ON 1 1 1 N011 1 OTA g=.55m iout=2m ref=580m Rout=1k Cout=1p vlow=300m vhigh=1 +M1 4 N008 1 1 Ndrn Temp=27 +S1 1 N008 2 X1N Sdrn +A2 N009 1 ON 1 1 1 N008 1 OTA g=100u iout=15u ref=550m Cout=1p vlow=0 vhigh=1e308 +C4 4 N009 1p Rpar=100G noiseless +C7 4 N012 1p +Bstart1 2 N009 I=dnlim(2u*(1.1-V(4,VBG)),0,.1u)*V(ON,1) +D5 N012 4 DLIM1 +C8 N009 1 1p +C11 4 1 1p +C13 X1N 1 1p +C10 N009 X1N 6p Rser=800k noiseless +C16 VBG 1 .1p +C6 VBG N012 1p +C5 2 X1N 1p +C9 2 N004 1p +C12 N004 4 1p +S3 1 N009 N010 1 SGLIT2 +D1 2 X1N DBIAS +D4 2 N004 DBIAS +D2 2 3 DBIAS +C14 2 3 1p +D7 3 1 DSHT +A3 3 1 1 1 1 1 N005 1 SCHMITT vt=2.3 vh=0 trise=10u +A4 2 1 1 1 1 1 N002 1 SCHMITT vt=2.3 vh=0 trise=500u tfall=20u +A5 N002 1 1 1 N005 _ON ON 1 AND trise=40u +D8 2 1 DBURN +Q4 4B N004 2 0 PNPPass Temp=27 +R5 4B 4 5 noiseless +A6 XB0 0 0 0 0 0 0 0 OTA g=0 in=1p ink=1.3 +C19 N009 N013 1p Rser=6Meg noiseless +C20 2 N010 400f Rser=10Meg noiseless +C21 N010 1 250f Rpar=50Meg noiseless +D9 N013 1 DLIMX +G4 1 N013 N010 1 100µ +G6 0 N014 1 N015 1m +L1 N014 0 12m Rser=1 noiseless +G7 1 XRR N014 0 15m +R8 XRR 1 1K noiseless +C18 N004 XRR 800f +C22 2 N015 40f +C23 N015 1 40f Rpar=1Meg noiseless +C24 N004 1 100f +C25 2 N010 150f Rser=100Meg noiseless +D10 XRR 1 DLIMX +D11 N010 1 DBICLMP +C15 N013 1 10p Rser=20k Rpar=10Meg noiseless +B2 VBG 4 I=25n*dnlim(V(4B,4)-10m,0,10m)**1.2 +R4 4 VBG 299.7K noiseless +S4 X1N 1 1 N010 SGLIT1 +G5 1 N010 _ON 1 10n +.model PNPPass PNP(IS=3.6e-16 BF=100 BR=1 ISC=1.5e-9 NC=1.9 IKF=14m TF=10n ITF=20m XTF=40 noiseless) +.model PNP1 PNP(IS=1e-16 Rb=100 BF=100 TF=10n noiseless) +.model NPN1 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=100 noiseless) +.model NPN2 NPN(IS=1e-16 BF=100 Rb=100 CJE=.1p CJC=.1p TF=1n VAF=90 noiseless) +.model DBGRS D(Ron=71k Roff=1G vfwd= 400m epsilon=200m noiseless) +.model DLIM1 D(Ron=1k Roff=100G vfwd=1 epsilon=500m noiseless) +.model DLIMX D(Ron=10 Roff=500k vfwd=1 epsilon=300m vrev=1 revepsilon=300m noiseless) +.model SGLIT1 SW(Ron=700k Roff=1G vt=300m vh=-100m ilimit=1.5u noiseless) +.model SGLIT2 SW(Ron=500k Roff=1G vt=120m vh=-80m noiseless) +.model DBICLMP D(Ron=1k Roff=200Meg vfwd=1 epsilon=400m vrev=1 revepsilon=400m noiseless) +.model DBURN D(Ron=100 Roff=1G vfwd=1 epsilon=500m ilimit=28.62u noiseless) +.model Dbias D(Ron=10 Roff=100Meg vfwd=300m epsilon=200m ilimit=500n noiseless) +.model Ndrn VDMOS(Kp=30u vto=2) +.model Sdrn SW(Ron=1k Roff=1Meg vt=560m vh=-100m noiseless) +.model DSHT D(Ron=100k Roff=1G vfwd=2.5 epsilon=500m noiseless) +.ends LT1461-5 diff --git a/spice/copy/sub/LT1500-3.sub b/spice/copy/sub/LT1500-3.sub new file mode 100755 index 0000000..9c0cd23 Binary files /dev/null and b/spice/copy/sub/LT1500-3.sub differ diff --git a/spice/copy/sub/LT1500.sub b/spice/copy/sub/LT1500.sub new file mode 100755 index 0000000..c99dbd3 Binary files /dev/null and b/spice/copy/sub/LT1500.sub differ diff --git a/spice/copy/sub/LT1501-3.3.sub b/spice/copy/sub/LT1501-3.3.sub new file mode 100755 index 0000000..019aba9 Binary files /dev/null and b/spice/copy/sub/LT1501-3.3.sub differ diff --git a/spice/copy/sub/LT1501-5.sub b/spice/copy/sub/LT1501-5.sub new file mode 100755 index 0000000..714d645 Binary files /dev/null and b/spice/copy/sub/LT1501-5.sub differ diff --git a/spice/copy/sub/LT1501.sub b/spice/copy/sub/LT1501.sub new file mode 100755 index 0000000..e81386a Binary files /dev/null and b/spice/copy/sub/LT1501.sub differ diff --git a/spice/copy/sub/LT1505-1.sub b/spice/copy/sub/LT1505-1.sub new file mode 100755 index 0000000..0bc4e78 Binary files /dev/null and b/spice/copy/sub/LT1505-1.sub differ diff --git a/spice/copy/sub/LT1505.sub b/spice/copy/sub/LT1505.sub new file mode 100755 index 0000000..6a02ae0 Binary files /dev/null and b/spice/copy/sub/LT1505.sub differ diff --git a/spice/copy/sub/LT1506.sub b/spice/copy/sub/LT1506.sub new file mode 100755 index 0000000..28212ef Binary files /dev/null and b/spice/copy/sub/LT1506.sub differ diff --git a/spice/copy/sub/LT1507.sub b/spice/copy/sub/LT1507.sub new file mode 100755 index 0000000..87f8c0a Binary files /dev/null and b/spice/copy/sub/LT1507.sub differ diff --git a/spice/copy/sub/LT1508.sub b/spice/copy/sub/LT1508.sub new file mode 100755 index 0000000..b2e9416 Binary files /dev/null and b/spice/copy/sub/LT1508.sub differ diff --git a/spice/copy/sub/LT1509.sub b/spice/copy/sub/LT1509.sub new file mode 100755 index 0000000..9d8287a Binary files /dev/null and b/spice/copy/sub/LT1509.sub differ diff --git a/spice/copy/sub/LT1510-5.sub b/spice/copy/sub/LT1510-5.sub new file mode 100755 index 0000000..51523e7 Binary files /dev/null and b/spice/copy/sub/LT1510-5.sub differ diff --git a/spice/copy/sub/LT1510.sub b/spice/copy/sub/LT1510.sub new file mode 100755 index 0000000..959bf7c Binary files /dev/null and b/spice/copy/sub/LT1510.sub differ diff --git a/spice/copy/sub/LT1512.sub b/spice/copy/sub/LT1512.sub new file mode 100755 index 0000000..5fd6ec6 Binary files /dev/null and b/spice/copy/sub/LT1512.sub differ diff --git a/spice/copy/sub/LT1513-2.sub b/spice/copy/sub/LT1513-2.sub new file mode 100755 index 0000000..79877bd Binary files /dev/null and b/spice/copy/sub/LT1513-2.sub differ diff --git a/spice/copy/sub/LT1513.sub b/spice/copy/sub/LT1513.sub new file mode 100755 index 0000000..95b274c Binary files /dev/null and b/spice/copy/sub/LT1513.sub differ diff --git a/spice/copy/sub/LT1521.lib b/spice/copy/sub/LT1521.lib new file mode 100755 index 0000000..d27adf1 --- /dev/null +++ b/spice/copy/sub/LT1521.lib @@ -0,0 +1,169 @@ +* Copyright © Linear Technology Corp. 2004. All rights reserved. +* +.subckt LT1521-3.3 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N005 0 NP temp=27 +C1 N002 N003 12p Rser=40K +Q4 N003 N003 N004 0 NP 10 temp=27 +R2 N004 3 5K +R3 N005 3 6K +C2 1 N003 20p Rser=2K +Q5 1 2 N006 0 FB temp=27 +R6 N006 N004 206.5K +I1 8 5 1.9µ load +G2 8 N003 N008 3 2.33µ +G1 8 N002 N008 3 2.33µ +R1 8 N001 450K +R8 N009 1 .7 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 8m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 5 3 A +D4 3 5 B +C4 8 N002 1p Rser=.8G +C6 2 3 10p +G4 0 N010 8 3 table(2.1 3m 10 3.6m) +C8 8 N003 500p Rser=.42G Rpar=8.6G +.model PN PNP(BF=25 Cje=500p Cjc=500p TF=20n) +.model NA NPN(BF=500K Cje=.1p Cjc=.1p Re=40) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.1) +.model B D(Ron=3 Vrev=7.05 Vfwd=.6) +.ends LT1521-3.3 +* +.subckt LT1521-3 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N005 0 NP temp=27 +C1 N002 N003 12p Rser=40K +Q4 N003 N003 N004 0 NP 10 temp=27 +R2 N004 3 5K +R3 N005 3 6K +C2 1 N003 20p Rser=2K +Q5 1 2 N006 0 FB temp=27 +R6 N006 N004 182K +I1 8 5 1.9µ load +G2 8 N003 N008 3 2.33µ +G1 8 N002 N008 3 2.33µ +R1 8 N001 450K +R8 N009 1 .7 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 8m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 5 3 A +D4 3 5 B +C4 8 N002 1p Rser=.8G +C6 2 3 10p +G4 0 N010 8 3 table(2.1 3m 10 3.6m) +C8 8 N003 500p Rser=.42G Rpar=8.6G +.model PN PNP(BF=25 Cje=500p Cjc=500p TF=20n) +.model NA NPN(BF=500K Cje=.1p Cjc=.1p Re=40) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.1) +.model B D(Ron=3 Vrev=7.05 Vfwd=.6) +.ends LT1521-3 +* +.subckt LT1521-5 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N005 0 NP temp=27 +C1 N002 N003 12p Rser=40K +Q4 N003 N003 N004 0 NP 10 temp=27 +R2 N004 3 5K +R3 N005 3 6K +C2 1 N003 20p Rser=2K +Q5 1 2 N006 0 FB temp=27 +R6 N006 N004 344K +I1 8 5 1.9µ load +G2 8 N003 N008 3 2.33µ +G1 8 N002 N008 3 2.33µ +R1 8 N001 450K +R8 N009 1 .7 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 8m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 5 3 A +D4 3 5 B +C4 8 N002 1p Rser=.8G +C6 2 3 10p +G4 0 N010 8 3 table(2.1 3m 10 3.6m) +C8 8 N003 500p Rser=.42G Rpar=8.6G +.model PN PNP(BF=25 Cje=500p Cjc=500p TF=20n) +.model NA NPN(BF=500K Cje=.1p Cjc=.1p Re=40) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.1) +.model B D(Ron=3 Vrev=7.05 Vfwd=.6) +.ends LT1521-5 +* +.subckt LT1521 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N005 0 NP temp=27 +C1 N002 N003 12p Rser=40K +Q4 N003 N003 N004 0 NP 10 temp=27 +R2 N004 3 5K +R3 N005 3 6K +C2 1 N003 20p Rser=2K +Q5 1 2 N006 0 FB temp=27 +R6 N006 N004 242.3K +I1 8 5 1.9µ load +G2 8 N003 N008 3 2.33µ +G1 8 N002 N008 3 2.33µ +R1 8 N001 450K +R8 N009 1 .7 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 8m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 5 3 A +D4 3 5 B +C4 8 N002 1p Rser=.8G +C6 2 3 10p +G4 0 N010 8 3 table(2.1 3m 10 3.6m) +C8 8 N003 500p Rser=.42G Rpar=8.6G +.model PN PNP(BF=25 Cje=500p Cjc=500p TF=20n) +.model NA NPN(BF=500K Cje=.1p Cjc=.1p Re=40) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.1) +.model B D(Ron=3 Vrev=7.05 Vfwd=.6) +.ends LT1521 diff --git a/spice/copy/sub/LT1528.lib b/spice/copy/sub/LT1528.lib new file mode 100755 index 0000000..5c8acc5 --- /dev/null +++ b/spice/copy/sub/LT1528.lib @@ -0,0 +1,38 @@ +* Copyright © Linear Technology Corp. 2010. All rights reserved. +* +.subckt LT1528 1 2 3 4 5 +Q1 N007 N005 5 0 PN +Q2 N005 N001 3 0 NA +Q3 N001 N009 N010 0 NP temp=27 +R2 N009 3 4.7K +R3 N010 3 500 +R6 2 N009 20.6K +I1 5 4 37µ load +G1 5 N001 N003 3 2µ +R1 5 N005 150K +R8 N007 1 .1 +A2 N006 0 N001 N001 N001 N001 3 N001 VARISTOR Rclamp=1K +D3 0 N006 F +G3 0 N006 1 N007 10m +Q7 N009 N005 N007 0 P 2m +C5 1 3 10p +C7 5 3 10p +G5 N006 0 N003 3 table(0 4.2m .95 0) +A1 4 3 3 3 3 3 N003 3 SCHMITT Vt=.975 Vh=1m trise=2m +D2 4 3 A +D4 3 4 B +C6 2 3 10p +G4 0 N006 5 3 table( 2,0 3,4.2m 10 5.6m) +C1 N001 N009 1p +C2 N005 N001 .2p Rser=1K +C4 5 N001 500p Rser=80Meg Rpar=.27G +S1 N001 3 3 N003 SD +.model PN PNP(BF=50 Cje=1n Cjc=1n tf=10n) +.model NA NPN(BF=450K Re=5) +.model NP NPN(BF=1500) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model A D(Ron=110 Vfwd=6.6) +.model B D(Ron=2 Vrev=7.5 Vfwd=.6) +.model SD SW(Ron=1K Roff=1T Vt=-.5 Vh=-.4) +.ends LT1528 \ No newline at end of file diff --git a/spice/copy/sub/LT1529.lib b/spice/copy/sub/LT1529.lib new file mode 100755 index 0000000..2569de2 --- /dev/null +++ b/spice/copy/sub/LT1529.lib @@ -0,0 +1,124 @@ +* Copyright © Linear Technology Corp. 2004. All rights reserved. +* +.subckt LT1529-3.3 1 2 3 4 5 +Q1 N009 N001 5 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N005 0 NP temp=27 +C1 N002 N003 20p Rser=200K +Q4 N003 N003 N004 0 NP 10 temp=27 +R2 N004 3 2K +R3 N005 3 2.4K +C2 1 N003 10p Rser=2K +Q5 1 2 N006 0 FB temp=27 +R6 N006 N004 80.8K +I1 5 4 4.5µ load +G2 5 N003 N008 3 7µ +G1 5 N002 N008 3 7µ +R1 5 N001 37K +R8 N009 1 .11 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 5 1 X +C5 1 3 10p +C7 5 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 4 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 4 3 A +D4 3 4 B +C6 2 3 10p +G4 0 N010 5 3 table(3 4.7m 10 5.8m) +C4 5 N003 5p Rser=.5G Rpar=2G +.model PN PNP(BF=25 Cje=500p Cjc=500p TF=20n) +.model NA NPN(BF=5Meg Cje=.2p Cjc=.2p Re=2) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.1) +.model B D(Ron=3 Vrev=7.05 Vfwd=.6) +.ends LT1529-3.3 +* +.subckt LT1529-5 1 2 3 4 5 +Q1 N009 N001 5 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N005 0 NP temp=27 +C1 N002 N003 20p Rser=200K +Q4 N003 N003 N004 0 NP 10 temp=27 +R2 N004 3 2K +R3 N005 3 2.4K +C2 1 N003 10p Rser=2K +Q5 1 2 N006 0 FB temp=27 +R6 N006 N004 135K +I1 5 4 4.5µ load +G2 5 N003 N008 3 7µ +G1 5 N002 N008 3 7µ +R1 5 N001 37K +R8 N009 1 .11 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 5 1 X +C5 1 3 10p +C7 5 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 4 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 4 3 A +D4 3 4 B +C6 2 3 10p +G4 0 N010 5 3 table(3 4.7m 10 5.8m) +C4 5 N003 5p Rser=.5G Rpar=2G +.model PN PNP(BF=25 Cje=500p Cjc=500p TF=20n) +.model NA NPN(BF=5Meg Cje=.2p Cjc=.2p Re=2) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.1) +.model B D(Ron=3 Vrev=7.05 Vfwd=.6) +.ends LT1529-5 +* +.subckt LT1529 1 2 3 4 5 +Q1 N009 N001 5 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N005 0 NP temp=27 +C1 N002 N003 20p Rser=200K +Q4 N003 N003 N004 0 NP 10 temp=27 +R2 N004 3 2K +R3 N005 3 2.4K +C2 1 N003 10p Rser=2K +Q5 1 2 N006 0 FB temp=27 +R6 N006 N004 95.2K +I1 5 4 4.5µ load +G2 5 N003 N008 3 7µ +G1 5 N002 N008 3 7µ +R1 5 N001 37K +R8 N009 1 .11 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 5 1 X +C5 1 3 10p +C7 5 3 10p +G5 N010 0 N008 3 table(0 3m 1 0) +A1 4 3 3 3 3 3 N008 3 SCHMITT Vt=.95 Vh=1m trise=2m +D2 4 3 A +D4 3 4 B +C6 2 3 10p +G4 0 N010 5 3 table(3 4.7m 10 5.8m) +C4 5 N003 5p Rser=.5G Rpar=2G +.model PN PNP(BF=25 Cje=500p Cjc=500p TF=20n) +.model NA NPN(BF=5Meg Cje=.2p Cjc=.2p Re=2) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=200) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model A D(Ron=110 Vfwd=6.1) +.model B D(Ron=3 Vrev=7.05 Vfwd=.6) +.ends LT1529 diff --git a/spice/copy/sub/LT1533.sub b/spice/copy/sub/LT1533.sub new file mode 100755 index 0000000..ae1bc30 Binary files /dev/null and b/spice/copy/sub/LT1533.sub differ diff --git a/spice/copy/sub/LT1534-1.sub b/spice/copy/sub/LT1534-1.sub new file mode 100755 index 0000000..b96d1c0 Binary files /dev/null and b/spice/copy/sub/LT1534-1.sub differ diff --git a/spice/copy/sub/LT1534.sub b/spice/copy/sub/LT1534.sub new file mode 100755 index 0000000..7dd83b0 Binary files /dev/null and b/spice/copy/sub/LT1534.sub differ diff --git a/spice/copy/sub/LT1568.sub b/spice/copy/sub/LT1568.sub new file mode 100755 index 0000000..63e4ef1 Binary files /dev/null and b/spice/copy/sub/LT1568.sub differ diff --git a/spice/copy/sub/LT1572.sub b/spice/copy/sub/LT1572.sub new file mode 100755 index 0000000..1786005 Binary files /dev/null and b/spice/copy/sub/LT1572.sub differ diff --git a/spice/copy/sub/LT1573.lib b/spice/copy/sub/LT1573.lib new file mode 100755 index 0000000..4ee2c9f --- /dev/null +++ b/spice/copy/sub/LT1573.lib @@ -0,0 +1,49 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005. All rights reserved. +* +.subckt LT1573 1 2 3 4 5 6 7 8 +C2 1 4 1p +Q1 N007 8 N017 0 NA +Q2 8 1 N015 0 FB +Q3 N005 N006 N015 0 FB +Q4 N005 N005 6 0 P +Q5 8 N005 6 0 P +R3 6 N006 100K +D1 N006 4 BG +R4 3 4 20K +A1 3 4 4 4 4 N016 N011 4 SCHMITT Vt=1.3 Vh=10m Trise=1u +G1 N015 4 N018 4 .75m +G2 4 N004 N002 4 Table(18m 1m 50m 2m .1 3.5m .2 6m .3 8.5m) +R9 N004 4 100 +A2 N004 5 6 6 6 6 N003 6 SCHMITT Vt=10m Vh=1m Vhigh=0 Vlow=-1 Trise=1u +Q6 N029 N003 N022 0 P +R11 6 N022 11K +Q7 2 N028 4 0 N +R12 N029 N028 1K +Q8 N029 N029 4 0 N +Q9 2 N024 N021 0 P +A3 6 4 4 4 4 4 N010 4 SCHMITT Vt=1.27 Vh=5m Trise=1u +Q11 N028 N025 6 0 P +Q12 N028 N026 N023 0 P +R15 6 N023 20K +G3 N025 4 N011 4 500n +G4 N024 4 N027 4 6.5µ +R13 6 N021 11K +D2 4 2 CLP +A5 6 7 6 6 6 6 N026 6 SCHMITT Vt=.7 Vh=1m Vhigh=0 Vlow=-1 Trise=10u +A7 2 4 4 4 4 N019 N027 4 SCHMITT Vt=1.4 Vh=10m Trise=1u +A4 N016 4 N010 4 N019 4 N018 4 AND Trise=50n +D3 6 2 ICG +C5 8 1 5p +R14 N017 4 20 +R16 5 N007 1m +G5 4 N002 5 N007 1 +R17 N002 4 1K +.model NA NPN(BF=4K Cje=10p Cjc=10p Rb=1 Br=100) +.model FB NPN(Cje=5p Cjc=5p BF=500) +.model P PNP(BF=100) +.model N NPN (BF=100) +.model BG D(Ron=1 Roff=1G Vfwd=1.265) +.model SHD SW(Ron=1 Roff=1G Vt=0.5 -Vh=0.2) +.model CLP D(Ron=100 Roff=10Meg Vrev=1.5) +.model ICG D(Ron=15K Ilimit=7u) +.ends LT1573 diff --git a/spice/copy/sub/LT1575.lib b/spice/copy/sub/LT1575.lib new file mode 100755 index 0000000..5de38df --- /dev/null +++ b/spice/copy/sub/LT1575.lib @@ -0,0 +1,390 @@ +* Copyright © Linear Technology Corp. 2014. All rights reserved. +* +.subckt LT1575-1.5 1 2 3 4 5 6 7 8 +A2 N014 0 N019 N019 N019 N019 5 N019 OTA g=15m iout=1m ref=1.21 Cout=2.8p Vhigh=1e308 Vlow=-1e308 +M1 2 N016 6 6 N temp=27 +M2 3 N016 6 6 P temp=27 +C3 2 6 1p +C4 6 3 1p +D5 N016 6 Y +R2 2 5 2Meg +R3 5 3 2Meg +G5 5 2 5 2 500m dir=1 vto=-990m +G6 3 5 3 5 500m dir=1 vto=-2.5 +G3 0 N019 3 0 .5m +G4 0 N019 2 0 .5m +C2 N019 0 .2p Rpar=1K +A1 7 8 3 3 3 3 N003 3 OTA g=1m iout=700u ref=-32m Rout=100k Cout=1p vlow=0 vhigh=1 +A3 8 4 3 3 3 3 N006 3 SCHMITT vt=500m vh=0 Rhigh=1G Rlow=100 Cout=100f +D1 N003 7 DSBDB +D2 N009 7 DSBDB +D3 2 N009 D100U +S1 3 N006 N009 3 SQ1 +A4 8 3 3 3 3 N011 3 3 SCHMITT vt=1.21 vh=0 trise=100u +S2 3 5 N010 3 SBJT1 +A5 3 N001 3 3 N011 3 N010 3 OR trise=10n +C9 N009 3 1p Rpar=50k +C11 8 3 500f +C12 7 3 500f +S4 1 2 N004 3 S15U +A6 N003 3 N006 3 N001 3 N005 3 OR trise=10n +S5 3 1 3 N004 S5U +A7 1 3 3 3 3 3 N001 3 SCHMITT vt=1.16 vh=50m trise=100n +S7 3 N016 N001 3 SBJT2 +G8 0 N012 N013 3 1µ +C14 0 N012 6f Rpar=1Meg +G9 0 N014 N012 0 1µ +C15 0 N014 6f Rpar=1Meg +G2 3 N016 5 3 1µ +C1 3 N016 .1f Rpar=1Meg +Q2 5 N003 3 0 NPN1 temp=27 +D4 2 3 DBURN1 +D6 2 3 DBURN2 +A8 2 3 3 3 3 3 ON 3 SCHMITT vt=3 vh=0 trise=10u +A9 3 N005 3 3 ON 3 N004 3 AND trise=10n IC=0 +C6 1 3 1p +G1 N012 0 2 3 88p +D7 1 3 DCLMP +C10 4 3 100f +R4 N013 3 7.75862k +R5 4 N013 1.8595k +A10 6 2 3 3 3 3 N006 3 SCHMITT vt=-.99 vh=10m Rout=10k Cout=100f +.model D100U D(Ron=100 Roff=1G vfwd=500m epsilon=500m ilimit=100u) +.model DSBDB D(Ron=100 Roff=1G vfwd=300m epsilon=200m) +.model SBJT1 SW(level=2 Ron=100 Roff=1G vt=500m vh=-200m ilimit=2m) +.model SBJT2 SW(Ron=100 Roff=1G vt=500m vh=-200m) +.model SQ1 SW(Ron=100 Roff=100k vt=700m vh=-300m) +.model DCLMP D(Ron=5k Roff=1G vfwd=1.58 epsilon=500m) +.model S15u SW(level=2 Ron=200 Roff=1G vt=500m vh=-200m ilimit=15u) +.model S5u SW(level=2 Ron=200 Roff=1G vt=-500m vh=-200m ilimit=5u) +.model NPN1 NPN BF=100 BR=1 Is=1e-016 Vaf=1k Var=20 Cjc=.5p Cje=.5p) +.model Y D(Ron=100 Roff=1G Vfwd=.95 epsilon=.1 Vrev=.95 revepsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DBURN1 D(Ron=100 Roff=1G vfwd=1.5 epsilon=500m ilimit=10.5m) +.model DBURN2 D(Ron=8k Roff=1G vfwd=7.5 epsilon=500m ilimit=5m) +.ends LT1575-1.5 +* +.subckt LT1575-2.8 1 2 3 4 5 6 7 8 +A2 N014 0 N019 N019 N019 N019 5 N019 OTA g=15m iout=1m ref=1.21 Cout=2.8p Vhigh=1e308 Vlow=-1e308 +M1 2 N016 6 6 N temp=27 +M2 3 N016 6 6 P temp=27 +C3 2 6 1p +C4 6 3 1p +D5 N016 6 Y +R2 2 5 2Meg +R3 5 3 2Meg +G5 5 2 5 2 500m dir=1 vto=-990m +G6 3 5 3 5 500m dir=1 vto=-2.5 +G3 0 N019 3 0 .5m +G4 0 N019 2 0 .5m +C2 N019 0 .2p Rpar=1K +A1 7 8 3 3 3 3 N003 3 OTA g=1m iout=700u ref=-32m Rout=100k Cout=1p vlow=0 vhigh=1 +A3 8 4 3 3 3 3 N006 3 SCHMITT vt=500m vh=0 Rhigh=1G Rlow=100 Cout=100f +D1 N003 7 DSBDB +D2 N009 7 DSBDB +D3 2 N009 D100U +S1 3 N006 N009 3 SQ1 +A4 8 3 3 3 3 N011 3 3 SCHMITT vt=1.21 vh=0 trise=100u +S2 3 5 N010 3 SBJT1 +A5 3 N001 3 3 N011 3 N010 3 OR trise=10n +C9 N009 3 1p Rpar=50k +C11 8 3 500f +C12 7 3 500f +S4 1 2 N004 3 S15U +A6 N003 3 N006 3 N001 3 N005 3 OR trise=10n +S5 3 1 3 N004 S5U +A7 1 3 3 3 3 3 N001 3 SCHMITT vt=1.16 vh=50m trise=100n +S7 3 N016 N001 3 SBJT2 +G8 0 N012 N013 3 1µ +C14 0 N012 6f Rpar=1Meg +G9 0 N014 N012 0 1µ +C15 0 N014 6f Rpar=1Meg +G2 3 N016 5 3 1µ +C1 3 N016 .1f Rpar=1Meg +Q2 5 N003 3 0 NPN1 temp=27 +D4 2 3 DBURN1 +D6 2 3 DBURN2 +A8 2 3 3 3 3 3 ON 3 SCHMITT vt=3 vh=0 trise=10u +A9 3 N005 3 3 ON 3 N004 3 AND trise=10n IC=0 +C6 1 3 1p +G1 N012 0 2 3 88p +D7 1 3 DCLMP +C10 4 3 100f +R4 N013 3 4.9308k +R5 4 N013 6.47933k +A10 6 2 3 3 3 3 N006 3 SCHMITT vt=-.99 vh=10m Rout=10k Cout=100f +.model D100U D(Ron=100 Roff=1G vfwd=500m epsilon=500m ilimit=100u) +.model DSBDB D(Ron=100 Roff=1G vfwd=300m epsilon=200m) +.model SBJT1 SW(level=2 Ron=100 Roff=1G vt=500m vh=-200m ilimit=2m) +.model SBJT2 SW(Ron=100 Roff=1G vt=500m vh=-200m) +.model SQ1 SW(Ron=100 Roff=100k vt=700m vh=-300m) +.model DCLMP D(Ron=5k Roff=1G vfwd=1.58 epsilon=500m) +.model S15u SW(level=2 Ron=200 Roff=1G vt=500m vh=-200m ilimit=15u) +.model S5u SW(level=2 Ron=200 Roff=1G vt=-500m vh=-200m ilimit=5u) +.model NPN1 NPN BF=100 BR=1 Is=1e-016 Vaf=1k Var=20 Cjc=.5p Cje=.5p) +.model Y D(Ron=100 Roff=1G Vfwd=.95 epsilon=.1 Vrev=.95 revepsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DBURN1 D(Ron=100 Roff=1G vfwd=1.5 epsilon=500m ilimit=10.5m) +.model DBURN2 D(Ron=8k Roff=1G vfwd=7.5 epsilon=500m ilimit=5m) +.ends LT1575-2.8 +* +.subckt LT1575-3.3 1 2 3 4 5 6 7 8 +A2 N014 0 N019 N019 N019 N019 5 N019 OTA g=15m iout=1m ref=1.21 Cout=2.8p Vhigh=1e308 Vlow=-1e308 +M1 2 N016 6 6 N temp=27 +M2 3 N016 6 6 P temp=27 +C3 2 6 1p +C4 6 3 1p +D5 N016 6 Y +R2 2 5 2Meg +R3 5 3 2Meg +G5 5 2 5 2 500m dir=1 vto=-990m +G6 3 5 3 5 500m dir=1 vto=-2.5 +G3 0 N019 3 0 .5m +G4 0 N019 2 0 .5m +C2 N019 0 .2p Rpar=1K +A1 7 8 3 3 3 3 N003 3 OTA g=1m iout=700u ref=-32m Rout=100k Cout=1p vlow=0 vhigh=1 +A3 8 4 3 3 3 3 N006 3 SCHMITT vt=500m vh=0 Rhigh=1G Rlow=100 Cout=100f +D1 N003 7 DSBDB +D2 N009 7 DSBDB +D3 2 N009 D100U +S1 3 N006 N009 3 SQ1 +A4 8 3 3 3 3 N011 3 3 SCHMITT vt=1.21 vh=0 trise=100u +S2 3 5 N010 3 SBJT1 +A5 3 N001 3 3 N011 3 N010 3 OR trise=10n +C9 N009 3 1p Rpar=50k +C11 8 3 500f +C12 7 3 500f +S4 1 2 N004 3 S15U +A6 N003 3 N006 3 N001 3 N005 3 OR trise=10n +S5 3 1 3 N004 S5U +A7 1 3 3 3 3 3 N001 3 SCHMITT vt=1.16 vh=50m trise=100n +S7 3 N016 N001 3 SBJT2 +G8 0 N012 N013 3 1µ +C14 0 N012 6f Rpar=1Meg +G9 0 N014 N012 0 1µ +C15 0 N014 6f Rpar=1Meg +G2 3 N016 5 3 1µ +C1 3 N016 .1f Rpar=1Meg +Q2 5 N003 3 0 NPN1 temp=27 +D4 2 3 DBURN1 +D6 2 3 DBURN2 +A8 2 3 3 3 3 3 ON 3 SCHMITT vt=3 vh=0 trise=10u +A9 3 N005 3 3 ON 3 N004 3 AND trise=10n IC=0 +C6 1 3 1p +G1 N012 0 2 3 88p +D7 1 3 DCLMP +C10 4 3 100f +R4 N013 3 5.2105k +R5 4 N013 9k +A10 6 2 3 3 3 3 N006 3 SCHMITT vt=-.99 vh=10m Rout=10k Cout=100f +.model D100U D(Ron=100 Roff=1G vfwd=500m epsilon=500m ilimit=100u) +.model DSBDB D(Ron=100 Roff=1G vfwd=300m epsilon=200m) +.model SBJT1 SW(level=2 Ron=100 Roff=1G vt=500m vh=-200m ilimit=2m) +.model SBJT2 SW(Ron=100 Roff=1G vt=500m vh=-200m) +.model SQ1 SW(Ron=100 Roff=100k vt=700m vh=-300m) +.model DCLMP D(Ron=5k Roff=1G vfwd=1.58 epsilon=500m) +.model S15u SW(level=2 Ron=200 Roff=1G vt=500m vh=-200m ilimit=15u) +.model S5u SW(level=2 Ron=200 Roff=1G vt=-500m vh=-200m ilimit=5u) +.model NPN1 NPN BF=100 BR=1 Is=1e-016 Vaf=1k Var=20 Cjc=.5p Cje=.5p) +.model Y D(Ron=100 Roff=1G Vfwd=.95 epsilon=.1 Vrev=.95 revepsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DBURN1 D(Ron=100 Roff=1G vfwd=1.5 epsilon=500m ilimit=10.5m) +.model DBURN2 D(Ron=8k Roff=1G vfwd=7.5 epsilon=500m ilimit=5m) +.ends LT1575-3.3 +* +.subckt LT1575-3.5 1 2 3 4 5 6 7 8 +A2 N014 0 N019 N019 N019 N019 5 N019 OTA g=15m iout=1m ref=1.21 Cout=2.8p Vhigh=1e308 Vlow=-1e308 +M1 2 N016 6 6 N temp=27 +M2 3 N016 6 6 P temp=27 +C3 2 6 1p +C4 6 3 1p +D5 N016 6 Y +R2 2 5 2Meg +R3 5 3 2Meg +G5 5 2 5 2 500m dir=1 vto=-990m +G6 3 5 3 5 500m dir=1 vto=-2.5 +G3 0 N019 3 0 .5m +G4 0 N019 2 0 .5m +C2 N019 0 .2p Rpar=1K +A1 7 8 3 3 3 3 N003 3 OTA g=1m iout=700u ref=-32m Rout=100k Cout=1p vlow=0 vhigh=1 +A3 8 4 3 3 3 3 N006 3 SCHMITT vt=500m vh=0 Rhigh=1G Rlow=100 Cout=100f +D1 N003 7 DSBDB +D2 N009 7 DSBDB +D3 2 N009 D100U +S1 3 N006 N009 3 SQ1 +A4 8 3 3 3 3 N011 3 3 SCHMITT vt=1.21 vh=0 trise=100u +S2 3 5 N010 3 SBJT1 +A5 3 N001 3 3 N011 3 N010 3 OR trise=10n +C9 N009 3 1p Rpar=50k +C11 8 3 500f +C12 7 3 500f +S4 1 2 N004 3 S15U +A6 N003 3 N006 3 N001 3 N005 3 OR trise=10n +S5 3 1 3 N004 S5U +A7 1 3 3 3 3 3 N001 3 SCHMITT vt=1.16 vh=50m trise=100n +S7 3 N016 N001 3 SBJT2 +G8 0 N012 N013 3 1µ +C14 0 N012 6f Rpar=1Meg +G9 0 N014 N012 0 1µ +C15 0 N014 6f Rpar=1Meg +G2 3 N016 5 3 1µ +C1 3 N016 .1f Rpar=1Meg +Q2 5 N003 3 0 NPN1 temp=27 +D4 2 3 DBURN1 +D6 2 3 DBURN2 +A8 2 3 3 3 3 3 ON 3 SCHMITT vt=3 vh=0 trise=10u +A9 3 N005 3 3 ON 3 N004 3 AND trise=10n IC=0 +C6 1 3 1p +G1 N012 0 2 3 88p +D7 1 3 DCLMP +C10 4 3 100f +R4 N013 3 5.349345k +R5 4 N013 10.124k +A10 6 2 3 3 3 3 N006 3 SCHMITT vt=-.99 vh=10m Rout=10k Cout=100f +.model D100U D(Ron=100 Roff=1G vfwd=500m epsilon=500m ilimit=100u) +.model DSBDB D(Ron=100 Roff=1G vfwd=300m epsilon=200m) +.model SBJT1 SW(level=2 Ron=100 Roff=1G vt=500m vh=-200m ilimit=2m) +.model SBJT2 SW(Ron=100 Roff=1G vt=500m vh=-200m) +.model SQ1 SW(Ron=100 Roff=100k vt=700m vh=-300m) +.model DCLMP D(Ron=5k Roff=1G vfwd=1.58 epsilon=500m) +.model S15u SW(level=2 Ron=200 Roff=1G vt=500m vh=-200m ilimit=15u) +.model S5u SW(level=2 Ron=200 Roff=1G vt=-500m vh=-200m ilimit=5u) +.model NPN1 NPN BF=100 BR=1 Is=1e-016 Vaf=1k Var=20 Cjc=.5p Cje=.5p) +.model Y D(Ron=100 Roff=1G Vfwd=.95 epsilon=.1 Vrev=.95 revepsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DBURN1 D(Ron=100 Roff=1G vfwd=1.5 epsilon=500m ilimit=10.5m) +.model DBURN2 D(Ron=8k Roff=1G vfwd=7.5 epsilon=500m ilimit=5m) +.ends LT1575-3.5 +* +.subckt LT1575-5 1 2 3 4 5 6 7 8 +A2 N014 0 N019 N019 N019 N019 5 N019 OTA g=15m iout=1m ref=1.21 Cout=2.8p Vhigh=1e308 Vlow=-1e308 +M1 2 N016 6 6 N temp=27 +M2 3 N016 6 6 P temp=27 +C3 2 6 1p +C4 6 3 1p +D5 N016 6 Y +R2 2 5 2Meg +R3 5 3 2Meg +G5 5 2 5 2 500m dir=1 vto=-990m +G6 3 5 3 5 500m dir=1 vto=-2.5 +G3 0 N019 3 0 .5m +G4 0 N019 2 0 .5m +C2 N019 0 .2p Rpar=1K +A1 7 8 3 3 3 3 N003 3 OTA g=1m iout=700u ref=-32m Rout=100k Cout=1p vlow=0 vhigh=1 +A3 8 4 3 3 3 3 N006 3 SCHMITT vt=500m vh=0 Rhigh=1G Rlow=100 Cout=100f +D1 N003 7 DSBDB +D2 N009 7 DSBDB +D3 2 N009 D100U +S1 3 N006 N009 3 SQ1 +A4 8 3 3 3 3 N011 3 3 SCHMITT vt=1.21 vh=0 trise=100u +S2 3 5 N010 3 SBJT1 +A5 3 N001 3 3 N011 3 N010 3 OR trise=10n +C9 N009 3 1p Rpar=50k +C11 8 3 500f +C12 7 3 500f +S4 1 2 N004 3 S15U +A6 N003 3 N006 3 N001 3 N005 3 OR trise=10n +S5 3 1 3 N004 S5U +A7 1 3 3 3 3 3 N001 3 SCHMITT vt=1.16 vh=50m trise=100n +S7 3 N016 N001 3 SBJT2 +G8 0 N012 N013 3 1µ +C14 0 N012 6f Rpar=1Meg +G9 0 N014 N012 0 1µ +C15 0 N014 6f Rpar=1Meg +G2 3 N016 5 3 1µ +C1 3 N016 .1f Rpar=1Meg +Q2 5 N003 3 0 NPN1 temp=27 +D4 2 3 DBURN1 +D6 2 3 DBURN2 +A8 2 3 3 3 3 3 ON 3 SCHMITT vt=3 vh=0 trise=10u +A9 3 N005 3 3 ON 3 N004 3 AND trise=10n IC=0 +C6 1 3 1p +G1 N012 0 2 3 88p +D7 1 3 DCLMP +C10 4 3 100f +R4 N013 3 6.5963k +R5 4 N013 20.6611k +A10 6 2 3 3 3 3 N006 3 SCHMITT vt=-.99 vh=10m Rout=10k Cout=100f +.model D100U D(Ron=100 Roff=1G vfwd=500m epsilon=500m ilimit=100u) +.model DSBDB D(Ron=100 Roff=1G vfwd=300m epsilon=200m) +.model SBJT1 SW(level=2 Ron=100 Roff=1G vt=500m vh=-200m ilimit=2m) +.model SBJT2 SW(Ron=100 Roff=1G vt=500m vh=-200m) +.model SQ1 SW(Ron=100 Roff=100k vt=700m vh=-300m) +.model DCLMP D(Ron=5k Roff=1G vfwd=1.58 epsilon=500m) +.model S15u SW(level=2 Ron=200 Roff=1G vt=500m vh=-200m ilimit=15u) +.model S5u SW(level=2 Ron=200 Roff=1G vt=-500m vh=-200m ilimit=5u) +.model NPN1 NPN BF=100 BR=1 Is=1e-016 Vaf=1k Var=20 Cjc=.5p Cje=.5p) +.model Y D(Ron=100 Roff=1G Vfwd=.95 epsilon=.1 Vrev=.95 revepsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DBURN1 D(Ron=100 Roff=1G vfwd=1.5 epsilon=500m ilimit=10.5m) +.model DBURN2 D(Ron=8k Roff=1G vfwd=7.5 epsilon=500m ilimit=5m) +.ends LT1575-5 +* +.subckt LT1575 1 2 3 4 5 6 7 8 +A2 N013 0 N018 N018 N018 N018 5 N018 OTA g=15m iout=1m ref=1.21 Cout=2.8p Vhigh=1e308 Vlow=-1e308 +M1 2 N015 6 6 N temp=27 +M2 3 N015 6 6 P temp=27 +C3 2 6 1p +C4 6 3 1p +D5 N015 6 Y +R2 2 5 2Meg +R3 5 3 2Meg +G5 5 2 5 2 500m dir=1 vto=-990m +G6 3 5 3 5 500m dir=1 vto=-2.5 +G3 0 N018 3 0 .5m +G4 0 N018 2 0 .5m +C2 N018 0 .2p Rpar=1K +A1 7 8 3 3 3 3 N003 3 OTA g=1m iout=700u ref=-32m Rout=100k Cout=1p vlow=0 vhigh=1 +A3 6 2 3 3 3 3 N006 3 SCHMITT vt=-.99 vh=10m Rout=10k Cout=100f +D1 N003 7 DSBDB +D2 N009 7 DSBDB +D3 2 N009 D100U +S1 3 N006 N009 3 SQ1 +A4 8 3 3 3 3 N011 3 3 SCHMITT vt=1.21 vh=0 trise=100u +S2 3 5 N010 3 SBJT1 +A5 3 N001 3 3 N011 3 N010 3 OR trise=10n +C9 N009 3 1p Rpar=50k +C11 8 3 500f +C12 7 3 500f +S4 1 2 N004 3 S15U +A6 N003 3 N006 3 N001 3 N005 3 OR trise=10n +S5 3 1 3 N004 S5U +A7 1 3 3 3 3 3 N001 3 SCHMITT vt=1.16 vh=50m trise=100n +S7 3 N015 N001 3 SBJT2 +G8 0 N012 4 3 1µ +C14 0 N012 6f Rpar=1Meg +G9 0 N013 N012 0 1µ +C15 0 N013 6f Rpar=1Meg +G2 3 N015 5 3 1µ +C1 3 N015 .1f Rpar=1Meg +Q2 5 N003 3 0 NPN1 temp=27 +D4 2 3 DBURN1 +D6 2 3 DBURN2 +A8 2 3 3 3 3 3 ON 3 SCHMITT vt=3 vh=0 trise=10u +A9 3 N005 3 3 ON 3 N004 3 AND trise=10n IC=0 +C6 1 3 1p +G1 N012 0 2 3 88p +D7 1 3 DCLMP +C10 4 3 100f +D8 2 4 DBIAS +.model D100U D(Ron=100 Roff=1G vfwd=500m epsilon=500m ilimit=100u) +.model DSBDB D(Ron=100 Roff=1G vfwd=300m epsilon=200m) +.model SBJT1 SW(level=2 Ron=100 Roff=1G vt=500m vh=-200m ilimit=2m) +.model SBJT2 SW(Ron=100 Roff=1G vt=500m vh=-200m) +.model SQ1 SW(Ron=100 Roff=100k vt=700m vh=-300m) +.model DCLMP D(Ron=5k Roff=1G vfwd=1.58 epsilon=500m) +.model S15u SW(level=2 Ron=200 Roff=1G vt=500m vh=-200m ilimit=15u) +.model S5u SW(level=2 Ron=200 Roff=1G vt=-500m vh=-200m ilimit=5u) +.model NPN1 NPN BF=100 BR=1 Is=1e-016 Vaf=1k Var=20 Cjc=.5p Cje=.5p) +.model DBIAS D(Ron=1k Roff=1G vfwd=2 epsilon=500m ilimit=.6u) +.model Y D(Ron=100 Roff=1G Vfwd=.95 epsilon=.1 Vrev=.95 revepsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DBURN1 D(Ron=100 Roff=1G vfwd=1.5 epsilon=500m ilimit=10.5m) +.model DBURN2 D(Ron=8k Roff=1G vfwd=7.5 epsilon=500m ilimit=5m) +.ends LT1575 diff --git a/spice/copy/sub/LT1576.sub b/spice/copy/sub/LT1576.sub new file mode 100755 index 0000000..89914e0 Binary files /dev/null and b/spice/copy/sub/LT1576.sub differ diff --git a/spice/copy/sub/LT1578-2.5.sub b/spice/copy/sub/LT1578-2.5.sub new file mode 100755 index 0000000..7932782 Binary files /dev/null and b/spice/copy/sub/LT1578-2.5.sub differ diff --git a/spice/copy/sub/LT1578.sub b/spice/copy/sub/LT1578.sub new file mode 100755 index 0000000..bee5f96 Binary files /dev/null and b/spice/copy/sub/LT1578.sub differ diff --git a/spice/copy/sub/LT1584.lib b/spice/copy/sub/LT1584.lib new file mode 100755 index 0000000..e5c6239 --- /dev/null +++ b/spice/copy/sub/LT1584.lib @@ -0,0 +1,433 @@ +* Copyright © Linear Technology Corp. 2014. All rights reserved. +* +.subckt LT1580-2.5 1 2 3 4 5 6 +Q1 C N003 4 0 NOUT temp=27 +Q2 N002 3 N005 0 N temp=27 +D1 6 N002 DBG1 +C1 N002 3 100f +C2 N002 1 50p Rser=100k +C3 6 N002 200f Rpar=233Meg +C4 1 N005 50p Rser=10 Rpar=10.974k +C5 3 N005 100f +C6 6 N005 200f +G1 3 X N002 3 1µ +C7 X 3 500f Rpar=1Meg +C8 6 X 150f +R3 5 C 61m +S1 3 X 5 C SCL +G3 N002 1 5 C 72n +B1 6 N003 I=(.5+.5*tanh((V(C,4)-115m)/10m))*dnlim(310m*V(X,3),1.69m, 100u) +D2 N003 4 DBETA +R1 3 1 208.732 +R2 1 2 207 +.model N NPN(BF=125 Is=1e-16) +.model NOUT NPN (BF=280 IKF=9.5 IS=1e-12 Cjc=100p Cje=100p VAF=100) +.model DBETA D(Ron=1 Roff=1Meg vfwd=500m epsilon=100m ilimit=4m) +.model DBG1 D(Ron=100 Roff=1G vfwd=600m epsilon=400m ilimit=50u) +.model SCL SW(Ron=1 Roff=100Meg vt=489m vh=-50m) +.model DMINI D(Ron=100 Roff=1Meg vfwd=500m epsilon=100m ilimit=3m) +.ends LT1580-2.5 +* +.subckt LT1580 1 2 3 4 5 6 +Q1 C N003 4 0 NOUT temp=27 +Q2 N002 3 N005 0 N temp=27 +D1 6 N002 DBG1 +C1 N002 3 100f +C2 N002 1 50p Rser=100k +C3 6 N002 200f Rpar=233Meg +C4 1 N005 50p Rser=10 Rpar=10.974k +C5 3 N005 100f +C6 6 N005 200f +G1 3 X N002 3 1µ +C7 X 3 500f Rpar=1Meg +C8 6 X 150f +R3 5 C 61m +S1 3 X 5 C SCL +G3 N002 1 5 C 72n +B1 6 N003 I=(.5+.5*tanh((V(C,4)-115m)/10m))*dnlim(310m*V(X,3),1.69m, 100u) +D2 N003 4 DBETA +.model N NPN(BF=125 Is=1e-16) +.model NOUT NPN (BF=280 IKF=9.5 IS=1e-12 Cjc=100p Cje=100p VAF=100) +.model DBETA D(Ron=1 Roff=1Meg vfwd=500m epsilon=100m ilimit=4m) +.model DBG1 D(Ron=100 Roff=1G vfwd=600m epsilon=400m ilimit=50u) +.model SCL SW(Ron=1 Roff=100Meg vt=489m vh=-50m) +.model DMINI D(Ron=100 Roff=1Meg vfwd=500m epsilon=100m ilimit=3m) +.ends LT1580 +* +.subckt LT1581-2.5 1 2 3 4 5 6 +R4 1 2 207 +Q1 C N003 4 0 NOUT temp=27 +Q2 N002 3 N005 0 N temp=27 +D1 6 N002 DBG1 +C1 N002 3 100f +C2 N002 1 50p Rser=100k +C3 6 N002 200f Rpar=195Meg +C4 1 N005 50p Rser=10 Rpar=9.0684k +C5 3 N005 100f +C6 6 N005 200f +G1 3 X N002 3 1µ +C7 X 3 500f Rpar=1Meg +C8 6 X 150f +R5 5 C 30.8m +S1 3 X 5 C SCL +G2 N002 1 5 C 121n +B1 6 N003 I=(.5+.5*tanh((V(C,4)-130m)/10m))*dnlim(750m*V(X,3),1.05m,100u) +D2 N003 4 DBETA +R1 3 1 209.111 +.model N NPN(BF=125 Is=1e-16) +.model NOUT NPN (BF=280 IKF=16 IS=1e-12 Cjc=100p Cje=100p VAF=100) +.model DBETA D(Ron=1 Roff=1Meg vfwd=500m epsilon=100m ilimit=4m) +.model DBG1 D(Ron=100 Roff=1G vfwd=630m epsilon=400m ilimit=60u) +.model SCL SW(Ron=1 Roff=100Meg vt=339m vh=-50m) +.model DMINI D(Ron=100 Roff=1Meg vfwd=500m epsilon=100m ilimit=3m) +.ends LT1581-2.5 +* +.subckt LT1581 1 2 3 4 5 6 +Q1 C N003 4 0 NOUT temp=27 +Q2 N002 3 N005 0 N temp=27 +D1 6 N002 DBG1 +C1 N002 3 100f +C2 N002 1 50p Rser=100k +C3 6 N002 200f Rpar=195Meg +C4 1 N005 50p Rser=10 Rpar=9.0684k +C5 3 N005 100f +C6 6 N005 200f +G1 3 X N002 3 1µ +C7 X 3 500f Rpar=1Meg +C8 6 X 150f +R3 5 C 30.8m +S1 3 X 5 C SCL +G3 N002 1 5 C 121n +B1 6 N003 I=(.5+.5*tanh((V(C,4)-130m)/10m))*dnlim(750m*V(X,3),1.05m,100u) +D2 N003 4 DBETA +.model N NPN(BF=125 Is=1e-16) +.model NOUT NPN (BF=280 IKF=16 IS=1e-12 Cjc=100p Cje=100p VAF=100) +.model DBETA D(Ron=1 Roff=1Meg vfwd=500m epsilon=100m ilimit=4m) +.model DBG1 D(Ron=100 Roff=1G vfwd=630m epsilon=400m ilimit=60u) +.model SCL SW(Ron=1 Roff=100Meg vt=339m vh=-50m) +.model DMINI D(Ron=100 Roff=1Meg vfwd=500m epsilon=100m ilimit=3m) +.ends LT1581 +* +.subckt LT1584-3.3 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 254 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),uplim(53m,71.9m-6.4m*V(3,2),1m),5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=100) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1584-3.3 +* +.subckt LT1584-3.38 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),uplim(53m,71.9m-6.4m*V(3,2),1m),5m) +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 263.9 +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=100) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1584-3.38 +* +.subckt LT1584-3.45 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 272.5 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),uplim(53m,71.9m-6.4m*V(3,2),1m),5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=100) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1584-3.45 +* +.subckt LT1584-3.6 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),uplim(53m,71.9m-6.4m*V(3,2),1m),5m) +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 291.1 +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=100) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1584-3.6 +* +.subckt LT1584 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 1 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 1 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),uplim(53m,71.9m-6.4m*V(3,2),1m),5m) +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=100) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1584 +* +.subckt LT1585-3.3 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 254 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),31.35m,5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1585-3.3 +* +.subckt LT1585-3.38 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 263.9 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),31.35m,5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1585-3.38 +* +.subckt LT1585-3.45 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 272.5 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),31.35m,5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1585-3.45 +* +.subckt LT1585-3.6 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 291.1 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),31.35m,5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1585-3.6 +* +.subckt LT1585 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 1 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 1 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),31.35m,5m) +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1585 +* +.subckt LT1587-3.3 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 254 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),24.8m,5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1587-3.3 +* +.subckt LT1587-3.38 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 263.9 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),24.8m,5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1587-3.38 +* +.subckt LT1587-3.45 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 272.5 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),24.8m,5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1587-3.45 +* +.subckt LT1587-3.6 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 N007 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 N007 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +R2 N004 N007 156 +R3 N007 1 291.1 +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),24.8m,5m) +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1587-3.6 +* +.subckt LT1587 1 2 3 +Q1 3 N002 N004 0 NOUT temp=27 +Q2 N003 N004 N006 0 N temp=27 +D1 3 N003 DBG1 +C2 N003 N004 100f +C4 N003 1 30p Rser=100k +C3 3 N003 200f Rpar=250Meg +C1 1 N006 100p Rser=10 Rpar=10k +C5 N004 N006 100f +B1 3 N002 I=uplim(dnlim(250m*V(X,2),13u,10u),24.8m,5m) +R4 2 N004 90µ +C6 3 N006 200f +G1 N004 X N003 N004 1µ +C8 X N004 500f Rpar=1Meg +C7 3 X 150f +.model N NPN(BF=125 Is=1.13e-16) +.model NOUT NPN (BF=150 IS=1e-12 Cjc=100p Cje=100p VAF=1000) +.model DBG1 D(Ron=100 Roff=1G vfwd=650m epsilon=400m ilimit=55u) +.ends LT1587 diff --git a/spice/copy/sub/LT1610.sub b/spice/copy/sub/LT1610.sub new file mode 100755 index 0000000..b07f438 Binary files /dev/null and b/spice/copy/sub/LT1610.sub differ diff --git a/spice/copy/sub/LT1611.sub b/spice/copy/sub/LT1611.sub new file mode 100755 index 0000000..701f0a0 Binary files /dev/null and b/spice/copy/sub/LT1611.sub differ diff --git a/spice/copy/sub/LT1612.sub b/spice/copy/sub/LT1612.sub new file mode 100755 index 0000000..ddac970 Binary files /dev/null and b/spice/copy/sub/LT1612.sub differ diff --git a/spice/copy/sub/LT1613.sub b/spice/copy/sub/LT1613.sub new file mode 100755 index 0000000..6f09a02 Binary files /dev/null and b/spice/copy/sub/LT1613.sub differ diff --git a/spice/copy/sub/LT1614.sub b/spice/copy/sub/LT1614.sub new file mode 100755 index 0000000..02a97e7 Binary files /dev/null and b/spice/copy/sub/LT1614.sub differ diff --git a/spice/copy/sub/LT1615-1.sub b/spice/copy/sub/LT1615-1.sub new file mode 100755 index 0000000..b8cf795 --- /dev/null +++ b/spice/copy/sub/LT1615-1.sub @@ -0,0 +1,6 @@ + + + +`æOyXÂ!©ð¸{䄱œ8c=jô€f¥z]«¾vGö÷*‡9Nà5mÖJš±Â†l$‰þf劦"MCnrö2gÍà—$./3¨ÇÅY¨ªUáQ~»¿ëQäZ±HW{î! N]â!w^0u6°)ªw5ã>HOnZfÈ\s$+$ôk®Ù"[¡ŠsmwmÖ„q\æÜHœ36z¨÷ªHˆkÍ?Œ›ý ¾½” …§!>óoJ€îh¢Ò’ WW:`Ö2¬o£„xÒÔʾ~‚î Í׫˯„ƒ «_™ž%½……\ðÌÚŸÓÄƣæù©µÍ>Ñ×F ü±—Ìð²+R½Ó%TÌa:o»y9rq™Ø Ú¦`¤ýB*­"ÎeåaÒŒ©;úà•dûâAê_|úܪR–3œ)¸3 !%ŸŸøzúñÞ8%¢;O´ĬÖIÒ- ë}ng™¸-fk|•öœCŠ2_X'VrÓ)It94ºêH6Ö Yñ'ûÁ4iϧPjnÜ–Ôø<ôjg‘QJ×ö-Y(&kVH=%•ˆ?¶ ­¿Ÿ~ÐtóåÌùÎe–]:Æ¿ d¼½¯ÕóçóÆUiàhXœ®w&þœc@ˆcM—؃ÐÆàJ˜+&E¼ +Ý7ÐMR~˜0$<‰CÍPD3}v˜ Z‰õHj,^Sy{ÛiF¨ÕÃ;cE½O9º ™”(Wç¼/,„ê0 OK4ONª*rWœª|þ-EWJE³­¥nÃPnDH<„ ›Xj~Sw2‘¶ð`.èau?t‚W +µP7 <=S¼èå„1×ñ.[›Cà(ªZAÌöu Qò¼™C{oÕ0E’©mtZG&`ó$fÞ±¶D‹³ˆÕ—…åüK á»B<§YÞ3ÙƒQÀìÓ•¦‚â‚Ùœh°É(<“4Ñ(¯ßD²è9(‡ëË"•P7±DŠ22Í.L \ No newline at end of file diff --git a/spice/copy/sub/LT1615.sub b/spice/copy/sub/LT1615.sub new file mode 100755 index 0000000..aa6e67a Binary files /dev/null and b/spice/copy/sub/LT1615.sub differ diff --git a/spice/copy/sub/LT1616.sub b/spice/copy/sub/LT1616.sub new file mode 100755 index 0000000..06683ec Binary files /dev/null and b/spice/copy/sub/LT1616.sub differ diff --git a/spice/copy/sub/LT1617-1.sub b/spice/copy/sub/LT1617-1.sub new file mode 100755 index 0000000..4795604 Binary files /dev/null and b/spice/copy/sub/LT1617-1.sub differ diff --git a/spice/copy/sub/LT1617.sub b/spice/copy/sub/LT1617.sub new file mode 100755 index 0000000..d2f4870 Binary files /dev/null and b/spice/copy/sub/LT1617.sub differ diff --git a/spice/copy/sub/LT1618.sub b/spice/copy/sub/LT1618.sub new file mode 100755 index 0000000..54aea2f Binary files /dev/null and b/spice/copy/sub/LT1618.sub differ diff --git a/spice/copy/sub/LT1619.sub b/spice/copy/sub/LT1619.sub new file mode 100755 index 0000000..b08a79c Binary files /dev/null and b/spice/copy/sub/LT1619.sub differ diff --git a/spice/copy/sub/LT1620.sub b/spice/copy/sub/LT1620.sub new file mode 100755 index 0000000..04bf267 Binary files /dev/null and b/spice/copy/sub/LT1620.sub differ diff --git a/spice/copy/sub/LT1620S8.sub b/spice/copy/sub/LT1620S8.sub new file mode 100755 index 0000000..1694b55 Binary files /dev/null and b/spice/copy/sub/LT1620S8.sub differ diff --git a/spice/copy/sub/LT1621.sub b/spice/copy/sub/LT1621.sub new file mode 100755 index 0000000..5dd331b Binary files /dev/null and b/spice/copy/sub/LT1621.sub differ diff --git a/spice/copy/sub/LT1641-1.sub b/spice/copy/sub/LT1641-1.sub new file mode 100755 index 0000000..91fca6f Binary files /dev/null and b/spice/copy/sub/LT1641-1.sub differ diff --git a/spice/copy/sub/LT1641-2.sub b/spice/copy/sub/LT1641-2.sub new file mode 100755 index 0000000..797272d Binary files /dev/null and b/spice/copy/sub/LT1641-2.sub differ diff --git a/spice/copy/sub/LT1676.sub b/spice/copy/sub/LT1676.sub new file mode 100755 index 0000000..300a7c0 Binary files /dev/null and b/spice/copy/sub/LT1676.sub differ diff --git a/spice/copy/sub/LT1680.sub b/spice/copy/sub/LT1680.sub new file mode 100755 index 0000000..b5d1df7 Binary files /dev/null and b/spice/copy/sub/LT1680.sub differ diff --git a/spice/copy/sub/LT1681.sub b/spice/copy/sub/LT1681.sub new file mode 100755 index 0000000..3b6e939 Binary files /dev/null and b/spice/copy/sub/LT1681.sub differ diff --git a/spice/copy/sub/LT1683.sub b/spice/copy/sub/LT1683.sub new file mode 100755 index 0000000..757d2f6 Binary files /dev/null and b/spice/copy/sub/LT1683.sub differ diff --git a/spice/copy/sub/LT1725.sub b/spice/copy/sub/LT1725.sub new file mode 100755 index 0000000..5bee4a2 Binary files /dev/null and b/spice/copy/sub/LT1725.sub differ diff --git a/spice/copy/sub/LT1737.sub b/spice/copy/sub/LT1737.sub new file mode 100755 index 0000000..07029bc Binary files /dev/null and b/spice/copy/sub/LT1737.sub differ diff --git a/spice/copy/sub/LT1738.sub b/spice/copy/sub/LT1738.sub new file mode 100755 index 0000000..8a17adc Binary files /dev/null and b/spice/copy/sub/LT1738.sub differ diff --git a/spice/copy/sub/LT1761.lib b/spice/copy/sub/LT1761.lib new file mode 100755 index 0000000..dadea79 --- /dev/null +++ b/spice/copy/sub/LT1761.lib @@ -0,0 +1,434 @@ +* Copyright © Linear Technology Corp. 2012. All rights reserved. +* +.subckt LT1761-1.2 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N010 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 2 12K +R3 N010 2 10K +C2 5 N003 15p +Q5 5 5 N009 0 FB temp=27 +R6 N009 4 102.5K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 5 2 10p +C7 1 2 10p +C8 4 2 1p +R10 5 2 244K +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-1.2 +* +.subckt LT1761-1.5 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N011 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 2 12K +R3 N011 2 10K +C2 5 N003 15p +Q5 5 N009 N010 0 FB temp=27 +R6 N010 4 106.8K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 5 2 10p +C7 1 2 10p +C8 4 2 1p +R9 5 N009 56K +R10 N009 2 244K +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-1.5 +* +.subckt LT1761-1.8 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N011 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 2 12K +R3 N011 2 10K +C2 5 N003 15p +Q5 5 N009 N010 0 FB temp=27 +R6 N010 4 106.8K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 5 2 10p +C7 1 2 10p +C8 4 2 1p +R9 5 N009 116K +R10 N009 2 244K +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-1.8 +* +.subckt LT1761-2.5 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N011 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 2 12K +R3 N011 2 10K +C2 5 N003 15p +Q5 5 N009 N010 0 FB temp=27 +R6 N010 4 106.8K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 5 2 10p +C7 1 2 10p +C8 4 2 1p +R9 5 N009 255K +R10 N009 2 244K +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-2.5 +* +.subckt LT1761-2.8 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N011 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 2 12K +R3 N011 2 10K +C2 5 N003 15p +Q5 5 N009 N010 0 FB temp=27 +R6 N010 4 106.8K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 5 2 10p +C7 1 2 10p +C8 4 2 1p +R9 5 N009 315K +R10 N009 2 244K +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-2.8 +* +.subckt LT1761-2 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N011 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 2 12K +R3 N011 2 10K +C2 5 N003 15p +Q5 5 N009 N010 0 FB temp=27 +R6 N010 4 106.8K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 5 2 10p +C7 1 2 10p +C8 4 2 1p +R9 5 N009 156K +R10 N009 2 244K +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-2 +* +.subckt LT1761-3.3 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N011 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 2 12K +R3 N011 2 10K +C2 5 N003 15p +Q5 5 N009 N010 0 FB temp=27 +R6 N010 4 106.8K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 5 2 10p +C7 1 2 10p +C8 4 2 1p +R9 5 N009 415K +R10 N009 2 244K +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-3.3 +* +.subckt LT1761-3 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N011 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 2 12K +R3 N011 2 10K +C2 5 N003 15p +Q5 5 N009 N010 0 FB temp=27 +R6 N010 4 106.8K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 5 2 10p +C7 1 2 10p +C8 4 2 1p +R9 5 N009 355K +R10 N009 2 244K +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-3 +* +.subckt LT1761-5 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N011 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 2 12K +R3 N011 2 10K +C2 5 N003 15p +Q5 5 N009 N010 0 FB temp=27 +R6 N010 4 106.8K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 5 2 10p +C7 1 2 10p +C8 4 2 1p +R9 5 N009 754K +R10 N009 2 244K +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-5 +* +.subckt LT1761-BYP 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N010 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 3 0 NP 10 temp=27 +R2 3 2 12K +R3 N010 2 10K +C2 5 N003 15p +Q5 5 4 N009 0 FB temp=27 +R6 N009 3 106.8K +A1 1 2 2 2 2 2 N001 2 SCHMITT Vt=.8 Vh=1m tau=1u +G2 1 N003 N001 2 1.2µ +G1 1 N008 N001 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 4 2 1p +C6 5 2 10p +C7 1 2 10p +C8 3 2 1p +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-BYP +* +.subckt LT1761-SD 1 2 3 4 5 +Q1 N006 N004 1 0 PN +Q2 N004 N008 2 0 NA +Q3 N008 N003 N010 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 N011 0 NP 10 temp=27 +R2 N011 2 12K +R3 N010 2 10K +C2 5 N003 15p +Q5 5 4 N009 0 FB temp=27 +R6 N009 N011 106.8K +R5 3 2 20Meg +I1 3 2 1µ load +A1 3 2 2 2 2 2 N002 2 SCHMITT Vt=.8 Vh=1m trise=1m +G2 1 N003 N002 2 1.2µ +G1 1 N008 N002 2 1.2µ +R1 1 N004 600K +R8 N006 5 1.17 +A2 N005 0 N008 N008 N008 N008 2 N008 VARISTOR +D3 0 N005 F +G3 0 N005 5 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 1 5 X +C5 4 2 1p +C6 5 2 10p +C7 1 2 10p +G4 0 N005 1 0 table(1.3 1m 2.4 3m 10 4m) +G5 N005 0 N002 2 table(0 3m 1 0) +C4 1 N003 100p Rser=.01G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1761-SD diff --git a/spice/copy/sub/LT1762.lib b/spice/copy/sub/LT1762.lib new file mode 100755 index 0000000..49db5cc --- /dev/null +++ b/spice/copy/sub/LT1762.lib @@ -0,0 +1,209 @@ +* Copyright © Linear Technology Corp. 2011. All rights reserved. +* +.subckt LT1762-2.5 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 4 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 12p Rser=250K +Q4 N003 N003 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N004 4 10K +C2 1 N003 15p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 3 106.8K +R5 5 4 20Meg +I1 5 4 1µ load +G2 8 N003 N008 4 1.2µ +G1 8 N002 N008 4 1.2µ +R1 8 N001 600K +R8 N009 1 .66 +A2 N010 0 N002 N002 N002 N002 4 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 4 10p +C7 8 4 10p +C8 3 4 1p +G4 0 N010 8 0 table(1.3 1m 2.4 2.1m 10 3.2m) +G5 N010 0 N008 4 table(0 2.1m 1 0) +C4 8 N002 .3p Rser=.8G +A1 5 4 4 4 4 4 N008 4 SCHMITT Vt=.8 Vh=1m trise=2m +R9 N007 4 244K +R10 2 N007 255K +C6 2 4 1p +C9 8 N003 100p Rser=.67G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1762-2.5 +* +.subckt LT1762-3.3 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 4 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 12p Rser=250K +Q4 N003 N003 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N004 4 10K +C2 1 N003 15p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 3 106.8K +R5 5 4 20Meg +I1 5 4 1µ load +G2 8 N003 N008 4 1.2µ +G1 8 N002 N008 4 1.2µ +R1 8 N001 600K +R8 N009 1 .66 +A2 N010 0 N002 N002 N002 N002 4 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 4 10p +C7 8 4 10p +C8 3 4 1p +G4 0 N010 8 0 table(1.3 1m 2.4 2.1m 10 3.2m) +G5 N010 0 N008 4 table(0 2.1m 1 0) +C4 8 N002 .3p Rser=.8G +A1 5 4 4 4 4 4 N008 4 SCHMITT Vt=.8 Vh=1m trise=2m +R9 N007 4 244K +R10 2 N007 415K +C6 2 4 1p +C9 8 N003 100p Rser=.67G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1762-3.3 +* +.subckt LT1762-3 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 4 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 12p Rser=250K +Q4 N003 N003 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N004 4 10K +C2 1 N003 15p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 3 106.8K +R5 5 4 20Meg +I1 5 4 1µ load +G2 8 N003 N008 4 1.2µ +G1 8 N002 N008 4 1.2µ +R1 8 N001 600K +R8 N009 1 .66 +A2 N010 0 N002 N002 N002 N002 4 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 4 10p +C7 8 4 10p +C8 3 4 1p +G4 0 N010 8 0 table(1.3 1m 2.4 2.1m 10 3.2m) +G5 N010 0 N008 4 table(0 2.1m 1 0) +C4 8 N002 .3p Rser=.8G +A1 5 4 4 4 4 4 N008 4 SCHMITT Vt=.8 Vh=1m trise=2m +R9 N007 4 244K +R10 2 N007 355K +C6 2 4 1p +C9 8 N003 100p Rser=.67G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1762-3 +* +.subckt LT1762-5 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 4 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 12p Rser=250K +Q4 N003 N003 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N004 4 10K +C2 1 N003 15p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 3 106.8K +R5 5 4 20Meg +I1 5 4 1µ load +G2 8 N003 N008 4 1.2µ +G1 8 N002 N008 4 1.2µ +R1 8 N001 600K +R8 N009 1 .66 +A2 N010 0 N002 N002 N002 N002 4 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 10m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 4 10p +C7 8 4 10p +C8 3 4 1p +G4 0 N010 8 0 table(1.3 1m 2.4 2.1m 10 3.2m) +G5 N010 0 N008 4 table(0 2.1m 1 0) +C4 8 N002 .3p Rser=.8G +A1 5 4 4 4 4 4 N008 4 SCHMITT Vt=.8 Vh=1m trise=2m +R9 N007 4 244K +R10 2 N007 753K +C6 2 4 1p +C9 8 N003 100p Rser=.67G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1762-5 +* +.subckt LT1762 1 2 3 4 5 6 7 8 +Q1 N008 N001 8 0 PN +Q2 N001 N002 4 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 12p Rser=250K +Q4 N003 N003 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N004 4 10K +C2 1 N003 15p +Q5 1 2 N005 0 FB temp=27 +R6 N005 3 106.8K +R5 5 4 20Meg +I1 5 4 1µ load +G2 8 N003 N007 4 1.2µ +G1 8 N002 N007 4 1.2µ +R1 8 N001 600K +R8 N008 1 .66 +A2 N009 0 N002 N002 N002 N002 4 N002 VARISTOR +D3 0 N009 F +G3 0 N009 1 N008 10m +Q7 N003 N001 N008 0 P 1m +D1 8 1 X +C5 1 4 10p +C7 8 4 10p +C8 3 4 1p +G4 0 N009 8 0 table(1.3 1m 2.4 2.1m 10 3.2m) +G5 N009 0 N007 4 table(0 2.1m 1 0) +C4 8 N002 .3p Rser=.8G +A1 5 4 4 4 4 4 N007 4 SCHMITT Vt=.8 Vh=1m trise=2m +C6 2 4 1p +C9 8 N003 100p Rser=.67G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1762 diff --git a/spice/copy/sub/LT1763.lib b/spice/copy/sub/LT1763.lib new file mode 100755 index 0000000..e98878f --- /dev/null +++ b/spice/copy/sub/LT1763.lib @@ -0,0 +1,448 @@ +* Copyright © Linear Technology Corp. 2013. All rights reserved. +* +.subckt LT1763-1.5 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 27p Rser=225K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 3 12K +R3 N004 3 10K +C2 1 N003 21p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 4 106.8K +R5 5 3 10Meg +I1 5 3 1µ load +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.75 Vh=1m trise=1m +G2 8 N003 N008 3 1.2µ +G1 8 N002 N008 3 1.2µ +R1 8 N001 600K +R8 N009 1 .1 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 20m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +C8 4 3 1p +C4 2 3 1p +R9 2 N007 56K +R10 N007 3 244K +G4 0 N010 8 0 table(1.3 1m 2.4 1.85m 10 2.3m) +G5 N010 0 N008 3 table(0 1.85m 1 0) +C6 8 N003 100p Rser=.45G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1763-1.5 +* +.subckt LT1763-1.8 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 27p Rser=225K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 3 12K +R3 N004 3 10K +C2 1 N003 21p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 4 106.8K +R5 5 3 10Meg +I1 5 3 1µ load +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.75 Vh=1m trise=1m +G2 8 N003 N008 3 1.2µ +G1 8 N002 N008 3 1.2µ +R1 8 N001 600K +R8 N009 1 .1 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 20m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +C8 4 3 1p +C4 2 3 1p +R9 2 N007 116K +R10 N007 3 244K +G4 0 N010 8 0 table(1.3 1m 2.4 1.85m 10 2.3m) +G5 N010 0 N008 3 table(0 1.85m 1 0) +C6 8 N003 100p Rser=.45G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1763-1.8 +* +.subckt LT1763-2.5 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 27p Rser=225K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 3 12K +R3 N004 3 10K +C2 1 N003 21p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 4 106.8K +R5 5 3 10Meg +I1 5 3 1µ load +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.75 Vh=1m trise=1m +G2 8 N003 N008 3 1.2µ +G1 8 N002 N008 3 1.2µ +R1 8 N001 600K +R8 N009 1 .1 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 20m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +C8 4 3 1p +C4 2 3 1p +R9 2 N007 255K +R10 N007 3 244K +G4 0 N010 8 0 table(1.3 1m 2.4 1.85m 10 2.3m) +G5 N010 0 N008 3 table(0 1.85m 1 0) +C6 8 N003 100p Rser=.45G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1763-2.5 +* +.subckt LT1763-3.3 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 27p Rser=225K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 3 12K +R3 N004 3 10K +C2 1 N003 21p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 4 106.8K +R5 5 3 10Meg +I1 5 3 1µ load +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.75 Vh=1m trise=1m +G2 8 N003 N008 3 1.2µ +G1 8 N002 N008 3 1.2µ +R1 8 N001 600K +R8 N009 1 .1 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 20m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +C8 4 3 1p +C4 2 3 1p +R9 2 N007 415K +R10 N007 3 244K +G4 0 N010 8 0 table(1.3 1m 2.4 1.85m 10 2.3m) +G5 N010 0 N008 3 table(0 1.85m 1 0) +C6 8 N003 100p Rser=.45G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1763-3.3 +* +.subckt LT1763-3 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 27p Rser=225K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 3 12K +R3 N004 3 10K +C2 1 N003 21p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 4 106.8K +R5 5 3 10Meg +I1 5 3 1µ load +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.75 Vh=1m trise=1m +G2 8 N003 N008 3 1.2µ +G1 8 N002 N008 3 1.2µ +R1 8 N001 600K +R8 N009 1 .1 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 20m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +C8 4 3 1p +C4 2 3 1p +R9 2 N007 355K +R10 N007 3 244K +G4 0 N010 8 0 table(1.3 1m 2.4 1.85m 10 2.3m) +G5 N010 0 N008 3 table(0 1.85m 1 0) +C6 8 N003 100p Rser=.45G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1763-3 +* +.subckt LT1763-5 1 2 3 4 5 6 7 8 +Q1 N009 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 27p Rser=225K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 3 12K +R3 N004 3 10K +C2 1 N003 21p +Q5 1 N007 N005 0 FB temp=27 +R6 N005 4 106.8K +R5 5 3 10Meg +I1 5 3 1µ load +A1 5 3 3 3 3 3 N008 3 SCHMITT Vt=.75 Vh=1m trise=1m +G2 8 N003 N008 3 1.2µ +G1 8 N002 N008 3 1.2µ +R1 8 N001 600K +R8 N009 1 .1 +A2 N010 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N010 F +G3 0 N010 1 N009 20m +Q7 N003 N001 N009 0 P 1m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +C8 4 3 1p +C4 2 3 1p +R9 2 N007 754K +R10 N007 3 244K +G4 0 N010 8 0 table(1.3 1m 2.4 1.85m 10 2.3m) +G5 N010 0 N008 3 table(0 1.85m 1 0) +C6 8 N003 100p Rser=.45G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1763-5 +* +.subckt LT1763 1 2 3 4 5 6 7 8 +Q1 N008 N001 8 0 PN +Q2 N001 N002 3 0 NA +Q3 N002 N003 N004 0 NP temp=27 +C1 N002 N003 27p Rser=225K +Q4 N003 N003 4 0 NP 10 temp=27 +R2 4 3 12K +R3 N004 3 10K +C2 1 N003 21p +Q5 1 2 N005 0 FB temp=27 +R6 N005 4 106.8K +R5 5 3 10Meg +I1 5 3 1µ load +A1 5 3 3 3 3 3 N007 3 SCHMITT Vt=.75 Vh=1m trise=1m +G2 8 N003 N007 3 1.2µ +G1 8 N002 N007 3 1.2µ +R1 8 N001 600K +R8 N008 1 .1 +A2 N009 0 N002 N002 N002 N002 3 N002 VARISTOR +D3 0 N009 F +G3 0 N009 1 N008 20m +Q7 N003 N001 N008 0 P 1m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +C8 4 3 1p +G5 N009 0 N007 3 table(0 1.85m 1 0) +C4 2 3 1p +G4 0 N009 8 0 table(1.3 1m 2.4 1.85m 10 2.3m) +C6 8 N003 100p Rser=.45G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1763 +* +.subckt LT3029 1 2 3 4 5 6 7 8 9 10 11 +Q1 N013 N009 8 0 PN +Q2 N009 N017 3 0 NA +Q3 N017 N007 N021 0 NP temp=27 +C1 N017 N007 27p Rser=225K +Q4 N007 N007 4 0 NP 10 temp=27 +R2 4 3 12K +R3 N021 3 10K +C2 1 N007 21p +Q5 1 2 N019 0 FB temp=27 +R6 N019 4 106.8K +R5 5 3 10Meg +I1 5 3 1µ load +A1 5 3 3 3 3 3 N002 3 SCHMITT Vt=.75 Vh=1m trise=1m +G2 8 N007 N002 3 1.2µ +G1 8 N017 N002 3 1.2µ +R1 8 N009 600K +R8 N013 1 .1 +A2 N011 0 N017 N017 N017 N017 3 N017 VARISTOR +D3 0 N011 F +G3 0 N011 1 N013 20m +Q7 N007 N009 N013 0 P 1m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +C8 4 3 1p +G5 N011 0 N002 3 table(0 1.85m 1 0) +C4 2 3 1p +G4 0 N011 8 0 table(1.3 1m 2.4 1.85m 10 2.3m) +C6 8 N007 100p Rser=.45G Rpar=6G +Q6 N014 N010 7 0 PN +Q8 N010 N018 3 0 NA +Q9 N018 N008 N022 0 NP temp=27 +C9 N018 N008 27p Rser=225K +Q10 N008 N008 11 0 NP 10 temp=27 +R4 11 3 12K +R9 N022 3 10K +C10 9 N008 21p +Q11 9 10 N020 0 FB temp=27 +R10 N020 11 106.8K +R11 6 3 10Meg +I2 6 3 1µ load +A3 6 3 3 3 3 3 N004 3 SCHMITT Vt=.75 Vh=1m trise=1m +G6 7 N008 N004 3 1.2µ +G7 7 N018 N004 3 1.2µ +R12 7 N010 600K +R13 N014 9 .1 +A4 N012 0 N018 N018 N018 N018 3 N018 VARISTOR +D2 0 N012 F +G8 0 N012 9 N014 20m +Q12 N008 N010 N014 0 P 1m +D4 7 9 X +C12 9 3 10p +C13 7 3 10p +C14 11 3 1p +G9 N012 0 N004 3 table(0 1.85m 1 0) +C15 10 3 1p +G10 0 N012 7 0 table(1.3 1m 2.4 1.85m 10 2.3m) +C16 7 N008 100p Rser=.45G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT3029 +* +.subckt LT3030 1 2 3 4 5 6 7 8 9 10 11 12 13 +Q1 N012 N010 8 0 PN +Q2 N010 N015 3 0 NA +Q3 N015 N009 N018 0 NP temp=27 +C1 N015 N009 27p Rser=225K +Q4 N009 N009 4 0 NP 10 temp=27 +R2 4 3 12K +R3 N018 3 10K +C2 1 N009 21p +Q5 N014 2 N017 0 FB temp=27 +R6 N017 4 106.8K +A1 5 3 3 3 3 3 N004 3 SCHMITT Vt=1.02 Vh=.19 trise=30n +G2 8 N009 N004 3 1.2µ +G1 8 N015 N004 3 1.2µ +R1 8 N010 600K +R8 N012 1 .1 +A2 N011 0 N015 N015 N015 N015 3 N015 VARISTOR +D3 0 N011 F +G3 0 N011 1 N012 20m +Q7 N009 N010 N012 0 P 1m +D1 8 1 X +C5 1 3 10p +C7 8 3 10p +C8 4 3 1p +G5 0 N011 N004 3 table(0 -3m 1 0) +C4 2 3 1p +G4 0 N011 8 1 table(2 2.5m 7 2.9m 10 .5m) +C6 8 N009 100p Rser=.45G Rpar=6G +C12 9 3 10p +C13 7 3 10p +C14 11 3 1p +C15 10 3 1p +C17 12 3 10p +S1 3 12 N005 3 PGDS +A5 N004 3 3 N006 3 3 N005 3 AND Trise=.1u +A6 2 3 3 3 3 N006 3 3 SCHMITT Vt=1.088 Vh=10m Trise=80u Tfall=.1u +R15 8 N014 5.7k +D6 2 8 ESD1 +D7 3 2 ESD2 +J15 5 3 N002 inpu +C18 5 3 1p +R5 N002 N008 12Meg +R16 N002 3 12.1Meg +Q13 8 N008 N007 0 NP +R17 N007 3 3.65Meg +Q6 N031 N029 7 0 PN +Q8 N029 N034 3 0 NA +Q9 N034 N028 N037 0 NP temp=27 +C9 N034 N028 27p Rser=225K +Q10 N028 N028 11 0 NP 10 temp=27 +R4 11 3 12K +R9 N037 3 10K +C10 9 N028 21p +Q11 N033 10 N036 0 FB temp=27 +R10 N036 11 106.8K +A3 6 3 3 3 3 3 N023 3 SCHMITT Vt=1.02 Vh=.19 trise=30n +G6 7 N028 N023 3 1.2µ +G7 7 N034 N023 3 1.2µ +R11 7 N029 600K +R12 N031 9 .3 +A4 N030 0 N034 N034 N034 N034 3 N034 VARISTOR +D2 0 N030 F +G8 0 N030 9 N031 20m +Q12 N028 N029 N031 0 P 1m +D4 7 9 X +G9 0 N030 N023 3 table(0 -3m 1 0) +G10 0 N030 7 9 table(2 2.5m 7 2.9m 10 .5m) +C16 7 N028 100p Rser=.45G Rpar=6G +S2 3 13 N024 3 PGDS +A7 N023 3 3 N025 3 3 N024 3 AND Trise=.1u +A8 10 3 3 3 3 N025 3 3 SCHMITT Vt=1.088 Vh=10m Trise=80u Tfall=.1u +R13 7 N033 5.7k +D5 10 7 ESD1 +D8 3 10 ESD2 +J14 6 3 N021 inpu +R18 N021 N027 12Meg +R20 N021 3 12.1Meg +Q14 7 N027 N026 0 NP +R21 N026 3 3.65Meg +C20 6 3 1p +C21 13 3 10p +.model X D(Ron=10 Vfwd=30) +.model PGDS SW(Ron=150 Roff=1G Vt=.5 Vh=-.1) +.model ESD1 D(Ron=2.7K Roff=5G Vfwd=3) +.model ESD2 D(Ron=1.2K Roff=5G Vfwd=1.5) +.model P PNP(BF=100) +.model F D(Ron=1m Roff=100K) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model NA NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n Is=1.722e-17) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model INPU NJF(Vto=-6.5 beta=10u Rd=300K) +.ends LT3030 diff --git a/spice/copy/sub/LT1764.lib b/spice/copy/sub/LT1764.lib new file mode 100755 index 0000000..1b94fb8 --- /dev/null +++ b/spice/copy/sub/LT1764.lib @@ -0,0 +1,194 @@ +* Copyright © Linear Technology Corp. 2016. All rights reserved. +* +.subckt LT1764-1.5 1 2 3 4 5 +Q1 N007 N005 2 0 PN temp=27 +Q2 N005 N010 3 0 NA temp=27 +Q3 N010 N004 N012 0 NP temp=27 +Q4 N004 N004 N013 0 NP 10 temp=27 +R2 N013 3 200 +R3 N012 3 175 +C2 4 N004 66p +Q5 4 N009 N011 0 FB temp=27 +R6 N011 N013 1.36K +R5 1 3 2Meg +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N004 N002 3 50µ +G1 2 N010 N002 3 50µ +R1 2 N005 50K +R8 N007 4 55m +A2 N006 0 N010 N010 N010 N010 3 N010 VARISTOR +D3 0 N006 F +G3 0 N006 4 N007 10m +Q7 N004 N005 N007 0 P .35m +D1 2 4 X +C5 4 3 10p +C7 2 3 10p +G4 0 N006 2 4 table(0 1.9m 8.5 2.7m 20 .5m) +G5 N006 0 N002 3 table(0 3m 1 0) +C1 5 3 1p +C4 2 N004 10n Rser=28Meg Rpar=50Meg +C6 2 N004 150p Rser=18Meg +R4 N009 3 3666 +R9 5 N009 875 +.model PN PNP(BF=25 Cje=250p Cjc=250p Tf=15n) +.model NA NPN(BF=450K Cje=5p Cjc=5p Re=2) +.model NP NPN(BF=150 Cje=5p Cjc=5p ) +.model FB NPN(Cje=10p Cjc=10p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1764-1.5 +* +.subckt LT1764-1.8 1 2 3 4 5 +Q1 N007 N005 2 0 PN temp=27 +Q2 N005 N010 3 0 NA temp=27 +Q3 N010 N004 N012 0 NP temp=27 +Q4 N004 N004 N013 0 NP 10 temp=27 +R2 N013 3 200 +R3 N012 3 175 +C2 4 N004 66p +Q5 4 N009 N011 0 FB temp=27 +R6 N011 N013 1.36K +R5 1 3 2Meg +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N004 N002 3 50µ +G1 2 N010 N002 3 50µ +R1 2 N005 50K +R8 N007 4 55m +A2 N006 0 N010 N010 N010 N010 3 N010 VARISTOR +D3 0 N006 F +G3 0 N006 4 N007 10m +Q7 N004 N005 N007 0 P .35m +D1 2 4 X +C5 4 3 10p +C7 2 3 10p +G4 0 N006 2 4 table(0 1.9m 8.5 2.7m 20 .5m) +G5 N006 0 N002 3 table(0 3m 1 0) +C1 5 3 1p +C4 2 N004 10n Rser=28Meg Rpar=50Meg +C6 2 N004 150p Rser=18Meg +R4 N009 3 3666 +R9 5 N009 1.8K +.model PN PNP(BF=25 Cje=250p Cjc=250p Tf=15n) +.model NA NPN(BF=450K Cje=5p Cjc=5p Re=2) +.model NP NPN(BF=150 Cje=5p Cjc=5p ) +.model FB NPN(Cje=10p Cjc=10p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1764-1.8 +* +.subckt LT1764-2.5 1 2 3 4 5 +Q1 N007 N005 2 0 PN temp=27 +Q2 N005 N010 3 0 NA temp=27 +Q3 N010 N004 N012 0 NP temp=27 +Q4 N004 N004 N013 0 NP 10 temp=27 +R2 N013 3 200 +R3 N012 3 175 +C2 4 N004 66p +Q5 4 N009 N011 0 FB temp=27 +R6 N011 N013 1.36K +R5 1 3 2Meg +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N004 N002 3 50µ +G1 2 N010 N002 3 50µ +R1 2 N005 50K +R8 N007 4 55m +A2 N006 0 N010 N010 N010 N010 3 N010 VARISTOR +D3 0 N006 F +G3 0 N006 4 N007 10m +Q7 N004 N005 N007 0 P .35m +D1 2 4 X +C5 4 3 10p +C7 2 3 10p +G4 0 N006 2 4 table(0 1.9m 8.5 2.7m 20 .5m) +G5 N006 0 N002 3 table(0 3m 1 0) +C1 5 3 1p +C4 2 N004 10n Rser=28Meg Rpar=50Meg +C6 2 N004 150p Rser=18Meg +R4 N009 3 3666 +R9 5 N009 3.89K +.model PN PNP(BF=25 Cje=250p Cjc=250p Tf=15n) +.model NA NPN(BF=450K Cje=5p Cjc=5p Re=2) +.model NP NPN(BF=150 Cje=5p Cjc=5p ) +.model FB NPN(Cje=10p Cjc=10p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1764-2.5 +* +.subckt LT1764-3.3 1 2 3 4 5 +Q1 N007 N005 2 0 PN temp=27 +Q2 N005 N010 3 0 NA temp=27 +Q3 N010 N004 N012 0 NP temp=27 +Q4 N004 N004 N013 0 NP 10 temp=27 +R2 N013 3 200 +R3 N012 3 175 +C2 4 N004 66p +Q5 4 N009 N011 0 FB temp=27 +R6 N011 N013 1.36K +R5 1 3 2Meg +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N004 N002 3 50µ +G1 2 N010 N002 3 50µ +R1 2 N005 50K +R8 N007 4 55m +A2 N006 0 N010 N010 N010 N010 3 N010 VARISTOR +D3 0 N006 F +G3 0 N006 4 N007 10m +Q7 N004 N005 N007 0 P .35m +D1 2 4 X +C5 4 3 10p +C7 2 3 10p +G4 0 N006 2 4 table(0 1.9m 8.5 2.7m 20 .5m) +G5 N006 0 N002 3 table(0 3m 1 0) +C1 5 3 1p +C4 2 N004 10n Rser=28Meg Rpar=50Meg +C6 2 N004 150p Rser=18Meg +R4 N009 3 3666 +R9 5 N009 6.3K +.model PN PNP(BF=25 Cje=250p Cjc=250p Tf=15n) +.model NA NPN(BF=450K Cje=5p Cjc=5p Re=2) +.model NP NPN(BF=150 Cje=5p Cjc=5p ) +.model FB NPN(Cje=10p Cjc=10p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1764-3.3 +* +.subckt LT1764 1 2 3 4 5 +Q1 N007 N005 2 0 PN temp=27 +Q2 N005 N009 3 0 NA +Q3 N009 N004 N011 0 NP temp=27 +Q4 N004 N004 N012 0 NP 10 temp=27 +R2 N012 3 200 +R3 N011 3 175 +C2 4 N004 66p +Q5 4 5 N010 0 FB temp=27 +R6 N010 N012 1.36K +R5 1 3 2Meg +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N004 N002 3 50µ +G1 2 N009 N002 3 50µ +R1 2 N005 50K +R8 N007 4 55m +A2 N006 0 N009 N009 N009 N009 3 N009 VARISTOR +D3 0 N006 F +G3 0 N006 4 N007 10m +Q7 N004 N005 N007 0 P .35m temp=27 +D1 2 4 X +C5 4 3 10p +C7 2 3 10p +G4 0 N006 2 4 table(0 1.9m 8.5 2.7m 20 .5m) +G5 N006 0 N002 3 table(0 3m 1 0) +C1 5 3 1p +C4 2 N004 10n Rser=28Meg Rpar=50Meg +C6 2 N004 150p Rser=18Meg +.model PN PNP(BF=25 Cje=250p Cjc=250p Tf=15n) +.model NA NPN(BF=450K Cje=5p Cjc=5p Re=2) +.model NP NPN(BF=150 Cje=5p Cjc=5p ) +.model FB NPN(Cje=10p Cjc=10p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT1764 diff --git a/spice/copy/sub/LT1765.sub b/spice/copy/sub/LT1765.sub new file mode 100755 index 0000000..0d0ef36 Binary files /dev/null and b/spice/copy/sub/LT1765.sub differ diff --git a/spice/copy/sub/LT1766.sub b/spice/copy/sub/LT1766.sub new file mode 100755 index 0000000..b6a0f17 Binary files /dev/null and b/spice/copy/sub/LT1766.sub differ diff --git a/spice/copy/sub/LT1767-x.x.sub b/spice/copy/sub/LT1767-x.x.sub new file mode 100755 index 0000000..6f5126a Binary files /dev/null and b/spice/copy/sub/LT1767-x.x.sub differ diff --git a/spice/copy/sub/LT1767.sub b/spice/copy/sub/LT1767.sub new file mode 100755 index 0000000..80b58ff Binary files /dev/null and b/spice/copy/sub/LT1767.sub differ diff --git a/spice/copy/sub/LT1776.sub b/spice/copy/sub/LT1776.sub new file mode 100755 index 0000000..bf1d4c4 Binary files /dev/null and b/spice/copy/sub/LT1776.sub differ diff --git a/spice/copy/sub/LT1777.sub b/spice/copy/sub/LT1777.sub new file mode 100755 index 0000000..81d3f72 Binary files /dev/null and b/spice/copy/sub/LT1777.sub differ diff --git a/spice/copy/sub/LT1786F.sub b/spice/copy/sub/LT1786F.sub new file mode 100755 index 0000000..74321a3 Binary files /dev/null and b/spice/copy/sub/LT1786F.sub differ diff --git a/spice/copy/sub/LT1790.lib b/spice/copy/sub/LT1790.lib new file mode 100755 index 0000000..e565029 --- /dev/null +++ b/spice/copy/sub/LT1790.lib @@ -0,0 +1,379 @@ +* Copyright © Linear Technology Corp. 2004m 2005. All rights reserved. +* +* Pinout: IN GROUND OUT +.SUBCKT LT1790-125 104 103 6 +CG1 118 0 0.5 +CILIM 107 0 10p +CREF 116 4 10p +DILIM1 107 105 DSW +DILIM2 106 107 DSW +DPWR1 111 109 DSW +DPWR2 110 103 DSW +DVLIM1 114 115 DSW +EVCC 7 0 104 0 1 +EVEE 4 0 103 0 1 +G1 0 118 116 102 111732 +GILIM1 0 105 121 6 1E4 +GILIM2 0 106 121 6 1E4 +GILIMO 118 0 107 0 0.01 +GITMPCO 104 103 113 0 4e-7 +GLINE 0 116 7 4 0.000125 +GLOAD 0 116 121 6 0.2 +GNOISE 0 116 108 0 1 +GOUT1 0 121 118 0 0.00125 +GPWR1 109 0 121 6 10 +GPWR2 110 0 121 6 10 +GTEMP 0 116 113 112 1.25e-5 +GVLIM2 0 114 104 111 480000000 +GVLIM3 114 0 7 121 1000 +GVLIMO 116 0 115 0 1000 +IDUM1 0 108 0 +IILIM1 0 105 10 +IILIM2 106 0 10 +ITEMP 0 113 1 +ITYP 104 103 3.5e-5 +IVLIM2 0 114 60 +IVOPT 0 116 1.25 +RFB1 102 6 0.01 +RFB2 102 103 100000000 +RG1 118 0 0.159155 +RILIM1 105 0 1 +RILIM2 106 0 1 +RILIM3 107 0 1 +RNOISE 108 0 241546000 +ROUT1 121 4 800 +RPWR1 109 7 1E3 +RPWR2 110 4 1E3 +RPWRS 111 104 1E-4 +RREF 116 4 1 +RSENSE 6 121 0.1 +RTEMP 113 0 1 TC1=1 +RVLIM2 114 0 1 +RVLIM3 115 0 1 +VDUM1 0 112 1 +.MODEL DSW D(IS=1E-10 RS=0 KF=0 XTI=0) +.ENDS LT1790-125 +* +* Pinout: IN GROUND OUT +.SUBCKT LT1790-2048 104 103 6 +CG1 118 0 0.5 +CILIM 107 0 10p +CREF 116 4 10p +DILIM1 107 105 DSW +DILIM2 106 107 DSW +DPWR1 111 109 DSW +DPWR2 110 103 DSW +DVLIM1 114 115 DSW +EVCC 7 0 104 0 1 +EVEE 4 0 103 0 1 +G1 0 118 116 102 111732 +GILIM1 0 105 121 6 1E4 +GILIM2 0 106 121 6 1E4 +GILIMO 118 0 107 0 0.01 +GITMPCO 104 103 113 0 4e-7 +GLINE 0 116 7 4 0.000125 +GLOAD 0 116 121 6 0.2 +GNOISE 0 116 108 0 1 +GOUT1 0 121 118 0 0.00125 +GPWR1 109 0 121 6 10 +GPWR2 110 0 121 6 10 +GTEMP 0 116 113 112 1.25e-5 +GVLIM2 0 114 104 111 480000000 +GVLIM3 114 0 7 121 1000 +GVLIMO 116 0 115 0 1000 +IDUM1 0 108 0 +IILIM1 0 105 10 +IILIM2 106 0 10 +ITEMP 0 113 1 +ITYP 104 103 3.5e-5 +IVLIM2 0 114 60 +IVOPT 0 116 2.048 +RFB1 102 6 0.01 +RFB2 102 103 100000000 +RG1 118 0 0.159155 +RILIM1 105 0 1 +RILIM2 106 0 1 +RILIM3 107 0 1 +RNOISE 108 0 241546000 +ROUT1 121 4 800 +RPWR1 109 7 1E3 +RPWR2 110 4 1E3 +RPWRS 111 104 1E-4 +RREF 116 4 1 +RSENSE 6 121 0.1 +RTEMP 113 0 1 TC1=1 +RVLIM2 114 0 1 +RVLIM3 115 0 1 +VDUM1 0 112 1 +.MODEL DSW D(IS=1E-10 RS=0 KF=0 XTI=0) +.ENDS LT1790-2048 +* +* Pinout: IN GROUND OUT +.SUBCKT LT1790-25 104 103 6 +CG1 118 0 0.5 +CILIM 107 0 10p +CREF 116 4 10p +DILIM1 107 105 DSW +DILIM2 106 107 DSW +DPWR1 111 109 DSW +DPWR2 110 103 DSW +DVLIM1 114 115 DSW +EVCC 7 0 104 0 1 +EVEE 4 0 103 0 1 +G1 0 118 116 102 111732 +GILIM1 0 105 121 6 1E4 +GILIM2 0 106 121 6 1E4 +GILIMO 118 0 107 0 0.01 +GITMPCO 104 103 113 0 4e-7 +GLINE 0 116 7 4 0.000125 +GLOAD 0 116 121 6 0.2 +GNOISE 0 116 108 0 1 +GOUT1 0 121 118 0 0.00125 +GPWR1 109 0 121 6 10 +GPWR2 110 0 121 6 10 +GTEMP 0 116 113 112 1.25e-5 +GVLIM2 0 114 104 111 480000000 +GVLIM3 114 0 7 121 1000 +GVLIMO 116 0 115 0 1000 +IDUM1 0 108 0 +IILIM1 0 105 10 +IILIM2 106 0 10 +ITEMP 0 113 1 +ITYP 104 103 3.5e-5 +IVLIM2 0 114 60 +IVOPT 0 116 2.5 +RFB1 102 6 0.01 +RFB2 102 103 100000000 +RG1 118 0 0.159155 +RILIM1 105 0 1 +RILIM2 106 0 1 +RILIM3 107 0 1 +RNOISE 108 0 241546000 +ROUT1 121 4 800 +RPWR1 109 7 1E3 +RPWR2 110 4 1E3 +RPWRS 111 104 1E-4 +RREF 116 4 1 +RSENSE 6 121 0.1 +RTEMP 113 0 1 TC1=1 +RVLIM2 114 0 1 +RVLIM3 115 0 1 +VDUM1 0 112 1 +.MODEL DSW D(IS=1E-10 RS=0 KF=0 XTI=0) +.ENDS LT1790-25 +* +* Pinout: IN GROUND OUT +.SUBCKT LT1790-3 104 103 6 +CG1 118 0 0.5 +CILIM 107 0 10p +CREF 116 4 10p +DILIM1 107 105 DSW +DILIM2 106 107 DSW +DPWR1 111 109 DSW +DPWR2 110 103 DSW +DVLIM1 114 115 DSW +EVCC 7 0 104 0 1 +EVEE 4 0 103 0 1 +G1 0 118 116 102 111732 +GILIM1 0 105 121 6 1E4 +GILIM2 0 106 121 6 1E4 +GILIMO 118 0 107 0 0.01 +GITMPCO 104 103 113 0 4e-7 +GLINE 0 116 7 4 0.000125 +GLOAD 0 116 121 6 0.2 +GNOISE 0 116 108 0 1 +GOUT1 0 121 118 0 0.00125 +GPWR1 109 0 121 6 10 +GPWR2 110 0 121 6 10 +GTEMP 0 116 113 112 1.25e-5 +GVLIM2 0 114 104 111 480000000 +GVLIM3 114 0 7 121 1000 +GVLIMO 116 0 115 0 1000 +IDUM1 0 108 0 +IILIM1 0 105 10 +IILIM2 106 0 10 +ITEMP 0 113 1 +ITYP 104 103 3.5e-5 +IVLIM2 0 114 60 +IVOPT 0 116 3 +RFB1 102 6 0.01 +RFB2 102 103 100000000 +RG1 118 0 0.159155 +RILIM1 105 0 1 +RILIM2 106 0 1 +RILIM3 107 0 1 +RNOISE 108 0 241546000 +ROUT1 121 4 800 +RPWR1 109 7 1E3 +RPWR2 110 4 1E3 +RPWRS 111 104 1E-4 +RREF 116 4 1 +RSENSE 6 121 0.1 +RTEMP 113 0 1 TC1=1 +RVLIM2 114 0 1 +RVLIM3 115 0 1 +VDUM1 0 112 1 +.MODEL DSW D(IS=1E-10 RS=0 KF=0 XTI=0) +.ENDS LT1790-3 +* +* Pinout: IN GROUND OUT +.SUBCKT LT1790-33 104 103 6 +CG1 118 0 0.5 +CILIM 107 0 10p +CREF 116 4 10p +DILIM1 107 105 DSW +DILIM2 106 107 DSW +DPWR1 111 109 DSW +DPWR2 110 103 DSW +DVLIM1 114 115 DSW +EVCC 7 0 104 0 1 +EVEE 4 0 103 0 1 +G1 0 118 116 102 111732 +GILIM1 0 105 121 6 1E4 +GILIM2 0 106 121 6 1E4 +GILIMO 118 0 107 0 0.01 +GITMPCO 104 103 113 0 4e-7 +GLINE 0 116 7 4 0.000125 +GLOAD 0 116 121 6 0.2 +GNOISE 0 116 108 0 1 +GOUT1 0 121 118 0 0.00125 +GPWR1 109 0 121 6 10 +GPWR2 110 0 121 6 10 +GTEMP 0 116 113 112 1.25e-5 +GVLIM2 0 114 104 111 480000000 +GVLIM3 114 0 7 121 1000 +GVLIMO 116 0 115 0 1000 +IDUM1 0 108 0 +IILIM1 0 105 10 +IILIM2 106 0 10 +ITEMP 0 113 1 +ITYP 104 103 3.5e-5 +IVLIM2 0 114 60 +IVOPT 0 116 3.3 +RFB1 102 6 0.01 +RFB2 102 103 100000000 +RG1 118 0 0.159155 +RILIM1 105 0 1 +RILIM2 106 0 1 +RILIM3 107 0 1 +RNOISE 108 0 241546000 +ROUT1 121 4 800 +RPWR1 109 7 1E3 +RPWR2 110 4 1E3 +RPWRS 111 104 1E-4 +RREF 116 4 1 +RSENSE 6 121 0.1 +RTEMP 113 0 1 TC1=1 +RVLIM2 114 0 1 +RVLIM3 115 0 1 +VDUM1 0 112 1 +.MODEL DSW D(IS=1E-10 RS=0 KF=0 XTI=0) +.ENDS LT1790-33 +* +* Pinout: IN GROUND OUT +.SUBCKT LT1790-4096 104 103 6 +CG1 118 0 0.5 +CILIM 107 0 10p +CREF 116 4 10p +DILIM1 107 105 DSW +DILIM2 106 107 DSW +DPWR1 111 109 DSW +DPWR2 110 103 DSW +DVLIM1 114 115 DSW +EVCC 7 0 104 0 1 +EVEE 4 0 103 0 1 +G1 0 118 116 102 111732 +GILIM1 0 105 121 6 1E4 +GILIM2 0 106 121 6 1E4 +GILIMO 118 0 107 0 0.01 +GITMPCO 104 103 113 0 4e-7 +GLINE 0 116 7 4 0.000125 +GLOAD 0 116 121 6 0.2 +GNOISE 0 116 108 0 1 +GOUT1 0 121 118 0 0.00125 +GPWR1 109 0 121 6 10 +GPWR2 110 0 121 6 10 +GTEMP 0 116 113 112 1.25e-5 +GVLIM2 0 114 104 111 480000000 +GVLIM3 114 0 7 121 1000 +GVLIMO 116 0 115 0 1000 +IDUM1 0 108 0 +IILIM1 0 105 10 +IILIM2 106 0 10 +ITEMP 0 113 1 +ITYP 104 103 3.5e-5 +IVLIM2 0 114 60 +IVOPT 0 116 4.096 +RFB1 102 6 0.01 +RFB2 102 103 100000000 +RG1 118 0 0.159155 +RILIM1 105 0 1 +RILIM2 106 0 1 +RILIM3 107 0 1 +RNOISE 108 0 241546000 +ROUT1 121 4 800 +RPWR1 109 7 1E3 +RPWR2 110 4 1E3 +RPWRS 111 104 1E-4 +RREF 116 4 1 +RSENSE 6 121 0.1 +RTEMP 113 0 1 TC1=1 +RVLIM2 114 0 1 +RVLIM3 115 0 1 +VDUM1 0 112 1 +.MODEL DSW D(IS=1E-10 RS=0 KF=0 XTI=0) +.ENDS LT1790-4096 +* +* Pinout: IN GROUND OUT +.SUBCKT LT1790-5 104 103 6 +CG1 118 0 0.5 +CILIM 107 0 10p +CREF 116 4 10p +DILIM1 107 105 DSW +DILIM2 106 107 DSW +DPWR1 111 109 DSW +DPWR2 110 103 DSW +DVLIM1 114 115 DSW +EVCC 7 0 104 0 1 +EVEE 4 0 103 0 1 +G1 0 118 116 102 111732 +GILIM1 0 105 121 6 1E4 +GILIM2 0 106 121 6 1E4 +GILIMO 118 0 107 0 0.01 +GITMPCO 104 103 113 0 4e-7 +GLINE 0 116 7 4 0.000125 +GLOAD 0 116 121 6 0.2 +GNOISE 0 116 108 0 1 +GOUT1 0 121 118 0 0.00125 +GPWR1 109 0 121 6 10 +GPWR2 110 0 121 6 10 +GTEMP 0 116 113 112 1.25e-5 +GVLIM2 0 114 104 111 480000000 +GVLIM3 114 0 7 121 1000 +GVLIMO 116 0 115 0 1000 +IDUM1 0 108 0 +IILIM1 0 105 10 +IILIM2 106 0 10 +ITEMP 0 113 1 +ITYP 104 103 3.5e-5 +IVLIM2 0 114 60 +IVOPT 0 116 5 +RFB1 102 6 0.01 +RFB2 102 103 100000000 +RG1 118 0 0.159155 +RILIM1 105 0 1 +RILIM2 106 0 1 +RILIM3 107 0 1 +RNOISE 108 0 241546000 +ROUT1 121 4 800 +RPWR1 109 7 1E3 +RPWR2 110 4 1E3 +RPWRS 111 104 1E-4 +RREF 116 4 1 +RSENSE 6 121 0.1 +RTEMP 113 0 1 TC1=1 +RVLIM2 114 0 1 +RVLIM3 115 0 1 +VDUM1 0 112 1 +.MODEL DSW D(IS=1E-10 RS=0 KF=0 XTI=0) +.ENDS LT1790-5 diff --git a/spice/copy/sub/LT1910.sub b/spice/copy/sub/LT1910.sub new file mode 100755 index 0000000..83fe416 Binary files /dev/null and b/spice/copy/sub/LT1910.sub differ diff --git a/spice/copy/sub/LT1912.sub b/spice/copy/sub/LT1912.sub new file mode 100755 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a/spice/copy/sub/LT1956.sub b/spice/copy/sub/LT1956.sub new file mode 100755 index 0000000..be1f1c8 Binary files /dev/null and b/spice/copy/sub/LT1956.sub differ diff --git a/spice/copy/sub/LT1959.sub b/spice/copy/sub/LT1959.sub new file mode 100755 index 0000000..926e342 Binary files /dev/null and b/spice/copy/sub/LT1959.sub differ diff --git a/spice/copy/sub/LT1961.sub b/spice/copy/sub/LT1961.sub new file mode 100755 index 0000000..e2910ec Binary files /dev/null and b/spice/copy/sub/LT1961.sub differ diff --git a/spice/copy/sub/LT1962.lib b/spice/copy/sub/LT1962.lib new file mode 100755 index 0000000..3afd4d8 --- /dev/null +++ b/spice/copy/sub/LT1962.lib @@ -0,0 +1,293 @@ +* Copyright © Linear Technology Corp. 2011. All rights reserved. +* +.subckt LT1962-1.5 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN +Q2 N005 N003 4 0 NA +Q3 N003 N004 N011 0 NP temp=27 +C1 N003 N004 27p Rser=225K +Q4 N004 N004 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N011 4 10K +C2 1 N004 25p +Q5 1 N009 N010 0 FB temp=27 +R6 N010 3 107K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m tau=10u +G2 8 N004 N002 4 1.2µ +G1 8 N003 N002 4 1.2µ +R1 8 N005 600K +R8 N007 1 .2 +A2 N006 0 N003 N003 N003 N003 4 N003 VARISTOR +D3 0 N006 F +G3 0 N006 1 N007 20m +Q7 N004 N005 N007 0 P 1m +D1 8 1 X +C5 2 4 1p +C6 1 4 10p +C7 8 4 10p +G4 0 N006 8 0 table(1.3 1m 2.4 3m 10 4m) +C4 8 N003 5p Rser=.6G +C8 3 4 1p +R9 2 N009 57K +R10 N009 4 244K +G5 N006 0 N002 4 table(0 4m 1 0) +C9 8 N004 300p Rser=.37G Rpar=6G +D2 5 4 S +.model P PNP(BF=100) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model NA NPN(BF=1Meg Cje=2p Cjc=2p Re=20) +.model PN PNP(BF=30 Cje=300p Cjc=300p Tf=10n) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model X D(Ron=10 Vfwd=30 epsilon=.5) +.model S D(Ron=3Meg Roff=100Meg Vfwd=.9 epsilon=.2 Ilimit=1u) +.ends LT1962-1.5 +* +.subckt LT1962-1.8 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN +Q2 N005 N003 4 0 NA +Q3 N003 N004 N011 0 NP temp=27 +C1 N003 N004 27p Rser=225K +Q4 N004 N004 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N011 4 10K +C2 1 N004 25p +Q5 1 N009 N010 0 FB temp=27 +R6 N010 3 107K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m tau=10u +G2 8 N004 N002 4 1.2µ +G1 8 N003 N002 4 1.2µ +R1 8 N005 600K +R8 N007 1 .2 +A2 N006 0 N003 N003 N003 N003 4 N003 VARISTOR +D3 0 N006 F +G3 0 N006 1 N007 20m +Q7 N004 N005 N007 0 P 1m +D1 8 1 X +C5 2 4 1p +C6 1 4 10p +C7 8 4 10p +G4 0 N006 8 0 table(1.3 1m 2.4 3m 10 4m) +C4 8 N003 5p Rser=.6G +C8 3 4 1p +R9 2 N009 117K +R10 N009 4 244K +G5 N006 0 N002 4 table(0 4m 1 0) +C9 8 N004 300p Rser=.37G Rpar=6G +D2 5 4 S +.model P PNP(BF=100) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model NA NPN(BF=1Meg Cje=2p Cjc=2p Re=20) +.model PN PNP(BF=30 Cje=300p Cjc=300p Tf=10n) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model X D(Ron=10 Vfwd=30 epsilon=.5) +.model S D(Ron=3Meg Roff=100Meg Vfwd=.9 epsilon=.2 Ilimit=1u) +.ends LT1962-1.8 +* +.subckt LT1962-2.5 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN +Q2 N005 N003 4 0 NA +Q3 N003 N004 N011 0 NP temp=27 +C1 N003 N004 27p Rser=225K +Q4 N004 N004 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N011 4 10K +C2 1 N004 25p +Q5 1 N009 N010 0 FB temp=27 +R6 N010 3 107K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m tau=10u +G2 8 N004 N002 4 1.2µ +G1 8 N003 N002 4 1.2µ +R1 8 N005 600K +R8 N007 1 .2 +A2 N006 0 N003 N003 N003 N003 4 N003 VARISTOR +D3 0 N006 F +G3 0 N006 1 N007 20m +Q7 N004 N005 N007 0 P 1m +D1 8 1 X +C5 2 4 1p +C6 1 4 10p +C7 8 4 10p +G4 0 N006 8 0 table(1.3 1m 2.4 3m 10 4m) +C4 8 N003 5p Rser=.6G +C8 3 4 1p +R9 2 N009 256K +R10 N009 4 244K +G5 N006 0 N002 4 table(0 4m 1 0) +C9 8 N004 300p Rser=.37G Rpar=6G +D2 5 4 S +.model P PNP(BF=100) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model NA NPN(BF=1Meg Cje=2p Cjc=2p Re=20) +.model PN PNP(BF=30 Cje=300p Cjc=300p Tf=10n) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model X D(Ron=10 Vfwd=30 epsilon=.5) +.model S D(Ron=3Meg Roff=100Meg Vfwd=.9 epsilon=.2 Ilimit=1u) +.ends LT1962-2.5 +* +.subckt LT1962-3.3 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN +Q2 N005 N003 4 0 NA +Q3 N003 N004 N011 0 NP temp=27 +C1 N003 N004 27p Rser=225K +Q4 N004 N004 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N011 4 10K +C2 1 N004 25p +Q5 1 N009 N010 0 FB temp=27 +R6 N010 3 107K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m tau=10u +G2 8 N004 N002 4 1.2µ +G1 8 N003 N002 4 1.2µ +R1 8 N005 600K +R8 N007 1 .2 +A2 N006 0 N003 N003 N003 N003 4 N003 VARISTOR +D3 0 N006 F +G3 0 N006 1 N007 20m +Q7 N004 N005 N007 0 P 1m +D1 8 1 X +C5 2 4 1p +C6 1 4 10p +C7 8 4 10p +G4 0 N006 8 0 table(1.3 1m 2.4 3m 10 4m) +C4 8 N003 5p Rser=.6G +C8 3 4 1p +R9 2 N009 415K +R10 N009 4 244K +G5 N006 0 N002 4 table(0 4m 1 0) +C9 8 N004 300p Rser=.37G Rpar=6G +D2 5 4 S +.model P PNP(BF=100) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model NA NPN(BF=1Meg Cje=2p Cjc=2p Re=20) +.model PN PNP(BF=30 Cje=300p Cjc=300p Tf=10n) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model X D(Ron=10 Vfwd=30 epsilon=.5) +.model S D(Ron=3Meg Roff=100Meg Vfwd=.9 epsilon=.2 Ilimit=1u) +.ends LT1962-3.3 +* +.subckt LT1962-3 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN +Q2 N005 N003 4 0 NA +Q3 N003 N004 N011 0 NP temp=27 +C1 N003 N004 27p Rser=225K +Q4 N004 N004 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N011 4 10K +C2 1 N004 25p +Q5 1 N009 N010 0 FB temp=27 +R6 N010 3 107K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m tau=10u +G2 8 N004 N002 4 1.2µ +G1 8 N003 N002 4 1.2µ +R1 8 N005 600K +R8 N007 1 .2 +A2 N006 0 N003 N003 N003 N003 4 N003 VARISTOR +D3 0 N006 F +G3 0 N006 1 N007 20m +Q7 N004 N005 N007 0 P 1m +D1 8 1 X +C5 2 4 1p +C6 1 4 10p +C7 8 4 10p +G4 0 N006 8 0 table(1.3 1m 2.4 3m 10 4m) +C4 8 N003 5p Rser=.6G +C8 3 4 1p +R9 2 N009 356K +R10 N009 4 244K +G5 N006 0 N002 4 table(0 4m 1 0) +C9 8 N004 300p Rser=.37G Rpar=6G +D2 5 4 S +.model P PNP(BF=100) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model NA NPN(BF=1Meg Cje=2p Cjc=2p Re=20) +.model PN PNP(BF=30 Cje=300p Cjc=300p Tf=10n) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model X D(Ron=10 Vfwd=30 epsilon=.5) +.model S D(Ron=3Meg Roff=100Meg Vfwd=.9 epsilon=.2 Ilimit=1u) +.ends LT1962-3 +* +.subckt LT1962-5 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN +Q2 N005 N003 4 0 NA +Q3 N003 N004 N011 0 NP temp=27 +C1 N003 N004 27p Rser=225K +Q4 N004 N004 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N011 4 10K +C2 1 N004 25p +Q5 1 N009 N010 0 FB temp=27 +R6 N010 3 107K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m tau=10u +G2 8 N004 N002 4 1.2µ +G1 8 N003 N002 4 1.2µ +R1 8 N005 600K +R8 N007 1 .2 +A2 N006 0 N003 N003 N003 N003 4 N003 VARISTOR +D3 0 N006 F +G3 0 N006 1 N007 20m +Q7 N004 N005 N007 0 P 1m +D1 8 1 X +C5 2 4 1p +C6 1 4 10p +C7 8 4 10p +G4 0 N006 8 0 table(1.3 1m 2.4 3m 10 4m) +C4 8 N003 5p Rser=.6G +C8 3 4 1p +R9 2 N009 755K +R10 N009 4 244K +G5 N006 0 N002 4 table(0 4m 1 0) +C9 8 N004 300p Rser=.37G Rpar=6G +D2 5 4 S +.model P PNP(BF=100) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model NA NPN(BF=1Meg Cje=2p Cjc=2p Re=20) +.model PN PNP(BF=30 Cje=300p Cjc=300p Tf=10n) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model X D(Ron=10 Vfwd=30 epsilon=.5) +.model S D(Ron=3Meg Roff=100Meg Vfwd=.9 epsilon=.2 Ilimit=1u) +.ends LT1962-5 +* +.subckt LT1962 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN +Q2 N005 N003 4 0 NA +Q3 N003 N004 N010 0 NP temp=27 +C1 N003 N004 27p Rser=225K +Q4 N004 N004 3 0 NP 10 temp=27 +R2 3 4 12K +R3 N010 4 10K +C2 1 N004 25p +Q5 1 2 N009 0 FB temp=27 +R6 N009 3 107K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m tau=10u +G2 8 N004 N002 4 1.2µ +G1 8 N003 N002 4 1.2µ +R1 8 N005 600K +R8 N007 1 .2 +A2 N006 0 N003 N003 N003 N003 4 N003 VARISTOR +D3 0 N006 F +G3 0 N006 1 N007 20m +Q7 N004 N005 N007 0 P 1m +D1 8 1 X +C5 2 4 1p +C6 1 4 10p +C7 8 4 10p +G4 0 N006 8 0 table(1.3 1m 2.4 3m 10 4m) +C4 8 N003 5p Rser=.6G +C8 3 4 1p +G5 N006 0 N002 4 table(0 4m 1 0) +C9 8 N004 300p Rser=.37G Rpar=6G +D2 5 4 S +.model P PNP(BF=100) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model NA NPN(BF=1Meg Cje=2p Cjc=2p Re=20) +.model PN PNP(BF=30 Cje=300p Cjc=300p Tf=10n) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model X D(Ron=10 Vfwd=30 epsilon=.5) +.model S D(Ron=3Meg Roff=100Meg Vfwd=.9 epsilon=.2 Ilimit=1u) +.ends LT1962 diff --git a/spice/copy/sub/LT1963.lib b/spice/copy/sub/LT1963.lib new file mode 100755 index 0000000..9962df2 --- /dev/null +++ b/spice/copy/sub/LT1963.lib @@ -0,0 +1,208 @@ +* Copyright © Linear Technology Corp. 2016. All rights reserved. +* +.subckt LT1963-1.5 1 2 3 4 5 +Q1 N008 N006 2 0 PN temp=27 +Q2 N006 N004 3 0 NA temp=27 +Q3 N004 N005 N012 0 NP temp=27 +C1 N004 N005 11p Rser=10K +Q4 N005 N005 N013 0 NP 10 temp=27 +R2 N013 3 200 +R3 N012 3 175 +C2 4 N005 65p +Q5 4 N010 N011 0 FB temp=27 +R6 N011 N013 1.361K +R5 1 3 10Meg +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N005 N002 3 50µ +G1 2 N004 N002 3 50µ +R1 2 N006 50K +R8 N008 4 .1 +A2 N007 0 N004 N004 N004 N004 3 N004 VARISTOR +D3 0 N007 F +G3 0 N007 4 N008 10m +G4 0 N007 2 4 table(9 4.5m 18 1.5m) +Q7 N005 N006 N008 0 P 1m temp=27 +C4 2 N004 300p Rser=20Meg +D1 2 4 X +C5 5 3 1p +C6 4 3 10p +C7 2 3 10p +G5 N007 0 N002 3 table(0 4.5m 1 0) +C8 2 N005 4n Rser=12Meg Rpar=70Meg +D2 1 3 3uA +R10 N010 3 3666 +R11 5 N010 882.5 +.model PN PNP(BF=25 Cje=200p Cjc=200p Tf=20n) +.model NA NPN(BF=170K Cje=5p Cjc=5p Re=5) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model FB NPN(Cje=10p Cjc=10p BF=100) +.model F D(Ron=1m Roff=1K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=29.5 epsilon=1) +.model 3uA D(Ron=250K Ilimit=3u) +.ends LT1963-1.5 +* +.subckt LT1963-1.8 1 2 3 4 5 +Q1 N008 N006 2 0 PN temp=27 +Q2 N006 N004 3 0 NA temp=27 +Q3 N004 N005 N012 0 NP temp=27 +C1 N004 N005 11p Rser=10K +Q4 N005 N005 N013 0 NP 10 temp=27 +R2 N013 3 200 +R3 N012 3 175 +C2 4 N005 65p +Q5 4 N010 N011 0 FB temp=27 +R6 N011 N013 1.361K +R5 1 3 10Meg +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N005 N002 3 50µ +G1 2 N004 N002 3 50µ +R1 2 N006 50K +R8 N008 4 .1 +A2 N007 0 N004 N004 N004 N004 3 N004 VARISTOR +D3 0 N007 F +G3 0 N007 4 N008 10m +G4 0 N007 2 4 table(9 4.5m 18 1.5m) +Q7 N005 N006 N008 0 P 1m temp=27 +C4 2 N004 300p Rser=20Meg +D1 2 4 X +C5 5 3 1p +C6 4 3 10p +C7 2 3 10p +G5 N007 0 N002 3 table(0 4.5m 1 0) +C8 2 N005 4n Rser=12Meg Rpar=70Meg +D2 1 3 3uA +R10 N010 3 3666 +R11 5 N010 1.785K +.model PN PNP(BF=25 Cje=200p Cjc=200p Tf=20n) +.model NA NPN(BF=170K Cje=5p Cjc=5p Re=5) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model FB NPN(Cje=10p Cjc=10p BF=100) +.model F D(Ron=1m Roff=1K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=29.5 epsilon=1) +.model 3uA D(Ron=250K Ilimit=3u) +.ends LT1963-1.8 +* +.subckt LT1963-2.5 1 2 3 4 5 +Q1 N008 N006 2 0 PN temp=27 +Q2 N006 N004 3 0 NA temp=27 +Q3 N004 N005 N012 0 NP temp=27 +C1 N004 N005 11p Rser=10K +Q4 N005 N005 N013 0 NP 10 temp=27 +R2 N013 3 200 +R3 N012 3 175 +C2 4 N005 65p +Q5 4 N010 N011 0 FB temp=27 +R6 N011 N013 1.361K +R5 1 3 10Meg +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N005 N002 3 50µ +G1 2 N004 N002 3 50µ +R1 2 N006 50K +R8 N008 4 .1 +A2 N007 0 N004 N004 N004 N004 3 N004 VARISTOR +D3 0 N007 F +G3 0 N007 4 N008 10m +G4 0 N007 2 4 table(9 4.5m 18 1.5m) +Q7 N005 N006 N008 0 P 1m temp=27 +C4 2 N004 300p Rser=20Meg +D1 2 4 X +C5 5 3 1p +C6 4 3 10p +C7 2 3 10p +G5 N007 0 N002 3 table(0 4.5m 1 0) +C8 2 N005 4n Rser=12Meg Rpar=70Meg +D2 1 3 3uA +R10 N010 3 3666 +R11 5 N010 3.9K +.model PN PNP(BF=25 Cje=200p Cjc=200p Tf=20n) +.model NA NPN(BF=170K Cje=5p Cjc=5p Re=5) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model FB NPN(Cje=10p Cjc=10p BF=100) +.model F D(Ron=1m Roff=1K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=29.5 epsilon=1) +.model 3uA D(Ron=250K Ilimit=3u) +.ends LT1963-2.5 +* +.subckt LT1963-3.3 1 2 3 4 5 +Q1 N008 N006 2 0 PN +Q2 N006 N004 3 0 NA temp=27 +Q3 N004 N005 N012 0 NP temp=27 +C1 N004 N005 11p Rser=10K +Q4 N005 N005 N013 0 NP 10 temp=27 +R2 N013 3 200 +R3 N012 3 175 +C2 4 N005 65p +Q5 4 N010 N011 0 FB temp=27 +R6 N011 N013 1.361K +R5 1 3 10Meg +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N005 N002 3 50µ +G1 2 N004 N002 3 50µ +R1 2 N006 50K +R8 N008 4 .1 +A2 N007 0 N004 N004 N004 N004 3 N004 VARISTOR +D3 0 N007 F +G3 0 N007 4 N008 10m +G4 0 N007 2 4 table(9 4.5m 18 1.5m) +Q7 N005 N006 N008 0 P 1m temp=27 +C4 2 N004 300p Rser=20Meg +D1 2 4 X +C5 5 3 1p +C6 4 3 10p +C7 2 3 10p +G5 N007 0 N002 3 table(0 4.5m 1 0) +C8 2 N005 4n Rser=12Meg Rpar=70Meg +D2 1 3 3uA +R10 N010 3 3666 +R11 5 N010 6.31K +.model PN PNP(BF=25 Cje=200p Cjc=200p Tf=20n) +.model NA NPN(BF=170K Cje=5p Cjc=5p Re=5) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model FB NPN(Cje=10p Cjc=10p BF=100) +.model F D(Ron=1m Roff=1K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=29.5 epsilon=1) +.model 3uA D(Ron=250K Ilimit=3u) +.ends LT1963-3.3 +* +.subckt LT1963 1 2 3 4 5 +Q1 N008 N006 2 0 PN temp=27 +Q2 N006 N004 3 0 NA temp=27 +Q3 N004 N005 N011 0 NP temp=27 +C1 N004 N005 11p Rser=10K +Q4 N005 N005 N012 0 NP 10 temp=27 +R2 N012 3 200 +R3 N011 3 175 +C2 4 N005 65p +Q5 4 5 N010 0 FB temp=27 +R6 N010 N012 1.361K +R5 1 3 10Meg +I1 1 3 3µ load +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=15u +G2 2 N005 N002 3 50µ +G1 2 N004 N002 3 50µ +R1 2 N006 50K +R8 N008 4 .1 +A2 N007 0 N004 N004 N004 N004 3 N004 VARISTOR +D3 0 N007 F +G3 0 N007 4 N008 10m +G4 0 N007 2 4 table(9 4.5m 18 1.5m) +Q7 N005 N006 N008 0 P 1m temp=27 +C4 2 N004 300p Rser=20Meg +D1 2 4 X +C5 5 3 1p +C6 4 3 10p +C7 2 3 10p +G5 N007 0 N002 3 table(0 4.5m 1 0) +C8 2 N005 4n Rser=12Meg Rpar=70Meg +.model PN PNP(BF=25 Cje=200p Cjc=200p Tf=20n) +.model NA NPN(BF=170K Cje=5p Cjc=5p Re=5) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model FB NPN(Cje=10p Cjc=10p BF=100) +.model F D(Ron=1m Roff=1K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=29.5 epsilon=1) +.ends LT1963 diff --git a/spice/copy/sub/LT1964.lib b/spice/copy/sub/LT1964.lib new file mode 100755 index 0000000..19026cd --- /dev/null +++ b/spice/copy/sub/LT1964.lib @@ -0,0 +1,126 @@ +* Copyright © Linear Technology Corp. 2011. All rights reserved. +* +.subckt LT1964-5 1 2 3 4 5 +Q2 N009 N007 N013 0 NA +Q3 N007 N010 N015 0 N temp=27 +C1 N007 N010 18p Rser=40K +Q4 N010 N010 N016 0 N 10 temp=27 +R2 N016 2 12K +R3 N015 2 10K +Q1 N016 N004 N008 0 P temp=27 +R6 1 N008 121.5K +R8 N013 2 1K +Q5 N009 N009 N006 0 P +Q6 N014 N009 1 0 P 6 +R1 N014 2 450K +R9 1 N006 4K +Q7 N012 N014 2 0 NP +R7 5 N012 .7 +Q8 2 N012 N007 0 P 4.5 +G1 1 N007 3 1 80µ +R5 1 3 5K +A1 1 4 0 0 0 0 N002 0 SCHMITT Vt=1.9 Vh=10m Rhigh=1 Rlow=1K +A2 4 1 0 0 0 0 N002 0 SCHMITT Vt=1.4 Vh=10m Rhigh=1 Rlow=1K +G2 1 N007 N002 0 1.2µ +G3 1 N010 N002 0 1.2µ +C4 0 N002 50µ +R4 4 1 5Meg +A3 0 N001 N007 N007 N007 N007 2 N007 VARISTOR +G4 0 N001 N012 5 10m +G6 0 N001 5 2 table( 7 4.3m 10 2.5m 20 1.5m) +C6 1 5 10p +C7 1 2 10p +R13 N004 1 240K +R14 5 N004 744K +D1 0 N001 X +C2 1 N010 500p Rser=.21G Rpar=6G +S1 0 N001 0 N002 SS +.model N NPN(Cje=5p Cjc=5p BF=150) +.model P PNP(Cje=5p Cjc=5p BF=150) +.model NP NPN(Cje=50p Cjc=50p BF=50) +.model NA NPN(Cje=1p Cjc=1p BF=8K) +.model X D(Ron=1 Roff=1K) +.model SS SW(Ron=1 Roff=1G Vt=-.95 Vh=-25m) +.ends LT1964-5 +* +.subckt LT1964-BYP 1 2 3 4 5 +Q2 N007 N005 N011 0 NA +Q3 N005 N008 N013 0 N temp=27 +C1 N005 N008 18p Rser=40K +Q4 N008 N008 N014 0 N 10 temp=27 +R2 N014 2 12K +R3 N013 2 10K +Q1 N014 4 N006 0 P temp=27 +R6 1 N006 121.5K +R8 N011 2 1K +Q5 N007 N007 N004 0 P +Q6 N012 N007 1 0 P 6 +R1 N012 2 450K +R9 1 N004 4K +Q7 N010 N012 2 0 NP +R7 5 N010 .7 +Q8 2 N010 N005 0 P 4.5 +G1 1 N005 3 1 80µ +R5 1 3 5K +A1 1 2 0 0 0 0 N002 0 SCHMITT Vt=1.9 Vh=10m Rhigh=1 Rlow=1K +A2 2 1 0 0 0 0 N002 0 SCHMITT Vt=1.4 Vh=10m Rhigh=1 Rlow=1K +G2 1 N005 N002 0 1.2µ +G3 1 N008 N002 0 1.2µ +C4 0 N002 .1µ +R4 2 1 5Meg +A3 0 N009 N005 N005 N005 N005 2 N005 VARISTOR +G4 0 N009 N010 5 10m +G6 0 N009 5 2 table( 7 4.3m 10 2.5m 20 1.5m) +C5 1 4 1p +C6 1 5 10p +C7 1 2 10p +D1 0 N009 X +C2 1 N008 500p Rser=.21G Rpar=6G +S1 1 N008 0 N002 SS +.model N NPN(Cje=5p Cjc=5p BF=150) +.model P PNP(Cje=5p Cjc=5p BF=150) +.model NP NPN(Cje=50p Cjc=50p BF=50) +.model NA NPN(Cje=1p Cjc=1p BF=8K) +.model X D(Ron=1 Roff=1K) +.model SS SW(Ron=10K Roff=1T Vt=-.5 Vh=-.4) +.ends LT1964-BYP +* +.subckt LT1964-SD 1 2 3 4 5 +Q2 N007 N010 N008 0 NA +Q3 N010 N012 N011 0 N temp=27 +C1 N010 N012 18p Rser=40K +Q4 N012 N012 N013 0 N 10 temp=27 +R2 N013 2 12K +R3 N011 2 10K +Q1 N013 4 N014 0 P temp=27 +R6 1 N014 121.5K +R8 N008 2 1K +Q5 N007 N007 N006 0 P +Q6 N005 N007 1 0 P 6 +R1 N005 2 450K +R9 1 N006 4K +Q7 N004 N005 2 0 NP +R7 5 N004 .7 +Q8 2 N004 N010 0 P 4.5 +A1 1 3 0 0 0 0 N009 0 SCHMITT Vt=1.9 Vh=10m Rhigh=1 Rlow=1K +A2 3 1 0 0 0 0 N009 0 SCHMITT Vt=1.4 Vh=10m Rhigh=1 Rlow=1K +G2 1 N010 N009 0 1.2µ +G3 1 N012 N009 0 1.2µ +C4 0 N009 50µ +R4 3 1 5Meg +A3 0 N003 N010 N010 N010 N010 2 N010 VARISTOR +G4 0 N003 N004 5 10m +G6 0 N003 5 2 table( 7 4.3m 10 2.5m 20 1.5m) +C5 1 4 1p +C6 1 5 10p +C7 1 2 10p +D1 0 N003 X +C2 1 N012 500p Rser=.21G Rpar=6G +S1 0 N003 0 N009 SS +.model N NPN(Cje=5p Cjc=5p BF=150) +.model P PNP(Cje=5p Cjc=5p BF=150) +.model NP NPN(Cje=50p Cjc=50p BF=50) +.model NA NPN(Cje=1p Cjc=1p BF=8K) +.model X D(Ron=1 Roff=1K) +.model SS SW(Ron=1 Roff=1G Vt=-.95 Vh=-25m) +.ends LT1964-SD diff --git a/spice/copy/sub/LT1965.lib b/spice/copy/sub/LT1965.lib new file mode 100755 index 0000000..bc4478a --- /dev/null +++ b/spice/copy/sub/LT1965.lib @@ -0,0 +1,81 @@ +* Copyright © Linear Technology Corp. 2017. All rights reserved. +* +.subckt LT1965-x.x 1 2 3 4 5 +Q1 N007 N005 2 0 PN +Q2 N005 N003 3 0 NA +Q3 N003 N004 N011 0 NP temp=27 +C1 N003 N004 11p Rser=20K +Q4 N004 N004 N012 0 NP 10 temp=27 +R2 N012 3 200 +R3 N011 3 175 +C2 4 N004 195p +Q5 4 N009 N010 0 FB temp=27 +R6 N010 N012 1.361K +R5 1 3 10Meg +I1 1 3 3µ load +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=10u +G2 2 N004 N002 3 50µ +G1 2 N003 N002 3 50µ +R1 2 N005 50K +R8 N007 4 .1 +A2 N006 0 N003 N003 N003 N003 3 N003 VARISTOR +D3 0 N006 F +G3 0 N006 4 N007 10m +G4 0 N006 2 4 table(0 3.5m 6 4.5m 14 2m) +Q7 N004 N005 N007 0 P 1m +C4 2 N003 300p Rser=20Meg +D1 2 4 X +C5 5 3 1p +C6 4 3 10p +C7 2 3 10p +G5 N006 0 N002 3 table(0 4.5m 1 0) +C8 2 N004 4n Rser=12Meg Rpar=35Meg +R4 5 N009 {R} +R7 N009 3 12.2K +.model P PNP(BF=100) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model NA NPN(BF=60K Cje=5p Cjc=5p Re=5) +.model PN PNP(BF=25 Cje=200p Cjc=200p Tf=20n) +.model FB NPN(Cje=10p Cjc=10p BF=100) +.model F D(Ron=1m Roff=570 epsilon=.1) +.model X D(Ron=10 Vfwd=30) +.ends LT1965-x.x +* +.subckt LT1965 1 2 3 4 5 +Q1 N007 N005 2 0 PN +Q2 N005 N003 3 0 NA +Q3 N003 N004 N010 0 NP temp=27 +C1 N003 N004 11p Rser=20K +Q4 N004 N004 N011 0 NP 10 temp=27 +R2 N011 3 200 +R3 N010 3 175 +C2 4 N004 195p +Q5 4 5 N009 0 FB temp=27 +R6 N009 N011 1.361K +R5 1 3 10Meg +I1 1 3 3µ load +A1 1 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=10u +G2 2 N004 N002 3 50µ +G1 2 N003 N002 3 50µ +R1 2 N005 50K +R8 N007 4 .1 +A2 N006 0 N003 N003 N003 N003 3 N003 VARISTOR +D3 0 N006 F +G3 0 N006 4 N007 10m +G4 0 N006 2 4 table(0 3.5m 6 4.5m 14 2m) +Q7 N004 N005 N007 0 P 1m +C4 2 N003 300p Rser=20Meg +D1 2 4 X +C5 5 3 1p +C6 4 3 10p +C7 2 3 10p +G5 N006 0 N002 3 table(0 4.5m 1 0) +C8 2 N004 4n Rser=12Meg Rpar=35Meg +.model P PNP(BF=100) +.model NP NPN(Cje=5p Cjc=5p BF=150) +.model NA NPN(BF=60K Cje=5p Cjc=5p Re=5) +.model PN PNP(BF=25 Cje=200p Cjc=200p Tf=20n) +.model FB NPN(Cje=10p Cjc=10p BF=100) +.model F D(Ron=1m Roff=570 epsilon=.1) +.model X D(Ron=10 Vfwd=30) +.ends LT1965 diff --git a/spice/copy/sub/LT1976.sub b/spice/copy/sub/LT1976.sub new file mode 100755 index 0000000..b709f7f Binary files /dev/null and b/spice/copy/sub/LT1976.sub differ diff --git a/spice/copy/sub/LT1976B.sub b/spice/copy/sub/LT1976B.sub new file mode 100755 index 0000000..b758880 Binary files /dev/null and b/spice/copy/sub/LT1976B.sub differ diff --git a/spice/copy/sub/LT1977.sub b/spice/copy/sub/LT1977.sub new file mode 100755 index 0000000..09b0326 Binary files /dev/null and b/spice/copy/sub/LT1977.sub differ diff --git a/spice/copy/sub/LT2940.sub b/spice/copy/sub/LT2940.sub new file mode 100755 index 0000000..b86f30f Binary files /dev/null and b/spice/copy/sub/LT2940.sub differ diff --git a/spice/copy/sub/LT3001.sub b/spice/copy/sub/LT3001.sub new file mode 100755 index 0000000..318989b Binary files /dev/null and b/spice/copy/sub/LT3001.sub differ diff --git a/spice/copy/sub/LT3002.sub b/spice/copy/sub/LT3002.sub new file mode 100755 index 0000000..866324a Binary files /dev/null and b/spice/copy/sub/LT3002.sub differ diff --git a/spice/copy/sub/LT3009.lib b/spice/copy/sub/LT3009.lib new file mode 100755 index 0000000..95b5bfd --- /dev/null +++ b/spice/copy/sub/LT3009.lib @@ -0,0 +1,595 @@ +* Copyright © Linear Technology Corp. 2012. All rights reserved. +* +.subckt LT3008-1.2 1 2 3 4 5 +Q1 N009 N007 1 0 PN temp=27 +Q2 N007 N011 4 0 NA temp=27 +Q3 N011 N006 N014 0 NP temp=27 +C1 N011 N006 22p Rser=14.7Meg +Q4 N006 N006 N015 0 NP 10 temp=27 +R1 N015 4 33.6K +R2 N014 4 28K +C2 2 N006 5p +R3 N013 N015 297.18K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m +G1 1 N006 N003 4 .4286µ +G2 1 N011 N003 4 .4286µ +R5 1 N007 1.68Meg +R6 N009 2 8 +A2 N008 0 N011 N011 N011 N011 4 N011 VARISTOR +D1 0 N008 F +G3 0 N008 2 N009 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N008 0 N003 4 table(0 3m 1 0) +C6 1 N006 .28p Rser=1G +M§Q6 2 N012 N013 N013 NM temp=27 +C7 3 4 1p +D3 1 N012 300pA +G4 0 N008 1 0 table(1.6 1.22m 45 1.59m) +G6 0 N016 1 N009 table(.1 6.73u .5 100u) +A3 N016 0 N011 N011 N011 N011 4 N011 VARISTOR +C9 N016 0 1p Rpar=100K +D4 5 4 SI +C8 5 4 1p +A4 4 N002 4 N004 4 4 N003 4 AND Trise=200u +A5 1 4 4 4 4 4 N004 4 SCHMITT Vt=1.8 Vh=1m +D2 4 2 SB +R4 3 N012 570K +R7 N012 4 570K +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=1e-14) +.model SI D(Ron=10Meg Ilimit=.65u epsilon=10) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3008-1.2 +* +.subckt LT3008-1.5 1 2 3 4 5 +Q1 N009 N007 1 0 PN temp=27 +Q2 N007 N011 4 0 NA temp=27 +Q3 N011 N006 N014 0 NP temp=27 +C1 N011 N006 22p Rser=14.7Meg +Q4 N006 N006 N015 0 NP 10 temp=27 +R1 N015 4 33.6K +R2 N014 4 28K +C2 2 N006 5p +R3 N013 N015 297.18K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m +G1 1 N006 N003 4 .4286µ +G2 1 N011 N003 4 .4286µ +R5 1 N007 1.68Meg +R6 N009 2 8 +A2 N008 0 N011 N011 N011 N011 4 N011 VARISTOR +D1 0 N008 F +G3 0 N008 2 N009 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N008 0 N003 4 table(0 3m 1 0) +C6 1 N006 .28p Rser=1G +M§Q6 2 N012 N013 N013 NM temp=27 +C7 3 4 1p +D3 1 N012 300pA +G4 0 N008 1 0 table(1.6 1.22m 45 1.59m) +G6 0 N016 1 N009 table(.1 6.73u .5 100u) +A3 N016 0 N011 N011 N011 N011 4 N011 VARISTOR +C9 N016 0 1p Rpar=100K +D4 5 4 SI +C8 5 4 1p +A4 4 N002 4 N004 4 4 N003 4 AND Trise=200u +A5 1 4 4 4 4 4 N004 4 SCHMITT Vt=1.8 Vh=1m +D2 4 2 SB +R4 3 N012 855K +R7 N012 4 570K +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=1e-14) +.model SI D(Ron=10Meg Ilimit=.65u epsilon=10) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3008-1.5 +* +.subckt LT3008-1.8 1 2 3 4 5 +Q1 N009 N007 1 0 PN temp=27 +Q2 N007 N011 4 0 NA temp=27 +Q3 N011 N006 N014 0 NP temp=27 +C1 N011 N006 22p Rser=14.7Meg +Q4 N006 N006 N015 0 NP 10 temp=27 +R1 N015 4 33.6K +R2 N014 4 28K +C2 2 N006 5p +R3 N013 N015 297.18K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m +G1 1 N006 N003 4 .4286µ +G2 1 N011 N003 4 .4286µ +R5 1 N007 1.68Meg +R6 N009 2 8 +A2 N008 0 N011 N011 N011 N011 4 N011 VARISTOR +D1 0 N008 F +G3 0 N008 2 N009 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N008 0 N003 4 table(0 3m 1 0) +C6 1 N006 .28p Rser=1G +M§Q6 2 N012 N013 N013 NM temp=27 +C7 3 4 1p +D3 1 N012 300pA +G4 0 N008 1 0 table(1.6 1.22m 45 1.59m) +G6 0 N016 1 N009 table(.1 6.73u .5 100u) +A3 N016 0 N011 N011 N011 N011 4 N011 VARISTOR +C9 N016 0 1p Rpar=100K +D4 5 4 SI +C8 5 4 1p +A4 4 N002 4 N004 4 4 N003 4 AND Trise=200u +A5 1 4 4 4 4 4 N004 4 SCHMITT Vt=1.8 Vh=1m +D2 4 2 SB +R4 3 N012 1140K +R7 N012 4 570K +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=1e-14) +.model SI D(Ron=10Meg Ilimit=.65u epsilon=10) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3008-1.8 +* +.subckt LT3008-2.5 1 2 3 4 5 +Q1 N009 N007 1 0 PN temp=27 +Q2 N007 N011 4 0 NA temp=27 +Q3 N011 N006 N014 0 NP temp=27 +C1 N011 N006 22p Rser=14.7Meg +Q4 N006 N006 N015 0 NP 10 temp=27 +R1 N015 4 33.6K +R2 N014 4 28K +C2 2 N006 5p +R3 N013 N015 297.18K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m +G1 1 N006 N003 4 .4286µ +G2 1 N011 N003 4 .4286µ +R5 1 N007 1.68Meg +R6 N009 2 8 +A2 N008 0 N011 N011 N011 N011 4 N011 VARISTOR +D1 0 N008 F +G3 0 N008 2 N009 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N008 0 N003 4 table(0 3m 1 0) +C6 1 N006 .28p Rser=1G +M§Q6 2 N012 N013 N013 NM temp=27 +C7 3 4 1p +D3 1 N012 300pA +G4 0 N008 1 0 table(1.6 1.22m 45 1.59m) +G6 0 N016 1 N009 table(.1 6.73u .5 100u) +A3 N016 0 N011 N011 N011 N011 4 N011 VARISTOR +C9 N016 0 1p Rpar=100K +D4 5 4 SI +C8 5 4 1p +A4 4 N002 4 N004 4 4 N003 4 AND Trise=200u +A5 1 4 4 4 4 4 N004 4 SCHMITT Vt=1.8 Vh=1m +D2 4 2 SB +R4 3 N012 1805K +R7 N012 4 570K +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=1e-14) +.model SI D(Ron=10Meg Ilimit=.65u epsilon=10) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3008-2.5 +* +.subckt LT3008-3.3 1 2 3 4 5 +Q1 N009 N007 1 0 PN temp=27 +Q2 N007 N011 4 0 NA temp=27 +Q3 N011 N006 N014 0 NP temp=27 +C1 N011 N006 22p Rser=14.7Meg +Q4 N006 N006 N015 0 NP 10 temp=27 +R1 N015 4 33.6K +R2 N014 4 28K +C2 2 N006 5p +R3 N013 N015 297.18K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m +G1 1 N006 N003 4 .4286µ +G2 1 N011 N003 4 .4286µ +R5 1 N007 1.68Meg +R6 N009 2 8 +A2 N008 0 N011 N011 N011 N011 4 N011 VARISTOR +D1 0 N008 F +G3 0 N008 2 N009 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N008 0 N003 4 table(0 3m 1 0) +C6 1 N006 .28p Rser=1G +M§Q6 2 N012 N013 N013 NM temp=27 +C7 3 4 1p +D3 1 N012 300pA +G4 0 N008 1 0 table(1.6 1.22m 45 1.59m) +G6 0 N016 1 N009 table(.1 6.73u .5 100u) +A3 N016 0 N011 N011 N011 N011 4 N011 VARISTOR +C9 N016 0 1p Rpar=100K +D4 5 4 SI +C8 5 4 1p +A4 4 N002 4 N004 4 4 N003 4 AND Trise=200u +A5 1 4 4 4 4 4 N004 4 SCHMITT Vt=1.8 Vh=1m +D2 4 2 SB +R4 3 N012 2565K +R7 N012 4 570K +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=1e-14) +.model SI D(Ron=10Meg Ilimit=.65u epsilon=10) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3008-3.3 +* +.subckt LT3008-5 1 2 3 4 5 +Q1 N009 N007 1 0 PN temp=27 +Q2 N007 N011 4 0 NA temp=27 +Q3 N011 N006 N014 0 NP temp=27 +C1 N011 N006 22p Rser=14.7Meg +Q4 N006 N006 N015 0 NP 10 temp=27 +R1 N015 4 33.6K +R2 N014 4 28K +C2 2 N006 5p +R3 N013 N015 297.18K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m +G1 1 N006 N003 4 .4286µ +G2 1 N011 N003 4 .4286µ +R5 1 N007 1.68Meg +R6 N009 2 8 +A2 N008 0 N011 N011 N011 N011 4 N011 VARISTOR +D1 0 N008 F +G3 0 N008 2 N009 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N008 0 N003 4 table(0 3m 1 0) +C6 1 N006 .28p Rser=1G +M§Q6 2 N012 N013 N013 NM temp=27 +C7 3 4 1p +D3 1 N012 300pA +G4 0 N008 1 0 table(1.6 1.22m 45 1.59m) +G6 0 N016 1 N009 table(.1 6.73u .5 100u) +A3 N016 0 N011 N011 N011 N011 4 N011 VARISTOR +C9 N016 0 1p Rpar=100K +D4 5 4 SI +C8 5 4 1p +A4 4 N002 4 N004 4 4 N003 4 AND Trise=200u +A5 1 4 4 4 4 4 N004 4 SCHMITT Vt=1.8 Vh=1m +D2 4 2 SB +R4 3 N012 4180K +R7 N012 4 570K +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=1e-14) +.model SI D(Ron=10Meg Ilimit=.65u epsilon=10) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3008-5 +* +.subckt LT3008 1 2 3 4 5 +Q1 N008 N006 1 0 PN temp=27 +Q2 N006 N010 4 0 NA temp=27 +Q3 N010 N005 N013 0 NP temp=27 +C1 N010 N005 22p Rser=14.7Meg +Q4 N005 N005 N014 0 NP 10 temp=27 +R1 N014 4 33.6K +R2 N013 4 28K +C2 2 N005 5p +R3 N012 N014 297.18K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m +G1 1 N005 N003 4 .4286µ +G2 1 N010 N003 4 .4286µ +R5 1 N006 1.68Meg +R6 N008 2 8 +A2 N007 0 N010 N010 N010 N010 4 N010 VARISTOR +D1 0 N007 F +G3 0 N007 2 N008 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N007 0 N003 4 table(0 3m 1 0) +C6 1 N005 .28p Rser=1G +M§Q6 2 3 N012 N012 NM temp=27 +C7 3 4 1p +D3 1 3 300pA +G4 0 N007 1 0 table(1.6 1.22m 45 1.59m) +G6 0 N015 1 N008 table(.1 6.73u .5 100u) +A3 N015 0 N010 N010 N010 N010 4 N010 VARISTOR +C9 N015 0 1p Rpar=100K +D4 5 4 SI +C8 5 4 1p +A4 4 N002 4 N004 4 4 N003 4 AND Trise=200u +A5 1 4 4 4 4 4 N004 4 SCHMITT Vt=1.8 Vh=1m +D2 4 2 SB +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=1e-14) +.model SI D(Ron=10Meg Ilimit=.65u epsilon=10) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3008 +* +.subckt LT3009-1.2 1 2 3 4 5 +Q1 N007 N005 1 0 PN temp=27 +Q2 N005 N009 4 0 NA temp=27 +Q3 N009 N004 N011 0 NP temp=27 +C1 N009 N004 22p Rser=14.7Meg +Q4 N004 N004 N012 0 NP 10 temp=27 +R1 N012 4 33.6K +R2 N011 4 28K +C2 2 N004 5p +R3 N010 N012 647.1K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m Trise=200u +G1 1 N004 N002 4 .4286µ +G2 1 N009 N002 4 .4286µ +R5 1 N005 1.68Meg +R6 N007 2 8 +A2 N006 0 N009 N009 N009 N009 4 N009 VARISTOR +D1 0 N006 F +G3 0 N006 2 N007 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N006 0 N002 4 table(0 3m 1 0) +C6 1 N004 280p Rser=1.876G Rpar=42G +M§Q6 2 2 N010 N010 NM temp=27 +D3 2 4 300pA +G4 0 N006 1 0 table(1.6 1.22m 20 1.45m) +C8 5 4 1p Rpar=40Meg +G6 0 N013 1 N007 table(.1 6.56u .5 100u) +A3 N013 0 N009 N009 N009 N009 4 N009 VARISTOR +C9 N013 0 1p Rpar=100K +D2 4 2 SB +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=3e-12) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3009-1.2 +* +.subckt LT3009-1.5 1 2 3 4 5 +Q1 N007 N005 1 0 PN temp=27 +Q2 N005 N009 4 0 NA temp=27 +Q3 N009 N004 N011 0 NP temp=27 +C1 N009 N004 22p Rser=14.7Meg +Q4 N004 N004 N012 0 NP 10 temp=27 +R1 N012 4 33.6K +R2 N011 4 28K +C2 2 N004 5p +R3 N010 N012 822K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m Trise=200u +G1 1 N004 N002 4 .4286µ +G2 1 N009 N002 4 .4286µ +R5 1 N005 1.68Meg +R6 N007 2 8 +A2 N006 0 N009 N009 N009 N009 4 N009 VARISTOR +D1 0 N006 F +G3 0 N006 2 N007 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N006 0 N002 4 table(0 3m 1 0) +C6 1 N004 280p Rser=1.876G Rpar=42G +M§Q6 2 2 N010 N010 NM temp=27 +D3 2 4 300pA +G4 0 N006 1 0 table(1.6 1.22m 20 1.45m) +C8 5 4 1p Rpar=40Meg +G6 0 N013 1 N007 table(.1 6.56u .5 100u) +A3 N013 0 N009 N009 N009 N009 4 N009 VARISTOR +C9 N013 0 1p Rpar=100K +D2 4 2 SB +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=3e-12) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3009-1.5 +* +.subckt LT3009-1.8 1 2 3 4 5 +Q1 N007 N005 1 0 PN temp=27 +Q2 N005 N009 4 0 NA temp=27 +Q3 N009 N004 N011 0 NP temp=27 +C1 N009 N004 22p Rser=14.7Meg +Q4 N004 N004 N012 0 NP 10 temp=27 +R1 N012 4 33.6K +R2 N011 4 28K +C2 2 N004 5p +R3 N010 N012 997K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m Trise=200u +G1 1 N004 N002 4 .4286µ +G2 1 N009 N002 4 .4286µ +R5 1 N005 1.68Meg +R6 N007 2 8 +A2 N006 0 N009 N009 N009 N009 4 N009 VARISTOR +D1 0 N006 F +G3 0 N006 2 N007 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N006 0 N002 4 table(0 3m 1 0) +C6 1 N004 280p Rser=1.876G Rpar=42G +M§Q6 2 2 N010 N010 NM temp=27 +D3 2 4 300pA +G4 0 N006 1 0 table(1.6 1.22m 20 1.45m) +C8 5 4 1p Rpar=40Meg +G6 0 N013 1 N007 table(.1 6.56u .5 100u) +A3 N013 0 N009 N009 N009 N009 4 N009 VARISTOR +C9 N013 0 1p Rpar=100K +D2 4 2 SB +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=3e-12) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3009-1.8 +* +.subckt LT3009-2.5 1 2 3 4 5 +Q1 N007 N005 1 0 PN temp=27 +Q2 N005 N009 4 0 NA temp=27 +Q3 N009 N004 N011 0 NP temp=27 +C1 N009 N004 22p Rser=14.7Meg +Q4 N004 N004 N012 0 NP 10 temp=27 +R1 N012 4 33.6K +R2 N011 4 28K +C2 2 N004 5p +R3 N010 N012 1405K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m Trise=200u +G1 1 N004 N002 4 .4286µ +G2 1 N009 N002 4 .4286µ +R5 1 N005 1.68Meg +R6 N007 2 8 +A2 N006 0 N009 N009 N009 N009 4 N009 VARISTOR +D1 0 N006 F +G3 0 N006 2 N007 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N006 0 N002 4 table(0 3m 1 0) +C6 1 N004 280p Rser=1.876G Rpar=42G +M§Q6 2 2 N010 N010 NM temp=27 +D3 2 4 300pA +G4 0 N006 1 0 table(1.6 1.22m 20 1.45m) +C8 5 4 1p Rpar=40Meg +G6 0 N013 1 N007 table(.1 6.56u .5 100u) +A3 N013 0 N009 N009 N009 N009 4 N009 VARISTOR +C9 N013 0 1p Rpar=100K +D2 4 2 SB +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=3e-12) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3009-2.5 +* +.subckt LT3009-3.3 1 2 3 4 5 +Q1 N007 N005 1 0 PN temp=27 +Q2 N005 N009 4 0 NA temp=27 +Q3 N009 N004 N011 0 NP temp=27 +C1 N009 N004 22p Rser=14.7Meg +Q4 N004 N004 N012 0 NP 10 temp=27 +R1 N012 4 33.6K +R2 N011 4 28K +C2 2 N004 5p +R3 N010 N012 1872K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m Trise=200u +G1 1 N004 N002 4 .4286µ +G2 1 N009 N002 4 .4286µ +R5 1 N005 1.68Meg +R6 N007 2 8 +A2 N006 0 N009 N009 N009 N009 4 N009 VARISTOR +D1 0 N006 F +G3 0 N006 2 N007 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N006 0 N002 4 table(0 3m 1 0) +C6 1 N004 280p Rser=1.876G Rpar=42G +M§Q6 2 2 N010 N010 NM temp=27 +D3 2 4 300pA +G4 0 N006 1 0 table(1.6 1.22m 20 1.45m) +C8 5 4 1p Rpar=40Meg +G6 0 N013 1 N007 table(.1 6.56u .5 100u) +A3 N013 0 N009 N009 N009 N009 4 N009 VARISTOR +C9 N013 0 1p Rpar=100K +D2 4 2 SB +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=3e-12) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3009-3.3 +* +.subckt LT3009-5 1 2 3 4 5 +Q1 N007 N005 1 0 PN temp=27 +Q2 N005 N009 4 0 NA temp=27 +Q3 N009 N004 N011 0 NP temp=27 +C1 N009 N004 22p Rser=14.7Meg +Q4 N004 N004 N012 0 NP 10 temp=27 +R1 N012 4 33.6K +R2 N011 4 28K +C2 2 N004 5p +R3 N010 N012 2864K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m Trise=200u +G1 1 N004 N002 4 .4286µ +G2 1 N009 N002 4 .4286µ +R5 1 N005 1.68Meg +R6 N007 2 8 +A2 N006 0 N009 N009 N009 N009 4 N009 VARISTOR +D1 0 N006 F +G3 0 N006 2 N007 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N006 0 N002 4 table(0 3m 1 0) +C6 1 N004 280p Rser=1.876G Rpar=42G +M§Q6 2 2 N010 N010 NM temp=27 +D3 2 4 300pA +G4 0 N006 1 0 table(1.6 1.22m 20 1.45m) +C8 5 4 1p Rpar=40Meg +G6 0 N013 1 N007 table(.1 6.56u .5 100u) +A3 N013 0 N009 N009 N009 N009 4 N009 VARISTOR +C9 N013 0 1p Rpar=100K +D2 4 2 SB +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=3e-12) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3009-5 +* +.subckt LT3009 1 2 3 4 5 +Q1 N007 N005 1 0 PN temp=27 +Q2 N005 N009 4 0 NA temp=27 +Q3 N009 N004 N011 0 NP temp=27 +C1 N009 N004 22p Rser=14.7Meg +Q4 N004 N004 N012 0 NP 10 temp=27 +R1 N012 4 33.6K +R2 N011 4 28K +C2 2 N004 5p +R3 N010 N012 297.18K +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.8 Vh=1m Trise=200u +G1 1 N004 N002 4 .4286µ +G2 1 N009 N002 4 .4286µ +R5 1 N005 1.68Meg +R6 N007 2 8 +A2 N006 0 N009 N009 N009 N009 4 N009 VARISTOR +D1 0 N006 F +G3 0 N006 2 N007 1.25m +C4 2 4 10p +C5 1 4 10p +G5 N006 0 N002 4 table(0 3m 1 0) +C6 1 N004 280p Rser=1.876G Rpar=42G +M§Q6 2 3 N010 N010 NM temp=27 +C7 3 4 1p +D3 1 3 300pA +G4 0 N006 1 0 table(1.6 1.22m 20 1.45m) +C8 5 4 1p Rpar=40Meg +G6 0 N013 1 N007 table(.1 6.56u .5 100u) +A3 N013 0 N009 N009 N009 N009 4 N009 VARISTOR +C9 N013 0 1p Rpar=100K +D2 4 2 SB +.model F D(Ron=1m Roff=1K) +.model NM VDMOS(Kp=10m Vto=0) +.model NP NPN(Cje=2p Cjc=2p BF=150) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=30) +.model 300pA D(Ron=1G Ilimit=.3n epsilon=.2) +.model PN PNP(BF=45.5 Cje=50p Cjc=50p Is=3e-12) +.model SB D(Ron=10 Roff=1T epsilon=1.2) +.ends LT3009 diff --git a/spice/copy/sub/LT3010.lib b/spice/copy/sub/LT3010.lib new file mode 100755 index 0000000..442c219 --- /dev/null +++ b/spice/copy/sub/LT3010.lib @@ -0,0 +1,126 @@ +* Copyright © Linear Technology Corp. 2009. All rights reserved. +* +.subckt LT3010-5 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN temp=27 +Q2 N005 N009 4 0 NA temp=27 +Q3 N009 N004 N012 0 NP temp=27 +C1 N009 4 6p Rser=500K +Q4 N004 N004 N013 0 NP 10 temp=27 +R2 N013 4 10K +R3 N012 4 12K +C2 1 N004 26p Rser=1K +Q5 1 N010 N011 0 FB temp=27 +R6 N011 N013 89.4K +G2 8 N004 N002 4 1.2µ +G1 8 N009 N002 4 1.2µ +R1 8 N005 225K +R8 N007 1 2 +A2 N006 0 N009 N009 N009 N009 4 N009 VARISTOR +D3 0 N006 F +G3 0 N006 1 N007 13m +Q7 N004 N005 N007 0 P .2m +C5 1 4 10p +C7 8 4 10p +G5 N006 0 N002 4 table(0 4.2m 1 0) +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.95 Vh=1m trise=2m +C6 2 4 10p +G4 0 N006 8 4 table(2.1 1.5m 5.5 4.2m 10 4.7m) +R5 8 N004 1.2G +R7 2 N010 371K +R9 N010 4 127.5K +D1 8 5 200nA +C4 5 4 1p +.model PN PNP(BF=25 Cje=100p Cjc=100p) +.model NA NPN(BF=170K Cje=.25p Cjc=.25p Re=50) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=123) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model 200nA D(Ron=4Meg Ilimit=200n epsilon=.1) +.ends LT3010-5 +* +.subckt LT3010 1 2 3 4 5 6 7 8 +Q1 N006 N004 8 0 PN +Q2 N004 N008 4 0 NA +Q3 N008 N003 N011 0 NP temp=27 +C1 N008 4 6p Rser=500K +Q4 N003 N003 N012 0 NP 10 temp=27 +R2 N012 4 10K +R3 N011 4 12K +C2 1 N003 26p Rser=1K +Q5 1 2 N010 0 FB temp=27 +R6 N010 N012 89.4K +I1 8 5 .2µ load +G2 8 N003 N002 4 1.2µ +G1 8 N008 N002 4 1.2µ +R1 8 N004 225K +R8 N006 1 2 +A2 N005 0 N008 N008 N008 N008 4 N008 VARISTOR +D3 4 N005 F +G3 4 N005 1 N006 13m +Q7 N003 N004 N006 0 P .2m +C5 1 4 10p +C7 8 4 10p +G5 N005 0 N002 4 table(0 4.2m 1 0) +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.95 Vh=1m trise=2m +C6 2 4 10p +G4 4 N005 8 4 table(2.1 1.5m 5.5 4.2m 10 4.7m) +R5 8 N003 1.2G +D1 N008 4 BIA +.model PN PNP(BF=25 Cje=100p Cjc=100p) +.model NA NPN(BF=170K Cje=.25p Cjc=.25p Re=50) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=123) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model BIA D(Ron=100K Roff=1G Vfwd=.91) +.ends LT3010 +* +.subckt LT3011 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN temp=27 +Q2 N005 N009 4 0 NA temp=27 +Q3 N009 N004 N011 0 NP temp=27 +C1 N009 4 6p Rser=500K +Q4 N004 N004 N012 0 NP 10 temp=27 +R2 N012 4 10K +R3 N011 4 12K +C2 1 N004 26p Rser=1K +Q5 1 2 N010 0 FB temp=27 +R6 N010 N012 84.5K +G2 8 N004 N002 4 1.2µ +G1 8 N009 N002 4 1.2µ +R1 8 N005 225K +R8 N007 1 2 +A2 N006 0 N009 N009 N009 N009 4 N009 VARISTOR +D3 0 N006 F +G3 0 N006 1 N007 13m +Q7 N004 N005 N007 0 P .2m +C5 1 4 10p +C7 8 4 10p +G5 N006 0 N002 4 table(0 4.2m 1 0) +A1 5 4 4 4 4 4 N002 4 SCHMITT Vt=.95 Vh=1m trise=2m +C6 2 4 10p +G4 0 N006 8 4 table(2.1 1.5m 5.5 4.2m 10 4.7m) +R5 8 N004 1.2G +D1 8 5 200nA +A3 3 4 4 4 4 N017 4 4 SCHMITT Vt=.925 Vh=.825 +A4 4 N013 N016 N017 4 4 N014 4 AND Trise=10n +A5 2 4 4 4 4 N018 N013 4 SCHMITT Vt=1.116 Vh=3m Trise=30u +M1 6 N022 4 4 PG +A7 N014 N018 4 4 4 4 3 4 SRFLOP ic=0 Vhigh=2.5 Vlow=0 Rout=1G Ref=.5 Isrc=3u Isink=-100u +C8 3 4 2p +A6 4 N017 4 N016 4 4 N022 4 AND tau=1u +A8 8 4 4 4 4 4 N023 4 SCHMITT Vt=2.6 Vh=.1 +A9 5 4 4 4 4 4 N021 4 SCHMITT Vt=.95 Vh=1m +A10 4 N021 4 N023 4 4 N016 4 AND Tau=1u +C9 5 4 1p +.model P PNP(BF=100) +.model NA NPN(BF=170K Cje=.25p Cjc=.25p Re=50) +.model 200nA D(Ron=4Meg Ilimit=200n epsilon=.1) +.model PN PNP(BF=25 Cje=100p Cjc=100p) +.model NP NPN(Cje=10p Cjc=10p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=123) +.model PG VDMOS(Kp=110u Cjo=5p) +.model F D(Ron=1m Roff=10K) +.ends LT3011 diff --git a/spice/copy/sub/LT3012.lib b/spice/copy/sub/LT3012.lib new file mode 100755 index 0000000..eba5264 --- /dev/null +++ b/spice/copy/sub/LT3012.lib @@ -0,0 +1,91 @@ +* Copyright © Linear Technology Corp. 2012. All rights reserved. +* +.subckt LT3012 1 2 3 4 5 6 7 8 9 10 +Q1 N008 N006 10 0 PN +Q2 N006 N004 5 0 NA +Q3 N004 N005 N011 0 NP +C1 N004 N005 6p Rser=500K +Q4 N005 N005 N013 0 NP 10 +R2 N013 5 12K +R3 N011 5 10K +C2 2 N005 30p Rser=1K +Q5 2 4 N012 0 FB +R6 N012 N013 111.6K +R5 8 5 10Meg +I1 8 5 3µ load +A1 8 5 5 5 5 5 N002 5 SCHMITT Vt=.8 Vh=1m trise=2m +G2 10 N005 N002 5 1.3µ +G1 10 N004 N002 5 1.3µ +R1 10 N006 70K +R8 N008 2 .2 +A2 N007 5 N004 N004 N004 N004 5 N004 VARISTOR +D3 5 N007 F +G3 5 N007 2 N008 250m +Q7 N005 N006 N008 0 P 5m +D1 10 2 X +C7 10 5 10p +G5 N007 5 N002 5 table(0 42m 1 0) +C4 10 N004 2p Rser=1G +C5 10 N005 1p Rser=1G +C8 4 5 1p +C9 2 5 10p +G4 5 N007 10 5 table(2 .01m 10 35.5m 30 40.5m 80 14m) +G6 10 5 10 5 table(25 0 80 175u) +A6 5 N002 5 5 5 5 N003 5 VARISTOR +R10 N003 10 10G +G7 10 5 N003 5 table(.9 0 1 45u) +.model PN PNP(BF=30 Cje=100p Cjc=100p Tf=10n Re=.25) +.model NA NPN(BF=1Meg Cje=40p Cjc=40p Re=20) +.model NP NPN(BF=150) +.model FB NPN(BF=150 Cje=100p Cjc=100p ) +.model F D(Ron=1m Roff=10K Vrev=10) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=90) +.model CDC NPN (BF=100 Re=8K Rb=1Meg) +.model P PNP (BF=1000 Re=1) +.model N1 NPN (BF=100 Rb=10Meg) +.ends LT3012 +* +.subckt LT3012B 1 2 3 4 5 6 7 8 9 10 +Q1 N008 N006 10 0 PN +Q2 N006 N004 5 0 NA +Q3 N004 N005 N011 0 NP +C1 N004 N005 6p Rser=500K +Q4 N005 N005 N013 0 NP 10 +R2 N013 5 12K +R3 N011 5 10K +C2 2 N005 30p Rser=1K +Q5 2 4 N012 0 FB +R6 N012 N013 111.6K +A1 10 5 5 5 5 5 N001 5 SCHMITT Vt=.8 Vh=1m trise=2m +G2 10 N005 N001 5 1.3µ +G1 10 N004 N001 5 1.3µ +R1 10 N006 70K +R8 N008 2 .2 +A2 N007 5 N004 N004 N004 N004 5 N004 VARISTOR +D3 5 N007 F +G3 5 N007 2 N008 250m +Q7 N005 N006 N008 0 P 5m +D1 10 2 X +C7 10 5 10p +G5 N007 5 N001 5 table(0 42m 1 0) +C4 10 N004 2p Rser=1G +C5 10 N005 1p Rser=1G +C8 4 5 1p +C9 2 5 10p +G4 5 N007 10 5 table(2 .01m 10 35.5m 30 40.5m 80 14m) +G6 10 5 10 5 table(25 0 80 175u) +A6 5 N001 5 5 5 5 N002 5 VARISTOR +R10 N002 10 10G +G7 10 5 N002 5 table(.9 0 1 45u) +.model PN PNP(BF=30 Cje=100p Cjc=100p Tf=10n Re=.25) +.model NA NPN(BF=1Meg Cje=40p Cjc=40p Re=20) +.model NP NPN(BF=150) +.model FB NPN(BF=150 Cje=100p Cjc=100p ) +.model F D(Ron=1m Roff=10K Vrev=10) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=90) +.model CDC NPN (BF=100 Re=8K Rb=1Meg) +.model P PNP (BF=1000 Re=1) +.model N1 NPN (BF=100 Rb=10Meg) +.ends LT3012B diff --git a/spice/copy/sub/LT3013.lib b/spice/copy/sub/LT3013.lib new file mode 100755 index 0000000..c6c00b7 --- /dev/null +++ b/spice/copy/sub/LT3013.lib @@ -0,0 +1,111 @@ +* Copyright © Linear Technology Corp. 2004. All rights reserved. +* +.subckt LT3013 1 2 3 4 5 6 7 8 9 10 +Q1 N016 N012 10 0 PN +Q2 N012 N010 5 0 NA +Q3 N010 N011 N020 0 NP +C1 N010 N011 6p Rser=500K +Q4 N011 N011 N022 0 NP 10 +R2 N022 5 12K +R3 N020 5 10K +C2 2 N011 30p Rser=1K +Q5 2 4 N021 0 FB +R6 N021 N022 111.6K +R5 8 5 10Meg +I1 8 5 3µ load +A1 8 5 5 5 5 5 N002 5 SCHMITT Vt=.8 Vh=1m trise=2m +G2 10 N011 N002 5 1.3µ +G1 10 N010 N002 5 1.3µ +R1 10 N012 70K +R8 N016 2 .2 +A2 N014 5 N010 N010 N010 N010 5 N010 VARISTOR +D3 5 N014 F +G3 5 N014 2 N016 250m +Q7 N011 N012 N016 0 P 5m +D1 10 2 X +C7 10 5 10p Rpar=50Meg +G5 N014 5 N002 5 table(0 42m 1 0) +C4 10 N010 2p Rser=1G +C5 10 N011 1p Rser=1G +C8 4 5 1p Rpar=50Meg +C9 2 5 10p Rpar=.1G +A3 4 5 5 5 5 N017 N015 5 SCHMITT Vt=1.16 Trise=10u Vh=10m +A4 N015 N017 5 5 5 N008 5 5 SRFLOP Trise=10u +Q6 7 N008 5 0 CDC +R11 N007 7 1K +Q8 N013 N005 N007 0 P +R12 N013 5 500K +Q9 N006 N013 5 0 N1 +Q10 6 N006 5 0 NP +A5 10 5 5 5 5 5 N005 5 SCHMITT Vt=0.7 Vh=1m Trise=1u Vhigh=1.07 +G4 5 N014 10 5 table(2 .01m 10 35.5m 30 40.5m 80 14m) +G6 10 5 10 5 table(25 0 80 175u) +A6 5 N002 5 5 5 5 N004 5 VARISTOR +R10 N004 10 10G +G7 10 5 N004 5 table(.9 0 1 45u) +G8 10 7 N005 5 3.35µ +G9 10 N006 N005 5 50n +.model PN PNP(BF=30 Cje=100p Cjc=100p Tf=10n Re=.25) +.model NA NPN(BF=1Meg Cje=40p Cjc=40p Re=20) +.model NP NPN(BF=600) +.model FB NPN(BF=150 Cje=100p Cjc=100p) +.model F D(Ron=1m Roff=10K Vrev=10) +.model X D(Ron=100 Vfwd=90) +.model CDC NPN (BF=100 Re=8K Rb=1Meg) +.model P PNP (BF=100 Rb=10) +.model N1 NPN (BF=100 Rb=10Meg) +.ends LT3013 +* +.subckt LT3013B 1 2 3 4 5 6 7 8 9 10 +Q1 N016 N012 10 0 PN +Q2 N012 N010 5 0 NA +Q3 N010 N011 N020 0 NP +C1 N010 N011 6p Rser=500K +Q4 N011 N011 N022 0 NP 10 +R2 N022 5 12K +R3 N020 5 10K +C2 2 N011 30p Rser=1K +Q5 2 4 N021 0 FB +R6 N021 N022 111.6K +A1 10 5 5 5 5 5 N002 5 SCHMITT Vt=.8 Vh=1m trise=2m +G2 10 N011 N002 5 1.3µ +G1 10 N010 N002 5 1.3µ +R1 10 N012 70K +R8 N016 2 .2 +A2 N014 5 N010 N010 N010 N010 5 N010 VARISTOR +D3 5 N014 F +G3 5 N014 2 N016 250m +Q7 N011 N012 N016 0 P 5m +D1 10 2 X +C7 10 5 10p +G5 N014 5 N002 5 table(0 42m 1 0) +C4 10 N010 2p Rser=1G +C5 10 N011 1p Rser=1G +C8 4 5 1p +C9 2 5 10p +A3 4 5 5 5 5 N017 N015 5 SCHMITT Vt=1.16 Trise=10u Vh=10m +A4 N015 N017 5 5 5 N008 5 5 SRFLOP Trise=10u +Q6 7 N008 5 0 CDC +R11 N007 7 1K +Q8 N013 N005 N007 0 P +R12 N013 5 500K +Q9 N006 N013 5 0 N1 +Q10 6 N006 5 0 NP +A5 10 5 5 5 5 5 N005 5 SCHMITT Vt=0.7 Vh=1m Trise=1u Vhigh=1.07 +G4 5 N014 10 5 table(2 .01m 10 35.5m 30 40.5m 80 14m) +G6 10 5 10 5 table(25 0 80 175u) +A6 5 N002 5 5 5 5 N004 5 VARISTOR +R10 N004 10 10G +G7 10 5 N004 5 table(.9 0 1 45u) +G8 10 7 N005 5 3.35µ +G9 10 N006 N005 5 50n +.model PN PNP(BF=30 Cje=100p Cjc=100p Tf=10n Re=.25) +.model NA NPN(BF=1Meg Cje=40p Cjc=40p Re=20) +.model NP NPN(BF=600) +.model FB NPN(BF=150 Cje=100p Cjc=100p ) +.model F D(Ron=1m Roff=10K Vrev=10) +.model X D(Ron=10 Vfwd=90) +.model CDC NPN (BF=100 Re=8K Rb=1Meg) +.model P PNP (BF=100 Rb=10) +.model N1 NPN (BF=100 Rb=10Meg) +.ends LT3013B diff --git a/spice/copy/sub/LT3014.lib b/spice/copy/sub/LT3014.lib new file mode 100755 index 0000000..d0978d3 --- /dev/null +++ b/spice/copy/sub/LT3014.lib @@ -0,0 +1,80 @@ +* Copyright © Linear Technology Corp. 2012. All rights reserved. +* +.subckt LT3014 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN Temp=27 +Q2 N005 N003 4 0 NA +Q3 N003 N004 N010 0 NP Temp=27 +C1 N003 4 4p Rser=700K +Q4 N004 N004 N012 0 NP 10 Temp=27 +R2 N012 4 72K +R3 N010 4 60K +C2 1 N004 13p Rser=500K +Q5 1 2 N011 0 FB Temp=27 +R6 N011 N012 703K +R5 5 4 10Meg +I1 5 4 3µ load +A1 5 4 4 4 4 4 N001 4 SCHMITT Vt=.8 Vh=1m trise=2m +G2 8 N004 N001 4 250n +G1 8 N003 N001 4 250n +R1 8 N005 1.67Meg +R8 N007 1 .2 +A2 N006 4 N003 N003 N003 N003 4 N003 VARISTOR +D3 4 N006 F +G3 4 N006 1 N007 250m +Q7 N004 N005 N007 0 P 3m +D1 8 1 X +C7 8 4 10p +G5 N006 4 N001 4 table(0 3m 1 0) +G4 4 N006 8 4 table(2 .05m 5.5 2.9m 25 3.9m) +C4 8 N003 2p Rser=1G +C5 8 N004 1p Rser=1G +C8 2 4 1p +C9 1 4 10p +S1 N003 4 4 N001 SDN +.model PN PNP(BF=30 Cje=100p Cjc=100p Tf=10n Re=1.5) +.model NA NPN(BF=1Meg Cje=5p Cjc=3p Re=100) +.model NP NPN(BF=150) +.model FB NPN(BF=195 Cje=100p Cjc=100p ) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=90) +.model SDN SW(Ron=1 Roff=10G Vt=-.5 Vh=-.1) +.ends LT3014 +* +.subckt LT3014B 1 2 3 4 5 6 7 8 +Q1 N007 N005 8 0 PN Temp=27 +Q2 N005 N003 4 0 NA +Q3 N003 N004 N010 0 NP Temp=27 +C1 N003 4 4p Rser=700K +Q4 N004 N004 N012 0 NP 10 Temp=27 +R2 N012 4 72K +R3 N010 4 60K +C2 1 N004 13p Rser=500K +Q5 1 2 N011 0 FB Temp=27 +R6 N011 N012 703K +A1 8 4 4 4 4 4 N001 4 SCHMITT Vt=.8 Vh=1m trise=2m +G2 8 N004 N001 4 250n +G1 8 N003 N001 4 250n +R1 8 N005 1.67Meg +R8 N007 1 .2 +A2 N006 4 N003 N003 N003 N003 4 N003 VARISTOR +D3 4 N006 F +G3 4 N006 1 N007 250m +Q7 N004 N005 N007 0 P 3m +D1 8 1 X +C7 8 4 10p +G4 4 N006 8 4 table(2 .05m 5.5 2.9m 25 3.9m) +C4 8 N003 2p Rser=1G +C5 8 N004 1p Rser=1G +C8 2 4 1p +C9 1 4 10p +S1 N003 4 4 N001 SDN +.model PN PNP(BF=30 Cje=100p Cjc=100p Tf=10n Re=1.5) +.model NA NPN(BF=1Meg Cje=5p Cjc=3p Re=100) +.model NP NPN(BF=150) +.model FB NPN(BF=195 Cje=100p Cjc=100p ) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=90) +.model SDN SW(Ron=1 Roff=10G Vt=-.5 Vh=-.1) +.ends LT3014B diff --git a/spice/copy/sub/LT3015.lib b/spice/copy/sub/LT3015.lib new file mode 100755 index 0000000..f511b5d --- /dev/null +++ b/spice/copy/sub/LT3015.lib @@ -0,0 +1,48 @@ +* Copyright © Linear Technology Corp. 2011. All rights reserved. +* +.subckt LT3015 1 2 3 4 5 +Q1 N010 N008 2 0 PN temp=27 +Q2 N008 N006 3 0 NA temp=27 +Q3 N006 N007 N013 0 NP temp=27 +C1 N006 N007 100p Rser=20K +Q4 N007 N007 N014 0 NP 10 temp=27 +R2 N014 3 96 +R3 N013 3 175 +C2 4 N007 195p +Q5 4 5 N012 0 FB temp=27 +R6 N012 N014 500 +G2 2 N007 N002 3 150µ +G1 2 N006 N002 3 150µ +R1 2 N008 50K +R8 N010 4 .1 +A2 N009 0 N006 N006 N006 N006 3 N006 VARISTOR +D3 N009 0 F +G3 0 N009 4 N010 10m +G4 0 N009 2 4 table(-18 -1.55m -10 -4.25m) +Q7 N007 N008 N010 0 P 13m temp=27 +C4 2 N006 300p Rser=20Meg +D1 4 2 X +C5 5 3 1p +C6 4 3 10p +C7 2 3 10p +G5 N009 0 N002 3 table(-1 0 0 -4.5m) +C8 2 N007 4n Rser=12Meg Rpar=35Meg +D2 1 3 S2 +D4 1 3 S1 +D5 3 1 S3 +A3 1 3 3 3 3 3 N001 3 SCHMITT Vt=.96 Vh=.24 +A4 3 N001 3 N004 3 N002 3 3 OR tau=10u ref=.5 Vhigh=0 Vlow=-1 +A1 1 3 3 3 3 N004 3 3 SCHMITT Vt=-.96 Vh=.24 +R5 5 2 .75G +G6 3 5 N002 3 60n +.model P NPN(BF=100) +.model NP PNP(Cje=10p Cjc=10p BF=150) +.model NA PNP(BF=6K Cje=5p Cjc=5p Re=50) +.model PN NPN(BF=300 Cje=400p Cjc=400p Tf=5n) +.model FB PNP(Cje=10p Cjc=10p BF=30K) +.model F D(Ron=1m Roff=570 epsilon=.1) +.model X D(Ron=10 Vfwd=30) +.model S1 D(Ron=250K epsilon=.5 Ilimit=10u) +.model S2 D(Ron=3Meg epsilon=.5) +.model S3 D(Ron=3Meg epsilon=2 Vfwd=3) +.ends LT3015 diff --git a/spice/copy/sub/LT3020.lib b/spice/copy/sub/LT3020.lib new file mode 100755 index 0000000..01a2a3e --- /dev/null +++ b/spice/copy/sub/LT3020.lib @@ -0,0 +1,127 @@ +* Copyright © Linear Technology Corp. 2011. All rights reserved. +* +.subckt LT3020-1.2 1 2 3 4 5 6 7 +Q1 N003 N007 N002 0 PE temp=27 +R15 N003 1 1m +A2 4 N008 4 N011 4 4 N005 4 AND Tau=1u +A1 5 4 4 4 4 4 N011 4 SCHMITT Vt=.8 Vh=1m trise=1u +A3 7 4 4 4 4 4 N008 4 SCHMITT Vt=.92 Vh=1m Trise=1u +A4 4 N012 N013 4 4 4 N007 4 OTA Vhigh=11 G=2 Iout=1.2m Ref=-.2 +G1 4 N012 N009 4 10µ +C2 N012 4 10p Rser=5K Rpar=100K +C3 N009 4 1p Rpar=1G +C4 N007 4 65n Rser=50 +D1 5 4 BIA +C5 7 4 1p Rpar=1G +A5 N006 4 N013 N013 N013 N013 4 N013 VARISTOR +D2 4 N006 F +G2 4 N006 1 N003 20 +G3 4 N006 N002 4 table(1.7 6.3m 10 7.2m) +R1 N013 N005 10Meg +G4 N002 4 N005 4 120µ +D3 N002 4 BIA +S1 4 1 N009 4 OV +A6 4 N002 N007 N007 N007 N007 4 N007 VARISTOR table(.5 0 10.5 10) +R2 1 N009 100K +R3 N009 4 20K +D4 7 N002 STUB +.model PE PNP(Rb=100 BF=155 Cjc=1n Cje=1n VAF=3) +.model BIA D(Ron=100 Roff=1G Ilimit=3u) +.model F D(Ron=1m Roff=10K Vrev=30) +.model OV SW(Ron=1 Roff=1G Vt=.21 Vh=-5m level=2 ilimit=16m oneway) +.model STUB D(Ron=10m Roff=.1G) +.ends LT3020-1.2 +* +.subckt LT3020-1.5 1 2 3 4 5 6 7 +Q1 N003 N007 N002 0 PE temp=27 +R15 N003 1 1m +A2 4 N008 4 N011 4 4 N005 4 AND Tau=1u +A1 5 4 4 4 4 4 N011 4 SCHMITT Vt=.8 Vh=1m trise=1u +A3 7 4 4 4 4 4 N008 4 SCHMITT Vt=.92 Vh=1m Trise=1u +A4 4 N012 N013 4 4 4 N007 4 OTA Vhigh=11 G=2 Iout=1.2m Ref=-.2 +G1 4 N012 N009 4 10µ +C2 N012 4 10p Rser=5K Rpar=100K +C3 N009 4 1p Rpar=1G +C4 N007 4 65n Rser=50 +D1 5 4 BIA +C5 7 4 1p Rpar=1G +A5 N006 4 N013 N013 N013 N013 4 N013 VARISTOR +D2 4 N006 F +G2 4 N006 1 N003 20 +G3 4 N006 N002 4 table(1.7 6.3m 10 7.2m) +R1 N013 N005 10Meg +G4 N002 4 N005 4 120µ +D3 N002 4 BIA +S1 4 1 N009 4 OV +A6 4 N002 N007 N007 N007 N007 4 N007 VARISTOR table(.5 0 10.5 10) +R2 1 N009 130K +R3 N009 4 20K +D4 7 N002 STUB +.model PE PNP(Rb=100 BF=155 Cjc=1n Cje=1n VAF=3) +.model BIA D(Ron=100 Roff=1G Ilimit=3u) +.model F D(Ron=1m Roff=10K Vrev=30) +.model OV SW(Ron=1 Roff=1G Vt=.21 Vh=-5m level=2 ilimit=16m oneway) +.model STUB D(Ron=10m Roff=.1G) +.ends LT3020-1.5 +* +.subckt LT3020-1.8 1 2 3 4 5 6 7 +Q1 N003 N007 N002 0 PE temp=27 +R15 N003 1 1m +A2 4 N008 4 N011 4 4 N005 4 AND Tau=1u +A1 5 4 4 4 4 4 N011 4 SCHMITT Vt=.8 Vh=1m trise=1u +A3 7 4 4 4 4 4 N008 4 SCHMITT Vt=.92 Vh=1m Trise=1u +A4 4 N012 N013 4 4 4 N007 4 OTA Vhigh=11 G=2 Iout=1.2m Ref=-.2 +G1 4 N012 N009 4 10µ +C2 N012 4 10p Rser=5K Rpar=100K +C3 N009 4 1p Rpar=1G +C4 N007 4 65n Rser=50 +D1 5 4 BIA +C5 7 4 1p Rpar=1G +A5 N006 4 N013 N013 N013 N013 4 N013 VARISTOR +D2 4 N006 F +G2 4 N006 1 N003 20 +G3 4 N006 N002 4 table(1.7 6.3m 10 7.2m) +R1 N013 N005 10Meg +G4 N002 4 N005 4 120µ +D3 N002 4 BIA +S1 4 1 N009 4 OV +A6 4 N002 N007 N007 N007 N007 4 N007 VARISTOR table(.5 0 10.5 10) +R2 1 N009 160K +R3 N009 4 20K +D4 7 N002 sTUB +.model PE PNP(Rb=100 BF=155 Cjc=1n Cje=1n VAF=3) +.model BIA D(Ron=100 Roff=1G Ilimit=3u) +.model F D(Ron=1m Roff=10K Vrev=30) +.model OV SW(Ron=1 Roff=1G Vt=.21 Vh=-5m level=2 ilimit=16m oneway) +.model STUB D(Ron=10m Roff=.1G) +.ends LT3020-1.8 +* +.subckt LT3020 1 2 3 4 5 6 7 +Q1 N003 N007 N002 0 PE temp=27 +R15 N003 1 1m +A2 4 N008 4 N010 4 4 N005 4 AND Tau=1u +A1 5 4 4 4 4 4 N010 4 SCHMITT Vt=.8 Vh=1m trise=1u +A3 7 4 4 4 4 4 N008 4 SCHMITT Vt=.92 Vh=1m Trise=1u +A4 4 N011 N013 4 4 4 N007 4 OTA Vhigh=11 G=2 Iout=1.2m Ref=-.2 +G1 4 N011 3 4 10µ +C2 N011 4 10p Rser=5K Rpar=100K +C3 3 4 1p Rpar=1G +C4 N007 4 65n Rser=50 +D1 5 4 BIA +C5 7 4 1p Rpar=1G +A5 N006 4 N013 N013 N013 N013 4 N013 VARISTOR +D2 4 N006 F +G2 4 N006 1 N003 20 +G3 4 N006 N002 4 table(1.7 6.3m 10 7.2m) +R1 N013 N005 10Meg +G4 N002 4 N005 4 120µ +D3 N002 4 BIA +S1 4 1 3 4 OV +A6 4 N002 N007 N007 N007 N007 4 N007 VARISTOR table(.5 0 10.5 10) +D4 7 N002 STUB +.model PE PNP(Rb=100 BF=155 Cjc=1n Cje=1n VAF=3) +.model BIA D(Ron=100 Roff=1G Ilimit=3u) +.model F D(Ron=1m Roff=10K Vrev=30) +.model OV SW(Ron=1 Roff=1G Vt=.21 Vh=-5m level=2 ilimit=16m oneway) +.model STUB D(Ron=10m Roff=.1G) +.ends LT3020 diff --git a/spice/copy/sub/LT3021.lib b/spice/copy/sub/LT3021.lib new file mode 100755 index 0000000..7e9ab25 --- /dev/null +++ b/spice/copy/sub/LT3021.lib @@ -0,0 +1,122 @@ +* Copyright © Linear Technology Corp. 2007. All rights reserved. +* +.subckt LT3021-1.2 1 2 3 4 5 6 7 8 9 10 11 12 +Q1 N002 N006 12 0 PE temp=27 +R15 N002 3 1m +A2 10 N007 10 N010 10 10 N004 10 AND Tau=1u +A1 9 10 10 10 10 10 N010 10 SCHMITT Vt=.8 Vh=1m trise=1u +A3 12 10 10 10 10 10 N007 10 SCHMITT Vt=.92 Vh=1m Trise=1u +A4 10 N011 N012 10 10 10 N006 10 OTA Vhigh=11 G=10 Iout=8m Ref=-.2 +G1 10 N011 N008 10 10µ +C2 N011 10 10p Rser=5K Rpar=100K +C3 N008 10 1p Rpar=1G +C4 N006 12 250n Rser=20 +D1 9 10 BIA +C5 12 10 1p Rpar=1G +A5 N005 10 N012 N012 N012 N012 10 N012 VARISTOR +D2 10 N005 F +G2 10 N005 3 N002 20 +G3 10 N005 12 10 table(1.7 28m 10 30m) +R1 N012 N004 10Meg +G4 12 10 N004 10 110µ +D3 12 10 BIA +S1 10 3 N008 10 OV +A6 10 12 N006 N006 N006 N006 10 N006 VARISTOR table(.5 0 10.5 10) +R5 3 7 .1m +R6 7 N008 100K +R7 N008 10 20K +.model PE PNP(Rb=100 BF=175 Cjc=1n Cje=1n VAF=3) +.model BIA D(Ron=100 Roff=1G Ilimit=3u) +.model F D(Ron=1m Roff=10K Vrev=30) +.model OV SW(Ron=1 Roff=1G Vt=.21 Vh=-5m level=2 ilimit=18m oneway) +.ends LT3021-1.2 +* +.subckt LT3021-1.5 1 2 3 4 5 6 7 8 9 10 11 12 +Q1 N002 N006 12 0 PE temp=27 +R15 N002 3 1m +A2 10 N007 10 N010 10 10 N004 10 AND Tau=1u +A1 9 10 10 10 10 10 N010 10 SCHMITT Vt=.8 Vh=1m trise=1u +A3 12 10 10 10 10 10 N007 10 SCHMITT Vt=.92 Vh=1m Trise=1u +A4 10 N011 N012 10 10 10 N006 10 OTA Vhigh=11 G=10 Iout=8m Ref=-.2 +G1 10 N011 N008 10 10µ +C2 N011 10 10p Rser=5K Rpar=100K +C3 N008 10 1p Rpar=1G +C4 N006 12 250n Rser=20 +D1 9 10 BIA +C5 12 10 1p Rpar=1G +A5 N005 10 N012 N012 N012 N012 10 N012 VARISTOR +D2 10 N005 F +G2 10 N005 3 N002 20 +G3 10 N005 12 10 table(1.7 28m 10 30m) +R1 N012 N004 10Meg +G4 12 10 N004 10 110µ +D3 12 10 BIA +S1 10 3 N008 10 OV +A6 10 12 N006 N006 N006 N006 10 N006 VARISTOR table(.5 0 10.5 10) +R5 3 7 .1m +R6 7 N008 130K +R7 N008 10 20K +.model PE PNP(Rb=100 BF=175 Cjc=1n Cje=1n VAF=3) +.model BIA D(Ron=100 Roff=1G Ilimit=3u) +.model F D(Ron=1m Roff=10K Vrev=30) +.model OV SW(Ron=1 Roff=1G Vt=.21 Vh=-5m level=2 ilimit=18m oneway) +.ends LT3021-1.5 +* +.subckt LT3021-1.8 1 2 3 4 5 6 7 8 9 10 11 12 +Q1 N002 N006 12 0 PE temp=27 +R15 N002 3 1m +A2 10 N007 10 N010 10 10 N004 10 AND Tau=1u +A1 9 10 10 10 10 10 N010 10 SCHMITT Vt=.8 Vh=1m trise=1u +A3 12 10 10 10 10 10 N007 10 SCHMITT Vt=.92 Vh=1m Trise=1u +A4 10 N011 N012 10 10 10 N006 10 OTA Vhigh=11 G=10 Iout=8m Ref=-.2 +G1 10 N011 N008 10 10µ +C2 N011 10 10p Rser=5K Rpar=100K +C3 N008 10 1p Rpar=1G +C4 N006 12 250n Rser=20 +D1 9 10 BIA +C5 12 10 1p Rpar=1G +A5 N005 10 N012 N012 N012 N012 10 N012 VARISTOR +D2 10 N005 F +G2 10 N005 3 N002 20 +G3 10 N005 12 10 table(1.7 28m 10 30m) +R1 N012 N004 10Meg +G4 12 10 N004 10 110µ +D3 12 10 BIA +S1 10 3 N008 10 OV +A6 10 12 N006 N006 N006 N006 10 N006 VARISTOR table(.5 0 10.5 10) +R5 3 7 .1m +R6 7 N008 160K +R7 N008 10 20K +.model PE PNP(Rb=100 BF=175 Cjc=1n Cje=1n VAF=3) +.model BIA D(Ron=100 Roff=1G Ilimit=3u) +.model F D(Ron=1m Roff=10K Vrev=30) +.model OV SW(Ron=1 Roff=1G Vt=.21 Vh=-5m level=2 ilimit=18m oneway) +.ends LT3021-1.8 +* +.subckt LT3021 1 2 3 4 5 6 7 8 9 10 11 12 +Q1 N002 N006 12 0 PE temp=27 +R15 N002 3 1m +A2 10 N007 10 N008 10 10 N004 10 AND Tau=1u +A1 9 10 10 10 10 10 N008 10 SCHMITT Vt=.8 Vh=1m trise=1u +A3 12 10 10 10 10 10 N007 10 SCHMITT Vt=.92 Vh=1m Trise=1u +A4 10 N009 N011 10 10 10 N006 10 OTA Vhigh=11 G=10 Iout=8m Ref=-.2 +G1 10 N009 7 10 10µ +C2 N009 10 10p Rser=5K Rpar=100K +C3 7 10 1p Rpar=1G +C4 N006 12 250n Rser=20 +D1 9 10 BIA +C5 12 10 1p Rpar=1G +A5 N005 10 N011 N011 N011 N011 10 N011 VARISTOR +D2 10 N005 F +G2 10 N005 3 N002 20 +G3 10 N005 12 10 table(1.7 28m 10 30m) +R1 N011 N004 10Meg +G4 12 10 N004 10 110µ +D3 12 10 BIA +S1 10 3 7 10 OV +A6 10 12 N006 N006 N006 N006 10 N006 VARISTOR table(.5 0 10.5 10) +.model PE PNP(Rb=100 BF=175 Cjc=1n Cje=1n VAF=3) +.model BIA D(Ron=100 Roff=1G Ilimit=3u) +.model F D(Ron=1m Roff=10K Vrev=30) +.model OV SW(Ron=1 Roff=1G Vt=.21 Vh=-5m level=2 ilimit=18m oneway) +.ends LT3021 diff --git a/spice/copy/sub/LT3022.sub b/spice/copy/sub/LT3022.sub new file mode 100755 index 0000000..cea793a Binary files /dev/null and b/spice/copy/sub/LT3022.sub differ diff --git a/spice/copy/sub/LT3023.lib b/spice/copy/sub/LT3023.lib new file mode 100755 index 0000000..56bfada --- /dev/null +++ b/spice/copy/sub/LT3023.lib @@ -0,0 +1,66 @@ +* Copyright © Linear Technology Corp. 2004. All rights reserved. +* +.subckt LT3023 1 2 3 4 5 6 7 8 9 10 +Q1 N006 N004 8 0 PN +Q2 N004 N008 3 0 NA +Q3 N008 N003 N010 0 NP temp=27 +C1 N008 N003 12p Rser=350K +Q4 N003 N003 5 0 NP 10 temp=27 +R2 5 3 12K +R3 N010 3 10K +C2 6 N003 15p +Q5 6 4 N009 0 FB temp=27 +R6 N009 5 106.8K +R5 7 3 20Meg +I1 7 3 1µ load +A1 7 3 3 3 3 3 N002 3 SCHMITT Vt=.8 Vh=1m trise=1m +G2 8 N003 N002 3 1.2µ +G1 8 N008 N002 3 1.2µ +R1 8 N004 600K +R8 N006 6 1.17 +A2 N005 3 N008 N008 N008 N008 3 N008 VARISTOR +D3 3 N005 F +G3 3 N005 6 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 8 6 X +C5 6 3 10p +C7 8 3 10p +C8 5 3 1p +G4 3 N005 8 3 table(1.3 1m 2.4 3m 10 4m) +G5 N005 3 N002 3 table(0 3m 1 0) +C4 8 N003 100p Rser=.67G Rpar=6G +Q6 N017 N015 8 0 PN +Q8 N015 N019 3 0 NA +Q9 N019 N014 N021 0 NP temp=27 +C6 N019 N014 12p Rser=350K +Q10 N014 N014 1 0 NP 10 temp=27 +R4 1 3 12K +R11 N021 3 10K +C9 10 N014 15p +Q11 10 2 N020 0 FB temp=27 +R12 N020 1 106.8K +R13 9 3 20Meg +I2 9 3 1µ load +A3 9 3 3 3 3 3 N012 3 SCHMITT Vt=.8 Vh=1m trise=1m +G6 8 N014 N012 3 1.2µ +G7 8 N019 N012 3 1.2µ +R14 8 N015 600K +R15 N017 10 1.17 +A4 N016 3 N019 N019 N019 N019 3 N019 VARISTOR +D2 3 N016 F +G8 3 N016 10 N017 10m +Q12 N014 N015 N017 0 P 1m +D4 8 10 X +C11 10 3 10p +C13 1 3 1p +G9 3 N016 8 3 table(1.3 1m 2.4 3m 10 4m) +G10 N016 3 N012 3 table(0 3m 1 0) +C14 8 N014 100p Rser=.67G Rpar=6G +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT3023 diff --git a/spice/copy/sub/LT3024.lib b/spice/copy/sub/LT3024.lib new file mode 100755 index 0000000..5747956 --- /dev/null +++ b/spice/copy/sub/LT3024.lib @@ -0,0 +1,67 @@ +* Copyright © Linear Technology Corp. 2004. All rights reserved. +* +.subckt LT3024 1 2 3 4 5 6 7 8 9 10 11 12 +Q1 N006 N004 9 0 PN +Q2 N004 N008 4 0 NA1 +Q3 N008 N003 N010 0 NP temp=27 +C1 N008 N003 27p Rser=225K +Q4 N003 N003 1 0 NP 10 temp=27 +R2 1 4 12K +R3 N010 4 10K +C2 2 N003 15p +Q5 2 12 N009 0 FB temp=27 +R6 N009 1 106.8K +R5 11 4 10Meg +I1 11 4 1µ load +A1 11 4 4 4 4 4 N002 4 SCHMITT Vt=.75 Vh=1m trise=1m +G2 9 N003 N002 4 1.2µ +G1 9 N008 N002 4 1.2µ +R1 9 N004 600K +R8 N006 2 .1 +A2 N005 4 N008 N008 N008 N008 4 N008 VARISTOR +D3 4 N005 F +G3 4 N005 2 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 9 2 X +C5 2 4 10p +C7 9 4 10p +C8 1 4 1p +G5 N005 4 N002 4 table(0 1.85m 1 0) +C4 9 N003 100p Rser=45G Rpar=6G +Q6 N017 N015 9 0 PN +Q8 N015 N019 4 0 NA +Q9 N019 N014 N021 0 NP temp=27 +C6 N019 N014 12p Rser=350K +Q10 N014 N014 6 0 NP 10 temp=27 +R4 6 4 12K +R11 N021 4 10K +C9 5 N014 15p +Q11 5 7 N020 0 FB temp=27 +R12 N020 6 106.8K +R13 8 4 20Meg +I2 8 4 1µ load +A3 8 4 4 4 4 4 N012 4 SCHMITT Vt=.8 Vh=1m trise=1m +G6 9 N014 N012 4 1.2µ +G7 9 N019 N012 4 1.2µ +R14 9 N015 600K +R15 N017 5 1.17 +A4 N016 4 N019 N019 N019 N019 4 N019 VARISTOR +D2 4 N016 F +G8 4 N016 5 N017 10m +Q12 N014 N015 N017 0 P 1m +D4 9 5 X +C11 5 4 10p +C13 6 4 1p +G9 4 N016 9 4 table(1.3 1m 2.4 3m 10 4m) +G10 N016 4 N012 4 table(0 3m 1 0) +C14 9 N014 100p Rser=.67G Rpar=6G +G4 4 N005 9 4 table(1.3 1m 2.4 1.85m 10 2.3m) +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model NA1 NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.ends LT3024 diff --git a/spice/copy/sub/LT3027.lib b/spice/copy/sub/LT3027.lib new file mode 100755 index 0000000..7d19188 --- /dev/null +++ b/spice/copy/sub/LT3027.lib @@ -0,0 +1,71 @@ +* Copyright © Linear Technology Corp. 2004. All rights reserved. +* +.subckt LT3027 1 2 3 4 5 6 7 8 9 10 11 +Q1 N003 N006 8 0 PN +Q2 N006 N009 11 0 NA +Q3 N009 N005 N011 0 NP temp=27 +C1 N009 N005 12p Rser=350K +Q4 N005 N005 5 0 NP 10 temp=27 +R2 5 11 12K +R3 N011 11 10K +C2 6 N005 15p +Q5 6 4 N010 0 FB temp=27 +R6 N010 5 106.8K +R5 7 11 20Meg +I1 7 11 1µ load +A1 7 11 11 11 11 11 N002 11 SCHMITT Vt=.8 Vh=1m trise=1m +G2 8 N005 N002 11 1.2µ +G1 8 N009 N002 11 1.2µ +R1 8 N006 600K +R8 N003 6 .117 +A2 N007 11 N009 N009 N009 N009 11 N009 VARISTOR +D3 11 N007 F +G3 11 N007 6 N003 100m +Q7 N005 N006 N003 0 P 1m +D1 8 6 X +C5 6 11 10p +C7 8 11 10p +C8 5 11 1p +G4 11 N007 8 11 table(1.3 1m 2.4 3m 10 4m) +G5 N007 11 N002 11 table(0 3m 1 0) +C4 8 N005 100p Rser=.67G Rpar=6G +Q6 N016 N019 9 0 PN +Q8 N019 N022 11 0 NA +Q9 N022 N018 N024 0 NP temp=27 +C6 N022 N018 12p Rser=350K +Q10 N018 N018 1 0 NP 10 temp=27 +R4 1 11 12K +R11 N024 11 10K +C9 10 N018 15p +Q11 10 2 N023 0 FB temp=27 +R12 N023 1 106.8K +R13 3 11 20Meg +I2 3 11 1µ load +A3 3 11 11 11 11 11 N014 11 SCHMITT Vt=.8 Vh=1m trise=10n +G6 9 N018 N014 11 1.2µ +G7 9 N022 N014 11 1.2µ +R14 9 N019 600K +R15 N016 10 1.17 +A4 N020 11 N022 N022 N022 N022 11 N022 VARISTOR +D2 11 N020 F +G8 11 N020 10 N016 10m +Q12 N018 N019 N016 0 P 1m +D4 9 10 X +C11 10 11 10p +C13 1 11 1p +G9 11 N020 9 11 table(1.3 1m 2.4 3m 10 4m) +G10 N020 11 N014 11 table(0 3m 1 0) +C14 9 N018 100p Rser=.67G Rpar=6G +C12 9 11 10p +G11 N007 11 N004 11 table(0 0 1 3m) +A5 N003 8 11 11 11 11 N004 11 SCHMITT Vt=10m Vh=1m +G12 N020 11 N017 11 table(0 0 1 3m) +A6 N016 9 11 11 11 11 N017 11 SCHMITT Vt=10m Vh=1m +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=600K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.ends LT3027 diff --git a/spice/copy/sub/LT3028.lib b/spice/copy/sub/LT3028.lib new file mode 100755 index 0000000..3efb9c6 --- /dev/null +++ b/spice/copy/sub/LT3028.lib @@ -0,0 +1,68 @@ +* Copyright © Linear Technology Corp. 2004. All rights reserved. +* +.subckt LT3028 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +Q1 N006 N004 13 0 PN +Q2 N004 N008 5 0 NA1 +Q3 N008 N003 N010 0 NP temp=27 +C1 N008 N003 27p Rser=225K +Q4 N003 N003 1 0 NP 10 temp=27 +R2 1 5 12K +R3 N010 5 10K +C2 3 N003 15p +Q5 3 16 N009 0 FB temp=27 +R6 N009 1 106.8K +R5 15 5 10Meg +I1 15 5 1µ load +A1 15 5 5 5 5 5 N002 5 SCHMITT Vt=.75 Vh=1m trise=1m +G2 13 N003 N002 5 1.2µ +G1 13 N008 N002 5 1.2µ +R1 13 N004 600K +R8 N006 3 .1 +A2 N005 5 N008 N008 N008 N008 5 N008 VARISTOR +D3 5 N005 F +G3 5 N005 3 N006 10m +Q7 N003 N004 N006 0 P 1m +D1 13 3 X +C5 3 5 10p +C7 13 5 10p +C8 1 5 1p +G5 N005 5 N002 5 table(0 1.85m 1 0) +C4 13 N003 100p Rser=45G Rpar=6G +Q6 N018 N016 11 0 PN +Q8 N016 N020 5 0 NA +Q9 N020 N015 N022 0 NP temp=27 +C6 N020 N015 12p Rser=350K +Q10 N015 N015 8 0 NP 10 temp=27 +R4 8 5 12K +R11 N022 5 10K +C9 6 N015 15p +Q11 6 9 N021 0 FB temp=27 +R12 N021 8 106.8K +R13 10 5 20Meg +I2 10 5 1µ load +A3 10 5 5 5 5 5 N013 5 SCHMITT Vt=.8 Vh=1m trise=1m +G6 11 N015 N013 5 1.2µ +G7 11 N020 N013 5 1.2µ +R14 11 N016 600K +R15 N018 6 1.17 +A4 N017 5 N020 N020 N020 N020 5 N020 VARISTOR +D2 5 N017 F +G8 5 N017 6 N018 10m +Q12 N015 N016 N018 0 P 1m +D4 11 6 X +C11 6 5 10p +C13 8 5 1p +G9 5 N017 11 5 table(1.3 1m 2.4 3m 10 4m) +G10 N017 5 N013 5 table(0 3m 1 0) +C14 11 N015 100p Rser=.67G Rpar=6G +G4 5 N005 13 5 table(1.3 1m 2.4 1.85m 10 2.3m) +C12 11 5 10p +.model PN PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model NA NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model NP NPN(Cje=1p Cjc=1p BF=150) +.model FB NPN(Cje=5p Cjc=5p BF=150) +.model F D(Ron=1m Roff=10K) +.model P PNP(BF=100) +.model X D(Ron=10 Vfwd=30) +.model NA1 NPN(BF=650K Cje=.5p Cjc=.5p Re=10) +.ends LT3028 diff --git a/spice/copy/sub/LT3032.lib b/spice/copy/sub/LT3032.lib new file mode 100755 index 0000000..c8c7a38 --- /dev/null +++ b/spice/copy/sub/LT3032.lib @@ -0,0 +1,161 @@ +* Copyright © Linear Technology Corp. 2011. All rights reserved. +* +.subckt LT3032-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +Q2 N018 N016 N024 0 NAx +Q3 N016 N019 N027 0 Nx temp=27 +C1 N016 N019 18p Rser=40K +Q4 N019 N019 N028 0 Nx 10 temp=27 +R2 N028 6 12K +R3 N027 6 10K +Q1 N028 N007 N017 0 Px temp=27 +R6 4 N017 121.5K +R8 N024 6 1K +Q5 N018 N018 N015 0 Px +Q6 N026 N018 4 0 Px 6 +R1 N026 6 450K +R9 4 N015 4K +Q7 N023 N026 6 0 NPx +R7 7 N023 .7 +Q8 6 N023 N016 0 Px 4.5 +G1 4 N016 11 4 80µ +R5 4 11 5K +A1 4 10 0 0 0 0 N006 0 SCHMITT Vt=1.9 Vh=10m Rhigh=1 Rlow=1K +A2 10 4 0 0 0 0 N006 0 SCHMITT Vt=1.4 Vh=10m Rhigh=1 Rlow=1K +G2 4 N016 N006 0 1.2µ +G3 4 N019 N006 0 1.2µ +C4 0 N006 .1µ +R4 10 4 5Meg +A3 0 N003 N016 N016 N016 N016 6 N016 VARISTOR +G4 0 N003 N023 7 10m +G6 0 N003 7 6 table( 7 4.3m 10 2.5m 20 1.5m) +C6 4 7 10p +C7 4 6 10p +D1 0 N003 Xx +C2 4 N019 500p Rser=.21G Rpar=6G +Q9 N012 N010 14 0 PNy temp=27 +Q10 N010 N008 4 0 NAy +Q11 N008 N009 N025 0 NPy temp=27 +C8 N008 N009 12p Rser=250K +Q12 N009 N009 3 0 NPy 10 temp=27 +R10 3 4 12K +R12 N025 4 10K +C9 1 N009 15p +Q13 1 N021 N022 0 FBy temp=27 +R13 N022 3 106.8K +R14 12 4 20Meg +I1 12 4 1µ load +G5 14 N009 N005 4 1.2µ +G7 14 N008 N005 4 1.2µ +R15 14 N010 600K +R16 N012 1 .66 +A4 N011 0 N008 N008 N008 N008 4 N008 VARISTOR +D2 0 N011 Fy +G8 0 N011 1 N012 10m +Q14 N009 N010 N012 0 Py 1m +D3 14 1 Xy +C11 1 4 10p +C12 14 4 10p +C13 3 4 1p +G9 0 N011 14 0 table(1.3 1m 2.4 2.1m 10 3.2m) +G10 N011 0 N005 4 table(0 2.1m 1 0) +C14 14 N008 .3p Rser=.8G +A5 12 4 4 4 4 4 N005 4 SCHMITT Vt=.8 Vh=1m trise=2m +C16 14 N009 100p Rser=.67G Rpar=6G +S1 0 N003 0 N006 SSx +R18 N007 4 240K +R19 7 N007 744K +R20 N021 4 244K +R21 1 N021 753K +.model Nx NPN(Cje=5p Cjc=5p BF=150) +.model Px PNP(Cje=5p Cjc=5p BF=150) +.model NAx NPN(Cje=1p Cjc=1p BF=8K) +.model NPx NPN(Cje=50p Cjc=50p BF=50) +.model Xx D(Ron=1 Roff=1K) +.model SSx SW(Ron=1 Roff=1G Vt=-.95 Vh=-25m) +.model Py PNP(BF=100) +.model NPy NPN(Cje=1p Cjc=1p BF=150) +.model NAy NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model PNy PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model FBy NPN(Cje=5p Cjc=5p BF=150) +.model Fy D(Ron=1m Roff=10K) +.model Xy D(Ron=10 Vfwd=30) +.ends LT3032-5 +* +.subckt LT3032 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +Q2 N017 N015 N021 0 NA +Q3 N015 N018 N024 0 N temp=27 +C1 N015 N018 18p Rser=40K +Q4 N018 N018 N025 0 N 10 temp=27 +R2 N025 6 12K +R3 N024 6 10K +Q1 N025 8 N016 0 P temp=27 +R6 4 N016 121.5K +R8 N021 6 1K +Q5 N017 N017 N014 0 P +Q6 N023 N017 4 0 P 6 +R1 N023 6 450K +R9 4 N014 4K +Q7 N020 N023 6 0 NP +R7 7 N020 .7 +Q8 6 N020 N015 0 P 4.5 +G1 4 N015 11 4 80µ +R5 4 11 5K +A1 4 10 0 0 0 0 N005 0 SCHMITT Vt=1.9 Vh=10m Rhigh=1 Rlow=1K +A2 10 4 0 0 0 0 N005 0 SCHMITT Vt=1.4 Vh=10m Rhigh=1 Rlow=1K +G2 4 N015 N005 0 1.2µ +G3 4 N018 N005 0 1.2µ +C4 0 N005 .1µ +R4 10 4 5Meg +A3 0 N002 N015 N015 N015 N015 6 N015 VARISTOR +G4 0 N002 N020 7 10m +G6 0 N002 7 6 table( 7 4.3m 10 2.5m 20 1.5m) +C5 4 8 1p +C6 4 7 10p +C7 4 6 10p +D1 0 N002 X +C2 4 N018 500p Rser=.21G Rpar=6G +Q9 N011 N009 14 0 PN_ temp=27 +Q10 N009 N007 4 0 NA_ +Q11 N007 N008 N022 0 NP_ temp=27 +C8 N007 N008 12p Rser=250K +Q12 N008 N008 3 0 NP_ 10 temp=27 +R10 3 4 12K +R12 N022 4 10K +C9 1 N008 15p +Q13 1 2 N019 0 FB_ temp=27 +R13 N019 3 106.8K +R14 12 4 20Meg +I1 12 4 1µ load +G5 14 N008 N004 4 1.2µ +G7 14 N007 N004 4 1.2µ +R15 14 N009 600K +R16 N011 1 .66 +A4 N010 0 N007 N007 N007 N007 4 N007 VARISTOR +D2 0 N010 F_ +G8 0 N010 1 N011 10m +Q14 N008 N009 N011 0 P_ 1m +D3 14 1 X_ +C11 1 4 10p +C12 14 4 10p +C13 3 4 1p +G9 0 N010 14 0 table(1.3 1m 2.4 2.1m 10 3.2m) +G10 N010 0 N004 4 table(0 2.1m 1 0) +C14 14 N007 .3p Rser=.8G +A5 12 4 4 4 4 4 N004 4 SCHMITT Vt=.8 Vh=1m trise=2m +C15 2 4 1p +C16 14 N008 100p Rser=.67G Rpar=6G +S1 0 N002 0 N005 SS +.model N NPN(Cje=5p Cjc=5p BF=150) +.model P PNP(Cje=5p Cjc=5p BF=150) +.model NA NPN(Cje=1p Cjc=1p BF=8K) +.model NP NPN(Cje=50p Cjc=50p BF=50) +.model X D(Ron=1 Roff=1K) +.model SS SW(Ron=1 Roff=1G Vt=-.95 Vh=-25m) +.model P_ PNP(BF=100) +.model NP_ NPN(Cje=1p Cjc=1p BF=150) +.model NA_ NPN(BF=500K Cje=.5p Cjc=.5p Re=40) +.model PN_ PNP(BF=25 Cje=150p Cjc=150p Tf=10n) +.model FB_ NPN(Cje=5p Cjc=5p BF=150) +.model F_ D(Ron=1m Roff=10K) +.model X_ D(Ron=10 Vfwd=30) +.ends LT3032 diff --git a/spice/copy/sub/LT3033.sub b/spice/copy/sub/LT3033.sub new file mode 100755 index 0000000..b845705 --- /dev/null +++ b/spice/copy/sub/LT3033.sub @@ -0,0 +1,6 @@ + + + +Aeõͦ¯û"˜“çõÊý Õÿð@%vÂa;úÉ_%³VÁ¨Ì¡åè;džûŸ*bDê^¬á$"Ù¶êxÇÄÚÓÏ…å”Âú‡•‡eL¡ß§#¸Ý#åÝ Íï+Á”ü‡A°‘÷µÝ.Úåãå.ܬKNˆžPÅìd´ðª¥ÝéNðž¯.Å\Q8ÖÙ žæ×ZÝ”ÄûÚ~Lm©õŠ}¤…ÔÊܲ¬êÆàÏГãUšá÷¼9öeîh›Ý¦/¶>!mŒuDÏè}Óv~”—Ø,Þ³v[³ˆ=%ªjÃPÑ—Ò áÛûæÖæðÜtëÌáö^«ìŸ››¾YXªL&ùìbS¹ïˆÛØŒB6œß¥²ëdЬô™yõÔó«2‡Yxï‘l°‚¥nfÊíü»Îþ•¬ï…ªÔ»I¨¥;_ •{¦éê­1« ¡°¦7Çø c‰y‹š4#ÕDà·â߇Xaº¨êá±Ð¡#FÐO*£ÅH{¦˜•‰ÔKŸAêÍéáÃ)”Éúù*‡ñqÓ×ÅÓœ‹ ?ü{MÏælšiK¶?†Ü.¨ŒM^1Ò€i¬£@Æð‡‘úFÇ–³]¬5¤êáË™ ýJˆÜY[÷ù¯¡¡mÿšŸçåÆ‘ëDS϶$Ò9âñà­¼´°]Q–ê<Ÿ±ÎúqvDÉÙZ 'ÏÁ!ƒõȹFþçAaºuüÚzè ˜hÄçñÞ¸ ½3Óf¨÷¢Àš>ª“üÕR˜Ç»²Î>øb’®´jC†Y·Ü?•“êÔÿÕ·þ€ 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b/spice/copy/sub/LT3063.lib @@ -0,0 +1,37 @@ +* Copyright (c) 1998-2014 Linear Technology Corporation. All rights reserved. +* +.subckt LT3063 1 2 3 4 5 6 7 8 +C2 7 8 2p Rpar=50Meg +A1 7 8 8 8 8 8 N007 8 SCHMITT Vt=.75 Vh=50m Trise=30n +A2 5 8 8 8 8 8 N004 8 SCHMITT Vt=1.19 Vh=5m Trise=30n +A3 8 N004 8 N007 8 N008 RN 8 AND Trise=30n Vhigh=.6 +R1 RN 1 100K +C3 1 8 .2p Rpar=1G +S1 1 8 8 RN SDN +A4 2 1 N011 8 8 8 N010 8 OTA G=100m asym Rout=10Meg Cout=20p Isource=50u Isink=-10u +Q1 3 N006 N002 0 PAS +Q2 N006 N010 8 0 NDR +C5 5 8 20p Rpar=50Meg +C6 3 8 10p Rpar=.1G +C7 2 8 .2p Rpar=1G +R5 5 N002 9m +R6 N005 8 100K +G1 8 N005 5 N002 1.111m +G2 8 N012 5 3 table( 7 3.1u 45 2u) +C8 N012 8 100p Rpar=100K +A5 N005 N012 8 8 8 8 N011 8 OTA g=20m Cout=2p Vlow=0 Ref=0 Rout=10Meg Vhigh=1 +C9 N010 8 3500p Rser=250 +M1 N019 N020 8 8 DISC temp=27 +R4 3 N019 10 +A6 N015 N018 N016 8 8 8 N020 8 OTA G=.1u Rout=10Meg linear Vhigh=2 +D1 N020 3 GEN +A7 3 8 8 8 8 8 N015 8 SCHMITT Vt=6.2 Vh=.1 Tau=5u Vhigh=0 Vlow=-2 +A8 N014 8 N018 8 RN 8 N016 8 DFLOP Trise=20n +A9 2 8 8 8 8 8 N014 8 SCHMITT Vt=.2 Vh=50m +A10 N008 8 8 8 8 8 N018 8 BUF Trise=.1u +.model GEN D(Ron=100 Roff=10G Vfwd=.35) +.model SDN SW(Ron=100 Roff=10G Vt=-.3 Vh=-.1) +.model PAS PNP(Bf=60 Rb=2 Re=.85 Cje=2p Cjc=2p) +.model NDR NPN(Bf=100 Cje=.1p Cjc=.1p Re=25 Rb=10) +.model DISC VDMOS(Kp=.4 Vto=.5 Rs=.2 Rd=10) +.ends LT3063 diff --git a/spice/copy/sub/LT3065.sub b/spice/copy/sub/LT3065.sub new file mode 100755 index 0000000..1159843 Binary files /dev/null and b/spice/copy/sub/LT3065.sub differ diff --git a/spice/copy/sub/LT3066.sub b/spice/copy/sub/LT3066.sub new file mode 100755 index 0000000..bcf52a0 Binary files /dev/null and b/spice/copy/sub/LT3066.sub differ diff --git a/spice/copy/sub/LT3070-1.sub b/spice/copy/sub/LT3070-1.sub new file mode 100755 index 0000000..5c4b486 Binary files /dev/null and b/spice/copy/sub/LT3070-1.sub differ diff --git a/spice/copy/sub/LT3070.sub b/spice/copy/sub/LT3070.sub new file mode 100755 index 0000000..9a6885a Binary files /dev/null and b/spice/copy/sub/LT3070.sub differ diff --git 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b/spice/copy/sub/LT4356-1.sub new file mode 100755 index 0000000..2f1ec70 Binary files /dev/null and b/spice/copy/sub/LT4356-1.sub differ diff --git a/spice/copy/sub/LT4356-2.sub b/spice/copy/sub/LT4356-2.sub new file mode 100755 index 0000000..3a30f48 Binary files /dev/null and b/spice/copy/sub/LT4356-2.sub differ diff --git a/spice/copy/sub/LT4356-3.sub b/spice/copy/sub/LT4356-3.sub new file mode 100755 index 0000000..76096f5 Binary files /dev/null and b/spice/copy/sub/LT4356-3.sub differ diff --git a/spice/copy/sub/LT4363-1.sub b/spice/copy/sub/LT4363-1.sub new file mode 100755 index 0000000..5736b4c Binary files /dev/null and b/spice/copy/sub/LT4363-1.sub differ diff --git a/spice/copy/sub/LT4363-2.sub b/spice/copy/sub/LT4363-2.sub new file mode 100755 index 0000000..994ca36 Binary files /dev/null and b/spice/copy/sub/LT4363-2.sub differ diff --git a/spice/copy/sub/LT4430.sub b/spice/copy/sub/LT4430.sub new file mode 100755 index 0000000..56a6702 Binary files /dev/null and b/spice/copy/sub/LT4430.sub differ diff --git a/spice/copy/sub/LT5400.lib b/spice/copy/sub/LT5400.lib new file mode 100755 index 0000000..cdc3aa6 --- /dev/null +++ b/spice/copy/sub/LT5400.lib @@ -0,0 +1,193 @@ +* Copyright © Analog Devices, Inc. 2019. All rights reserved. +* +.subckt LT5400-1 1 2 3 4 5 6 7 8 9 +R1 8 1 10K +R2 7 2 10K +R3 6 3 10K +R4 5 4 10K +C1 1 9 2.75p +C3 2 9 2.75p +C4 3 9 2.75p +C5 4 9 2.75p +C6 8 9 2.75p +C7 7 9 2.75p +C8 6 9 2.75p +C9 5 9 2.75p +C10 1 2 .7p +C11 2 3 .7p +C12 3 4 .7p +C13 8 7 .7p +C14 7 6 .7p +C15 6 5 .7p +.ends LT5400-1 +* +.subckt LT5400-2 1 2 3 4 5 6 7 8 9 +C1 1 9 2.75p +C2 2 9 2.75p +C3 3 9 2.75p +C4 4 9 2.75p +C5 8 9 2.75p +C6 7 9 2.75p +C7 6 9 2.75p +C8 5 9 2.75p +C9 1 2 .7p +C10 2 3 .7p +C11 3 4 .7p +C12 8 7 .7p +C13 7 6 .7p +C14 6 5 .7p +R1 8 1 100K +R2 7 2 100K +R3 6 3 100K +R4 5 4 100K +.ends LT5400-2 +* +.subckt LT5400-3 1 2 3 4 5 6 7 8 9 +R1 8 1 100K +R2 7 2 10K +R3 6 3 10K +R4 5 4 100K +C1 1 9 2.75p +C2 2 9 2.75p +C3 3 9 2.75p +C4 4 9 2.75p +C5 8 9 2.75p +C6 7 9 2.75p +C7 6 9 2.75p +C8 5 9 2.75p +C9 1 2 .7p +C10 2 3 .7p +C11 3 4 .7p +C12 8 7 .7p +C13 7 6 .7p +C14 6 5 .7p +.ends LT5400-3 +* +.subckt LT5400-4 1 2 3 4 5 6 7 8 9 +R1 8 1 1K +R2 7 2 1K +R3 6 3 1K +R4 5 4 1K +C1 1 9 2.75p +C2 2 9 2.75p +C3 3 9 2.75p +C4 4 9 2.75p +C5 8 9 2.75p +C6 7 9 2.75p +C7 6 9 2.75p +C8 5 9 2.75p +C9 1 2 .7p +C10 2 3 .7p +C11 3 4 .7p +C12 8 7 .7p +C13 7 6 .7p +C14 6 5 .7p +.ends LT5400-4 +* +.subckt LT5400-5 1 2 3 4 5 6 7 8 9 +R1 8 1 1Meg +R2 7 2 1Meg +R3 6 3 1Meg +R4 5 4 1Meg +C1 1 9 2.75p +C2 2 9 2.75p +C3 3 9 2.75p +C4 4 9 2.75p +C5 8 9 2.75p +C6 7 9 2.75p +C7 6 9 2.75p +C8 5 9 2.75p +C9 1 2 .7p +C10 2 3 .7p +C11 3 4 .7p +C12 8 7 .7p +C13 7 6 .7p +C14 6 5 .7p +.ends LT5400-5 +* +.subckt LT5400-6 1 2 3 4 5 6 7 8 9 +R1 8 1 5K +R2 7 2 1K +R3 6 3 1K +R4 5 4 5K +C1 1 9 2.75p +C2 2 9 2.75p +C3 3 9 2.75p +C4 4 9 2.75p +C5 8 9 2.75p +C6 7 9 2.75p +C7 6 9 2.75p +C8 5 9 2.75p +C9 1 2 .7p +C10 2 3 .7p +C11 3 4 .7p +C12 8 7 .7p +C13 7 6 .7p +C14 6 5 .7p +.ends LT5400-6 +* +.subckt LT5400-7 1 2 3 4 5 6 7 8 9 +R1 8 1 5K +R2 7 2 1.25K +R3 6 3 1.25K +R4 5 4 5K +C1 1 9 2.75p +C2 2 9 2.75p +C3 3 9 2.75p +C4 4 9 2.75p +C5 8 9 2.75p +C6 7 9 2.75p +C7 6 9 2.75p +C8 5 9 2.75p +C9 1 2 .7p +C10 2 3 .7p +C11 3 4 .7p +C12 8 7 .7p +C13 7 6 .7p +C14 6 5 .7p +.ends LT5400-7 +* +.subckt LT5400-8 1 2 3 4 5 6 7 8 9 +R1 8 1 9K +R2 7 2 1K +R3 6 3 1K +R4 5 4 9K +C1 1 9 2.75p +C2 2 9 2.75p +C3 3 9 2.75p +C4 4 9 2.75p +C5 8 9 2.75p +C6 7 9 2.75p +C7 6 9 2.75p +C8 5 9 2.75p +C9 1 2 .7p +C10 2 3 .7p +C11 3 4 .7p +C12 8 7 .7p +C13 7 6 .7p +C14 6 5 .7p +.ends LT5400-8 +* +.subckt LT5401 1 2 3 4 5 6 7 8 9 10 11 +D1 1 11 ESD +C3 5 11 3.4p +C4 4 11 3.4p +C5 3 11 3.4p +C6 2 11 3.4p +C7 9 11 3.4p +C8 6 11 3.4p +C9 7 11 3.4p +C10 8 11 3.4p +C11 5 1 .5p Rpar=700 +C12 4 5 .5p Rpar=350 +C13 3 4 .5p Rpar=350 +C15 6 10 .5p Rpar=700 +C16 7 6 .5p Rpar=350 +C17 8 7 .5p Rpar=350 +C14 2 3 .5p Rpar=700 +C18 9 8 .5p Rpar=700 +C1 1 11 3.4p +C2 10 11 3.4p +D2 10 11 ESD +.model ESD D(Ron=1 Roff=1T epsilon=1 revepsilon=1 Vfwd=37 Vrev=37) +.ends LT5401 diff --git a/spice/copy/sub/LT6372-0.2.sub b/spice/copy/sub/LT6372-0.2.sub new file mode 100755 index 0000000..c7710f6 Binary files /dev/null and b/spice/copy/sub/LT6372-0.2.sub differ diff --git a/spice/copy/sub/LT6600-10.sub b/spice/copy/sub/LT6600-10.sub new file mode 100755 index 0000000..4ac9eb7 Binary files /dev/null and b/spice/copy/sub/LT6600-10.sub differ diff --git a/spice/copy/sub/LT6600-15.sub b/spice/copy/sub/LT6600-15.sub new file mode 100755 index 0000000..36dc8a4 Binary files /dev/null and b/spice/copy/sub/LT6600-15.sub differ diff --git a/spice/copy/sub/LT6600-2.5.sub b/spice/copy/sub/LT6600-2.5.sub new file mode 100755 index 0000000..84d20cb Binary files /dev/null and b/spice/copy/sub/LT6600-2.5.sub differ diff --git a/spice/copy/sub/LT6600-20.sub b/spice/copy/sub/LT6600-20.sub new file mode 100755 index 0000000..6040ac9 Binary files /dev/null and b/spice/copy/sub/LT6600-20.sub differ diff --git a/spice/copy/sub/LT6600-5.sub b/spice/copy/sub/LT6600-5.sub new file mode 100755 index 0000000..c2ce1eb Binary files /dev/null and b/spice/copy/sub/LT6600-5.sub differ diff --git a/spice/copy/sub/LT6654.lib b/spice/copy/sub/LT6654.lib new file mode 100755 index 0000000..f0547e0 --- /dev/null +++ b/spice/copy/sub/LT6654.lib @@ -0,0 +1,343 @@ +* Copyright (c) Linear Technology Corp. 2014. All rights reserved. +* +.subckt LT6654-1.25 1 2 3 +B2 N005 0 I=10u*(V(OUTS,GNDS)-1.24999) +C10 N005 0 1p Rpar=100K noiseless +A5 N002 0 0 0 0 0 N003 0 OTA g=50u iout=200u Cout=5p Vhigh=1e308 Vlow=-1e308 +D9 N003 0 DLIM +C13 2 1 1000p +D7 2 1 DP +A1 0 N005 0 0 0 0 N002 0 OTA g=1m linear en=3.2u/((25+log(freq))+1m*dnlim(freq-40k,1,1k)) Cout=800p Rout=1.5k Vlow=-1e308 Vhigh=1e308 +M1 OUTS N009 GNDS GNDS NI temp=27 +C2 2 OUTS .1p Rpar=100Meg noiseless +M2 OUTS N004 2 2 PI temp=27 +C3 OUTS 1 .1p Rpar=10Meg noiseless +M3 N004 N004 2 2 PI temp=27 M=10m +M4 N009 N009 1 1 NI temp=27 M=10m +A3 0 N006 2 2 2 2 N009 2 OTA g=1m asym isource=300u isink=-10u vlow=-1e308 vhigh=1e308 +D1 2 N004 DLIMP +C1 N003 N002 76p Rser=200k noiseless +C4 N003 N002 76.7p Rser=150k noiseless +C6 2 N004 1p +C7 N009 1 1p +C8 2 N008 1p +R1 N008 1 100k noiseless +G1 1 N005 1 N008 1µ +R2 GNDS 1 13.5m noiseless +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear Cout=5f Vlow=-1e308 Vhigh=1e308 +R3 3 OUTS 3m noiseless +G2 0 VDO 3 2 50µ +A7 3 OUTS 0 0 0 0 VDO 0 OTA g=2.1 asym isource=24u Isink=-50n Vhigh=1e308 Vlow=-1e308 +D3 OUTS GNDS DIVOS +D4 N006 0 DNLG +G3 2 N005 2 1 15p +G6 0 VDO OUTS 3 80m +G7 0 N003 VDO 0 10m vto=-250m dir=1 +A2 0 N006 1 1 1 1 N004 1 OTA g=.5m asym isource=1u Isink=-400u Vlow=-1e308 Vhigh=1e308 +D2 N004 1 DIMIN +C9 VDO 0 100f Rpar=20k noiseless +C11 GNDS 1 1p +.model DP D(Roff=1G Ron=100 Vfwd=.5 epsilon=.5 ilimit=134u noiseless) +.model PI VDMOS(Vto=-300m Kp=40m pchan Cgs=1p oneway) +.model NI VDMOS(Vto=300m Kp=40m Cgs=1p) +.model DLIM D(Ron=100 Roff=100Meg Vfwd=7 Vrev=9.5 epsilon=100m revepsilon=100m noiseless) +.model DNLG D(Ron=3Meg Roff=800k vfwd=50m epsilon=50m vrev=10m revepsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=3.5 epsilon=100m noiseless) +.model DIVOS D(Ron=1k Roff=1g vfwd=1 epsilon=1 ilimit=86u noiseless) +.model DIMIN D(Ron=100 Roff=1g vfwd=700m epsilon=700m ilimit=2.7u noiseless) +.ends LT6654-1.25 +* +.subckt LT6654-2.048 1 2 3 +B2 N005 0 I=10u*(V(OUTS,GNDS)-2.04799) +C10 N005 0 1p Rpar=100K noiseless +A5 N002 0 0 0 0 0 N003 0 OTA g=50u iout=200u Cout=5p Vhigh=1e308 Vlow=-1e308 +D9 N003 0 DLIM +C13 2 1 1000p +D7 2 1 DP +A1 0 N005 0 0 0 0 N002 0 OTA g=1m linear en=4.5u/((25+log(freq))+1m*dnlim(freq-40k,1,1k)) Cout=800p Rout=1.5k Vlow=-1e308 Vhigh=1e308 +M1 OUTS N009 GNDS GNDS NI temp=27 +C2 2 OUTS .1p Rpar=100Meg noiseless +M2 OUTS N004 2 2 PI temp=27 +C3 OUTS 1 .1p Rpar=10Meg noiseless +M3 N004 N004 2 2 PI temp=27 M=10m +M4 N009 N009 1 1 NI temp=27 M=10m +A3 0 N006 2 2 2 2 N009 2 OTA g=1m asym isource=300u isink=-10u vlow=-1e308 vhigh=1e308 +D1 2 N004 DLIMP +C1 N003 N002 76p Rser=200k noiseless +C4 N003 N002 76.7p Rser=150k noiseless +C6 2 N004 1p +C7 N009 1 1p +C8 2 N008 1p +R1 N008 1 100k noiseless +G1 1 N005 1 N008 1µ +R2 GNDS 1 16m noiseless +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear Cout=5f Vlow=-1e308 Vhigh=1e308 +R3 3 OUTS 3m noiseless +A6 OUTS 3 0 0 0 0 N011 0 OTA g=1 asym ref=-400n isource=100n Isink=-80n Rout=1Meg Vlow=-1e308 Vhigh=1e308 +G2 0 VDO 3 2 50µ +A7 3 OUTS 0 0 0 0 VDO 0 OTA g=.7 asym isource=4.7u Isink=-.1u Vhigh=1e308 Vlow=-1e308 +D3 OUTS GNDS DIVOS +D4 N006 0 DNLG +G4 2 N005 2 0 8.2p +G3 2 N005 2 1 8.2p +G6 0 VDO OUTS 3 .16 +G7 0 N003 VDO N011 10m vto=0 dir=1 +A2 0 N006 1 1 1 1 N004 1 OTA g=.5m asym isource=1u Isink=-400u in=255f/(1+1m*dnlim(freq-50k,1,1k)) Vlow=-1e308 Vhigh=1e308 +D2 N004 1 DIMIN +G5 0 VDO 3 2 10m vto=120m dir=1 +C9 VDO 0 100f Rpar=20k noiseless +C11 GNDS 1 1p +.model DP D(Roff=1G Ron=100 Vfwd=.5 epsilon=.5 ilimit=134u noiseless) +.model PI VDMOS(Vto=-300m Kp=40m pchan Cgs=1p oneway) +.model NI VDMOS(Vto=300m Kp=40m Cgs=1p) +.model DLIM D(Ron=100 Roff=100Meg Vfwd=7 Vrev=6 epsilon=100m revepsilon=100m noiseless) +.model DNLG D(Ron=3Meg Roff=800k vfwd=50m epsilon=50m vrev=10m revepsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=3.5 epsilon=100m noiseless) +.model DIVOS D(Ron=1k Roff=1g vfwd=1 epsilon=1 ilimit=86u noiseless) +.model DIMIN D(Ron=100 Roff=1g vfwd=700m epsilon=700m ilimit=2.7u noiseless) +.ends LT6654-2.048 +* +.subckt LT6654-2.5 1 2 3 +B2 N005 0 I=10u*(V(OUTS,GNDS)-2.49999) +C10 N005 0 1p Rpar=100K noiseless +A5 N002 0 0 0 0 0 N003 0 OTA g=50u iout=200u Cout=5p Vhigh=1e308 Vlow=-1e308 +D9 N003 0 DLIM +C13 2 1 1000p +D7 2 1 DP +A1 0 N005 0 0 0 0 N002 0 OTA g=1m linear en=5.2u/((25+log(freq))+1m*dnlim(freq-40k,1,1k)) Cout=800p Rout=1.5k Vlow=-1e308 Vhigh=1e308 +M1 OUTS N009 GNDS GNDS NI temp=27 +C2 2 OUTS .1p Rpar=100Meg noiseless +M2 OUTS N004 2 2 PI temp=27 +C3 OUTS 1 .1p Rpar=10Meg noiseless +M3 N004 N004 2 2 PI temp=27 M=10m +M4 N009 N009 1 1 NI temp=27 M=10m +A3 0 N006 2 2 2 2 N009 2 OTA g=1m asym isource=300u isink=-10u vlow=-1e308 vhigh=1e308 +D1 2 N004 DLIMP +C1 N003 N002 76p Rser=200k noiseless +C4 N003 N002 76.7p Rser=150k noiseless +C6 2 N004 1p +C7 N009 1 1p +C8 2 N008 1p +R1 N008 1 100k noiseless +G1 1 N005 1 N008 1µ +R2 GNDS 1 17m noiseless +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear Cout=5f Vlow=-1e308 Vhigh=1e308 +R3 3 OUTS 3m noiseless +A6 OUTS 3 0 0 0 0 N011 0 OTA g=1 asym ref=-400n isource=100n Isink=-80n Rout=1Meg Vlow=-1e308 Vhigh=1e308 +G2 0 VDO 3 2 50µ +A7 3 OUTS 0 0 0 0 VDO 0 OTA g=.7 asym isource=4.7u Isink=-.1u Vhigh=1e308 Vlow=-1e308 +D3 OUTS GNDS DIVOS +D4 N006 0 DNLG +G3 2 N005 2 1 30p +G6 0 VDO OUTS 3 .16 +G7 0 N003 VDO N011 10m vto=0 dir=1 +A2 0 N006 1 1 1 1 N004 1 OTA g=.5m asym isource=1u Isink=-400u in=400f/(1+1m*dnlim(freq-50k,1,1k)) Vlow=-1e308 Vhigh=1e308 +D2 N004 1 DIMIN +G5 0 VDO 3 2 10m vto=120m dir=1 +C11 GNDS 1 1p +C9 VDO 0 100f Rpar=20k noiseless +.model DP D(Roff=1G Ron=100 Vfwd=.5 epsilon=.5 ilimit=134u noiseless) +.model PI VDMOS(Vto=-300m Kp=40m pchan Cgs=1p oneway) +.model NI VDMOS(Vto=300m Kp=40m Cgs=1p) +.model DLIM D(Ron=100 Roff=100Meg Vfwd=7 Vrev=4 epsilon=100m revepsilon=100m noiseless) +.model DNLG D(Ron=3Meg Roff=800k vfwd=50m epsilon=50m vrev=10m revepsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=3.5 epsilon=100m noiseless) +.model DIVOS D(Ron=1k Roff=1g vfwd=1 epsilon=1 ilimit=86u noiseless) +.model DIMIN D(Ron=100 Roff=1g vfwd=700m epsilon=700m ilimit=2.7u noiseless) +.ends LT6654-2.5 +* +.subckt LT6654-3.3 1 2 3 +B2 N005 0 I=7.76u*(V(OUTS,GNDS)-3.29998) +C10 N005 0 1p Rpar=100K noiseless +A5 N002 0 0 0 0 0 N003 0 OTA g=50u iout=200u Cout=5p Vhigh=1e308 Vlow=-1e308 +D9 N003 0 DLIM +C13 2 1 1000p +D7 2 1 DP +A1 0 N005 0 0 0 0 N002 0 OTA g=1m linear en=4.5u/((25+log(freq))+1m*dnlim(freq-40k,1,1k)) Cout=800p Rout=1.5k Vlow=-1e308 Vhigh=1e308 +M1 OUTS N009 GNDS GNDS NI temp=27 +C2 2 OUTS .1p Rpar=100Meg noiseless +M2 OUTS N004 2 2 PI temp=27 +C3 OUTS 1 .1p Rpar=10Meg noiseless +M3 N004 N004 2 2 PI temp=27 M=10m +M4 N009 N009 1 1 NI temp=27 M=10m +A3 0 N006 2 2 2 2 N009 2 OTA g=1m asym isource=300u isink=-10u vlow=-1e308 vhigh=1e308 +D1 2 N004 DLIMP +C1 N003 N002 76p Rser=200k noiseless +C4 N003 N002 76.7p Rser=150k noiseless +C6 2 N004 1p +C7 N009 1 1p +C8 2 N008 1p +R1 N008 1 100k noiseless +G1 1 N005 1 N008 1µ +R2 GNDS 1 30.8m noiseless +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear Cout=5f Vlow=-1e308 Vhigh=1e308 +R3 3 OUTS 3m noiseless +A6 OUTS 3 0 0 0 0 N011 0 OTA g=1 asym ref=-400n isource=100n Isink=-80n Rout=1Meg Vlow=-1e308 Vhigh=1e308 +G2 0 VDO 3 2 50µ +A7 3 OUTS 0 0 0 0 VDO 0 OTA g=.7 asym isource=4.7u Isink=-.1u Vhigh=1e308 Vlow=-1e308 +D3 OUTS GNDS DIVOS +D4 N006 0 DNLG +G3 2 N005 2 1 26.2p +G6 0 VDO OUTS 3 .16 +G7 0 N003 VDO N011 10m vto=0 dir=1 +A2 0 N006 1 1 1 1 N004 1 OTA g=.5m asym isource=1u Isink=-400u in=320f/(1+1m*dnlim(freq-50k,1,1k)) Vlow=-1e308 Vhigh=1e308 +D2 N004 1 DIMIN +G5 0 VDO 3 2 10m vto=120m dir=1 +C9 VDO 0 100f Rpar=20k noiseless +C11 GNDS 1 10p +.model DP D(Roff=1G Ron=100 Vfwd=.5 epsilon=.5 ilimit=134u noiseless) +.model PI VDMOS(Vto=-300m Kp=40m pchan Cgs=1p oneway) +.model NI VDMOS(Vto=300m Kp=40m Cgs=1p) +.model DLIM D(Ron=100 Roff=100Meg Vfwd=7 Vrev=3.2 epsilon=100m revepsilon=100m noiseless) +.model DNLG D(Ron=3Meg Roff=800k vfwd=50m epsilon=50m vrev=10m revepsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=3.5 epsilon=100m noiseless) +.model DIVOS D(Ron=1k Roff=1g vfwd=1 epsilon=1 ilimit=86u noiseless) +.model DIMIN D(Ron=100 Roff=1g vfwd=700m epsilon=700m ilimit=2.7u noiseless) +.ends LT6654-3.3 +* +.subckt LT6654-3 1 2 3 +B2 N005 0 I=8.6u*(V(OUTS,GNDS)-2.99998) +C10 N005 0 1p Rpar=100K noiseless +A5 N002 0 0 0 0 0 N003 0 OTA g=50u iout=200u Cout=5p Vhigh=1e308 Vlow=-1e308 +D9 N003 0 DLIM +C13 2 1 1000p +D7 2 1 DP +A1 0 N005 0 0 0 0 N002 0 OTA g=1m linear en=4.8u/((25+log(freq))+1m*dnlim(freq-40k,1,1k)) Cout=800p Rout=1.5k Vlow=-1e308 Vhigh=1e308 +M1 OUTS N009 GNDS GNDS NI temp=27 +C2 2 OUTS .1p Rpar=100Meg noiseless +M2 OUTS N004 2 2 PI temp=27 +C3 OUTS 1 .1p Rpar=10Meg noiseless +M3 N004 N004 2 2 PI temp=27 M=10m +M4 N009 N009 1 1 NI temp=27 M=10m +A3 0 N006 2 2 2 2 N009 2 OTA g=1m asym isource=300u isink=-10u vlow=-1e308 vhigh=1e308 +D1 2 N004 DLIMP +C1 N003 N002 76p Rser=200k noiseless +C4 N003 N002 76.7p Rser=150k noiseless +C6 2 N004 1p +C7 N009 1 1p +C8 2 N008 1p +R1 N008 1 100k noiseless +G1 1 N005 1 N008 1µ +R2 GNDS 1 25.7m noiseless +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear Cout=5f Vlow=-1e308 Vhigh=1e308 +R3 3 OUTS 3m noiseless +A6 OUTS 3 0 0 0 0 N011 0 OTA g=1 asym ref=-400n isource=100n Isink=-80n Rout=1Meg Vlow=-1e308 Vhigh=1e308 +G2 0 VDO 3 2 50µ +A7 3 OUTS 0 0 0 0 VDO 0 OTA g=.7 asym isource=4.7u Isink=-.1u Vhigh=1e308 Vlow=-1e308 +D3 OUTS GNDS DIVOS +D4 N006 0 DNLG +G3 2 N005 2 1 27.6p +G6 0 VDO OUTS 3 .16 +G7 0 N003 VDO N011 10m vto=0 dir=1 +A2 0 N006 1 1 1 1 N004 1 OTA g=.5m asym isource=1u Isink=-400u in=350f/(1+1m*dnlim(freq-50k,1,1k)) Vlow=-1e308 Vhigh=1e308 +D2 N004 1 DIMIN +G5 0 VDO 3 2 10m vto=120m dir=1 +C9 VDO 0 100f Rpar=20k noiseless +C11 GNDS 1 10p +.model DP D(Roff=1G Ron=100 Vfwd=.5 epsilon=.5 ilimit=134u noiseless) +.model PI VDMOS(Vto=-300m Kp=40m pchan Cgs=1p oneway) +.model NI VDMOS(Vto=300m Kp=40m Cgs=1p) +.model DLIM D(Ron=100 Roff=100Meg Vfwd=7 Vrev=3.5 epsilon=100m revepsilon=100m noiseless) +.model DNLG D(Ron=3Meg Roff=800k vfwd=50m epsilon=50m vrev=10m revepsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=3.5 epsilon=100m noiseless) +.model DIVOS D(Ron=1k Roff=1g vfwd=1 epsilon=1 ilimit=86u noiseless) +.model DIMIN D(Ron=100 Roff=1g vfwd=700m epsilon=700m ilimit=2.7u noiseless) +.ends LT6654-3 +* +.subckt LT6654-4.096 1 2 3 +B2 N005 0 I=5.5u*(V(OUTS,GNDS)-4.09597-2*V(OUTS,3)) +C10 N005 0 1p Rpar=100K noiseless +A5 N002 0 0 0 0 0 N003 0 OTA g=50u iout=200u Cout=5p Vhigh=1e308 Vlow=-1e308 +D9 N003 0 DLIM +C13 2 1 1000p +D7 2 1 DP +A1 0 N005 0 0 0 0 N002 0 OTA g=1m linear en=4u/((25+log(freq))+1m*dnlim(freq-40k,1,1k)) Cout=800p Rout=1.5k Vlow=-1e308 Vhigh=1e308 +M1 OUTS N009 GNDS GNDS NI temp=27 +C2 2 OUTS .1p Rpar=100Meg noiseless +M2 OUTS N004 2 2 PI temp=27 +C3 OUTS 1 .1p Rpar=10Meg noiseless +M3 N004 N004 2 2 PI temp=27 M=10m +M4 N009 N009 1 1 NI temp=27 M=10m +A3 0 N006 2 2 2 2 N009 2 OTA g=1m asym isource=300u isink=-10u vlow=-1e308 vhigh=1e308 +D1 2 N004 DLIMP +C1 N003 N002 76p Rser=200k noiseless +C4 N003 N002 76.7p Rser=150k noiseless +C6 2 N004 1p +C7 N009 1 1p +C8 2 N008 1p +R1 N008 1 100k noiseless +G1 1 N005 1 N008 1µ +R2 GNDS 1 44.5m noiseless +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear Cout=5f Vlow=-1e308 Vhigh=1e308 +R3 3 OUTS 3m noiseless +A6 OUTS 3 0 0 0 0 N011 0 OTA g=1 asym ref=-400n isource=100n Isink=-80n Rout=1Meg Vlow=-1e308 Vhigh=1e308 +G2 0 VDO 3 2 50µ +A7 3 OUTS 0 0 0 0 VDO 0 OTA g=.7 asym isource=4.7u Isink=-.1u Vhigh=1e308 Vlow=-1e308 +D3 OUTS GNDS DIVOS +D4 N006 0 DNLG +G3 2 N005 2 1 22.3p +G6 0 VDO OUTS 3 .16 +G7 0 N003 VDO N011 10m vto=0 dir=1 +A2 0 N006 1 1 1 1 N004 1 OTA g=.5m asym isource=1u Isink=-400u in=240f/(1+1m*dnlim(freq-50k,1,1k)) Vlow=-1e308 Vhigh=1e308 +D2 N004 1 DIMIN +G5 0 VDO 3 2 10m vto=120m dir=1 +C9 VDO 0 100f Rpar=20k noiseless +C11 GNDS 1 10p +.model DP D(Roff=1G Ron=100 Vfwd=.5 epsilon=.5 ilimit=134u noiseless) +.model PI VDMOS(Vto=-300m Kp=40m pchan Cgs=1p oneway) +.model NI VDMOS(Vto=300m Kp=40m Cgs=1p) +.model DLIM D(Ron=100 Roff=100Meg Vfwd=7 Vrev=2.4 epsilon=100m revepsilon=100m noiseless) +.model DNLG D(Ron=3Meg Roff=800k vfwd=50m epsilon=50m vrev=10m revepsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=3.5 epsilon=100m noiseless) +.model DIVOS D(Ron=1k Roff=1g vfwd=1 epsilon=1 ilimit=86u noiseless) +.model DIMIN D(Ron=100 Roff=1g vfwd=700m epsilon=700m ilimit=2.7u noiseless) +.ends LT6654-4.096 +* +.subckt LT6654-5 1 2 3 +C10 N005 0 1p Rpar=100K noiseless +A5 N002 0 0 0 0 0 N003 0 OTA g=50u iout=200u Cout=5p Vhigh=1e308 Vlow=-1e308 +D9 N003 0 DLIM +C13 2 1 1000p +D7 2 1 DP +A1 0 N005 0 0 0 0 N002 0 OTA g=1m linear en=3.2u/((25+log(freq))+1m*dnlim(freq-40k,1,1k)) Cout=800p Rout=1.5k Vlow=-1e308 Vhigh=1e308 +M1 OUTS N009 GNDS GNDS NI temp=27 +C2 2 OUTS .1p Rpar=100Meg noiseless +M2 OUTS N004 2 2 PI temp=27 +C3 OUTS 1 .1p Rpar=10Meg noiseless +M3 N004 N004 2 2 PI temp=27 M=10m +M4 N009 N009 1 1 NI temp=27 M=10m +A3 0 N006 2 2 2 2 N009 2 OTA g=1m asym isource=300u isink=-10u vlow=-1e308 vhigh=1e308 +D1 2 N004 DLIMP +C1 N003 N002 76p Rser=200k noiseless +C4 N003 N002 76.7p Rser=150k noiseless +C6 2 N004 1p +C7 N009 1 1p +C8 2 N008 1p +R1 N008 1 100k noiseless +G1 1 N005 1 N008 1µ +R2 GNDS 1 65m noiseless +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear Cout=5f Vlow=-1e308 Vhigh=1e308 +R3 3 OUTS 3m noiseless +A6 OUTS 3 0 0 0 0 N011 0 OTA g=1 asym ref=-400n isource=100n Isink=-80n Rout=1Meg Vlow=-1e308 Vhigh=1e308 +G2 0 VDO 3 2 50µ +A7 3 OUTS 0 0 0 0 VDO 0 OTA g=.7 asym isource=4.7u Isink=-.1u Vhigh=1e308 Vlow=-1e308 +D3 OUTS GNDS DIVOS +D4 N006 0 DNLG +G3 2 N005 2 1 18p +G6 0 VDO OUTS 3 .16 +G7 0 N003 VDO N011 10m vto=0 dir=1 +A2 0 N006 1 1 1 1 N004 1 OTA g=.5m asym isource=1u Isink=-400u in=150f/(1+1m*dnlim(freq-50k,1,1k)) Vlow=-1e308 Vhigh=1e308 +D2 N004 1 DIMIN +G5 0 VDO 3 2 10m vto=120m dir=1 +B1 N005 0 I=3u*(V(OUTS,GNDS)-4.99995-4*V(OUTS,3)) +C9 VDO 0 100f Rpar=20k noiseless +C11 GNDS 1 10p +.model DP D(Roff=1G Ron=100 Vfwd=.5 epsilon=.5 ilimit=134u noiseless) +.model PI VDMOS(Vto=-300m Kp=40m pchan Cgs=1p oneway) +.model NI VDMOS(Vto=300m Kp=40m Cgs=1p) +.model DLIM D(Ron=100 Roff=100Meg Vfwd=7 Vrev=1.5 epsilon=100m revepsilon=100m noiseless) +.model DNLG D(Ron=3Meg Roff=800k vfwd=50m epsilon=50m vrev=10m revepsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=3.5 epsilon=100m noiseless) +.model DIVOS D(Ron=1k Roff=1g vfwd=1 epsilon=1 ilimit=86u noiseless) +.model DIMIN D(Ron=100 Roff=1g vfwd=700m epsilon=700m ilimit=2.7u noiseless) +.ends LT6654-5 diff --git a/spice/copy/sub/LT6656.lib b/spice/copy/sub/LT6656.lib new file mode 100755 index 0000000..1af2e7d --- /dev/null +++ b/spice/copy/sub/LT6656.lib @@ -0,0 +1,456 @@ +* Copyright © Linear Technology Corp. 2016. All rights reserved. +* +.subckt LT6656-1.25 1 2 3 +C15 2 1 100f +C1 CORE 0 100f Rpar=1.2Meg noiseless +B1 0 CORE I=2.02867u+4.05e-12*V(2,1) +Q1 C1 B1 E1 0 PNPSRC M=40 temp=27 +B2 B1 1 I=260u*(.5+.5*tanh((V(on)-.5)/60m))*(.5+.5*tanh((-V(err)-80m)/100m)+.5+.5*tanh((-V(err)+130m)/20m))/dnlim(-4.1+5*dnlim(1.3333*V(2,E1),.1u,.1u)/dnlim(V(C1,C2),.1u,.1u),1,10m) +M1 1 N009 3 3 PSNK temp=27 +B3 N009 1 I=.1u*(.5+.5*tanh((V(on)-.5)/50m))*dnlim(uplim(V(err0A)-3.4,.7,.2)+uplim(.1*(V(err0A)-3.4),.3,.3),0,1e-3) +G1 0 N004 err0 0 1e-3 +L1 N004 0 1.346 Rser=1.18K Rpar=6.43K noiseless +C2 err0 0 450n Rpar=2Meg noiseless +G3 0 err N005 0 1µ +C3 err 0 3p Rpar=1Meg noiseless +G4 0 N005 N004 0 1m +L2 N005 0 60m Rser=1.13k Rpar=8.7k Cpar=191p noiseless +D1 3 1 DBGB +D2 2 B1 Dlowcur +R5 SEN 0 1Meg noiseless +B4 0 SEN I=.974u*V(3,1) +R2 2 E1 750m noiseless +B5 0 SEN I=40n*V(C1,C2) +C5 2 N003 100f +G2 err 0 N002 0 200µ +G5 0 N002 N003 1 1m +C7 N008 0 1p Rpar=2Meg noiseless +G6 0 err0A N008 0 1e-6 +L4 err0A 0 23.5 Cpar=127f Rser=1.18Meg Rpar=6.55Meg noiseless +C9 3 N009 5p Rpar=10Meg noiseless +D5 err0 0 DLIM1 +C13 3 1 1p Rpar=100Meg noiseless +B8 3 1 I=.4*V(3,1)*(.5+.5*tanh((V(on)-.5)/60m))*dnlim(.5u*(V(deltahysB)-1.5),0,10n) +D3 N007 err0 DLINK +G7 0 N007 N008 0 1m +C10 N007 0 800p Rpar=1k noiseless +C6 deltahysB 0 8n Rpar=1Meg noiseless +C14 N010 0 100p Rpar=1k noiseless +B11 0 N010 I=dnlim(uplim(-100m*V(err0)+29m,11m,.1m),0,.1m) +D6 N010 deltahysB D1wy +A3 2 1 0 0 0 0 On 0 SCHMITT vt=1.35 vh=0 trise=3m +S1 CORE 0 0 On SOFF +L3 N002 0 .31 Rser=1.56k Rpar=2.78k Cpar=7.96e-9 noiseless +C8 N003 1 5p Rpar=1Meg noiseless +D7 1 2 DREV +D8 1 3 DOUT +A4 Core Sen 0 0 0 0 err0 0 OTA g=1m linear en=2.2u vlow=-1e308 vhigh=1e308 +A1 Core Sen 0 0 0 0 N008 0 OTA g=1m linear en=2u vlow=-1e308 vhigh=1e308 +D9 N008 0 DLIM2 +D10 2 1 DBURN +R1 C2 3 10 noiseless +R3 C1 C2 1 noiseless +B6 3 C2 I=uplim(dnlim(140*V(C1,C2)-1.3m,100u,100u),8m,6m) +.model PSNK VDMOS(vto=-500m kp=34m pchan) +.model DBGB D(Ron=1k Roff=1G vfwd=600m epsilon=300m ilimit=400n noiseless) +.model Dout D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DREV D(Ron=50k Roff=1G vfwd=14 epsilon=3 noiseless) +.model SOFF SW(Ron=1k Roff=1.2Meg vt=-.4 vh=-.3 noiseless) +.model DBURN D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=.264u) +.model D1wy D(Ron=1K Roff=1G vfwd=1 epsilon=300m noiseless) +.model DLIM1 D(Ron=100 Roff=2Meg vfwd=300m epsilon=100m vrev=100m revepsilon=-100m noiseless) +.model DLIM2 D(Ron=20 Roff=2Meg vfwd=30 epsilon=500m vrev=10 revepsilon=500m) +.model Dlowcur D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=150n revilimit=80n noiseless) +.model DLINK D(Ron=300k Roff=1G vfwd=1 epsilon=500m ilimit=4u noiseless) +.model pnpsrc pnp (is=1.48e-016 bf=457 nf=1 vaf=41 ikf=5.34e-005 ise=5e-017 ne=1.29 br=60 nr=1 var=8.3 ikr=2.9e-005 rb=650 irb=10 rbm=500 noiseless) +.ends LT6656-1.25 +* +.subckt LT6656-2.048 1 2 3 +C15 2 1 100f +C1 CORE 0 100f Rpar=1.2Meg noiseless +B1 0 CORE I=2.02867u+4.05e-12*V(2,1) +Q1 C1 B1 E1 0 PNPSRC M=40 temp=27 +B2 B1 1 I=260u*(.5+.5*tanh((V(on)-.5)/60m))*(.5+.5*tanh((-V(err)-80m)/100m)+.5+.5*tanh((-V(err)+130m)/20m))/dnlim(-4.1+5*dnlim(1.3333*V(2,E1),.1u,.1u)/dnlim(V(C1,C2),.1u,.1u),1,10m) +M1 1 N009 3 3 PSNK temp=27 +B3 N009 1 I=.1u*(.5+.5*tanh((V(on)-.5)/50m))*dnlim(uplim(V(err0A)-3.4,.7,.2)+uplim(.1*(V(err0A)-3.4),.3,.3),0,1e-3) +G1 0 N004 err0 0 1e-3 +L1 N004 0 1.346 Rser=1.18K Rpar=6.43K noiseless +C2 err0 0 450n Rpar=2Meg noiseless +G3 0 err N005 0 1µ +C3 err 0 3p Rpar=1Meg noiseless +G4 0 N005 N004 0 1m +L2 N005 0 60m Rser=1.13k Rpar=8.7k Cpar=191p noiseless +D1 3 1 DBGB +D2 2 B1 Dlowcur +R5 SEN 0 1Meg noiseless +B4 0 SEN I=.594482u*V(3,1) +R2 2 E1 750m noiseless +B5 0 SEN I=36n*V(C1,C2) +C5 2 N003 100f +G2 err 0 N002 0 122µ +G5 0 N002 N003 1 1m +C7 N008 0 1p Rpar=2Meg noiseless +G6 0 err0A N008 0 1e-6 +L4 err0A 0 23.5 Cpar=127f Rser=1.18Meg Rpar=6.55Meg noiseless +C9 3 N009 5p Rpar=10Meg noiseless +D5 err0 0 DLIM1 +C13 3 1 1p Rpar=100Meg noiseless +B8 3 1 I=.4*V(3,1)*(.5+.5*tanh((V(on)-.5)/60m))*dnlim(.5u*(V(deltahysB)-1.5),0,10n) +D3 N007 err0 DLINK +G7 0 N007 N008 0 1m +C10 N007 0 800p Rpar=1k noiseless +C6 deltahysB 0 8n Rpar=1Meg noiseless +C14 N010 0 100p Rpar=1k noiseless +B11 0 N010 I=dnlim(uplim(-100m*V(err0)+29m,11m,.1m),0,.1m) +D6 N010 deltahysB D1wy +A3 2 1 0 0 0 0 On 0 SCHMITT vt=1.35 vh=0 trise=3m +S1 CORE 0 0 On SOFF +L3 N002 0 .31 Rser=1.56k Rpar=2.78k Cpar=7.96e-9 noiseless +C8 N003 1 5p Rpar=1Meg noiseless +D7 1 2 DREV +D8 1 3 DOUT +A4 Core Sen 0 0 0 0 err0 0 OTA g=1m linear en=2.2u vlow=-1e308 vhigh=1e308 +A1 Core Sen 0 0 0 0 N008 0 OTA g=1m linear en=2u vlow=-1e308 vhigh=1e308 +D9 N008 0 DLIM2 +D10 2 1 DBURN +R1 C2 3 10 noiseless +R3 C1 C2 1 noiseless +B6 3 C2 I=uplim(dnlim(140*V(C1,C2)-1.3m,100u,100u),8m,6m) +.model PSNK VDMOS(vto=-500m kp=34m pchan) +.model DBGB D(Ron=1k Roff=1G vfwd=600m epsilon=300m ilimit=400n noiseless) +.model Dout D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DREV D(Ron=50k Roff=1G vfwd=14 epsilon=3 noiseless) +.model SOFF SW(Ron=1k Roff=1.2Meg vt=-.4 vh=-.3 noiseless) +.model DBURN D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=.264u) +.model D1wy D(Ron=1K Roff=1G vfwd=1 epsilon=300m noiseless) +.model DLIM1 D(Ron=100 Roff=2Meg vfwd=300m epsilon=100m vrev=100m revepsilon=-100m noiseless) +.model DLIM2 D(Ron=20 Roff=2Meg vfwd=30 epsilon=500m vrev=10 revepsilon=500m) +.model Dlowcur D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=150n revilimit=80n noiseless) +.model DLINK D(Ron=300k Roff=1G vfwd=1 epsilon=500m ilimit=4u noiseless) +.model pnpsrc pnp (is=1.48e-016 bf=457 nf=1 vaf=41 ikf=5.34e-005 ise=5e-017 ne=1.29 br=60 nr=1 var=8.3 ikr=2.9e-005 rb=650 irb=10 rbm=500 noiseless) +.ends LT6656-2.048 +* +.subckt LT6656-2.5 1 2 3 +C15 2 1 100f +C1 CORE 0 100f Rpar=1.2Meg noiseless +B1 0 CORE I=2.02867u+4.05e-12*V(2,1) +Q1 C1 B1 E1 0 PNPSRC M=40 temp=27 +B2 B1 1 I=260u*(.5+.5*tanh((V(on)-.5)/60m))*(.5+.5*tanh((-V(err)-80m)/100m)+.5+.5*tanh((-V(err)+130m)/20m))/dnlim(-4.1+5*dnlim(1.3333*V(2,E1),.1u,.1u)/dnlim(V(C1,C2),.1u,.1u),1,10m) +M1 1 N009 3 3 PSNK temp=27 +B3 N009 1 I=.1u*(.5+.5*tanh((V(on)-.5)/50m))*dnlim(uplim(V(err0A)-3.4,.7,.2)+uplim(.1*(V(err0A)-3.4),.3,.3),0,1e-3) +G1 0 N004 err0 0 1e-3 +L1 N004 0 1.346 Rser=1.18K Rpar=6.43K noiseless +C2 err0 0 450n Rpar=2Meg noiseless +G3 0 err N005 0 1µ +C3 err 0 3p Rpar=1Meg noiseless +G4 0 N005 N004 0 1m +L2 N005 0 60m Rser=1.13k Rpar=8.7k Cpar=191p noiseless +D1 3 1 DBGB +D2 2 B1 Dlowcur +R5 SEN 0 1Meg noiseless +B4 0 SEN I=.487u*V(3,1) +R2 2 E1 750m noiseless +B5 0 SEN I=30n*V(C1,C2) +C5 2 N003 100f +G2 err 0 N002 0 100µ +G5 0 N002 N003 1 1m +C7 N008 0 1p Rpar=2Meg noiseless +G6 0 err0A N008 0 1e-6 +L4 err0A 0 23.5 Cpar=127f Rser=1.18Meg Rpar=6.55Meg noiseless +C9 3 N009 5p Rpar=10Meg noiseless +D5 err0 0 DLIM1 +C13 3 1 1p Rpar=100Meg noiseless +B8 3 1 I=.4*V(3,1)*(.5+.5*tanh((V(on)-.5)/60m))*dnlim(.5u*(V(deltahysB)-1.5),0,10n) +D3 N007 err0 DLINK +G7 0 N007 N008 0 1m +C10 N007 0 800p Rpar=1k noiseless +C6 deltahysB 0 8n Rpar=1Meg noiseless +C14 N010 0 100p Rpar=1k noiseless +B11 0 N010 I=dnlim(uplim(-100m*V(err0)+29m,11m,.1m),0,.1m) +D6 N010 deltahysB D1wy +A3 2 1 0 0 0 0 On 0 SCHMITT vt=1.35 vh=0 trise=3m +S1 CORE 0 0 On SOFF +L3 N002 0 .31 Rser=1.56k Rpar=2.78k Cpar=7.96e-9 noiseless +C8 N003 1 5p Rpar=1Meg noiseless +D7 1 2 DREV +D8 1 3 DOUT +A4 Core Sen 0 0 0 0 err0 0 OTA g=1m linear en=2.2u vlow=-1e308 vhigh=1e308 +A1 Core Sen 0 0 0 0 N008 0 OTA g=1m linear en=2u vlow=-1e308 vhigh=1e308 +D9 N008 0 DLIM2 +D10 2 1 DBURN +R1 C2 3 10 noiseless +R3 C1 C2 1 noiseless +B6 3 C2 I=uplim(dnlim(140*V(C1,C2)-1.3m,100u,100u),8m,6m) +.model PSNK VDMOS(vto=-500m kp=34m pchan) +.model DBGB D(Ron=1k Roff=1G vfwd=600m epsilon=300m ilimit=400n noiseless) +.model Dout D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DREV D(Ron=50k Roff=1G vfwd=14 epsilon=3 noiseless) +.model SOFF SW(Ron=1k Roff=1.2Meg vt=-.4 vh=-.3 noiseless) +.model DBURN D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=.264u) +.model D1wy D(Ron=1K Roff=1G vfwd=1 epsilon=300m noiseless) +.model DLIM1 D(Ron=100 Roff=2Meg vfwd=300m epsilon=100m vrev=100m revepsilon=-100m noiseless) +.model DLIM2 D(Ron=20 Roff=2Meg vfwd=30 epsilon=500m vrev=10 revepsilon=500m) +.model Dlowcur D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=150n revilimit=80n noiseless) +.model DLINK D(Ron=300k Roff=1G vfwd=1 epsilon=500m ilimit=4u noiseless) +.model pnpsrc pnp (is=1.48e-016 bf=457 nf=1 vaf=41 ikf=5.34e-005 ise=5e-017 ne=1.29 br=60 nr=1 var=8.3 ikr=2.9e-005 rb=650 irb=10 rbm=500 noiseless) +.ends LT6656-2.5 +* +.subckt LT6656-3.3 1 2 3 +C15 2 1 100f +C1 CORE 0 100f Rpar=1.2Meg noiseless +B1 0 CORE I=2.02867u+4.05e-12*V(2,1) +Q1 C1 B1 E1 0 PNPSRC M=40 temp=27 +B2 B1 1 I=260u*(.5+.5*tanh((V(on)-.5)/60m))*(.5+.5*tanh((-V(err)-80m)/100m)+.5+.5*tanh((-V(err)+130m)/20m))/dnlim(-4.1+5*dnlim(1.3333*V(2,E1),.1u,.1u)/dnlim(V(C1,C2),.1u,.1u),1,10m) +M1 1 N009 3 3 PSNK temp=27 +B3 N009 1 I=.1u*(.5+.5*tanh((V(on)-.5)/50m))*dnlim(uplim(V(err0A)-3.4,.7,.2)+uplim(.1*(V(err0A)-3.4),.3,.3),0,1e-3) +G1 0 N004 err0 0 1e-3 +L1 N004 0 1.346 Rser=1.18K Rpar=6.43K noiseless +C2 err0 0 450n Rpar=2Meg noiseless +G3 0 err N005 0 1µ +C3 err 0 3p Rpar=1Meg noiseless +G4 0 N005 N004 0 1m +L2 N005 0 60m Rser=1.13k Rpar=8.7k Cpar=191p noiseless +D1 3 1 DBGB +D2 2 B1 Dlowcur +R5 SEN 0 1Meg noiseless +B4 0 SEN I=.36561686u*V(3,1) +R2 2 E1 750m noiseless +B5 0 SEN I=22.7n*V(C1,C2) +C5 2 N003 100f +G2 err 0 N002 0 132µ +G5 0 N002 N003 1 1m +C7 N008 0 1p Rpar=2Meg noiseless +G6 0 err0A N008 0 1e-6 +L4 err0A 0 23.5 Cpar=127f Rser=1.18Meg Rpar=6.55Meg noiseless +C9 3 N009 5p Rpar=10Meg noiseless +D5 err0 0 DLIM1 +C13 3 1 1p Rpar=100Meg noiseless +B8 3 1 I=.4*V(3,1)*(.5+.5*tanh((V(on)-.5)/60m))*dnlim(.5u*(V(deltahysB)-1.5),0,10n) +D3 N007 err0 DLINK +G7 0 N007 N008 0 1m +C10 N007 0 800p Rpar=1k noiseless +C6 deltahysB 0 8n Rpar=1Meg noiseless +C14 N010 0 100p Rpar=1k noiseless +B11 0 N010 I=dnlim(uplim(-100m*V(err0)+29m,11m,.1m),0,.1m) +D6 N010 deltahysB D1wy +A3 2 1 0 0 0 0 On 0 SCHMITT vt=1.35 vh=0 trise=3m +S1 CORE 0 0 On SOFF +L3 N002 0 .31 Rser=1.56k Rpar=2.78k Cpar=7.96e-9 noiseless +C8 N003 1 5p Rpar=1Meg noiseless +D7 1 2 DREV +D8 1 3 DOUT +A4 Core Sen 0 0 0 0 err0 0 OTA g=1m linear en=2.2u vlow=-1e308 vhigh=1e308 +A1 Core Sen 0 0 0 0 N008 0 OTA g=1m linear en=2u vlow=-1e308 vhigh=1e308 +D9 N008 0 DLIM2 +D10 2 1 DBURN +R1 C2 3 10 noiseless +R3 C1 C2 1 noiseless +B6 3 C2 I=uplim(dnlim(140*V(C1,C2)-1.3m,100u,100u),8m,6m) +.model PSNK VDMOS(vto=-500m kp=34m pchan) +.model DBGB D(Ron=1k Roff=1G vfwd=600m epsilon=300m ilimit=400n noiseless) +.model Dout D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DREV D(Ron=50k Roff=1G vfwd=14 epsilon=3 noiseless) +.model SOFF SW(Ron=1k Roff=1.2Meg vt=-.4 vh=-.3 noiseless) +.model DBURN D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=.264u) +.model D1wy D(Ron=1K Roff=1G vfwd=1 epsilon=300m noiseless) +.model DLIM1 D(Ron=100 Roff=2Meg vfwd=300m epsilon=100m vrev=100m revepsilon=-100m noiseless) +.model DLIM2 D(Ron=20 Roff=2Meg vfwd=30 epsilon=500m vrev=10 revepsilon=500m) +.model Dlowcur D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=150n revilimit=80n noiseless) +.model DLINK D(Ron=300k Roff=1G vfwd=1 epsilon=500m ilimit=4u noiseless) +.model pnpsrc pnp (is=1.48e-016 bf=457 nf=1 vaf=41 ikf=5.34e-005 ise=5e-017 ne=1.29 br=60 nr=1 var=8.3 ikr=2.9e-005 rb=650 irb=10 rbm=500 noiseless) +.ends LT6656-3.3 +* +.subckt LT6656-3 1 2 3 +C15 2 1 100f +C1 CORE 0 100f Rpar=1.2Meg noiseless +B1 0 CORE I=2.02867u+4.05e-12*V(2,1) +Q1 C1 B1 E1 0 PNPSRC M=40 temp=27 +B2 B1 1 I=260u*(.5+.5*tanh((V(on)-.5)/60m))*(.5+.5*tanh((-V(err)-80m)/100m)+.5+.5*tanh((-V(err)+130m)/20m))/dnlim(-4.1+5*dnlim(1.3333*V(2,E1),.1u,.1u)/dnlim(V(C1,C2),.1u,.1u),1,10m) +M1 1 N009 3 3 PSNK temp=27 +B3 N009 1 I=.1u*(.5+.5*tanh((V(on)-.5)/50m))*dnlim(uplim(V(err0A)-3.4,.7,.2)+uplim(.1*(V(err0A)-3.4),.3,.3),0,1e-3) +G1 0 N004 err0 0 1e-3 +L1 N004 0 1.346 Rser=1.18K Rpar=6.43K noiseless +C2 err0 0 450n Rpar=2Meg noiseless +G3 0 err N005 0 1µ +C3 err 0 3p Rpar=1Meg noiseless +G4 0 N005 N004 0 1m +L2 N005 0 60m Rser=1.13k Rpar=8.7k Cpar=191p noiseless +D1 3 1 DBGB +D2 2 B1 Dlowcur +R5 SEN 0 1Meg noiseless +B4 0 SEN I=.40583394u*V(3,1) +R2 2 E1 750m noiseless +B5 0 SEN I=25n*V(C1,C2) +C5 2 N003 100f +G2 err 0 N002 0 122µ +G5 0 N002 N003 1 1m +C7 N008 0 1p Rpar=2Meg noiseless +G6 0 err0A N008 0 1e-6 +L4 err0A 0 23.5 Cpar=127f Rser=1.18Meg Rpar=6.55Meg noiseless +C9 3 N009 5p Rpar=10Meg noiseless +D5 err0 0 DLIM1 +C13 3 1 1p Rpar=100Meg noiseless +B8 3 1 I=.4*V(3,1)*(.5+.5*tanh((V(on)-.5)/60m))*dnlim(.5u*(V(deltahysB)-1.5),0,10n) +D3 N007 err0 DLINK +G7 0 N007 N008 0 1m +C10 N007 0 800p Rpar=1k noiseless +C6 deltahysB 0 8n Rpar=1Meg noiseless +C14 N010 0 100p Rpar=1k noiseless +B11 0 N010 I=dnlim(uplim(-100m*V(err0)+29m,11m,.1m),0,.1m) +D6 N010 deltahysB D1wy +A3 2 1 0 0 0 0 On 0 SCHMITT vt=1.35 vh=0 trise=3m +S1 CORE 0 0 On SOFF +L3 N002 0 .31 Rser=1.56k Rpar=2.78k Cpar=7.96e-9 noiseless +C8 N003 1 5p Rpar=1Meg noiseless +D7 1 2 DREV +D8 1 3 DOUT +A4 Core Sen 0 0 0 0 err0 0 OTA g=1m linear en=2.2u vlow=-1e308 vhigh=1e308 +A1 Core Sen 0 0 0 0 N008 0 OTA g=1m linear en=2u vlow=-1e308 vhigh=1e308 +D9 N008 0 DLIM2 +D10 2 1 DBURN +R1 C2 3 10 noiseless +R3 C1 C2 1 noiseless +B6 3 C2 I=uplim(dnlim(140*V(C1,C2)-1.3m,100u,100u),8m,6m) +.model PSNK VDMOS(vto=-500m kp=34m pchan) +.model DBGB D(Ron=1k Roff=1G vfwd=600m epsilon=300m ilimit=400n noiseless) +.model Dout D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DREV D(Ron=50k Roff=1G vfwd=14 epsilon=3 noiseless) +.model SOFF SW(Ron=1k Roff=1.2Meg vt=-.4 vh=-.3 noiseless) +.model DBURN D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=.264u) +.model D1wy D(Ron=1K Roff=1G vfwd=1 epsilon=300m noiseless) +.model DLIM1 D(Ron=100 Roff=2Meg vfwd=300m epsilon=100m vrev=100m revepsilon=-100m noiseless) +.model DLIM2 D(Ron=20 Roff=2Meg vfwd=30 epsilon=500m vrev=10 revepsilon=500m) +.model Dlowcur D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=150n revilimit=80n noiseless) +.model DLINK D(Ron=300k Roff=1G vfwd=1 epsilon=500m ilimit=4u noiseless) +.model pnpsrc pnp (is=1.48e-016 bf=457 nf=1 vaf=41 ikf=5.34e-005 ise=5e-017 ne=1.29 br=60 nr=1 var=8.3 ikr=2.9e-005 rb=650 irb=10 rbm=500 noiseless) +.ends LT6656-3 +* +.subckt LT6656-4.096 1 2 3 +C15 2 1 100f +C1 CORE 0 100f Rpar=1.2Meg noiseless +B1 0 CORE I=2.02867u+4.05e-12*V(2,1) +Q1 C1 B1 E1 0 PNPSRC M=40 temp=27 +B2 B1 1 I=260u*(.5+.5*tanh((V(on)-.5)/60m))*(.5+.5*tanh((-V(err)-80m)/100m)+.5+.5*tanh((-V(err)+130m)/20m))/dnlim(-4.1+5*dnlim(1.3333*V(2,E1),.1u,.1u)/dnlim(V(C1,C2),.1u,.1u),1,10m) +M1 1 N009 3 3 PSNK temp=27 +B3 N009 1 I=.1u*(.5+.5*tanh((V(on)-.5)/50m))*dnlim(uplim(V(err0A)-3.4,.7,.2)+uplim(.1*(V(err0A)-3.4),.3,.3),0,1e-3) +G1 0 N004 err0 0 1e-3 +L1 N004 0 1.346 Rser=1.18K Rpar=6.43K noiseless +C2 err0 0 450n Rpar=2Meg noiseless +G3 0 err N005 0 1µ +C3 err 0 3p Rpar=1Meg noiseless +G4 0 N005 N004 0 1m +L2 N005 0 60m Rser=1.13k Rpar=8.7k Cpar=191p noiseless +D1 3 1 DBGB +D2 2 B1 Dlowcur +R5 SEN 0 1Meg noiseless +B4 0 SEN I=.2972424u*V(3,1) +R2 2 E1 750m noiseless +B5 0 SEN I=22.7n*V(C1,C2) +C5 2 N003 100f +G2 err 0 N002 0 164µ +G5 0 N002 N003 1 1m +C7 N008 0 1p Rpar=2Meg noiseless +G6 0 err0A N008 0 1e-6 +L4 err0A 0 23.5 Cpar=127f Rser=1.18Meg Rpar=6.55Meg noiseless +C9 3 N009 5p Rpar=10Meg noiseless +D5 err0 0 DLIM1 +C13 3 1 1p Rpar=100Meg noiseless +B8 3 1 I=.4*V(3,1)*(.5+.5*tanh((V(on)-.5)/60m))*dnlim(.5u*(V(deltahysB)-1.5),0,10n) +D3 N007 err0 DLINK +G7 0 N007 N008 0 1m +C10 N007 0 800p Rpar=1k noiseless +C6 deltahysB 0 8n Rpar=1Meg noiseless +C14 N010 0 100p Rpar=1k noiseless +B11 0 N010 I=dnlim(uplim(-100m*V(err0)+29m,11m,.1m),0,.1m) +D6 N010 deltahysB D1wy +A3 2 1 0 0 0 0 On 0 SCHMITT vt=1.35 vh=0 trise=3m +S1 CORE 0 0 On SOFF +L3 N002 0 .31 Rser=1.56k Rpar=2.78k Cpar=7.96e-9 noiseless +C8 N003 1 5p Rpar=1Meg noiseless +D7 1 2 DREV +D8 1 3 DOUT +A4 Core Sen 0 0 0 0 err0 0 OTA g=1m linear en=2.2u vlow=-1e308 vhigh=1e308 +A1 Core Sen 0 0 0 0 N008 0 OTA g=1m linear en=2u vlow=-1e308 vhigh=1e308 +D9 N008 0 DLIM2 +D10 2 1 DBURN +R1 C2 3 10 noiseless +R3 C1 C2 1 noiseless +B6 3 C2 I=uplim(dnlim(140*V(C1,C2)-1.3m,100u,100u),8m,6m) +.model PSNK VDMOS(vto=-500m kp=34m pchan) +.model DBGB D(Ron=1k Roff=1G vfwd=600m epsilon=300m ilimit=400n noiseless) +.model Dout D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DREV D(Ron=50k Roff=1G vfwd=14 epsilon=3 noiseless) +.model SOFF SW(Ron=1k Roff=1.2Meg vt=-.4 vh=-.3 noiseless) +.model DBURN D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=.264u) +.model D1wy D(Ron=1K Roff=1G vfwd=1 epsilon=300m noiseless) +.model DLIM1 D(Ron=100 Roff=2Meg vfwd=300m epsilon=100m vrev=100m revepsilon=-100m noiseless) +.model DLIM2 D(Ron=20 Roff=2Meg vfwd=30 epsilon=500m vrev=10 revepsilon=500m) +.model Dlowcur D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=150n revilimit=80n noiseless) +.model DLINK D(Ron=300k Roff=1G vfwd=1 epsilon=500m ilimit=4u noiseless) +.model pnpsrc pnp (is=1.48e-016 bf=457 nf=1 vaf=41 ikf=5.34e-005 ise=5e-017 ne=1.29 br=60 nr=1 var=8.3 ikr=2.9e-005 rb=650 irb=10 rbm=500 noiseless) +.ends LT6656-4.096 +* +.subckt LT6656-5 1 2 3 +C15 2 1 100f +C1 CORE 0 100f Rpar=1.2Meg noiseless +B1 0 CORE I=2.02867u+4.05e-12*V(2,1) +Q1 C1 B1 E1 0 PNPSRC M=40 temp=27 +B2 B1 1 I=260u*(.5+.5*tanh((V(on)-.5)/60m))*(.5+.5*tanh((-V(err)-80m)/100m)+.5+.5*tanh((-V(err)+130m)/20m))/dnlim(-4.1+5*dnlim(1.3333*V(2,E1),.1u,.1u)/dnlim(V(C1,C2),.1u,.1u),1,10m) +M1 1 N009 3 3 PSNK temp=27 +B3 N009 1 I=.1u*(.5+.5*tanh((V(on)-.5)/50m))*dnlim(uplim(V(err0A)-3.4,.7,.2)+uplim(.1*(V(err0A)-3.4),.3,.3),0,1e-3) +G1 0 N004 err0 0 1e-3 +L1 N004 0 1.346 Rser=1.18K Rpar=6.43K noiseless +C2 err0 0 450n Rpar=2Meg noiseless +G3 0 err N005 0 1µ +C3 err 0 3p Rpar=1Meg noiseless +G4 0 N005 N004 0 1m +L2 N005 0 60m Rser=1.13k Rpar=8.7k Cpar=191p noiseless +D1 3 1 DBGB +D2 2 B1 Dlowcur +R5 SEN 0 1Meg noiseless +B4 0 SEN I=.2435013u*V(3,1) +R2 2 E1 750m noiseless +B5 0 SEN I=22.7n*V(C1,C2) +C5 2 N003 100f +G2 err 0 N002 0 200µ +G5 0 N002 N003 1 1m +C7 N008 0 1p Rpar=2Meg noiseless +G6 0 err0A N008 0 1e-6 +L4 err0A 0 23.5 Cpar=127f Rser=1.18Meg Rpar=6.55Meg noiseless +C9 3 N009 5p Rpar=10Meg noiseless +D5 err0 0 DLIM1 +C13 3 1 1p Rpar=100Meg noiseless +B8 3 1 I=.4*V(3,1)*(.5+.5*tanh((V(on)-.5)/60m))*dnlim(.5u*(V(deltahysB)-1.5),0,10n) +D3 N007 err0 DLINK +G7 0 N007 N008 0 1m +C10 N007 0 800p Rpar=1k noiseless +C6 deltahysB 0 8n Rpar=1Meg noiseless +C14 N010 0 100p Rpar=1k noiseless +B11 0 N010 I=dnlim(uplim(-100m*V(err0)+29m,11m,.1m),0,.1m) +D6 N010 deltahysB D1wy +A3 2 1 0 0 0 0 On 0 SCHMITT vt=1.35 vh=0 trise=3m +S1 CORE 0 0 On SOFF +L3 N002 0 .31 Rser=1.56k Rpar=2.78k Cpar=7.96e-9 noiseless +C8 N003 1 5p Rpar=1Meg noiseless +D7 1 2 DREV +D8 1 3 DOUT +A4 Core Sen 0 0 0 0 err0 0 OTA g=1m linear en=2.2u vlow=-1e308 vhigh=1e308 +A1 Core Sen 0 0 0 0 N008 0 OTA g=1m linear en=2u vlow=-1e308 vhigh=1e308 +D9 N008 0 DLIM2 +D10 2 1 DBURN +R1 C2 3 10 noiseless +R3 C1 C2 1 noiseless +B6 3 C2 I=uplim(dnlim(140*V(C1,C2)-1.3m,100u,100u),8m,6m) +.model PSNK VDMOS(vto=-500m kp=34m pchan) +.model DBGB D(Ron=1k Roff=1G vfwd=600m epsilon=300m ilimit=400n noiseless) +.model Dout D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DREV D(Ron=50k Roff=1G vfwd=14 epsilon=3 noiseless) +.model SOFF SW(Ron=1k Roff=1.2Meg vt=-.4 vh=-.3 noiseless) +.model DBURN D(Ron=1k Roff=1G vfwd=600m epsilon=500m ilimit=.264u) +.model D1wy D(Ron=1K Roff=1G vfwd=1 epsilon=300m noiseless) +.model DLIM1 D(Ron=100 Roff=2Meg vfwd=300m epsilon=100m vrev=100m revepsilon=-100m noiseless) +.model DLIM2 D(Ron=20 Roff=2Meg vfwd=30 epsilon=500m vrev=10 revepsilon=500m) +.model Dlowcur D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=150n revilimit=80n noiseless) +.model DLINK D(Ron=300k Roff=1G vfwd=1 epsilon=500m ilimit=4u noiseless) +.model pnpsrc pnp (is=1.48e-016 bf=457 nf=1 vaf=41 ikf=5.34e-005 ise=5e-017 ne=1.29 br=60 nr=1 var=8.3 ikr=2.9e-005 rb=650 irb=10 rbm=500 noiseless) +.ends LT6656-5 diff --git a/spice/copy/sub/LT6657.lib b/spice/copy/sub/LT6657.lib new file mode 100755 index 0000000..f66e762 --- /dev/null +++ b/spice/copy/sub/LT6657.lib @@ -0,0 +1,420 @@ +* Copyright © Analog Devices 2018. All rights reserved. +* +.subckt LT6657-1.25 1 2 3 4 +C2 N004 0 200f Rpar=100K noiseless +R6 N003 0 500Meg noiseless +A2 0 N004 0 0 0 0 N003 0 OTA g=230u iout=30u Cout=25p en=30n enk=3 Vlow=0 Vhigh=2.5 +L1 ERREF 0 5.58m noiseless Rser=1.09k Rpar=12.111111k Cpar=1.23p +M1 N009 NG 4 4 NI temp=27 +D1 NG 4 DLIMN +M2 N007 PG SP SP PI temp=27 +D2 1 PG DLIMP +A1 ERROUT 3 4 4 4 4 PG 4 OTA g=50n ref=-60m linear vlow=-1e308 vhigh=1e308 +C4 3 4 1p Rpar=1G noiseless +D3 3 N009 DSBD +D4 N009 4 DBIAS +G5 1 PG 1 SP 1µ vto=30m dir=1 +G6 NG 4 N007 N009 20n vto=400m dir=1 +A3 ERROUT 3 4 4 4 4 NG 4 OTA g=50n linear ref=24m vlow=-1e308 vhigh=1e308 +G7 0 N004 CORE 3 10µ +C6 2 4 100f +C7 3 N009 100f +C11 N007 3 1p +C5 1 PG 4f Rser=300Meg noiseless +C10 NG 4 4f Rser=300Meg noiseless +B2 4 ERROUT I=1u*uplim(dnlim(V(ERREF),-100m,10m),V(1,4),100m) +B3 4 PGmax I=1u*dnlim(V(3,4),dnlim(V(1,4),1,.1),100m) +C9 PGmax 4 1p Rpar=1Meg noiseless +G3 PG 4 PG PGmax 100µ vto=100m dir=1 +G2 4 NG 4 NG 10µ vto=100m dir=1 +A4 2 4 0 0 0 SHDN 0 0 SCHMITT vt=1 vh=75m trise=1u +G4 4 PG HighZ 0 10µ vto=.5 dir=1 +G8 NG 4 HighZ 0 10µ vto=.5 dir=1 +C3 1 SP 100f Rpar=5 noiseless +C12 N009 4 1p Rpar=100Meg noiseless +C13 CORE 4 100f Rpar=600k noiseless +B4 4 CORE I=(.5+.5*tanh((V(1,4)-1.175)/50m))*2.0833512u+3e-13*V(1,4) +C14 1 CORE 2f +D5 2 4 Dshut +L2 ERROUT 4 .15 Rser=1.228Meg Rpar=5.384Meg noiseless +G9 4 N002 1 4 2m +C16 N002 CORE 4f +L3 N002 4 1.5m Rpar=8k Rser=100m noiseless +D6 N002 4 DCLMP +C17 N002 4 50p +BBURN 1 4 I=12m*Max(V(1,SP),0)*(1+V(SXX)) +G1 0 ERREF N003 0 1m +G12 ERROUT 4 ERROUT 3 1m vto=1 dir=1 +G13 4 ERROUT 3 ERROUT 1m vto=1 dir=1 +B5 4 PGMIN I=1m*(V(1,4)-2.8) +C18 PGMIN 4 1p Rpar=1k noiseless +D8 PGMIN PGmax DLIM1 +A6 4 3 4 4 4 4 PGmax 4 OTA g=70n asym isource=1u isink=-10u ref=0 vlow=-1e308 vhigh=1e308 +A5 4 3 0 0 0 0 SXX 0 OTA g=40u iout=10m ref=0 Rout=1k Cout=1p vlow=-1 vhigh=0 +A7 1 4 0 0 0 N001 0 0 SCHMITT vt=1 vh=0 trise=100n +A8 SHDN 0 0 N001 0 0 HighZ 0 OR trise=100n +B6 3 1 I=(.5+.5*tanh((V(4,1)-31.7)/1))*uplim(dnlim(19m*(V(3,4)-9.5),0,.1m),30m,1m) +C15 1 4 100f +B7 4 PG I=1m*MAX(V(SP,1)-1m,0) +S2 N007 3 0 SHDN2 SON +G11 0 SHDN2 SHDN 0 1m +C19 SHDN2 0 1p Rpar=2k noiseless +S4 SHDN2 0 4 3 SHUTOVRD +C1 1 3 1p Rpar=1G noiseless +BBURN2 1 4 I=MAX(0,uplim(220m*(V(1,SP)-1.85m),270u,160u)) +B8 1 4 I=10u*uplim(dnlim(V(2,4)-600m,0,50m),800m,100m) +B9 1 4 I=(662u+4.15u*TEMP)*tanh(dnlim(2*V(1,4)-600m,0,100m))*(.5+.5*tanh((V(SXX,SHDN)+.26)/80m)) +B1 3 N007 I=dnlim(uplim(3.2*V(1,SP)+5.9m,74m,15m),5.9m,1m)*(.5+.5*tanh((.2-V(SHDN2))/40m)) +G15 4 CORE SP 1 800p +G14 CORE 4 1 SP 1µ vto=35m dir=1 +G10 CORE 4 3 N009 .22n vto=300m dir=1 +.model NI VDMOS(Vto=300m kp=30m ksubthres=.1 mtriode=1.5 lambda=.001 is=0) +.model PI VDMOS(Vto=-300m Kp=30m ksubthres=.4 mtriode=2 lambda=.001 is=0 pchan) +.model SBURN SW(level=2 Ron=10 Roff=100G vt=-.5 vh=-.3 ilimit=.781m oneway epsilon=100m noiseless) +.model Dshut D(Ron=1Meg Rrev=330k Roff=1G vfwd=1.1 epsilon=500m Vrev=100m revepsilon=200m ilimit=6u noiseless) +.model DLIMN D(Ron=10k Roff=100Meg Vfwd=1.28 epsilon=500m noiseless) +.model DLIMP D(Ron=50k Roff=100Meg Vfwd=1.35 epsilon=500m noiseless) +.model DCLMP D(Ron=1 Roff=20k vfwd=200m epsilon=50m vrev=200m revepsilon=50m noiseless) +.model SON SW(Ron=1 Roff=1G vt=-.5 vh=-.3 noiseless) +.model DSBD D(Ron=40 Roff=1G vfwd=300m epsilon=100m noiseless) +.model DBIAS D(Ron=1k Roff=1G vfwd=300m epsilon=200m ilimit=10u noiseless) +.model DLIM1 D(Ron=1k Roff=1G vfwd=100m epsilon=50m noiseless) +.model SHUTOVRD SW(Ron=1 Roff=2k vt=3 vh=-1 noiseless) +.model SLD SW(Ron=100 Roff=1k vt=.5 vh=-.3 ilimit=5m noiseless) +.ends LT6657-1.25 +* +.subckt LT6657-2.5 1 2 3 4 +C2 N004 0 200f Rpar=100K noiseless +R6 N003 0 500Meg noiseless +A2 0 N004 0 0 0 0 N003 0 OTA g=230u iout=30u Cout=25p en=31.5n enk=1.5 Vlow=0 Vhigh=5 +L1 ERREF 0 5.58m noiseless Rser=1.09k Rpar=12.111111k Cpar=1.23p +M1 N009 NG 4 4 NI temp=27 +D1 NG 4 DLIMN +M2 N007 PG SP SP PI temp=27 +D2 1 PG DLIMP +A1 ERROUT 3 4 4 4 4 PG 4 OTA g=50n ref=-60m linear vlow=-1e308 vhigh=1e308 +C4 3 4 1p Rpar=1G noiseless +D3 3 N009 DSBD +D4 N009 4 DBIAS +G5 1 PG 1 SP 1µ vto=30m dir=1 +G6 NG 4 N007 N009 20n vto=400m dir=1 +A3 ERROUT 3 4 4 4 4 NG 4 OTA g=50n linear ref=24m vlow=-1e308 vhigh=1e308 +G7 0 N004 CORE FB 10µ +C6 2 4 100f +C7 3 N009 100f +C11 N007 3 1p +B1 3 N007 I=dnlim(uplim(3.2*V(1,SP)+5.9m,74m,15m),5.9m,1m)*(.5+.5*tanh((.2-V(SHDN2))/40m)) +C5 1 PG 4f Rser=300Meg noiseless +C10 NG 4 4f Rser=300Meg noiseless +B2 4 ERROUT I=1u*uplim(dnlim(V(ERREF),-100m,10m),V(1,4),100m) +B3 4 PGmax I=1u*dnlim(V(3,4),dnlim(V(1,4),1,.1),100m) +C9 PGmax 4 1p Rpar=1Meg noiseless +G3 PG 4 PG PGmax 100µ vto=100m dir=1 +G2 4 NG 4 NG 10µ vto=100m dir=1 +A4 2 4 0 0 0 SHDN 0 0 SCHMITT vt=1.185 vh=75m trise=1u +G4 4 PG HighZ 0 10µ vto=.5 dir=1 +G8 NG 4 HighZ 0 10µ vto=.5 dir=1 +C3 1 SP 100f Rpar=5 noiseless +C12 N009 4 1p Rpar=100Meg noiseless +C13 CORE 4 100f Rpar=600k noiseless +B4 4 CORE I=(.5+.5*tanh((V(1,4)-1.2)/50m))*2.033u+3e-13*V(1,4) +C14 1 CORE 2f +D5 2 4 Dshut +L2 ERROUT 4 .15 Rser=1.228Meg Rpar=5.384Meg noiseless +G9 4 N002 1 4 2m +C16 N002 CORE 4f +L3 N002 4 1.5m Rpar=8k Rser=100m noiseless +D6 N002 4 DCLMP +C17 N002 4 50p +BBURN 1 4 I=12m*Max(V(1,SP),0)*(1+V(SXX)) +G1 0 ERREF N003 0 1m +G12 ERROUT 4 ERROUT 3 1m vto=1 dir=1 +G13 4 ERROUT 3 ERROUT 1m vto=1 dir=1 +B5 4 PGMIN I=1m*(V(1,4)-2.8) +C18 PGMIN 4 1p Rpar=1k noiseless +D8 PGMIN PGmax DLIM1 +A6 4 3 4 4 4 4 PGmax 4 OTA g=70n asym isource=1u isink=-10u ref=0 vlow=-1e308 vhigh=1e308 +A5 4 3 0 0 0 0 SXX 0 OTA g=40u iout=10m ref=0 Rout=1k Cout=1p vlow=-1 vhigh=0 +A7 1 4 0 0 0 N001 0 0 SCHMITT vt=1 vh=0 trise=100n +A8 SHDN 0 0 N001 0 0 HighZ 0 OR trise=100n +B6 3 1 I=(.5+.5*tanh((V(4,1)-31.7)/1))*uplim(dnlim(19m*(V(3,4)-9.5),0,.1m),30m,1m) +C15 1 4 100f +B7 4 PG I=1m*MAX(V(SP,1)-1m,0) +R1 3 FB 10.495507k noiseless +R4 FB 4 10k noiseless +G10 CORE 4 3 N009 .22n vto=300m dir=1 +S2 N007 3 0 SHDN2 SON +G11 0 SHDN2 SHDN 0 1m +C19 SHDN2 0 1p Rpar=2k noiseless +S4 SHDN2 0 4 3 SHUTOVRD +C1 1 3 1p Rpar=1G noiseless +G15 4 CORE 1 SP 800p +BBURN2 1 4 I=MAX(0,uplim(220m*(V(1,SP)-1.85m),270u,160u)) +B8 1 4 I=10u*uplim(dnlim(V(2,4)-600m,0,50m),800m,100m) +B9 1 4 I=(662u+4.15u*TEMP)*tanh(dnlim(2*V(1,4)-600m,0,100m))*(.5+.5*tanh((V(SXX,SHDN)+.26)/80m)) +.model NI VDMOS(Vto=300m kp=30m ksubthres=.1 mtriode=1.5 lambda=.001 is=0) +.model PI VDMOS(Vto=-300m Kp=30m ksubthres=.4 mtriode=2 lambda=.001 is=0 pchan) +.model SBURN SW(level=2 Ron=10 Roff=100G vt=-.5 vh=-.3 ilimit=.781m oneway epsilon=100m noiseless) +.model Dshut D(Ron=1Meg Rrev=330k Roff=1G vfwd=1.1 epsilon=500m Vrev=100m revepsilon=200m ilimit=6u noiseless) +.model DLIMN D(Ron=10k Roff=100Meg Vfwd=1.28 epsilon=500m noiseless) +.model DLIMP D(Ron=50k Roff=100Meg Vfwd=1.35 epsilon=500m noiseless) +.model DCLMP D(Ron=1 Roff=20k vfwd=200m epsilon=50m vrev=200m revepsilon=50m noiseless) +.model SON SW(Ron=1 Roff=1G vt=-.5 vh=-.3 noiseless) +.model DSBD D(Ron=40 Roff=1G vfwd=300m epsilon=100m noiseless) +.model DBIAS D(Ron=1k Roff=1G vfwd=300m epsilon=200m ilimit=10u noiseless) +.model DLIM1 D(Ron=1k Roff=1G vfwd=100m epsilon=50m noiseless) +.model SHUTOVRD SW(Ron=1 Roff=2k vt=3 vh=-1 noiseless) +.model SLD SW(Ron=100 Roff=1k vt=.5 vh=-.3 ilimit=5m noiseless) +.ends LT6657-2.5 +* +.subckt LT6657-3 1 2 3 4 +C2 N004 0 200f Rpar=100K noiseless +R6 N003 0 500Meg noiseless +A2 0 N004 0 0 0 0 N003 0 OTA g=230u iout=30u Cout=25p en=31.5n enk=1.8 Vlow=0 Vhigh=6 +L1 ERREF 0 5.58m noiseless Rser=1.09k Rpar=12.111111k Cpar=1.23p +M1 N009 NG 4 4 NI temp=27 +D1 NG 4 DLIMN +M2 N007 PG SP SP PI temp=27 +D2 1 PG DLIMP +A1 ERROUT 3 4 4 4 4 PG 4 OTA g=50n ref=-60m linear vlow=-1e308 vhigh=1e308 +C4 3 4 1p Rpar=1G noiseless +D3 3 N009 DSBD +D4 N009 4 DBIAS +G5 1 PG 1 SP 1µ vto=30m dir=1 +G6 NG 4 N007 N009 20n vto=400m dir=1 +A3 ERROUT 3 4 4 4 4 NG 4 OTA g=50n linear ref=24m vlow=-1e308 vhigh=1e308 +G7 0 N004 CORE FB 10µ +C6 2 4 100f +C7 3 N009 100f +C11 N007 3 1p +B1 3 N007 I=dnlim(uplim(3.2*V(1,SP)+5.9m,74m,15m),5.9m,1m)*(.5+.5*tanh((.2-V(SHDN2))/40m)) +C5 1 PG 4f Rser=300Meg noiseless +C10 NG 4 4f Rser=300Meg noiseless +B2 4 ERROUT I=1u*uplim(dnlim(V(ERREF),-100m,10m),V(1,4),100m) +B3 4 PGmax I=1u*dnlim(V(3,4),dnlim(V(1,4),1,.1),100m) +C9 PGmax 4 1p Rpar=1Meg noiseless +G3 PG 4 PG PGmax 100µ vto=100m dir=1 +G2 4 NG 4 NG 10µ vto=100m dir=1 +A4 2 4 0 0 0 SHDN 0 0 SCHMITT vt=1.185 vh=75m trise=1u +G4 4 PG HighZ 0 10µ vto=.5 dir=1 +G8 NG 4 HighZ 0 10µ vto=.5 dir=1 +C3 1 SP 100f Rpar=5 noiseless +C12 N009 4 1p Rpar=100Meg noiseless +C13 CORE 4 100f Rpar=600k noiseless +B4 4 CORE I=(.5+.5*tanh((V(1,4)-1.2)/50m))*2.033u+3e-13*V(1,4) +C14 1 CORE 2f +D5 2 4 Dshut +L2 ERROUT 4 .15 Rser=1.228Meg Rpar=5.384Meg noiseless +G9 4 N002 1 4 2m +C16 N002 CORE 4f +L3 N002 4 1.5m Rpar=8k Rser=100m noiseless +D6 N002 4 DCLMP +C17 N002 4 50p +BBURN 1 4 I=12m*Max(V(1,SP),0)*(1+V(SXX)) +G1 0 ERREF N003 0 1m +G12 ERROUT 4 ERROUT 3 1m vto=1 dir=1 +G13 4 ERROUT 3 ERROUT 1m vto=1 dir=1 +B5 4 PGMIN I=1m*(V(1,4)-2.8) +C18 PGMIN 4 1p Rpar=1k noiseless +D8 PGMIN PGmax DLIM1 +A6 4 3 4 4 4 4 PGmax 4 OTA g=70n asym isource=1u isink=-10u ref=0 vlow=-1e308 vhigh=1e308 +A5 4 3 0 0 0 0 SXX 0 OTA g=40u iout=10m ref=0 Rout=1k Cout=1p vlow=-1 vhigh=0 +A7 1 4 0 0 0 N001 0 0 SCHMITT vt=1 vh=0 trise=100n +A8 SHDN 0 0 N001 0 0 HighZ 0 OR trise=100n +B6 3 1 I=(.5+.5*tanh((V(4,1)-31.7)/1))*uplim(dnlim(19m*(V(3,4)-9.5),0,.1m),30m,1m) +C15 1 4 100f +B7 4 PG I=1m*MAX(V(SP,1)-1m,0) +R1 3 FB 10.5k noiseless +R4 FB 4 7.1944k noiseless +G10 CORE 4 3 N009 .22n vto=300m dir=1 +S2 N007 3 0 SHDN2 SON +G11 0 SHDN2 SHDN 0 1m +C19 SHDN2 0 1p Rpar=2k noiseless +S4 SHDN2 0 4 3 SHUTOVRD +C1 1 3 1p Rpar=1G noiseless +G15 4 CORE 1 SP 800p +BBURN2 1 4 I=MAX(0,uplim(220m*(V(1,SP)-1.85m),270u,160u)) +B8 1 4 I=10u*uplim(dnlim(V(2,4)-600m,0,50m),800m,100m) +B9 1 4 I=(662u+4.15u*TEMP)*tanh(dnlim(2*V(1,4)-600m,0,100m))*(.5+.5*tanh((V(SXX,SHDN)+.26)/80m)) +.model NI VDMOS(Vto=300m kp=30m ksubthres=.1 mtriode=1.5 lambda=.001 is=0) +.model PI VDMOS(Vto=-300m Kp=30m ksubthres=.4 mtriode=2 lambda=.001 is=0 pchan) +.model SBURN SW(level=2 Ron=10 Roff=100G vt=-.5 vh=-.3 ilimit=.781m oneway epsilon=100m noiseless) +.model Dshut D(Ron=1Meg Rrev=330k Roff=1G vfwd=1.1 epsilon=500m Vrev=100m revepsilon=200m ilimit=6u noiseless) +.model DLIMN D(Ron=10k Roff=100Meg Vfwd=1.28 epsilon=500m noiseless) +.model DLIMP D(Ron=50k Roff=100Meg Vfwd=1.35 epsilon=500m noiseless) +.model DCLMP D(Ron=1 Roff=20k vfwd=200m epsilon=50m vrev=200m revepsilon=50m noiseless) +.model SON SW(Ron=1 Roff=1G vt=-.5 vh=-.3 noiseless) +.model DSBD D(Ron=40 Roff=1G vfwd=300m epsilon=100m noiseless) +.model DBIAS D(Ron=1k Roff=1G vfwd=300m epsilon=200m ilimit=10u noiseless) +.model DLIM1 D(Ron=1k Roff=1G vfwd=100m epsilon=50m noiseless) +.model SHUTOVRD SW(Ron=1 Roff=2k vt=3 vh=-1 noiseless) +.model SLD SW(Ron=100 Roff=1k vt=.5 vh=-.3 ilimit=5m noiseless) +.ends LT6657-3 +* +.subckt LT6657-4.096 1 2 3 4 +C2 N004 0 200f Rpar=100K noiseless +R6 N003 0 500Meg noiseless +A2 0 N004 0 0 0 0 N003 0 OTA g=230u iout=30u Cout=25p en=31.5n enk=2.5 Vlow=0 Vhigh=8 +L1 ERREF 0 5.58m noiseless Rser=1.09k Rpar=12.111111k Cpar=1.23p +M1 N009 NG 4 4 NI temp=27 +D1 NG 4 DLIMN +M2 N007 PG SP SP PI temp=27 +D2 1 PG DLIMP +A1 ERROUT 3 4 4 4 4 PG 4 OTA g=50n ref=-60m linear vlow=-1e308 vhigh=1e308 +C4 3 4 1p Rpar=1G noiseless +D3 3 N009 DSBD +D4 N009 4 DBIAS +G5 1 PG 1 SP 1µ vto=30m dir=1 +G6 NG 4 N007 N009 20n vto=400m dir=1 +A3 ERROUT 3 4 4 4 4 NG 4 OTA g=50n linear ref=24m vlow=-1e308 vhigh=1e308 +G7 0 N004 CORE FB 10µ +C6 2 4 100f +C7 3 N009 100f +C11 N007 3 1p +B1 3 N007 I=dnlim(uplim(3.2*V(1,SP)+5.9m,74m,15m),5.9m,1m)*(.5+.5*tanh((.2-V(SHDN2))/40m)) +C5 1 PG 4f Rser=300Meg noiseless +C10 NG 4 4f Rser=300Meg noiseless +B2 4 ERROUT I=1u*uplim(dnlim(V(ERREF),-100m,10m),V(1,4),100m) +B3 4 PGmax I=1u*dnlim(V(3,4),dnlim(V(1,4),1,.1),100m) +C9 PGmax 4 1p Rpar=1Meg noiseless +G3 PG 4 PG PGmax 100µ vto=100m dir=1 +G2 4 NG 4 NG 10µ vto=100m dir=1 +A4 2 4 0 0 0 SHDN 0 0 SCHMITT vt=1.185 vh=75m trise=1u +G4 4 PG HighZ 0 10µ vto=.5 dir=1 +G8 NG 4 HighZ 0 10µ vto=.5 dir=1 +C3 1 SP 100f Rpar=5 noiseless +C12 N009 4 1p Rpar=100Meg noiseless +C13 CORE 4 100f Rpar=600k noiseless +B4 4 CORE I=(.5+.5*tanh((V(1,4)-1.2)/50m))*2.033u+3e-13*V(1,4) +C14 1 CORE 2f +D5 2 4 Dshut +L2 ERROUT 4 .15 Rser=1.228Meg Rpar=5.384Meg noiseless +G9 4 N002 1 4 2m +C16 N002 CORE 4f +L3 N002 4 1.5m Rpar=8k Rser=100m noiseless +D6 N002 4 DCLMP +C17 N002 4 50p +BBURN 1 4 I=12m*Max(V(1,SP),0)*(1+V(SXX)) +G1 0 ERREF N003 0 1m +G12 ERROUT 4 ERROUT 3 1m vto=1 dir=1 +G13 4 ERROUT 3 ERROUT 1m vto=1 dir=1 +B5 4 PGMIN I=1m*(V(1,4)-2.8) +C18 PGMIN 4 1p Rpar=1k noiseless +D8 PGMIN PGmax DLIM1 +A6 4 3 4 4 4 4 PGmax 4 OTA g=70n asym isource=1u isink=-10u ref=0 vlow=-1e308 vhigh=1e308 +A5 4 3 0 0 0 0 SXX 0 OTA g=40u iout=10m ref=0 Rout=1k Cout=1p vlow=-1 vhigh=0 +A7 1 4 0 0 0 N001 0 0 SCHMITT vt=1 vh=0 trise=100n +A8 SHDN 0 0 N001 0 0 HighZ 0 OR trise=100n +B6 3 1 I=(.5+.5*tanh((V(4,1)-31.7)/1))*uplim(dnlim(19m*(V(3,4)-9.5),0,.1m),30m,1m) +C15 1 4 100f +B7 4 PG I=1m*MAX(V(SP,1)-1m,0) +R1 3 FB 10.5k noiseless +R4 FB 4 4.4528984k noiseless +G10 CORE 4 3 N009 .36n vto=300m dir=1 +S2 N007 3 0 SHDN2 SON +G11 0 SHDN2 SHDN 0 1m +C19 SHDN2 0 1p Rpar=2k noiseless +S4 SHDN2 0 4 3 SHUTOVRD +C1 1 3 1p Rpar=1G noiseless +G15 4 CORE 1 SP 1310p +BBURN2 1 4 I=MAX(0,uplim(220m*(V(1,SP)-1.85m),270u,160u)) +B8 1 4 I=10u*uplim(dnlim(V(2,4)-600m,0,50m),800m,100m) +B9 1 4 I=(662u+4.15u*TEMP)*tanh(dnlim(2*V(1,4)-600m,0,100m))*(.5+.5*tanh((V(SXX,SHDN)+.26)/80m)) +.model NI VDMOS(Vto=300m kp=30m ksubthres=.1 mtriode=1.5 lambda=.001 is=0) +.model PI VDMOS(Vto=-300m Kp=30m ksubthres=.4 mtriode=2 lambda=.001 is=0 pchan) +.model SBURN SW(level=2 Ron=10 Roff=100G vt=-.5 vh=-.3 ilimit=.781m oneway epsilon=100m noiseless) +.model Dshut D(Ron=1Meg Rrev=330k Roff=1G vfwd=1.1 epsilon=500m Vrev=100m revepsilon=200m ilimit=6u noiseless) +.model DLIMN D(Ron=10k Roff=100Meg Vfwd=1.28 epsilon=500m noiseless) +.model DLIMP D(Ron=50k Roff=100Meg Vfwd=1.35 epsilon=500m noiseless) +.model DCLMP D(Ron=1 Roff=20k vfwd=200m epsilon=50m vrev=200m revepsilon=50m noiseless) +.model SON SW(Ron=1 Roff=1G vt=-.5 vh=-.3 noiseless) +.model DSBD D(Ron=40 Roff=1G vfwd=300m epsilon=100m noiseless) +.model DBIAS D(Ron=1k Roff=1G vfwd=300m epsilon=200m ilimit=10u noiseless) +.model DLIM1 D(Ron=1k Roff=1G vfwd=100m epsilon=50m noiseless) +.model SHUTOVRD SW(Ron=1 Roff=2k vt=3 vh=-1 noiseless) +.model SLD SW(Ron=100 Roff=10k vt=.5 vh=-.3 ilimit=5m noiseless) +.ends LT6657-4.096 +* +.subckt LT6657-5 1 2 3 4 +C2 N004 0 200f Rpar=100K noiseless +R6 N003 0 500Meg noiseless +A2 0 N004 0 0 0 0 N003 0 OTA g=230u iout=30u Cout=25p en=31.5n enk=3 Vlow=0 Vhigh=10 +L1 ERREF 0 5.58m noiseless Rser=1.09k Rpar=12.111111k Cpar=1.23p +M1 N009 NG 4 4 NI temp=27 +D1 NG 4 DLIMN +M2 N007 PG SP SP PI temp=27 +D2 1 PG DLIMP +A1 ERROUT 3 4 4 4 4 PG 4 OTA g=50n ref=-60m linear vlow=-1e308 vhigh=1e308 +C4 3 4 1p Rpar=1G noiseless +D3 3 N009 DSBD +D4 N009 4 DBIAS +G5 1 PG 1 SP 1µ vto=30m dir=1 +G6 NG 4 N007 N009 20n vto=400m dir=1 +A3 ERROUT 3 4 4 4 4 NG 4 OTA g=50n linear ref=24m vlow=-1e308 vhigh=1e308 +G7 0 N004 CORE FB 10µ +C6 2 4 100f +C7 3 N009 100f +C11 N007 3 1p +B1 3 N007 I=dnlim(uplim(3.2*V(1,SP)+5.9m,74m,15m),5.9m,1m)*(.5+.5*tanh((.2-V(SHDN2))/40m)) +C5 1 PG 4f Rser=300Meg noiseless +C10 NG 4 4f Rser=300Meg noiseless +B2 4 ERROUT I=1u*uplim(dnlim(V(ERREF),-100m,10m),V(1,4),100m) +B3 4 PGmax I=1u*dnlim(V(3,4),dnlim(V(1,4),1,.1),100m) +C9 PGmax 4 1p Rpar=1Meg noiseless +G3 PG 4 PG PGmax 100µ vto=100m dir=1 +G2 4 NG 4 NG 10µ vto=100m dir=1 +A4 2 4 0 0 0 SHDN 0 0 SCHMITT vt=1.185 vh=75m trise=1u +G4 4 PG HighZ 0 10µ vto=.5 dir=1 +G8 NG 4 HighZ 0 10µ vto=.5 dir=1 +C3 1 SP 100f Rpar=5 noiseless +C12 N009 4 1p Rpar=100Meg noiseless +C13 CORE 4 100f Rpar=600k noiseless +B4 4 CORE I=(.5+.5*tanh((V(1,4)-1.2)/50m))*2.033u+3e-13*V(1,4) +C14 1 CORE 2f +D5 2 4 Dshut +L2 ERROUT 4 .15 Rser=1.228Meg Rpar=5.384Meg noiseless +G9 4 N002 1 4 2m +C16 N002 CORE 4f +L3 N002 4 1.5m Rpar=8k Rser=100m noiseless +D6 N002 4 DCLMP +C17 N002 4 50p +BBURN 1 4 I=12m*Max(V(1,SP),0)*(1+V(SXX)) +G1 0 ERREF N003 0 1m +G12 ERROUT 4 ERROUT 3 1m vto=1 dir=1 +G13 4 ERROUT 3 ERROUT 1m vto=1 dir=1 +B5 4 PGMIN I=1m*(V(1,4)-2.8) +C18 PGMIN 4 1p Rpar=1k noiseless +D8 PGMIN PGmax DLIM1 +A6 4 3 4 4 4 4 PGmax 4 OTA g=70n asym isource=1u isink=-10u ref=0 vlow=-1e308 vhigh=1e308 +A5 4 3 0 0 0 0 SXX 0 OTA g=40u iout=10m ref=0 Rout=1k Cout=1p vlow=-1 vhigh=0 +A7 1 4 0 0 0 N001 0 0 SCHMITT vt=1 vh=0 trise=100n +A8 SHDN 0 0 N001 0 0 HighZ 0 OR trise=100n +B6 3 1 I=(.5+.5*tanh((V(4,1)-31.7)/1))*uplim(dnlim(19m*(V(3,4)-9.5),0,.1m),30m,1m) +C15 1 4 100f +B7 4 PG I=1m*MAX(V(SP,1)-1m,0) +R1 3 FB 10.5k noiseless +R4 FB 4 3.388k noiseless +G10 CORE 4 3 N009 .44n vto=300m dir=1 +S2 N007 3 0 SHDN2 SON +G11 0 SHDN2 SHDN 0 1m +C19 SHDN2 0 1p Rpar=2k noiseless +S4 SHDN2 0 4 3 SHUTOVRD +C1 1 3 1p Rpar=1G noiseless +G15 4 CORE 1 SP 1600p +BBURN2 1 4 I=MAX(0,uplim(220m*(V(1,SP)-1.85m),270u,160u)) +B8 1 4 I=10u*uplim(dnlim(V(2,4)-600m,0,50m),800m,100m) +B9 1 4 I=(662u+4.15u*TEMP)*tanh(dnlim(2*V(1,4)-600m,0,100m))*(.5+.5*tanh((V(SXX,SHDN)+.26)/80m)) +.model NI VDMOS(Vto=300m kp=30m ksubthres=.1 mtriode=1.5 lambda=.001 is=0) +.model PI VDMOS(Vto=-300m Kp=30m ksubthres=.4 mtriode=2 lambda=.001 is=0 pchan) +.model SBURN SW(level=2 Ron=10 Roff=100G vt=-.5 vh=-.3 ilimit=.781m oneway epsilon=100m noiseless) +.model Dshut D(Ron=1Meg Rrev=330k Roff=1G vfwd=1.1 epsilon=500m Vrev=100m revepsilon=200m ilimit=6u noiseless) +.model DLIMN D(Ron=10k Roff=100Meg Vfwd=1.28 epsilon=500m noiseless) +.model DLIMP D(Ron=50k Roff=100Meg Vfwd=1.35 epsilon=500m noiseless) +.model DCLMP D(Ron=1 Roff=20k vfwd=200m epsilon=50m vrev=200m revepsilon=50m noiseless) +.model SON SW(Ron=1 Roff=1G vt=-.5 vh=-.3 noiseless) +.model DSBD D(Ron=40 Roff=1G vfwd=300m epsilon=100m noiseless) +.model DBIAS D(Ron=1k Roff=1G vfwd=300m epsilon=200m ilimit=10u noiseless) +.model DLIM1 D(Ron=1k Roff=1G vfwd=100m epsilon=50m noiseless) +.model SHUTOVRD SW(Ron=1 Roff=2k vt=3 vh=-1 noiseless) +.model SLD SW(Ron=100 Roff=10k vt=.5 vh=-.3 ilimit=5m noiseless) +.ends LT6657-5 diff --git a/spice/copy/sub/LT6658.lib b/spice/copy/sub/LT6658.lib new file mode 100755 index 0000000..2492178 --- /dev/null +++ b/spice/copy/sub/LT6658.lib @@ -0,0 +1,783 @@ +* Copyright © Analog Devices 2018. All rights reserved. +* +.subckt LT6658-1.2 1 2 3 4 5 6 7 8 9 10 11 +A3 11 INM1 10 10 10 10 N002 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-13 Vhigh=1 +R2 7 INM1 768 noiseless +C1 6 N002 38p Rser=20k noiseless +C2 2 6 100f Rpar=1g noiseless +C3 6 10 100f Rpar=1g noiseless +Q1 S1 N004 6 0 NPN1 temp=27 +Q2 C2_1 N008 10 0 NPN1 temp=27 +C5 N003 10 1p Rpar=3k noiseless +C6 6 C2_1 100f Rpar=1 noiseless +C11 N008 10 100f Rpar=5k noiseless +C15 N002 10 10f +R5 2 S1 3.4 noiseless +D1 N003 N004 DILIM1 +G3 10 Vout1DRV 10 N002 1m +L1 Vout1DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C4 2 N004 1p +G1 0 N009 2 10 1m +B6 10 BGREF I=(.5+.5*tanh((V(1,10)-3.45)/10m))*1.251254u +C18 INM1 10 100f +C19 7 10 100f +B7 10 N008 I=uplim(dnlim(500u*(V(6,Vout1DRV)-20*V(6,C2_1)),130u,10u),800u,100u) +B5 10 N003 I=(.5+.5*tanh((V(On)-.8)/10m))*uplim(333.33u*(V(Vout1DRV,10)+580m),667u*V(2,10)+2m,10u) +D4 10 6 DSUB +D5 10 7 DSUB +D6 10 1 DSUB +D7 10 2 DSUB +D11 10 4 DSUB +A5 11 INM2 10 10 10 10 N015 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-10 Vhigh=1 +R6 9 INM2 768 noiseless +C22 8 N015 38p Rser=20k noiseless +C23 3 8 100f Rpar=1g noiseless +C24 8 10 100f Rpar=1g noiseless +Q3 S2 N017 8 0 NPN1 temp=27 +Q4 C2_2 N019 10 0 NPN1 temp=27 +C25 N016 10 1p Rpar=3k noiseless +C26 8 C2_2 100f Rpar=1 noiseless +C27 N019 10 100f Rpar=5k noiseless +C28 N015 10 10f +R9 3 S2 9 noiseless +S2 N017 10 8 S2 SDRP2 +D12 N016 N017 DILIM2 +G9 10 Vout2DRV 10 N015 1m +L6 Vout2DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C29 3 N017 1p +C30 INM2 10 100f +C31 9 10 100f +B1 10 N019 I=uplim(dnlim(500u*(V(8,Vout2DRV)-35*V(8,C2_2)),130u,10u),800u,100u) +B2 10 N016 I=(.5+.5*tanh((V(On)-.8)/100m))*uplim(333.33u*(V(Vout2DRV,10)+580m),667u*V(3,10)+2m,10u) +D13 10 8 DSUB +D14 10 9 DSUB +D15 10 3 DSUB +S3 N011 1 10 N011 S2V +C32 N011 10 100f Rpar=1Meg noiseless +D16 N011 4 DOD1 +D17 1 10 DBurnBG1 +D18 1 10 DBurnBG2 +S4 10 2 On 0 Sburn1 +S6 10 2 On 0 Sburn2 +S5 10 3 On 0 Sburn1 +S7 10 3 On 0 Sburn2 +B3 10 N008 I=(.5+.5*tanh((.9-V(On))/10m))*60u +B4 10 N019 I=(.5+.5*tanh((.9-V(On))/10m))*60u +A6 4 10 0 0 0 0 On 0 SCHMITT vt=1.4 vh=0 Rhigh=100k Rlow=1.5Meg Cout=100p +R10 BGREF 10 1Meg tc=1e-6,0,8e-11 noiseless +A2 5 BGREF 0 0 0 0 N025 0 OTA g=10u linear en=50n enk=2 Vlow=-1e308 Vhigh=1e308 +M3 1 N023 5 5 NBG temp=27 +M4 10 N023 5 5 PBG temp=27 +C33 1 5 1p +C34 5 10 1p +G17 10 N023 N024 10 1µ +C35 N023 10 100f Rpar=1Meg noiseless +C36 5 N024 12p Rser=280k noiseless +D21 10 5 DSUB +G18 10 N024 N025 0 50µ +C37 N024 10 5p Rser=1 noiseless +C38 N025 0 5p Rser=1k Rpar=100K noiseless +D22 N024 10 DBGLIM +R11 11 5 400 noiseless +D23 10 11 DSUB +A7 10 11 10 10 10 10 10 10 OTA g=0 linear in=170p/(1+freq/200k) vlow=-1e308 vhigh=1e308 +C39 11 10 100f +G5 0 N009 3 0 10µ +G10 10 0 3 10 1n +G2 N002 10 3 10 50p +G20 N015 10 2A 10 50p +A1 2 S1 10 10 10 10 N002 10 OTA g=160n iout=1u vlow=-1e308 vhigh=1e308 +A4 3 S2 10 10 10 10 N015 10 OTA g=70n iout=1u vlow=-1e308 vhigh=1e308 +G6 10 0 2A 0 500p +G19 0 2A 2 0 1 +L2 2A 0 795µ Rser=1 Rpar=5k noiseless +R1 11 10 9600 noiseless +L3 N009 0 132m Rser=1k Rpar=833k noiseless +L4 N010 0 79.8m Rser=1k Rpar=500k noiseless +G4 10 N023 0 N027 30n +G8 0 N010 N009 0 4.5µ +D2 N023 5 Y +D3 5 N023 Y +G11 0 N020 3 10 1m +G13 0 N020 2 0 10µ +L8 N020 0 26.6m Rser=1k Rpar=166k Cpar=10f noiseless +G16 0 N021 N020 0 4.5µ +G7 0 N026 1 10 100µ +G12 0 N027 N026 0 1m +L5 N026 0 2.66 Rser=10 Rpar=3.33k noiseless +S1 N004 10 6 S1 SDRP1 +G14 10 N002 0 N010 1µ +G15 10 N015 0 N021 1µ +C7 N009 0 1p Rser=10k noiseless +L7 N027 0 2.66 Rser=10 Rpar=3.33k noiseless +L9 N021 0 26.6m Rser=1k Rpar=166k Cpar=10f noiseless +C8 N021 N020 5p Rser=1 noiseless +.model NPN1 NPN(IS=1E-14 VAF=100 BF=80 BR=1 ISC=1e-11 NC=2 IKR=15m CJC=100f CJE=100f noiseless) +.model DILIM1 D(Ron=50 Roff=50 ilimit=2.5m noiseless) +.model DILIM2 D(Ron=50 Roff=50 ilimit=1.47m noiseless) +.model DSUB D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBGLIM D(Ron=10 Roff=20Meg vfwd=6.5 epsilon=500m vrev=-1 revepsilon=500m noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=740m epsilon=100m noiseless) +.model NBG VDMOS(Vto=-100m Kp=80m noiseless) +.model PBG VDMOS(Vto=100m Kp=80m pchan noiseless) +.model SDRP1 SW(Ron=1 Roff=1Meg vt=-1.44 vh=-300m noiseless) +.model SDRP2 SW(Ron=1 Roff=1Meg vt=-1.34 vh=-300m noiseless) +.model S2V SW(level=2 Ron=1k Roff=1G vt=-2 vh=-20m noiseless) +.model DOD1 D(Ron=59.4k Roff=1G vfwd=200m epsilon=10m noiseless) +.model DBurnBG1 D(Ron=100 Roff=1G vfwd=0 epsilon=1 ilimit=569u noiseless) +.model DBurnBG2 D(Ron=700k Roff=1G vfwd=1 epsilon=1 noiseless) +.model Sburn1 SW(Ron=1k Roff=1G vt=.5 vh=-200m ilimit=97u noiseless) +.model Sburn2 SW(Ron=700k Roff=1G vt=.5 vh=-200m noiseless) +.ends LT6658-1.2 +* +.subckt LT6658-1.8 1 2 3 4 5 6 7 8 9 10 11 +A3 11 INM1 10 10 10 10 N002 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-13 Vhigh=1 +R2 7 INM1 768 noiseless +C1 6 N002 38p Rser=20k noiseless +C2 2 6 100f Rpar=1g noiseless +C3 6 10 100f Rpar=1g noiseless +Q1 S1 N004 6 0 NPN1 temp=27 +Q2 C2_1 N008 10 0 NPN1 temp=27 +C5 N003 10 1p Rpar=3k noiseless +C6 6 C2_1 100f Rpar=1 noiseless +C11 N008 10 100f Rpar=5k noiseless +C15 N002 10 10f +R5 2 S1 3.4 noiseless +S1 N004 10 6 S1 SDRP1 +D1 N003 N004 DILIM1 +G3 10 Vout1DRV 10 N002 1m +L1 Vout1DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C4 2 N004 1p +B6 10 BGREF I=(.5+.5*tanh((V(1,10)-3.45)/10m))*2.050103u +C18 INM1 10 100f +C19 7 10 100f +B7 10 N008 I=uplim(dnlim(500u*(V(6,Vout1DRV)-20*V(6,C2_1)),130u,10u),800u,100u) +B5 10 N003 I=(.5+.5*tanh((V(On)-.8)/10m))*uplim(333.33u*(V(Vout1DRV,10)+580m),667u*V(2,10)+2m,10u) +D4 10 6 DSUB +D5 10 7 DSUB +D6 10 1 DSUB +D7 10 2 DSUB +D11 10 4 DSUB +A5 11 INM2 10 10 10 10 N015 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-10 Vhigh=1 +R6 9 INM2 768 noiseless +C22 8 N015 38p Rser=20k noiseless +C23 3 8 100f Rpar=1g noiseless +C24 8 10 100f Rpar=1g noiseless +Q3 S2 N017 8 0 NPN1 temp=27 +Q4 C2_2 N019 10 0 NPN1 temp=27 +C25 N016 10 1p Rpar=3k noiseless +C26 8 C2_2 100f Rpar=1 noiseless +C27 N019 10 100f Rpar=5k noiseless +C28 N015 10 10f +R9 3 S2 9 noiseless +S2 N017 10 8 S2 SDRP2 +D12 N016 N017 DILIM2 +G9 10 Vout2DRV 10 N015 1m +L6 Vout2DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C29 3 N017 1p +C30 INM2 10 100f +C31 9 10 100f +B1 10 N019 I=uplim(dnlim(500u*(V(8,Vout2DRV)-35*V(8,C2_2)),130u,10u),800u,100u) +B2 10 N016 I=(.5+.5*tanh((V(On)-.8)/100m))*uplim(333.33u*(V(Vout2DRV,10)+580m),667u*V(3,10)+2m,10u) +D13 10 8 DSUB +D14 10 9 DSUB +D15 10 3 DSUB +S3 N010 1 10 N010 S2V +C32 N010 10 100f Rpar=1Meg noiseless +D16 N010 4 DOD1 +D17 1 10 DBurnBG1 +D18 1 10 DBurnBG2 +S4 10 2 On 0 Sburn1 +S6 10 2 On 0 Sburn2 +S5 10 3 On 0 Sburn1 +S7 10 3 On 0 Sburn2 +B3 10 N008 I=(.5+.5*tanh((.9-V(On))/10m))*60u +B4 10 N019 I=(.5+.5*tanh((.9-V(On))/10m))*60u +A6 4 10 0 0 0 0 On 0 SCHMITT vt=1.4 vh=0 Rhigh=100k Rlow=1.5Meg Cout=100p +R10 BGREF 10 1Meg tc=0,-2e-8,8e-11 noiseless +A2 5 BGREF 0 0 0 0 N025 0 OTA g=10u linear en=100n enk=2 Vlow=-1e308 Vhigh=1e308 +M3 1 N023 5 5 NBG temp=27 +M4 10 N023 5 5 PBG temp=27 +C33 1 5 1p +C34 5 10 1p +G17 10 N023 N024 10 1µ +C35 N023 10 100f Rpar=1Meg noiseless +C36 5 N024 20p Rser=280k noiseless +D21 10 5 DSUB +G18 10 N024 N025 0 50µ +C37 N024 10 5p Rser=1 noiseless +C38 N025 0 5p Rser=1k Rpar=100K noiseless +D22 N024 10 DBGLIM +R11 11 5 400 noiseless +D23 10 11 DSUB +A7 10 11 10 10 10 10 10 10 OTA g=0 linear in=170p/(1+freq/200k) vlow=-1e308 vhigh=1e308 +C39 11 10 100f +G10 10 0 3 10 1n +G2 N002 10 3 10 50p +G20 N015 10 2A 10 50p +A1 2 S1 10 10 10 10 N002 10 OTA g=160n iout=1u vlow=-1e308 vhigh=1e308 +A4 3 S2 10 10 10 10 N015 10 OTA g=70n iout=1u vlow=-1e308 vhigh=1e308 +G6 10 0 2A 0 500p +G19 0 2A 2 0 1 +L2 2A 0 795µ Rser=1 Rpar=5k noiseless +R1 11 10 2903 noiseless +D2 N023 5 Y +D3 5 N023 Y +L3 N009 0 79.7m Rser=1k Rpar=500k noiseless +G1 0 N009 N011 0 4.5µ +G5 10 N002 0 N009 1µ +G7 0 N011 2 10 1m +G8 0 N011 3 0 10µ +L4 N011 0 88.6m Rser=1k Rpar=555k noiseless +L7 N021 0 26.6m Rser=1k Rpar=166k Cpar=10f noiseless +G11 0 N021 N020 0 4.5µ +G12 10 N015 0 N021 1µ +G13 0 N020 3 10 1m +G16 0 N020 2 0 10µ +G4 10 N023 0 BVPSRRN 30n +G14 0 N027 1 10 100µ +G15 0 BVPSRRN N027 0 1m +L5 N027 0 2.66 Rser=10 Rpar=3.33k noiseless +L9 BVPSRRN 0 2.66 Rser=10 Rpar=3.33k noiseless +L8 N020 0 26.6m Rser=1k Rpar=166k Cpar=10f noiseless +.model NPN1 NPN(IS=1E-14 VAF=100 BF=80 BR=1 ISC=1e-11 NC=2 IKR=15m CJC=100f CJE=100f noiseless) +.model DILIM1 D(Ron=50 Roff=50 ilimit=2.5m noiseless) +.model DILIM2 D(Ron=50 Roff=50 ilimit=1.47m noiseless) +.model DSUB D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBGLIM D(Ron=10 Roff=20Meg vfwd=6.5 epsilon=500m vrev=-1 revepsilon=500m noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=740m epsilon=100m noiseless) +.model NBG VDMOS(Vto=-100m Kp=80m noiseless) +.model PBG VDMOS(Vto=100m Kp=80m pchan noiseless) +.model SDRP1 SW(Ron=1 Roff=1Meg vt=-1.44 vh=-300m noiseless) +.model SDRP2 SW(Ron=1 Roff=1Meg vt=-1.34 vh=-300m noiseless) +.model S2V SW(level=2 Ron=1k Roff=1G vt=-2 vh=-20m noiseless) +.model DOD1 D(Ron=59.4k Roff=1G vfwd=200m epsilon=10m noiseless) +.model DBurnBG1 D(Ron=100 Roff=1G vfwd=0 epsilon=1 ilimit=569u noiseless) +.model DBurnBG2 D(Ron=700k Roff=1G vfwd=1 epsilon=1 noiseless) +.model Sburn1 SW(Ron=1k Roff=1G vt=.5 vh=-200m ilimit=97u noiseless) +.model Sburn2 SW(Ron=700k Roff=1G vt=.5 vh=-200m noiseless) +.ends LT6658-1.8 +* +.subckt LT6658-2.5 1 2 3 4 5 6 7 8 9 10 11 +A3 11 INM1 10 10 10 10 N002 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-13 Vhigh=1 +R2 7 INM1 800 noiseless +C1 6 N002 38p Rser=20k noiseless +C2 2 6 100f Rpar=1g noiseless +C3 6 10 100f Rpar=1g noiseless +Q1 S1 N004 6 0 NPN1 temp=27 +Q2 C2_1 N008 10 0 NPN1 temp=27 +C5 N003 10 1p Rpar=3k noiseless +C6 6 C2_1 100f Rpar=1 noiseless +C11 N008 10 100f Rpar=5k noiseless +C15 N002 10 10f +R5 2 S1 3.4 noiseless +S1 N004 10 6 S1 SDRP1 +D1 N003 N004 DILIM1 +G3 10 Vout1DRV 10 N002 1m +L1 Vout1DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C4 2 N004 1p +G1 0 N009 2 10 1m +G7 0 N010 N009 0 1m +B6 10 BGREF I=(.5+.5*tanh((V(1,10)-3.45)/10m))*2.5025u +C18 INM1 10 100f +C19 7 10 100f +B7 10 N008 I=uplim(dnlim(500u*(V(6,Vout1DRV)-70*V(6,C2_1)),130u,10u),800u,100u) +B5 10 N003 I=(.5+.5*tanh((V(On)-.8)/10m))*uplim(333.33u*(V(Vout1DRV,10)+580m),667u*V(2,10)+2m,10u) +D4 10 6 DSUB +D5 10 7 DSUB +D6 10 1 DSUB +D7 10 2 DSUB +D11 10 4 DSUB +A5 11 INM2 10 10 10 10 N015 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-10 Vhigh=1 +R6 9 INM2 800 noiseless +C22 8 N015 38p Rser=20k noiseless +C23 3 8 100f Rpar=1g noiseless +C24 8 10 100f Rpar=1g noiseless +Q3 S2 N017 8 0 NPN1 temp=27 +Q4 C2_2 N019 10 0 NPN1 temp=27 +C25 N016 10 1p Rpar=3k noiseless +C26 8 C2_2 100f Rpar=1 noiseless +C27 N019 10 100f Rpar=5k noiseless +C28 N015 10 10f +R9 3 S2 9 noiseless +S2 N017 10 8 S2 SDRP2 +D12 N016 N017 DILIM2 +G9 10 Vout2DRV 10 N015 1m +L6 Vout2DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C29 3 N017 1p +G11 0 N020 3 10 1m +L7 N020 0 159m Rser=1k Rpar=10Meg noiseless +G12 0 N021 N020 0 1m +C30 INM2 10 100f +C31 9 10 100f +B1 10 N019 I=uplim(dnlim(500u*(V(8,Vout2DRV)-35*V(8,C2_2)),130u,10u),800u,100u) +B2 10 N016 I=(.5+.5*tanh((V(On)-.8)/100m))*uplim(333.33u*(V(Vout2DRV,10)+580m),667u*V(3,10)+2m,10u) +L8 N021 0 23.8m Rser=1.5k Rpar=3k noiseless +D13 10 8 DSUB +D14 10 9 DSUB +D15 10 3 DSUB +S3 N011 1 10 N011 S2V +C32 N011 10 100f Rpar=1Meg noiseless +D16 N011 4 DOD1 +D17 1 10 DBurnBG1 +D18 1 10 DBurnBG2 +S4 10 2 On 0 Sburn1 +S6 10 2 On 0 Sburn2 +S5 10 3 On 0 Sburn1 +S7 10 3 On 0 Sburn2 +B3 10 N008 I=(.5+.5*tanh((.9-V(On))/10m))*60u +B4 10 N019 I=(.5+.5*tanh((.9-V(On))/10m))*60u +A6 4 10 0 0 0 0 On 0 SCHMITT vt=1.4 vh=0 Rhigh=100k Rlow=1.5Meg Cout=100p +R10 BGREF 10 1Meg tc=0,-8e-8,0,3e-12 noiseless +G14 0 N026 1 10 100µ +G15 0 N027 N026 0 10µ +G16 10 N024 0 N027 500n +A2 5 BGREF 0 0 0 0 N025 0 OTA g=10u linear en=150n enk=2 Vlow=-1e308 Vhigh=1e308 +M3 1 N023 5 5 NBG temp=27 +M4 10 N023 5 5 PBG temp=27 +C33 1 5 1p +C34 5 10 1p +D19 5 N023 Y +G17 10 N023 N024 10 1µ +C35 N023 10 1f Rpar=1Meg noiseless +C36 5 N024 30p Rser=280k noiseless +D20 N023 5 Y +D21 10 5 DSUB +G18 10 N024 N025 0 50µ +C37 N024 10 5p Rser=1 noiseless +C38 N025 0 5p Rser=100k Rpar=100K noiseless +D22 N024 10 DBGLIM +R11 11 5 400 noiseless +D23 10 11 DSUB +A7 10 11 10 10 10 10 10 10 OTA g=0 linear in=170p/(1+freq/200k) vlow=-1e308 vhigh=1e308 +C39 11 10 100f +G5 0 N009 3 0 10µ +G10 10 11 3 10 1n +G2 N002 10 3 10 50p +G8 0 N020 2 10 10µ +G20 N015 10 2A 10 50p +L5 N026 0 637m Rser=10 Rpar=8k +A1 2 S1 10 10 10 10 N002 10 OTA g=200n iout=1u vlow=-1e308 vhigh=1e308 +A4 3 S2 10 10 10 10 N015 10 OTA g=80n iout=1u vlow=-1e308 vhigh=1e308 +G6 10 11 2A 0 500p +G19 0 2A 2 0 1 +L2 2A 0 795µ Rser=1 Rpar=5k noiseless +G4 10 N002 0 N010 4n +G13 10 N015 0 N021 4n +L3 N009 0 159m Rser=1k Rpar=10Meg noiseless +L4 N010 0 23.8m Rser=1.5k Rpar=3k noiseless +L9 N027 0 637m Rser=10 Rpar=8k +.model NPN1 NPN(IS=1E-14 VAF=100 BF=80 BR=1 ISC=1e-11 NC=2 IKR=15m CJC=100f CJE=100f noiseless) +.model DILIM1 D(Ron=50 Roff=50 ilimit=2.5m noiseless) +.model DILIM2 D(Ron=50 Roff=50 ilimit=1.47m noiseless) +.model DSUB D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBGLIM D(Ron=10 Roff=20Meg vfwd=6.5 epsilon=500m vrev=-1 revepsilon=500m noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=740m epsilon=100m noiseless) +.model NBG VDMOS(Vto=-100m Kp=80m noiseless) +.model PBG VDMOS(Vto=100m Kp=80m pchan noiseless) +.model SDRP1 SW(Ron=1 Roff=1Meg vt=-1.44 vh=-300m noiseless) +.model SDRP2 SW(Ron=1 Roff=1Meg vt=-1.34 vh=-300m noiseless) +.model S2V SW(level=2 Ron=1k Roff=1G vt=-2 vh=-20m noiseless) +.model DOD1 D(Ron=59.4k Roff=1G vfwd=200m epsilon=10m noiseless) +.model DBurnBG1 D(Ron=100 Roff=1G vfwd=0 epsilon=1 ilimit=569u noiseless) +.model DBurnBG2 D(Ron=700k Roff=1G vfwd=1 epsilon=1 noiseless) +.model Sburn1 SW(Ron=1k Roff=1G vt=.5 vh=-200m ilimit=97u noiseless) +.model Sburn2 SW(Ron=700k Roff=1G vt=.5 vh=-200m noiseless) +.ends LT6658-2.5 +* +.subckt LT6658-3.3 1 2 3 4 5 6 7 8 9 10 11 +A3 11 INM1 10 10 10 10 N002 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-13 Vhigh=1 +R2 7 INM1 800 noiseless +C1 6 N002 38p Rser=20k noiseless +C2 2 6 100f Rpar=1g noiseless +C3 6 10 100f Rpar=1g noiseless +Q1 S1 N004 6 0 NPN1 temp=27 +Q2 C2_1 N008 10 0 NPN1 temp=27 +C5 N003 10 1p Rpar=3k noiseless +C6 6 C2_1 100f Rpar=1 noiseless +C11 N008 10 100f Rpar=5k noiseless +C15 N002 10 10f +R5 2 S1 3.4 noiseless +S1 N004 10 6 S1 SDRP1 +D1 N003 N004 DILIM1 +G3 10 Vout1DRV 10 N002 1m +L1 Vout1DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C4 2 N004 1p +G1 0 N009 2 10 1m +G7 0 N010 N009 0 1m +B6 10 BGREF I=(.5+.5*tanh((V(1,10)-3.45)/10m))*3.3033u +C18 INM1 10 100f +C19 7 10 100f +B7 10 N008 I=uplim(dnlim(500u*(V(6,Vout1DRV)-70*V(6,C2_1)),130u,10u),800u,100u) +B5 10 N003 I=(.5+.5*tanh((V(On)-.8)/10m))*uplim(333.33u*(V(Vout1DRV,10)+580m),667u*V(2,10)+2m,10u) +D4 10 6 DSUB +D5 10 7 DSUB +D6 10 1 DSUB +D7 10 2 DSUB +D11 10 4 DSUB +A5 11 INM2 10 10 10 10 N017 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-10 Vhigh=1 +R6 9 INM2 800 noiseless +C22 8 N017 38p Rser=20k noiseless +C23 3 8 100f Rpar=1g noiseless +C24 8 10 100f Rpar=1g noiseless +Q3 S2 N016 8 0 NPN1 temp=27 +Q4 C2_2 N019 10 0 NPN1 temp=27 +C25 N015 10 1p Rpar=3k noiseless +C26 8 C2_2 100f Rpar=1 noiseless +C27 N019 10 100f Rpar=5k noiseless +C28 N017 10 10f +R9 3 S2 9 noiseless +S2 N016 10 8 S2 SDRP2 +D12 N015 N016 DILIM2 +G9 10 Vout2DRV 10 N017 1m +L6 Vout2DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C29 3 N016 1p +G11 0 N020 3 10 1m +G12 0 N021 N020 0 1m +C30 INM2 10 100f +C31 9 10 100f +B1 10 N019 I=uplim(dnlim(500u*(V(8,Vout2DRV)-35*V(8,C2_2)),130u,10u),800u,100u) +B2 10 N015 I=(.5+.5*tanh((V(On)-.8)/100m))*uplim(333.33u*(V(Vout2DRV,10)+580m),667u*V(3,10)+2m,10u) +D13 10 8 DSUB +D14 10 9 DSUB +D15 10 3 DSUB +S3 N011 1 10 N011 S2V +C32 N011 10 100f Rpar=1Meg noiseless +D16 N011 4 DOD1 +D17 1 10 DBurnBG1 +D18 1 10 DBurnBG2 +S4 10 2 On 0 Sburn1 +S6 10 2 On 0 Sburn2 +S5 10 3 On 0 Sburn1 +S7 10 3 On 0 Sburn2 +B3 10 N008 I=(.5+.5*tanh((.9-V(On))/10m))*60u +B4 10 N019 I=(.5+.5*tanh((.9-V(On))/10m))*60u +A6 4 10 0 0 0 0 On 0 SCHMITT vt=1.4 vh=0 Rhigh=100k Rlow=1.5Meg Cout=100p +G14 0 N027 1 10 100µ +G15 0 N028 N027 0 10µ +G16 10 N024 0 N028 10µ +A2 5 BGREF 0 0 0 0 N025 0 OTA g=10u linear en=238n enk=4 Vlow=-1e308 Vhigh=1e308 +M3 1 N023 5 5 NBG temp=27 +M4 10 N023 5 5 PBG temp=27 +C33 1 5 1p +C34 5 10 1p +D19 5 N023 Y +G17 10 N023 N024 10 1µ +C35 N023 10 1f Rpar=1Meg noiseless +C36 5 N024 30p Rser=280k noiseless +D20 N023 5 Y +D21 10 5 DSUB +G18 10 N024 N025 0 50µ +C37 N024 10 5p Rser=1 noiseless +C38 N025 0 5p Rser=100k Rpar=100K noiseless +D22 N024 10 DBGLIM +R11 11 5 400 noiseless +D23 10 11 DSUB +A7 10 11 10 10 10 10 10 10 OTA g=0 linear in=170p/(1+freq/200k) vlow=-1e308 vhigh=1e308 +C39 11 10 100f +G5 0 N009 3 0 10µ +G10 10 11 3 10 1n +G2 N002 10 3 10 50p +G6 10 11 N026 0 5n +G8 0 N020 2 10 10µ +G19 0 N026 1 0 1 +G20 N017 10 2A 10 50p +L3 N009 0 213m Rser=1k Rpar=13Meg noiseless +L4 N010 0 16.4m Rser=1.03k Rpar=34k noiseless +L2 N026 0 1.1m Rser=1 Rpar=6.9k noiseless +L5 N027 0 228m Rser=10 Rpar=2.86k noiseless +R1 BGREF 10 1Meg tc=0,-8e-8,0 noiseless +A1 2 S1 10 10 10 10 N002 10 OTA g=200n iout=1u vlow=-1e308 vhigh=1e308 +A4 3 S2 10 10 10 10 N017 10 OTA g=80n iout=1u vlow=-1e308 vhigh=1e308 +G21 10 11 2A 0 500p +G22 0 2A 2 0 1 +L10 2A 0 795µ Rser=1 Rpar=5k noiseless +G4 10 N017 0 N021 4n +G13 10 N002 0 N010 4n +D2 N027 0 DLS +L7 N020 0 213m Rser=1k Rpar=13Meg noiseless +L8 N021 0 16.4m Rser=1.03k Rpar=34k noiseless +L9 N028 0 228m Rser=10 Rpar=2.86k noiseless +.model NPN1 NPN(IS=1E-14 VAF=100 BF=80 BR=1 ISC=1e-11 NC=2 IKR=15m CJC=100f CJE=100f noiseless) +.model DILIM1 D(Ron=50 Roff=50 ilimit=2.5m noiseless) +.model DILIM2 D(Ron=50 Roff=50 ilimit=1.47m noiseless) +.model DSUB D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBGLIM D(Ron=10 Roff=20Meg vfwd=6.5 epsilon=500m vrev=-1 revepsilon=500m noiseless) +.model DLS D(Ron=500 Roff=100k vfwd=100m epsilon=100m vrev=100m revepsilon=100m noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=740m epsilon=100m noiseless) +.model NBG VDMOS(Vto=-100m Kp=80m noiseless) +.model PBG VDMOS(Vto=100m Kp=80m pchan noiseless) +.model SDRP1 SW(Ron=1 Roff=1Meg vt=-1.44 vh=-300m noiseless) +.model SDRP2 SW(Ron=1 Roff=1Meg vt=-1.34 vh=-300m noiseless) +.model S2V SW(level=2 Ron=1k Roff=1G vt=-2 vh=-20m noiseless) +.model DOD1 D(Ron=59.4k Roff=1G vfwd=200m epsilon=10m noiseless) +.model DBurnBG1 D(Ron=100 Roff=1G vfwd=0 epsilon=1 ilimit=569u noiseless) +.model DBurnBG2 D(Ron=700k Roff=1G vfwd=1 epsilon=1 noiseless) +.model Sburn1 SW(Ron=1k Roff=1G vt=.5 vh=-200m ilimit=97u noiseless) +.model Sburn2 SW(Ron=700k Roff=1G vt=.5 vh=-200m noiseless) +.ends LT6658-3.3 +* +.subckt LT6658-3 1 2 3 4 5 6 7 8 9 10 11 +A3 11 INM1 10 10 10 10 N002 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-13 Vhigh=1 +R2 7 INM1 800 noiseless +C1 6 N002 38p Rser=20k noiseless +C2 2 6 100f Rpar=1g noiseless +C3 6 10 100f Rpar=1g noiseless +Q1 S1 N004 6 0 NPN1 temp=27 +Q2 C2_1 N008 10 0 NPN1 temp=27 +C5 N003 10 1p Rpar=3k noiseless +C6 6 C2_1 100f Rpar=1 noiseless +C11 N008 10 100f Rpar=5k noiseless +C15 N002 10 10f +R5 2 S1 3.4 noiseless +S1 N004 10 6 S1 SDRP1 +D1 N003 N004 DILIM1 +G3 10 Vout1DRV 10 N002 1m +L1 Vout1DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C4 2 N004 1p +G1 0 N009 2 10 1m +G7 0 N010 N009 0 1m +B6 10 BGREF I=(.5+.5*tanh((V(1,10)-3.45)/10m))*3.003u +C18 INM1 10 100f +C19 7 10 100f +B7 10 N008 I=uplim(dnlim(500u*(V(6,Vout1DRV)-70*V(6,C2_1)),130u,10u),800u,100u) +B5 10 N003 I=(.5+.5*tanh((V(On)-.8)/10m))*uplim(333.33u*(V(Vout1DRV,10)+580m),667u*V(2,10)+2m,10u) +D4 10 6 DSUB +D5 10 7 DSUB +D6 10 1 DSUB +D7 10 2 DSUB +D11 10 4 DSUB +A5 11 INM2 10 10 10 10 N017 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-10 Vhigh=1 +R6 9 INM2 800 noiseless +C22 8 N017 38p Rser=20k noiseless +C23 3 8 100f Rpar=1g noiseless +C24 8 10 100f Rpar=1g noiseless +Q3 S2 N016 8 0 NPN1 temp=27 +Q4 C2_2 N019 10 0 NPN1 temp=27 +C25 N015 10 1p Rpar=3k noiseless +C26 8 C2_2 100f Rpar=1 noiseless +C27 N019 10 100f Rpar=5k noiseless +C28 N017 10 10f +R9 3 S2 9 noiseless +S2 N016 10 8 S2 SDRP2 +D12 N015 N016 DILIM2 +G9 10 Vout2DRV 10 N017 1m +L6 Vout2DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C29 3 N016 1p +G11 0 N020 3 10 1m +G12 0 N021 N020 0 1m +C30 INM2 10 100f +C31 9 10 100f +B1 10 N019 I=uplim(dnlim(500u*(V(8,Vout2DRV)-35*V(8,C2_2)),130u,10u),800u,100u) +B2 10 N015 I=(.5+.5*tanh((V(On)-.8)/100m))*uplim(333.33u*(V(Vout2DRV,10)+580m),667u*V(3,10)+2m,10u) +D13 10 8 DSUB +D14 10 9 DSUB +D15 10 3 DSUB +S3 N011 1 10 N011 S2V +C32 N011 10 100f Rpar=1Meg noiseless +D16 N011 4 DOD1 +D17 1 10 DBurnBG1 +D18 1 10 DBurnBG2 +S4 10 2 On 0 Sburn1 +S6 10 2 On 0 Sburn2 +S5 10 3 On 0 Sburn1 +S7 10 3 On 0 Sburn2 +B3 10 N008 I=(.5+.5*tanh((.9-V(On))/10m))*60u +B4 10 N019 I=(.5+.5*tanh((.9-V(On))/10m))*60u +A6 4 10 0 0 0 0 On 0 SCHMITT vt=1.4 vh=0 Rhigh=100k Rlow=1.5Meg Cout=100p +G14 0 N027 1 10 100µ +G15 0 N028 N027 0 10µ +G16 10 N024 0 N028 4.4e-6 +A2 5 BGREF 0 0 0 0 N025 0 OTA g=10u linear en=184n enk=4.4 Vlow=-1e308 Vhigh=1e308 +M3 1 N023 5 5 NBG temp=27 +M4 10 N023 5 5 PBG temp=27 +C33 1 5 1p +C34 5 10 1p +D19 5 N023 Y +G17 10 N023 N024 10 1µ +C35 N023 10 1f Rpar=1Meg noiseless +C36 5 N024 30p Rser=280k noiseless +D20 N023 5 Y +D21 10 5 DSUB +G18 10 N024 N025 0 50µ +C37 N024 10 5p Rser=1 noiseless +C38 N025 0 5p Rser=100k Rpar=100K noiseless +D22 N024 10 DBGLIM +R11 11 5 400 noiseless +D23 10 11 DSUB +A7 10 11 10 10 10 10 10 10 OTA g=0 linear in=170p/(1+freq/200k) vlow=-1e308 vhigh=1e308 +C39 11 10 100f +G5 0 N009 3 0 10µ +G10 10 11 3 10 1n +G2 N002 10 3 10 50p +G6 10 11 N026 0 3.2n +G8 0 N020 2 10 10µ +G19 0 N026 1 0 1 +G20 N017 10 2A 10 50p +L3 N009 0 189m Rser=1k Rpar=11.9Meg noiseless +L4 N010 0 16.6m Rser=1.046k Rpar=23.4k noiseless +L2 N026 0 946µ Rser=1 Rpar=6.06k noiseless +L5 N027 0 228m Rser=10 Rpar=2.86k noiseless +R1 BGREF 10 1Meg tc=0,-8e-8,0 noiseless +A1 2 S1 10 10 10 10 N002 10 OTA g=200n iout=1u vlow=-1e308 vhigh=1e308 +A4 3 S2 10 10 10 10 N017 10 OTA g=80n iout=1u vlow=-1e308 vhigh=1e308 +G21 10 11 2A 0 500p +G22 0 2A 2 0 1 +L10 2A 0 795µ Rser=1 Rpar=5k noiseless +G4 10 N002 0 N010 4n +G13 10 N017 0 N021 4n +L7 N020 0 189m Rser=1k Rpar=11.9Meg noiseless +L8 N021 0 16.6m Rser=1.046k Rpar=23.4k noiseless +L9 N028 0 228m Rser=10 Rpar=2.86k noiseless +D2 N027 0 DLS +.model NPN1 NPN(IS=1E-14 VAF=100 BF=80 BR=1 ISC=1e-11 NC=2 IKR=15m CJC=100f CJE=100f noiseless) +.model DILIM1 D(Ron=50 Roff=50 ilimit=2.5m noiseless) +.model DILIM2 D(Ron=50 Roff=50 ilimit=1.47m noiseless) +.model DSUB D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBGLIM D(Ron=10 Roff=20Meg vfwd=6.5 epsilon=500m vrev=-1 revepsilon=500m noiseless) +.model DLS D(Ron=500 Roff=100k vfwd=100m epsilon=100m vrev=100m revepsilon=100m noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=740m epsilon=100m noiseless) +.model NBG VDMOS(Vto=-100m Kp=80m noiseless) +.model PBG VDMOS(Vto=100m Kp=80m pchan noiseless) +.model SDRP1 SW(Ron=1 Roff=1Meg vt=-1.44 vh=-300m noiseless) +.model SDRP2 SW(Ron=1 Roff=1Meg vt=-1.34 vh=-300m noiseless) +.model S2V SW(level=2 Ron=1k Roff=1G vt=-2 vh=-20m noiseless) +.model DOD1 D(Ron=59.4k Roff=1G vfwd=200m epsilon=10m noiseless) +.model DBurnBG1 D(Ron=100 Roff=1G vfwd=0 epsilon=1 ilimit=569u noiseless) +.model DBurnBG2 D(Ron=700k Roff=1G vfwd=1 epsilon=1 noiseless) +.model Sburn1 SW(Ron=1k Roff=1G vt=.5 vh=-200m ilimit=97u noiseless) +.model Sburn2 SW(Ron=700k Roff=1G vt=.5 vh=-200m noiseless) +.ends LT6658-3 +* +.subckt LT6658-5 1 2 3 4 5 6 7 8 9 10 11 +A3 11 INM1 10 10 10 10 N002 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-13 Vhigh=1 +R2 7 INM1 800 noiseless +C1 6 N002 38p Rser=20k noiseless +C2 2 6 100f Rpar=1g noiseless +C3 6 10 100f Rpar=1g noiseless +Q1 S1 N004 6 0 NPN1 temp=27 +Q2 C2_1 N008 10 0 NPN1 temp=27 +C5 N003 10 1p Rpar=3k noiseless +C6 6 C2_1 100f Rpar=1 noiseless +C11 N008 10 100f Rpar=5k noiseless +C15 N002 10 10f +R5 2 S1 3.4 noiseless +S1 N004 10 6 S1 SDRP1 +D1 N003 N004 DILIM1 +G3 10 Vout1DRV 10 N002 1m +L1 Vout1DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C4 2 N004 1p +G1 0 N009 2 10 1m +G7 0 N010 N009 0 1m +B6 10 BGREF I=(.5+.5*tanh((V(1,10)-3.45)/10m))*2.5025u +C18 INM1 10 100f +C19 7 10 100f +B7 10 N008 I=uplim(dnlim(500u*(V(6,Vout1DRV)-70*V(6,C2_1)),130u,10u),800u,100u) +B5 10 N003 I=(.5+.5*tanh((V(On)-.8)/10m))*uplim(333.33u*(V(Vout1DRV,10)+580m),667u*V(2,10)+2m,10u) +D4 10 6 DSUB +D5 10 7 DSUB +D6 10 1 DSUB +D7 10 2 DSUB +D11 10 4 DSUB +A5 11 INM2 10 10 10 10 N017 10 OTA g=2.1m linear en=7.77n enk=1 Rout=120Meg Vlow=-10 Vhigh=1 +R6 9 INM2 800 noiseless +C22 8 N017 38p Rser=20k noiseless +C23 3 8 100f Rpar=1g noiseless +C24 8 10 100f Rpar=1g noiseless +Q3 S2 N016 8 0 NPN1 temp=27 +Q4 C2_2 N019 10 0 NPN1 temp=27 +C25 N015 10 1p Rpar=3k noiseless +C26 8 C2_2 100f Rpar=1 noiseless +C27 N019 10 100f Rpar=5k noiseless +C28 N017 10 10f +R9 3 S2 9 noiseless +S2 N016 10 8 S2 SDRP2 +D12 N015 N016 DILIM2 +G9 10 Vout2DRV 10 N017 1m +L6 Vout2DRV 10 20.18m Rser=1.521k Rpar=2.9166k noiseless +C29 3 N016 1p +G11 0 N020 3 10 1m +G12 0 N021 N020 0 1m +C30 INM2 10 100f +C31 9 10 100f +B1 10 N019 I=uplim(dnlim(500u*(V(8,Vout2DRV)-35*V(8,C2_2)),130u,10u),800u,100u) +B2 10 N015 I=(.5+.5*tanh((V(On)-.8)/100m))*uplim(333.33u*(V(Vout2DRV,10)+580m),667u*V(3,10)+2m,10u) +D13 10 8 DSUB +D14 10 9 DSUB +D15 10 3 DSUB +S3 N011 1 10 N011 S2V +C32 N011 10 100f Rpar=1Meg noiseless +D16 N011 4 DOD1 +D17 1 10 DBurnBG1 +D18 1 10 DBurnBG2 +S4 10 2 On 0 Sburn1 +S6 10 2 On 0 Sburn2 +S5 10 3 On 0 Sburn1 +S7 10 3 On 0 Sburn2 +B3 10 N008 I=(.5+.5*tanh((.9-V(On))/10m))*60u +B4 10 N019 I=(.5+.5*tanh((.9-V(On))/10m))*60u +A6 4 10 0 0 0 0 On 0 SCHMITT vt=1.4 vh=0 Rhigh=100k Rlow=1.5Meg Cout=100p +G14 0 N027 1 10 100µ +G15 0 N028 N027 0 10µ +G16 10 N024 0 N028 20µ +A2 5 BGREF 0 0 0 0 N025 0 OTA g=10u linear en=320n enk=5 Vlow=-1e308 Vhigh=1e308 +M3 1 N023 5 5 NBG temp=27 +M4 10 N023 5 5 PBG temp=27 +C33 1 5 1p +C34 5 10 1p +D19 5 N023 Y +G17 10 N023 N024 10 1µ +C35 N023 10 1f Rpar=1Meg noiseless +C36 5 N024 30p Rser=280k noiseless +D20 N023 5 Y +D21 10 5 DSUB +G18 10 N024 N025 0 50µ +C37 N024 10 5p Rser=1 noiseless +C38 N025 0 5p Rser=100k Rpar=100K noiseless +D22 N024 10 DBGLIM +R11 11 5 400 noiseless +D23 10 11 DSUB +A7 10 11 10 10 10 10 10 10 OTA g=0 linear in=170p/(1+freq/200k) vlow=-1e308 vhigh=1e308 +C39 11 10 100f +G5 0 N009 3 0 10µ +G10 10 11 3 10 1n +G2 N002 10 3 10 50p +G6 10 11 N026 0 16n +G8 0 N020 2 10 10µ +G19 0 N026 1 0 1 +G20 N017 10 2A 10 50p +L3 N009 0 795m Rser=1k Rpar=50Meg noiseless +L4 N010 0 16m Rser=1.01k Rpar=100k noiseless +L2 N026 0 6.36m Rser=1 Rpar=40k +L5 N027 0 79.6m Rser=10 Rpar=7.5k noiseless +R1 BGREF 10 2Meg tc=0,-8e-8,0 noiseless +A1 2 S1 10 10 10 10 N002 10 OTA g=200n iout=1u vlow=-1e308 vhigh=1e308 +A4 3 S2 10 10 10 10 N017 10 OTA g=80n iout=1u vlow=-1e308 vhigh=1e308 +G21 10 11 2A 0 500p +G22 0 2A 2 0 1 +L10 2A 0 795µ Rser=1 Rpar=5k noiseless +G4 10 N002 0 N010 4n +G13 10 N017 0 N021 4n +L9 N028 0 79.6m Rser=10 Rpar=7.5k noiseless +L7 N020 0 795m Rser=1k Rpar=50Meg noiseless +L8 N021 0 16m Rser=1.01k Rpar=100k noiseless +D2 N027 0 DLS +.model NPN1 NPN(IS=1E-14 VAF=100 BF=80 BR=1 ISC=1e-11 NC=2 IKR=15m CJC=100f CJE=100f noiseless) +.model DILIM1 D(Ron=50 Roff=50 ilimit=2.5m noiseless) +.model DILIM2 D(Ron=50 Roff=50 ilimit=1.47m noiseless) +.model DSUB D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBGLIM D(Ron=10 Roff=20Meg vfwd=6.5 epsilon=500m vrev=-1 revepsilon=500m noiseless) +.model DLS D(Ron=500 Roff=100k vfwd=100m epsilon=100m vrev=100m revepsilon=100m noiseless) +.model DLS D(Ron=500 Roff=100k vfwd=100m epsilon=100m vrev=100m revepsilon=100m noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=740m epsilon=100m noiseless) +.model NBG VDMOS(Vto=-100m Kp=80m noiseless) +.model PBG VDMOS(Vto=100m Kp=80m pchan noiseless) +.model SDRP1 SW(Ron=1 Roff=1Meg vt=-1.44 vh=-300m noiseless) +.model SDRP2 SW(Ron=1 Roff=1Meg vt=-1.34 vh=-300m noiseless) +.model S2V SW(level=2 Ron=1k Roff=1G vt=-2 vh=-20m noiseless) +.model DOD1 D(Ron=59.4k Roff=1G vfwd=200m epsilon=10m noiseless) +.model DBurnBG1 D(Ron=100 Roff=1G vfwd=0 epsilon=1 ilimit=569u noiseless) +.model DBurnBG2 D(Ron=700k Roff=1G vfwd=1 epsilon=1 noiseless) +.model Sburn1 SW(Ron=1k Roff=1G vt=.5 vh=-200m ilimit=97u noiseless) +.model Sburn2 SW(Ron=700k Roff=1G vt=.5 vh=-200m noiseless) +.ends LT6658-5 diff --git a/spice/copy/sub/LT7101.sub b/spice/copy/sub/LT7101.sub new file mode 100755 index 0000000..bbc5c86 Binary files /dev/null and b/spice/copy/sub/LT7101.sub differ diff --git a/spice/copy/sub/LT8210.sub b/spice/copy/sub/LT8210.sub new file mode 100755 index 0000000..a17e2de Binary files /dev/null and b/spice/copy/sub/LT8210.sub differ diff --git a/spice/copy/sub/LT8228.sub b/spice/copy/sub/LT8228.sub new file mode 100755 index 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All rights reserved. +* +.subckt LT1001 1 2 3 4 5 +A1 0 N004 0 0 0 0 X 0 OTA g=150u Iout=7u Cout=28p en=9.8n enk=4 Vhigh=1e308 Vlow=-1e308 +A2 2 1 0 0 0 0 0 0 OTA g=0 in=.1p ink=70 +C2 N004 0 .75p Rpar=100K noiseless +R1 3 X 10G noiseless +R2 X 4 10G noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +D1 5 X X +C3 N005 0 .075p Rpar=1Meg noiseless +D4 2 1 DI +C5 2 1 1p Rpar=80Meg +C7 3 5 .2p +C8 5 4 .2p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.3), V(4)+.9, .3)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.899,.3), V(4)+.899, .3)+1n*V(2) +B3 0 N005 I=1u*dnlim(uplim(V(x),V(3)-.9,.5), V(4)+.9,.5)+1p*V(x) +C9 3 1 .5p Rpar=1.12T noiseless +C4 1 4 .5p Rpar=1.12T noiseless +C6 2 4 .5p Rpar=1.12T noiseless +C10 3 2 .5p Rpar=1.12T noiseless +.model X D(Ron=10K Roff=1T Vfwd=.82 Vrev=.82 epsilon=.1 revepsilon=.1) +.model N VDMOS(Vto=-300m Kp=50m) +.model P VDMOS(Vto=300m Kp=50m pchan) +.model DI D(Ron=1.15K Roff=1G Vfwd=1 Vrev=1 epsilon=1 revepsilon=1 noiseless) +.ends LT1001 +* +.subckt LT1006 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=31f ink=85 +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 .12p Rpar=1Meg noiseless +C2 2 1 1p Rpar=417Meg noiseless +C3 3 5 .2p +C4 5 4 .2p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)-1.0,.1), V(4)-0.4, .1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)-0.99,.1), V(4)-0.41, .1)+1n*V(2) +C6 3 1 .5p Rpar=20G noiseless +C7 1 4 .5p noiseless Rpar=20G +C8 2 4 .5p Rpar=20G noiseless +C9 3 2 .5p Rpar=20G noiseless +A2 0 N003 0 0 0 0 X 0 OTA g=0.14m Iout=13.8u en=21n enk=2 Vhigh=1e308 Vlow=-1e308 +C10 N003 0 1.2p Rpar=100K noiseless +D2 1 3 DBIAS temp=27 +D3 2 3 DBIAS temp=27 +D4 X 3 XU +D5 4 X XD +D1 N004 5 YU +D6 5 N004 YD +G1 0 N004 X 0 1µ +C5 X 4 16p +C11 3 X 16p +.model XU D(Ron=1K Roff=50G Vfwd=-.64 epsilon=.3 noiseless) +.model XD D(Ron=1K Roff=50G Vfwd=-8m epsilon=.1 noiseless) +.model YU D(Ron=40K Roff=1T Vfwd=.9 epsilon=.1 noiseless) +.model YD D(Ron=100K Roff=1T Vfwd=0.4 epsilon=.1 noiseless) +.model N VDMOS(Vto=-120m Kp=50m mtriode=1) +.model P VDMOS(Vto=120m Kp=50m mtriode=1 pchan) +.model DBIAS D(Is=8.8n Rs=100 N=2 noiseless) +.ends LT1006 +* +.subckt LT1007 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=0.4p ink=120 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C1 N005 0 0.02f Rpar=1Meg noiseless +C2 2 1 1p Rpar=21G noiseless +C3 3 5 .2p +C4 5 4 .2p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-2.4,.1), V(4)+2.4, .1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-2.39,.1), V(4)+2.39, .1) +C6 3 1 .5p Rpar=21G noiseless +C7 1 4 .5p noiseless Rpar=21G +C8 2 4 .5p Rpar=21G noiseless +C9 3 2 .5p Rpar=21G noiseless +A2 0 N004 0 0 0 0 X 0 OTA g=0.51m Iout=19.2u Cout=6.98p en=2.3n enk=2 Vhigh=1e308 Vlow=-1e308 +C10 N004 0 72.3f Rpar=100K noiseless +C17 N009 0 72.8p noiseless Rser=721.6 Rpar=1000 +G12 0 N009 N008 0 1m +C12 N008 0 45.74p noiseless Rser=1.739k Rpar=1000 +G2 0 N008 X 0 1m +G1 0 N011 N010 0 1m +L1 N011 0 55.9µ Rser=1.58k Rpar=2.7241379310345K Cpar=1.48p noiseless +G3 0 N010 N009 0 1m +L2 N010 0 83.1µ Rser=2.34K Rpar=1.74626865671643K Cpar=3.36p noiseless +D2 2 1 DI +D3 3 4 DCPOW +D4 N005 5 Y +D5 5 N005 Y +D1 X 3 X +D6 4 X X +G5 0 N005 N011 0 1µ +.model X D(Ron=1K Roff=100G Vfwd=-1.2 epsilon=1 noiseless) +.model Y D(Ron=10k Roff=1T Vfwd=1.2 epsilon=.1 noiseless) +.model N VDMOS(Vto=-360m Kp=20m mtriode=1) +.model P VDMOS(Vto=360m Kp=20m mtriode=1 pchan) +.model DI D(Ron=5000 Roff=100G Vfwd=1 Vrev=1 epsilon=1 revepsilon=1 noiseless) +.model DCPOW D(Ron=100.0 Roff=1G Vfwd=1.0 Vrev=100.0 ilimit=1.37m noiseless) +.ends LT1007 +* +.subckt LT1008 1 2 3 4 5 6 7 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=5.6f ink=117 +C1 2 4 .1p Rpar=1.5T noiseless +C2 3 2 .1p Rpar=1.5T noiseless +C6 3 1 .1p Rpar=1.5T noiseless +C9 1 4 .1p Rpar=1.5T noiseless +M1 3 N008 5 5 N temp=27 +M2 4 N008 5 5 P temp=27 +C10 N008 0 1f Rpar=1Meg noiseless +C11 3 5 .5p +C12 5 4 .5p +D4 N008 5 Y +D5 5 N008 Y +G2 0 N008 N009 0 1µ +D2 3 N006 DLOADA +D3 3 6 DLOADB +C14 3 N006 50p +C16 3 6 50p +D6 N013 4 DTAIL +R3 3 N007 4.2K noiseless +R1 7 N009 3K noiseless +Q5 N009 N011 N014 0 NM1 temp=27 +D7 N011 N014 DQ23 temp=27 +C13 N014 4 2p +D8 N014 4 D300u +D9 N009 N014 D6u +G1 3 N014 N009 N014 100m vto=670m dir=1 +M3 N006 2 N013 N013 NIN temp=27 +M4 6 N012 N013 N013 NIN temp=27 +C4 N013 4 1p +D10 2 1 DIN +A2 0 0 1 1 1 1 N012 1 OTA g=.1 linear rout=10 en=14n enk=4.8 vlow=-1e308 vhigh=1e308 +G3 N009 N014 N009 3 1m vto=-.75 dir=1 +C3 N009 4 1p +C5 N006 2 1p +C17 6 N012 1p +C18 7 4 1p +S3 3 N006 1 3 SINUL +S1 3 6 2 3 SINUL +C19 6 N009 3p +C15 3 N007 1p +Q21 N011 N006 N007 0 PM1 temp=27 +Q22 N009 6 N007 0 PM1 temp=27 +C20 N006 4 1p +C21 6 4 1p +.model N VDMOS(Vto=-80m Kp=25m) +.model P VDMOS(Vto=80m Kp=25m pchan) +.model Y D(Ron=1k Roff=1T Vfwd=800m epsilon=100m noiseless) +.model NIN VDMOS(vto=700m Kp=6m) +.model NM1 NPN BF=100 Is=1e-16 tf=.3n Rb=500 Cjc=.5p Cje=.5p noiseless +.model PM1 PNP BF=100 BR=20 Xtb=1 Is=1.355e-15 Vaf=980 Var=20 nf=1.0115 Ikf=.0001 Ikr=.416m Tf=10n Isc=1.23e-14 nc=1.094 ++ tr=100n Ise=1.914e-14 ne=1.7053 Irb=1.726e-04 Rc=290 rb=250 trb1=7m rbm=10 noiseless ++ Cjc=.5p Vjc=.7671 mjc=.3163 Cje=.5p Vje=.7671 mje=.3163 +.model DLOADA D(Ron=23k Roff=1g vfwd=500m epsilon=150m noiseless) +.model DLOADB D(Ron=21.8703k Roff=1g vfwd=500m epsilon=150m noiseless) +.model DTAIL D(Ron=4k Roff=100Meg vfwd=200m epsilon=100m ilimit=13.9u noiseless) +.model DL1 D(Ron=560 Roff=1g vfwd=1 epsilon=100m ilimit=15u noiseless) +.model DIN D(Ron=1k Roff=1g vfwd= 1.1 epsilon=100m noiseless) +.model D300U D(Ron=100 Roff=1g vfwd=100m epsilon=50m ilimit=300u noiseless) +.model D6U D(Ron=100 Roff=1g vfwd=500m epsilon=100m ilimit=6u noiseless) +.model DQ23 D(Is=2.4e-16 n=1.0 noiseless) +.model SINUL SW(level=2 Ron=5k Roff=1G vt=-850m vh=100m noiseless) +.ends LT1008 +* +.subckt LT1010 1 2 3 4 5 +Q21 3 N008 N005 0 LPNPS temp=27 +Q29 4 N006 N007 0 NPN1 temp=27 +D1 2 N005 DIBIAS1 +Q3 N002 N005 N007 0 NPN1 temp=27 +R4 N006 N005 200 noiseless +C2 N006 N007 2p Rpar=3k noiseless +R3 5 N007 7 noiseless +Q30 N007 N012 3 0 NPN2 temp=27 +A1 2 4 0 0 0 0 N004 0 OTA g=200u linear vlow=.5 vhigh=19 ref=.8 Rout=1Meg Cout=5p +Q1 N002 N002 2 0 LPNP temp=27 +C1 N012 3 100f Rpar=8k noiseless +C6 2 4 200f Rpar=300 noiseless +Q2 2 2 4 0 NPNB temp=27 +G1 3 N012 N011 0 .5m +Q4 N006 N002 2 0 LPNP temp=27 +C5 2 N005 2p +S1 N012 3 3 N007 SLSAT +G3 N006 3 N007 5 50m vto=1.9 dir=1 +D2 1 N007 DCLM +G5 N012 3 5 N007 50m vto=2.1 dir=1 +G4 0 N011 N004 0 1µ +L2 N011 0 32m Rser=1Meg noiseless +C4 2 N002 20f +A2 0 0 1 1 1 1 N008 1 OTA g=.1 Rout=10 linear en=17n enk=300 vlow=-1e308 vhigh=1e308 +A3 0 1 0 0 0 0 0 0 OTA g=0 in=13p ink=1.1k +.model LPNPS PNP(BF=50 BR=30 Is=1e-15 VAF=1000 VAR=1000 Tf=10n Cjc=1p Cje=100f rb=200 IKF=150u noiseless) +.model LPNP PNP(BF=40 BR=40 Is=1e-16 VAF=1000 VAR=1000 Tf=80n Cjc=1p Cje=1p IKF=100u rb=10 noiseless) +.model NPN1 NPN(BF=100 BR=20 Is=1e-16 Cjc=1p Cje=1p TF=1n IKF=200m Rb=20 noiseless) +.model NPN2 NPN(BF=100 BR=20 Is=1e-16 Cjc=1p Cje=1p TF=500p IKF=200m Rb=10 noiseless) +.model NPNB NPN(BF=100 BR=20 Is=1e-27 Cjc=1p Cje=1p TF=15n IKF=200m Rb=20 noiseless) +.model SLSAT SW(Ron=100 Roff=8k vt=-3.2 vh=-3 noiseless) +.model DCLM D(Ron=70 Roff=1g vfwd=6.5 epsilon=700m vrev=5.4 revepsilon=700m noiseless) +.model DIBIAS1 D(Ron=1 Roff=1Meg Vfwd=1 epsilon=10m ilimit=500u noiseless) +.ends LT1010 +* +.subckt LT1012 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=6f ink=120 +B1 0 N006 I=10u*dnlim(uplim(V(1),V(3)-.65,.1), V(4)+0.65, .1)+1n*V(1) +B2 N006 0 I=10u*dnlim(uplim(V(2),V(3)-.64,.1), V(4)+.64, .1)+1n*V(2) +C6 3 1 .1p Rpar=1.5T noiseless +C7 1 4 .1p noiseless Rpar=1.5T +C8 2 4 .1p Rpar=1.5T noiseless +C9 3 2 .1p Rpar=1.5T noiseless +C10 N006 0 448f Rpar=100K noiseless +M1 3 N008 5 5 N temp=27 +M2 4 N008 5 5 P temp=27 +C1 N008 0 44.8f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +D5 N008 5 YU +D6 5 N008 YD +G1 0 N008 N003 0 1µ +C2 2 1 1p +A3 0 N006 0 0 0 0 N007 0 OTA g=1m linear en=13n enk=2.5 Vhigh=1e308 Vlow=-1e308 +G4 0 N004 N005 0 1m +L1 N005 0 1.54m Cpar=29.8p Rser=3.31k Rpar=1.43290043290044k +L2 N004 0 304µ Cpar=13.6p Rser=2.07k Rpar=1.93457943925235k noiseless +A2 0 N004 0 0 0 0 N003 0 OTA g=415u iout=20.9u Vhigh=1e308 Vlow=-1e308 +C11 N003 0 113p Rser=10k noiseless +C12 N007 0 1.13n Rpar=1k noiseless +G2 0 N005 N007 0 1m +D2 3 4 DC +D3 2 1 DIN +A4 0 N004 N010 0 0 0 N003 0 OTA g=40u asym isource=20u isink=-40u vlow=-1e308 vhigh=1e308 +C13 N010 0 100p Rpar=1k noiseless +B3 0 N010 I=(.5m+.5m*tanh((V(2,1)-1)/50m))+(.5m+.5m*tanh((V(1,2)-1)/50m)) +R1 3 N003 10G noiseless +G3 N003 0 N003 3 5m dir=1 vto=-.6 +G5 0 N003 4 N003 5m dir=1 vto=-.6 +R2 N003 4 10G noiseless +C14 N008 5 30f Rser=10k noiseless +.model YU D(Ron=1.1k Roff=1T Vfwd=1.09 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=1 epsilon=.1 noiseless) +.model DIN D(Ron=10 Roff=50Meg vfwd=900m epsilon=200m vrev=900m revepsilon=200m noiseless) +.model DC D(Ron=1k, Roff=1T Vfwd=1 ilimit=332u noiseless) +.model N VDMOS(Vto=-40m Kp=60m) +.model P VDMOS(Vto=40m Kp=60m pchan) +.ends LT1012 +* +.subckt LT1013 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=15f ink=60 +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)-0.4, .1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)-1.09,.1), V(4)-0.41, .1)+1n*V(2) +C6 3 1 .1p Rpar=20G noiseless +C7 1 4 .1p noiseless Rpar=20G +C8 2 4 .1p Rpar=20G noiseless +C9 3 2 .1p Rpar=20G noiseless +C10 N003 0 1f Rpar=100K noiseless +D1 N005 3 XU +D4 4 N005 XD +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 12f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +D5 N004 5 YU +D6 5 N004 YD +G1 0 N004 N005 0 1µ +C2 2 1 1f Rpar=435Meg noiseless +A2 0 N006 0 0 0 0 N005 0 OTA g=160u iout=9.59u Cout=23.4p Vhigh=1e308 Vlow=-1e308 +G2 0 N006 N007 0 1m +L2 N006 0 .457m Cpar=5.08p Rser=1.29k Rpar=4.448275862068965k noiseless +A3 0 N003 0 0 0 0 N007 0 OTA g=1m linear en=20.2n enk=2 Vhigh=1e308 Vlow=-1e308 +C11 N007 0 532p Rpar=1k noiseless +D2 2 3 DBIAS +D3 1 3 DBIAS +.model XU D(Ron=1K Roff=100G Vfwd=-.72 epsilon=1.0 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-.114 epsilon=1.0 noiseless) +.model YU D(Ron=500 Roff=1T Vfwd=.77 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=.74 epsilon=.1 noiseless) +.model DBIAS D(Ron=1k Roff=1T Vrev=0.6 revilimit=12n noiseless) +.model N VDMOS(Vto=-100m Kp=70m) +.model P VDMOS(Vto=100m Kp=70m pchan) +.ends LT1013 +* +.subckt LT1016 1 2 3 4 5 6 7 8 +A3 5 6 0 0 0 0 N016 0 SCHMITT Vt=1.5 Vh=0 tau=3n +B1 0 VD0 I=10u*dnlim(uplim(V(2),V(1)-1.4,.1), V(4)+1.15,.1)+1n*V(2) +B2 VD0 0 I=10u*dnlim(uplim(V(3),V(1)-1.39,.1), V(4)+1.14, .1)+1n*V(3) +C1 VD0 0 .01f Rpar=100K noiseless +A1 0 VD0 0 0 0 0 N006 0 OTA g=11m iout=75u Vlow=-1e308 Vhigh=1e308 Cout=1f +C5 1 7 .1p +C6 7 6 .1p +G5 0 N002 N006 0 68n +D5 0 N006 DLAT +G2 0 N011 0 N006 68n +A2 N009 0 N016 0 0 0 N006 0 OTA g=500u linear Vlow=-1e308 Vhigh=1e308 +D1 0 N009 DLAT +C3 N009 0 1f +G3 0 N009 0 N006 500µ +C4 3 4 1.75p +C10 2 4 1.75p +D13 1 4 DP1 +D14 1 6 DP2 +D3 N002 1 XU +D4 6 N002 XD +M1 1 N003 7 7 N temp=27 +M2 6 N007 7 7 P temp=27 +D15 N003 6 DVLU1 +R6 N003 N002 4G +D16 N003 6 DVLU2 +R7 N007 N002 4G +D17 6 N007 DVLD +C2 N002 0 .04f +C7 1 8 .1p +C8 8 6 .1p +D7 N011 1 XU +D8 6 N011 XD +M3 1 N012 8 8 N temp=27 +M4 6 N014 8 8 P temp=27 +D18 N012 6 DVLU1 +R8 N012 N011 4G +D19 N012 6 DVLU2 +R9 N014 N011 4G +D20 6 N014 DVLD +C9 N011 0 .04f +C11 1 3 1.75p +C12 1 2 1.75p +D2 3 2 DBIASC +D6 2 4 DBIAS +D9 3 4 DBIAS +D10 1 5 DLATCH +.model DBIAS D(Ron=1k Roff=10G Vfwd=1 epsilon=.1 ilimit=2.5u) +.model DBIASC D(Ron=1 Roff=10G Vfwd= 1u Vrev=1u ++ epsilon=200u revepsilon=200u ilimit=2.5u revilimit=2.5u) +.model DLATCH D(Ron=1k Roff=10Meg Vfwd=1 epsilon=.1 ilimit=500u) +.model DP1 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=3m) +.model DP2 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=17.7m) +.model XU D(Ron=1k Roff=1.7G Vfwd=6.8 epsilon=.1) +.model XD D(Ron=1k Roff=637Meg Vfwd=9 epsilon=.1) +.model DVLU1 D(Ron=1.5G Roff=100G Vfwd=1.1 epsilon=2.5) +.model DVLU2 D(Ron= 5Meg Roff=100G Vfwd=3.5 epsilon=.1) +.model DVLD D(Ron= 5Meg Roff=100G Vfwd=-150m epsilon=.1) +.model DLAT D(Ron=1 Roff=10k Vfwd=500m Vrev=500m epsilon=5m revepsilon=5m) +.model N VDMOS(Vto= -300m kp=230m rds=2k) +.model P VDMOS(Vto= 400m Kp=25m rds=2k pchan ) +.ends LT1016 +* +.subckt LT1022 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.8f ink=1 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-2.9,.1), V(4)+2.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-2.89,.1), V(4)+2.89, .1)+1n*V(2) +C6 3 1 1p Rpar=4T noiseless +C7 1 4 1p noiseless Rpar=4T +C8 2 4 1p Rpar=4T noiseless +C9 3 2 1p Rpar=4T noiseless +A2 0 N004 0 0 0 0 N006 0 OTA g=8.4u iout=3.6u Cout=172.8f en=14n enk=10 Vhigh=1e308 Vlow=-1e308 +C10 N004 0 20f Rpar=100K noiseless +D1 N006 3 X +D4 4 N006 X +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C1 N005 0 11.9f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +D5 N005 5 Y +D6 5 N005 Y +G1 0 N005 N006 0 1µ +D3 3 4 DC +.model X D(Ron=1K Roff=100G Vfwd=-1.95 epsilon=1.0 noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=0.865 epsilon=0.1 noiseless) +.model N VDMOS(Vto=-500m Kp=40m) +.model P VDMOS(Vto=500m Kp=40m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=200u noiseless) +.ends LT1022 +* +.subckt LT1028 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.9p ink=250 incm=2.4p incmk=250 +M1 3 N009 5 5 N temp=27 +M2 4 N009 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-2.7,.1), V(4)+2.7, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-2.69,.1), V(4)+2.69, .1)+1n*V(2) +C6 3 1 2.5p Rpar=1.2G noiseless +C7 1 4 2.5p noiseless Rpar=1.2G +C8 2 4 2.5p Rpar=1.2G noiseless +C9 3 2 2.5p Rpar=1.2G noiseless +A2 0 N004 0 0 0 0 N010 0 OTA g=630u Iout=17.51u en=.85n+freq*36u/(8k*freq+(freq-400k)**2) Vlow=-1e308 Vhigh=1e308 Cout= 1.35p enk=3 +C10 N004 0 1f Rpar=100K noiseless +D4 N010 3 X +D5 4 N010 X +D1 N009 5 Y +D6 5 N009 Y +D7 3 4 DP +C11 2 1 12.5p Rpar=20k noiseless +G3 0 N007 N006 0 1m +L3 N007 0 63.3µ Rser=1.081k Rpar=13.3456790123457k noiseless +G4 0 N005 N010 0 1m +L4 N005 0 1.437m Rser=2.25k Rpar=1.8k Cpar=70.46p noiseless +G5 0 N006 N005 0 1m +L5 N006 0 86.112µ noiseless Rpar=3.127659574468084k Cpar=1.8p Rser=1.47k +C1 N008 0 140.4p noiseless Rser=416.7 Rpar=1k +G1 0 N008 N007 0 1m +C2 N009 0 140.4f noiseless Rser=416.7k Rpar=1Meg +G2 0 N009 N008 0 1µ +D2 2 1 DIN +.model X D(Ron=1K Roff=100G Vfwd=-2 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=1.18 epsilon=.1 noiseless) +.model N VDMOS(Vto=-200m Kp=40m) +.model P VDMOS(Vto=200m Kp=40m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=6.602m noiseless) +.model DIN D(Ron=100 Roff=1T Vfwd=1.8 Vrev=1.8 noiseless) +.ends LT1028 +* +.subckt LT1037 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.38p ink=120 +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C1 N007 0 318f Rser=0 Rpar=1Meg noiseless +C2 2 1 1p +C3 3 5 .2p +C4 5 4 .2p +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)-2.4,.1), V(4)+2.4, .1)+1n*V(1) +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)-2.39,.1), V(4)+2.39, .1)+1n*V(2) +C6 3 1 .5p Rpar=21G noiseless +C7 1 4 .5p noiseless Rpar=21G +C8 2 4 .5p Rpar=21G noiseless +C9 3 2 .5p Rpar=21G noiseless +C10 N005 0 25f Rpar=100K noiseless +D2 2 1 DI +D3 3 4 DCPOW +G4 0 N007 N004 0 1µ +D1 N007 5 Y +D4 5 N007 Y +D5 N008 3 X +D6 4 N008 X +A3 0 N005 0 0 0 0 N008 0 OTA G=.51m Iout=25u Cout=1.35p en=2.3n enk=2 Vhigh=1e308 Vlow=-1e308 +G3 0 N004 N006 0 1m +L3 N004 0 0.1m Rser=1.1K Rpar=11K Cpar=0.18p noiseless +G5 0 N006 N008 0 1m +L4 N006 0 46.6µ Rser=1.96K Rpar=2.04166666666667K Cpar=1.92p noiseless +.model X D(Ron=1K Roff=78G Vfwd=-1.35 epsilon=1 noiseless) +.model Y D(Ron=10k Roff=1T Vfwd=1.35 epsilon=.1 noiseless) +.model N VDMOS(Vto=-360m Kp=20m mtriode=1) +.model P VDMOS(Vto=360m Kp=20m mtriode=1 pchan) +.model DI D(Ron=1k Roff=100G Vfwd=1 Vrev=1 epsilon=1 revepsilon=1 noiseless) +.model DCPOW D(Ron=100.0 Roff=1G Vfwd=1.0 Vrev=100.0 ilimit=1.37m noiseless) +.ends LT1037 +* +*CCM Fri Jan 3 12:04:23 1998 +* S1A S2A CA+ S3A S4A CA- OSC VDD VSS +.SUBCKT LTC1043 7 8 11 13 14 12 16 4 17 +.IC V(20)=0 +RIN1 16 17 1.0E9 +RIN2 16 20 50 +DINP 20 4 DX +DINN 17 20 DX +COSC 20 17 2.4e-11 +GBIAS 20 17 POLY(2) 4 17 73 17 0.0 -4.0E-6 -8.0E-6 +GINV 17 73 72 20 1.0E-1 +RINV1 73 17 1.0E4 +CINV1 73 17 2.2E-10 +DINV1 73 74 DX +VINV1 74 17 DC -0.86 +DINV2 75 73 DX +EINV2 75 17 POLY(1) 17 4 0.8 1.0 +GTV 17 72 4 17 1.16E-3 +RTV 72 17 1.0E3 +RHYST 73 72 1.4E3 +GSCS 17 76 73 17 2.5E-3 +RSCS 76 17 1.0E3 +DSCS 77 76 DX +VSDN2 77 17 DC -4.2 +EST1 24 17 76 17 1.0 +RST1 24 25 113 +RST2 25 26 85 +DST1 24 26 DX +CST1 25 17 1.2E-9 +EST2 44 17 POLY(1) 17 76 -5 1 +RST3 44 45 113 +RST4 45 46 85 +DST2 44 46 DX +CST2 45 17 1.2E-9 +XS1A 7 11 25 4 17 X1LTC1043 +XS2A 8 11 45 4 17 X1LTC1043 +XS3A 13 12 25 4 17 X1LTC1043 +XS4A 14 12 45 4 17 X1LTC1043 +RPC 4 17 25000 +.MODEL DX D IS=8e-16 RS=0 XTI=0 +.ENDS LTC1043 +* +.SUBCKT X1LTC1043 1 2 25 14 15 ;NESTED SUBCIRCUIT--DO NOT CALL +GSW 1 31 POLY(2) 25 15 1 31 0 0 6e-13 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 2.56E-6 +RTC 33 15 995.41 TC=-0.002298 +GTC 15 33 31 2 0.001 +GPK1 15 50 POLY(2) 1 15 14 15 0 1.0E-3 -0.0006 +RPK1 50 15 1.0E3 +DPK1 50 51 DX +RPK2 51 15 1.0E4 +GPK2 15 52 POLY(2) 1 15 51 15 0 1.0E-3 -1.4E-3 +RPK3 52 15 1.0E3 +GSV1 15 53 TABLE {V(14,15)}= ++ (3.0, 6.8E-3) (5.0, 4.15E-3) (7.0, 2.9E-3) (9.0, 2.25E-3) (10.0, 1.95E-3) ++ (12.0, 1.58E-3) (15.0, 1.23E-3) (18.0, 1.0E-3) +RSV1 53 15 1.0E3 +GSV2 15 54 POLY(2) 53 15 52 15 0 0 0 0 1.0E-3 +RSV2 54 15 1.0E3 +GON 31 2 POLY(2) 33 15 54 15 0 0.009972 0 0 0 0 0 0 -3.437e-5 +RON1 1 31 1.0E12 +RON2 31 2 1.0E9 +CDS 1 2 5e-13 +CDG 2 15 1e-12 +CSG 1 15 1e-12 +.MODEL DX D IS=8e-16 RS=0 XTI=0 +.ENDS X1LTC1043 +* +.subckt LTC1047 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.5f +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 .5p Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 X0 I=10u*dnlim(uplim(V(1),V(3)-1.0,.1), V(4)-0.4, .1)+1n*V(1) +B2 X0 0 I=10u*dnlim(uplim(V(2),V(3)-.99,.1), V(4)-0.41, .1)+1n*V(2) +C9 3 2 6p Rser=100 noiseless +A2 0 X0 0 0 0 0 N006 0 OTA g=7m Iout=832u Cout=4n en=168n Vhigh=1e308 Vlow=-1e308 +C10 X0 0 .1p Rpar=100K noiseless +D1 N004 5 YU +D6 5 N004 YD +G4 0 N005 N006 0 1m +D7 3 4 DP +G3 N006 0 N006 3 10m dir=1 vto=.25 +G6 0 N006 4 N006 10m dir=1 vto=-.2 +R4 3 N006 10G +R5 N006 4 10G +C12 N005 0 50p Rpar=1k noiseless +G2 0 N004 N005 0 1µ +C2 3 1 6p Rser=100 noiseless +C6 2 4 6p Rser=100 noiseless +C7 1 4 6p Rser=100 noiseless +.model YU D(Ron=10K Roff=1T Vfwd=.7 epsilon=.4 noiseless) +.model YD D(Ron=10k Roff=1T Vfwd=.6 epsilon=.4 noiseless) +.model N VDMOS(Vto=-40m Kp=2m) +.model P VDMOS(Vto=30m Kp=20m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=57.1u noiseless) +.ends LTC1047 +* +.subckt LTC1049 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2f +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 894f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-0.3, .1)+1n*V(1) +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-0.31, .1)+1n*V(2) +C9 3 2 1p Rser=100 noiseless +C10 N005 0 10f Rpar=100K noiseless +D1 N004 5 YU +D6 5 N004 YD +D7 3 4 DP +G3 N007 0 N007 3 60m dir=1 vto=-.1 +G6 0 N007 4 N007 60m dir=1 vto=-.2 +R4 3 N007 1G +R5 N007 4 1G +G2 0 N004 N006 0 1µ +C2 3 1 1p Rser=100 noiseless +C6 2 4 1p Rser=100 noiseless +C7 1 4 1p Rser=100 noiseless +G1 0 N006 N007 0 1m +L2 N006 0 815µ Rser=1.69k Rpar=2.44927536231884057968k Cpar=11.7p noiseless +R3 3 4 200k noiseless +A2 0 N005 0 0 0 0 N007 0 OTA g=205m Iout=18m en=29n+(58n+ 1n*min(max(freq,3k),10k)**.5)/(1.2+ (max(freq,10k)/10k)**3.5) Cout=22n Vlow=-1e308 Vhigh=1e308 +.model YU D(Ron=10K Roff=1T Vfwd=.7 epsilon=.4 noiseless) +.model YD D(Ron=10k Roff=1T Vfwd=.6 epsilon=.4 noiseless) +.model N VDMOS(Vto=-200m Kp=2m) +.model P VDMOS(Vto=200m Kp=20m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=57.6u noiseless) +.ends LTC1049 +* +.subckt LTC1050 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2f +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 176f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-0.3, .1)+1n*V(1) +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-0.31, .1)+1n*V(2) +C9 3 2 1p Rser=100 noiseless +C10 N005 0 100f Rpar=100K noiseless +D1 N004 5 YU +D6 5 N004 YD +D7 3 4 DP +G3 X 0 X 3 500m dir=1 vto=-.25 +G6 0 X 4 X 500m dir=1 vto=-.2 +R4 3 X 1G +R5 X 4 1G +G2 0 N004 N006 0 1µ +C2 3 1 1p Rser=100 noiseless +C6 2 4 1p Rser=100 noiseless +C7 1 4 1p Rser=100 noiseless +G1 0 N006 X 0 1m +R3 3 4 20k noiseless +L1 N006 0 246µ Rser=2.05k Rpar=1.95238095238095238123k Cpar=10.9p noiseless +A2 0 N005 0 0 0 0 X 0 OTA g=205m Iout=82m en=22n+(58n+ 1n*min(max(freq,1.2k),2.6k)**.65)/(1.3+ (max(freq,2.6k)/2.6k)**.8 +1e-16*freq**4) Cout=20n Vlow=-1e308 Vhigh=1e308 +.model YU D(Ron=10K Roff=1T Vfwd=.4 epsilon=.4 noiseless) +.model YD D(Ron=10k Roff=1T Vfwd=1.2 epsilon=.4 noiseless) +.model N VDMOS(Vto=-150m Kp=20m) +.model P VDMOS(Vto=150m Kp=20m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=276.6u noiseless) +.ends LTC1050 +* +.subckt LTC1051 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2f +M1 3 N006 5 5 N temp=27 +M2 4 N006 5 5 P temp=27 +C1 N006 0 470f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 N007 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-0.3, .1)+1n*V(1) +B2 N007 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-0.31, .1)+1n*V(2) +C9 3 2 1p Rser=100 noiseless +C10 N007 0 1f Rpar=100K noiseless +D1 N006 5 YU +D6 5 N006 YD +D7 3 4 DP +G3 N004 0 N004 3 100m dir=1 vto=0 +G6 0 N004 4 N004 100m dir=1 vto=0 +R4 3 N004 1G +R5 N004 4 1G +G2 0 N006 N008 0 1µ +C2 3 1 1p Rser=100 noiseless +C6 2 4 1p Rser=100 noiseless +C7 1 4 1p Rser=100 noiseless +R3 3 4 22k noiseless +G4 0 N008 N004 0 1m +L2 N008 0 262µ Rser=1.16k Rpar=7.25k Cpar=1.1p noiseless +C11 N004 0 .8n Rser=200 noiseless +A3 0 N005 0 0 0 0 N004 0 OTA g=20.5m Iout=3.6m Vlow=-1e308 Vhigh=1e308 +A2 0 N007 0 0 0 0 N005 0 OTA g=1u linear en=67n/(max(freq,2.6k)/2.6k)**.8 Cout=200f Rout=1Meg Vlow=-1e308 Vhigh=1e308 +.model YU D(Ron=10K Roff=1T Vfwd=.4 epsilon=.4 noiseless) +.model YD D(Ron=10k Roff=1T Vfwd=1.2 epsilon=.4 noiseless) +.model N VDMOS(Vto=-200m Kp=15m) +.model P VDMOS(Vto=200m Kp=20m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=200.825u noiseless) +.ends LTC1051 +* +.subckt LTC1052 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.6f +M1 3 N008 5 5 N temp=27 +M2 4 N008 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N006 I=10u*dnlim(uplim(V(1),V(3)-1.3,.1), V(4)-0.3, .1)+1n*V(1) +B2 N006 0 I=10u*dnlim(uplim(V(2),V(3)-1.29,.1), V(4)-0.31, .1)+1n*V(2) +C9 3 2 1p Rser=100 noiseless +C10 N006 0 1f Rpar=100K noiseless +D1 N008 5 YU +D6 5 N008 YD +D7 3 4 DP +G3 N004 0 N004 3 600m dir=1 vto=-.1 +G6 0 N004 4 N004 600m dir=1 vto=-.1 +R4 3 N004 1G +R5 N004 4 1G +C2 3 1 1p Rser=100 noiseless +C6 2 4 1p Rser=100 noiseless +C7 1 4 1p Rser=100 noiseless +R3 3 4 22k noiseless +G4 0 N008 N004 0 1µ +A3 0 N005 0 0 0 0 N004 0 OTA g=60.5m Iout=22.5m Cout=5n Vlow=-1e308 Vhigh=1e308 +C8 N008 0 1f Rpar=1Meg noiseless +L2 N007 0 39.3m Rser=123k Rpar=534.78k Cpar=31.8f noiseless +G2 0 N005 N007 0 .1µ +C11 N005 0 100f Rpar=10Meg noiseless +D2 N005 N007 DLS +A2 0 N006 0 0 0 0 N007 0 OTA g=12u linear en=103.5n+6n*(70m*min(max(freq,70),140) -63m*min(max(freq,140),350)) Vlow=-1 Vhigh=1 +.model YU D(Ron=10K Roff=1T Vfwd=.4 epsilon=.5 noiseless) +.model YD D(Ron=10k Roff=1T Vfwd=.5 epsilon=.4 noiseless) +.model N VDMOS(Vto=-200m Kp=15m) +.model P VDMOS(Vto=200m Kp=20m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=.900825m noiseless) +.model DLS D(Roff=1G Ron=100k Vfwd=1.3 Vrev=1.3 epsilon=100m revepsilon=100m noiseless) +.ends LTC1052 +* +.subckt LT1055 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.8f ink=100 +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)-2.9,.1), V(4)+2.9, .1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)-2.89,.1), V(4)+2.89, .1)+1n*V(2) +C6 3 1 2p Rpar=4T noiseless +C7 1 4 2p noiseless Rpar=4T +C8 2 4 2p Rpar=4T noiseless +C9 3 2 2p Rpar=4T noiseless +A2 0 N003 0 0 0 0 X 0 OTA g=8.4u asym isource=3.21u isink=-11u Cout=279f en=14n enk=20 Vhigh=1e308 Vlow=-1e308 +C10 N003 0 1f Rpar=100K noiseless +D1 X 3 X +D4 4 X X +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 21f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +D5 N004 5 Y +D6 5 N004 Y +G1 0 N004 X 0 1µ +D3 3 4 DC +.model X D(Ron=1K Roff=100G Vfwd=-1.86 epsilon=1.0 noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=.805 epsilon=0.1 noiseless) +.model N VDMOS(Vto=-300m Kp=60m) +.model P VDMOS(Vto=300m Kp=60m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=100u noiseless) +.ends LT1055 +* +.subckt LT1056 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.8f ink=100 +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)-2.9,.1), V(4)+2.9, .1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)-2.89,.1), V(4)+2.89, .1)+1n*V(2) +C6 3 1 2p Rpar=4T noiseless +C7 1 4 2p noiseless Rpar=4T +C8 2 4 2p Rpar=4T noiseless +C9 3 2 2p Rpar=4T noiseless +A2 0 N003 0 0 0 0 X 0 OTA g=8.4u asym isource=3.28u isink=-9.84u Cout=205f en=15n enk=28 Vhigh=1e308 Vlow=-1e308 +C10 N003 0 1f Rpar=100K noiseless +D1 X 3 X +D4 4 X X +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 22f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +D5 N004 5 Y +D6 5 N004 Y +G1 0 N004 X 0 1µ +D3 3 4 DC +.model X D(Ron=1K Roff=100G Vfwd=-1.86 epsilon=1.0 noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=.805 epsilon=0.1 noiseless) +.model N VDMOS(Vto=-300m Kp=60m) +.model P VDMOS(Vto=300m Kp=60m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=2.3m noiseless) +.ends LT1056 +* +.subckt LT1057 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.5f ink=100 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)-.7,.1), V(4)+3.4, .1)+1n*V(1) +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)-.69,.1), V(4)+3.39, .1)+1n*V(2) +C6 3 1 2p Rpar=2T noiseless +C7 1 4 2p noiseless Rpar=2T +C8 2 4 2p Rpar=2T noiseless +C9 3 2 2p Rpar=2T noiseless +A2 0 N005 0 0 0 0 N006 0 OTA g=7u asym isource=2.98u isink=-4.4u cout=220f en=13n enk=28 Vhigh=1e308 Vlow=-1e308 +C10 N005 0 1f Rpar=100K noiseless +D1 N006 3 X +D4 4 N006 X +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 12f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +D5 N004 5 YU +D6 5 N004 YD +G1 0 N004 N006 0 1µ +C2 5 N004 10f Rser=10k noiseless +.model X D(Ron=1K Roff=100G Vfwd=-1.8 epsilon=1.0 noiseless) +.model YU D(Ron=500 Roff=1T Vfwd=1.30 epsilon=0.1 noiseless) +.model YD D(Ron=500 Roff=1T Vfwd = 1.24 epsilon=0.1 noiseless) +.model N VDMOS(Vto=-400m Kp=20m) +.model P VDMOS(Vto=400m Kp=20m pchan) +.ends LT1057 +* +.subckt LT1078 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=20f ink=60 +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 914f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)-0.4, .1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)-1.09,.1), V(4)-0.41, .1)+1n*V(2) +C6 3 1 .5p Rpar=24G noiseless +C7 1 4 .5p noiseless Rpar=24G +C8 2 4 .5p Rpar=24G noiseless +C9 3 2 .5p Rpar=24G noiseless +A2 0 N003 0 0 0 0 X 0 OTA g=21u Iout=1.03u Cout=14.6p en=28n enk=.7 Vhigh=1e308 Vlow=-1e308 +C10 N003 0 10f Rpar=100K noiseless +D2 3 1 DBIAS +D3 3 2 DBIAS +D4 X 3 XU +D5 4 X XD +D1 N004 5 Y +D6 5 N004 Y +G1 0 N004 N009 0 1µ +G2 0 N008 N007 0 1m +L1 N008 0 1.68m Rser=1.39k Rpar=3.564102564102564k Cpar=28.01p noiseless +C11 5 N004 8p noiseless Rser=100k +G4 0 N009 N008 0 1m +C12 N009 0 5.15n Rpar=1e3 +G5 0 N007 X 0 1m +L3 N007 0 2.63m noiseless Rser=1100.833965125099 Rpar=10917.2932330827 +R3 2 1 857Meg noiseless +D7 3 4 DP +.model XU D(Ron=1K Roff=100G Vfwd=-.624 epsilon=.3 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-15.3m epsilon=.1 noiseless) +.model Y D(Ron=100K Roff=1T Vfwd=.5 epsilon=.1 noiseless) +.model N VDMOS(Vto=-10m Kp=50m) +.model P VDMOS(Vto=10m Kp=50m pchan) +.model DBIAS D(Roff=1T Ron=1k Vfwd=1 ilimit=6n noiseless) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=35.4u noiseless) +.ends LT1078 +* +.subckt LT1097 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=8f ink=140 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.7,.1), V(4)+.7, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.69,.1), V(4)+.69, .1)+1n*V(2) +C6 3 1 .5p Rpar=4T noiseless +C7 1 4 .5p noiseless Rpar=4T +C8 2 4 .5p Rpar=4T noiseless +C9 3 2 .5p Rpar=4T noiseless +A2 0 N004 0 0 0 0 N005 0 OTA g=52.5u iout=2.4u cout=12p en=14n enk=2.5 Vhigh=1e308 Vlow=-1e308 +C10 N004 0 400f Rpar=100K noiseless +D1 N005 3 X +D4 4 N005 X +M1 3 N003 5 5 N temp=27 +M2 4 N003 5 5 P temp=27 +C1 N003 0 40f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +D5 N003 5 YU +D6 5 N003 YD +G1 0 N003 N005 0 1µ +C2 2 1 .1p Rpar=80Meg noiseless +D2 3 4 DP +.model X D(Ron=1K Roff=100G Vfwd=-.95 epsilon=1.0 noiseless) +.model YU D(Ron=500 Roff=1T Vfwd=.98 epsilon=0.1 noiseless) +.model YD D(Ron=500 Roff=1T Vfwd = .915 epsilon=0.1 noiseless) +.model N VDMOS(Vto=-17m Kp=30m) +.model P VDMOS(Vto=17m Kp=30m pchan) +.model DP D(Ron=1k Roff=1T Vfwd=0.7 ilimit=345.5u noiseless) +.ends LT1097 +* +.subckt LTC1100 1 2 3 4 5 6 7 8 +M1 5 N007 N001 N001 N temp=27 +M2 4 N007 N001 N001 P temp=27 +C3 5 N001 .5p +C4 N001 4 .5p +B1 0 N005 I=10u*dnlim(uplim(V(3),V(5)-1.3,.1), V(4)-0.3, .1)+1n*V(3) +B2 N005 0 I=10u*dnlim(uplim(V(2),V(5)-1.29,.1), V(4)-0.31, .1)+1n*V(2) +C9 5 2 1p Rser=100 noiseless +C10 N005 0 1f Rpar=100K noiseless +D1 N007 N001 YU +D6 N001 N007 YD +G3 N003 0 N003 5 600m dir=1 vto=-.1 +G6 0 N003 4 N003 600m dir=1 vto=-.1 +R4 5 N003 1G +R5 N003 4 1G +C2 5 3 1p Rser=100 noiseless +C6 2 4 1p Rser=100 noiseless +C7 3 4 1p Rser=100 noiseless +R3 5 4 7.5k noiseless +G4 0 N007 N003 0 1µ +A3 0 N004 0 0 0 0 N003 0 OTA g=60.5m Iout=22.5m Cout=5n Vlow=-1e308 Vhigh=1e308 +C8 N007 0 1f Rpar=1Meg noiseless +L2 N006 0 39.3m Rser=123k Rpar=534.78k Cpar=31.8f noiseless +G2 0 N004 N006 0 .1µ +C11 N004 0 100f Rpar=10Meg noiseless +D2 N004 N006 DLS +M3 5 N016 8 8 N temp=27 +M4 4 N016 8 8 P temp=27 +C1 5 8 .5p +C5 8 4 .5p +B3 0 N014 I=10u*dnlim(uplim(V(6),V(5)-1.3,.1), V(4)-0.3, .1)+1n*V(6) +B4 N014 0 I=10u*dnlim(uplim(V(7),V(5)-1.29,.1), V(4)-0.31, .1)+1n*V(7) +C12 5 7 1p Rser=100 noiseless +C13 N014 0 1f Rpar=100K noiseless +D3 N016 8 YU +D4 8 N016 YD +G1 N012 0 N012 5 600m dir=1 vto=-.1 +G5 0 N012 4 N012 600m dir=1 vto=-.1 +R1 5 N012 1G +R2 N012 4 1G +C14 5 6 1p Rser=100 noiseless +C15 7 4 1p Rser=100 noiseless +C16 6 4 1p Rser=100 noiseless +G7 0 N016 N012 0 1µ +A5 0 N013 0 0 0 0 N012 0 OTA g=60.5m Iout=22.5m Cout=5n Vlow=-1e308 Vhigh=1e308 +C17 N016 0 1f Rpar=1Meg noiseless +L1 N015 0 39.3m Rser=123k Rpar=534.78k Cpar=31.8f noiseless +G8 0 N013 N015 0 .1µ +C18 N013 0 100f Rpar=10Meg noiseless +D8 N013 N015 DLS +D5 5 4 DP +R8 2 1 247.5k +R9 N001 2 2.5k +R7 N001 7 2.5k +R6 8 7 247.5k +A1 0 N005 0 0 0 0 N006 0 OTA g=12u linear en=70.5n -5.5p*min(max(freq,100),8k) Vlow=-1 Vhigh=1 +A2 0 N014 0 0 0 0 N015 0 OTA g=12u linear en=70.5n -5.5p*min(max(freq,100),8k) Vlow=-1 Vhigh=1 +.model YU D(Ron=20K Roff=1T Vfwd=.3 epsilon=.5 noiseless) +.model YD D(Ron=10k Roff=1T Vfwd=.5 epsilon=.4 noiseless) +.model N VDMOS(Vto=-200m Kp=15m) +.model P VDMOS(Vto=200m Kp=20m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=.378m noiseless) +.model DLS D(Roff=1G Ron=100k Vfwd=1.3 Vrev=1.3 epsilon=100m revepsilon=100m noiseless) +.ends LTC1100 +* +.subckt LT1101 1 2 3 4 5 6 7 8 +R1 1 2 828E3 +R2 2 100 82800 +R3 100 101 9.2E3 +R4 101 102 9.2E3 +R5 102 7 82800 +R6 7 8 828E3 +X1 3 100 5 4 101 LT1078 +X2 6 102 5 4 8 LT1078 +.ends LT1101 +* +* GND GA IN- VN VP IN+ GB OUT +.subckt LT1102 1 2 3 4 5 6 7 8 +R1 1 2 162000 +R2 2 100 16200 +R3 100 101 1800 +R4 101 102 1800 +R5 102 7 16200 +R6 7 8 162000 +X1 3 100 5 4 101 LT1057 +X2 6 102 5 4 8 LT1057 +R7 3 0 1E12 +R8 6 0 1E12 +.ends LT1102 +* +.subckt LT1112 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=8f ink=140 +B1 0 N007 I=10u*dnlim(uplim(V(1),V(3)-.65,.1), V(4)+0.65, .1)+1n*V(1) +B2 N007 0 I=10u*dnlim(uplim(V(2),V(3)-.64,.1), V(4)+.64, .1)+1n*V(2) +C6 3 1 .1p Rpar=1.5T noiseless +C7 1 4 .1p noiseless Rpar=1.5T +C8 2 4 .1p Rpar=1.5T noiseless +C9 3 2 .1p Rpar=1.5T noiseless +C10 N007 0 448f Rpar=100K noiseless +M1 N006 N009 5 5 N temp=27 +M2 N012 N009 5 5 P temp=27 +C1 N009 0 44.8f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +D5 N009 5 YU +D6 5 N009 YD +G1 0 N009 N003 0 1µ +C2 2 1 1p +A3 0 N007 0 0 0 0 N008 0 OTA g=1m linear en=13n enk=2.5 Vhigh=1e308 Vlow=-1e308 +G4 0 N004 N005 0 1m +L1 N005 0 1.54m Cpar=29.8p Rser=3.31k Rpar=1.43290043290044k +L2 N004 0 304µ Cpar=13.6p Rser=2.07k Rpar=1.93457943925235k noiseless +A2 0 N004 0 0 0 0 N003 0 OTA g=415u iout=29u Vhigh=1e308 Vlow=-1e308 +C11 N003 0 113p Rser=10k noiseless +C12 N008 0 1.13n Rpar=1k noiseless +G2 0 N005 N008 0 1m +D2 3 4 DC +D3 2 1 DIN +A4 0 N004 N011 0 0 0 N003 0 OTA g=40u asym isource=20u isink=-40u vlow=-1e308 vhigh=1e308 +C13 N011 0 100p Rpar=1k noiseless +B3 0 N011 I=(.5m+.5m*tanh((V(2,1)-1)/50m))+(.5m+.5m*tanh((V(1,2)-1)/50m)) +R1 3 N003 10G noiseless +G3 N003 0 N003 N006 5m dir=1 vto=-.85 +G5 0 N003 N012 N003 5m dir=1 vto=-.85 +R2 N003 4 10G noiseless +R3 3 N006 150 noiseless +R4 N012 4 150 noiseless +.model YU D(Ron=1.1k Roff=1T Vfwd=1.15 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=1.1 epsilon=.1 noiseless) +.model DIN D(Ron=10 Roff=50Meg vfwd=900m epsilon=200m vrev=900m revepsilon=200m noiseless) +.model DC D(Ron=1k, Roff=1T Vfwd=1 ilimit=334u noiseless) +.model N VDMOS(Vto=-40m Kp=20m) +.model P VDMOS(Vto=40m Kp=20m pchan) +.ends LT1112 +* +.subckt LT1113 1 2 3 4 5 +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 430f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+3.9, .1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+3.89, .1)+1n*V(2) +C6 3 1 7p Rpar=200G noiseless +C7 1 4 7p noiseless Rpar=200G +C8 2 4 7p Rpar=200G noiseless +C9 3 2 7p Rpar=200G noiseless +A2 0 N003 0 0 0 0 N006 0 OTA g=100.8u Iout=10.869u Cout=2.78p en=4.5n enk=120 Vhigh=1e308 Vlow=-1e308 +C10 N003 0 10f Rpar=100K noiseless +D2 3 1 DBIAS +D3 3 2 DBIAS +D4 N006 3 X +D5 4 N006 X +D1 N004 5 Y +D6 5 N004 Y +G2 0 N005 N006 0 1m +L1 N005 0 166µ Rser=1.04k Rpar=26k Cpar=63.7f noiseless +D7 3 4 DP +G1 0 N004 N005 0 1µ +A3 2 1 0 0 0 0 0 0 OTA g=0 in=1f incm=1e-17*freq/(1+1e-12*freq**2) +.model X D(Ron=1K Roff=100G Vfwd=-1.22 epsilon=.3 noiseless) +.model Y D(Ron=10K Roff=1T Vfwd=0.8 epsilon=.1 noiseless) +.model N VDMOS(Vto=-220m Kp=55m) +.model P VDMOS(Vto=220m Kp=55m pchan) +.model DBIAS D(Roff=1T Ron=1k Vfwd=1 ilimit=300p noiseless) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=3.97m noiseless) +.ends LT1113 +* +.subckt LT1116 1 2 3 4 5 6 7 8 +A3 5 6 0 0 0 0 N010 0 SCHMITT Vt=1.5 Vh=0 tau=3n +B1 0 VD0 I=10u*dnlim(uplim(V(2),V(1)-2.4,.1), V(4)-.1,.1)+1n*V(2) +B2 VD0 0 I=10u*dnlim(uplim(V(3),V(1)-2.39,.1), V(4)-0.11, .1)+1n*V(3) +C1 VD0 0 .01f Rpar=100K noiseless +A1 0 VD0 0 0 0 0 VD1 0 OTA g=11m iout=75u Vlow=-1e308 Vhigh=1e308 Cout=1f +C5 1 7 .1p +C6 7 6 .1p +G5 0 X VD1 0 60n +D5 0 VD1 DLAT +G2 0 XN 0 VD1 60n +A2 N005 0 N010 0 0 0 VD1 0 OTA g=500u linear Vlow=-1e308 Vhigh=1e308 +D1 0 N005 DLAT +C3 N005 0 1f +G3 0 N005 0 VD1 500µ +C4 3 4 1.75p +C10 2 4 1.75p +D13 1 4 DP1 +D14 1 6 DP2 +D3 X 1 XU +D4 6 X XD +M1 1 VN 7 7 N temp=27 +M2 6 VP 7 7 P temp=27 +R6 VN X 4G +D16 VN 6 DVLU2 +R7 VP X 4G +D17 6 VP DVLD +C7 1 8 .1p +C8 8 6 .1p +D7 XN 1 XU +D8 6 XN XD +M3 1 N007 8 8 N temp=27 +M4 6 N008 8 8 P temp=27 +R8 N007 XN 4G +D19 N007 6 DVLU2 +R9 N008 XN 4G +D20 6 N008 DVLD +C11 1 3 1.75p +C12 1 2 1.75p +D6 1 3 DBIAS +D9 1 2 DBIAS +D10 1 5 DLATCH +A4 0 VD1 0 0 0 0 X 0 OTA g=80n asym isource=1u isink=0 Vlow=-1e308 Vhigh=1e308 Cout=.09f +A5 VD1 0 0 0 0 0 XN 0 OTA g=80n asym isource=1u isink=0 Vlow=-1e308 Vhigh=1e308 Cout=.09f +.model DBIAS D(Ron=10k Roff=10G Vfwd=1.35 epsilon=.1 ilimit=10u) +.model DLATCH D(Ron=1k Roff=10Meg Vfwd=1 epsilon=.1 ilimit=500u) +.model DP1 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=5m) +.model DP2 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=18.2m) +.model XU D(Ron=1k Roff=1.7G Vfwd=1 epsilon=.1) +.model XD D(Ron=1k Roff=637Meg Vfwd=8.5 epsilon=.1) +.model DVLU1 D(Ron=1.5G Roff=100G Vfwd=1.1 epsilon=2.5) +.model DVLU2 D(Ron= 5Meg Roff=100G Vfwd=3.5 epsilon=.1) +.model DVLD D(Ron= 5Meg Roff=100G Vfwd=-580m epsilon=.1) +.model DLAT D(Ron=1 Roff=10k Vfwd=560m Vrev=560m epsilon=5m revepsilon=5m) +.model N VDMOS(Vto= -300m kp=230m rds=2k) +.model P VDMOS(Vto= 400m Kp=580m rds=2k pchan ) +.ends LT1116 +* +.subckt LT1122 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2f ink=2 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-3.9,.1), V(4)+3.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-3.89,.1), V(4)+3.89, .1)+1n*V(2) +C6 3 1 2p Rpar=1T noiseless +C7 1 4 2p noiseless Rpar=1T +C8 2 4 2p Rpar=1T noiseless +C9 3 2 2p Rpar=1T noiseless +A2 0 N004 0 0 0 0 N007 0 OTA g=10.6u Iout=10.49u en=14n enk=210 Vlow=-1e308 Vhigh=1e308 Cout= 130f +C10 N004 0 31.33f Rpar=100K noiseless +D4 N007 3 X +D5 4 N007 X +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +G2 0 N006 N007 0 1m +L4 N006 0 25.9µ Cpar=1.3p Rser=2.29k Rpar=1.775193798449612403K noiseless +C1 N005 0 3.83f Rpar=1Meg noiseless +G4 0 N005 N006 0 1µ +.model X D(Ron=1K Roff=100G Vfwd=-2.5 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=2.0 epsilon=.1 noiseless) +.model N VDMOS(Vto=-330m Kp=50m) +.model P VDMOS(Vto=330m Kp=50m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=4.78m noiseless) +.ends LT1122 +* +.subckt LT1124 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.3p ink=100 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-2.1,.1), V(4)+2.1, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-2.09,.1), V(4)+2.09, .1)+1n*V(2) +C6 3 1 .1p +C7 1 4 .1p +C8 2 4 .1p +C9 3 2 .1p +A2 0 N004 0 0 0 0 N007 0 OTA g=.34m Iout=18.7u en=2.7n enk=2.3 Vlow=-1e308 Vhigh=1e308 Cout= 4.1p +C10 N004 0 1.5f Rpar=100K noiseless +D4 N007 3 X +D5 4 N007 X +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +G2 0 N006 N007 0 1m +L4 N006 0 141µ Cpar=5.89p Rser=1.96k Rpar=2.0416666666666666667K noiseless +C2 N005 0 .457p Rpar=1Meg Rser=244.5k noiseless +G1 0 N005 N006 0 1µ +D2 2 1 DIN +.model X D(Ron=1K Roff=100G Vfwd=-1.26 epsilon=.1 noiseless) +.model Y D(Ron=100 Roff=1T Vfwd=.83 epsilon=.1 noiseless) +.model N VDMOS(Vto=-320m Kp=40m) +.model P VDMOS(Vto=320m Kp=40m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=.252m noiseless) +.model DIN D(Roff=1T Ron=1k Vfwd=1 Vrev=1 noiseless) +.ends LT1124 +* +.subckt LT1126 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.3p ink=100 +M1 3 N006 5 5 N temp=27 +M2 4 N006 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-2.1,.1), V(4)+2.1, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-2.09,.1), V(4)+2.09, .1)+1n*V(2) +C6 3 1 .1p +C7 1 4 .1p +C8 2 4 .1p +C9 3 2 .1p +A2 0 N004 0 0 0 0 N008 0 OTA g=412.3m Iout=14.5m en=2.7n enk=2.3 Vlow=-1e308 Vhigh=1e308 Cout= 4.15u +C10 N004 0 22.7f Rpar=100K noiseless +D4 N006 3 X +D5 4 N006 X +D1 N006 5 Y +D6 5 N006 Y +D7 3 4 DP +D2 2 1 DIN +G3 0 N007 N008 0 1m +L1 N007 0 144.7µ Cpar=.285p Rpar=11k Rser=1.1k noiseless +G2 0 N005 N007 0 1m +L2 N005 0 144.7µ Cpar=.285p Rpar=11k Rser=1.1k noiseless +G1 0 N006 N005 0 82.46n +C2 N006 0 2.63e-17 +D3 0 N008 DCL +.model X D(Ron=1K Roff=100G Vfwd=-1.2 epsilon=.1 noiseless) +.model Y D(Ron=100 Roff=1T Vfwd=.83 epsilon=.1 noiseless) +.model N VDMOS(Vto=-320m Kp=40m) +.model P VDMOS(Vto=320m Kp=40m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=.552m noiseless) +.model DIN D(Roff=1T Ron=1k Vfwd=1 Vrev=1 noiseless) +.model DCL D(Roff=10k Ron=.1 Vfwd=20m Vrev=20m epsilon=4m noiseless) +.ends LT1126 +* +.subckt LT1128 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.9p ink=250 +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N008 I=10u*dnlim(uplim(V(1),V(3)-2.7,.1), V(4)+2.7, .1)+1n*V(1) +B2 N008 0 I=10u*dnlim(uplim(V(2),V(3)-2.69,.1), V(4)+2.69, .1)+1n*V(2) +C6 3 1 2.5p Rpar=1.2G noiseless +C7 1 4 2.5p noiseless Rpar=1.2G +C8 2 4 2.5p Rpar=1.2G noiseless +C9 3 2 2.5p Rpar=1.2G noiseless +A2 0 N008 0 0 0 0 X 0 OTA g=630u Iout=78.9u en=.85n+freq*36u/(8k*freq+(freq-400k)**2) Vlow=-1e308 Vhigh=1e308 Cout= 5.9p enk=3 +C10 N008 0 1f Rpar=100K noiseless +D4 X 3 X +D5 4 X X +D1 N007 5 Y +D6 5 N007 Y +D7 3 4 DP +C11 2 1 12.5p Rpar=20k noiseless +D2 2 1 DIN +G1 0 N004 X 0 1m +L3 N004 0 100.47µ Rser=1.01636k Rpar=62.1246943765281k noiseless +G2 0 N006 N005 0 1m +L4 N006 0 1.86m Cpar=2p Rser=1.39k Rpar=3.564102564102564k noiseless +G3 0 N005 N004 0 1m +L5 N005 0 2.56m noiseless Rpar=2.086956521739131k Cpar=.103n Rser=1.92k +C1 N007 0 1.67p Rpar=1Meg Rser=58.823k noiseless +G4 0 N007 N006 0 1µ +.model X D(Ron=1K Roff=100G Vfwd=-2 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=1.375 epsilon=.1 noiseless) +.model N VDMOS(Vto=-200m Kp=31m) +.model P VDMOS(Vto=200m Kp=31m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=6.783m noiseless) +.model DIN D(Ron=100 Roff=1T Vfwd=1.8 Vrev=1.8 noiseless) +.ends LT1128 +* +.subckt LTC1150 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.8f +M1 3 N006 5 5 N temp=27 +M2 4 N006 5 5 P temp=27 +C1 N006 0 400f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 N007 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-0.3, .1)+1n*V(1) +B2 N007 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-0.31, .1)+1n*V(2) +C9 3 2 1p Rser=100 noiseless +C10 N007 0 1f Rpar=100K noiseless +D1 N006 5 YU +D6 5 N006 YD +D7 3 4 DP +G3 N004 0 N004 3 600m dir=1 vto=-.5 +G6 0 N004 4 N004 600m dir=1 vto=-.6 +R4 3 N004 1G +R5 N004 4 1G +G2 0 N006 N008 0 1µ +C2 3 1 1p Rser=100 noiseless +C6 2 4 1p Rser=100 noiseless +C7 1 4 1p Rser=100 noiseless +R3 3 4 22Meg noiseless +G4 0 N008 N004 0 1m +L2 N008 0 436µ Rser=1.3703703703703703704k Rpar=3.7k Cpar=6.63p noiseless +C8 N005 0 2.6p noiseless Rser=6.7k Rpar=500k +G1 0 N004 N005 0 20.5m +A2 0 N007 0 0 0 0 N005 0 OTA g=200u linear en=15n+(43n+ 1n*min(max(freq,350),600)**.83)/ (1.3+ (max(freq,600)/600)**1.2 +1e-14*freq**4) Vlow=-10.4 Vhigh=10.4 +C12 N004 0 70n Rser=6 noiseless +.model YU D(Ron=1.5K Roff=1T Vfwd=.2 epsilon=.3 noiseless) +.model YD D(Ron=38k Roff=1T Vfwd=.1 epsilon=.1 noiseless) +.model N VDMOS(Vto=-200m Kp=20m) +.model P VDMOS(Vto=200m Kp=30m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=313.73u noiseless) +.ends LTC1150 +* +.subckt LTC1151 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2.2f +M1 3 N006 5 5 N temp=27 +M2 4 N006 5 5 P temp=27 +C1 N006 0 200f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 N007 I=10u*dnlim(uplim(V(1),V(3)-1.6,.1), V(4)-0.3, .1)+1n*V(1) +B2 N007 0 I=10u*dnlim(uplim(V(2),V(3)-1.59,.1), V(4)-0.31, .1)+1n*V(2) +C9 3 2 1p Rser=100 noiseless +C10 N007 0 1f Rpar=100K noiseless +D1 N006 5 YU +D6 5 N006 YD +D7 3 4 DP +G3 N004 0 N004 3 600m dir=1 vto=-.5 +G6 0 N004 4 N004 600m dir=1 vto=-.6 +R4 3 N004 1G +R5 N004 4 1G +G2 0 N006 N008 0 1µ +C2 3 1 1p Rser=100 noiseless +C6 2 4 1p Rser=100 noiseless +C7 1 4 1p Rser=100 noiseless +R3 3 4 22Meg noiseless +G4 0 N008 N004 0 1m +L2 N008 0 383µ Rser=1.2k Rpar=6k Cpar=2p noiseless +C8 N005 0 1p noiseless Rser=10k Rpar=500k +G1 0 N004 N005 0 2.05m +C12 N004 0 1.3n Rser=120 noiseless +A2 0 N007 0 0 0 0 N005 0 OTA g=20u linear en=15n+ 100n/ (1.5+ (max(freq,10)/10)**.8) Vlow=-1.62 Vhigh=1.62 +.model YU D(Ron=1.5K Roff=1T Vfwd=.2 epsilon=.3 noiseless) +.model YD D(Ron=38k Roff=1T Vfwd=.1 epsilon=.1 noiseless) +.model N VDMOS(Vto=-200m Kp=20m) +.model P VDMOS(Vto=200m Kp=30m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=313.73u noiseless) +.ends LTC1151 +* +.subckt LTC1152 1 2 3 4 5 6 7 8 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.6f +B1 0 N009 I=10u*dnlim(uplim(V(1),V(3)+.4,.1), V(4)-.4, .1)+1n*V(1) +B2 N009 0 I=10u*dnlim(uplim(V(2),V(3)+.41,.1), V(4)-.41, .1)+1n*V(2) +C9 3 2 1p Rpar=1T noiseless +C10 N009 0 10f Rpar=100K noiseless +M1 3 N011 N013 N013 N temp=27 +M2 4 N014 N013 N013 P temp=27 +C3 3 5 1p Rpar=1G noiseless +D5 N011 N013 YU +D6 N013 N014 YD +R2 3 N012 2G noiseless +R3 N012 4 2G noiseless +A3 7 3 0 0 0 0 N010 0 SCHMITT Vt=-2 Vh=10m tau=50u +A4 N010 0 N012 N012 N012 N012 N011 N012 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-15 Rout=1k Cout=.1p +A5 N010 0 N012 N012 N012 N014 N012 N012 SCHMITT Vt=.5 Vh=10m Vhigh=15 Vlow=0 Rout=1k Cout=.1p +C4 5 4 1p Rpar=1G noiseless +C14 0 6 17p Rpar=6k noiseless +C1 2 4 1p Rpar=1T noiseless +C6 3 1 1p Rpar=1T noiseless +C7 1 4 1p Rpar=1T noiseless +A7 6 0 N010 0 0 0 N012 0 OTA g=3.2m iout=500u Cout=560p Vlow=-1e308 Vhigh=1e308 +G1 N012 0 N012 3 500m dir=1 vto=.01 +G2 0 N012 4 N012 500m dir=1 vto=.01 +G8 3 N003 N005 3 1 +G9 3 N003 8 3 2 +G10 N005 3 N003 3 1 +G11 8 3 N003 3 2 +R6 N003 3 1G noiseless +C12 N005 3 1p Rpar=1Meg noiseless +S3 N005 N004 N010 0 SHTCP +C11 8 3 1p Rpar=100Meg noiseless +R1 4 N007 1Meg noiseless +D7 3 N007 DREF +R8 N004 3 100Meg noiseless +S4 4 N004 N004 N007 SREG +D8 3 8 DCP +G3 0 6 0 N015 167µ +D1 3 7 DSIN +S1 N013 5 3 4 SRO +C2 3 N013 1p Rpar=1G noiseless +C15 N013 4 1p Rpar=1G noiseless +A2 0 N009 0 0 0 0 N015 0 OTA g=1m iout=100u en=130n/(1+ (freq/2e3)**1.9) Rout=1k Cout=50p Vlow=-1e308 Vhigh=1e308 +S2 3 4 N010 0 SPOW +.model YU D(Ron=100 Roff=1T Vfwd=.55 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.65 epsilon=.1 noiseless) +.model N VDMOS(Vto=-100m Kp=50m) +.model P VDMOS(Vto=100m Kp=50m pchan) +.model DSIN D(Ron=10k Roff=1G Vfwd=.7 epsilon=10m ilimit=1u noiseless) +.model shutD SW(Ron=1T Roff=10k vt=.5 vh=-.1) +.model DS D(Ron=100 Roff=1G Vfwd=.2 Vrev=.2 epsilon=0.1 revepsilon=0.1 noiseless) +.model SPOW SW(level=2 Ron=500 Roff=1G vt=.5 vh=-.1 ilimit=2.06m noiseless) +.model SREG SW(level=2 Ron=100 Roff=1G vt=-.1 vh=-10m noiseless) +.model SRO SW(level=2 Ron=10 Roff=400 vt=4.7 vh=-1.2 noiseless) +.model DREF D(Ron=1k Roff=100Meg vfwd=5.2 epsilon=10m noiseless) +.model DCP D(Ron=100 Roff=100Meg vfwd=.7 epsilon=100m noiseless) +.model SHTCP SW(level=2 Ron=28k Roff=1G vt=.5 vh=-.1 ilimit=.2m noiseless) +.ends LTC1152 +* +.subckt LT1167 1 2 3 4 5 6 7 8 +A2 0 N014 0 0 0 0 N017 0 OTA g=27.8u Iout=5u Cout=270f en=5.3n enk=10 Vhigh=1e308 Vlow=-1e308 +DU1 N017 7 XU +DD1 4 N017 XD +DU2 N006 7 XU +DD2 4 N006 XD +G2 0 N003 N006 0 1m +C3 N003 0 100f Rpar=1k +R6 N004 1 24.7k noiseless +R7 1 8 1t noiseless +R8 8 N018 24.7k noiseless +C5 7 2 .8p Rpar=2T noiseless +C6 7 1 .1p Rpar=2T noiseless +C7 7 3 .8p Rpar=2T noiseless +C8 2 4 .8p Rpar=2T noiseless +C9 1 4 .1p Rpar=2T noiseless +C10 3 4 .8p Rpar=2T noiseless +C11 7 8 .1p Rpar=2T noiseless +C12 8 4 .1p Rpar=2T noiseless +DU3 N011 7 X2U +DD3 4 N011 X2D +G1 0 N009 N011 0 1µ +CG1 N009 0 160f Rpar=1Meg noiseless +R1 N004 N005 10k noiseless +R2 N018 N012 10k noiseless +M1 7 N010 6 6 N temp=27 +M2 4 N010 6 6 P temp=27 +D1 N010 6 YU +D2 6 N010 YD +A1 0 N002 0 0 0 0 N006 0 OTA g=27.8u Iout=5u Cout=270f en=5.3n enk=10 Vhigh=1e308 Vlow=-1e308 +A0 2 3 0 0 0 0 0 0 OTA g=0 in=57f ink=37 +C13 N002 0 50f Rpar=100K noiseless +C15 N014 0 50f Rpar=100K noiseless +CG4 7 6 1p +CG5 6 4 1p +M3 7 N003 N004 N004 NINT temp=27 +M4 4 N003 N004 N004 PINT temp=27 +M5 7 N016 N018 N018 NINT temp=27 +M6 4 N016 N018 N018 PINT temp=27 +G3 0 N016 N017 0 1m +C17 N016 0 100f Rpar=1k noiseless +A3 N005 N012 0 0 0 0 N011 0 OTA g=238.8u Iout=54.2u Cout=45p en=33.5n enk=16 Vlow=-1e308 Vhigh=1e308 +C1 0 N004 1p +C18 N018 0 1p +C19 1 8 5p Rser=20 noiseless +C20 2 3 .8p +C21 N004 1 5p Rser=20 noiseless +C22 8 N018 5p Rser=20 noiseless +R3 N005 6 10k noiseless +R4 N012 5 10k noiseless +C2 0 N005 1p +C14 N012 0 1p +DB2 7 4 DP +G5 0 N010 N009 0 10µ +CG2 N010 0 2p Rpar=100k noiseless +B1 0 N002 I=10u*dnlim(uplim(V(2)-.5,V(7)-1.79,.1), V(4)+1.29, .1)+1n*V(2) +B2 0 N014 I=10u*dnlim(uplim(V(3)-.5,V(7)-1.8,.1), V(4)+1.3, .1)+1n*V(3) +B3 N002 0 I=10u*dnlim(uplim(V(1),V(7)-1.79,.1), V(4)+.5, .1)+1n*V(1) +B4 N014 0 I=10u*dnlim(uplim(V(8),V(7)-.5,.1), V(4)+.5, .1)+1n*V(8) +.model XU D(Ron=1k Roff=100g Vfwd=0 epsilon=100m noiseless) +.model XD D(Ron=1k Roff=100g Vfwd=0 epsilon=100m noiseless) +.model DP D(Ron=1k Vfwd=.6 epsilon=100m ilimit=405u noiseless) +.model NINT VDMOS(Vto=-40m Kp=100m) +.model PINT VDMOS(Vto=40m Kp=100m pchan) +.model X2U D(Ron=1k Roff=100G Vfwd=-.9 epsilon=.1 noiseless) +.model X2D D(Ron=1k Roff=100G Vfwd=-.65 epsilon=.1 noiseless) +.model YU D(Ron=50 Roff=1G Vfwd=.63 epsilon=.1 noiseless) +.model YD D(Ron=500 Roff=1G Vfwd=.65 epsilon=.1 noiseless) +.model N VDMOS(Vto=-80m Kp=100m Rds=1Meg) +.model P VDMOS(Vto=80m Kp=100m Rds=1Meg pchan) +.model DDROP D(Roff=100k Ron=5 Vfwd=150m Vrev=1 epsilon=.1 noiseless) +.ends LT1167 +* +.subckt LT1168 1 2 3 4 5 6 7 8 +A2 0 N019 0 0 0 0 N016 0 OTA g=27.8u Iout=400n Cout=800f en=7n enk=10 Vhigh=1e308 Vlow=-1e308 +DU1 N016 7 XU +DD1 4 N016 XD +DU2 N006 7 XU +DD2 4 N006 XD +G2 0 N003 N006 0 1m +C3 N003 0 50f Rpar=1k +R6 N004 8 24.7k noiseless +R7 8 1 1t noiseless +R8 1 N017 24.7k noiseless +C5 7 2 .8p Rpar=2T noiseless +C6 7 8 .8p Rpar=2T noiseless +C7 7 3 .8p Rpar=2T noiseless +C8 2 4 .8p Rpar=2T noiseless +C9 8 4 .8p Rpar=2T noiseless +C10 3 4 .8p Rpar=2T noiseless +C11 7 1 .8p Rpar=2T noiseless +C12 1 4 .8p Rpar=2T noiseless +DU3 N011 7 X2U +DD3 4 N011 X2D +G1 0 N009 N010 0 1µ +CG1 N009 0 4p Rpar=1Meg noiseless +R1 N004 N005 30k noiseless +R2 N017 N012 30k noiseless +M1 7 N009 6 6 N temp=27 +M2 4 N009 6 6 P temp=27 +D1 N009 6 YU +D2 6 N009 YD +A1 0 N002 0 0 0 0 N006 0 OTA g=27.8u Iout=400n Cout=800f en=7n enk=10 Vhigh=1e308 Vlow=-1e308 +A0 2 3 0 0 0 0 0 0 OTA g=0 in=29f ink=54 +B1 0 N002 I=10u*dnlim(uplim(V(2),V(7)-1.09,.1), V(4)+1.79, .1)+1n*V(2) +C13 N002 0 5f Rpar=100K noiseless +C15 N019 0 5f Rpar=100K noiseless +CG4 7 6 1p +CG5 6 4 1p +M3 7 N003 N004 N004 NINT temp=27 +M4 4 N003 N004 N004 PINT temp=27 +M5 7 N015 N017 N017 NINT temp=27 +M6 4 N015 N017 N017 PINT temp=27 +G3 0 N015 N016 0 1m +C17 N015 0 50f Rpar=1k noiseless +A3 N005 N012 0 0 0 0 N011 0 OTA g=238.8u Iout=17.7u Cout=35p en=80n enk=2.5 Vlow=-1e308 Vhigh=1e308 +C19 8 1 5p Rser=10 noiseless +C20 2 3 .8p +C21 N004 8 5p Rser=10 noiseless +C22 1 N017 8p Rser=10 noiseless +R3 N005 6 30k noiseless +R4 N012 5 30k noiseless +C2 0 N005 .1p +C14 N012 0 .1p +DB2 7 4 DP +G4 N002 0 8 0 10µ +B2 0 N019 I=10u*dnlim(uplim(V(3),V(7)-1.1,.1), V(4)+1.8, .1)+1n*V(3) +G6 N019 0 1 0 10µ +G5 0 N010 N011 0 1m +L1 N010 0 2.49m Rpar=2.78k Rser=1.56k cpar=6.4p noiseless +C1 0 N004 1p Rser=10 noiseless +C4 N017 0 1p Rser=10 noiseless +C18 6 N009 6p Rser=300k noiseless +C16 N005 N012 .1p +.model XU D(Ron=1k Roff=100g Vfwd=0 epsilon=100m noiseless) +.model XD D(Ron=1k Roff=100g Vfwd=0 epsilon=100m noiseless) +.model DP D(Ron=500 Vfwd=.6 epsilon=100m ilimit=221.4u noiseless) +.model NINT VDMOS(Vto=-15m Kp=2.8m) +.model PINT VDMOS(Vto=15m Kp=2.8m pchan) +.model X2U D(Ron=1k Roff=100G Vfwd=-.8 epsilon=.1 noiseless) +.model X2D D(Ron=1k Roff=100G Vfwd=-.65 epsilon=.1 noiseless) +.model YU D(Ron=50 Roff=1G Vfwd=1.2 epsilon=.1 noiseless) +.model YD D(Ron=500 Roff=1G Vfwd=1.4 epsilon=.1 noiseless) +.model N VDMOS(Vto=-80m Kp=40m) +.model P VDMOS(Vto=80m Kp=40m pchan) +.model DDROP D(Roff=100k Ron=5 Vfwd=150m Vrev=1 epsilon=.1 noiseless) +.ends LT1168 +* +.subckt LT1169 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1f incm=3.5e-18*freq/(1+1e-12*freq**2) +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+3.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+3.8, .1)+1n*V(2) +C6 3 1 .75p Rpar=2.0e15 noiseless +C7 1 4 .75p noiseless Rpar=2.0e15 +C8 2 4 .75p Rpar=2.0e15 noiseless +C9 3 2 .75p Rpar=2.0e15 noiseless +A2 0 N004 0 0 0 0 N007 0 OTA g=94.5u Iout=11.31u en=6n enk=60 Vlow=-1e308 Vhigh=1e308 Cout= 2.69p +C10 N004 0 20f Rpar=100K noiseless +D4 N007 3 X +D5 4 N007 X +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +G2 0 N006 N007 0 1m +L4 N006 0 132.9µ Cpar=8.04p Rser=3.14k Rpar=1.467289719626168224K noiseless +C2 N005 0 384f noiseless Rser=481k Rpar=1Meg +G1 0 N005 N006 0 1µ +R3 2 1 10T noiseless +D2 2 4 DBIAS +D3 1 4 DBIAS +.model X D(Ron=1K Roff=100G Vfwd=-1.24 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=1.5 epsilon=.1 noiseless) +.model N VDMOS(Vto=-200m Kp=43m) +.model P VDMOS(Vto=200m Kp=43m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=4.44m noiseless) +.model DBIAS D(Ron=10T Roff=100T epsilon=.1 Vfwd=5 noiseless) +.ends LT1169 +* +.subckt LT1178 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=10f ink=120 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C1 N005 0 12.8p Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.0,.1), V(4)-0.4, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.99,.1), V(4)-0.41, .1)+1n*V(2) +C6 3 1 .5p Rpar=24G noiseless +C7 1 4 .5p noiseless Rpar=24G +C8 2 4 .5p Rpar=24G noiseless +C9 3 2 .5p Rpar=24G noiseless +A2 0 N004 0 0 0 0 X 0 OTA g=14.8u Iout=923n Cout=36.9p en=49n enk=.5 Vhigh=1e308 Vlow=-1e308 +C10 N004 0 13.15p Rpar=100K noiseless +D2 3 1 DBIAS +D3 3 2 DBIAS +D4 X 3 XU +D5 4 X XD +D1 N005 5 YU +D6 5 N005 YD +G1 0 N005 N009 0 1µ +G2 0 N008 N010 0 1m +G4 0 N009 N008 0 1m +G5 0 N010 X 0 1m +R3 2 1 2G noiseless +D7 3 4 DP +L3 N009 0 3.18m Rser=1k noiseless +L2 N010 0 11m Rser=2.78k Rpar=1.5617977528089887641k Cpar=636p noiseless +C2 5 N005 6p Rser=10k noiseless +L1 N008 0 11m Rser=2.78k Rpar=1.5617977528089887641k Cpar=636p noiseless +.model XU D(Ron=1K Roff=100G Vfwd=-.585 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-23.4m epsilon=.1 noiseless) +.model YU D(Ron=10K Roff=1T Vfwd=1.9 epsilon=.1 noiseless) +.model YD D(Ron=10k Roff=1T Vfwd=1.22 epsilon=.1 noiseless) +.model N VDMOS(Vto=-3m Kp=9m) +.model P VDMOS(Vto=8m Kp=20m pchan) +.model DBIAS D(Roff=1T Ron=1k Vfwd=1 ilimit=3n noiseless) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=12.8u noiseless) +.ends LT1178 +* +.subckt LT1187 1 2 3 4 5 6 7 8 +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+2.39, .1)+1n*V(2) +M1 5 N015 4 4 NI1 temp=27 +C2 3 5 2p Rpar=100k noiseless +D5 N015 4 DLIMNB +C11 5 4 2p Rpar=100k +A4 0 N005 0 0 0 0 N004 0 OTA g=1m linear en=62.6n enk=791 Vlow=-.5 Vhigh=.4 +A5 N004 0 N014 N014 N014 N014 N009 N014 OTA g=550n linear cout=5f Vlow=-1e308 Vhigh=1e308 +G1 4 N015 N009 N014 60n +D9 N009 N014 DLIM +C13 3 4 1000p +C1 N004 0 2.8p Rpar=1k noiseless +G2 0 N014 4 0 .5m +G4 0 N014 3 0 .5m +C18 N014 0 200p Rpar=1K noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.46p ink=614 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+2.4, .1)+1n*V(1)-27.399n +S1 N006 4 N016 0 SBIAS +C4 3 2 1p Rser=100 Rpar=50Meg noiseless +R4 2 1 100k noiseless +R5 6 7 100k noiseless +A6 8 3 0 0 0 0 N016 0 SCHMITT trise=100n tfall=100n vt=-2.1 vh=10m +D13 3 8 DSHUT +S8 4 N015 0 N016 SHUT1 +D3 2 N006 DBIAS +D19 3 N006 DPOW2 +A2 6 7 0 0 0 0 0 0 OTA g=0 in=1.46p ink=614 +M2 3 N010 5 5 NI2 temp=27 +D8 N010 N012 DLIMNT +R1 5 N012 500k +C9 N015 4 1f Rser=1k noiseless +C3 N010 5 100f +S4 4 N012 N009 N014 SNPN +C7 N010 N009 1.15f +C19 N012 4 100f +C20 3 N010 10f +D21 N010 5 Y +S6 N012 4 0 N016 SHUT2 +S7 N010 4 0 N016 SHUT2 +C21 N006 4 1p +D1 3 N010 DMB +C17 N010 N012 8p Rser=1 noiseless +C22 3 8 1p +C5 3 1 1p Rser=100 Rpar=50Meg noiseless +C6 3 6 1p Rser=100 Rpar=50Meg noiseless +C8 3 7 1p Rser=100 Rpar=50Meg noiseless +C12 4 2 1p Rser=100 Rpar=20Meg noiseless +C14 4 1 1p Rser=100 Rpar=20Meg noiseless +C15 4 6 1p Rser=100 Rpar=20Meg noiseless +C16 4 7 1p Rser=100 Rpar=20Meg noiseless +D2 3 4 DPOW1 +C23 N008 0 3f Rpar=200K noiseless +B3 N008 0 I=10.1u*dnlim(uplim(V(7),V(3)-1.39,.1), V(4)+2.39, .1)+1n*V(7) +B4 0 N008 I=10.1u*dnlim(uplim(V(6),V(3)-1.4,.1), V(4)+2.4, .1)+1n*V(6) +A3 0 N008 0 0 0 0 N004 0 OTA g=1m linear Vlow=-.5 Vhigh=.4 +C10 N005 0 3f Rpar=200K noiseless +D4 N005 0 DINLIMA +D6 N008 0 DINLIMB +D7 1 N006 DBIAS +D10 6 N006 DBIAS +D11 7 N006 DBIAS +D12 3 N006 DPOW3 +.model SBIAS SW(level=2 Ron=10 Roff=1G vt=.5 vh=-.2 noiseless) +.model DBIAS D(Ron=620k Roff=1G vfwd=-6.3 epsilon=.2 ilimit=56n noiseless) +.model DSHUT D(Ron=1k Roff=110k Vfwd=1.7 epsilon=.1 ilimit=20u noiseless) +.model SPOW SW(level=2 Ron=10 Roff=1Meg vt=.5 vh=-.2 ilimit=1f noiseless) +.model DPOW1 D(Ron=1k Roff=1G vfwd=1 epsilon=.1 ilimit=.614m noiseless) +.model DPOW2 D(Ron=100 Roff=1G vfwd=1 epsilon=.1 ilimit= 1.2m noiseless) +.model DPOW3 D(Ron=1.2k Roff=1G Vfwd=.5 epsilon=.1 noiseless) +.model NI1 VDMOS(Vto=300m kp=70m lambda=.001) +.model NI2 VDMOS(Vto=400m kp=70m lambda=.001) +.model DLIM D(Ron=1k Roff=70Meg Vfwd=1 Vrev=1 epsilon=50m revepsilon=50m noiseless) +.model DLIMNB D(Ron=100k Roff=100Meg Vfwd=1.2 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMNT D(Ron=100 Roff=100Meg Vfwd=1 Vrev=2 epsilon=.1 revepsilon=.1 noiseless) +.model DINLIMA D(Ron=100 Roff=200k Vfwd=380m Vrev=380m epsilon=10m revepsilon=10m noiseless) +.model DINLIMB D(Ron=100 Roff=200k Vfwd=390m Vrev=390m epsilon=10m revepsilon=10m noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1 Roff=100G vt=-.8 vh=-100m noiseless) +.model SNPN SW(Ron=10 Roff=1Meg vt=170m vh=-200m noiseless) +.model DMB D(Ron=10 Roff=1Meg vfwd=.1 epsilon=.1 ilimit=100u noiseless) +.model Y D(Ron=4k Roff=1g vfwd=.95 epsilon=.1 noiseless) +.ends LT1187 +* +.subckt LT1189 1 2 3 4 5 6 7 8 +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+2.39, .1)+1n*V(2) +M1 5 N015 4 4 NI1 temp=27 +C2 3 5 2p Rpar=100k noiseless +D5 N015 4 DLIMNB +C11 5 4 2p Rpar=100k +A4 0 N005 0 0 0 0 N004 0 OTA g=1m iout=110u en=29.4n enk=385 Vlow=-1 Vhigh=1 +A5 N004 0 N014 N014 N014 N014 N009 N014 OTA g=1.3u linear cout=5f Vlow=-1e308 Vhigh=1e308 +G1 4 N015 N009 N014 60n +D9 N009 N014 DLIM +C13 3 4 1000p +C1 N004 0 2.6p Rpar=1k noiseless +G2 0 N014 4 0 .5m +G4 0 N014 3 0 .5m +C18 N014 0 200p Rpar=1K noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.2p ink=673 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+2.4, .1)+1n*V(1)-11.599n +S1 N006 4 N016 0 SBIAS +C4 3 2 1p Rser=100 Rpar=50Meg noiseless +R4 2 1 100k noiseless +R5 6 7 100k noiseless +A6 8 3 0 0 0 0 N016 0 SCHMITT trise=100n tfall=100n vt=-2.1 vh=10m +D13 3 8 DSHUT +S8 4 N015 0 N016 SHUT1 +D3 2 N006 DBIAS +D19 3 N006 DPOW2 +A2 6 7 0 0 0 0 0 0 OTA g=0 in=1.2p ink=673 +M2 3 N010 5 5 NI2 temp=27 +D8 N010 N012 DLIMNT +R1 5 N012 500k +C9 N015 4 .1f Rser=1k noiseless +C3 N010 5 100f +S4 4 N012 N009 N014 SNPN +C7 N010 N009 .65f +C19 N012 4 100f +C20 3 N010 10f +D21 N010 5 Y +S6 N012 4 0 N016 SHUT2 +S7 N010 4 0 N016 SHUT2 +C21 N006 4 1p +D1 3 N010 DMB +C17 N010 N012 8p Rser=1 noiseless +C22 3 8 1p +C5 3 1 1p Rser=100 Rpar=50Meg noiseless +C6 3 6 1p Rser=100 Rpar=50Meg noiseless +C8 3 7 1p Rser=100 Rpar=50Meg noiseless +C12 4 2 1p Rser=100 Rpar=20Meg noiseless +C14 4 1 1p Rser=100 Rpar=20Meg noiseless +C15 4 6 1p Rser=100 Rpar=20Meg noiseless +C16 4 7 1p Rser=100 Rpar=20Meg noiseless +D2 3 4 DPOW1 +C23 N008 0 3f Rpar=200K noiseless +B3 N008 0 I=10.1u*dnlim(uplim(V(7),V(3)-1.39,.1), V(4)+2.39, .1)+1n*V(7) +B4 0 N008 I=10.1u*dnlim(uplim(V(6),V(3)-1.4,.1), V(4)+2.4, .1)+1n*V(6) +A3 0 N008 0 0 0 0 N004 0 OTA g=1m iout=110u Vlow=-1 Vhigh=1 +C10 N005 0 3f Rpar=200K noiseless +D4 N005 0 DINLIMA +D6 N008 0 DINLIMB +D7 1 N006 DBIAS +D10 6 N006 DBIAS +D11 7 N006 DBIAS +D12 3 N006 DPOW3 +.model SBIAS SW(level=2 Ron=10 Roff=1G vt=.5 vh=-.2 noiseless) +.model DBIAS D(Ron=620k Roff=1G vfwd=-6.3 epsilon=.2 ilimit=56n noiseless) +.model DSHUT D(Ron=1k Roff=110k Vfwd=1.7 epsilon=.1 ilimit=20u noiseless) +.model SPOW SW(level=2 Ron=10 Roff=1Meg vt=.5 vh=-.2 ilimit=1f noiseless) +.model DPOW1 D(Ron=1k Roff=1G vfwd=1 epsilon=.1 ilimit=.614m noiseless) +.model DPOW2 D(Ron=100 Roff=1G vfwd=1 epsilon=.1 ilimit= 1.2m noiseless) +.model DPOW3 D(Ron=1.2k Roff=1G Vfwd=.5 epsilon=.1 noiseless) +.model NI1 VDMOS(Vto=300m kp=70m lambda=.001) +.model NI2 VDMOS(Vto=400m kp=70m lambda=.001) +.model DLIM D(Ron=1k Roff=70Meg Vfwd=1 Vrev=1 epsilon=50m revepsilon=50m noiseless) +.model DLIMNB D(Ron=100k Roff=100Meg Vfwd=1.2 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMNT D(Ron=100 Roff=100Meg Vfwd=1 Vrev=2 epsilon=.1 revepsilon=.1 noiseless) +.model DINLIMA D(Ron=100 Roff=200k Vfwd=170m Vrev=170m epsilon=10m revepsilon=10m noiseless) +.model DINLIMB D(Ron=100 Roff=200k Vfwd=180m Vrev=180m epsilon=10m revepsilon=10m noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1 Roff=100G vt=-.8 vh=-100m noiseless) +.model SNPN SW(Ron=10 Roff=1Meg vt=170m vh=-200m noiseless) +.model DMB D(Ron=10 Roff=1Meg vfwd=.1 epsilon=.1 ilimit=100u noiseless) +.model Y D(Ron=4k Roff=1g vfwd=.95 epsilon=.1 noiseless) +.ends LT1189 +* +.subckt LT1190 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=3.37p ink=4k +M1 3 N005 5 5 N temp=27 +M2 4 N012 5 5 P temp=27 +C3 3 5 4p +C4 5 4 4p +B1 0 N006 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+1.4, .1) +B2 N006 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+1.39, .1) +C6 3 1 1.1p Rpar=10Meg noiseless +C7 1 4 1.1p noiseless Rpar=10Meg +C8 2 4 1.1p Rpar=10Meg noiseless +C9 3 2 1.1p Rpar=10Meg noiseless +C10 N006 0 11.9f Rpar=100K noiseless +D1 N005 5 YU +D6 5 N012 YD +D7 3 4 DP +C11 2 1 1p Rpar=130k noiseless +A3 0 N009 0 0 0 0 N008 0 OTA g=.40u Iout=1.17u Cout=1.57f en=0 Vhigh=1e308 Vlow=-1e308 +D2 N008 3 XU +D3 4 N008 XD +C2 N011 0 1.19p Rpar=1k noiseless +G3 0 N007 N008 0 1µ +L2 N007 0 3.29m Rser=1Meg noiseless +G1 0 N009 N011 0 1µ +C1 N009 0 1f Rpar=1Meg noiseless +A4 N004 0 N007 N007 N007 N007 N005 N007 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-12 Rout=10Meg Cout=50f +A5 N004 0 N007 N007 N007 N012 N007 N007 SCHMITT Vt=.5 Vh=10m Vhigh=12 Vlow=0 Rout=10Meg Cout=50f +R3 3 6 500k +A6 6 4 0 0 0 0 N004 0 SCHMITT Vt=1 Vh=10m tau=100n +S1 4 3 N004 0 IQ +A2 0 N006 N004 0 0 0 N011 0 OTA g=1m linear en=11n enk=200k Vlow=-1e308 Vhigh=1e308 +.model XU D(Ron=1K Roff=100G Vfwd=-.95 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-23.4m epsilon=.1 noiseless) +.model YU D(Ron=100 Roff=1T Vfwd=.49 epsilon=.01 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.87 epsilon=.1 noiseless) +.model IQ SW(Vt=.5 Vh=-.3 Ron=1.5 Roff=10Meg ilimit= 30.445m level=2) +.model N VDMOS(Vto=-50m Kp=600m) +.model P VDMOS(Vto=50m Kp=200m pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 ilimit=1.3m noiseless) +.ends LT1190 +* +.subckt LT1191 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=3.37p ink=4k +M1 3 N006 5 5 N temp=27 +M2 4 N012 5 5 P temp=27 +C3 3 5 4p +C4 5 4 4p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+1.4, .1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+1.39, .1) +C6 3 1 1p Rpar=10Meg noiseless +C7 1 4 1p noiseless Rpar=10Meg +C8 2 4 1p Rpar=10Meg noiseless +C9 3 2 1p Rpar=10Meg noiseless +C10 N004 0 6.36f Rpar=100K noiseless +D1 N006 5 YU +D6 5 N012 YD +D7 3 4 DP +C11 2 1 1p Rpar=70k noiseless +A3 0 N011 0 0 0 0 N009 0 OTA g=.945u Iout=3.3u Cout=1.86f en=0 Vhigh=1e308 Vlow=-1e308 +D2 N009 3 XU +D3 4 N009 XD +C2 N011 0 637f Rpar=1k noiseless +A4 N005 0 N007 N007 N007 N007 N006 N007 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-12 Rout=10Meg Cout=50f +A5 N005 0 N007 N007 N007 N012 N007 N007 SCHMITT Vt=.5 Vh=10m Vhigh=12 Vlow=0 Rout=10Meg Cout=50f +R3 3 6 500k +A6 6 4 0 0 0 0 N005 0 SCHMITT Vt=1 Vh=10m tau=100n +S1 4 3 N005 0 IQ +A2 0 N004 N005 0 0 0 N011 0 OTA g=1m linear en=23n enk=1.6k Vlow=-1e308 Vhigh=1e308 +G1 0 N008 N009 0 1m +G4 0 N007 N008 0 1m +L3 N008 0 5.09µ Rser=4k Cpar=318.3f Rpar=1.3333333333333333333k noiseless +L4 N007 0 5.09µ Rser=4k Cpar=318.3f Rpar=1.3333333333333333333k noiseless +.model XU D(Ron=1K Roff=100G Vfwd=-.95 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-23.4m epsilon=.1 noiseless) +.model YU D(Ron=100 Roff=1T Vfwd=.49 epsilon=.01 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.87 epsilon=.1 noiseless) +.model IQ SW(Vt=.5 Vh=-.3 Ron=1.5 Roff=10Meg ilimit= 30.345m level=2) +.model N VDMOS(Vto=-50m Kp=600m) +.model P VDMOS(Vto=50m Kp=200m pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 ilimit=1.3m noiseless) +.ends LT1191 +* +.subckt LT1192 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=3.37p ink=4k +M1 3 N006 5 5 N temp=27 +M2 4 N012 5 5 P temp=27 +C3 3 5 4p +C4 5 4 4p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+1.4, .1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+1.39, .1) +C6 3 1 .9p Rpar=10Meg noiseless +C7 1 4 .9p noiseless Rpar=10Meg +C8 2 4 .9p Rpar=10Meg noiseless +C9 3 2 .9p Rpar=10Meg noiseless +C10 N004 0 7.92f Rpar=100K noiseless +D1 N006 5 YU +D6 5 N012 YD +D7 3 4 DP +C11 2 1 .8p Rpar=16k noiseless +A3 0 N011 0 0 0 0 N009 0 OTA g=3.75u Iout=.47u Cout=1.52f en=0 Vhigh=1e308 Vlow=-1e308 +D2 N009 3 XU +D3 4 N009 XD +C2 N011 0 19.48p Rpar=1k noiseless +A4 N005 0 N007 N007 N007 N007 N006 N007 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-12 Rout=10Meg Cout=50f +A5 N005 0 N007 N007 N007 N012 N007 N007 SCHMITT Vt=.5 Vh=10m Vhigh=12 Vlow=0 Rout=10Meg Cout=50f +R3 3 6 500k +A6 6 4 0 0 0 0 N005 0 SCHMITT Vt=1 Vh=10m tau=100n +S1 4 3 N005 0 IQ +A2 0 N004 N005 0 0 0 N011 0 OTA g=1m linear en=6.4n enk=10k Vlow=-1e308 Vhigh=1e308 +G1 0 N008 N009 0 1m +G4 0 N007 N008 0 1m +L3 N008 0 17.8µ Rser=1.08k Cpar=20.9f Rpar=13.5k noiseless +L4 N007 0 4.08µ Rser=2.74k Cpar=234f Rpar=1.5747126436781609193k noiseless +.model XU D(Ron=1K Roff=100G Vfwd=-.95 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-23.4m epsilon=.1 noiseless) +.model YU D(Ron=100 Roff=1T Vfwd=.49 epsilon=.01 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.87 epsilon=.1 noiseless) +.model IQ SW(Vt=.5 Vh=-.3 Ron=1.5 Roff=10Meg ilimit= 30.345m level=2) +.model N VDMOS(Vto=-50m Kp=600m) +.model P VDMOS(Vto=50m Kp=200m pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 ilimit=1.3m noiseless) +.ends LT1192 +* +.subckt LT1193 1 2 3 4 5 6 7 8 +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+1.89, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +M1 5 N014 4 4 NI1 temp=27 +C2 3 5 2p Rpar=100k noiseless +D5 N014 4 DLIMNB +C11 5 4 2p Rpar=100k +A4 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=48.8n enk=505 Vlow=-1.11 Vhigh=1.11 +A5 N005 0 N013 N013 N013 N013 N008 N013 OTA g=1.5u linear cout=12f Vlow=-1e308 Vhigh=1e308 +G1 4 N014 N008 N013 60n +D9 N008 N013 DLIM +C13 3 4 1000p +C1 N005 0 3p Rpar=1k noiseless +G2 0 N013 4 0 .5m +G4 0 N013 3 0 .5m +C18 N013 0 200p Rpar=1K noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=3.4p ink=4k +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.9, .1)+1n*V(1)-13.33n +S1 N006 3 N015 0 SBIAS +C4 3 2 1p Rser=100 Rpar=9Meg noiseless +R4 2 1 100k noiseless +R5 6 7 100k noiseless +A6 8 3 0 0 0 0 N015 0 SCHMITT trise=100n tfall=100n vt=-2.1 vh=10m +D13 3 8 DSHUT +B5 N004 0 I=10u*dnlim(uplim(V(7),V(3)-1.39,.1), V(4)+1.89, .1)+1n*V(7) +B6 0 N004 I=10u*dnlim(uplim(V(6),V(3)-1.4,.1), V(4)+1.9, .1)+1n*V(6) +S8 4 N014 0 N015 SHUT1 +D3 N006 2 DBIAS +D16 N006 1 DBIAS +D17 N006 6 DBIAS +D18 N006 7 DBIAS +D19 N006 4 DPOW2 +A2 6 7 0 0 0 0 0 0 OTA g=0 in=3.4p ink=4k +M2 3 N009 5 5 NI2 temp=27 +D8 N009 N011 DLIMNT +R1 5 N011 500k +C9 N014 4 1f Rser=1k noiseless +C3 N009 5 100f +S4 4 N011 N008 N013 SNPN +C7 N009 N008 3f +C19 N011 4 100f +C20 3 N009 10f +D21 N009 5 Y +S6 N011 4 0 N015 SHUT2 +S7 N009 4 0 N015 SHUT2 +C21 N006 4 1p +D1 3 N009 DMB +C17 N009 N011 8p Rser=1 noiseless +C22 3 8 1p +C5 3 1 1p Rser=100 Rpar=9Meg noiseless +C6 3 6 1p Rser=100 Rpar=9Meg noiseless +C8 3 7 1p Rser=100 Rpar=9Meg noiseless +C12 4 2 1p Rser=100 Rpar=6Meg noiseless +C14 4 1 1p Rser=100 Rpar=6Meg noiseless +C15 4 6 1p Rser=100 Rpar=6Meg noiseless +C16 4 7 1p Rser=100 Rpar=6Meg noiseless +D2 3 4 DPOW1 +.model SBIAS SW(level=2 Ron=10 Roff=1G vt=.5 vh=-.2 noiseless) +.model DBIAS D(Ron=620k Roff=1G vfwd=-6.3 epsilon=.2 ilimit=400n noiseless) +.model DSHUT D(Ron=1k Roff=110k Vfwd=1.7 epsilon=.1 ilimit=20u noiseless) +.model SPOW SW(level=2 Ron=10 Roff=1Meg vt=.5 vh=-.2 ilimit=1f noiseless) +.model DPOW1 D(Ron=1k Roff=1G vfwd=1 epsilon=.1 ilimit=1.15m noiseless) +.model DPOW2 D(Ron=2.1k Roff=1G Vfwd=.5 epsilon=.1 noiseless) +.model NI1 VDMOS(Vto=300m kp=200m lambda=.001) +.model NI2 VDMOS(Vto=400m kp=200m lambda=.001) +.model DLIM D(Ron=1k Roff=70Meg Vfwd=1 Vrev=1 epsilon=50m revepsilon=50m noiseless) +.model DLIMNB D(Ron=100k Roff=100Meg Vfwd=1.2 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMNT D(Ron=100 Roff=100Meg Vfwd=1 Vrev=2 epsilon=.1 revepsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1 Roff=100G vt=-.8 vh=-100m noiseless) +.model SNPN SW(Ron=10 Roff=1Meg vt=200m vh=-180m noiseless) +.model DMB D(Ron=10 Roff=1Meg vfwd=.1 epsilon=.1 ilimit=100u noiseless) +.model Y D(Ron=4k Roff=1g vfwd=.9 epsilon=.1 noiseless) +.ends LT1193 +* +.subckt LT1194 1 2 3 4 5 6 7 8 +C10 N003 0 1f Rpar=100K noiseless +M1 5 N015 4 4 NI1 temp=27 +C2 3 5 2p Rpar=100k noiseless +D5 N015 4 DLIMNB +C11 5 4 2p Rpar=100k +A4 0 N003 0 0 0 0 N002 0 OTA g=1m linear en=14.4n enk=856 Vlow=-1.11 Vhigh=1.11 +A5 N002 0 N007 N007 N007 N007 N005 N007 OTA g=1.5u linear cout=6f Vlow=-1e308 Vhigh=1e308 +G1 4 N015 N005 N007 60n +D9 N005 N007 DLIM +C13 3 4 1000p +C1 N002 0 1p Rpar=1k noiseless +G2 0 N007 4 0 .5m +C18 N007 0 200p Rpar=1K noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=3.4p ink=3.9k +C4 3 2 1p Rser=100 Rpar=9Meg noiseless +R4 2 1 100k noiseless +R5 6 FB 100k noiseless +B5 N003 0 I=10u*dnlim(uplim(V(FB),V(3)-1.39,.1), V(4)+1.89, .1)+1n*V(FB) +B6 0 N003 I=10u*dnlim(uplim(V(6),V(3)-1.4,.1), V(4)+1.9, .1)+1n*V(6) +D3 3 2 DBIAS +D16 3 1 DBIAS +D17 3 6 DBIAS +D18 3 FB DBIAS +D19 3 4 DPOW +A2 6 FB 0 0 0 0 0 0 OTA g=0 in=3.4p ink=3.9k +M2 3 N006 5 5 NI2 temp=27 +D8 N006 N012 DLIMNT +R1 5 N012 500k +C9 N015 4 1f Rser=1k noiseless +C3 N006 5 100f +S4 4 N012 N005 N007 SNPN +C7 N006 N005 1f +C19 N012 4 100f +C20 3 N006 10f +D21 N006 5 Y +D1 3 N006 DMB +C17 N006 N012 8p Rser=1 noiseless +C5 3 1 1p Rser=100 Rpar=9Meg noiseless +C6 3 6 1p Rser=100 Rpar=9Meg noiseless +C8 3 FB 1p Rser=100 Rpar=9Meg noiseless +C12 4 2 1p Rser=100 Rpar=6Meg noiseless +C14 4 1 1p Rser=100 Rpar=6Meg noiseless +C15 4 6 1p Rser=100 Rpar=6Meg noiseless +C16 4 FB 1p Rser=100 Rpar=6Meg noiseless +R2 5 FB 4.5k +R3 FB 6 500 +B3 N013 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+1.89, .1)+1n*V(2) +A3 0 N013 0 0 0 0 N002 0 OTA g=1m linear Vlow=-1.11 Vhigh=1.11 +S1 0 N013 7 4 SWX1 +S2 N013 0 8 4 SWX1 +S6 N007 N008 7 4 SWVC +S3 N013 0 5 N008 SWVLIM +C21 3 N008 10f Rpar=1Meg noiseless +C23 N013 0 1f Rpar=100k noiseless +B1 0 N013 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.9, .1)+1n*V(1)-13.33n +G3 0 N007 3 0 .5m +C22 N011 4 10f Rpar=1Meg noiseless +S5 N011 N007 8 4 SWVC +S7 0 N013 N011 5 SWVLIM +C24 N007 N011 10f +C25 N008 N007 10f +C27 4 7 500f Rpar=500k noiseless +C28 4 8 500f Rpar=500k noiseless +.model DBIAS D(Ron=620k Roff=1G vfwd=-6.3 epsilon=.2 ilimit=400n noiseless) +.model DPOW D(Ron=4k Roff=1G Vfwd=.5 epsilon=.1 noiseless) +.model NI1 VDMOS(Vto=300m kp=200m lambda=.001) +.model NI2 VDMOS(Vto=400m kp=200m lambda=.001) +.model DLIM D(Ron=1k Roff=70Meg Vfwd=1 Vrev=1 epsilon=50m revepsilon=50m noiseless) +.model DLIMNB D(Ron=100k Roff=100Meg Vfwd=1.2 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMNT D(Ron=100 Roff=100Meg Vfwd=1 Vrev=2 epsilon=.1 revepsilon=.1 noiseless) +.model SNPN SW(Ron=10 Roff=1Meg vt=200m vh=-180m noiseless) +.model SWX1 SW(level=2 Ron=50k Roff=10G vt=-.1 vh=-.4 oneway) +.model SWVLIM SW(level=2 Ron=100 Roff=10Meg vt=-50m vh=-50m) +.model SWVC SW(level=2 Ron=1k Roff=300Meg vt=1.7 vh=-1.6) +.model DMB D(Ron=10 Roff=1Meg vfwd=.1 epsilon=.1 ilimit=100u noiseless) +.model Y D(Ron=4k Roff=1g vfwd=.9 epsilon=.1 noiseless) +.ends LT1194 +* +.subckt LT1195 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2p ink=400 +M1 3 N008 5 5 N temp=27 +M2 4 N013 5 5 P temp=27 +C3 3 5 4p +C4 5 4 4p +B1 0 N006 I=10u*dnlim(uplim(V(1),V(3)-.7,.1), V(4)+1.0, .1) +B2 N006 0 I=10u*dnlim(uplim(V(2),V(3)-.69,.1), V(4)+.99, .1) +C6 3 1 1.1p Rpar=40Meg noiseless +C7 1 4 1.1p noiseless Rpar=40Meg +C8 2 4 1.1p Rpar=40Meg noiseless +C9 3 2 1.1p Rpar=40Meg noiseless +C10 N006 0 3f Rpar=100K noiseless +D1 N008 5 Y +D6 5 N013 Y +D7 3 4 DP +C11 2 1 .1p Rpar=230k noiseless +A3 0 N009 0 0 0 0 N010 0 OTA g=.158u Iout=78n Cout=.45f en=0 Vhigh=1e308 Vlow=-1e308 +D2 N010 3 X +D3 4 N010 X +C2 N011 0 7p Rpar=1k noiseless +A4 N007 0 N005 N005 N005 N005 N008 N005 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-12 Rout=10Meg Cout=50f +A5 N007 0 N005 N005 N005 N013 N005 N005 SCHMITT Vt=.5 Vh=10m Vhigh=12 Vlow=0 Rout=10Meg Cout=50f +R3 3 6 2Meg +A6 6 4 0 0 0 0 N007 0 SCHMITT Vt=1 Vh=10m tau=120n +S1 4 3 N007 0 IQ +A2 0 N006 N007 0 0 0 N011 0 OTA g=1m linear en=68n enk=520 Vlow=-1e308 Vhigh=1e308 +G4 0 N004 N010 0 1m +G2 0 N005 N004 0 1m +G3 0 N009 N011 0 1m +L3 N009 0 5.72µ Rser=1.74k Cpar=193f Rpar=2.3513513513513513513k noiseless +L1 N004 0 5.72µ Rser=1.74k Cpar=193f Rpar=2.3513513513513513513k noiseless +L2 N005 0 5.72µ Rser=1.74k Cpar=193f Rpar=2.3513513513513513513k noiseless +.model X D(Ron=1K Roff=100G Vfwd=-.90 epsilon=.1 noiseless) +.model Y D(Ron=100 Roff=1T Vfwd=.435 epsilon=.1 noiseless) +.model IQ SW(Vt=.5 Vh=-.3 Ron=1.5 Roff=10Meg ilimit= 9.82m level=2) +.model N VDMOS(Vto=-50m Kp=300m) +.model P VDMOS(Vto=50m Kp=300m pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 ilimit=.8m noiseless) +.ends LT1195 +* +.subckt LT1206 1 2 3 4 5 6 +R2 N009 N014 10K noiseless +R3 N014 N018 10K noiseless +Q1 N005 N009 2 0 N temp=27 +Q2 N019 N018 2 0 P temp=27 +M1 3 N011 N013 N013 N temp=27 +M2 4 N011 N013 N013 P temp=27 +C4 3 5 2.2p +C5 5 4 2.2p +D1 3 N009 1uA m=81 +R19 3 N005 100 noiseless +R20 N019 4 100 noiseless +G5 0 N008 N005 3 12µ +G6 N008 0 4 N019 12µ +D3 N016 3 X +D4 4 N016 X +C2 3 2 1p +C6 3 1 1p +C7 2 4 1p +C8 1 4 1p +A2 0 0 1 1 1 1 N014 1 OTA G=.1 Rout=10 Vhigh=100 Vlow=-100 en=3.6n Linear enk=30 +A3 0 1 0 0 0 0 0 0 OTA in=2p ink=100 +A4 0 2 0 0 0 0 0 0 OTA in=30p ink=30 +D2 N018 4 1uA m=81 +A5 N010 0 0 0 0 0 N016 0 OTA G=555u Iout=10u Vlow=-1e308 Vhigh=1e308 +C3 0 N008 0.35p Rpar=1K noiseless +D5 N013 N011 Y +C9 N006 N010 .06p Rser=50K Cpar=.02p noiseless +G1 0 N010 N008 0 20m +R1 N010 0 50 noiseless +G2 0 N006 N016 0 20m +R5 N006 0 50 noiseless +G3 0 N011 N015 0 10µ +C1 N011 0 .0035p Rpar=100K noiseless +D6 N006 N015 S +C11 N015 0 3.5p +L1 N013 5 .09µ Rser=5 Rpar=50 Cpar=50p noiseless +C13 3 N013 2.2p +C14 N013 4 2.2p +R7 6 N006 25 noiseless +D7 3 4 Q +C15 3 6 2.2p +C16 6 4 2.2p +.model N NPN(Cje=.25p Cjc=.25p noiseless) +.model P PNP(Cje=.25p Cjc=.25p noiseless) +.model N VDMOS(Vto=-.1 Kp=.5) +.model P VDMOS(Vto=.1 Kp=.5 pchan) +.model 1uA D(Ron=100K epsilon=.5 Ilimit=1u noiseless) +.model X D(Ron=1K Roff=1G epsilon=.5 Vfwd=-.4 noiseless) +.model Y D(Ron=1K Roff=1G epsilon=.5 revepsilon=.5 Vfwd=1 Vrev=1 noiseless) +.model S D(Ron=100 Roff=100 Ilimit=3.25m RevIlimit=3.25m Vrev=0 noiseless) +.model Q D(Ron=100 Ilimit=16.9m epsilon=2 noiseless) +.ends LT1206 +* +.subckt LT1208 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.1p ink=2k +C2 2 1 .1p Rpar=250k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.9,.1), V(4)+1.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.89,.1), V(4)+1.89, .1)+1n*V(2) +C6 3 1 1p Rpar=80Meg noiseless +C7 1 4 1p noiseless Rpar=80Meg +C8 2 4 1p Rpar=80Meg noiseless +C9 3 2 1p Rpar=80Meg noiseless +A2 0 N004 0 0 0 0 N007 0 OTA g=1.43m iout=2.2m Cout=4.9p en=22n enk=1k Vhigh=1e308 Vlow=-1e308 +C10 N004 0 9f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C1 N005 0 .9f Rpar=1Meg noiseless +C3 3 5 5p +C4 5 4 5p +D5 N005 5 Y +D6 5 N005 Y +G1 0 N005 N006 0 1µ +D3 3 4 DC +R2 3 N007 10Meg noiseless +R3 N007 4 10Meg noiseless +G2 0 N006 N007 0 1m +C11 0 N006 .9p Rpar=1k noiseless +D1 4 1 DBIAS +D2 4 2 DBIAS +C13 5 N007 4p Rser=10k noiseless +G3 N007 0 N007 3 500m dir=1 vto=-.66 +G4 0 N007 4 N007 500m dir=1 vto=-.66 +.model Y D(Ron=1k Roff=1T Vfwd=.96 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=60m) +.model P VDMOS(Vto=150m Kp=60m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=6.32m noiseless) +.model DBIAS D(Ron=1k Roff=1T Vrev=1 revilimit=4u noiseless) +.ends LT1208 +* +.subckt LT1210 1 2 3 4 5 6 +R2 N010 N014 10K noiseless +R3 N014 N018 10K noiseless +Q1 N005 N010 2 0 N temp=27 +Q2 N019 N018 2 0 P temp=27 +M1 3 N011 N013 N013 N temp=27 +M2 4 N011 N013 N013 P temp=27 +C4 3 5 2.2p +C5 5 4 2.2p +D1 3 N010 1uA m=81 +R19 3 N005 100 noiseless +R20 N019 4 100 noiseless +G5 0 N006 N005 3 12µ +G6 N006 0 4 N019 12µ +D3 N016 3 X +D4 4 N016 X +C2 3 2 1p +C6 3 1 1p +C7 2 4 1p +C8 1 4 1p +A2 0 0 1 1 1 1 N014 1 OTA G=.1 Rout=10 Vhigh=100 Vlow=-100 en=3n Linear enk=30 +A3 0 1 0 0 0 0 0 0 OTA in=2p ink=600 +A4 0 2 0 0 0 0 0 0 OTA in=40p ink=30 +D2 N018 4 1uA m=81 +A5 N007 0 0 0 0 0 N016 0 OTA G=555u Iout=10u Vlow=-1e308 Vhigh=1e308 +C3 0 N006 .7p Rpar=1K noiseless +D5 N013 N011 Y +C9 N008 N007 .1p Rser=30K Cpar=.01p noiseless +G1 0 N007 N006 0 20m +R1 N007 0 50 noiseless +G2 0 N008 N016 0 20m +R5 N008 0 50 noiseless +G3 0 N011 N015 0 10µ +C1 N011 0 .007p Rpar=100K noiseless +D6 N008 N015 S +C11 N015 0 7p +L1 N013 5 .03µ Rser=.9 Rpar=10 Cpar=250p noiseless +C13 3 N013 2.2p +C14 N013 4 2.2p +R7 6 N008 25 noiseless +D7 3 4 Q +C15 3 6 2.2p +C16 6 4 2.2p +.model N NPN(Cje=.25p Cjc=.25p noiseless) +.model P PNP(Cje=.25p Cjc=.25p noiseless) +.model N VDMOS(Vto=-.15 Kp=2) +.model P VDMOS(Vto=.15 Kp=2 pchan) +.model 1uA D(Ron=100K epsilon=.5 Ilimit=1u noiseless) +.model X D(Ron=1K Roff=.82G epsilon=.5 Vfwd=-1.7 noiseless) +.model Y D(Ron=1K Roff=1G epsilon=.5 revepsilon=.5 Vfwd=1 Vrev=1 noiseless) +.model S D(Ron=100 Roff=100 Ilimit=6m RevIlimit=6m Vrev=0 noiseless) +.model Q D(Ron=100 Ilimit=11.9m epsilon=2 noiseless) +.ends LT1210 +* +.subckt LT1211 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.2p ink=190 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)-.4, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.09,.1), V(4)-.41, .1)+1n*V(2) +C6 3 1 5p Rpar=1G noiseless +C7 1 4 5p noiseless Rpar=1G +C8 2 4 5p Rpar=1G noiseless +C9 3 2 5p Rpar=1G noiseless +A2 0 N004 0 0 0 0 N007 0 OTA g=40u Iout=3.1u en=12n enk=1.5 Vlow=-1e308 Vhigh=1e308 Cout=500f +C10 N004 0 5f Rpar=100K noiseless +D4 N007 3 XU +D5 4 N007 XD +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +G2 0 N006 N007 0 1m +L4 N006 0 120µ Cpar=1.02p Rser=1.24k Rpar=5.166666666666666667k noiseless +C1 N005 0 225f Rpar=1Meg noiseless +G4 0 N005 N006 0 1µ +D2 2 3 DBIAS +D3 1 3 DBIAS +R3 2 1 41.7Meg noiseless +.model XU D(Ron=1K Roff=100G Vfwd=-.6 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=0.1 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=.88 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=90m) +.model DBIAS D(Ron=1k Roff=1T Vrev=1 revilimit=50n noiseless) +.model P VDMOS(Vto=150m Kp=90m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=.39m noiseless) +.ends LT1211 +* +.subckt LT1213 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.2p ink=80 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)-.4, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.09,.1), V(4)-.41, .1)+1n*V(2) +C6 3 1 5p Rpar=400Meg noiseless +C7 1 4 5p noiseless Rpar=400Meg +C8 2 4 5p Rpar=400Meg noiseless +C9 3 2 5p Rpar=400Meg noiseless +A2 0 N004 0 0 0 0 N007 0 OTA g=20u Iout=1.07u en=9.5n enk=1.2 Vlow=-1e308 Vhigh=1e308 Cout=124f +C10 N004 0 14f Rpar=100K noiseless +D4 N007 3 XU +D5 4 N007 XD +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +G2 0 N006 N007 0 1m +L4 N006 0 54.2µ Cpar=68.4f Rser=1.32k Rpar=4.125k noiseless +C1 N005 0 100f Rpar=1Meg noiseless +G4 0 N005 N006 0 1µ +D2 2 3 DBIAS +D3 1 3 DBIAS +R3 2 1 50Meg noiseless +.model XU D(Ron=1K Roff=100G Vfwd=-.6 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=0.1 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=.82 epsilon=.1 noiseless) +.model N VDMOS(Vto=-140m Kp=100m) +.model P VDMOS(Vto=140m Kp=100m pchan) +.model DBIAS D(Ron=1k Roff=1T Vrev=1 revilimit=80n noiseless) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=1.72m noiseless) +.ends LT1213 +* +.subckt LT1215 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.5p ink=2k +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.7,.1), V(4)-.4, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.69,.1), V(4)-.41, .1)+1n*V(2) +C6 3 1 5p Rpar=400Meg noiseless +C7 1 4 5p noiseless Rpar=400Meg +C8 2 4 5p Rpar=400Meg noiseless +C9 3 2 5p Rpar=400Meg noiseless +A2 0 N004 0 0 0 0 N007 0 OTA g=20u Iout=4.2u en=12.5n enk=4 Vlow=-1e308 Vhigh=1e308 Cout=139f +C10 N004 0 5f Rpar=100K noiseless +D4 N007 3 XU +D5 4 N007 XD +D1 N005 5 Y +D6 5 N005 Y +G2 0 N006 N007 0 1m +L4 N006 0 23.6µ Cpar=344f Rser=1.35k Rpar=3.857142857142857143k noiseless +C1 N005 0 58.9f Rpar=1Meg noiseless +G4 0 N005 N006 0 1µ +D2 2 3 DBIAS +D3 1 3 DBIAS +R3 2 1 50Meg noiseless +.model XU D(Ron=1K Roff=100G Vfwd=-.63 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=0.2 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=.58 epsilon=.1 noiseless) +.model N VDMOS(Vto=-295m Kp=120m) +.model P VDMOS(Vto=295m Kp=120m pchan) +.model DBIAS D(Ron=1k Roff=1T Vrev=1 revilimit=420n noiseless) +.ends LT1215 +* +.subckt LT1217 1 2 3 4 5 +R2 N006 N009 10K noiseless +R3 N009 N012 10K noiseless +Q1 N004 N006 2 0 N temp=27 +Q2 N013 N012 2 0 P temp=27 +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C4 3 5 5p +C5 5 4 5p +D1 3 N006 1uA m=71.2 +R19 3 N004 100 noiseless +R20 N013 4 100 noiseless +G5 0 N005 3 N004 5m +G6 N005 0 N013 4 5m +D3 N010 3 X +D4 4 N010 X +G3 0 N007 N010 0 10µ +C1 N007 0 .05p Rser=80K Rpar=100K noiseless +C2 3 2 .15p +C6 3 1 .75p +C7 2 4 .15p +C8 1 4 .75p +A2 0 0 1 1 1 1 N009 1 OTA G=.1 Rout=10 Linear Vhigh=100 Vlow=-100 en=6.5n enk=.1 +A3 0 1 0 0 0 0 0 0 OTA in=.7p ink=.1 +A4 0 2 0 0 0 0 0 0 OTA in=7p ink=.8 +D2 N012 4 1uA m=71.2 +A5 0 N005 0 0 0 0 N010 0 OTA G=3µ Iout=50u Cout=.1p Vlow=-1e308 Vhigh=1e308 +C3 0 N005 .05p Rpar=14.5K noiseless +D5 5 N007 Y +R5 3 4 140K noiseless +.model N NPN(Cje=.56p Cjc=.15p noiseless) +.model P PNP(Cje=.56p Cjc=.15p noiseless) +.model N VDMOS(Vto=-250m Kp=20m) +.model P VDMOS(Vto=250m Kp=20m pchan) +.model 1uA D(Ron=100K epsilon=.5 Ilimit=1u noiseless) +.model X D(Ron=1K Roff=100Meg epsilon=1 Vfwd=-1.8 noiseless) +.model Y D(Ron=5K Roff=1G epsilon=2 revepsilon=2 Vfwd=1.5 Vrev=1.5 noiseless) +.ends LT1217 +* +.subckt LT1218 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=50f ink=2.5k +M1 3 N006 5 5 N temp=27 +M2 4 N013 5 5 P temp=27 +C3 3 5 20p Rpar=1G noiseless +B1 0 N007 I=10u*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+1n*V(1) +B2 N007 0 I=10u*dnlim(uplim(V(2),V(3)+.31,.1), V(4)-.31, .1)+1n*V(2) +C6 3 1 1p +C7 1 4 1p +C8 2 4 1p +C9 3 2 1p +C10 N007 0 500f Rpar=100K noiseless +D1 N006 5 YU +D6 5 N013 YD +D7 3 4 DP +D2 N009 3 XU +D3 4 N009 XD +C2 N010 N016 5.2p noiseless +A4 N005 0 N008 N008 N008 N008 N006 N008 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-18 Rout=1k Cout=5p +A5 N005 0 N008 N008 N008 N013 N008 N008 SCHMITT Vt=.5 Vh=10m Vhigh=18 Vlow=0 Rout=1k Cout=5p +R3 3 6 1.6Meg +S1 4 3 N005 0 IQ +A2 0 N012 N005 0 0 0 N010 0 OTA g=10u iout=540n Vlow=-1e308 Vhigh=1e308 +G2 0 N009 N010 0 20n +C12 N009 0 3f noiseless +A3 0 N007 N005 0 0 0 N012 0 OTA g=1m linear en=33n enk=5 Vlow=-1e308 Vhigh=1e308 +C1 N012 0 50p Rpar=1k noiseless +R6 N016 0 100 noiseless +G3 0 N016 0 N009 5m +D4 0 N010 DLIM +D5 N004 1 DBIASU +D8 2 N014 DBIASD +D10 N004 2 DBIASU +R4 3 N014 416k noiseless +D9 1 N014 DBIASD +G1 0 N016 0 5 5m +C4 5 4 20p Rpar=1G noiseless +S2 N014 4 N005 0 SHBD +S3 3 N004 N005 0 SHBU +A7 6 3 0 0 0 0 N005 0 SCHMITT Vt=-1 Vh=10m tau=5u +R5 N004 4 100Meg noiseless +C11 N004 0 1f +C13 0 N014 1f +G4 0 N008 N009 0 .1µ +C14 N008 0 1f Rpar=10Meg noiseless +.model DBIASD D(Ron=1K Roff=10G Vfwd= 1.2 ilimit=33n noiseless) +.model DBIASU D(Ron=1Meg Roff=10G Vfwd=-0.1 ilimit=12n noiseless) +.model SHBD SW(Vt=.5 Vh=-.3 Ron=416k Roff=1G) +.model SHBU SW(Vt=.5 Vh=-.3 Ron=1k Roff=1T) +.model IQ SW(Vt=.5 Vh=-.3 Ron=1k Roff=100Meg ilimit=350.6u level=2) +.model XU D(Ron=1k Roff=10G Vfwd=1.8 epsilon=.1 noiseless) +.model XD D(Ron=1k Roff=10G Vfwd=1.11 epsilon=.1 noiseless) +.model YU D(Ron=100 Roff=1T Vfwd=1.8 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=1.11 epsilon=.1 noiseless) +.model N VDMOS(Vto=-50m Kp=10m) +.model P VDMOS(Vto=50m Kp=25m pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 ilimit=8u noiseless) +.model DLIM D(Ron=100k Roff=1G Vfwd=250m Vrev=250m epsilon=.1 revepsilon=.1 noiseless) +.ends LT1218 +* +.subckt LT1219 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=50f ink=2.5k +M1 3 N006 5 5 N temp=27 +M2 4 N013 5 5 P temp=27 +C3 3 5 20p noiseless +B1 0 N007 I=10u*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+1n*V(1) +B2 N007 0 I=10u*dnlim(uplim(V(2),V(3)+.31,.1), V(4)-.31, .1)+1n*V(2) +C6 3 1 1p +C7 1 4 1p +C8 2 4 1p +C9 3 2 1p +C10 N007 0 1f Rpar=100K noiseless +D1 N006 5 YU +D6 5 N013 YD +D7 3 4 DP +D2 N009 3 XU +D3 4 N009 XD +C2 N008 N016 6.2p noiseless +A4 N005 0 N010 N010 N010 N010 N006 N010 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-18 Rout=1k Cout=5p +A5 N005 0 N010 N010 N010 N013 N010 N010 SCHMITT Vt=.5 Vh=10m Vhigh=18 Vlow=0 Rout=1k Cout=5p +R3 3 6 1.6Meg +S1 4 3 N005 0 IQ +A2 0 N011 N005 0 0 0 N008 0 OTA g=10u iout=315n Vlow=-1e308 Vhigh=1e308 +G2 0 N009 N008 0 20n +C12 N009 0 1f +A3 0 N007 N005 0 0 0 N011 0 OTA g=1m linear en=33n enk=5 Vlow=-1e308 Vhigh=1e308 +R6 N016 0 100 noiseless +G3 0 N016 0 N009 2m +D4 0 N008 DLIM +D5 N004 1 DBIASU +D8 2 N014 DBIASD +D10 N004 2 DBIASU +R4 3 N014 416k noiseless +D9 1 N014 DBIASD +G1 0 N016 0 5 8m +C4 5 4 20p noiseless +S2 N014 4 N005 0 SHBD +S3 3 N004 N005 0 SHBU +A7 6 3 0 0 0 0 N005 0 SCHMITT Vt=-1 Vh=10m tau=5u +R5 N004 4 100Meg noiseless +C11 N004 0 1f +C13 0 N014 1f +L1 N011 0 2.51m Cpar=75.6p Rser=1.66k Rpar=2.5151515151515151515k +G4 0 N010 N009 0 .1µ +C1 N010 0 1f Rpar=10Meg noiseless +.model DBIASD D(Ron=1K Roff=10G Vfwd= 1.2 ilimit=33n noiseless) +.model DBIASU D(Ron=1Meg Roff=10G Vfwd=-0.1 ilimit=12n noiseless) +.model SHBD SW(Vt=.5 Vh=-.3 Ron=416k Roff=1G) +.model SHBU SW(Vt=.5 Vh=-.3 Ron=1k Roff=1T) +.model IQ SW(Vt=.5 Vh=-.3 Ron=1k Roff=100Meg ilimit=350.6u level=2) +.model XU D(Ron=1k Roff=10G Vfwd=1.8 epsilon=.1 noiseless) +.model XD D(Ron=1k Roff=10G Vfwd=1.11 epsilon=.1 noiseless) +.model YU D(Ron=100 Roff=1T Vfwd=1.8 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=1.11 epsilon=.1 noiseless) +.model N VDMOS(Vto=-50m Kp=10m) +.model P VDMOS(Vto=50m Kp=25m pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 ilimit=8u noiseless) +.model DLIM D(Ron=100k Roff=1G Vfwd=250m Vrev=250m epsilon=.1 revepsilon=.1 noiseless) +.ends LT1219 +* +.subckt LT1220 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2p ink=1k +C2 2 1 300f Rpar=150k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+1.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+1.89, .1)+1n*V(2) +C6 3 1 1p Rpar=90Meg noiseless +C7 1 4 1p noiseless Rpar=90Meg +C8 2 4 1p Rpar=90Meg noiseless +C9 3 2 1p Rpar=90Meg noiseless +A2 0 N004 0 0 0 0 N007 0 OTA g=5.1m iout=4.6m Cout=18p en=17n enk=500 Vhigh=1e308 Vlow=-1e308 +C10 N004 0 .1f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 4p +C4 5 4 4p +D5 N005 5 Y +D6 5 N005 Y +G1 0 N005 N006 0 1µ +D3 3 4 DC +R2 3 N007 20Meg noiseless +R3 N007 4 20Meg noiseless +L1 N005 0 6m Cpar=.295f Rser=2.25Meg Rpar=1.8Meg noiseless +G2 0 N006 N007 0 1m +C1 0 N006 2.2p Rpar=1k noiseless +C11 5 N007 15p Rser=1k noiseless +G3 N007 0 N007 5 500m dir=1 vto=1 +G4 0 N007 5 N007 500m dir=1 vto=1 +G5 N007 3 N007 3 500m dir=1 vto=-1.37 +G6 4 N007 4 N007 500m dir=1 vto=-1.37 +.model Y D(Ron=1k Roff=1T Vfwd=.85 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=7.1m noiseless) +.ends LT1220 +* +.subckt LT1221 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.8p*exp(27/(freq+20)**.6) +C2 2 1 300f Rpar=80k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+1.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+1.89, .1)+1n*V(2) +C6 3 1 1p Rpar=90Meg noiseless +C7 1 4 1p noiseless Rpar=90Meg +C8 2 4 1p Rpar=90Meg noiseless +C9 3 2 1p Rpar=90Meg noiseless +A2 0 N004 0 0 0 0 N007 0 OTA g=5m iout=1.58m Cout=5.5p en=17n enk=500 Vhigh=1e308 Vlow=-1e308 +C10 N004 0 1f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 4p +C4 5 4 4p +D5 N005 5 Y +D6 5 N005 Y +D3 3 4 DC +R2 3 N007 40Meg noiseless +R3 N007 4 40Meg noiseless +G2 0 N006 N007 0 1m +C1 0 N006 1.6p Rpar=1k noiseless +C11 5 N007 9p Rser=2k noiseless +G1 0 N005 N006 0 1m +C12 0 N005 1.6p Rpar=1k noiseless +G3 N007 0 N007 3 500m dir=1 vto=-1.37 +G4 0 N007 4 N007 500m dir=1 vto=-1.37 +G5 N007 0 N007 5 500m dir=1 vto=1 +G6 0 N007 5 N007 500m dir=1 vto=1 +.model Y D(Ron=1k Roff=1T Vfwd=.85 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=7.1m noiseless) +.ends LT1221 +* +.subckt LT1222 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.8p*exp(27/(freq+20)**.6) +C2 2 1 600f Rpar=12k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+1.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+1.89, .1)+1n*V(2) +C6 3 1 1p Rpar=90Meg noiseless +C7 1 4 1p noiseless Rpar=90Meg +C8 2 4 1p Rpar=90Meg noiseless +C9 3 2 1p Rpar=90Meg noiseless +A2 0 N006 0 0 0 0 6 0 OTA g=18.75m iout=1.24m Cout=6p Vhigh=1e308 Vlow=-1e308 +C10 N004 0 .2f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +D5 N005 5 Y +D6 5 N005 Y +D3 3 4 DC +R2 3 6 21.33Meg noiseless +R3 6 4 21.33Meg noiseless +S3 0 6 6 3 swHigh +S2 6 0 4 6 swLow +C11 5 6 10p Rser=1k +S1 0 6 6 5 swLim +S4 6 0 5 6 swLim +A3 0 N004 0 0 0 0 N006 0 OTA g=1u linear en=3n enk=150 Vhigh=1e308 Vlow=-1e308 +G3 0 N005 N007 0 1µ +L1 0 N005 29.6m Cpar=1.36f Rser=10.2Meg Rpar=1.1086956521739130433Meg noiseless +G1 0 N007 6 0 1µ +L2 N007 0 29.6m Cpar=1.36f Rser=10.2Meg Rpar=1.1086956521739130433Meg noiseless +L3 N006 0 29.6m Cpar=1.36f Rser=10.2Meg Rpar=1.1086956521739130433Meg noiseless +.model Y D(Ron=1k Roff=1T Vfwd=.85 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=7.1m noiseless) +.model swHigh SW(Ron=1 Roff=1T vt= -1.3 vh=-.1) +.model swLow SW(Ron=1 Roff=1T vt= -1.3 vh=-.1) +.model swLim SW(level=2 Ron=1 Roff=1T vt=1.5 vh=-.1 ilimit=10m) +.ends LT1222 +* +.subckt LT1223 1 2 3 4 5 +R2 N006 N009 10K noiseless +R3 N009 N012 10K noiseless +Q1 N004 N006 2 0 N temp=27 +Q2 N013 N012 2 0 P temp=27 +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C4 3 5 1p +C5 5 4 1p +D1 3 N006 1uA m=72.5 +R19 3 N004 100 noiseless +R20 N013 4 100 noiseless +G5 0 N005 3 N004 5m +G6 N005 0 N013 4 5m +D3 N010 3 X +D4 4 N010 X +G3 0 N007 N010 0 10µ +C1 N007 0 .01p Rser=50K Rpar=100K noiseless +C2 3 2 .15p +C6 3 1 .75p +C7 2 4 .15p +C8 1 4 .75p +A2 0 0 1 1 1 1 N009 1 OTA G=.1 Rout=10 Linear Vhigh=100 Vlow=-100 en=3.3n enk=100 +A3 0 1 0 0 0 0 0 0 OTA in=2.2p ink=100 +A4 0 2 0 0 0 0 0 0 OTA in=20p ink=100 +D2 N012 4 1uA m=72.5 +A5 0 N005 0 0 0 0 N010 0 OTA G=30µ Iout=200u Cout=.15p Vlow=-1e308 Vhigh=1e308 +C3 0 N005 .01p Rpar=7.4K noiseless +D5 5 N007 Y +R5 3 4 6.3K noiseless +.model N NPN(Cje=.56p Cjc=.15p noiseless) +.model P PNP(Cje=.56p Cjc=.15p noiseless) +.model N VDMOS(Vto=-135m Kp=105m) +.model P VDMOS(Vto=135m Kp=105m pchan) +.model 1uA D(Ron=100K epsilon=.5 Ilimit=1u noiseless) +.model X D(Ron=1K Roff=100Meg epsilon=.1 Vfwd=-2 noiseless) +.model Y D(Ron=1K Roff=1G epsilon=.1 revepsilon=.1 Vfwd=1.1 Vrev=1.1 noiseless) +.ends LT1223 +* +.subckt LT1224 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1p ink=10k +C2 2 1 300f Rpar=250k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+1.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+1.89, .1)+1n*V(2) +C6 3 1 1p Rpar=80Meg noiseless +C7 1 4 1p noiseless Rpar=80Meg +C8 2 4 1p Rpar=80Meg noiseless +C9 3 2 1p Rpar=80Meg noiseless +A2 0 N008 0 0 0 0 N006 0 OTA g=.7m iout=1.17m Cout=2.47p Vhigh=1e308 Vlow=-1e308 +C10 N004 0 1f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +D5 N005 5 Y +D6 5 N005 Y +D3 3 4 DC +R2 3 N006 20Meg noiseless +R3 N006 4 20Meg noiseless +C11 5 N006 15p Rser=1.2k noiseless +A3 0 N004 0 0 0 0 N007 0 OTA g=1m linear Cout=1.5p en=20n enk=2.5k Rout=1k Vhigh=1e308 Vlow=-1e308 +G3 0 N005 N006 0 1µ +L2 N005 0 9.28m Rser=7Meg Rpar=1.166666666666666667Meg noiseless +G4 0 N008 N007 0 1m +C12 0 N008 1.5p Rpar=1k noiseless +D2 1 4 DBIAS +D4 2 4 DBIAS +G1 N006 0 N006 5 500m dir=1 vto=2 +G2 0 N006 5 N006 500m dir=1 vto=2 +G5 N006 0 N006 3 500m dir=1 vto=-1.025 +G6 4 N006 4 N006 500m dir=1 vto=-1.025 +.model Y D(Ron=1k Roff=1T Vfwd=.85 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1 ilimit=6.1m noiseless) +.model DBIAS D(Ron=1k Roff=1G Vfwd=1 ilimit=4u noiseless) +.ends LT1224 +* +.subckt LT1225 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.5p ink=100 +C2 2 1 300f Rpar=70k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+1.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+1.89, .1)+1n*V(2) +C6 3 1 1p Rpar=80Meg noiseless +C7 1 4 1p noiseless Rpar=80Meg +C8 2 4 1p Rpar=80Meg noiseless +C9 3 2 1p Rpar=80Meg noiseless +A2 0 N004 0 0 0 0 N008 0 OTA g=4m iout=1.86m Cout=4.32p en=7n enk=1.8k Vhigh=1e308 Vlow=-1e308 +C10 N004 0 5f Rpar=100K noiseless +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +D5 N007 5 Y +D6 5 N007 Y +D3 3 4 DC +R2 3 N008 10Meg noiseless +R3 N008 4 10Meg noiseless +G2 0 N006 N005 0 1µ +C11 5 N008 6p Rser=2k +G3 0 N005 N008 0 1m +C13 0 N005 2p Rpar=1k noiseless +L2 0 N006 21.2m Cpar=1.32f Rser=4meg Rpar=1.3333333333333333334Meg noiseless +D1 1 4 DBIAS +D2 2 4 DBIAS +G1 0 N007 N006 0 1µ +L1 0 N007 21.2m Cpar=1.32f Rser=4meg Rpar=1.3333333333333333334Meg noiseless +G4 N008 0 N008 5 500m dir=1 vto=5 +G5 0 N008 5 N008 500m dir=1 vto=5 +G6 N008 0 N008 3 500m dir=1 vto=-1.025 +G7 0 N008 4 N008 500m dir=1 vto=-1.025 +.model Y D(Ron=1k Roff=1T Vfwd=.85 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1 ilimit=6.1m noiseless) +.model DBIAS D(Ron=1k Roff=1G Vfwd=1 ilimit=4u noiseless) +.ends LT1225 +* +.subckt LT1226 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.5p ink=200 +C2 2 1 1p Rpar=15k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+1.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+1.89, .1)+1n*V(2) +C6 3 1 1p Rpar=80Meg noiseless +C7 1 4 1p noiseless Rpar=80Meg +C8 2 4 1p Rpar=80Meg noiseless +C9 3 2 1p Rpar=80Meg noiseless +A2 0 N007 0 0 0 0 N008 0 OTA g=15m iout=1.05m Cout=2.38p Vhigh=1e308 Vlow=-1e308 +C10 N004 0 3f Rpar=100K noiseless +M1 3 N006 5 5 N temp=27 +M2 4 N006 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +D5 N006 5 Y +D6 5 N006 Y +D3 3 4 DC +R2 3 N008 20Meg noiseless +R3 N008 4 20Meg noiseless +C11 5 N008 5p Rser=2k noiseless +A3 0 N004 0 0 0 0 N007 0 OTA g=1u linear en=2.6n enk=90 Vhigh=1e308 Vlow=-1e308 +G1 0 N005 N008 0 1µ +L3 N007 0 21.34m Cpar=1.318f Rser=4.69Meg Rpar=1.2710027100271002708Meg noiseless +G2 0 N006 N005 0 1µ +L1 N005 0 21.34m Cpar=1.318f Rser=4.69Meg Rpar=1.2710027100271002708Meg noiseless +L2 N006 0 21.34m Cpar=1.318f Rser=4.69Meg Rpar=1.2710027100271002708Meg noiseless +D1 2 4 DBIAS +D2 1 4 DBIAS +G3 N008 0 N008 5 500m dir=1 vto=2 +G4 0 N008 5 N008 500m dir=1 vto=2 +G5 N008 0 N008 3 500m dir=1 vto=-1.025 +G6 0 N008 4 N008 500m dir=1 vto=-1.025 +.model Y D(Ron=1k Roff=1T Vfwd=.85 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=80m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=6.1m noiseless) +.model DBIAS D(Ron=1k Roff=1G Vfwd=1 ilimit=4u noiseless) +.ends LT1226 +* +.subckt LT1227 1 2 3 4 5 +Q1 N005 N009 2 0 N temp=27 +Q2 N016 N014 2 0 P temp=27 +M1 3 N011 5 5 N temp=27 +M2 4 N011 5 5 P temp=27 +C4 3 5 .7p +C5 5 4 .7p +A2 0 0 1 1 1 1 N010 1 OTA G=.1 Rout=10 Linear Vhigh=100 Vlow=-100 en=3.2n enk=100 +A3 0 1 0 0 0 0 0 0 OTA in=1.7p ink=100 +A4 0 2 0 0 0 0 0 0 OTA in=32p ink=100 +C3 0 N008 3f Rpar=192K noiseless +D5 5 N011 Y +R5 3 4 10.4K noiseless +R3 3 N012 100Meg noiseless +R6 N012 4 100Meg noiseless +G8 N012 0 N012 3 10m dir=1 vto=-.8 +G9 0 N012 4 N012 10m dir=1 vto=-.8 +C7 N016 4 2p Rpar=185 noiseless +Q3 3 N010 N014 0 N temp=27 M=.5 +Q4 4 N010 N009 0 P temp=27 M=.5 +D1 3 N009 DBIAS +D2 N014 4 DBIAS +A6 4 N016 N007 N007 N007 N007 0 N007 OTA G=7u iout=5u Vlow=-1e308 Vhigh=1e308 +G1 0 N011 N012 0 10µ +L1 N011 0 1.59m Cpar=8.84f Rpar=120k Rser=600k +A1 N005 3 N004 0 0 0 N007 0 OTA G=7u iout=5u vlow=-1e308 vhigh=1e308 +A7 3 N005 0 0 0 0 N004 0 OTA G=1m asym ref=1.2 isource=12u isink=-1m Rout=100k Cout=100f Vlow=.4 Vhigh=1 +C1 N015 0 16f +A8 N012 N015 N006 0 0 0 N012 0 OTA G=1 linear vlow=-1e308 vhigh=1e308 +R7 N012 N015 1 noiseless +A9 3 4 0 0 0 0 N006 0 OTA G=23.8n linear ref=29.8 Rout=1Meg Cout=1 Vlow=0 Vhigh=1 +R8 N008 N007 1 noiseless +A10 N007 N008 N006 0 0 0 N007 0 OTA G=1 linear vlow=-1e308 vhigh=1e308 +C2 3 N005 2p Rpar=185 noiseless +C6 N014 4 1p Rser=50 noiseless +C8 3 N009 1p Rser=50 noiseless +D3 3 4 DP +G2 0 N012 N007 0 24.2µ +C12 3 1 1.5p Rser=100 +C9 1 4 1.5p Rser=100 +.model DP D(Ron=100 Roff=1G vfwd=3 ilimit=3.42m noiseless) +.model DBIAS D(Ron=1k Roff=1Meg vfwd=700m epsilon=10m ilimit=450u noiseless) +.model N NPN(Cje=.1p Cjc=.2p tf=180p bf=40 Rb=300 Re=25 Vaf=1k Rc=100 noiseless) +.model P PNP(Cje=.1p Cjc=.2p tf=180p bf=40 Rb=300 Re=25 Vaf=1k Rc=100 noiseless) +.model N VDMOS(Vto=-.2 Kp=.1) +.model P VDMOS(Vto=.2 Kp=.1 pchan) +.model Y D(Ron=1K Roff=1G epsilon=.1 revepsilon=.1 Vfwd=.71 Vrev=.71 noiseless) +.ends LT1227 +* +* LT1228 OTA and CFA +* SUBCIRCUIT CONNECTIONS MATCH DATASHEET PINOUT FOR 8-PIN DIP +*1=IOUT OTA/+IN CFA +*2=-IN OTA +*3=+IN OTA +*4=V- +*5=ISET CFA +*6=OUTPUT CFA +*7=V+ +*8=-IN CFA +.SUBCKT LT1228 1 2 3 4 5 6 7 8 +* THE OTA +Q11 5 5 21 QN 10 +Q12 21 21 22 QN 10 +VC 22 4 DC 0 +F1 26 4 VC 0.375 +F2 27 4 VC 0.25 +F3 28 4 VC 0.375 +F4 7 23 VC 1.6 +F5 7 24 VC 1.6 +VB 7 25 DC 1.4 +CE1 23 7 11PF +CE2 24 7 11PF +RE13 23 32 120 +RE14 24 33 120 +Q13 29 25 32 QPI +Q14 1 25 33 QPI +Q15 23 3 28 QNI 9 +Q16 23 3 27 QNI +Q17 23 3 26 QNI +Q18 24 2 26 QNI 9 +Q19 24 2 27 QNI +Q20 24 2 28 QNI +VM 29 4 DC 1.4 +FM 1 4 VM 1 +DM 29 1 DC +C1 1 7 5PF +Q2A 4 1 10 QP 0.5 +Q3A 11 10 200 QN +Q4A 11 11 7 QP +Q5A 9 11 7 QP +Q6A 12 11 7 QP +Q7A 4 9 12 QP +Q8A 7 12 13 QN 10 +RSCA 13 6 10 +IBA 7 10 DC 300U +Q2B 7 1 110 QN 0.5 +Q3B 111 110 200 QP +Q4B 111 111 4 QN +Q5B 9 111 4 QN +Q6B 112 111 4 QN +Q7B 7 9 112 QN +Q8B 4 112 113 QP 10 +RSCB 6 113 10 +IBB 110 4 DC 300U +RC 8 200 20 +R9 9 0 201600 +D1 9 6 DC +D2 6 9 DC +.MODEL DC D +.MODEL QNI NPN +.MODEL QN NPN(IS=168E-18 BF=150 ISC=40E-18 NC=1 RB=250 RE=8 RC=100 ++CJE=0.37P VJE=0.65 MJE=0.33 FC=0.7 CJC=0.8P VJC=0.62 MJC=0.44 ++TF=300P +.MODEL QPI PNP +.MODEL QP PNP(IS=230E-18 BF=150 ISC=113E-18 NC=1 RB=250 RE=8 RC=100 ++CJE=0.34P VJE=0.75 MJE=0.40 FC=0.7 CJC=0.8P VJC=0.5 MJC=0.36 ++TF=300P +.ENDS LT1228 +* +.subckt LT1229 1 2 3 4 5 +R2 N006 N009 10K noiseless +R3 N009 N012 10K noiseless +Q1 N004 N006 2 0 N temp=27 +Q2 N013 N012 2 0 P temp=27 +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C4 3 5 2p +C5 5 4 2p +D1 3 N006 1uA m=76 +R19 3 N004 100 noiseless +R20 N013 4 100 noiseless +G5 0 N005 3 N004 5m +G6 N005 0 N013 4 5m +D3 N010 3 X +D4 4 N010 X +G3 0 N007 N010 0 1m +C1 N007 0 .3p Rser=0 Rpar=1K noiseless +C2 3 2 .15p +C6 3 1 1.5p +C7 2 4 .15p +C8 1 4 1.5p +A2 0 0 1 1 1 1 N009 1 OTA G=.1 Rout=10 Linear Vhigh=100 Vlow=-100 en=3.2n enk=20 +A3 0 1 0 0 0 0 0 0 OTA in=1.4p ink=40 +A4 0 2 0 0 0 0 0 0 OTA in=32p ink=10 +D2 N012 4 1uA m=76 +A5 0 N005 0 0 0 0 N010 0 OTA G=2.1µ Iout=4.4u Cout=.007p Vlow=-1e308 Vhigh=1e308 +C3 0 N005 .09p Rpar=4.2K noiseless +D5 5 N007 Y +R5 3 4 10K noiseless +.model N NPN(Cje=.3p Cjc=.2p noiseless) +.model P PNP(Cje=.3p Cjc=.2p noiseless) +.model N VDMOS(Vto=-.1 Kp=.5) +.model P VDMOS(Vto=.1 Kp=.5 pchan) +.model 1uA D(Ron=100K epsilon=.5 Ilimit=1u noiseless) +.model X D(Ron=100 Roff=100Meg epsilon=.25 Vfwd=-.75 noiseless) +.model Y D(Ron=100 Roff=10G epsilon=.1 revepsilon=.1 Vfwd=.3 Vrev=.3 noiseless) +.ends LT1229 +* +.subckt LTC1250 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=4f +M1 3 N006 5 5 N temp=27 +M2 4 N006 5 5 P temp=27 +C1 N006 0 100f Rpar=100k noiseless +C3 3 5 .5p +C4 5 4 .5p +B1 0 N007 I=10u*dnlim(uplim(V(1),V(3)-1.6,.1), V(4)-0.3, .1)+1n*V(1) +B2 N007 0 I=10u*dnlim(uplim(V(2),V(3)-1.59,.1), V(4)-0.31, .1)+1n*V(2) +C9 3 2 27.5p Rser=10 noiseless +C10 N007 0 1f Rpar=100K noiseless +D1 N006 5 YU +D6 5 N006 YD +D7 3 4 DP +G3 N004 0 N004 3 1 dir=1 vto=-.55 +G6 0 N004 4 N004 1 dir=1 vto=-.55 +R4 3 N004 1G +R5 N004 4 1G +G2 0 N006 N004 0 10µ +C2 3 1 27.5p Rser=10 noiseless +C6 2 4 27.5p Rser=10 noiseless +C7 1 4 27.5p Rser=10 noiseless +R3 3 4 8k noiseless +C8 N005 0 400f noiseless Rser=110k Rpar=500k +G1 0 N004 N005 0 2.05m +C12 N004 0 25n noiseless +C11 5 N006 800f Rser=10k noiseless +A2 0 N007 0 0 0 0 N005 0 OTA g=633u linear en= 7n+ 33n/ (1 + (freq/400)**1.5) Vlow=-120 Vhigh=120 +.model YU D(Ron=1K Roff=1T Vfwd=.5 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=.5 epsilon=.2 noiseless) +.model N VDMOS(Vto=-100m Kp=50m) +.model P VDMOS(Vto=100m Kp=50m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=1.5m noiseless) +.ends LTC1250 +* +* LT1251 VIDEO FADER +* CONNECTIONS: AS PER DATASHEET PINOUT +*1=FIRST NON-INVERTING INPUT +*2=FIRST INVERTING INPUT +*3=CONTROL VOLTAGE INPUT +*4=CONTROL CURRENT INPUT +*5=CONTROL RESISTOR, RC +*6=NULL INPUT +*7=NEGATIVE SUPPLY +*8=OUTPUT +*9=POSITIVE SUPPLY +*10=FULL SCALE RESISTOR, RFS +*11=FULL SCALE CURRENT INPUT +*12=FULL SCALE VOLTAGE INPUT +*13=SECOND INVERTING INPUT +*14=SECOND NON-INVERTING INPUT +.SUBCKT LT1251 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +*FIRST INPUT STAGE +IB1 1 0 500NA +RI1 1 0 17MEG +C1 1 0 1.5PF +E1 2A 0 VALUE={LIMIT (V(1),V(8N)+0.4,V(8P)-0.4)+V(EN)/30} +VOS1 2A 2B 2.5MV +R1 2B 2 27 +C2 2 0 1PF +*SECOND INPUT STAGE +IB2 14 0 450NA +RI2 14 0 17MEG +C14 14 0 1.5PF +E2 13A 0 VALUE={LIMIT (V(14),V(8N)+0.4,V(8P)-0.4)+V(EN)/30} +VOS2 13A 13B 1.5MV +R2 13B 13 27 +C13 13 0 1PF +*CONTROL AMP +IBC 3 0 -300NA +RIC 3 0 100MEG +C3 3 0 1PF +R3 3 3A 1600 +CBWC 3A 0 10PF +EC 3B 0 3A 0 1.0 +VOSC 3B 4 5MV +C4 4 0 1PF +RC 4 5 5K +C5 5 0 1PF +*FULL SCALE AMP +IBFS 12 0 -300NA +RIFS 12 0 100MEG +C12 12 0 1PF +R12 12 12A 1600 +CBWFS 12A 0 10PF +EFS 12B 0 12A 0 1.0 +VOSFS 12B 11 -5MV +C11 11 0 1PF +RFS 11 10 5K +C10 10 0 1PF +*GENERATING K +EK K 0 TABLE {I(VOSC)/I(VOSFS)} = (-100,0) (0.04,0) (0.1,0.11) (0.9,0.907) (0.95,1.0) (100,1.0) +RDUMMY K 0 1MEG +RNOISE1 EN 0 200K +RNOISE2 EN 0 200K +*GENERATES 40.7NV/RTHZ +*NULL CIRCUIT +GNULL 7 6A VALUE={I(VOSFS)} +RN1 6A 7 200 +VNULL 6A 6B 0.0V +RN2 6B 6 400 +C6 6 7 1PF +*OUTPUT STAGE +E6 8A 0 VALUE={1.8MEG*(I(VOS1)*V(K)+I(VOS2)*(1-V(K))-I(VNULL)+0.10UA+0.0007*V(EN))} +RG 8A 8B 1.8MEG +CG 8B 0 3.4PF +E8 8C 0 8B 0 1.0 +V8 8C 8D 0.0V +R8 8D 8 11 +*OUTPUT SWING AND CURRENT LIMIT +DP 8B 8P D1 +VDP 8P 9 -1.4V +DN 8N 8B D1 +VDN 8N 7 1.4V +.MODEL D1 D +GCL 8B 0 TABLE {I(V8)}=(-1,-1) (-0.04,0) (0.04,0) (1,1) +*SUPPLY CURRENT +GQ 9 7 VALUE={1MA+24*I(VOSFS)+(V(7)-V(9))/20K} +GCC 9 0 TABLE {I(V8)}=(-1,0) (0,0) (1,1) +GEE 7 0 TABLE {I(V8)}=(-1,-1) (0,0) (1,0) +.ENDS LT1251 +* +.SUBCKT LT1252 3 2 7 4 6 +Q2A 4 3 10 QPI 0.5 +Q3A 11 10 200 QNI +Q4A 11 11 7 QPI +Q5A 9 11 7 QPI +Q6A 12 11 7 QPI 2 +Q7A 4 9 12 QPI +Q8A 7 12 13 QNI 10 +RSCA 13 6 12 +IBA 7 10 DC 325U +RBA 7 10 73K +DIA 10 7 DCC 3 +Q2B 7 3 110 QNI 0.5 +Q3B 111 110 200 QPI +Q4B 111 111 4 QNI +Q5B 9 111 4 QNI +Q6B 112 111 4 QNI 2 +Q7B 7 9 112 QNI +Q8B 4 112 113 QPI 10 +RSCB 6 113 12 +IBB 110 4 DC 325U +RBB 110 4 73K +DIB 4 110 DCC 5 +CM1 7 11 10PF +CM2 111 4 10PF +RIB 4 111 35K +RC 2 200 75 +R9 9 0 250K +D1 9 6 DC +D2 6 9 DC +D3 9 7 DCC +D4 4 9 DCC +.MODEL DC D +.MODEL DCC D CJO=3PF VJ=0.62 M=0.44 +.MODEL QNI NPN TF=225P +.MODEL QPI PNP TF=225P +.ENDS LT1252 +* +.SUBCKT LT1253 3 2 7 4 6 +Q2A 4 3 10 QP 0.5 +Q3A 11 10 200 QN +Q4A 11 11 7 QP +RIB 11 7 35K +Q5A 9 11 7 QP +Q6A 12 11 7 QP +Q7A 4 9 12 QP +Q8A 7 12 13 QN 10 +RSCA 13 6 10 +IBA 7 10 DC 300U +Q2B 7 3 110 QN 0.5 +Q3B 111 110 200 QP +Q4B 111 111 4 QN +Q5B 9 111 4 QN +Q6B 112 111 4 QN +Q7B 7 9 112 QN +Q8B 4 112 113 QP 10 +RSCB 6 113 10 +IBB 110 4 DC 300U +RC 2 200 20 +R9 9 0 201600 +D1 9 6 DC +D2 6 9 DC +.MODEL DC D +.MODEL QN NPN(IS=200E-18 BF=150 ISC=40E-18 NC=1 RB=250 RE=8 RC=100 ++CJE=0.37P VJE=0.65 MJE=0.33 FC=0.7 CJC=0.8P VJC=0.62 MJC=0.44 TF=300P +.MODEL QP PNP(IS=170E-18 BF=150 ISC=113E-18 NC=1 RB=250 RE=8 RC=100 ++CJE=0.34P VJE=0.75 MJE=0.40 FC=0.7 CJC=0.8P VJC=0.5 MJC=0.36 TF=300P +.ENDS LT1253 +* +.SUBCKT LT1254 3 2 7 4 6 +Q2A 4 3 10 QP 0.5 +Q3A 11 10 200 QN +Q4A 11 11 7 QP +RIB 11 7 35K +Q5A 9 11 7 QP +Q6A 12 11 7 QP +Q7A 4 9 12 QP +Q8A 7 12 13 QN 10 +RSCA 13 6 10 +IBA 7 10 DC 300U +Q2B 7 3 110 QN 0.5 +Q3B 111 110 200 QP +Q4B 111 111 4 QN +Q5B 9 111 4 QN +Q6B 112 111 4 QN +Q7B 7 9 112 QN +Q8B 4 112 113 QP 10 +RSCB 6 113 10 +IBB 110 4 DC 300U +RC 2 200 20 +R9 9 0 201600 +D1 9 6 DC +D2 6 9 DC +.MODEL DC D +.MODEL QN NPN(IS=200E-18 BF=150 ISC=40E-18 NC=1 RB=250 RE=8 RC=100 ++CJE=0.37P VJE=0.65 MJE=0.33 FC=0.7 CJC=0.8P VJC=0.62 MJC=0.44 TF=300P +.MODEL QP PNP(IS=170E-18 BF=150 ISC=113E-18 NC=1 RB=250 RE=8 RC=100 ++CJE=0.34P VJE=0.75 MJE=0.40 FC=0.7 CJC=0.8P VJC=0.5 MJC=0.36 TF=300P +.ENDS LT1254 +* +* LT1256 VIDEO FADER +* CONNECTIONS: AS PER DATASHEET PINOUT +*1=FIRST NON-INVERTING INPUT +*2=FIRST INVERTING INPUT +*3=CONTROL VOLTAGE INPUT +*4=CONTROL CURRENT INPUT +*5=CONTROL RESISTOR, RC +*6=NULL INPUT +*7=NEGATIVE SUPPLY +*8=OUTPUT +*9=POSITIVE SUPPLY +*10=FULL SCALE RESISTOR, RFS +*11=FULL SCALE CURRENT INPUT +*12=FULL SCALE VOLTAGE INPUT +*13=SECOND INVERTING INPUT +*14=SECOND NON-INVERTING INPUT +.SUBCKT LT1256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +*FIRST INPUT STAGE +IB1 1 0 500NA +RI1 1 0 17MEG +C1 1 0 1.5PF +E1 2A 0 VALUE={LIMIT (V(1),V(8N)+0.4,V(8P)-0.4)+V(EN)/30} +VOS1 2A 2B 2.5MV +R1 2B 2 27 +C2 2 0 1PF +*SECOND INPUT STAGE +IB2 14 0 450NA +RI2 14 0 17MEG +C14 14 0 1.5PF +E2 13A 0 VALUE={LIMIT (V(14),V(8N)+0.4,V(8P)-0.4)+V(EN)/30} +VOS2 13A 13B 1.5MV +R2 13B 13 27 +C13 13 0 1PF +*CONTROL AMP +IBC 3 0 -300NA +RIC 3 0 100MEG +C3 3 0 1PF +R3 3 3A 1600 +CBWC 3A 0 10PF +EC 3B 0 3A 0 1.0 +VOSC 3B 4 5MV +C4 4 0 1PF +RC 4 5 5K +C5 5 0 1PF +* +*FULL SCALE AMP +IBFS 12 0 -300NA +RIFS 12 0 100MEG +C12 12 0 1PF +R12 12 12A 1600 +CBWFS 12A 0 10PF +EFS 12B 0 12A 0 1.0 +VOSFS 12B 11 -5MV +C11 11 0 1PF +RFS 11 10 5K +C10 10 0 1PF +* +*GENERATING K +EK K 0 TABLE {I(VOSC)/I(VOSFS)} = (-100,0) (0,0) (0.2,0.21) (0.9,0.9) (1.0,1.0) (100,1.0) +RDUMMY K 0 1MEG +RNOISE1 EN 0 200K +RNOISE2 EN 0 200K +*GENERATES 40.7NV/RTHZ +* +*NULL CIRCUIT +GNULL 7 6A VALUE={I(VOSFS)} +RN1 6A 7 200 +VNULL 6A 6B 0.0V +RN2 6B 6 400 +C6 6 7 1PF +*OUTPUT STAGE +E6 8A 0 VALUE={1.8MEG*(I(VOS1)*V(K)+I(VOS2)*(1-V(K))-I(VNULL)+0.10UA+0.0007*V(EN))} +RG 8A 8B 1.8MEG +CG 8B 0 3.4PF +E8 8C 0 8B 0 1.0 +V8 8C 8D 0.0V +R8 8D 8 11 +*OUTPUT SWING AND CURRENT LIMIT +DP 8B 8P D1 +VDP 8P 9 -1.4V +DN 8N 8B D1 +VDN 8N 7 1.4V +.MODEL D1 D +GCL 8B 0 TABLE {I(V8)}=(-1,-1) (-0.04,0) (0.04,0) (1,1) +*SUPPLY CURRENT +GQ 9 7 VALUE={1MA+24*I(VOSFS)+(V(7)-V(9))/20K} +GCC 9 0 TABLE {I(V8)}=(-1,0) (0,0) (1,1) +GEE 7 0 TABLE {I(V8)}=(-1,-1) (0,0) (1,0) +.ENDS LT1256 +* +.subckt LT1259 1 2 3 4 5 +R2 N006 N009 10K noiseless +R3 N009 N012 10K noiseless +Q1 N004 N006 2 0 N temp=27 +Q2 N013 N012 2 0 P temp=27 +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C4 3 5 2.2p +C5 5 4 2.2p +D1 3 N006 1uA m=83.2 +R19 3 N004 100 noiseless +R20 N013 4 100 noiseless +G5 0 N005 3 N004 1m +G6 N005 0 N013 4 1m +D3 N010 3 X +D4 4 N010 X +G3 0 N007 N010 0 10µ +C1 N007 0 .008p Rpar=100K noiseless +C2 3 2 .5p +C6 3 1 1p +C7 2 4 .5p +C8 1 4 1p +A2 0 0 1 1 1 1 N009 1 OTA G=.1 Rout=10 Linear Vhigh=100 Vlow=-100 en=3.6n enk=100 +A3 0 1 0 0 0 0 0 0 OTA in=1.3p ink=100 +A4 0 2 0 0 0 0 0 0 OTA in=45p ink=100 +D2 N012 4 1uA m=83.2 +A5 0 N005 0 0 0 0 N010 0 OTA G=30u Iout=25u Cout=.01p Vlow=-1e308 Vhigh=1e308 +C3 0 N005 .3p Rpar=1.92K noiseless +D5 5 N007 Y +D6 3 4 1mA m=1.2 +.model N NPN(Cje=.25p Cjc=.15p noiseless) +.model P PNP(Cje=.25p Cjc=.15p noiseless) +.model N VDMOS(Vto=-.5 Kp=.02) +.model P VDMOS(Vto=.5 Kp=.02 pchan) +.model 1uA D(Ron=100K epsilon=.5 Ilimit=1u noiseless) +.model X D(Ron=1K Roff=100Meg epsilon=.2 Vfwd=-.2 noiseless) +.model Y D(Ron=1K Roff=1G epsilon=.5 revepsilon=.5 Vfwd=1.8 Vrev=1.8 noiseless) +.model 1mA D(Ron=2K Ilimit=1m epsilon=3 noiseless) +.ends LT1259 +* +.SUBCKT LT1328 IN FILTER FSW GND DATA VCC MODE VBIAS +* PIN NUMBER 1 2 3 4 5 6 7 8 +* PREAMP +GPREAMP 0 VPG NVB IN 7.7E-3 +QC1 VPG VPG VC1 NPN +VC1 VC1 GND DC 4 +QC2 VC2 VC2 VPG NPN +VC2 VC2 GND DC 1 +RPREG VPG 0 200K +CPREG VPG 0 10PF +EPREAMP PREOUT1 0 VPG 0 1 +RFB IN PREOUT1 50K +RBPRE PREOUT1 RB 1K +REPRE IN RE 25 +QPRE VCC RB RE [GND] NPN 10X +QDPRE IN IN PREOUT1 [GND] NPN +* +* BIAS +VBIAS NVB 0 DC 1.4V +* +* AC LOOP +GAC 0 FILTER PREOUT1 NVB 16.7E-6 +EAC NAC 0 FILTER 0 1 +RFILTER FILTER 0 10MEG +QC3 FILTER FILTER VC3 NPN +VC3 VC3 GND DC 4 +QC4 VC4 VC4 FILTER NPN +VC4 VC4 GND DC 1 +RIN IN NAC 2K +* +* THRESHOLD +VT VP1 PREOUT1 DC .7V +RVP VP1 VP 10K +QP VCC VP NEP [GND] NPN +QB VCC PRE VBIAS [GND] NPN +RBQB PRE VP 2K +RTH NEP PREOUT 500 +IP PREOUT GND DC 10U +IB VBIAS GND DC 10U +* +* COMPARATOR +GCOMP 0 NCOMP VBIAS PREOUT 2 +QC5 NCOMP NCOMP VC5 [GND] NPN +VC5 VC5 GND DC 4.3V +QC6 VC6 VC6 NCOMP [GND] NPN +VC6 VC6 GND DC .7V +* +QC7 NCT NCT NCOMP [GND] NPN +QC8 NCT NCT NCO [GND] NPN +QC9 NCOMP NCOMP NCB [GND] NPN +QC10 NCO NCO NCB [GND] NPN +ICT VCC NCT DC 400UA +ICB NCB GND DC 2MA +CCOMP NCO 0 10PF +QC11 NCO NCO VC11 [GND] NPN +VC11 VC11 GND DC 3.6 +QC12 VC12 VC12 NCO [GND] NPN +VC12 VC12 GND DC 1.2 +*TCOMP NCO 0 NCOT 0 ZO=100MEG TD=100NS +ECOMP DATA 0 LAPLACE {V(NCO)} = {EXP(-S*200N)} ; 0 1 +* +* FILTER SWITCH +RF MODE NSW 10K +QF1 NSW NSW NSWE NPN +RF2 NSWE NSWB 5K +QF2 FSW NSWB GND NPN 50X +ICC VCC 0 DC 1.6mA +IEE 0 GND DC -8.2mA +.MODEL NPN NPN(BF=200 IS=1E-16 NF=1 NE=1.5 NC=2 NK=.5) +.ENDS LT1328 +* +*HERE IS A PHOTODIODE FOR TESTING THE LT1328, SIMILAR TO SFH-205. +*A=ANODE (COMMON), K=CATHODE (OUTPUT), AND L=LIGHT INPUT. +*DRIVE LIGHT INPUT (L) WITH A CURRENT SOURCE CONNECTED AS FOLLOWS: +*IPD A L; USE PULSE, PWL, ETC. WAVEFORMS. THE 1328PD TAKES CARE OF +*FREQUENCY RESPONSE, SETTLING, AND DIODE CAPACITANCE. +.SUBCKT LT1328PD A K L +DPD 0 K DPD +R1 L A 1 +C1 L A 18N ;SETTLING TAIL FOR 125NS PULSES +GD K A L A 1.0 +ET 2 A L A 0.18 +R3 2 3 1 +C2 3 A 1U +GT K A 3 A 1 +* +.Model DPD D(IS=8.5E-10 XTI=0.5 N=1.35 IKF=390u TIKF=0 ++ RS=150 TRS1=0.022 TRS2=5u CJO=72p VJ=0.4 M=0.5 ++ FC=0.5 TT=10p EG=0.69 ISR=100p NR=2 BV=100 IBV=100u ++ NBV=1 IBVL=0 NBVL=1 KF=0 AF=1 +.ENDS LT1328PD +* +.subckt LT1351 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.5p ink=15 +C2 2 1 1p Rpar=20Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.4, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+1.39, .1)+1n*V(2) +C9 3 2 1.5p Rpar=1.2G noiseless +C10 N004 0 80f Rpar=100K noiseless +M1 3 N006 5 5 N temp=27 +M2 4 N008 5 5 P temp=27 +C3 3 5 1p Rpar=100Meg noiseless +D5 N006 5 YU +D6 5 N008 YD +D3 3 4 DC +R2 3 N007 2G noiseless +R3 N007 4 2G noiseless +C13 N007 5 6p Rser=30k noiseless +R4 3 6 3Meg noiseless +A3 6 4 0 0 0 0 S1 0 SCHMITT Vt=2 Vh=10m tau=1u +A4 S1 0 N007 N007 N007 N007 N006 N007 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-12 Rout=1k Cout=4p +A5 S1 0 N007 N007 N007 N008 N007 N007 SCHMITT Vt=.5 Vh=10m Vhigh=12 Vlow=0 Rout=1k Cout=4p +S9 N007 5 S1 0 shutD +C4 5 4 1p Rpar=100Meg noiseless +D1 XP N005 DS +G4 0 XP N010 0 .5µ +C14 0 XP 18f Rpar=1Meg noiseless +C1 2 4 1.5p Rpar=1.2G noiseless +C6 3 1 1.5p Rpar=1.2G noiseless +C7 1 4 1.5p Rpar=1.2G noiseless +A7 0 XP S1 0 0 0 N007 0 OTA g=168u iout=1.6m Cout=4.48p Vlow=-1e308 Vhigh=1e308 +A6 0 N004 0 0 0 0 N010 0 OTA g=1m linear Cout=18p en=14n enk=10 Rout=1k Vhigh=1e308 Vlow=-1e308 +A2 0 N004 0 0 0 0 N005 0 OTA g=1m linear Cout=5p en=14n enk=10 Rout=1k Vhigh=1e308 Vlow=-1e308 +S1 N011 4 S1 0 swBias +D2 2 N011 DBIAS +D4 1 N011 DBIAS +G1 N007 0 N007 3 500m dir=1 vto=-.88 +G2 0 N007 4 N007 500m dir=1 vto=-.88 +.model YU D(Ron=100 Roff=1T Vfwd=.95 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.97 epsilon=.1 noiseless) +.model N VDMOS(Vto=-80m Kp=75m) +.model P VDMOS(Vto=80m Kp=75m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=10u noiseless) +.model DBIAS D(Ron=1Meg Roff=1G Vfwd=.6 ilimit=10n noiseless) +.model swBias SW(Ron=1Meg Roff=1T vt=.5 vh=-.1) +.model shutD SW(Ron=1T Roff=10k vt=.5 vh=-.1) +.model DS D(Ron=100 Roff=1G Vfwd=.2 Vrev=.2 epsilon=0.1 revepsilon=0.1 noiseless) +.ends LT1351 +* +.subckt LT1352 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.5p ink=15 +C2 2 1 1p Rpar=20Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.4, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+1.39, .1)+1n*V(2) +C9 3 2 1.5p Rpar=1.2G noiseless +C10 N004 0 80f Rpar=100K noiseless +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C3 3 5 1p Rpar=100Meg noiseless +D5 N007 5 YU +D6 5 N007 YD +D3 3 4 DC +R2 3 N007 2G noiseless +R3 N007 4 2G noiseless +C13 N007 5 6p Rser=30k noiseless +C4 5 4 1p Rpar=100Meg noiseless +D1 N006 N005 DS +G4 0 N006 N009 0 .5µ +C14 0 N006 18f Rpar=1Meg noiseless +C1 2 4 1.5p Rpar=1.2G noiseless +C6 3 1 1.5p Rpar=1.2G noiseless +C7 1 4 1.5p Rpar=1.2G noiseless +A6 0 N004 0 0 0 0 N009 0 OTA g=1m linear Cout=18p en=14n enk=10 Rout=1k Vhigh=1e308 Vlow=-1e308 +A2 0 N004 0 0 0 0 N005 0 OTA g=1m linear Cout=5p en=14n enk=10 Rout=1k Vhigh=1e308 Vlow=-1e308 +D2 2 4 DBIAS +D4 1 4 DBIAS +A3 0 N006 0 0 0 0 N007 0 OTA g=168u iout=1.6m Cout=4.48p Vlow=-1e308 Vhigh=1e308 +G1 N007 0 N007 3 500m dir=1 vto=-.88 +G2 0 N007 4 N007 500m dir=1 vto=-.88 +.model YU D(Ron=100 Roff=1T Vfwd=.95 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.97 epsilon=.1 noiseless) +.model N VDMOS(Vto=-80m Kp=75m) +.model P VDMOS(Vto=80m Kp=75m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=10u noiseless) +.model DBIAS D(Ron=2Meg Roff=1G Vfwd=.6 ilimit=10n noiseless) +.model DS D(Ron=100 Roff=1G Vfwd=.2 Vrev=.2 epsilon=0.1 revepsilon=0.1 noiseless) +.ends LT1352 +* +.subckt LT1354 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.3p ink=200 +C2 2 1 1p Rpar=11Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.5, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+1.49, .1)+1n*V(2) +C9 3 2 1.5p Rpar=320Meg noiseless +C10 N004 0 8f Rpar=100K noiseless +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C3 3 5 1p +D5 N007 5 YU +D6 5 N007 YD +C13 N007 5 1.5p Rser=30k noiseless +C4 5 4 1p +D1 N006 N005 DS +G4 0 N006 N009 0 .7µ +C14 0 N006 4f Rpar=1Meg noiseless +C1 2 4 1.5p Rpar=320Meg noiseless +C6 3 1 1.5p Rpar=320Meg noiseless +C7 1 4 1.5p Rpar=320Meg noiseless +A6 0 N004 0 0 0 0 N009 0 OTA g=1m linear Cout=4p en=10n enk=150 Rout=1k Vhigh=1e308 Vlow=-1e308 +A2 0 N004 0 0 0 0 N005 0 OTA g=1m linear Cout=2p en=10n enk=150 Rout=1k Vhigh=1e308 Vlow=-1e308 +D2 2 4 DBIAS +D4 1 4 DBIAS +A3 0 N006 0 0 0 0 N007 0 OTA g=51.5u iout=1.6m Cout=490f Vlow=-1e308 Vhigh=1e308 +R1 3 N007 2G noiseless +R2 N007 4 2G noiseless +G1 N007 0 N007 3 10m dir=1 vto=-.878 +G2 0 N007 4 N007 10m dir=1 vto=-.878 +.model YU D(Ron=100 Roff=1T Vfwd=.75 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.8 epsilon=.1 noiseless) +.model N VDMOS(Vto=-141m Kp=100m) +.model P VDMOS(Vto=141m Kp=100m pchan) +.model DBIAS D(Ron=1Meg Roff=1G Vfwd=.6 ilimit=80n noiseless) +.model DS D(Ron=100 Roff=1G Vfwd=.2 Vrev=.2 epsilon=0.01 revepsilon=0.01 noiseless) +.ends LT1354 +* +.subckt LT1357 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.8p ink=200 +C2 2 1 .1p Rpar=6Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.7, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+1.69, .1)+1n*V(2) +C9 3 2 1.5p Rpar=160Meg noiseless +C10 N004 0 6f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 1p +D5 N005 5 YU +D6 5 N005 YD +R2 3 N006 1G noiseless +R3 N006 4 1G noiseless +C13 N006 5 1.2p Rser=12k noiseless +C4 5 4 1p +G4 0 N008 N007 0 1µ +C14 0 N008 .6f Rpar=1Meg noiseless +C1 2 4 1.5p Rpar=160Meg noiseless +C6 3 1 1.5p Rpar=160Meg noiseless +C7 1 4 1.5p Rpar=160Meg noiseless +A6 0 N004 0 0 0 0 N007 0 OTA g=1m linear Cout=4.0p en=8n enk=100 Rout=1k Vhigh=1e308 Vlow=-1e308 +D2 2 4 DBIAS +D4 1 4 DBIAS +A3 0 N008 0 0 0 0 N006 0 OTA g=133u iout=.642m Cout=845f Vlow=-1e308 Vhigh=1e308 +G1 0 N005 N006 0 1e-6 +L1 N005 0 65.3m Rser=5.33Meg Rpar=1.23094688221709006929Meg noiseless +D1 3 4 DC +G2 N006 0 N006 3 100m dir=1 vto=-.83 +G3 0 N006 4 N006 100m dir=1 vto=-.83 +.model YU D(Ron=100 Roff=1T Vfwd=.76 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.78 epsilon=.1 noiseless) +.model N VDMOS(Vto=-141m Kp=100m) +.model P VDMOS(Vto=141m Kp=100m pchan) +.model DBIAS D(Ron=1Meg Roff=1G Vfwd=.6 ilimit=120n noiseless) +.model DLIM D(Ron=1 Roff=1Meg Vfwd=1.5 Vrev=1.5 epsilon=.1 revepsilon=.1 noiseless) +.model DC D(Ron=10k Roff=100Meg Vfwd=1 ilimit=1.012m noiseless) +.ends LT1357 +* +.subckt LT1360 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.9p ink=90 +C2 2 1 1p Rpar=5Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.6, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+1.59, .1)+1n*V(2) +C9 3 2 1.5p Rpar=100Meg noiseless +C10 N004 0 7f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 1p +D5 N005 5 YU +D6 5 N005 YD +R2 3 N006 42Meg noiseless +R3 N006 4 42Meg noiseless +C13 N006 5 2p Rser=5k noiseless +C4 5 4 1p +C1 2 4 1.5p Rpar=100Meg noiseless +C6 3 1 1.5p Rpar=100Meg noiseless +C7 1 4 1.5p Rpar=100Meg noiseless +A6 0 N004 0 0 0 0 N007 0 OTA g=1u linear Cout=1.3f en=9n enk=110 Vhigh=1e308 Vlow=-1e308 +D2 2 4 DBIAS +D4 1 4 DBIAS +A3 0 N007 0 0 0 0 N006 0 OTA g=534u iout=10m Cout=1.7p Vlow=-1e308 Vhigh=1e308 +D1 N007 0 DSlewLim +G1 0 N005 N006 0 1µ +C8 0 N005 1f Rpar=1Meg noiseless +D3 3 4 DC +C11 N006 5 30p Rser=200k noiseless +G2 N006 0 N006 3 100m dir=1 vto=-.814 +G3 0 N006 4 N006 100m dir=1 vto=-.814 +.model YU D(Ron=100 Roff=1T Vfwd=.805 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.785 epsilon=.1 noiseless) +.model N VDMOS(Vto=-130m Kp=120m) +.model P VDMOS(Vto=130m Kp=120m pchan) +.model DBIAS D(Ron=1Meg Roff=1G Vfwd=.6 ilimit=80n epsilon=500m noiseless) +.model DSlewLim D(Ron=550k Roff=1Meg Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1 noiseless) +.model DC D(Ron=2k Roff=1G Vfwd=1 epsilon=.1 ilimit=2.99m noiseless) +.ends LT1360 +* +.subckt LT1363 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1p ink=200 +C2 2 1 .1p Rpar=5Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+1.6, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+1.59, .1)+1n*V(2) +C9 3 2 1.5p Rpar=100Meg noiseless +C10 N004 0 6f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 1p +D5 N005 5 YU +D6 5 N005 YD +R2 3 N006 80Meg noiseless +R3 N006 4 80Meg noiseless +C13 N006 5 20p Rser=200k noiseless +C4 5 4 1p +C1 2 4 1.5p Rpar=100Meg noiseless +C6 3 1 1.5p Rpar=100Meg noiseless +C7 1 4 1.5p Rpar=100Meg noiseless +A6 0 N004 0 0 0 0 N007 0 OTA g=1u linear Cout=1.5f en=9n enk=250 Vhigh=1e308 Vlow=-1e308 +D2 2 4 DBIAS +D4 1 4 DBIAS +A3 0 N007 0 0 0 0 N006 0 OTA g=225u iout=5m Cout=512f Vlow=-1e308 Vhigh=1e308 +D1 N007 0 DSlewLim +G1 0 N005 N006 0 1µ +C8 0 N005 .6f Rpar=1Meg noiseless +D3 3 4 DC +C11 N006 5 800f Rser=4k noiseless +G2 N006 0 N006 3 100m dir=1 vto=-.811 +G3 0 N006 4 N006 100m dir=1 vto=-.635 +.model YU D(Ron=100 Roff=1T Vfwd=.755 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=1.2 epsilon=.1 noiseless) +.model N VDMOS(Vto=-180m Kp=230m) +.model P VDMOS(Vto=150m Kp=120m pchan) +.model DBIAS D(Ron=100k Roff=1G Vfwd=.6 ilimit=.6u noiseless) +.model DSlewLim D(Ron=410k Roff=1Meg Vfwd=1 Vrev=1 epsilon=.2 revepsilon=.2 noiseless) +.model DC D(Ron=2k Roff=1G Vfwd=1 epsilon=.1 ilimit=4.103m noiseless) +.ends LT1363 +* +.subckt LT1366 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=67f ink=100 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 20p Rpar=1G noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+1n*V(2) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.31,.1), V(4)-.31, .1)+1n*V(2) +C6 3 1 6p +C7 1 4 6p +C8 2 4 6p +C9 3 2 6p +C10 N004 0 500f Rpar=100K noiseless +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +D2 N009 3 XU +D3 4 N009 XD +C2 N007 N012 7p noiseless +G2 0 N009 N007 0 20n +C12 N009 0 3f +C1 N008 0 50p Rpar=1k noiseless +R6 N012 0 100 noiseless +G3 0 N012 0 N009 5m +D4 0 N007 DLIM +D5 3 1 DBIASU +D8 2 N006 DBIASD +D10 3 2 DBIASU +R4 3 N006 416k noiseless +D9 1 N006 DBIASD +G1 0 N012 0 5 5m +C4 5 4 20p Rpar=1G noiseless +G4 0 N005 N009 0 1µ +C14 N005 0 1f Rpar=1Meg noiseless +R5 N006 4 416k noiseless +A4 0 N004 0 0 0 0 N008 0 OTA g=1m linear en=29n enk=.6 Vlow=-1e308 Vhigh=1e308 +A5 0 N008 0 0 0 0 N007 0 OTA g=20u iout=945n Vlow=-1e308 Vhigh=1e308 +.model DBIASD D(Ron=1K Roff=10G Vfwd= 1.1 ilimit=20n noiseless) +.model DBIASU D(Ron=1Meg Roff=10G Vfwd=-0.1 ilimit=10n noiseless) +.model XU D(Ron=1k Roff=10G Vfwd=2.45 epsilon=.1 noiseless) +.model XD D(Ron=1k Roff=10G Vfwd=1.44 epsilon=.1 noiseless) +.model Y D(Ron=100 Roff=1T Vfwd=3.1 epsilon=.1 noiseless) +.model N VDMOS(Vto=-45m Kp=15m) +.model P VDMOS(Vto=45m Kp=15m pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 ilimit=318.8u noiseless) +.model DLIM D(Ron=100k Roff=1G Vfwd=250m Vrev=250m epsilon=.1 revepsilon=.1 noiseless) +.ends LT1366 +* +.subckt LT1368 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=67f ink=100 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 20p Rpar=1G noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+1n*V(2) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.31,.1), V(4)-.31, .1)+1n*V(2) +C6 3 1 6p +C7 1 4 6p +C8 2 4 6p +C9 3 2 6p +C10 N004 0 13p Rpar=100K noiseless +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +D2 N009 3 XU +D3 4 N009 XD +C2 N007 N012 8p noiseless +G2 0 N009 N007 0 20n +C12 N009 0 1f +R6 N012 0 100 noiseless +G3 0 N012 0 N009 7m +D4 0 N007 DLIM +D5 3 1 DBIASU +D8 2 N006 DBIASD +D10 3 2 DBIASU +R4 3 N006 416k noiseless +D9 1 N006 DBIASD +G1 0 N012 0 5 3m +C4 5 4 20p Rpar=1G noiseless +G4 0 N005 N009 0 1µ +C14 N005 0 .2f Rpar=1Meg noiseless +R5 N006 4 416k noiseless +A4 0 N004 0 0 0 0 N008 0 OTA g=1m linear en=29n enk=.6 Vlow=-1e308 Vhigh=1e308 +A5 0 N008 0 0 0 0 N007 0 OTA g=20u iout=533n Vlow=-1e308 Vhigh=1e308 +L1 N008 0 3.5m Rser=1k noiseless +.model DBIASD D(Ron=1K Roff=10G Vfwd= 1.1 ilimit=20n noiseless) +.model DBIASU D(Ron=1Meg Roff=10G Vfwd=-0.1 ilimit=10n noiseless) +.model XU D(Ron=1k Roff=10G Vfwd=2.45 epsilon=.1 noiseless) +.model XD D(Ron=1k Roff=10G Vfwd=1.44 epsilon=.1 noiseless) +.model Y D(Ron=100 Roff=1T Vfwd=3.1 epsilon=.1 noiseless) +.model N VDMOS(Vto=-45m Kp=15m) +.model P VDMOS(Vto=45m Kp=15m pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 ilimit=318.8u noiseless) +.model DLIM D(Ron=100k Roff=1G Vfwd=250m Vrev=250m epsilon=.1 revepsilon=.1 noiseless) +.ends LT1368 +* +.subckt LT1394 1 2 3 4 5 6 7 8 +A1 5 6 0 0 0 0 N016 0 SCHMITT Vt=1.5 Vh=0 tau=.1n +B1 0 N002 I=10u*dnlim(uplim(V(2),V(1)-1.1,.1), V(4)-.5,.1)+1n*V(2) +B2 N002 0 I=10u*dnlim(uplim(V(3),V(1)-1.09,.1), V(4)-.51, .1)+1n*V(3) +C1 N002 0 .01f Rpar=100K noiseless +A2 0 N002 0 0 0 0 N007 0 OTA g=11m iout=75u Vlow=-1e308 Vhigh=1e308 Cout=10f +C2 1 7 2.5p +C3 7 6 2.5p +G1 0 N004 N007 0 70n +D1 0 N007 DLAT +G2 0 N013 0 N007 70n +A3 N010 0 N016 0 0 0 N007 0 OTA g=500u linear Vlow=-1e308 Vhigh=1e308 +D2 0 N010 DLAT +C4 N010 0 1f +G3 0 N010 0 N007 500µ +C5 3 4 1.4p +C6 2 4 1.4p +D3 1 4 DP1 +D4 1 6 DP2 +M1 1 N003 7 7 N temp=27 +M2 6 N008 7 7 P temp=27 +R1 N003 N004 4G +D5 N003 6 DVLU1 +R2 N008 N004 4G +D6 6 N008 DVLD +C7 N004 0 .022f +C8 1 3 1.4p +C9 1 2 1.4p +D7 2 3 DBIASC +D8 1 3 DBIAS +D9 1 2 DBIAS +D10 1 5 DLATCH +D11 N004 1 DSIU temp=27 +D12 6 N004 DSID temp=27 +R3 1 N004 979.5Meg +R4 N004 6 637Meg +D13 N003 7 DLIMN2 +D14 N003 6 DVLU2 +D21 N003 7 DLIMN1 +D22 7 N008 DLIMP +C10 1 8 2.5p +C11 8 6 2.5p +M3 1 N011 8 8 N temp=27 +M4 6 N017 8 8 P temp=27 +R5 N011 N013 4G +D15 N011 6 DVLU1 +R6 N017 N013 4G +D16 6 N017 DVLD +C12 N013 0 .022f +R7 1 N013 979.5Meg +R8 N013 6 637Meg +D19 N011 8 DLIMN2 +D20 N011 6 DVLU2 +D23 N011 8 DLIMN1 +D24 8 N017 DLIMP +D17 N013 1 DSIU temp=27 +D18 6 N013 DSID temp=27 +.model DBIAS D(Ron=1k Roff=10G Vfwd=1 epsilon=.1 ilimit=1u) +.model DBIASC D(Ron=10k Roff=10G Vfwd= 1u Vrev=1u ++ epsilon=10u revepsilon=10u ilimit=1u revilimit=1u) +.model DLATCH D(Ron=1k Roff=10Meg Vfwd=1 epsilon=.1 ilimit=4u) +.model DP1 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=1.2m) +.model DP2 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=4.8m) +.model DVLU1 D(Ron= 5Meg Roff=100G Vfwd=4.0 epsilon=.1) +.model DVLU2 D(Ron=3G Roff=100G Vfwd=1 epsilon=.1) +.model DVLD D(Ron= 5Meg Roff=100G Vfwd=-380m epsilon=.1) +.model DLAT D(Ron=1 Roff=10k Vfwd=600m Vrev=600m epsilon=5m revepsilon=5m) +.model DSIU D(Is=1.0e-30 N=2 TT=8.8e-9) +.model DSID D(Is=1.0e-30 N=2 TT=8e-9) +.model DLIMN1 D(Ron=500Meg Roff=10G Vfwd=.25 epsilon=.1) +.model DLIMN2 D(Ron=1k Roff=10G Vfwd=.5 epsilon=.1) +.model DLIMP D(Ron=1k Roff=10G Vfwd=120m epsilon=.1) +.model N VDMOS(Vto= -20m kp=150m rds=100Meg) +.model P VDMOS(Vto= 200m Kp=500m rds=10Meg pchan ) +.ends LT1394 +* +.subckt LT1395 1 2 3 4 5 +Q32 N006 N006 3 0 P6 M=1 temp=27 +R23 3 N006 11k noiseless +R24 N008 N013 300 noiseless +Q35 N021 N021 4 0 N6 M=1 temp=27 +Q36 N008 N006 3 0 P6 M=5 temp=27 +C4 N008 N006 .8p +R27 N008 5 13.6 noiseless +Q2 N017 N021 4 0 N6 M=5 temp=27 +C5 N017 N021 .8p +Q1 4 N012 N009 0 P2 M=2 temp=27 +Q3 3 N012 N016 0 N2 M=2 temp=27 +R5 N016 N019 120 noiseless +R6 3 N007 300 noiseless +Q4 N007 N009 2 0 N1 M=1 temp=27 +Q5 N020 N019 2 0 P1 M=1 temp=27 +D1 3 N009 DBIAS +D2 N019 4 DBIAS +M1 N006 N010 N008 N008 N temp=27 +M2 N021 N010 N017 N017 P temp=27 +R8 3 N005 75 noiseless +Q6 N011 N004 N005 0 PG1 temp=27 +Q7 N011 N022 N023 0 NG1 temp=27 +I1 N004 3 5.667m +I2 4 N022 5.667m +C9 3 N007 100f +C10 N020 4 100f +C12 3 2 700f Rser=1.5k noiseless +C11 1 4 1p +C13 3 1 1p +R11 N005 N011 100k noiseless +C18 3 N009 100f +C19 N019 4 100f +Q8 N005 N009 N014 0 N1 M=1 temp=27 +Q9 N023 N019 N014 0 P1 M=1 temp=27 +C20 N014 4 1.9p +C21 N011 N007 .9p +C2 N011 N020 .9p +C24 N004 N011 100f +C25 N011 N022 100f +G1 4 N018 N011 4 1m +L1 N018 4 3µ Rser=4.142k Rpar=1.3183k noiseless +C1 3 5 100f Rser=100 noiseless +Q10 4 N013 N011 0 PG1B temp=27 +Q11 3 N013 N011 0 NG1B temp=27 +G5 N011 3 3 1 6µ +G7 N011 4 4 1 5µ +G2 4 N010 N018 4 1m +C15 N010 4 150f Rpar=1k noiseless +D3 4 4 DOFFADJ +A3 0 0 1 1 1 1 N012 1 OTA G=6m Rout=150 Linear Vhigh=1e308 Vlow=-1e308 en=4.5n enk=250 +A4 0 2 0 0 0 0 0 0 OTA in=25p ink=800 +A5 0 1 0 0 0 0 0 0 OTA in=6p ink=1K +R3 N020 4 300 noiseless +A7 3 N007 3 3 3 3 N004 3 OTA g=5.2m iout=8m Rout=150 Cout=10f vlow=-1.45 vhigh=0 +A1 4 N020 4 4 4 4 N022 4 OTA g=5.2m iout=8m Rout=150 Cout=10f vlow=0 vhigh=1.45 +R7 N011 N023 100k noiseless +C3 2 4 700f Rser=1.5k noiseless +R9 N023 4 75 noiseless +R10 N013 N017 300 noiseless +R12 5 N017 13.6 noiseless +C6 5 4 100f Rser=100 noiseless +R13 N021 4 11k noiseless +I3 N012 1 16.87µ +.model N VDMOS(Vto=-.1 Kp=100m Cgs=10f Cgdmax=10f Cgdmin=10f) +.model P VDMOS(Vto=.1 Kp=100m Cgs=10f Cgdmax=10f Cgdmin=10f pchan) +.model DBIAS D(Ron=10 Roff=1G vfwd=80m epsilon=100m ilimit=450u noiseless) +.model DOFFADJ D(Ron=10 Roff=1G vfwd=100m epsilon=100m ilimit=26.97u noiseless) +.model NG1 NPN (IS=1e-17 BF=80 VAF=80 RB=500 TF=5e-11 IKF=4m XTF=3 ITF=2m CJE=200f CJC=200f noiseless) +.model PG1 PNP (IS=1e-17 BF=80 VAF=80 RB=500 TF=2.5e-11 IKF=4m XTF=3 ITF=2m CJE=200f CJC=200f noiseless) +.model NG1B NPN (IS=1e-17 BF=80 VAF=80 RB=100 noiseless ) +.model PG1B PNP (IS=1e-17 BF=80 VAF=80 RB=100 noiseless ) +.MODEL P1 PNP ++ IS =7.0E-18 BF =38 ++ VAF = 1.0E3 NF = 1.0 ++ IKF = 6.0E-3 ++ ISE = 10.0E-15 NE = 1.8 ++ BR = 1.5 NR = 0.90 IKR = 1.0 ++ VAR = 1.0E3 ++ ISC = 3.0E-15 NC = 2.0 ++ RE = 5.0 ++ RB =100 ++ RBM =20 ++ IRB = 500u ++ RCO = 600 ++ GAMMA=3.5e-9 ++ CJE = 26.0E-15 VJE = 0.99 MJE = 0.55 ++ CJC = 60.7E-15 VJC = 0.88 MJC = 0.45 ++ XCJC = .5 ++ FC = 0.95 ++ TF = 6E-12 XTF = 0 VTF = 1.5 ++ ITF = 15.0E-03 ++ TR = 1.0E-09 ++ noiseless + .MODEL P2 AKO:P1 PNP ++ IS =14.0E-18 ++ IKF =12.0E-03 ++ ISE =20.0E-15 ++ ISC =6E-15 ++ RE =2.5 ++ RB =50 ++ RBM =10 ++ IRB =1E-3 ++ RCO = 300 ++ CJE =52.1E-15 ++ CJC =109E-15 ++ ITF =30.0E-03 + .MODEL P6 AKO:P1 PNP ++ IS =42E-18 ++ IKF =36E-03 ++ ISE =60.0E-15 ++ ISC =18E-15 ++ RE =.833 ++ RB =300 ++ RBM =300 ++ RCO = 100 ++ CJE =146E-15 ++ CJC =162E-15 ++ ITF =90E-03 +.MODEL N1 NPN ++ IS =20E-18 BF =135 ++ VAF =1.0E3 NF = 1.0 ++ IKF = 7.0E-3 ++ ISE = 10.0E-18 NE = 1.5 ++ BR = 1.5 NR = 0.95 IKR = 100E-03 ++ VAR = 1.0E3 ++ ISC = 0.0 ++ RE = 5.0 ++ RB =300 ++ RBM =30 ++ IRB = 500u ++ RCO = 750.0 ++ GAMMA=9.5e-9 ++ CJE = 29.7E-15 VJE = 0.99 MJE = 0.50 ++ CJC = 28.3E-15 VJC = 0.74 MJC = 0.50 ++ XCJC = .5 ++ FC = 0.95 ++ TF = 19.2E-12 XTF = 45 VTF = 1.9 ++ ITF = 15.0E-03 ++ TR = 1.0E-09 ++ noiseless +.MODEL N2 AKO:N1 NPN ++ IS =40E-18 ++ IKF =14.0E-03 ++ ISE =20.0E-18 ++ RE =2.5 ++ RB =150 ++ RBM =15 ++ IRB =1e-3 ++ RCO =375 ++ CJE =59.4E-15 ++ CJC =50.9E-15 ++ ITF =30.0E-03 +.MODEL N6 AKO:N1 NPN ++ VAF=1000 ++ IS =120E-18 ++ IKF =42.0E-03 ++ ISE =60.0E-18 ++ RE =.83 ++ RB =300 ++ RBM =300 ++ RCO =125 ++ CJE =149.0E-15 ++ CJC =75.4E-15 ++ ITF =90.0E-03 +.ends LT1395 +* +.subckt LT1398 1 2 3 4 5 6 +Q32 N010 N010 N007 0 P6 M=1 temp=27 +R24 N016 N017 300 noiseless +Q35 N025 N025 N030 0 N6 M=1 temp=27 +Q36 5 N010 N008 0 P6 M=5 temp=27 +R27 N016 5 37.5 noiseless +Q2 5 N025 N031 0 N6 M=5 temp=27 +Q1 4 N014 N013 0 P2 M=2 temp=27 +Q3 3 N014 N020 0 N2 M=2 temp=27 +R5 N020 N023 300 noiseless +R6 3 N006 300 noiseless +Q4 N006 N009 2 0 N1 M=1 temp=27 +Q5 N029 N023 2 0 P1 M=1 temp=27 +M1 N010 N015 N016 N016 N temp=27 +M2 N025 N024 N022 N022 P temp=27 +R8 3 N005 150 noiseless +Q6 N012 N004 N005 0 PG1 temp=27 +Q7 N012 N027 N028 0 NG1 temp=27 +C9 3 N006 100f +C10 N029 4 100f +C12 3 2 300f Rser=600 noiseless +C11 1 4 1p +C13 3 1 1p +C18 3 N009 100f +C19 N023 4 100f +Q8 N005 N009 N018 0 N1 M=1 temp=27 +Q9 N028 N023 N018 0 P1 M=1 temp=27 +C20 N018 4 .8p +C1 3 5 100f Rser=100 noiseless +Q10 4 N017 N012 0 PG1B temp=27 +Q11 3 N017 N012 0 NG1B temp=27 +G2 4 N021 N012 4 1m +C15 N021 4 1e-20 Rpar=1k noiseless +A3 0 0 1 1 1 1 N014 1 OTA G=6m Rout=150 Linear Vhigh=1e308 Vlow=-1e308 en=4.5n enk=250 +A4 0 2 0 0 0 0 0 0 OTA in=25p ink=800 +A5 0 1 0 0 0 0 0 0 OTA in=6p ink=1K +R3 N029 4 300 noiseless +A7 3 N006 3 3 3 3 N004 3 OTA g=6.07m iout=8m Rout=150 Cout=10f vlow=-1.3 vhigh=0 +A1 4 N029 4 4 4 4 N027 4 OTA g=6.07m iout=8m Rout=150 Cout=10f vlow=0 vhigh=1.3 +C3 2 4 300f Rser=600 noiseless +R9 N028 4 150 noiseless +R10 N017 N022 300 noiseless +R12 5 N022 37.5 noiseless +C6 5 4 100f Rser=100 noiseless +R13 N030 4 50 noiseless +R15 N031 4 7.5 noiseless +R16 3 N007 50 noiseless +R17 3 N008 7.5 noiseless +C2 N012 4 1.6p +R18 N009 N013 150 noiseless +D4 3 6 DSHDN +C4 6 4 500f +A2 3 6 0 0 0 0 On 0 SCHMITT vt=3 vh=0 trise=48n tfall=75n +S2 4 N023 On 0 SBIAS +S1 N009 3 On 0 SBIAS +G3 N004 3 On 0 5.667m +G4 4 N027 On 0 5.667m +B1 N012 3 I=4.5u*(.5+.5*tanh((V(ON)-.5)/10m))*V(3,1) +B3 N012 4 I=4u*(.5+.5*tanh((V(ON)-.5)/10m))*V(4,1) +A6 On 0 N021 N021 N021 N021 N015 N021 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-12 Rout=1K Cout=10f +A8 On 0 N021 N021 N021 N024 N021 N021 SCHMITT Vt=.5 Vh=10m Vhigh=12 Vlow=0 Rout=1k Cout=10f +S3 N012 N005 ON 0 SHIZ +S4 N028 N012 ON 0 SHIZ +I1 N014 1 95.119µ +.model NG1 NPN (IS=1e-17 BF=80 VAF=80 RB=500 TF=5e-11 IKF=4m XTF=3 ITF=2m CJE=200f CJC=200f noiseless) +.model PG1 PNP (IS=1e-17 BF=80 VAF=80 RB=500 TF=2.5e-11 IKF=4m XTF=3 ITF=2m CJE=200f CJC=200f noiseless) +.model NG1B NPN (IS=1e-17 BF=80 VAF=80 RB=100 noiseless ) +.model PG1B PNP (IS=1e-17 BF=80 VAF=80 RB=100 noiseless ) +.MODEL P1 PNP ++ IS =7.0E-18 BF =38 ++ VAF = 1.0E3 NF = 1.0 ++ IKF = 6.0E-3 ++ ISE = 10.0E-15 NE = 1.8 ++ BR = 1.5 NR = 0.90 IKR = 1.0 ++ VAR = 1.0E3 ++ ISC = 3.0E-15 NC = 2.0 ++ RE = 5.0 ++ RB =100 ++ RBM =20 ++ IRB = 500u ++ RCO = 600 ++ GAMMA=3.5e-9 ++ CJE = 26.0E-15 VJE = 0.99 MJE = 0.55 ++ CJC = 60.7E-15 VJC = 0.88 MJC = 0.45 ++ XCJC = .5 ++ FC = 0.95 ++ TF = 6E-12 XTF = 0 VTF = 1.5 ++ ITF = 15.0E-03 ++ TR = 1.0E-09 ++ noiseless + .MODEL P2 AKO:P1 PNP ++ IS =14.0E-18 ++ IKF =12.0E-03 ++ ISE =20.0E-15 NE=1.572 ++ ISC =6E-15 ++ RE =2.5 ++ RB =50 ++ RBM =10 ++ IRB =1E-3 ++ RCO = 300 ++ CJE =52.1E-15 ++ CJC =109E-15 ++ ITF =30.0E-03 + .MODEL P6 AKO:P1 PNP ++ IS =42E-18 ++ IKF =36E-03 ++ ISE =60.0E-15 ++ ISC =18E-15 ++ RE =.833 ++ RB =300 ++ RBM =300 ++ RCO = 100 ++ CJE =146E-15 ++ CJC =162E-15 ++ ITF =90E-03 +.MODEL N1 NPN ++ IS =20E-18 BF =135 ++ VAF =1.0E3 NF = 1.0 ++ IKF = 7.0E-3 ++ ISE = 10.0E-18 NE = 1.5 ++ BR = 1.5 NR = 0.95 IKR = 100E-03 ++ VAR = 1.0E3 ++ ISC = 0.0 ++ RE = 5.0 ++ RB =300 ++ RBM =30 ++ IRB = 500u ++ RCO = 750.0 ++ GAMMA=9.5e-9 ++ CJE = 29.7E-15 VJE = 0.99 MJE = 0.50 ++ CJC = 28.3E-15 VJC = 0.74 MJC = 0.50 ++ XCJC = .5 ++ FC = 0.95 ++ TF = 19.2E-12 XTF = 45 VTF = 1.9 ++ ITF = 15.0E-03 ++ TR = 1.0E-09 ++ noiseless +.MODEL N2 AKO:N1 NPN ++ IS =40E-18 ++ IKF =14.0E-03 ++ ISE =20.0E-18 ++ RE =2.5 ++ RB =150 ++ RBM =15 ++ IRB =1e-3 ++ RCO =375 ++ CJE =59.4E-15 ++ CJC =50.9E-15 ++ ITF =30.0E-03 +.MODEL N6 AKO:N1 NPN ++ VAF=1000 ++ IS =120E-18 ++ IKF =42.0E-03 ++ ISE =60.0E-18 ++ RE =.83 ++ RB =300 ++ RBM =300 ++ RCO =125 ++ CJE =149.0E-15 ++ CJC =75.4E-15 ++ ITF =90.0E-03 +.model DSHDN D(Ron=1K Roff=1G vfwd=600m epsilon=600m ilimit=30u noiseless) +.model SBIAS SW(level=2 Ron=1 Roff=1G vt=.5 vh=-.1 ilimit=220u noiseless) +.model SHIZ SW(Ron=100K Roff=100Meg vt=.5 vh=-.2 noiseless) +.model N VDMOS(Vto=-50m Kp=140m Cgs=10f Cgdmax=10f Cgdmin=10f) +.model P VDMOS(Vto=50m Kp=140m Cgs=10f Cgdmax=10f Cgdmin=10f pchan) +.ends LT1398 +* +.subckt LT1413 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=15f ink=60 +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)-0.4, .1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)-1.09,.1), V(4)-0.41, .1)+1n*V(2) +C6 3 1 .1p Rpar=20G noiseless +C7 1 4 .1p noiseless Rpar=20G +C8 2 4 .1p Rpar=20G noiseless +C9 3 2 .1p Rpar=20G noiseless +C10 N003 0 0.1f Rpar=100K noiseless +D1 N005 3 XU +D4 4 N005 XD +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 15f Rpar=1Meg noiseless +C3 3 5 .5p +C4 5 4 .5p +D5 N004 5 YU +D6 5 N004 YD +G1 0 N004 N005 0 1µ +C2 2 1 1f Rpar=435Meg noiseless +A2 0 N006 0 0 0 0 N005 0 OTA g=29.3u iout=1.43u Cout=4.76p Vhigh=1e308 Vlow=-1e308 +G2 0 N006 N007 0 1m +L2 N006 0 .707m Cpar=11.7p Rser=1.39k Rpar=3.564102564102564k noiseless +A3 0 N003 0 0 0 0 N007 0 OTA g=1m linear en=20.2n enk=2 Vhigh=1e308 Vlow=-1e308 +C11 N007 0 759p Rpar=1k noiseless +D2 2 3 DBIAS +D3 1 3 DBIAS +.model XU D(Ron=1K Roff=100G Vfwd=1.0 epsilon=1.0 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-.114 epsilon=1.0 noiseless) +.model YU D(Ron=500 Roff=1T Vfwd=.77 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=.74 epsilon=.1 noiseless) +.model DBIAS D(Ron=1k Roff=1T Vrev=0.6 revilimit=12n noiseless) +.model N VDMOS(Vto=-100m Kp=70m) +.model P VDMOS(Vto=100m Kp=70m pchan) +.ends LT1413 +* +.subckt LTC1440 1 2 3 4 5 6 7 8 +B1 0 N003 I=100u*dnlim(uplim(V(1),V(3)-1.2,.1), V(4)-.2 ,.1)+10n*V(1) +B2 N003 0 I=100u*dnlim(uplim(V(2),V(3)-1.19,.1), V(4)-.21, .1)+10n*V(2) +A1 0 N003 0 0 0 0 N006 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C2 N009 0 1p +M1 5 N009 6 6 NOUT temp=27 +C5 3 5 .5p +C6 5 6 .5p Rpar=100Meg +D5 0 N006 DLAT +C4 7 4 20p +R6 3 N009 590Meg +R7 N009 6 590Meg +G3 N009 0 N009 N002 100µ dir=1 vto=0 +G4 0 N009 6 N009 100µ dir=1 vto=.3 +A3 0 N006 N008 0 0 0 N003 0 OTA g=20u linear cout=10f Vlow=-1e308 Vhigh=1e308 +C10 4 1 .5p +C12 4 2 .5p +C13 4 8 .5p +M3 3 N013 7 7 NREF temp=27 +A4 7 N014 4 4 4 4 N013 4 OTA g=5u iout=500n Vlow=-1e308 Vhigh=1e308 Cout=1p Rout=1g +D2 N014 4 DREF +M5 4 N013 7 7 PREF temp=27 +D4 N013 7 DREFILIM1 +D6 7 N013 DREFILIM2 +D7 N002 6 DNL +A5 N006 0 0 0 0 0 N009 0 OTA g=2u iout=1u Vlow=-1e308 Vhigh=1e308 +C14 5 N009 100f +D8 N003 0 DINNLP +D9 0 N003 DINNLN +D1 0 N008 DLIMHYST +C3 N008 0 100f Rpar=1Meg +C7 0 N003 1f Rpar=2Meg +R9 8 7 10Meg +G2 0 N008 7 8 59m +M2 5 N007 3 3 POUT temp=27 +A2 6 N009 0 0 0 0 N007 0 OTA g=100n linear Vlow=-1e308 Vhigh=1e308 ref=100m +G5 N010 3 N002 6 4n +D3 N007 3 DLIMP +G6 0 N009 N010 N007 100µ dir=1 vto=0 +C1 3 N002 100f Rpar=600Meg +C8 3 N010 100f Rpar=500Meg +C9 3 N007 .01f +C11 3 N014 100f Rpar=10Meg +S1 3 N007 6 3 SOFF +S2 N009 6 6 3 SOFF +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model POUT VDMOS(Vto=-20m kp=200m mtriode=.5 rd=10 pchan) +.model NREF VDMOS(Vto=-39m kp=10m) +.model PREF VDMOS(Vto=39m kp=1m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DREF D(Ron=1 Roff=1T Vfwd=1.182 epsilon=.1) +.model DREFILIM1 D(Roff=1G Ron=1k Vfwd=700m epsilon=100m) +.model DREFILIM2 D(Roff=1G Ron=250k Vfwd=100m epsilon=80m) +.model DINNLP D(Vfwd=900m Ron=300k Roff=5Meg epsilon=30m) +.model DINNLN D(Vfwd=80m epsilon=50m Ron=360k Roff=100Meg) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMHYST D(Ron=.1 Roff=100 Vfwd=0 epsilon=10m Vrev=320m revepsilon=5m) +.model DLIMP D(Vfwd=300m Roff=200Meg Ron=100k epsilon=100m) +.model SOFF SW(Ron=1 Roff=1G Vt=-1.8 Vh=-.2) +.ends LTC1440 +* +.subckt LTC1441 1 2 3 4 5 +B1 0 N003 I=100u*dnlim(uplim(V(3),V(5)-1.2,.1), V(2)-.2 ,.1)+10n*V(3) +B2 N003 0 I=100u*dnlim(uplim(V(4),V(5)-1.19,.1), V(2)-.21, .1)+10n*V(2) +A1 0 N003 0 0 0 0 N006 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C2 N008 0 1p +M1 1 N008 2 2 NOUT temp=27 +C5 5 1 .5p +C6 1 2 .5p Rpar=100Meg +D5 0 N006 DLAT +R6 5 N008 590Meg +R7 N008 2 590Meg +G3 N008 0 N008 N002 100µ dir=1 vto=0 +G4 0 N008 2 N008 100µ dir=1 vto=.3 +C10 N005 3 .5p +C12 N005 4 .5p +D7 N002 2 DNL +A5 N006 0 0 0 0 0 N008 0 OTA g=2u iout=1u Vlow=-1e308 Vhigh=1e308 +C14 1 N008 100f +D8 N003 0 DINNLP +D9 0 N003 DINNLN +C7 0 N003 1f Rpar=2Meg +M2 1 N007 5 5 POUT temp=27 +A2 2 N008 0 0 0 0 N007 0 OTA g=100n linear Vlow=-1e308 Vhigh=1e308 ref=100m +G5 N009 5 N002 2 4n +D3 N007 5 DLIMP +G6 0 N008 N009 N007 100µ dir=1 vto=0 +C1 5 N002 100f Rpar=600Meg +C8 5 N009 100f Rpar=500Meg +C9 5 N007 .01f +S1 5 N007 2 5 SOFF +S2 N008 2 2 5 SOFF +D1 5 2 DP +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model POUT VDMOS(Vto=-20m kp=200m mtriode=.5 rd=10 pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DINNLP D(Vfwd=900m Ron=300k Roff=5Meg epsilon=30m) +.model DINNLN D(Vfwd=80m epsilon=50m Ron=360k Roff=100Meg) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMP D(Vfwd=300m Roff=200Meg Ron=100k epsilon=100m) +.model DP D(Vfwd=1.5 Ron=100 Roff=1G epsilon=.1 ilimit=1.7u) +.model SOFF SW(Ron=1 Roff=1G Vt=-1.8 Vh=-.2) +.ends LTC1441 +* +.subckt LTC1442 1 2 3 4 5 6 7 8 +B1 0 N003 I=100u*dnlim(uplim(V(3),V(7)-1.2,.1), V(2)-.2 ,.1)+10n*V(3) +B2 N003 0 I=100u*dnlim(uplim(V(6),V(7)-1.19,.1), V(2)-.21, .1)+10n*V(6) +A1 0 N003 0 0 0 0 N006 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C2 N009 0 1p +M1 1 N009 2 2 NOUT temp=27 +C5 7 1 .5p +C6 1 2 .5p Rpar=100Meg +D5 0 N006 DLAT +C4 6 2 20p +R6 7 N009 590Meg +R7 N009 2 590Meg +G3 N009 0 N009 N002 100µ dir=1 vto=0 +G4 0 N009 2 N009 100µ dir=1 vto=.3 +A3 0 N006 N008 0 0 0 N003 0 OTA g=20u linear cout=10f Vlow=-1e308 Vhigh=1e308 +C10 2 3 .5p +C12 2 4 .5p +C13 2 5 .5p +M3 7 N014 6 6 NREF temp=27 +A4 6 N015 2 2 2 2 N014 2 OTA g=5u iout=500n Vlow=-1e308 Vhigh=1e308 Cout=1p Rout=1g +D2 N015 2 DREF +M5 2 N014 6 6 PREF temp=27 +D4 N014 6 DREFILIM1 +D6 6 N014 DREFILIM2 +D7 N002 2 DNL +A5 N006 0 0 0 0 0 N009 0 OTA g=2u iout=1u Vlow=-1e308 Vhigh=1e308 +C14 1 N009 100f +D8 N003 0 DINNLP +D9 0 N003 DINNLN +D1 0 N008 DLIMHYST +C3 N008 0 100f Rpar=1Meg +C7 0 N003 1f Rpar=2Meg +R9 5 6 10Meg +G2 0 N008 6 5 59m +M2 1 N007 7 7 POUT temp=27 +A2 2 N009 0 0 0 0 N007 0 OTA g=100n linear Vlow=-1e308 Vhigh=1e308 ref=100m +G5 N011 7 N002 2 4n +D3 N007 7 DLIMP +G6 0 N009 N011 N007 100µ dir=1 vto=0 +C1 7 N002 100f Rpar=600Meg +C8 7 N011 100f Rpar=500Meg +C9 7 N007 .01f +C11 7 N015 100f Rpar=10Meg +S1 7 N007 2 7 SOFF +S2 N009 2 2 7 SOFF +B3 0 N017 I=100u*dnlim(uplim(V(6),V(7)-1.2,.1), V(2)-.2 ,.1)+10n*V(6) +B4 N017 0 I=100u*dnlim(uplim(V(4),V(7)-1.19,.1), V(2)-.21, .1)+10n*V(4) +A6 0 N017 0 0 0 0 N019 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C15 N021 0 1p +M4 8 N021 2 2 NOUT temp=27 +C16 7 8 .5p +C17 8 2 .5p Rpar=100Meg +D10 0 N019 DLAT +R1 7 N021 590Meg +R2 N021 2 590Meg +G1 N021 0 N021 N016 100µ dir=1 vto=0 +G7 0 N021 2 N021 100µ dir=1 vto=.3 +A7 0 N019 N008 0 0 0 N017 0 OTA g=20u linear cout=10f Vlow=-1e308 Vhigh=1e308 +D11 N016 2 DNL +A8 N019 0 0 0 0 0 N021 0 OTA g=2u iout=1u Vlow=-1e308 Vhigh=1e308 +C18 8 N021 100f +D12 N017 0 DINNLP +D13 0 N017 DINNLN +C19 0 N017 1f Rpar=2Meg +M6 8 N020 7 7 POUT temp=27 +A9 2 N021 0 0 0 0 N020 0 OTA g=100n linear Vlow=-1e308 Vhigh=1e308 ref=100m +G8 N022 7 N016 2 4n +D14 N020 7 DLIMP +G9 0 N021 N022 N020 100µ dir=1 vto=0 +C20 7 N016 100f Rpar=600Meg +C21 7 N022 100f Rpar=500Meg +C22 7 N020 .01f +S3 7 N020 2 7 SOFF +S4 N021 2 2 7 SOFF +D15 7 2 DP +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model POUT VDMOS(Vto=-20m kp=200m mtriode=.5 rd=10 pchan) +.model NREF VDMOS(Vto=-39m kp=10m) +.model PREF VDMOS(Vto=39m kp=1m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DP D(Ron=100 Roff=1G Vfwd=1.5 epsilon=.1 ilimit=1.5u) +.model DREF D(Ron=1 Roff=1T Vfwd=1.182 epsilon=.1) +.model DREFILIM1 D(Roff=1G Ron=1k Vfwd=700m epsilon=100m) +.model DREFILIM2 D(Roff=1G Ron=250k Vfwd=100m epsilon=80m) +.model DINNLP D(Vfwd=900m Ron=300k Roff=5Meg epsilon=30m) +.model DINNLN D(Vfwd=80m epsilon=50m Ron=360k Roff=100Meg) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMHYST D(Ron=.1 Roff=100 Vfwd=0 epsilon=10m Vrev=320m revepsilon=5m) +.model DLIMP D(Vfwd=300m Roff=200Meg Ron=100k epsilon=100m) +.model SOFF SW(Ron=1 Roff=1G Vt=-1.8 Vh=-.2) +.ends LTC1442 +* +.subckt LTC1443 1 2 3 4 5 6 7 +B1 0 N003 I=100u*dnlim(uplim(V(4),V(2)-1.2,.1), V(6)-.2 ,.1)+10n*V(1) +B2 N003 0 I=100u*dnlim(uplim(V(3),V(2)-1.19,.1), V(6)-.21, .1)+10n*V(2) +A1 0 N003 0 0 0 0 N005 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C2 N007 0 1p +M1 1 N007 7 7 NOUT temp=27 +C5 2 1 .5p +C6 1 7 .5p Rpar=100Meg +D5 0 N005 DLAT +C4 5 6 20p +R6 2 N007 590Meg +R7 N007 7 590Meg +G3 N007 0 N007 N002 100µ dir=1 vto=0 +G4 0 N007 7 N007 100µ dir=1 vto=.3 +C10 6 4 .5p +C12 6 3 .5p +M3 2 N011 5 5 NREF temp=27 +A4 5 N012 6 6 6 6 N011 6 OTA g=5u iout=500n Vlow=-1e308 Vhigh=1e308 Cout=1p Rout=1g +D2 N012 6 DREF +M5 6 N011 5 5 PREF temp=27 +D4 N011 5 DREFILIM1 +D6 5 N011 DREFILIM2 +D7 N002 7 DNL +A5 N005 0 0 0 0 0 N007 0 OTA g=2u iout=1u Vlow=-1e308 Vhigh=1e308 +C14 1 N007 100f +D8 N003 0 DINNLP +D9 0 N003 DINNLN +C7 0 N003 1f Rpar=2Meg +M2 1 N006 2 2 POUT temp=27 +A2 7 N007 0 0 0 0 N006 0 OTA g=100n linear Vlow=-1e308 Vhigh=1e308 ref=100m +G5 N009 2 N002 7 4n +D3 N006 2 DLIMP +G6 0 N007 N009 N006 100µ dir=1 vto=0 +C1 2 N002 100f Rpar=600Meg +C8 2 N009 100f Rpar=500Meg +C9 2 N006 .01f +C11 2 N012 100f Rpar=10Meg +S1 2 N006 7 2 SOFF +S2 N007 7 7 2 SOFF +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model POUT VDMOS(Vto=-20m kp=200m mtriode=.5 rd=10 pchan) +.model NREF VDMOS(Vto=-33m kp=5m) +.model PREF VDMOS(Vto=33m kp=1m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DREF D(Ron=1 Roff=1T Vfwd=1.182 epsilon=.1) +.model DREFILIM1 D(Roff=1G Ron=1k Vfwd=245m epsilon=100m) +.model DREFILIM2 D(Roff=1G Ron=250k Vfwd=141m epsilon=85m) +.model DINNLP D(Vfwd=900m Ron=300k Roff=5Meg epsilon=30m) +.model DINNLN D(Vfwd=80m epsilon=50m Ron=360k Roff=100Meg) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMHYST D(Ron=.1 Roff=100 Vfwd=0 epsilon=10m Vrev=320m revepsilon=5m) +.model DLIMP D(Vfwd=300m Roff=200Meg Ron=100k epsilon=100m) +.model SOFF SW(Ron=1 Roff=1G Vt=-1.8 Vh=-.2) +.ends LTC1443 +* +.subckt LTC1444 1 2 3 4 5 6 7 +B1 0 N003 I=100u*dnlim(uplim(V(4),V(2)-1.2,.1), V(6)-.2 ,.1)+10n*V(4) +B2 N003 0 I=100u*dnlim(uplim(V(3),V(2)-1.19,.1), V(6)-.21, .1)+10n*V(3) +A1 0 N003 0 0 0 0 N006 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C2 N009 0 1p +M1 1 N009 6 6 NOUT temp=27 +C5 2 1 .5p +C6 1 6 .5p Rpar=100Meg +D5 0 N006 DLAT +C4 5 6 20p +R6 2 N009 590Meg +R7 N009 6 590Meg +G3 N009 0 N009 N002 100µ dir=1 vto=0 +G4 0 N009 6 N009 100µ dir=1 vto=.3 +A3 0 N006 N008 0 0 0 N003 0 OTA g=18u linear cout=10f Vlow=-1e308 Vhigh=1e308 +C10 6 3 .5p +C12 6 4 .5p +C13 6 7 .5p +M3 2 N013 5 5 NREF temp=27 +A4 5 N014 6 6 6 6 N013 6 OTA g=5u iout=500n Vlow=-1e308 Vhigh=1e308 Cout=1p Rout=1g +D2 N014 6 DREF +M5 6 N013 5 5 PREF temp=27 +D4 N013 5 DREFILIM1 +D6 5 N013 DREFILIM2 +D7 N002 6 DNL +A5 N006 0 0 0 0 0 N009 0 OTA g=2u iout=1u Vlow=-1e308 Vhigh=1e308 +C14 1 N009 100f +D8 N003 0 DINNLP +D9 0 N003 DINNLN +D1 0 N008 DLIMHYST +C3 N008 0 100f Rpar=1Meg +C7 0 N003 1f Rpar=2Meg +R9 7 5 10Meg +G2 0 N008 5 7 59m +A2 6 N009 0 0 0 0 N007 0 OTA g=100n linear Vlow=-1e308 Vhigh=1e308 ref=100m +G5 N010 2 N002 6 4n +D3 N007 2 DLIMP +G6 0 N009 N010 N007 100µ dir=1 vto=0 +C1 2 N002 100f Rpar=600Meg +C8 2 N010 100f Rpar=500Meg +C9 2 N007 .01f +C11 2 N014 100f Rpar=10Meg +S1 2 N007 6 2 SOFF +S2 N009 6 6 2 SOFF +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model POUT VDMOS(Vto=-20m kp=200m mtriode=.5 rd=10 pchan) +.model NREF VDMOS(Vto=-33m kp=5m) +.model PREF VDMOS(Vto=33m kp=1m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DINNLP D(Vfwd=900m Ron=300k Roff=5Meg epsilon=30m) +.model DINNLN D(Vfwd=80m epsilon=50m Ron=360k Roff=100Meg) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMHYST D(Ron=.1 Roff=100 Vfwd=0 epsilon=10m Vrev=320m revepsilon=5m) +.model DLIMP D(Vfwd=300m Roff=200Meg Ron=100k epsilon=100m) +.model SOFF SW(Ron=1 Roff=1G Vt=-1.8 Vh=-.2) +.model DREF D(Ron=1 Roff=1T Vfwd=1.221 epsilon=.1) +.model DREFILIM1 D(Roff=1G Ron=1k Vfwd=245m epsilon=100m) +.model DREFILIM2 D(Roff=1G Ron=250k Vfwd=141m epsilon=85m) +.ends LTC1444 +* +.subckt LTC1445 1 2 3 4 5 6 7 +B1 0 N003 I=100u*dnlim(uplim(V(4),V(2)-1.2,.1), V(6)-.2 ,.1)+10n*V(4) +B2 N003 0 I=100u*dnlim(uplim(V(3),V(2)-1.19,.1), V(6)-.21, .1)+10n*V(3) +A1 0 N003 0 0 0 0 N006 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C2 N009 0 1p +M1 1 N009 6 6 NOUT temp=27 +C5 2 1 .5p +C6 1 6 .5p Rpar=100Meg +D5 0 N006 DLAT +C4 5 6 20p +R6 2 N009 590Meg +R7 N009 6 590Meg +G3 N009 0 N009 N002 100µ dir=1 vto=0 +G4 0 N009 6 N009 100µ dir=1 vto=.3 +A3 0 N006 N008 0 0 0 N003 0 OTA g=18u linear cout=10f Vlow=-1e308 Vhigh=1e308 +C10 6 3 .5p +C12 6 4 .5p +C13 6 7 .5p +M3 2 N013 5 5 NREF temp=27 +A4 5 N014 6 6 6 6 N013 6 OTA g=5u iout=500n Vlow=-1e308 Vhigh=1e308 Cout=1p Rout=1g +D2 N014 6 DREF +M5 6 N013 5 5 PREF temp=27 +D4 N013 5 DREFILIM1 +D6 5 N013 DREFILIM2 +D7 N002 6 DNL +A5 N006 0 0 0 0 0 N009 0 OTA g=2u iout=1u Vlow=-1e308 Vhigh=1e308 +C14 1 N009 100f +D8 N003 0 DINNLP +D9 0 N003 DINNLN +D1 0 N008 DLIMHYST +C3 N008 0 100f Rpar=1Meg +C7 0 N003 1f Rpar=2Meg +R9 7 5 10Meg +G2 0 N008 5 7 59m +M2 1 N007 2 2 POUT temp=27 +A2 6 N009 0 0 0 0 N007 0 OTA g=100n linear Vlow=-1e308 Vhigh=1e308 ref=100m +G5 N010 2 N002 6 4n +D3 N007 2 DLIMP +G6 0 N009 N010 N007 100µ dir=1 vto=0 +C1 2 N002 100f Rpar=600Meg +C8 2 N010 100f Rpar=500Meg +C9 2 N007 .01f +C11 2 N014 100f Rpar=10Meg +S1 2 N007 6 2 SOFF +S2 N009 6 6 2 SOFF +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model POUT VDMOS(Vto=-20m kp=200m mtriode=.5 rd=10 pchan) +.model NREF VDMOS(Vto=-33m kp=5m) +.model PREF VDMOS(Vto=33m kp=1m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DINNLP D(Vfwd=900m Ron=300k Roff=5Meg epsilon=30m) +.model DINNLN D(Vfwd=80m epsilon=50m Ron=360k Roff=100Meg) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMHYST D(Ron=.1 Roff=100 Vfwd=0 epsilon=10m Vrev=320m revepsilon=5m) +.model DLIMP D(Vfwd=300m Roff=200Meg Ron=100k epsilon=100m) +.model SOFF SW(Ron=1 Roff=1G Vt=-1.8 Vh=-.2) +.model DREF D(Ron=1 Roff=1T Vfwd=1.221 epsilon=.1) +.model DREFILIM1 D(Roff=1G Ron=1k Vfwd=245m epsilon=100m) +.model DREFILIM2 D(Roff=1G Ron=250k Vfwd=141m epsilon=85m) +.ends LTC1445 +* +.subckt LT1462 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.5f +C2 2 1 1p Rpar=1T noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.5,.1), V(4)+1.3, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.51,.1), V(4)+1.29, .1)+1n*V(2) +C9 3 2 1.5p Rpar=1T noiseless +C10 N004 0 7f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .1p +D5 N005 5 Y +D6 5 N005 Y +R2 3 N006 100G noiseless +R3 N006 4 100G noiseless +C4 5 4 .1p +C1 2 4 1.5p Rpar=1T noiseless +C6 3 1 1.5p Rpar=1T noiseless +C7 1 4 1.5p Rpar=1T noiseless +A6 0 N004 0 0 0 0 N007 0 OTA g=1u linear Cout=454f en=76n enk=5 Rout=1Meg Vhigh=1e308 Vlow=-1e308 +D2 2 4 DBIAS +D4 1 4 DBIAS +A3 0 N007 0 0 0 0 N006 0 OTA g=15u iout=2.06u Cout=13.5p Vlow=-1e308 Vhigh=1e308 +G1 0 N005 N006 0 1µ +C8 0 N005 290f Rpar=1Meg noiseless +D3 3 4 DC +C11 N006 5 10p Rser=400k noiseless +G2 N006 0 N006 3 100m dir=1 vto=-.6 +G3 0 N006 4 N006 100m dir=1 vto=-.6 +.model Y D(Ron=100 Roff=1T Vfwd=3.15 epsilon=.1 noiseless) +.model N VDMOS(Vto=-70m Kp=5m) +.model P VDMOS(Vto=70m Kp=5m pchan) +.model DBIAS D(Ron=100Meg Roff=1T epsilon=.5 ilimit=.5p noiseless) +.model DC D(Ron=2k Roff=1G Vfwd=1 epsilon=.1 ilimit=15.7u noiseless) +.ends LT1462 +* +.subckt LT1464 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.4f +C2 2 1 1p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.5,.1), V(4)+1.5, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.51,.1), V(4)+1.49, .1)+1n*V(2) +C9 3 2 1.5p +C10 N004 0 .5f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .1p +D5 N005 5 Y +D6 5 N005 Y +R2 3 N006 100G noiseless +R3 N006 4 100G noiseless +C4 5 4 .1p +C1 2 4 1.5p +C6 3 1 1.5p +C7 1 4 1.5p +A6 0 N004 0 0 0 0 N007 0 OTA g=1.25u linear Cout=58f en=24n enk=9 Rout=1Meg Vhigh=1e308 Vlow=-1e308 +D2 2 4 DBIAS +D4 1 4 DBIAS +A3 0 N007 0 0 0 0 N006 0 OTA g=20u iout=3.75u Cout=3.97p Vlow=-1e308 Vhigh=1e308 +G1 0 N005 N006 0 1µ +C8 0 N005 11f Rpar=1Meg noiseless +D3 3 4 DC +C11 N006 5 3p Rser=300k noiseless +G2 N006 0 N006 3 100m dir=1 vto=-1.1 +G3 0 N006 4 N006 100m dir=1 vto=-1.1 +.model Y D(Ron=100 Roff=1T Vfwd=1.2 epsilon=.1 noiseless) +.model N VDMOS(Vto=-10m Kp=100m) +.model P VDMOS(Vto=10m Kp=100m pchan) +.model DBIAS D(Ron=1T Roff=1T Ilimit=.4p noiseless) +.model DC D(Ron=2k Roff=1G Vfwd=1 epsilon=.1 ilimit=130u noiseless) +.ends LT1464 +* +.subckt LT1466 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=48f ink=67 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.15,.1), V(4)-.15, .1)+1n*V(1)-26.7p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.16,.1), V(4)-.16, .1)+1n*V(2) +C10 N004 0 1p Rpar=100K noiseless +M1 5 N012 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 N012 4 DLIMN +M2 5 N008 3 3 PI temp=27 +D8 3 N008 DLIMP +C3 3 N008 50p Rser=220k noiseless +A3 N009 N010 4 4 4 4 N008 4 OTA g=200n ref=-27m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C12 N012 4 50p Rser=220k noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=1m linear en=44.9n enk=5 Rout=1k Cout=550p Vlow=-1e308 Vhigh=1e308 +C16 N010 5 4p Rser=40k noiseless +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=4.5u iout=160n Vhigh=1e308 Vlow=-1e308 +G1 4 N012 N010 N009 400n +D9 N010 N009 DLIM +C7 3 1 .5p Rser=100 noiseless +C13 3 4 1000p +G2 0 N009 4 0 .5m +G4 0 N009 3 0 .5m +C18 N009 0 200p Rpar=1K noiseless +G3 0 N007 N006 0 1m +C8 N007 0 150p Rpar=1k noiseless +D1 3 1 DB1 +D2 3 2 DB1 +C4 3 2 .5p Rser=100 noiseless +C5 2 4 .5p Rser=100 noiseless +C6 1 4 .5p Rser=100 noiseless +D3 3 N005 DB2 +D4 2 N005 DB3 +D6 1 N005 DB3 +R3 N005 4 100Meg noiseless +.model NI VDMOS(Vto=300m kp=70m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=24m lambda=.01 pchan is=0) +.model DLIM D(Ron=100k Roff=700Meg Vfwd=1 Vrev=1 epsilon=50m revepsilon=50m noiseless) +.model DLIMN D(Ron=10k Roff=100Meg Vfwd=.85 Vrev=-.3 epsilon=.1 revepsilon=10m noiseless) +.model DLIMP D(Ron=10k Roff=100Meg Vfwd=1.2 Vrev=-.3 epsilon=100m revepsilon=10m noiseless) +.model DB1 D(Ron=1k Roff=50g vfwd=0 epsilon=10m ilimit=6n noiseless) +.model DB2 D(Ron=1k Roff=50g vfwd=1.7 epsilon=100m noiseless) +.model DB3 D(Ron=1k Roff=50g vfwd=200m epsilon=100m ilimit=9n noiseless) +.ends LT1466 +* +.subckt LT1468 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.6p ink=16.4 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N006 I=10u*dnlim(uplim(V(1),V(3)-1.3,.1), V(4)+.5, .1)+1n*V(1) +B2 N006 0 I=10u*dnlim(uplim(V(2),V(3)-1.29,.1), V(4)+0.49, .1)+1n*V(2) +C6 3 1 2p Rser=100 Rpar=480Meg noiseless +C7 1 4 2p noiseless Rser=100 Rpar=480Meg +C8 2 4 2p Rser=100 Rpar=480Meg noiseless +C9 3 2 2p Rser=100 Rpar=480Meg noiseless +C10 N006 0 18.47f Rpar=100K noiseless +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +C11 2 1 1p Rpar=150k noiseless +A2 0 N006 0 0 0 0 N007 0 OTA g=42.1u Iout=1.7u Cout=74.3f en=5n enk=40 Vhigh=1e308 Vlow=-1e308 +D2 N007 3 XU +D3 4 N007 XD +G2 0 N004 N007 0 1m +L2 N004 0 28.64µ Rpar=6.882352941176470585k Rser=1.17k Cpar=139.3f noiseless +G1 0 N005 N004 0 1µ +C1 N005 0 106.1f Rpar=1Meg noiseless +C2 5 N005 110f Rser=10k noiseless +D4 2 1 DI +.model XU D(Ron=1K Roff=100G Vfwd=-1.3 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-1.3 epsilon=.1 noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=.28 epsilon=.1 noiseless) +.model N VDMOS(Vto=-50m Kp=550m) +.model P VDMOS(Vto=50m Kp=550m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=3.413m noiseless) +.model DI D(Ron=250 Roff=1T Vfwd=1 Vrev=1 noiseless) +.ends LT1468 +* +.subckt LT1490A 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=14f ink=114 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+44,.1), V(4)-.1, .1)+1n*V(1) -262p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+44.01,.1), V(4)-.11, .1)+1n*V(2) +C9 3 2 2.3p Rser=2k Rpar=5G noiseless +C10 N004 0 200f Rpar=100K noiseless +D4 3 N009 DBIA3 +C2 3 5 1p Rpar=1g noiseless +D5 VN 4 DLIMN1 +A3 0 X6 3 3 3 3 VP 3 OTA g=800n linear ref=-30m vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +D2 3 2 DBIA2 +D3 3 1 DBIA2 +D10 1 N009 DBIA1 +D11 2 N009 DBIA1 +D6 VN 4 DLIMN2 +A4 0 N004 0 0 0 0 N006 0 OTA g=1m linear en=49.8n enk=3.5 Vhigh=1e308 Vlow=-1e308 +C16 X5 N008 12p +C1 0 N007 1.5p Rpar=5Meg noiseless +A5 N007 0 0 0 0 0 X5 0 OTA g=14u iout=843n Vhigh=1e308 Vlow=-1e308 +D12 1 3 DBIAOT +D13 2 3 DBIAOT +C5 N009 4 20p Rpar=5Meg noiseless +D9 X5 0 DLIM +C6 2 4 2.3p Rser=2k Rpar=5G noiseless +C7 3 1 2.3p Rser=2k Rpar=5G noiseless +C8 1 4 2.3p Rser=2k Rpar=5G noiseless +R3 2 1 17Meg noiseless +C13 3 4 100p +G2 0 N007 N006 0 200n +D7 3 4 DP +L1 N006 0 6.61m Rser=1.12k Rpar=9.33k Cpar=15.7p noiseless +S1 X5 0 4 3 SHUT +S2 3 VP 4 3 SHUT +S3 VN 4 4 3 SHUT +D1 3 VP DLIMP +M1 5 VP N005 N005 PI temp=27 +M2 5 VN 4 4 NI temp=27 +C3 VP 5 .1f +C12 5 VN .1f +A2 0 X6 4 4 4 4 VN 4 OTA g=50n linear ref=30m vlow=-1e308 vhigh=1e308 +D8 3 N005 DILIMU +C14 3 N005 1p Rpar=1g noiseless +G1 0 X6 X5 0 1µ +R7 X6 0 1Meg noiseless +B4 X7 0 I=300p*ddt(V(X7))*(.5+.5*tanh((-380m-V(VP,3))/10m)) +R4 X7 X6 1.5K noiseless +G3 0 N008 5 N011 10m +R8 3 N011 1Meg noiseless +R10 N011 4 1Meg noiseless +C15 N008 0 100f Rpar=100 noiseless +.model DBIA1 D(Ron=1k Roff=100G Vfwd=.1 ilimit=25n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1k Roff=100G Vfwd=0 ilimit=1n epsilon=10m noiseless) +.model DBIA3 D(Ron=1k Roff=10G Vfwd=.7 epsilon=.1 noiseless) +.model DBIAOT D(Ron=50k Vfwd=0 ilimit=2.5u epsilon=50m noiseless) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=28.3u noiseless) +.model DILIMU D(Ron=.1 Roff=100k Vfwd=21m epsilon=2m noiseless) +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.5 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.model DLIMN1 D(Ron=100k Roff=400Meg Vfwd=1.7 Vrev=-310m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=100Meg Roff=1G Vfwd=50m epsilon=100m ilimit=10n noiseless) +.model PI VDMOS(Vto=-300m Kp=32m pchan is=0 noiseless) +.model NI VDMOS(Vto=300m kp=19m noiseless) +.model DLIM D(Ron=10 Roff=70Meg Vfwd=300m Vrev=20m epsilon=10m revepsilon=10m noiseless) +.ends LT1490A +* +.subckt LT1492 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=117f ink=43.5 +M1 3 N005 5 5 N temp=27 +M2 4 N008 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.3,.1), V(4)-.35, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.29,.1), V(4)-.36, .1)+1n*V(2) +C6 3 1 5p Rpar=1.6G noiseless +C7 1 4 5p noiseless Rpar=1.6G +C8 2 4 5p Rpar=1.6G noiseless +C9 3 2 5p Rpar=1.6G noiseless +A2 0 N007 0 0 0 0 N005 0 OTA g=7u iout=1.2u Vlow=-1e308 Vhigh=1e308 Cout=257f +C10 N004 0 1f Rpar=100K noiseless +D4 N005 3 XU +D5 4 N005 XD +D1 N005 5 YU +D6 5 N008 YD +D7 3 4 DP +D2 2 3 DBIASU +D3 1 3 DBIASU +R3 2 1 40Meg noiseless +D8 5 N008 YTAU temp=27 +A3 0 N004 0 0 0 0 N006 0 OTA g=1u linear en=16.5n enk=1 Vlow=-1e308 Vhigh=1e308 Cout=600f +D9 0 N006 DLIM +D10 4 2 DBIASD +D11 4 1 DBIASD +G2 0 N007 N006 0 1m +L2 N007 0 335µ cpar=1f Rser=1160 Rpar=7250 noiseless +G1 0 N008 N005 0 1µ +C1 N008 0 1f Rpar=1Meg noiseless +R4 3 4 333k noiseless +.model XU D(Ron=1K Roff=100G Vfwd=-.66 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=.6 epsilon=.1 noiseless) +.model YU D(Ron=500 Roff=1T Vfwd=2.19 epsilon=.1 noiseless) +.model YD D(Ron=500 Roff=1T Vfwd=2.2 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=20m) +.model P VDMOS(Vto=150m Kp=20m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=184.8u noiseless) +.model DBIASU D(Ron=1k Roff=1T Vfwd=.8 epsilon=.1 Vrev=.8 revepsilon=.1 revilimit=45n noiseless) +.model DBIASD D(Ron=100 Roff=1T Vfwd=.74 epsilon=.2 noiseless) +.model YTAU D(Is=1e-30 N=10 TT=8e-2) +.model DLIM D(Ron=1 Roff=1e6 Vfwd=133m Vrev=133m epsilon=10m revepsilon=10m noiseless) +.ends LT1492 +* +.subckt LT1494 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=8f ink=54.7 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+37,.1), V(4)-.1, .1)+1n*V(1)-663p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+37.01,.1), V(4)-.11, .1)+1n*V(2) +C9 3 2 2.3p Rser=2k noiseless +C10 N004 0 100p Rpar=100K noiseless +D4 3 N011 DBIA3 +M1 5 N012 N014 N014 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D1 3 N005 DVLIMU +D5 N012 4 DLIMN1 +M2 5 N006 N005 N005 PI temp=27 +D8 3 N006 DLIMP1 +C3 3 N006 600p Rser=700k noiseless +A3 N007 N010 4 4 4 4 N006 4 OTA g=800n ref=-.021 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C12 N012 4 10f Rser=2k noiseless +C4 3 N005 1p Rpar=1g noiseless +D2 3 2 DBIA2 +D3 3 1 DBIA2 +D10 1 N011 DBIA1 +D11 2 N011 DBIA1 +D6 N012 4 DLIMN2 +A4 0 N004 0 0 0 0 N008 0 OTA g=1u linear en=232n/freq**.05 Vhigh=1e308 Vlow=-1e308 +C16 N010 5 30p +A5 N009 0 N007 N007 N007 N007 N010 N007 OTA g=500n iout=29.5n Vhigh=1e308 Vlow=-1e308 +D12 1 3 DBIAOT +D13 2 3 DBIAOT +G1 4 N012 N010 N007 50n +C5 N011 4 20p Rpar=50Meg noiseless +E1 N007 4 3 4 0.5 +D9 N010 N007 DLIM +C6 2 4 2.3p Rser=2k noiseless +C7 3 1 2.3p Rser=2k noiseless +C8 1 4 2.3p Rser=2k noiseless +C13 3 4 1000p +C15 N006 N012 10p Rser=300k noiseless +D7 3 4 DP +C17 0 N008 8p Rpar=1Meg noiseless +C19 0 N009 8p Rpar=1Meg noiseless +G4 0 N009 N008 0 1µ +D14 N014 4 DVLIMD +C1 N014 4 1p Rpar=1g noiseless +D15 3 N006 DLIMP2 +C14 N006 5 2p +S1 N010 N007 N007 3 SHUT +S2 3 N006 4 3 SHUT +S3 N012 4 4 3 SHUT +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=.81u noiseless) +.model DBIA1 D(Ron=100k Roff=100T Vfwd=.1 ilimit=1.6p epsilon=.1 noiseless) +.model DBIA2 D(Ron=100k Roff=10T Vfwd=0 ilimit=.2p epsilon=1m noiseless) +.model DBIA3 D(Ron=10Meg Roff=100G Vfwd=.7 epsilon=.1 noiseless) +.model DBIAOT D(Ron=50k Roff=100T Vfwd=0 ilimit=170p epsilon=50m noiseless) +.model DVLIMU D(Ron=10 Roff=1Meg Vfwd=34m epsilon=2m noiseless) +.model DVLIMD D(Ron=10 Roff=1Meg Vfwd=49m epsilon=2m noiseless) +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.1 noiseless) +.model NI VDMOS(Vto=300m kp=1.5m lambda=.01) +.model DLIMN1 D(Ron=100 Roff=2g Vfwd=1.8 Vrev=-320m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=400Meg Roff=2G Vfwd=-10m epsilon=100m ilimit=900p noiseless) +.model PI VDMOS(Vto=-300m Kp=2m lambda=.01 pchan is=0) +.model DLIMP1 D(Ron=100k Roff=300Meg Vfwd=1.33 Vrev=-320m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=100Meg Roff=2g Vfwd=-10m epsilon=100m ilimit=3.5n noiseless) +.model DLIM D(Ron=100k Roff=500Meg Vfwd=100m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.ends LT1494 +* +.subckt LT1497 1 2 3 4 5 +R2 N006 N009 10K noiseless +R3 N009 N012 10K noiseless +Q1 N004 N006 2 0 N temp=27 +Q2 N013 N012 2 0 P temp=27 +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C4 3 5 2.2p +C5 5 4 2.2p +D1 3 N006 1uA m=99 +R19 3 N004 100 noiseless +R20 N013 4 100 noiseless +G5 0 N005 3 N004 1m +G6 N005 0 N013 4 1m +D3 N010 3 X +D4 4 N010 X +G3 0 N007 N010 0 10µ +C1 N007 0 .02p Rpar=100K noiseless +C2 3 2 .5p +C6 3 1 1.5p +C7 2 4 .5p +C8 1 4 1.5p +A2 0 0 1 1 1 1 N009 1 OTA G=.1 Rout=10 Linear Vhigh=100 Vlow=-100 en=3n enk=200 +A3 0 1 0 0 0 0 0 0 OTA in=2p ink=80 +A4 0 2 0 0 0 0 0 0 OTA in=20p ink=150 +D2 N012 4 1uA m=99 +A5 0 N005 0 0 0 0 N010 0 OTA G=27.5u Iout=15u Cout=.02p Vlow=-1e308 Vhigh=1e308 +C3 0 N005 2p Rpar=1K noiseless +D5 5 N007 Y +D6 3 4 1mA m=2.4 +.model N NPN(Cje=.2p Cjc=.2p noiseless) +.model P PNP(Cje=.2p Cjc=.2p noiseless) +.model N VDMOS(Vto=-.2 Kp=.1) +.model P VDMOS(Vto=.2 Kp=.1 pchan) +.model 1uA D(Ron=100K epsilon=.5 Ilimit=1u noiseless) +.model X D(Ron=1K Roff=100Meg epsilon=.2 Vfwd=-.75 noiseless) +.model Y D(Ron=3K Roff=1G epsilon=.3 revepsilon=.3 Vfwd=1.65 Vrev=1.65 noiseless) +.model 1mA D(Ron=2K Ilimit=1m epsilon=3 noiseless) +.ends LT1497 +* +.subckt LT1498 1 2 3 4 5 +C2 2 1 .1p Rpar=100Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.3,.1), V(4)-.3, .1)+1n*V(2) +C6 3 1 2.5p Rpar=1G noiseless +C7 1 4 2.5p noiseless Rpar=1G +C8 2 4 2.5p Rpar=1G noiseless +C9 3 2 2.5p Rpar=1G noiseless +A2 0 N007 0 0 0 0 N009 0 OTA g=76u iout=47u Cout=10p Vhigh=1e308 Vlow=-1e308 +C10 N004 0 28f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 1p +C4 5 4 1p +D5 N005 5 YU +D6 5 N005 YD +D3 3 4 DC +R2 3 N009 10G noiseless +R3 N009 4 10G noiseless +C11 5 N009 35p Rser=7k noiseless +A3 0 N004 0 0 0 0 N006 0 OTA g=1m linear en=12n enk=13 Cout=10p Vlow=-1e308 Vhigh=1e308 +G4 0 N005 N009 0 1e-6 +L2 N005 0 89.8m Rser=2.98Meg Cpar=5.33f Rpar=1.5050505050505050505Meg noiseless +D1 2 1 DCLMP +D7 N006 0 DCLMPI +G5 0 N007 N006 0 1e-5 +C12 N007 0 390f Rpar=1Meg Rser=723k noiseless +D4 N007 N006 DLSIG +D2 3 2 DBIASU +D8 1 N008 DBIASD +R1 3 N008 12.5K noiseless +R6 N008 4 12.5K noiseless +D9 2 N008 DBIASD +D10 3 1 DBIASU +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.2p*exp(3.55/(freq**.3)) +G1 N009 0 N009 3 200m dir=1 vto=.09 +G2 0 N009 4 N009 200m dir=1 vto=.14 +.model YU D(Ron=10k Roff=1T Vfwd=.57 epsilon=.1 noiseless) +.model YD D(Ron=5k Roff=1T Vfwd=.465 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=80m) +.model P VDMOS(Vto=150m Kp=110m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=451.26u noiseless) +.model DCLMP D(Ron=800 Roff=1G Vfwd=0.8 Vrev=0.8 epsilon=.1 revepsilon=.1 noiseless) +.model DLSIG D(Ron=1k Roff=1G Vfwd=.6 Vrev=.6 epsilon=.1 revepsilon=.1 noiseless) +.model DCLMPI D(Ron=1 Roff=1k Vfwd=0.8 Vrev=0.8 epsilon=1. revepsilon=.1 noiseless) +.model DBIASD D(Ron=100K Roff=10G Vfwd= 1.2 ilimit=500n epsilon=.1 noiseless) +.model DBIASU D(Ron=100K Roff=10G Vfwd=-0.2 ilimit=250n epsilon=.1 noiseless) +.ends LT1498 +* +.subckt LTC1540 1 2 3 4 5 6 7 8 +B1 0 N004 I=100u*dnlim(uplim(V(3),V(7)-1.2,.1), V(2)-.2 ,.1)+10n*V(3) +B2 N004 0 I=100u*dnlim(uplim(V(4),V(7)-1.19,.1), V(2)-.21, .1)+10n*V(4) +A1 0 N004 0 0 0 0 N007 0 OTA g=50n asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=3p +C2 N009 0 1p +M1 8 N009 1 1 NOUT temp=27 +C5 7 8 .1p +C6 8 1 .1p Rpar=100Meg +D5 0 N007 DLAT +C4 6 2 20p +R6 7 N009 590Meg +R7 N009 1 590Meg +G3 N009 0 N009 N003 100µ dir=1 vto=0 +G4 0 N009 1 N009 100µ dir=1 vto=.3 +A3 0 N007 N002 0 0 0 N004 0 OTA g=22u linear cout=10f Vlow=-1e308 Vhigh=1e308 +C10 2 3 .5p +C12 2 4 .5p +C13 2 5 .5p +M3 7 N013 6 6 NREF temp=27 +A4 6 N014 2 2 2 2 N013 2 OTA g=5u iout=500n Vlow=-1e308 Vhigh=1e308 Cout=1p Rout=1g +D2 N014 2 DREF +M5 2 N013 6 6 PREF temp=27 +D4 N013 6 DREFILIM1A +D6 6 N013 DREFILIM2A +D7 N003 1 DNL +A5 N007 0 0 0 0 0 N009 0 OTA g=2u iout=1u Vlow=-1e308 Vhigh=1e308 +C14 8 N009 100f +D8 N004 0 DINNLP1 +D9 0 N004 DINNLN1 +D1 0 N002 DLIMHYST +C3 N002 0 100f Rpar=1Meg +C7 0 N004 1f Rpar=2Meg +R9 5 6 10Meg +G2 0 N002 6 5 59m +M2 8 N008 7 7 POUT temp=27 +A2 1 N009 0 0 0 0 N008 0 OTA g=100n linear Vlow=-1e308 Vhigh=1e308 ref=100m +G5 N010 7 N003 1 4n +D3 N008 7 DLIMP +G6 0 N009 N010 N008 100µ dir=1 vto=0 +C1 7 N003 100f Rpar=600Meg +C8 7 N010 100f Rpar=500Meg +C9 7 N008 .01f +C11 7 N014 100f Rpar=100Meg +S1 7 N008 1 7 SOFF +S2 N009 1 1 7 SOFF +D10 6 N013 DREFILIM2B +D11 N013 6 DREFILIM1B +D12 N004 0 DINNLP2 +D13 0 N004 DINNLN2 +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model POUT VDMOS(Vto=-18m kp=200m mtriode=.5 rd=10 pchan) +.model NREF VDMOS(Vto=-18m kp=5m) +.model PREF VDMOS(Vto=20m kp=1m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DINNLP1 D(Vfwd=1.05 Ron=25k Roff=5Meg epsilon=30m) +.model DINNLP2 D(Vfwd=1.3 Roff=1G Ron=100 epsilon=50m) +.model DINNLN1 D(Vfwd=1.05 epsilon=50m Ron=25k Roff=100Meg) +.model DINNLN2 D(Vfwd=1.3 Roff=1G Ron=100 epsilon=50m) +.model DLAT D(Ron=1 Roff=100Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMHYST D(Ron=.1 Roff=100 Vfwd=0 epsilon=10m Vrev=320m revepsilon=5m) +.model DLIMP D(Vfwd=300m Roff=200Meg Ron=100k epsilon=100m) +.model SOFF SW(Ron=1 Roff=1G Vt=-1.8 Vh=-.2) +.model DREF D(Ron=10 Roff=1T Vfwd=1.182 epsilon=.1) +.model DREFILIM1A D(Roff=4G Ron=200Meg Vfwd=100m epsilon=100m) +.model DREFILIM1B D(Roff=4G Ron=1Meg Vfwd=950m epsilon=100m) +.model DREFILIM2A D(Roff=4G Ron=1Meg Vfwd=90m epsilon=200m) +.model DREFILIM2B D(Roff=4G Ron=100k Vfwd=185m epsilon=100m) +.ends LTC1540 +* +.subckt LTC1541 1 2 3 4 5 6 7 8 +B1 0 N003 I=100u*dnlim(uplim(V(5),V(8)-1.2,.1), V(4)-.2 ,.1)+10n*V(5)-210n*V(VLAT,VREF) +B2 N003 0 I=100u*dnlim(uplim(V(6),V(8)-1.19,.1), V(4)-.21, .1)+10n*V(6) +A1 N003 0 VREF VREF VREF VREF VLAT VREF OTA g=38u linear Vlow=-1e308 Vhigh=1e308 Cout=10f +D5 VREF VLAT DLAT +C4 6 4 .5p +C10 4 5 .5p +M3 8 N005 6 6 NREF temp=27 +A4 6 N007 4 4 4 4 N005 4 OTA g=5u iout=500n Vlow=-1e308 Vhigh=1e308 Cout=1p Rout=1g +D2 N007 4 DREF +M5 4 N005 6 6 PREF temp=27 +D4 N005 6 DREFILIM1A +D6 6 N005 DREFILIM2 +D9 0 N003 DINNL +C11 8 N007 100f Rpar=10Meg +M1 7 N010 4 4 NOUT temp=27 +D1 N010 4 DLIMNC +M2 7 N006 8 8 POUT temp=27 +D3 8 N006 DLIMPC +C1 8 N006 .1f Rser=7Meg noiseless +A2 VREF VLAT 4 4 4 4 N006 4 OTA g=200n ref=-16m linear vlow=-1e308 vhigh=1e308 +C2 8 7 .1p Rpar=10Meg noiseless +C3 7 4 .1p Rpar=10Meg noiseless +C6 N006 7 .01f Rser=1k noiseless +C9 N010 4 .1f Rser=7Meg noiseless +S1 8 N006 4 8 SOFF +S2 N010 4 4 8 SOFF +A3 VREF VLAT 4 4 4 4 N010 4 OTA g=200n ref=16m linear vlow=-1e308 vhigh=1e308 +D7 N005 6 DREFILIM1B +A5 2 3 0 0 0 0 0 0 OTA g=0 in=11.3f ink=12.8 +B3 0 N012 I=10u*dnlim(uplim(V(3),V(8)-1.2,.1), V(4)-.15, .1)+1n*V(3)-2n +B4 N012 0 I=10u*dnlim(uplim(V(2),V(8)-1.19,.1), V(4)-.16, .1)+1n*V(2) +C5 N012 0 500f Rpar=100K noiseless +M4 1 N017 4 4 NI temp=27 +C12 8 1 1p Rpar=10G noiseless +D8 N017 4 DLIMN1 +M6 1 VP 8 8 PI temp=27 +C13 8 VP 5p Rser=100k noiseless +C14 1 4 1p Rpar=10G noiseless +C15 N017 4 1p Rser=500k noiseless +A6 0 N012 0 0 0 0 N013 0 OTA g=1u linear en=300n Vhigh=1e308 Vlow=-1e308 +C16 N015 1 38p +A7 N013 0 VREF VREF VREF VREF N015 VREF OTA g=4u iout=304n Vhigh=1e308 Vlow=-1e308 +G1 4 N017 N015 VREF 10n +D10 N015 VREF DLIM +C17 VP 1 400f +B5 VP 4 I=2n*V(VP,1)/dnlim(V(8,4),1.7,.1) +C18 8 3 3p Rpar=4T noiseless +C19 8 4 1000p +C20 VP N017 200f Rser=250k noiseless +C21 N013 0 6p Rpar=1Meg noiseless +G2 0 VREF 4 0 .5m +G3 0 VREF 8 0 .5m +C22 VREF 0 500p Rpar=1k noiseless +D11 N017 4 DLIMN2 +C23 8 2 3p Rpar=4T noiseless +C24 3 4 3p Rpar=4T noiseless +C25 2 4 3p Rpar=4T noiseless +R1 2 3 10G noiseless +D12 2 4 DBIAS +D13 3 4 DBIAS +A8 VREF N015 4 4 4 4 VP 4 OTA g=350n ref=-.057 linear vlow=-1e308 vhigh=1e308 +D14 8 VP DLIMP1 +D15 8 VP DLIMP2 +S3 8 VP 4 8 SOFF +S4 N017 4 4 8 SOFF +C8 7 N010 .01f Rser=1k noiseless +C27 VLAT 7 20p +L1 N003 0 2.26 Cpar=12p Rpar=116k Rser=711k +D16 8 4 DP +D17 5 4 DBIAS +.model NOUT VDMOS(Vto=305m kp=18m) +.model POUT VDMOS(Vto=-305m kp=10m pchan) +.model NREF VDMOS(Vto=-33m kp=100u) +.model PREF VDMOS(Vto=33m kp=1m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DINNL D(Vfwd=220m Vrev=220m Ron=100 Roff=5Meg epsilon=80m revepsilon=80m) +.model DLAT D(Ron=100 Roff=100Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMNC D(Ron=100k Roff=100Meg Vfwd=2.42 Vrev=-300m epsilon=900m revepsilon=10m) +.model DLIMPC D(Ron=100k Roff=100Meg Vfwd=4.2 Vrev=-300m epsilon=10m revepsilon=10m) +.model SOFF SW(Ron=100 Roff=100G Vt=-1.8 Vh=-.2 noiseless) +.model DREF D(Ron=1 Roff=1T Vfwd=1.2 epsilon=.1) +.model DREFILIM1A D(Roff=1G Ron=50Meg Vfwd=150m epsilon=100m) +.model DREFILIM1B D(Roff=1G Ron=1Meg Vfwd=880m epsilon=200m) +.model DREFILIM2 D(Roff=1G Ron=10Meg Vfwd=2.3 epsilon=500m) +.model DP D(Ron=1k Roff=1G Vfwd=1.8 epsilon=.1 ilimit=4u) +.model DBIAS D(Ron=1Meg Roff=4T Vfwd=.5 epsilon=.1 ilimit=10p noiseless) +.model NI VDMOS(Vto=300m kp=20m) +.model PI VDMOS(Vto=-300m Kp=20m pchan) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=4 Vrev=2.5 epsilon=10m revepsilon=10m noiseless) +.model DLIMN1 D(Ron=20k Roff=1g Vfwd=.72 Vrev=-280m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=600Meg Roff=2G Vfwd=200m epsilon=5m ilimit=150p noiseless) +.model DLIMP1 D(Ron=100k Roff=500Meg Vfwd=.65 Vrev=-305m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=100Meg Roff=10g Vfwd=100m epsilon=10m ilimit=2.5n noiseless) +.ends LTC1541 +* +.subckt LTC1542 1 2 3 4 5 6 7 8 +B1 0 N003 I=100u*dnlim(uplim(V(5),V(8)-1.2,.1), V(4)-.2 ,.1)+10n*V(5)-210n*V(VLAT,VREF) +B2 N003 0 I=100u*dnlim(uplim(V(6),V(8)-1.19,.1), V(4)-.21, .1)+10n*V(6) +A1 N003 0 VREF VREF VREF VREF VLAT VREF OTA g=38u linear Vlow=-1e308 Vhigh=1e308 Cout=10f +D5 VREF VLAT DLAT +C4 6 4 .5p +C10 4 5 .5p +D9 0 N003 DINNL +M1 7 N008 4 4 NOUT temp=27 +D1 N008 4 DLIMNC +M2 7 N005 8 8 POUT temp=27 +D3 8 N005 DLIMPC +C1 8 N005 .1f Rser=7Meg noiseless +A2 VREF VLAT 4 4 4 4 N005 4 OTA g=200n ref=-16m linear vlow=-1e308 vhigh=1e308 +C2 8 7 .1p Rpar=10Meg noiseless +C3 7 4 .1p Rpar=10Meg noiseless +C6 N005 7 .01f Rser=1k noiseless +C9 N008 4 .1f Rser=7Meg noiseless +S1 8 N005 4 8 SOFF +S2 N008 4 4 8 SOFF +A3 VREF VLAT 4 4 4 4 N008 4 OTA g=200n ref=16m linear vlow=-1e308 vhigh=1e308 +A5 2 3 0 0 0 0 0 0 OTA g=0 in=11.3f ink=12.8 +B3 0 N010 I=10u*dnlim(uplim(V(3),V(8)-1.2,.1), V(4)-.15, .1)+1n*V(3)-2n +B4 N010 0 I=10u*dnlim(uplim(V(2),V(8)-1.19,.1), V(4)-.16, .1)+1n*V(2) +C5 N010 0 500f Rpar=100K noiseless +M4 1 N015 4 4 NI temp=27 +C12 8 1 1p Rpar=10G noiseless +D8 N015 4 DLIMN1 +M6 1 VP 8 8 PI temp=27 +C13 8 VP 5p Rser=100k noiseless +C14 1 4 1p Rpar=10G noiseless +C15 N015 4 1p Rser=500k noiseless +A6 0 N010 0 0 0 0 N011 0 OTA g=1u linear en=300n Vhigh=1e308 Vlow=-1e308 +C16 N013 1 38p +A7 N011 0 VREF VREF VREF VREF N013 VREF OTA g=4u iout=304n Vhigh=1e308 Vlow=-1e308 +G1 4 N015 N013 VREF 10n +D10 N013 VREF DLIM +C17 VP 1 400f +B5 VP 4 I=2n*V(VP,1)/dnlim(V(8,4),1.7,.1) +C18 8 3 3p Rpar=4T noiseless +C19 8 4 1000p +C20 VP N015 200f Rser=250k noiseless +C21 N011 0 6p Rpar=1Meg noiseless +G2 0 VREF 4 0 .5m +G3 0 VREF 8 0 .5m +C22 VREF 0 500p Rpar=1k noiseless +D11 N015 4 DLIMN2 +C23 8 2 3p Rpar=4T noiseless +C24 3 4 3p Rpar=4T noiseless +C25 2 4 3p Rpar=4T noiseless +R1 2 3 10G noiseless +D12 2 4 DBIAS +D13 3 4 DBIAS +A8 VREF N013 4 4 4 4 VP 4 OTA g=350n ref=-.057 linear vlow=-1e308 vhigh=1e308 +D14 8 VP DLIMP1 +D15 8 VP DLIMP2 +S3 8 VP 4 8 SOFF +S4 N015 4 4 8 SOFF +C8 7 N008 .01f Rser=1k noiseless +C27 VLAT 7 20p +L1 N003 0 2.26 Cpar=12p Rpar=116k Rser=711k +D16 8 4 DP +D2 5 4 DBIAS +D4 6 4 DBIAS +.model NOUT VDMOS(Vto=305m kp=18m) +.model POUT VDMOS(Vto=-305m kp=10m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DINNL D(Vfwd=220m Vrev=220m Ron=100 Roff=5Meg epsilon=80m revepsilon=80m) +.model DLAT D(Ron=100 Roff=100Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMNC D(Ron=100k Roff=100Meg Vfwd=2.42 Vrev=-300m epsilon=900m revepsilon=10m) +.model DLIMPC D(Ron=100k Roff=100Meg Vfwd=4.2 Vrev=-300m epsilon=10m revepsilon=10m) +.model SOFF SW(Ron=100 Roff=100G Vt=-1.8 Vh=-.2 noiseless) +.model DP D(Ron=1k Roff=1G Vfwd=1.8 epsilon=.1 ilimit=4u) +.model DBIAS D(Ron=1Meg Roff=4T Vfwd=.5 epsilon=.1 ilimit=10p noiseless) +.model NI VDMOS(Vto=300m kp=20m) +.model PI VDMOS(Vto=-300m Kp=20m pchan) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=4 Vrev=2.5 epsilon=10m revepsilon=10m noiseless) +.model DLIMN1 D(Ron=20k Roff=1g Vfwd=.72 Vrev=-280m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=600Meg Roff=2G Vfwd=200m epsilon=5m ilimit=150p noiseless) +.model DLIMP1 D(Ron=100k Roff=500Meg Vfwd=.65 Vrev=-305m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=100Meg Roff=10g Vfwd=100m epsilon=10m ilimit=2.5n noiseless) +.ends LTC1542 +* +.subckt LT1630 1 2 3 4 5 +B1 0 N004 I=1m*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+100n*V(1)-30.6n +B2 N004 0 I=1m*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+100n*V(2) +C10 N004 0 1f Rpar=1K noiseless +M1 5 N012 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +M2 5 N005 3 3 PI temp=27 +C3 3 N005 100f Rser=120Meg noiseless +A3 N006 N009 4 4 4 4 N005 4 OTA g=35n ref=-.011 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C12 N012 4 100f Rser=120Meg noiseless +D6 N012 4 DLIMN1 +A4 0 N004 0 0 0 0 N007 0 OTA g=1u linear en=5.9n enk=24.6 Vhigh=1e308 Vlow=-1e308 +C16 N009 5 4p +A5 N008 0 N006 N006 N006 N006 N009 N006 OTA g=1250u iout=44u Cout=100f Vhigh=1e308 Vlow=-1e308 +G1 4 N012 N009 N006 20n +D7 3 4 DP +C17 0 N007 250f Rpar=2Meg noiseless +G4 0 N008 N007 0 1m +D14 3 N005 DLIMP2 +L1 N008 0 69.3µ Cpar=829f Rser=1.31k Rpar=4.22k noiseless +G2 0 N006 3 0 .5m +G3 0 N006 4 0 .5m +C14 N006 0 1p noiseless Rpar=1k +D9 N009 N006 DLIM1 +D10 3 N005 DLIMP1 +D11 0 N007 DLIM0 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=891f ink=19 +C1 3 2 2.5p Rpar=100Meg noiseless +D1 2 1 DINLIM +D2 3 N010 DBIASR +D3 1 N010 DBIASIN +D4 2 N010 DBIASIN +D5 2 3 DBIASO +D8 1 3 DBIASO +D12 4 1 DBIASB +D13 4 2 DBIASB +C4 3 1 2.5p Rpar=100Meg noiseless +C5 2 4 2.5p Rpar=100Meg noiseless +C6 1 4 2.5p Rpar=100Meg noiseless +C7 N010 4 100f Rpar=500k +.model NI VDMOS(Vto=300m kp=20m lambda=.01) +.model PI VDMOS(Vto=-300m kp=20m lambda=.01 pchan) +.model DP D(Roff=1G Ron=100 Vfwd=0.5 ilimit=1.87m noiseless) +.model DLIM0 D(Ron=100 Roff=2Meg vfwd=42m epsilon=5m vrev=42m revepsilon=5m noiseless) +.model DLIM1 D(Ron=10 Roff=60k Vfwd=100m epsilon=10m Vrev=100m revepsilon=10m noiseless) +.model DLIMP1 D(Ron=100k Roff=45g Vfwd=1.8 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DLIMP2 D(Ron=1g Roff=10g Vfwd=0 epsilon=100m ilimit=300p noiseless) +.model DLIMN1 D(Ron=1Meg Roff=15g Vfwd=2.2 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model DBIASR D(Ron=1k Roff=10Meg Vfwd=1.2 epsilon=.1 noiseless) +.model DBIASIN D(Ron=100k Roff=1G Vfwd=0 epsilon=.1 ilimit=1.08u noiseless) +.model DBIASO D(Ron=100k Roff=1G Vfwd=.9 Vrev=-.9 epsilon=.1 revepsilon=10m revilimit=620n noiseless) +.model DBIASB D(Ron=100k Roff=1G Vfwd=.8 epsilon=.1 noiseless) +.model DINLIM D(Ron=570 Roff=10G Vfwd=.8 Vrev=.8 epsilon=.1 revepsilon=.1 noiseless) +.ends LT1630 +* +.subckt LT1632 1 2 3 4 5 +B1 0 N004 I=1m*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+100n*V(1)-28.89n +B2 N004 0 I=1m*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+100n*V(2) +C10 N004 0 .1f Rpar=1K noiseless +M1 5 N012 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +M2 5 N005 3 3 PI temp=27 +C3 3 N005 100f Rser=200Meg noiseless +A3 N006 N009 4 4 4 4 N005 4 OTA g=35n ref=-.04 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C12 N012 4 100f Rser=200Meg noiseless +D6 N012 4 DLIMN +A4 0 N004 0 0 0 0 N007 0 OTA g=5u linear en=11.9n enk=20 Vhigh=1e308 Vlow=-1e308 +C16 N009 5 300f +A5 N008 0 N006 N006 N006 N006 N009 N006 OTA g=13u iout=12u Cout=100f Vhigh=1e308 Vlow=-1e308 +G1 4 N012 N009 N006 5n +C7 3 1 2p Rser=225 noiseless +C13 3 4 1000p +D7 3 4 DP +C17 0 N007 200f Rpar=2Meg noiseless +G4 0 N008 N007 0 1m +D14 3 N005 DLIMP +L1 N008 0 91.35µ Cpar=353f Rser=1.15k Rpar=7.67k noiseless +G2 0 N006 3 0 .5m +G3 0 N006 4 0 .5m +C14 N006 0 100f noiseless Rpar=1k +D9 N009 N006 DLIM1 +C8 2 1 2p Rser=450 Rpar=8Meg noiseless +D17 N007 0 DSI Temp=27 +D19 0 N007 DSI Temp=27 +D1 3 N010 DBIASR +C5 N010 4 100f Rpar=83.3k noiseless +D2 2 1 DINLIM +D3 2 3 DBIASO +D4 1 3 DBIASO +D5 2 N010 DBIASIN +D8 1 N010 DBIASIN +C1 3 2 2p Rser=225 noiseless +C4 1 4 2p Rser=225 noiseless +C6 2 4 2p Rser=225 noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.6p ink=26 +.model NI VDMOS(Vto=300m kp=20m lambda=.01) +.model PI VDMOS(Vto=-300m kp=20m lambda=.01 pchan) +.model DP D(Roff=1G Ron=100 Vfwd=0.5 ilimit=3.42m noiseless) +.model DSI D(Is=1e-17 n=1 tt=500p noiseless) +.model DLIM1 D(Ron=10 Roff=6Meg Vfwd=2 epsilon=100m Vrev=2 revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=2.3 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DLIMN D(Ron=1Meg Roff=5g Vfwd=2.2 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model DBIASR D(Ron=1k Roff=10Meg Vfwd=1.2 epsilon=.1 noiseless) +.model DBIASIN D(Ron=100k Roff=1G Vfwd=0 epsilon=.1 ilimit=2.3u noiseless) +.model DBIASO D(Ron=100k Roff=1G Vfwd=.9 Vrev=-.9 epsilon=.1 revepsilon=10m revilimit=1.15u noiseless) +.model DBIASB D(Ron=100k Roff=1G Vfwd=.8 epsilon=.1 noiseless) +.model DINLIM D(Ron=600 Roff=10G Vfwd=1.5 Vrev=1.5 epsilon=.1 revepsilon=.1 noiseless) +.model DLIM D(Ron=1k Roff=17.7Meg Vfwd=2.5 Vrev=2.5 epsilon=1 revepsilon=1 noiseless) +.ends LT1632 +* +.subckt LT1635 1 2 3 4 5 6 7 +M1 3 N010 6 6 NREF temp=27 +M2 6 4 4 4 NREFCS temp=27 +A1 0 N009 4 4 4 4 N010 4 OTA g=35.6u Iout=35n Vhigh=1e308 Vlow=-1e308 +D1 N010 3 XUREF +D2 4 N010 XDREF +B2 N009 0 I=10u*dnlim(uplim(V(7),V(3)-0.9,.1), V(4)-.2, .1) +C1 N009 0 10f Rpar=100K noiseless +D3 N010 6 DILIM +A2 2 1 0 0 0 0 0 0 OTA g=0 in=230f ink=1.45 +C3 2 1 1p Rpar=25Meg noiseless +C9 3 2 .5p Rser=6k Rpar=12G noiseless +D4 1 3 DBIAS +D5 2 3 DBIAS +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.8,.1), V(4)-.1, .1)+1n*V(1)-12.5n +B3 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.79,.1), V(4)-.12, .1)+1n*V(2) +C2 N004 0 10f Rpar=100K noiseless +M3 5 N007 4 4 NI temp=27 +C4 3 5 1p Rpar=1g noiseless +D7 N007 4 DLIMN1 +M4 5 VP 3 3 PI temp=27 +D8 3 VP DLIMP +C5 3 VP 10p Rser=500k noiseless +A3 N005 X4 4 4 4 4 VP 4 OTA g=800n ref=-.69 linear vlow=-1e308 vhigh=1e308 +C10 5 4 1p Rpar=1g noiseless +C11 N007 4 10f Rser=1Meg noiseless +D9 N007 4 DLIMN2 +A4 0 N004 0 0 0 0 X1 0 OTA g=1u linear en=52n enk=.97 rout=1Meg cout=18p Vlow=-.5 Vhigh=.2 +C13 X4 5 4p +A5 X3 0 N005 N005 N005 N005 X4 N005 OTA g=7.9u asym isource=240n isink=-192n rout=70Meg Vlow=-1e308 Vhigh=1e308 +G1 4 N007 X4 N005 29n +B4 VP 4 I=10n*V(VP,5)/dnlim(V(3,4),2,.1) +C14 VP N007 100f Rser=1Meg +G2 0 X3 X2 0 1m +L1 X3 0 8.06m Cpar=353f Rser=1.01k Rpar=101k noiseless +B5 0 N009 I=10u*v(4)+2u +C16 3 7 .5p Rpar=12G noiseless +C17 7 4 .5p Rpar=12G noiseless +E2 N005 4 3 4 0.5 +C18 N005 N010 7p +C19 X2 0 23p Rser=384k Rpar=1Meg noiseless +G4 0 X2 X1 0 1µ +D6 3 4 DP +C12 3 6 1p Rpar=1g noiseless +C15 6 4 1p Rpar=1g noiseless +C6 3 1 .5p Rser=6k Rpar=12G noiseless +C7 2 4 .5p Rser=6k Rpar=12G noiseless +C8 1 4 .5p Rser=6k Rpar=12G noiseless +D10 X2 X1 DLS +.model NREF VDMOS(vto=-200m kp=30m) +.model NREFCS VDMOS(vto=-300m kp=800u oneway) +.model DILIM D(Ron=1k Roff=550Meg Vfwd=210m epsilon=10m noiseless) +.model XUREF D(Ron=1k Roff=10G Vfwd=-950m epsilon=1 noiseless) +.model XDREF D(Ron=1k Roff=10G Vfwd=100m epsilon=100m noiseless) +.model DBIAS D(Ron=1Meg Roff=10G Vrev=.8 revilimit=1.5n noiseless) +.model DLS D(Ron=100 Roff=10G vfwd=100m vrev=100m epsilon=10m revepsilon=10m noiseless) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=85.62u noiseless) +.model NI VDMOS(Vto=300m kp=15m lambda=.01 rs=2) +.model PI VDMOS(Vto=-300m Kp=15m lambda=.01 pchan) +.model DLIMN1 D(Ron=200k Roff=400Meg Vfwd=4 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=12Meg Roff=1G Vfwd=-40m epsilon=50m ilimit=21.8n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=3 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.ends LT1635 +* +.subckt LT1636 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=34.3f ink=40.1 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)+44,.1), V(4)-.1, .1)+1n*V(1)-113.7p +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)+44.01,.1), V(4)-.11, .1)+1n*V(2) +C9 3 2 2p Rser=2k Rpar=24G noiseless +C10 N005 0 200f Rpar=100K noiseless +D4 3 N010 DBIA3 +D2 3 2 DBIA2 +D3 3 1 DBIA2 +D10 1 N010 DBIA1 +D11 2 N010 DBIA1 +A4 0 N005 0 0 0 0 N007 0 OTA g=1u linear en=51.98n enk=.86 Vhigh=1e308 Vlow=-1e308 +A5 N008 0 0 0 0 0 X5 0 OTA g=20u iout=840n Vhigh=1e308 Vlow=-1e308 +D12 1 3 DBIAOT +D13 2 3 DBIAOT +C5 N010 4 20p Rpar=15Meg noiseless +D9 X5 0 DLIM +C6 2 4 2p Rser=2k noiseless +C7 3 1 2p Rser=2k Rpar=24G noiseless +C8 1 4 2p Rser=2k noiseless +R3 2 1 13Meg noiseless +C13 3 4 100p +G3 0 N004 3 4 50n +S4 N004 0 6 4 SHUTI +C20 N007 0 15p noiseless Rpar=1Meg +G7 0 N008 N007 0 1m +L1 N008 0 7.7m Cpar=8.8p Rser=1.21k Rpar=5.76k noiseless +C21 N004 0 18p +C17 4 6 100f Rpar=1Meg noiseless +D14 4 1 DPROT +D15 4 2 DPROT +C2 3 5 1p Rpar=1g noiseless +D1 VN 4 DLIMN1 +A2 0 X6 3 3 3 3 VP 3 OTA g=800n linear ref=-20m vlow=-1e308 vhigh=1e308 +C3 5 4 1p Rpar=1g noiseless +D5 VN 4 DLIMN2 +C4 X5 N009 12p +S1 X5 0 0 N004 SHUT +S3 VN 4 0 N004 SHUT +D6 3 VP DLIMP +M1 5 VP N006 N006 PI temp=27 +M2 5 VN 4 4 NI temp=27 +C11 VP 5 .1f +C12 5 VN .1f +A3 0 X6 4 4 4 4 VN 4 OTA g=50n linear ref=20m vlow=-1e308 vhigh=1e308 +D8 3 N006 DILIMU +C14 3 N006 1p Rpar=1g noiseless +G1 0 N009 5 N012 10m +R6 3 N012 8Meg noiseless +R7 N012 4 8Meg noiseless +C16 N009 0 100f Rpar=100 noiseless +G2 0 X6 X5 0 1µ +R4 X6 0 1Meg noiseless +R8 X7 X6 2K noiseless +S2 3 VP 0 N004 SHUT +S5 3 4 N004 0 SP +B4 X7 0 I=300p*ddt(V(X7))*(.5+.5*tanh((-360m-V(VP,3))/5m)) +.model DBIA1 D(Ron=1k Roff=100G Vfwd=.1 ilimit=15n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1k Roff=100G Vfwd=0 ilimit=5n epsilon=10m noiseless) +.model DBIA3 D(Ron=1k Roff=10G Vfwd=.7 epsilon=.1 noiseless) +.model DBIAOT D(Ron=10k Vfwd=0 ilimit=2.2u epsilon=50m noiseless) +.model DPROT D(Ron=1k Roff=24G Vfwd=1 epsilon=10m noiseless) +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.9 noiseless) +.model SHUTI SW(Ron=100 Roff=20Meg vt=1.2 vh=-10m noiseless) +.model DILIMU D(Ron=.1 Roff=100k Vfwd=21m epsilon=2m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.3 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.model DLIMN1 D(Ron=100k Roff=400Meg Vfwd=1.5 Vrev=-310m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=100Meg Roff=1G Vfwd=50m epsilon=100m ilimit=10n noiseless) +.model SP SW(level=2 Ron=100 Roff=1G vt=.5 vh=-200m ilimit=45.47u noiseless) +.model PI VDMOS(Vto=-300m Kp=32m pchan is=0 noiseless) +.model NI VDMOS(Vto=300m kp=19m Rd=50 noiseless) +.model DLIM D(Ron=10 Roff=70Meg Vfwd=300m Vrev=20m epsilon=10m revepsilon=10m noiseless) +.ends LT1636 +* +.subckt LT1637 1 2 3 4 5 6 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)+44,.1), V(4)-.1, .1)+1n*V(1)-158.9p +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)+44.01,.1), V(4)-.11, .1)+1n*V(2) +C10 N005 0 200f Rpar=100K noiseless +D4 3 N010 DBIA3 +D2 3 2 DBIA2 +D3 3 1 DBIA2 +D10 1 N010 DBIA1 +D11 2 N010 DBIA1 +A5 N008 0 0 0 0 0 X5 0 OTA g=20u iout=1.06u Vhigh=1e308 Vlow=-1e308 +D12 1 3 DBIAOT +D13 2 3 DBIAOT +C5 N010 4 20p Rpar=15Meg noiseless +D9 X5 0 DLIM +C13 3 4 100p +G3 0 N004 3 4 50n +S4 N004 0 6 4 SHUTI +C21 N004 0 18p +C17 4 6 100f Rpar=1Meg noiseless +D14 4 1 DPROT +D15 4 2 DPROT +C2 3 5 1p Rpar=1G noiseless +D1 VN 4 DLIMN1 +A2 0 X6 3 3 3 3 VP 3 OTA g=800n linear ref=-25m vlow=-1e308 vhigh=1e308 +C3 5 4 1p Rpar=1G noiseless +D5 VN 4 DLIMN2 +C4 X5 N009 2.8p +S1 X5 0 0 N004 SHUT +S3 VN 4 0 N004 SHUT +D6 3 VP DLIMP +M1 5 VP N006 N006 PI temp=27 +M2 5 VN 4 4 NI temp=27 +C11 VP 5 .01f +C12 5 VN .01f +A3 0 X6 4 4 4 4 VN 4 OTA g=50n linear ref=25m vlow=-1e308 vhigh=1e308 +D8 3 N006 DILIMU +C14 3 N006 1p Rpar=1g noiseless +G1 0 N009 5 N012 10m +R6 3 N012 2Meg noiseless +R7 N012 4 2Meg noiseless +C16 N009 0 1f Rpar=100 noiseless +G2 0 X6 X5 0 1µ +R4 X6 0 1Meg noiseless +B3 X7 0 I=120p*ddt(V(X7))*(.5+.5*tanh((-380m-V(VP,3))/20m)) +R8 X7 X6 10K noiseless +S2 3 VP 0 N004 SHUT +S5 3 4 N004 0 SP +C1 3 1 2p Rser=2k Rpar=4.4G noiseless +C6 1 4 2p Rser=2k Rpar=4.4G noiseless +C7 3 2 2p Rser=2k Rpar=4.4G noiseless +C8 2 4 2p Rser=2k Rpar=4.4G noiseless +R3 2 1 3Meg noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=74.8f ink=143 +G4 0 N008 N007 0 1m +L1 N008 0 2.5m Cpar=70f Rser=1.1k Rpar=11k noiseless +A4 0 N005 0 0 0 0 N007 0 OTA g=1u linear en=27n enk=1.3 cout=4p Rout=1Meg Vlow=-1e308 Vhigh=1e308 +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.9 noiseless) +.model SHUTI SW(Ron=100 Roff=20Meg vt=1.2 vh=-10m noiseless) +.model DILIMU D(Ron=.1 Roff=100k Vfwd=25m epsilon=2m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.15 Vrev=-.3 epsilon=100m revepsilon=10m noiseless) +.model DLIMN1 D(Ron=100k Roff=400Meg Vfwd=1.5 Vrev=-310m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=100Meg Roff=1G Vfwd=50m epsilon=100m ilimit=10n noiseless) +.model SP SW(level=2 Ron=100 Roff=1G vt=.5 vh=-200m ilimit=219.8u noiseless) +.model PI VDMOS(Vto=-300m Kp=32m pchan is=0 noiseless) +.model NI VDMOS(Vto=300m kp=19m Rd=50 noiseless) +.model DLIM D(Ron=10 Roff=70Meg Vfwd=300m Vrev=20m epsilon=20m revepsilon=10m noiseless) +.model DBIA1 D(Ron=1k Roff=100G Vfwd=.1 ilimit=100n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1k Roff=100G Vfwd=0 ilimit=20n epsilon=10m noiseless) +.model DBIA3 D(Ron=1k Roff=10G Vfwd=.9 epsilon=.1 noiseless) +.model DBIAOT D(Ron=10k Vfwd=0 ilimit=22u epsilon=50m noiseless) +.model DPROT D(Ron=1.3k Roff=4.4G Vfwd=1 epsilon=10m noiseless) +.ends LT1637 +* +.subckt LT1638 1 2 3 4 5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+44,.1), V(4)-.1, .1)+1n*V(1)-158.9p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+44.01,.1), V(4)-.11, .1)+1n*V(2) +C10 N004 0 200f Rpar=100K noiseless +D4 3 N009 DBIA3 +D2 3 2 DBIA2 +D3 3 1 DBIA2 +D10 1 N009 DBIA1 +D11 2 N009 DBIA1 +A5 N007 0 0 0 0 0 X5 0 OTA g=20u iout=1.07u Vhigh=1e308 Vlow=-1e308 +D12 1 3 DBIAOT +D13 2 3 DBIAOT +C5 N009 4 20p Rpar=15Meg noiseless +D9 X5 0 DLIM +C13 3 4 100p Rpar=714k noiseless +D14 4 1 DPROT +D15 4 2 DPROT +C2 3 5 1p Rpar=1G noiseless +D1 VN 4 DLIMN1 +A2 0 X6 3 3 3 3 VP 3 OTA g=800n linear ref=-22m vlow=-1e308 vhigh=1e308 +C3 5 4 1p Rpar=1G noiseless +D5 VN 4 DLIMN2 +C4 X5 N008 2.8p +D6 3 VP DLIMP +M1 5 VP N005 N005 PI temp=27 +M2 5 VN 4 4 NI temp=27 +C11 VP 5 .01f +C12 5 VN .01f +A3 0 X6 4 4 4 4 VN 4 OTA g=65n linear ref=22m vlow=-1e308 vhigh=1e308 +D8 3 N005 DILIMU +C14 3 N005 1p Rpar=1g noiseless +G1 0 N008 5 N011 10m +R6 3 N011 2Meg noiseless +R7 N011 4 2Meg noiseless +C16 N008 0 1f Rpar=100 noiseless +G2 0 X6 X5 0 1µ +R4 X6 0 1Meg noiseless +B3 X7 0 I=120p*ddt(V(X7))*(.5+.5*tanh((-380m-V(VP,3))/15m)) +R8 X7 X6 10K noiseless +G4 0 N007 N006 0 1m +L1 N007 0 1.26m Cpar=4p Rser=1.28k Rpar=4.57k noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=1u linear en=19.8n enk=10.6 cout=2p Rout=1Meg Vlow=-1e308 Vhigh=1e308 +R3 2 1 2.5Meg noiseless +C1 3 1 2.3p Rser=2k Rpar=2G noiseless +C6 3 2 2.3p Rser=2k Rpar=2G noiseless +C7 1 4 2.3p Rser=2k Rpar=2G noiseless +C8 2 4 2.3p Rser=2k Rpar=2G noiseless +D7 3 4 DP +A1 2 1 0 0 0 0 0 0 OTA g=0 in=300f+350f/(Max(freq,.1)**.5) ink=40 +.model DILIMU D(Ron=.1 Roff=100k Vfwd=25m epsilon=2m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.15 Vrev=-.3 epsilon=100m revepsilon=10m noiseless) +.model DLIMN1 D(Ron=100k Roff=400Meg Vfwd=1.5 Vrev=-310m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=100Meg Roff=1G Vfwd=50m epsilon=100m ilimit=10n noiseless) +.model DP D(Ron=1k vfwd=600m epsilon=600m ilimit=153.5u noiseless) +.model PI VDMOS(Vto=-300m Kp=32m pchan is=0 noiseless) +.model NI VDMOS(Vto=300m kp=19m noiseless) +.model DLIM D(Ron=10 Roff=70Meg Vfwd=300m Vrev=20m epsilon=20m revepsilon=10m noiseless) +.model DBIA1 D(Ron=1k Roff=100G Vfwd=.1 ilimit=64n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1k Roff=100G Vfwd=0 ilimit=22n epsilon=10m noiseless) +.model DBIA3 D(Ron=1k Roff=10G Vfwd=.7 epsilon=.1 noiseless) +.model DBIAOT D(Ron=10k Vfwd=0 ilimit=8.1u epsilon=50m noiseless) +.model DPROT D(Ron=1k Roff=2G Vfwd=1 epsilon=10m noiseless) +.ends LT1638 +* +.subckt LT1671 1 2 3 4 5 6 7 8 +A1 5 6 0 0 0 0 N015 0 SCHMITT Vt=1.5 Vh=0 trise=78n tfall=.1n +B1 0 N002 I=10u*dnlim(uplim(V(2),V(1)-1.3,.1), V(4)-.5,.1)+1n*V(2) +B2 N002 0 I=10u*dnlim(uplim(V(3),V(1)-1.29,.1), V(4)-.51, .1)+1n*V(3) +C1 N002 0 1f Rpar=100K noiseless +A2 0 N002 0 0 0 0 N007 0 OTA isource=75u isink=-62u g=11m asym Vlow=-1e308 Vhigh=1e308 Cout=7.4p +C2 1 7 2.5p +C3 7 6 2.5p +G1 0 N004 N007 0 120n +D1 0 N007 DLAT +G2 0 XN0 0 N007 120n +A3 N010 0 N015 0 0 0 N007 0 OTA g=300u linear Vlow=-1e308 Vhigh=1e308 +D2 0 N010 DLAT +C4 N010 0 100f +G3 0 N010 0 N007 500µ +C5 3 4 1.1p +C6 2 4 1.1p +D3 1 4 DP1 +D4 1 6 DP2 +M1 1 N003 7 7 N temp=27 +M2 6 N008 7 7 P temp=27 +R1 N003 N004 4G +D5 N003 6 DVLU1 +R2 N008 N004 4G +D6 6 N008 DVLD +C7 N004 0 .022f +C8 1 3 1.1p +C9 1 2 1.1p +D8 3 4 DBIAS +D9 2 4 DBIAS +D10 1 5 DLATCH +D11 N004 1 DSIU temp=27 +D12 6 N004 DSID temp=27 +R3 1 N004 979.5Meg +R4 N004 6 637Meg +D13 N003 7 DLIMN2 +D14 N003 6 DVLU2 +D21 N003 7 DLIMN1 +D22 7 N008 DLIMP +C10 1 8 2.5p +C11 8 6 2.5p +M3 1 N011 8 8 N temp=27 +M4 6 N016 8 8 P temp=27 +R5 N011 XN0 4G +D15 N011 6 DVLU1 +R6 N016 XN0 4G +D16 6 N016 DVLD +C12 XN0 0 .022f +R7 1 XN0 979.5Meg +R8 XN0 6 637Meg +D19 N011 8 DLIMN2 +D20 N011 6 DVLU2 +D23 N011 8 DLIMN1 +D24 8 N016 DLIMP +D17 XN0 1 DSIU temp=27 +D18 6 XN0 DSID temp=27 +.model DBIAS D(Ron=1k Roff=10G Vfwd=.5 epsilon=.1 ilimit=120n) +.model DLATCH D(Ron=1k Roff=10Meg Vfwd=1 epsilon=.1 ilimit=2.5u) +.model DP1 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=368u) +.model DP2 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=75u) +.model DVLU1 D(Ron= 5Meg Roff=500G Vfwd=4.0 epsilon=.1) +.model DVLU2 D(Ron=1.2G Roff=500G Vfwd=2.5 epsilon=.1) +.model DVLD D(Ron= 5Meg Roff=100G Vfwd=-500m epsilon=.1) +.model DLAT D(Ron=1 Roff=10k Vfwd=600m Vrev=600m epsilon=5m revepsilon=5m) +.model DSIU D(Is=1.0e-30 N=2 TT=8.8e-9) +.model DSID D(Is=1.0e-30 N=2 TT=8e-9) +.model DLIMN1 D(Ron=155Meg Roff=10G Vfwd=.2 epsilon=.1) +.model DLIMN2 D(Ron=1k Roff=10G Vfwd=.5 epsilon=.1) +.model DLIMP D(Ron=30Meg Roff=10G Vfwd=2m epsilon=1m ilimit=1.2n) +.model N VDMOS(Vto= -20m kp=150m rds=100Meg) +.model P VDMOS(Vto= 200m Kp=500m rds=10Meg pchan ) +.ends LT1671 +* +.subckt LT1677 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=276f ink=178 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-17.2p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C9 3 2 2.1p Rpar=4G noiseless +C10 N004 0 5f Rpar=100K noiseless +D4 N009 4 DBIA2 +M1 5 VN 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 VN 4 DLIMN1 +M2 5 VP 3 3 PI temp=27 +D8 3 VP DLIMP +C3 3 VP 4p Rser=1Meg noiseless +A3 N007 N008 4 4 4 4 VP 4 OTA g=800n ref=-.02 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C12 VN 4 10f Rser=250k noiseless +D10 N009 1 DBIA1 +D6 VN 4 DLIMN2 +A4 0 N004 0 0 0 0 N005 0 OTA g=10u linear en=3.2n enk=25 Vhigh=1e308 Vlow=-1e308 +C16 N008 5 60p Rser=500 noiseless +A5 N006 0 N007 N007 N007 N007 N008 N007 OTA g=2.64m iout=151u Vhigh=1e308 Vlow=-1e308 +D12 1 3 DBIAOT +D13 2 3 DBIAOT +G1 4 VN N008 N007 30n +C5 3 N009 20p Rpar=1Meg noiseless +C14 VP 5 50f +B3 VP 4 I=25n*V(VP,5)/dnlim(V(3,4),2,.1) +C7 3 1 2.1p Rpar=4G noiseless +C13 3 4 1000p +C15 VP VN 200f Rser=250k noiseless +D7 3 4 DP +D15 1 2 DINP +C6 1 4 2.1p Rpar=4G noiseless +C8 2 4 2.1p Rpar=4G noiseless +S2 0 N005 5 3 LIMU +S3 N005 0 4 5 LIMD +D1 N008 N007 DLIM +D9 N009 2 DBIA1 +L2 N005 0 11.41m Cpar=4.5f Rser=143k Rpar=498k noiseless +C1 N006 0 375p Rpar=1k Rser=212 noiseless +G2 0 N006 N005 0 1m +G3 0 N007 4 0 50m +G4 0 N007 3 0 50m +C4 N007 0 80p Rpar=10 +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=1.085m noiseless) +.model DBIA1 D(Ron=1k Roff=100G Vfwd=.1 ilimit=390n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1k Roff=10G Vfwd=1.3 epsilon=.1 noiseless) +.model DBIAOT D(Ron=10k Vfwd=-.7 ilimit=193n epsilon=50m noiseless) +.model DINP D(Ron=100 Roff=10G Vfwd=1.4 Vrev=1.4 epsilon=100m revepsilon=100m noiseless) +.model LIMU SW(level=2 Ron=1 Roff=2Meg vt=-100m vh=-10m oneway noiseless) +.model LIMD SW(level=2 Ron=1 Roff=2Meg vt=-60m vh=-10m oneway noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01 rs=5) +.model DLIMN1 D(Ron=100k Roff=3g Vfwd=2.1 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=500k Roff=1G Vfwd=1 epsilon=1.2 ilimit=200n noiseless) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0 rs=2) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.6 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7Meg Vfwd=2.3 Vrev=1 epsilon=10m revepsilon=10m noiseless) +.ends LT1677 +* +.subckt LT1719 1 2 3 4 5 6 7 8 +B1 0 N004 I=10u*dnlim(uplim(V(2),V(1)-1.1,.1), V(4)-.2 ,.1)+1n*V(2)+144n*V(VDH) +B2 N004 0 I=10u*dnlim(uplim(V(3),V(1)-1.09,.1), V(4)-.21, .1)+1n*V(3) +C1 N004 0 1f Rpar=100K +D5 0 VDH DLAT +C4 3 4 .2p +C10 2 4 .2p +M3 7 N014 N015 N015 NI temp=27 +M4 7 N009 N008 N008 PI temp=27 +C7 8 7 1p +C8 7 5 1p +D8 8 N008 DILIMU1 +D16 N015 5 DILIMD +C9 8 N008 100f +C14 N015 5 100f +R7 N013 5 2G +D3 N013 5 DSIONN temp=27 +D7 5 N013 DSIOFFN temp=27 +G2 0 N013 0 VDH 90n +C2 7 N014 .06f +D1 N011 8 DSIOFFP temp=27 +D15 8 N011 DSIONP temp=27 +R1 8 N011 2G +C15 N009 7 .08f +A2 VDH 0 0 0 0 0 N013 0 OTA g=60n asym isource=0 isink=-100n Vlow=-1e308 Vhigh=1e308 Cout=.05f +A3 VDH 0 0 0 0 0 N011 0 OTA g=50n asym isource=100n isink=0 Vlow=-1e308 Vhigh=1e308 Cout=.05f +C5 1 3 .2p +C6 1 2 .2p +D2 N006 3 DBIAS +D4 N006 2 DBIAS +G3 0 N011 0 VDH 120n +D9 8 N008 DILIMU2 +A4 N002 0 N011 N011 N011 N011 N009 N011 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=14 Rout=1k Cout=100f +A5 N002 0 N013 N013 N013 N014 N013 N013 SCHMITT Vt=.5 Vh=10m Vhigh=-14 Vlow=0 Rout=1k Cout=100f +A6 8 6 0 0 0 0 N002 0 SCHMITT Vt=1 Vh=0 tau=5n +A7 0 N004 N002 0 0 0 VDH 0 OTA g=10m iout=100u Cout=30f Vlow=-1e308 Vhigh=1e308 +D10 8 6 DSHUT +C3 8 6 100f +S1 5 8 N002 0 SVSP +S2 N006 1 N002 0 SBIAS +S3 4 1 N002 0 SV+P +S4 2 3 N002 0 SBIASC +.model NI VDMOS(Vto=100m kp=100m mtriode= 1 rds=100k) +.model PI VDMOS(Vto=-100m Kp=300m mtriode=1 rds=100k pchan) +.model DSHUT D(Ron=70k Roff=1Meg Vfwd=.6 epsilon=.1 ilimit=100u) +.model SVSP SW(level=2 Ron=50 Roff=100Meg Vt=.5 Vh=-.1 ilimit=3.7m) +.model SV+P SW(level=2 Ron=50 Roff=100Meg Vt=.5 Vh=-.1 ilimit=.9m) +.model SBIAS SW(level=2 Ron=1k Roff=1G Vt=.5 Vh=-.1) +.model SBIASC SW(level=2 Ron=10k Roff=10G Vt=.5 Vh=-.1 ilimit=2.5u) +.model DBIAS D(Ron=1k Roff=10G Vfwd=1 epsilon=.1 ilimit=2.5u) +.model DLAT D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9) +.model DILIMU1 D(Ron=15 Roff=100k Vfwd=180m ilimit=11m epsilon=50m Vrev=-180m revepsilon=50m) +.model DILIMU2 D(Ron=70 Roff=100k Vfwd=.3 epsilon=100m) +.model DILIMD D(Ron=7 Roff=100k Vfwd=170m ilimit=40m epsilon=50m Vrev=-170m revepsilon=50m) +.model DSIONN D(Is=1e-30 N=2 TT=2e-10) +.model DSIOFFN D(Is=1e-10 N=1 TT= 1e-10) +.model DSIONP D(Is=1e-30 N=2 TT=1e-10) +.model DSIOFFP D(Is=1e-10 N=1 TT=1e-9) +.ends LT1719 +* +.subckt LT1720 1 2 3 4 5 +B1 0 N001 I=10u*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)-.2 ,.1)+1n*V(1)+144n*V(VDH) +B2 N001 0 I=10u*dnlim(uplim(V(2),V(3)-1.09,.1), V(4)-.21, .1)+1n*V(2) +C1 N001 0 1f Rpar=100K +A1 0 N001 0 0 0 0 VDH 0 OTA g=10m iout=100u Vlow=-1e308 Vhigh=1e308 Cout=30f +D5 0 VDH DLAT +C4 2 4 .2p +C10 1 4 .2p +D13 3 4 DP +M3 5 N008 N009 N009 NI temp=27 +M4 5 N006 N004 N004 PI temp=27 +C7 3 5 1p +C8 5 4 1p +D8 3 N004 DILIMU1 +D16 N009 4 DILIMD +C9 3 N004 100f +C14 N009 4 100f +R7 N008 4 2G +D3 N008 4 DSIONN temp=27 +D7 4 N008 DSIOFFN temp=27 +G2 0 N008 0 VDH 90n +C2 5 N008 .06f +D1 N006 3 DSIOFFP temp=27 +D15 3 N006 DSIONP temp=27 +R1 3 N006 2G +C15 N006 5 .08f +A2 VDH 0 0 0 0 0 N008 0 OTA g=60n asym isource=0 isink=-100n Vlow=-1e308 Vhigh=1e308 Cout=.05f +A3 VDH 0 0 0 0 0 N006 0 OTA g=50n asym isource=100n isink=0 Vlow=-1e308 Vhigh=1e308 Cout=.05f +C5 3 2 .2p +C6 3 1 .2p +D2 3 2 DBIAS +D4 3 1 DBIAS +D6 1 2 DBIASC +G3 0 N006 0 VDH 120n +D9 3 N004 DILIMU2 +R2 3 4 2k +.model NI VDMOS(Vto=100m kp=100m mtriode= 1 rds=1Meg) +.model PI VDMOS(Vto=-100m Kp=300m mtriode=1 rds=1Meg pchan) +.model DP D(Ron=100 Roff=1Meg Vfwd=1 ilimit=1.49m epsilon=.1) +.model DBIAS D(Ron=1k Roff=10G Vfwd=1 epsilon=.1 ilimit=2.5u) +.model DBIASC D(Ron=10k Roff=10G Vfwd= 1u Vrev=1u ++ epsilon=10u revepsilon=10u ilimit=2.5u revilimit=2.5u) +.model DLAT D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9) +.model DILIMU1 D(Ron=15 Roff=100k Vfwd=180m ilimit=11m epsilon=50m Vrev=-180m revepsilon=50m) +.model DILIMU2 D(Ron=70 Roff=100k Vfwd=.3 epsilon=100m) +.model DILIMD D(Ron=7 Roff=100k Vfwd=170m ilimit=40m epsilon=50m Vrev=-170m revepsilon=50m) +.model DSIONN D(Is=1e-30 N=2 TT=2e-10) +.model DSIOFFN D(Is=1e-10 N=1 TT= 1e-10) +.model DSIONP D(Is=1e-30 N=2 TT=1e-10) +.model DSIOFFP D(Is=1e-10 N=1 TT=1e-9) +.ends LT1720 +* +.subckt LT1722 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.2p ink=17.8 +C2 2 1 2p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+.89, .1)+1n*V(2) +C9 3 2 1p Rpar=70Meg noiseless +C10 N004 0 .1f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 1p +D5 N005 5 YU +D6 5 N005 YD +R2 3 N006 1G noiseless +R3 N006 4 1G noiseless +C4 5 4 1p +C1 2 4 1p Rpar=70Meg noiseless +C6 3 1 1p Rpar=70Meg noiseless +C7 1 4 1p Rpar=70Meg noiseless +D2 2 4 DBIAS +D4 1 4 DBIAS +A3 0 N007 0 0 0 0 N006 0 OTA g=36u iout=2.1u Cout=28.6f Vlow=-1e308 Vhigh=1e308 +G1 0 N005 N006 0 1e-4 +L1 N005 0 107µ Rser=10.1k Cpar=0.0265f Rpar=1.009999999999999998Meg noiseless +D1 3 4 DP +G2 N006 0 N006 3 100m dir=1 vto=-1.03 +G3 0 N006 4 N006 100m dir=1 vto=-1.03 +A2 0 N004 0 0 0 0 N007 0 OTA g=1u asym isource=.2u isink=-.4u en=3.7n enk=563 Cout=40f Rout=1Meg Vlow=-.15 Vhigh=.15 +D3 2 1 DIN +.model YU D(Ron=100 Roff=1T Vfwd=.9 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.82 epsilon=.1 noiseless) +.model N VDMOS(Vto=-180m Kp=130m) +.model P VDMOS(Vto=180m Kp=130m pchan) +.model DBIAS D(Ron=1Meg Roff=1G Vfwd=.6 ilimit=20n noiseless) +.model DLIM D(Ron=1 Roff=1Meg Vfwd=1.5 Vrev=1.5 epsilon=.1 revepsilon=.1 noiseless) +.model DP D(Ron=1k Roff=100Meg Vfwd=1 ilimit=1.594m noiseless) +.model DIN D(Ron=200 Roff=50k Vfwd=.9 epsilon=.1 noiseless) +.ends LT1722 +* +.subckt LT1782 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=48.8f ink=50.5 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(4)+18.1,.1), V(4)-.1, .1)+1n*V(1)-1.7377n +B2 N005 0 I=10u*dnlim(uplim(V(2),V(4)+18.11,.1), V(4)-.11, .1)+1n*V(2) +C9 3 2 2.5p Rser=2k Rpar=10G noiseless +C10 N005 0 500f Rpar=100K noiseless +D4 3 N010 DBIA3 +M1 5 VN 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D1 3 N008 DILIMU +D5 VN 4 DLIMN1 +M2 5 VP N008 N008 PI temp=27 +D8 3 VP DLIMP +A3 0 X6 3 3 3 3 VP 3 OTA g=800n ref=-345m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C4 3 N008 1p Rpar=1G noiseless +D2 3 2 DBIA2 +D3 3 1 DBIA2 +D10 1 N010 DBIA1 +D11 2 N010 DBIA1 +D6 VN 4 DLIMN2 +A4 0 N005 0 0 0 0 N006 0 OTA g=1u linear en=50n enk=1.26 Vhigh=1e308 Vlow=-1e308 +C16 X5 N009 20p +A5 N007 0 0 0 0 0 X5 0 OTA g=28u iout=1.67u Vhigh=1e308 Vlow=-1e308 +D12 1 3 DBIAOT +D13 2 3 DBIAOT +C5 N010 4 20p Rpar=15Meg noiseless +D9 X5 0 DLIM +C6 2 4 2.5p Rser=2k noiseless +C7 3 1 2.5p Rser=2k Rpar=10G noiseless +C8 1 4 2.5p Rser=2k noiseless +R3 2 1 6.5Meg noiseless +C13 3 4 100p +S1 X5 0 0 N004 SHUT +S2 3 VP 0 N004 SHUT +S3 VN 4 0 N004 SHUT +G3 0 N004 3 4 50n +S4 N004 0 6 4 SHUTI +C20 N006 0 6p noiseless Rpar=2Meg +G7 0 N007 N006 0 1m +L1 N007 0 4m Cpar=1.79p Rser=1.13k Rpar=8.69k noiseless +C21 N004 0 18p +C17 4 6 100f Rpar=1Meg noiseless +D14 4 1 DPROT +D15 4 2 DPROT +G5 0 X6 X5 0 1µ +R4 X6 0 1Meg noiseless +R5 X7 X6 30K noiseless +B4 X7 0 I=100p*ddt(V(X7))*(.5+.5*tanh((-360m-V(VP,3))/5m)) +R6 3 N012 2Meg noiseless +R7 N012 4 2Meg noiseless +G2 0 N009 5 N012 10m +C1 N009 0 100f Rpar=100 noiseless +C3 VP 5 1f +C12 5 VN 1f +A2 0 X6 4 4 4 4 VN 4 OTA g=29n ref=345m linear vlow=-1e308 vhigh=1e308 +D16 N006 0 DLIMIN +G4 0 X6 3 N008 1m vto=80m dir=1 +S5 3 4 N004 0 SP +D7 3 4 DP +.model SP SW(Roff=100Meg Ron=1k vt=.5 vh=-200m ilimit=27.87u noiseless) +.model DP D(Roff=100Meg Ron=1k vfwd=600m epsilon=500m ilimit=2.41u noiseless) +.model DLIMIN D(Ron=1k Roff=2Meg vfwd=80m epsilon=20m vrev=80m revepsilon=20m noiseless) +.model DBIA1 D(Ron=1k Roff=100G Vfwd=.1 ilimit=24n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1k Roff=100G Vfwd=0 ilimit=8n epsilon=10m noiseless) +.model DBIA3 D(Ron=1k Roff=10G Vfwd=.9 epsilon=.1 noiseless) +.model DBIAOT D(Ron=10k Vfwd=0 ilimit=4u epsilon=50m noiseless) +.model DPROT D(Ron=6k Roff=10G Vfwd=1 epsilon=10m noiseless) +.model DILIMU D(Ron=2 Roff=100k Vfwd=39m epsilon=2m noiseless) +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.9 noiseless) +.model SHUTI SW(Ron=100 Roff=20Meg vt=1.2 vh=-10m noiseless) +.model NI VDMOS(Vto=300m kp=15m lambda=.01 rs=2) +.model DLIMN1 D(Ron=200k Roff=400Meg Vfwd=2.45 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=12Meg Roff=1G Vfwd=-40m epsilon=50m ilimit=21.8n noiseless) +.model PI VDMOS(Vto=-300m Kp=15m lambda=.01 pchan is=0) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=3.4 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=1 Vrev=.1 epsilon=10m revepsilon=10m noiseless) +.ends LT1782 +* +.subckt LT1783 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=115f ink=466 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(4)+18.1,.1), V(4)-.1, .1)+1n*V(1)-1.732n +B2 N005 0 I=10u*dnlim(uplim(V(2),V(4)+18.11,.1), V(4)-.11, .1)+1n*V(2) +C10 N005 0 10f Rpar=100K noiseless +D4 3 N010 DBIA3 +D2 3 2 DBIA2 +D3 3 1 DBIA2 +D10 1 N010 DBIA1 +D11 2 N010 DBIA1 +A4 0 N005 0 0 0 0 N006 0 OTA g=1u linear en=20n enk=8 cout=884f Vlow=-1e308 Vhigh=1e308 +D12 1 3 DBIAOT +D13 2 3 DBIAOT +C5 N010 4 20p Rpar=10Meg noiseless +R3 2 1 1.3Meg noiseless +C13 3 4 100p +D7 3 4 DP +G3 0 N004 3 4 50n +S4 N004 0 6 4 SHUTI +G7 0 N007 N006 0 1m +L1 N007 0 535µ Cpar=2.06p Rser=1.18k Rpar=6.56k noiseless +C21 N004 0 6p +C1 4 6 100f Rpar=1Meg noiseless +D14 N006 0 DLIMIN +D15 4 1 DPROT +D16 4 2 DPROT +C6 3 1 2.5p Rser=2k Rpar=10G noiseless +C7 3 2 2.5p Rser=2k Rpar=10G noiseless +C8 1 4 2.5p Rser=2k Rpar=10G noiseless +C9 2 4 2.5p Rser=2k Rpar=10G noiseless +M1 5 VN 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D1 3 N008 DILIMU +D5 VN 4 DLIMN1 +M2 5 VP N008 N008 PI temp=27 +D6 3 VP DLIMP +A2 0 X6 3 3 3 3 VP 3 OTA g=800n ref=-345m linear vlow=-1e308 vhigh=1e308 +C3 5 4 1p Rpar=1g noiseless +C4 3 N008 1p Rpar=1G noiseless +D8 VN 4 DLIMN2 +C11 X5 N009 3.5p +A3 N007 0 0 0 0 0 X5 0 OTA g=28u iout=1.8u Vhigh=1e308 Vlow=-1e308 +D9 X5 0 DLIM +S1 X5 0 0 N004 SHUT +S2 3 VP 0 N004 SHUT +S3 VN 4 0 N004 SHUT +R4 3 N012 8Meg noiseless +R5 N012 4 8Meg noiseless +G1 0 N009 5 N012 10m +C12 N009 0 10f Rpar=100 noiseless +C14 VP 5 .1f +C15 5 VN .1f +A5 0 X6 4 4 4 4 VN 4 OTA g=30n ref=345m linear vlow=-1e308 vhigh=1e308 +G2 0 X6 3 N008 1m vto=90m dir=1 +G4 0 X6 X5 0 1µ +R6 X6 0 1Meg noiseless +R7 X7 X6 40K noiseless +B3 X7 0 I=10p*ddt(V(X7))*(.5+.5*tanh((-400m-V(VP,3))/5m)) +S5 3 4 N004 0 SP2 +S6 3 4 N004 0 SP1 +.model DLIMIN D(Ron=1k Roff=1Meg vfwd=80m epsilon=20m vrev=80m revepsilon=20m noiseless) +.model DBIA1 D(Ron=1k Roff=100G Vfwd=.1 ilimit=130n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1k Roff=100G Vfwd=0 ilimit=30n epsilon=10m noiseless) +.model DBIA3 D(Ron=1k Roff=10G Vfwd=.9 epsilon=.1 noiseless) +.model DBIAOT D(Ron=10k Vfwd=0 ilimit=35u epsilon=50m noiseless) +.model DPROT D(Ron=1k Roff=2G Vfwd=1 epsilon=10m noiseless) +.model SP1 SW(Roff=100Meg Ron=1k vt=.5 vh=-200m ilimit=89.4u noiseless) +.model SP2 SW(Roff=100Meg Ron=300k vt=.5 vh=-200m ilimit=40u noiseless) +.model DP D(Roff=100Meg Ron=1k vfwd=600m epsilon=500m ilimit=4.3u noiseless) +.model DILIMU D(Ron=2 Roff=100k Vfwd=59m epsilon=2m noiseless) +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.9 noiseless) +.model SHUTI SW(Ron=100 Roff=20Meg vt=1.2 vh=-10m noiseless) +.model NI VDMOS(Vto=300m kp=15m lambda=.01 noiseless) +.model PI VDMOS(Vto=-300m Kp=15m lambda=.01 pchan is=0 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=3.6 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=1 Vrev=1 epsilon=10m revepsilon=10m noiseless) +.model DLIMN1 D(Ron=200k Roff=700Meg Vfwd=2.2 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=15Meg Roff=1G Vfwd=-10m epsilon=50m ilimit=25.7n noiseless) +.ends LT1783 +* +.subckt LT1787 1 2 3 4 5 6 7 +R1 7 6 1.25k +R2 VSPP 7 1.25k +R3 1 2 1.25k +R4 VSNP 1 1.25k +C1 1 3 100f +C2 7 3 100f +M1 3 N010 N009 N009 POUT Temp=27 +C3 N004 0 100f Rpar=100K noiseless +B1 N004 0 I=10u*dnlim(uplim(V(VSNP),V(6)+.11,.1), V(6)-.7, .1)+10n*V(VSNP) +B2 0 N004 I=10u*dnlim(uplim(V(VSPP),V(2)+.1,.1), V(6)-.7, .1)+10n*V(VSPP) +D1 2 N001 DLIMP +A1 N005 0 0 0 0 0 N001 0 OTA g=200n ref=-56m linear cout=2f vlow=-1e308 vhigh=1e308 +A2 0 N004 0 0 0 0 N005 0 OTA g=20u asym cout=800p isource=300n isink=-100n Vlow=-1e308 Vhigh=1e308 +D2 N005 0 DLIM +M2 4 N001 N003 N003 POUT Temp=27 +D3 2 N010 DLIMP +A4 0 N005 0 0 0 0 N010 0 OTA g=200n ref=-56m linear cout=2f vlow=-1e308 vhigh=1e308 +D6 2 3 DP +R6 VSPP VSNP 25G +R7 4 5 20k +G1 4 3 0 N011 800µ +S1 N011 0 3 4 SWSAT +G2 0 N011 VSNP 1 1m +D7 VSPP N003 DDROP +D8 VSNP N009 DDROP +C6 VSNP 3 100f +C7 VSPP 3 100f +C8 N009 3 10f +C9 N003 3 10f +C10 3 4 1.5p +D5 0 N011 DSINKL +C4 0 N011 1p +.model DLIM D(Ron=100 Roff=7Meg Vfwd=20m Vrev=40m epsilon=10m revepsilon=10m) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=3 Vrev=-.6 epsilon=10m revepsilon=10m) +.model DDROP D(Ron=10 Roff=100k Vfwd=.7 epsilon=50m) +.model POUT VDMOS(Vto=-300m Kp=30m mtriode=.1 rs=10 cgs=20f rds=1g is=0 pchan) +.model DBIAS D(Ron=100k Roff=1G Vfwd=.5 epsilon=.1 ilimit=2u) +.model DP D(Ron=10k Roff=1G Vfwd=0.5 epsilon=.1 ilimit=19u) +.model DSINKL D(Ron=100 Roff=1G Vfwd=430m Vrev=50m epsilon=50m revepsilon=10m) +.model SWSAT SW(Ron=10 Roff=1K vt=-25m vh=-15m ) +.ends LT1787 +* +.subckt LT1792 1 2 3 4 5 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)+3.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)+3.8, .1)+1n*V(2) +C6 3 1 7p Rpar=200g noiseless +C7 1 4 7p noiseless Rpar=200g +C8 2 4 7p Rpar=200g noiseless +C9 3 2 7p Rpar=200g noiseless +A2 0 N004 0 0 0 0 N008 0 OTA g=90u Iout=7.2u en=4.1n enk=30 Vlow=-1e308 Vhigh=1e308 Cout= 2.1p +C10 N004 0 20f Rpar=100K noiseless +D4 N008 3 XU +D5 4 N008 XD +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +G2 0 N007 N006 0 1m +L4 N007 0 88.9µ Cpar=685f Rser=1.23k Rpar=5.347826086956521739k noiseless +C2 N005 0 347f Rpar=1Meg noiseless +G1 0 N005 N007 0 1µ +G3 0 N006 N008 0 1m +L1 N006 0 103.1µ Cpar=1.89p Rser=1.42k Rpar=3.3809523809523809525k noiseless +A3 2 1 0 0 0 0 0 0 OTA g=0 in=1f incm=1e-17*freq/(1+1e-12*freq**2) +.model XU D(Ron=1K Roff=100G Vfwd=-1.0 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-1.2 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=.9 epsilon=.1 noiseless) +.model N VDMOS(Vto=-200m Kp=43m) +.model P VDMOS(Vto=200m Kp=43m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=3.339m noiseless) +.ends LT1792 +* +.subckt LT1793 1 2 3 4 5 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.7,.1), V(4)+3.15, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.69,.1), V(4)+3.14, .1)+1n*V(2) +C6 3 1 750f Rpar=200t noiseless +C7 1 4 750f noiseless Rpar=200t +C8 2 4 750f Rpar=200t noiseless +C9 3 2 750f Rpar=200t noiseless +A2 0 N004 0 0 0 0 N008 0 OTA g=94u Iout=10.3u en=5.9n enk=28 Vlow=-1e308 Vhigh=1e308 Cout= 3p +C10 N004 0 30f Rpar=100K noiseless +D4 N008 3 XU +D5 4 N008 XD +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +G2 0 N007 N006 0 1m +L4 N007 0 88.9µ Cpar=685f Rser=1.23k Rpar=5.347826086956521739k noiseless +C2 N005 0 347f Rpar=1Meg noiseless +G1 0 N005 N007 0 1µ +G3 0 N006 N008 0 1m +L1 N006 0 103.1µ Cpar=1.89p Rser=1.42k Rpar=3.3809523809523809525k noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1f incm=3.5e-18*freq/(1+1e-12*freq**2) +.model XU D(Ron=1K Roff=100G Vfwd=-1.0 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-1.2 epsilon=.1 noiseless) +.model Y D(Ron=500 Roff=1T Vfwd=.9 epsilon=.1 noiseless) +.model N VDMOS(Vto=-200m Kp=43m) +.model P VDMOS(Vto=200m Kp=43m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=3.339m noiseless) +.ends LT1793 +* +.subckt LT1795 1 2 3 4 5 6 7 8 +Q1 N006 N005 2 0 N temp=27 +Q2 N022 N020 2 0 P temp=27 +M1 3 N007 N013 N013 N temp=27 +M2 4 N007 N021 N021 P temp=27 +R19 3 N006 120 noiseless +R20 N022 4 120 noiseless +G5 0 N011 N006 3 12µ +G6 N011 0 4 N022 12µ +C2 3 2 1p +C6 3 1 1p +C7 2 4 1p +C8 1 4 1p +A2 0 0 1 1 1 1 N016 1 OTA G=.1 Rout=10 Vhigh=100 Vlow=-100 en=3.6n Linear enk=30 +A3 0 1 0 0 0 0 0 0 OTA in=2p ink=100 +A4 0 2 0 0 0 0 0 0 OTA in=30p ink=30 +A5 N008 0 0 0 0 0 N018 0 OTA G=555u Iout=10u Vlow=-1e308 Vhigh=1e308 +C3 0 N011 1p Rpar=1K noiseless +C9 N009 N008 45f Rser=50K Cpar=15f noiseless +G1 0 N008 N011 0 9m +R1 N008 0 50 noiseless +G2 0 N009 N018 0 20m +R5 N009 0 50 noiseless +G3 0 N012 N017 0 2µ +C1 N012 0 4.5f noiseless Rpar=500k +D6 N009 N017 S +C11 N017 0 5.9p +R7 8 N009 25 noiseless +C15 3 8 1p +C16 8 4 1p +D8 7A 6 DSHDN +D9 4 6 DSUB +G4 7 4 7 7A .1 +G7 0 N007 N012 0 .2m +C5 N007 0 10f Rpar=5k noiseless +S2 N005 N016 7 6 SHD2 +S3 N016 N020 7 6 SHD2 +S5 4 N005 6 7 SHD3 +S6 N020 3 6 7 SHD3 +G10 N018 0 N018 3 500m dir=1 vto=-1.3 +G11 0 N018 4 N018 500m dir=1 vto=-1.3 +R2 3 N018 1G noiseless +R3 N018 4 1G noiseless +A1 7A 7 3 3 3 3 N005 3 OTA g=6m iout=90u Vlow=-100 Vhigh=-.3 ref=17m +S1 N017 N009 N014 0 SS +C4 5 N007 1.2p +R10 7A 7 10 +D1 7A 6 DSHDN1 +D2 N012 N013 Y +S4 5 N021 N014 0 SRO +S7 N013 5 N014 0 SRO +C17 N013 5 2p +C18 5 N021 2p +D3 N021 N012 Y +A7 7A 7 3 3 3 3 4 3 OTA g=9 iout=13m ref=-16.5u vlow=-50 vhigh=50 +G8 0 N014 7 7A .1 +C13 N014 0 1p Rpar=10k noiseless +A6 7A 7 N020 N020 N020 N020 4 N020 OTA g=6m iout=90u Vlow=-100 Vhigh=-.3 ref=17m +G12 N014 0 6 7 5m vto=-.6 dir=1 +C10 7A 6 10f +C14 7 6 100f +.model N NPN(Cje=.25p Cjc=.25p BF=180 noiseless) +.model P PNP(Cje=.25p Cjc=.25p BF=180 noiseless) +.model N VDMOS(Vto=-.2 Kp=1.2) +.model P VDMOS(Vto=.2 Kp=1.2 pchan) +.model Y D(Ron=1K Roff=1G epsilon=100m Vfwd=1.05 noiseless) +.model S D(Ron=200 Roff=200 Ilimit=2.7m RevIlimit=5.4m Vrev=0 noiseless) +.model SS SW(level=2 Ron=200 Roff=2Meg vt=100m vh=-3 ilimit=2.7m noiseless) +.model DSUB D(Ron=10 Roff=1G vfwd=.6 epsilon=.1 noiseless) +.model DSHDN1 D(Ron=100k Roff=1G vfwd=1.5 epsilon=200m noiseless) +.model DSHDN D(Ron=1.8k Roff=1G vfwd=1.15 epsilon=.25 ilimit=.26m noiseless) +.model SHD2 SW(Ron=10k Roff=1G vt=1 vh=-.2 noiseless) +.model SRO SW(Ron=.1 Roff=200k vt=-900m vh=-12 noiseless) +.model SHD3 SW(Ron=10 Roff=1G vt=-1 vh=-.2 noiseless) +.model SGM SW(Ron=1Meg Roff=1g vt=-1.4 vh=-1 noiseless) +.ends LT1795 +* +.subckt LT1797 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=228f ink=182 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-5n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 10f Rpar=100K noiseless +D4 3 N012 DBIA3 +M1 5 N013 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D1 3 N005 DVLIMU +D5 N013 4 DLIMN1 +M2 5 N008 N005 N005 PI temp=27 +D8 3 N008 DLIMP1 +C3 3 N008 .3f Rser=10Meg noiseless +A3 N009 N010 4 4 4 4 N008 4 OTA g=80n ref=-.0375 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C12 N013 4 .1f Rser=1Meg noiseless +C4 3 N005 1p Rpar=1g noiseless +D10 1 N012 DBIA1 +D11 2 N012 DBIA1 +D6 N013 4 DLIMN2 +A4 0 N004 0 0 0 0 N006 0 OTA g=1u linear en=19.9n enk=121 Vhigh=1e308 Vlow=-1e308 +C16 N010 5 700f +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=40u iout=1.75u Rout=800k Vhigh=1e308 Vlow=-1e308 +D12 1 3 DBIAOT +D13 2 3 DBIAOT +G1 4 N013 N010 N009 20n +C5 N012 4 20p Rpar=15.7k noiseless +C7 3 1 2p Rser=2k Rpar=200Meg noiseless +C13 3 4 1000p +C15 N008 N013 1f Rser=1Meg noiseless +D7 3 4 DP +C17 0 N006 170f Rpar=1Meg noiseless +G4 0 N007 N006 0 1m +C14 N008 5 .2f +D14 3 N008 DLIMP2 +L1 N007 0 122µ Cpar=477f Rser=1.15k Rpar=7.67k noiseless +C1 3 2 2p Rser=2k Rpar=200Meg noiseless +C6 1 4 2p Rser=2k noiseless +C8 2 4 2p Rser=2k noiseless +D15 1 2 DIN +D16 N012 1 DBIA2 +D3 N012 2 DBIA2 +G2 0 N009 4 0 .5m +G3 0 N009 3 0 .5m +C9 N009 0 1p Rpar=1k +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=.1m noiseless) +.model DBIA1 D(Ron=1k Roff=200Meg Vfwd=0 ilimit=50n epsilon=.2 noiseless) +.model DBIA2 D(Ron=1k Roff=10T Vfwd=-.1 epsilon=.2 ilimit=104n noiseless) +.model DBIA3 D(Ron=1k Roff=100G Vfwd=.4 epsilon=10m noiseless) +.model DBIAOT D(Ron=20k Roff=100T Vfwd=1 epsilon=50m noiseless) +.model DVLIMU D(Ron=10 Roff=1Meg Vfwd=45m epsilon=2m noiseless) +.model NI VDMOS(Vto=300m kp=100m lambda=.01) +.model DLIMN1 D(Ron=100 Roff=10g Vfwd=1.2 Vrev=-340m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=800Meg Roff=10g Vfwd=-10m epsilon=100m ilimit=300p noiseless) +.model PI VDMOS(Vto=-300m Kp=100m lambda=.01 pchan is=0) +.model DLIMP1 D(Ron=100k Roff=1G Vfwd=2 Vrev=-340m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=180Meg Roff=2g Vfwd=120m epsilon=100m ilimit=1.5n noiseless) +.model DIN D(Ron=20k Roff=330k Vfwd=1 Vrev=1 epsilon=100m revepsilon=100m noiseless) +.ends LT1797 +* +.subckt LT1800 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=998f ink=47.8 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-240p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 7f Rpar=100K noiseless +D4 3 N011 DBIA3 +M1 5 N012 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 N012 4 DLIMN1 +M2 5 N007 3 3 PI temp=27 +D8 3 N007 DLIMP1 +C3 3 N007 .12f Rser=40Meg noiseless +A3 N008 N009 4 4 4 4 N007 4 OTA g=80n ref=-.015 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C12 N012 4 .02f Rser=1Meg noiseless +D10 1 N011 DBIA1 +D11 2 N011 DBIA1 +D6 N012 4 DLIMN2 +A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear en=8.3n enk=514 Vhigh=1e308 Vlow=-1e308 +C16 N009 5 600f +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=300u iout=15.1u Rout=800k Vhigh=1e308 Vlow=-1e308 +D12 1 3 DESD +D13 2 3 DESD +G1 4 N012 N009 N008 20n +C5 N011 4 20p Rpar=25k noiseless +C7 3 1 1p Rpar=10g noiseless +C13 3 4 1000p +C15 N007 N012 .1f Rser=10Meg noiseless +D7 3 4 DP +C17 0 N005 37f Rpar=1Meg noiseless +G4 0 N006 N005 0 1m +D14 3 N007 DLIMP2 +L1 N006 0 18.3µ Cpar=70.7f Rser=1.15k Rpar=7.67k noiseless +D15 1 2 DIN +D16 N011 1 DBIA2 +D3 N011 2 DBIA2 +C4 N007 5 .01f +D1 4 2 DESD +D2 4 2 DESD +C1 3 2 1p Rpar=10g noiseless +C6 1 4 1p Rpar=10g noiseless +C8 2 4 1p Rpar=10g noiseless +G2 0 N008 4 0 5m +G3 0 N008 3 0 5m +C9 N008 0 10p Rpar=100 +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=180u noiseless) +.model DBIA1 D(Ron=1k Roff=10G Vfwd=0 ilimit=500n epsilon=.2 noiseless) +.model DBIA2 D(Ron=1k Roff=10T Vfwd=-.1 epsilon=.2 ilimit=25n noiseless) +.model DBIA3 D(Ron=100 Roff=100G Vfwd=1.1 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model DVLIMU D(Ron=10 Roff=1Meg Vfwd=45m epsilon=2m noiseless) +.model NI VDMOS(Vto=300m kp=100m lambda=.01) +.model DLIMN1 D(Ron=100 Roff=10g Vfwd=1.25 Vrev=-340m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=100Meg Roff=10g Vfwd=400m epsilon=700m noiseless) +.model PI VDMOS(Vto=-300m kp=100m lambda=.01 pchan is=0) +.model DLIMP1 D(Ron=100 Roff=1G Vfwd=1.14 Vrev=-340m epsilon=600m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=40Meg Roff=2g Vfwd=400m epsilon=500m noiseless) +.model DIN D(Ron=2k Roff=100g Vfwd=1.5 Vrev=1.5 epsilon=100m revepsilon=100m noiseless) +.ends LT1800 +* +.subckt LT1806 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.48p ink=455 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-517p +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N005 0 1f Rpar=100K noiseless +D4 3 N012 DBIA3 +M1 5 N013 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 N013 4 DLIMN1 +M2 5 N006 3 3 PI temp=27 +D8 3 N006 DLIMP1 +C3 3 N006 .12f Rpar=100G Rser=20Meg noiseless +C11 5 4 1p Rpar=1g noiseless +C12 N013 4 .02f Rser=1Meg noiseless Rpar=100G +D6 N013 4 DLIMN2 +A4 0 N005 0 0 0 0 N008 0 OTA g=1u linear en=3.49n enk=72.2 Vhigh=.2 Vlow=-.2 +C16 N010 5 1.4p +D12 1 3 DESD +D13 2 3 DESD +C7 3 1 1p Rpar=10g noiseless +C13 3 4 1000p +C15 N006 N013 .01f Rser=10Meg noiseless +D7 3 N004 DPB +C17 0 N008 20f Rpar=1Meg noiseless +G4 0 N009 N008 0 1m +D14 3 N006 DLIMP2 +L1 N009 0 6.93µ Cpar=11.05f Rser=1.09k Rpar=12.11k noiseless +D15 1 2 DIN +D16 N012 1 DBIA2 +D3 N012 2 DBIA2 +C4 N006 5 .02f +D1 4 2 DESD +D2 4 1 DESD +C1 3 2 1p Rpar=10g noiseless +C6 1 4 1p Rpar=10g noiseless +C8 2 4 1p Rpar=10g noiseless +C14 N007 N010 10f Rpar=80k noiseless +D9 3 6 DSHUT +G2 4 N013 N010 N007 20n +A10 3 6 N007 N007 N007 N014 N007 N007 SCHMITT Vt=2 Vh=10m tau=20n +A2 N009 0 N014 N007 N007 N007 N010 N007 OTA g=3m iout=203u Vhigh=1e308 Vlow=-1e308 +A3 N007 N010 N014 N007 N007 N007 N006 N007 OTA g=80n ref=-.03 linear Vlow=-1e308 Vhigh=1e308 +S1 4 N012 N007 N014 SWB +D17 2 N004 DBIA1 +D11 1 N004 DBIA1 +S2 N004 4 N014 N007 SWB2 +C18 N012 4 20p Rpar=50G noiseless +C5 3 N004 20p Rpar=20G noiseless +C19 N004 4 20p Rpar=20G noiseless +S3 3 4 N014 N007 SWP +C21 N007 0 100p Rpar=10 +G5 0 N007 4 0 50m +G6 0 N007 3 0 50m +.model DPB D(Roff=1G Ron=100 Vfwd=1.1 noiseless) +.model SWP SW(Roff=1G Ron=3.3k vt=.5 vh=-.1) +.model SWB SW(Ron=1 Roff=5G vt=-.5 vh=-.1) +.model SWB2 SW(level=2 Ron=100 Roff=500g vt=.5 vh=-.1 ilimit=4.58m) +.model DBIA1 D(Ron=100k Roff=50Meg Vfwd=0 ilimit=1u epsilon=.1 noiseless) +.model DBIA2 D(Ron=50k Roff=10T Vfwd=0 epsilon=.1 ilimit=4.9u noiseless) +.model DBIA3 D(Ron=50k Roff=100G Vfwd=1.1 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model DVLIMU D(Ron=10 Roff=1Meg Vfwd=45m epsilon=2m noiseless) +.model NI VDMOS(Vto=300m kp=250m lambda=.01) +.model DLIMN1 D(Ron=100 Roff=5g Vfwd=.85 Vrev=-340m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=500Meg Roff=10g Vfwd=200m epsilon=700m noiseless) +.model PI VDMOS(Vto=-300m kp=250m lambda=.01 pchan is=0) +.model DLIMP1 D(Ron=100 Roff=500Meg Vfwd=.86 Vrev=-340m epsilon=600m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=80Meg Roff=2g Vfwd=300m epsilon=500m noiseless) +.model DIN D(Ron=2k Roff=100g Vfwd=1.5 Vrev=1.5 epsilon=100m revepsilon=100m noiseless) +.model DSHUT D(Ron=36k Roff=1g Vfwd=.5 epsilon=100m noiseless) +.ends LT1806 +* +.subckt LT1807 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.48p ink=455 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-517p +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N005 0 1f Rpar=100K noiseless +D4 3 N012 DBIA3 +M1 5 N013 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 N013 4 DLIMN1 +M2 5 N009 3 3 PI temp=27 +D8 3 N009 DLIMP1 +C3 3 N009 .12f Rpar=100G Rser=20Meg noiseless +C11 5 4 1p Rpar=1g noiseless +C12 N013 4 .02f Rser=1Meg noiseless Rpar=100G +D6 N013 4 DLIMN2 +A4 0 N005 0 0 0 0 N006 0 OTA g=1u linear en=3.49n enk=72.2 Vhigh=.2 Vlow=-.2 +C16 N008 5 1.4p +D12 1 3 DESD +D13 2 3 DESD +C7 3 1 1p Rpar=10g noiseless +C13 3 4 1000p +C15 N009 N013 .01f Rser=10Meg noiseless +D7 3 N004 DPB +C17 0 N006 20f Rpar=1Meg noiseless +G4 0 N007 N006 0 1m +D14 3 N009 DLIMP2 +L1 N007 0 6.93µ Cpar=11.05f Rser=1.09k Rpar=12.11k noiseless +D15 1 2 DIN +D16 N012 1 DBIA2 +D3 N012 2 DBIA2 +C4 N009 5 .02f +D1 4 2 DESD +D2 4 1 DESD +C1 3 2 1p Rpar=10g noiseless +C6 1 4 1p Rpar=10g noiseless +C8 2 4 1p Rpar=10g noiseless +C14 N010 N008 10f Rpar=80k noiseless +G2 4 N013 N008 N010 20n +D17 2 N004 DBIA1 +D11 1 N004 DBIA1 +C18 N012 4 20p Rpar=50G noiseless +C5 3 N004 20p Rpar=20G noiseless +C19 N004 4 20p Rpar=20G noiseless +R3 3 4 3.3k noiseless +D10 N004 4 DP +A5 N007 0 N010 N010 N010 N010 N008 N010 OTA g=3m iout=203u Vhigh=1e308 Vlow=-1e308 +A2 N010 N008 0 0 0 0 N009 0 OTA g=80n ref=-.03 linear Vhigh=1e308 Vlow=-1e308 +G1 0 N010 4 0 50m +G3 0 N010 3 0 50m +C20 N010 0 100p Rpar=10 +.model DPB D(Roff=1G Ron=100 Vfwd=1.1 noiseless) +.model DP D(Roff=500G Ron=100 vfwd=0 ilimit=4.58m noiseless) +.model DBIA1 D(Ron=100k Roff=50Meg Vfwd=0 ilimit=1u epsilon=.1 noiseless) +.model DBIA2 D(Ron=50k Roff=10T Vfwd=0 epsilon=.1 ilimit=4.9u noiseless) +.model DBIA3 D(Ron=50k Roff=100G Vfwd=1.1 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model DVLIMU D(Ron=10 Roff=1Meg Vfwd=45m epsilon=2m noiseless) +.model NI VDMOS(Vto=300m kp=250m lambda=.01) +.model DLIMN1 D(Ron=100 Roff=5g Vfwd=.85 Vrev=-340m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=500Meg Roff=10g Vfwd=200m epsilon=700m noiseless) +.model PI VDMOS(Vto=-300m kp=250m lambda=.01 pchan is=0) +.model DLIMP1 D(Ron=100 Roff=500Meg Vfwd=.86 Vrev=-340m epsilon=600m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=80Meg Roff=2g Vfwd=300m epsilon=500m noiseless) +.model DIN D(Ron=2k Roff=100g Vfwd=1.5 Vrev=1.5 epsilon=100m revepsilon=100m noiseless) +.ends LT1807 +* +.subckt LT1809 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=4.7p ink=1.11k +B1 0 N006 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-1.867n +B2 N006 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N006 0 .01f Rpar=100K noiseless +D4 3 N012 DBIA3 +M1 5 N013 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 N013 4 DLIMN1 +M2 5 N005 3 3 PI temp=27 +D8 3 N005 DLIMP1 +C3 3 N005 .12f Rpar=100G Rser=20Meg noiseless +C11 5 4 1p Rpar=1g noiseless +C12 N013 4 .02f Rser=1Meg noiseless Rpar=100G +D6 N013 4 DLIMN2 +A4 0 N006 0 0 0 0 N008 0 OTA g=1m linear en=14.5n enk=2.24k Vhigh=.56 Vlow=-.56 +C16 N010 5 .7p +D12 1 3 DESD +D13 2 3 DESD +C7 3 1 1p Rpar=10g noiseless +C13 3 4 1000p +C15 N005 N013 .01f Rser=10Meg noiseless +D7 3 N004 DPB +C17 0 N008 600f Rpar=1k noiseless +D14 3 N005 DLIMP2 +D15 1 2 DIN +D16 N012 1 DBIA2 +D3 N012 2 DBIA2 +C4 N005 5 .02f +D1 4 2 DESD +D2 4 1 DESD +C1 3 2 1p Rpar=10g noiseless +C6 1 4 1p Rpar=10g noiseless +C8 2 4 1p Rpar=10g noiseless +C14 N007 N010 10f Rpar=80k noiseless +D9 3 6 DSHUT +G2 4 N013 N010 N007 20n +A10 3 6 N007 N007 N007 N014 N007 N007 SCHMITT Vt=2 Vh=10m td=40n trise=80n tfall=80n +A2 N009 0 N014 N007 N007 N007 N010 N007 OTA g=760u iout=275u Vhigh=1e308 Vlow=-1e308 +A3 N007 N010 N014 N007 N007 N007 N005 N007 OTA g=80n ref=-.03 linear Vlow=-1e308 Vhigh=1e308 +S1 4 N012 N007 N014 SWB +D17 2 N004 DBIA1 +D11 1 N004 DBIA1 +S2 N004 4 N014 N007 SWB2 +C18 N012 4 20p Rpar=50G noiseless +C5 3 N004 20p Rpar=20G noiseless +C19 N004 4 20p Rpar=20G noiseless +S3 3 4 N014 N007 SWP +C22 N009 0 1.33p Rser=2k Rpar=1k noiseless +G4 0 N009 N008 0 1m +G7 0 N007 4 0 50m +G8 0 N007 3 0 50m +C20 N007 0 100p Rpar=10 +.model DPB D(Roff=1G Ron=80 Vfwd=1.1 noiseless) +.model SWP SW(Roff=1G Ron=10k vt=.5 vh=-.1) +.model SWB SW(Ron=1 Roff=5G vt=-.5 vh=-.1) +.model SWB2 SW(level=2 Ron=80 Roff=500g vt=.5 vh=-.1 ilimit=9.83m) +.model DBIA1 D(Ron=100k Roff=10Meg Vfwd=0 ilimit=1.8u epsilon=.1 noiseless) +.model DBIA2 D(Ron=20k Roff=10T Vfwd=0 epsilon=50m ilimit=7u noiseless) +.model DBIA3 D(Ron=10k Roff=100G Vfwd=1.1 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model DVLIMU D(Ron=10 Roff=1Meg Vfwd=45m epsilon=2m noiseless) +.model NI VDMOS(Vto=300m kp=350m lambda=.01) +.model DLIMN1 D(Ron=100 Roff=5g Vfwd=.85 Vrev=-340m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=500Meg Roff=10g Vfwd=200m epsilon=700m noiseless) +.model PI VDMOS(Vto=-300m kp=300m lambda=.01 pchan) +.model DLIMP1 D(Ron=100 Roff=500Meg Vfwd=.835 Vrev=-340m epsilon=600m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=80Meg Roff=2g Vfwd=300m epsilon=500m noiseless) +.model DIN D(Ron=2k Roff=100g Vfwd=1.5 Vrev=1.5 epsilon=100m revepsilon=100m noiseless) +.model DSHUT D(Ron=11.2k Roff=1g Vfwd=.5 epsilon=100m noiseless) +.ends LT1809 +* +.subckt LT1810 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=4.7p ink=1.11k +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-1.867n +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N005 0 .01f Rpar=100K noiseless +D4 3 N012 DBIA3 +M1 5 N013 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 N013 4 DLIMN1 +M2 5 N008 3 3 PI temp=27 +D8 3 N008 DLIMP1 +C3 3 N008 .12f Rpar=100G Rser=20Meg noiseless +C11 5 4 1p Rpar=1g noiseless +C12 N013 4 .02f Rser=1Meg noiseless Rpar=100G +D6 N013 4 DLIMN2 +A4 0 N005 0 0 0 0 N006 0 OTA g=1m linear en=14.5n enk=2.24k Vhigh=.56 Vlow=-.56 +C16 N010 5 .7p +D12 1 3 DESD +D13 2 3 DESD +C7 3 1 1p Rpar=10g noiseless +C13 3 4 1000p +C15 N008 N013 .01f Rser=10Meg noiseless +D7 3 N004 DPB +C17 0 N006 600f Rpar=1k noiseless +D14 3 N008 DLIMP2 +D15 1 2 DIN +D16 N012 1 DBIA2 +D3 N012 2 DBIA2 +C4 N008 5 .02f +D1 4 2 DESD +D2 4 1 DESD +C1 3 2 1p Rpar=10g noiseless +C6 1 4 1p Rpar=10g noiseless +C8 2 4 1p Rpar=10g noiseless +C14 N009 N010 10f Rpar=80k noiseless +G2 4 N013 N010 N009 20n +D17 2 N004 DBIA1 +D11 1 N004 DBIA1 +C18 N012 4 20p Rpar=50G noiseless +C5 3 N004 20p Rpar=20G noiseless +C19 N004 4 20p Rpar=20G noiseless +C22 N007 0 1.33p Rser=2k Rpar=1k noiseless +G4 0 N007 N006 0 1m +D10 N004 4 DP +R3 3 4 10k noiseless +A6 N009 N010 0 0 0 0 N008 0 OTA g=80n ref=-.03 linear Vlow=-1e308 Vhigh=1e308 +A3 N007 0 N009 N009 N009 N009 N010 N009 OTA g=760u iout=275u Vlow=-1e308 Vhigh=1e308 +G1 0 N009 4 0 50m +G3 0 N009 3 0 50m +C20 N009 0 100p Rpar=10 +.model DPB D(Roff=1G Ron=80 Vfwd=1.1 noiseless) +.model DP D(Ron=80 Roff=500G Vfwd=0 ilimit=9.7m noiseless) +.model DBIA1 D(Ron=100k Roff=10Meg Vfwd=0 ilimit=1.8u epsilon=.1 noiseless) +.model DBIA2 D(Ron=20k Roff=10T Vfwd=0 epsilon=50m ilimit=7u noiseless) +.model DBIA3 D(Ron=10k Roff=100G Vfwd=1.1 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model DVLIMU D(Ron=10 Roff=1Meg Vfwd=45m epsilon=2m noiseless) +.model NI VDMOS(Vto=300m kp=350m lambda=.01) +.model DLIMN1 D(Ron=100 Roff=5g Vfwd=.85 Vrev=-340m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=500Meg Roff=10g Vfwd=200m epsilon=700m noiseless) +.model PI VDMOS(Vto=-300m kp=300m lambda=.01 pchan) +.model DLIMP1 D(Ron=100 Roff=500Meg Vfwd=.835 Vrev=-340m epsilon=600m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=80Meg Roff=2g Vfwd=300m epsilon=500m noiseless) +.model DIN D(Ron=2k Roff=100g Vfwd=1.5 Vrev=1.5 epsilon=100m revepsilon=100m noiseless) +.ends LT1810 +* +.subckt LT1812 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.99p ink=246 +C2 2 1 .1p Rpar=1.6Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.7,.1), V(4)+.7, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.69,.1), V(4)+.69, .1)+1n*V(2) +C9 3 2 1p Rpar=20Meg noiseless +C10 N004 0 6f Rpar=100K noiseless +C13 N006 5 3.2p Rser=800 noiseless +C1 2 4 1p Rpar=20Meg noiseless +C6 3 1 1p Rpar=20Meg noiseless +C7 1 4 1p Rpar=20Meg noiseless +D2 3 1 DBIAS +D4 3 2 DBIAS +A2 3 6 0 0 0 N008 0 0 SCHMITT Vt=2 Vh=10m tau=200n Vlow=0 Vhigh=1 +D8 3 6 DSHUT +C11 N010 0 6.4f Rser=77.8k Rpar=100k noiseless +G2 0 N010 N005 0 10µ +A3 0 N004 N008 0 0 0 N005 0 OTA g=1m linear Rout=2k Cout=400f en=7.95n enk=133 Vlow=-1e308 Vhigh=1e308 +D5 N005 0 DNLSlew +D6 N011 0 DNLSlew2 +S3 N005 N011 4 3 SLWMOD +C14 N005 N011 1p +G5 4 N006 N010 0 900µ +M1 3 N007 N009 N009 N temp=27 +M2 4 N013 N009 N009 P temp=27 +C4 3 N009 1p noiseless +C5 N009 4 1p noiseless +S1 5 N009 N008 0 swZombie +C15 3 5 1p noiseless +C16 5 4 1p noiseless +C19 3 N006 .66p Rpar=6Meg noiseless +G6 N010 0 N006 3 1m dir=1 vto=-.95 +G3 4 N010 4 N006 1m dir=1 vto=-.95 +C8 N006 4 .66p Rpar=6Meg noiseless +D1 N007 N009 YF1 +D3 N009 N013 YR1 +R2 N007 N006 1Meg noiseless +C12 3 N007 .04f +C17 N007 4 .04f +D7 N007 N009 YF2 +D9 N009 N013 YR2 +R3 N013 N006 1Meg noiseless +C18 N013 4 .04f +C20 3 N013 .04f +G1 N007 N013 0 N008 5µ vto=-500m dir=1 +.model YF1 D(Ron=900k Roff=1G Vfwd=50m epsilon=100m noiseless) +.model YF2 D(Ron=100k Roff=1G Vfwd=380m epsilon=100m noiseless) +.model YR1 D(Ron=800k Roff=1G Vfwd=50m epsilon=100m noiseless) +.model YR2 D(Ron=100k Roff=1G Vfwd=400m epsilon=100m noiseless) +.model DBIAS D(Ron=100k Roff=1G Vfwd=.6 ilimit=.9u noiseless) +.model DSHUT D(Ron=180k Vfwd=.6 epsilon=.1 noiseless) +.model N VDMOS(Vto=-133m Kp=340m noiseless) +.model P VDMOS(Vto=133m Kp=340m pchan noiseless) +.model swZombie SW(Ron=1 Roff=500 vt=.5 vh=-300m noiseless) +.model DNLSlew D(Ron=300 Roff=2k Rrev=250 vfwd=500m epsilon=200m ilimit=1.4m vrev=1.1 revepsilon=500m noiseless) +.model DNLSlew2 D(Ron=50 Roff=100k Rrev=800 vfwd=100m epsilon=100m vrev=100m revepsilon=100m noiseless) +.model SLWMOD SW(level=2 Ron=10 Roff=1Meg vt=-7.5 vh=-5 noiseless) +.ends LT1812 +* +.subckt LT1813 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.99p ink=246 +C2 2 1 .1p Rpar=1.6Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.7,.1), V(4)+.7, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.69,.1), V(4)+.69, .1)+1n*V(2) +C9 3 2 1p Rpar=20Meg noiseless +C10 N004 0 6f Rpar=100K noiseless +C13 N006 5 3.2p Rser=800 noiseless +C1 2 4 1p Rpar=20Meg noiseless +C6 3 1 1p Rpar=20Meg noiseless +C7 1 4 1p Rpar=20Meg noiseless +D2 3 1 DBIAS +D4 3 2 DBIAS +C11 N009 0 6.4f Rser=77.8k Rpar=100k noiseless +G2 0 N009 N005 0 10µ +A3 0 N004 0 0 0 0 N005 0 OTA g=1m linear Rout=2k Cout=400f en=7.95n enk=133 Vlow=-1e308 Vhigh=1e308 +D5 N005 0 DNLSlew +D6 N010 0 DNLSlew2 +S3 N005 N010 4 3 SLWMOD +C14 N005 N010 1p +G5 4 N006 N009 0 900µ +M1 3 N007 N008 N008 N temp=27 +M2 4 N012 N008 N008 P temp=27 +C4 3 N008 1p noiseless +C5 N008 4 1p noiseless +C15 3 5 1p noiseless +C16 5 4 1p noiseless +C19 3 N006 .66p Rpar=6Meg noiseless +G6 N009 0 N006 3 1m dir=1 vto=-.95 +G3 4 N009 4 N006 1m dir=1 vto=-.95 +C8 N006 4 .66p Rpar=6Meg noiseless +D1 N007 N008 YF1 +D3 N008 N012 YR1 +R2 N007 N006 1Meg noiseless +C12 3 N007 .04f +C17 N007 4 .04f +D7 N007 N008 YF2 +D9 N008 N012 YR2 +R3 N012 N006 1Meg noiseless +C18 N012 4 .04f +C20 3 N012 .04f +R4 5 N008 1 noiseless +.model YF1 D(Ron=900k Roff=1G Vfwd=50m epsilon=100m noiseless) +.model YF2 D(Ron=100k Roff=1G Vfwd=380m epsilon=100m noiseless) +.model YR1 D(Ron=800k Roff=1G Vfwd=50m epsilon=100m noiseless) +.model YR2 D(Ron=100k Roff=1G Vfwd=400m epsilon=100m noiseless) +.model DBIAS D(Ron=100k Roff=1G Vfwd=.6 ilimit=.9u noiseless) +.model N VDMOS(Vto=-133m Kp=340m noiseless) +.model P VDMOS(Vto=133m Kp=340m pchan noiseless) +.model swZombie SW(Ron=1 Roff=500 vt=.5 vh=-300m noiseless) +.model DNLSlew D(Ron=300 Roff=2k Rrev=250 vfwd=500m epsilon=200m ilimit=1.4m vrev=1.1 revepsilon=500m noiseless) +.model DNLSlew2 D(Ron=50 Roff=100k Rrev=800 vfwd=100m epsilon=100m vrev=100m revepsilon=100m noiseless) +.model SLWMOD SW(level=2 Ron=10 Roff=1Meg vt=-7.5 vh=-5 noiseless) +.ends LT1813 +* +.subckt LT1881 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=21f ink=20 +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)-0.9,.1), V(4)+0.9, .1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)-0.89,.1), V(4)+0.89, .1)+1n*V(2) +C6 3 1 .1p Rpar=400G noiseless +C7 1 4 .1p noiseless Rpar=400G +C8 2 4 .1p Rpar=400G noiseless +C9 3 2 .1p Rpar=400G noiseless +A2 0 N003 0 0 0 0 X 0 OTA g=33.7u asym isink=-1.66u isource=3.28u Cout=8.7p en=14n enk=2 Vhigh=1e308 Vlow=-1e308 +C10 N003 0 1f Rpar=100K noiseless +D1 X 3 XU +D4 4 X XD +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 10.6f Rpar=1Meg noiseless +C3 3 5 0.5p +C4 5 4 0.5p +D5 N004 5 Y +D6 5 N004 Y +G1 0 N004 N005 0 1µ +C12 N006 0 2.12n noiseless Rser=1.5k Rpar=1k +G4 0 N006 X 0 1m +C13 N005 0 265p noiseless Rpar=1k +G5 0 N005 N006 0 1m +C2 2 1 1.8p Rpar=20Meg noiseless +.model XU D(Ron=1K Roff=100G Vfwd=-.2 epsilon=1.0 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-20m epsilon=1.0 noiseless) +.model Y D(Ron=1.1k Roff=1T Vfwd=.75 epsilon=.1 noiseless) +.model N VDMOS(Vto=-135m Kp=70m) +.model P VDMOS(Vto=135m Kp=70m pchan) +.ends LT1881 +* +.subckt LT1884 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=50f ink=10 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+0.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+0.89, .1)+1n*V(2) +C6 3 1 .5p Rpar=1T noiseless +C7 1 4 .5p noiseless Rpar=1T +C8 2 4 .5p Rpar=1T noiseless +C9 3 2 .5p Rpar=1T noiseless +A2 0 N004 0 0 0 0 X 0 OTA g=33.7u asym isink=-1.88u isource=2.42u Cout=2.668p en=9.5n enk=2 Vhigh=1e308 Vlow=-1e308 +C10 N004 0 0.1f Rpar=100K noiseless +D1 X 3 XU +D4 4 X XD +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C1 N005 0 2f Rpar=1Meg noiseless +C3 3 5 0.5p +C4 5 4 0.5p +D5 N005 5 Y +D6 5 N005 Y +G1 0 N005 N006 0 1µ +C11 N009 0 1.79n Rser=65.2 Rpar=1k +G2 0 N009 X 0 1m +G3 0 N010 N009 0 1m +L1 N010 0 1.44m Rser=1.24k Rpar=5.16666666666667k Cpar=2.2p noiseless +G4 0 N006 N010 0 1m +L2 N006 0 0.4956m Rser=4.23k Rpar=1.309597523219814k Cpar=3p noiseless +D2 1 4 DBIAS +D3 2 4 DBIAS +.model XU D(Ron=1K Roff=100G Vfwd=-.229 epsilon=1.0 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-20m epsilon=1.0 noiseless) +.model Y D(Ron=4.8k Roff=1T Vfwd=.79 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=54.5m) +.model P VDMOS(Vto=150m Kp=54.5m pchan) +.model DBIAS D(Ron=1Meg Roff=1T vfwd=600m epsilon=500m ilimit=100p) +.ends LT1884 +* +.subckt LT1886 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.9p ink=1.1k +C2 2 1 .1p Rpar=35k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3),.1), V(4)+.7, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+0.01,.1), V(4)+.69, .1)+1n*V(2) +C9 3 2 1p Rpar=20Meg noiseless +C10 N004 0 5f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 1p +D5 N005 5 YU +D6 5 N005 YD +C4 5 4 1p +C1 2 4 1p Rpar=20Meg noiseless +C6 3 1 1p Rpar=20Meg noiseless +C7 1 4 1p Rpar=20Meg noiseless +D2 2 4 DBIAS +D4 1 4 DBIAS +G1 0 N005 N007 0 100µ +C8 0 N005 8f Rpar=10k noiseless +R1 3 4 5.7k noiseless +D1 N006 3 X +D7 4 N006 X +A2 0 N004 0 0 0 0 N006 0 OTA g=2.4u en=5.95n enk=166 cout=.549f iout=112n Vhigh=1e308 Vlow=-1e308 +D8 2 1 DIN +G2 0 N007 N006 0 1m +C11 0 N007 400f Rpar=1k noiseless +.model X D(Ron=1k Roff=10G Vfwd=-.7 epsilon=.5 noiseless) +.model YU D(Ron=10 Roff=1T Vfwd=1.63 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=1.13 epsilon=.1 noiseless) +.model N VDMOS(Vto=-140m Kp=500m) +.model P VDMOS(Vto=140m Kp=500m pchan) +.model DBIAS D(Ron=10k Roff=1T Vfwd=.6 ilimit=1.5u noiseless) +.model DIN D(Ron=500 Roff=1G Vfwd=.8 Vrev=.8 epsilon=.1 revepsilon=.1 noiseless) +.ends LT1886 +* +.subckt LT1920 1 2 3 4 5 6 7 8 +A2 0 N014 0 0 0 0 N017 0 OTA g=27.8u Iout=5u Cout=270f en=5.3n enk=10 Vhigh=1e308 Vlow=-1e308 +DU1 N017 7 XU +DD1 4 N017 XD +DU2 N006 7 XU +DD2 4 N006 XD +G2 0 N003 N006 0 1m +C3 N003 0 100f Rpar=1k +R6 N004 1 24.7k noiseless +R7 1 8 1t noiseless +R8 8 N018 24.7k noiseless +DB1 7 2 DBIAS +DB4 7 3 DBIAS +C5 7 2 .8p Rpar=400g noiseless +C6 7 1 .1p Rpar=400g noiseless +C7 7 3 .8p Rpar=400g noiseless +C8 2 4 .8p Rpar=400g noiseless +C9 1 4 .1p Rpar=400g noiseless +C10 3 4 .8p Rpar=400g noiseless +C11 7 8 .1p Rpar=400g noiseless +C12 8 4 .1p Rpar=400g noiseless +DU3 N011 7 X2U +DD3 4 N011 X2D +G1 0 N009 N011 0 1µ +CG1 N009 0 160f Rpar=1Meg noiseless +R1 N004 N005 10k noiseless +R2 N018 N012 10k noiseless +M1 7 N010 6 6 N temp=27 +M2 4 N010 6 6 P temp=27 +D1 N010 6 YU +D2 6 N010 YD +A1 0 N002 0 0 0 0 N006 0 OTA g=27.8u Iout=5u Cout=270f en=5.3n enk=10 Vhigh=1e308 Vlow=-1e308 +A0 2 3 0 0 0 0 0 0 OTA g=0 in=57f ink=37 +B1 0 N002 I=10u*dnlim(uplim(V(2)-.5,V(7)-1.79,.1), V(4)+1.29, .1)+1n*V(2) +C13 N002 0 50f Rpar=100K noiseless +C15 N014 0 50f Rpar=100K noiseless +CG4 7 6 1p +CG5 6 4 1p +M3 7 N003 N004 N004 NINT temp=27 +M4 4 N003 N004 N004 PINT temp=27 +M5 7 N016 N018 N018 NINT temp=27 +M6 4 N016 N018 N018 PINT temp=27 +G3 0 N016 N017 0 1m +C17 N016 0 100f Rpar=1k noiseless +A3 N005 N012 0 0 0 0 N011 0 OTA g=238.8u Iout=54.2u Cout=45p en=33.5n enk=16 Vlow=-1e308 Vhigh=1e308 +C1 0 N004 1p +C18 N018 0 1p +C19 1 8 5p Rser=20 noiseless +C20 2 3 .8p +C21 N004 1 5p Rser=20 noiseless +C22 8 N018 5p Rser=20 noiseless +R3 N005 6 10k noiseless +R4 N012 5 10k noiseless +C2 0 N005 1p +C14 N012 0 1p +DB2 7 4 DP +B2 0 N014 I=10u*dnlim(uplim(V(3)-.5,V(7)-1.8,.1), V(4)+1.3, .1)+1n*V(3) +G5 0 N010 N009 0 10µ +CG2 N010 0 2p Rpar=100k noiseless +B3 N002 0 I=10u*dnlim(uplim(V(1),V(7)-1.79,.1), V(4)+.5, .1)+1n*V(1) +B4 N014 0 I=10u*dnlim(uplim(V(8),V(7)-.5,.1), V(4)+.5, .1)+1n*V(8) +.model XU D(Ron=1k Roff=100g Vfwd=0 epsilon=100m noiseless) +.model XD D(Ron=1k Roff=100g Vfwd=0 epsilon=100m noiseless) +.model DBIAS D(Ron=1Meg Vfwd=.7 ilimit=.5n noiseless) +.model DP D(Ron=1k Vfwd=.6 epsilon=100m ilimit=405u noiseless) +.model NINT VDMOS(Vto=-40m Kp=100m) +.model PINT VDMOS(Vto=40m Kp=100m pchan) +.model X2U D(Ron=1k Roff=100G Vfwd=-.9 epsilon=.1 noiseless) +.model X2D D(Ron=1k Roff=100G Vfwd=-.65 epsilon=.1 noiseless) +.model YU D(Ron=50 Roff=1G Vfwd=.63 epsilon=.1 noiseless) +.model YD D(Ron=500 Roff=1G Vfwd=.65 epsilon=.1 noiseless) +.model N VDMOS(Vto=-80m Kp=100m Rds=1Meg) +.model P VDMOS(Vto=80m Kp=100m Rds=1Meg pchan) +.model DDROP D(Roff=100k Ron=5 Vfwd=150m Vrev=1 epsilon=.1 noiseless) +.ends LT1920 +* +.subckt LTC2050 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)-.4, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)-.41, .1)+1n*V(2) +C9 3 2 .85p Rpar=1T noiseless +C10 N004 0 1f Rpar=100K noiseless +M1 3 N006 5 5 N temp=27 +M2 4 N010 5 5 P temp=27 +D5 N006 5 Y +D6 5 N010 Y +R2 3 N008 2G noiseless +R3 N008 4 2G noiseless +A3 6 3 0 0 0 0 N005 0 SCHMITT Vt=-1.5 Vh=100m tau=50u +A4 N005 0 N008 N008 N008 N008 N006 N008 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-15 Rout=1k Cout=.1p +A5 N005 0 N008 N008 N008 N010 N008 N008 SCHMITT Vt=.5 Vh=10m Vhigh=15 Vlow=0 Rout=1k Cout=.1p +C14 0 N007 15p Rpar=6k noiseless +A7 N007 0 N005 0 0 0 N008 0 OTA g=3.2m iout=1m Vlow=-1e308 Vhigh=1e308 +G1 N008 0 N008 3 500m dir=1 vto=.3 +G2 0 N008 4 N008 500m dir=1 vto=.45 +G3 0 N007 0 N009 167µ +D1 3 6 DSIN +C2 3 5 1p Rpar=1G noiseless +C15 5 4 1p Rpar=1G noiseless +A2 0 N004 0 0 0 0 N009 0 OTA g=3.2m linear en=79n Rout=1k Cout=40p Vlow=-1e308 Vhigh=1e308 +S2 3 4 N005 0 SPOW +C3 N008 0 500p Rser=100 noiseless +C1 2 4 .85p Rpar=1T noiseless +C4 3 1 .85p Rpar=1T noiseless +C6 1 4 .85p Rpar=1T noiseless +R4 3 4 3.3Meg noiseless +.model Y D(Ron=100 Roff=1T Vfwd=.6 epsilon=.1 noiseless) +.model N VDMOS(Vto=-100m Kp=90m) +.model P VDMOS(Vto=100m Kp=70m pchan) +.model DSIN D(Ron=100k Roff=100Meg Vfwd=.1 epsilon=100m ilimit=.5u noiseless) +.model shutD SW(Ron=1T Roff=10k vt=.5 vh=-.1) +.model DS D(Ron=100 Roff=1G Vfwd=.2 Vrev=.2 epsilon=0.1 revepsilon=0.1 noiseless) +.model SPOW SW(level=2 Ron=500 Roff=1G vt=.5 vh=-.1 ilimit=.5m noiseless) +.ends LTC2050 +* +* NODES 1 AND 8 = COMPENSATION PINS +.SUBCKT LM108A 3 2 7 4 6 1 8 +* USE C=30 PF IN MAIN CIRCUIT (CA TO CB). +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 2 10 QM1 +Q2 90 3 11 QM2 +DDM1 2 3 DM2 +DDM2 3 2 DM2 +C1 80 90 5.46e-12 +RE1 10 12 224.6 +RE2 11 12 224.6 +IEE 12 4 6.001e-6 +RE 12 0 33330000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 3.576E-10 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +* EXTERNAL COMP CAP USED FOR C2 (SEE NOTE ABOVE). +GB 1 0 8 0 31.46 +* OUTPUT +RO1 1 6 111.1 +RO2 1 0 888.9 +RC 17 0 3.533E-04 +GC 0 17 6 0 2830 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 1.766 +VE 14 4 1.766 +IP 7 4 0.000294 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=5714) +.MODEL QM2 NPN(IS=8.093E-16 BF=6316) +.MODEL DM1 D(IS=1.192E-10) +.MODEL DM2 D(IS=8e-16) +.ENDS LM108A +* +.SUBCKT LH2108A 3 2 7 4 6 1 8 +X_LH2108A 3 2 7 4 6 1 8 LM108A +.ENDS LH2108A +* +* NODES 1 AND 8 = COMPENSATION PINS +.SUBCKT LM308 3 2 7 4 6 1 8 +* USE C=30 PF IN MAIN CIRCUIT (CA TO CB). +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 2 10 QM1 +Q2 90 3 11 QM2 +DDM1 2 3 DM2 +DDM2 3 2 DM2 +C1 80 90 5.46e-12 +RE1 10 12 224.5 +RE2 11 12 224.5 +IEE 12 4 6.003e-6 +RE 12 0 33320000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 1.131e-9 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +* EXTERNAL COMP CAP USED FOR C2 (SEE NOTE ABOVE). +GB 1 0 8 0 31.46 +* OUTPUT +RO1 1 6 111.1 +RO2 1 0 888.9 +RC 17 0 3.533E-04 +GC 0 17 6 0 2830 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 1.766 +VE 14 4 1.766 +IP 7 4 0.000294 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=1875) +.MODEL QM2 NPN(IS=8.643E-16 BF=2143) +.MODEL DM1 D(IS=1.192E-10) +.MODEL DM2 D(IS=8e-16) +.ENDS LM308 +* +* NODES 1 AND 8 = COMPENSATION PINS +.SUBCKT LM308A 3 2 7 4 6 1 8 +* USE C=30 PF IN MAIN CIRCUIT (CA TO CB). +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 2 10 QM1 +Q2 90 3 11 QM2 +DDM1 2 3 DM2 +DDM2 3 2 DM2 +C1 80 90 5.46e-12 +RE1 10 12 224.5 +RE2 11 12 224.5 +IEE 12 4 6.003e-6 +RE 12 0 33320000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 3.576E-10 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +* EXTERNAL COMP CAP USED FOR C2 (SEE NOTE ABOVE). +GB 1 0 8 0 31.46 +* OUTPUT +RO1 1 6 111.1 +RO2 1 0 888.9 +RC 17 0 3.533E-04 +GC 0 17 6 0 2830 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 1.766 +VE 14 4 1.766 +IP 7 4 0.000294 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=1875) +.MODEL QM2 NPN(IS=8.093E-16 BF=2143) +.MODEL DM1 D(IS=1.192E-10) +.MODEL DM2 D(IS=8e-16) +.ENDS LM308A +* +* NODES 1 AND 8 = COMPENSATION PINS +.SUBCKT LM108 3 2 7 4 6 1 8 +* USE C=30 PF IN MAIN CIRCUIT (CA TO CB). +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 2 10 QM1 +Q2 90 3 11 QM2 +DDM1 2 3 DM2 +DDM2 3 2 DM2 +C1 80 90 5.46e-12 +RE1 10 12 224.6 +RE2 11 12 224.6 +IEE 12 4 6.001e-6 +RE 12 0 33330000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 1.131e-9 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +* EXTERNAL COMP CAP USED FOR C2 (SEE NOTE ABOVE). +GB 1 0 8 0 31.46 +* OUTPUT +RO1 1 6 111.1 +RO2 1 0 888.9 +RC 17 0 3.533E-04 +GC 0 17 6 0 2830 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 1.766 +VE 14 4 1.766 +IP 7 4 0.000294 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=5714) +.MODEL QM2 NPN(IS=8.22e-16 BF=6316) +.MODEL DM1 D(IS=1.192E-10) +.MODEL DM2 D(IS=8e-16) +.ENDS LM108 +* +.SUBCKT LH2108 3 2 7 4 6 1 8 +X_LH2108 3 2 7 4 6 1 8 LM108 +.ENDS LH2108 +* +* NODES 1 AND 8 = COMPENSATION PINS +.SUBCKT LM101A 3 2 7 4 6 1 8 +* USE C=30 PF IN MAIN CIRCUIT (CA TO CB). +* INPUT +RC1 7 80 5895 +RC2 7 90 5895 +Q1 80 2 10 QM1 +Q2 90 3 11 QM2 +C1 80 90 5.46e-12 +RE1 10 12 2438 +RE2 11 12 2438 +IEE 12 4 1.506e-5 +RE 12 0 13280000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 2.689e-9 +GA 8 0 80 90 1.696E-04 +R2 8 0 100000 +* EXTERNAL COMP CAP USED FOR C2 (SEE NOTE ABOVE). +GB 1 0 8 0 140.1 +* OUTPUT +RO1 1 6 33.33 +RO2 1 0 66.67 +RC 17 0 4.758e-5 +GC 0 17 6 0 21020 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 1.808 +VE 14 4 1.808 +IP 7 4 0.001785 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=243.9) +.MODEL QM2 NPN(IS=8.22e-16 BF=256.4) +.MODEL DM1 D(IS=3.337E-15) +.MODEL DM2 D(IS=8e-16) +.ENDS LM101A +* +* NODES 1 AND 8 = COMPENSATION PINS +.SUBCKT LM301A 3 2 7 4 6 1 8 +* USE C=30 PF IN MAIN CIRCUIT (CA TO CB). +* INPUT +RC1 7 80 5895 +RC2 7 90 5895 +Q1 80 2 10 QM1 +Q2 90 3 11 QM2 +C1 80 90 5.46e-12 +RE1 10 12 2438 +RE2 11 12 2438 +IEE 12 4 1.506e-5 +RE 12 0 13280000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 2.689e-9 +GA 8 0 80 90 1.696E-04 +R2 8 0 100000 +* EXTERNAL COMP CAP USED FOR C2 (SEE NOTE ABOVE). +GB 1 0 8 0 140.1 +* OUTPUT +RO1 1 6 33.33 +RO2 1 0 66.67 +RC 17 0 4.758e-5 +GC 0 17 6 0 21020 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 1.808 +VE 14 4 1.808 +IP 7 4 0.001785 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=104.9) +.MODEL QM2 NPN(IS=8.647E-16 BF=109.5) +.MODEL DM1 D(IS=3.337E-15) +.MODEL DM2 D(IS=8e-16) +.ENDS LM301A +* +* OP AMP SECTION FOLLOWS 3-2-7-4-6 CONVENTION +* 8=REFERENCE FEEDBACK +* 1=REFERENCE OUTPUT +.SUBCKT LM10C 3 2 7 4 6 1 8 +RC1 4 80 53050 +RC2 4 90 53050 +Q1 80 102 10 QM1 +Q2 90 103 11 QM2 +RB1 2 102 4000 +RB2 3 103 4000 +DCM1 105 102 DM2 +DCM2 105 103 DM2 +VCMC 105 4 0.4 +C1 80 90 2.598E-11 +RE1 10 12 41340 +RE2 11 12 41340 +IEE 7 12 4.524e-6 +RE 12 0 44210000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 85 12 0 1.497E-10 +GA 85 0 80 90 1.885e-5 +R2 85 0 100000 +C2 15 85 3e-11 +GB 15 0 85 0 245.5 +* OUTPUT +RO1 15 110 100 +RO2A 15 0 1083 +RO2B 6 110 817 +EC 17 0 110 0 1 +D1 15 17 DM1 +D2 17 15 DM1 +D3 110 13 DM2 +D4 14 110 DM2 +D5 6 110 DM2 +D6 110 6 DM2 +VC 7 13 0.8075 +VE 14 4 0.8075 +IP 7 4 2.955E-04 +DSUB 4 7 DM2 +* REFERENCE +ER 1 4 8 200 70E3 +VR 200 4 0.200 +RRIN 200 4 1E9 +IBR 8 4 22E-9 +.MODEL QM1 PNP(IS=8e-16 BF=184.4) +.MODEL QM2 PNP(IS=8.156E-16 BF=190.7) +.MODEL DM1 D(IS=2.784E-32) +.MODEL DM2 D(IS=8e-16 BV=49.5) +.ENDS LM10C +* +.SUBCKT LM318 3 2 7 4 6 +* INPUT +RC1 7 80 707.4 +RC2 7 90 707.4 +Q1 80 2 10 QM1 +Q2 90 3 11 QM1 +C1 80 91 300E-12 +RXC1 91 90 1E3 +CXC1 91 90 15E-12 +C2 1 8 5e-12 +RB1 2 102 1 +RB2 3 103 1 +DDM1 102 104 DM2 +VZ1 104 103 5.5 +DDM2 103 105 DM2 +VZ2 105 102 5.5 +RE1 10 12 620.9 +RE2 11 12 620.9 +IEE 12 4 0.0006 +RE 12 0 333200 +CE 12 0 2.632E-13 +GCM 0 8 12 0 1.414e-8 +GA 8 0 80 90 0.001414 +R2 8 0 100000 +GB 1 0 8 0 53.18 +RO2 1 0 74 +RS 1 6 1 +ECL 18 0 1 6 31.72 +GCL 0 8 20 0 1 +RCL 20 0 1E3 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.6473 +RPLA 7 70 1E4 +RPLB 7 131 1E5 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.6473 +RNLA 60 4 1E4 +RNLB 141 4 1E5 +IP 7 4 0.0044 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=1818) +.MODEL QM2 NPN(IS=9.347E-16 BF=2222) +.MODEL DM1 D(IS=1e-19) +.MODEL DM2 D(IS=8e-16) +.MODEL DM3 D(IS=1e-20) +.ENDS LM318 +* +.SUBCKT LM318S8 3 2 7 4 6 +X_LM318S8 3 2 7 4 6 LM318 +.ENDS LM318S8 +* +.subckt LT118A 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=195f ink=550 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C2 2 1 2p +C3 3 5 .5p +C4 5 4 .5p +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-3.4,.1), V(4)+3.4, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-3.39,.1), V(4)+3.39, .1)+1n*V(2) +C6 3 1 .5p +C7 1 4 .5p +C8 2 4 .5p +C9 3 2 .5p +C10 N004 0 8f Rpar=100K noiseless +D2 2 1 DI +D3 3 4 DCPOW +D1 N005 5 Y +D4 5 N005 Y +D5 N005 3 X +D6 4 N005 X +A3 0 N004 0 0 0 0 N008 0 OTA G=70.7m asym isrc=47.2m isink= -33m Cout=229n en=11n enk=200 Vhigh=1e308 Vlow=-1e308 +G5 0 N006 N008 0 1m +L4 N006 0 5.81m Rser=1.96K Rser=2k Rpar=2k Cpar=4.77p noiseless +D7 0 N008 DCL +G2 0 N005 N007 0 14.14n +C1 N005 0 2.89e-17 +G3 0 N007 N006 0 1m +L2 N007 0 308µ Rser=1.96K Rser=1k noiseless +D8 1 4 DBIAS +D9 2 4 DBIAS +.model X D(Ron=1K Roff=100G Vfwd=-1.8 epsilon=.1 noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=0.43 epsilon=.1 noiseless) +.model N VDMOS(Vto=-200m Kp=120m mtriode=1) +.model P VDMOS(Vto=200m Kp=120m mtriode=1 pchan) +.model DI D(Ron=400 Roff=100G Vfwd=5 Vrev=5 epsilon=1 revepsilon=1 noiseless) +.model DCPOW D(Ron=100.0 Roff=1G Vfwd=1.0 Vrev=100.0 ilimit=2.6m noiseless) +.model DCL D(Roff=10k Ron=0.1 Vfwd=100m Vrev=100m epsilon=4m noiseless) +.model DBIAS D(Ron=1k Roff=1T Vfwd=2.0 ilimit=120n noiseless) +.ends LT118A +* +.SUBCKT LM307 3 2 7 4 6 +* INPUT +RC1 7 80 5895 +RC2 7 90 5895 +Q1 80 2 10 QM1 +Q2 90 3 11 QM2 +C1 80 90 5.46e-12 +RE1 10 12 2438 +RE2 11 12 2438 +IEE 12 4 1.506e-5 +RE 12 0 13280000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 2.689e-9 +GA 8 0 80 90 1.696E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 140.1 +* OUTPUT +RO1 1 6 33.33 +RO2 1 0 66.67 +RC 17 0 4.758e-5 +GC 0 17 6 0 21020 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 1.808 +VE 14 4 1.808 +IP 7 4 0.001785 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=104.9) +.MODEL QM2 NPN(IS=8.647E-16 BF=109.5) +.MODEL DM1 D(IS=3.337E-15) +.MODEL DM2 D(IS=8e-16) +.ENDS LM307 +* +.SUBCKT LM118 3 2 7 4 6 +* INPUT +RC1 7 80 707.4 +RC2 7 90 707.4 +Q1 80 2 10 QM1 +Q2 90 3 11 QM1 +C1 80 91 300E-12 +RXC1 91 90 1E3 +CXC1 91 90 15E-12 +C2 1 8 5e-12 +RB1 2 102 1 +RB2 3 103 1 +DDM1 102 104 DM2 +VZ1 104 103 5.5 +DDM2 103 105 DM2 +VZ2 105 102 5.5 +RE1 10 12 620.9 +RE2 11 12 620.9 +IEE 12 4 0.0006 +RE 12 0 333200 +CE 12 0 2.632E-13 +GCM 0 8 12 0 1.414e-8 +GA 8 0 80 90 0.001414 +R2 8 0 100000 +GB 1 0 8 0 53.18 +RO2 1 0 74 +RS 1 6 1 +ECL 18 0 1 6 31.72 +GCL 0 8 20 0 1 +RCL 20 0 1E3 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.6473 +RPLA 7 70 1E4 +RPLB 7 131 1E5 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.6473 +RNLA 60 4 1E4 +RNLB 141 4 1E5 +IP 7 4 0.0044 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=2439) +.MODEL QM2 NPN(IS=8.6435E-16 BF=2564.1) +.MODEL DM1 D(IS=1e-19) +.MODEL DM2 D(IS=8e-16) +.MODEL DM3 D(IS=1e-20) +.ENDS LM118 +* +.SUBCKT LM107 3 2 7 4 6 +* INPUT +RC1 7 80 5895 +RC2 7 90 5895 +Q1 80 2 10 QM1 +Q2 90 3 11 QM2 +C1 80 90 5.46e-12 +RE1 10 12 2438 +RE2 11 12 2438 +IEE 12 4 1.506e-5 +RE 12 0 13280000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 2.689e-9 +GA 8 0 80 90 1.696E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 140.1 +* OUTPUT +RO1 1 6 33.33 +RO2 1 0 66.67 +RC 17 0 4.758e-5 +GC 0 17 6 0 21020 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 1.808 +VE 14 4 1.808 +IP 7 4 0.001785 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=243.9) +.MODEL QM2 NPN(IS=8.22e-16 BF=256.4) +.MODEL DM1 D(IS=3.337E-15) +.MODEL DM2 D(IS=8e-16) +.ENDS LM107 +* +.SUBCKT LF412A 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 930.73 +RD2 40 90 930.73 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.0006 +GOSIT 7 12 90 80 0.0003 +* INTERMEDIATE +GCM 0 8 12 0 1.0744e-8 +GA 8 0 80 90 0.0010744 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 29.73 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.925 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1615 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1615 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.0012 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=2e-11 BETA=9.6199E-04 VTO=-1) +.MODEL JM2 PJF(IS=1e-11 BETA=9.6199E-04 VTO=-0.9997) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF412A +* +.SUBCKT LF412 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 964.58 +RD2 40 90 964.58 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00052 +GOSIT 7 12 90 80 0.00026 +* INTERMEDIATE +GCM 0 8 12 0 1.0367e-8 +GA 8 0 80 90 0.0010367 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 24.474 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.774 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1575 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1575 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.00138 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=2.75e-11 BETA=0.0010335 VTO=-1) +.MODEL JM2 PJF(IS=1.25e-11 BETA=0.0010335 VTO=-0.9995) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=43.2) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF412 +* +.SUBCKT LF156A 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 1061 +RD2 40 90 1061 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00048 +GOSIT 7 12 90 80 0.00024 +* INTERMEDIATE +GCM 0 8 12 0 9.4248e-9 +GA 8 0 80 90 9.4248E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 28.609 +RO2 1 0 74 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.69 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1552 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1552 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.00452 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=3.15e-11 BETA=9.2528E-04 VTO=-1) +.MODEL JM2 PJF(IS=2.85e-11 BETA=9.2528E-04 VTO=-0.999) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF156A +* +.SUBCKT LF156 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 1061 +RD2 40 90 1061 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00048 +GOSIT 7 12 90 80 0.00024 +* INTERMEDIATE +GCM 0 8 12 0 9.4248e-9 +GA 8 0 80 90 9.4248E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 28.609 +RO2 1 0 74 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.69 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1552 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1552 +RNLA 60 4 10000 +RNLB 141 4 100000 +* +IP 7 4 0.00452 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=3.15e-11 BETA=9.2528E-04 VTO=-1) +.MODEL JM2 PJF(IS=2.85e-11 BETA=9.2528E-04 VTO=-0.998) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF156 +* +.SUBCKT LF356A 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 1061 +RD2 40 90 1061 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00048 +GOSIT 7 12 90 80 0.00024 +* INTERMEDIATE +GCM 0 8 12 0 9.4248e-9 +GA 8 0 80 90 9.4248E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 28.609 +RO2 1 0 74 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.69 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1552 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1552 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.00452 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=3.15e-11 BETA=9.2528E-04 VTO=-1) +.MODEL JM2 PJF(IS=2.85e-11 BETA=9.2528E-04 VTO=-0.999) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF356A +* +.SUBCKT LF356 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 1061 +RD2 40 90 1061 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00048 +GOSIT 7 12 90 80 0.00024 +* INTERMEDIATE +GCM 0 8 12 0 9.4248e-9 +GA 8 0 80 90 9.4248E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 28.609 +RO2 1 0 74 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.69 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1552 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1552 +RNLA 60 4 10000 +RNLB 141 4 100000 +* +IP 7 4 0.00452 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=3.15e-11 BETA=9.2528E-04 VTO=-1) +.MODEL JM2 PJF(IS=2.85e-11 BETA=9.2528E-04 VTO=-0.997) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=43.2) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF356 +* +.SUBCKT LF155A 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 2122.1 +RD2 40 90 2122.1 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00028 +GOSIT 7 12 90 80 0.00014 +* INTERMEDIATE +GCM 0 8 12 0 4.7124e-9 +GA 8 0 80 90 4.7124E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 42.768 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.124 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1403 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1403 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.00172 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=3.15e-11 BETA=3.9655E-04 VTO=-1) +.MODEL JM2 PJF(IS=2.85e-11 BETA=3.9655E-04 VTO=-0.999) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF155A +* +.SUBCKT LF155 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 2122.1 +RD2 40 90 2122.1 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00028 +GOSIT 7 12 90 80 0.00014 +* INTERMEDIATE +GCM 0 8 12 0 4.7124e-9 +GA 8 0 80 90 4.7124E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 42.768 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.124 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1403 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1403 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.00172 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=3.15e-11 BETA=3.9655E-04 VTO=-1) +.MODEL JM2 PJF(IS=2.85e-11 BETA=3.9655E-04 VTO=-0.998) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF155 +* +.SUBCKT LF355A 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 2122.1 +RD2 40 90 2122.1 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00028 +GOSIT 7 12 90 80 0.00014 +* INTERMEDIATE +GCM 0 8 12 0 4.7124e-9 +GA 8 0 80 90 4.7124E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 42.768 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.124 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1403 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1403 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.00172 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=3.15e-11 BETA=3.9655E-04 VTO=-1) +.MODEL JM2 PJF(IS=2.85e-11 BETA=3.9655E-04 VTO=-0.999) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF355A +* +.SUBCKT LF355 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 2122.1 +RD2 40 90 2122.1 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00024 +GOSIT 7 12 90 80 0.00012 +* INTERMEDIATE +GCM 0 8 12 0 4.7124e-9 +GA 8 0 80 90 4.7124E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 42.768 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 19.963 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.136 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.136 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.00176 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=3.15e-11 BETA=4.6264E-04 VTO=-1) +.MODEL JM2 PJF(IS=2.85e-11 BETA=4.6264E-04 VTO=-0.997) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=43.2) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS LF355 +* +.SUBCKT OP07C 3 2 7 4 6 +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 102 10 QM1 +Q2 90 103 11 QM2 +RB1 2 102 500 +RB2 3 103 500 +DDM1 102 104 DM2 +DDM3 104 103 DM2 +DDM2 103 105 DM2 +DDM4 105 102 DM2 +C1 80 90 5.46e-12 +RE1 10 12 1948 +RE2 11 12 1948 +IEE 12 4 7.502e-6 +RE 12 0 26660000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 5.668E-11 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 1294 +* OUTPUT +RO1 1 6 25.75 +RO2 1 0 34.25 +RC 17 0 6.634e-6 +GC 0 17 6 0 150700 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 2.803 +VE 14 4 2.803 +IP 7 4 0.002492 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=1705) +.MODEL QM2 NPN(IS=8.019E-16 BF=2679) +.MODEL DM1 D(IS=1.486e-8) +.MODEL DM2 D(IS=8e-16) +.ENDS OP07C +* +.SUBCKT OP07CS8 3 2 7 4 6 +X_OP07CS8 3 2 7 4 6 OP07C +.ENDS OP07CS8 +* +.SUBCKT OP07E 3 2 7 4 6 +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 102 10 QM1 +Q2 90 103 11 QM2 +RB1 2 102 500 +RB2 3 103 500 +DDM1 102 104 DM2 +DDM3 104 103 DM2 +DDM2 103 105 DM2 +DDM4 105 102 DM2 +C1 80 90 5.46e-12 +RE1 10 12 1948 +RE2 11 12 1948 +IEE 12 4 7.502e-6 +RE 12 0 26660000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 5.668E-11 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 1294 +* OUTPUT +RO1 1 6 25.75 +RO2 1 0 34.25 +RC 17 0 6.634e-6 +GC 0 17 6 0 150700 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 2.803 +VE 14 4 2.803 +IP 7 4 0.002492 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=2586) +.MODEL QM2 NPN(IS=8.009E-16 BF=3947) +.MODEL DM1 D(IS=1.486e-8) +.MODEL DM2 D(IS=8e-16) +.ENDS OP07E +* +.SUBCKT OP07A 3 2 7 4 6 +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 102 10 QM1 +Q2 90 103 11 QM2 +RB1 2 102 500 +RB2 3 103 500 +DDM1 102 104 DM2 +DDM3 104 103 DM2 +DDM2 103 105 DM2 +DDM4 105 102 DM2 +C1 80 90 5.46e-12 +RE1 10 12 1948 +RE2 11 12 1948 +IEE 12 4 7.502e-6 +RE 12 0 26660000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 5.668E-11 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 1294 +* OUTPUT +RO1 1 6 25.75 +RO2 1 0 34.25 +RC 17 0 6.634e-6 +GC 0 17 6 0 150700 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 2.803 +VE 14 4 2.803 +IP 7 4 0.002492 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=4412) +.MODEL QM2 NPN(IS=8.003E-16 BF=6818) +.MODEL DM1 D(IS=1.486e-8) +.MODEL DM2 D(IS=8e-16) +.ENDS OP07A +* +.SUBCKT OP05C 3 2 7 4 6 +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 102 10 QM1 +Q2 90 103 11 QM2 +RB1 2 102 500 +RB2 3 103 500 +DDM1 102 104 DM2 +DDM3 104 103 DM2 +DDM2 103 105 DM2 +DDM4 105 102 DM2 +C1 80 90 5.46e-12 +RE1 10 12 3097 +RE2 11 12 3097 +IEE 12 4 9.002e-6 +RE 12 0 22220000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 5.668E-11 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 664.7 +* OUTPUT +RO1 1 6 33.33 +RO2 1 0 66.67 +RC 17 0 1.393e-5 +GC 0 17 6 0 71790 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 2.803 +VE 14 4 2.803 +IP 7 4 0.002991 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=1667) +.MODEL QM2 NPN(IS=8.094E-16 BF=5001) +.MODEL DM1 D(IS=5.991E-12) +.MODEL DM2 D(IS=8e-16) +.ENDS OP05C +* +.SUBCKT OP05E 3 2 7 4 6 +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 102 10 QM1 +Q2 90 103 11 QM2 +RB1 2 102 500 +RB2 3 103 500 +DDM1 102 104 DM2 +DDM3 104 103 DM2 +DDM2 103 105 DM2 +DDM4 105 102 DM2 +C1 80 90 5.46e-12 +RE1 10 12 3097 +RE2 11 12 3097 +IEE 12 4 9.002e-6 +RE 12 0 22220000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 5.668E-11 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 664.7 +* OUTPUT +RO1 1 6 33.33 +RO2 1 0 66.67 +RC 17 0 1.393e-5 +GC 0 17 6 0 71790 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 2.803 +VE 14 4 2.803 +IP 7 4 0.002991 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=2501) +.MODEL QM2 NPN(IS=8.062E-16 BF=7502) +.MODEL DM1 D(IS=5.991E-12) +.MODEL DM2 D(IS=8e-16) +.ENDS OP05E +* +.SUBCKT OP05A 3 2 7 4 6 +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 102 10 QM1 +Q2 90 103 11 QM2 +RB1 2 102 500 +RB2 3 103 500 +DDM1 102 104 DM2 +DDM3 104 103 DM2 +DDM2 103 105 DM2 +DDM4 105 102 DM2 +C1 80 90 5.46e-12 +RE1 10 12 3097 +RE2 11 12 3097 +IEE 12 4 9.002e-6 +RE 12 0 22220000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 5.668E-11 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 664.7 +* OUTPUT +RO1 1 6 33.33 +RO2 1 0 66.67 +RC 17 0 1.393e-5 +GC 0 17 6 0 71790 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 2.803 +VE 14 4 2.803 +IP 7 4 0.002991 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=4287) +.MODEL QM2 NPN(IS=8.022E-16 BF=12860) +.MODEL DM1 D(IS=5.991E-12) +.MODEL DM2 D(IS=8e-16) +.ENDS OP05A +* +.SUBCKT OP16B 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 698.05 +RD2 40 90 698.05 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00072 +GOSIT 7 12 90 80 0.00036 +* INTERMEDIATE +GCM 0 8 12 0 1.4326e-8 +GA 8 0 80 90 0.0014326 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 21.118 +RO2 1 0 74 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 21.119 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1666 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1666 +RNLA 60 4 10000 +RNLB 141 4 100000 +* +IP 7 4 0.00388 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=4.5e-11 BETA=0.0014252 VTO=-1) +.MODEL JM2 PJF(IS=3.5e-11 BETA=0.0014252 VTO=-0.9996) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS OP16B +* +.SUBCKT OP16F 3 2 7 4 6 +X_OP16F 3 2 7 4 6 OP16B +.ENDS OP16F +* +.SUBCKT OP16A 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 663.15 +RD2 40 90 663.15 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.0008 +GOSIT 7 12 90 80 0.0004 +* INTERMEDIATE +GCM 0 8 12 0 1.508e-8 +GA 8 0 80 90 0.001508 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 22.51 +RO2 1 0 74 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 21.231 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +* +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1696 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1696 +RNLA 60 4 10000 +RNLB 141 4 100000 +* +IP 7 4 0.0038 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=2.25e-11 BETA=0.0014212 VTO=-1) +.MODEL JM2 PJF(IS=1.75e-11 BETA=0.0014212 VTO=-0.9998) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS OP16A +* +.SUBCKT OP16E 3 2 7 4 6 +X_OP16E 3 2 7 4 6 OP16A +.ENDS OP16E +* +.SUBCKT OP16C 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 736.83 +RD2 40 90 736.83 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00064 +GOSIT 7 12 90 80 0.00032 +* INTERMEDIATE +GCM 0 8 12 0 2.151e-8 +GA 8 0 80 90 0.0013572 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 19.867 +RO2 1 0 74 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.994 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +* +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1633 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1633 +RNLA 60 4 10000 +RNLB 141 4 100000 +* +IP 7 4 0.00416 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=9e-11 BETA=0.001439 VTO=-1) +.MODEL JM2 PJF(IS=7e-11 BETA=0.001439 VTO=-0.9995) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=43.2) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS OP16C +* +.SUBCKT OP16G 3 2 7 4 6 +X_OP16G 3 2 7 4 6 OP16C +.ENDS OP16G +* +.SUBCKT OP15B 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 930.73 +RD2 40 90 930.73 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00044 +GOSIT 7 12 90 80 0.00022 +* INTERMEDIATE +GCM 0 8 12 0 1.0744e-8 +GA 8 0 80 90 0.0010744 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 21.047 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.598 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +* +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1528 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1528 +RNLA 60 4 10000 +RNLB 141 4 100000 +* +IP 7 4 0.00226 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=4.5e-11 BETA=0.0013118 VTO=-1) +.MODEL JM2 PJF(IS=3.5e-11 BETA=0.0013118 VTO=-0.9996) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS OP15B +* +.SUBCKT OP15F 3 2 7 4 6 +X_OP15F 3 2 7 4 6 OP15B +.ENDS OP15F +* +.SUBCKT OP15A 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 884.19 +RD2 40 90 884.19 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00052 +GOSIT 7 12 90 80 0.00026 +* INTERMEDIATE +GCM 0 8 12 0 1.131e-8 +GA 8 0 80 90 0.001131 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 22.434 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.774 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +* +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1575 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1575 +RNLA 60 4 10000 +RNLB 141 4 100000 +* +IP 7 4 0.00218 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=2.05e-11 BETA=0.0012299 VTO=-1) +.MODEL JM2 PJF(IS=1.55e-11 BETA=0.0012299 VTO=-0.9998) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS OP15A +* +.SUBCKT OP15E 3 2 7 4 6 +X_OP15E 3 2 7 4 6 OP15A +.ENDS OP15E +* +.SUBCKT OP15C 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 982.44 +RD2 40 90 982.44 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00036 +GOSIT 7 12 90 80 0.00018 +* INTERMEDIATE +GCM 0 8 12 0 1.6132e-8 +GA 8 0 80 90 0.0010179 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 19.8 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.387 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1472 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1472 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.00244 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=9e-11 BETA=0.001439 VTO=-1) +.MODEL JM2 PJF(IS=7e-11 BETA=0.001439 VTO=-0.9995) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=43.2) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS OP15C +* +.SUBCKT OP15G 3 2 7 4 6 +X_OP15G 3 2 7 4 6 OP15C +.ENDS OP15G +* +.SUBCKT OP215A 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 930.73 +RD2 40 90 930.73 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.0006 +GOSIT 7 12 90 80 0.0003 +* INTERMEDIATE +GCM 0 8 12 0 1.0744e-8 +GA 8 0 80 90 0.0010744 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 37.427 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.925 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1615 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1615 +RNLA 60 4 10000 +RNLB 141 4 100000 +IP 7 4 0.0013 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=2e-11 BETA=9.6199E-04 VTO=-1) +.MODEL JM2 PJF(IS=1e-11 BETA=9.6199E-04 VTO=-0.9998) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=52.8) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS OP215A +* +.SUBCKT OP215E 3 2 7 4 6 +X_OP215E 3 2 7 4 6 OP215A +.ENDS OP215E +* +.SUBCKT OP215C 3 2 7 4 6 +* INPUT +VCM2 40 4 2 +RD1 40 80 964.58 +RD2 40 90 964.58 +J1 80 102 12 JM1 +J2 90 103 12 JM2 +CIN 2 3 4e-12 +RG1 2 102 2 +RG2 3 103 2 +** CM CLAMP +* DCM1 107 103 DM4 +* DCM2 105 107 DM4 +* VCMC 105 4 4.0E+00 +* ECMP 106 4 103 4 1 +* RCMP 107 106 1E+04 +* DCM3 109 102 DM4 +* DCM4 105 109 DM4 +* ECMN 108 4 102 4 1 +* RCMN 109 108 1E+04 +** END CM CLAMP +C1 80 90 1.5e-11 +ISS 7 12 0.00052 +GOSIT 7 12 90 80 0.00026 +* INTERMEDIATE +GCM 0 8 12 0 1.0367e-8 +GA 8 0 80 90 0.0010367 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 24.474 +RO2 1 0 99 +* OUTPUT +RSO 1 6 1 +ECL 18 0 1 6 20.774 +GCL 0 8 20 0 1 +RCL 20 0 1000 +D1 18 20 DM1 +D2 20 18 DM1 +* +D3A 131 70 DM3 +D3B 13 131 DM3 +GPL 0 8 70 7 1 +VC 13 6 3.1575 +RPLA 7 70 10000 +RPLB 7 131 100000 +D4A 60 141 DM3 +D4B 141 14 DM3 +GNL 0 8 60 4 1 +VE 6 14 3.1575 +RNLA 60 4 10000 +RNLB 141 4 100000 +* +IP 7 4 0.00138 +DSUB 4 7 DM2 +.MODEL JM1 PJF(IS=2.75e-11 BETA=0.0010335 VTO=-1) +.MODEL JM2 PJF(IS=1.25e-11 BETA=0.0010335 VTO=-0.9995) +.MODEL DM1 D(IS=1e-15) +.MODEL DM2 D(IS=8e-16 BV=43.2) +.MODEL DM3 D(IS=1e-16) +.MODEL DM4 D(IS=1e-9) +.ENDS OP215C +* +.SUBCKT OP215G 3 2 7 4 6 +X_OP215G 3 2 7 4 6 OP215C +.ENDS OP215G +* +.SUBCKT OP97 3 2 7 4 6 +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 2 10 QM1 +Q2 90 3 11 QM2 +DDM1 2 3 DM2 +DDM2 3 2 DM2 +C1 80 90 5.46e-12 +RE1 10 12 224.6 +RE2 11 12 224.6 +IEE 12 4 6e-6 +RE 12 0 33330000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 2.841E-11 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 196 +* OUTPUT +RO1 1 6 100 +RO2 1 0 900 +RC 17 0 1.063E-04 +GC 0 17 6 0 9408 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 1.785 +VE 14 4 1.785 +IP 7 4 0.000374 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=75000) +.MODEL QM2 NPN(IS=8.008E-16 BF=150000) +.MODEL DM1 D(IS=1.179E-19) +.MODEL DM2 D(IS=8e-16) +.ENDS OP97 +* +.SUBCKT OP07 3 2 7 4 6 +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 102 10 QM1 +Q2 90 103 11 QM2 +RB1 2 102 500 +RB2 3 103 500 +DDM1 102 104 DM2 +DDM3 104 103 DM2 +DDM2 103 105 DM2 +DDM4 105 102 DM2 +C1 80 90 5.46e-12 +RE1 10 12 1948 +RE2 11 12 1948 +IEE 12 4 7.502e-6 +RE 12 0 26660000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 5.668E-11 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 1294 +* OUTPUT +RO1 1 6 25.75 +RO2 1 0 34.25 +RC 17 0 6.634e-6 +GC 0 17 6 0 150700 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 2.803 +VE 14 4 2.803 +IP 7 4 0.002492 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=3125) +.MODEL QM2 NPN(IS=8.009E-16 BF=4688) +.MODEL DM1 D(IS=1.486e-8) +.MODEL DM2 D(IS=8e-16) +.ENDS OP07 +* +.SUBCKT OP05 3 2 7 4 6 +* INPUT +RC1 7 80 8842 +RC2 7 90 8842 +Q1 80 102 10 QM1 +Q2 90 103 11 QM2 +RB1 2 102 500 +RB2 3 103 500 +DDM1 102 104 DM2 +DDM3 104 103 DM2 +DDM2 103 105 DM2 +DDM4 105 102 DM2 +C1 80 90 5.46e-12 +RE1 10 12 3097 +RE2 11 12 3097 +IEE 12 4 9.002e-6 +RE 12 0 22220000 +CE 12 0 1.579E-12 +* INTERMEDIATE +GCM 0 8 12 0 5.668E-11 +GA 8 0 80 90 1.131E-04 +R2 8 0 100000 +C2 1 8 3e-11 +GB 1 0 8 0 664.7 +* OUTPUT +RO1 1 6 33.33 +RO2 1 0 66.67 +RC 17 0 1.393e-5 +GC 0 17 6 0 71790 +D1 1 17 DM1 +D2 17 1 DM1 +D3 6 13 DM2 +D4 14 6 DM2 +VC 7 13 2.803 +VE 14 4 2.803 +IP 7 4 0.002991 +DSUB 4 7 DM2 +.MODEL QM1 NPN(IS=8e-16 BF=3000) +.MODEL QM2 NPN(IS=8.062E-16 BF=9000) +.MODEL DM1 D(IS=5.991E-12) +.MODEL DM2 D(IS=8e-16) +.ENDS OP05 +* +.subckt LT1166 1 2 3 4 5 6 7 8 +Q4 N039 N028 N035 0 PN +Q3 N031 N028 3 0 PN m=5 +Q1 N009 N021 N025 0 NP +Q2 N021 N017 3 0 NP m=5 +R1 2 N025 200 +R2 N035 2 200 +Q5 3 N039 4 0 NP m=40 +Q6 N035 N039 4 0 NP +Q7 N028 N040 N042 0 NP +R3 4 N042 1K +Q8 N040 N040 N043 0 NP +R4 4 N043 1K +Q9 N026 N040 N044 0 NP +R6 4 N044 1K +Q10 1 N019 4 0 NP m=20 +Q40 3 N009 1 0 PN m=40 +Q39 N025 N009 1 0 PN +Q11 N029 N037 N045 0 NP +Q12 N034 N037 4 0 NP +Q13 N037 N041 4 0 NP +Q14 N041 N041 4 0 NP +Q15 N033 N040 N046 0 NP +Q16 1 N038 N039 0 NP +Q17 N038 N036 N033 0 PN +R7 4 N019 1.2K +R8 4 N045 160 +R9 N029 N032 120 +R10 4 N046 1K +R11 N027 5 5K +R12 N033 3 5K +R13 N034 3 1K +Q18 N041 N034 N016 0 PN +Q19 N037 N027 N016 0 PN +R28 N036 6 200 +Q20 N032 N029 3 0 PN +Q21 4 N032 N030 0 PN m=10 +Q22 N014 N024 N030 0 NP m=10 +Q23 N024 N018 3 0 NP +C3 N027 N037 5p +Q24 N011 N022 N026 0 NP +Q25 N001 N015 N026 0 NP +Q26 N012 N020 N023 0 NP +Q27 4 N012 N009 0 PN +Q28 N023 N010 N008 0 PN +R14 3 N015 1K +R15 3 N023 5K +R16 N022 8 5K +R17 N008 1 1K +R18 N007 1 160 +R19 N024 N018 120 +R20 N006 1 1K +R21 N013 1 10 +R22 N005 1 1K +R23 N004 1 1K +R25 N003 1 1K +R26 N002 1 1K +R27 N020 7 200 +Q29 N001 N001 1 0 PN +Q30 N011 N001 1 0 PN +Q31 N015 N011 1 0 PN +Q32 N018 N011 N007 0 PN +Q33 N014 N010 N006 0 PN +Q34 N019 N014 N013 0 PN +Q35 N016 N010 N005 0 PN +Q36 N040 N010 N004 0 PN +Q37 N010 N010 N003 0 PN +Q38 N017 N010 N002 0 PN +C2 N011 N022 5p +C1 N014 N019 20p +R29 N021 N017 200 +R30 N028 N031 200 +D2 3 4 DZ_N +D1 1 3 DZ_N +C4 1 3 4p +C5 3 4 4p +D3 N010 4 D140u +R5 N010 4 1Meg +D4 1 N012 D1uA +D5 N038 4 D1uA +R24 1 N012 1Meg +R31 N038 4 1Meg +.model DZ_N D(Ron=1.5 Roff=1G vfwd=12.8 epsilon=1.5 ilimit=500m) +.model D140u D(Ron=100 Roff=1G vfwd=2.8 epsilon=100m ilimit=140u) +.model NP NPN(BF=125 Cje=.2p Cjc=.2p Rb=100 VAF=100 TF=6e-10 RC=1 RE=1) +.model PN PNP(BF=125 Cje=.2p Cjc=.2p Rb=100 VAF=100 TF=8e-10 RC=1 RE=1) +.model D1uA D(Ron=1k Roff=1k vfwd=0 ilimit=1u) +.ends LT1166 +* +.subckt LT1880 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=70f ink=80 +C2 2 1 2.7p Rpar=380.4Meg noiseless +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)+0.9, .1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)-1.09,.1), V(4)+0.89, .1)+1n*V(2) +C6 3 1 .5p Rpar=840G noiseless +C7 1 4 .5p noiseless Rpar=840G +C8 2 4 .5p Rpar=840G noiseless +C9 3 2 .5p Rpar=840G noiseless +A2 0 N003 0 0 0 0 X 0 OTA g=51.78u asym Isink=-4.15u Isrc=3u Cout=7.5p en=11n enk=10 Vhigh=1e308 Vlow=-1e308 +C10 N003 0 60f Rpar=100K noiseless +D2 2 1 DI +D1 X 3 XU +D4 4 X XD +M1 3 N004 5 5 N temp=27 +M2 4 N004 5 5 P temp=27 +C1 N004 0 6f Rpar=1Meg noiseless +C3 3 5 10p +C4 5 4 10p +D5 N004 5 YU +D6 5 N004 YD +G1 0 N004 N007 0 1µ +G3 0 N007 N008 0 1m +L1 N007 0 1.m Rser=1.02898550724638K Rpar=35.5K Cpar=33f noiseless +C11 N008 N009 1.2n +G2 0 N008 X 0 1m +R3 N008 0 1K noiseless +GFB N009 0 5 0 .1 +RFB N009 0 1 noiseless +D3 3 4 DC +.model XU D(Ron=1K Roff=65G Vfwd=0.24 epsilon=1 noiseless) +.model XD D(Ron=1K Roff=65G Vfwd=0.48 epsilon=1 noiseless) +.model YU D(Ron=1k Roff=1T Vfwd=0.628 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=0.679 epsilon=.1 noiseless) +.model N VDMOS(Vto=-240m Kp=40m) +.model P VDMOS(Vto=240m Kp=40m pchan) +.model DI D(Ron=1k Roff=100G Vfwd=60m Vrev=60m epsilon=1 revepsilon=1 noiseless) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=350u noiseless) +.ends LT1880 +* +.subckt LT317A 1 2 3 +Q27 3 N005 N009 0 NPN1BH temp=27 +Q28 N004 N009 N017 0 NPN2 +R4 N017 2 .1 noiseless +C1 N012 2 30p +Q19 N007 N006 N005 0 LPNP temp=27 +Q18 N012 N007 N005 0 LPNP temp=27 +R21 N006 N007 1.6k noiseless +Q17 N012 2 N019 0 NPN1 temp=27 +R22 N019 1 12k noiseless +C2 N012 1 30p +Q20 N007 2 N014 0 NPN1 M=10 temp=27 +R23 N014 N019 2.5k noiseless +R26 N009 2 160 noiseless +R1 0 N003 27Meg noiseless +A1 3 2 0 0 0 0 N003 0 OTA g=15n linear vlow=-1e308 vhigh=1e308 +A2 0 N003 2 2 2 2 N002 2 OTA g=22n linear ref=8.8 vlow=-1e308 vhigh=1e308 +G2 N002 2 N002 3 .1m vto=250m dir=1 +G3 2 N002 2 N002 .1m vto=-80m dir=1 +M1 2 N002 N005 N005 PM1 +C3 N010 N012 .1f Rpar=20k noiseless +C6 3 N002 .1f Rpar=100Meg noiseless +C7 N002 2 1f Rpar=100Meg noiseless +C8 3 N004 1p Rpar=220m noiseless +D1 N005 N010 DDROP +C10 0 N003 600f Rser=50k noiseless +Q1 N005 N016 2 0 NPN1BH temp=27 +C17 N005 N010 30p +A5 N015 N017 2 2 2 2 N016 2 OTA g=2.27u iout=5u Rout=10Meg Cout=1p vlow=0 vhigh=10 +D7 3 2 DB1 +D8 3 2 DB2 +D9 3 2 DB3 +C5 3 2 10p +C4 N013 N018 10p +G1 0 N013 3 2 20m +G4 0 N011 N018 0 2m +G10 0 N011 N018 0 30 vto=.1m dir=1 +G11 N011 0 0 N018 30 vto=.1m dir=1 +D4 N011 0 DD +C9 N011 0 1f +C13 N018 0 1p Rpar=100 noiseless +G5 N003 0 N008 0 100µ +G6 3 N012 N011 0 1µ +D3 N004 N005 DBIASS +D2 3 2 DBRK +C11 N008 0 60p Rser=333k Rpar=1Meg noiseless +G7 0 N008 N010 N012 1µ +C12 N013 0 10p Rpar=100 noiseless +A3 3 2 2 2 2 2 N015 2 OTA g=90n linear rout=100k cout=10f ref=18 vlow=-.12 vhigh=.08 +.model LPNP PNP(BF=100 BR=40 Is=1e-16 VAF=10 VAR=10 Cjc=1p Cje=1p noiseless) +.model NPN1 NPN(BF=100 BR=20 Is=1e-16 Cjc=.1p Cje=.1p TF=.1n noiseless) +.model NPN1BH NPN(BF=1000 BR=20 Is=1e-15 Cjc=1p Cje=1p TF=.1n noiseless) +.model NPN2 NPN(BF=100 BR=20 Is=1e-14 Cjc=10p Cje=1p TF=.1n IKF=2 Rb=2 Re=20m noiseless) +.model PM1 VDMOS(vto=1 kp=1m pchan) +.model DBIASS D(Ron=10 Roff=1g vfwd=10m epsilon=10m ilimit=300u noiseless) +.model DDROP D(Ron=100 Roff=1g vfwd=650m epsilon=100m noiseless) +.model DD D(Ron=10 Roff=100k vfwd=100 epsilon=1 vrev=100 revepsilon=1 noiseless) +.model DB1 D(Ron=100 Roff=1g Vfwd=1 epsilon=50m ilimit=800u noiseless) +.model DB2 D(Ron=25k Roff=1g Vfwd=1 epsilon=50m noiseless) +.model DB3 D(Ron=30k Roff=1g Vfwd=15 epsilon=200m noiseless) +.model DBRK D(Ron=10 Roff=1g vfwd=40.1 epsilon=100m) +.ends LT317A +* +.subckt RH101A 1 2 3 4 5 6 7 +A1 2 3 0 0 0 0 0 0 OTA g=0 in=.4p ink=55 +M1 6 N006 5 5 N temp=27 +M2 4 N006 5 5 P temp=27 +C10 N006 0 100f Rpar=1Meg noiseless +C11 6 5 .5p +C12 5 4 .5p +G2 0 N006 N009 0 1µ +R3 6 N009 100k noiseless +R4 N009 4 100k noiseless +G4 N009 6 N009 6 1m dir=1 vto=-.75 +G5 4 N009 4 N009 1m dir=1 vto=-.5 +A3 N008 4 4 4 4 4 N009 4 OTA g=5.6m iout=300u ref=1.035 Vlow=-1e308 Vhigh=1e308 +R5 7 N009 500 noiseless +C7 7 1 300f +D1 N013 4 DBIAS +Q1 6 N007 N010 0 NM1A temp=27 +Q2 6 2 N011 0 NM1A temp=27 +Q3 N014 N013 N010 0 PM1 temp=27 +Q4 1 N013 N011 0 PM1 temp=27 +C3 N013 4 10p +D6 N014 4 DBC temp=27 +C13 1 4 100f Rpar=100Meg noiseless +C14 N015 4 100f Rpar=100Meg noiseless +C15 N016 4 5p Rpar=40k noiseless +C16 N014 N015 100f Rpar=1.7k noiseless +C1 7 4 10f +M3 1 N016 4 4 NMIR +M4 N015 N016 4 4 NMIR +C6 N014 4 1p +M5 6 N014 N016 N016 NMIR +Q5 6 1 N008 0 NM1 temp=27 +C5 N009 0 10f +C9 N008 4 100f Rpar=40k noiseless +C2 N014 N016 100f +D2 N006 5 Y +D3 5 N006 Y +A2 0 0 3 3 3 3 N007 3 OTA G=.1 Rout=10 Linear Vhigh=100 Vlow=-100 en=20n enk=10 +D4 6 4 DPOW +.model DBC D(Ron=10kRoff=1g vfwd=600m epsilon=10m ilimit=200n noiseless) +.model NMIR VDMOS(Vto=700m Kp=25m) +.model N VDMOS(Vto=-200m Kp=10m) +.model P VDMOS(Vto=200m Kp=10m pchan) +.model Y D(Ron=1k Roff=1T Vfwd=2.2 epsilon=100m noiseless) +.model NM1A NPN (BF=614 Is=1e-16 tf=.3n Rb=500 Cjc=.5p Cje=.5p Vaf=100 noiseless) +.model NM1 NPN (BF=100 Is=1e-12 tf=.3n Rb=500 Cjc=.5p Cje=.5p Vaf=100 noiseless) +.model PM1 PNP (BF=1 BR=1 Xtb=1 Is=1e-16 tf=10n Cjc=1p Cje=.5p Vaf=100 noiseless) +.model DBIAS D(Ron=100 Roff=1g vfwd=500m epsilon=100m ilimit=20u noiseless) +.model DPOW D(Ron=100 Roff=1g vfwd=1.2 epsilon=100m ilimit=1.36m noiseless) +.ends RH101A +* +.subckt RH111 1 2 3 4 5 6 7 8 +B1 0 N003 I=10u*dnlim(uplim(V(2),V(8)-1.1,.1), V(4)+.2,.1)+1n*V(2)-.01n +B2 N003 0 I=10u*dnlim(uplim(V(3),V(8)-1.09,.1), V(4)+0.19, .1)+1n*V(3) +C1 N003 0 10f Rpar=3Meg +A2 0 N003 0 0 0 0 N006 0 OTA g=60u asym isource=.15u isink=-.9u Vlow=-1e308 Vhigh=1e308 +D3 8 4 DP1 +C5 8 3 3p Rpar=10g +S2 N010 7 0 N006 Sout +D2 N010 1 DDROP +S1 1 N010 8 1 Ssat +R2 8 5 1k +A1 8 5 5 5 5 5 4 5 OTA g=.62m linear Vlow=-1e308 Vhigh=1e308 ref=.389 +A3 8 6 6 6 6 6 4 6 OTA g=.62m linear Vlow=-1e308 Vhigh=1e308 ref=.389 +R3 8 6 1k +G2 0 N003 5 6 7.3µ +S4 1 8 0 N006 Sgpwr +R5 4 1 100Meg +C8 N010 1 .1p +C9 7 1 5p +D1 0 N006 DLAT1 +C2 8 7 1p +C3 3 4 3p Rpar=10g +C4 8 2 3p Rpar=10g +C6 2 4 3p Rpar=10g +D4 N003 0 DNLF +G4 0 N006 8 6 1m dir=1 vto=.3 +D5 N006 0 DLAT2 +D6 0 N003 DNLR +G1 0 N004 1 8 1m +C10 N004 0 10f Rpar=1k +C13 N007 N004 10f +R1 N007 0 100k +G3 0 N006 N007 0 1m vto=50m dir=1 +G5 N006 0 0 N007 1m vto=20m dir=1 +C12 N003 N004 1.2f +C7 0 N006 110f +S13 3 8 2 3 Sin1 +S14 3 8 2 3 Sin2 +S15 3 8 2 3 Sin3 +S19 2 8 3 2 Sin1 +S20 2 8 3 2 Sin2 +S21 2 8 3 2 Sin3 +.model DP1 D(Ron=100 Roff=1Meg Vfwd=1 epsilon=100m ilimit=3.8m) +.model DLAT1 D(Ron=100k Roff=10Meg Vfwd=.2 epsilon=30m Vrev=1 revepsilon=.1) +.model DLAT2 D(Ron=1 Roff=12Meg Vfwd=1.1 epsilon=100m) +.model DNLR D(Ron=70k Roff=1g Vfwd=4.5m epsilon=1m) +.model DNLF D(Ron=30k Roff=1g Vfwd=.2m epsilon=1m) +.model Sout SW(Roff=1G Ron=10 Vt=-100m vh=-.3 vser=.15) +.model Sgpwr SW(level=2 Roff=1Meg Ron=1 Vt=0 vh=-.2 ilimit=1m vser=1) +.model Ssat2 SW(Roff=100Meg Ron=10 vt=.5 vh=-.1) +.model Ssat SW(Roff=100Meg Ron=1 vt=2.5 vh=-1) +.model SGC SW(Ron=5k Roff=1Meg vt=500m vh=-300m) +.model DDROP D(Ron=1 Roff=1G Vfwd=1.9 epsilon=.1) +.model Sin1 SW(Roff=100g Ron=1k vt=-6 vh=-100m ilimit=60n) +.model Sin2 SW(Roff=100g Ron=1k vt=70m vh=-100m ilimit=32n) +.model Sin3 SW(Roff=100g Ron=1k vt=6 vh=-100m ilimit=60n) +.ends RH111 +* +.subckt RH27C 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.4p ink=174 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-2.6,.1), V(4)+2.6, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-2.59,.1), V(4)+2.59, .1)+1n*V(2) +C9 3 2 .1p Rpar=4g noiseless +C10 N004 0 1f Rpar=100K noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +D5 N005 5 YU +D6 5 N005 YD +G1 0 N005 N006 0 1µ +A3 0 N004 0 0 0 0 N009 0 OTA g=1m linear en=3.2n enk=2.6 Vhigh=1e308 Vlow=-1e308 +A2 0 N007 0 0 0 0 N006 0 OTA g=32m iout=1.82m Vhigh=1e308 Vlow=-1e308 +C11 N006 0 640p Rser=2 noiseless +C12 N009 0 50p Rpar=1k noiseless +G2 0 N008 N009 0 1m +D2 3 4 DC +R3 3 N006 100Meg noiseless +R4 N006 4 100Meg noiseless +G3 N006 0 N006 3 50m dir=1 vto=-1 +G5 0 N006 4 N006 50m dir=1 vto=-1.4 +L1 N008 0 41.45µ Cpar=1.06p Rser=1.56k Rpar=2.786k noiseless +G4 0 N007 N008 0 1m +C1 N005 0 1f Rpar=1Meg noiseless +C2 2 1 .1p Rpar=1.5T noiseless +C5 2 4 .1p Rpar=4g noiseless +C6 3 1 .1p Rpar=4g noiseless +C7 1 4 .1p Rpar=4g noiseless +D1 2 1 DIN +R5 3 4 25k noiseless +L2 N007 0 41.45µ Cpar=1.06p Rser=1.56k Rpar=2.786k noiseless +.model DIN D(Ron=1k Roff=10g vfwd=.7 epsilon=100m vrev=.7 revepsilon=100m noiseless) +.model YU D(Ron=30k Roff=1T Vfwd=.95 epsilon=.1 noiseless) +.model YD D(Ron=60k Roff=1T Vfwd=.87 epsilon=.1 noiseless) +.model DC D(Ron=1k, Roff=1T Vfwd=1 ilimit=1.26m noiseless) +.model N VDMOS(Vto=-200m Kp=27m) +.model P VDMOS(Vto=200m Kp=27m pchan) +.ends RH27C +* +.subckt RH37C 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.4p ink=174 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-2.6,.1), V(4)+2.6, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-2.59,.1), V(4)+2.59, .1)+1n*V(2) +C9 3 2 .1p Rpar=4g noiseless +C10 N004 0 10f Rpar=100K noiseless +M1 3 N008 5 5 N temp=27 +M2 4 N008 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +D5 N008 5 YU +D6 5 N008 YD +G1 0 N008 N009 0 1µ +A3 0 N004 0 0 0 0 N007 0 OTA g=1m iout=100u en=3.2n enk=2.6 Vhigh=1e308 Vlow=-1e308 +C11 N009 0 80p Rser=100 noiseless +C12 N007 0 390p Rpar=1k noiseless +G2 0 N005 N007 0 1m +D2 3 4 DC +R3 3 N009 100Meg noiseless +R4 N009 4 100Meg noiseless +G3 N009 0 N009 3 50m dir=1 vto=-1 +G5 0 N009 4 N009 50m dir=1 vto=-1.4 +L1 N005 0 157µ Cpar=46.4f Rser=1.04k Rpar=26k noiseless +G4 0 N006 N005 0 1m +C1 N008 0 4f Rpar=1Meg noiseless +C2 2 1 .1p Rpar=1.5T noiseless +C5 2 4 .1p Rpar=4g noiseless +C6 3 1 .1p Rpar=4g noiseless +C7 1 4 .1p Rpar=4g noiseless +D1 2 1 DIN +R5 3 4 25k noiseless +A2 0 N010 0 0 0 0 N009 0 OTA g=32m iout=1.45m Vhigh=1e308 Vlow=-1e308 +C8 N006 0 4p Rpar=1k noiseless +G6 0 N010 N006 0 1m +C13 N010 0 4p Rpar=1k noiseless +.model DIN D(Ron=1k Roff=10g vfwd=.7 epsilon=100m vrev=.7 revepsilon=100m noiseless) +.model YU D(Ron=30k Roff=1T Vfwd=.95 epsilon=.1 noiseless) +.model YD D(Ron=60k Roff=1T Vfwd=.87 epsilon=.1 noiseless) +.model DC D(Ron=1k, Roff=1T Vfwd=1 ilimit=1.26m noiseless) +.model N VDMOS(Vto=-200m Kp=27m) +.model P VDMOS(Vto=200m Kp=27m pchan) +.ends RH37C +* +.subckt RH117H 1 2 3 +Q27 3 N005 N009 0 NPN1BH temp=27 +Q28 N004 N009 N017 0 NPN2 +R4 N017 2 .1 noiseless +C1 N012 2 30p +Q19 N007 N006 N005 0 LPNP temp=27 +Q18 N012 N007 N005 0 LPNP temp=27 +R21 N006 N007 1.6k noiseless +Q17 N012 2 N019 0 NPN1 temp=27 +R22 N019 1 12k noiseless +C2 N012 1 30p +Q20 N007 2 N014 0 NPN1 M=10 temp=27 +R23 N014 N019 2.5k noiseless +R26 N009 2 160 noiseless +R1 0 N003 27Meg noiseless +A1 3 2 0 0 0 0 N003 0 OTA g=15n linear vlow=-1e308 vhigh=1e308 +A2 0 N003 2 2 2 2 N002 2 OTA g=22n linear ref=8.8 vlow=-1e308 vhigh=1e308 +G2 N002 2 N002 3 .1m vto=250m dir=1 +G3 2 N002 2 N002 .1m vto=-80m dir=1 +M1 2 N002 N005 N005 PM1 +C3 N010 N012 .1f Rpar=20k noiseless +C6 3 N002 .1f Rpar=100Meg noiseless +C7 N002 2 1f Rpar=100Meg noiseless +C8 3 N004 1p Rpar=220m noiseless +D1 N005 N010 DDROP +C10 0 N003 600f Rser=50k noiseless +Q1 N005 N016 2 0 NPN1BH temp=27 +C17 N005 N010 30p +A5 N015 N017 2 2 2 2 N016 2 OTA g=100u iout=5u Rout=10Meg Cout=1p vlow=0 vhigh=10 +D7 3 2 DB1 +D8 3 2 DB2 +D9 3 2 DB3 +C5 3 2 10p +C4 N013 N018 10p +G1 0 N013 3 2 20m +G4 0 N011 N018 0 2m +G10 0 N011 N018 0 30 vto=.1m dir=1 +G11 N011 0 0 N018 30 vto=.1m dir=1 +D4 N011 0 DD +C9 N011 0 1f +C13 N018 0 1p Rpar=100 noiseless +G5 N003 0 N008 0 100µ +G6 3 N012 N011 0 1µ +D3 N004 N005 DBIASS +D2 3 2 DBRK +C11 N008 0 60p Rser=333k Rpar=1Meg noiseless +G7 0 N008 N010 N012 1µ +C12 N013 0 10p Rpar=100 noiseless +A3 3 2 2 2 2 2 N015 2 OTA g=30n linear rout=100k cout=10f ref=42 vlow=.02 vhigh=.08 +.model LPNP PNP(BF=100 BR=40 Is=1e-16 VAF=10 VAR=10 Cjc=1p Cje=1p noiseless) +.model NPN1 NPN(BF=100 BR=20 Is=1e-16 Cjc=.1p Cje=.1p TF=.1n noiseless) +.model NPN1BH NPN(BF=1000 BR=20 Is=1e-15 Cjc=1p Cje=1p TF=.1n noiseless) +.model NPN2 NPN(BF=100 BR=20 Is=1e-14 Cjc=10p Cje=1p TF=.1n IKF=2 Rb=2 Re=20m noiseless) +.model PM1 VDMOS(vto=1 kp=1m pchan) +.model DBIASS D(Ron=10 Roff=1g vfwd=10m epsilon=10m ilimit=300u noiseless) +.model DDROP D(Ron=100 Roff=1g vfwd=650m epsilon=100m noiseless) +.model DD D(Ron=10 Roff=100k vfwd=100 epsilon=1 vrev=100 revepsilon=1 noiseless) +.model DB1 D(Ron=100 Roff=1g Vfwd=1 epsilon=50m ilimit=800u noiseless) +.model DB2 D(Ron=25k Roff=1g Vfwd=1 epsilon=50m noiseless) +.model DB3 D(Ron=30k Roff=1g Vfwd=15 epsilon=200m noiseless) +.model DBRK D(Ron=10 Roff=1g vfwd=40.1 epsilon=100m) +.ends RH117H +* +.subckt RH117K 1 2 3 +Q27 3 N005 N009 0 NPN1BH temp=27 +Q28 N004 N009 N017 0 NPN2 +R4 N017 2 .1 noiseless +C1 N012 2 30p +Q19 N007 N006 N005 0 LPNP temp=27 +Q18 N012 N007 N005 0 LPNP temp=27 +R21 N006 N007 1.6k noiseless +Q17 N012 2 N019 0 NPN1 temp=27 +R22 N019 1 12k noiseless +C2 N012 1 30p +Q20 N007 2 N014 0 NPN1 M=10 temp=27 +R23 N014 N019 2.5k noiseless +R26 N009 2 160 noiseless +R1 0 N003 27Meg noiseless +A1 3 2 0 0 0 0 N003 0 OTA g=15n linear vlow=-1e308 vhigh=1e308 +A2 0 N003 2 2 2 2 N002 2 OTA g=22n linear ref=8.8 vlow=-1e308 vhigh=1e308 +G2 N002 2 N002 3 .1m vto=250m dir=1 +G3 2 N002 2 N002 .1m vto=-80m dir=1 +M1 2 N002 N005 N005 PM1 +C3 N010 N012 .1f Rpar=20k noiseless +C6 3 N002 .1f Rpar=100Meg noiseless +C7 N002 2 1f Rpar=100Meg noiseless +C8 3 N004 1p Rpar=220m noiseless +D1 N005 N010 DDROP +C10 0 N003 600f Rser=50k noiseless +A4 3 2 2 2 2 2 N015 2 OTA g=75n linear rout=100k cout=10f ref=42 vlow=.05 vhigh=.225 +Q1 N005 N016 2 0 NPN1BH temp=27 +C17 N005 N010 30p +A5 N015 N017 2 2 2 2 N016 2 OTA g=100u iout=5u Rout=10Meg Cout=1p vlow=0 vhigh=10 +D7 3 2 DB1 +D8 3 2 DB2 +D9 3 2 DB3 +C5 3 2 10p +C4 N013 N018 10p +G1 0 N013 3 2 20m +G4 0 N011 N018 0 2m +G10 0 N011 N018 0 30 vto=.1m dir=1 +G11 N011 0 0 N018 30 vto=.1m dir=1 +D4 N011 0 DD +C9 N011 0 1f +C13 N018 0 1p Rpar=100 noiseless +G5 N003 0 N008 0 100µ +G6 3 N012 N011 0 1µ +D3 N004 N005 DBIASS +D2 3 2 DBRK +C11 N008 0 60p Rser=333k Rpar=1Meg noiseless +G7 0 N008 N010 N012 1µ +C12 N013 0 10p Rpar=100 noiseless +.model LPNP PNP(BF=100 BR=40 Is=1e-16 VAF=10 VAR=10 Cjc=1p Cje=1p noiseless) +.model NPN1 NPN(BF=100 BR=20 Is=1e-16 Cjc=.1p Cje=.1p TF=.1n noiseless) +.model NPN1BH NPN(BF=1000 BR=20 Is=1e-15 Cjc=1p Cje=1p TF=.1n noiseless) +.model NPN2 NPN(BF=100 BR=20 Is=1e-14 Cjc=10p Cje=1p TF=.1n IKF=2 Rb=2 Re=20m noiseless) +.model PM1 VDMOS(vto=1 kp=1m pchan) +.model DBIASS D(Ron=10 Roff=1g vfwd=10m epsilon=10m ilimit=300u noiseless) +.model DDROP D(Ron=100 Roff=1g vfwd=650m epsilon=100m noiseless) +.model DD D(Ron=10 Roff=100k vfwd=100 epsilon=1 vrev=100 revepsilon=1 noiseless) +.model DB1 D(Ron=100 Roff=1g Vfwd=1 epsilon=50m ilimit=800u noiseless) +.model DB2 D(Ron=25k Roff=1g Vfwd=1 epsilon=50m noiseless) +.model DB3 D(Ron=30k Roff=1g Vfwd=15 epsilon=200m noiseless) +.model DBRK D(Ron=10 Roff=1g vfwd=40.1 epsilon=100m) +.ends RH117K + diff --git a/spice/copy/sub/LTC1.lib b/spice/copy/sub/LTC1.lib new file mode 100755 index 0000000..0ed8564 --- /dev/null +++ b/spice/copy/sub/LTC1.lib @@ -0,0 +1,2617 @@ +* Copyright © Analog Devices, Inc. 2019. All rights reserved. +* +.subckt LT1011 1 2 3 4 5 6 7 8 +B1 0 N002 I=10u*dnlim(uplim(V(2),V(8)-1.25,.1),V(4)+.2,.1)-.1n +B2 N002 0 I=10u*dnlim(uplim(V(3),V(8)-1.25,.1),V(4)+.2, .1) +C1 N002 0 10f Rpar=1G noiseless +A2 0 N002 0 0 0 0 N004 0 OTA g=60u asym isource=.2u isink=-.7u Vlow=-1e308 Vhigh=1e308 +D3 8 4 DP1 +C5 8 3 3p Rpar=2.5g +D9 8 3 DBIAS +D10 8 2 DBIAS +S2 N009 7 0 N004 Sout +D2 N009 1 DDROP +S1 1 N009 8 1 Ssat +R2 8 5 1k +A1 8 5 5 5 5 5 4 5 OTA g=.62m linear Vlow=-1e308 Vhigh=1e308 ref=.389 +A3 8 6 6 6 6 6 4 6 OTA g=.62m linear Vlow=-1e308 Vhigh=1e308 ref=.389 +R3 8 6 1k +G2 0 N002 5 6 7.3µ +S4 1 8 0 N004 Sgpwr +R5 4 1 100Meg +C8 N009 1 .1p +C9 7 1 5p +D1 0 N004 DLAT1 +A4 8 1 0 0 0 0 N003 0 OTA g=500u asym isource=2.5u isink=1n Vlow=-1e308 Vhigh=1e308 ref=3 cout=1p Rout=200k +A5 N004 0 N003 0 0 0 N008 0 OTA g=3 linear Vlow=-1e308 Vhigh=1e308 cout=1f rout=1 +C11 N008 N004 110f +C2 8 7 1p +C12 N004 1 5f +C7 1 N002 1f +C3 3 4 3p Rpar=2.5g +C4 8 2 3p Rpar=2.5g +C6 2 4 3p Rpar=2.5g +D6 N002 0 DNL1 +D4 N002 0 DNL2 +G4 0 N004 8 6 1m dir=1 vto=.3 +D5 N004 0 DLAT2 +B3 0 N002 I=100u*uplim(dnlim(V(2,8)+1.4,0,.1n)*dnlim(V(3,8)+1.4,0,.1)+ dnlim(V(4,2)-.1,0,.1)*dnlim(V(4,3)-.1,0,.1),1,.1) +.model DP1 D(Ron=100 Roff=1Meg Vfwd=1 epsilon=100m ilimit=1.4m) +.model DBIAS D(Ron=10k Roff=10G Vfwd=1.35 epsilon=.1 ilimit=20n) +.model DLAT1 D(Ron=100k Roff=10Meg Vfwd=.2 epsilon=30m Vrev=1 revepsilon=.1) +.model DLAT2 D(Ron=1 Roff=10Meg Vfwd=1.1 epsilon=100m) +.model DNL1 D(Ron=100k Roff=1.3Meg Vfwd=5m epsilon=5m Vrev=20m revepsilon=5m) +.model DNL2 D(Ron=400k Vfwd=0 epsilon=1m) +.model Sout SW(Roff=1G Ron=10 Vt=0 vh=-.1 vser=.15) +.model Sgpwr SW(level=2 Roff=1Meg Ron=1 Vt=0 vh=-.2 ilimit=1.5m vser=1) +.model Ssat2 SW(Roff=100Meg Ron=10 vt=.5 vh=-.1) +.model Ssat SW(Roff=100Meg Ron=1 vt=2.5 vh=-1) +.model SGC SW(Ron=5k Roff=1Meg vt=500m vh=-300m) +.model DDROP D(Ron=1 Roff=1G Vfwd=1.9 epsilon=.1) +.ends LT1011 +* +* Pinout: IN+ IN- VCC VEE OUT LATCH +.SUBCKT LT1015 3 2 7 4 6 107 +ROUT2 6 4 1E8 +CDUM1 138 4 0.01p +CDUM2 4 3 0.01p +CIBIAS1 112 0 10p +CIBIAS2 111 0 10p +CLATCH1 140 0 10p +CPROP 135 0 7.0E-9 +CTRF 148 0 3.0E-9 +DHYST1 108 109 DSW +DHYST2 108 136 DSW +DILIM1 114 116 DSW +DILIM2 116 115 DSW +DPROP1 125 0 DIODE +DPROP2 0 125 DIODE +DPWR1 146 126 DSW +DPWR2 127 101 DSW +DVLIM1 142 121 DVLIM +DVLIM2 123 142 DVLIM +DVLIM3 145 121 DVLIM +DVLIM4 123 145 DVLIM +EGND 102 0 101 0 1 +EHYST1 109 0 118 0 1E5 +EIBIAS1 113 0 3 2 100 +EILIM1 117 0 116 0 100 +EIN 139 0 118 0 1 +EINCM1 105 0 3 0 1 +EINCM2 106 0 2 0 1 +ELATCH1 120 0 142 143 0.1 +ELDO1 121 0 146 122 1 +ELDO2 123 0 101 124 1 +EOM 144 0 143 0 1 +ETRF 128 0 145 0 1 +EVCC1 132 0 7 0 1 +EVEE1 134 0 4 0 1 +EVS 147 0 146 0 1 +GCMRR 0 118 137 141 1.0E-5 +GGAIN 0 145 135 0 1 +GHYST2 0 125 136 0 1 +GIBIAS1 3 0 111 0 1E-6 +GIBIAS2 2 0 112 0 1E-6 +GILIM1 0 114 142 119 1E4 +GILIM2 115 0 119 142 1E4 +GILIM3 0 149 148 117 1 +GIN 0 118 3 138 1 +GOUT 0 142 149 144 2 +GPROP 0 125 140 0 2511.89 +GPSRRN 0 118 4 141 1.0E-5 +GPSRRP 0 118 7 141 1.0E-5 +GPWRO1 126 0 142 119 10 +GPWRO2 127 0 142 119 10 +IHYST2 0 108 125.594 +IIBIAS 0 110 1.5E+1 +ILIM1 114 0 1.5E+2 +ILIM2 0 115 1.5E+2 +IOS 3 2 1.0E-7 +ITYP1 7 0 3.3E-2 +ITYP2 0 4 3.3E-2 +IVOS 0 118 1.0E-3 +RDUM1 130 119 0.001 +RHYST2 108 0 1k +RHYST3 136 0 1 +RIBIAS1 112 0 1 +RIBIAS2 111 0 1 +RIBIAS3 110 112 10k +RILIM 119 142 0.1 +RILIM1 116 0 1 +RILIM2 114 0 1 +RILIM3 115 0 1 +RILIM4 149 0 1 +RIN 118 0 1 +RINCM1 137 105 1 +RINCM2 106 137 1 +RLATCH 7 107 1E9 +RLATCH1 140 0 1 +RMID1 141 132 1 +RMID2 134 141 1 +ROUT 144 142 1 +ROX 145 0 1000 +RPROP1 125 0 1 +RPROP2 135 125 1.307 +RPWR1 126 147 1E3 +RPWR2 127 102 1E3 +RSHD7 130 6 1E-4 +RTRF 148 128 0.63662 +RVCC 7 146 1E-4 +RVEE 4 101 1E-4 +RVNOI 138 2 603865 +RVOM1 143 147 1 +RVOM2 102 143 1 +SIBIAS1 111 110 113 0 SWBIAS +SLATCH1 140 139 107 134 SWLATCH +SLATCH2 140 120 107 134 SWLATCHX +VLDO1 122 0 2.9557 +VLDO2 0 124 1.8557 +.MODEL SWHYST VSWITCH(ROFF=1E5 RON=1E-4 VON=1 VOFF=-1) +.MODEL SWLATCH VSWITCH(ROFF=1E7 RON=1E-4 VON=1.80 VOFF=2.2) +.MODEL SWLATCHX VSWITCH(ROFF=1E7 RON=1E-4 VON=2.20 VOFF=1.8) +.MODEL SWBIAS VSWITCH(ROFF=1E7 RON=1E-4 VON=2 VOFF=-2) +.MODEL SHDN VSWITCH(ROFF=1G RON=0.1 VON=1.80 VOFF=2.0) +.MODEL SHDNX VSWITCH(ROFF=1E7 RON=0.001 VON=2.00 VOFF=1.8) +.MODEL SHDNO VSWITCH(ROFF=1000000 RON=0.001 VON=1.80 VOFF=2.0) +.MODEL SHDNOX VSWITCH(ROFF=1000000 RON=0.001 VON=2.00 VOFF=1.80) +.MODEL DSW D(IS=1E-10 RS=0 XTI=0 KF=0) +.MODEL DIODE D(IS=1E-18 KF=0 XTI=0 RS=1E-8) +.MODEL DVLIM D(IS=1E-24 KF=0 RS=0 XTI=0) +.ENDS LT1015 +* +.subckt LT1017 1 2 3 4 5 +B1 0 N002 I=10u*dnlim(uplim(V(1),V(3)-.6,.1), V(4)-.35,.1)+1n*V(1)-.53n +B2 N002 0 I=10u*dnlim(uplim(V(2),V(3)-.59,.1), V(4)-.36, .1)+1n*V(2) +C1 N002 0 1f Rpar=100K noiseless +A1 0 N002 0 0 0 0 N009 0 OTA g=11m iout=1.1m Vlow=-1e308 Vhigh=1e308 Cout=1p +C5 3 5 5p +C6 5 4 15p +D5 0 N009 DLAT +C4 2 4 .1p +C10 1 4 .1p +C11 3 2 .1p +C12 3 1 .1p +D2 2 1 DBIASC +D6 1 4 DBIAS +D9 2 4 DBIAS +M1 5 N008 N011 N011 N temp=27 +D1 N011 4 DOUTN1 +D7 N011 4 DOUTN3 +D8 N011 4 DOUTN2 +D10 3 N003 DOUTP +D11 4 N007 XD +C2 5 N008 3e-17 Rser=1G +D15 N008 N007 DASYM +R2 N008 4 100G +C7 N008 0 1e-16 +G2 4 N007 0 N009 25n +C8 N007 4 320f +R3 3 4 4Meg +GP1 3 4 N011 4 2m +C9 N011 4 1p +C13 3 N003 1p +D3 3 5 DTRICKLE +SW1 4 N004 5 4 SPFB +M3 5 N004 N003 N003 P temp=27 +D12 3 N004 DLIMP +C3 3 N004 5p Rpar=10Meg +D4 4 5 DSI temp=27 +G1 3 4 3 N004 100µ +.model DBIAS D(Ron=1k Roff=10G Vfwd=1 epsilon=.1 ilimit=3n) +.model DBIASC D(Ron=20Meg Roff=10G Vfwd= 1u Vrev=1u ++ epsilon=10u revepsilon=10u ilimit=3n revilimit=3n) +.model XD D(Ron=1k Roff=1G Vfwd=1.2 Vrev=1 epsilon=.1 revepsilon=.1) +.model DLAT D(Ron=100 Roff=10k Vfwd=2.4 Vrev=1.9 epsilon=2.1 revepsilon=1.6) +.model N VDMOS(Vto=100m kp=1.5 rds=200Meg) +.model DOUTN1 D(Vfwd=5m Ron=2k Roff=100k epsilon=.1m) +.model DOUTN2 D(Vfwd=25m Ron=35 Roff=100k epsilon=10m) +.model DOUTN3 D(Vfwd=55m Ron=2 Roff=100k epsilon=20m ilimit=55m Vrev=-55m revepsilon=20m ) +.model DSI D(cjo=130p m=.5 vj=1 is=1e-30 n=5) +.model DASYM D(Ron=1G Roff=2G Vfwd=0 epsilon=100m) +.model SPFB sw(Ron=10Meg Roff=1G vt=.19 vh=-.05) +.model DTRICKLE D(Ron=1k Roff=50Meg Vfwd=.5 ilimit=4u epsilon=.1) +.model P VDMOS(Vto=-20m kp=18m rds=100Meg pchan) +.model DLIMP D(Vfwd=.2 Ron=10k Roff=1G epsilon=.1) +.model DOUTP D(Vfwd=39m Ron=1k Roff=1G epsilon=10m Vrev=-39m revepsilon=10m) +.ends LT1017 +* +.subckt LT1018 1 2 3 4 5 +B1 0 N002 I=10u*dnlim(uplim(V(1),V(3)-.6,.1), V(4)-.35,.1)+1n*V(1)-583p +B2 N002 0 I=10u*dnlim(uplim(V(2),V(3)-.59,.1), V(4)-.36, .1)+1n*V(2) +C1 N002 0 1f Rpar=100K noiseless +A1 0 N002 0 0 0 0 N009 0 OTA g=11m iout=1.1m Vlow=-1e308 Vhigh=1e308 Cout=1p +C5 3 5 1p +C6 5 4 15p +D5 0 N009 DLAT +C4 2 4 .1p +C10 1 4 .1p +D13 3 4 DP +C11 3 2 .1p +C12 3 1 .1p +D2 2 1 DBIASC +D6 1 4 DBIAS +D9 2 4 DBIAS +M1 5 N008 N011 N011 N temp=27 +D7 N011 4 DOUTN3 +D8 N011 4 DOUTN2 +D10 3 N003 DOUTP +M2 5 N004 N003 N003 P temp=27 +D11 4 N007 XD +D14 4 5 DSI TEMP=27 +C2 5 N008 7e-17 Rser=1G +D15 N008 N007 DASYM +R2 N008 4 100G +C7 N008 0 5e-16 +G2 0 N007 0 N009 25n +C8 N007 4 55f +R3 3 4 3.5Meg +GP1 3 4 N011 4 4m +C9 N011 4 1p Rpar=1K +C13 3 N003 1p +SW1 4 N004 5 4 SPFB +C3 3 N004 3p Rpar=10Meg +D1 3 N004 DLIMP +D3 3 5 DTRICKLE +G3 3 4 3 N004 135µ +.model DP D(Ron=100 Roff=1Meg Vfwd=1 ilimit=56u) +.model DBIAS D(Ron=1k Roff=10G Vfwd=1 epsilon=.1 ilimit=3n) +.model DBIASC D(Ron=20Meg Roff=10G Vfwd= 1u Vrev=1u ++ epsilon=10u revepsilon=10u ilimit=3n revilimit=3n) +.model XD D(Ron=1k Roff=1G Vfwd=1.2 Vrev=1 epsilon=.1 revepsilon=.1) +.model DLAT D(Ron=100 Roff=10k Vfwd=2.4 Vrev=1.9 epsilon=2.1 revepsilon=1.6) +.model N VDMOS(Vto=100m kp=1.5 rds=100Meg) +.model DOUTN2 D(Vfwd=25m Ron=35 Roff=100k epsilon=10m Vrev=-25m revepsilon=10m) +.model DOUTN3 D(Vfwd=55m Ron=2 Roff=100k epsilon=20m ilimit=55m ) +.model P VDMOS(Vto=-20m kp=25.1m rds=200Meg pchan ) +.model DOUTP D(Vfwd=39m Ron=100 Roff=1G epsilon=10m Vrev=-39m revepsilon=10m) +.model DLIMP D(Vfwd=.2 Ron=10k Roff=1G epsilon=.1) +.model DSI D( cjo= 130p m=.5 vj=1 is=1e-30 n=5) +.model DASYM D(Ron=1G Roff=2G Vfwd=0 epsilon=100m) +.model SPFB sw(Ron=10Meg Roff=1G vt=.15 vh=-.05) +.model DTRICKLE D(Ron=1k Roff=50Meg Vfwd=.5 ilimit=9u epsilon=.1) +.ends LT1018 +* +.subckt LT1711 1 2 3 4 5 6 7 8 +A3 8 5 0 0 0 0 LE 0 SCHMITT Vt=1.6 Vh=100m tau=1n +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2 ,.1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C1 N003 0 .01f Rpar=100K noiseless +A1 0 N003 0 0 0 0 N005 0 OTA g=6m iout=500u Vlow=-1e308 Vhigh=1e308 Cout=1f +R1 8 5 333k +M1 6 N010 5 5 NI temp=27 +M2 6 N006 3 3 PI temp=27 +C5 3 6 .5p +C6 6 5 .5p +D5 0 N005 DLAT +A2 N013 0 LE 0 0 0 N005 0 OTA g=1m linear Vlow=-1e308 Vhigh=1e308 +D1 0 N013 DLAT +C3 N013 0 1f +G3 0 N013 0 N005 1m +R2 3 N002 1k +R3 N002 4 4k +D2 N002 2 DBOUT1 +D6 N002 2 DBOUT2 +D9 2 N002 DBIN +D10 N012 1 DBOUT1 +D11 N012 1 DBOUT2 +D12 1 N012 DBIN +C4 2 4 .5p +C10 1 4 .5p +C11 4 5 .5p +C12 N002 5 5p +R4 3 N012 1k +R5 N012 4 4k +C13 N012 5 5p +D13 3 4 DP1 +D14 3 5 DP2 +G1 0 N004 5 0 .5m +G2 0 N004 3 0 .5m +C2 N004 0 200p Rpar=1K noiseless +A4 N005 0 N004 N004 N004 N004 N007 N004 OTA g=7n linear cout=.037f ref=430m rout=50Meg Vlow=-1e308 Vhigh=1e308 +D4 3 N006 DLIMP +C7 3 N006 .05f Rser=1Meg noiseless +A5 N004 N007 5 5 5 5 N006 5 OTA g=20n ref=-299m linear vlow=-1e308 vhigh=1e308 +G4 5 N010 N007 N004 20n +C8 N010 5 .05f Rser=1Meg noiseless +D7 N010 5 DLIMN +C9 N006 6 .002f +C14 6 N010 .002f +M3 7 N018 5 5 NI temp=27 +M4 7 N014 3 3 PI temp=27 +C15 3 7 .5p +C16 7 5 .5p +A6 0 N005 N004 N004 N004 N004 N015 N004 OTA g=7n linear cout=.037f ref=430m rout=50Meg Vlow=-1e308 Vhigh=1e308 +D3 3 N014 DLIMP +C17 3 N014 .05f Rser=1Meg noiseless +A7 N004 N015 5 5 5 5 N014 5 OTA g=20n ref=-299m linear vlow=-1e308 vhigh=1e308 +G5 5 N018 N015 N004 20n +C18 N018 5 .05f Rser=1Meg noiseless +D8 N018 5 DLIMN +C19 N014 7 .002f +C20 7 N018 .002f +B3 N005 0 I=if(time<1e-12 & V(LE) > .5,if(V(1,2)>0,-1m,1m),0) +.model NI VDMOS(Vto=300m kp=2 mtriode=.15 rds=1Meg) +.model PI VDMOS(Vto=-300m Kp=1.8 mtriode=.15 rds=1Meg pchan) +.model DBIN D(Ron=50k Roff=1G Vfwd=0 epsilon=.1 ilimit=1.9u) +.model DBOUT1 D(Ron=100k Roff=1G Vfwd=0 epsilon=.1 ilimit=2u) +.model DBOUT2 D(Ron=600k Roff=1G Vfwd=.4 epsilon=.1) +.model DLAT D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=540m Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=540m Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DP1 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=6m) +.model DP2 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=7m) +.ends LT1711 +* +.subckt LT1713 1 2 3 4 5 6 7 8 +A3 8 5 0 0 0 0 N018 0 SCHMITT Vt=1.6 Vh=100m tau=1n +B1 0 N003 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2 ,.1)+1n*V(1) +B2 N003 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C1 N003 0 1f Rpar=100K noiseless +A1 0 N003 0 0 0 0 N008 0 OTA g=15m iout=100u Vlow=-1e308 Vhigh=1e308 Cout=1f +C2 N005 0 .04f +R1 8 5 333k +M1 6 N005 N009 N009 NI temp=27 +M2 6 N005 N004 N004 PI temp=27 +C5 3 6 5p +C6 6 5 5p +G5 0 N014 N008 0 65n +D5 0 N008 DLAT +G2 0 N005 0 N008 65n +A2 N012 0 N018 0 0 0 N008 0 OTA g=10m linear Vlow=-1e308 Vhigh=1e308 +D1 0 N012 DLAT +C3 N012 0 1p +G3 0 N012 0 N008 10m +R2 3 N002 2k +R3 N002 4 8k +D2 N002 2 DBOUT1 +D6 N002 2 DBOUT2 +D9 2 N002 DBIN +D10 N011 1 DBOUT1 +D11 N011 1 DBOUT2 +D12 1 N011 DBIN +C4 2 4 .5p +C10 1 4 .5p +C11 4 5 .5p +C12 N002 5 5p +R4 3 N011 2k +R5 N011 4 8k +C13 N011 5 5p +D13 3 4 DP1 +D14 3 5 DP2 +R6 3 N005 590Meg +R7 N005 5 537Meg +D3 N005 3 DSIU temp=27 +D7 5 N005 DSID temp=27 +D15 3 N004 DILIMU +D17 N011 1 DBOUT3 +D18 N002 2 DBOUT3 +D19 N009 5 DILIMD +C14 6 N005 .016f +C7 N014 0 .04f +M3 7 N014 N017 N017 NI temp=27 +M4 7 N014 N013 N013 PI temp=27 +C8 3 7 5p +C9 7 5 5p +R8 3 N014 590Meg +R9 N014 5 537Meg +D4 N014 3 DSIU temp=27 +D8 5 N014 DSID temp=27 +D16 3 N013 DILIMU +D20 N017 5 DILIMD +C15 7 N014 .016f +C16 3 N004 100f +C17 N009 5 100f +C18 3 N013 100f +C19 N017 5 100f +.model DLAT D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9) +.model DILIMU D(Ron=10 Roff=1k Vfwd=120m ilimit=42m epsilon=50m Vrev=-120m revepsilon=50m) +.model DILIMD D(Ron=10 Roff=1k Vfwd=110m ilimit=50m epsilon=50m Vrev=-110m revepsilon=50m) +.model DSIU D(Is=1e-10 N=1 TT=6.5e-9) +.model DSID D(Is=1e-10 N=1 TT=6.2e-9) +.model NI VDMOS(Vto=100m kp=160m mtriode= .1 rds=10k) +.model PI VDMOS(Vto=-80m Kp=160m mtriode=.1 rds=10k pchan) +.model DP1 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=2m) +.model DP2 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=1.05m) +.model DBIN D(Ron=50k Roff=1G Vfwd=0 epsilon=.1 ilimit=1u) +.model DBOUT1 D(Ron=100k Roff=1G Vfwd=0 epsilon=.1 ilimit=.9u) +.model DBOUT2 D(Ron=1.7Meg Roff=1G Vfwd=.4 epsilon=.1) +.model DBOUT3 D(Ron=100k Roff=1G Vfwd=2.4 epsilon=.1 ilimit = 600n) +.ends LT1713 +* +.subckt LT1715 1 2 3 4 5 6 7 +B1 0 N002 I=10u*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)-.2 ,.1)+1n*V(1)+144n*V(VDH) +B2 N002 0 I=10u*dnlim(uplim(V(2),V(3)-1.09,.1), V(4)-.21, .1)+1n*V(2) +C1 N002 0 1f Rpar=100K +A1 0 N002 0 0 0 0 VDH 0 OTA g=10m iout=100u Vlow=-1e308 Vhigh=1e308 Cout=30f +D5 0 VDH DLAT +C4 2 4 .2p +C10 1 4 .2p +C11 4 6 2p +D13 3 4 DP1 +D14 5 4 DP2 +M3 7 N009 N010 N010 NI temp=27 +M4 7 N007 N005 N005 PI temp=27 +C7 5 7 1p +C8 7 6 1p +D8 5 N005 DILIMU +D16 N010 6 DILIMD +C9 5 N005 100f +C14 N010 6 100f +R7 N009 6 2G +D3 N009 6 DSIONN temp=27 +D7 6 N009 DSIOFFN temp=27 +G2 0 N009 0 VDH 90n +C2 7 N009 .035f +D1 N007 5 DSIOFFP temp=27 +D15 5 N007 DSIONP temp=27 +R1 5 N007 2G +C15 N007 7 .04f +A2 VDH 0 0 0 0 0 N009 0 OTA g=30n asym isource=0 isink=-100n Vlow=-1e308 Vhigh=1e308 Cout=.05f +A3 VDH 0 0 0 0 0 N007 0 OTA g=40n asym isource=100n isink=0 Vlow=-1e308 Vhigh=1e308 Cout=.08f +C5 3 2 .2p +C6 3 1 .2p +D2 3 2 DBIAS +D4 3 1 DBIAS +D6 1 2 DBIASC +D9 5 6 DP3 +C12 5 3 2p +G3 0 N007 0 VDH 90n +.model DLAT D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9) +.model DILIMU D(Ron=3 Roff=100k Vfwd=130m ilimit=30m epsilon=50m Vrev=-130m revepsilon=50m) +.model DILIMD D(Ron=3 Roff=100k Vfwd=130m ilimit=40m epsilon=50m Vrev=-130m revepsilon=50m) +.model DSIONN D(Is=1e-30 N=2 TT=8e-10) +.model DSIOFFN D(Is=1e-10 N=1 TT= 1.1e-9) +.model DSIONP D(Is=1e-30 N=2 TT=3e-10) +.model DSIOFFP D(Is=1e-10 N=1 TT=1.1e-9) +.model NI VDMOS(Vto=100m kp=600m mtriode= .1 rds=10k) +.model PI VDMOS(Vto=-100m Kp=300m mtriode=.1 rds=10k pchan) +.model DP1 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=1m epsilon=.1) +.model DP2 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=1.9m epsilon=.1) +.model DP3 D(Ron=100 Roff=1Meg Vfwd=1 ilimit=2.23m epsilon=.1) +.model DBIAS D(Ron=1k Roff=10G Vfwd=1 epsilon=.1 ilimit=2.5u) +.model DBIASC D(Ron=10k Roff=10G Vfwd= 1u Vrev=1u ++ epsilon=10u revepsilon=10u ilimit=2.5u revilimit=2.5u) +.ends LT1715 +* +.subckt LT1716 1 2 3 4 5 +B1 0 N002 I=10u*dnlim(uplim(V(1),V(4)+44,.1), V(4)-.6,.1)+1n*V(1)-370p +B2 N002 0 I=10u*dnlim(uplim(V(2),V(4)+44.1,.1), V(4)-.61, .1)+1n*V(2) +C1 N002 0 1f Rpar=100K noiseless +A1 0 N002 0 0 0 0 N009 0 OTA g=11m iout=1.1m Vlow=-1e308 Vhigh=1e308 Cout=1p +C5 3 5 5p +C6 5 4 5p +D5 0 N009 DLAT +C4 2 4 .1p +C10 1 4 .1p +C11 3 2 .1p +C12 3 1 .1p +D2 2 1 DBIASC +D6 3 1 DBIAS +D9 3 2 DBIAS +M1 5 N008 N011 N011 N temp=27 +D7 N011 4 DOUTN2 +D8 N011 4 DOUTN1 +D10 3 N003 DOUTP +D11 4 N007 XD +C2 5 N008 2.3e-16 Rser=1G +D15 N008 N007 DASYM +R2 N008 4 100G +C7 N008 0 1e-16 +G2 4 N007 0 N009 55n +C8 N007 4 40f +GP1 3 4 N011 4 100µ +C9 N011 4 1p Rpar=100Meg +C13 3 N003 1p +D3 3 5 DTRICKLE +SW1 4 N004 5 4 SPFB +M3 5 N004 N003 N003 P temp=27 +D12 3 N004 DLIMP +C3 3 N004 1p Rpar=10Meg +D4 4 5 DSI temp=27 +D1 3 4 DP +.model DP D(Ron=10k Roff=1G Vfwd=2 epsilon=.1 ilimit=34.4u) +.model DBIAS D(Ron=1k Roff=10G Vfwd=0 epsilon=.1 ilimit=1.75n) +.model DBIASC D(Ron=10Meg Roff=10G Vfwd= 1u Vrev=1u ++ epsilon=10u revepsilon=10u ilimit=1.75n revilimit=1.75n) +.model XD D(Ron=1k Roff=1G Vfwd=2.5 Vrev=2.5 epsilon=.1 revepsilon=.1) +.model DLAT D(Ron=100 Roff=10k Vfwd=1 Vrev=1.3 epsilon=.9 revepsilon=1.2) +.model N VDMOS(Vto=100m kp=63m rds=200Meg) +.model DOUTN1 D(Vfwd=15m Ron=500 Roff=100k epsilon=10m Vrev=0 revepsilon=10m) +.model DOUTN2 D(Vfwd=75m Ron=90 Roff=100k epsilon=20m) +.model DSI D(cjo=70p m=.5 vj=1 is=1e-30 n=5) +.model DASYM D(Ron=2.5G Roff=2G Vfwd=0 epsilon=100m) +.model SPFB sw(Ron=10Meg Roff=10G vt=.2 vh=-.05) +.model DTRICKLE D(Ron=1k Roff=50Meg Vfwd=.5 ilimit=5.5u epsilon=.1) +.model P VDMOS(Vto=-20m kp=18m rds=100Meg pchan) +.model DLIMP D(Vfwd=.26 Ron=10k Roff=1G epsilon=.1) +.model DOUTP D(Vfwd=29m Ron=1.6k Roff=1G epsilon=10m Vrev=-29m revepsilon=10m) +.ends LT1716 +* +.subckt LT1794 1 2 3 4 5 6 7 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=800f ink=100 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+.89, .1)+1n*V(2) +C6 3 1 1.5p Rpar=100Meg noiseless +C7 1 4 1.5p noiseless Rpar=100Meg +C8 2 4 1.5p Rpar=100Meg noiseless +C9 3 2 1.5p Rpar=100Meg noiseless +A2 0 N006 0 0 0 0 N008 0 OTA g=1m linear Cout=900f Vhigh=1e308 Vlow=-1e308 +C10 N004 0 10f Rpar=100k noiseless +M1 3 N005 N007 N007 N temp=27 +M2 4 N005 N013 N013 P temp=27 +C3 3 5 2p +C4 5 4 2p +D5 N005 N007 Y +A3 0 N004 0 0 0 0 N006 0 OTA g=1m linear en=8n enk=4 Rout=1k Cout=4p Vlow=-560m Vhigh=560m +G2 0 N005 N008 0 1µ +G5 N008 0 N008 3 500m dir=1 vto=-.3 +G6 0 N008 4 N008 500m dir=1 vto=-.3 +D4 N009 7 DSREF +D7 4 7 DPAR +C1 N009 7 500f +C11 N005 0 3f Rpar=1Meg noiseless +S1 5 N013 6 N009 SRO +S2 N007 5 6 N009 SRO +S3 N006 0 N009 6 SSLEWL +R2 3 N008 20Meg noiseless +C2 N007 5 2p +C12 5 N013 2p +S4 N006 N011 N009 6 SPOLE +C13 N011 0 40p +R3 N008 4 20Meg noiseless +R6 2 1 6.9Meg noiseless +G1 N009 4 6 N009 330µ +C14 6 7 500f +D1 N013 N005 Y +A5 6 N009 4 4 4 4 3 4 OTA g=14.2m asym isink=-35m isource=10u ref=.1 Vlow=-1e308 Vhigh=1e308 +R1 N009 6 1.8k noiseless +D2 3 4 DC +.model Y D(Ron=100 Roff=1T Vfwd=1.14 epsilon=.1 noiseless) +.model N VDMOS(Vto=-50m Kp=1) +.model P VDMOS(Vto=50m Kp=1 pchan) +.model DC D(Ron=10k Roff=1Meg vfwd=2 ilimit=21.4u noiseless) +.model DSREF D(Ron=1 Roff=100Meg vfwd=1.2 epsilon=2 noiseless) +.model DPAR D(Ron=10 Roff=1G vfwd=.7 epsilon=100m noiseless) +.model SRO SW(Ron=.1 Roff=1.2k vt=.7 vh=-1.2 noiseless) +.model SQC SW(level=2 Ron=400 Roff=1G vt=1.5 vh=-300m ilimit=40m noiseless) +.model SSLEWL SW(Ron=50 Roff=100k vt=-.3 vh=-.8 noiseless) +.model SPOLE SW(Ron=1 Roff=100k vt=-.2 vh=-.8 noiseless) +.ends LT1794 +* +.subckt LT1970 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 +A1 0 N008 N007 0 0 0 N009 0 OTA g=150u Iout=16.2u Cout=10p en=15n enk=4 Vhigh=1e308 Vlow=-1e308 +A2 8 9 0 0 0 0 0 0 OTA g=0 in=3p ink=70 +C2 N008 0 .5p Rpar=100K noiseless +R1 7 N009 50Meg noiseless +R2 N009 1 50Meg noiseless +C7 19 3 .2p Rpar=200k noiseless +B1 0 N008 I=10u*dnlim(uplim(V(9),V(7)-1.3,.1), V(1)+.4, .1)+1n*V(9) +B2 N008 0 I=10u*dnlim(uplim(V(8),V(7)-1.299,.1), V(1)+.399, .1)+1n*V(8) +C9 7 9 .5p Rpar=700Meg noiseless +G1 0 N013 4 5 10m +R6 N013 0 1K +A4 N013 N015 N007 0 0 0 N014 0 OTA g=2.5m Isrc=100n Isink=-170u asym Vhigh=1e308 Vlow=-1e308 +B3 0 N015 I=1m*dnlim(V(13,14), 40m, 10m) +R10 N015 0 1K +A3 N013 N018 N007 0 0 0 N017 0 OTA g=2.5m Isrc=170u Isink=-100n asym Vhigh=1e308 Vlow=-1e308 +B4 0 N018 I=-1m*dnlim(V(12,14), 40m, 10m) +R9 N018 0 1K +C1 12 14 1p +C3 13 14 1p +C11 4 14 1p +C12 6 14 1p +S1 17 14 N017 N009 Ilim +S2 16 14 N009 N014 Ilim +C13 15 14 1p +A6 15 14 0 0 0 0 N007 0 SCHMITT Vt=1 Vh=1m Tau=500n +C14 5 14 1p +C15 17 14 1p +C16 16 14 1p +C18 N014 N009 10p Rpar=8K +C17 N017 N009 10p Rpar=8K +A5 13 12 N007 0 0 0 4 0 OTA G=55u Iout=250u Vhigh=1e308 Vlow=-1e308 +D2 1 12 200nA +D3 1 13 200nA +C4 9 1 .5p Rpar=700Meg noiseless +C6 8 1 .5p Rpar=700Meg noiseless +C10 7 8 .5p Rpar=700Meg noiseless +C5 8 9 1p Rpar=101K noiseless +M1 19 N006 3 3 N temp=27 +M2 2 N012 3 3 P temp=27 +D1 N006 3 Y +D4 3 N012 Y +A7 N005 0 N009 N009 N009 N009 N006 N009 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-20 Rout=100k Cout=1p +A8 N005 0 N009 N009 N009 N012 N009 N009 SCHMITT Vt=.5 Vh=10m Vhigh=20 Vlow=0 Rout=100k Cout=1p +C19 3 N009 50f Rser=100k noiseless +G2 N009 0 N009 7 100m dir=1 vto=.01 +G3 0 N009 1 N009 100m dir=1 vto=.01 +S3 7 1 N007 0 swPow +S4 7 8 N007 0 sbias +S5 7 9 N007 0 sbias +C8 3 2 .2p Rpar=200k noiseless +A9 N007 0 0 0 0 0 N005 0 BUF Trise=100n Tfall=5u +R7 6 5 1K +.model Ilim SW(Ron=100 Roff=1G Vt=50m Vh=-5m) +.model 200nA D(Ron=2Meg Ilimit=200n epsilon=.6) +.model Sbias SW(level=2 Ron=10k Roff=1G Vt=.5 Vh=-.1 ilimit=160n noiseless) +.model SwPow SW(level=2 Ron=1k Roff=95k ilimit=3m Vt=.5 Vh=-.1 noiseless) +.model Y D(Ron=100 Roff=1T Vfwd=1.455 epsilon=.1 noiseless) +.model N VDMOS(Vto=-110m Kp=650m rds=200k) +.model P VDMOS(Vto=110m Kp=650m rds=200k pchan) +.ends LT1970 +* +.subckt LT1991 1 2 3 4 5 6 7 8 9 10 +B1 0 N006 I=10u*dnlim(uplim(V(VINP),V(7)-1.1,.1), V(4)+.9, .1)+1n*V(VINP) +B2 N006 0 I=10u*dnlim(uplim(V(VINM),V(7)-1.09,.1), V(4)+.89, .1)+1n*V(VINM) +C6 7 VINP .5p Rpar=4T noiseless +C7 VINP 4 .5p noiseless Rpar=4T +C8 VINM 4 .5p Rpar=4T noiseless +C9 7 VINM .5p Rpar=4T noiseless +A2 0 N006 0 0 0 0 N008 0 OTA g=5m iout=145u cout=1.2n en=16n enk=5 Vhigh=1e308 Vlow=-1e308 +C10 N006 0 2f Rpar=100K noiseless +M1 7 N005 6 6 N temp=27 +M2 4 N005 6 6 P temp=27 +C1 N005 0 3.2p Rpar=1Meg noiseless +C3 7 6 .5p +C4 6 4 .5p +D5 N005 6 YU +D6 6 N005 YD +G1 0 N005 N008 0 1µ +D2 7 4 DP +R1 VINM 10 450k +R6 7 N008 1G noiseless +R12 N008 4 1G noiseless +G2 N008 0 N008 7 500m dir=1 vto=-50m +G3 0 N008 4 N008 500m dir=1 vto=-50m +R13 7 4 833k noiseless +R2 VINP 1 450k +C2 6 VINM 4p Rpar=450k +A1 VINM VINP 0 0 0 0 0 0 OTA g=0 in=45f ink=5 +R3 VINM 9 150k +R4 VINM 8 50k +R5 VINP 2 150k +R7 VINP 3 50k +C11 VINP 5 4p Rpar=450k +D1 VINP 4 DBIAS +D3 VINM 4 DBIAS +C12 9 4 10f +C13 10 4 10f +C14 8 4 10f +C15 1 4 10f +C16 4 2 10f +C17 4 3 10f +.model X D(Ron=1K Roff=100G Vfwd=-.95 epsilon=1.0 noiseless) +.model YU D(Ron=500 Roff=1T Vfwd=.55 epsilon=0.1 noiseless) +.model YD D(Ron=500 Roff=1T Vfwd = .75 epsilon=0.1 noiseless) +.model N VDMOS(Vto=-35m Kp=70m) +.model P VDMOS(Vto=35m Kp=70m pchan) +.model DP D(Ron=1k Roff=1T Vfwd=0.7 ilimit=51.12u noiseless) +.model DBIAS D(Ron=1k Roff=1T Vfwd=.7 ilimit=2.5n noiseless) +.ends LT1991 +* +.subckt LT1996 1 2 3 4 5 6 7 8 9 10 +B1 0 N006 I=10u*dnlim(uplim(V(VINP),V(7)-1.1,.1), V(4)+.9, .1)+1n*V(VINP) +B2 N006 0 I=10u*dnlim(uplim(V(VINM),V(7)-1.09,.1), V(4)+.89, .1)+1n*V(VINM) +C6 7 VINP .5p Rpar=4T noiseless +C7 VINP 4 .5p noiseless Rpar=4T +C8 VINM 4 .5p Rpar=4T noiseless +C9 7 VINM .5p Rpar=4T noiseless +A2 0 N006 0 0 0 0 N008 0 OTA g=5m iout=145u cout=1.2n en=16n enk=5 Vhigh=1e308 Vlow=-1e308 +C10 N006 0 2f Rpar=100K noiseless +M1 7 N005 6 6 N temp=27 +M2 4 N005 6 6 P temp=27 +C1 N005 0 3.2p Rpar=1Meg noiseless +C3 7 6 .5p +C4 6 4 .5p +D5 N005 6 YU +D6 6 N005 YD +G1 0 N005 N008 0 1µ +D2 7 4 DP +R1 VINM 10 50k +R6 7 N008 1G noiseless +R12 N008 4 1G noiseless +G2 N008 0 N008 7 500m dir=1 vto=-50m +G3 0 N008 4 N008 500m dir=1 vto=-50m +R13 7 4 833k noiseless +R2 VINP 1 50k +C2 6 VINM 4p Rpar=450k +A1 VINM VINP 0 0 0 0 0 0 OTA g=0 in=45f ink=5 +R4 VINM 8 5.555555555555556k +C11 VINP 5 4p Rpar=450k +D1 VINP 4 DBIAS +D3 VINM 4 DBIAS +C12 9 4 10f +C13 10 4 10f +C14 8 4 10f +C15 1 4 10f +C16 4 2 10f +C17 4 3 10f +R3 VINM 9 16.6666666666667k +R5 VINP 3 5.555555555555556k +R7 VINP 2 16.6666666666667k +.model X D(Ron=1K Roff=100G Vfwd=-.95 epsilon=1.0 noiseless) +.model YU D(Ron=500 Roff=1T Vfwd=.55 epsilon=0.1 noiseless) +.model YD D(Ron=500 Roff=1T Vfwd = .75 epsilon=0.1 noiseless) +.model N VDMOS(Vto=-35m Kp=70m) +.model P VDMOS(Vto=35m Kp=70m pchan) +.model DP D(Ron=1k Roff=1T Vfwd=0.7 ilimit=51.12u noiseless) +.model DBIAS D(Ron=1k Roff=1T Vfwd=.7 ilimit=2.5n noiseless) +.ends LT1996 +* +.subckt LT6650 1 2 3 4 +A1 4 2 N003 2 2 2 N004 2 OTA g=50u Iout=100n Ref=.4 Cout=120p Vlow=-10 Vhigh=100 Rout=5G +M1 1 N002 3 3 N m=8 temp=27 +M2 2 N002 3 3 P temp=27 +C7 1 3 5p +C8 3 2 5p +D1 N004 1 X +D2 2 N004 X +C2 1 4 1p +C3 4 2 1p +G1 2 N002 N004 2 10µ +C4 N002 2 5n Rser=15K Rpar=100K noiseless +D3 N002 3 Y +A2 1 2 2 2 2 2 N003 2 SCHMITT Vt=1.35 Vh=1m Tau=10u +S1 N002 3 2 N003 O +.model X D(Ron=10K Roff=1T epsilon=1 noiseless) +.model Y D(Ron=100 Roff=1G epsilon=10m Vfwd=12m Vrev=85m revepsilon=30m noiseless) +.model N VDMOS(Vto=-3.3m Kp=2) +.model P VDMOS(Vto=3.3m Kp=2 pchan) +.model O SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4 noiseless) +.ends LT6650 +* +.subckt LT6700-1 1 2 3 4 5 6 +B2 N002 0 I=100u*dnlim(uplim(V(4),V(2)+18.6,.1), V(2)-.4, .1)- 424n*V(VINTB) -39.568u-100u*V(2) +A1 0 N002 0 0 0 0 VINTB 0 OTA g=4.7u asym isource=9u isink=-1.1u Vlow=-1e308 Vhigh=1e308 Cout=25p +C2 N006 N009 500f +M1 N007 N006 2 2 NOUT temp=27 +C5 5 6 .5p +C6 6 2 5p +D5 0 VINTB DLATB +D13 5 2 DP +R6 5 N006 590Meg +R7 N006 2 590Meg +G3 N006 0 N006 N004 100µ dir=1 vto=0 +G4 0 N006 2 N006 500m dir=1 vto=.3 +R3 5 N004 600Meg +A5 VINTB 0 0 0 0 0 N006 0 OTA g=2m asym Vlow=-1e308 Vhigh=1e308 isource=1u isink=-.115u +C14 N007 N006 50f +D8 N002 0 DINNLP +D9 0 N002 DINNLN +C7 0 N002 10f Rpar=40Meg +D1 N004 2 DNL +R1 N004 2 400Meg +R2 6 N007 1 +G1 5 2 6 N007 .1 +D2 N003 2 DBR +R4 5 N003 10Meg +D3 N003 4 DB1 +D4 N003 4 DB2 +C1 N003 2 10f +C3 4 2 .5p +C4 3 2 .5p +D6 N003 3 DB1 +D7 N003 3 DB2 +A2 0 N011 0 0 0 0 VINTA 0 OTA g=4.7u asym isource=3.5u isink=-1.5u Vlow=-1e308 Vhigh=1e308 Cout=25p +C8 N009 N014 500f +M2 N015 N014 2 2 NOUT temp=27 +C9 5 1 .5p +C10 1 2 5p +D10 0 VINTA DLATA +R5 5 N014 590Meg +R8 N014 2 590Meg +G2 N014 0 N014 N004 100µ dir=1 vto=0 +G5 0 N014 2 N014 500m dir=1 vto=.3 +A3 VINTA 0 0 0 0 0 N014 0 OTA g=2m asym Vlow=-1e308 Vhigh=1e308 isource=1u isink=-.115u +C11 N015 N014 50f +D11 N011 0 DINNLP +D12 0 N011 DINNLN +C12 0 N011 10f Rpar=40Meg +R13 1 N015 1 +G6 5 2 1 N015 .1 +B1 0 N011 I=100u*dnlim(uplim(V(3),V(2)+18.6,.1), V(2)-.4, .1)+322n*V(VINTA) -39.658u-100u*V(2) +G7 0 N009 2 0 5m +G8 0 N009 5 0 5m +C13 N009 0 2p Rpar=100 +.model DINNLP D(Vfwd=200m Ron=300k Roff=400Meg epsilon=30m) +.model DINNLN D(Vfwd=40m epsilon=10m Ron=100k Roff=400Meg) +.model NOUT VDMOS(Vto=5m kp=150m mtriode=.8 rds=600g) +.model DNL D(Vfwd=.9 epsilon=.3 Ron=100k Roff=400Meg) +.model DP D(Ron=100 Roff=1G Vfwd=1 ilimit=6.04u) +.model DBR D(Ron=10K Roff=1G Vfwd=.55 epsilon=.1) +.model DB1 D(Ron=50Meg Roff=1T Vfwd=60m epsilon=100m ilimit=1.8n) +.model DB2 D(Ron=35Meg Roff=1T Vfwd=450m epsilon=50m) +.model DLATA D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLATB D(Ron=1 Roff=10Meg Vfwd=.5 Vrev=1 epsilon=.5 revepsilon=.5) +.ends LT6700-1 +* +.subckt LT6700-2 1 2 3 4 5 6 +B2 N002 0 I=100u*dnlim(uplim(V(4),V(2)+18.6,.1), V(2)-.4, .1)- 424n*V(VINTB) -39.568u-100u*V(2) +A1 0 N002 0 0 0 0 VINTB 0 OTA g=4.7u asym isource=9u isink=-1.1u Vlow=-1e308 Vhigh=1e308 Cout=25p +C2 N006 N009 500f +M1 N007 N006 2 2 NOUT temp=27 +C5 5 6 .5p +C6 6 2 5p +D5 0 VINTB DLAT +D13 5 2 DP +R6 5 N006 590Meg +R7 N006 2 590Meg +G3 N006 0 N006 N004 100µ dir=1 vto=0 +G4 0 N006 2 N006 500m dir=1 vto=.3 +R3 5 N004 600Meg +A5 VINTB 0 0 0 0 0 N006 0 OTA g=2m asym Vlow=-1e308 Vhigh=1e308 isource=1u isink=-.115u +C14 N007 N006 50f +D8 N002 0 DINNLP +D9 0 N002 DINNLN +C7 0 N002 10f Rpar=40Meg +D1 N004 2 DNL +R1 N004 2 400Meg +R2 6 N007 1 +G1 5 2 6 N007 .1 +D2 N003 2 DBR +R4 5 N003 10Meg +D3 N003 4 DB1 +D4 N003 4 DB2 +C1 N003 2 10f +C3 4 2 .5p +C4 3 2 .5p +D6 N003 3 DB1 +D7 N003 3 DB2 +C8 N009 N014 500f +M2 N015 N014 2 2 NOUT temp=27 +C9 5 1 .5p +C10 1 2 5p +D10 0 VINTA DLAT +R5 5 N014 590Meg +R8 N014 2 590Meg +G2 N014 0 N014 N004 100µ dir=1 vto=0 +G5 0 N014 2 N014 500m dir=1 vto=.3 +A3 VINTA 0 0 0 0 0 N014 0 OTA g=2m asym Vlow=-1e308 Vhigh=1e308 isource=1u isink=-.115u +C11 N015 N014 50f +D11 N011 0 DINNLP +D12 0 N011 DINNLN +C12 0 N011 10f Rpar=40Meg +R13 1 N015 1 +G6 5 2 1 N015 .1 +B1 N011 0 I=100u*dnlim(uplim(V(3),V(2)+18.6,.1), V(2)-.4, .1)- 424n*V(VINTA) -39.568u-100u*V(2) +A2 0 N011 0 0 0 0 VINTA 0 OTA g=4.7u asym isource=9u isink=-1.1u Vlow=-1e308 Vhigh=1e308 Cout=25p +G7 0 N009 2 0 5m +G8 0 N009 5 0 5m +C13 N009 0 2p Rpar=100 +.model DINNLP D(Vfwd=200m Ron=300k Roff=400Meg epsilon=30m) +.model DINNLN D(Vfwd=40m epsilon=10m Ron=100k Roff=400Meg) +.model NOUT VDMOS(Vto=5m kp=150m mtriode=.8 rds=600g) +.model DNL D(Vfwd=.9 epsilon=.3 Ron=100k Roff=400Meg) +.model DP D(Ron=100 Roff=1G Vfwd=1 ilimit=6.04u) +.model DBR D(Ron=10K Roff=1G Vfwd=.55 epsilon=.1) +.model DB1 D(Ron=50Meg Roff=1T Vfwd=60m epsilon=100m ilimit=1.8n) +.model DB2 D(Ron=35Meg Roff=1T Vfwd=450m epsilon=50m) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=.5 Vrev=1 epsilon=.5 revepsilon=.5) +.ends LT6700-2 +* +.subckt LT6700-3 1 2 3 4 5 6 +C2 N006 N009 500f +M1 N007 N006 2 2 NOUT temp=27 +C5 5 6 .5p +C6 6 2 5p +D5 0 VINTB DLAT +D13 5 2 DP +R6 5 N006 590Meg +R7 N006 2 590Meg +G3 N006 0 N006 N004 100µ dir=1 vto=0 +G4 0 N006 2 N006 500m dir=1 vto=.3 +R3 5 N004 600Meg +A5 VINTB 0 0 0 0 0 N006 0 OTA g=2m asym Vlow=-1e308 Vhigh=1e308 isource=1u isink=-.115u +C14 N007 N006 50f +D8 N002 0 DINNLP +D9 0 N002 DINNLN +C7 0 N002 10f Rpar=40Meg +D1 N004 2 DNL +R1 N004 2 400Meg +R2 6 N007 1 +G1 5 2 6 N007 .1 +D2 N003 2 DBR +R4 5 N003 10Meg +D3 N003 4 DB1 +D4 N003 4 DB2 +C1 N003 2 10f +C3 4 2 .5p +C4 3 2 .5p +D6 N003 3 DB1 +D7 N003 3 DB2 +A2 0 N011 0 0 0 0 VINTA 0 OTA g=4.7u asym isource=3.5u isink=-1.5u Vlow=-1e308 Vhigh=1e308 Cout=25p +C8 N009 N014 500f +M2 N015 N014 2 2 NOUT temp=27 +C9 5 1 .5p +C10 1 2 5p +D10 0 VINTA DLAT +R5 5 N014 590Meg +R8 N014 2 590Meg +G2 N014 0 N014 N004 100µ dir=1 vto=0 +G5 0 N014 2 N014 500m dir=1 vto=.3 +A3 VINTA 0 0 0 0 0 N014 0 OTA g=2m asym Vlow=-1e308 Vhigh=1e308 isource=1u isink=-.115u +C11 N015 N014 50f +D11 N011 0 DINNLP +D12 0 N011 DINNLN +C12 0 N011 10f Rpar=40Meg +R13 1 N015 1 +G6 5 2 1 N015 .1 +B1 0 N011 I=100u*dnlim(uplim(V(3),V(2)+18.6,.1), V(2)-.4, .1)+322n*V(VINTA) -39.658u-100U*V(2) +A1 0 N002 0 0 0 0 VINTB 0 OTA g=4.7u asym isource=3.5u isink=-1.5u Vlow=-1e308 Vhigh=1e308 Cout=25p +B2 0 N002 I=100u*dnlim(uplim(V(4),V(2)+18.6,.1), V(2)-.4, .1)+322n*V(VINTB) -39.658u-100u*V(2) +G7 0 N009 2 0 5m +G8 0 N009 5 0 5m +C13 N009 0 2p Rpar=100 +.model DINNLP D(Vfwd=200m Ron=300k Roff=400Meg epsilon=30m) +.model DINNLN D(Vfwd=40m epsilon=10m Ron=100k Roff=400Meg) +.model NOUT VDMOS(Vto=5m kp=150m mtriode=.8 rds=600g) +.model DNL D(Vfwd=.9 epsilon=.3 Ron=100k Roff=400Meg) +.model DP D(Ron=100 Roff=1G Vfwd=1 ilimit=6.04u) +.model DBR D(Ron=10K Roff=1G Vfwd=.55 epsilon=.1) +.model DB1 D(Ron=50Meg Roff=1T Vfwd=60m epsilon=100m ilimit=1.8n) +.model DB2 D(Ron=35Meg Roff=1T Vfwd=450m epsilon=50m) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.ends LT6700-3 +* +* LPWR SUMA INVINA LPOUTA AGND V- ENB SUMB INVINB LPOUTB V+ +.SUBCKT LTC1563-2 100 2 4 6 7 8 9 11 13 15 16 +C1A 4 6 53.85P +C1B 13 15 39.17P +C2B 11 12 87.97P +C2A 2 10 64.24P +RI6 6 19 50K +RI18 15 14 50K +RI7 19 10 40K +RI9 14 12 40K +CPARA 2 0 4.5p +CPARB 11 0 4.5p +RI20 17 7 20K +RI19 7 18 20K +XI26 7 4 8 16 6 1 9 OPAMP1563 +XI25 7 13 8 16 15 1 9 OPAMP1563 +XI24 7 14 8 16 12 1 9 OPAMP1563 +XI23 7 19 8 16 10 1 9 OPAMP1563 +XS2 9 18 8 SwitchA2 +XS1 9 16 17 SwitchA2 +Rmike 1 7 1G +.subckt OpAmp1563 1 2 11 12 25 100 9 +M1 7 3 5 5 P L=3E-6 W=1200E-6 +M2 6 2 5 5 P L=3E-6 W=1200E-6 +RI1 7 11 1.6k +RI2 6 11 1.6k +G1 12a 5a POLY(1) (12,11) 15E-6 1E-6 ;LP +G2 12bb 5bb POLY(1) (12,11) 65E-6 8E-6 ;HS +XSW1 3a 12 12a SwitchA2 +XSW2 3a 12 12b SwitchB +XSW3 3a 12a 0 SwitchB +XSW4 3a 12b 0 SwitchA2 +XSW5 3a 5a 5 SwitchA2 +XSW6 3a 5b 5 SwitchB +XSW7 3a 5a 0 SwitchB +XSW8 3a 5b 0 SwitchA2 +XSW9 9 12b 12bb SwitchA2 +XSW10 9 12bb 0 SwitchB +XS11 9 5bb 5b SwitchA2 +XS12 9 5bb 0 SwitchB +V1 12 4 .75 +D1 5 4 DX +Rn 3 10 700 +EVOS 10 1 POLY(2) (17,15) (19,15) -.70m 1 1 +XI10 N_3 N_2 11 12 3a 2inor +XI8 100 12 N_2 SWITCHN +XI9 9 12 N_3 SWITCHN +RI6 N_2 11 10meg +RI7 N_3 11 10meg +ECM 16 15 POLY(2) (0,15) (2,15) 0 .35 .35 +RCM1 16 17 70E3 +RCM2 17 15 10 +CCM 16 17 6.43E-12 +RPS1 18 19 4.5E3 +RPS2 19 15 1 +CPS 18 19 100p +EPS 18 0 POLY(1) (12,11) 0 1 +E2 15 0 POLY(2) (12,0) (11,0) 0 .5 .5 +GIS1 11a 11c (12,11) .035m +GIS2 11bb 11dd (12,11) .2m +XSW11 3a 12 11a SwitchA2 +XSW12 3a 12 11b SwitchB +XSW13 3a 11c 11 SwitchA2 +XSW14 3a 11d 11 SwitchB +XSW15 3a 11a 0 SwitchB +XSW16 3a 11b 0 SwitchA2 +XSW17 3a 11c 0 SwitchB +XSW18 3a 11d 0 SwitchA2 +XSW19 9 11bb 11b SwitchA2 +XSW20 9 11bb 0 SwitchB +XS21 9 11dd 11d SwitchA2 +XS22 9 11dd 0 SwitchB +E1a 13a 15a POLY(1) (7,6) 0 4 +E1b 13bb 15bb POLY(1) (7,6) 0 8 ;HS gain +R1 13 14 5E+3 +C1a 14a 14c 13.5E-12 +C1b 14bb 14dd 2E-12 +XSW21 3a 13 13a SwitchA2 +XSW22 3a 13 13b SwitchB +XSW23 3a 15a 15 SwitchA2 +XSW24 3a 15b 15 SwitchB +XSW25 3a 13a 0 SwitchB +XSW26 3a 15a 0 SwitchB +XSW27 3a 13b 0 SwitchA2 +XSW28 3a 15b 0 SwitchA2 +XS29 9 13b 13bb SwitchA2 +XS30 9 13bb 0 SwitchB +XS31 9 15bb 15b SwitchA2 +XS32 9 15bb 0 SwitchB +XS33 9 14b 14bb SwitchA2 +XS34 9 14bb 0 SwitchB +XS35 9 14dd 14d SwitchA2 +XS36 9 14dd 0 SwitchB +XSW29 3a 14 14a SwitchA2 +XSW30 3a 14 14b SwitchB +XSW31 3a 14c 15 SwitchA2 +XSW32 3a 14d 15 SwitchB +XSW33 3a 14a 0 SwitchB +XSW34 3a 14b 0 SwitchA2 +XSW35 3a 14c 0 SwitchB +XSW36 3a 14d 0 SwitchA2 +M3 25 23 12 12 P L=3E-6 W=1400E-6 +M4 25 24 11 11 N L=3E-6 W=840E-6 +M5 23 23 12 12 P L=6E-6 W=.35E-6 +M6 24 24 11 11 N L=6E-6 W=.21E-6 +GM5a 23a 23c POLY(2)(12,11)(15,14) 8e-9 2.1E-9 1.08E-4 ;LP +GM6a 12a 12c POLY(2)(12,11)(14,15) 8e-9 2.1E-9 1.08E-4 ;LP +GM5b 23bb 23dd POLY(2)(12,11)(15,14) 5e-8 2.24E-8 1.08E-4 ;HS +GM6b 12bb 12dd POLY(2)(12,11)(14,15) 5e-8 2.24E-8 1.08E-4 ;HS +CO1 25 23 17E-12 +CO2 25 24 17E-12 +XSW37 3a 23 23a SwitchA2 +XSW38 3a 23c 11 SwitchA2 +XSW39 3a 23 23b SwitchB +XSW40 3a 23d 11 SwitchB +XSW41 3a 23a 0 SwitchB +XSW42 3a 23b 0 SwitchA2 +XSW43 3a 23c 0 SwitchB +XSW44 3a 23d 0 SwitchA2 +XSW45 9 23b 23bb SwitchA2 +XSW46 9 23bb 0 SwitchB +XS47 9 23dd 23d SwitchA2 +XS48 9 23dd 0 SwitchB +XSW47 3a 12 12a SwitchA2 +XSW48 3a 12c 24 SwitchA2 +XSW49 3a 12 12b SwitchB +XSW50 3a 12d 24 SwitchB +XSW51 3a 12a 0 SwitchB +XSW52 3a 12b 0 SwitchA2 +XSW53 3a 12c 0 SwitchB +XSW54 3a 12d 0 SwitchA2 +XS55 9 12b 12bb SwitchA2 +XS56 9 12bb 0 SwitchB +XS57 9 12dd 12d SwitchA2 +XS58 9 12dd 0 SwitchB +.MODEL DX D(IS=1E-14 RS=5) +.MODEL P PMOS(LEVEL=2 KF=2.5E-26 KP=16E-6 VTO=-.7 LAMBDA=.001 RD=8) +.MODEL N NMOS(LEVEL=2 KF=3.5E-28 KP=52E-6 VTO= .7 LAMBDA=.001 RD=5) +.ENDS OpAmp1563 +.subckt switchN 1 2 3 +S1 3 2 1 0 SwN +.model swn vswitch(Ron=1000 Roff=10E6 Von=2.2 Voff=0.5) +.ends switchN +.subckt switchA2 1 2 3 +S1 3 2 1 0 SwA +.model swa vswitch(Ron=10 Roff=100E8 Von=.5 Voff=2.2) +.ends switchA2 +.subckt switchB 1 2 3 +S1 3 2 1 0 SwB +.model swb vswitch(Ron=10 Roff=100E8 Von=2.2 Voff=.5) +.ends switchB +.SUBCKT 2inor 9 100 11 12 3a +XI25 100 12 N_1 SWITCHP +XI27 9 N_1 QB SWITCHP +XI26 QB 12 3a SWITCHP +XI24 100 QB 11 SWITCHN +XI23 9 QB 11 SWITCHN +XI22 QB 3a 11 SWITCHN +.ENDS 2inor +.subckt switchP 1 2 3 +S1 3 2 1 0 Swp +.model swp vswitch(Ron=1000 Roff=10E6 Von=0.5 Voff=2.2) +.ends switchP +.ENDS LTC1563-2 +* +* LPWR SUMA INVINA LPOUTA AGND V- ENB SUMB INVINB LPOUTB V+ +.SUBCKT LTC1563-3 100 2 4 6 7 8 9 11 13 15 16 +C1A 4 6 34.96P +C1B 13 15 26.84P +C2B 11 12 40.35P +C2A 2 10 38.80P +RI6 6 19 50K +RI18 15 14 50K +RI7 19 10 40K +RI9 14 12 40K +CPARA 2 0 4.5p +CPARB 11 0 4.5p +RI20 17 7 20K +RI19 7 18 20K +XI26 7 4 8 16 6 1 9 OPAMP1563 +XI25 7 13 8 16 15 1 9 OPAMP1563 +XI24 7 14 8 16 12 1 9 OPAMP1563 +XI23 7 19 8 16 10 1 9 OPAMP1563 +XS2 9 18 8 SwitchA2 +XS1 9 16 17 SwitchA2 +Rmike 1 7 1G +* +.subckt OpAmp1563 1 2 11 12 25 100 9 +M1 7 3 5 5 P L=3E-6 W=1200E-6 +M2 6 2 5 5 P L=3E-6 W=1200E-6 +RI1 7 11 1.6k +RI2 6 11 1.6k +G1 12a 5a POLY(1) (12,11) 15E-6 1E-6 ;LP +G2 12bb 5bb POLY(1) (12,11) 65E-6 8E-6 ;HS +XSW1 3a 12 12a SwitchA2 +XSW2 3a 12 12b SwitchB +XSW3 3a 12a 0 SwitchB +XSW4 3a 12b 0 SwitchA2 +XSW5 3a 5a 5 SwitchA2 +XSW6 3a 5b 5 SwitchB +XSW7 3a 5a 0 SwitchB +XSW8 3a 5b 0 SwitchA2 +XSW9 9 12b 12bb SwitchA2 +XSW10 9 12bb 0 SwitchB +XS11 9 5bb 5b SwitchA2 +XS12 9 5bb 0 SwitchB +V1 12 4 .75 +D1 5 4 DX +Rn 3 10 700 +EVOS 10 1 POLY(2) (17,15) (19,15) -.70m 1 1 +XI10 N_3 N_2 11 12 3a 2inor +XI8 100 12 N_2 SWITCHN +XI9 9 12 N_3 SWITCHN +RI6 N_2 11 10meg +RI7 N_3 11 10meg +ECM 16 15 POLY(2) (0,15) (2,15) 0 .35 .35 +RCM1 16 17 70E3 +RCM2 17 15 10 +CCM 16 17 6.43E-12 +RPS1 18 19 4.5E3 +RPS2 19 15 1 +CPS 18 19 100p +EPS 18 0 POLY(1) (12,11) 0 1 +E2 15 0 POLY(2) (12,0) (11,0) 0 .5 .5 +GIS1 11a 11c (12,11) .035m +GIS2 11bb 11dd (12,11) .2m +XSW11 3a 12 11a SwitchA2 +XSW12 3a 12 11b SwitchB +XSW13 3a 11c 11 SwitchA2 +XSW14 3a 11d 11 SwitchB +XSW15 3a 11a 0 SwitchB +XSW16 3a 11b 0 SwitchA2 +XSW17 3a 11c 0 SwitchB +XSW18 3a 11d 0 SwitchA2 +XSW19 9 11bb 11b SwitchA2 +XSW20 9 11bb 0 SwitchB +XS21 9 11dd 11d SwitchA2 +XS22 9 11dd 0 SwitchB +E1a 13a 15a POLY(1) (7,6) 0 4 +E1b 13bb 15bb POLY(1) (7,6) 0 8 ;HS gain +R1 13 14 5E+3 +C1a 14a 14c 13.5E-12 +C1b 14bb 14dd 2E-12 +XSW21 3a 13 13a SwitchA2 +XSW22 3a 13 13b SwitchB +XSW23 3a 15a 15 SwitchA2 +XSW24 3a 15b 15 SwitchB +XSW25 3a 13a 0 SwitchB +XSW26 3a 15a 0 SwitchB +XSW27 3a 13b 0 SwitchA2 +XSW28 3a 15b 0 SwitchA2 +XS29 9 13b 13bb SwitchA2 +XS30 9 13bb 0 SwitchB +XS31 9 15bb 15b SwitchA2 +XS32 9 15bb 0 SwitchB +XS33 9 14b 14bb SwitchA2 +XS34 9 14bb 0 SwitchB +XS35 9 14dd 14d SwitchA2 +XS36 9 14dd 0 SwitchB +XSW29 3a 14 14a SwitchA2 +XSW30 3a 14 14b SwitchB +XSW31 3a 14c 15 SwitchA2 +XSW32 3a 14d 15 SwitchB +XSW33 3a 14a 0 SwitchB +XSW34 3a 14b 0 SwitchA2 +XSW35 3a 14c 0 SwitchB +XSW36 3a 14d 0 SwitchA2 +M3 25 23 12 12 P L=3E-6 W=1400E-6 +M4 25 24 11 11 N L=3E-6 W=840E-6 +M5 23 23 12 12 P L=6E-6 W=.35E-6 +M6 24 24 11 11 N L=6E-6 W=.21E-6 +GM5a 23a 23c POLY(2)(12,11)(15,14) 8e-9 2.1E-9 1.08E-4 ;LP +GM6a 12a 12c POLY(2)(12,11)(14,15) 8e-9 2.1E-9 1.08E-4 ;LP +GM5b 23bb 23dd POLY(2)(12,11)(15,14) 5e-8 2.24E-8 1.08E-4 ;HS +GM6b 12bb 12dd POLY(2)(12,11)(14,15) 5e-8 2.24E-8 1.08E-4 ;HS +CO1 25 23 17E-12 +CO2 25 24 17E-12 +XSW37 3a 23 23a SwitchA2 +XSW38 3a 23c 11 SwitchA2 +XSW39 3a 23 23b SwitchB +XSW40 3a 23d 11 SwitchB +XSW41 3a 23a 0 SwitchB +XSW42 3a 23b 0 SwitchA2 +XSW43 3a 23c 0 SwitchB +XSW44 3a 23d 0 SwitchA2 +XSW45 9 23b 23bb SwitchA2 +XSW46 9 23bb 0 SwitchB +XS47 9 23dd 23d SwitchA2 +XS48 9 23dd 0 SwitchB +XSW47 3a 12 12a SwitchA2 +XSW48 3a 12c 24 SwitchA2 +XSW49 3a 12 12b SwitchB +XSW50 3a 12d 24 SwitchB +XSW51 3a 12a 0 SwitchB +XSW52 3a 12b 0 SwitchA2 +XSW53 3a 12c 0 SwitchB +XSW54 3a 12d 0 SwitchA2 +XS55 9 12b 12bb SwitchA2 +XS56 9 12bb 0 SwitchB +XS57 9 12dd 12d SwitchA2 +XS58 9 12dd 0 SwitchB +.MODEL DX D(IS=1E-14 RS=5) +.MODEL P PMOS(LEVEL=2 KF=2.5E-26 KP=16E-6 VTO=-.7 LAMBDA=.001 RD=8) +.MODEL N NMOS(LEVEL=2 KF=3.5E-28 KP=52E-6 VTO= .7 LAMBDA=.001 RD=5) +.ENDS OpAmp1563 +.subckt switchN 1 2 3 +S1 3 2 1 0 SwN +.model swn vswitch(Ron=1000 Roff=10E6 Von=2.2 Voff=0.5) +.ends switchN +.subckt switchA2 1 2 3 +S1 3 2 1 0 SwA +.model swa vswitch(Ron=10 Roff=100E8 Von=.5 Voff=2.2) +.ends switchA2 +.subckt switchB 1 2 3 +S1 3 2 1 0 SwB +.model swb vswitch(Ron=10 Roff=100E8 Von=2.2 Voff=.5) +.ends switchB +.SUBCKT 2inor 9 100 11 12 3a +XI25 100 12 N_1 SWITCHP +XI27 9 N_1 QB SWITCHP +XI26 QB 12 3a SWITCHP +XI24 100 QB 11 SWITCHN +XI23 9 QB 11 SWITCHN +XI22 QB 3a 11 SWITCHN +.ENDS 2inor +.subckt switchP 1 2 3 +S1 3 2 1 0 Swp +.model swp vswitch(Ron=1000 Roff=10E6 Von=0.5 Voff=2.2) +.ends switchP +.ENDS LTC1563-3 +* +.subckt LTC1841 1 2 3 4 5 +B1 0 N002 I=100u*dnlim(uplim(V(1),V(3)-1.2,.1), V(4)-.2 ,.1)+1n*V(1) +B2 N002 0 I=100u*dnlim(uplim(V(2),V(3)-1.19,.1), V(4)-.21, .1)+1n*V(2) +A1 0 N002 0 0 0 0 N004 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C2 N007 0 1p +M1 5 N007 4 4 NOUT temp=27 +C5 3 5 .5p +C6 5 4 .5p +D5 0 N004 DLAT +D13 3 4 DP +R6 3 N007 590Meg +R7 N007 4 590Meg +G3 N007 0 N007 N005 100µ dir=1 vto=0 +G4 0 N007 4 N007 500m dir=1 vto=.3 +C10 4 1 .5p +C12 4 2 .5p +R3 3 N005 600Meg +D7 N005 4 DNL +A5 N004 0 0 0 0 0 N007 0 OTA g=2m iout=1u Vlow=-1e308 Vhigh=1e308 +C14 5 N007 120f +D8 N002 0 DINNLP +D9 0 N002 DINNLN +C7 0 N002 1f Rpar=1Meg +.model DINNLP D(Vfwd=900m Ron=300k Roff=5Meg epsilon=30m) +.model DINNLN D(Vfwd=80m epsilon=50m Ron=360k Roff=100Meg) +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DP D(Ron=100 Roff=1G Vfwd=1 ilimit=1.75u) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.ends LTC1841 +* +.subckt LTC1842 1 2 3 4 5 6 7 8 +B1 0 N002 I=100u*dnlim(uplim(V(3),V(7)-1.2,.1), V(2)-.2 ,.1)+1n*V(3) +B2 N002 0 I=100u*dnlim(uplim(V(6),V(7)-1.19,.1), V(2)-.21, .1)+1n*V(6) +A1 0 N002 0 0 0 0 N005 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C2 N008 0 1p +M1 1 N008 2 2 NOUT temp=27 +C5 7 1 .5p +C6 1 2 .5p +D5 0 N005 DLAT +C4 6 2 20p +D13 7 2 DP +R6 7 N008 590Meg +R7 N008 2 590Meg +G3 N008 0 N008 N006 100µ dir=1 vto=0 +G4 0 N008 2 N008 500m dir=1 vto=.3 +A3 0 N005 N010 0 0 0 N002 0 OTA g=20u linear cout=10f Vlow=-1e308 Vhigh=1e308 +C10 2 4 .5p +C12 2 3 .5p +C13 2 5 .5p +M3 7 N013 6 6 NREF temp=27 +A4 6 N014 2 2 2 2 N013 2 OTA g=5u iout=500n Vlow=-1e308 Vhigh=1e308 Cout=1p Rout=1g +D2 N014 2 DREF +R2 7 N014 10Meg +M5 2 N013 6 6 PREF temp=27 +D4 N013 6 DREFILIM1 +D6 6 N013 DREFILIM2 +R3 7 N006 600Meg +D7 N006 2 DNL +A5 N005 0 0 0 0 0 N008 0 OTA g=2m iout=1u Vlow=-1e308 Vhigh=1e308 +C14 1 N008 120f +D8 N002 0 DINNLP +D9 0 N002 DINNLN +G1 0 N010 6 5 59m +D1 0 N010 DLIMHYST +C3 N010 0 100f Rpar=1Meg +C7 0 N002 1f Rpar=1Meg +B3 0 N011 I=100u*dnlim(uplim(V(4),V(7)-1.2,.1), V(2)-.2 ,.1)+1n*V(4) +B4 N011 0 I=100u*dnlim(uplim(V(6),V(7)-1.19,.1), V(2)-.21, .1)+1n*V(6) +A2 0 N011 0 0 0 0 N012 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C1 N017 0 1p +M2 8 N017 2 2 NOUT temp=27 +C8 7 8 .5p +C9 8 2 .5p +D3 0 N012 DLAT +R1 7 N017 590Meg +R4 N017 2 590Meg +G2 N017 0 N017 N015 100µ dir=1 vto=0 +G5 0 N017 2 N017 500m dir=1 vto=.3 +A6 0 N012 N010 0 0 0 N011 0 OTA g=20u linear cout=10f Vlow=-1e308 Vhigh=1e308 +R5 7 N015 600Meg +D10 N015 2 DNL +A7 N012 0 0 0 0 0 N017 0 OTA g=2m iout=1u Vlow=-1e308 Vhigh=1e308 +C11 8 N017 120f +D11 N011 0 DINNLP +D12 0 N011 DINNLN +C15 0 N011 1f Rpar=1Meg +R9 5 6 10Meg +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model NREF VDMOS(Vto=-50m kp=10m) +.model PREF VDMOS(Vto=50m kp=1m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DP D(Ron=100 Roff=1G Vfwd=1 ilimit=.2u) +.model DREF D(Ron=1 Roff=1T Vfwd=1.182 epsilon=.1) +.model DREFILIM1 D(Roff=1G Ron=1k Vfwd=700m epsilon=100m) +.model DREFILIM2 D(Roff=1G Ron=250k Vfwd=100m epsilon=80m) +.model DINNLP D(Vfwd=900m Ron=300k Roff=5Meg epsilon=30m) +.model DINNLN D(Vfwd=80m epsilon=50m Ron=360k Roff=100Meg) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMHYST D(Ron=.1 Roff=100 Vfwd=0 epsilon=10m Vrev=320m revepsilon=5m) +.ends LTC1842 +* +.subckt LTC1843 1 2 3 4 5 6 7 8 +B1 0 N002 I=100u*dnlim(uplim(V(3),V(7)-1.2,.1), V(2)-.2 ,.1)+1n*V(3) +B2 N002 0 I=100u*dnlim(uplim(V(6),V(7)-1.19,.1), V(2)-.21, .1)+1n*V(6) +A1 0 N002 0 0 0 0 N005 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C2 N008 0 1p +M1 1 N008 2 2 NOUT temp=27 +C5 7 1 .5p +C6 1 2 .5p +D5 0 N005 DLAT +C4 6 2 20p +D13 7 2 DP +R6 7 N008 590Meg +R7 N008 2 590Meg +G3 N008 0 N008 N006 100µ dir=1 vto=0 +G4 0 N008 2 N008 500m dir=1 vto=.3 +A3 0 N005 N010 0 0 0 N002 0 OTA g=20u linear cout=10f Vlow=-1e308 Vhigh=1e308 +C10 2 4 .5p +C12 2 3 .5p +C13 2 5 .5p +M3 7 N013 6 6 NREF temp=27 +A4 6 N014 2 2 2 2 N013 2 OTA g=5u iout=500n Vlow=-1e308 Vhigh=1e308 Cout=1p Rout=1g +D2 N014 2 DREF +R2 7 N014 10Meg +M5 2 N013 6 6 PREF temp=27 +D4 N013 6 DREFILIM1 +D6 6 N013 DREFILIM2 +R3 7 N006 600Meg +D7 N006 2 DNL +A5 N005 0 0 0 0 0 N008 0 OTA g=2m iout=1u Vlow=-1e308 Vhigh=1e308 +C14 1 N008 120f +D8 N002 0 DINNLP +D9 0 N002 DINNLN +G1 0 N010 6 5 59m +D1 0 N010 DLIMHYST +C3 N010 0 100f Rpar=1Meg +C7 0 N002 1f Rpar=1Meg +B3 0 N011 I=100u*dnlim(uplim(V(6),V(7)-1.2,.1), V(2)-.2 ,.1)+1n*V(6) +B4 N011 0 I=100u*dnlim(uplim(V(4),V(7)-1.19,.1), V(2)-.21, .1)+1n*V(4) +A2 0 N011 0 0 0 0 N012 0 OTA g=1u asym isource=1.9u isink=-1.2u Vlow=-1e308 Vhigh=1e308 Cout=5p +C1 N017 0 1p +M2 8 N017 2 2 NOUT temp=27 +C8 7 8 .5p +C9 8 2 .5p +D3 0 N012 DLAT +R1 7 N017 590Meg +R4 N017 2 590Meg +G2 N017 0 N017 N015 100µ dir=1 vto=0 +G5 0 N017 2 N017 500m dir=1 vto=.3 +A6 0 N012 N010 0 0 0 N011 0 OTA g=20u linear cout=10f Vlow=-1e308 Vhigh=1e308 +R5 7 N015 600Meg +D10 N015 2 DNL +A7 N012 0 0 0 0 0 N017 0 OTA g=2m iout=1u Vlow=-1e308 Vhigh=1e308 +C11 8 N017 120f +D11 N011 0 DINNLP +D12 0 N011 DINNLN +C15 0 N011 1f Rpar=1Meg +R9 5 6 10Meg +.model NOUT VDMOS(Vto=5m kp=.6 mtriode=.15 rs=1.8 rds=10g) +.model NREF VDMOS(Vto=-50m kp=10m) +.model PREF VDMOS(Vto=50m kp=1m pchan) +.model DNL D(Vfwd=.3 epsilon=.1 Ron=200Meg Roff=60Meg) +.model DP D(Ron=100 Roff=1G Vfwd=1 ilimit=.2u) +.model DREF D(Ron=1 Roff=1T Vfwd=1.182 epsilon=.1) +.model DREFILIM1 D(Roff=1G Ron=1k Vfwd=700m epsilon=100m) +.model DREFILIM2 D(Roff=1G Ron=250k Vfwd=100m epsilon=80m) +.model DINNLP D(Vfwd=900m Ron=300k Roff=5Meg epsilon=30m) +.model DINNLN D(Vfwd=80m epsilon=50m Ron=360k Roff=100Meg) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.model DLIMHYST D(Ron=.1 Roff=100 Vfwd=0 epsilon=10m Vrev=320m revepsilon=5m) +.ends LTC1843 +* +* OUT AGND VIN V- G0 G1 G2 V+ +.subckt LTC6910-1 OUT AGND IN 27 G0 G1 G2 VPLUS +R2 14 IN 10K +R10 22 IN 10K +R9 21 IN 10K +R8 20 IN 10K +R7 19 IN 10K +R5 17 IN 10K +R4 16 IN 10K +R3 15 IN 10K +R1 IN 13 10K +R6 18 IN 10K +R11 24 23 50K +R12 25 24 30K +R13 26 25 10K +R14 OUT 26 10K +R15 VPLUS AGND 10K +R16 AGND 27 10K +RI71 G2A 27 100K +RI73 G0A 27 100K +RI72 G1A 27 100K +XI21 6 27 VPLUS 12 inverter +XI22 G0A 27 VPLUS 3 inverter +XI23 G1A 27 VPLUS 2 inverter +XI24 G2A 27 VPLUS 1 inverter +XI18 G0A G1A G2A 27 VPLUS 9 nand3in +XI19 G0A G1A 1 27 VPLUS 4 nand3in +XI20 3 2 1 27 VPLUS 6 nand3in +XI17 3 2 27 VPLUS 5 nand2in +XI16 4 1 27 VPLUS 7 nand2in +XI15 2 1 27 VPLUS 8 nand2in +XI14 G1A G2A 27 VPLUS 10 nand2in +XI13 5 G2A 27 VPLUS 11 nand2in +C1 OUT 23 1.6PF +XI53 AGND 23 27 VPLUS OUT OPAMP6910 +MI54 13 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI63 14 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI62 15 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI61 16 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI60 17 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI59 18 7 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI58 19 7 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI57 20 7 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI56 21 8 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI55 22 6 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI67 24 9 23 27 N L=2U W=24U AS=108P AD=108P PS=57U PD=57U +MI66 25 10 23 27 N L=2U W=48U AS=216P AD=216P PS=105U PD=105U +MI65 26 11 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI64 OUT 12 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +XI76 G2 VPLUS G2A SWITCHN +XI75 G1 VPLUS G1A SWITCHN +XI74 G0 VPLUS G0A SWITCHN +* +.subckt OpAmp6910 1 2 11 12 25 +M1 7 3 5 5 P L=2E-6 W=1312E-6 +M2 6 2 5 5 P L=2E-6 W=1312E-6 +RI1 7 8 500 +RI2 6 9 500 +I1 12 5 400E-6 +V1 12 4 .75 +V2 8 11 .6 +V3 9 11 .6 +D1 5 4 DX +Rn 3 10 700 +EVOS 10 1 POLY(2) (17,15) (19,15) -.70m 1 1 +ECM 16 15 POLY(2) (0,15) (2,15) 0 .35 .35 +RCM1 16 17 70E3 +RCM2 17 15 10 +CCM 16 17 6.43E-12 +RPS1 18 19 4.5E3 +RPS2 19 15 1 +CPS 18 19 100p +EPS 18 0 POLY(1) (12,11) 0 1 +E2 15 0 POLY(2) (12,0) (11,0) 0 .5 .5 +GIS 12 11 (12,11) .18m +E1 13 15 POLY(1) (7,6) 0 7 +R1 13 14 1E+3 +C1 14 15 9.78E-12 +M3 25 23 12 12 P L=2.5E-6 W=11200E-6 +M4 25 24 11 11 N L=2.5E-6 W=5600E-6 +M5 23 23 12 12 P L=2.5E-6 W=1.35E-6 +M6 24 24 11 11 N L=2.5E-6 W=.525E-6 +GM5 23 11 POLY(1) (15,14) 9.644E-8 2.08E-5 +GM6 12 24 POLY(1) (14,15) 7.5E-8 2.08E-5 +CO1 25 23 1.68E-12 +CO2 25 24 1.68E-12 +.ENDS OpAmp6910 +.subckt switchP 1 2 3 +S1 3 2 1 0 Swp +.model swp vswitch(Ron=1000 Roff=10E6 Von=0.5 Voff=2.2) +.ends switchP +.subckt switchN 1 2 3 +S1 3 2 1 0 SwN +.model swn vswitch(Ron=1000 Roff=10E6 Von=2.2 Voff=0.5) +.ends switchN +.SUBCKT inverter 1 4 8 2 +XSN 1 2 4 SWITCHN +XSP 1 8 2 SWITCHP +.ENDS inverter +.SUBCKT nand2in 1 2 4 8 3 +XI4 1 3 5 SWITCHN +XI3 2 5 4 SWITCHN +XI2 1 8 3 SWITCHP +XI1 2 8 3 SWITCHP +.ENDS nand2in +.SUBCKT nand3in 1 2 3 4 8 5 +XI6 3 7 4 SWITCHN +XI5 2 6 7 SWITCHN +XI4 1 5 6 SWITCHN +XI3 2 8 5 SWITCHP +XI2 3 8 5 SWITCHP +XI1 1 8 5 SWITCHP +.ENDS nand3in +.MODEL DX D(IS=1E-14 RS=5) +.MODEL P PMOS(LEVEL=2 KF=2.5E-26 KP=16E-6 VTO=-.7 LAMBDA=.001 RD=8) +.MODEL N NMOS(LEVEL=2 KF=3.5E-28 KP=52E-6 VTO= .7 LAMBDA=.001 RD=5) +.ENDS LTC6910-1 +* +* OUT AGND VIN V- G0 G1 G2 V+ +.subckt LTC6910-2 OUT AGND IN 27 G0 G1 G2 VPLUS +R11 24 23 40K +R12 25 24 20K +R13 26 25 10K +R14 OUT 26 10K +R2 14 IN 10K +R10 22 IN 10K +R9 21 IN 10K +R7 19 IN 10K +R4 16 IN 10K +RI27R3 15 IN 10K +R1 IN 13 10K +R6 18 IN 10K +R15 VPLUS AGND 10K +R16 AGND 27 10K +RI70 G2A 27 100K +RI69 G1A 27 100K +RI68 G0A 27 100K +XI21 6 27 VPLUS 12 inverter +XI24 G2A 27 VPLUS 1 inverter +XI23 G1A 27 VPLUS 2 inverter +XI22 G0A 27 VPLUS 3 inverter +XI18 G0A G1A G2A 27 VPLUS 9 nand3in +XI19 G0A G1A 1 27 VPLUS 4 nand3in +XI20 3 2 1 27 VPLUS 6 nand3in +XI17 3 2 27 VPLUS 5 nand2in +XI16 4 1 27 VPLUS 7 nand2in +XI15 2 1 27 VPLUS 8 nand2in +XI14 G1A G2A 27 VPLUS 10 nand2in +XI13 5 G2A 27 VPLUS 11 nand2in +C1 OUT 23 1.6PF +MI63 13 G2A 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI62 15 G2A 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI61 16 G2A 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI60 19 7 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI59 21 8 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI58 22 6 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI57 14 G2A 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI56 18 7 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI55 25 10 23 27 N L=2U W=48U AS=216.000P AD=216.000P PS=105.000U PD=105.000U +MI54 26 11 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI53 OUT 12 23 27 N L=2U W=96U AS=432.000P AD=432.000P PS=201.000U PD=201.000U +MI52 24 9 23 27 N L=2U W=24U AS=108.000P AD=108.000P PS=57.000U PD=57.000U +XI64 AGND 23 27 VPLUS OUT OPAMP6910 +XI67 G0 VPLUS G0A SWITCHN +XI66 G1 VPLUS G1A SWITCHN +XI65 G2 VPLUS G2A SWITCHN +* +.subckt OpAmp6910 1 2 11 12 25 +M1 7 3 5 5 P L=2E-6 W=1312E-6 +M2 6 2 5 5 P L=2E-6 W=1312E-6 +RI1 7 8 500 +RI2 6 9 500 +I1 12 5 400E-6 +V1 12 4 .75 +V2 8 11 .6 +V3 9 11 .6 +D1 5 4 DX +Rn 3 10 700 +EVOS 10 1 POLY(2) (17,15) (19,15) -.70m 1 1 +ECM 16 15 POLY(2) (0,15) (2,15) 0 .35 .35 +RCM1 16 17 70E3 +RCM2 17 15 10 +CCM 16 17 6.43E-12 +RPS1 18 19 4.5E3 +RPS2 19 15 1 +CPS 18 19 100p +EPS 18 0 POLY(1) (12,11) 0 1 +E2 15 0 POLY(2) (12,0) (11,0) 0 .5 .5 +GIS 12 11 (12,11) .18m +E1 13 15 POLY(1) (7,6) 0 7 +R1 13 14 1E+3 +C1 14 15 9.78E-12 +M3 25 23 12 12 P L=2.5E-6 W=11200E-6 +M4 25 24 11 11 N L=2.5E-6 W=5600E-6 +M5 23 23 12 12 P L=2.5E-6 W=1.35E-6 +M6 24 24 11 11 N L=2.5E-6 W=.525E-6 +GM5 23 11 POLY(1) (15,14) 9.644E-8 2.08E-5 +GM6 12 24 POLY(1) (14,15) 7.5E-8 2.08E-5 +CO1 25 23 1.68E-12 +CO2 25 24 1.68E-12 +.ENDS OpAmp6910 +.subckt switchP 1 2 3 +S1 3 2 1 0 Swp +.model swp vswitch(Ron=1000 Roff=10E6 Von=0.5 Voff=2.2) +.ends switchP +.subckt switchN 1 2 3 +S1 3 2 1 0 SwN +.model swn vswitch(Ron=1000 Roff=10E6 Von=2.2 Voff=0.5) +.ends switchN +.SUBCKT inverter 1 4 8 2 +XSN 1 2 4 SWITCHN +XSP 1 8 2 SWITCHP +.ENDS inverter +.SUBCKT nand2in 1 2 4 8 3 +XI4 1 3 5 SWITCHN +XI3 2 5 4 SWITCHN +XI2 1 8 3 SWITCHP +XI1 2 8 3 SWITCHP +.ENDS nand2in +.SUBCKT nand3in 1 2 3 4 8 5 +XI6 3 7 4 SWITCHN +XI5 2 6 7 SWITCHN +XI4 1 5 6 SWITCHN +XI3 2 8 5 SWITCHP +XI2 3 8 5 SWITCHP +XI1 1 8 5 SWITCHP +.ENDS nand3in +.MODEL DX D(IS=1E-14 RS=5) +.MODEL P PMOS(LEVEL=2 KF=2.5E-26 KP=16E-6 VTO=-.7 LAMBDA=.001 RD=8) +.MODEL N NMOS(LEVEL=2 KF=3.5E-28 KP=52E-6 VTO= .7 LAMBDA=.001 RD=5) +.ENDS LTC6910-2 +* +* OUT AGND VIN V- G0 G1 G2 V+ +.subckt LTC6910-3 OUT AGND IN 27 G0 G1 G2 VPLUS +R2 14 IN 10K +R9 21 IN 10K +R7 19 IN 10K +R4 16 IN 10K +RI27R3 15 IN 10K +R1 IN 13 10K +R6 18 IN 10K +R14 OUT 26 10K +R15 VPLUS AGND 10K +R16 AGND 27 10K +RI70 27 G2A 100K +RI69 G1A 27 100K +RI68 G0A 27 100K +XI24 G2A 27 VPLUS 1 inverter +XI23 G1A 27 VPLUS 2 inverter +XI21 N_1 27 VPLUS 12 inverter +XI22 G0A 27 VPLUS 3 inverter +XI20 3 2 1 27 VPLUS N_1 nand3in +C1 OUT 23 1.6PF +XI52 N_2 27 27 VPLUS 11 nand2in +XI63 27 27 27 VPLUS N_2 nand2in +MI62 18 G1A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI61 19 G1A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI60 21 G0A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI59 26 11 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI58 OUT 12 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI57 13 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI56 14 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI55 15 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI54 16 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +XI64 AGND 23 27 VPLUS OUT OPAMP6910 +XI67 G2 VPLUS G2A SWITCHN +XI66 G1 VPLUS G1A SWITCHN +XI65 G0 VPLUS G0A SWITCHN +* +.subckt OpAmp6910 1 2 11 12 25 +M1 7 3 5 5 P L=2E-6 W=1312E-6 +M2 6 2 5 5 P L=2E-6 W=1312E-6 +RI1 7 8 500 +RI2 6 9 500 +I1 12 5 400E-6 +V1 12 4 .75 +V2 8 11 .6 +V3 9 11 .6 +D1 5 4 DX +Rn 3 10 700 +EVOS 10 1 POLY(2) (17,15) (19,15) -.70m 1 1 +ECM 16 15 POLY(2) (0,15) (2,15) 0 .35 .35 +RCM1 16 17 70E3 +RCM2 17 15 10 +CCM 16 17 6.43E-12 +RPS1 18 19 4.5E3 +RPS2 19 15 1 +CPS 18 19 100p +EPS 18 0 POLY(1) (12,11) 0 1 +E2 15 0 POLY(2) (12,0) (11,0) 0 .5 .5 +GIS 12 11 (12,11) .18m +E1 13 15 POLY(1) (7,6) 0 7 +R1 13 14 1E+3 +C1 14 15 9.78E-12 +M3 25 23 12 12 P L=2.5E-6 W=11200E-6 +M4 25 24 11 11 N L=2.5E-6 W=5600E-6 +M5 23 23 12 12 P L=2.5E-6 W=1.35E-6 +M6 24 24 11 11 N L=2.5E-6 W=.525E-6 +GM5 23 11 POLY(1) (15,14) 9.644E-8 2.08E-5 +GM6 12 24 POLY(1) (14,15) 7.5E-8 2.08E-5 +CO1 25 23 1.68E-12 +CO2 25 24 1.68E-12 +.ENDS OpAmp6910 +.subckt switchP 1 2 3 +S1 3 2 1 0 Swp +.model swp vswitch(Ron=1000 Roff=10E6 Von=0.5 Voff=2.2) +.ends switchP +.subckt switchN 1 2 3 +S1 3 2 1 0 SwN +.model swn vswitch(Ron=1000 Roff=10E6 Von=2.2 Voff=0.5) +.ends switchN +.SUBCKT inverter 1 4 8 2 +XSN 1 2 4 SWITCHN +XSP 1 8 2 SWITCHP +.ENDS inverter +.SUBCKT nand2in 1 2 4 8 3 +XI4 1 3 5 SWITCHN +XI3 2 5 4 SWITCHN +XI2 1 8 3 SWITCHP +XI1 2 8 3 SWITCHP +.ENDS nand2in +.SUBCKT nand3in 1 2 3 4 8 5 +XI6 3 7 4 SWITCHN +XI5 2 6 7 SWITCHN +XI4 1 5 6 SWITCHN +XI3 2 8 5 SWITCHP +XI2 3 8 5 SWITCHP +XI1 1 8 5 SWITCHP +.ENDS nand3in +.MODEL DX D(IS=1E-14 RS=5) +.MODEL P PMOS(LEVEL=2 KF=2.5E-26 KP=16E-6 VTO=-.7 LAMBDA=.001 RD=8) +.MODEL N NMOS(LEVEL=2 KF=3.5E-28 KP=52E-6 VTO= .7 LAMBDA=.001 RD=5) +.ENDS LTC6910-3 +* +* INA AGND INB G0 G1 G2 V+ OUTB V- OUTA +.subckt LTC6911-1 INA AGND INB G0 G1 G2 VPLUS OUTB 27 OUTA +R10 22 INA 10K +R2 14 INA 10K +R9 21 INA 10K +R8 20 INA 10K +R7 19 INA 10K +R5 17 INA 10K +R4 16 INA 10K +R3 15 INA 10K +R1 INA 13 10K +R6 18 INA 10K +RI87B 22B INB 10K +RI86B 14B INB 10K +RI85B 21B INB 10K +RI84B 20B INB 10K +RI83B 19B INB 10K +RI82B 17B INB 10K +RI81B 16B INB 10K +RI80B 15B INB 10K +RI79B INB 13B 10K +RI78B 18B INB 10K +R11 24 23 50K +R12 25 24 30K +R13 26 25 10K +R14 OUTA 26 10K +R15 VPLUS AGND 10K +R16 AGND 27 10K +R11B 24B N_1 50K +R12B 25B 24B 30K +R13B 26B 25B 10K +R14B OUTB 26B 10K +R15B VPLUS AGND 10K +R16B AGND 27 10K +RI94 G0A 27 100K +RI93 G1A 27 100K +RI92 G2A 27 100K +XI21 6 27 VPLUS 12 inverter +XI24 G2A 27 VPLUS 1 inverter +XI23 G1A 27 VPLUS 2 inverter +XI22 G0A 27 VPLUS 3 inverter +XI20 3 2 1 27 VPLUS 6 nand3in +XI18 G0A G1A G2A 27 VPLUS 9 nand3in +XI19 G0A G1A 1 27 VPLUS 4 nand3in +XI17 3 2 27 VPLUS 5 nand2in +XI16 4 1 27 VPLUS 7 nand2in +XI15 2 1 27 VPLUS 8 nand2in +XI14 G1A G2A 27 VPLUS 10 nand2in +XI13 5 G2A 27 VPLUS 11 nand2in +C1 OUTA 23 1.6PF +CI88 OUTB N_1 1.6PF +XI53 AGND 23 27 VPLUS OUTA OPAMP6910 +XI54B AGND N_1 27 VPLUS OUTB OPAMP6910 +MI55 22 6 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI54 13 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI63 14 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI62 15 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI61 16 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI60 17 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI59 18 7 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI58 19 7 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI57 20 7 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI56 21 8 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI77B 22B 6 N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI76B 13B G2A N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI75B 14B G2A N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI74B 15B G2A N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI73B 16B G2A N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI72B 17B G2A N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI71B 18B 7 N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI70B 19B 7 N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI69B 20B 7 N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI68B 21B 8 N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI67 24 9 23 27 N L=2U W=24U AS=108P AD=108P PS=57U PD=57U +MI66 25 10 23 27 N L=2U W=48U AS=216P AD=216P PS=105U PD=105U +MI65 26 11 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI64 OUTA 12 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI67B 24B 9 N_1 27 N L=2U W=24U AS=108P AD=108P PS=57U PD=57U +MI66B 25B 10 N_1 27 N L=2U W=48U AS=216P AD=216P PS=105U PD=105U +MI65B 26B 11 N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI64B OUTB 12 N_1 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +XI91 G0 VPLUS G0A SWITCHN +XI90 G1 VPLUS G1A SWITCHN +XI89 G2 VPLUS G2A SWITCHN +* +.subckt OpAmp6910 1 2 11 12 25 +M1 7 3 5 5 P L=2E-6 W=1312E-6 +M2 6 2 5 5 P L=2E-6 W=1312E-6 +RI1 7 8 500 +RI2 6 9 500 +I1 12 5 400E-6 +V1 12 4 .75 +V2 8 11 .6 +V3 9 11 .6 +D1 5 4 DX +Rn 3 10 700 +EVOS 10 1 POLY(2) (17,15) (19,15) -.70m 1 1 +ECM 16 15 POLY(2) (0,15) (2,15) 0 .35 .35 +RCM1 16 17 70E3 +RCM2 17 15 10 +CCM 16 17 6.43E-12 +RPS1 18 19 4.5E3 +RPS2 19 15 1 +CPS 18 19 100p +EPS 18 0 POLY(1) (12,11) 0 1 +E2 15 0 POLY(2) (12,0) (11,0) 0 .5 .5 +GIS 12 11 (12,11) .18m +E1 13 15 POLY(1) (7,6) 0 7 +R1 13 14 1E+3 +C1 14 15 9.78E-12 +M3 25 23 12 12 P L=2.5E-6 W=11200E-6 +M4 25 24 11 11 N L=2.5E-6 W=5600E-6 +M5 23 23 12 12 P L=2.5E-6 W=1.35E-6 +M6 24 24 11 11 N L=2.5E-6 W=.525E-6 +GM5 23 11 POLY(1) (15,14) 9.644E-8 2.08E-5 +GM6 12 24 POLY(1) (14,15) 7.5E-8 2.08E-5 +CO1 25 23 1.68E-12 +CO2 25 24 1.68E-12 +.ENDS OpAmp6910 +.subckt switchP 1 2 3 +S1 3 2 1 0 Swp +.model swp vswitch(Ron=1000 Roff=10E6 Von=0.5 Voff=2.2) +.ends switchP +.subckt switchN 1 2 3 +S1 3 2 1 0 SwN +.model swn vswitch(Ron=1000 Roff=10E6 Von=2.2 Voff=0.5) +.ends switchN +.SUBCKT inverter 1 4 8 2 +XSN 1 2 4 SWITCHN +XSP 1 8 2 SWITCHP +.ENDS inverter +.SUBCKT nand2in 1 2 4 8 3 +XI4 1 3 5 SWITCHN +XI3 2 5 4 SWITCHN +XI2 1 8 3 SWITCHP +XI1 2 8 3 SWITCHP +.ENDS nand2in +.SUBCKT nand3in 1 2 3 4 8 5 +XI6 3 7 4 SWITCHN +XI5 2 6 7 SWITCHN +XI4 1 5 6 SWITCHN +XI3 2 8 5 SWITCHP +XI2 3 8 5 SWITCHP +XI1 1 8 5 SWITCHP +.ENDS nand3in +.MODEL DX D(IS=1E-14 RS=5) +.MODEL P PMOS(LEVEL=2 KF=2.5E-26 KP=16E-6 VTO=-.7 LAMBDA=.001 RD=8) +.MODEL N NMOS(LEVEL=2 KF=3.5E-28 KP=52E-6 VTO= .7 LAMBDA=.001 RD=5) +.ENDS LTC6911-1 +* +* INA AGND INB G0 G1 G2 V+ OUTB V- OUTA +.subckt LTC6911-2 INA AGND INB G0 G1 G2 VPLUS OUTB 27 OUTA +R2 14 INA 10K +R10 22 INA 10K +R9 21 INA 10K +R7 19 INA 10K +R4 16 INA 10K +RI27R3 15 INA 10K +R1 INA 13 10K +R6 18 INA 10K +RI79B 14B INB 10K +RI78B 22B INB 10K +RI77B 21B INB 10K +RI76B 19B INB 10K +RI75B 16B INB 10K +RI74B 15B INB 10K +RI73B INB 13B 10K +RI72B 18B INB 10K +R15 VPLUS AGND 10K +R16 AGND 27 10K +RI84B VPLUS AGND 10K +RI83B AGND 27 10K +R11 24 23 40K +R12 25 24 20K +R13 26 25 10K +R14 OUTA 26 10K +RI92 24B 23B 40K +RI91 25B 24B 20K +RI90 26B 25B 10K +RI89 OUTB 26B 10K +RI98 27 G0A 100K +RI97 27 G1A 100K +RI96 27 G2A 100K +XI24 G2A 27 VPLUS 1 inverter +XI23 G1A 27 VPLUS 2 inverter +XI22 G0A 27 VPLUS 3 inverter +XI21 6 27 VPLUS 12 inverter +XI18 G0A G1A G2A 27 VPLUS 9 nand3in +XI19 G0A G1A 1 27 VPLUS 4 nand3in +XI20 3 2 1 27 VPLUS 6 nand3in +XI17 3 2 27 VPLUS 5 nand2in +XI16 4 1 27 VPLUS 7 nand2in +XI15 2 1 27 VPLUS 8 nand2in +XI14 G1A G2A 27 VPLUS 10 nand2in +XI13 5 G2A 27 VPLUS 11 nand2in +C1 OUTA 23 1.6PF +CI82B OUTB 23B 1.6PF +MI63 13 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI62 15 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI61 16 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI60 19 7 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI59 21 8 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI58 22 6 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI57 14 G2A 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI56 18 7 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI71 13B G2A 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI70 15B G2A 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI69 16B G2A 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI68 19B 7 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI67 21B 8 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI66 22B 6 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI65 14B G2A 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI64 18B 7 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI55 25 10 23 27 N L=2U W=48U AS=216P AD=216P PS=105U PD=105U +MI54 26 11 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI53 OUTA 12 23 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI52 24 9 23 27 N L=2U W=24U AS=108P AD=108P PS=57U PD=57U +MI88 25B 10 23B 27 N L=2U W=48U AS=216P AD=216P PS=105U PD=105U +MI87 26B 11 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI86 OUTB 12 23B 27 N L=2U W=96U AS=432P AD=432P PS=201U PD=201U +MI85 24B 9 23B 27 N L=2U W=24U AS=108P AD=108P PS=57U PD=57U +XI80 AGND 23 27 VPLUS OUTA OPAMP6910 +XI81B AGND 23B 27 VPLUS OUTB OPAMP6910 +XI95 G0 VPLUS G0A SWITCHN +XI94 G1 VPLUS G1A SWITCHN +XI93 G2 VPLUS G2A SWITCHN +.ENDS LTC6911-2 +* +.subckt OpAmp6910 1 2 11 12 25 +M1 7 3 5 5 P L=2E-6 W=1312E-6 +M2 6 2 5 5 P L=2E-6 W=1312E-6 +RI1 7 8 500 +RI2 6 9 500 +I1 12 5 400E-6 +V1 12 4 .75 +V2 8 11 .6 +V3 9 11 .6 +D1 5 4 DX +Rn 3 10 700 +EVOS 10 1 POLY(2) (17,15) (19,15) -.70m 1 1 +ECM 16 15 POLY(2) (0,15) (2,15) 0 .35 .35 +RCM1 16 17 70E3 +RCM2 17 15 10 +CCM 16 17 6.43E-12 +RPS1 18 19 4.5E3 +RPS2 19 15 1 +CPS 18 19 100p +EPS 18 0 POLY(1) (12,11) 0 1 +E2 15 0 POLY(2) (12,0) (11,0) 0 .5 .5 +GIS 12 11 (12,11) .18m +E1 13 15 POLY(1) (7,6) 0 7 +R1 13 14 1E+3 +C1 14 15 9.78E-12 +M3 25 23 12 12 P L=2.5E-6 W=11200E-6 +M4 25 24 11 11 N L=2.5E-6 W=5600E-6 +M5 23 23 12 12 P L=2.5E-6 W=1.35E-6 +M6 24 24 11 11 N L=2.5E-6 W=.525E-6 +GM5 23 11 POLY(1) (15,14) 9.644E-8 2.08E-5 +GM6 12 24 POLY(1) (14,15) 7.5E-8 2.08E-5 +CO1 25 23 1.68E-12 +CO2 25 24 1.68E-12 +.ENDS OpAmp6910 +.subckt switchP 1 2 3 +S1 3 2 1 0 Swp +.model swp vswitch(Ron=1000 Roff=10E6 Von=0.5 Voff=2.2) +.ends switchP +.subckt switchN 1 2 3 +S1 3 2 1 0 SwN +.model swn vswitch(Ron=1000 Roff=10E6 Von=2.2 Voff=0.5) +.ends switchN +.SUBCKT inverter 1 4 8 2 +XSN 1 2 4 SWITCHN +XSP 1 8 2 SWITCHP +.ENDS inverter +.SUBCKT nand2in 1 2 4 8 3 +XI4 1 3 5 SWITCHN +XI3 2 5 4 SWITCHN +XI2 1 8 3 SWITCHP +XI1 2 8 3 SWITCHP +.ENDS nand2in +.SUBCKT nand3in 1 2 3 4 8 5 +XI6 3 7 4 SWITCHN +XI5 2 6 7 SWITCHN +XI4 1 5 6 SWITCHN +XI3 2 8 5 SWITCHP +XI2 3 8 5 SWITCHP +XI1 1 8 5 SWITCHP +.ENDS nand3in +.MODEL DX D(IS=1E-14 RS=5) +.MODEL P PMOS(LEVEL=2 KF=2.5E-26 KP=16E-6 VTO=-.7 LAMBDA=.001 RD=8) +.MODEL N NMOS(LEVEL=2 KF=3.5E-28 KP=52E-6 VTO= .7 LAMBDA=.001 RD=5) +* +.subckt LTC6754 1 2 3 4 5 6 7 8 9 +B1 0 VDIN I=10u*dnlim(uplim(V(4),V(2)+.15,.1), V(3)-.2 ,.1)+1n*V(4) +B2 VDIN 0 I=10u*dnlim(uplim(V(5),V(2)+.15,.1), V(3)-.21, .1)+1n*V(5) +C1 VDIN 0 .5f Rpar=470k +D5 0 VDH0 DLAT +C4 5 3 .55p +C10 4 3 .55p +C7 1 9 200f +C8 9 3 200f +C5 2 5 .55p Rpar=6.5Meg +R3 2 6 378k +A6 N005 0 N002 0 0 0 VDH0 0 OTA g=500u linear Vlow=-1e308 Vhigh=1e308 +D6 0 N005 DLAT +C3 N005 0 1p +G1 0 N005 0 VDH0 500µ +R4 N004 7 14.5k +A8 7 3 0 0 0 N002 0 0 SCHMITT vt=.4 vh=0 trise=1n tfall=1.5n +C11 VH 0 1p Rpar=2k +B3 0 VDIN I=5u*V(VH)*tanh(V(VDH0)/1m) +S6 0 VH 7 3 SHYOFF +D1 VDIN 0 DVGAIN +D3 7 3 DBLE +D2 2 5 DBIASR +D4 5 3 DBIASF +S2 3 2 ON 0 SVCCP +D7 2 4 DBIASR +D8 4 3 DBIASF +C15 1 8 200f +C16 8 3 200f +D10 2 3 DBURNSDI +R1 2 3 19.2k +D11 1 3 DBURNSDO +S8 3 1 ON 0 SVDDP +S9 3 1 ON 0 SVDDP2 +S10 0 VDH0 0 ON SOFF +D12 3 8 DESD +D13 8 1 DESD +D14 9 1 DESD +D15 3 9 DESD +D17 5 2 DESD +D16 3 5 DESD +D18 5 4 DBIASC +C19 2 4 .55p Rpar=6.5Meg +D9 4 2 DESD +D19 3 4 DESD +D20 6 2 DESD +D21 3 6 DESD +C6 6 3 500f +R2 9 Vcm 10Meg +R5 Vcm 8 10Meg +M1 N011 N011 3 3 NPD +M2 9 N011 3 3 NPD M=100 +B4 3 N011 I=(18u+1u*V(ICM))*(1-V(VDH)) +D22 3 N011 DLIM1 +M3 N009 N009 1 1 PPU +M4 9 N009 1 1 PPU M=100 +B5 N009 1 I=(18u-1u*V(ICM))*(V(VDH)+1) +D23 N009 1 DLIM1 +M5 N015 N015 3 3 NPD +M6 8 N015 3 3 NPD M=100 +B6 3 N015 I=(18u+1u*V(ICM))*(V(VDH)+1) +D24 3 N015 DLIM1 +M7 N013 N013 1 1 PPU +M8 8 N013 1 1 PPU M=100 +B7 N013 1 I=(18u-1u*V(ICM))*(1-V(VDH)) +D25 N013 1 DLIM1 +C2 VDH0 0 40f +B8 0 VDH0 I=100u*tanh(V(VDIN)/50m)*uplim(dnlim(100m*V(1,3)+1,1,.1),1.5,.1) +A2 0 VDH0 0 0 0 0 VDH 0 OTA g=2.5m iout=5m Rout=1k Cout=700f vlow=-1 vhigh=1 +C9 VDH0 0 q=120f*dnlim(x,.7,.1)**1.5-100f*dnlim(-x,.7,.1)**1.5 +D26 VDIN 0 DVLIM +C12 9 8 3p +G2 0 VH 7 3 Table(784m 40.3u 959m 37.5u 1.036 24u 1.079 13u 1.106 11u 1.14 7u 1.1581 5u 1.25 4.5u 1.45 0) +S1 1 N009 0 ON SSHUT +S3 N011 3 0 ON SSHUT +S4 1 N013 0 ON SSHUT +S7 N015 3 0 ON SSHUT +A1 6 3 0 0 0 0 N014 0 SCHMITT vt=1 vh=.1 trise=111.5n tfall=110.5n +S11 ICM 0 0 ON SSHUT2 +A3 3 Vcm 0 0 0 0 ICM 0 OTA g=100m iout=18u ref=-1.26 Rout=1Meg Cout=1f vlow=-1e308 vhigh=1e308 +A4 ONF 0 0 0 0 0 ON 0 BUF trise=10n ref=.5 vlow=-1 vhigh=1 +D27 2 6 DSHT +D28 3 7 DESD +D29 7 2 DESD +C13 1 3 5p Rpar=83k +C14 N004 3 1p Rpar=100 +G3 3 N004 ONF 0 12.52m +A5 2 3 0 0 0 0 PowOK 0 SCHMITT vt=2.4 vh=0 trise=200n +A7 PowOK 0 0 0 N014 0 ONF 0 AND trise=111.5n tfall=110.5n +.model SVCCP SW(level=2 Ron=50 Roff=100Meg Vt=.5 Vh=-.2 ilimit=1.624m) +.model SVDDP SW(level=2 Ron=10 Roff=100Meg vt=.5 vh=-.2 ilimit=5.96m) +.model SVDDP2 SW(Ron=4.17k Roff=100Meg vt=.5 vh=-.2) +.model DVGAIN D(Ron=15k Roff=2Meg vfwd=15.3m epsilon=10m vrev=15.3m revepsilon=10m) +.model DVLIM D(Ron=1k Roff=100Meg vfwd=60m epsilon=10m vrev=60m revepsilon=10m) +.model SHYOFF SW(Ron=1 Roff=2k vt=1.65 vh=-100m) +.model DBLE D(Ron=31k Roff=1Meg vfwd=1.3 epsilon=100m) +.model DLAT D(Ron=1 Roff=76k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9) +.model SSHUT SW(Ron=1k Roff=1G vt=0 vh=-.3) +.model SSHUT2 SW(Ron=1k Roff=1G vt=-.3 vh=-.3) +.model DBIASF D(Ron=300k Roff=1G vfwd=-400m epsilon=200m ilimit=.700u ) +.model DBIASR D(Ron=80k Roff=1G vfwd=1 epsilon=150m ilimit=1.8u ) +.model SOFF SW(Ron=1 Roff=100Meg vt=-.5 vh=-.2) +.model DESD D(Ron=100 Roff=1G vfwd=650m epsilon=500m) +.model DBURNSDI D(Ron=100 Roff=1Meg vfwd=1.6 epsilon=500m ilimit=500u) +.model DBURNSDO D(Ron=100 Roff=1Meg vfwd=1.6 epsilon=500m ilimit=209u) +.model DBIASC D(Roff=100Meg Ron=55k vfwd=10u vrev=10u epsilon=10u revepsilon=10u ilimit=1u revilimit=1u) +.model NPD VDMOS(kp=72.45u ksubthres=.1 vto=1) +.model PPU VDMOS(kp=72.45u vto=-1 ksubthres=.1 pchan) +.model DLIM1 D(Ron=100 Roff=1G vfwd=1 epsilon=500m) +.model DSHT D(Ron=10k Roff=100Meg vfwd=2.2 epsilon=500m ilimit=.8u) +.ends LTC6754 +* +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +.subckt LT6018 1 2 3 4 5 6 7 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-2.9,.1), V(4)+2.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-2.89,.1), V(4)+2.89, .1)+1n*V(2) +C10 N004 0 10f Rpar=100K noiseless +C13 3 4 10p +G2 0 N013 4 0 .5m +G4 0 N013 3 0 .5m +C18 N013 0 200p Rpar=1K noiseless +D10 3 4 DPSHDN +R5 3 N008 100Meg noiseless +R6 N008 4 100Meg noiseless +G1 N008 0 N008 3 500m dir=1 vto=0 +G3 0 N008 4 N008 500m dir=1 vto=0 +G6 0 N005 N008 0 1m +C1 N005 0 50p Rpar=1k noiseless +G7 0 VoutP N005 0 1m +L1 VoutP 0 70.7µ Rser=1.111111111111111k Rpar=10k noiseless +C2 3 5 2p Rpar=1g noiseless +C3 5 4 2p Rpar=1g noiseless +Q1 3 N007 5 0 NPN1 temp=27 +Q2 C1 N015 4 0 NPN1 temp=27 +R3 N006 4 10 noiseless +D3 N006 N007 DILIM +B3 3 N015 I=(.5+.5*tanh((V(On)-.5)/10m))*uplim(dnlim(10m*(V(5,VoutP)),dnlim(1m*V(5,VoutP)+60u,60n,10n),1u),6m,10u) +D4 N007 5 DLK +B5 4 N006 I=(.5+.5*tanh((V(On)-.5)/10m))*uplim(100m*(V(VoutP,4)+820m),100m*V(3,4),1m) +A4 0 N004 0 0 0 0 N009 0 OTA g=1m linear Rout=1k enk=.5 en=1.2n*(1+freq/1.1Meg)/(1+freq/28Meg)**2.5 Vlow=-1e308 Vhigh=1e308 +G15 0 N008 N009 0 table(-15,-350m,-10,-165m,-5,-110m,-2,-50m,-1,-30m,-100m,-26m,100m,26m,1,30m,5,66m,15,110m) +C9 N008 0 2.75n +A1 2 1 0 0 0 0 0 0 OTA g=0 in=750f ink=120 incm=2.9p incmk=350 +D1 1 3 DPROT +D2 2 3 DPROT +C4 3 1 1.75p Rser=5k Rpar=100Meg noiseless +C6 4 6 100f +C7 3 2 1.75p Rser=5k Rpar=100Meg noiseless +C8 1 4 1.75p Rser=5k Rpar=100Meg noiseless +C11 2 4 1.75p Rser=5k Rpar=100Meg noiseless +D5 4 6 DPROT +D6 4 7 DPROT +D7 3 6 ENB +A2 6 7 0 0 0 0 N019 0 SCHMITT vt=1.25 vh=400m trise=45u tfall=40u +A3 N017 0 N019 0 N020 0 ON 0 AND trise=100n +D8 1 N012 DBIAS1 +D9 2 N012 DBIAS1 +S2 N012 4 ON 0 Sbias1 +B6 2 4 I=(.5+.5*tanh((V(On)-.5)/10m))*uplim(40u*MAX(V(2,1)-100m,0)**2,110u,80u) +B7 1 4 I=(.5+.5*tanh((V(On)-.5)/100m))*uplim(40u*MAX(V(1,2)-100m,0)**2,110u,80u) +D11 2 1 DBIASZ +S3 2 3 Vdiff 0 SBIAS2 +S4 1 3 0 Vdiff SBIAS2 +B8 3 1 I=5u*(.5+.5*tanh((V(On)-.5)/10m))*(.5+.5*tanh((V(3,1)-.5)/100m)) +B9 3 2 I=5u*(.5+.5*tanh((V(On)-.5)/100m))*(.5+.5*tanh((V(3,2)-.5)/100m)) +A5 3 4 0 0 0 0 N020 0 SCHMITT vt=7.9 vh=0 trise=100u tfall=10u +D12 3 7 ENB +C15 N012 4 100f +C16 4 7 100f +D13 4 1 DPROT +D14 4 2 DPROT +D15 6 3 DPROT +D16 7 3 DPROT +G8 0 Vdiff 1 2 1m +C17 Vdiff 0 1p +S6 Vdiff 0 0 ON SbiasOff +C14 N007 4 1p +C19 5 C1 100f Rpar=1 noiseless +S5 N015 4 4 N014 SNSAT +C20 N014 4 100f Rpar=1Meg noiseless +G5 4 N014 5 4 1µ +B10 N014 4 I=uplim(.4m*MAX(V(5,C1)+22m,0)**2,1u,10n)+uplim(18m*MAX(V(5,C1)-14.2m,0)**2,310n,40n) +C5 2 N010 30.25p +S1 1 N010 On 0 SCAP +S7 3 4 ON 0 SP +D17 3 5 DLKO +A6 3 7 0 0 0 0 N017 0 SCHMITT vt=2.9 vh=0 trise=45u +.model NPN1 NPN(IS=1E-14 VAF=100 BF=80 IKF=20m BR=1 ISC=1e-11 NC=2 IKR=15m CJC=100f CJE=100f noiseless) +.model DILIM D(Ron=600 Roff=600 ilimit=4.8m noiseless) +.model DLK D(Ron=600 Roff=1G vfwd=400m epsilon=300m ilimit=300u noiseless) +.model DLKO D(Ron=1Meg Roff=1G vfwd=400m epsilon=300m ilimit=.1u noiseless) +.model SNSAT SW(level=2 Ron=1 Roff=10Meg vt=113.3m vh=-5m noiseless) +.model DPSHDN D(Ron=1k Roff=1G vfwd=1.5 epsilon=1 ilimit=4.31u noiseless) +.model SP SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.2 ilimit=3.2m noiseless) +.model ENB D(Ron=100k Roff=1G vfwd=1 epsilon=500m ilimit=700n noiseless) +.model DPROT D(Ron=1k Roff=24G Vfwd=1 epsilon=500m noiseless) +.model SCAP SW(Ron=1k Roff=1G vt=.5 vh=-.3 noiseless) +.model SBIAS1 SW(level=2 Ron=100k Roff=1G vt=.5 vh=-200m ilimit=10u noiseless) +.model SBIAS2 SW(level=2 Ron=50k Roff=280Meg vt=4.5 vh=-200m ilimit=95u oneway epsilon=100m noiseless) +.model SbiasOff SW(Ron=1 Roff=1k vt=-.5 vh=-.3 noiseless) +.model DBIAS1 D(Ron=4.5k Roff=1G vfwd=600m epsilon=500m noiseless) +.model DBIASZ D(Ron=50k Roff=1G vfwd=4.5 epsilon=500m vrev=4.5 revepsilon=300m noiseless) +.ends LT6018 +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +* 04-15-2020 +* +.subckt LTC6226 1 2 3 4 5 6 +C7 4 1 500f Rser=100 noiseless +C4 2 1 3p Rser=100 noiseless +C13 4 5 10p +D1 3 4 DESD +D2 5 3 DESD +S5 4 5 _SHDN_D 0 SPOW +D4 4 5 DPOWSD +D6 5 6 DESD +A3 6 4 0 0 0 0 _SHDN 0 SCHMITT vt=-2.175 vh=575m trise=4.126u tfall=1500n +D7 6 4 DESD +C6 5 6 100f +D5 2 4 DESD +D8 5 2 DESD +D11 1 4 DESD +D12 5 1 DESD +D20 4 2 DBIAS2 +D18 4 1 DBIAS2 +C8 3 N004 7p +C21 N005 0 {C1_P1} Rpar={1/alpha_P1} noiseless +G11 0 N006 N005 0 {alpha_P2} +C16 N006 0 {C1_P2} Rpar={1/alpha_P2} noiseless +A1 0 N007 Mid Mid Mid Mid X1 Mid OTA g=26m iout=2.8m vlow=-1e308 vhigh=1e308 +C1 4 2 500f Rser=100 noiseless +C3 1 5 500f Rser=100 noiseless +C5 2 5 500f Rser=100 noiseless +D3 4 PG DLIMP +D9 NG 5 DLIMN +C17 NG 5 100f Rser=500 noiseless +C24 4 3 1p Rpar=200k noiseless +Q1 3 NG 5 0 NPN1 temp=27 +Q2 3 PG 4 0 PNP1 temp=27 +C20 3 PG 3.4p Rser=250 noiseless +C11 N012 PG 3.6p +C9 X1 NG 3.6p +C12 4 PG 100f Rser=22 noiseless +C15 X1 N013 1p +R12 N013 Mid 2k noiseless +B7 N013 Mid I=20m*dnlim(uplim(V(X1,Mid),300m,100m)-150m,0,10m) +C19 N007 0 {C1_PZ1} Rpar={R2_PZ1} Rser={R1_PZ1} noiseless +G10 0 N007 N006 0 {alpha_PZ1} +C25 X1 Mid 1p Rser=10 noiseless +R13 X1 N012 10 noiseless +B9 N012 X1 I=uplim(100m*dnlim(1m-V(X1,Mid),0,10m),3m,1m) +B10 Mid N013 I=40m*dnlim(-150m+uplim(-V(X1,Mid),300m,100m),0,10m) +D15 2 1 DIN +D16 SL 0 DVARSLW1 +D17 SL 0 DVARSLW2 +D10 4 2 DBIAS1 +D13 4 1 DBIAS1 +D14 2 1 DBIASD +S1 4 PG 0 _SHDN_D SWoff +S2 NG 5 0 _SHDN_D SWoff +S3 X1 Mid 0 _SHDN_D SWoff2 +C14 3 NG 3.4p Rser=250 noiseless +A4 0 2 0 0 0 0 0 0 OTA g=0 in=1p ink=200k +A7 0 1 0 0 0 0 0 0 OTA g=0 in=1p ink=200k +A6 N008 0 _SHDN_D 0 0 0 N005 0 OTA g={alpha_P1} linear en=1n enk=3.5k vlow=-1e308 vhigh=1e308 +D25 N005 0 DLIM2 +D26 X1 Mid DLIM1 +A2 _SHDN 0 0 0 0 0 _SHDN_D 0 BUF trise=100n +D21 4 6 DPULLUP +G8 6 5 6 4 2µ vto=-1.25 dir=1 +C10 Mid 0 10p Rpar=10 noiseless +G1 0 Mid 4 0 100m +G2 0 Mid 5 0 100m +R4 N004 X1 1k noiseless +G14 Mid 4 N004 X1 500µ +G13 Mid 5 N004 X1 500µ +D19 X1 Mid DSI N=.36 temp =27 +B1 0 N008 I=10u*dnlim(uplim(V(1),V(4)-1.19,10m), V(5)-.2, 10m) +B2 N008 0 I=10u*dnlim(uplim(V(2),V(4)-1.19,10m), V(5)-.2, 10m) +C2 N008 0 .1f Rpar=100K noiseless +G20 0 N008 1 2 1n +B5 0 SL I=dnlim(350u*V(4,5)-600u,100u,10u) +C18 3 5 1p Rpar=200k noiseless +S4 4 5 0 _SHDN_D SPOWSD +B4 PG 4 I=vminp/2e3-500u*(V(X1,Mid)-voffp) +B6 PG 4 I=1m*(.5+.5*tanh((715m-V(4,PG))/1m)) +B11 PG 4 I=1m*V(SL)*dnlim(-200m-V(X1,Mid),0,20m) +B13 4 PG I=1m*V(SL)*dnlim(V(X1,Mid)-200m,0,20m) +B3 5 NG I=vminn/2e3+500u*(V(X1,Mid)+voffn) +B8 5 NG I=1m*(.5+.5*tanh((715m-V(NG,5))/1m)) +B12 NG 5 I=1m*V(SL)*dnlim(-200m-V(X1,Mid),0,20m) +B14 5 NG I=1m*V(SL)*dnlim(V(X1,Mid)-200m,0,20m) +.model SPOW SW(Ron=100 Roff=10G vt=.5 vh=-.3 ilimit=5m noiseless) +.model SPOWSD SW(Ron=56K Roff=1G vt=-.5 vh=-.3 noiseless) +.model DPOWSD D(Ron=1K Roff=1G vfwd=600m epsilon=500m ilimit=114u noiseless) +.model DESD D(Ron=100 Roff=1g Vfwd=700m epsilon=500m noiseless) +.model DPULLUP D(Ron=580k Roff=100Meg vfwd=1.2 epsilon=500m noiseless) +.param vs=10 +.model DBIAS1 D(Ron=6Meg Roff=1G vfwd=100m epsilon=100m noiseless) +.model DBIAS2 D(Ron=1k Roff=1G vfwd=100m epsilon=100m ilimit=8u noiseless) +.model DBIASD D(Ron=4.7k Roff=4.7k vrev=0 ilimit=9u revilimit=9u noiseless) +.model DIN D(Ron=100 Roff=1G vfwd=700m epsilon=500m vrev=700m revepsilon=500m noiseless) +.param alpha_P1=1.0e-3 pole_P1=4e8 ++ C1_P1 = alpha_P1/(2*pi*pole_P1) +.param alpha_P2=1.0e-3 pole_P2=4e8 ++ C1_P2 = alpha_P2/(2*pi*pole_P2) +.param vminp = 400m +.param voffp = 360m +.param vminn=400m +.param voffn = 360m +.model DLIMN D(Ron=10 Roff=2k Vfwd=880m epsilon=10m noiseless) +.model DLIMP D(Ron=10 Roff=2k Vfwd=880m epsilon=10m noiseless) +.model NPN1 NPN(IS=1e-16 BF=500 BR=1.2 Quasimod RCO=25 VO=10 VAF=500 noiseless) +.model PNP1 PNP(IS=1e-16 BF=500 BR=1.5 RC=16 VAF=500 noiseless) +.model SWoff SW(Ron=10 Roff=7Meg vt=-500m vh=-100m noiseless) +.param alpha_PZ1=1.0e-3 pole_PZ1=2e7 zero_PZ1=7e7 ++ R2_PZ1=1.0/alpha_PZ1 R1_PZ1=1.0/(alpha_PZ1*(zero_PZ1/pole_PZ1 - 1.0)) ++C1_PZ1=1.0/(2.0*pi*zero_PZ1*R1_PZ1) +.model DVARSLW1 D(Ron=1k Roff=10k vfwd=900m epsilon=200m noiseless) +.model DVARSLW2 D(Ron=10 Roff=1k vfwd=1.34 epsilon=200m vrev=100m revepsilon=100m noiseless) +.model DSI D(IS=1e-15 Rs=150k noiseless) +.model SWoff2 SW(Ron=10 Roff=14Meg vt=-500m vh=-100m noiseless) +.model DLIM1 D(Ron=10 Roff=14Meg vfwd=465m epsilon=30m vrev=465m revepsilon=30m noiseless) +.model DLIM2 D(Ron=10 Roff=100Meg vfwd=100m epsilon=30m vrev=100m revepsilon=30m noiseless) +.ends LTC6226 +* +* +* Copyright (c) 1998-2021 Analog Devices, Inc. All rights reserved. +* +.subckt LTC6228 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-1.1,.1), V(5)-.2, .1)+1n*V(1) + 3.5456p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-1.09,.1), V(5)-.21, .1)+1n*V(2) +C10 N004 0 .1f Rpar=100K noiseless +C16 XC N009 20p +C7 4 1 750f Rser=1k noiseless +C4 2 1 3.5p Rser=1k noiseless +C13 4 5 10p +D1 3 4 DESD +D2 5 3 DESD +C20 XC 0 1p +D3 XC 0 DANTISAT +G4 0 N007 N006 0 1m +S5 4 5 _SHDN 0 SPOW +D4 4 5 DPOWSD +M3 3 PG 4 4 PI temp=27 +M4 3 NG 5 5 NI temp=27 +D9 4 PG DLIMP +D10 NG 5 DLIMN +B7 5 NG I=(.5+.5*tanh((V(_SHDN)-500m)/100m))*dnlim(550n+1.2u*(V(XC)+270m),550n,100n) +B8 PG 4 I=(.5+.5*tanh((V(_SHDN)-500m)/100m))*dnlim(522n-1.2u*(V(XC)-270m),522n,100n) +C19 4 3 100f +C22 3 5 100f +C8 N008 0 80f Rpar=1k noiseless +C11 N006 0 3.7p Rser=538 Rpar=1k noiseless +G7 0 N008 N007 0 1m +R6 4 Mid 15.5k noiseless +D6 5 6 DESD +S1 6 4 4 6 SWSHT +G1 6 5 6 4 1µ vto=-1.5 dir=1 +A2 4 6 0 0 0 0 _BCANCL 0 SCHMITT vt=500m vh=10m trise=100n +C2 4 6 1p +A3 4 6 0 0 0 _SHDN 0 0 SCHMITT vt=2.5 vh=10m trise=1.2u +D7 6 4 DESD +C6 5 6 100f +D5 2 4 DESD +D8 5 2 DESD +D11 1 4 DESD +D12 5 1 DESD +D13 2 1 DIN +S6 4 N010 _BCANCL 0 SWBIAS1 +C23 4 N010 1p rpar=2Meg noiseless +S10 4 N010 N005 0 SWBIAS2 +D20 N010 2 DBIAS +D18 N010 1 DBIAS +C27 N005 0 1p rpar=1k noiseless +I4 0 N005 1m +S11 0 N005 _BCANCL 0 SWBIAS3 +G8 0 N005 5 N010 1m +C21 N007 0 80f Rpar=1k noiseless +A5 _SHDN 0 0 0 0 0 _SHDN_D 0 BUF trise=100n +R4 Mid 5 15.5k noiseless +C1 1 5 750f Rser=1k noiseless +C3 4 2 750f Rser=1k noiseless +C5 2 5 750f Rser=1k noiseless +R5 N009 0 1 noiseless +G3 0 N009 3 Mid 1 +C15 X4 0 80f Rpar=1k noiseless +G9 0 X4 N008 0 1m +C17 4 PG .82f Rser=1.75Meg noiseless +C12 NG 5 .82f Rser=1.75Meg noiseless +B3 0 XC I=dnlim(uplim(10.2m*tanh(11.275*V(X4)),10.2m*dnlim(V(SLWFAC),.2,.1),2m),-10.2m*dnlim(V(SLWFAC),.2,.1),2m) +G2 0 SLWFAC 4 5 150µ +C18 SLWFAC 0 100p Rpar=1k +I1 SLWFAC 0 50µ +S2 N013 0 _BCANCL 0 SWN +G5 0 2 N013 0 1n +S3 N015 0 _BCANCL 0 SWN +G6 0 1 N015 0 1n +A8 N015 0 0 0 0 0 0 0 OTA g=0 in=2.8n*((1+.3/freq)*(1+300k/freq))**.4 +A1 N013 0 0 0 0 0 0 0 OTA g=0 in=2.8n*((1+.3/freq)*(1+300k/freq))**.4 +A6 N004 0 _SHDN_D 0 0 0 N006 0 OTA g=1m linear en=.88n enk=45k vlow=-400m vhigh=400m +.model DANTISAT D(Ron=100 Roff=623k vfwd=300m epsilon=100m vrev=300m revepsilon=100m noiseless) +.model SWSHT SW(Ron=600k Roff=1G vt=900m vh=-600m noiseless) +.model SPOW SW(Ron=100 Roff=10G vt=.5 vh=-.3 ilimit=2.9m noiseless) +.model DPOWSD D(Ron=1K Roff=1G vfwd=600m epsilon=500m ilimit=128u noiseless) +.model DESD D(Ron=100 Roff=1g Vfwd=700m epsilon=500m noiseless) +.model SWN SW(Ron=1Meg Roff=2Meg vt=.5 vh=-200m noiseless) +.param vs=10 +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.model PI VDMOS(Vto=-300m kp=80m mtriode=.8 ksubthres=10m lambda=5e-5 pchan noiseless) +.model NI VDMOS(Vto=300m kp=90m mtriode=1.2 ksubthres=10m lambda=5e-5 noiseless) +.model DIN D(Ron=100 Roff=1G vfwd=700m epsilon=500m vrev=700m revepsilon=500m noiseless) +.model SWBIAS1 SW(level=2 ron=100 roff=1G vt=.5 vh=-200m ilimit=30u noiseless) +.model SWBIAS2 SW(level=2 ron=100 roff=1G vt=.4 vh=-50m ilimit=32u noiseless) +.model SWBIAS3 SW(ron=1 Roff=1G vt=500m vh=-200m noiseless) +.model DBIAS D(Ron=500 Roff=1G vfwd=100m epsilon=100m noiseless) +.ends LTC6228 +* +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +.subckt LT6370 1 2 3 4 5 6 7 8 +G2 0 N002 N003 0 1m +C3 N002 0 27p Rpar=1k noiseless +C5 7 2 7.95p +C6 7 1 .1p +R1 A1out INNF 10k +CG4 7 6 1p +CG5 6 4 1p +M3 7 N002 A1out A1out NINT temp=27 +M4 4 N002 A1out A1out PINT temp=27 +M5 7 N017 A2out A2out NINT temp=27 +M6 4 N017 A2out A2out PINT temp=27 +G3 0 N017 N016 0 1m +C17 N017 0 27p Rpar=1k noiseless +C20 2 3 .9p +DB2 7 4 DP +C4 7 N003 180p Rpar=200Meg noiseless +A1 1 2X 0 0 0 0 N003 0 OTA g=30m iout=5m en=4.9n enk=2.5 Vhigh=1e308 Vlow=-1e308 +G4 N003 0 N003 7 100m vto=-600m dir=1 +G6 0 N003 4 N003 100m vto=-600m dir=1 +A2 8 3X 0 0 0 0 N016 0 OTA g=30m iout=5m en=4.9n enk=2.5 Vhigh=1e308 Vlow=-1e308 +D11 1 7 DESD +D12 4 1 DESD +D13 8 7 DESD +D14 4 8 DESD +C13 N003 4 180p Rpar=200Meg noiseless +C15 7 N016 180p Rpar=200Meg noiseless +C16 N016 4 180p Rpar=200Meg noiseless +C8 INNF INPF 100f +M1 N005 PG 7 7 PI temp=27 +M2 6 NG 4 4 NI temp=27 +D1 7 PG DLIMP +D2 NG 4 DLIMN +C10 7 PG 1f Rser=400k noiseless +C14 NG 4 1f Rser=400k noiseless +B5 4 NG I=dnlim(400n+.7u*(V(XC)+240m),400n,200n) +B6 PG 7 I=dnlim(400n-.7u*(V(XC)-240m),400n,200n) +R8 N005 6 1 noiseless +I1 6 N005 800m +R9 7 Mid 1Meg noiseless +B7 0 N009 I=10u*dnlim(uplim(V(INPF),V(7)-1.59,.1), V(4)-.2, .1)+1n*V(INPF)-31.5p +B8 N009 0 I=10u*dnlim(uplim(V(INNF),V(7)-1.60,.1), V(4)-.21, .1)+1n*V(INNF) +C18 N009 0 .1f Rpar=100K noiseless +C19 XC N010 10p +C21 XC 0 1p +D3 XC 0 DANTISAT +C22 N008 0 8p Rpar=1k noiseless +G5 0 N008 N007 0 1m +C26 N007 0 8p Rpar=1k noiseless +R11 N010 0 1 noiseless +G11 0 N010 6 Mid 1 +A6 0 N008 0 0 0 0 XC 0 OTA g=250u iout=125u vlow=-1e308 vhigh=1e308 +C25 7 A1out 100f +C27 A1out 4 100f +C28 7 A2out 100f +C29 A2out 4 100f +G1 0 N016 4 N016 100m vto=-600m dir=1 +G7 N016 0 N016 7 100m vto=-600m dir=1 +R10 Mid 4 1Meg noiseless +A7 N009 0 0 0 0 0 N007 0 OTA g=1m linear en=26n enk=1.1 vlow=-1e308 vhigh=1e308 +C1 2 4 7.95p +C2 7 3 7.95p +C7 3 4 7.95p +A3 2 0 0 0 0 0 0 0 OTA g=0 in=93.4f ink=3 +A8 3 0 0 0 0 0 0 0 OTA g=0 in=93.4f ink=3 +A9 2 3 0 0 0 0 0 0 OTA g=0 incm=176.8f incmk=1.8 +R13 A1out 1 12.1k +A10 N004 0 4 4 4 4 1 4 OTA g=200u iout=300u vlow=-1e309 vhigh=1e309 +L3 N004 0 102.3µ Rser=4.5k Rpar=1.286k noiseless +C9 1 4 .1p +C11 7 8 .1p +C12 8 4 .1p +D4 2 7 DESD +D5 4 2 DESD +G9 0 N004 1 2X 1m +R14 2X 0 1k noiseless +I3 0 2X 600µ +R15 A2out 8 12.1k +A11 N014 0 4 4 4 4 8 4 OTA g=200u iout=300u vlow=-1e309 vhigh=1e309 +L1 N014 0 102.3µ Rser=4.5k Rpar=1.286k noiseless +I4 0 3X 600µ +G15 0 N014 8 3X 1m +B9 0 2X I=999.9u*dnlim(uplim(V(2),V(7)-1.25,.1), V(4)+1.7, .1)+100n*V(2) +B10 0 3X I=999.9u*dnlim(uplim(V(3),V(7)-1.25,.1), V(4)+1.7, .1)+100n*V(3) +D6 4 5 DESD +R6 3X 0 1k noiseless +R2 INNF 6 10k +R3 A2out INPF 10k +R4 INPF 5 10k +D7 INNF INPF DSI temp=27 +D8 INPF INNF DSI temp=27 +D9 4 3 DESD +D10 3 7 DESD +.model DP D(Ron=100 Roff=1G Vfwd=.6 epsilon=500m ilimit=1.47m noiseless) +.model NINT VDMOS(Vto=-40m Kp=100m noiseless) +.model PINT VDMOS(Vto=40m Kp=100m pchan noiseless) +.model DESD D(Ron=100 Roff=400G vfwd=600m epsilon=500m noiseless) +.model PI VDMOS(Vto=-300m kp=30m mtriode=.3 ksubthres=10m lambda=5e-4 pchan noiseless) +.model NI VDMOS(Vto=300m kp=25m mtriode=.4 ksubthres=10m lambda=5e-4 noiseless) +.model DANTISAT D(Ron=100 Roff=25.5Meg vfwd=3 epsilon=100m vrev=3 revepsilon=100m noiseless) +.param RG= 100T +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2.3 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.model DSI D(Is=1e-16 TT=200n noiseless) +.ends LT6370 + + diff --git a/spice/copy/sub/LTC1040.sub b/spice/copy/sub/LTC1040.sub new file mode 100755 index 0000000..58afe4e Binary files /dev/null and b/spice/copy/sub/LTC1040.sub differ diff --git a/spice/copy/sub/LTC1041.sub b/spice/copy/sub/LTC1041.sub new file mode 100755 index 0000000..064f572 Binary files /dev/null and b/spice/copy/sub/LTC1041.sub differ diff --git a/spice/copy/sub/LTC1042.sub b/spice/copy/sub/LTC1042.sub new file mode 100755 index 0000000..60e6773 Binary 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a/spice/copy/sub/LTC1775.sub b/spice/copy/sub/LTC1775.sub new file mode 100755 index 0000000..4a7a44a Binary files /dev/null and b/spice/copy/sub/LTC1775.sub differ diff --git a/spice/copy/sub/LTC1778-1.sub b/spice/copy/sub/LTC1778-1.sub new file mode 100755 index 0000000..c30b51f Binary files /dev/null and b/spice/copy/sub/LTC1778-1.sub differ diff --git a/spice/copy/sub/LTC1778.sub b/spice/copy/sub/LTC1778.sub new file mode 100755 index 0000000..904213f Binary files /dev/null and b/spice/copy/sub/LTC1778.sub differ diff --git a/spice/copy/sub/LTC1779.sub b/spice/copy/sub/LTC1779.sub new file mode 100755 index 0000000..cb756fc Binary files /dev/null and b/spice/copy/sub/LTC1779.sub differ diff --git a/spice/copy/sub/LTC1798.lib b/spice/copy/sub/LTC1798.lib new file mode 100755 index 0000000..6dd5fc2 --- /dev/null +++ b/spice/copy/sub/LTC1798.lib @@ -0,0 +1,20 @@ +* Copyright © Linear Technology Corp. 2004. All rights reserved. +* +.subckt LTC1798 1 2 3 4 +S1 4 2 N001 4 T +S2 1 4 4 N001 B +A1 3 1 0 0 0 0 N001 0 OTA G={Avol/Rout} Ref=2.385 Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} Vhigh=1e308 Vlow=-1e308 +C3 4 1 1p +C4 2 4 1p +R2 N001 1 {2*Rout} noiseless +R1 2 N001 {2*Rout} noiseless +G1 0 N001 1 N001 table(0 0 10 {2*slew*Cout}) +G2 N001 0 N001 2 table(0 0 10 {2*slew*Cout}) +R3 3 1 238.5Meg +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model T SW(Ron=200 Roff=2G Vt=0 Vh=-.1 Vser={Rail} ilimit=15m noiseless) +.param Avol=1Meg GBW=100K Slew=100K rail=0 +.param en=0 enk=0 in=0 ink=0 +.model B SW(Ron=200 Roff=2G Vt=0 Vh=-.1 Vser={Rail} ilimit=3m noiseless) +.ends LTC1798 diff --git a/spice/copy/sub/LTC1799.sub b/spice/copy/sub/LTC1799.sub new file mode 100755 index 0000000..653ac89 Binary files /dev/null and b/spice/copy/sub/LTC1799.sub differ diff --git a/spice/copy/sub/LTC1844.lib b/spice/copy/sub/LTC1844.lib new file mode 100755 index 0000000..28071cb --- /dev/null +++ b/spice/copy/sub/LTC1844.lib @@ -0,0 +1,188 @@ +* Copyright © Linear Technology Corp. 2014. All rights reserved. +* +.subckt LTC1844-1.5 1 2 3 4 +C4 3 2 1p +C7 N005 2 10f Rpar=1Meg +C1 4 2 1p +M1 4 N003 S S P1 temp=27 +C2 1 2 1p +C3 N003 1 100f Rpar=1Meg noiseless +A1 N005 N004 ON2 0 0 0 N006 0 OTA g=1.55u linear Rout=100Meg en=280n vlow=0 vhigh=10 +G1 N003 1 N006 0 1µ +C5 N004 2 1.5p Rpar=1Meg noiseless +I2 2 N004 1.25µ +G2 N004 2 2 N003 1m vto=0 dir=1 +G3 2 N004 1 2 833p +R2 S 1 .11 noiseless +G4 N004 0 1 S 100m vto=35m dir=1 +A2 0 ON 0 0 0 0 ON2 0 OTA g=1u iout=10u Cout=100f Rout=2Meg vlow=0 vhigh=1 +S1 ON2 0 4 1 SREV +S2 N003 4 4 1 SREV2 +A4 3 2 0 0 0 0 ON 0 SCHMITT vt=.65 vh=50m trise=90u +C9 N004 1 1p Rser=200Meg noiseless +B3 1 2 I=V(ON)*table(V(1,4) ,-100, 7u, -1, 7u, -.8, 15u, -50m, 15u, -10m, 35u, 100, 35u) +B1 4 2 I=V(ON)*table(V(1,4) ,-100, 5u, -270m, 5u, -20m, 5u, 0, 0) +C10 N006 0 100f Rser=10Meg noiseless +G6 N003 1 ON2 0 800n +C8 N004 1 100f +R3 4 N005 200k +.model P1 VDMOS(mtriode=1.1 Vto=-1.05 Kp=.85 lambda=1u Cgdmax=100f Cgdmin=100f pchan is=0 ) +.model SREV SW(Ron=1 Roff=1G vt=-10m vh=-20m noiseless) +.model SREV2 SW(Ron=1 Roff=1G vt=295m vh=-50m noiseless) +.ends LTC1844-1.5 +* +.subckt LTC1844-1.8 1 2 3 4 +C4 3 2 1p +C7 N005 2 10f Rpar=1Meg +C1 4 2 1p +M1 4 N003 S S P1 temp=27 +C2 1 2 1p +C3 N003 1 100f Rpar=1Meg noiseless +A1 N005 N004 ON2 0 0 0 N006 0 OTA g=1.55u linear Rout=100Meg en=280n vlow=0 vhigh=10 +G1 N003 1 N006 0 1µ +C5 N004 2 1.5p Rpar=1Meg noiseless +I2 2 N004 1.25µ +G2 N004 2 2 N003 1m vto=0 dir=1 +G3 2 N004 1 2 833p +R2 S 1 .11 noiseless +G4 N004 0 1 S 100m vto=35m dir=1 +A2 0 ON 0 0 0 0 ON2 0 OTA g=1u iout=10u Cout=100f Rout=2Meg vlow=0 vhigh=1 +S1 ON2 0 4 1 SREV +S2 N003 4 4 1 SREV2 +A4 3 2 0 0 0 0 ON 0 SCHMITT vt=.65 vh=50m trise=90u +C9 N004 1 1p Rser=200Meg noiseless +B3 1 2 I=V(ON)*table(V(1,4) ,-100, 7u, -1, 7u, -.8, 15u, -50m, 15u, -10m, 35u, 100, 35u) +B1 4 2 I=V(ON)*table(V(1,4) ,-100, 5u, -270m, 5u, -20m, 5u, 0, 0) +C10 N006 0 100f Rser=10Meg noiseless +G6 N003 1 ON2 0 800n +C8 N004 1 100f +R3 4 N005 440k +.model P1 VDMOS(mtriode=1.1 Vto=-1.05 Kp=.85 lambda=1u Cgdmax=100f Cgdmin=100f pchan is=0 ) +.model SREV SW(Ron=1 Roff=1G vt=-10m vh=-20m noiseless) +.model SREV2 SW(Ron=1 Roff=1G vt=295m vh=-50m noiseless) +.ends LTC1844-1.8 +* +.subckt LTC1844-2.5 1 2 3 4 +C4 3 2 1p +C7 N005 2 10f Rpar=1Meg +C1 4 2 1p +M1 4 N003 S S P1 temp=27 +C2 1 2 1p +C3 N003 1 100f Rpar=1Meg noiseless +A1 N005 N004 ON2 0 0 0 N006 0 OTA g=1.55u linear Rout=100Meg en=280n vlow=0 vhigh=10 +G1 N003 1 N006 0 1µ +C5 N004 2 1.5p Rpar=1Meg noiseless +I2 2 N004 1.25µ +G2 N004 2 2 N003 1m vto=0 dir=1 +G3 2 N004 1 2 833p +R2 S 1 .11 noiseless +G4 N004 0 1 S 100m vto=35m dir=1 +A2 0 ON 0 0 0 0 ON2 0 OTA g=1u iout=10u Cout=100f Rout=2Meg vlow=0 vhigh=1 +S1 ON2 0 4 1 SREV +S2 N003 4 4 1 SREV2 +A4 3 2 0 0 0 0 ON 0 SCHMITT vt=.65 vh=50m trise=90u +C9 N004 1 1p Rser=200Meg noiseless +B3 1 2 I=V(ON)*table(V(1,4) ,-100, 7u, -1, 7u, -.8, 15u, -50m, 15u, -10m, 35u, 100, 35u) +B1 4 2 I=V(ON)*table(V(1,4) ,-100, 5u, -270m, 5u, -20m, 5u, 0, 0) +C10 N006 0 100f Rser=10Meg noiseless +G6 N003 1 ON2 0 800n +C8 N004 1 100f +R3 4 N005 1Meg +.model P1 VDMOS(mtriode=1.1 Vto=-1.05 Kp=.85 lambda=1u Cgdmax=100f Cgdmin=100f pchan is=0 ) +.model SREV SW(Ron=1 Roff=1G vt=-10m vh=-20m noiseless) +.model SREV2 SW(Ron=1 Roff=1G vt=295m vh=-50m noiseless) +.ends LTC1844-2.5 +* +.subckt LTC1844-2.8 1 2 3 4 +C4 3 2 1p +C7 N005 2 10f Rpar=1Meg +C1 4 2 1p +M1 4 N003 S S P1 temp=27 +C2 1 2 1p +C3 N003 1 100f Rpar=1Meg noiseless +A1 N005 N004 ON2 0 0 0 N006 0 OTA g=1.55u linear Rout=100Meg en=280n vlow=0 vhigh=10 +G1 N003 1 N006 0 1µ +C5 N004 2 1.5p Rpar=1Meg noiseless +I2 2 N004 1.25µ +G2 N004 2 2 N003 1m vto=0 dir=1 +G3 2 N004 1 2 833p +R2 S 1 .11 noiseless +G4 N004 0 1 S 100m vto=35m dir=1 +A2 0 ON 0 0 0 0 ON2 0 OTA g=1u iout=10u Cout=100f Rout=2Meg vlow=0 vhigh=1 +S1 ON2 0 4 1 SREV +S2 N003 4 4 1 SREV2 +A4 3 2 0 0 0 0 ON 0 SCHMITT vt=.65 vh=50m trise=90u +C9 N004 1 1p Rser=200Meg noiseless +B3 1 2 I=V(ON)*table(V(1,4) ,-100, 7u, -1, 7u, -.8, 15u, -50m, 15u, -10m, 35u, 100, 35u) +B1 4 2 I=V(ON)*table(V(1,4) ,-100, 5u, -270m, 5u, -20m, 5u, 0, 0) +C10 N006 0 100f Rser=10Meg noiseless +G6 N003 1 ON2 0 800n +C8 N004 1 100f +R3 4 N005 1.24Meg +.model P1 VDMOS(mtriode=1.1 Vto=-1.05 Kp=.85 lambda=1u Cgdmax=100f Cgdmin=100f pchan is=0 ) +.model SREV SW(Ron=1 Roff=1G vt=-10m vh=-20m noiseless) +.model SREV2 SW(Ron=1 Roff=1G vt=295m vh=-50m noiseless) +.ends LTC1844-2.8 +* +.subckt LTC1844-3.3 1 2 3 4 +C4 3 2 1p +C7 N005 2 10f Rpar=1Meg +C1 4 2 1p +M1 4 N003 S S P1 temp=27 +C2 1 2 1p +C3 N003 1 100f Rpar=1Meg noiseless +A1 N005 N004 ON2 0 0 0 N006 0 OTA g=1.55u linear Rout=100Meg en=280n vlow=0 vhigh=10 +G1 N003 1 N006 0 1µ +C5 N004 2 1.5p Rpar=1Meg noiseless +I2 2 N004 1.25µ +G2 N004 2 2 N003 1m vto=0 dir=1 +G3 2 N004 1 2 833p +R2 S 1 .11 noiseless +G4 N004 0 1 S 100m vto=35m dir=1 +A2 0 ON 0 0 0 0 ON2 0 OTA g=1u iout=10u Cout=100f Rout=2Meg vlow=0 vhigh=1 +S1 ON2 0 4 1 SREV +S2 N003 4 4 1 SREV2 +A4 3 2 0 0 0 0 ON 0 SCHMITT vt=.65 vh=50m trise=90u +C9 N004 1 1p Rser=200Meg noiseless +B3 1 2 I=V(ON)*table(V(1,4) ,-100, 7u, -1, 7u, -.8, 15u, -50m, 15u, -10m, 35u, 100, 35u) +B1 4 2 I=V(ON)*table(V(1,4) ,-100, 5u, -270m, 5u, -20m, 5u, 0, 0) +C10 N006 0 100f Rser=10Meg noiseless +G6 N003 1 ON2 0 800n +C8 N004 1 100f +R3 4 N005 1.64Meg +.model P1 VDMOS(mtriode=1.1 Vto=-1.05 Kp=.85 lambda=1u Cgdmax=100f Cgdmin=100f pchan is=0 ) +.model SREV SW(Ron=1 Roff=1G vt=-10m vh=-20m noiseless) +.model SREV2 SW(Ron=1 Roff=1G vt=295m vh=-50m noiseless) +.ends LTC1844-3.3 +* +.subckt LTC1844-SD 1 2 3 4 5 +C4 3 2 1p +C7 4 2 1p +C1 5 2 1p +M1 5 N003 S S P1 temp=27 +C2 1 2 1p +C3 N003 1 100f Rpar=1Meg noiseless +D1 4 2 DADJB +A1 4 N004 ON2 0 0 0 N006 0 OTA g=1.55u linear Rout=100Meg en=280n vlow=0 vhigh=10 +G1 N003 1 N006 0 1µ +C5 N004 2 1.5p Rpar=1Meg noiseless +I2 2 N004 1.25µ +G2 N004 2 2 N003 1m vto=0 dir=1 +G3 2 N004 1 2 833p +R2 S 1 .11 noiseless +G4 N004 0 1 S 100m vto=35m dir=1 +A2 0 ON 0 0 0 0 ON2 0 OTA g=1u iout=10u Cout=100f Rout=2Meg vlow=0 vhigh=1 +S1 ON2 0 5 1 SREV +S2 N003 5 5 1 SREV2 +A4 3 2 0 0 0 0 ON 0 SCHMITT vt=.65 vh=50m trise=90u +C9 N004 1 1p Rser=200Meg noiseless +B3 1 2 I=V(ON)*table(V(1,5) ,-100, 7u, -1, 7u, -.8, 15u, -50m, 15u, -10m, 35u, 100, 35u) +B1 5 2 I=V(ON)*table(V(1,5) ,-100, 5u, -270m, 5u, -20m, 5u, 0, 0) +C10 N006 0 100f Rser=10Meg noiseless +G6 N003 1 ON2 0 800n +C8 N004 1 100f +.model P1 VDMOS(mtriode=1.1 Vto=-1.05 Kp=.85 lambda=1u Cgdmax=100f Cgdmin=100f pchan is=0 ) +.model DADJB D(Ron=100k Roff=1G vfwd=600m epsilon=500m ilimit=30n noiseless) +.model SREV SW(Ron=1 Roff=1G vt=-10m vh=-20m noiseless) +.model SREV2 SW(Ron=1 Roff=1G vt=295m vh=-50m noiseless) +.ends LTC1844-SD diff --git a/spice/copy/sub/LTC1871-1.sub b/spice/copy/sub/LTC1871-1.sub new file mode 100755 index 0000000..faddd88 Binary files /dev/null and b/spice/copy/sub/LTC1871-1.sub differ diff --git a/spice/copy/sub/LTC1871-7.sub b/spice/copy/sub/LTC1871-7.sub new file mode 100755 index 0000000..2f8b6f6 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b/spice/copy/sub/LTC1875.sub new file mode 100755 index 0000000..60158b6 Binary files /dev/null and b/spice/copy/sub/LTC1875.sub differ diff --git a/spice/copy/sub/LTC1877.sub b/spice/copy/sub/LTC1877.sub new file mode 100755 index 0000000..6ac5e42 Binary files /dev/null and b/spice/copy/sub/LTC1877.sub differ diff --git a/spice/copy/sub/LTC1878.sub b/spice/copy/sub/LTC1878.sub new file mode 100755 index 0000000..62e8384 Binary files /dev/null and b/spice/copy/sub/LTC1878.sub differ diff --git a/spice/copy/sub/LTC1879.sub b/spice/copy/sub/LTC1879.sub new file mode 100755 index 0000000..7dc1523 Binary files /dev/null and b/spice/copy/sub/LTC1879.sub differ diff --git a/spice/copy/sub/LTC1911-1.5.sub b/spice/copy/sub/LTC1911-1.5.sub new file mode 100755 index 0000000..a97550c Binary files /dev/null and b/spice/copy/sub/LTC1911-1.5.sub differ diff --git a/spice/copy/sub/LTC1911-1.8.sub b/spice/copy/sub/LTC1911-1.8.sub new file mode 100755 index 0000000..257dc12 Binary files /dev/null and b/spice/copy/sub/LTC1911-1.8.sub differ diff --git a/spice/copy/sub/LTC1922-1.sub b/spice/copy/sub/LTC1922-1.sub new file mode 100755 index 0000000..a072f94 Binary files /dev/null and b/spice/copy/sub/LTC1922-1.sub differ diff --git a/spice/copy/sub/LTC1928-5.sub b/spice/copy/sub/LTC1928-5.sub new file mode 100755 index 0000000..06b3b8b Binary files /dev/null and b/spice/copy/sub/LTC1928-5.sub differ diff --git a/spice/copy/sub/LTC1929-PG.sub b/spice/copy/sub/LTC1929-PG.sub new file mode 100755 index 0000000..9ab3aaa Binary files /dev/null and b/spice/copy/sub/LTC1929-PG.sub differ diff --git a/spice/copy/sub/LTC1929.sub b/spice/copy/sub/LTC1929.sub new file mode 100755 index 0000000..93fa877 Binary files /dev/null and b/spice/copy/sub/LTC1929.sub differ diff --git a/spice/copy/sub/LTC1966.lib b/spice/copy/sub/LTC1966.lib new file mode 100755 index 0000000..9730c92 --- /dev/null +++ b/spice/copy/sub/LTC1966.lib @@ -0,0 +1,123 @@ +* Copyright © Linear Technology Corp. 2016. All rights reserved. +* +.subckt LTC1966 1 2 3 4 5 6 7 +RIN2 11A 13A 300K +DS3 N001 N003 DS +RIN3 N001 11A 50 +CIN2 11A 0 10p Rpar=1k +DIN1 2 7 DIN +DIN2 4 2 DIN +DIN3 4 3 DIN +DIN4 3 7 DIN +RS1 22A 2 6K +RS2 33A 3 6K +RS3 22A 33A 100Meg +CS3 33A 1 2.5p +CS2 22A 1 2.5p +B1 0 11A I=1m*ABS(V(10A)/MAX(V(5,6)+4E-4,4E-4)*MIN(MAX(V(5,6)*4.183,1m),ABS(V(10A)))) +DS1 13A 0 DS +BVCC N003 0 V=.56*V(7,1)-.750 +B2 0 N008 I=10u*dnlim(uplim(V(22A),V(7)+.1,.1), V(4)-.1, .1) +B3 N008 0 I=10u*dnlim(uplim(V(33A),V(7)+.1,.1), V(4)-.1, .1) +C1 N008 0 1f Rpar=200K noiseless +G1 0 10A N008 0 1m +C2 10A 0 160p Rpar=1k +D2 7 1 DSUP1 +D3 1 4 DSUP3 +D4 N008 0 DDIFLIM +B4 7 5 I=11.765u*(ABS(V(11A))+V(6,1)) +G2 1 VDDMIN 1 4 .333m +R1 VDDMIN 1 1k +I1 1 VDDMIN 2.7m +S2 N008 0 VDDMIN 7 SVDDOFF +S3 N008 0 4 1 SVSSOFF +G3 5 1 5 6 1m vto=1.05 dir=1 +COUT2 1 5 8.7p Rpar=85k +S1 N008 0 4 6 SVSSOFF +S5 0 11A 6 7 SREFLIM +G4 5 1 5 7 100m vto=-10m dir=1 +.model DDIFLIM D(Ron=100 Roff=200k vfwd=2 epsilon=300m vrev=2 revepsilon=300m) +.model SREFLIM SW(Ron=1 Roff=1G vt=-900m vh=-300m) +.model SVDDOFF SW(Ron=1 Roff=1G vt=0 vh=-100m) +.model SVSSOFF SW(Ron=1 Roff=1G vt=100m vh=-100m) +.model DSUP1 D(ron=100 roff=1Meg vfwd=1.5 epsilon=500m ilimit=155u) +.model DSUP3 D(ron=100 roff=1G vfwd=100m epsilon=100m ilimit=12u) +.model DS D (IS=1E-16 RS=0 KF=0 XTI=0) +.model DIN D (IS=1E-13 RS=0 KF=0 XTI=0) +.ends LTC1966 +* +.subckt LTC1967 1 2 3 4 5 6 +RIN2 11A 13A 150K +DS3 N001 N003 DS +RIN3 N001 11A 50 +CIN2 11A 0 10p Rpar=1k +DIN1 2 6 DIN +DIN2 1 2 DIN +DIN3 1 3 DIN +DIN4 3 6 DIN +RS1 22A 2 2K +RS2 33A 3 2K +RS3 22A 33A 100Meg +CS3 33A 1 800f +CS2 22A 1 800f +B1 0 11A I=1m*ABS(V(10A)/MAX(V(4,5)+2m,2m)*MIN(MAX(V(4,5)*4.183,1m),ABS(V(10A)))) +DS1 13A 0 DS +BVCC N003 0 V=.5*V(6,1)-.750 +B2 0 N008 I=10u*dnlim(uplim(V(22A),V(6)+.1,.1), V(1)-.1, .1) +B3 N008 0 I=10u*dnlim(uplim(V(33A),V(6)+.1,.1), V(1)-.1, .1) +C1 N008 0 1f Rpar=200K noiseless +G1 0 10A N008 0 1m +C2 10A 0 400f Rpar=1k +D2 6 1 DSUP1 +D4 N008 0 DDIFLIM +B4 6 4 I=20u*(ABS(V(11A))+2m+V(5,1)) +S2 N008 0 1 6 SVDDOFF +G3 4 1 4 5 1m vto=1.05 dir=1 +COUT2 1 4 8.7p Rpar=50K +S1 N008 0 1 6 SVSSOFF +G4 4 1 4 6 100m vto=-10m dir=1 +.model DDIFLIM D(Ron=100 Roff=200k vfwd=2 epsilon=300m vrev=2 revepsilon=300m) +.model SVDDOFF SW(Ron=1 Roff=1G vt=-4.3 vh=-100m) +.model SVSSOFF SW(Ron=1 Roff=1G vt=100m vh=-100m) +.model DSUP1 D(ron=100 roff=1Meg vfwd=1.5 epsilon=500m ilimit=330u) +.model DS D (IS=1E-16 RS=0 KF=0 XTI=0) +.model DIN D (IS=1E-13 RS=0 KF=0 XTI=0) +.ends LTC1967 +* +.subckt LTC1968 1 2 3 4 5 6 +RIN2 11A 13A 150K +DS3 N001 N003 DS +RIN3 N001 11A 50 +CIN2 11A 0 10p Rpar=1k +DIN1 2 6 DIN +DIN2 1 2 DIN +DIN3 1 3 DIN +DIN4 3 6 DIN +RS1 22A 2 2K +RS2 33A 3 2K +RS3 22A 33A 100Meg +CS3 33A 1 800f +CS2 22A 1 800f +B1 0 11A I=1m*ABS(V(10A)/MAX(V(4,5)+2m,2m)*MIN(MAX(V(4,5)*4.183,1m),ABS(V(10A)))) +DS1 13A 0 DS +BVCC N003 0 V=.5*V(6,1)-.750 +B2 0 N008 I=10u*dnlim(uplim(V(22A),V(6)+.1,.1), V(1)-.1, .1) +B3 N008 0 I=10u*dnlim(uplim(V(33A),V(6)+.1,.1), V(1)-.1, .1) +C1 N008 0 1f Rpar=200K noiseless +G1 0 10A N008 0 1m +C2 10A 0 15p Rpar=1k +D2 6 1 DSUP1 +D4 N008 0 DDIFLIM +B4 6 4 I=80u*(ABS(V(11A))+2m+V(5,1)) +S2 N008 0 1 6 SVDDOFF +G3 4 1 4 5 1m vto=1.05 dir=1 +COUT2 1 4 8.7p Rpar=12.5K +S1 N008 0 1 6 SVSSOFF +G4 4 1 4 6 100m vto=-10m dir=1 +.model DDIFLIM D(Ron=100 Roff=200k vfwd=2 epsilon=300m vrev=2 revepsilon=300m) +.model SVDDOFF SW(Ron=1 Roff=1G vt=-4.3 vh=-100m) +.model SVSSOFF SW(Ron=1 Roff=1G vt=100m vh=-100m) +.model DSUP1 D(ron=100 roff=1Meg vfwd=1.5 epsilon=500m ilimit=2.3m) +.model DS D (IS=1E-16 RS=0 KF=0 XTI=0) +.model DIN D (IS=1E-13 RS=0 KF=0 XTI=0) +.ends LTC1968 diff --git a/spice/copy/sub/LTC1981.sub b/spice/copy/sub/LTC1981.sub new file mode 100755 index 0000000..cf514ca Binary files /dev/null and b/spice/copy/sub/LTC1981.sub differ diff --git a/spice/copy/sub/LTC1982.sub b/spice/copy/sub/LTC1982.sub new file mode 100755 index 0000000..5468ff2 Binary files /dev/null and b/spice/copy/sub/LTC1982.sub differ diff --git a/spice/copy/sub/LTC1983-3.sub b/spice/copy/sub/LTC1983-3.sub new file mode 100755 index 0000000..e26b0e7 Binary files /dev/null and b/spice/copy/sub/LTC1983-3.sub differ diff --git a/spice/copy/sub/LTC1983-5.sub b/spice/copy/sub/LTC1983-5.sub new file mode 100755 index 0000000..86eecc8 Binary files /dev/null and b/spice/copy/sub/LTC1983-5.sub differ diff --git a/spice/copy/sub/LTC1986.sub b/spice/copy/sub/LTC1986.sub new file mode 100755 index 0000000..2cf7547 Binary files /dev/null and b/spice/copy/sub/LTC1986.sub differ diff --git a/spice/copy/sub/LTC1998.sub b/spice/copy/sub/LTC1998.sub new file mode 100755 index 0000000..11becc4 Binary files /dev/null and b/spice/copy/sub/LTC1998.sub differ diff --git a/spice/copy/sub/LTC2.lib b/spice/copy/sub/LTC2.lib new file mode 100755 index 0000000..746b802 --- /dev/null +++ b/spice/copy/sub/LTC2.lib @@ -0,0 +1,2356 @@ +* Copyright © 2004-2015 Linear Technology Corporation. +* All rights reserved. +* +.subckt LT1457 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.5f ink=1 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(4)-.6,.1), V(5)+3.4, .1)+1n*V(1) +B2 N005 0 I=10u*dnlim(uplim(V(2),V(4)-.59,.1), V(5)+3.39, .1)+1n*V(2) +C6 4 1 2p Rpar=2T noiseless +C7 1 5 2p noiseless Rpar=2T +C8 2 5 2p Rpar=2T noiseless +C9 4 2 2p Rpar=2T noiseless +A2 0 N005 0 0 0 0 XP 0 OTA g=7.12m asym isource=2.65m isink=-4.6m cout=660p en=12.8n enk=31 Vhigh=1e308 Vlow=-1e308 +C10 N005 0 1f Rpar=100K noiseless +M1 4 N004 3 3 N temp=27 +M2 5 N004 3 3 P temp=27 +C1 N004 0 12f Rpar=1Meg noiseless +C3 4 3 0.5p +C4 3 5 0.5p +D5 N004 3 YU +D6 3 N004 YD +G1 0 N004 XP 0 1µ +C2 3 N004 20f Rser=10k noiseless +R3 4 XP 100Meg noiseless +R4 XP 5 100Meg noiseless +G2 XP 0 XP 4 500m dir=1 vto=-1.8 +G3 0 XP 5 XP 500m dir=1 vto=-1.8 +D1 4 5 DP +.model X D(Ron=1K Roff=100G Vfwd=-2.06 epsilon=1.0 noiseless) +.model YU D(Ron=500 Roff=1T Vfwd=1.30 epsilon=0.1 noiseless) +.model YD D(Ron=500 Roff=1T Vfwd = 1.2 epsilon=0.1 noiseless) +.model DP D(Ron=100 Roff=1g Vfwd=2 epsilon=.2 ilimit=.2m noiseless) +.model N VDMOS(Vto=-400m Kp=20m) +.model P VDMOS(Vto=400m Kp=20m pchan) +.ends LT1457 +* +.subckt LTC1477 1 2 3 4 5 6 7 +C4 1 5 500f +M1 2D N004 1 1 N1 M=2 +M2 7 N004 1 1 N2 M=.7 +M3 6 N004 1 1 N2 M=.7 +R2 2 2D 25m +C2 6 5 500f +C3 2 5 500f +C5 7 5 500f +C6 3 5 500f +C8 N004 5 1p Rpar=800k +D2 N003 N004 DILIM +S4 N004 5 N008 5 SOFF +S5 1 N004 N010 N011 SCL +A1 2D 2 0 0 0 0 N010 0 OTA g=390u linear Rout=100k Cout=10f vlow=1e-308 vhigh=1e308 +C7 N011 0 10f Rpar=100k +G1 5 N002 N005 0 1 +R1 N005 0 1G +G2 5 N003 0 N005 .22 +G3 0 N005 5 N003 .22 +C1 N002 5 10p Rpar=10Meg +G4 0 N005 N002 5 1 +S1 N002 3 N006 N003 SCPREG +C9 3 5 1p +G6 5 N006 3 N009 table(-1 -50n 0 0 900m 0 1.5 50n 2 70n 2.2 75n 3 90n 4.5 120n) +C10 N006 5 1f Rpar=100Meg +M4 N007 N004 1 1 NCGD +R6 N004 N003 1Meg +R7 2D 1 100Meg +R10 1 5 100Meg +D3 N011 0 DLIM +R3 7 2D 500Meg +R4 6 2D 500Meg +D4 5 1 DESD +G8 3 5 3 N009 table(0 0 1 0 2 5u 3.3 19.2u 5 43.1u 6 55u) +G7 0 N011 1 3 80µ vto=-.9 dir=1 +R8 2 N007 20 +A5 4 5 5 5 5 N009 5 5 SCHMITT vt=1.35 vh=50m trise=1u tfall=400u Vlow=0 Vhigh=10 +D1 5 4 DESD +C12 4 5 500f +A6 3 5 5 5 5 5 N012 5 SCHMITT vt=1.8 vh=0 trise=1u vlow=0 vhigh=10 +A7 N009 5 5 N012 5 5 N008 5 AND trise=1u Ref=5 Vlow=0 Vhigh=10 +.model SCPREG SW(level=2 Ron=100 Roff=100Meg vt=0 vh=-50m) +.model SCL SW(level=2 Ron=1 Roff=1G vt=813m vh=-100m) +.model DLIM D(Ron=100 Roff=1Meg vfwd=8 epsilon=1) +.model DESD D(Ron=1 Roff=1G vfwd=1 epsilon=500m) +.model N1 VDMOS(vto=3 kp=1 mtriode=1.5 Cgs=20n Rs=15m Cjo=100p Is=0) +.model N2 VDMOS(vto=2.62 kp=1 mtriode=1.5 Cgs=20n Rs=32m Rd=50m Cjo=100p Is=0) +.model NCGD VDMOS(vto=3 kp=1u Cgdmax=40n Cgdmin=10n Is=0) +.model DILIM D(Ron=10k Roff=10k vfwd=1 epsilon=100m ilimit=400u) +.model SOFF SW(level=2 Ron=80 Roff=100Meg vt=2 vh=1) +.ends LTC1477 +* +.subckt LT1672 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=8f ink=54.7 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)+37,.1), V(5)-.1, .1)+1n*V(1)-663p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)+37.01,.1), V(5)-.11, .1)+1n*V(2) +C9 4 2 2.3p Rser=2k noiseless +C10 N004 0 200p Rpar=100K noiseless +D4 4 N011 DBIA3 +M1 3 N012 N014 N014 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +D1 4 N005 DVLIMU +D5 N012 5 DLIMN1 +M2 3 N006 N005 N005 PI temp=27 +D8 4 N006 DLIMP1 +C3 4 N006 100p Rser=600k noiseless +A3 N009 N010 5 5 5 5 N006 5 OTA g=800n ref=-.021 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=1g noiseless +C12 N012 5 50f Rser=20k noiseless +C4 4 N005 1p Rpar=1g noiseless +D2 4 2 DBIA2 +D3 4 1 DBIA2 +D10 1 N011 DBIA1 +D11 2 N011 DBIA1 +D6 N012 5 DLIMN2 +A4 0 N004 0 0 0 0 N007 0 OTA g=1u linear en=232n/freq**.05 Vhigh=1e308 Vlow=-1e308 +C16 N010 3 6.6p +A5 N008 0 N009 N009 N009 N009 N010 N009 OTA g=500n iout=33.5n Vhigh=1e308 Vlow=-1e308 +D12 1 4 DBIAOT +D13 2 4 DBIAOT +G1 5 N012 N010 N009 50n +C5 N011 5 20p Rpar=50Meg noiseless +D9 N010 N009 DLIM +C6 2 5 2.3p Rser=2k noiseless +C7 4 1 2.3p Rser=2k noiseless +C8 1 5 2.3p Rser=2k noiseless +C13 4 5 1000p +C15 N006 N012 100f Rser=500k noiseless +D7 4 5 DP +C17 0 N007 8p Rpar=1Meg noiseless +C19 0 N008 8p Rpar=1Meg noiseless +G4 0 N008 N007 0 1µ +D14 N014 5 DVLIMD +C1 N014 5 1p Rpar=1g noiseless +D15 4 N006 DLIMP2 +S1 N010 N009 N009 4 SHUT +S2 4 N006 5 4 SHUT +S3 N012 5 5 4 SHUT +C14 N006 3 5p Rser=1Meg noiseless +G2 0 N009 5 0 .5m +G3 0 N009 4 0 .5m +C18 N009 0 150p Rpar=1K +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=.81u noiseless) +.model DBIA1 D(Ron=100k Roff=100T Vfwd=.1 ilimit=1.6p epsilon=.1 noiseless) +.model DBIA2 D(Ron=100k Roff=10T Vfwd=0 ilimit=.2p epsilon=1m noiseless) +.model DBIA3 D(Ron=10Meg Roff=100G Vfwd=.7 epsilon=.1 noiseless) +.model DBIAOT D(Ron=50k Roff=100T Vfwd=0 ilimit=170p epsilon=50m noiseless) +.model DVLIMU D(Ron=10 Roff=1Meg Vfwd=34m epsilon=2m noiseless) +.model DVLIMD D(Ron=10 Roff=1Meg Vfwd=49m epsilon=2m noiseless) +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.1 noiseless) +.model NI VDMOS(Vto=300m kp=1.5m lambda=.01) +.model DLIMN1 D(Ron=100 Roff=2g Vfwd=1.8 Vrev=-320m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=400Meg Roff=2G Vfwd=-10m epsilon=100m ilimit=900p noiseless) +.model PI VDMOS(Vto=-300m Kp=2m lambda=.01 pchan is=0) +.model DLIMP1 D(Ron=100k Roff=300Meg Vfwd=1.33 Vrev=-320m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=100Meg Roff=2g Vfwd=-10m epsilon=100m ilimit=3.5n noiseless) +.model DLIM D(Ron=100k Roff=500Meg Vfwd=100m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.ends LT1672 +* +.subckt LT1784 1 2 3 4 5 6 +C10 N006 0 10f Rpar=100K noiseless +A4 0 N006 0 0 0 0 N007 0 OTA g=1u linear en=20n enk=8 cout=600f Vlow=-1e308 Vhigh=1e308 +C13 4 5 100p +D7 4 5 DP +G7 0 N008 N007 0 1m +L1 N008 0 402.5µ Cpar=1.32p Rser=1.14k Rpar=8.14k noiseless +D14 N007 0 DLIMIN +M1 3 VN 5 5 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +D1 4 N009 DILIMU +D5 VN 5 DLIMN1 +M2 3 VP N009 N009 PI temp=27 +D6 4 VP DLIMP +A2 0 X6 4 4 4 4 VP 4 OTA g=800n ref=-345m linear vlow=-1e308 vhigh=1e308 +C3 3 5 1p Rpar=1g noiseless +C4 4 N009 1p Rpar=1G noiseless +D8 VN 5 DLIMN2 +C11 X5 N010 1.75p +A3 N008 0 0 0 0 0 X5 0 OTA g=28u iout=4.5u Vhigh=1e308 Vlow=-1e308 +D9 X5 0 DLIM +S1 X5 0 0 N004 SHUT +S2 4 VP 0 N004 SHUT +S3 VN 5 0 N004 SHUT +R4 4 N013 8Meg noiseless +R5 N013 5 8Meg noiseless +G1 0 N010 3 N013 10m +C12 N010 0 10f Rpar=100 noiseless +C14 VP 3 .1f +C15 3 VN .1f +A5 0 X6 5 5 5 5 VN 5 OTA g=30n ref=345m linear vlow=-1e308 vhigh=1e308 +G2 0 X6 4 N009 1m vto=90m dir=1 +G4 0 X6 X5 0 1µ +R6 X6 0 1Meg noiseless +R7 X7 X6 28K noiseless +B3 X7 0 I=15p*ddt(V(X7))*(.5+.5*tanh((-400m-V(VP,4))/5m)) +S5 4 5 N004 0 SP2 +S6 4 5 N004 0 SP1 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=300f ink=20.8 +C1 4 2 2.5p Rser=1k Rpar=300Meg noiseless +D2 4 N011 DBIA3 +D3 N005 2 DBIA2 +D4 N005 1 DBIA2 +D10 1 N011 DBIA1 +D11 2 N011 DBIA1 +D12 1 N005 DBIAOT1 +D13 2 N005 DBIAOT1 +C5 N011 5 20p +C6 2 5 2.5p Rser=1k noiseless +C7 4 1 2.5p Rser=1k Rpar=300Meg noiseless +C8 1 5 2.5p Rser=1k noiseless +G3 0 N004 4 5 50n +S4 N004 0 6 5 SHUTI +C9 N004 0 4.5p +C16 5 6 100f Rpar=10Meg noiseless +D15 5 1 DPROT +D16 5 2 DPROT +D17 1 N005 DBIAOT2 +D18 2 N005 DBIAOT2 +S7 N011 5 N004 0 SWBIAS +S8 4 N005 N004 0 SWBIAS2 +C17 4 N005 500f +S9 2 1 N004 0 SIN +D19 6 5 DSHUT +B1 N006 0 I=10u*dnlim(uplim(V(2),V(5)+18.11,.1), V(5)-.11, .1)+1n*V(2) +B2 0 N006 I=10u*dnlim(uplim(V(1),V(5)+18.1,.1), V(5)-.1, .1)+1n*V(1)-1.732n +.model DLIMIN D(Ron=1k Roff=1Meg vfwd=200m epsilon=20m vrev=200m revepsilon=20m noiseless) +.model DPROT D(Ron=1k Roff=2G Vfwd=1 epsilon=10m noiseless) +.model SIN SW(ron=200k Roff=1G vt=.5 vh=-100m noiseless) +.model DSHUT D(Ron=1.11Meg Roff=10Meg vfwd=20m epsilon=20m ilimit=9.9u) +.model SP1 SW(Roff=100Meg Ron=1k vt=.5 vh=-200m ilimit=362.1u noiseless) +.model SP2 SW(Roff=100Meg Ron=190k vt=.5 vh=-200m ilimit=65u noiseless) +.model DP D(Roff=100Meg Ron=1k vfwd=600m epsilon=500m ilimit=5.3u noiseless) +.model DILIMU D(Ron=2 Roff=100k Vfwd=59m epsilon=2m noiseless) +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.9 noiseless) +.model SHUTI SW(Ron=100 Roff=20Meg vt=1.2 vh=-10m noiseless) +.model NI VDMOS(Vto=300m kp=15m lambda=.01 noiseless) +.model PI VDMOS(Vto=-300m Kp=15m lambda=.01 pchan is=0 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=3.6 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.model DLIM D(Ron=10k Roff=70Meg Vfwd=2 Vrev=100m epsilon=10m revepsilon=10m noiseless) +.model DLIMN1 D(Ron=200k Roff=700Meg Vfwd=2.2 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=15Meg Roff=1G Vfwd=-10m epsilon=50m ilimit=25.7n noiseless) +.model DBIA1 D(Ron=1k Roff=100G Vfwd=.1 ilimit=715n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1k Roff=100G Vfwd=0 ilimit=300n epsilon=10m noiseless) +.model DBIA3 D(Ron=1k Roff=10G Vfwd=1.1 epsilon=.1 noiseless) +.model SWBIAS SW(Ron=500k Roff=1G vt=.5 vh=-200m noiseless) +.model SWBIAS2 SW(Ron=5k Roff=1G vt=.5 vh=-200m noiseless) +.model DBIAOT1 D(Ron=2k Vfwd=0 ilimit=150u epsilon=10m noiseless) +.model DBIAOT2 D(Ron=208k Vfwd=0 ilimit=200u epsilon=50m noiseless) +.ends LT1784 +* +.subckt LT1803 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2.49p ink=88.2 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1)-240p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C10 N004 0 3f Rpar=100K noiseless +D4 4 N011 DBIA3 +M1 3 N012 5 5 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +D5 N012 5 DLIMN1 +M2 3 N008 4 4 PI temp=27 +D8 4 N008 DLIMP1 +C3 4 N008 .08f Rser=20Meg noiseless +A3 N009 N007 5 5 5 5 N008 5 OTA g=80n ref=-.015 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=1g noiseless +C12 N012 5 .02f Rser=1Meg noiseless +D10 1 N011 DBIA1 +D11 2 N011 DBIA1 +D6 N012 5 DLIMN2 +A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear en=20.5n enk=512 Vhigh=.21 Vlow=-.21 +C16 N007 3 6p +D12 1 4 DESD +D13 2 4 DESD +G1 5 N012 N007 N009 20n +C5 N011 5 20p Rpar=100k noiseless +C7 4 1 1p Rpar=10g noiseless +C13 4 5 1000p +C15 N008 N012 .1f Rser=10Meg noiseless +D7 4 5 DP +C17 0 N005 37f Rpar=1Meg noiseless +G4 0 N006 N005 0 1m +D14 4 N008 DLIMP2 +L1 N006 0 13.1µ Cpar=108f Rser=1.24k Rpar=5.17k noiseless +D15 1 2 DIN +D16 N011 1 DBIA2 +D3 N011 2 DBIA2 +C4 N008 3 .01f +D1 5 2 DESD +D2 5 2 DESD +C1 4 2 1p Rpar=10g noiseless +C6 1 5 1p Rpar=10g noiseless +C8 2 5 1p Rpar=10g noiseless +C14 N009 N007 10f Rpar=80k noiseless +G3 N009 N007 0 N006 3m +G2 0 N009 5 0 50m +G5 0 N009 4 0 50m +C18 N009 0 100p Rpar=10 +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=1.7m noiseless) +.model DBIA1 D(Ron=1k Roff=10G Vfwd=0 ilimit=2.5u epsilon=.2 noiseless) +.model DBIA2 D(Ron=1k Roff=10T Vfwd=-.1 epsilon=.2 ilimit=125n noiseless) +.model DBIA3 D(Ron=100 Roff=100G Vfwd=1.1 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model DVLIMU D(Ron=10 Roff=1Meg Vfwd=45m epsilon=2m noiseless) +.model NI VDMOS(Vto=300m kp=150m lambda=.01) +.model DLIMN1 D(Ron=100 Roff=10g Vfwd=1.07 Vrev=-340m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=100Meg Roff=10g Vfwd=320m epsilon=700m noiseless) +.model PI VDMOS(Vto=-300m kp=150m lambda=.01 pchan is=0) +.model DLIMP1 D(Ron=100 Roff=1G Vfwd=.94 Vrev=-340m epsilon=600m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=40Meg Roff=2g Vfwd=320m epsilon=500m noiseless) +.model DIN D(Ron=2k Roff=100g Vfwd=1.5 Vrev=1.5 epsilon=100m revepsilon=100m noiseless) +.ends LT1803 +* +.subckt LT1815 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.28p ink=288 +C2 2 1 .1p Rpar=750k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.7,.1), V(5)+.7, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.69,.1), V(5)+.69, .1)+1n*V(2) +C9 4 2 1p Rpar=10Meg noiseless +C10 N004 0 1f Rpar=100K noiseless +M1 4 N005 3 3 N temp=27 +M2 5 N005 3 3 P temp=27 +C3 4 3 1p +D5 N005 3 YU +D6 3 N005 YD +R2 4 N007 80Meg noiseless +R3 N007 5 80Meg noiseless +C4 3 5 1p +C1 2 5 1p Rpar=10G noiseless +C6 4 1 1p Rpar=10Meg noiseless +C7 1 5 1p Rpar=10G noiseless +A6 0 N004 0 0 0 0 N006 0 OTA g=10m linear Cout=1p en=5.96n enk=126 Vhigh=1e308 rout=1k Vlow=-1e308 +D2 4 1 DBIAS +D4 4 2 DBIAS +G1 0 N005 N007 0 100µ +C8 0 N005 2f Rpar=10k noiseless +D3 4 5 DC +D7 N006 N009 DNL +C12 N009 0 6.5p Rpar=10k +G2 0 N007 N006 0 7.8µ +C14 N007 0 49.7f +R1 4 5 25k noiseless +G3 N007 0 N007 4 100m dir=1 vto=-.89 +G4 0 N007 5 N007 100m dir=1 vto=-.89 +.model YU D(Ron=10 Roff=1T Vfwd=.68 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.61 epsilon=.1 noiseless) +.model N VDMOS(Vto=-100m Kp=390m) +.model P VDMOS(Vto=100m Kp=300m pchan) +.model DBIAS D(Ron=100k Roff=1T Vfwd=.6 ilimit=2u noiseless) +.model DC D(Ron=100 Roff=1G Vfwd=1 epsilon=.1 ilimit=4.393m noiseless) +.model DNL D(Ron=100 Roff=10k Vfwd=4.2 Vrev=4.2 epsilon=.5 revepsilon=.5 noiseless) +.ends LT1815 +* +.subckt LT1818 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1.19p ink=189 +C2 2 1 1f Rpar=750k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.7,.1), V(5)+.7, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.69,.1), V(5)+.69, .1)+1n*V(2) +C9 4 2 .75p Rpar=10Meg noiseless +C10 N004 0 1f Rpar=100K noiseless +M1 4 N006 3 3 N temp=27 +M2 5 N006 3 3 P temp=27 +C3 4 3 .1p +D5 N006 3 YU +D6 3 N006 YD +R2 4 N007 100Meg noiseless +R3 N007 5 100Meg noiseless +C4 3 5 .1p +C1 2 5 .75p Rpar=10G noiseless +C6 4 1 .75p Rpar=10Meg noiseless +C7 1 5 .75p Rpar=10G noiseless +D2 4 1 DBIAS +D4 4 2 DBIAS +D3 4 5 DC +G2 0 N007 N008 0 5µ +C14 N007 0 20f +R1 4 5 10k noiseless +A2 0 N004 0 0 0 0 N008 0 OTA g=10m linear Cout=428f en=5.96n enk=126 Vhigh=100 rout=1k Vlow=-100 +D7 N006 N005 DLS +G1 0 N005 N007 0 10µ +C12 N005 0 10f Rpar=100K noiseless +D1 N008 0 DNL +C11 N006 0 1.7f Rser=705k Rpar=1Meg noiseless +G5 0 N006 N007 0 1µ +G3 N007 0 N007 4 100m dir=1 vto=-.89 +G4 0 N007 5 N007 100m dir=1 vto=-.89 +.model YU D(Ron=10 Roff=1T Vfwd=.68 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.68 epsilon=.1 noiseless) +.model N VDMOS(Vto=-100m Kp=390m) +.model P VDMOS(Vto=100m Kp=300m pchan) +.model DBIAS D(Ron=100k Roff=1T Vfwd=.6 ilimit=1.5u noiseless) +.model DC D(Ron=100 Roff=1G Vfwd=1 epsilon=.1 ilimit=6.294m noiseless) +.model DNL D(Ron=650 Roff=10k Vfwd=2.8 Vrev=2.8 epsilon=.5 revepsilon=.5 noiseless) +.model DLS D(Ron=10k Roff=1T Vfwd=200m Vrev=200m epsilon=20m revepsilon=20m noiseless) +.ends LT1818 +* +.subckt LT6010 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=100f ink=24.6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-1.1,.1), V(5)+.9, .1)+1n*V(1)-89p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-1.09,.1), V(5)+.89, .1)+1n*V(2) +C10 N004 0 50f Rpar=100K noiseless +M1 3 N011 5 5 NI temp=27 +C2 4 3 1p Rpar=860k noiseless +D5 N011 5 DLIMN +M2 3 N007 4 4 PI temp=27 +D8 4 N007 DLIMP +C3 4 N007 500f Rser=1.5Meg noiseless +A3 N008 N009 5 5 5 5 N007 5 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=860k noiseless +C12 N011 5 10f Rser=250k noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=1u linear en=14n enk=4.2 Vhigh=1e308 Vlow=-1e308 +C16 N009 3 12p +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=30u iout=1.335u Vhigh=1e308 Vlow=-1e308 +G1 5 N011 N009 N008 200n +D9 N009 N008 DLIM +C14 N007 3 4f +C7 4 1 2p Rser=2k Rpar=240G noiseless +C13 4 5 1000p +C15 N007 N011 50f Rser=1Meg noiseless +S1 N009 N008 0 N005 SHUT2 +C1 N006 0 260f Rpar=1Meg noiseless +C17 5 6 500f Rpar=1Meg noiseless +G2 0 N008 5 0 .5m +G4 0 N008 4 0 .5m +C18 N008 0 200p Rpar=1K noiseless +D1 2 1 DIN +D3 6 5 DSHUT +S4 N007 4 0 N005 SHUT1 +S2 5 N011 0 N005 SHUT1 +A6 6 5 0 0 0 N005 0 0 SCHMITT Vt=.189 Vh=10m trise=1u tfall=30u +C4 4 2 2p Rser=2k Rpar=240G noiseless +C5 1 5 2p Rser=2k Rpar=240G noiseless +C6 2 5 2p Rser=2k Rpar=240G noiseless +S3 5 2 N005 0 SBIAS +S5 5 1 N005 0 SBIAS +S6 4 5 N005 0 SPOW2 +S7 4 5 N005 0 SPOW1 +.model DSHUT D(Ron=85k Roff=1Meg Vfwd=.6 epsilon=100m noiseless) +.model DIN D(Ron=1k Roff=20Meg Vfwd=1.5 epsilon=.1 Vrev=1.5 revepsilon=.1 noiseless) +.model SBIAS SW(level=2 Ron=50Meg Roff=100G vt=.5 vh=-.1 ilimit 18p noiseless ) +.model SPOW1 SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=37u noiseless) +.model SPOW2 SW(Ron=255k Roff=1G vt=.5 vh=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=305m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SHUTI SW(level=2 Ron=100k Roff=20Meg vt=.2 vh=-50m noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=200m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.model DSLIM D(Ron=100 Roff=1G Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.3 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.25 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.ends LT6010 +* +.subckt LT6011 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=100f ink=24.6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-1.1,.1), V(5)+.9, .1)+1n*V(1)-89p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-1.09,.1), V(5)+.89, .1)+1n*V(2) +C10 N004 0 50f Rpar=100K noiseless +M1 3 N010 5 5 NI temp=27 +C2 4 3 1p Rpar=860k noiseless +D5 N010 5 DLIMN +M2 3 N006 4 4 PI temp=27 +D8 4 N006 DLIMP +C3 4 N006 500f Rser=1.5Meg noiseless +A3 N007 N008 5 5 5 5 N006 5 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=860k noiseless +C12 N010 5 10f Rser=250k noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear en=14n enk=4.2 Vhigh=1e308 Vlow=-1e308 +C16 N008 3 12p +A5 N005 0 N007 N007 N007 N007 N008 N007 OTA g=30u iout=1.335u Vhigh=1e308 Vlow=-1e308 +G1 5 N010 N008 N007 200n +D9 N008 N007 DLIM +C14 N006 3 4f +C7 4 1 2p Rser=2k Rpar=240G noiseless +C13 4 5 1000p Rpar=255k noiseless +C15 N006 N010 50f Rser=1Meg noiseless +C1 N005 0 260f Rpar=1Meg noiseless +G2 0 N007 5 0 .5m +G4 0 N007 4 0 .5m +C18 N007 0 200p Rpar=1K noiseless +D1 2 1 DIN +C4 4 2 2p Rser=2k Rpar=240G noiseless +C5 1 5 2p Rser=2k Rpar=240G noiseless +C6 2 5 2p Rser=2k Rpar=240G noiseless +D2 4 5 DPOW +D3 2 5 DBIAS +D4 1 5 DBIAS +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=200m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.3 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.25 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DIN D(Ron=1k Roff=20Meg Vfwd=1.5 epsilon=.1 Vrev=1.5 revepsilon=.1 noiseless) +.model DBIAS D(Ron=10G Roff=100G Vfwd=.3 epsilon=.1 ilimit=18p noiseless) +.model DPOW D(Ron=1k Vfwd=.5 epsilon=.1 ilimit=37u noiseless) +.ends LT6011 +* +.subckt LT6200 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2.16p ink=351 incm=2.7p incmk=351 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1)-3.21n +B2 N005 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C10 N005 0 .1f Rpar=100K noiseless +M1 3 N013 5 5 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +M2 3 N006 4 4 PI temp=27 +C3 4 N006 .1f Rser=25Meg noiseless +C11 3 5 1p Rpar=1g noiseless +C12 N013 5 .1f Rser=25Meg noiseless +D6 N013 5 DLIMN +A4 0 N005 0 0 0 0 N007 0 OTA g=1u linear en=1.08n enk=2.7k Vhigh=1e308 Vlow=-1e308 +C16 N011 3 63f +D12 1 4 DESD +D13 2 4 DESD +G1 5 N013 N011 N009 10n +C7 4 1 1.55p Rpar=11Meg noiseless +C17 0 N007 8f Rpar=1Meg noiseless +G4 0 N008 N007 0 1m +D14 4 N006 DLIMP +L1 N008 0 5.73µ Cpar=7.46f Rser=1.08k Rpar=13.5k noiseless +D15 1 2 DIN +D16 N014 1 DBIA2 +D3 N014 2 DBIA2 +D1 5 2 DESD +D2 5 2 DESD +C1 4 2 1.55p Rpar=11Meg noiseless +C6 1 5 1.55p Rpar=11Meg noiseless +C8 2 5 1.55p Rpar=11Meg noiseless +C4 2 1 1.1p Rpar=2.1k Noiseless +D5 N014 1 DBIA3 +D8 N014 2 DBIA3 +A6 N008 0 N015 N009 N009 N009 N011 N009 OTA g=60u iout=3.15u Rout=800k Vlow=-1e308 Vhigh=1e308 +A2 4 6 N009 N009 N009 N015 N009 N009 SCHMITT Vt=1.5 Vh=10m tau=20n +D9 4 6 DSHUT +A5 N009 N011 N015 N009 N009 N009 N006 N009 OTA g=52.5n ref=-.03 linear Vlow=-1e308 Vhigh=1e308 +D17 2 N004 DBIA1 +D18 1 N004 DBIA1 +S1 5 N014 N009 N015 SWB +S2 N010 5 N015 N009 SWB2 +C5 N014 5 20p Rpar=1Meg noiseless +D4 4 N014 DBIAZ1 +D7 4 N010 DBIAZ2 +C14 4 N010 20p Rpar=100g noiseless +G5 0 N009 5 0 50m +G6 0 N009 4 0 50m +C15 N009 0 100p Rpar=10 +S3 N010 N004 N015 N009 SWB3 +S4 4 5 N015 N009 SWP +C13 4 5 1000p +.model DBIA1 D(Ron=10k Roff=.62Meg Vfwd=0 ilimit=7.6u epsilon=.1 noiseless) +.model DBIA2 D(Ron=10k Roff=1g Vfwd=-.1 epsilon=.2 ilimit=7.6u noiseless) +.model DBIA3 D(Ron=1k Roff=1g Vfwd=2.9 epsilon=.1 ilimit=8.4u noiseless) +.model DBIAZ1 D(Ron=100 Roff=100G Vfwd=.95 epsilon=10m ilimit=1.2m noiseless) +.model DBIAZ2 D(Ron=1 Roff=100G Vfwd=.95 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model NI VDMOS(Vto=300m kp=55m lambda=.01) +.model PI VDMOS(Vto=-300m kp=55m lambda=.01 pchan is=0) +.model DSHUT D(Ron=20k Roff=1g Vfwd=.6 epsilon=100m noiseless) +.model DIN D(Ron=300 Roff=100g Vfwd=.8 Vrev=.8 epsilon=100m revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=2 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DLIMN D(Ron=1Meg Roff=5g Vfwd=2.1 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model SWP SW(Roff=1G Ron=1.3k vt=.5 vh=-.1) +.model SWB SW(Ron=1 Roff=5G vt=-.5 vh=-.1) +.model SWB2 SW(level=2 Ron=10 Roff=500g vt=.5 vh=-.1 ilimit=6.43m) +.model SWB3 SW(Ron=1k Roff=100g vt=.5 vh=-.1) +.ends LT6200 +* +.subckt LT6200-5 1 2 3 4 5 6 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1)-3.21n +B2 N005 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C10 N005 0 .1f Rpar=100K noiseless +M1 3 N013 5 5 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +M2 3 N006 4 4 PI temp=27 +C3 4 N006 .2f Rser=35Meg noiseless +C11 3 5 1p Rpar=1g noiseless +C12 N013 5 .2f Rser=35Meg noiseless +D6 N013 5 DLIMN +A4 0 N005 0 0 0 0 N007 0 OTA g=1u linear en=1.08n enk=2.7k Vhigh=100m Vlow=-100m +C16 N011 3 10f +D12 1 4 DESD +D13 2 4 DESD +G1 5 N013 N011 N009 10n +C7 4 1 1.55p Rpar=11Meg noiseless +C17 0 N007 10f Rpar=1Meg noiseless +G4 0 N008 N007 0 1m +D14 4 N006 DLIMP +L1 N008 0 4.44µ Cpar=11.37f Rser=1.12k Rpar=9.333k noiseless +D15 1 2 DIN +D16 N014 1 DBIA2 +D3 N014 2 DBIA2 +D1 5 2 DESD +D2 5 2 DESD +C1 4 2 1.55p Rpar=11Meg noiseless +C6 1 5 1.55p Rpar=11Meg noiseless +C8 2 5 1.55p Rpar=11Meg noiseless +C4 2 1 1.1p Rpar=2.1k Noiseless +D5 N014 1 DBIA3 +D8 N014 2 DBIA3 +A6 N008 0 N015 N009 N009 N009 N011 N009 OTA g=60u iout=2.61u Rout=800k Vlow=-1e308 Vhigh=1e308 +A2 4 6 N009 N009 N009 N015 N009 N009 SCHMITT Vt=1.5 Vh=10m tau=20n +D9 4 6 DSHUT +A5 N009 N011 N015 N009 N009 N009 N006 N009 OTA g=52.5n ref=-.03 linear Vlow=-1e308 Vhigh=1e308 +D17 2 N004 DBIA1 +D18 1 N004 DBIA1 +S1 5 N014 N009 N015 SWB +S2 N010 5 N015 N009 SWB2 +C5 N014 5 20p Rpar=1Meg noiseless +D4 4 N014 DBIAZ1 +D7 4 N010 DBIAZ2 +C14 4 N010 20p Rpar=100g noiseless +G5 0 N009 5 0 50m +G6 0 N009 4 0 50m +C15 N009 0 100p Rpar=10 +S3 N010 N004 N015 N009 SWB3 +S4 4 5 N015 N009 SWP +C13 4 5 1000p +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2.16p ink=351 incm=2.7p incmk=351 +.model DBIA1 D(Ron=10k Roff=.62Meg Vfwd=0 ilimit=7.6u epsilon=.1 noiseless) +.model DBIA2 D(Ron=10k Roff=1g Vfwd=-.1 epsilon=.2 ilimit=7.6u noiseless) +.model DBIA3 D(Ron=1k Roff=1g Vfwd=2.9 epsilon=.1 ilimit=8.4u noiseless) +.model DBIAZ1 D(Ron=100 Roff=100G Vfwd=.95 epsilon=10m ilimit=1.2m noiseless) +.model DBIAZ2 D(Ron=1 Roff=100G Vfwd=.95 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model NI VDMOS(Vto=300m kp=55m lambda=.01) +.model PI VDMOS(Vto=-300m kp=55m lambda=.01 pchan is=0) +.model DSHUT D(Ron=20k Roff=1g Vfwd=.6 epsilon=100m noiseless) +.model DIN D(Ron=300 Roff=100g Vfwd=.8 Vrev=.8 epsilon=100m revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=2 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DLIMN D(Ron=1Meg Roff=5g Vfwd=2.1 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model SWP SW(Roff=1G Ron=1.3k vt=.5 vh=-.1) +.model SWB SW(Ron=1 Roff=5G vt=-.5 vh=-.1) +.model SWB2 SW(level=2 Ron=10 Roff=500g vt=.5 vh=-.1 ilimit=6.43m) +.model SWB3 SW(Ron=1k Roff=100g vt=.5 vh=-.1) +.ends LT6200-5 +* +.subckt LT6200-10 1 2 3 4 5 6 +B1 0 X0 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1)-3.21n +B2 X0 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C10 X0 0 .1f Rpar=100K noiseless +M1 3 N012 5 5 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +M2 3 N005 4 4 PI temp=27 +C3 4 N005 .2f Rser=35Meg noiseless +C11 3 5 1p Rpar=1g noiseless +C12 N012 5 .2f Rser=35Meg noiseless +D6 N012 5 DLIMN +A4 0 X0 0 0 0 0 N006 0 OTA g=1u linear en=1.08n enk=2.7k Vhigh=60m Vlow=-60m +C16 N010 3 5.8f +D12 1 4 DESD +D13 2 4 DESD +G1 5 N012 N010 N008 10n +C7 4 1 1.55p Rpar=11Meg noiseless +C17 0 N006 8f Rpar=1Meg noiseless +G4 0 N007 N006 0 1m +D14 4 N005 DLIMP +L1 N007 0 4.83µ Cpar=26.5f Rser=1.21k Rpar=5.76k noiseless +D15 1 2 DIN +D16 N013 1 DBIA2 +D3 N013 2 DBIA2 +D1 5 2 DESD +D2 5 2 DESD +C1 4 2 1.55p Rpar=11Meg noiseless +C6 1 5 1.55p Rpar=11Meg noiseless +C8 2 5 1.55p Rpar=11Meg noiseless +C4 2 1 1.1p Rpar=2.1k Noiseless +D5 N013 1 DBIA3 +D8 N013 2 DBIA3 +A6 N007 0 N014 N008 N008 N008 N010 N008 OTA g=60u iout=3.58u Rout=800k Vlow=-1e308 Vhigh=1e308 +A2 4 6 N008 N008 N008 N014 N008 N008 SCHMITT Vt=1.5 Vh=10m tau=20n +D9 4 6 DSHUT +A5 N008 N010 N014 N008 N008 N008 N005 N008 OTA g=52.5n ref=-.03 linear Vlow=-1e308 Vhigh=1e308 +D17 2 N004 DBIA1 +D18 1 N004 DBIA1 +S1 5 N013 N008 N014 SWB +S2 N009 5 N014 N008 SWB2 +C5 N013 5 20p Rpar=1Meg noiseless +D4 4 N013 DBIAZ1 +D7 4 N009 DBIAZ2 +C14 4 N009 20p Rpar=100g noiseless +G5 0 N008 5 0 50m +G6 0 N008 4 0 50m +C15 N008 0 100p Rpar=10 +S3 N009 N004 N014 N008 SWB3 +S4 4 5 N014 N008 SWP +C13 4 5 1000p +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2.16p ink=351 incm=2.7p incmk=351 +.model DBIA1 D(Ron=10k Roff=.62Meg Vfwd=0 ilimit=7.6u epsilon=.1 noiseless) +.model DBIA2 D(Ron=10k Roff=1g Vfwd=-.1 epsilon=.2 ilimit=7.6u noiseless) +.model DBIA3 D(Ron=1k Roff=1g Vfwd=2.9 epsilon=.1 ilimit=8.4u noiseless) +.model DBIAZ1 D(Ron=100 Roff=100G Vfwd=.95 epsilon=10m ilimit=1.2m noiseless) +.model DBIAZ2 D(Ron=1 Roff=100G Vfwd=.95 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model NI VDMOS(Vto=300m kp=55m lambda=.01) +.model PI VDMOS(Vto=-300m kp=55m lambda=.01 pchan is=0) +.model DSHUT D(Ron=20k Roff=1g Vfwd=.6 epsilon=100m noiseless) +.model DIN D(Ron=300 Roff=100g Vfwd=.8 Vrev=.8 epsilon=100m revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=2 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DLIMN D(Ron=1Meg Roff=5g Vfwd=2.1 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model SWP SW(Roff=1G Ron=1.3k vt=.5 vh=-.1) +.model SWB SW(Ron=1 Roff=5G vt=-.5 vh=-.1) +.model SWB2 SW(level=2 Ron=10 Roff=500g vt=.5 vh=-.1 ilimit=6.43m) +.model SWB3 SW(Ron=1k Roff=100g vt=.5 vh=-.1) +.ends LT6200-10 +* +.subckt LT6201 1 2 3 4 5 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1)-3.21n +B2 N005 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C10 N005 0 .1f Rpar=100K noiseless +M1 3 N012 5 5 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +M2 3 N006 4 4 PI temp=27 +C3 4 N006 .1f Rser=25Meg noiseless +C11 3 5 1p Rpar=1g noiseless +C12 N012 5 .1f Rser=25Meg noiseless +D6 N012 5 DLIMN +A4 0 N005 0 0 0 0 N007 0 OTA g=1u linear en=1.08n enk=2.7k Vhigh=1e308 Vlow=-1e308 +C16 N010 3 63f +D12 1 4 DESD +D13 2 4 DESD +G1 5 N012 N010 N009 10n +C7 4 1 1.55p Rpar=11Meg noiseless +C17 0 N007 8f Rpar=1Meg noiseless +G4 0 N008 N007 0 1m +D14 4 N006 DLIMP +L1 N008 0 5.73µ Cpar=7.46f Rser=1.08k Rpar=13.5k noiseless +D15 1 2 DIN +D16 N004 1 DBIA2 +D3 N004 2 DBIA2 +D1 5 2 DESD +D2 5 2 DESD +C1 4 2 1.55p Rpar=11Meg noiseless +C6 1 5 1.55p Rpar=11Meg noiseless +C8 2 5 1.55p Rpar=11Meg noiseless +C4 2 1 1.1p Rpar=2.1k Noiseless +D5 N004 1 DBIA3 +D8 N004 2 DBIA3 +D17 2 N004 DBIA1 +D18 1 N004 DBIA1 +C5 N004 5 20p Rpar=1Meg noiseless +D7 4 N004 DBIAZ2 +C14 4 N004 20p Rpar=100g noiseless +G5 0 N009 5 0 50m +G6 0 N009 4 0 50m +C15 N009 0 100p Rpar=10 +C13 4 5 1000p +R3 4 5 1.3k noiseless +D10 N004 5 DBIAZ3 +A3 N008 0 N009 N009 N009 N009 N010 N009 OTA g=60u iout=3.15u Rout=800k Vlow=-1e308 Vhigh=1e308 +A6 N009 N010 N009 N009 N009 N009 N006 N009 OTA linear g=52.5n ref=-.03 Vlow=-1e308 Vhigh=1e308 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2.16p ink=351 incm=2.7p incmk=351 +.model DBIA1 D(Ron=10k Roff=.62Meg Vfwd=0 ilimit=7.6u epsilon=.1 noiseless) +.model DBIA2 D(Ron=10k Roff=1g Vfwd=-.1 epsilon=.2 ilimit=7.6u noiseless) +.model DBIA3 D(Ron=1k Roff=1g Vfwd=2.9 epsilon=.1 ilimit=8.4u noiseless) +.model DBIAZ2 D(Ron=1 Roff=100G Vfwd=.95 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model NI VDMOS(Vto=300m kp=55m lambda=.01) +.model PI VDMOS(Vto=-300m kp=55m lambda=.01 pchan is=0) +.model DSHUT D(Ron=20k Roff=1g Vfwd=.6 epsilon=100m noiseless) +.model DIN D(Ron=300 Roff=100g Vfwd=.8 Vrev=.8 epsilon=100m revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=2 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DLIMN D(Ron=1Meg Roff=5g Vfwd=2.1 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model DBIAZ3 D(Ron=10 Roff=100g Vfwd=.3 epsilon=.1 ilimit=6.43m) +.ends LT6201 +* +.subckt LT6202 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=749f ink=196 incm=.8p incmk=196 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1)-2.21n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C10 N004 0 .1f Rpar=100K noiseless +D4 4 N011 DBIAZ +M1 3 N012 5 5 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +M2 3 N005 4 4 PI temp=27 +C3 4 N005 1f Rser=150Meg noiseless +A3 N006 N009 5 5 5 5 N005 5 OTA g=35n ref=-.04 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=1g noiseless +C12 N012 5 1f Rser=150Meg noiseless +D10 1 N011 DBIA1 +D11 2 N011 DBIA1 +D6 N012 5 DLIMN +A4 0 N004 0 0 0 0 N007 0 OTA g=1u linear en=2n enk=1.45k Vhigh=1e308 Vlow=-1e308 +C16 N009 3 400f +A5 N008 0 N006 N006 N006 N006 N009 N006 OTA g=258u iout=10.1u Rout=800k Vhigh=1e308 Vlow=-1e308 +D12 1 4 DESD +D13 2 4 DESD +G1 5 N012 N009 N006 5n +C5 N011 5 20p Rpar=10k noiseless +C7 4 1 .9p Rpar=8Meg noiseless +C13 4 5 1000p +D7 4 5 DP +C17 0 N007 8f Rpar=1Meg noiseless +G4 0 N008 N007 0 1m +D14 4 N005 DLIMP +L1 N008 0 5.88µ Cpar=13.3f Rser=1.11k Rpar=10.09k noiseless +D15 1 2 DIN +D16 N011 1 DBIA2 +D3 N011 2 DBIA2 +D1 5 2 DESD +D2 5 2 DESD +C1 4 2 .9p Rpar=8Meg noiseless +C6 1 5 .9p Rpar=8Meg noiseless +C8 2 5 .9p Rpar=8Meg noiseless +C4 2 1 .6p Rpar=12k Noiseless +D5 N011 1 DBIA3 +D8 N011 2 DBIA3 +G2 0 N006 5 0 .5m +G3 0 N006 4 0 .5m +C14 N006 0 .2p Rpar=1K +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=1.28m noiseless) +.model DBIA1 D(Ron=10k Roff=10Meg Vfwd=0 ilimit=.7u epsilon=.1 noiseless) +.model DBIA2 D(Ron=10k Roff=1g Vfwd=-.1 epsilon=.2 ilimit=1.4u noiseless) +.model DBIA3 D(Ron=1k Roff=1g Vfwd=2.8 epsilon=.1 ilimit=.9u noiseless) +.model DBIAZ D(Ron=100 Roff=100G Vfwd=1.1 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model NI VDMOS(Vto=300m kp=20m lambda=.01) +.model DLIMN D(Ron=1Meg Roff=5g Vfwd=2.45 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model PI VDMOS(Vto=-300m kp=20m lambda=.01 pchan is=0) +.model DLIMP D(Ron=100k Roff=1g Vfwd=2.45 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DIN D(Ron=1k Roff=100g Vfwd=.8 Vrev=.8 epsilon=100m revepsilon=100m noiseless) +.ends LT6202 +* +.subckt LT6205 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=3.9p ink=588 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-2,.1), V(5)-.2, .1)+1n*V(1)-320p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-1.9,.1), V(5)-.21, .1)+1n*V(2) +C10 N004 0 4f Rpar=100K noiseless +M1 3 N011 5 5 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +M2 3 N005 4 4 PI temp=27 +C3 4 N005 10f Rser=120Meg noiseless +A3 N008 N009 5 5 5 5 N005 5 OTA g=20n ref=-.052 linear Vlow=-1e308 Vhigh=1e308 +C11 3 5 1p Rpar=1g noiseless +C12 N011 5 10f Rser=120Meg noiseless +D10 4 2 DBIA1 +D6 N011 5 DLIMN +A4 0 N004 0 0 0 0 N007 0 OTA g=1m linear en=8.8n enk=470 Vhigh=1e308 Vlow=-1e308 +C16 N009 3 .75p +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=690u iout=.77m Rout=800k Vhigh=1e308 Vlow=-1e308 +D12 1 4 DESD +D13 2 4 DESD +G1 5 N011 N009 N008 7n +C7 4 1 1p Rpar=20Meg noiseless +C13 4 5 1000p Rpar=22.5k noiseless +D7 4 5 DP +C17 0 N007 .8p Rpar=1k noiseless +D14 4 N005 DLIMP +D15 1 2 DIN +D1 5 2 DESD +D2 5 1 DESD +C1 4 2 1p Rpar=20Meg noiseless +C6 1 5 1p Rpar=20Meg noiseless +C8 2 5 1p Rpar=20Meg noiseless +G2 0 N008 4 0 .5m +G3 0 N008 5 0 .5m +C14 N008 0 .2p Rpar=1K noiseless +C18 N005 3 10f Rser=200Meg noiseless +C19 3 N011 10f Rser=200Meg noiseless +D9 N006 0 DX +G5 0 N006 N007 0 .18m +C4 0 N006 .8p Rpar=10k noiseless +A2 0 N007 0 0 0 0 N006 0 OTA g=.9m iout=20u Vhigh=1e308 Vlow=-1e308 +D3 4 1 DBIA1 +D4 4 2 DBIA2 +D5 4 1 DBIA2 +.model DP D(Roff=1G Ron=100 Vfwd=0.5 ilimit=2.125m noiseless) +.model NI VDMOS(Vto=300m kp=20m lambda=.01) +.model PI VDMOS(Vto=-300m kp=20m lambda=.01 pchan) +.model DBIA1 D(Ron=1.5Meg Roff=1G Vfwd=1.7 epsilon=.1 noiseless) +.model DBIA2 D(Ron=10k Roff=1G Vfwd=1.5 epsilon=.1 ilimit=7u noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model DIN D(Ron=1k Roff=100g Vfwd=1.5 Vrev=1.5 epsilon=100m revepsilon=100m noiseless) +.model DX D(Ron=1k Roff=1k Vfwd=0 Vrev=0 ilimit=.2m revilimit=.2m) +.model DLIMN D(Ron=1Meg Roff=5g Vfwd=3.2 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=2 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.ends LT6205 +* +.subckt LT6230 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1p ink=33.5 incm=2.2p incmk=33.5 +C10 N004 0 .5f Rpar=100K noiseless +M1 3 N012 5 5 NI temp=27 +C2 4 3 1p Rpar=200Meg noiseless +D5 N012 5 DLIMN1 +M2 3 N008 4 4 PI temp=27 +D8 4 N008 DLIMP1 +C3 4 N008 1f Rser=50Meg noiseless +A3 N009 N010 5 5 5 5 N008 5 OTA g=20n ref=-.94 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=200Meg noiseless +C12 N012 5 1f Rser=50Meg noiseless +C16 N010 3 50f +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=65u iout=3.78u Vhigh=1e308 Vlow=-1e308 +G1 5 N012 N010 N009 20n +C7 4 1 1.45p Rser=200 Rpar=40Meg noiseless +C13 4 5 1000p Rpar=190Meg noiseless +S1 N010 N009 0 N005 SHUT2 +C1 N006 0 17p +C17 5 6 500f Rpar=100Meg noiseless +G2 0 N009 5 0 .5m +G4 0 N009 4 0 .5m +C18 N009 0 200p Rpar=1K noiseless +D1 2 1 DIN +D3 4 6 DSHUT +S4 N008 4 0 N005 SHUT1 +S2 5 N012 0 N005 SHUT1 +S3 5 2 N005 0 SBIAS +S5 5 1 N005 0 SBIAS +S7 4 5 N005 0 SPOW +D2 4 N008 DLIMP2 +D4 N012 5 DLIMN2 +C8 2 1 6.25p Rser=100 noiseless +G3 0 N007 N006 0 1m +L1 N007 0 8.6µ Cpar=12.7f Rser=1.09k Rpar=12.1k noiseless +D6 N006 0 DLIM1 +C4 4 2 1.45p Rser=200 Rpar=40Meg noiseless +C5 1 5 1.45p Rser=200 Rpar=40Meg noiseless +C6 2 5 1.45p Rser=200 Rpar=40Meg noiseless +C9 N007 3 15f +D7 N010 N009 DLIM2 +A2 6 4 0 0 0 N005 0 0 SCHMITT Vt=-.4 trise=1u tfall=90u +A4 0 N004 0 0 0 0 N006 0 OTA g=1m linear enk=201 en=2.26n/(.4+ 110n*dnlim(15Meg-freq,10k,7Meg) + 20n*dnlim(freq-30Meg,10k,5Meg)) enk=201 Vlow=-1e308 Vhigh=1e308 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-uplim(dnlim(-.119+.2059*V(4,5),.56,.01),.91,.01),.1), V(5)+uplim(dnlim(.38+.2059*V(4,5),1.06,.01),1.41,.01), .1)+1n*V(1)-1.035n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-uplim(dnlim(-.129+.2059*V(4,5),.55,.01),.9,.01),.1), V(5)+uplim(dnlim(.37+.2059*V(4,5),1.05,.01),1.4,.01), .1)+1n*V(2) +.model DSHUT D(Ron=170k Roff=1G Vfwd=2 epsilon=100m noiseless) +.model DIN D(Ron=100 Roff=7.5k Vfwd=.8 epsilon=.1 Vrev=.8 revepsilon=.1 noiseless) +.model SBIAS SW(level=2 Ron=5k Roff=10G vt=.5 vh=-.1 ilimit=5u vser=.8 noiseless ) +.model SPOW SW(Ron=92.6k Roff=1G vt=.5 vh=.1 noiseless) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m Vser=295m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=120m Rd=8) +.model PI VDMOS(Vto=-300m Kp=120m Rd=8 pchan) +.model DSLIM D(Ron=100 Roff=1k Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIM1 D(Ron=1 Roff=1k Vfwd=70m epsilon=10m Vrev=70m revepsilon=10m noiseless) +.model DLIM2 D(Ron=1k Roff=70Meg Vfwd=2.1 epsilon=.1 Vrev=1.9 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.ends LT6230 +* +.subckt LT6230-10 1 2 3 4 5 6 +C10 N004 0 2f Rpar=100K noiseless +M1 3 N012 5 5 NI temp=27 +C2 4 3 1p Rpar=200Meg noiseless +D5 N012 5 DLIMN1 +M2 3 N008 4 4 PI temp=27 +D8 4 N008 DLIMP1 +C3 4 N008 1f Rser=50Meg noiseless +A3 N009 N010 5 5 5 5 N008 5 OTA g=20n ref=-.94 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=200Meg noiseless +C12 N012 5 1f Rser=50Meg noiseless +C16 N010 3 8f +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=65u asym isource=4u isink=-3.8u Vhigh=1e308 Vlow=-1e308 +G1 5 N012 N010 N009 20n +C7 4 1 1.45p Rser=200 Rpar=40Meg noiseless +C13 4 5 1000p Rpar=190Meg noiseless +S1 N010 N009 0 N005 SHUT2 +C1 N006 0 25p +C17 5 6 500f Rpar=100Meg noiseless +G2 0 N009 5 0 .5m +G4 0 N009 4 0 .5m +C18 N009 0 200p Rpar=1K noiseless +D1 2 1 DIN +D3 4 6 DSHUT +S4 N008 4 0 N005 SHUT1 +S2 5 N012 0 N005 SHUT1 +S3 5 2 N005 0 SBIAS +S5 5 1 N005 0 SBIAS +S7 4 5 N005 0 SPOW +D2 4 N008 DLIMP2 +D4 N012 5 DLIMN2 +C8 2 1 6.25p Rser=100 noiseless +G3 0 N007 N006 0 1m +L1 N007 0 8.6µ Cpar=12.7f Rser=1.09k Rpar=12.1k noiseless +D6 N006 0 DLIM1 +C4 4 2 1.45p Rser=200 Rpar=40Meg noiseless +C5 1 5 1.45p Rser=200 Rpar=40Meg noiseless +C6 2 5 1.45p Rser=200 Rpar=40Meg noiseless +D7 N010 N009 DLIM2 +A2 6 4 0 0 0 N005 0 0 SCHMITT Vt=-.4 trise=1u tfall=90u +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1p ink=33.5 incm=2.2p incmk=33.5 +A4 0 N004 0 0 0 0 N006 0 OTA g=1m linear enk=201 en=2.26n/(.4+ 110n*dnlim(15Meg-freq,10k,7Meg) + 20n*dnlim(freq-30Meg,10k,5Meg)) enk=201 Vlow=-1e308 Vhigh=1e308 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-uplim(dnlim(-.119+.2059*V(4,5),.56,.01),.91,.01),.1), V(5)+uplim(dnlim(.38+.2059*V(4,5),1.06,.01),1.41,.01), .1)+1n*V(1)-1.035n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-uplim(dnlim(-.129+.2059*V(4,5),.55,.01),.9,.01),.1), V(5)+uplim(dnlim(.37+.2059*V(4,5),1.05,.01),1.4,.01), .1)+1n*V(2) +.model DSHUT D(Ron=170k Roff=1G Vfwd=2 epsilon=100m noiseless) +.model DIN D(Ron=100 Roff=7.5k Vfwd=.8 epsilon=.1 Vrev=.8 revepsilon=.1 noiseless) +.model SBIAS SW(level=2 Ron=5k Roff=10G vt=.5 vh=-.1 ilimit=5u vser=.8 noiseless ) +.model SPOW SW(Ron=92.6k Roff=1G vt=.5 vh=.1 noiseless) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m Vser=295m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=120m Rd=8) +.model PI VDMOS(Vto=-300m Kp=120m Rd=8 pchan) +.model DSLIM D(Ron=100 Roff=1k Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIM1 D(Ron=1 Roff=1k Vfwd=60m epsilon=10m Vrev=83m revepsilon=10m noiseless) +.model DLIM2 D(Ron=1k Roff=70Meg Vfwd=2.1 epsilon=.1 Vrev=1.9 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.ends LT6230-10 +* +.subckt LT6231 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2.4p ink=33.5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-uplim(dnlim(-.119+.2059*V(4,5),.56,.01),.91,.01),.1), V(5)+uplim(dnlim(.38+.2059*V(4,5),1.06,.01),1.41,.01), .1)+1n*V(1)-1.035n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-uplim(dnlim(-.129+.2059*V(4,5),.55,.01),.9,.01),.1), V(5)+uplim(dnlim(.37+.2059*V(4,5),1.05,.01),1.4,.01), .1)+1n*V(2) +C10 N004 0 .5f Rpar=100K noiseless +M1 3 N011 5 5 NI temp=27 +C2 4 3 1p Rpar=200Meg noiseless +D5 N011 5 DLIMN1 +M2 3 N007 4 4 PI temp=27 +D8 4 N007 DLIMP1 +C3 4 N007 1f Rser=50Meg noiseless +A3 N008 N009 5 5 5 5 N007 5 OTA g=20n ref=-.94 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=200Meg noiseless +C12 N011 5 1f Rser=50Meg noiseless +C16 N009 3 50f +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=65u iout=3.78u Vhigh=1e308 Vlow=-1e308 +G1 5 N011 N009 N008 20n +C7 4 1 1.45p Rser=200 Rpar=40Meg noiseless +C13 4 5 100p Rpar=92.6k noiseless +C1 N005 0 17p +G2 0 N008 5 0 .5m +G4 0 N008 4 0 .5m +C18 N008 0 200p Rpar=1K noiseless +D1 2 1 DIN +D2 4 N007 DLIMP2 +D4 N011 5 DLIMN2 +C8 2 1 6.25p Rser=100 noiseless +G3 0 N006 N005 0 1m +L1 N006 0 8.6µ Cpar=12.7f Rser=1.09k Rpar=12.1k noiseless +D6 N005 0 DLIM1 +C4 4 2 1.45p Rser=200 Rpar=40Meg noiseless +C5 1 5 1.45p Rser=200 Rpar=40Meg noiseless +C6 2 5 1.45p Rser=200 Rpar=40Meg noiseless +C9 N006 3 15f +D7 N009 N008 DLIM2 +D3 2 5 DBIAS +D9 1 5 DBIAS +A2 0 N004 0 0 0 0 N005 0 OTA g=1m linear enk=201 en=2.26n/(.4+ 110n*dnlim(15Meg-freq,10k,7Meg) + 20n*dnlim(freq-30Meg,10k,5Meg)) enk=201 Vlow=-1e308 Vhigh=1e308 +.model DSHUT D(Ron=170k Roff=1G Vfwd=2 epsilon=100m noiseless) +.model DIN D(Ron=100 Roff=7.5k Vfwd=.8 epsilon=.1 Vrev=.8 revepsilon=.1 noiseless) +.model DBIAS D(Ron=5k Roff=1G Vfwd=.75 epsilon=50m ilimit=5u noiseless) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m Vser=295m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=120m Rd=8) +.model PI VDMOS(Vto=-300m Kp=120m Rd=8 pchan) +.model DSLIM D(Ron=100 Roff=1k Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIM1 D(Ron=1 Roff=1k Vfwd=70m epsilon=10m Vrev=70m revepsilon=10m noiseless) +.model DLIM2 D(Ron=1k Roff=70Meg Vfwd=2.1 epsilon=.1 Vrev=1.9 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.ends LT6231 +* +.subckt LT6233 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.43p ink=38 incm=.65p incmk=38 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.9,.1), V(5)+1.4, .1)+1n*V(1)-.6n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.89,.1), V(5)+1.39, .1)+1n*V(2) +C10 N004 0 .5f Rpar=100K noiseless +M1 3 N012 5 5 NI temp=27 +C2 4 3 1p Rpar=200Meg noiseless +D5 N012 5 DLIMN1 +M2 3 N008 4 4 PI temp=27 +D8 4 N008 DLIMP1 +C3 4 N008 1f Rser=50Meg noiseless +A3 N009 N010 5 5 5 5 N008 5 OTA g=20n ref=-.415 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=200Meg noiseless +C12 N012 5 1f Rser=50Meg noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=1m asym en=1.9n enk=74 isource=78u Isink=-98u Vlow=-1e308 Vhigh=1e308 +C16 N010 3 138f +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=50u iout=2.75u Vhigh=1e308 Vlow=-1e308 +G1 5 N012 N010 N009 20n +C7 4 1 1.25p Rser=200 Rpar=40Meg noiseless +C13 4 5 1000p Rpar=190Meg noiseless +S1 N010 N009 0 N005 SHUT2 +C1 N006 0 35p Rpar=1k noiseless +C17 5 6 500f Rpar=100Meg noiseless +G2 0 N009 5 0 .5m +G4 0 N009 4 0 .5m +C18 N009 0 200p Rpar=1K noiseless +D1 2 1 DIN +D3 4 6 DSHUT +S4 N008 4 0 N005 SHUT1 +S2 5 N012 0 N005 SHUT1 +S3 5 2 N005 0 SBIAS +S5 5 1 N005 0 SBIAS +D2 4 N008 DLIMP2 +D4 N012 5 DLIMN2 +C8 2 1 1.7p Rser=100 Rpar=25k noiseless +G3 0 N007 N006 0 1m +L1 N007 0 18.8µ Cpar=52f Rser=1.12k Rpar=9.33k noiseless +C4 4 2 1.25p Rser=200 Rpar=40Meg noiseless +C5 1 5 1.25p Rser=200 Rpar=40Meg noiseless +C6 2 5 1.25p Rser=200 Rpar=40Meg noiseless +D7 N010 N009 DLIM2 +A2 6 4 0 0 0 N005 0 0 SCHMITT Vt=-.4 trise=1u tfall=90u +.model DSHUT D(Ron=170k Roff=1G Vfwd=2 epsilon=100m noiseless) +.model DIN D(Ron=1k Roff=1Meg Vfwd=.7 epsilon=.1 Vrev=.7 revepsilon=.1 noiseless) +.model SBIAS SW(level=2 Ron=5k Roff=10G vt=.5 vh=-.1 ilimit=1.5u vser=.8 noiseless ) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m Vser=295m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=400m) +.model PI VDMOS(Vto=-300m Kp=400m pchan) +.model DSLIM D(Ron=100 Roff=1k Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIM2 D(Ron=1k Roff=70Meg Vfwd=2.1 epsilon=.1 Vrev=1.9 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=.75 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=.75 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.ends LT6233 +* +.subckt LT6233-10 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.9,.1), V(5)+1.4, .1)+1n*V(1)-.6n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.89,.1), V(5)+1.39, .1)+1n*V(2) +C10 N004 0 .5f Rpar=100K noiseless +M1 3 N012 5 5 NI temp=27 +C2 4 3 1p Rpar=200Meg noiseless +D5 N012 5 DLIMN1 +M2 3 N008 4 4 PI temp=27 +D8 4 N008 DLIMP1 +C3 4 N008 1f Rser=50Meg noiseless +A3 N009 N010 5 5 5 5 N008 5 OTA g=20n ref=-.415 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=200Meg noiseless +C12 N012 5 1f Rser=50Meg noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=1m asym en=1.9n enk=74 isource=83u isink=-103.5u Vlow=-1e308 Vhigh=1e308 +C16 N010 3 245f +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=500u iout=44u Vhigh=1e308 Vlow=-1e308 +G1 5 N012 N010 N009 20n +C7 4 1 1.25p Rser=200 Rpar=40Meg noiseless +C13 4 5 1000p Rpar=190Meg noiseless +S1 N010 N009 0 N005 SHUT2 +C1 N006 0 50p Rpar=1k noiseless +C17 5 6 500f Rpar=100Meg noiseless +G2 0 N009 5 0 .5m +G4 0 N009 4 0 .5m +C18 N009 0 200p Rpar=1K noiseless +D1 2 1 DIN +D3 4 6 DSHUT +S4 N008 4 0 N005 SHUT1 +S2 5 N012 0 N005 SHUT1 +S3 5 2 N005 0 SBIAS +S5 5 1 N005 0 SBIAS +D2 4 N008 DLIMP2 +D4 N012 5 DLIMN2 +C8 2 1 1.7p Rser=100 Rpar=25k noiseless +G3 0 N007 N006 0 1m +L1 N007 0 15.3µ Cpar=66f Rser=1.16k Rpar=7.25k noiseless +C4 4 2 1.25p Rser=200 Rpar=40Meg noiseless +C5 1 5 1.25p Rser=200 Rpar=40Meg noiseless +C6 2 5 1.25p Rser=200 Rpar=40Meg noiseless +D7 N010 N009 DLIM2 +A2 6 4 0 0 0 N005 0 0 SCHMITT Vt=-.4 trise=1u tfall=90u +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.43p ink=38 incm=.65p incmk=38 +.model DSHUT D(Ron=170k Roff=1G Vfwd=2 epsilon=100m noiseless) +.model DIN D(Ron=1k Roff=1Meg Vfwd=.7 epsilon=.1 Vrev=.7 revepsilon=.1 noiseless) +.model SBIAS SW(level=2 Ron=5k Roff=10G vt=.5 vh=-.1 ilimit=1.5u vser=.8 noiseless ) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m Vser=295m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=400m) +.model PI VDMOS(Vto=-300m Kp=400m pchan) +.model DSLIM D(Ron=100 Roff=1k Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIM2 D(Ron=1k Roff=7Meg Vfwd=2.1 epsilon=.1 Vrev=1.9 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=.75 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=.75 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.ends LT6233-10 +* +.subckt LT6234 1 2 3 4 5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.9,.1), V(5)+1.4, .1)+1n*V(1)-.6n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.89,.1), V(5)+1.39, .1)+1n*V(2) +C10 N004 0 .5f Rpar=100K noiseless +M1 3 N011 5 5 NI temp=27 +C2 4 3 1p Rpar=200Meg noiseless +D5 N011 5 DLIMN1 +M2 3 N007 4 4 PI temp=27 +D8 4 N007 DLIMP1 +C3 4 N007 1f Rser=50Meg noiseless +A3 N008 N009 5 5 5 5 N007 5 OTA g=20n ref=-.415 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=200Meg noiseless +C12 N011 5 1f Rser=50Meg noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1m asym en=1.9n enk=74 isource=78u Isink=-98u Vlow=-1e308 Vhigh=1e308 +C16 N009 3 138f +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=50u iout=2.75u Vhigh=1e308 Vlow=-1e308 +G1 5 N011 N009 N008 20n +C7 4 1 1.25p Rser=200 Rpar=40Meg noiseless +C13 4 5 1000p Rpar=190Meg noiseless +C1 N005 0 35p Rpar=1k noiseless +G2 0 N008 5 0 .5m +G4 0 N008 4 0 .5m +C18 N008 0 200p Rpar=1K noiseless +D1 2 1 DIN +D2 4 N007 DLIMP2 +D4 N011 5 DLIMN2 +C8 2 1 1.7p Rser=100 Rpar=25k noiseless +G3 0 N006 N005 0 1m +L1 N006 0 18.8µ Cpar=52f Rser=1.12k Rpar=9.33k noiseless +C4 4 2 1.25p Rser=200 Rpar=40Meg noiseless +C5 1 5 1.25p Rser=200 Rpar=40Meg noiseless +C6 2 5 1.25p Rser=200 Rpar=40Meg noiseless +D7 N009 N008 DLIM2 +D3 1 5 DBIAS +D6 2 5 DBIAS +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.43p ink=38 incm=.65p incmk=38 +.model DIN D(Ron=1k Roff=1Meg Vfwd=.7 epsilon=.1 Vrev=.7 revepsilon=.1 noiseless) +.model DBIAS D(Ron=5k Roff=10G vfwd=.75 epsilon=.1 ilimit=1.5u noiseless) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m Vser=295m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=400m) +.model PI VDMOS(Vto=-300m Kp=400m pchan) +.model DSLIM D(Ron=100 Roff=1k Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIM2 D(Ron=1k Roff=70Meg Vfwd=2.1 epsilon=.1 Vrev=1.9 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=.75 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=.75 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.ends LT6234 +* +.subckt LT6550 1 2 3 4 5 +B2 N002 0 I=10u*dnlim(uplim(V(VINM),V(3)+.21,.1), V(4)-.21, .1)+1n*V(VINM) +C10 N002 0 1f Rpar=100K noiseless +M1 5 N010 4 4 NI temp=27 +C2 3 5 1p Rpar=100Meg noiseless +D5 N010 4 DLIMN +M2 5 N004 3 3 PI temp=27 +D8 3 N004 DLIMP +A3 N005 N006 4 4 4 4 N004 4 OTA g=200n ref=-50m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=100Meg noiseless +A4 0 N002 0 0 0 0 X1 0 OTA g=1m linear en=12n Vhigh=10 Vlow=-10 +A5 N003 0 N005 N005 N005 N005 N006 N005 OTA g=68u iout=51u Vhigh=1e308 Vlow=-1e308 +G1 4 N010 N006 N005 200n +D9 N006 N005 DLIM +C7 3 1 1p Rser=1k Rpar=700k noiseless +C13 3 4 1000p +C1 X1 0 300f Rpar=1k noiseless +G2 0 N005 4 0 .5m +G4 0 N005 3 0 .5m +C18 N005 0 200p Rpar=1K noiseless +D10 1 3 DESD +D11 4 1 DESD +A1 VINM 1 0 0 0 0 0 0 OTA g=0 in=8p +C8 N004 5 .1f Rser=40Meg noiseless +C9 5 N010 .1f Rser=40Meg noiseless +C4 3 VINM 1p Rser=1k Rpar=5T noiseless +C5 1 4 1p Rser=1k Rpar=1Meg noiseless +C6 VINM 4 1p Rser=1k Rpar=5T noiseless +D3 3 4 DPOW +C3 3 N004 20f Rser=15Meg noiseless +C12 N010 4 20f Rser=15Meg noiseless +C14 N006 5 100f +B1 0 N002 I=10u*dnlim(uplim(V(1),V(3)-1.65,.1), V(4)-.2, .1)+1n*V(1)-52.54p +R1 5 VINM 450 noiseless +R2 VINM 2 450 noiseless +G3 0 N003 X1 0 1m +C15 N003 0 100f Rpar=1k noiseless +D1 VINM 1 DIN +S2 1 3 N005 1 SBIAS +.model SBIAS SW(level=2 Ron=3k Roff=1Meg vt=.2 vh=-.2 ilimit=13u noiseless) +.model DPOW D(Ron=100 Roff=1G Vfwd=.6 epsilon=.1 ilimit=7.28m noiseless) +.model DIN D(Ron=400 Roff=1G Vfwd=1.4 epsilon=.1 noiseless) +.model NI VDMOS(Vto=300m kp=60m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=60m lambda=.01 pchan) +.model DLIM D(Ron=1k Roff=70Meg Vfwd=4 Vrev=4 epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.6 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.6 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.ends LT6550 +* +.subckt LT6551 1 2 3 4 +B2 N002 0 I=10u*dnlim(uplim(V(VINM),V(3)+.21,.1), V(2)-.21, .1)+1n*V(VINM) +C10 N002 0 1f Rpar=100K noiseless +M1 4 N009 2 2 NI temp=27 +C2 3 4 1p Rpar=100Meg noiseless +D5 N009 2 DLIMN +M2 4 N004 3 3 PI temp=27 +D8 3 N004 DLIMP +A3 N005 N006 2 2 2 2 N004 2 OTA g=200n ref=-50m linear vlow=-1e308 vhigh=1e308 +C11 4 2 1p Rpar=100Meg noiseless +A4 0 N002 0 0 0 0 X1 0 OTA g=1m linear en=12n Vhigh=10 Vlow=-10 +A5 N003 0 N005 N005 N005 N005 N006 N005 OTA g=68u iout=51u Vhigh=1e308 Vlow=-1e308 +G1 2 N009 N006 N005 200n +D9 N006 N005 DLIM +C7 3 1 1p Rser=1k Rpar=700k noiseless +C13 3 2 1000p +C1 X1 0 300f Rpar=1k noiseless +G2 0 N005 2 0 .5m +G4 0 N005 3 0 .5m +C18 N005 0 200p Rpar=1K noiseless +D10 1 3 DESD +D11 2 1 DESD +A1 VINM 1 0 0 0 0 0 0 OTA g=0 in=8p +C8 N004 4 .1f Rser=40Meg noiseless +C9 4 N009 .1f Rser=40Meg noiseless +C4 3 VINM 1p Rser=1k Rpar=5T noiseless +C5 1 2 1p Rser=1k Rpar=1Meg noiseless +C6 VINM 2 1p Rser=1k Rpar=5T noiseless +D3 3 2 DPOW +C3 3 N004 20f Rser=15Meg noiseless +C12 N009 2 20f Rser=15Meg noiseless +C14 N006 4 100f +B1 0 N002 I=10u*dnlim(uplim(V(1),V(3)-1.65,.1), V(2)-.2, .1)+1n*V(1)-52.54p +R1 4 VINM 450 noiseless +R2 VINM 2 450 noiseless +G3 0 N003 X1 0 1m +C15 N003 0 100f Rpar=1k noiseless +D1 VINM 1 DIN +S2 1 3 N005 1 SBIAS +.model SBIAS SW(level=2 Ron=3k Roff=1Meg vt=.2 vh=-.2 ilimit=13u noiseless) +.model DPOW D(Ron=100 Roff=1G Vfwd=.6 epsilon=.1 ilimit=7.28m noiseless) +.model DIN D(Ron=400 Roff=1G Vfwd=1.4 epsilon=.1 noiseless) +.model NI VDMOS(Vto=300m kp=60m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=60m lambda=.01 pchan) +.model DLIM D(Ron=1k Roff=70Meg Vfwd=4 Vrev=4 epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.6 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.6 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.ends LT6551 +* +.subckt LTC2052 1 2 3 4 5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.9,.1), V(5)-.4, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.89,.1), V(5)-.41, .1)+1n*V(2) +C9 4 2 .85p Rpar=1T noiseless +C10 N004 0 1f Rpar=100K noiseless +M1 4 N005 3 3 N temp=27 +M2 5 N005 3 3 P temp=27 +D5 N005 3 Y +D6 3 N005 Y +R2 4 N005 2G noiseless +R3 N005 5 2G noiseless +C14 0 N006 15p Rpar=6k noiseless +G1 N005 0 N005 4 500m dir=1 vto=.3 +G2 0 N005 5 N005 500m dir=1 vto=.45 +G3 0 N006 0 N007 167µ +C2 4 3 1p Rpar=1G noiseless +C15 3 5 1p Rpar=1G noiseless +A2 0 N004 0 0 0 0 N007 0 OTA g=3.2m linear en=79n Rout=1k Cout=40p Vlow=-1e308 Vhigh=1e308 +C3 N005 0 500p Rser=100 noiseless +C1 2 5 .85p Rpar=1T noiseless +C4 4 1 .85p Rpar=1T noiseless +C6 1 5 .85p Rpar=1T noiseless +R4 4 5 3.3Meg noiseless +D1 4 5 DPOW +A1 N006 0 0 0 0 0 N005 0 OTA g=3.2m iout=1m Vlow=-1e308 Vhigh=1e308 +.model Y D(Ron=100 Roff=1T Vfwd=.6 epsilon=.1 noiseless) +.model N VDMOS(Vto=-100m Kp=90m) +.model P VDMOS(Vto=100m Kp=70m pchan) +.model shutD SW(Ron=1T Roff=10k vt=.5 vh=-.1) +.model DS D(Ron=100 Roff=1G Vfwd=.2 Vrev=.2 epsilon=0.1 revepsilon=0.1 noiseless) +.model SPOW SW(level=2 Ron=500 Roff=1G vt=.5 vh=-.1 ilimit=.5m noiseless) +.model DPOW D(Ron=500 Roff=1G vfwd=.5 epsilon=.1 ilimit=.450m noiseless) +.ends LTC2052 +* +.subckt LTC2054 1 2 3 4 5 +M1 4 X3 N005 N005 N temp=27 +M2 5 X3 N009 N009 P temp=27 +C1 X3 0 20f Rpar=1Meg noiseless +C3 4 3 .5p +C4 3 5 .5p +B1 0 N006 I=10u*dnlim(uplim(V(1),V(4)-.4,.1), V(5)-0.3, .1)+1n*V(1) +B2 N006 0 I=10u*dnlim(uplim(V(2),V(4)-.39,.1), V(5)-0.31, .1)+1n*V(2) +C9 4 2 1p Rser=100 noiseless +C10 N006 0 1f Rpar=100K noiseless +D1 X3 3 YU +D6 3 X3 YD +D7 4 5 DP +G3 N004 0 N004 4 600m dir=1 vto=0.2 +G6 0 N004 5 N004 600m dir=1 vto=0.4 +R4 4 N004 1G +R5 N004 5 1G +G2 0 X3 N004 0 1µ +C2 4 1 1p Rser=100 noiseless +C6 2 5 1p Rser=100 noiseless +C7 1 5 1p Rser=100 noiseless +R3 4 5 111k noiseless +R1 3 N009 1k +R2 N005 3 1k +S1 3 N005 4 5 SUL +S2 N009 3 4 5 SDL +C11 4 N005 100f +C13 N009 5 100f +A3 0 N007 0 0 0 0 N004 0 OTA g=2.05m iout=3.1m Cout=6n Vlow=-1e308 Vhigh=1e308 +A1 0 N006 0 0 0 0 N007 0 OTA g=20u linear Vlow=-5 Vhigh=5 Rout=500k Cout=200f en= 1n + 128n/ (1.1+ (min(freq,1.5k)/800)**1.8 + (max(1.8k,freq)/3k)**1.8) +D2 5 2 DESD +D3 2 4 DESD +D4 5 1 DESD +D5 1 4 DESD +.model YU D(Ron=10k Roff=1T Vfwd=1 epsilon=.2 noiseless) +.model YD D(Ron=2k Roff=1T Vfwd=.98 epsilon=.2 noiseless) +.model N VDMOS(Vto=-10m Kp=12m) +.model P VDMOS(Vto=10m Kp=10m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=84.4u noiseless) +.model SUL SW(Ron=1 Roff=80 vt=4 vh=-1) +.model SDL SW(Ron=1 Roff=400 vt=7.5 vh=-5) +.model DESD D(Ron=100 Roff=1T vfwd=600m epsilon=600m) +.ends LTC2054 +* +.subckt LT1678 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=276f ink=178 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1)-17.2p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C9 4 2 2.1p Rpar=4G noiseless +C10 N004 0 2f Rpar=100K noiseless +D4 N009 5 DBIA2 +M1 3 N010 5 5 NI temp=27 +C2 4 3 1p Rpar=1g noiseless +D5 N010 5 DLIMN1 +M2 3 VP 4 4 PI temp=27 +D8 4 VP DLIMP +C3 4 VP 40p Rser=180k noiseless +A3 N006 N008 5 5 5 5 VP 5 OTA g=800n ref=-.02 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=1g noiseless +C12 N010 5 10f Rser=250k noiseless +D10 N009 1 DBIA1 +D6 N010 5 DLIMN2 +A4 0 N004 0 0 0 0 N005 0 OTA g=10u linear en=3.9n enk=28 Vhigh=1e308 Vlow=-1e308 +C16 N008 3 7p Rser=100 noiseless +A5 N007 0 N006 N006 N006 N006 N008 N006 OTA g=1m iout=42.6u Vhigh=1e308 Vlow=-1e308 +D12 1 4 DBIAOT +D13 2 4 DBIAOT +G1 5 N010 N008 N006 30n +C5 4 N009 20p Rpar=1Meg noiseless +C14 VP 3 10f +B3 VP 5 I=25n*V(VP,3)/dnlim(V(4,5),2,.1) +C7 4 1 2.1p Rpar=4G noiseless +C13 4 5 1000p +C15 VP N010 100f Rser=100k noiseless +D7 4 5 DP +D15 1 2 DINP +C6 1 5 2.1p Rpar=4G noiseless +C8 2 5 2.1p Rpar=4G noiseless +S2 0 N005 3 4 LIMU +S3 N005 0 5 3 LIMD +D1 N008 N006 DLIM +D9 N009 2 DBIA1 +C1 N007 0 274p Rpar=1k Rser=290.3 noiseless +G2 0 N007 N005 0 1m +L1 N005 0 4.03m Cpar=3.93f Rser=127k Rpar=470.4k noiseless +S1 5 N010 5 3 LIMD2 +G3 0 N006 5 0 5m +G4 0 N006 4 0 5m +C4 N006 0 20p Rpar=100 +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=840u noiseless) +.model DBIA1 D(Ron=1k Roff=100G Vfwd=.1 ilimit=390n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1k Roff=10G Vfwd=1.3 epsilon=.1 noiseless) +.model DBIAOT D(Ron=10k Vfwd=-.7 ilimit=193n epsilon=50m noiseless) +.model DINP D(Ron=100 Roff=10G Vfwd=1.4 Vrev=1.4 epsilon=100m revepsilon=100m noiseless) +.model LIMU SW(level=2 Ron=1 Roff=2Meg vt=-100m vh=-10m oneway noiseless) +.model LIMD SW(level=2 Ron=1 Roff=2Meg vt=-60m vh=-10m oneway noiseless) +.model LIMD2 SW(level=2 Ron=1Meg Roff=1T vt=-60m vh=-10m oneway) +.model NI VDMOS(Vto=300m kp=30m lambda=.01 rs=5 is=0) +.model DLIMN1 D(Ron=100k Roff=3g Vfwd=1.6 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=500k Roff=1G Vfwd=1 epsilon=1.2 ilimit=70n noiseless) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0 rs=2) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=2.2 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7Meg Vfwd=2.3 Vrev=5 epsilon=10m revepsilon=10m noiseless) +.ends LT1678 +* +.subckt LT6013 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=147f ink=45.5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-1.1,.1), V(5)+.9, .1)+1n*V(1)-89p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-1.09,.1), V(5)+.89, .1)+1n*V(2) +C10 N004 0 400f Rpar=100K noiseless +M1 3 N010 5 5 NI temp=27 +C2 4 3 1p Rpar=860k noiseless +D5 N010 5 DLIMN +M2 3 N006 4 4 PI temp=27 +D8 4 N006 DLIMP +C3 4 N006 500f Rser=1.5Meg noiseless +A3 N007 N008 5 5 5 5 N006 5 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=860k noiseless +C12 N010 5 10f Rser=250k noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear en=9.5n enk=2.6 Vhigh=1e308 Vlow=-1e308 +C16 N008 3 3p +A5 N005 0 N007 N007 N007 N007 N008 N007 OTA g=30u iout=601n Vhigh=1e308 Vlow=-1e308 +G1 5 N010 N008 N007 200n +D9 N008 N007 DLIM +C14 N006 3 4f +C7 4 1 2p Rser=2k Rpar=240G noiseless +C13 4 5 1000p Rpar=896k noiseless +C15 N006 N010 50f Rser=1Meg noiseless +C1 N005 0 260f Rpar=1Meg noiseless +G2 0 N007 5 0 .5m +G4 0 N007 4 0 .5m +C18 N007 0 200p Rpar=1K noiseless +D1 2 1 DIN +C4 4 2 2p Rser=2k Rpar=240G noiseless +C5 1 5 2p Rser=2k Rpar=240G noiseless +C6 2 5 2p Rser=2k Rpar=240G noiseless +D2 4 5 DPOW +D3 2 5 DBIAS +D4 1 5 DBIAS +.model DIN D(Ron=1k Roff=20Meg Vfwd=1.5 epsilon=.1 Vrev=1.5 revepsilon=.1 noiseless) +.model DBIAS D(Ron=50Meg Roff=100G Vfwd=.6 epsilon=.1 ilimit=99p noiseless) +.model DPOW D(Ron=1k Vfwd=.5 epsilon=.1 ilimit=60.7u noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=200m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.3 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.25 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.ends LT6013 +* +.subckt LT6016 1 2 3 4 5 +B1 0 N006 I=10u*dnlim(uplim(V(1),V(4)+76.1,.1), V(4)-.15, .1)+1n*V(1)-10.72254n +B2 N006 0 I=10u*dnlim(uplim(V(2),V(4)+76.1,.1), V(4)-.16, .1)+1n*V(2) +C10 N006 0 50f Rpar=100K noiseless +M1 N016 NG 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 NG 4 DLIMN1 +M2 5 N007 N004 N004 PI temp=27 +A3 N013 N015 4 4 4 4 N007 4 OTA g=2u ref=-.305 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +D6 NG 4 DLIMN2 +C16 N015 5 1.8p +A5 N011 0 N013 N013 N013 N013 N015 N013 OTA g=25u asym isource=1.8u isink=-2.8u Vlow=-1e308 Vhigh=1e308 +G1 4 NG N015 N013 140n +D9 N015 N013 DLIM +C7 3 1 2.5p Rser=1k Rpar=100G noiseless +C13 3 4 10p +C1 N009 0 25f +G2 0 N013 4 0 .5m +G4 0 N013 3 0 .5m +C18 N013 0 200p Rpar=1K noiseless +C4 3 2 2.5p Rser=1k Rpar=100G noiseless +C6 1 4 2.5p Rser=1k Rpar=100G noiseless +C8 2 4 2.5p Rser=1k Rpar=100G noiseless +D3 3 N004 DSBD +C5 3 N004 100f Rpar=10Meg noiseless +D4 N004 N007 DLIMP +D2 N009 0 DLIM0 +D1 4 5 DESD +D8 4 1 DESD +D10 4 2 DESD +A2 N014 0 0 0 0 0 0 0 OTA g=0 in=11.4p ink=15 +D11 5 N016 DNR +C15 N016 4 100f Rpar=10Meg noiseless +D7 N007 3 DLIMPR +D12 3 4 DP +A6 4 3 0 0 0 0 N005 0 OTA g=2u iout=1u ref=-2.5 Rout=1Meg Cout=100f vlow=-1e308 vhigh=1e308 +S4 N012 4 N005 0 SBiasN +D13 3 N012 DBiasDrop +C14 N012 4 100f +S2 N004 N007 0 N005 SHUT +S3 NG 4 0 N005 SHUT +D16 2 1 D1Meg +C17 N010 0 54.26f noiseless Rser=2.667Meg Rpar=1Meg +G3 0 N010 N009 0 1µ +D17 0 N009 DNLIN +C19 N011 0 25f noiseless Rpar=1Meg +G5 0 N011 N010 0 1µ +S5 N013 N015 4 5 SGK +C3 3 N007 .9p Rser=700k noiseless +C12 NG 4 .9p Rser=700k noiseless +D14 2 N012 DBiasOTT +D15 1 N012 DBiasOTT +S1 0 N008 3 2 SNOI +A7 N008 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=100f ink=255 +GNOI_I 1 2 N014 0 1µ +S6 0 N014 3 2 SNOI +A4 0 N006 0 0 0 0 N009 0 OTA g=1u linear en=18n enk=3 Vhigh=1e308 Vlow=-1e308 +GNOI_V N006 0 N008 0 10n +.model DP D(Ron=1k Roff=1G Vfwd=2.5 epsilon=100m ilimit=32u noiseless) +.model DESD D(Ron=1k Roff=1G vfwd=700m epsilon=100m noiseless) +.model SNOI SW(Ron=1 Roff=1Meg vt=1.2 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m Mtriode=.9 lambda=.01) +.model PI VDMOS(Vto=-300m Kp=120m lambda=.01 pchan is=0) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=1 epsilon=100m Vrev=1 epsilon=100m noiseless) +.model DNLIN D(Roff=1.8Meg Ron=800k vfwd=0 epsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=8Meg Vfwd=500m Vrev=100m epsilon=10m revepsilon=10m noiseless) +.model SHUT SW(level=2 Ron=10k Roff=100G vt=-.5 vh=-.2 noiseless) +.model DSBD D( Ron=100 Roff=100Meg Vfwd=420m epsilon=50m Vrev=100 revepsilon=10m noiseless) +.model DNR D(Ron=10 Roff=1G Vfwd=1m epsilon=300m noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.2 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=44n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1 epsilon=10m noiseless) +.model DLIMPR D(Ron=5Meg Roff=1G Vfwd=100m epsilon=10m noiseless) +.model SGK SW(level=2 Ron=65k Roff=100G vt=-260m vh=150m oneway epsilon=10m noiseless) +.model SBiasN SW(level=2 Ron=10k Roff=1g vt=.5 vh=-.2 ilimit=28u noiseless) +.model DBiasDrop D(Ron=1k Roff=1G vfwd=1.6 epsilon=500m noiseless) +.model DBiasOTT D(Ron=500 Roff=1G vfwd=700m epsilon=200m noiseless) +.model D1Meg D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=10n revilimit=10n noiseless) +.ends LT6016 +* +.subckt LTC6268 1 2 3 4 5 6 +A1 2 REF 0 0 0 0 0 0 OTA g=0 in=1p*uplim((freq/20Meg)**.9,3,.2)*dnlim((freq/60Meg)**1.5,1,.2) +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.4,.1), V(5)-.2, .1)+1n*V(1)-7.501009n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.39,.1), V(5)-.21, .1)+1n*V(2) +C10 N004 0 .1f Rpar=100K noiseless +M1 3 N010 5 5 NI temp=27 +C2 4 3 10f +M2 3 N005 4 4 PI temp=27 +C3 4 N005 10f Rser=5Meg noiseless +C11 3 5 10f +C12 N010 5 10f Rser=5Meg noiseless +D6 N010 5 DLIMN +A4 0 N004 0 0 0 0 N006 0 OTA g=1m linear en=4n*dnlim((120k/freq)**.342,1,.1)*dnlim((2Meg/freq)**.1,1,.1)*dnlim((freq/40Meg)**.35,1,.1) Vhigh=1e308 Vlow=-1e308 +C16 N008 3 .9p +G1 5 N010 N008 REF 100n +C7 4 1 225f +C17 0 N006 120f Rpar=1k noiseless +G4 0 N007 N006 0 1m +D14 4 N005 DLIMP +C4 2 1 100f +A6 N007 0 N009 REF REF REF N008 REF OTA g=2.5m asym isource=256u isink=-410u Rout=40k Vlow=-1e308 Vhigh=1e308 +D9 4 6 DSHUT +A5 REF N008 N013 REF REF REF N005 REF OTA g=100n ref=-150m linear Vlow=-1e308 Vhigh=1e308 +C14 4 5 20p Rpar=12.8k noiseless +S4 4 5 N013 REF SWP +C13 4 5 10p +A3 6 5 REF REF REF REF N013 REF SCHMITT vt=1.2 vh=.2 trise=900n tfall=800n +G2 0 REF 4 0 50m +G3 0 REF 5 0 50m +C19 REF 0 100p Rpar=10 noiseless +GESD1 2 4 2 4 1 vto=600m dir=1 +GESD2 5 2 5 2 1 vto=600m dir=1 +GESD3 1 4 1 4 1 vto=600m dir=1 +GESD4 5 1 5 1 1 vto=600m dir=1 +D1 3 4 DESD +D2 5 3 DESD +C1 4 2 225f +C5 1 5 225f +C6 2 5 225f +C8 0 N007 120f Rpar=1k noiseless +A2 1 REF 0 0 0 0 0 0 OTA g=0 in=1p*uplim((freq/20Meg)**.9,3,.2)*dnlim((freq/60Meg)**1.5,1,.2) +A7 N013 REF REF REF REF REF N009 REF BUF trise=100n +.model NI VDMOS(Vto=300m kp=100m lambda=.01) +.model PI VDMOS(Vto=-300m kp=100m lambda=.01 pchan is=0) +.model DSHUT D(Ron=1k Roff=1g Vfwd=.6 epsilon=100m ilimit=2u noiseless) +.model DIN D(Ron=300 Roff=100g Vfwd=.8 Vrev=.8 epsilon=100m revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.4 Vrev=340m epsilon=200m revepsilon=100m noiseless) +.model DLIMN D(Ron=1Meg Roff=100Meg Vfwd=800m Vrev=340m epsilon=200m revepsilon=100m noiseless) +.model SWP SW(Roff=1G Ron=500 vt=.5 vh=-.1 ilimit=5.6m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.ends LTC6268 +* +.subckt LTC6268-10 1 2 3 4 5 6 +A1 2 REF 0 0 0 0 0 0 OTA g=0 in=1p*uplim(freq/14.3Meg,12,.5) +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.4,.1), V(5)-.2, .1)+1n*V(1)-7.501009n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.39,.1), V(5)-.21, .1)+1n*V(2) +C10 N004 0 .1f Rpar=100K noiseless +M1 3 N010 5 5 NI temp=27 +C2 4 3 10f +M2 3 N005 4 4 PI temp=27 +C3 4 N005 10f Rser=5Meg noiseless +C11 3 5 10f +C12 N010 5 10f Rser=5Meg noiseless +D6 N010 5 DLIMN +A4 0 N004 0 0 0 0 N006 0 OTA g=1m linear en=4n*dnlim((50k/freq)**.31,1,.1)*dnlim((900k/freq)**.15,1,.1)*dnlim((freq/80Meg)**.22,1,.1) Vhigh=1e308 Vlow=-1e308 +C16 N008 3 80f +G1 5 N010 N008 REF 100n +C7 4 1 225f +C17 0 N006 120f Rpar=1k noiseless +G4 0 N007 N006 0 1m +D14 4 N005 DLIMP +C4 2 1 100f +A6 N007 0 N009 REF REF REF N008 REF OTA g=2.5m asym isource=85.7u isink=-127.4u Rout=40k Vlow=-1e308 Vhigh=1e308 +D9 4 6 DSHUT +A5 REF N008 N013 REF REF REF N005 REF OTA g=100n ref=-150m linear Vlow=-1e308 Vhigh=1e308 +C14 4 5 20p Rpar=12.8k noiseless +S4 4 5 N013 REF SWP +C13 4 5 10p +A3 6 5 REF REF REF REF N013 REF SCHMITT vt=1.2 vh=.2 trise=900n tfall=800n +G2 0 REF 4 0 50m +G3 0 REF 5 0 50m +C19 REF 0 100p Rpar=10 noiseless +GESD1 2 4 2 4 1 vto=600m dir=1 +GESD2 5 2 5 2 1 vto=600m dir=1 +GESD3 1 4 1 4 1 vto=600m dir=1 +GESD4 5 1 5 1 1 vto=600m dir=1 +D1 3 4 DESD +D2 5 3 DESD +C1 4 2 225f +C5 1 5 225f +C6 2 5 225f +C8 0 N007 120f Rpar=1k noiseless +A2 1 REF 0 0 0 0 0 0 OTA g=0 in=1p*uplim(freq/14.3Meg,12,.5) +A7 N013 REF REF REF REF REF N009 REF BUF trise=100n +.model NI VDMOS(Vto=300m kp=100m lambda=.01) +.model PI VDMOS(Vto=-300m kp=100m lambda=.01 pchan is=0) +.model DSHUT D(Ron=1k Roff=1g Vfwd=.6 epsilon=100m ilimit=2u noiseless) +.model DIN D(Ron=300 Roff=100g Vfwd=.8 Vrev=.8 epsilon=100m revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.4 Vrev=340m epsilon=200m revepsilon=100m noiseless) +.model DLIMN D(Ron=1Meg Roff=100Meg Vfwd=800m Vrev=340m epsilon=200m revepsilon=100m noiseless) +.model SWP SW(Roff=1G Ron=500 vt=.5 vh=-.1 ilimit=5.6m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.ends LTC6268-10 +* +.subckt LTC6363 1 2 3 4 5 6 7 8 +A5 N010 0 0 0 0 0 N011 0 OTA g=20m iout=412u cout=1f Vhigh=1e308 Vlow=-1e308 +D9 N011 0 DLIM +C7 3 8 .1p Rser=1k Rpar=1G noiseless +C13 3 6 10p +S1 N011 0 0 _SHDN SHUT +C17 6 7 500f +A2 7 Mid 0 0 0 0 _SHDN 0 SCHMITT trise=4u tfall=2u vt=.8 vh=.4 +D6 1 3 DESD +D7 6 1 DESD +D10 8 3 DESD +D11 6 8 DESD +A1 0 8 0 0 0 0 0 0 OTA g=0 in=550f ink=3.3k +A7 0 N010 0 0 0 0 N028 0 OTA g=20m iout=412u cout=1f Vhigh=1e308 Vlow=-1e308 +D13 N028 0 DLIM +S3 N028 0 0 _SHDN SHUT +A8 0 N027 0 0 0 0 N015 0 OTA g=10m linear en=14.3n enk=1.1k Rout=1k Cout=20p ref=0 Vlow=-1e308 Vhigh=1e308 +R5 3 2 3.6Meg noiseless +R6 2 6 3.6Meg noiseless +G6 0 N028 0 N015 250µ +G7 0 N011 0 N015 250µ +D14 N015 0 DCML +C1 1 8 2p Rser=500 Rpar=40k noiseless +C2 3 4 1p Rpar=100Meg noiseless +C8 4 6 1p Rpar=100Meg noiseless +C9 3 5 1p Rpar=100Meg noiseless +C11 5 6 1p Rpar=100Meg noiseless +R10 3 7 10Meg noiseless +S7 6 3 _SHDN 0 SPOWR1 +A10 0 1 0 0 0 0 0 0 OTA g=0 in=550f ink=3.3k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +B1 0 N006 I=10u*dnlim(uplim(V(8),V(3)-1.3,.1), V(6)-.3, .1)+1n*V(8) +B2 N006 0 I=10u*dnlim(uplim(V(1),V(3)-1.29,.1), V(6)-.31, .1)+1n*V(1) +C20 N006 0 1f Rpar=100K noiseless +C4 3 1 .1p Rser=1k Rpar=1G noiseless +C5 8 6 .1p Rser=1k Rpar=1G noiseless +C6 1 6 .1p Rser=1k Rpar=1G noiseless +B3 0 N027 I=10u*dnlim(uplim(V(2),V(3)-.4,.1), V(6)+.42, .1) +B4 N027 0 I=5u*(V(4)+V(5)) +C30 N027 0 .1f Rpar=100K noiseless +B7 3 1 I=(272n+25n*V(1,6))*(.5+.5*tanh((V(3,1)-500m)/200m))+ 25n/dnlim(V(1,6)+.06,.02,.01) +B8 3 8 I=(272n+25n*V(8,6))*(.5+.5*tanh((V(3,8)-500m)/200m))+ 25n/dnlim(V(8,6)+.06,.02,.01) +D21 3 7 DSPU +R4 3 Mid 10Meg noiseless +D22 3 6 DPOW +S8 6 3 _SHDN 0 SPOWR2 +A9 0 N007 0 0 0 0 N008 0 OTA g=1m linear Rout=1k Cout=3.25p vlow=-1e308 vhigh=1e308 +R9 Mid 6 10Meg noiseless +L1 N010 0 242µ Rser=10.68k Rpar=157.1k noiseless +G1 0 N010 N009 0 100µ +M1 N012 N005 3 3 PI temp=27 +M2 N019 N018 6 6 NI temp=27 +D2 3 N005 DLIMP +D3 N018 6 DLIMN +B5 6 N018 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6+460n*(V(XXP)+100m),300m/1e6,100n) +B6 N005 3 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6-460n*(V(XXP)-100m),300m/1e6,100n) +D5 3 N024 DLIMP +D8 N030 6 DLIMN +A3 0 N006 0 0 0 0 N007 0 OTA g=1m linear en=2.9n enk=4k Rout=1k Cout=300p Vlow=-60m Vhigh=60m epsilon=20m +G10 0 XXP N011 0 1µ +L3 XXP 0 134m Rser=1.095Meg Rpar=11.538Meg noiseless +G11 0 XXN N028 0 1µ +C3 3 N005 .1f Rser=10Meg noiseless +C10 N018 6 .1f Rser=10Meg noiseless +C12 3 N024 .1f Rser=10Meg noiseless +C15 N030 6 .1f Rser=10Meg noiseless +C24 N011 N016 9p +C16 N023 N028 9p +G3 0 N009 N008 0 10µ +L2 N009 0 397.8µ Rser=100k noiseless +G12 0 N016 4 Mid 100m +C14 N016 0 1p Rpar=10 noiseless +G13 0 N023 5 Mid 100m +C19 N023 0 1p Rpar=10 noiseless +R13 N012 4 3.333 noiseless +I1 4 N012 36m +R14 4 N019 3 noiseless +I2 N019 4 33m +M3 N026 N024 3 3 PI temp=27 +M4 N031 N030 6 6 NI temp=27 +R15 N026 5 3.333 noiseless +I3 5 N026 36m +R16 5 N031 3 noiseless +I4 N031 5 33m +L4 XXN 0 134m Rser=1.095Meg Rpar=11.538Meg noiseless +B12 N024 3 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6-460n*(V(XXN)-100m),300m/1e6,100n) +B9 6 N030 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6+460n*(V(XXN)+100m),300m/1e6,100n) +R17 4 5 2Meg noiseless +.model DPOW D(Ron=190k Roff=1G Vfwd=1 epsilon=1 noiseless) +.model SPOWR1 SW(level=2 Ron=200 Roff=1g vt=.5 vh=-.1 ilimit=1.13m noiseless) +.model SPOWR2 SW(Ron=49k Roff=1G vt=.5 vh=-.1 noiseless) +.model DSPU D(Ron=100k Roff=1g Vfwd=100m epsilon=100m ilimit=10u noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=24.8Meg Vfwd=3 Vrev=3 epsilon=100m revepsilon=100m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model SHUT SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=50m ksubthres=100m Mtriode=2 lambda=.0001 noiseless) +.model PI VDMOS(Vto=-300m Kp=50m ksubthres=100m Mtriode=2.2 lambda=.0001 pchan noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.ends LTC6363 +* +.subckt LTC6363-.5 1 2 3 4 5 6 7 8 +D9 N009 0 DLIM +C7 3 INP .1p Rser=1k Rpar=1G noiseless +C13 3 6 10p +S1 N009 0 0 _SHDN SHUT +C17 6 7 500f +A2 7 Mid 0 0 0 0 _SHDN 0 SCHMITT trise=4u tfall=2u vt=.8 vh=.4 +D6 INN 3 DESD +D7 6 INN DESD +D10 INP 3 DESD +D11 6 INP DESD +A1 0 INP 0 0 0 0 0 0 OTA g=0 in=550f ink=3.3k +D13 N025 0 DLIM +S3 N025 0 0 _SHDN SHUT +A8 0 N024 0 0 0 0 N013 0 OTA g=10m linear en=14.3n enk=1.1k Rout=1k Cout=20p ref=0 Vlow=-1e308 Vhigh=1e308 +R5 3 2 3.6Meg noiseless +R6 2 6 3.6Meg noiseless +G6 0 N025 0 N013 250µ +G7 0 N009 0 N013 250µ +D14 N013 0 DCML +C1 INN INP 2p Rser=1k Rpar=40k noiseless +R10 3 7 10Meg noiseless +S7 6 3 _SHDN 0 SPOWR1 +A10 0 INN 0 0 0 0 0 0 OTA g=0 in=550f ink=3.3k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +B1 0 N004 I=10u*dnlim(uplim(V(INP),V(3)-1.3,.1), V(6)-.3, .1)+1n*V(INP) +B2 N004 0 I=10u*dnlim(uplim(V(INN),V(3)-1.29,.1), V(6)-.31, .1)+1n*V(INN) +C20 N004 0 1f Rpar=100K noiseless +C4 3 INN .1p Rser=1k Rpar=1G noiseless +C5 INP 6 .1p Rser=1k Rpar=1G noiseless +C6 INN 6 .1p Rser=1k Rpar=1G noiseless +B3 0 N024 I=10u*dnlim(uplim(V(2),V(3)-.4,.1), V(6)+.42, .1) +B4 N024 0 I=5u*(V(4)+V(5)) +C30 N024 0 .1f Rpar=100K noiseless +B7 3 INN I=(272n+25n*V(INN,6))*(.5+.5*tanh((V(3,INN)-500m)/200m))+ 25n/dnlim(V(INN,6)+.06,.02,.01) +B8 3 INP I=(272n+25n*V(INP,6))*(.5+.5*tanh((V(3,INP)-500m)/200m))+ 25n/dnlim(V(INP,6)+.06,.02,.01) +D21 3 7 DSPU +R4 3 Mid 10Meg noiseless +D22 3 6 DPOW +S8 6 3 _SHDN 0 SPOWR2 +R9 Mid 6 10Meg noiseless +M1 N010 N003 3 3 PI temp=27 +M2 N016 N015 6 6 NI temp=27 +D2 3 N003 DLIMP +D3 N015 6 DLIMN +B5 6 N015 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6+460n*(V(XXP)+100m),300m/1e6,100n) +B6 N003 3 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6-460n*(V(XXP)-100m),300m/1e6,100n) +D5 3 N021 DLIMP +D8 N026 6 DLIMN +G10 0 XXP N009 0 1µ +G11 0 XXN N025 0 1µ +C3 3 N003 .1f Rser=10Meg noiseless +C10 N015 6 .1f Rser=10Meg noiseless +C12 3 N021 .1f Rser=10Meg noiseless +C15 N026 6 .1f Rser=10Meg noiseless +G12 0 N014 4 Mid 100m +C14 N014 0 1p Rpar=10 noiseless +G13 0 N020 5 Mid 100m +C19 N020 0 1p Rpar=10 noiseless +R13 N010 4 3.333 noiseless +I1 4 N010 36m +R14 4 N016 3 noiseless +I2 N016 4 33m +M3 N023 N021 3 3 PI temp=27 +M4 N027 N026 6 6 NI temp=27 +R15 N023 5 3.333 noiseless +I3 5 N023 36m +R16 5 N027 3 noiseless +I4 N027 5 33m +B12 N021 3 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6-460n*(V(XXN)-100m),300m/1e6,100n) +B9 6 N026 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6+460n*(V(XXN)+100m),300m/1e6,100n) +R17 4 5 2Meg noiseless +R1 INN 1 1.4K +R2 INP 8 1.4K +R3 4 INN 700 +R7 5 INP 700 +C18 1 6 4p Rser= 10 noiseless +C22 INN 6 6p Rser=10 noiseless +C2 3 4 2p Rpar=100Meg Rser=10 noiseless +G1 0 N007 N005 0 1m +C27 N007 0 800f Rpar=1k noiseless +G2 0 N008 N007 0 1m +C21 6 8 4p Rser= 10 noiseless +C23 6 INP 6p Rser=10 noiseless +C8 4 6 2p Rpar=100Meg Rser=10 noiseless +C9 3 5 4p Rpar=100Meg Rser=10 noiseless +C11 5 6 4p Rpar=100Meg Rser=10 noiseless +A3 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=2.9n enk=4k Rout=1k Cout=2p Vlow=-190m Vhigh=190m epsilon=20m +C25 N008 0 7.96p Rpar=1k Rser=4k noiseless +A4 N008 0 0 0 0 0 N009 0 OTA g=20m iout=4.6m cout=1f Vhigh=1e308 Vlow=-1e308 +A5 0 N008 0 0 0 0 N025 0 OTA g=20m iout=4.6m cout=1f Vhigh=1e308 Vlow=-1e308 +L1 XXP 0 .707 Rser=1.11Meg Rpar=10Meg +L2 XXN 0 .707 Rser=1.11Meg Rpar=10Meg +C16 N009 N014 130p Rser=15 noiseless +C24 N020 N025 130p Rser=15 noiseless +.model DPOW D(Ron=190k Roff=1G Vfwd=1 epsilon=1 noiseless) +.model SPOWR1 SW(level=2 Ron=200 Roff=1g vt=.5 vh=-.1 ilimit=1.13m noiseless) +.model SPOWR2 SW(Ron=49k Roff=1G vt=.5 vh=-.1 noiseless) +.model DSPU D(Ron=100k Roff=1g Vfwd=100m epsilon=100m ilimit=10u noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=24.8Meg Vfwd=3 Vrev=3 epsilon=100m revepsilon=100m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model SHUT SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=50m ksubthres=100m Mtriode=2 lambda=.0001 noiseless) +.model PI VDMOS(Vto=-300m Kp=50m ksubthres=100m Mtriode=2.2 lambda=.0001 pchan noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.ends LTC6363-.5 +* +.subckt LTC6363-1 1 2 3 4 5 6 7 8 +D9 N009 0 DLIM +C7 3 INP .1p Rser=1k Rpar=1G noiseless +C13 3 6 10p +S1 N009 0 0 _SHDN SHUT +C17 6 7 500f +A2 7 Mid 0 0 0 0 _SHDN 0 SCHMITT trise=4u tfall=2u vt=.8 vh=.4 +D6 INN 3 DESD +D7 6 INN DESD +D10 INP 3 DESD +D11 6 INP DESD +A1 0 INP 0 0 0 0 0 0 OTA g=0 in=550f ink=3.3k +D13 N025 0 DLIM +S3 N025 0 0 _SHDN SHUT +A8 0 N024 0 0 0 0 N013 0 OTA g=10m linear en=14.3n enk=1.1k Rout=1k Cout=20p ref=0 Vlow=-1e308 Vhigh=1e308 +R5 3 2 3.6Meg noiseless +R6 2 6 3.6Meg noiseless +G6 0 N025 0 N013 250µ +G7 0 N009 0 N013 250µ +D14 N013 0 DCML +C1 INN INP 2p Rser=1k Rpar=40k noiseless +R10 3 7 10Meg noiseless +S7 6 3 _SHDN 0 SPOWR1 +A10 0 INN 0 0 0 0 0 0 OTA g=0 in=550f ink=3.3k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +B1 0 N004 I=10u*dnlim(uplim(V(INP),V(3)-1.3,.1), V(6)-.3, .1)+1n*V(INP) +B2 N004 0 I=10u*dnlim(uplim(V(INN),V(3)-1.29,.1), V(6)-.31, .1)+1n*V(INN) +C20 N004 0 1f Rpar=100K noiseless +C4 3 INN .1p Rser=1k Rpar=1G noiseless +C5 INP 6 .1p Rser=1k Rpar=1G noiseless +C6 INN 6 .1p Rser=1k Rpar=1G noiseless +B3 0 N024 I=10u*dnlim(uplim(V(2),V(3)-.4,.1), V(6)+.42, .1) +B4 N024 0 I=5u*(V(4)+V(5)) +C30 N024 0 .1f Rpar=100K noiseless +B7 3 INN I=(272n+25n*V(INN,6))*(.5+.5*tanh((V(3,INN)-500m)/200m))+ 25n/dnlim(V(INN,6)+.06,.02,.01) +B8 3 INP I=(272n+25n*V(INP,6))*(.5+.5*tanh((V(3,INP)-500m)/200m))+ 25n/dnlim(V(INP,6)+.06,.02,.01) +D21 3 7 DSPU +R4 3 Mid 10Meg noiseless +D22 3 6 DPOW +S8 6 3 _SHDN 0 SPOWR2 +R9 Mid 6 10Meg noiseless +M1 N010 N003 3 3 PI temp=27 +M2 N016 N015 6 6 NI temp=27 +D2 3 N003 DLIMP +D3 N015 6 DLIMN +B5 6 N015 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6+460n*(V(XXP)+100m),300m/1e6,100n) +B6 N003 3 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6-460n*(V(XXP)-100m),300m/1e6,100n) +D5 3 N021 DLIMP +D8 N026 6 DLIMN +G10 0 XXP N009 0 1µ +G11 0 XXN N025 0 1µ +C3 3 N003 .1f Rser=10Meg noiseless +C10 N015 6 .1f Rser=10Meg noiseless +C12 3 N021 .1f Rser=10Meg noiseless +C15 N026 6 .1f Rser=10Meg noiseless +G12 0 N014 4 Mid 100m +C14 N014 0 1p Rpar=10 noiseless +G13 0 N020 5 Mid 100m +C19 N020 0 1p Rpar=10 noiseless +R13 N010 4 3.333 noiseless +I1 4 N010 36m +R14 4 N016 3 noiseless +I2 N016 4 33m +M3 N023 N021 3 3 PI temp=27 +M4 N027 N026 6 6 NI temp=27 +R15 N023 5 3.333 noiseless +I3 5 N023 36m +R16 5 N027 3 noiseless +I4 N027 5 33m +B12 N021 3 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6-460n*(V(XXN)-100m),300m/1e6,100n) +B9 6 N026 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6+460n*(V(XXN)+100m),300m/1e6,100n) +R17 4 5 2Meg noiseless +R1 INN 1 1050 +R2 INP 8 1050 +R3 4 INN 1050 +R7 5 INP 1050 +C18 1 6 3p Rser= 10 noiseless +C22 INN 6 6p Rser=10 noiseless +C2 3 4 4p Rpar=100Meg Rser=10 noiseless +A3 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=2.9n enk=4k Rout=1k Cout=2p Vlow=-170m Vhigh=170m epsilon=20m +G1 0 N007 N005 0 1m +C27 N007 0 800f Rpar=1k noiseless +C28 N008 0 21.2p Rpar=1k Rser=1.5k noiseless +G2 0 N008 N007 0 1m +A4 N008 0 0 0 0 0 N009 0 OTA g=20m iout=3.1m cout=1f Vhigh=1e308 Vlow=-1e308 +A5 0 N008 0 0 0 0 N025 0 OTA g=20m iout=3.1m cout=1f Vhigh=1e308 Vlow=-1e308 +L1 XXP 0 .694 Rser=1.09Meg Rpar=12Meg noiseless +L2 XXN 0 .694 Rser=1.09Meg Rpar=12Meg noiseless +C21 6 8 3p Rser= 10 noiseless +C23 6 INP 6p Rser=10 noiseless +C8 4 6 4p Rpar=100Meg Rser=10 noiseless +C9 3 5 4p Rpar=100Meg Rser=10 noiseless +C11 5 6 4p Rpar=100Meg Rser=10 noiseless +C24 N009 N014 100p Rser=15 noiseless +C16 N020 N025 100p Rser=15 noiseless +.model DPOW D(Ron=190k Roff=1G Vfwd=1 epsilon=1 noiseless) +.model SPOWR1 SW(level=2 Ron=200 Roff=1g vt=.5 vh=-.1 ilimit=1.13m noiseless) +.model SPOWR2 SW(Ron=49k Roff=1G vt=.5 vh=-.1 noiseless) +.model DSPU D(Ron=100k Roff=1g Vfwd=100m epsilon=100m ilimit=10u noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=24.8Meg Vfwd=3 Vrev=3 epsilon=100m revepsilon=100m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model SHUT SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=50m ksubthres=100m Mtriode=2 lambda=.0001 noiseless) +.model PI VDMOS(Vto=-300m Kp=50m ksubthres=100m Mtriode=2.2 lambda=.0001 pchan noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.ends LTC6363-1 +* +.subckt LTC6363-2 1 2 3 4 5 6 7 8 +D9 N009 0 DLIM +C7 3 INP .1p Rser=1k Rpar=1G noiseless +C13 3 6 10p +S1 N009 0 0 _SHDN SHUT +C17 6 7 500f +A2 7 Mid 0 0 0 0 _SHDN 0 SCHMITT trise=4u tfall=2u vt=.8 vh=.4 +D6 INN 3 DESD +D7 6 INN DESD +D10 INP 3 DESD +D11 6 INP DESD +A1 0 INP 0 0 0 0 0 0 OTA g=0 in=550f ink=3.3k +D13 N025 0 DLIM +S3 N025 0 0 _SHDN SHUT +A8 0 N024 0 0 0 0 N013 0 OTA g=10m linear en=14.3n enk=1.1k Rout=1k Cout=20p ref=0 Vlow=-1e308 Vhigh=1e308 +R5 3 2 3.6Meg noiseless +R6 2 6 3.6Meg noiseless +G6 0 N025 0 N013 250µ +G7 0 N009 0 N013 250µ +D14 N013 0 DCML +C1 INN INP 2p Rser=1k Rpar=40k noiseless +R10 3 7 10Meg noiseless +S7 6 3 _SHDN 0 SPOWR1 +A10 0 INN 0 0 0 0 0 0 OTA g=0 in=550f ink=3.3k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +B1 0 N004 I=10u*dnlim(uplim(V(INP),V(3)-1.3,.1), V(6)-.3, .1)+1n*V(INP) +B2 N004 0 I=10u*dnlim(uplim(V(INN),V(3)-1.29,.1), V(6)-.31, .1)+1n*V(INN) +C20 N004 0 1f Rpar=100K noiseless +C4 3 INN .1p Rser=1k Rpar=1G noiseless +C5 INP 6 .1p Rser=1k Rpar=1G noiseless +C6 INN 6 .1p Rser=1k Rpar=1G noiseless +B3 0 N024 I=10u*dnlim(uplim(V(2),V(3)-.4,.1), V(6)+.42, .1) +B4 N024 0 I=5u*(V(4)+V(5)) +C30 N024 0 .1f Rpar=100K noiseless +B7 3 INN I=(272n+25n*V(INN,6))*(.5+.5*tanh((V(3,INN)-500m)/200m))+ 25n/dnlim(V(INN,6)+.06,.02,.01) +B8 3 INP I=(272n+25n*V(INP,6))*(.5+.5*tanh((V(3,INP)-500m)/200m))+ 25n/dnlim(V(INP,6)+.06,.02,.01) +D21 3 7 DSPU +R4 3 Mid 10Meg noiseless +D22 3 6 DPOW +S8 6 3 _SHDN 0 SPOWR2 +R9 Mid 6 10Meg noiseless +M1 N010 N003 3 3 PI temp=27 +M2 N016 N015 6 6 NI temp=27 +D2 3 N003 DLIMP +D3 N015 6 DLIMN +B5 6 N015 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6+460n*(V(XXP)+100m),300m/1e6,100n) +B6 N003 3 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6-460n*(V(XXP)-100m),300m/1e6,100n) +D5 3 N021 DLIMP +D8 N026 6 DLIMN +G10 0 XXP N009 0 1µ +G11 0 XXN N025 0 1µ +C3 3 N003 .1f Rser=10Meg noiseless +C10 N015 6 .1f Rser=10Meg noiseless +C12 3 N021 .1f Rser=10Meg noiseless +C15 N026 6 .1f Rser=10Meg noiseless +G12 0 N014 4 Mid 100m +C14 N014 0 1p Rpar=10 noiseless +G13 0 N020 5 Mid 100m +C19 N020 0 1p Rpar=10 noiseless +R13 N010 4 3.333 noiseless +I1 4 N010 36m +R14 4 N016 3 noiseless +I2 N016 4 33m +M3 N023 N021 3 3 PI temp=27 +M4 N027 N026 6 6 NI temp=27 +R15 N023 5 3.333 noiseless +I3 5 N023 36m +R16 5 N027 3 noiseless +I4 N027 5 33m +B12 N021 3 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6-460n*(V(XXN)-100m),300m/1e6,100n) +B9 6 N026 I=(.5+.5*tanh((V(_SHDN)-500m)/200m))*dnlim(300m/1e6+460n*(V(XXN)+100m),300m/1e6,100n) +R17 4 5 2Meg noiseless +R1 INN 1 700 +R2 INP 8 700 +R3 4 INN 1.4K +R7 5 INP 1.4K +C18 1 6 2p Rser= 10 noiseless +C22 INN 6 7.9p Rser=10 noiseless +C2 3 4 4p Rpar=100Meg Rser=10 noiseless +G1 0 N007 N005 0 1m +C27 N007 0 800f Rpar=1k noiseless +C28 N008 0 21.2p Rpar=1k Rser=1.5k noiseless +G2 0 N008 N007 0 1m +C21 6 8 2p Rser= 10 noiseless +C23 6 INP 7.9p Rser=10 noiseless +C8 4 6 4p Rpar=100Meg Rser=10 noiseless +C9 3 5 4p Rpar=100Meg Rser=10 noiseless +C11 5 6 4p Rpar=100Meg Rser=10 noiseless +A3 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=2.9n enk=4k Rout=1k Cout=6p Vlow=-230m Vhigh=230m epsilon=20m +L1 XXP 0 1.15 Rser=1.08Meg Rpar=13.3Meg +L2 XXN 0 1.15 Rser=1.08Meg Rpar=13.3Meg +C16 N009 N014 138p Rser=15 noiseless +C24 N020 N025 138p Rser=15 noiseless +A4 N008 0 0 0 0 0 N009 0 OTA g=20m iout=4.2m cout=1f Vhigh=1e308 Vlow=-1e308 +A5 0 N008 0 0 0 0 N025 0 OTA g=20m iout=4.2m cout=1f Vhigh=1e308 Vlow=-1e308 +.model DPOW D(Ron=190k Roff=1G Vfwd=1 epsilon=1 noiseless) +.model SPOWR1 SW(level=2 Ron=200 Roff=1g vt=.5 vh=-.1 ilimit=1.13m noiseless) +.model SPOWR2 SW(Ron=49k Roff=1G vt=.5 vh=-.1 noiseless) +.model DSPU D(Ron=100k Roff=1g Vfwd=100m epsilon=100m ilimit=10u noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=24.8Meg Vfwd=3 Vrev=3 epsilon=100m revepsilon=100m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model SHUT SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=50m ksubthres=100m Mtriode=2 lambda=.0001 noiseless) +.model PI VDMOS(Vto=-300m Kp=50m ksubthres=100m Mtriode=2.2 lambda=.0001 pchan noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.ends LTC6363-2 +* +.subckt LTC2058 1 2 3 4 5 6 7 +A3 N010 N020 0 0 0 0 N019 0 SCHMITT Vt=1.3 Vh=0 trise=20u tfall=20u +C2 6 5 10p +S2 6 4 ON 0 SPOW2 +R6 N010 1 10K noiseless +R8 N020 7 10K noiseless +A1 6 4 0 0 0 0 N012 0 SCHMITT Vt=4.75 Vh=50m tau=50u +A6 N012 0 0 0 N019 0 ON 0 AND trise=1u tfall=1u +C7 4 N010 100f +C8 4 N020 100f Rpar=100Meg noiseless +D8 4 1 DESDL +D9 4 7 DESDL +D10 1 6 DESDL +D11 7 6 DESDL +D12 2 3 DIN +S5 6 4 ON 0 SPOW1 +C16 4 1 100f +C17 4 7 100f +C6 6 2 4p Rser=500 noiseless +D16 6 4 DPOW +C18 6 4 100p +D1 3 6 DESDH +D3 4 3 DESDH +D4 2 6 DESDH +D7 4 2 DESDH +S10 0 VInoi 6 4 Snoise +D19 6 N010 DP5U +D20 N020 4 DP75U +G2 0 N018 5 Mid 100m +R2 N018 0 10 noiseless +C10 N003 N018 3p Rser=10 noiseless +C11 N011 N018 50p Rser=18k noiseless +M1 5 PG 6 6 Pout temp=27 +M2 5 NG 4 4 Nout temp=27 +A4 0 N009 6 6 6 6 PG 6 OTA g=200n linear ref=-700m vlow=-5 vhigh=0 +A5 0 N015 4 4 4 4 NG 4 OTA g=200n linear ref=700m vlow=0 vhigh=5 +G1 0 N013 N004 0 1m +L1 N004 0 9.28m Rser=1.75K Rpar=2.33K noiseless +G4 0 N004 N003 0 192.3µ +C22 N003 0 1p Rser=400k noiseless +R12 6 PG 10Meg noiseless +C12 PG 5 .1f +C14 5 NG .1f +C19 N011 0 1p Rser=600Meg noiseless +A8 On 0 N013 N013 N013 N013 N015 N013 SCHMITT vt=.5 vh=0 trise=100n vlow=-5 vhigh=0 +A9 On 0 N013 N013 N013 N009 N013 N013 SCHMITT vt=.5 vh=0 trise=100n vlow=0 vhigh=5 +D2 N011 0 DLIMINT1 +R3 6 Mid 7.2Meg noiseless +R14 Mid 4 7.2Meg noiseless +G5 0 N003 N011 0 3.74µ +D5 N003 0 DLIMINT2 +S1 6 5 On 0 SoutLd1 +S3 5 4 On 0 SoutLd2 +C13 5 4 10p +D6 6 2 Dbias1 +D13 3 4 Dbias1 +D15 3 4 Dbias2 +D14 2 4 Dbias2 +C9 2 4 4p Rser=500 noiseless +C1 6 3 4p Rser=500 noiseless +C4 3 4 4p Rser=500 noiseless +C15 2 3 10p Rser=500 noiseless +C20 6 N010 100f Rpar=100Meg noiseless +D17 N020 N010 DZ +C21 N010 N020 100f +B1 0 N007 I=10u*dnlim(uplim(V(3),V(6)-1.4,.1), V(4)-0.3, .1)+1n*V(3) + 52.28f +B2 N007 0 I=10u*dnlim(uplim(V(2),V(6)-1.41,.1), V(4)-0.31, .1)+1n*V(2) +R4 NG 4 10Meg noiseless +C23 N007 0 1f Rpar=100k noiseless +GInoi 2 3 N006 0 1µ +C3 N006 0 4p Rpar=1Meg noiseless +G3 0 N006 VInoi 0 1µ +L2 N013 0 9.28m Rser=1.75K Rpar=2.33K noiseless +A2 0 N007 0 0 0 0 N008 0 OTA g=1u linear en= 9n*(1+(freq/35k)**2)*(1+(freq/75k)**2.3)/((1+(freq/50k)**4)) Rout=1Meg Cout=20f Vlow=-1e308 Vhigh=1e308 +A7 N008 0 On 0 0 0 N011 0 OTA g=800u asym isrc=87u isink=-82u vlow=-1e308 vhigh=1e308 +.model SPOW1 SW(level=2 Ron=500 Roff=1G vt=.5 vh=-.1 ilimit=518.05u noiseless) +.model SPOW2 SW(level=2 Ron=335K Roff=1G vt=.5 vh=-.1 noiseless) +.model DPOW D(Ron=10k Roff=1G vfwd=2 epsilon=500m ilimit=2.16u noiseless) +.model DP5U D(Ron=1k Roff=100Meg vfwd=100m epsilon=100m ilimit=.5u noiseless) +.model DP75U D(Ron=1k Roff=100Meg vfwd=100m epsilon=100m ilimit=.75u noiseless) +.model DZ D(Ron=100 Roff=1G vfwd=700m epsilon=500m vrev=5.15 revepsilon=100m noiseless) +.model Snoise SW(level=2 ron=2.5Meg Roff=180Meg vt=25 vh=-20) +.model DESDH D(Ron=100 Roff=500T vfwd=700m epsilon=700m noiseless) +.model DESDL D(Ron=100 Roff=1G vfwd=700m epsilon=700m noiseless) +.model DLIMINT1 D(Ron=100 Roff=100Meg vfwd=2.4 vrev=1.8 epsilon=20m revepsilon=20m noiseless) +.model DLIMINT2 D(Ron=100 Roff=100Meg vfwd=9.5 vrev=9.5 epsilon=20m revepsilon=20m noiseless) +.param CL = 1f +.model SoutLd1 SW(level=2 Ron=1k Roff=10G vt=.5 vh=100m ilimit=100u noiseless) +.model SoutLd2 SW(level=2 Ron=1k Roff=10G vt=.5 vh=100m ilimit=125u noiseless) +.model Dbias1 D(Ron=1Meg Roff=1T vfwd=0 epsilon=100m ilimit=30p noiseless) +.model Dbias2 D(Ron=10G Roff=1T vfwd=22 epsilon=2 ilimit=60p noiseless) +.model DIN D(Ron=500 Roff=225k vfwd=700m vrev=700m epsilon=500m revepsilon=500m noiseless) +.model Pout VDMOS(Vto=-1 Kp=3m mtriode=1.9 lambda=1m ksubthres=.1 Rb=10 pchan noiseless) +.model Nout VDMOS(Vto=1 Kp=5m lambda=1m ksubthres=.1 Rb=10 noiseless) +.ends LTC2058 +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +.subckt LT6372-1 1 2 3 4 5 6 7 8 9 10 11 12 13 +G2 0 N002 N003 0 1m +C3 N002 0 27p Rpar=1k noiseless +C5 7 2 7.95p +C6 7 1 .1p +R1 A1out INNF 10k +CG4 7 6 1p +CG5 6 4 1p +M3 7 N002 A1out A1out NINT temp=27 +M4 4 N002 A1out A1out PINT temp=27 +M5 7 N017 A2out A2out NINT temp=27 +M6 4 N017 A2out A2out PINT temp=27 +G3 0 N017 N016 0 1m +C17 N017 0 27p Rpar=1k noiseless +C20 2 3 .9p +DB2 7 4 DP +C4 7 N003 180p Rpar=200Meg noiseless +A1 9 2X 0 0 0 0 N003 0 OTA g=30m iout=5m en=4.9n enk=2.5 Vhigh=1e308 Vlow=-1e308 +G4 N003 0 N003 7 100m vto=-600m dir=1 +G6 0 N003 4 N003 100m vto=-600m dir=1 +A2 10 3X 0 0 0 0 N016 0 OTA g=30m iout=5m en=4.9n enk=2.5 Vhigh=1e308 Vlow=-1e308 +D11 1 7 DESD +D12 4 1 DESD +D13 8 7 DESD +D14 4 8 DESD +C13 N003 4 180p Rpar=200Meg noiseless +C15 7 N016 180p Rpar=200Meg noiseless +C16 N016 4 180p Rpar=200Meg noiseless +C8 INNF INPF 100f +M1 N006 PG 7 7 PI temp=27 +M2 6 NG 4 4 NI temp=27 +D1 7 PG DLIMP +D2 NG 4 DLIMN +C10 7 PG 1f Rser=400k noiseless +C14 NG 4 1f Rser=400k noiseless +B5 4 NG I=dnlim(400n+.7u*(V(XC)+240m),400n,200n) +B6 PG 7 I=dnlim(400n-.7u*(V(XC)-240m),400n,200n) +R8 N006 6 1 noiseless +I1 6 N006 800m +R9 7 Mid 1Meg noiseless +B7 0 N010 I=10u*dnlim(uplim(V(INPF),V(7)-1.59,.1), V(4)-.2, .1)+1n*V(INPF)-31.5p +B8 N010 0 I=10u*dnlim(uplim(V(INNF),V(7)-1.60,.1), V(4)-.21, .1)+1n*V(INNF) +C18 N010 0 .1f Rpar=100K noiseless +C19 XC N011 10p +C21 XC 0 1p +D3 XC 0 DANTISAT +C22 N009 0 8p Rpar=1k noiseless +G5 0 N009 N008 0 1m +C26 N008 0 8p Rpar=1k noiseless +R11 N011 0 1 noiseless +G11 0 N011 6 Mid 1 +A6 0 N009 0 0 0 0 XC 0 OTA g=250u iout=125u vlow=-1e308 vhigh=1e308 +C25 7 A1out 100f +C27 A1out 4 100f +C28 7 A2out 100f +C29 A2out 4 100f +G1 0 N016 4 N016 100m vto=-600m dir=1 +G7 N016 0 N016 7 100m vto=-600m dir=1 +R10 Mid 4 1Meg noiseless +A7 N010 0 0 0 0 0 N008 0 OTA g=1m linear en=26n enk=1.1 vlow=-1e308 vhigh=1e308 +C1 2 4 7.95p +C2 7 3 7.95p +C7 3 4 7.95p +A3 2 0 0 0 0 0 0 0 OTA g=0 in=93.4f ink=3 +A8 3 0 0 0 0 0 0 0 OTA g=0 in=93.4f ink=3 +A9 2 3 0 0 0 0 0 0 OTA g=0 incm=176.8f incmk=1.8 +R13 A1out 1 12.1k +A10 N005 0 4 4 4 4 9 4 OTA g=200u iout=300u vlow=-1e309 vhigh=1e309 +L3 N005 0 102.3µ Rser=4.5k Rpar=1.286k noiseless +C9 1 4 .1p +C11 7 8 .1p +C12 8 4 .1p +D4 2 7 DESD +D5 4 2 DESD +G9 0 N005 9 2X 1m +R14 2X 0 1k noiseless +I3 0 2X 600µ +R15 A2out 8 12.1k +A11 N013 0 4 4 4 4 10 4 OTA g=200u iout=300u vlow=-1e309 vhigh=1e309 +L1 N013 0 102.3µ Rser=4.5k Rpar=1.286k noiseless +I4 0 3X 600µ +G15 0 N013 10 3X 1m +B9 0 2X I=999.9u*dnlim(uplim(V(2),V(7)-1.25,.1), V(4)+1.7, .1)+100n*V(2) +B10 0 3X I=999.9u*dnlim(uplim(V(3),V(7)-1.25,.1), V(4)+1.7, .1)+100n*V(3) +D6 4 5 DESD +R6 3X 0 1k noiseless +R2 INNF 6 10k +R3 A2out INPF 10k +R4 INPF 5 20k +D7 3 7 DESD +D8 4 3 DESD +D9 9 7 DESD +D10 4 9 DESD +C23 7 9 .1p +C24 9 4 .1p +D17 10 7 DESD +D18 4 10 DESD +C32 7 10 .1p +C33 10 4 .1p +D16 4 11 DESD +R7 INPF 11 20k +C30 CactH 0 1p Rpar=3k noiseless +G8 0 CactH 6 12 1m +S1 CactH 0 12 7 SCLMPOH +S2 0 CactH 4 12 SCLMPOL +S3 4 6 CactH 0 SCLMP1 +S4 0 XC CactH 0 SCLMP2 +C31 CactL 0 1p Rpar=3k noiseless +S5 CactL 0 13 7 SCLMPOH +S6 0 CactL 4 13 SCLMPOL +G10 0 CactL 13 6 1m +S7 6 7 CactL 0 SCLMP1 +S8 0 XC CactL 0 SCLMP2 +M7 4 PG 7 7 PI temp=27 M=.4 +D15 INNF INPF DSI temp=27 +D19 INPF INNF DSI temp=27 +R16 7 12 1G +R17 7 13 1G +R18 12 4 1G +R19 13 4 1G +.model DP D(Ron=100 Roff=1G Vfwd=.6 epsilon=500m ilimit=1.15m noiseless) +.model NINT VDMOS(Vto=-40m Kp=100m noiseless) +.model PINT VDMOS(Vto=40m Kp=100m pchan noiseless) +.model DESD D(Ron=100 Roff=400G vfwd=600m epsilon=500m noiseless) +.model PI VDMOS(Vto=-300m kp=30m mtriode=.3 ksubthres=10m lambda=5e-4 pchan noiseless) +.model NI VDMOS(Vto=300m kp=25m mtriode=.4 ksubthres=10m lambda=5e-4 noiseless) +.model DANTISAT D(Ron=100 Roff=25.5Meg vfwd=3 epsilon=100m vrev=3 revepsilon=100m noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=2.3 epsilon=100m noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=2 epsilon=100m noiseless) +.model DSI D(Is=1e-16 TT=200n noiseless) +.param RG= 100T +.model SCLMPOH SW(Ron=1 Roff=3k vt=-1.8 vh=-200m noiseless) +.model SCLMPOL SW(Ron=1 Roff=3k vt=-1.3 vh=-200m noiseless) +.model SCLMP1 SW(level=2 Ron=100 Roff=100Meg vt=455m vh=-10m noiseless) +.model SCLMP2 SW(level=2 Ron=1 Roff=300Meg vt=450m vh=-10m noiseless) +.ends LT6372-1 + diff --git a/spice/copy/sub/LTC2311-12.sub b/spice/copy/sub/LTC2311-12.sub new file mode 100755 index 0000000..818e5cd Binary files /dev/null and b/spice/copy/sub/LTC2311-12.sub differ diff --git a/spice/copy/sub/LTC2311-14.sub b/spice/copy/sub/LTC2311-14.sub new file mode 100755 index 0000000..2882a30 Binary files /dev/null and b/spice/copy/sub/LTC2311-14.sub differ diff --git a/spice/copy/sub/LTC2311-16.sub b/spice/copy/sub/LTC2311-16.sub new file mode 100755 index 0000000..58cf7f9 Binary files /dev/null and b/spice/copy/sub/LTC2311-16.sub differ diff --git a/spice/copy/sub/LTC2323-12.sub b/spice/copy/sub/LTC2323-12.sub new file mode 100755 index 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0000000..6b208de --- /dev/null +++ b/spice/copy/sub/LTC2862-1.lib @@ -0,0 +1,193 @@ +* Copyright (c) Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005. All rights reserved. +* +.subckt LTC2862-1 1 2 3 4 5 6 7 8 9 10 11 12 +MZPDRV 10 N002 N004 N004 PDRV +MZNDRV N007 N006 N009 N009 NDRV +G1 0 vrefGR 12 6 1m +C1 vrefGR 0 100f Rpar=500 +C2 N005 0 550f Rpar=1g +S1 VCCGR N005 N003 0 SDIN +S2 N005 0 0 N003 SDIN +D1 N005 vrefGR DCLP +S3 12 N002 N005 vrefGRH SDPU +S4 N002 6 vrefGRL N005 SDPD +G3 0 VCCGR 12 6 10m +C4 VCCGR 0 100f Rpar=100 +C7 N010 0 550f Rpar=1g +S9 VCCGR N010 N003 0 SDIN +S10 N010 0 0 N003 SDIN +D3 N010 vrefGR DCLN +S11 12 N006 N010 vrefGRH SDNU +S12 N006 6 vrefGRL N010 SDND +C8 N006 6 1p Rpar=1Meg +C6 12 10 1p Rpar=100meg +C5 10 6 1p Rpar=100meg +C17 N002 10 200f +C18 N007 N006 200f +C3 12 N002 1p Rpar=1Meg +G5 6 N002 VIlimUZ IlimUPZ 100m vto=0 dir=1 +I1 0 IlimUPZ 15µ +S19 IlimUPZ 0 12 10 SIout +G12 0 VIlimDZ N009 6 3.8m +C31 VIlimDZ 0 100f Rpar=10k +I2 0 IlimDNZ 15µ +S22 IlimDNZ 0 10 6 SIout +G13 N006 12 VIlimDZ IlimDNZ 100m vto=0 dir=1 +C9 N007 6 1p Rpar=10Meg +C11 N009 6 1p Rpar=2.6 +C12 IlimUPZ 0 10p +C13 IlimDNZ 0 10p +G4 0 VIlimUZ 12 N004 1m +C14 VIlimUZ 0 100f Rpar=10k +S6 12 N006 SPDZ 0 SPullDwn +D2 12 N004 D1way +S5 12 N004 SRONZ 0 SREV +A3 3 vref 0 0 0 0 DEF 0 SCHMITT vt=0 vh=50m trise=10n +S7 6 N006 _DE 0 Soff +S8 N002 12 _DE 0 Soff +G14 0 SRONZ 12 10 20µ +C10 SRONZ 0 100f Rpar=2Meg +I3 0 SRONZ 6µ +S13 0 SRONZ 0 DE Soff2 +D4 SRONZ 0 DLSR +G15 0 SPDZ 10 12 1µ +C15 SPDZ 0 100f Rpar=2Meg +I4 SPDZ 0 4µ +S14 0 SPDZ 0 DE Soff2 +D6 SPDZ 0 DLSR +G16 0 N003 4 vref 1µ +C32 N003 0 1f Rpar=1Meg +C34 12 N004 1p +G17 0 vref 12 0 1m +C19 vref 0 100f Rpar=500 +G18 0 vref 6 0 1m +MZPDRV1 11 N014 N015 N015 PDRV +MZNDRV1 N018 N017 N019 N019 NDRV +C23 N016 0 550f Rpar=1g +S16 VCCGR N016 0 N003 SDIN +S21 N016 0 N003 0 SDIN +D8 N016 vrefGR DCLP +S25 12 N014 N016 vrefGRH SDPU +S26 N014 6 vrefGRL N016 SDPD +C37 N023 0 550f Rpar=1g +S27 VCCGR N023 0 N003 SDIN +S28 N023 0 N003 0 SDIN +D14 N023 vrefGR DCLN +S29 12 N017 N023 vrefGRH SDNU +S30 N017 6 vrefGRL N023 SDND +C38 N017 6 1p Rpar=1Meg +C39 12 11 1p Rpar=100meg +C40 11 6 1p Rpar=100meg +C41 N014 11 200f +C42 N018 N017 200f +C44 12 N014 1p Rpar=1Meg +G20 6 N014 VIlimUY IlimUPY 100m vto=0 dir=1 +I5 0 IlimUPY 15µ +S36 IlimUPY 0 12 11 SIout +G21 0 VIlimDY N019 6 3.8m +I6 0 IlimDNY 15µ +S37 IlimDNY 0 11 6 SIout +G22 N017 12 VIlimDY IlimDNY 100m vto=0 dir=1 +C54 N019 6 1p Rpar=2.6 +C55 IlimUPY 0 10p +C56 IlimDNY 0 10p +G23 0 VIlimUY 12 N015 1m +S38 12 N017 SPDY 0 SPullDwn +D22 12 N015 D1way +S39 12 N015 SRONY 0 SREV +S40 6 N017 _DE 0 Soff +S41 N014 12 _DE 0 Soff +G24 0 SRONY 12 11 20µ +C58 SRONY 0 100f Rpar=2Meg +I7 0 SRONY 6µ +S42 0 SRONY 0 DE Soff2 +D23 SRONY 0 DLSR +G25 0 SPDY 11 12 1µ +C59 SPDY 0 100f Rpar=2Meg +I8 SPDY 0 4µ +S43 0 SPDY 0 DE Soff2 +D24 SPDY 0 DLSR +C61 12 N015 1p +D5 10 N007 DNout +D15 11 N018 DNout +C45 N018 6 1p Rpar=10Meg +C49 10 N007 .5p +C53 11 N018 .5p +C63 N004 10 1p +C64 N007 N009 1p +C65 N015 11 1p +C66 N018 N019 1p +A9 _DE 0 vrefGR vrefGR vrefGR vrefGR vrefGRH vrefGR SCHMITT vt=.5 trise=5n vlow=0 vhigh=10 +A10 0 _DE vrefGR vrefGR vrefGR vrefGR vrefGRL vrefGR SCHMITT vt=-.5 trise=5n vlow=-10 vhigh=0 +A11 2 vref 0 0 0 N020 0 0 SCHMITT vt=0 vh=50m trise=10n +A12 DEF 0 0 0 0 0 N013 0 BUF Trise=12u Tfall=40n +S46 N011 DEF ON 0 SDelay +A13 N011 0 0 0 N013 _DE DE 0 OR trise=10n +C28 N011 0 1p Rpar=1k +A17 N025 0 N028 0 FailSafe 0 N031 0 OR trise=1n ref=.5 vlow=-1 vhigh=1 tripdt=1n +S45 12 1 N031 N032 SRO +S47 1 6 N039 N031 SRO +C67 12 1 500f +C68 1 6 500f +A19 N041 0 N042 0 _RE 0 Disable 0 OR trise=5n tripdt=2n +A20 Disable 0 0 0 0 0 N032 0 BUF ref=.5 trise=5n vlow=0 vhigh=1.5 +A21 Disable 0 0 0 0 N039 0 0 BUF ref=.5 trise=5n vlow=-1.5 vhigh=0 +A22 N020 0 0 0 0 0 N024 0 BUF Trise=10u Tfall=5n +S48 N021 N020 ON 0 SDelay +A23 N021 0 0 0 N024 _RE 0 0 OR trise=5n +C70 N021 0 1p Rpar=1k +G7 0 N040 11 6 .5m +G8 0 N040 10 6 .5m +C71 N040 0 100f Rpar=1k +A24 N040 0 0 0 0 0 N041 0 SCHMITT vt=26 vh=100m trise=10n +A25 0 N040 0 0 0 0 N042 0 SCHMITT vt=26 vh=100m trise=10n +S49 6 12 N020 0 SRPOW +A15 N026 N030 0 0 0 0 N028 0 SRFLOP trise=1n ref=.48 vlow=0 vhigh=1 +A26 11 10 0 0 0 0 N029 0 SCHMITT vt=75m vh=0 trise=1n +A27 0 0 N029 0 N026 0 N027 0 DFLOP trise=10n tfall=1n +A28 N027 0 0 0 0 0 N026 0 BUF trise=76n tfall=5n +A29 10 11 0 0 0 0 N038 0 SCHMITT vt=75m vh=0 trise=1n +A30 0 0 N038 0 N030 0 N033 0 DFLOP trise=10n tfall=1n +A31 N033 0 0 0 0 0 N030 0 BUF trise=76n tfall=5n +A32 11 10 0 0 0 0 N025 0 SCHMITT vt=75m vh=0 trise=500u tfall=1n +A33 _RE 0 0 0 _DE ON 0 0 AND trise=5n tfall=80n +S50 6 12 DEF 0 STPOW1 +D26 6 4 ESDL +D27 6 3 ESDL +D29 6 2 ESDL +D30 6 11 ESDH +D31 6 10 ESDH +C29 11 6 500f Rpar=112k +C36 10 6 500f Rpar=112k +D32 6 11 ESDH +D33 6 1 ESDL +D34 6 10 ESDH +C57 VIlimUY 0 100f Rpar=10k +C52 VIlimDY 0 100f Rpar=10k +A1 12 N037 0 0 0 0 FailSafe 0 SRFLOP trise=6u tfall=10n +A2 11 10 0 0 0 N036 0 0 SCHMITT vt=-62.5m vh=12.5m trise=10n +A4 N036 0 0 0 _RE 0 N037 0 OR trise=5n tripdt=2n +.model PDRV VDMOS(vto=-700m kp=400m mtriode=.3 rd=500m lambda=.1 subthres=5u is=0 pchan) +.model NDRV VDMOS(vto=700m kp=210m mtriode=.7 rd=1.2 lambda=.05 subthres=5u is=0) +.model DCLP D(Ron=10 Roff=1g vfwd=600m epsilon=100m vrev=500m epsilon=100m) +.model SDIN SW(Ron=100k Roff=1g vt=-100m vh=-200m) +.model SDPU SW(Ron=5k Roff=1G vt=0 vh=-100m) +.model SDPD SW(Ron=4k Roff=1G vt=0 vh=-100m) +.model DCLN D(Ron=10 Roff=1g vfwd=550m epsilon=100m vrev=490m epsilon=100m) +.model SDNU SW(Ron=8k Roff=1G vt=0 vh=-100m) +.model SDND SW(Ron=4k Roff=1G vt=0 vh=-100m) +.model ESDL D(Ron=60 Roff=1g vfwd=700m epsilon=500m vrev=10 revepsilon=500m) +.model ESDH D(Ron=60 Roff=1g vfwd=62 epsilon=1 vrev=62 revepsilon=1) +.model SIout SW(Ron=20k Roff=1Meg vt=30 vh=-20) +.model Sdelay SW(Ron=1 Roff=1g vt=.5 vh=-.2) +.model SREV SW(level=2 Ron=.1 Roff=10Meg vt=1 vh=-.1 ilimit=50m oneway epsilon=100m) +.model D1way D(Ron=10 Roff=10 vfwd=0 vrev=0 revilimit=1u) +.model SPullDwn SW(Ron=100 Roff=1g vt=1 vh=-1 ilimit=10m) +.model Soff SW(Ron=1 Roff=1Meg vt=.5 vh=-.2) +.model Soff2 SW(Ron=1 Roff=2Meg vt=-.5 vh=-.2) +.model DLSR D(Ron=1 Roff=10Meg vfwd=2 epsilon=500m vrev=2 revepsilon=500m) +.model SRPOW SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=400u) +.model STPOW1 SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=500u) +.model SRO SW(Ron=125 Roff=1g vt=-100m vh=-200m ilimit=20m) +.model DNout D(Ron=1.1 Roff=1g vfwd=450m epsilon=500m) +.ends LTC2862-1 diff --git a/spice/copy/sub/LTC2862-2.lib b/spice/copy/sub/LTC2862-2.lib new file mode 100755 index 0000000..d9ca159 --- /dev/null +++ b/spice/copy/sub/LTC2862-2.lib @@ -0,0 +1,206 @@ +* Copyright (c) Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005. All rights reserved. +* +.subckt LTC2862-2 1 2 3 4 5 6 7 8 9 10 11 12 +MZPDRV 10 N002 N003 N003 PDRV +MZNDRV N010 N006 N013 N013 NDRV +G1 0 vrefGR 12 6 1m +C1 vrefGR 0 100p Rpar=500 +G3 0 VCCGR 12 6 10m +C4 VCCGR 0 100p Rpar=100 +C8 N006 6 1p Rpar=1Meg +C6 12 10 1p Rpar=100meg +C5 10 6 1p Rpar=100meg +C17 N002 10 200f +C18 N010 N006 200f +S17 12 N008 N007 0 SDIN2 +S18 N008 6 0 N007 SDIN2 +C20 N008 6 1p Rpar=1g +C3 12 N002 1p Rpar=1Meg +D7 12 N006 DBIAS1 +C22 N009 N008 200f Rpar=1.5Meg +G2 0 N004 vref N009 10m +D9 N004 N005 DPPD +D10 N011 N004 DNPU +D11 12 N002 DP +D12 N006 6 DN +D13 N002 6 DBIAS1 +C27 0 N005 1p Rpar=1k +C24 N006 6 1p +C25 12 N002 1p +A2 N005 0 6 6 6 6 N002 6 OTA g=10m linear vlow=0 vhigh=1e308 +A4 N011 0 12 12 12 12 N006 12 OTA g=10m linear vlow=-1e308 vhigh=0 +G5 6 N002 VIlimUZ IlimUPZ 100m vto=0 dir=1 +I1 0 IlimUPZ 15µ +S19 IlimUPZ 0 12 10 SIout +G12 0 VIlimDZ N013 6 3.8m +C31 VIlimDZ 0 100f Rpar=10k +I2 0 IlimDNZ 15µ +S22 IlimDNZ 0 10 6 SIout +G13 N006 12 VIlimDZ IlimDNZ 100m vto=0 dir=1 +C9 N010 6 1p Rpar=10Meg +C11 N013 6 1p Rpar=2.6 +C12 IlimUPZ 0 10p +C13 IlimDNZ 0 10p +G4 0 VIlimUZ 12 N003 1m +C14 VIlimUZ 0 100f Rpar=10k +S6 12 N006 SPDZ 0 SPullDwn +D2 12 N003 D1way +S5 12 N003 SRONZ 0 SREV +A3 3 vref 0 0 0 0 DEF 0 SCHMITT vt=0 vh=50m trise=10n +S7 6 N006 _DE 0 Soff +S8 N002 12 _DE 0 Soff +G14 0 SRONZ 12 10 20µ +C10 SRONZ 0 100f Rpar=2Meg +I3 0 SRONZ 6µ +S13 0 SRONZ 0 DE Soff2 +D4 SRONZ 0 DLSR +G15 0 SPDZ 10 12 1µ +C15 SPDZ 0 100f Rpar=2Meg +I4 SPDZ 0 4µ +S14 0 SPDZ 0 DE Soff2 +D6 SPDZ 0 DLSR +G16 0 N007 4 vref 1µ +C32 N007 0 1f Rpar=1Meg +C33 N004 0 1p Rpar=100 +C34 12 N003 1p +C35 N009 10 .5p +G17 0 vref 12 0 1m +C19 vref 0 100p Rpar=500 +G18 0 vref 6 0 1m +MZPDRV1 11 N017 N018 N018 PDRV +MZNDRV1 N024 N021 N026 N026 NDRV +C38 N021 6 1p Rpar=1Meg +C39 12 11 1p Rpar=100meg +C40 11 6 1p Rpar=100meg +C41 N017 11 200f +C42 N024 N021 200f +S31 12 N022 0 N007 SDIN2 +S32 N022 6 N007 0 SDIN2 +C43 N022 6 1p Rpar=1g +C44 12 N017 1p Rpar=1Meg +D16 12 N021 DBIAS1 +C46 N023 N022 200f Rpar=1.5Meg +G6 0 N019 vref N023 10m +D17 N019 N020 DPPD +D18 N025 N019 DNPU +D19 12 N017 DP +D20 N021 6 DN +D21 N017 6 DBIAS1 +C50 N021 6 1p +C51 12 N017 1p +A7 N020 0 6 6 6 6 N017 6 OTA g=10m linear vlow=0 vhigh=1e308 +A8 N025 0 12 12 12 12 N021 12 OTA g=10m linear vlow=-1e308 vhigh=0 +G20 6 N017 VIlimUY IlimUPY 100m vto=0 dir=1 +I5 0 IlimUPY 15µ +S36 IlimUPY 0 12 11 SIout +G21 0 VIlimDY N026 6 3.8m +I6 0 IlimDNY 15µ +S37 IlimDNY 0 11 6 SIout +G22 N021 12 VIlimDY IlimDNY 100m vto=0 dir=1 +C54 N026 6 1p Rpar=2.6 +C55 IlimUPY 0 10p +C56 IlimDNY 0 10p +G23 0 VIlimUY 12 N018 1m +S38 12 N021 SPDY 0 SPullDwn +D22 12 N018 D1way +S39 12 N018 SRONY 0 SREV +S40 6 N021 _DE 0 Soff +S41 N017 12 _DE 0 Soff +G24 0 SRONY 12 11 20µ +C58 SRONY 0 100f Rpar=2Meg +I7 0 SRONY 6µ +S42 0 SRONY 0 DE Soff2 +D23 SRONY 0 DLSR +G25 0 SPDY 11 12 1µ +C59 SPDY 0 100f Rpar=2Meg +I8 SPDY 0 4µ +S43 0 SPDY 0 DE Soff2 +D24 SPDY 0 DLSR +C60 N019 0 1p Rpar=100 +C61 12 N018 1p +C62 N023 11 .5p +D5 10 N010 DNout +D15 11 N024 DNout +C45 N024 6 1p Rpar=10Meg +C49 10 N010 .5p +C53 11 N024 .5p +C63 N003 10 1p +C64 N010 N013 1p +C65 N018 11 1p +C66 N024 N026 1p +A11 2 vref 0 0 0 N027 0 0 SCHMITT vt=0 vh=50m trise=10n +A12 DEF 0 0 0 0 0 N016 0 BUF Trise=12u Tfall=40n +S46 N014 DEF ON 0 SDelay +A13 N014 0 0 0 N016 _DE DE 0 OR trise=10n +C28 N014 0 1p Rpar=1k +A17 N031 0 N034 0 FailSafe 0 N037 0 OR trise=1n ref=.5 vlow=-1 vhigh=1 tripdt=1n +S45 12 1 N037 N038 SRO +S47 1 6 N045 N037 SRO +C67 12 1 500f +C68 1 6 500f +A19 N047 0 N048 0 _RE 0 Disable 0 OR trise=5n tripdt=2n +A20 Disable 0 0 0 0 0 N038 0 BUF ref=.5 trise=5n vlow=0 vhigh=1.5 +A21 Disable 0 0 0 0 N045 0 0 BUF ref=.5 trise=5n vlow=-1.5 vhigh=0 +A22 N027 0 0 0 0 0 N030 0 BUF Trise=10u Tfall=5n +S48 N028 N027 ON 0 SDelay +A23 N028 0 0 0 N030 _RE 0 0 OR trise=5n +C70 N028 0 1p Rpar=1k +G7 0 N046 11 6 .5m +G8 0 N046 10 6 .5m +C71 N046 0 100f Rpar=1k +A24 N046 0 0 0 0 0 N047 0 SCHMITT vt=26 vh=100m trise=10n +A25 0 N046 0 0 0 0 N048 0 SCHMITT vt=26 vh=100m trise=10n +S49 6 12 N027 0 SRPOW +A15 N032 N036 0 0 0 0 N034 0 SRFLOP trise=1n ref=.48 vlow=0 vhigh=1 +A26 11 10 0 0 0 0 N035 0 SCHMITT vt=75m vh=0 trise=1n +A27 0 0 N035 0 N032 0 N033 0 DFLOP trise=10n tfall=1n +A28 N033 0 0 0 0 0 N032 0 BUF trise=76n tfall=5n +A29 10 11 0 0 0 0 N044 0 SCHMITT vt=75m vh=0 trise=1n +A30 0 0 N044 0 N036 0 N039 0 DFLOP trise=10n tfall=1n +A31 N039 0 0 0 0 0 N036 0 BUF trise=76n tfall=5n +A32 11 10 0 0 0 0 N031 0 SCHMITT vt=75m vh=0 trise=500u tfall=1n +A33 _RE 0 0 0 _DE ON 0 0 AND trise=5n tfall=80n +S50 6 12 DEF 0 STPOW1 +D26 6 4 ESDL +D27 6 3 ESDL +D29 6 2 ESDL +D30 6 11 ESDH +D31 6 10 ESDH +C29 11 6 500f Rpar=112k +C36 10 6 500f Rpar=112k +D32 6 11 ESDH +D33 6 1 ESDL +D34 6 10 ESDH +C57 VIlimUY 0 100f Rpar=10k +C52 VIlimDY 0 100f Rpar=10k +A16 12 N042 0 0 0 0 FailSafe 0 SRFLOP trise=6u tfall=10n +A18 11 10 0 0 0 N041 0 0 SCHMITT vt=-62.5m vh=12.5m trise=10n +A34 N041 0 0 0 _RE 0 N042 0 OR trise=5n tripdt=2n +C2 0 N011 1p Rpar=1k +C7 0 N020 1p Rpar=1k +C16 0 N025 1p Rpar=1k +S1 6 12 DEF 0 STPOW2 +.model PDRV VDMOS(vto=-700m kp=400m mtriode=.3 rd=500m lambda=.1 subthres=5u is=0 pchan) +.model NDRV VDMOS(vto=700m kp=210m mtriode=.7 rd=1.2 lambda=.05 subthres=5u is=0) +.model SDIN2 SW(Ron=1k Roff=1g vt=-100m vh=-200m) +.model DP D(Ron=150k Roff=1g vfwd=660m epsilon=500m) +.model DN D(Ron=400k Roff=1g vfwd=550m epsilon=900m) +.model ESDL D(Ron=60 Roff=1g vfwd=700m epsilon=500m vrev=10 revepsilon=500m) +.model ESDH D(Ron=60 Roff=1g vfwd=62 epsilon=1 vrev=62 revepsilon=1) +.model SIout SW(Ron=20k Roff=1Meg vt=30 vh=-20) +.model Sdelay SW(Ron=1 Roff=1g vt=.5 vh=-.2) +.model SREV SW(level=2 Ron=.1 Roff=10Meg vt=1 vh=-.1 ilimit=50m oneway epsilon=100m) +.model D1way D(Ron=10 Roff=10 vfwd=0 vrev=0 revilimit=1u) +.model SPullDwn SW(Ron=100 Roff=1g vt=1 vh=-1 ilimit=10m) +.model Soff SW(Ron=1 Roff=1Meg vt=.5 vh=-.2) +.model Soff2 SW(Ron=1 Roff=2Meg vt=-.5 vh=-.2) +.model DLSR D(Ron=1 Roff=10Meg vfwd=2 epsilon=500m vrev=2 revepsilon=500m) +.model SRPOW SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=400u) +.model STPOW1 SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=500u) +.model STPOW2 SW(Ron=10 Roff=1g vt=.5 vh=-.2 ilimit=2.4m) +.model SRO SW(Ron=125 Roff=1g vt=-100m vh=-200m ilimit=20m) +.model DPPD D(ron=200k Roff=100g vfwd=-160m epsilon=100m ilimit=10u) +.model DNPU D(ron=200k Roff=100g vfwd=-160m epsilon=100m ilimit=10u) +.model DBIAS1 D(Ron=100k Roff=1g vfwd=100m epsilon=100m ilimit=1u) +.model DNout D(Ron=1.1 Roff=1g vfwd=450m epsilon=500m) +.ends LTC2862-2 diff --git a/spice/copy/sub/LTC2863-1.lib b/spice/copy/sub/LTC2863-1.lib new file mode 100755 index 0000000..707d1ad --- /dev/null +++ b/spice/copy/sub/LTC2863-1.lib @@ -0,0 +1,165 @@ +* Copyright (c) Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005. All rights reserved. +* +.subckt LTC2863-1 1 2 3 4 5 6 7 8 9 10 11 12 +MZPDRV 9 N002 N004 N004 PDRV +MZNDRV N008 N007 N010 N010 NDRV +G1 0 vrefGR 12 6 1m +C1 vrefGR 0 100f Rpar=500 +C2 N005 0 550f Rpar=1g +S1 VCCGR N005 N003 0 SDIN +S2 N005 0 0 N003 SDIN +D1 N005 vrefGR DCLP +S3 12 N002 N005 vrefGR SDPU +S4 N002 6 vrefGR N005 SDPD +G3 0 VCCGR 12 6 10m +C4 VCCGR 0 100f Rpar=100 +C7 N011 0 550f Rpar=1g +S9 VCCGR N011 N003 0 SDIN +S10 N011 0 0 N003 SDIN +D3 N011 vrefGR DCLN +S11 12 N007 N011 vrefGR SDNU +S12 N007 6 vrefGR N011 SDND +C8 N007 6 1p Rpar=500k +C6 12 9 1p Rpar=100meg +C5 9 6 1p Rpar=100meg +C17 N002 9 200f +C18 N008 N007 200f +C3 12 N002 1p Rpar=500k +G5 6 N002 VIlimUZ IlimUPZ 100m vto=0 dir=1 +I1 0 IlimUPZ 15µ +S19 IlimUPZ 0 12 9 SIout +G12 0 VIlimDZ N010 6 3.8m +C31 VIlimDZ 0 100f Rpar=10k +I2 0 IlimDNZ 15µ +S22 IlimDNZ 0 9 6 SIout +G13 N007 12 VIlimDZ IlimDNZ 100m vto=0 dir=1 +C9 N008 6 1p Rpar=10Meg +C11 N010 6 1p Rpar=2.6 +C12 IlimUPZ 0 10p +C13 IlimDNZ 0 10p +G4 0 VIlimUZ 12 N004 1m +C14 VIlimUZ 0 100f Rpar=10k +S6 12 N007 SPDZ 0 SPullDwn +D2 12 N004 D1way +S5 12 N004 SRONZ 0 SREV +G14 0 SRONZ 12 9 20µ +C10 SRONZ 0 100f Rpar=1Meg +I3 0 SRONZ 6µ +D4 SRONZ 0 DLSR +G15 0 SPDZ 9 12 1µ +C15 SPDZ 0 100f Rpar=1Meg +I4 SPDZ 0 4µ +D6 SPDZ 0 DLSR +G16 0 N003 4 vref 1µ +C32 N003 0 1f Rpar=1Meg +C34 12 N004 1p +G17 0 vref 12 0 1m +C19 vref 0 100f Rpar=500 +G18 0 vref 6 0 1m +MZPDRV1 8 N012 N013 N013 PDRV +MZNDRV1 N017 N016 N018 N018 NDRV +C23 N014 0 550f Rpar=1g +S16 VCCGR N014 0 N003 SDIN +S21 N014 0 N003 0 SDIN +D8 N014 vrefGR DCLP +S25 12 N012 N014 vrefGR SDPU +S26 N012 6 vrefGR N014 SDPD +C37 N019 0 550f Rpar=1g +S27 VCCGR N019 0 N003 SDIN +S28 N019 0 N003 0 SDIN +D14 N019 vrefGR DCLN +S29 12 N016 N019 vrefGR SDNU +S30 N016 6 vrefGR N019 SDND +C38 N016 6 1p Rpar=500k +C39 12 8 1p Rpar=100meg +C40 8 6 1p Rpar=100meg +C41 N012 8 200f +C42 N017 N016 200f +C44 12 N012 1p Rpar=500k +G20 6 N012 VIlimUY IlimUPY 100m vto=0 dir=1 +I5 0 IlimUPY 15µ +S36 IlimUPY 0 12 8 SIout +G21 0 VIlimDY N018 6 3.8m +I6 0 IlimDNY 15µ +S37 IlimDNY 0 8 6 SIout +G22 N016 12 VIlimDY IlimDNY 100m vto=0 dir=1 +C54 N018 6 1p Rpar=2.6 +C55 IlimUPY 0 10p +C56 IlimDNY 0 10p +G23 0 VIlimUY 12 N013 1m +S38 12 N016 SPDY 0 SPullDwn +D22 12 N013 D1way +S39 12 N013 SRONY 0 SREV +G24 0 SRONY 12 8 20µ +C58 SRONY 0 100f Rpar=1Meg +I7 0 SRONY 6µ +D23 SRONY 0 DLSR +G25 0 SPDY 8 12 1µ +C59 SPDY 0 100f Rpar=1Meg +I8 SPDY 0 4µ +D24 SPDY 0 DLSR +C61 12 N013 1p +D5 9 N008 DNout +D15 8 N017 DNout +C45 N017 6 1p Rpar=10Meg +C49 9 N008 .5p +C53 8 N017 .5p +C63 N004 9 1p +C64 N008 N010 1p +C65 N013 8 1p +C66 N017 N018 1p +A17 N020 0 N023 0 FailSafe 0 N026 0 OR trise=1n ref=.5 vlow=-1 vhigh=1 tripdt=1n +S45 12 1 N026 N027 SRO +S47 1 6 N033 N026 SRO +C67 12 1 500f +C68 1 6 500f +A19 N035 0 N036 0 0 0 Disable 0 OR trise=5n tripdt=2n +A20 Disable 0 0 0 0 0 N027 0 BUF ref=.5 trise=5n vlow=0 vhigh=1.5 +A21 Disable 0 0 0 0 N033 0 0 BUF ref=.5 trise=5n vlow=-1.5 vhigh=0 +G7 0 N034 11 6 .5m +G8 0 N034 10 6 .5m +C71 N034 0 100f Rpar=1k +A24 N034 0 0 0 0 0 N035 0 SCHMITT vt=26 vh=100m trise=10n +A25 0 N034 0 0 0 0 N036 0 SCHMITT vt=26 vh=100m trise=10n +A15 N021 N025 0 0 0 0 N023 0 SRFLOP trise=1n ref=.48 vlow=0 vhigh=1 +A26 11 10 0 0 0 0 N024 0 SCHMITT vt=75m vh=0 trise=1n +A27 0 0 N024 0 N021 0 N022 0 DFLOP trise=10n tfall=1n +A28 N022 0 0 0 0 0 N021 0 BUF trise=76n tfall=5n +A29 10 11 0 0 0 0 N032 0 SCHMITT vt=75m vh=0 trise=1n +A30 0 0 N032 0 N025 0 N028 0 DFLOP trise=10n tfall=1n +A31 N028 0 0 0 0 0 N025 0 BUF trise=76n tfall=5n +A32 11 10 0 0 0 0 N020 0 SCHMITT vt=75m vh=0 trise=500u tfall=1n +D26 6 4 ESDL +D30 6 11 ESDH +D31 6 10 ESDH +C29 11 6 500f Rpar=112k +C36 10 6 500f Rpar=112k +D32 6 8 ESDH +D33 6 1 ESDL +D34 6 9 ESDH +C57 VIlimUY 0 100f Rpar=10k +C52 VIlimDY 0 100f Rpar=10k +A1 12 N031 0 0 0 0 FailSafe 0 SRFLOP trise=6u tfall=10n +A2 11 10 0 0 0 N031 0 0 SCHMITT vt=-62.5m vh=12.5m trise=10n +D7 12 6 DPOW +.model PDRV VDMOS(vto=-700m kp=400m mtriode=.3 rd=500m lambda=.1 subthres=5u is=0 pchan) +.model NDRV VDMOS(vto=700m kp=210m mtriode=.7 rd=1.2 lambda=.05 subthres=5u is=0) +.model DCLP D(Ron=10 Roff=1g vfwd=600m epsilon=100m vrev=500m epsilon=100m) +.model SDIN SW(Ron=100k Roff=1g vt=-100m vh=-200m) +.model SDPU SW(Ron=5k Roff=1G vt=0 vh=-100m) +.model SDPD SW(Ron=4k Roff=1G vt=0 vh=-100m) +.model DCLN D(Ron=10 Roff=1g vfwd=550m epsilon=100m vrev=490m epsilon=100m) +.model SDNU SW(Ron=8k Roff=1G vt=0 vh=-100m) +.model SDND SW(Ron=4k Roff=1G vt=0 vh=-100m) +.model ESDL D(Ron=60 Roff=1g vfwd=700m epsilon=500m vrev=10 revepsilon=500m) +.model ESDH D(Ron=60 Roff=1g vfwd=62 epsilon=1 vrev=62 revepsilon=1) +.model SIout SW(Ron=20k Roff=1Meg vt=30 vh=-20) +.model Sdelay SW(Ron=1 Roff=1g vt=.5 vh=-.2) +.model SREV SW(level=2 Ron=.1 Roff=10Meg vt=1 vh=-.1 ilimit=50m oneway epsilon=100m) +.model D1way D(Ron=10 Roff=10 vfwd=0 vrev=0 revilimit=1u) +.model SPullDwn SW(Ron=100 Roff=1g vt=1 vh=-1 ilimit=10m) +.model DLSR D(Ron=1 Roff=10Meg vfwd=2 epsilon=500m vrev=2 revepsilon=500m) +.model DPOW D(Ron=10 Roff=1G vfwd=2.6 epsilon=200m ilimit=900u) +.model SRO SW(Ron=125 Roff=1g vt=-100m vh=-200m ilimit=20m) +.model DNout D(Ron=1.1 Roff=1g vfwd=450m epsilon=500m) +.ends LTC2863-1 diff --git a/spice/copy/sub/LTC2863-2.lib b/spice/copy/sub/LTC2863-2.lib new file mode 100755 index 0000000..9e840b1 --- /dev/null +++ b/spice/copy/sub/LTC2863-2.lib @@ -0,0 +1,178 @@ +* Copyright (c) Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005. All rights reserved. +* +.subckt LTC2863-2 1 2 3 4 5 6 7 8 9 10 11 12 +MZPDRV 9 N002 N003 N003 PDRV +MZNDRV N011 N007 N014 N014 NDRV +G1 0 vrefGR 12 6 1m +C1 vrefGR 0 100p Rpar=500 +G3 0 VCCGR 12 6 10m +C4 VCCGR 0 100p Rpar=100 +C8 N007 6 1p Rpar=500k +C6 12 9 1p Rpar=100meg +C5 9 6 1p Rpar=100meg +C17 N002 9 200f +C18 N011 N007 200f +S17 12 N009 N008 0 SDIN2 +S18 N009 6 0 N008 SDIN2 +C20 N009 6 1p Rpar=1g +C3 12 N002 1p Rpar=500k +D7 12 N007 DBIAS1 +C22 N010 N009 200f Rpar=1.5Meg +G2 0 N005 vref N010 10m +D9 N005 N006 DPPD +D10 N012 N005 DNPU +D11 12 N002 DP +D12 N007 6 DN +D13 N002 6 DBIAS1 +C27 0 N006 1p Rpar=1k +C24 N007 6 1p +C25 12 N002 1p +A2 N006 0 6 6 6 6 N002 6 OTA g=10m linear vlow=0 vhigh=1e308 +A4 N012 0 12 12 12 12 N007 12 OTA g=10m linear vlow=-1e308 vhigh=0 +G5 6 N002 VIlimUZ IlimUPZ 100m vto=0 dir=1 +I1 0 IlimUPZ 15µ +S19 IlimUPZ 0 12 9 SIout +G12 0 VIlimDZ N014 6 3.8m +C31 VIlimDZ 0 100f Rpar=10k +I2 0 IlimDNZ 15µ +S22 IlimDNZ 0 9 6 SIout +G13 N007 12 VIlimDZ IlimDNZ 100m vto=0 dir=1 +C9 N011 6 1p Rpar=10Meg +C11 N014 6 1p Rpar=2.6 +C12 IlimUPZ 0 10p +C13 IlimDNZ 0 10p +G4 0 VIlimUZ 12 N003 1m +C14 VIlimUZ 0 100f Rpar=10k +S6 12 N007 SPDZ 0 SPullDwn +D2 12 N003 D1way +S5 12 N003 SRONZ 0 SREV +G14 0 SRONZ 12 9 20µ +C10 SRONZ 0 100f Rpar=1Meg +I3 0 SRONZ 6µ +D4 SRONZ 0 DLSR +G15 0 SPDZ 9 12 1µ +C15 SPDZ 0 100f Rpar=1Meg +I4 SPDZ 0 4µ +D6 SPDZ 0 DLSR +G16 0 N008 4 vref 1µ +C32 N008 0 1f Rpar=1Meg +C33 N005 0 1p Rpar=100 +C34 12 N003 1p +C35 N010 9 .5p +G17 0 vref 12 0 1m +C19 vref 0 100p Rpar=500 +G18 0 vref 6 0 1m +MZPDRV1 8 N015 N016 N016 PDRV +MZNDRV1 N023 N020 N025 N025 NDRV +C38 N020 6 1p Rpar=500k +C39 12 8 1p Rpar=100meg +C40 8 6 1p Rpar=100meg +C41 N015 8 200f +C42 N023 N020 200f +S31 12 N021 0 N008 SDIN2 +S32 N021 6 N008 0 SDIN2 +C43 N021 6 1p Rpar=1g +C44 12 N015 1p Rpar=500k +D16 12 N020 DBIAS1 +C46 N022 N021 200f Rpar=1.5Meg +G6 0 N018 vref N022 10m +D17 N018 N019 DPPD +D18 N024 N018 DNPU +D19 12 N015 DP +D20 N020 6 DN +D21 N015 6 DBIAS1 +C50 N020 6 1p +C51 12 N015 1p +A7 N019 0 6 6 6 6 N015 6 OTA g=10m linear vlow=0 vhigh=1e308 +A8 N024 0 12 12 12 12 N020 12 OTA g=10m linear vlow=-1e308 vhigh=0 +G20 6 N015 VIlimUY IlimUPY 100m vto=0 dir=1 +I5 0 IlimUPY 15µ +S36 IlimUPY 0 12 8 SIout +G21 0 VIlimDY N025 6 3.8m +I6 0 IlimDNY 15µ +S37 IlimDNY 0 8 6 SIout +G22 N020 12 VIlimDY IlimDNY 100m vto=0 dir=1 +C54 N025 6 1p Rpar=2.6 +C55 IlimUPY 0 10p +C56 IlimDNY 0 10p +G23 0 VIlimUY 12 N016 1m +S38 12 N020 SPDY 0 SPullDwn +D22 12 N016 D1way +S39 12 N016 SRONY 0 SREV +G24 0 SRONY 12 8 20µ +C58 SRONY 0 100f Rpar=1Meg +I7 0 SRONY 6µ +D23 SRONY 0 DLSR +G25 0 SPDY 8 12 1µ +C59 SPDY 0 100f Rpar=1Meg +I8 SPDY 0 4µ +D24 SPDY 0 DLSR +C60 N018 0 1p Rpar=100 +C61 12 N016 1p +C62 N022 8 .5p +D5 9 N011 DNout +D15 8 N023 DNout +C45 N023 6 1p Rpar=10Meg +C49 9 N011 .5p +C53 8 N023 .5p +C63 N003 9 1p +C64 N011 N014 1p +C65 N016 8 1p +C66 N023 N025 1p +A17 N026 0 N029 0 FailSafe 0 N032 0 OR trise=1n ref=.5 vlow=-1 vhigh=1 tripdt=1n +S45 12 1 N032 N033 SRO +S47 1 6 N039 N032 SRO +C67 12 1 500f +C68 1 6 500f +A19 N041 0 N042 0 0 0 Disable 0 OR trise=5n tripdt=2n +A20 Disable 0 0 0 0 0 N033 0 BUF ref=.5 trise=5n vlow=0 vhigh=1.5 +A21 Disable 0 0 0 0 N039 0 0 BUF ref=.5 trise=5n vlow=-1.5 vhigh=0 +G7 0 N040 11 6 .5m +G8 0 N040 10 6 .5m +C71 N040 0 100f Rpar=1k +A24 N040 0 0 0 0 0 N041 0 SCHMITT vt=26 vh=100m trise=10n +A25 0 N040 0 0 0 0 N042 0 SCHMITT vt=26 vh=100m trise=10n +A15 N027 N031 0 0 0 0 N029 0 SRFLOP trise=1n ref=.48 vlow=0 vhigh=1 +A26 11 10 0 0 0 0 N030 0 SCHMITT vt=75m vh=0 trise=1n +A27 0 0 N030 0 N027 0 N028 0 DFLOP trise=10n tfall=1n +A28 N028 0 0 0 0 0 N027 0 BUF trise=76n tfall=5n +A29 10 11 0 0 0 0 N038 0 SCHMITT vt=75m vh=0 trise=1n +A30 0 0 N038 0 N031 0 N034 0 DFLOP trise=10n tfall=1n +A31 N034 0 0 0 0 0 N031 0 BUF trise=76n tfall=5n +A32 11 10 0 0 0 0 N026 0 SCHMITT vt=75m vh=0 trise=500u tfall=1n +D26 6 4 ESDL +D30 6 11 ESDH +D31 6 10 ESDH +C29 11 6 500f Rpar=112k +C36 10 6 500f Rpar=112k +D32 6 8 ESDH +D33 6 1 ESDL +D34 6 9 ESDH +C57 VIlimUY 0 100f Rpar=10k +C52 VIlimDY 0 100f Rpar=10k +A16 12 N036 0 0 0 0 FailSafe 0 SRFLOP trise=6u tfall=10n +A18 11 10 0 0 0 N036 0 0 SCHMITT vt=-62.5m vh=12.5m trise=10n +C2 0 N012 1p Rpar=1k +C7 0 N019 1p Rpar=1k +C16 0 N024 1p Rpar=1k +D1 12 6 DPOW +.model PDRV VDMOS(vto=-700m kp=400m mtriode=.3 rd=500m lambda=.1 subthres=5u is=0 pchan) +.model NDRV VDMOS(vto=700m kp=210m mtriode=.7 rd=1.2 lambda=.05 subthres=5u is=0) +.model SDIN2 SW(Ron=1k Roff=1g vt=-100m vh=-200m) +.model DP D(Ron=150k Roff=1g vfwd=660m epsilon=500m) +.model DN D(Ron=400k Roff=1g vfwd=550m epsilon=900m) +.model ESDL D(Ron=60 Roff=1g vfwd=700m epsilon=500m vrev=10 revepsilon=500m) +.model ESDH D(Ron=60 Roff=1g vfwd=62 epsilon=1 vrev=62 revepsilon=1) +.model SIout SW(Ron=20k Roff=1Meg vt=30 vh=-20) +.model Sdelay SW(Ron=1 Roff=1g vt=.5 vh=-.2) +.model SREV SW(level=2 Ron=.1 Roff=10Meg vt=1 vh=-.1 ilimit=50m oneway epsilon=100m) +.model D1way D(Ron=10 Roff=10 vfwd=0 vrev=0 revilimit=1u) +.model SPullDwn SW(Ron=100 Roff=1g vt=1 vh=-1 ilimit=10m) +.model DLSR D(Ron=1 Roff=10Meg vfwd=2 epsilon=500m vrev=2 revepsilon=500m) +.model DPOW D(Ron=10 Roff=1g vfwd=1.6 epsilon=200m ilimit=3.3m) +.model SRO SW(Ron=125 Roff=1g vt=-100m vh=-200m ilimit=20m) +.model DPPD D(ron=200k Roff=100g vfwd=-160m epsilon=100m ilimit=10u) +.model DNPU D(ron=200k Roff=100g vfwd=-160m epsilon=100m ilimit=10u) +.model DBIAS1 D(Ron=100k Roff=1g vfwd=100m epsilon=100m ilimit=1u) +.model DNout D(Ron=1.1 Roff=1g vfwd=450m epsilon=500m) +.ends LTC2863-2 diff --git a/spice/copy/sub/LTC2864-1.lib b/spice/copy/sub/LTC2864-1.lib new file mode 100755 index 0000000..803f72b --- /dev/null +++ b/spice/copy/sub/LTC2864-1.lib @@ -0,0 +1,193 @@ +* Copyright (c) Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005. All rights reserved. +* +.subckt LTC2864-1 1 2 3 4 5 6 7 8 9 10 11 12 +MZPDRV 9 N002 N004 N004 PDRV +MZNDRV N008 N007 N010 N010 NDRV +G1 0 vrefGR 12 6 1m +C1 vrefGR 0 100f Rpar=500 +C2 N005 0 550f Rpar=1g +S1 VCCGR N005 N003 0 SDIN +S2 N005 0 0 N003 SDIN +D1 N005 vrefGR DCLP +S3 12 N002 N005 vrefGRH SDPU +S4 N002 6 vrefGRL N005 SDPD +G3 0 VCCGR 12 6 10m +C4 VCCGR 0 100f Rpar=100 +C7 N011 0 550f Rpar=1g +S9 VCCGR N011 N003 0 SDIN +S10 N011 0 0 N003 SDIN +D3 N011 vrefGR DCLN +S11 12 N007 N011 vrefGRH SDNU +S12 N007 6 vrefGRL N011 SDND +C8 N007 6 1p Rpar=1Meg +C6 12 9 1p Rpar=100meg +C5 9 6 1p Rpar=100meg +C17 N002 9 200f +C18 N008 N007 200f +C3 12 N002 1p Rpar=1Meg +G5 6 N002 VIlimUZ IlimUPZ 100m vto=0 dir=1 +I1 0 IlimUPZ 15µ +S19 IlimUPZ 0 12 9 SIout +G12 0 VIlimDZ N010 6 3.8m +C31 VIlimDZ 0 100f Rpar=10k +I2 0 IlimDNZ 15µ +S22 IlimDNZ 0 9 6 SIout +G13 N007 12 VIlimDZ IlimDNZ 100m vto=0 dir=1 +C9 N008 6 1p Rpar=10Meg +C11 N010 6 1p Rpar=2.6 +C12 IlimUPZ 0 10p +C13 IlimDNZ 0 10p +G4 0 VIlimUZ 12 N004 1m +C14 VIlimUZ 0 100f Rpar=10k +S6 12 N007 SPDZ 0 SPullDwn +D2 12 N004 D1way +S5 12 N004 SRONZ 0 SREV +A3 3 vref 0 0 0 0 DEF 0 SCHMITT vt=0 vh=50m trise=10n +S7 6 N007 _DE 0 Soff +S8 N002 12 _DE 0 Soff +G14 0 SRONZ 12 9 20µ +C10 SRONZ 0 100f Rpar=2Meg +I3 0 SRONZ 6µ +S13 0 SRONZ 0 DE Soff2 +D4 SRONZ 0 DLSR +G15 0 SPDZ 9 12 1µ +C15 SPDZ 0 100f Rpar=2Meg +I4 SPDZ 0 4µ +S14 0 SPDZ 0 DE Soff2 +D6 SPDZ 0 DLSR +G16 0 N003 4 vref 1µ +C32 N003 0 1f Rpar=1Meg +C34 12 N004 1p +G17 0 vref 12 0 1m +C19 vref 0 100f Rpar=500 +G18 0 vref 6 0 1m +MZPDRV1 8 N015 N016 N016 PDRV +MZNDRV1 N020 N019 N021 N021 NDRV +C23 N017 0 550f Rpar=1g +S16 VCCGR N017 0 N003 SDIN +S21 N017 0 N003 0 SDIN +D8 N017 vrefGR DCLP +S25 12 N015 N017 vrefGRH SDPU +S26 N015 6 vrefGRL N017 SDPD +C37 N025 0 550f Rpar=1g +S27 VCCGR N025 0 N003 SDIN +S28 N025 0 N003 0 SDIN +D14 N025 vrefGR DCLN +S29 12 N019 N025 vrefGRH SDNU +S30 N019 6 vrefGRL N025 SDND +C38 N019 6 1p Rpar=1Meg +C39 12 8 1p Rpar=100meg +C40 8 6 1p Rpar=100meg +C41 N015 8 200f +C42 N020 N019 200f +C44 12 N015 1p Rpar=1Meg +G20 6 N015 VIlimUY IlimUPY 100m vto=0 dir=1 +I5 0 IlimUPY 15µ +S36 IlimUPY 0 12 8 SIout +G21 0 VIlimDY N021 6 3.8m +I6 0 IlimDNY 15µ +S37 IlimDNY 0 8 6 SIout +G22 N019 12 VIlimDY IlimDNY 100m vto=0 dir=1 +C54 N021 6 1p Rpar=2.6 +C55 IlimUPY 0 10p +C56 IlimDNY 0 10p +G23 0 VIlimUY 12 N016 1m +S38 12 N019 SPDY 0 SPullDwn +D22 12 N016 D1way +S39 12 N016 SRONY 0 SREV +S40 6 N019 _DE 0 Soff +S41 N015 12 _DE 0 Soff +G24 0 SRONY 12 8 20µ +C58 SRONY 0 100f Rpar=2Meg +I7 0 SRONY 6µ +S42 0 SRONY 0 DE Soff2 +D23 SRONY 0 DLSR +G25 0 SPDY 8 12 1µ +C59 SPDY 0 100f Rpar=2Meg +I8 SPDY 0 4µ +S43 0 SPDY 0 DE Soff2 +D24 SPDY 0 DLSR +C61 12 N016 1p +D5 9 N008 DNout +D15 8 N020 DNout +C45 N020 6 1p Rpar=10Meg +C49 9 N008 .5p +C53 8 N020 .5p +C63 N004 9 1p +C64 N008 N010 1p +C65 N016 8 1p +C66 N020 N021 1p +A9 _DE 0 vrefGR vrefGR vrefGR vrefGR vrefGRH vrefGR SCHMITT vt=.5 trise=5n vlow=0 vhigh=10 +A10 0 _DE vrefGR vrefGR vrefGR vrefGR vrefGRL vrefGR SCHMITT vt=-.5 trise=5n vlow=-10 vhigh=0 +A11 2 vref 0 0 0 N022 0 0 SCHMITT vt=0 vh=50m trise=10n +A12 DEF 0 0 0 0 0 N014 0 BUF Trise=12u Tfall=40n +S46 N012 DEF ON 0 SDelay +A13 N012 0 0 0 N014 _DE DE 0 OR trise=10n +C28 N012 0 1p Rpar=1k +A17 N027 0 N030 0 FailSafe 0 N033 0 OR trise=1n ref=.5 vlow=-1 vhigh=1 tripdt=1n +S45 12 1 N033 N034 SRO +S47 1 6 N041 N033 SRO +C67 12 1 500f +C68 1 6 500f +A19 N043 0 N044 0 _RE 0 Disable 0 OR trise=5n tripdt=2n +A20 Disable 0 0 0 0 0 N034 0 BUF ref=.5 trise=5n vlow=0 vhigh=1.5 +A21 Disable 0 0 0 0 N041 0 0 BUF ref=.5 trise=5n vlow=-1.5 vhigh=0 +A22 N022 0 0 0 0 0 N026 0 BUF Trise=10u Tfall=5n +S48 N023 N022 ON 0 SDelay +A23 N023 0 0 0 N026 _RE 0 0 OR trise=5n +C70 N023 0 1p Rpar=1k +G7 0 N042 11 6 .5m +G8 0 N042 10 6 .5m +C71 N042 0 100f Rpar=1k +A24 N042 0 0 0 0 0 N043 0 SCHMITT vt=26 vh=100m trise=10n +A25 0 N042 0 0 0 0 N044 0 SCHMITT vt=26 vh=100m trise=10n +S49 6 12 N022 0 SRPOW +A15 N028 N032 0 0 0 0 N030 0 SRFLOP trise=1n ref=.48 vlow=0 vhigh=1 +A26 11 10 0 0 0 0 N031 0 SCHMITT vt=75m vh=0 trise=1n +A27 0 0 N031 0 N028 0 N029 0 DFLOP trise=10n tfall=1n +A28 N029 0 0 0 0 0 N028 0 BUF trise=76n tfall=5n +A29 10 11 0 0 0 0 N040 0 SCHMITT vt=75m vh=0 trise=1n +A30 0 0 N040 0 N032 0 N035 0 DFLOP trise=10n tfall=1n +A31 N035 0 0 0 0 0 N032 0 BUF trise=76n tfall=5n +A32 11 10 0 0 0 0 N027 0 SCHMITT vt=75m vh=0 trise=500u tfall=1n +A33 _RE 0 0 0 _DE ON 0 0 AND trise=5n tfall=80n +S50 6 12 DEF 0 STPOW1 +D26 6 4 ESDL +D27 6 3 ESDL +D29 6 2 ESDL +D30 6 11 ESDH +D31 6 10 ESDH +C29 11 6 500f Rpar=112k +C36 10 6 500f Rpar=112k +D32 6 8 ESDH +D33 6 1 ESDL +D34 6 9 ESDH +C57 VIlimUY 0 100f Rpar=10k +C52 VIlimDY 0 100f Rpar=10k +A1 12 N039 0 0 0 0 FailSafe 0 SRFLOP trise=6u tfall=10n +A2 11 10 0 0 0 N038 0 0 SCHMITT vt=-62.5m vh=12.5m trise=10n +A4 N038 0 0 0 _RE 0 N039 0 OR trise=5n tripdt=2n +.model PDRV VDMOS(vto=-700m kp=400m mtriode=.3 rd=500m lambda=.1 subthres=5u is=0 pchan) +.model NDRV VDMOS(vto=700m kp=210m mtriode=.7 rd=1.2 lambda=.05 subthres=5u is=0) +.model DCLP D(Ron=10 Roff=1g vfwd=600m epsilon=100m vrev=500m epsilon=100m) +.model SDIN SW(Ron=100k Roff=1g vt=-100m vh=-200m) +.model SDPU SW(Ron=5k Roff=1G vt=0 vh=-100m) +.model SDPD SW(Ron=4k Roff=1G vt=0 vh=-100m) +.model DCLN D(Ron=10 Roff=1g vfwd=550m epsilon=100m vrev=490m epsilon=100m) +.model SDNU SW(Ron=8k Roff=1G vt=0 vh=-100m) +.model SDND SW(Ron=4k Roff=1G vt=0 vh=-100m) +.model ESDL D(Ron=60 Roff=1g vfwd=700m epsilon=500m vrev=10 revepsilon=500m) +.model ESDH D(Ron=60 Roff=1g vfwd=62 epsilon=1 vrev=62 revepsilon=1) +.model SIout SW(Ron=20k Roff=1Meg vt=30 vh=-20) +.model Sdelay SW(Ron=1 Roff=1g vt=.5 vh=-.2) +.model SREV SW(level=2 Ron=.1 Roff=10Meg vt=1 vh=-.1 ilimit=50m oneway epsilon=100m) +.model D1way D(Ron=10 Roff=10 vfwd=0 vrev=0 revilimit=1u) +.model SPullDwn SW(Ron=100 Roff=1g vt=1 vh=-1 ilimit=10m) +.model Soff SW(Ron=1 Roff=1Meg vt=.5 vh=-.2) +.model Soff2 SW(Ron=1 Roff=2Meg vt=-.5 vh=-.2) +.model DLSR D(Ron=1 Roff=10Meg vfwd=2 epsilon=500m vrev=2 revepsilon=500m) +.model SRPOW SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=400u) +.model STPOW1 SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=500u) +.model SRO SW(Ron=125 Roff=1g vt=-100m vh=-200m ilimit=20m) +.model DNout D(Ron=1.1 Roff=1g vfwd=450m epsilon=500m) +.ends LTC2864-1 diff --git a/spice/copy/sub/LTC2864-2.lib b/spice/copy/sub/LTC2864-2.lib new file mode 100755 index 0000000..ce74678 --- /dev/null +++ b/spice/copy/sub/LTC2864-2.lib @@ -0,0 +1,206 @@ +* Copyright (c) Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005. All rights reserved. +* +.subckt LTC2864-2 1 2 3 4 5 6 7 8 9 10 11 12 +MZPDRV 9 N002 N003 N003 PDRV +MZNDRV N011 N007 N014 N014 NDRV +G1 0 vrefGR 12 6 1m +C1 vrefGR 0 100p Rpar=500 +G3 0 VCCGR 12 6 10m +C4 VCCGR 0 100p Rpar=100 +C8 N007 6 1p Rpar=1Meg +C6 12 9 1p Rpar=100meg +C5 9 6 1p Rpar=100meg +C17 N002 9 200f +C18 N011 N007 200f +S17 12 N009 N008 0 SDIN2 +S18 N009 6 0 N008 SDIN2 +C20 N009 6 1p Rpar=1g +C3 12 N002 1p Rpar=1Meg +D7 12 N007 DBIAS1 +C22 N010 N009 200f Rpar=1.5Meg +G2 0 N005 vref N010 10m +D9 N005 N006 DPPD +D10 N012 N005 DNPU +D11 12 N002 DP +D12 N007 6 DN +D13 N002 6 DBIAS1 +C27 0 N006 1p Rpar=1k +C24 N007 6 1p +C25 12 N002 1p +A2 N006 0 6 6 6 6 N002 6 OTA g=10m linear vlow=0 vhigh=1e308 +A4 N012 0 12 12 12 12 N007 12 OTA g=10m linear vlow=-1e308 vhigh=0 +G5 6 N002 VIlimUZ IlimUPZ 100m vto=0 dir=1 +I1 0 IlimUPZ 15µ +S19 IlimUPZ 0 12 9 SIout +G12 0 VIlimDZ N014 6 3.8m +C31 VIlimDZ 0 100f Rpar=10k +I2 0 IlimDNZ 15µ +S22 IlimDNZ 0 9 6 SIout +G13 N007 12 VIlimDZ IlimDNZ 100m vto=0 dir=1 +C9 N011 6 1p Rpar=10Meg +C11 N014 6 1p Rpar=2.6 +C12 IlimUPZ 0 10p +C13 IlimDNZ 0 10p +G4 0 VIlimUZ 12 N003 1m +C14 VIlimUZ 0 100f Rpar=10k +S6 12 N007 SPDZ 0 SPullDwn +D2 12 N003 D1way +S5 12 N003 SRONZ 0 SREV +A3 3 vref 0 0 0 0 DEF 0 SCHMITT vt=0 vh=50m trise=10n +S7 6 N007 _DE 0 Soff +S8 N002 12 _DE 0 Soff +G14 0 SRONZ 12 9 20µ +C10 SRONZ 0 100f Rpar=2Meg +I3 0 SRONZ 6µ +S13 0 SRONZ 0 DE Soff2 +D4 SRONZ 0 DLSR +G15 0 SPDZ 9 12 1µ +C15 SPDZ 0 100f Rpar=2Meg +I4 SPDZ 0 4µ +S14 0 SPDZ 0 DE Soff2 +D6 SPDZ 0 DLSR +G16 0 N008 4 vref 1µ +C32 N008 0 1f Rpar=1Meg +C33 N005 0 1p Rpar=100 +C34 12 N003 1p +C35 N010 9 .5p +G17 0 vref 12 0 1m +C19 vref 0 100p Rpar=500 +G18 0 vref 6 0 1m +MZPDRV1 8 N018 N019 N019 PDRV +MZNDRV1 N026 N023 N028 N028 NDRV +C38 N023 6 1p Rpar=1Meg +C39 12 8 1p Rpar=100meg +C40 8 6 1p Rpar=100meg +C41 N018 8 200f +C42 N026 N023 200f +S31 12 N024 0 N008 SDIN2 +S32 N024 6 N008 0 SDIN2 +C43 N024 6 1p Rpar=1g +C44 12 N018 1p Rpar=1Meg +D16 12 N023 DBIAS1 +C46 N025 N024 200f Rpar=1.5Meg +G6 0 N021 vref N025 10m +D17 N021 N022 DPPD +D18 N027 N021 DNPU +D19 12 N018 DP +D20 N023 6 DN +D21 N018 6 DBIAS1 +C50 N023 6 1p +C51 12 N018 1p +A7 N022 0 6 6 6 6 N018 6 OTA g=10m linear vlow=0 vhigh=1e308 +A8 N027 0 12 12 12 12 N023 12 OTA g=10m linear vlow=-1e308 vhigh=0 +G20 6 N018 VIlimUY IlimUPY 100m vto=0 dir=1 +I5 0 IlimUPY 15µ +S36 IlimUPY 0 12 8 SIout +G21 0 VIlimDY N028 6 3.8m +I6 0 IlimDNY 15µ +S37 IlimDNY 0 8 6 SIout +G22 N023 12 VIlimDY IlimDNY 100m vto=0 dir=1 +C54 N028 6 1p Rpar=2.6 +C55 IlimUPY 0 10p +C56 IlimDNY 0 10p +G23 0 VIlimUY 12 N019 1m +S38 12 N023 SPDY 0 SPullDwn +D22 12 N019 D1way +S39 12 N019 SRONY 0 SREV +S40 6 N023 _DE 0 Soff +S41 N018 12 _DE 0 Soff +G24 0 SRONY 12 8 20µ +C58 SRONY 0 100f Rpar=2Meg +I7 0 SRONY 6µ +S42 0 SRONY 0 DE Soff2 +D23 SRONY 0 DLSR +G25 0 SPDY 8 12 1µ +C59 SPDY 0 100f Rpar=2Meg +I8 SPDY 0 4µ +S43 0 SPDY 0 DE Soff2 +D24 SPDY 0 DLSR +C60 N021 0 1p Rpar=100 +C61 12 N019 1p +C62 N025 8 .5p +D5 9 N011 DNout +D15 8 N026 DNout +C45 N026 6 1p Rpar=10Meg +C49 9 N011 .5p +C53 8 N026 .5p +C63 N003 9 1p +C64 N011 N014 1p +C65 N019 8 1p +C66 N026 N028 1p +A11 2 vref 0 0 0 N029 0 0 SCHMITT vt=0 vh=50m trise=10n +A12 DEF 0 0 0 0 0 N017 0 BUF Trise=12u Tfall=40n +S46 N015 DEF ON 0 SDelay +A13 N015 0 0 0 N017 _DE DE 0 OR trise=10n +C28 N015 0 1p Rpar=1k +A17 N033 0 N036 0 FailSafe 0 N039 0 OR trise=1n ref=.5 vlow=-1 vhigh=1 tripdt=1n +S45 12 1 N039 N040 SRO +S47 1 6 N047 N039 SRO +C67 12 1 500f +C68 1 6 500f +A19 N049 0 N050 0 _RE 0 Disable 0 OR trise=5n tripdt=2n +A20 Disable 0 0 0 0 0 N040 0 BUF ref=.5 trise=5n vlow=0 vhigh=1.5 +A21 Disable 0 0 0 0 N047 0 0 BUF ref=.5 trise=5n vlow=-1.5 vhigh=0 +A22 N029 0 0 0 0 0 N032 0 BUF Trise=10u Tfall=5n +S48 N030 N029 ON 0 SDelay +A23 N030 0 0 0 N032 _RE 0 0 OR trise=5n +C70 N030 0 1p Rpar=1k +G7 0 N048 11 6 .5m +G8 0 N048 10 6 .5m +C71 N048 0 100f Rpar=1k +A24 N048 0 0 0 0 0 N049 0 SCHMITT vt=26 vh=100m trise=10n +A25 0 N048 0 0 0 0 N050 0 SCHMITT vt=26 vh=100m trise=10n +S49 6 12 N029 0 SRPOW +A15 N034 N038 0 0 0 0 N036 0 SRFLOP trise=1n ref=.48 vlow=0 vhigh=1 +A26 11 10 0 0 0 0 N037 0 SCHMITT vt=75m vh=0 trise=1n +A27 0 0 N037 0 N034 0 N035 0 DFLOP trise=10n tfall=1n +A28 N035 0 0 0 0 0 N034 0 BUF trise=76n tfall=5n +A29 10 11 0 0 0 0 N046 0 SCHMITT vt=75m vh=0 trise=1n +A30 0 0 N046 0 N038 0 N041 0 DFLOP trise=10n tfall=1n +A31 N041 0 0 0 0 0 N038 0 BUF trise=76n tfall=5n +A32 11 10 0 0 0 0 N033 0 SCHMITT vt=75m vh=0 trise=500u tfall=1n +A33 _RE 0 0 0 _DE ON 0 0 AND trise=5n tfall=80n +S50 6 12 DEF 0 STPOW1 +D26 6 4 ESDL +D27 6 3 ESDL +D29 6 2 ESDL +D30 6 11 ESDH +D31 6 10 ESDH +C29 11 6 500f Rpar=112k +C36 10 6 500f Rpar=112k +D32 6 8 ESDH +D33 6 1 ESDL +D34 6 9 ESDH +C57 VIlimUY 0 100f Rpar=10k +C52 VIlimDY 0 100f Rpar=10k +A16 12 N044 0 0 0 0 FailSafe 0 SRFLOP trise=6u tfall=10n +A18 11 10 0 0 0 N043 0 0 SCHMITT vt=-62.5m vh=12.5m trise=10n +A34 N043 0 0 0 _RE 0 N044 0 OR trise=5n tripdt=2n +C2 0 N012 1p Rpar=1k +C7 0 N022 1p Rpar=1k +C16 0 N027 1p Rpar=1k +S1 6 12 DEF 0 STPOW2 +.model PDRV VDMOS(vto=-700m kp=400m mtriode=.3 rd=500m lambda=.1 subthres=5u is=0 pchan) +.model NDRV VDMOS(vto=700m kp=210m mtriode=.7 rd=1.2 lambda=.05 subthres=5u is=0) +.model SDIN2 SW(Ron=1k Roff=1g vt=-100m vh=-200m) +.model DP D(Ron=150k Roff=1g vfwd=660m epsilon=500m) +.model DN D(Ron=400k Roff=1g vfwd=550m epsilon=900m) +.model ESDL D(Ron=60 Roff=1g vfwd=700m epsilon=500m vrev=10 revepsilon=500m) +.model ESDH D(Ron=60 Roff=1g vfwd=62 epsilon=1 vrev=62 revepsilon=1) +.model SIout SW(Ron=20k Roff=1Meg vt=30 vh=-20) +.model Sdelay SW(Ron=1 Roff=1g vt=.5 vh=-.2) +.model SREV SW(level=2 Ron=.1 Roff=10Meg vt=1 vh=-.1 ilimit=50m oneway epsilon=100m) +.model D1way D(Ron=10 Roff=10 vfwd=0 vrev=0 revilimit=1u) +.model SPullDwn SW(Ron=100 Roff=1g vt=1 vh=-1 ilimit=10m) +.model Soff SW(Ron=1 Roff=1Meg vt=.5 vh=-.2) +.model Soff2 SW(Ron=1 Roff=2Meg vt=-.5 vh=-.2) +.model DLSR D(Ron=1 Roff=10Meg vfwd=2 epsilon=500m vrev=2 revepsilon=500m) +.model SRPOW SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=400u) +.model STPOW1 SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=500u) +.model STPOW2 SW(Ron=10 Roff=1g vt=.5 vh=-.2 ilimit=2.4m) +.model SRO SW(Ron=125 Roff=1g vt=-100m vh=-200m ilimit=20m) +.model DPPD D(ron=200k Roff=100g vfwd=-160m epsilon=100m ilimit=10u) +.model DNPU D(ron=200k Roff=100g vfwd=-160m epsilon=100m ilimit=10u) +.model DBIAS1 D(Ron=100k Roff=1g vfwd=100m epsilon=100m ilimit=1u) +.model DNout D(Ron=1.1 Roff=1g vfwd=450m epsilon=500m) +.ends LTC2864-2 diff --git a/spice/copy/sub/LTC2865.lib b/spice/copy/sub/LTC2865.lib new file mode 100755 index 0000000..81834ff --- /dev/null +++ b/spice/copy/sub/LTC2865.lib @@ -0,0 +1,264 @@ +* Copyright (c) 1998-2015 Linear Technology Corporation. All rights reserved. +* +.subckt LTC2865 1 2 3 4 5 6 7 8 9 10 11 12 +MZPDRV 9 N002 N005 N005 PDRV +MZNDRV N013 N010 N017 N017 NDRV +G1 0 vrefGR 12 6 1m +C1 vrefGR 0 100f Rpar=500 +C2 N006 0 550f Rpar=1g +S1 VCCGR N006 DI3 0 SDIN +S2 N006 0 0 DI3 SDIN +D1 N006 vrefGR DCLP +S3 12 N002 N006 vrefGRH SDPU +S4 N002 6 vrefGRL N006 SDPD +G3 0 VCCGR 12 6 10m +C4 VCCGR 0 100f Rpar=100 +C7 N018 0 550f Rpar=1g +S9 VCCGR N018 DI3 0 SDIN +S10 N018 0 0 DI3 SDIN +D3 N018 vrefGR DCLN +S11 12 N010 N018 vrefGRH SDNU +S12 N010 6 vrefGRL N018 SDND +C8 N010 6 1p Rpar=1Meg +C6 12 9 1p Rpar=100meg +C5 9 6 1p Rpar=100meg +C17 N002 9 200f +C18 N013 N010 200f +S17 12 N011 DI3 0 SDIN2 +S18 N011 6 0 DI3 SDIN2 +C20 N011 6 1p Rpar=1g +C3 12 N002 1p Rpar=1Meg +D7 12 N015 DBIAS1 +C22 N012 N011 200f Rpar=1.5Meg +G2 0 N008 vref N012 10m +D9 N008 N009 DPPD +D10 N014 N008 DNPU +D11 12 N004 DP +D12 N015 6 DN +S20 N002 N004 0 _TXslow SMODE1 +D13 N004 6 DBIAS1 +S23 0 N014 _TXslow2 0 SMODE3 +S24 0 N009 _TXslow2 0 SMODE3 +C26 N014 0 1p +C27 0 N009 1p +C24 N015 6 1p +C25 12 N004 1p +A2 N009 0 6 6 6 6 N004 6 OTA g=10m linear vlow=0 vhigh=1e308 +A4 N014 0 12 12 12 12 N015 12 OTA g=10m linear vlow=-1e308 vhigh=0 +G5 6 N002 VIlimUZ IlimUPZ 100m vto=0 dir=1 +I1 0 IlimUPZ 15µ +S19 IlimUPZ 0 12 9 SIout +G12 0 VIlimDZ N017 6 3.8m +C31 VIlimDZ 0 100f Rpar=10k +I2 0 IlimDNZ 15µ +S22 IlimDNZ 0 9 6 SIout +G13 N010 12 VIlimDZ IlimDNZ 100m vto=0 dir=1 +C9 N013 6 1p Rpar=10Meg +C11 N017 6 1p Rpar=2.6 +C12 IlimUPZ 0 10p +C13 IlimDNZ 0 10p +G4 0 VIlimUZ 12 N005 1m +C14 VIlimUZ 0 100f Rpar=10k +S6 12 N010 SPDZ 0 SPullDwn +D2 12 N005 D1way +S5 12 N005 SRONZ 0 SREV +A3 3 vlref 0 0 0 0 N020 0 SCHMITT vt=0 vh=50m trise=10n +A5 DE 0 0 0 _SLO _TXfast 0 0 AND trise=5n +A6 _DE 0 0 0 _SLO 0 _TXslow 0 OR trise=50n tfall=500n +S7 6 N010 _DE 0 Soff +S8 N002 12 _DE 0 Soff +G14 0 SRONZ 12 9 20µ +C10 SRONZ 0 100f Rpar=2Meg +I3 0 SRONZ 6µ +S13 0 SRONZ 0 DE Soff2 +D4 SRONZ 0 DLSR +G15 0 SPDZ 9 12 1µ +C15 SPDZ 0 100f Rpar=2Meg +I4 SPDZ 0 4µ +S14 0 SPDZ 0 DE Soff2 +D6 SPDZ 0 DLSR +C16 5 vlref 1p Rpar=1Meg +C30 vlref 6 1p Rpar=1Meg +G16 0 DI3 DI2 0 table=(.49 -1u, .51 1u) +C32 DI3 0 1f Rpar=1Meg +A1 7 vlref 0 0 0 0 _SLO 0 SCHMITT vt=0 vh=50m trise=100n +C33 N008 0 1p Rpar=100 +S15 N015 N010 0 _TXslow SMODE1 +C34 12 N005 1p +C35 N012 9 .5p +G17 0 vref 12 0 1m +C19 vref 0 100f Rpar=500 +G18 0 vref 6 0 1m +MZPDRV1 8 N023 N025 N025 PDRV +MZNDRV1 N034 N030 N037 N037 NDRV +C23 N026 0 550f Rpar=1g +S16 VCCGR N026 0 DI3 SDIN +S21 N026 0 DI3 0 SDIN +D8 N026 vrefGR DCLP +S25 12 N023 N026 vrefGRH SDPU +S26 N023 6 vrefGRL N026 SDPD +C37 N042 0 550f Rpar=1g +S27 VCCGR N042 0 DI3 SDIN +S28 N042 0 DI3 0 SDIN +D14 N042 vrefGR DCLN +S29 12 N030 N042 vrefGRH SDNU +S30 N030 6 vrefGRL N042 SDND +C38 N030 6 1p Rpar=1Meg +C39 12 8 1p Rpar=100meg +C40 8 6 1p Rpar=100meg +C41 N023 8 200f +C42 N034 N030 200f +S31 12 N032 0 DI3 SDIN2 +S32 N032 6 DI3 0 SDIN2 +C43 N032 6 1p Rpar=1g +C44 12 N023 1p Rpar=1Meg +D16 12 N036 DBIAS1 +C46 N033 N032 200f Rpar=1.5Meg +G6 0 N028 vref N033 10m +D17 N028 N029 DPPD +D18 N035 N028 DNPU +D19 12 N024 DP +D20 N036 6 DN +S33 N023 N024 0 _TXslow SMODE1 +D21 N024 6 DBIAS1 +S34 0 N035 _TXslow2 0 SMODE3 +S35 0 N029 _TXslow2 0 SMODE3 +C47 N035 0 1p +C48 0 N029 1p +C50 N036 6 1p +C51 12 N024 1p +A7 N029 0 6 6 6 6 N024 6 OTA g=10m linear vlow=0 vhigh=1e308 +A8 N035 0 12 12 12 12 N036 12 OTA g=10m linear vlow=-1e308 vhigh=0 +G20 6 N023 VIlimUY IlimUPY 100m vto=0 dir=1 +I5 0 IlimUPY 15µ +S36 IlimUPY 0 12 8 SIout +G21 0 VIlimDY N037 6 3.8m +I6 0 IlimDNY 15µ +S37 IlimDNY 0 8 6 SIout +G22 N030 12 VIlimDY IlimDNY 100m vto=0 dir=1 +C54 N037 6 1p Rpar=2.6 +C55 IlimUPY 0 10p +C56 IlimDNY 0 10p +G23 0 VIlimUY 12 N025 1m +S38 12 N030 SPDY 0 SPullDwn +D22 12 N025 D1way +S39 12 N025 SRONY 0 SREV +S40 6 N030 _DE 0 Soff +S41 N023 12 _DE 0 Soff +G24 0 SRONY 12 8 20µ +C58 SRONY 0 100f Rpar=2Meg +I7 0 SRONY 6µ +S42 0 SRONY 0 DE Soff2 +D23 SRONY 0 DLSR +G25 0 SPDY 8 12 1µ +C59 SPDY 0 100f Rpar=2Meg +I8 SPDY 0 4µ +S43 0 SPDY 0 DE Soff2 +D24 SPDY 0 DLSR +C60 N028 0 1p Rpar=100 +S44 N036 N030 0 _TXslow SMODE1 +C61 12 N025 1p +C62 N033 8 .5p +D5 9 N013 DNout +D15 8 N034 DNout +C45 N034 6 1p Rpar=10Meg +C49 9 N013 .5p +C53 8 N034 .5p +C63 N005 9 1p +C64 N013 N017 1p +C65 N025 8 1p +C66 N034 N037 1p +A9 _Txfast 0 vrefGR vrefGR vrefGR vrefGR vrefGRH vrefGR SCHMITT vt=.5 trise=5n vlow=0 vhigh=10 +A10 0 _Txfast vrefGR vrefGR vrefGR vrefGR vrefGRL vrefGR SCHMITT vt=-.5 trise=5n vlow=-10 vhigh=0 +A11 2 vlref 0 0 0 N039 0 0 SCHMITT vt=0 vh=50m trise=10n +A12 DEF 0 0 0 0 0 N022 0 BUF Trise=12u Tfall=40n +S46 N021 DEF ON 0 SDelay +A13 N021 0 0 0 N022 _DE DE 0 OR trise=10n +C28 N021 0 1p Rpar=1k +A14 _DE 0 0 0 _SLO 0 _TXslow2 0 OR Rhigh=1k Rlow=600k Cout=1p +A16 5 N057 0 0 0 0 FailSafe 0 SRFLOP trise=6u tfall=10n +A17 N044 0 N047 0 FailSafe 0 N050 0 OR trise=1n ref=.5 vlow=-1 vhigh=1 tripdt=1n +A18 11 10 0 0 0 N056 0 0 SCHMITT vt=-62.5m vh=12.5m trise=10n +S45 5 1 N050 N051 SRO +S47 1 6 N058 N050 SRO +C67 5 1 500f +C68 1 6 500f +A19 N060 0 N061 0 _RE 0 Disable 0 OR trise=5n tripdt=2n +A20 Disable 0 0 0 0 0 N051 0 BUF ref=.5 trise=5n vlow=0 vhigh=1.5 +A21 Disable 0 0 0 0 N058 0 0 BUF ref=.5 trise=5n vlow=-1.5 vhigh=0 +A22 N040 0 0 0 0 0 N043 0 BUF Trise=10u Tfall=5n +S48 N041 N040 ON 0 SDelay +A23 N041 0 0 0 N043 _RE 0 0 OR trise=5n +C70 N041 0 1p Rpar=1k +G7 0 N059 11 6 .5m +G8 0 N059 10 6 .5m +C71 N059 0 100f Rpar=1k +A24 N059 0 0 0 0 0 N060 0 SCHMITT vt=26 vh=100m trise=10n +A25 0 N059 0 0 0 0 N061 0 SCHMITT vt=26 vh=100m trise=10n +S49 6 12 N040 0 SRPOW +S51 6 12 DEF _SLO STPOW2 +A15 N045 N049 0 0 0 0 N047 0 SRFLOP trise=1n ref=.48 vlow=0 vhigh=1 +A26 11 10 0 0 0 0 N048 0 SCHMITT vt=75m vh=0 trise=1n +A27 0 0 N048 0 N045 0 N046 0 DFLOP trise=10n tfall=1n +A28 N046 0 0 0 0 0 N045 0 BUF trise=76n tfall=5n +A29 10 11 0 0 0 0 N055 0 SCHMITT vt=75m vh=0 trise=1n +A30 0 0 N055 0 N049 0 N052 0 DFLOP trise=10n tfall=1n +A31 N052 0 0 0 0 0 N049 0 BUF trise=76n tfall=5n +A32 11 10 0 0 0 0 N044 0 SCHMITT vt=75m vh=0 trise=500u tfall=1n +A33 _RE 0 0 0 _DE ON 0 0 AND trise=5n tfall=80n +S50 6 12 DEF 0 STPOW1 +D25 6 5 ESDL +D26 6 4 ESDL +D27 6 3 ESDL +D28 6 7 ESDL +D29 6 2 ESDL +D30 6 11 ESDH +D31 6 10 ESDH +C29 11 6 500f Rpar=112k +C36 10 6 500f Rpar=112k +D32 6 8 ESDH +D33 6 1 ESDL +D34 6 9 ESDH +C57 VIlimUY 0 100f Rpar=10k +C52 VIlimDY 0 100f Rpar=10k +A34 N056 0 0 0 _RE 0 N057 0 OR trise=5n tripdt=2n +ADI 4 vlref 0 0 0 0 DI2 0 SCHMITT vt=0 vh=50m trise=10n +AVL 5 6 0 0 0 0 VLgood 0 SCHMITT vt=0.95 vh=50m trise=10n +ADE N020 0 0 0 VLgood 0 DEF 0 AND trise=10n +ARE N039 0 0 0 VLgood 0 N040 0 AND trise=5n +ASX DE _RE _SLO 0 0 SLex 0 0 OR trise=5n +SLX 6 12 SLex 0 SLEXPOW +.model PDRV VDMOS(vto=-700m kp=400m mtriode=.3 rd=500m lambda=.1 subthres=5u is=0 pchan) +.model NDRV VDMOS(vto=700m kp=210m mtriode=.7 rd=1.2 lambda=.05 subthres=5u is=0) +.model DCLP D(Ron=10 Roff=1g vfwd=600m epsilon=100m vrev=500m epsilon=100m) +.model SDIN SW(Ron=100k Roff=1g vt=-100m vh=-200m) +.model SDIN2 SW(Ron=1k Roff=1g vt=-100m vh=-200m) +.model SDPU SW(Ron=5k Roff=1G vt=0 vh=-100m) +.model SDPD SW(Ron=4k Roff=1G vt=0 vh=-100m) +.model DCLN D(Ron=10 Roff=1g vfwd=550m epsilon=100m vrev=490m epsilon=100m) +.model SDNU SW(Ron=8k Roff=1G vt=0 vh=-100m) +.model SDND SW(Ron=4k Roff=1G vt=0 vh=-100m) +.model DP D(Ron=150k Roff=1g vfwd=660m epsilon=500m) +.model DN D(Ron=400k Roff=1g vfwd=550m epsilon=900m) +.model ESDL D(Ron=60 Roff=1g vfwd=700m epsilon=500m vrev=10 revepsilon=500m) +.model ESDH D(Ron=60 Roff=1g vfwd=62 epsilon=1 vrev=62 revepsilon=1) +.model SIout SW(Ron=20k Roff=1Meg vt=30 vh=-20) +.model SMODE1 SW(level=2 Ron=1 Roff=1g vt=-.5 vh=-.2) +.model SMODE3 SW(Ron=.1 Roff=1k vt=.5 vh=-.5) +.model Sdelay SW(Ron=1 Roff=1g vt=.5 vh=-.2) +.model SREV SW(level=2 Ron=.1 Roff=10Meg vt=1 vh=-.1 ilimit=50m oneway epsilon=100m) +.model D1way D(Ron=10 Roff=10 vfwd=0 vrev=0 revilimit=1u) +.model SPullDwn SW(Ron=100 Roff=1g vt=1 vh=-1 ilimit=10m) +.model Soff SW(Ron=1 Roff=1Meg vt=.5 vh=-.2) +.model Soff2 SW(Ron=1 Roff=2Meg vt=-.5 vh=-.2) +.model DLSR D(Ron=1 Roff=10Meg vfwd=2 epsilon=500m vrev=2 revepsilon=500m) +.model SRPOW SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=793u) +.model STPOW1 SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=62u) +.model STPOW2 SW(Ron=10 Roff=1g vt=.5 vh=-.2 ilimit=2.2m) +.model SLEXPOW SW(Ron=100 Roff=1g vt=.5 vh=-.4 ilimit=260u) +.model SRO SW(Ron=125 Roff=1g vt=-100m vh=-200m ilimit=20m) +.model DPPD D(ron=200k Roff=100g vfwd=-160m epsilon=100m ilimit=10u) +.model DNPU D(ron=200k Roff=100g vfwd=-160m epsilon=100m ilimit=10u) +.model DBIAS1 D(Ron=100k Roff=1g vfwd=100m epsilon=100m ilimit=1u) +.model DNout D(Ron=1.1 Roff=1g vfwd=450m epsilon=500m) +.ends LTC2865 diff --git a/spice/copy/sub/LTC2900-1.sub b/spice/copy/sub/LTC2900-1.sub new file mode 100755 index 0000000..d677956 Binary files /dev/null and b/spice/copy/sub/LTC2900-1.sub differ diff --git a/spice/copy/sub/LTC2900-2.sub b/spice/copy/sub/LTC2900-2.sub new file mode 100755 index 0000000..9914128 Binary files /dev/null and b/spice/copy/sub/LTC2900-2.sub differ diff --git a/spice/copy/sub/LTC2902-1.sub b/spice/copy/sub/LTC2902-1.sub new file mode 100755 index 0000000..4c053fc Binary files /dev/null and b/spice/copy/sub/LTC2902-1.sub differ diff --git a/spice/copy/sub/LTC2902-2.sub b/spice/copy/sub/LTC2902-2.sub new file mode 100755 index 0000000..1f61b62 Binary files /dev/null and b/spice/copy/sub/LTC2902-2.sub differ diff --git a/spice/copy/sub/LTC2903-A1.sub b/spice/copy/sub/LTC2903-A1.sub new file mode 100755 index 0000000..49dca3b Binary files /dev/null and b/spice/copy/sub/LTC2903-A1.sub differ diff --git a/spice/copy/sub/LTC2903-B1.sub b/spice/copy/sub/LTC2903-B1.sub new file mode 100755 index 0000000..10a2656 Binary files /dev/null and b/spice/copy/sub/LTC2903-B1.sub differ diff --git a/spice/copy/sub/LTC2903-C1.sub b/spice/copy/sub/LTC2903-C1.sub new file mode 100755 index 0000000..88ac206 Binary files /dev/null and b/spice/copy/sub/LTC2903-C1.sub differ diff --git a/spice/copy/sub/LTC2903-D1.sub b/spice/copy/sub/LTC2903-D1.sub new file mode 100755 index 0000000..20e15f7 Binary files /dev/null and b/spice/copy/sub/LTC2903-D1.sub differ diff --git a/spice/copy/sub/LTC2903-E1.sub b/spice/copy/sub/LTC2903-E1.sub new file mode 100755 index 0000000..f2ebc53 Binary files /dev/null and b/spice/copy/sub/LTC2903-E1.sub differ diff --git a/spice/copy/sub/LTC2904.sub b/spice/copy/sub/LTC2904.sub new file mode 100755 index 0000000..64eb9e2 Binary files /dev/null and b/spice/copy/sub/LTC2904.sub differ diff --git a/spice/copy/sub/LTC2905.sub b/spice/copy/sub/LTC2905.sub new file mode 100755 index 0000000..5f7352c Binary files /dev/null and b/spice/copy/sub/LTC2905.sub differ diff --git a/spice/copy/sub/LTC2906.sub b/spice/copy/sub/LTC2906.sub new file mode 100755 index 0000000..c1edd81 Binary files /dev/null and b/spice/copy/sub/LTC2906.sub differ diff --git a/spice/copy/sub/LTC2907.sub b/spice/copy/sub/LTC2907.sub new file mode 100755 index 0000000..1e82974 Binary files /dev/null and b/spice/copy/sub/LTC2907.sub differ diff --git a/spice/copy/sub/LTC2908-A1.sub b/spice/copy/sub/LTC2908-A1.sub new file mode 100755 index 0000000..e7576c3 Binary files /dev/null and b/spice/copy/sub/LTC2908-A1.sub differ diff --git a/spice/copy/sub/LTC2908-B1.sub b/spice/copy/sub/LTC2908-B1.sub new file mode 100755 index 0000000..37f4047 Binary files /dev/null and b/spice/copy/sub/LTC2908-B1.sub differ diff --git a/spice/copy/sub/LTC2908-C1.sub b/spice/copy/sub/LTC2908-C1.sub new file mode 100755 index 0000000..e72896a Binary files /dev/null and b/spice/copy/sub/LTC2908-C1.sub differ diff --git a/spice/copy/sub/LTC2909-25.sub b/spice/copy/sub/LTC2909-25.sub new file mode 100755 index 0000000..f46c9fc Binary files /dev/null and b/spice/copy/sub/LTC2909-25.sub differ diff --git a/spice/copy/sub/LTC2909-33.sub b/spice/copy/sub/LTC2909-33.sub new file mode 100755 index 0000000..222a7c3 Binary files /dev/null and b/spice/copy/sub/LTC2909-33.sub differ diff --git a/spice/copy/sub/LTC2909-50.sub b/spice/copy/sub/LTC2909-50.sub new file mode 100755 index 0000000..3e5ac41 Binary files /dev/null and b/spice/copy/sub/LTC2909-50.sub differ diff --git a/spice/copy/sub/LTC2910.sub b/spice/copy/sub/LTC2910.sub new file mode 100755 index 0000000..5fec9eb Binary files /dev/null and b/spice/copy/sub/LTC2910.sub differ diff --git a/spice/copy/sub/LTC2912-1.sub b/spice/copy/sub/LTC2912-1.sub new file mode 100755 index 0000000..c9bca73 Binary files /dev/null and b/spice/copy/sub/LTC2912-1.sub differ diff --git a/spice/copy/sub/LTC2912-2.sub b/spice/copy/sub/LTC2912-2.sub new file mode 100755 index 0000000..f71bdcd Binary files /dev/null and b/spice/copy/sub/LTC2912-2.sub differ diff --git a/spice/copy/sub/LTC2912-3.sub b/spice/copy/sub/LTC2912-3.sub new file mode 100755 index 0000000..d3c134d Binary files /dev/null and b/spice/copy/sub/LTC2912-3.sub differ diff --git a/spice/copy/sub/LTC2913-1.sub b/spice/copy/sub/LTC2913-1.sub new file mode 100755 index 0000000..4f69a6d Binary files /dev/null and b/spice/copy/sub/LTC2913-1.sub differ diff --git a/spice/copy/sub/LTC2913-2.sub b/spice/copy/sub/LTC2913-2.sub new file mode 100755 index 0000000..507119c Binary files /dev/null and b/spice/copy/sub/LTC2913-2.sub differ diff --git a/spice/copy/sub/LTC2914-1.sub b/spice/copy/sub/LTC2914-1.sub new file mode 100755 index 0000000..612bcc0 Binary files /dev/null and b/spice/copy/sub/LTC2914-1.sub differ diff --git a/spice/copy/sub/LTC2914-2.sub b/spice/copy/sub/LTC2914-2.sub new file mode 100755 index 0000000..9a73a6f Binary files /dev/null and b/spice/copy/sub/LTC2914-2.sub differ diff --git a/spice/copy/sub/LTC2919-25.sub b/spice/copy/sub/LTC2919-25.sub new file mode 100755 index 0000000..232c439 Binary files /dev/null and b/spice/copy/sub/LTC2919-25.sub differ diff --git a/spice/copy/sub/LTC2919-33.sub b/spice/copy/sub/LTC2919-33.sub new file mode 100755 index 0000000..150a0ae Binary files /dev/null and b/spice/copy/sub/LTC2919-33.sub differ diff --git a/spice/copy/sub/LTC2919-50.sub b/spice/copy/sub/LTC2919-50.sub new file mode 100755 index 0000000..1d11aae Binary files /dev/null and b/spice/copy/sub/LTC2919-50.sub differ diff --git a/spice/copy/sub/LTC2920-1.sub b/spice/copy/sub/LTC2920-1.sub new file mode 100755 index 0000000..7e4d5a7 Binary files /dev/null and b/spice/copy/sub/LTC2920-1.sub differ diff --git a/spice/copy/sub/LTC2920-2.sub b/spice/copy/sub/LTC2920-2.sub new file mode 100755 index 0000000..53a889c Binary files /dev/null and b/spice/copy/sub/LTC2920-2.sub differ diff --git a/spice/copy/sub/LTC2921-2.5.sub b/spice/copy/sub/LTC2921-2.5.sub new file mode 100755 index 0000000..5355409 Binary files /dev/null and b/spice/copy/sub/LTC2921-2.5.sub differ diff --git a/spice/copy/sub/LTC2921-3.3.sub b/spice/copy/sub/LTC2921-3.3.sub new file mode 100755 index 0000000..e098609 Binary files /dev/null and b/spice/copy/sub/LTC2921-3.3.sub differ diff --git a/spice/copy/sub/LTC2921.sub b/spice/copy/sub/LTC2921.sub new file mode 100755 index 0000000..a1326c5 Binary files /dev/null and b/spice/copy/sub/LTC2921.sub differ diff --git a/spice/copy/sub/LTC2922-2.5.sub b/spice/copy/sub/LTC2922-2.5.sub new file mode 100755 index 0000000..3af7046 Binary files /dev/null and b/spice/copy/sub/LTC2922-2.5.sub differ diff --git a/spice/copy/sub/LTC2922-3.3.sub b/spice/copy/sub/LTC2922-3.3.sub new file mode 100755 index 0000000..30461d4 Binary files /dev/null and b/spice/copy/sub/LTC2922-3.3.sub differ diff --git a/spice/copy/sub/LTC2922.sub b/spice/copy/sub/LTC2922.sub new file mode 100755 index 0000000..4ac89be Binary files /dev/null and b/spice/copy/sub/LTC2922.sub differ diff --git a/spice/copy/sub/LTC2923.sub b/spice/copy/sub/LTC2923.sub new file mode 100755 index 0000000..6c63fcc Binary files /dev/null and b/spice/copy/sub/LTC2923.sub differ diff --git a/spice/copy/sub/LTC2924.sub b/spice/copy/sub/LTC2924.sub new file mode 100755 index 0000000..9dc2b8e Binary files /dev/null and b/spice/copy/sub/LTC2924.sub differ diff --git a/spice/copy/sub/LTC2925.lib b/spice/copy/sub/LTC2925.lib new file mode 100755 index 0000000..2062277 --- /dev/null +++ b/spice/copy/sub/LTC2925.lib @@ -0,0 +1,18044 @@ +* LTspice Encrypted File +* +* This encrypted file has been supplied by a 3rd +* party vendor that does not wish to publicize +* the technology used to implement this library. +* +* Permission is granted to use this file for +* simulations but not to reverse engineer its +* contents. +* +* Begin: + 47 2F F1 69 82 7E E8 61 69 74 B1 36 60 43 79 B9 + 63 E9 6B 09 C9 42 20 96 0C 59 95 47 46 E6 68 3C + ED 42 CA 2A 84 06 01 90 C6 0E 17 68 40 7D D9 BA + 5A 67 A9 EE B3 20 3D A6 19 46 58 5D FD 0D 17 8A + 7D CD 5C C5 11 A6 26 6F 75 B7 B9 EF 5C 86 D6 E1 + EE B7 7A E6 B5 4A C3 6E 1B 75 E3 D1 7C 90 72 61 + 4D 93 FD 7B FE D1 39 42 A8 E8 C7 6E 46 0C 5E EB + 1B 2B FA 7F 25 B2 27 10 38 63 E4 3E 8F CE FA BA + 71 15 22 06 C2 1A EA 3E 34 EC D2 89 32 E5 0A 91 + A7 C3 D5 5C BB 89 11 CC 11 63 1A 50 6C AD 10 15 + F8 B5 55 73 60 CF AD DA 84 C4 89 A5 AD 59 A2 B2 + D7 97 08 9E 87 C4 8A B8 48 E1 90 80 8A 69 0C 37 + 84 A4 AB 55 32 42 2B 5F DA BE 78 AC 3A 51 41 CA + 22 98 2C 41 1C 8A 37 D9 8F 61 32 DE C2 BA 23 3F + 8B F1 3A 6F 08 B0 07 A6 64 62 43 53 23 B9 5C 8F + 9B 23 0E 30 7D B4 E1 3C 2C 40 70 70 DC B5 D6 7E + D7 C9 BE 6E 9E E5 80 1C 8A 3B 7B 63 E9 39 1A 09 + 97 3F E0 8D C1 CE B9 71 EC C6 0F 66 1B 5F 36 DA + 11 A7 3D 38 54 11 66 28 48 22 31 E0 C9 A9 1A 5A + 2F C6 EC 87 73 71 AE D1 01 48 15 4F 85 88 DE DE + 7A 09 47 9D B0 CA 5B 0B 1F 11 85 3A 88 F2 44 F6 + B6 9E CD 40 12 35 1D 92 F7 70 ED 1E F8 57 59 DF + 59 06 4E 57 EA 11 5E AD D6 2E F6 8A EC F4 73 08 + 97 1C 36 1E 66 68 5D 09 5D 94 C8 C0 E0 AF 23 61 + 95 93 29 F0 47 49 7E 94 4F E4 7A 60 18 B6 89 22 + 30 C2 6E 96 E5 8F 33 00 C1 8A C6 62 5E 68 30 2A + 2B F4 7B 27 F6 89 BE 9E 98 A7 43 20 16 30 9B 8C + C2 A1 64 25 37 C1 C9 81 1E E9 65 38 4C A8 01 4A + DF 72 D7 BF EE 02 69 4F 5C 2B A7 41 1E 9B EA AB + BE 63 B7 73 3B DD 03 45 2A C9 4F F9 FE 9D 62 61 + F0 C3 C2 E1 D8 53 45 30 CE 8F 4F 1E A8 EE D2 65 + 76 2C C7 8D 3D 6B BF B9 F3 17 35 A7 2B 44 4C E7 + 53 2F 51 F5 AC 6E F5 A5 53 30 54 23 07 AF AF E9 + 4F CB B9 F5 44 92 0D 54 E2 64 DC A9 E9 52 2D 62 + 84 A0 7C 2B 34 07 63 1A FE 17 49 A1 7D 36 26 8C + 7B A8 69 98 FB 32 F1 F7 E7 AE 92 41 99 A1 DF FE + 2E FF AA 4B 0F 2D FF 18 4C 7E 46 34 77 7C AB 8C + 78 5F 5C 1E 80 D3 07 BE E7 0E 15 3F C6 E3 34 DC + 71 19 7B 05 D6 88 49 F6 F9 79 0E 58 09 AF 8A C3 + 41 8D C9 05 FE 82 BA 49 10 6D 3F DA 2B E7 6B F4 + CB 7B B6 66 54 9B 6B E8 F8 47 3A 58 CE 98 A7 82 + D2 02 2A B2 EC 35 14 B0 C5 08 70 89 C7 90 50 C5 + 9E D1 4B A8 DF 21 FF 6F 87 1A F4 11 EC 48 2E 19 + B6 48 4A 3F 96 6C 41 BE 3B 73 7B DC E4 C8 67 A3 + 0B 20 4F 38 F4 84 AC 89 D7 43 7F 8B D8 43 44 B2 + 48 77 FD 2A B9 E5 0C A3 28 08 55 B1 51 83 F1 84 + EC 1D 4D 9E 2B CF 5C AB 83 B1 2E 5A AB 92 5D C7 + D7 9E 82 D1 EF 09 B1 31 22 00 0C C4 4E D2 80 CC + 6E FA E3 9E C9 1E 98 86 E4 EC 38 AA BA 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99 6B 3D + 7C C2 C4 00 B5 E3 F2 64 66 35 8C D3 59 63 27 ED + 49 8C BD C6 49 2D 11 2B 89 84 04 E0 E4 8D F6 06 + 2E C8 98 0D 0A 7F D4 5F FD C0 02 A9 FA 29 39 C6 + 53 B7 EC 4C 2F 90 E8 35 94 8B 66 57 53 82 9F 11 + 99 AE 99 52 41 C7 A1 99 40 01 4F DC F2 58 E1 E9 + 80 D5 DB 86 32 89 07 A3 4D D1 55 44 46 11 F7 83 + 5E 5F EC F3 0A E1 FC C1 22 CD 8E 70 D6 90 68 E8 + 35 8B 63 65 1D EB 01 FA 31 50 31 F8 6D 72 0F 21 + 31 D4 E9 72 C9 97 34 1B 0D 34 D0 EA 9B 40 47 49 + 7F 60 03 8F 00 7F 35 D5 A3 ED FD 92 49 7C 6C A3 + FF 4F 6B 0F 90 5E 7C F5 8A 01 A6 64 38 EC BA 63 + 9A 04 21 80 CA 52 C5 7E 63 64 B7 38 14 9A BA 4F + EA D2 3E AB 26 CA 27 03 93 4D 8F 2E 2C E6 0F 4F + 84 D3 25 99 F6 89 E3 83 FF 7C B4 97 B9 7D 47 28 + 87 17 FB 6B 65 72 33 33 BB B8 8C 64 AF CA A6 A0 + BB 39 C0 91 5E 86 91 EF 65 3C B4 68 9F 81 5A 34 + ED FD 15 F0 7A D4 B3 AE A0 BB 64 62 2F 6D DE B0 + 15 E3 1A 33 8B EE 0C C3 E4 94 CF 6F C6 C5 9F F2 + CC EB FC C6 46 77 66 4C 47 6C 8D CF 48 0B 24 16 + C6 6D 97 88 80 FE 1D 76 95 7D 27 FC 8F A0 EF B9 + 03 61 D2 ED 80 CA 89 A0 58 04 40 7E 3A 1D 87 8E + 7F 0F DF E9 F2 7F A9 AB AE AD CC B1 0A D3 D8 EE + 9C 69 34 16 A3 38 82 E4 +* End 277504229 2198575446 \ No newline at end of file diff --git a/spice/copy/sub/LTC2926.sub b/spice/copy/sub/LTC2926.sub new file mode 100755 index 0000000..1bafbc8 Binary files /dev/null and b/spice/copy/sub/LTC2926.sub differ diff --git a/spice/copy/sub/LTC2927.sub b/spice/copy/sub/LTC2927.sub new file mode 100755 index 0000000..43f6ecb Binary files /dev/null and b/spice/copy/sub/LTC2927.sub differ diff --git a/spice/copy/sub/LTC2930.sub b/spice/copy/sub/LTC2930.sub new file mode 100755 index 0000000..31ea17f Binary files /dev/null and b/spice/copy/sub/LTC2930.sub differ diff --git a/spice/copy/sub/LTC2932.sub b/spice/copy/sub/LTC2932.sub new file mode 100755 index 0000000..8d84b2e Binary files /dev/null and b/spice/copy/sub/LTC2932.sub differ diff --git a/spice/copy/sub/LTC2934-1.sub b/spice/copy/sub/LTC2934-1.sub new file mode 100755 index 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/dev/null and b/spice/copy/sub/LTC2997.sub differ diff --git a/spice/copy/sub/LTC3.lib b/spice/copy/sub/LTC3.lib new file mode 100755 index 0000000..7f0bc78 --- /dev/null +++ b/spice/copy/sub/LTC3.lib @@ -0,0 +1,2365 @@ +* Copyright © Linear Technology Corp. 2005-2015. All rights reserved. +* +.subckt LT1004-1.2 1 2 +R2 1 N007 550k Tc2=2e-5 noiseless +Q14 2 2 N007 0 PNP1 Temp=27 +Q4 N004 N004 N003 0 PNP1 Temp=27 +R6 1 N003 7.5k noiseless +Q3 N005 N004 1 0 PNP1 M=10 Temp=27 +R8 N005 2 500k noiseless +Q1 1 N005 2 0 NPN1 M=10 Temp=27 +C1 N004 N005 20p +S1 C 0 2 1 SOFF +Q2 N008 N008 2 0 NPN1 Temp=27 +R4 1 N008 600k noiseless +Q5 N006 N008 N010 0 NPN1 Temp=27 +R5 N010 2 60k noiseless +Q6 N004 N006 N009 0 NPN1 Temp=27 +R7 N009 2 500 noiseless +QNN1 N006 D 1 0 PNP1 Temp=27 +C3 D N006 20p +D1 1 2 DBURN +D2 2 1 DFOR Temp=27 +A1 N007 1 0 0 0 0 C 0 OTA g=100n linear ref=-629.08639m en=360n*(1+5e-7*freq**1.5)/(1+1e-7*freq**1.5) enk=9 Rout=1Meg Cout=100f vlow=-100m vhigh=10 +B1 D 2 I=(5u*V(C))*(.5+.5*tanh((V(D,2)-50m)/10m))*(.5+.5*tanh((V(1,D)-100m)/10m)) +C2 D 2 1p Rpar=100Meg noiseless +C4 N008 2 700f +.model DBURN D(Ron=80k Roff=100Meg vfwd=600m epsilon=500m noiseless) +.model DFOR D(IS=1e-11 Rs=10 N=1.2) +.model SOFF SW(Ron=1 Roff=200Meg vt=-600m vh=600m noiseless) +.model NPN1 NPN(BF=120 VAF=100 TF=1n IKF=5m CJC=.1p CJE=.1p noiseless) +.model NPN2 NPN(BF=120 VAF=100 TF=1n IKF=5m CJC=.1p CJE=1p noiseless) +.model PNP1 PNP(Bf=40 VAF=100 TF=10n IKF=1m CJC=.1p CJE=.1p noiseless) +.ends LT1004-1.2 +* +.subckt LT1004-2.5 1 2 +R2 1 N007 550k Tc1=-4e-4 Tc2=2.6e-5 noiseless +Q14 2 N010 N007 0 PNP1 Temp=27 +Q4 N004 N004 N003 0 PNP1 Temp=27 +R6 1 N003 7.5k noiseless +Q3 N005 N004 1 0 PNP1 Temp=27 +R8 N005 2 500k noiseless +Q1 1 N005 2 0 NPN1 M=10 Temp=27 +C1 N004 N005 20p +S1 C 0 2 1 SOFF +A2 N007 1 0 0 0 0 C 0 OTA g=100n linear ref=-645.55448m en=360n enk=10 Rout=10Meg Cout=400f vlow=-10 vhigh=10 +Q2 N008 N008 2 0 NPN1 Temp=27 +R4 1 N008 600k noiseless +Q5 N006 N008 N011 0 NPN1 Temp=27 +R5 N011 2 60k noiseless +Q6 N004 N006 N009 0 NPN1 Temp=27 +R7 N009 2 500 noiseless +QNN1 N006 D 1 0 PNP1 Temp=27 +C3 D N006 20p +B1 D 2 I=(2u*V(C))*(.5+.5*tanh((V(D,2)-50m)/10m))*(.5+.5*tanh((V(1,D)-100m)/10m)) +C4 D 2 1p Rpar=100Meg noiseless +D1 1 2 DBURN +D2 2 1 DFOR Temp=27 +R1 1 N010 500k noiseless +R10 N010 2 500k noiseless +D3 0 C DTRAN Temp=27 +.model NPN1 NPN(BF=120 VAF=100 TF=1n IKF=5m CJC=.1p CJE=.1p noiseless) +.model PNP1 PNP(Bf=40 VAF=100 TF=10n IKF=1m CJC=.1p CJE=.1p noiseless) +.model DTRAN D(IS=1e-12 TT=100u noiseless) +.model DBURN D(Ron=500k Roff=100Meg vfwd=600m epsilon=500m noiseless) +.model DFOR D(IS=1e-11 Rs=10 N=1.2) +.model SOFF SW(Ron=1 Roff=200Meg vt=-600m vh=-600m noiseless) +.ends LT1004-2.5 +* +.subckt LT1009 1 2 3 +M1 1 N005 2 2 N temp=27 +C3 1 2 10p +R1 1 N003 100K tc2=-.6u noiseless +C1 N003 2 17.5f Rser=28.6K Rpar=100K noiseless +G1 2 N005 N003 2 10µ +C2 N005 2 .1p Rpar=100K Rser=5K noiseless +R2 N004 3 30K noiseless +D1 2 1 Y +R6 1 N004 7K noiseless +R7 N004 2 7K noiseless +G2 2 N003 N004 3 1.1µ +.model N VDMOS(Vto=1.25 Kp=10K Is=0) +.model Y D(Ron=.4 Roff=10Meg Vfwd=.6 epsilon=.5 noiseless) +.ends LT1009 +* +.subckt LT1021-5 1 2 3 4 +A1 3 N007 2 2 2 2 N005 2 OTA g=50u Iout=50u Cout=10p Vlow=-10 Vhigh=100 Rout=5G Ref=5 +M1 N002 N003 3 3 N temp=27 +M2 2 N003 3 3 P temp=27 +C7 N002 3 5p +C8 3 2 5p +D1 1 N002 1V +D2 2 N005 X +G1 2 N003 N005 2 10µ +C4 N003 2 2p Rser=20K Rpar=100K noiseless +D3 N003 3 Y +A2 1 2 2 2 2 2 N004 2 SCHMITT Vt=2.5 Vh=1m Trise=100n +S1 N003 3 2 N004 O +C2 N002 2 10p Rpar=250K noiseless +D5 N002 2 Q +C3 1 2 10p +G2 N005 2 N005 1 1m Vto=5 dir=1 +C1 4 2 1p +G3 2 N007 4 N010 1µ +G4 2 N007 4 3 1µ +C5 N007 2 1p Rpar=66K +R1 3 4 100K noiseless +R2 4 N010 100K noiseless +R3 N010 2 300K tc1=-3.6m tc2=6u noiseless +.model X D(Ron=10K Roff=1T Vfwd=-1 epsilon=.1 noiseless) +.model 1V D(Ron=10 Roff=1T Vfwd=.8 epsilon=.2 noiseless) +.model Y D(Ron=100 Roff=1G epsilon=.3 Vfwd=.6 Vrev=.6 revepsilon=.3 noiseless) +.model Z D(Ron=100 Roff=1G epsilon=1 noiseless) +.model Q D(Ron=1K Roff=1K Ilimit=.8m noiseless) +.model N VDMOS(Vto=-3m Kp=.1) +.model P VDMOS(Vto=3m Kp=.1 pchan) +.model O SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4 noiseless) +.ends LT1021-5 +* +.subckt LT1021-7 1 2 3 +A1 3 2 2 2 2 2 N005 2 OTA g=50u Iout=50u Cout=10p Vlow=-10 Vhigh=100 Rout=5G Ref=7 +M1 N002 N003 3 3 N temp=27 +M2 2 N003 3 3 P temp=27 +C7 N002 3 5p +C8 3 2 5p +D1 1 N002 1V +D2 2 N005 X +G1 2 N003 N005 2 10µ +C4 N003 2 2p Rser=20K Rpar=100K noiseless +D3 N003 3 Y +A2 1 2 2 2 2 2 N004 2 SCHMITT Vt=2.5 Vh=1m Trise=100n +S1 N003 3 2 N004 O +C2 N002 2 10p Rpar=250K +D5 N002 2 Q +C3 1 2 10p +G2 N005 2 N005 1 1m Vto=5 dir=1 +D4 3 1 Z +.model X D(Ron=10K Roff=1T Vfwd=-1 epsilon=.1 noiseless) +.model 1V D(Ron=10 Roff=1T Vfwd=.8 epsilon=.2 noiseless) +.model Y D(Ron=100 Roff=1G epsilon=.3 Vfwd=.6 Vrev=.6 revepsilon=.3 noiseless) +.model Z D(Ron=100 Roff=1G epsilon=1 noiseless) +.model Q D(Ron=1K Roff=1K Ilimit=.8m noiseless) +.model N VDMOS(Vto=-3m Kp=.1) +.model P VDMOS(Vto=3m Kp=.1 pchan) +.model O SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4 noiseless) +.ends LT1021-7 +* +.subckt LT1021-10 1 2 3 4 +A1 3 N007 2 2 2 2 N005 2 OTA g=50u Iout=50u Cout=10p Vlow=-10 Vhigh=100 Rout=5G Ref=10 +M1 N002 N003 3 3 N temp=27 +M2 2 N003 3 3 P temp=27 +C7 N002 3 5p +C8 3 2 5p +D1 1 N002 1V +D2 2 N005 X +G1 2 N003 N005 2 10µ +C4 N003 2 2p Rser=20K Rpar=100K noiseless +D3 N003 3 Y +A2 1 2 2 2 2 2 N004 2 SCHMITT Vt=2.5 Vh=1m Trise=100n +S1 N003 3 2 N004 O +C2 N002 2 10p Rpar=250K noiseless +D5 N002 2 Q +C3 1 2 10p +G2 N005 2 N005 1 1m Vto=5 dir=1 +D4 3 1 Z +C1 4 2 1p +R1 3 4 24K noiseless +G3 2 N007 4 2 1µ +G4 2 N007 4 3 1µ +C5 N007 2 1p Rpar=10.4K +R2 4 2 24K noiseless +.model X D(Ron=10K Roff=1T Vfwd=-1 epsilon=.1 noiseless) +.model 1V D(Ron=10 Roff=1T Vfwd=.8 epsilon=.2 noiseless) +.model Y D(Ron=100 Roff=1G epsilon=.3 Vfwd=.6 Vrev=.6 revepsilon=.3 noiseless) +.model Z D(Ron=100 Roff=1G epsilon=1 noiseless) +.model Q D(Ron=1K Roff=1K Ilimit=.8m noiseless) +.model N VDMOS(Vto=-3m Kp=.1) +.model P VDMOS(Vto=3m Kp=.1 pchan) +.model O SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4 noiseless) +.ends LT1021-10 +* +.subckt LT1789-1 1 2 3 4 5 6 7 8 +R6 A2out 8 100k noiseless +R8 1 A1out 100k noiseless +Q1 N009 N004 8 0 PNP1 Temp=27 +D1 7 8 D1p7u +Q2 N022 N019 1 0 PNP1 Temp=27 +D2 7 1 D1p7u +C1 N009 4 1p Rpar=50k noiseless +R1 A2out VINM 110k noiseless +R2 A1out VINP 110k noiseless +C7 7 8 1p +C8 7 1 1p +C9 7 A2out 500f +M1 7 N002 A2out A2out NINT temp=27 +M2 4 N002 A2out A2out PINT temp=27 +R9 7 N002 20Meg noiseless +R10 N002 4 20Meg noiseless +G1 N002 0 N002 7 500m dir=1 vto=-250m +G2 0 N002 4 N002 500m dir=1 vto=-50m +M3 7 N021 A1out A1out NINT temp=27 +M4 4 N021 A1out A1out PINT temp=27 +R11 7 N021 20Meg noiseless +R12 N021 4 20Meg noiseless +G3 N021 0 N021 7 500m dir=1 vto=-250m +G4 0 N021 4 N021 500m dir=1 vto=-50m +A3 N011 0 0 0 0 0 N002 0 OTA g=20m iout=500u Cout=8n Vhigh=1e308 Vlow=-1e308 +C5 A2out N011 24p +A2 4 N022 0 0 0 0 N017 0 OTA g=18u linear Ref=-85m en=100n enk=1.5 Rout=100k Cout=1p vlow=-1e308 vhigh=1e308 +A4 N017 0 0 0 0 0 N021 0 OTA g=20m iout=500u Cout=8n Vhigh=1e308 Vlow=-1e308 +C13 A1out N017 24p +C15 A2out 4 500f +C16 7 A1out 500f +C17 A1out 4 500f +C10 7 VINM 500f +C11 VINM 4 500f +C12 7 VINP 500f +C18 VINP 4 500f +R15 VINM 6 110k noiseless +R16 VINP 5 110k noiseless +A6 4 N009 0 0 0 0 N011 0 OTA g=18u linear Ref=-85m en=100n enk=1.5 Rout=100k Cout=1p vlow=-1e308 vhigh=1e308 +A1 2 3 0 0 0 0 0 0 OTA g=0 in=57f ink=170 +M5 6 N023 4 4 NI temp=27 +C3 7 6 1p Rpar=10Meg noiseless +M6 6 N006 N005 N005 PI temp=27 +C4 7 N006 1p Rser=6Meg noiseless +A5 N010 N013 4 4 4 4 N006 4 OTA g=35n ref=-.0222 linear vlow=-1e308 vhigh=1e308 +C6 6 4 1p Rpar=10Meg noiseless +C14 N023 4 1p Rser=6Meg noiseless +D3 N023 4 DLIMN +A7 N008 0 N010 N010 N010 N010 N013 N010 OTA g=7u asym isink=-310n isrc=230n Cout=100f Vlow=-1e308 Vhigh=1e308 +G5 4 N023 N013 N010 5n +D4 7 N006 DLIMP +G6 0 N010 7 0 .5m +G7 0 N010 4 0 .5m +C20 N010 0 1p noiseless Rpar=1k +D5 N013 N010 DLIM1 +CG1 N008 0 3p Rpar=1Meg Rser=600k noiseless +B1 0 N003 I=10u*dnlim(uplim(V(VINP),V(7)-.58,.1), V(4)-.15, .1)+1n*V(VINP)-189.42p +B2 N003 0 I=10u*dnlim(uplim(V(VINM),V(7)-.57,.1), V(4)-.16, .1)+1n*V(VINM) +C21 N003 0 10p Rpar=100K noiseless +A9 0 N003 0 0 0 0 N008 0 OTA g=1u linear en=20n enk=1.9 Vhigh=1e308 Vlow=-1e308 +G8 7 N006 6 7 100µ vto=-200m dir=1 +R13 7 N005 1 noiseless +G10 7 N006 7 N005 20m vto=.2m dir=1 +G9 N023 4 4 6 100µ vto=-80m dir=1 +C22 6 N013 10p +D6 7 4 Dburn +S3 N009 4 4 2 SINRA +C19 N022 4 1p Rpar=50k noiseless +S4 N022 4 4 3 SINRA +D7 2 7 DESD +D8 4 2 DESD +D9 3 7 DESD +D10 4 3 DESD +D11 4 5 DESD +D12 5 7 DESD +D13 N020 7 DESD +D14 4 N020 DESD +R3 N004 2 10 noiseless +A8 2 N004 0 0 0 0 0 0 OTA g=0 in=2.5n ink=1.4 +R4 N019 3 10 noiseless +A10 N019 3 0 0 0 0 0 0 OTA g=0 in=2.5n ink=1.4 +.model NINT VDMOS(Vto=-10m Kp=100m Is=0) +.model PINT VDMOS(Vto=10m Kp=100m Is=0 pchan) +.model PNP1 PNP(Is=1.4e-16 Vaf=200 Bf=100 Br=5 Cje=2p Cjc=1p noiseless) +.model D1p7u D(Ron=100 Roff=1g vfwd=330m epsilon=30m ilimit=1.7u noiseless) +.model SINRA SW(Ron=1 Roff=10G vt=100m vh=-100m noiseless) +.model DESD D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model NI VDMOS(Vto=300m kp=20m lambda=.01 Rs=200 Is=0) +.model PI VDMOS(Vto=-300m kp=20m lambda=.01 Is=0 pchan) +.model Dburn D(Ron=10k Roff=1g vfwd=1 epsilon=500m ilimit=45.9u noiseless) +.model DLIM1 D(Ron=100 Roff=100Meg Vfwd=2 epsilon=100m Vrev=2 revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=800m Vrev=-290m epsilon=500m revepsilon=20m noiseless) +.model DLIMN D(Ron=50Meg Roff=5g Vfwd=1.5 Vrev=-290m epsilon=500m revepsilon=20m noiseless) +.ends LT1789-1 +* +.subckt LT1789-10 1 2 3 4 5 6 7 8 +R6 A2out 8 100k noiseless +R8 1 A1out 100k noiseless +Q1 N008 N004 8 0 PNP1 temp=27 +D1 7 8 D1p7u +Q2 N021 N018 1 0 PNP1 temp=27 +D2 7 1 D1p7u +C1 N008 4 1p Rpar=50k noiseless +R1 A2out VINM 10k noiseless +R2 A1out VINP 10k noiseless +C7 7 8 1p +C8 7 1 1p +C9 7 A2out 500f +M1 7 N002 A2out A2out NINT temp=27 +M2 4 N002 A2out A2out PINT temp=27 +R9 7 N002 20Meg noiseless +R10 N002 4 20Meg noiseless +G1 N002 0 N002 7 500m dir=1 vto=-250m +G2 0 N002 4 N002 500m dir=1 vto=-50m +M3 7 N020 A1out A1out NINT temp=27 +M4 4 N020 A1out A1out PINT temp=27 +R11 7 N020 20Meg noiseless +R12 N020 4 20Meg noiseless +G3 N020 0 N020 7 500m dir=1 vto=-250m +G4 0 N020 4 N020 500m dir=1 vto=-50m +A3 N010 0 0 0 0 0 N002 0 OTA g=20m iout=500u Cout=8n Vhigh=1e308 Vlow=-1e308 +C5 A2out N010 24p +A2 4 N021 0 0 0 0 N016 0 OTA g=18u linear Ref=-85m en=81n enk=1.4 Rout=100k Cout=1p vlow=-1e308 vhigh=1e308 +A4 N016 0 0 0 0 0 N020 0 OTA g=20m iout=500u Cout=8n Vhigh=1e308 Vlow=-1e308 +C13 A1out N016 24p +C15 A2out 4 500f +C16 7 A1out 500f +C17 A1out 4 500f +C10 7 VINM 500f +C11 VINM 4 500f +C12 7 VINP 500f +C18 VINP 4 500f +R15 VINM 6 100k noiseless +R16 VINP 5 100k noiseless +A6 4 N008 0 0 0 0 N010 0 OTA g=18u linear Ref=-85m en=81n enk=1.4 Rout=100k Cout=1p vlow=-1e308 vhigh=1e308 +A1 2 3 0 0 0 0 0 0 OTA g=0 in=57f ink=170 +M5 6 NG 4 4 NI temp=27 +C3 7 6 1p Rpar=10Meg noiseless +M6 6 PG N005 N005 PI temp=27 +C4 7 PG 220f Rser=6Meg noiseless +A5 N009 N012 4 4 4 4 PG 4 OTA g=35n ref=-.0222 linear vlow=-1e308 vhigh=1e308 +C6 6 4 1p Rpar=10Meg noiseless +C14 NG 4 220f Rser=6Meg noiseless +D3 NG 4 DLIMN +A7 N007 0 N009 N009 N009 N009 N012 N009 OTA g=7u asym isink=-280n isrc=230n Cout=100f Vlow=-1e308 Vhigh=1e308 +G5 4 NG N012 N009 5n +D4 7 PG DLIMP +G6 0 N009 7 0 .5m +G7 0 N009 4 0 .5m +C20 N009 0 1p noiseless Rpar=1k +D5 N012 N009 DLIM1 +CG1 N007 0 2p Rpar=1Meg Rser=600k noiseless +B1 0 N003 I=10u*dnlim(uplim(V(VINP),V(7)-.58,.1), V(4)-.15, .1)+1n*V(VINP)-190.9p +B2 N003 0 I=10u*dnlim(uplim(V(VINM),V(7)-.57,.1), V(4)-.16, .1)+1n*V(VINM) +C21 N003 0 10f Rpar=100K noiseless +A9 0 N003 0 0 0 0 N007 0 OTA g=1u linear en=20n enk=1.9 Vhigh=1e308 Vlow=-1e308 +G8 7 PG 6 7 100µ vto=-200m dir=1 +R13 7 N005 1 noiseless +G10 7 PG 7 N005 20m vto=.2m dir=1 +G9 NG 4 4 6 100µ vto=-80m dir=1 +C22 6 N012 3.44p +D6 7 4 Dburn +S3 N008 4 4 2 SINRA +C19 N021 4 1p Rpar=50k noiseless +S4 N021 4 4 3 SINRA +D7 2 7 DESD +D8 4 2 DESD +D9 3 7 DESD +D10 4 3 DESD +D11 4 5 DESD +D12 5 7 DESD +D13 N019 7 DESD +D14 4 N019 DESD +R3 N004 2 10 noiseless +R4 N018 3 10 noiseless +A11 2 N004 0 0 0 0 0 0 OTA g=0 in=2.5n ink=1.4 +A12 N018 3 0 0 0 0 0 0 OTA g=0 in=2.5n ink=1.4 +.model NINT VDMOS(Vto=-10m Kp=100m Is=0) +.model PINT VDMOS(Vto=10m Kp=100m Is=0 pchan) +.model PNP1 PNP(Is=1.4E-16 Vaf=200 Bf=100 Br=5 Cje=2p Cjc=1p noiseless) +.model D1p7u D(Ron=100 Roff=1g vfwd=330m epsilon=30m ilimit=1.7u noiseless) +.model SINRA SW(Ron=1 Roff=10G vt=100 vh=-100m noiseless) +.model DESD D(Ron=100 Roff=1G vfwd=600m epsilon=500m noiseless) +.model NI VDMOS(Vto=300m kp=20m lambda=.01 Rs=200 Is=0) +.model PI VDMOS(Vto=-300m kp=20m lambda=.01 Is=0 pchan) +.model Dburn D(Ron=10k Roff=1g vfwd=1 epsilon=500m ilimit=45.9u noiseless) +.model DLIM1 D(Ron=100 Roff=100Meg Vfwd=2 epsilon=100m Vrev=2 revepsilon=100m noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=800m Vrev=-290m epsilon=500m revepsilon=10m noiseless) +.model DLIMN D(Ron=50Meg Roff=5g Vfwd=1.5 Vrev=-290m epsilon=500m revepsilon=10m noiseless) +.ends LT1789-10 +* +.subckt LT1990 1 2 3 4 5 6 7 8 +B1 0 N006 I=10u*dnlim(uplim(V(VINP),V(7)-.74,.1), V(4)+.9, .1)+1n*V(VINP) +B2 N006 0 I=10u*dnlim(uplim(V(VINM),V(7)-.73,.1), V(4)+.89, .1)+1n*V(VINM) +C6 7 VINP .5p Rpar=4T noiseless +C7 VINP 4 .5p noiseless Rpar=4T +C8 VINM 4 .5p Rpar=4T noiseless +C9 7 VINM .5p Rpar=4T noiseless +A2 0 N006 0 0 0 0 N009 0 OTA g=5m iout=216u cout=415p en=37n enk=1.3 Vhigh=1e308 Vlow=-1e308 +C10 N006 0 400f Rpar=100K noiseless +M1 7 N005 6 6 N temp=27 +M2 4 N005 6 6 P temp=27 +C1 N005 0 1.4p Rpar=1Meg noiseless +C3 7 6 .5p +C4 6 4 .5p +D5 N005 6 YU +D6 6 N005 YD +G1 0 N005 N009 0 1µ +D2 7 4 DP +R1 VINM 2 1Meg noiseless +R3 VINM 1 40k noiseless +R7 5 N008 10k +R8 N002 6 100k noiseless +R9 VINM N002 900k noiseless +R10 8 N002 10k noiseless +R6 7 N009 1G noiseless +R12 N009 4 1G noiseless +G2 N009 0 N009 7 500m dir=1 vto=-26m +G3 0 N009 4 N009 500m dir=1 vto=-26m +R13 7 4 714k noiseless +R4 1 VINP 40k noiseless +R2 VINP 3 1Meg noiseless +R11 N008 VINP 900k noiseless +R5 1 N008 100k noiseless +.model X D(Ron=1K Roff=100G Vfwd=-.95 epsilon=1.0 noiseless) +.model YU D(Ron=500 Roff=1T Vfwd=.62 epsilon=0.1 noiseless) +.model YD D(Ron=500 Roff=1T Vfwd = .95 epsilon=0.1 noiseless) +.model N VDMOS(Vto=-35m Kp=40m) +.model P VDMOS(Vto=35m Kp=40m pchan) +.model DP D(Ron=1k Roff=1T Vfwd=0.7 ilimit=73.5u noiseless) +.ends LT1990 +* +.subckt LT1993-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C1 INAMI INAPI .1p Rpar=100Meg noiseless +B1 0 N002 I=10u*dnlim(uplim(V(INAPI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INAPI) +B2 N002 0 I=10u*dnlim(uplim(V(INAMI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INAMI) +C2 3 INAMI 1p Rpar=20Meg noiseless +C3 N002 0 .5f Rpar=100K noiseless +R5 3 N007 100Meg noiseless +R6 N007 4 100Meg noiseless +C5 INAMI 4 1p Rpar=20Meg noiseless +C6 3 INAPI 1p Rpar=20Meg noiseless +C7 INAPI 4 1p Rpar=20Meg noiseless +M1 3 N004 5 5 N temp=27 +M2 4 N012 5 5 P temp=27 +C12 3 5 .8p +D6 N004 5 Y +D7 5 N012 Y +A3 N003 0 N007 N007 N007 N007 N004 N007 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A4 N003 0 N007 N007 N007 N012 N007 N007 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +C13 5 4 .8p Rpar=100Meg noiseless +G3 N007 0 N007 3 100m dir=1 vto=-1.15 +G4 0 N007 4 N007 100m dir=1 vto=-.14 +R2 INAMI 14 200 +R3 INAPI 16 200 +R4 5 INAMI 200 +C4 INCMI 2 .1p Rpar=1.6Meg noiseless +B3 0 N015 I=10u*dnlim(uplim(V(2),V(1)-1.2,.1), V(12)+.9, .1)+1n*V(2) +B4 N015 0 I=10u*dnlim(uplim(V(INCMI),V(1)-1.19,.1), V(12)+.89, .1)+1n*V(INCMI) +C9 1 INCMI 1p Rpar=20Meg noiseless +C10 N015 0 1f Rpar=100K noiseless +R7 1 N018 100Meg noiseless +R8 N018 12 100Meg noiseless +C11 INCMI 12 1p Rpar=20Meg noiseless +C14 1 2 1p Rpar=20Meg noiseless +C15 2 12 1p Rpar=2.95Meg noiseless +A7 0 N015 N003 0 0 0 N018 0 OTA g=1m iout=100u Cout=620f en=4n Vhigh=1e308 Vlow=-1e308 +G5 N018 0 N018 1 100m dir=1 vto=-1 +G6 0 N018 12 N018 100m dir=1 vto=-.8 +S2 3 4 N003 0 swPow +G7 0 INCMI N018 0 100m +C16 0 INCMI 100f Rpar=10 noiseless +R1 INAPI INCMI 200 +A8 11 12 0 0 0 N003 0 0 SCHMITT Vt=1 Vh=10m trise=20n tfall=300n Vlow=0 Vhigh=1 +R9 5 6 25 +C18 INBPI INBMI .1p Rpar=100Meg noiseless +B5 0 N022 I=10u*dnlim(uplim(V(INBMI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INBMI) +B6 N022 0 I=10u*dnlim(uplim(V(INBPI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INBPI) +C19 10 INBPI 1p Rpar=20Meg noiseless +C20 N022 0 .5f Rpar=100K noiseless +R10 10 N025 100Meg noiseless +R11 N025 9 100Meg noiseless +C21 INBPI 9 1p Rpar=20Meg noiseless +C22 10 INBMI 1p Rpar=20Meg noiseless +C23 INBMI 9 1p Rpar=20Meg noiseless +M3 10 N023 8 8 N temp=27 +M4 9 N029 8 8 P temp=27 +C25 10 8 .8p +D9 N023 8 Y +D10 8 N029 Y +A9 N003 0 N025 N025 N025 N025 N023 N025 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A10 N003 0 N025 N025 N025 N029 N025 N025 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +G9 N025 0 N025 10 100m dir=1 vto=-1.15 +G10 0 N025 9 N025 100m dir=1 vto=-.14 +R12 INBPI 15 200 +R13 INBMI 13 200 +R14 8 INBPI 200 +C27 7 9 12p Rpar=1T noiseless +R16 8 7 25 +R15 INCMI INBMI 200 +C17 6 4 12p Rpar=1T noiseless +C28 6 7 12p Rpar=1T noiseless +G1 0 N009 N008 0 1m +L3 N009 0 .806µ Cpar=.035f Rser=1.01k Rpar=101k noiseless +G2 0 N027 N026 0 1m +L1 N027 0 .806µ Cpar=.035f Rser=1.01k Rpar=101k noiseless +C8 8 9 .8p Rpar=100Meg noiseless +A15 0 N009 0 0 0 0 N007 0 OTA g=1m iout=50u Cout=70f Vlow=-1e308 Vhigh=1e308 +A11 0 N027 0 0 0 0 N025 0 OTA g=1m iout=50u Cout=70f Vlow=-1e308 Vhigh=1e308 +R18 12 11 2Meg noiseless +A12 0 N002 N003 0 0 0 N008 0 OTA g=1u linear Cout=1.8f en=1n+10p*freq**.28 Rout=1Meg Vlow=-64m Vhigh=64m +A5 0 N022 N003 0 0 0 N026 0 OTA g=1u linear Cout=1.8f en=1n+10p*freq**.28 Rout=1Meg Vlow=-64m Vhigh=64m +S4 N006 4 N003 0 swBias +D11 INAMI N006 DBIAS +D1 INAPI N006 DBIAS +S3 10 9 N003 0 swPow +S5 N024 9 N003 0 swBias +D2 INBPI N024 DBIAS +D4 INBMI N024 DBIAS +S1 1 12 N003 0 swPow +S6 N016 12 N003 0 swBias +D3 INCMI N016 DBIAS +D5 2 N016 DBIAS +.model Y D(Ron=100 Roff=1T Vfwd=.45 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=300m) +.model P VDMOS(Vto=150m Kp=300m pchan) +.model swPow SW(level=2 Ron=50 Roff=75.8k vt=.5 vh=-50m ilimit=28.9m noiseless) +.model swBias SW(Ron=10k Roff=100G vt=.5 vh=-50m noiseless) +.model DBIAS D(Ron=10k Roff=1G Vfwd=.6 ilimit=5u noiseless) +.model DC D(Ron=2k Roff=1G Vfwd=1 epsilon=.1 ilimit=374u noiseless) +.model DNL D(Ron=100 Roff=10k Vfwd=7 Vrev=4 epsilon=.5 revepsilon=.5 noiseless) +.ends LT1993-2 +* +.subckt LT1993-4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C1 INAMI INAPI .1f Rpar=100Meg noiseless +B1 0 N002 I=10u*dnlim(uplim(V(INAPI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INAPI) +B2 N002 0 I=10u*dnlim(uplim(V(INAMI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INAMI) +C2 3 INAMI 1p Rpar=20Meg noiseless +C3 N002 0 .02f Rpar=100K noiseless +R5 3 N008 100Meg noiseless +R6 N008 4 100Meg noiseless +C5 INAMI 4 1p Rpar=20Meg noiseless +C6 3 INAPI 1p Rpar=20Meg noiseless +C7 INAPI 4 1p Rpar=20Meg noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N013 5 5 P temp=27 +C12 3 5 .8p +D6 N005 5 Y +D7 5 N013 Y +A3 N004 0 N008 N008 N008 N008 N005 N008 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A4 N004 0 N008 N008 N008 N013 N008 N008 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +C13 5 4 .8p Rpar=100Meg noiseless +G3 N008 0 N008 3 100m dir=1 vto=-1.15 +G4 0 N008 4 N008 100m dir=1 vto=-.14 +R2 INAMI 14 100 +R3 INAPI 16 100 +R4 5 INAMI 200 +C4 INCMI 2 .1p Rpar=1.6Meg noiseless +B3 0 N016 I=10u*dnlim(uplim(V(2),V(1)-1.2,.1), V(12)+.9, .1)+1n*V(2) +B4 N016 0 I=10u*dnlim(uplim(V(INCMI),V(1)-1.19,.1), V(12)+.89, .1)+1n*V(INCMI) +C9 1 INCMI 1p Rpar=20Meg noiseless +C10 N016 0 1f Rpar=100K noiseless +R7 1 N019 100Meg noiseless +R8 N019 12 100Meg noiseless +C11 INCMI 12 1p Rpar=20Meg noiseless +C14 1 2 1p Rpar=20Meg noiseless +C15 2 12 1p Rpar=2.95Meg noiseless +A7 0 N016 N004 0 0 0 N019 0 OTA g=1m iout=100u Cout=620f en=4n Vhigh=1e308 Vlow=-1e308 +G5 N019 0 N019 1 100m dir=1 vto=-1 +G6 0 N019 12 N019 100m dir=1 vto=-.8 +S2 3 4 N004 0 swPow +G7 0 INCMI N019 0 100m +C16 0 INCMI 100f Rpar=10 noiseless +R1 INAPI INCMI 200 +A8 11 12 0 0 0 N004 0 0 SCHMITT Vt=1 Vh=10m trise=20n tfall=300n Vlow=0 Vhigh=1 +R9 5 6 25 +C18 INBPI INBMI .1f Rpar=100Meg noiseless +B5 0 N023 I=10u*dnlim(uplim(V(INBMI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INBMI) +B6 N023 0 I=10u*dnlim(uplim(V(INBPI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INBPI) +C19 10 INBPI 1p Rpar=20Meg noiseless +C20 N023 0 .02f Rpar=100K noiseless +R10 10 N027 100Meg noiseless +R11 N027 9 100Meg noiseless +C21 INBPI 9 1p Rpar=20Meg noiseless +C22 10 INBMI 1p Rpar=20Meg noiseless +C23 INBMI 9 1p Rpar=20Meg noiseless +M3 10 N025 8 8 N temp=27 +M4 9 N031 8 8 P temp=27 +C25 10 8 .8p +D9 N025 8 Y +D10 8 N031 Y +A9 N004 0 N027 N027 N027 N027 N025 N027 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A10 N004 0 N027 N027 N027 N031 N027 N027 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +G9 N027 0 N027 10 100m dir=1 vto=-1.15 +G10 0 N027 9 N027 100m dir=1 vto=-.14 +R12 INBPI 15 100 +R13 INBMI 13 100 +R14 8 INBPI 200 +C27 7 9 12p Rpar=1T noiseless +R16 8 7 25 +R15 INCMI INBMI 200 +C17 6 4 12p Rpar=1T noiseless +C28 6 7 12p Rpar=1T noiseless +G1 0 N009 N011 0 1m +G2 0 N028 N030 0 1m +C8 8 9 .8p Rpar=100Meg noiseless +A15 0 N009 0 0 0 0 N008 0 OTA g=1m iout=49u Cout=70f Vlow=-1e308 Vhigh=1e308 +A11 0 N028 0 0 0 0 N027 0 OTA g=1m iout=49u Cout=70f Vlow=-1e308 Vhigh=1e308 +R18 12 11 2Meg noiseless +S4 N007 4 N004 0 swBias +D11 INAMI N007 DBIAS +D1 INAPI N007 DBIAS +S3 10 9 N004 0 swPow +S5 N026 9 N004 0 swBias +D2 INBPI N026 DBIAS +D4 INBMI N026 DBIAS +S1 1 12 N004 0 swPow +S6 N017 12 N004 0 swBias +D3 INCMI N017 DBIAS +D5 2 N017 DBIAS +C24 N009 0 30f Rpar=1k noiseless +C26 N028 0 30f Rpar=1k noiseless +G8 0 N011 N003 0 1m +C29 N011 0 30f Rpar=1k noiseless +G11 0 N030 N024 0 1m +C30 N030 0 30f Rpar=1k noiseless +A1 0 N002 N004 0 0 0 N003 0 OTA g=1m linear Cout=20f en=.85n+10p*freq**.28 Rout=1k Vlow=-100m Vhigh=100m +A2 0 N023 N004 0 0 0 N024 0 OTA g=1m linear Cout=20f en=.85n+10p*freq**.28 Rout=1k Vlow=-100m Vhigh=100m +.model Y D(Ron=100 Roff=1T Vfwd=.45 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=300m) +.model P VDMOS(Vto=150m Kp=300m pchan) +.model swPow SW(level=2 Ron=50 Roff=75.8k vt=.5 vh=-50m ilimit=28.9m noiseless) +.model swBias SW(Ron=10k Roff=100G vt=.5 vh=-50m noiseless) +.model DBIAS D(Ron=10k Roff=1G Vfwd=.6 ilimit=5u noiseless) +.model DC D(Ron=2k Roff=1G Vfwd=1 epsilon=.1 ilimit=374u noiseless) +.model DNL D(Ron=100 Roff=10k Vfwd=7 Vrev=4 epsilon=.5 revepsilon=.5 noiseless) +.ends LT1993-4 +* +.subckt LT1993-10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C1 INAMI INAPI .1f Rpar=100Meg noiseless +B1 0 N002 I=10u*dnlim(uplim(V(INAPI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INAPI) +B2 N002 0 I=10u*dnlim(uplim(V(INAMI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INAMI) +C2 3 INAMI 1p Rpar=20Meg noiseless +C3 N002 0 .06f Rpar=100K noiseless +R5 3 N008 100Meg noiseless +R6 N008 4 100Meg noiseless +C5 INAMI 4 1p Rpar=20Meg noiseless +C6 3 INAPI 1p Rpar=20Meg noiseless +C7 INAPI 4 1p Rpar=20Meg noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N013 5 5 P temp=27 +C12 3 5 .8p +D6 N005 5 Y +D7 5 N013 Y +A3 N004 0 N008 N008 N008 N008 N005 N008 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A4 N004 0 N008 N008 N008 N013 N008 N008 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +C13 5 4 .8p Rpar=100Meg noiseless +G3 N008 0 N008 3 100m dir=1 vto=-1.15 +G4 0 N008 4 N008 100m dir=1 vto=-.14 +R2 INAMI 14 100 +R3 INAPI 16 100 +R4 5 INAMI 500 +C4 INCMI 2 .1p Rpar=1.6Meg noiseless +B3 0 N016 I=10u*dnlim(uplim(V(2),V(1)-1.2,.1), V(12)+.9, .1)+1n*V(2) +B4 N016 0 I=10u*dnlim(uplim(V(INCMI),V(1)-1.19,.1), V(12)+.89, .1)+1n*V(INCMI) +C9 1 INCMI 1p Rpar=20Meg noiseless +C10 N016 0 1f Rpar=100K noiseless +R7 1 N019 100Meg noiseless +R8 N019 12 100Meg noiseless +C11 INCMI 12 1p Rpar=20Meg noiseless +C14 1 2 1p Rpar=20Meg noiseless +C15 2 12 1p Rpar=2.95Meg noiseless +A7 0 N016 N004 0 0 0 N019 0 OTA g=1m iout=100u Cout=620f en=4n Vhigh=1e308 Vlow=-1e308 +G5 N019 0 N019 1 100m dir=1 vto=-1 +G6 0 N019 12 N019 100m dir=1 vto=-.8 +S2 3 4 N004 0 swPow +G7 0 INCMI N019 0 100m +C16 0 INCMI 100f Rpar=10 noiseless +R1 INAPI INCMI 500 +A8 11 12 0 0 0 N004 0 0 SCHMITT Vt=1 Vh=10m trise=20n tfall=300n Vlow=0 Vhigh=1 +R9 5 6 25 +C18 INBPI INBMI .1f Rpar=100Meg noiseless +B5 0 N023 I=10u*dnlim(uplim(V(INBMI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INBMI) +B6 N023 0 I=10u*dnlim(uplim(V(INBPI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INBPI) +C19 10 INBPI 1p Rpar=20Meg noiseless +C20 N023 0 .06f Rpar=100K noiseless +R10 10 N027 100Meg noiseless +R11 N027 9 100Meg noiseless +C21 INBPI 9 1p Rpar=20Meg noiseless +C22 10 INBMI 1p Rpar=20Meg noiseless +C23 INBMI 9 1p Rpar=20Meg noiseless +M3 10 N025 8 8 N temp=27 +M4 9 N031 8 8 P temp=27 +C25 10 8 .8p +D9 N025 8 Y +D10 8 N031 Y +A9 N004 0 N027 N027 N027 N027 N025 N027 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A10 N004 0 N027 N027 N027 N031 N027 N027 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +G9 N027 0 N027 10 100m dir=1 vto=-1.15 +G10 0 N027 9 N027 100m dir=1 vto=-.14 +R12 INBPI 15 100 +R13 INBMI 13 100 +R14 8 INBPI 500 +C27 7 9 12p Rpar=1T noiseless +R16 8 7 25 +R15 INCMI INBMI 500 +C17 6 4 12p Rpar=1T noiseless +C28 6 7 12p Rpar=1T noiseless +G1 0 N009 N011 0 1m +G2 0 N028 N030 0 1m +C8 8 9 .8p Rpar=100Meg noiseless +A15 0 N009 0 0 0 0 N008 0 OTA g=1m iout=32.8u Cout=50f Vlow=-1e308 Vhigh=1e308 +A11 0 N028 0 0 0 0 N027 0 OTA g=1m iout=32.8u Cout=50f Vlow=-1e308 Vhigh=1e308 +R18 12 11 2Meg noiseless +S4 N007 4 N004 0 swBias +D11 INAMI N007 DBIAS +D1 INAPI N007 DBIAS +S3 10 9 N004 0 swPow +S5 N026 9 N004 0 swBias +D2 INBPI N026 DBIAS +D4 INBMI N026 DBIAS +S1 1 12 N004 0 swPow +S6 N017 12 N004 0 swBias +D3 INCMI N017 DBIAS +D5 2 N017 DBIAS +C24 N009 0 60f Rpar=1k noiseless +C26 N028 0 60f Rpar=1k noiseless +G8 0 N011 N003 0 1m +C29 N011 0 60f Rpar=1k noiseless +G11 0 N030 N024 0 1m +C30 N030 0 60f Rpar=1k noiseless +A1 0 N002 N004 0 0 0 N003 0 OTA g=1m linear Cout=20f en=.85n+10p*freq**.26 Rout=1k Vlow=-64m Vhigh=64m +A2 0 N023 N004 0 0 0 N024 0 OTA g=1m linear Cout=20f en=.85n+10p*freq**.26 Rout=1k Vlow=-64m Vhigh=64m +.model Y D(Ron=100 Roff=1T Vfwd=.45 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=300m) +.model P VDMOS(Vto=150m Kp=300m pchan) +.model swPow SW(level=2 Ron=50 Roff=75.8k vt=.5 vh=-50m ilimit=28.9m noiseless) +.model swBias SW(Ron=10k Roff=100G vt=.5 vh=-50m noiseless) +.model DBIAS D(Ron=10k Roff=1G Vfwd=.6 ilimit=5u noiseless) +.model DC D(Ron=2k Roff=1G Vfwd=1 epsilon=.1 ilimit=374u noiseless) +.model DNL D(Ron=100 Roff=10k Vfwd=7 Vrev=4 epsilon=.5 revepsilon=.5 noiseless) +.ends LT1993-10 +* +.SUBCKT 1993AMPA10 3 2 7 4 6 8 +CG1 125 0 1.7E-10 +CG2 128 0 800p +CG3 126 0 23n +CG4 129 0 1100p +DOUT1 25 26 DOUTP +DOUT2 26 25 DOUTN +DVL1 120 125 DVLIM +DVL2 120 0 DVLIM +EPWR1 117 0 VALUE={V(31)+V(25,26)-V(41,42)} +EPWR2 118 0 VALUE={V(30)+V(25,26)+V(41,42)} +ESHD1 42 0 VALUE={V(31)-10} +EVLIM1 30 0 VALUE={V(7)-1.25} +EVLIM2 31 0 VALUE={V(4)+0.45} +GG1 0 125 VALUE={0.02*TANH(V(23))} +GG2 0 128 127 0 6.2832 +GG3 0 126 125 0 6.2832 +GG4 0 129 128 0 6.2832 +GGAIN 0 23 115 2 338 +GINX 0 115 3 0 1 +GOUT 0 25 VALUE={1E-3*TANH(V(24))} +GPWR 7 4 116 31 0.1 +GSHD1 119 0 8 4 1 +GVNOI1 0 115 121 0 1 +GZP1 0 24 129 0 0.1 +GZP2 0 127 126 0 0.1 +IDUM1 121 0 0 +IPWR1 0 116 -7m +IPWR2 7 4 175u +ISHD2 0 119 2 +IVOS 0 115 2.5m +LZP1 123 0 3.5n +LZP2 122 0 10n +MOUT1 30 25 26 26 NOUT +MOUT1X 7 117 31 31 NOUT +MOUT2 31 25 26 26 POUT +MOUT2X 4 118 30 30 POUT +MSHD1 26 119 124 124 NSW +MSHD10 31 119 116 116 PSW +MSHD11 41 119 31 31 PSW +MSHD2 6 119 124 124 NSW +RA 23 0 0.1 +RG1 125 0 1000 +RG2 128 0 0.159155 +RG3 126 0 0.159155 +RG4 129 0 0.159155 +RINX 115 0 1 +ROUT1 30 25 2E4 +ROUT2 25 31 2E4 +RPWR 116 31 10 +RSHD2 119 31 10 +RSHD3 42 41 1k +RSHDNZ 6 26 1E8 +RVNOI 121 0 140 +RZP1 24 122 10 +RZP2 127 123 10 +RZP3 123 0 30 +RZP4 122 0 35 +.MODEL NOUT NMOS(KP=5 VTO=-150m) +.MODEL POUT PMOS(KP=5 VTO=150m) +.MODEL NOUTX NMOS(KP=5 VTO=0) +.MODEL POUTX PMOS(KP=5 VTO=0) +.MODEL PSW PMOS(KP=5 VTO=-1M) +.MODEL NSW NMOS(KP=5 VTO=1M) +.MODEL DOUTP D(KF=0 RS=0 IS=1.028E-7) +.MODEL DOUTN D(KF=0 RS=0 IS=1.028E-7) +.MODEL DVLIM D(BV=0.5 IS=1E-10 KF=0 RS=0 XTI=0) +.ENDS 1993AMPA10 +* +.SUBCKT 1993AMPC 3 2 7 4 6 8 +CG1 122 0 1E-9 +CG2 124 0 1n +CG3 123 0 35n +CIN1 3 7 0.5p +CIN2 3 4 0.5p +DOUT1 25 26 DOUTP +DOUT2 26 25 DOUTN +DVL1 119 122 DVLIM +DVL2 119 0 DVLIM +EPWR1 116 0 VALUE={V(31)+V(25,26)-V(41,42)} +EPWR2 117 0 VALUE={V(30)+V(25,26)+V(41,42)} +ESHD1 42 0 VALUE={V(31)-10} +EVLIM1 30 0 VALUE={V(7)-1.1} +EVLIM2 31 0 VALUE={V(4)+0.7} +GG1 0 122 VALUE={0.5*TANH(V(23))} +GG2 0 124 123 0 6.2832 +GG3 0 123 122 0 6.2832 +GGAIN 0 23 115 2 0.77 +GINX 0 115 3 0 1 +GOUT 0 25 VALUE={1E-3*TANH(V(24))} +GSHD1 118 0 8 4 1 +GZP1 0 24 124 0 0.1 +IBIAS 3 0 10u +ISHD2 0 118 2 +IVOS 0 115 5m +LZP1 120 0 20n +MOUT1 30 25 26 26 NOUT +MOUT1X 7 116 31 31 NOUT +MOUT2 31 25 26 26 POUT +MOUT2X 4 117 30 30 POUT +MSHD1 26 118 121 121 NSW +MSHD11 41 118 31 31 PSW +MSHD2 6 118 121 121 NSW +RA 23 0 0.1 +RG1 122 0 1000 +RG2 124 0 0.159155 +RG3 123 0 0.159155 +RIN1 3 7 2E6 +RIN2 3 4 2E6 +RINX 115 0 1 +ROUT1 30 25 2E5 +ROUT2 25 31 2E5 +RSHD2 118 31 10 +RSHD3 42 41 1k +RSHDNZ 6 26 1E8 +RZP1 24 120 10 +RZP2 120 0 90 +.MODEL NOUT NMOS(KP=5 VTO=-10m) +.MODEL POUT PMOS(KP=5 VTO=10m) +.MODEL PSW PMOS(KP=5 VTO=-1M) +.MODEL NSW NMOS(KP=5 VTO=1M) +.MODEL DOUTP D(KF=0 RS=0 IS=1.028E-6) +.MODEL DOUTN D(KF=0 RS=0 IS=1.028E-6) +.MODEL DVLIM D(BV=0.5 IS=1E-10 KF=0 RS=0 XTI=0) +.ENDS 1993AMPC +* +.SUBCKT 1993AMPA4 3 2 7 4 6 8 +CG1 125 0 5e-10 +CG2 128 0 800p +CG3 126 0 25n +CG4 129 0 1100p +DOUT1 25 26 DOUTP +DOUT2 26 25 DOUTN +DVL1 120 125 DVLIM +DVL2 120 0 DVLIM +EPWR1 117 0 VALUE={V(31)+V(25,26)-V(41,42)} +EPWR2 118 0 VALUE={V(30)+V(25,26)+V(41,42)} +ESHD1 42 0 VALUE={V(31)-10} +EVLIM1 30 0 VALUE={V(7)-1.25} +EVLIM2 31 0 VALUE={V(4)+0.45} +GG1 0 125 VALUE={0.06*TANH(V(23))} +GG2 0 128 127 0 6.2832 +GG3 0 126 125 0 6.2832 +GG4 0 129 128 0 6.2832 +GGAIN 0 23 115 2 248 +GINX 0 115 3 0 1 +GOUT 0 25 VALUE={1E-3*TANH(V(24))} +GPWR 7 4 116 31 0.1 +GSHD1 119 0 8 4 1 +GVNOI1 0 115 121 0 1 +GZP1 0 24 129 0 0.1 +GZP2 0 127 126 0 0.1 +IDUM1 121 0 0 +IPWR1 0 116 -7m +IPWR2 7 4 175u +ISHD2 0 119 2 +IVOS 0 115 2.5m +LZP1 123 0 3.5n +LZP2 122 0 10n +MOUT1 30 25 26 26 NOUT +MOUT1X 7 117 31 31 NOUT +MOUT2 31 25 26 26 POUT +MOUT2X 4 118 30 30 POUT +MSHD1 26 119 124 124 NSW +MSHD10 31 119 116 116 PSW +MSHD11 41 119 31 31 PSW +MSHD2 6 119 124 124 NSW +RA 23 0 0.1 +RG1 125 0 1000 +RG2 128 0 0.159155 +RG3 126 0 0.159155 +RG4 129 0 0.159155 +RINX 115 0 1 +ROUT1 30 25 2E4 +ROUT2 25 31 2E4 +RPWR 116 31 10 +RSHD2 119 31 10 +RSHD3 42 41 1k +RSHDNZ 6 26 1E8 +RVNOI 121 0 125 +RZP1 24 122 10 +RZP2 127 123 10 +RZP3 123 0 30 +RZP4 122 0 35 +.MODEL NOUT NMOS(KP=5 VTO=-150m) +.MODEL POUT PMOS(KP=5 VTO=150m) +.MODEL NOUTX NMOS(KP=5 VTO=0) +.MODEL POUTX PMOS(KP=5 VTO=0) +.MODEL PSW PMOS(KP=5 VTO=-1M) +.MODEL NSW NMOS(KP=5 VTO=1M) +.MODEL DOUTP D(KF=0 RS=0 IS=1.028E-7) +.MODEL DOUTN D(KF=0 RS=0 IS=1.028E-7) +.MODEL DVLIM D(BV=0.5 IS=1E-10 KF=0 RS=0 XTI=0) +.ENDS 1993AMPA4 +* +.SUBCKT 1993AMPC 3 2 7 4 6 8 +CG1 122 0 1E-9 +CG2 124 0 1n +CG3 123 0 35n +CIN1 3 7 0.5p +CIN2 3 4 0.5p +DOUT1 25 26 DOUTP +DOUT2 26 25 DOUTN +DVL1 119 122 DVLIM +DVL2 119 0 DVLIM +EPWR1 116 0 VALUE={V(31)+V(25,26)-V(41,42)} +EPWR2 117 0 VALUE={V(30)+V(25,26)+V(41,42)} +ESHD1 42 0 VALUE={V(31)-10} +EVLIM1 30 0 VALUE={V(7)-1.1} +EVLIM2 31 0 VALUE={V(4)+0.7} +GG1 0 122 VALUE={0.5*TANH(V(23))} +GG2 0 124 123 0 6.2832 +GG3 0 123 122 0 6.2832 +GGAIN 0 23 115 2 0.77 +GINX 0 115 3 0 1 +GOUT 0 25 VALUE={1E-3*TANH(V(24))} +GSHD1 118 0 8 4 1 +GZP1 0 24 124 0 0.1 +IBIAS 3 0 10u +ISHD2 0 118 2 +IVOS 0 115 5m +LZP1 120 0 20n +MOUT1 30 25 26 26 NOUT +MOUT1X 7 116 31 31 NOUT +MOUT2 31 25 26 26 POUT +MOUT2X 4 117 30 30 POUT +MSHD1 26 118 121 121 NSW +MSHD11 41 118 31 31 PSW +MSHD2 6 118 121 121 NSW +RA 23 0 0.1 +RG1 122 0 1000 +RG2 124 0 0.159155 +RG3 123 0 0.159155 +RIN1 3 7 2E6 +RIN2 3 4 2E6 +RINX 115 0 1 +ROUT1 30 25 2E5 +ROUT2 25 31 2E5 +RSHD2 118 31 10 +RSHD3 42 41 1k +RSHDNZ 6 26 1E8 +RZP1 24 120 10 +RZP2 120 0 90 +.MODEL NOUT NMOS(KP=5 VTO=-10m) +.MODEL POUT PMOS(KP=5 VTO=10m) +.MODEL PSW PMOS(KP=5 VTO=-1M) +.MODEL NSW NMOS(KP=5 VTO=1M) +.MODEL DOUTP D(KF=0 RS=0 IS=1.028E-6) +.MODEL DOUTN D(KF=0 RS=0 IS=1.028E-6) +.MODEL DVLIM D(BV=0.5 IS=1E-10 KF=0 RS=0 XTI=0) +.ENDS 1993AMPC +* +.subckt LT1994 1 2 3 4 5 6 7 8 +A1 1 8 0 0 0 0 0 0 OTA g=0 in=2.5p ink=638 +C5 3 1 2p Rser=1.4Meg +C6 X0 0 1f Rpar=100K noiseless +M1 3 N009 4 4 N temp=27 +M2 6 N012 4 4 P temp=27 +C7 N006 0 1.4f +C8 N015 0 1.4f +M3 3 N016 5 5 N temp=27 +M4 6 N020 5 5 P temp=27 +D4 N016 5 Y +D5 5 N020 Y +D8 4 N012 Y +D9 N009 4 Y +R9 4 VCM 4K noiseless +R11 VCM 5 4K noiseless +B1 0 X0 I=10u*dnlim(uplim(V(8),V(3)-1.15,.1), V(6)-.2, .1)+1n*V(8) +B2 X0 0 I=10u*dnlim(uplim(V(1),V(3)-1.14,.1), V(6)-.21, .1)+1n*V(1) +C19 3 4 1p +C12 4 6 1p +C16 3 5 1p +C17 5 6 1p +R7 3 N006 10Meg noiseless +R10 N006 6 10Meg noiseless +R13 N015 6 10Meg noiseless +R6 3 N015 10Meg noiseless +D3 6 8 DCLP +D2 6 1 DCLP +D6 8 3 DCLP +D7 1 3 DCLP +B5 0 N008 I=10u*dnlim(uplim(V(2),V(3)-.7,.1), V(6)+1, .1)+1n*V(2) +C9 N008 0 10f Rpar=100K noiseless +B6 N008 0 I=10u*dnlim(uplim(V(VCM),V(3)-.69,.1), V(6)+.99, .1)+1n*V(VCM) +C13 N004 0 1f +A6 3 7 0 0 0 N007 0 0 SCHMITT Vt=2 Vh=10m trise=1u tfall=1u +A7 N007 0 N006 N006 N006 N006 N009 N006 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=4p +A8 N007 0 N006 N006 N006 N012 N006 N006 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=4p +A9 N007 0 N015 N015 N015 N015 N016 N015 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=4p +A10 N007 0 N015 N015 N015 N020 N015 N015 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=4p +A11 0 X0 N007 0 0 0 N017 0 OTA g=1m linear Cout=100f Rout=1k en=3n enk=876 Vlow=-1e308 Vhigh=1e308 +A5 N017 0 N018 N018 N018 N018 N004 N018 OTA g=100u iout=13.3u Vlow=-1e308 Vhigh=1e308 +C10 5 N018 200f +G3 0 N015 0 N018 200n +G1 0 N006 0 N004 200n +S6 N004 0 N006 3 swLim +S1 0 N004 6 N006 swLim +S5 N018 0 N015 3 swLim +S4 0 N018 6 N015 swLim +C15 4 N004 200f +D10 1 8 DINP +C1 1 6 2p Rser=1.4Meg noiseless +C2 3 8 2p Rser=1.4Meg noiseless +C3 8 6 2p Rser=1.4Meg noiseless +C4 3 2 1p Rpar=80K noiseless +C18 2 6 1p Rpar=80K noiseless +S2 3 1 N007 0 swBias +S3 3 8 N007 0 swBias +S7 3 6 N007 0 swPow +D1 3 6 DPOW +D11 3 7 DSHUT +R2 3 6 17K noiseless +A4 0 N008 N007 0 0 0 N011 0 OTA g=1m linear en=15n enk=10 Rout=1k Cout=200p Vlow=-40m Vhigh=40m +G2 0 N004 0 N011 5µ +G4 0 N018 0 N011 5µ +S8 N004 0 0 N007 swShut +S9 0 N018 0 N007 swShut +C14 0 N018 1f +.model N VDMOS(Vto=-200m Kp=155m) +.model P VDMOS(Vto=200m Kp=155m pchan) +.model Y D(Ron=50 Roff=1T Vfwd=.8 epsilon=10m noiseless) +.model DSHUT D(Ron=60K Roff=300k Vfwd=1.5 epsilon=.2 noiseless) +.model DPOW D(Ron=1k ilimit=20u Vfwd=.5 epsilon=.1 noiseless) +.model DINP D(Ron=100 Roff=4.5k Vfwd=1.1 epsilon=.1 noiseless) +.model DCLP D(Ron=500 Roff=1G vfwd=.8 epsilon=.1 noiseless) +.model swBias SW(level=2 Ron=1k Roff=1G vt= .5 vh=-100m ilimit=18u noiseless ) +.model swPow SW(level=2 Ron=80 Roff=1G vt=.5 vh=-100m ilimit=7.35m noiseless) +.model swLim SW(Ron=100k Roff=1T vt=150m vh=-100m level=2 ilimit=100u oneway noiseless) +.model swShut SW(Ron=10k Roff=500Meg vt=-.5 vh=-.1 noiseless) +.ends LT1994 +* +.subckt LT6100 1 2 3 4 5 6 7 8 +C1 2 8 .2p +C2 8 4 .2p +C3 2 1 .2p +C4 1 4 .2p +C5 N002 0 10f Rpar=100K noiseless +A2 0 N002 0 0 0 0 N005 0 OTA g=500u iout=100u Cout=40p Vlow=-1e308 Vhigh=1e308 +R1 VSPP 8 5k +R2 VSNP 1 5k +C6 2 VSNP .2p +C7 VSNP 4 .2p +C8 2 VSPP .2p +C9 VSPP 4 .2p +M1 VSPP N005 N006 N006 NI temp=27 +C12 N006 4 100f Rpar=50k +C13 2 7 100f +C14 7 4 100f +C19 2 3 500f +C20 3 4 500f +R4 N006 3 10k +B3 0 N009 I=10u*dnlim(uplim(V(3),V(2)-1,.1), V(4)-.3, .1)+ 1n*V(3) -2.7n +B4 N009 0 I=10u*dnlim(uplim(V(VINN),V(2)-0.99,.1), V(4)-.31, .1) + 1n*V(VINN) +C15 N009 0 .8p Rpar=100K noiseless +R3 VINN 5 25k +R5 VINN 7 8.3333333k +R6 VINN 6 25k +C16 2 VINN 500f +C17 VINN 4 500f +B1 N002 0 I=10u*dnlim(uplim(V(VSNP),V(4)+48.11,.1), V(2)+1.29, .1) + 1n*V(VSNP) +B2 0 N002 I=10u*dnlim(uplim(V(VSPP),V(4)+48.1,.1), V(2)+1.3, .1)+ 1n*V(VSPP) +R7 2 N005 2G +R9 N005 4 2G +G2 N005 0 N005 2 500m dir=1 vto=0 +G3 0 N005 4 N005 400m dir=1 vto=-.315 +M2 5 N014 4 4 NOUT temp=27 +D1 N014 4 DLIMN +M3 5 N010 2 2 POUT temp=27 +D2 2 N010 DLIMP +C10 2 N010 200f Rser=10Meg +A3 0 N012 0 0 0 0 N010 0 OTA g=200n ref=-39m linear vlow=-1e308 vhigh=1e308 +C11 N014 4 200f Rser=10Meg noiseless +C18 N012 5 80p +A4 N011 0 0 0 0 0 N012 0 OTA g=90u iout=4u Vhigh=1e308 Vlow=-1e308 +G1 4 N014 N012 0 200n +S1 N012 0 0 N004 SHUT2 +S2 N010 2 0 N004 SHUT1 +S3 4 N014 0 N004 SHUT1 +C24 2 5 2p +C25 5 4 2p +A1 0 N009 0 0 0 0 N011 0 OTA g=1m linear rout=1k cout=1n Vhigh=1e308 Vlow=-1e308 +C21 2 6 100f +C22 6 4 100f +A6 2 4 0 0 0 0 N004 0 SCHMITT vt=2.5 trise=15u tfall=15u +S5 4 VSNP N004 0 SBIAS1 +S6 VSPP VSNP N004 0 SBIASC +S7 4 VSPP N004 0 SBIAS1 +S4 4 N005 0 N004 SHUT2 +S8 4 2 N004 0 SWP +D3 N012 0 DLIM +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=305m) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m) +.model DLIM D(Ron=1 Roff=700k Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=.6 Vrev=-300m epsilon=.1) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=.58 Vrev=-300m epsilon=10m revepsilon=10m) +.model NI VDMOS(Vto=300m Kp=20m) +.model NOUT VDMOS(Vto=300m kp=30m lambda=.01) +.model POUT VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0) +.model SBIAS1 SW (level=2 Ron=10k Roff=1G ilimit=4.5u vt=.5 vh=-.1) +.model SBIASC SW(level=2 Ron=22k Roff=1G ilimit=15u vt=-.5 vh=-.1) +.model SWP SW(level=2 Ron=10k Roff=1G ilimit=22.5u vt=-.5 vh=-.1) +.ends LT6100 +* +* Note 1: For greater numerical accuracy in transient simulation, decrease the maximum simulation time step. +* Note 2: This is a simplified model with no shutdown functionality. +* Node List (same as IC): GND IN1 IN2 VSS VOUT OUTRTN VDD +.SUBCKT LTC1966 1 2 3 4 5 6 7 +RIND 3 2 8E6 +RINC1 1 2 2E8 +RINC2 1 3 2E8 +ISUP1 7 1 155u +ISUP2 1 4 12u +GIN2 0 11 VALUE={1m*ABS(V(10)/(V(5,6)+4E-4)*MIN(V(5,6)*4.183,ABS(V(10))))} +RIN1 10 0 1k +RIN2 11 13 300k +DS1 13 0 DS +CIN1 10 0 160p +DS3 12 31 DS +RIN3 12 11 50 +EOUT 20 0 VALUE={ABS(V(11))+V(6)} +ROUT 5 20 85k +COUT 5 6 8.7p +REN 8 7 5E6 +GIN1 0 10 2 3 1m +RIN4 11 0 1k +EVCC 31 0 VALUE={0.56*V(7,1)-0.750} +CIN2 11 0 10p +.MODEL DS D(IS=1E-16 RS=0 KF=0 XTI=0) +.ENDS LTC1966 +* +** +* +* Note 1: For greater numerical accuracy in transient simulation, decrease the maximum simulation time step. +* Note 2: This is a simplified model with no shutdown functionality. +* Node List (same as IC): GND IN1 IN2 VOUT OUTRTN V+ +.SUBCKT LTC1967 1 2 3 5 6 7 +RIND 3 2 5E6 +RINC1 1 2 2E8 +RINC2 1 3 2E8 +ISUP1 7 1 330u +GIN2 0 11 VALUE={1m*ABS(V(10)/(V(5,6)+0.002)*MIN(V(5,6)*4.183+1E-6,ABS(V(10))))} +RIN1 10 0 1k +RIN2 11 13 150k +DS1 13 0 DS +CIN1 10 0 40p +DS3 12 31 DS +RIN3 12 11 50 +EOUT 20 0 VALUE={ABS(V(11))+0.002+V(6)} +ROUT 5 20 50k +COUT 5 6 8.7p +REN 8 7 5E6 +GIN1 0 10 2 3 1m +RIN4 11 0 1k +EVCC 31 0 VALUE={0.5*V(7,1)-0.750} +CIN2 11 0 10p +.MODEL DS D(IS=1E-16 RS=0 KF=0 XTI=0) +.ENDS LTC1967 +* +** +* +* Note 1: For greater numerical accuracy in transient simulation, decrease the maximum simulation time step. +* Note 2: This is a simplified model with no shutdown functionality. +* Node List (same as IC): GND IN1 IN2 VOUT OUTRTN V+ +.SUBCKT LTC1968 1 2 3 5 6 7 +RIND 3 2 1.2E6 +RINC1 1 2 2E8 +RINC2 1 3 2E8 +ISUP1 7 1 2.3E-3 +GIN2 0 11 VALUE={1m*ABS(V(10)/(V(5,6)+0.002)*MIN(V(5,6)*4.183+1E-6,ABS(V(10))))} +RIN1 10 0 1k +RIN2 11 13 150k +DS1 13 0 DS +CIN1 10 0 15p +DS3 12 31 DS +RIN3 12 11 50 +EOUT 20 0 VALUE={ABS(V(11))+0.002+V(6)} +ROUT 5 20 12.5k +COUT 5 6 8.7p +REN 8 7 5E6 +GIN1 0 10 2 3 1m +RIN4 11 0 1k +EVCC 31 0 VALUE={0.5*V(7,1)-0.750} +CIN2 11 0 10p +.MODEL DS D(IS=1E-16 RS=0 KF=0 XTI=0) +.ENDS LTC1968 +* +.subckt LTC6101 1 2 3 4 5 +D14 N004 4 DINI +A1 0 X0 0 0 0 0 X1 0 OTA g=8m linear Vlow=-1e308 Vhigh=1e308 +D15 XGN 0 DLIM2 +M3 1 PG 3 3 PII temp=27 +C22 3 PG 10f Rpar=1Meg noiseless +C27 XGN 0 1.5n Rpar=100Meg noiseless +B3 X0 0 I=10u*dnlim(uplim(V(3),V(5)+.31,.1), V(5)-uplim(.4*V(5,2)-.59,1.91,.1), .1)+1n*V(3) +B4 0 X0 I=10u*dnlim(uplim(V(4),V(5)+.3,.1), V(5)-uplim(.4*V(5,2)-.6,1.9,.1), .1)+1n*V(4) +D17 N004 5 D10Z +D16 5 N004 D3D +D18 2 1 D10Z +C28 1 2 1p +G7 PG 3 N002 0 1µ +B5 0 N002 I=1u*uplim(-V(XGN)+60m,70m*V(5,2)+300m,10m) +C29 N002 0 1f Rpar=1Meg noiseless +B6 PG 3 I=290n + 1.1n*uplim(V(5,2),10,2) +C12 5 N004 1p Rser=100 noiseless +C20 N004 2 1p Rser=100 noiseless +C23 5 4 1p Rser=100 noiseless +C24 4 2 1p Rser=100 noiseless +D20 N004 2 DBIAS +D21 4 2 DBIAS +D22 5 2 DP +C25 5 2 10p Rpar=361k noiseless +D24 1 3 DESD +C26 3 1 1p +C14 X1 0 300p Rpar=1k noiseless +A4 0 X0 0 0 0 0 X1A 0 OTA g=800m linear Vlow=-1e308 Vhigh=1e308 +R5 X1A 0 10 noiseless +A6 0 X1 0 0 0 0 XGN 0 OTA g=625u linear vlow=-1e308 vhigh=1e308 +D19 X1A X1 DLS +D25 X0 0 DSlewB1 +C19 X0 0 1f Rpar=1Meg noiseless +D26 X0 0 DSlewB2 +D27 3 PG DgainKill +.model DINI D(Ron=10k Roff=10T vfwd=600m epsilon=500m vrev=600m revepsilon=500m noiseless) +.model DLS D(Ron=10 Roff=100Meg vfwd=50m epsilon=10n vrev=50m revepsilon=10m noiseless) +.model D3D D(Ron=5k Roff=1G vfwd=1.8 epsilon=1.2 noiseless) +.model D10Z D(Ron=100 Roff=1G vfwd=600m epsilon=500m vrev=10.1 revepsilon=500m noiseless) +.model DBIAS D(Ron=1k Roff=1T vfwd=600m epsilon=500m ilimit=85n noiseless) +.model DLIM2 D(Ron=10 Roff=100Meg, vfwd=10m epsilon=20m vrev=990m revepsilon=100m noiseless) +.model PII VDMOS(Vto=-300m Kp=100m Is=0 Rs=50 pchan noiseless) +.model DSlewB1 D(Roff=125k Ron=200k vfwd=20m epsilon=3m vrev=20m revepsilon=3m noiseless) +.model DSlewB2 D(Roff=500k Ron=10K vfwd=200m epsilon=100m vrev=200m revepsilon=100m noiseless) +.model DgainKill D(Ron=1Meg Roff=2Meg vfwd=350m epsilon=100m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DP D(Ron=1k Roff=1G Vfwd=.5 epsilon=100m ilimit=209u noiseless) +.ends LTC6101 +* +.subckt LTC6702 1 2 3 4 5 +B1 0 N002 I=10u*dnlim(uplim(V(1),V(3)-1.1,.1), V(4)-.2 ,.1)+1n*V(1)+402n*V(VDH) +B2 N002 0 I=10u*dnlim(uplim(V(2),V(3)-1.09,.1), V(4)-.21, .1)+1n*V(2) +C1 N002 0 10f Rpar=100K +A1 0 N002 0 0 0 0 VDH 0 OTA g=3m iout=100u Vlow=-1e308 Vhigh=1e308 Cout=100f +C4 2 4 .2p +C10 1 4 .2p +D13 3 4 DP1 +M3 5 N008 4 4 NI temp=27 +M4 5 N004 3 3 PI temp=27 +C7 3 5 1p +C8 5 4 1p +C2 5 N008 12f +C15 N004 5 12f +C5 3 2 .2p +C6 3 1 .2p +D2 2 4 DLEAK +S1 N004 4 0 N003 SWON +S2 N008 3 N003 0 SWON +C3 3 N004 10f +C11 N003 0 5.2p +C9 N008 4 10f +D1 0 N003 DLAT2 +G2 0 N003 0 VDH 10µ +R3 VDH 0 10k +S3 3 N004 N003 0 SWOFF +S4 N008 4 0 N003 SWOFF +D3 1 4 DLEAK +.model DLAT D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9) +.model DLAT2 D(Ron=100 Roff=200k Vfwd=470m Vrev=470m epsilon=50m revepsilon=50m) +.model DLEAK D(Ron=1k Roff=10G Vfwd=.1 epsilon=.1 ilimit=10p) +.model DP1 D(Ron=100 Roff=100Meg Vfwd=1 ilimit=24u epsilon=.1) +.model PI VDMOS(Vto=-100m kp=40m rd=.1 rds=100Meg is=0 pchan) +.model NI VDMOS(Vto=100m kp=70m rd=1.5 rds=100Meg) +.model SWON SW(level=2 Ron=10k Roff=1G Vt=120m vh=-5m ilimit=3.7u noiseless) +.model SWOFF SW(Ron=100 Roff=1G Vt=40m vh=-10m noiseless) +.ends LTC6702 +* +.subckt LTC6601-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 +M1 11 N016 13 13 NI temp=27 +D5 N016 13 DLIMN +M2 11 N008 14 14 PI temp=27 +D8 14 N008 DLIMP +C3 14 N008 3f Rser=2Meg noiseless +A3 N011 N012 13 13 13 13 N008 13 OTA g=250n ref=-60m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N011 N011 N011 N011 N012 N011 OTA g=500u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 13 N016 N012 N011 250n +D9 N012 N011 DLIM +C7 14 INP 1p Rser=8 Rpar=2Meg noiseless +C13 14 13 1000p +S1 N012 N011 0 N007 SHUT2 +C17 13 3 500f +S4 N008 14 0 N007 SHUT1 +S2 13 N016 0 N007 SHUT1 +A2 3 13 0 0 0 0 N007 0 SCHMITT trise=.5u tfall=.5u vt=.4 vh=0 +A1 0 INP 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +M3 15 N024 13 13 NI temp=27 +D3 N024 13 DLIMN +M4 15 N022 14 14 PI temp=27 +D12 14 N022 DLIMP +A6 N011 N023 13 13 13 13 N022 13 OTA g=300n ref=-60m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N011 N011 N011 N011 N023 N011 OTA g=500u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 13 N024 N023 N011 250n +D13 N023 N011 DLIM +S3 N023 N011 0 N007 SHUT2 +S5 N022 14 0 N007 SHUT1 +S6 13 N024 0 N007 SHUT1 +R3 11 N018 860 noiseless +R4 15 N018 860 noiseless +A8 N018 12 0 0 0 0 N014 0 OTA g=10m linear en=9n enk=20k Rout=1k Cout=2p ref=-586u Vlow=-1e308 Vhigh=1e308 +G6 N011 N023 0 N014 100µ +G7 N011 N012 0 N014 100µ +D14 N014 0 DCML +C2 14 11 .5p Rpar=1Meg noiseless +C8 11 13 .5p Rpar=1Meg noiseless +C9 14 15 .5p Rpar=1Meg noiseless +C11 15 13 .5p Rpar=1Meg noiseless +C14 N012 11 1.1p noiseless +D2 14 13 DPOWS +A10 0 INM 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +D18 3 13 DBIAS +C10 N006 0 8f Rpar=1Meg noiseless +B1 0 N005 I=10u*dnlim(uplim(V(INP),V(14)-1.3,.1), V(13)-.3, .1)+1n*V(INP) +B2 N005 0 I=10u*dnlim(uplim(V(INM),V(14)-1.29,.1), V(13)-.31, .1)+1n*V(INM) +C20 N005 0 2f Rpar=100K noiseless +G8 0 N011 13 0 .5m +G9 0 N011 14 0 .5m +C21 N011 0 200p Rpar=1K noiseless +D15 0 N006 DLIMI +C1 N008 11 .01f Rser=20Meg noiseless +C22 11 N016 .01f Rser=20Meg noiseless +C23 N022 15 .01f Rser=20Meg noiseless +C25 15 N024 .01f Rser=20Meg noiseless +C12 N016 13 3f Rser=2Meg noiseless +C15 14 N022 3f Rser=2Meg noiseless +C19 N024 13 3f Rser=2Meg noiseless +R9 12 13 36k +R11 14 12 36k +S8 14 INM N007 0 SBIAS +S9 14 INP N007 0 SBIAS +A4 0 N005 0 0 0 0 N006 0 OTA g=1m linear en=2.1n enk=20k Vhigh=1e308 Vlow=-1e308 +C26 INM 11 48.2p +R1 INM N003 125 +R7 N003 4 100 +R2 N003 5 200 +R8 N003 6 400 +R12 INP N002 125 +R13 N002 2 100 +R14 N002 1 200 +R15 N002 20 400 +R16 11 N003 400 +C27 N002 11 81.5p +C31 8 N002 33.3p +C30 7 N002 16.1p +C28 10 INM 21.1p +C32 9 INM 10.55p +C33 INP 15 48.2p +R17 15 N002 400 +C34 N003 15 81.5p +C35 16 INP 21.1p +C36 17 INP 10.55p +C37 18 N003 33.3p +C38 19 N003 16.1p +C18 N003 0 1p +C24 N002 0 1p +C4 14 INM 1p Rser=8 Rpar=2Meg noiseless +C5 INP 13 1p Rser=8 Rpar=2Meg noiseless +C6 INM 13 1p Rser=8 Rpar=2Meg noiseless +S10 N006 0 13 3 Gain +S11 13 14 3 13 Hpow +C16 15 N023 1.1p noiseless +D1 8 14 DESD +D17 13 8 DESD +D19 7 14 DESD +D20 13 7 DESD +D4 10 14 DESD +D6 9 14 DESD +D7 13 9 DESD +D10 13 10 DESD +D11 5 14 DESD +D16 6 14 DESD +D21 13 6 DESD +D22 13 5 DESD +D23 2 14 DESD +D24 4 14 DESD +D25 13 4 DESD +D26 13 2 DESD +D27 20 14 DESD +D28 1 14 DESD +D29 13 1 DESD +D30 13 20 DESD +D31 12 14 DESD +D32 3 14 DESD +D33 13 3 DESD +D34 13 12 DESD +D35 16 14 DESD +D36 17 14 DESD +D37 13 17 DESD +D38 13 16 DESD +D39 18 14 DESD +D40 19 14 DESD +D41 13 19 DESD +D42 13 18 DESD +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=265u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=1p noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=23u noiseless) +.model DBIAS D(Ron=150k Roff=1Meg Vfwd=1.4 epsilon=150m Vrev=-1.4 revepsilon=150m noiseless) +.model DIN D(Ron=100 Roff=3k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=60m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=2.5 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.5 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=70k Vfwd=400m Vrev=400m epsilon=100m revepsilon=100m noiseless) +.model DLIMI D(Ron=1 Roff=1Meg Vfwd=.5 Vrev=.5 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model Gain SW(level=2 Ron=9k Roff=12k vt=-2.2 vh=-200m noiseless) +.model Hpow SW(level=2 Ron=10 Roff=100k vt=2.2 vh=-200m ilimit=16.58m noiseless) +.ends LTC6601-1 +* +.subckt LTC6605-7 1 2 3 4 5 6 7 8 9 10 +M1 6 N016 8 8 NI temp=27 +D5 N016 8 DLIMN +M2 6 N008 9 9 PI temp=27 +D8 9 N008 DLIMP +C3 9 N008 3f Rser=2Meg noiseless +A3 N010 N012 8 8 8 8 N008 8 OTA g=250n ref=-60m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N010 N010 N010 N010 N012 N010 OTA g=500u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 8 N016 N012 N010 250n +D9 N012 N010 DLIM +C7 9 INP 1p Rser=8 Rpar=2Meg noiseless +C13 9 8 1000p +S1 N012 N010 0 N007 SHUT2 +C17 8 3 500f +S4 N008 9 0 N007 SHUT1 +S2 8 N016 0 N007 SHUT1 +A2 3 8 0 0 0 0 N007 0 SCHMITT trise=.5u tfall=.5u vt=.4 vh=0 +A1 0 INP 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +M3 10 N025 8 8 NI temp=27 +D3 N025 8 DLIMN +M4 10 N023 9 9 PI temp=27 +D12 9 N023 DLIMP +A6 N010 N024 8 8 8 8 N023 8 OTA g=300n ref=-60m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N010 N010 N010 N010 N024 N010 OTA g=500u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 8 N025 N024 N010 250n +D13 N024 N010 DLIM +S3 N024 N010 0 N007 SHUT2 +S5 N023 9 0 N007 SHUT1 +S6 8 N025 0 N007 SHUT1 +R3 6 N018 860 noiseless +R4 10 N018 860 noiseless +A8 N018 7 0 0 0 0 N015 0 OTA g=10m linear en=9n enk=20k Rout=1k Cout=2p ref=-586u Vlow=-1e308 Vhigh=1e308 +G6 N010 N024 0 N015 100µ +G7 N010 N012 0 N015 100µ +D14 N015 0 DCML +C2 9 6 .5p Rpar=1Meg noiseless +C8 6 8 .5p Rpar=1Meg noiseless +C9 9 10 .5p Rpar=1Meg noiseless +C11 10 8 .5p Rpar=1Meg noiseless +C14 N012 6 1.1p noiseless +D2 9 8 DPOWS +A10 0 INM 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +D18 3 8 DBIAS +C10 N006 0 8f Rpar=1Meg noiseless +B1 0 N005 I=10u*dnlim(uplim(V(INP),V(9)-1.3,.1), V(8)-.3, .1)+1n*V(INP) +B2 N005 0 I=10u*dnlim(uplim(V(INM),V(9)-1.29,.1), V(8)-.31, .1)+1n*V(INM) +C20 N005 0 2f Rpar=100K noiseless +G8 0 N010 8 0 .5m +G9 0 N010 9 0 .5m +C21 N010 0 200p Rpar=1K noiseless +D15 0 N006 DLIMI +C1 N008 6 .01f Rser=20Meg noiseless +C22 6 N016 .01f Rser=20Meg noiseless +C23 N023 10 .01f Rser=20Meg noiseless +C25 10 N025 .01f Rser=20Meg noiseless +C12 N016 8 3f Rser=2Meg noiseless +C15 9 N023 3f Rser=2Meg noiseless +C19 N025 8 3f Rser=2Meg noiseless +R9 7 8 36k +R11 9 7 36k +S8 9 INM N007 0 SBIAS +S9 9 INP N007 0 SBIAS +A4 0 N005 0 0 0 0 N006 0 OTA g=1m linear en=2.1n enk=20k Vhigh=1e308 Vlow=-1e308 +C26 INM 6 69.3p +R1 INM N002 125 +R7 N002 4 100 +R8 N002 5 400 +R12 INP N001 125 +R13 N001 2 100 +R15 N001 1 400 +R16 6 N002 400 +C27 N001 6 114.8p +C33 INP 10 69.3p +R17 10 N001 400 +C34 N002 10 114.8p +C18 N002 0 300f +C24 N001 0 300f +C4 9 INM 1p Rser=8 Rpar=2Meg noiseless +C5 INP 8 1p Rser=8 Rpar=2Meg noiseless +C6 INM 8 1p Rser=8 Rpar=2Meg noiseless +S10 N006 0 8 3 Gain +S11 8 9 3 8 Hpow +C16 10 N024 1.1p noiseless +D16 5 9 DESD +D21 8 5 DESD +D23 2 9 DESD +D24 4 9 DESD +D25 8 4 DESD +D26 8 2 DESD +D27 1 9 DESD +D30 8 1 DESD +D31 7 9 DESD +D32 3 9 DESD +D33 8 3 DESD +D34 8 7 DESD +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=265u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=1p noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=23u noiseless) +.model DBIAS D(Ron=150k Roff=1Meg Vfwd=1.4 epsilon=150m Vrev=-1.4 revepsilon=150m noiseless) +.model DIN D(Ron=100 Roff=3k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=60m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=2.5 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.5 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=70k Vfwd=400m Vrev=400m epsilon=100m revepsilon=100m noiseless) +.model DLIMI D(Ron=1 Roff=1Meg Vfwd=.5 Vrev=.5 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model Gain SW(level=2 Ron=9k Roff=12k vt=-2.2 vh=-200m noiseless) +.model Hpow SW(level=2 Ron=10 Roff=100k vt=2.2 vh=-200m ilimit=16.58m noiseless) +.ends LTC6605-7 +* +.subckt LTC6605-10 1 2 3 4 5 6 7 8 9 10 +M1 6 N016 8 8 NI temp=27 +D5 N016 8 DLIMN +M2 6 N008 9 9 PI temp=27 +D8 9 N008 DLIMP +C3 9 N008 3f Rser=2Meg noiseless +A3 N010 N012 8 8 8 8 N008 8 OTA g=250n ref=-60m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N010 N010 N010 N010 N012 N010 OTA g=500u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 8 N016 N012 N010 250n +D9 N012 N010 DLIM +C7 9 INP 1p Rser=8 Rpar=2Meg noiseless +C13 9 8 1000p +S1 N012 N010 0 N007 SHUT2 +C17 8 3 500f +S4 N008 9 0 N007 SHUT1 +S2 8 N016 0 N007 SHUT1 +A2 3 8 0 0 0 0 N007 0 SCHMITT trise=.5u tfall=.5u vt=.4 vh=0 +A1 0 INP 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +M3 10 N025 8 8 NI temp=27 +D3 N025 8 DLIMN +M4 10 N023 9 9 PI temp=27 +D12 9 N023 DLIMP +A6 N010 N024 8 8 8 8 N023 8 OTA g=300n ref=-60m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N010 N010 N010 N010 N024 N010 OTA g=500u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 8 N025 N024 N010 250n +D13 N024 N010 DLIM +S3 N024 N010 0 N007 SHUT2 +S5 N023 9 0 N007 SHUT1 +S6 8 N025 0 N007 SHUT1 +R3 6 N018 860 noiseless +R4 10 N018 860 noiseless +A8 N018 7 0 0 0 0 N015 0 OTA g=10m linear en=9n enk=20k Rout=1k Cout=2p ref=-586u Vlow=-1e308 Vhigh=1e308 +G6 N010 N024 0 N015 100µ +G7 N010 N012 0 N015 100µ +D14 N015 0 DCML +C2 9 6 .5p Rpar=1Meg noiseless +C8 6 8 .5p Rpar=1Meg noiseless +C9 9 10 .5p Rpar=1Meg noiseless +C11 10 8 .5p Rpar=1Meg noiseless +C14 N012 6 1.1p noiseless +D2 9 8 DPOWS +A10 0 INM 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +D18 3 8 DBIAS +C10 N006 0 8f Rpar=1Meg noiseless +B1 0 N005 I=10u*dnlim(uplim(V(INP),V(9)-1.3,.1), V(8)-.3, .1)+1n*V(INP) +B2 N005 0 I=10u*dnlim(uplim(V(INM),V(9)-1.29,.1), V(8)-.31, .1)+1n*V(INM) +C20 N005 0 2f Rpar=100K noiseless +G8 0 N010 8 0 .5m +G9 0 N010 9 0 .5m +C21 N010 0 200p Rpar=1K noiseless +D15 0 N006 DLIMI +C1 N008 6 .01f Rser=20Meg noiseless +C22 6 N016 .01f Rser=20Meg noiseless +C23 N023 10 .01f Rser=20Meg noiseless +C25 10 N025 .01f Rser=20Meg noiseless +C12 N016 8 3f Rser=2Meg noiseless +C15 9 N023 3f Rser=2Meg noiseless +C19 N025 8 3f Rser=2Meg noiseless +R9 7 8 36k +R11 9 7 36k +S8 9 INM N007 0 SBIAS +S9 9 INP N007 0 SBIAS +A4 0 N005 0 0 0 0 N006 0 OTA g=1m linear en=2.1n enk=20k Vhigh=1e308 Vlow=-1e308 +C26 INM 6 48.2p +R1 INM N002 125 +R7 N002 4 100 +R8 N002 5 400 +R12 INP N001 125 +R13 N001 2 100 +R15 N001 1 400 +R16 6 N002 400 +C27 N001 6 81.5p +C33 INP 10 48.2p +R17 10 N001 400 +C34 N002 10 81.5p +C18 N002 0 300f +C24 N001 0 300f +C4 9 INM 1p Rser=8 Rpar=2Meg noiseless +C5 INP 8 1p Rser=8 Rpar=2Meg noiseless +C6 INM 8 1p Rser=8 Rpar=2Meg noiseless +S10 N006 0 8 3 Gain +S11 8 9 3 8 Hpow +C16 10 N024 1.1p noiseless +D16 5 9 DESD +D21 8 5 DESD +D23 2 9 DESD +D24 4 9 DESD +D25 8 4 DESD +D26 8 2 DESD +D27 1 9 DESD +D30 8 1 DESD +D31 7 9 DESD +D32 3 9 DESD +D33 8 3 DESD +D34 8 7 DESD +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=265u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=1p noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=23u noiseless) +.model DBIAS D(Ron=150k Roff=1Meg Vfwd=1.4 epsilon=150m Vrev=-1.4 revepsilon=150m noiseless) +.model DIN D(Ron=100 Roff=3k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=60m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=2.5 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.5 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=70k Vfwd=400m Vrev=400m epsilon=100m revepsilon=100m noiseless) +.model DLIMI D(Ron=1 Roff=1Meg Vfwd=.5 Vrev=.5 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model Gain SW(level=2 Ron=9k Roff=12k vt=-2.2 vh=-200m noiseless) +.model Hpow SW(level=2 Ron=10 Roff=100k vt=2.2 vh=-200m ilimit=16.58m noiseless) +.ends LTC6605-10 +* +.subckt LTC6605-14 1 2 3 4 5 6 7 8 9 10 +M1 6 N016 8 8 NI temp=27 +D5 N016 8 DLIMN +M2 6 N008 9 9 PI temp=27 +D8 9 N008 DLIMP +C3 9 N008 3f Rser=2Meg noiseless +A3 N010 N012 8 8 8 8 N008 8 OTA g=250n ref=-60m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N010 N010 N010 N010 N012 N010 OTA g=500u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 8 N016 N012 N010 250n +D9 N012 N010 DLIM +C7 9 INP 1p Rser=8 Rpar=2Meg noiseless +C13 9 8 1000p +S1 N012 N010 0 N007 SHUT2 +C17 8 3 500f +S4 N008 9 0 N007 SHUT1 +S2 8 N016 0 N007 SHUT1 +A2 3 8 0 0 0 0 N007 0 SCHMITT trise=.5u tfall=.5u vt=.4 vh=0 +A1 0 INP 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +M3 10 N025 8 8 NI temp=27 +D3 N025 8 DLIMN +M4 10 N023 9 9 PI temp=27 +D12 9 N023 DLIMP +A6 N010 N024 8 8 8 8 N023 8 OTA g=300n ref=-60m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N010 N010 N010 N010 N024 N010 OTA g=500u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 8 N025 N024 N010 250n +D13 N024 N010 DLIM +S3 N024 N010 0 N007 SHUT2 +S5 N023 9 0 N007 SHUT1 +S6 8 N025 0 N007 SHUT1 +R3 6 N018 860 noiseless +R4 10 N018 860 noiseless +A8 N018 7 0 0 0 0 N015 0 OTA g=10m linear en=9n enk=20k Rout=1k Cout=2p ref=-586u Vlow=-1e308 Vhigh=1e308 +G6 N010 N024 0 N015 100µ +G7 N010 N012 0 N015 100µ +D14 N015 0 DCML +C2 9 6 .5p Rpar=1Meg noiseless +C8 6 8 .5p Rpar=1Meg noiseless +C9 9 10 .5p Rpar=1Meg noiseless +C11 10 8 .5p Rpar=1Meg noiseless +C14 N012 6 1.1p noiseless +D2 9 8 DPOWS +A10 0 INM 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +D18 3 8 DBIAS +C10 N006 0 8f Rpar=1Meg noiseless +B1 0 N005 I=10u*dnlim(uplim(V(INP),V(9)-1.3,.1), V(8)-.3, .1)+1n*V(INP) +B2 N005 0 I=10u*dnlim(uplim(V(INM),V(9)-1.29,.1), V(8)-.31, .1)+1n*V(INM) +C20 N005 0 2f Rpar=100K noiseless +G8 0 N010 8 0 .5m +G9 0 N010 9 0 .5m +C21 N010 0 200p Rpar=1K noiseless +D15 0 N006 DLIMI +C1 N008 6 .01f Rser=20Meg noiseless +C22 6 N016 .01f Rser=20Meg noiseless +C23 N023 10 .01f Rser=20Meg noiseless +C25 10 N025 .01f Rser=20Meg noiseless +C12 N016 8 3f Rser=2Meg noiseless +C15 9 N023 3f Rser=2Meg noiseless +C19 N025 8 3f Rser=2Meg noiseless +R9 7 8 36k +R11 9 7 36k +S8 9 INM N007 0 SBIAS +S9 9 INP N007 0 SBIAS +A4 0 N005 0 0 0 0 N006 0 OTA g=1m linear en=2.1n enk=20k Vhigh=1e308 Vlow=-1e308 +C26 INM 6 48.2p +R1 INM N002 125 +R7 N002 4 100 +R8 N002 5 200 +R12 INP N001 125 +R13 N001 2 100 +R15 N001 1 200 +R16 6 N002 200 +C27 N001 6 81.5p +C33 INP 10 48.2p +R17 10 N001 200 +C34 N002 10 81.5p +C18 N002 0 300f +C24 N001 0 300f +C4 9 INM 1p Rser=8 Rpar=2Meg noiseless +C5 INP 8 1p Rser=8 Rpar=2Meg noiseless +C6 INM 8 1p Rser=8 Rpar=2Meg noiseless +S10 N006 0 8 3 Gain +S11 8 9 3 8 Hpow +C16 10 N024 1.1p noiseless +D16 5 9 DESD +D21 8 5 DESD +D23 2 9 DESD +D24 4 9 DESD +D25 8 4 DESD +D26 8 2 DESD +D27 1 9 DESD +D30 8 1 DESD +D31 7 9 DESD +D32 3 9 DESD +D33 8 3 DESD +D34 8 7 DESD +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=265u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=1p noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=23u noiseless) +.model DBIAS D(Ron=150k Roff=1Meg Vfwd=1.4 epsilon=150m Vrev=-1.4 revepsilon=150m noiseless) +.model DIN D(Ron=100 Roff=3k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=60m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=2.5 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.5 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=70k Vfwd=400m Vrev=400m epsilon=100m revepsilon=100m noiseless) +.model DLIMI D(Ron=1 Roff=1Meg Vfwd=.5 Vrev=.5 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model Gain SW(level=2 Ron=9k Roff=12k vt=-2.2 vh=-200m noiseless) +.model Hpow SW(level=2 Ron=10 Roff=100k vt=2.2 vh=-200m ilimit=16.58m noiseless) +.ends LTC6605-14 +* +.subckt LT1634-1.25 1 2 +M1 1 N004 2 2 N temp=27 +C3 1 2 10p +R1 1 N002 500K tc = 0 -.25u 0 30p noiseless +D1 2 1 Y +R3 N002 2 500K +A1 N002 2 2 2 2 2 N003 2 OTA Vhigh=0 Vlow=-2 Ref=.6248 G=10u Iout=100u G=100u +G1 2 N004 2 N003 1µ +R5 N004 2 1Meg +C1 N003 N002 80p Rser=3Meg Rpar=500Meg +C2 1 N004 5p Rser=50Meg +.model N VDMOS(Vto=0 Kp=.05 Is=0) +.model Y D(Ron=15 Roff=10Meg Vfwd=.4 epsilon=.5 noiseless) +.ends LT1634-1.25 +* +.subckt LT1634-2.5 1 2 +M1 1 N005 2 2 N temp=27 +C3 1 2 10p +R1 1 N003 500K tc = 0 -.25u 0 30p noiseless +D1 2 1 Y +R3 N003 2 500K +A1 N003 2 2 2 2 2 N004 2 OTA Vhigh=0 Vlow=-4 Ref=1.2496 G=10u Iout=100u G=100u +G1 2 N005 2 N004 1µ +R5 N005 2 1Meg +C1 N004 N003 100p Rser=8Meg Rpar=500Meg +C2 1 N005 5p Rser=50Meg +.model N VDMOS(Vto=0 Kp=.01 Is=0) +.model Y D(Ron=15 Roff=10Meg Vfwd=.4 epsilon=.5 noiseless) +.ends LT1634-2.5 +* +.subckt LT1634-4.096 1 2 +M1 1 N005 2 2 N temp=27 +C3 1 2 10p +R1 1 N003 500K tc = 0 -.45u 0 55p noiseless +D1 2 1 Y +R3 N003 2 500K +A1 N003 2 2 2 2 2 N004 2 OTA Vhigh=0 Vlow=-4 Ref=2.047 G=10u Iout=100u G=100u +G1 2 N005 2 N004 1µ +R5 N005 2 1Meg +C1 N004 N003 40p Rser=8Meg Rpar=500Meg +C2 1 N005 2.5p Rser=50Meg +.model N VDMOS(Vto=0 Kp=.01 Is=0) +.model Y D(Ron=15 Roff=10Meg Vfwd=.4 epsilon=.5 noiseless) +.ends LT1634-4.096 +* +.subckt LT1634-5 1 2 +M1 1 N005 2 2 N temp=27 +C3 1 2 10p +R1 1 N003 500K tc = 0 -.4u 0 50p noiseless +D1 2 1 Y +R3 N003 2 500K +A1 N003 2 2 2 2 2 N004 2 OTA Vhigh=0 Vlow=-4 Ref=2.499 G=10u Iout=100u G=100u +G1 2 N005 2 N004 1µ +R5 N005 2 1Meg +C1 N004 N003 50p Rser=8Meg Rpar=500Meg +C2 1 N005 2.5p Rser=50Meg +.model N VDMOS(Vto=0 Kp=.01 Is=0) +.model Y D(Ron=15 Roff=10Meg Vfwd=.4 epsilon=.5 noiseless) +.ends LT1634-5 +* +* +* Copyright (c) 1998-2020 Analog Devices, Inc. All rights reserved. +* +.subckt LT6020 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=37f +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.3,.1), V(4)+1.1, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.29,.1), V(4)+1.09, .1)+1n*V(2) +C10 N004 0 10f Rpar=100K noiseless +M1 5 N012 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +M2 5 N006 3 3 PI temp=27 +D8 3 N006 DLIMP +C3 3 N006 10p Rser=1.2Meg noiseless +C11 5 4 1p Rpar=1g noiseless +D6 N012 4 DLIMN +A4 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=46.1n enk=.202 Vhigh=2.2 Vlow=-2.5 +C16 N008 5 2.2p Rser=30k noiseless +A5 N005 0 N007 N007 N007 N007 N008 N007 OTA g=6u linear Vhigh=1e308 Vlow=-1e308 +D12 1 3 DPROT +D13 2 3 DPROT +D9 N008 N007 DLIM +C7 3 1 .75p Rser=5k Rpar=34G noiseless +C13 3 4 100p +C1 N005 0 1p Rpar=2k noiseless +G2 0 N007 4 0 .5m +G4 0 N007 3 0 .5m +C18 N007 0 200p Rpar=1K noiseless +C4 3 2 .75p Rser=5k Rpar=34G noiseless +C6 1 4 .75p Rser=5k Rpar=34G noiseless +C8 2 4 .75p Rser=5k Rpar=34G noiseless +C5 N006 5 300f +C9 5 N012 300f +D3 N005 N010 DSLIM2 +L1 N010 0 100µ Rpar=1k Cpar=800p noiseless +C12 N012 4 10p Rser=1.2Meg noiseless +C14 3 N006 100f +C15 N012 4 100f +G3 3 N012 N008 N007 1.5µ +G1 N006 4 N007 N008 1.5µ +D4 3 N009 DS +VS1 N009 4 0 +F1 3 N012 VS1 .1 +F2 N006 4 VS1 .1 +C20 2 1 1p Rser=10k Rpar=100Meg noiseless +G5 2 4 2 1 10n vto=0 dir=1 +G8 1 4 1 2 10n vto=0 dir=1 +G9 3 2 4 2 10µ vto=-1.2 dir=1 +G10 2 4 2 3 30µ vto=-1.4 dir=1 +G11 3 1 4 1 10µ vto=-1.2 dir=1 +G12 1 4 1 3 30µ vto=-1.4 dir=1 +S4 3 1 2 1 SBIAS +S5 2 3 1 2 SBIAS +D7 N005 0 DSLIM1 +D10 3 4 DP +S6 3 N006 5 3 SUPLIM +.model DP D(Ron=1k Roff=1G vfwd=1.5 epsilon=1 ilimit=88.1u) +.model DPROT D(Ron=1k Roff=24G Vfwd=1 epsilon=500m noiseless) +.model SBIAS SW(level=2 Ron=100k Roff=100G vt=5.2 vh=-200m ilimit=1u noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=1 Vrev=1 epsilon=100m revepsilon=100m noiseless) +.model DSLIM1 D(Ron=10 Roff=4k vfwd=100m epsilon=50m vrev=100m revepsilon=50m ilimit=1m revilimit=1m noiseless) +.model DSLIM2 D(Ron=250 Roff=4k vfwd=650m epsilon=200m vrev=650m revepsilon=200m ilimit=4m revilimit=4m noiseless) +.model DS D(Ron=24Meg Roff=1G vfwd=1 epsilon=500m ilimit=31n noiseless) +.model SUPLIM SW(Ron=1k Roff=10G vt=-80m vh=-50m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=800m Vrev=-.3 epsilon=100m revepsilon=10m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=600m Vrev=-.3 epsilon=100m revepsilon=10m noiseless) +.ends LT6020 +* +.subckt LT6020-1 1 2 3 4 5 6 7 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=37f +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.3,.1), V(4)+1.1, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.29,.1), V(4)+1.09, .1)+1n*V(2) +C10 N004 0 10f Rpar=100K noiseless +M1 5 N013 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +M2 5 N007 3 3 PI temp=27 +D8 3 N007 DLIMP +C3 3 N007 10p Rser=1.2Meg noiseless +C11 5 4 1p Rpar=1g noiseless +D6 N013 4 DLIMN +A4 0 N004 0 0 0 0 N006 0 OTA g=1m linear en=46.1n enk=.202 Vhigh=2.2 Vlow=-2.5 +C16 N009 5 2.2p Rser=30k noiseless +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=6u linear Vhigh=1e308 Vlow=-1e308 +D12 1 3 DPROT +D13 2 3 DPROT +D9 N009 N008 DLIM +C7 3 1 .75p Rser=5k Rpar=34G noiseless +C13 3 4 100p +S1 N009 N008 N005 0 SHUT +S2 3 N007 N005 0 SHUT +S3 N013 4 N005 0 SHUT +C1 N006 0 1p Rpar=2k noiseless +C17 3 6 100f noiseless +G2 0 N008 4 0 .5m +G4 0 N008 3 0 .5m +C18 N008 0 200p Rpar=1K noiseless +C4 3 2 .75p Rser=5k Rpar=34G noiseless +C6 1 4 .75p Rser=5k Rpar=34G noiseless +C8 2 4 .75p Rser=5k Rpar=34G noiseless +D2 4 6 DPROT +C5 N007 5 300f +C9 5 N013 300f +D3 N006 N011 DSLIM2 +L1 N011 0 100µ Rpar=1k Cpar=800p noiseless +C12 N013 4 10p Rser=1.2Meg noiseless +C14 3 N007 100f +C15 N013 4 100f +G3 3 N013 N009 N008 1.5µ +G1 N007 4 N008 N009 1.5µ +D4 3 N010 DS +VS1 N010 4 0 +F1 3 N013 VS1 .1 +F2 N007 4 VS1 .1 +C20 2 1 1p Rser=10k Rpar=100Meg noiseless +G5 2 4 2 1 10n vto=0 dir=1 +G8 1 4 1 2 10n vto=0 dir=1 +G9 3 2 4 2 10µ vto=-1.2 dir=1 +G10 2 4 2 3 30µ vto=-1.4 dir=1 +G11 3 1 4 1 10µ vto=-1.2 dir=1 +G12 1 4 1 3 30µ vto=-1.4 dir=1 +S4 3 1 2 1 SBIAS +S5 2 3 1 2 SBIAS +D1 4 7 DPROT +D5 3 6 DEN +A2 6 7 0 0 0 0 N016 0 SCHMITT vt=1.25 vh=450m trise=100u tfall=10u +A3 3 7 0 0 0 0 N017 0 SCHMITT vt=2.9 vh=50m trise=100u tfall=10u +A6 N016 0 0 N017 0 N005 0 0 AND trise=50u tfall=100u +D7 N006 0 DSLIM1 +D10 3 4 DP +S6 3 N007 5 3 SUPLIM +.model DP D(Ron=1k Roff=1G vfwd=1.5 epsilon=1 ilimit=88.1u) +.model DEN D(Ron=100k Roff=1G vfwd=1 epsilon=500m ilimit=100n noiseless) +.model DPROT D(Ron=1k Roff=24G Vfwd=1 epsilon=500m noiseless) +.model SBIAS SW(level=2 Ron=100k Roff=100G vt=5.2 vh=-200m ilimit=1u noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=1 Vrev=1 epsilon=100m revepsilon=100m noiseless) +.model DSLIM1 D(Ron=10 Roff=4k vfwd=100m epsilon=50m vrev=100m revepsilon=50m ilimit=1m revilimit=1m noiseless) +.model DSLIM2 D(Ron=250 Roff=4k vfwd=650m epsilon=200m vrev=650m revepsilon=200m ilimit=4m revilimit=4m noiseless) +.model DS D(Ron=24Meg Roff=1G vfwd=1 epsilon=500m ilimit=31n noiseless) +.model SHUT SW(Ron=1 Roff=100G vt=.5 vh=-.2 noiseless) +.model SUPLIM SW(Ron=1k Roff=10G vt=-80m vh=-50m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=800m Vrev=-.3 epsilon=100m revepsilon=10m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=600m Vrev=-.3 epsilon=100m revepsilon=10m noiseless) +.ends LT6020-1 +* +.subckt LT6375 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +A1 INM INP 0 0 0 0 0 0 OTA g=0 in=88f ink=289 +C7 9 INP 2.5p Rser=1k Rpar=100G noiseless +D8 15 INP DESD +D10 15 INM DESD +GNOI INP INM N009 0 1µ +S9 0 N009 9 INM SNOI +A6 15 9 0 0 0 0 N014 0 OTA g=2u iout=1u ref=-2.5 Rout=1Meg Cout=100f vlow=-1e308 vhigh=1e308 +S4 N007 15 On 0 SBiasN +D13 9 N007 DBiasDrop +D14 INM N007 DBiasOTT +D15 INP N007 DBiasOTT +C14 N007 15 100f +D16 INM INP D1Meg +C17 8 INM 1.7p +R1 12 INM 19k +R2 11 INM 38k +R3 10 INM 23.75k +R4 INP 3 19k +R5 INP 4 38k +R6 INP 5 23.75k +A8 N014 0 0 N016 0 0 On 0 AND trise=35u +B1 0 X0 I=10u*dnlim(uplim(V(INP),V(15)+76.1,.1), V(15)-.15, .1)+1n*V(INP)-10.723162n +B2 X0 0 I=10u*dnlim(uplim(V(INM),V(15)+76.1,.1), V(15)-.16, .1)+1n*V(INM) +C1 X0 0 50f Rpar=100K noiseless +M1 N011 NG 15 15 NI temp=27 +C2 9 8 1p Rpar=1g noiseless +D1 NG 15 DLIMN1 +M2 8 PG 9 9 PI temp=27 +A3 N008 X4 15 15 15 15 PG 15 OTA g=2u ref=-.305 linear vlow=-1e308 vhigh=1e308 +C5 8 15 1p Rpar=1g noiseless +D2 NG 15 DLIMN2 +C11 X4 8 .6p +A5 N004 0 N008 N008 N008 N008 X4 N008 OTA g=25u asym isource=1.5u isink=-2.5u Vlow=-1e308 Vhigh=1e308 +G1 15 NG X4 N008 140n +D3 X4 N008 DLIM +C12 9 15 10p +C13 X1 0 25f +G2 0 N008 15 0 .5m +G3 0 N008 9 0 .5m +C15 N008 0 200p Rpar=1K noiseless +D5 9 PG DLIMP +D6 X1 0 DLIM0 +D7 15 8 DESD +D9 8 N011 DNR +C18 N011 15 100f Rpar=10Meg noiseless +D11 PG 9 DLIMPR +S1 9 PG 0 On SHUT +S2 NG 15 0 On SHUT +G4 0 N003 X1 0 1µ +D17 0 X1 DNLIN +C20 N004 0 25f noiseless Rpar=1Meg +G5 0 N004 N003 0 1µ +S3 N008 X4 15 8 SGK +C4 9 INM 2.5p Rser=1k Rpar=100G noiseless +C6 INP 15 2.5p Rser=1k Rpar=100G noiseless +C8 INM 15 2.5p Rser=1k Rpar=100G noiseless +C21 15 10 500f +C29 15 INM 1p Rser=1k noiseless +C30 15 15 1p Rser=1k noiseless +C3 9 PG 1p Rser=300k noiseless +C10 NG 15 1p Rser=700k noiseless +C22 15 11 500f +C23 15 12 500f +C24 15 3 500f +C25 15 4 500f +C26 15 5 500f +C27 15 INP 950f +R13 N001 INM 95k +R14 8 N001 95k +C31 N001 15 3p +R7 N017 6 95k +R8 INP N017 95k +C28 N017 15 3p +C32 INM INP 2p +C19 N003 0 54.26f noiseless Rser=2.667Meg Rpar=1Meg +R10 N006 14 95k +R11 INM N006 95k +C33 N006 15 3p +R12 N013 1 95k +R15 INP N013 95k +C34 N013 15 3p +A2 N009 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=5 +S5 0 N005 9 INM SNOI +A9 N005 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=5 +GNOI_V1 X0 0 N005 0 10n +D18 9 7 DST +A10 7 9 0 0 0 0 N016 0 SCHMITT vt=-1.85 vh=-.4 trise=1u +A7 0 X0 On 0 0 0 X1 0 OTA g=1u linear en=18n enk=3 vlow=-1e308 vhigh=1e308 +B3 9 15 I=(.5+.5*tanh((V(On)-.5)/100m))*(41.5u-.762u*V(9,15)) +R16 9 15 5Meg noiseless +D4 9 15 DLK +C16 INP 6 1.7p +C35 6 15 1p +.model DESD D(Ron=1k Roff=1G vfwd=700m epsilon=100m noiseless) +.model SNOI SW(Ron=1 Roff=1Meg vt=1.2 vh=-100m noiseless) +.model DST D(Ron=200 Roff=1G vfwd=100m epsilon=-100m ilimit=10u) +.model DLK D(Ron=10k Roff=1G vfwd=1 epsilon=500m ilimit=3.4u) +.model NI VDMOS(Vto=300m kp=60m Mtriode=.9 lambda=.01) +.model PI VDMOS(Vto=-300m Kp=120m lambda=.01 mtriode=.17 pchan is=0) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=1 epsilon=100m Vrev=1 epsilon=100m noiseless) +.model DNLIN D(Roff=1.8Meg Ron=800k vfwd=0 epsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=8Meg Vfwd=900m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.model SHUT SW(level=2 Ron=10k Roff=100G vt=-.5 vh=-.2 noiseless) +.model DNR D(Ron=10 Roff=1G Vfwd=2m epsilon=10m noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.2 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=44n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=840m epsilon=10m noiseless) +.model DLIMPR D(Ron=5Meg Roff=1G Vfwd=100m epsilon=10m noiseless) +.model SGK SW(level=2 Ron=65k Roff=100G vt=-260m vh=150m oneway epsilon=10m noiseless) +.model SBiasN SW(level=2 Ron=10k Roff=1g vt=.5 vh=-.2 ilimit=28u noiseless) +.model DBiasDrop D(Ron=1k Roff=1G vfwd=2.27 epsilon=500m noiseless) +.model DBiasOTT D(Ron=500 Roff=1G vfwd=700m epsilon=200m noiseless) +.model D1Meg D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=10n revilimit=10n noiseless) +.ends LT6375 +* +.subckt LTC6258 1 2 3 4 5 6 +B1 0 N007 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1) +B2 N007 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C10 N007 0 .1f Rpar=100K noiseless +M1 N016 N014 5 5 NI temp=27 +C2 4 3 10f Rpar=10Meg noiseless +M2 N008 N004 4 4 PI temp=27 +D6 N014 5 DLIMN +A4 0 N007 0 0 0 0 N006 0 OTA g=1u linear en=35n*uplim((1+freq/110k)**1.1,7,1)/(1+(freq/800k)**5.5) enk=20 Vlow=-1e308 Vhigh=1e308 +C16 N011 3 6.3p noiseless +C7 4 1 600f Rpar=12G noiseless +D14 4 N004 DLIMP +C4 2 1 650f Rpar=2Meg noiseless +A6 N010 0 N012 N009 N009 N009 N011 N009 OTA g=52.1u iout=2.6u Vlow=-1e308 Vhigh=1e308 +A5 N009 N011 N012 N009 N009 N009 N004 N009 OTA g=12n ref=-290m linear Vlow=-1e308 Vhigh=1e308 +C14 4 5 20p Rpar=100Meg noiseless +S4 5 4 N009 N012 SWSP +C13 4 5 10p +A3 6 5 N009 N009 N009 N009 N017 N009 SCHMITT vt=.9 vh=0 trise=286u tfall=9u +G2 0 REF 4 0 50m +G3 0 REF 5 0 50m +C19 REF 0 100p Rpar=10 noiseless +GESD1 2 4 2 4 1 vto=600m dir=1 +GESD2 5 2 5 2 1 vto=600m dir=1 +D1 3 4 DESD +D2 5 3 DESD +A8 N009 N011 N012 N009 N009 N009 N014 N009 OTA g=12n linear ref=290m vlow=-1e308 vhigh=1e308 +C12 N011 N013 80p +C20 N011 N009 1p +D3 N011 N009 DANTISAT +R3 N008 3 10 noiseless +I1 3 N008 2.5m +D4 3 N016 DSAT +I2 N016 3 1µ +R4 N009 REF 10 noiseless +A7 N009 REF 4 4 4 4 0 4 OTA g=100m asym isource=10m isink=-1u vlow=-1e308 vhigh=1e308 +A9 REF N009 0 0 0 0 5 0 OTA g=100m asym isource=10m isink=-1u vlow=-1e308 vhigh=1e308 +D5 2 1 DIN +C11 3 5 10f Rpar=10Meg noiseless +A10 N013 N009 N009 N009 N009 N009 N013 N009 OTA g=33u iout=1u vlow=-1e308 vhigh=1e308 +C15 4 N004 1f +C17 N014 5 1f +C18 N006 0 486f Rser=818K Rpar=1Meg noiseless +G4 0 N010 N006 0 1µ +C21 N010 0 40f Rpar=1Meg noiseless +D7 4 6 Dshut +D8 N011 N009 DGAINVR +A11 N017 N009 N009 N009 N009 N009 N012 N009 BUF trise=5u +C1 1 5 600f Rpar=12G noiseless +C3 4 2 600f Rpar=12G noiseless +C5 2 5 600f Rpar=12G noiseless +S7 4 5 N012 N009 SWP +A2 2 1 0 0 0 0 0 0 OTA g=0 incm=400f*(1+exp((freq-200k)/100k))/(1+exp((freq-400k)/100k))**1.5 +S1 N005 2 N012 N009 SB1 +A1 2 4 5 5 5 5 N005 5 OTA g=10n asym isource=.1n isink=-10n ref=-1 vlow=-1e308 vhigh=1e308 +C8 N005 2 100f +C22 4 N005 10f Rpar=1.4G noiseless +C23 N005 5 10f Rpar=1.4G noiseless +A13 1 N009 N018 5 5 5 1 5 OTA g=1.5n asym isource=20n isink=-1.5n vlow=-1e308 vhigh=1e308 +A12 N017 N009 5 5 5 5 N018 5 SCHMITT trise=5u +.model Dshut D(Ron=10k Roff=100Meg vfwd=600m epsilon=300m ilimit=60n noiseless) +.model SWP SW(level=2 Roff=1G Ron=3k vt=.5 vh=-.1 ilimit=1.1u noiseless) +.model SWSP SW(level=2 Ron=1G Ron=10k vt=-.5 vh=-.1 ilimit=3.62u noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model NI VDMOS(Vto=300m kp=15m mtriode=.75 lambda=.01 noiseless) +.model PI VDMOS(Vto=-300m kp=15m mtriode=.9 lambda=.01 pchan is=0 noiseless) +.model DIN D(Ron=110 Roff=100g Vfwd=1.4 Vrev=1.4 epsilon=800m revepsilon=800m noiseless) +.model SB1 SW(level=2 Ron=10k Roff=1G vt=.5 vh=-.1 ilimit=4n noiseless) +.model DLIMP D(Ron=10k Roff=100Meg Vfwd=1.45 Vrev=320m epsilon=200m revepsilon=20m noiseless) +.model DLIMN D(Ron=10k Roff=100Meg Vfwd=2 Vrev=320m epsilon=200m revepsilon=20m noiseless) +.model DANTISAT D(Ron=1k Roff=29.75Meg vfwd=2 epsilon=100m vrev=2 revepsilon=100m noiseless) +.model DGAINVR D(Ron=40Meg Roff=5.4Meg vfwd=21m epsilon=18m vrev=21m revepsilon=18m noiseless) +.model DSAT D(Ron=10 Roff=7k vfwd=67m epsilon=30m noiseless) +.ends LTC6258 +* +.subckt LTC2063 1 2 3 4 5 6 +B1 0 N005 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1) +B2 N005 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C10 N005 0 .1f Rpar=100K noiseless +M1 3 NG 5 5 NI temp=27 +C2 4 3 8p Rpar=10G noiseless +M2 3 PG 4 4 PI temp=27 +A4 N005 0 0 0 0 0 X1 0 OTA g=10m linear en=230n*uplim((1+freq/1.5k)**1.8,10,2)/(uplim((1+freq/9k)**2,6,2)*MIN((1+exp((freq-50k)/8k)),18)) Vlow=-1e308 Vhigh=1e308 +C16 XC N010 8n +C7 4 N006 350f Rpar=10G noiseless +C4 N008 N006 3.3p Rser=1k noiseless +C14 4 5 20p +C13 4 5 10p +A3 6 5 0 0 0 0 N004 0 SCHMITT vt=.9 vh=0 trise=500u tfall=100u +G2 0 Mid 4 0 5m +G3 0 Mid 5 0 5m +GESD1 N008 4 N008 4 1 vto=600m dir=1 +GESD2 5 N008 5 N008 1 vto=600m dir=1 +GESD3 N006 4 N006 4 1 vto=600m dir=1 +GESD4 5 N006 5 N006 1 vto=600m dir=1 +D1 3 4 DESD +D2 5 3 DESD +C20 XC 0 1p +D3 XC 0 DANTISAT +C11 3 5 8p Rpar=10G noiseless +C15 4 PG 200f Rser=45Meg Rpar=200Meg noiseless +G4 0 N007 X1 0 1µ +C21 N007 0 250p Rpar=1Meg noiseless +D7 4 6 Dshut +C1 N006 5 350f Rpar=20G noiseless +C3 4 N008 350f Rpar=10G noiseless +C5 N008 5 350f Rpar=20G noiseless +L1 X1 0 16.4m cpar=442p rser=102 rpar=3.02k noiseless +R5 N008 2 10K noiseless +C6 NG 5 200f Rser=45Meg Rpar=200Meg noiseless +C8 3 NG 1f +C17 PG 3 1f +G7 4 PG Mid PG 1m vto=.9 dir=1 +G5 NG 5 NG Mid 1m vto=1.2 dir=1 +G6 0 N010 3 Mid 2m +C18 N010 0 1n Rpar=500 noiseless +S2 4 PG 0 N004 SOFF +S3 5 NG 0 N013 SOFF +S4 4 5 N004 0 SPOW2 +S5 4 5 N004 0 SPOW1 +D4 4 5 DPOWSD +A7 0 XC 4 4 4 4 PG 4 OTA g=12n linear ref=-319.4m vlow=-1e308 vhigh=1e308 +A9 0 XC 5 5 5 5 NG 5 OTA g=12n linear ref=319.4m vlow=-1e308 vhigh=1e308 +R4 N006 1 10K noiseless +A8 1 0 0 0 0 0 0 0 OTA g=0 in=12f*(1+freq/300)**.7 +A1 2 0 0 0 0 0 0 0 OTA g=0 in=12f*(1+freq/300)**.7 +S1 N009 XC 0 N004 SOFF2 +D5 N009 0 DOFF +C12 XC N009 100f +A2 N004 0 0 0 0 0 N013 0 BUF trise=100u +R6 Mid 0 100 noiseless +A6 0 N007 0 0 0 0 XC 0 OTA g=1.1m iout=28.1u vlow=-1e308 vhigh=1e308 +B5 0 XC I=uplim(dnlim(1-dnlim(10*(V(XC)+200m),0,100m),0,100m)*dnlim(100u*(V(X1)-100m),0,.1u),50u,1u) +B6 XC 0 I=uplim(dnlim(1-dnlim(-10*(V(XC)-200m),0,100m),0,100m)*dnlim(80u*(-100m-V(X1)),0,.1u),40u,1u) +.model NI VDMOS(Vto=600m kp=15m mtriode=1.15 ksubthres=100m lambda=.01 noiseless) +.model PI VDMOS(Vto=-600m kp=15m mtriode=.9 ksubthres=100m lambda=.01 pchan is=0 noiseless) +.model DANTISAT D(Ron=10k Roff=300Meg vfwd=4.7 epsilon=100m vrev=4.7 revepsilon=100m noiseless) +.model SPOW1 SW(Ron=32Meg Roff=10G vt=.5 vh=-.3 noiseless) +.model SPOW2 SW(level=2 Ron=1k Roff=10G vt=.5 vh=-.2 ilimit=.3069u noiseless) +.model DPOWSD D(Ron=10K Roff=10G vfwd=600m epsilon=500m ilimit=34.4n noiseless) +.model Dshut D(Ron=1k Roff=1G vfwd=600m epsilon=300m ilimit=50n noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.param CL=1f +.model SOFF SW(Ron=1k Roff=200Meg vt=-.5 vh=-.3 noiseless) +.model SOFF2 SW(Ron=1k Roff=600Meg vt=-.5 vh=-.4 noiseless) +.model DOFF D (Ron=1k Roff=10G vfwd=600m epsilon=200m vrev=600m revepsilon=200m noiseless) +.param vs=5 +.ends LTC2063 +* +.subckt LTC6560 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +C6 MID1 0 900f Rpar=1k noiseless +B2 0 MID1 I=1m*(V(ch1_st1_out,17)-1.70086) +R2 ch1_st1_out 5 7.86K +C30 N004 5 440f +C31 11 N004 6p Rser=15 Rpar=29.5 noiseless +G7 0 X1 11 N004 1m +C32 X1 0 12f Rpar=30.3k noiseless +A13 0 N005 PowOK 17 17 17 N004 17 OTA g=28m asym ref=-79.1m isource=1u isink=-4.4m in=1p/(1+freq/300Meg) vlow=0 vhigh=1e308 +G8 0 N005 6 5 1m +C33 N005 0 30f Rpar=1k noiseless +C34 5 17 400f Rser=1.75k Rpar=1Meg noiseless +D4 5 17 Din +C36 6 17 1p Rpar=1.4K noiseless +B12 17 PowOK I= uplim(dnlim(400n*V(11,17)-.71u,0,10n)+dnlim(10n*V(11,17),0,10n),1u,10n) +C50 PowOK 17 1p Rpar=1Meg noiseless +B14 17 6 I=1.057148m*dnlim(uplim(.8*(V(11,17)-.8),.25,100m)+uplim(.235*(V(11,17)-1),.75,10m),0,.1)+uplim(dnlim(30u*V(11,17),0,1u),50u,1u) +C52 1 17 5p +C53 11 17 5p Rpar=3k noiseless +A14 0 N004 0 0 0 0 0 0 OTA in=15p +A2 0 5 0 0 0 0 0 0 OTA in= 4.9p/dnlim((freq/1e6)**.14,.3,.1) +800f*(1+freq/600Meg) +D10 1 17 Dleak1 +B16 11 17 I=uplim((20m*MAX(V(11,17)-1.8,0))**1.5,10m,1m) +D6 11 17 Dleak0 +G14 0 MID1BUF MID1 0 1 +R12 MID1BUF 0 10 noiseless +D8 MID1BUF MID1DECAY DSAT +C44 MID1DECAY 0 1p Rpar=100k noiseless +S1 MID1DECAY N012 0 Sat SSAT2 +C45 GainLoss 0 1p Rpar=1k noiseless +B23 0 GainLoss0 I=1m*uplim(dnlim(250m*(.1*dnlim(V(MID1BUF),V(MID1DECAY),.1)-111m),0,10m),700m,10m) +G1 0 GainLoss GainLoss0 0 1m +I1 N012 0 200m +C51 N012 0 10p Rpar=10 noiseless +B28 0 GainlossM1 I=1u*dnlim(V(GainLoss0,GainLoss),0,100u) +C55 mid_out 0 300f Rpar=1k noiseless +S3 0 GainLoss0 0 MID1 SGLLin +B19 0 Sat I=1m*dnlim(V(MID1)-100m,0,10m) +C4 Sat 0 2.5p Rpar=1k noiseless +I2 0 N011 200m +C43 N011 0 10p Rpar=10 noiseless +S4 N011 MID1DECAY 0 Sat SSAT1 +C42 GainLoss0 0 100f Rpar=1k noiseless +R11 OutPreBuf 17 1Meg noiseless +D9 15 17 DI0 +M3 1 N013 15 15 NOUT temp=27 +C61 1 N013 10f Rpar=20Meg noiseless +C62 N013 17 10f Rpar=20Meg noiseless +S5 1 N013 15 N013 SlimOL +D11 N013 15 DCL +C63 14 17 100f noiseless +R13 15 14 50 +A19 15 OutPreBuf PowOK 17 17 17 N013 17 OTA g=100u iout=1m vlow=0 vhigh=5 +C1 GainlossM1 0 12f Rpar=2Meg Rser=10k noiseless +B3 0 GainlossM0 I=1m*dnlim(V(GainLoss0,GainLoss),0,100u) +C41 GainlossM0 0 100f Rpar=1k noiseless +G15 0 N008 mid_out 0 100m +R7 N008 0 100 noiseless +C54 N008 SlimSensA 1p +R8 SlimSensA 0 100 noiseless +C57 slewfac 0 1p Rpar=1k noiseless +B18 0 slewfac I=3m+2m*tanh((V(mid1)-1)/400m) +B17 0 mid_out I=dnlim(5m*uplim(.1*dnlim(V(MID1BUF),V(MID1DECAY),.1)-dnlim(.95*(.1*dnlim(V(MID1BUF),V(MID1DECAY),.1)-200m),0,20m),200m,30m)*(.5+.5*tanh((400m-V(SlimSensA))/10m)),-100u,10u) +S2 GainlossM1 0 0 mid_out SGLKILL +G16 mid_out 0 GainlossM1 0 2m +C59 17 ch1_st1_out 10f Rpar=2k noiseless +D2 17 N007 DSUB +R9 5 N007 10 noiseless +C39 Inode1 0 10p Rpar=100 noiseless +G13 0 Inode1 5 N007 100m +I6 Inode1 0 10µ +C58 N007 17 10f +B21 5 17 I=dnlim(45m*V(Inode1),0,5u) +C49 12 17 1.5p Rpar=29k noiseless +A20 12 17 0 0 0 _HiZ HiZ 0 SCHMITT vt=1.15 vh=350m trise=10n +G19 17 OutPreBuf PowOK 17 .6µ +B5 17 OutPreBuf I=(.5+.5*tanh((V(_Hiz)-.5)/100m ))*1u*uplim(.5 + 2*V(mid_out) + 2*V(glitch2),2.5,50m) +B7 11 ch1_st1_out I=(.5+.5*tanh((V(11,ch1_st1_out)/10m)))*(468.7u+2.2313m*V(_HiZ)-1m*V(X1))*V(PowOK,17) +D15 GainlossM0 GainlossM1 DGLSPD +C67 15 17 100f Rpar=1Meg noiseless +A25 0 0 hiztran 0 N010 0 glitch_OMUX 0 DFLOP trise=3n tfall=1n +G20 0 glitch2 glitch_OMUX 0 1µ +C68 glitch2 0 1f Rpar=1Meg Rser=500k noiseless +R17 hiztran 0 1K +A28 glitch_OMUX 0 0 0 0 0 N010 0 BUF trise=10n +B1 1 17 I=uplim((10m*MAX(V(11,17)-2.8,0))**1.5,1.5m,500u) +.model Din D(Roff=1G Ron=8k vfwd=1.1 epsilon=700m noiseless) +.model Dleak0 D(ron=1k Roff=100k vfwd=4 epsilon=200m noiseless) +.model Dleak1 D(ron=100 Roff=1Meg vfwd=2.5 epsilon=200m ilimit=500u revilimit=100u noiseless) +.model DSUB D(IS=1e-16 TT=100n noiseless) +.model DSAT D(Ron=100 Roff=1G vfwd=200m epsilon=200m noiseless) +.model SSAT1 SW(level=2 Ron=20, Roff=1Meg, vt=-.5 vh=-.2 ilimit=50m oneway epsilon=100m noiseless) +.model SSAT2 SW(level=2 Ron=100, Roff=1Meg, vt=-.5 vh=-.2 ilimit=5m noiseless) +.model SGLLin SW(Ron=100 Roff=10Meg vt=-225m vh=-30m noiseless) +.model DI0 D(Ron=100 Roff=1Meg vfwd=0 epsilon=300m ilimit=420u noiseless) +.model SlimOL SW(Ron=100k Roff=400Meg vt=0 vh=-100m noiseless) +.model DCL D(Ron=1k Roff=1G vfwd=1.88 epsilon=20m noiseless) +.model DGLSPD D(Ron=100 Roff=10Meg vfwd=20m epsilon=50m noiseless) +.model SGLKILL SW(Ron=1 Roff=2Meg vt=-100m vh=-50m noiseless) +.model NOUT VDMOS(Vto=1 Kp=100m noiseless) +.machine +.state notrans 0 +.state trans 1 +.rule * notrans V(Hiz) > .9 | V(Hiz) < .1 +.rule notrans trans V(Hiz) < .8 & V(Hiz) > .2 +.output (hiztran) state +.endmachine +.ends LTC6560 diff --git a/spice/copy/sub/LTC3025.lib b/spice/copy/sub/LTC3025.lib new file mode 100755 index 0000000..7dfae01 --- /dev/null +++ b/spice/copy/sub/LTC3025.lib @@ -0,0 +1,154 @@ +* Copyright © Linear Technology Corp. 2015. All rights reserved. +* +.subckt LTC3025-1 1 2 3 4 5 6 +A5 6 2 2 2 2 2 N012 2 SCHMITT Vt=0.8 Vh=2m Vhigh=.4 Vlow=0 Rout=1K Tau=1u +C4 6 2 10p Rpar=10Meg +R3 P001 N012 10 +C5 P001 2 120n +M1 3 N009 N006 N006 NPE +C7 5 2 10p Rpar=10Meg +C8 3 2 10p Rpar=10Meg +A3 1 2 2 2 2 N002 2 2 SCHMITT Vt=2.2 Vh=2m Trise=50n +S2 2 N012 N004 2 SDN +A12 5 N012 N003 2 2 2 N010 2 OTA G=50u Rout=10Meg Vhigh=5 Vlow=-1 +R2 4 N006 1m +G2 2 N003 3 2 table(1 8.7m 2 11m 3 12m 4.5 13m 5 14m) +D2 2 N003 ILMT +G1 2 N003 4 N006 10 +C1 4 2 10p Rpar=10Meg +A1 3 2 2 2 2 N005 2 2 SCHMITT Vt=.9 Vh=2m Trise=50n +A2 2 N002 2 N005 2 2 N004 2 OR Trise=50n +C2 N009 2 .5p +C3 1 N009 .5p +S1 N009 1 N010 N009 OPOS +S3 2 N009 N009 N010 OPOSD +C9 N010 2 100p Rser=100K +.model NPE VDMOS(Vto=.25 Kp=50 Rd=.15) +.model SDN SW(Ron=1 Roff=100Meg Vt=0.5 Vh=-0.2) +.model ILMT D(Ron=1m Roff=10K Vrev=10) +.model OPOS SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Vser=1.1 Ilimit=100u level=2) +.model OPOSD SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Ilimit=100u level=2) +.ends LTC3025-1 +* +.subckt LTC3025-2 1 2 3 4 5 6 +A5 6 2 2 2 2 2 N012 2 SCHMITT Vt=0.8 Vh=2m Vhigh=.4 Vlow=0 Rout=1K Tau=1u +C4 6 2 10p Rpar=10Meg +R3 P001 N012 10 +C5 P001 2 120n +M1 3 N009 N006 N006 NPE +C8 3 2 10p Rpar=10Meg +A3 1 2 2 2 2 N002 2 2 SCHMITT Vt=2.2 Vh=2m Trise=50n +S2 2 N012 N004 2 SDN +A12 N013 N012 N003 2 2 2 N010 2 OTA G=50u Rout=10Meg Vhigh=5 Vlow=-1 +R2 4 N006 1m +G2 2 N003 3 2 table(1 8.7m 2 11m 3 12m 4.5 13m 5 14m) +D2 2 N003 ILMT +G1 2 N003 4 N006 10 +C1 4 2 10p Rpar=10Meg +A1 3 2 2 2 2 N005 2 2 SCHMITT Vt=.9 Vh=2m Trise=50n +A2 2 N002 2 N005 2 2 N004 2 OR Trise=50n +R4 5 N013 80K +R5 N013 2 40K +C2 N009 2 .5p +C3 1 N009 .5p +S1 N009 1 N010 N009 OPOS +S3 2 N009 N009 N010 OPOSD +C7 N010 2 100p Rser=100K +.model NPE VDMOS(Vto=.25 Kp=50 Rd=.15) +.model SDN SW(Ron=1 Roff=100Meg Vt=0.5 Vh=-0.2) +.model ILMT D(Ron=1m Roff=10K Vrev=10) +.model OPOS SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Vser=1.1 Ilimit=100u level=2) +.model OPOSD SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Ilimit=100u level=2) +.ends LTC3025-2 +* +.subckt LTC3025-3 1 2 3 4 5 6 +A5 6 2 2 2 2 2 N012 2 SCHMITT Vt=0.8 Vh=2m Vhigh=.4 Vlow=0 Rout=1K Tau=1u +C4 6 2 10p Rpar=10Meg +R3 P001 N012 10 +C5 P001 2 120n +M1 3 N009 N006 N006 NPE +C8 3 2 10p Rpar=10Meg +A3 1 2 2 2 2 N002 2 2 SCHMITT Vt=2.2 Vh=2m Trise=50n +S2 2 N012 N004 2 SDN +A12 N013 N012 N003 2 2 2 N010 2 OTA G=50u Rout=10Meg Vhigh=5 Vlow=-1 +R2 4 N006 1m +G2 2 N003 3 2 table(1 8.7m 2 11m 3 12m 4.5 13m 5 14m) +D2 2 N003 ILMT +G1 2 N003 4 N006 10 +C1 4 2 10p Rpar=10Meg +A1 3 2 2 2 2 N005 2 2 SCHMITT Vt=.9 Vh=2m Trise=50n +A2 2 N002 2 N005 2 2 N004 2 OR Trise=50n +R4 5 N013 110K +R5 N013 2 40K +C2 N009 2 .5p +C3 1 N009 .5p +S1 N009 1 N010 N009 OPOS +S3 2 N009 N009 N010 OPOSD +C7 N010 2 100p Rser=100K +.model NPE VDMOS(Vto=.25 Kp=50 Rd=.15) +.model SDN SW(Ron=1 Roff=100Meg Vt=0.5 Vh=-0.2) +.model ILMT D(Ron=1m Roff=10K Vrev=10) +.model OPOS SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Vser=1.1 Ilimit=100u level=2) +.model OPOSD SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Ilimit=100u level=2) +.ends LTC3025-3 +* +.subckt LTC3025-4 1 2 3 4 5 6 +A5 6 2 2 2 2 2 N012 2 SCHMITT Vt=0.8 Vh=2m Vhigh=.4 Vlow=0 Rout=1K Tau=1u +C4 6 2 10p Rpar=10Meg +R3 P001 N012 10 +C5 P001 2 120n +M1 3 N009 N006 N006 NPE +C8 3 2 10p Rpar=10Meg +A3 1 2 2 2 2 N002 2 2 SCHMITT Vt=2.2 Vh=2m Trise=50n +S2 2 N012 N004 2 SDN +A12 N013 N012 N003 2 2 2 N010 2 OTA G=50u Rout=10Meg Vhigh=5 Vlow=-1 +R2 4 N006 1m +G2 2 N003 3 2 table(1 8.7m 2 11m 3 12m 4.5 13m 5 14m) +D2 2 N003 ILMT +G1 2 N003 4 N006 10 +C1 4 2 10p Rpar=10Meg +A1 3 2 2 2 2 N005 2 2 SCHMITT Vt=.9 Vh=2m Trise=50n +A2 2 N002 2 N005 2 2 N004 2 OR Trise=50n +R4 5 N013 140K +R5 N013 2 40K +C2 N009 2 .5p +C3 1 N009 .5p +S1 N009 1 N010 N009 OPOS +S3 2 N009 N009 N010 OPOSD +C7 N010 2 100p Rser=100K +.model NPE VDMOS(Vto=.25 Kp=50 Rd=.15) +.model SDN SW(Ron=1 Roff=100Meg Vt=0.5 Vh=-0.2) +.model ILMT D(Ron=1m Roff=10K Vrev=10) +.model OPOS SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Vser=1.1 Ilimit=100u level=2) +.model OPOSD SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Ilimit=100u level=2) +.ends LTC3025-4 +* +.subckt LTC3025 1 2 3 4 5 6 +A5 6 2 2 2 2 2 N012 2 SCHMITT Vt=0.8 Vh=2m Vhigh=.4 Vlow=0 Rout=1K Tau=1u +C4 6 2 10p Rpar=10Meg +R3 P001 N012 10 +C5 P001 2 120n +M1 3 N009 N006 N006 PE +C7 5 2 10p Rpar=10Meg +C8 3 2 10p Rpar=10Meg +A3 1 2 2 2 2 N002 2 2 SCHMITT Vt=2.2 Vh=2m Trise=50n +S2 2 N012 N004 2 SW +A12 5 N012 N003 2 2 2 N010 2 OTA G=50u Rout=10Meg Vhigh=5 Vlow=-1 +R2 4 N006 1m +G2 2 N003 3 2 table(1 6.2m 3.5 8.4m 5 13.2m) +D2 2 N003 ILMT +G1 2 N003 4 N006 10 +C1 4 2 10p Rpar=10Meg +A1 3 2 2 2 2 N005 2 2 SCHMITT Vt=.9 Vh=2m Trise=50n +A2 2 N002 2 N005 2 2 N004 2 OR Trise=50n +C2 N009 2 .5p +C3 1 N009 .5p +S1 N009 1 N010 N009 OPOS +S3 2 N009 N009 N010 OPOSD +C9 N010 2 100p Rser=100K +.model PE VDMOS(Vto=.25 Kp=50 Rd=.15) +.model SW SW(Ron=1 Roff=100Meg Vt=0.5 Vh=-0.2) +.model ILMT D(Ron=1m Roff=10K Vrev=10) +.model OPOS SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Vser=1.051 Ilimit=100u level=2) +.model OPOSD SW(Ron=10 Roff=100Meg Vt=0 Vh=-.1 Ilimit=100u level=2) +.ends LTC3025 diff --git a/spice/copy/sub/LTC3026.lib b/spice/copy/sub/LTC3026.lib new file mode 100755 index 0000000..438b0e5 --- /dev/null +++ b/spice/copy/sub/LTC3026.lib @@ -0,0 +1,76 @@ +* Copyright © Linear Technology Corp. 2011. All rights reserved. +* +.subckt LTC3026-1 1 2 3 4 5 6 7 8 9 +A5 6 3 3 3 3 3 N011 3 SCHMITT Vt=0.8 Vh=2m +C4 6 3 1p Rpar=50Meg +M1 1 N009 N006 N006 PE temp=27 +C7 8 3 1p Rpar=.1G +C8 1 3 10p Rpar=10Meg +S3 3 7 N015 3 PGD +A7 8 3 3 3 3 N015 3 3 SCHMITT Vt=.368 Vh=4m Trise=50n +C1 7 3 2p Rpar=1G +S5 3 9 N013 3 OSD +A9 8 3 3 3 3 3 N013 3 SCHMITT Vt=0.4 Vh=2m Trise=50n +A12 8 N004 N003 3 3 3 N009 3 OTA G=50u Rout=10Meg Vhigh=5.5 Vlow=-1 +R2 9 N006 1m +G2 3 N003 1 3 table(1 3.2m 2.2 3.4m) +D2 3 N003 ILMT +G1 3 N003 9 N006 1 +C2 3 N003 1p +R1 4 3 1m +A1 1 3 3 3 3 3 N005 3 SCHMITT Vt=1.14 Vh=2m +A2 N001 N011 3 N005 3 3 N004 3 AND Vhigh=.4 Trise=.2m Tfall=1u ref=.5 +D1 1 3 INId m=.6 +G3 1 3 N004 3 237µ +A3 5 3 3 3 3 3 N001 3 SCHMITT Vt=4.24 Vh=10m +D3 5 3 INId +G4 5 3 N004 3 437µ +C5 5 3 1p Rpar=.1G +.model INId D(Ron=1K Roff=.1G Vfwd=0.7 Ilimit=1u) +.model PE VDMOS(Vto=0 Kp=50 Rd=67m) +.model PGD SW(Ron=50 Roff=100Meg Vt=0.5 Vh=-0.1) +.model OSD SW(Ron=150 Roff=10G Vt=.5 Vh=-.1 Ilimit=12m Vser=.75) +.model ILMT D(Ron=1m Roff=10K Vrev=10) +.ends LTC3026-1 +* +.subckt LTC3026 1 2 3 4 5 6 7 8 9 +A5 6 3 3 3 3 3 N021 3 SCHMITT Vt=0.8 Vh=2m Vhigh=.4 Vlow=0 Rout=1K +C4 6 3 100p Rpar=10Meg +C5 N021 3 50n Rser=10 +M1 1 N019 N016 N016 PE +C7 8 3 100p Rpar=10Meg +C8 1 3 100p Rpar=10Meg +D1 4 5 STA +S1 3 4 N007 3 Q +A3 N012 3 3 3 3 N014 3 3 SCHMITT Vt=.336 Vh=2m Trise=50n +R4 5 N012 18.4K +S3 3 7 P001 3 SW +A7 8 3 3 3 3 P001 3 3 SCHMITT Vt=.368 Vh=4m Trise=50n +S2 3 N021 N014 3 SW +A6 N012 3 3 3 3 N010 3 3 SCHMITT Vt=.4 Vh=2m Trise=50n +A8 N005 N009 3 3 3 N008 N004 3 SRFLOP Trise=50n +S4 5 4 N013 3 Q +A1 N006 3 3 3 3 N009 N005 3 SCHMITT Vt=81m Vh=71m Trise=50n +A2 N003 N008 3 N010 N011 3 N007 3 AND Trise=50n +A4 N003 N004 3 N010 N011 3 N013 3 AND Trise=50n +R1 N012 3 1.6K +C1 7 3 100p Rpar=10Meg +S5 3 9 P002 3 OSD +A9 8 3 3 3 3 3 P002 3 SCHMITT Vt=0.4 Vh=2m Trise=50n +A10 1 3 3 3 3 3 N011 3 SCHMITT Vt=1.14 Vh=2m +A11 6 3 3 3 3 3 N003 3 SCHMITT Vt=.8 Vh=2m +A12 8 N021 N015 3 3 3 N019 3 OTA G=50u Rout=10Meg Vhigh=5 Vlow=-1 +R2 9 N016 1m +G2 3 N015 1 3 table(1 3.2m 2.2 3.4m) +D2 3 N015 ILMT +G1 3 N015 9 N016 1 +B2 3 N006 I=1m*(I(S1)+I(S4)+I(D1)) Rpar=1K +C2 3 N015 1p +.model STA D(Ron=1 Roff=10Meg Vfwd=0.7) +.model PE VDMOS(Vto=0 Kp=50 Rd=67m) +.model Q SW(Ron=1 Roff=10Meg Vt=0.5 Vh=-.2) +.model SW SW(Ron=1 Roff=100Meg Vt=0.5 Vh=-0.2) +.model OSD SW(Ron=1K Roff=100Meg Vt=0.5 Vh=-0.2) +.model ILMT D(Ron=1m Roff=10K Vrev=10) +.timedomain +.ends LTC3026 diff --git a/spice/copy/sub/LTC3035.sub b/spice/copy/sub/LTC3035.sub new file mode 100755 index 0000000..f91b8d4 Binary files /dev/null and b/spice/copy/sub/LTC3035.sub differ diff --git a/spice/copy/sub/LTC3100.sub b/spice/copy/sub/LTC3100.sub new file mode 100755 index 0000000..87501ab Binary files /dev/null and b/spice/copy/sub/LTC3100.sub differ diff --git a/spice/copy/sub/LTC3101.sub b/spice/copy/sub/LTC3101.sub new file mode 100755 index 0000000..5b2a316 Binary files /dev/null and b/spice/copy/sub/LTC3101.sub differ diff --git a/spice/copy/sub/LTC3103.sub b/spice/copy/sub/LTC3103.sub new file mode 100755 index 0000000..f35ddc9 Binary files /dev/null and b/spice/copy/sub/LTC3103.sub differ diff --git a/spice/copy/sub/LTC3104.sub b/spice/copy/sub/LTC3104.sub new file mode 100755 index 0000000..765be69 Binary files /dev/null and b/spice/copy/sub/LTC3104.sub differ diff --git a/spice/copy/sub/LTC3105.sub b/spice/copy/sub/LTC3105.sub new file mode 100755 index 0000000..95484db Binary files /dev/null and b/spice/copy/sub/LTC3105.sub differ diff --git a/spice/copy/sub/LTC3106.sub b/spice/copy/sub/LTC3106.sub new file mode 100755 index 0000000..d906f5f Binary files /dev/null and b/spice/copy/sub/LTC3106.sub differ diff --git a/spice/copy/sub/LTC3107.sub b/spice/copy/sub/LTC3107.sub new file mode 100755 index 0000000..83806d3 Binary files /dev/null and b/spice/copy/sub/LTC3107.sub differ diff --git a/spice/copy/sub/LTC3108-1.sub b/spice/copy/sub/LTC3108-1.sub new file mode 100755 index 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100755 index 0000000..7897633 Binary files /dev/null and b/spice/copy/sub/LTC3899.sub differ diff --git a/spice/copy/sub/LTC3900.sub b/spice/copy/sub/LTC3900.sub new file mode 100755 index 0000000..0d9b46c Binary files /dev/null and b/spice/copy/sub/LTC3900.sub differ diff --git a/spice/copy/sub/LTC3901.sub b/spice/copy/sub/LTC3901.sub new file mode 100755 index 0000000..901c2c7 Binary files /dev/null and b/spice/copy/sub/LTC3901.sub differ diff --git a/spice/copy/sub/LTC4.lib b/spice/copy/sub/LTC4.lib new file mode 100755 index 0000000..1c0112e --- /dev/null +++ b/spice/copy/sub/LTC4.lib @@ -0,0 +1,2488 @@ +* Copyright © Linear Technology Corp. 04/07/2006. All rights reserved. +* +.subckt LT6411 1 2 3 4 5 6 7 8 9 10 +B1 0 N004 I=10u*dnlim(uplim(V(7),V(3)-.9,.1), V(1)+.9, .1)+1n*V(7) +B2 N004 0 I=10u*dnlim(uplim(V(INM1),V(3)-.89,.1), V(1)+.89, .1)+1n*V(INM1) +C10 N004 0 .1f Rpar=100K noiseless +R2 3 N011 80Meg noiseless +R3 N011 1 80Meg noiseless +C6 3 7 .5p Rpar=1Meg noiseless +C7 7 1 .5p Rpar=1Meg noiseless +G1 0 N008 N011 0 1µ +C8 0 N008 .03f Rpar=1Meg noiseless +G2 0 N011 N010 0 100µ +C14 N011 N015 120f +A2 5 6 0 0 0 N006 0 0 SCHMITT Vt=1.3 Vh=10m tau=200n Vlow=0 Vhigh=1 +M1 3 N007 4 4 N temp=27 +M2 1 N016 4 4 P temp=27 +D1 N007 4 Y +D9 4 N016 Y +A5 N006 0 N008 N008 N008 N008 N007 N008 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A7 N006 0 N008 N008 N008 N016 N008 N008 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C3 3 4 1p +S2 3 1 N006 0 swPow +A3 0 N004 N006 0 0 0 N010 0 OTA g=10m linear Cout=.01f en=7.7n enk=2.5k Vhigh=1e308 rout=1k Vlow=-1e308 +G3 N011 0 N011 3 100m dir=1 vto=-.78 +G4 0 N011 1 N011 100m dir=1 vto=-.78 +R1 4 INM1 370 +R4 INM1 8 370 +R5 3 5 46k +A4 8 7 0 0 0 0 0 0 OTA g=0 in=4p ink=2.3k +D3 N004 0 DSI temp=27 +D4 0 N004 DSI temp=27 +D6 N003 INM1 DSI2 temp=27 +C1 INM1 7 .1p Rser=150 noiseless +I1 3 N009 7m +S1 N003 N009 N006 0 SW2 +G5 N009 3 3 7 10m +C2 3 N009 .1p Rpar=100 noiseless +I2 N014 1 7m +G6 1 N014 7 1 10m +C9 N014 1 .1p Rpar=100 noiseless +D5 INM1 N005 DSI2 temp=27 +S3 N014 N005 N006 0 SW2 +G7 0 N015 1 0 .5m +G8 0 N015 3 0 .5m +C11 N015 0 200p Rpar=1K noiseless +B3 0 N022 I=10u*dnlim(uplim(V(10),V(3)-.9,.1), V(1)+.9, .1)+1n*V(10) +B4 N022 0 I=10u*dnlim(uplim(V(INM2),V(3)-.89,.1), V(1)+.89, .1)+1n*V(INM2) +C5 N022 0 .1f Rpar=100K noiseless +R10 3 N028 80Meg noiseless +R11 N028 1 80Meg noiseless +G9 0 N025 N028 0 1µ +C12 0 N025 .03f Rpar=1Meg noiseless +G10 0 N028 N027 0 100µ +C13 N028 N032 120f +M3 3 N024 2 2 N temp=27 +M4 1 N033 2 2 P temp=27 +D8 N024 2 Y +D10 2 N033 Y +A6 N006 0 N025 N025 N025 N025 N024 N025 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A8 N006 0 N025 N025 N025 N033 N025 N025 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +A9 0 N022 N006 0 0 0 N027 0 OTA g=10m linear Cout=.01f en=7.7n enk=2.5k Vhigh=1e308 rout=1k Vlow=-1e308 +G11 N028 0 N028 3 100m dir=1 vto=-.78 +G12 0 N028 1 N028 100m dir=1 vto=-.78 +R12 2 INM2 370 +R13 INM2 9 370 +A10 9 10 0 0 0 0 0 0 OTA g=0 in=4p ink=2.3k +D11 N022 0 DSI temp=27 +D12 0 N022 DSI temp=27 +D13 N021 INM2 DSI2 temp=27 +C17 INM2 10 .1p Rser=150 noiseless +I3 3 N026 7m +S5 N021 N026 N006 0 SW2 +G13 N026 3 3 10 10m +C18 3 N026 .1p Rpar=100 noiseless +I4 N031 1 7m +G14 1 N031 10 1 10m +C19 N031 1 .1p Rpar=100 noiseless +D14 INM2 N023 DSI2 temp=27 +S6 N031 N023 N006 0 SW2 +G15 0 N032 1 0 .5m +G16 0 N032 3 0 .5m +C20 N032 0 200p Rpar=1K noiseless +C4 4 1 1p +C15 3 2 1p +C16 2 1 1p +S4 7 3 N006 0 SWB +S7 10 3 N006 0 SWB +.model Y D(Ron=100k Roff=1G Vfwd=1.5 epsilon=.2 noiseless) +.model N VDMOS(Vto=-150m Kp=50m) +.model P VDMOS(Vto=150m Kp=50m pchan) +.model swPow SW(level=2 Ron=100 Roff=1G vt=.5 vh=-50m ilimit=6.73m noiseless) +.model SWB SW(Ron=10k Roff=1g vt=.5 vh=-.3 ilimit=17u noiseless) +.model DSI D(Is=1e-15 TT=100p noiseless) +.model DGC D(Ron=10k Roff=1Meg Vfwd=3.2 Vrev=3.2 epsilon=100m revepsilon=100m noiseless) +.model DSI2 D(Is=1e-20 TT=300n cjo=1f noiseless) +.model SW2 SW(level=2 Ron=1 Roff=1G vt=.5 vh=-.3 ilimit=1m noiseless) +.ends LT6411 +* +.subckt LT6553 1 2 3 4 5 6 7 8 9 10 11 12 +B1 0 N004 I=10u*dnlim(uplim(V(3),V(10)-.9,.1), V(8)+.9, .1)+1n*V(3) +B2 N004 0 I=10u*dnlim(uplim(V(INMR),V(10)-.89,.1), V(8)+.89, .1)+1n*V(INMR) +C10 N004 0 .1f Rpar=100K noiseless +R2 10 N011 80Meg noiseless +R3 N011 8 80Meg noiseless +C6 10 3 .5p Rpar=10Meg noiseless +C7 3 8 .5p Rpar=10Meg noiseless +G1 0 N008 N011 0 1µ +C8 0 N008 .14f Rpar=1Meg noiseless +G2 0 N011 N010 0 100µ +C14 N011 N015 120f +A2 1 2 0 0 0 N006 0 0 SCHMITT Vt=1.5 Vh=10m trise=50n tfall=300n Vlow=0 Vhigh=1 +M1 10 N007 12 12 N temp=27 +M2 8 N016 12 12 P temp=27 +D1 N007 12 YU +D9 12 N016 YD +A5 N006 0 N008 N008 N008 N008 N007 N008 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A7 N006 0 N008 N008 N008 N016 N008 N008 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C3 10 12 1p +S2 10 8 N006 0 swPow +A3 0 N004 N006 0 0 0 N010 0 OTA g=10m linear Cout=.01f en=7.7n enk=2.5k Vhigh=4 rout=1k Vlow=-4 +G3 N011 0 N011 10 100m dir=1 vto=-.72 +G4 0 N011 8 N011 100m dir=1 vto=-.78 +R1 12 INMR 370 +R4 INMR 4 370 +R5 10 1 49k +A4 4 3 0 0 0 0 0 0 OTA g=0 in=4p ink=2.3k +D3 N004 0 DSI temp=27 +D4 0 N004 DSI temp=27 +D6 N003 INMR DSI2 temp=27 +C1 INMR 3 .1p Rser=150 noiseless +I1 10 N009 7m +S1 N003 N009 N006 0 SW2 +G5 N009 10 10 3 10m +C2 10 N009 .1p Rpar=120 noiseless +I2 N014 8 7m +G6 8 N014 3 8 10m +C9 N014 8 .1p Rpar=120 noiseless +D5 INMR N005 DSI2 temp=27 +S3 N014 N005 N006 0 SW2 +G7 0 N015 8 0 .5m +G8 0 N015 10 0 .5m +C11 N015 0 200p Rpar=1K noiseless +C4 12 8 1p +S4 3 10 N006 0 SWB +R6 2 8 1Meg +B3 0 N021 I=10u*dnlim(uplim(V(5),V(10)-.9,.1), V(8)+.9, .1)+1n*V(5) +B4 N021 0 I=10u*dnlim(uplim(V(INMG),V(10)-.89,.1), V(8)+.89, .1)+1n*V(INMG) +C5 N021 0 .1f Rpar=100K noiseless +R7 10 N027 80Meg noiseless +R8 N027 8 80Meg noiseless +C12 10 5 .5p Rpar=10Meg noiseless +C13 5 8 .5p Rpar=10Meg noiseless +G9 0 N024 N027 0 1µ +C15 0 N024 .14f Rpar=1Meg noiseless +G10 0 N027 N026 0 100µ +C16 N027 N031 120f +M3 10 N023 11 11 N temp=27 +M4 8 N032 11 11 P temp=27 +D2 N023 11 YU +D7 11 N032 YD +A6 N006 0 N024 N024 N024 N024 N023 N024 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A8 N006 0 N024 N024 N024 N032 N024 N024 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C17 10 11 1p +A9 0 N021 N006 0 0 0 N026 0 OTA g=10m linear Cout=.01f en=7.7n enk=2.5k Vhigh=4 rout=1k Vlow=-4 +G11 N027 0 N027 10 100m dir=1 vto=-.72 +G12 0 N027 8 N027 100m dir=1 vto=-.78 +R10 11 INMG 370 +R11 INMG 4 370 +A10 4 5 0 0 0 0 0 0 OTA g=0 in=4p ink=2.3k +D8 N021 0 DSI temp=27 +D10 0 N021 DSI temp=27 +D11 N020 INMG DSI2 temp=27 +C18 INMG 5 .1p Rser=150 noiseless +I3 10 N025 7m +S6 N020 N025 N006 0 SW2 +G13 N025 10 10 5 10m +C19 10 N025 .1p Rpar=120 noiseless +I4 N030 8 7m +G14 8 N030 5 8 10m +C20 N030 8 .1p Rpar=120 noiseless +D12 INMG N022 DSI2 temp=27 +S7 N030 N022 N006 0 SW2 +G15 0 N031 8 0 .5m +G16 0 N031 10 0 .5m +C21 N031 0 200p Rpar=1K noiseless +C22 11 8 1p +S8 5 10 N006 0 SWB +B5 0 N035 I=10u*dnlim(uplim(V(7),V(10)-.9,.1), V(8)+.9, .1)+1n*V(7) +B6 N035 0 I=10u*dnlim(uplim(V(INMB),V(10)-.89,.1), V(8)+.89, .1)+1n*V(INMB) +C23 N035 0 .1f Rpar=100K noiseless +R12 10 N041 80Meg noiseless +R14 N041 8 80Meg noiseless +C24 10 7 .5p Rpar=1Meg noiseless +C25 7 8 .5p Rpar=1Meg noiseless +G17 0 N038 N041 0 1µ +C26 0 N038 .14f Rpar=1Meg noiseless +G18 0 N041 N040 0 100µ +C27 N041 N045 120f +M5 10 N037 9 9 N temp=27 +M6 8 N046 9 9 P temp=27 +D13 N037 9 YU +D14 9 N046 YD +A1 N006 0 N038 N038 N038 N038 N037 N038 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A11 N006 0 N038 N038 N038 N046 N038 N038 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C28 10 9 1p +A12 0 N035 N006 0 0 0 N040 0 OTA g=10m linear Cout=.01f en=7.7n enk=2.5k Vhigh=4 rout=1k Vlow=-4 +G19 N041 0 N041 10 100m dir=1 vto=-.72 +G20 0 N041 8 N041 100m dir=1 vto=-.78 +R15 9 INMB 370 +R16 INMB 6 370 +A13 6 7 0 0 0 0 0 0 OTA g=0 in=4p ink=2.3k +D15 N035 0 DSI temp=27 +D16 0 N035 DSI temp=27 +D17 N034 INMB DSI2 temp=27 +C29 INMB 7 .1p Rser=150 noiseless +I5 10 N039 7m +S10 N034 N039 N006 0 SW2 +G21 N039 10 10 7 10m +C30 10 N039 .1p Rpar=120 noiseless +I6 N044 8 7m +G22 8 N044 7 8 10m +C31 N044 8 .1p Rpar=120 noiseless +D18 INMB N036 DSI2 temp=27 +S11 N044 N036 N006 0 SW2 +G23 0 N045 8 0 .5m +G24 0 N045 10 0 .5m +C32 N045 0 200p Rpar=1K noiseless +C33 9 8 1p +S12 7 10 N006 0 SWB +.model YU D(Ron=100k Roff=1G Vfwd=1.59 epsilon=.2 noiseless) +.model YD D(Ron=100k Roff=1G Vfwd=1.6 epsilon=.3 noiseless) +.model N VDMOS(Vto=-150m Kp=50m) +.model P VDMOS(Vto=150m Kp=50m pchan) +.model swPow SW(level=2 Ron=100 Roff=1G vt=.5 vh=-50m ilimit=22.23m noiseless) +.model SWB SW(Ron=10k Roff=1g vt=.5 vh=-.3 ilimit=17u noiseless) +.model DSI D(Is=1e-15 TT=1p noiseless) +.model DGC D(Ron=10k Roff=1Meg Vfwd=3.2 Vrev=3.2 epsilon=100m revepsilon=100m noiseless) +.model DSI2 D(Is=1e-20 TT=300n cjo=1f noiseless) +.model SW2 SW(level=2 Ron=1 Roff=1G vt=.5 vh=-.3 ilimit=1m noiseless) +.ends LT6553 +* +* Pinout (Same as IC): EN/ -IN +IN V- REF RG OUT V+ +.SUBCKT LTC2053 1 2 3 4 5 6 7 8 +.timedomain +RG1 24 0 1591550 +CG1 24 0 1.4E-6 +GG3 0 25 24 0 6.2832 +RG3 25 0 0.159155 +CG3 25 0 5E-6 +DIN1 2 8 DIN +DIN2 3 8 DIN +DIN3 4 3 DIN +DIN4 4 2 DIN +RSHDN 8 1 1E7 +GG1 0 24 VALUE={4E-3*TANH(V(23))} +MOUT1 8 26 27 27 NOUT +MOUT2 4 26 27 27 POUT +DOUT1 26 27 DOUTP +DOUT2 27 26 DOUTN +GOUT 0 26 VALUE={1m*TANH(V(25))} +ROUT1 8 26 2E5 +ROUT2 26 4 2E5 +RA 23 0 5 +DVL1 29 24 DVLIM +DVL2 29 0 DVLIM +SIN1 3 11 71 76 SIN +SIN2 2 12 71 76 SIN +SIN3 11 21 72 76 SIN +SIN4 12 5 72 76 SIN +CIN1 11 12 1E-9 +CIN2 21 5 1E-9 +VSW1 71 0 PULSE(0 1 0 5u 5u 150u 330u) +VSW2 72 0 PULSE(0 1 165u 5u 5u 145u 330u) +EICML 75 0 VALUE={V(8)-1.6} +GGAIN 0 23 VALUE={(V(21,6)+1.58E-6*V(8,4))} +GPWR 8 4 VALUE={8E-6+7.5E-4*(0.5+0.5*TANH(10*(1.5-V(1,4))))} +DICML 21 75 DIN +SSD1 7 27 1 4 SSD +RINZ 6 4 5E9 +* GB changed Rinz from 5e6 to 5e9 July 27, 2011 +GVOS 0 23 28 0 -1E-5 +RVOS 28 0 1 TC1=0.005 +IVOS 0 28 1 +CPAR1 12 4 1E-13 +ESHD 76 0 VALUE={0.5+0.5*TANH(3*(V(1,4)-1.75))} +.MODEL SIN VSWITCH(RON=1k ROFF=1E11 VON=0.8 VOFF=0.2) +.MODEL SSD VSWITCH(RON=10 ROFF=1E11 VON=1.25 VOFF=1.75) +* GB changed Roff from 1e9 to 1e11 July 27, 2011 +.MODEL NOUT NMOS(KP=1 VTO=10M) +.MODEL POUT PMOS(KP=1 VTO=-10M) +.MODEL DOUTP D(KF=0 RS=0 IS=1.6036E-8) +.MODEL DOUTN D(KF=0 RS=0 IS=1.6036E-8) +.MODEL DIN D(IS=1E-14 KF=0 RS=0) +.MODEL DVLIM D(BV=5 IS=1E-18 KF=0 RS=0 XTI=0) +.ENDS LTC2053 +* +.subckt LTC6241 1 2 3 4 5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-178.3p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +M1 5 N011 4 4 NI temp=27 +C2 3 5 1p Rpar=100Meg noiseless +D5 N011 4 DLIMN +M2 5 N007 3 3 PI temp=27 +D8 3 N007 DLIMP +C3 3 N007 2p Rser=15Meg noiseless +A3 N008 N009 4 4 4 4 N007 4 OTA g=20n ref=-420m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=100Meg noiseless +C12 N011 4 2p Rser=15Meg noiseless +C16 N009 5 180f Rser=200k noiseless +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=23u iout=2.9u Vhigh=1e308 Vlow=-1e308 +G1 4 N011 N009 N008 20n +D9 N009 N008 DLIM +C7 3 1 1.75p Rser=100 Rpar=5T noiseless +C13 3 4 1000p Rpar=5k noiseless +C1 N005 0 350f Rpar=1Meg noiseless +G2 0 N008 4 0 .5m +G4 0 N008 3 0 .5m +C18 N008 0 200p Rpar=1K noiseless +G3 0 N006 N005 0 1m +L1 N006 0 114.5µ Cpar=149f Rser=1.08k Rpar=13.5k noiseless +D6 2 3 DESD temp=27 +D7 4 2 DESD temp=27 +D10 1 3 DESD temp=27 +D11 4 1 DESD temp=27 +D1 3 2 DBIAS +C8 N007 5 1f Rser=5k noiseless +C9 5 N011 1f Rser=5k noiseless +D2 3 4 DP +D3 3 1 DBIAS +A2 0 N004 0 0 0 0 N005 0 OTA g=1u linear en=6.8n enk=55 Vlow=-.132 Vhigh=.132 +C4 3 2 1.75p Rser=100 Rpar=5T noiseless +C5 1 4 1.75p Rser=100 Rpar=5T noiseless +C6 2 4 1.75p Rser=100 Rpar=5T noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.51f + 3.5e-19*freq**1.1 +.model NI VDMOS(Vto=300m kp=35m lambda=.08) +.model PI VDMOS(Vto=-300m Kp=25m lambda=.08 pchan) +.model DLIM D(Ron=10k Roff=500Meg Vfwd=5 Vrev=5 epsilon=10m revepsilon=10m noiseless) +.model DESD D(Rs=100 Is=1e-15) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.5 Vrev=-280m epsilon=10m revepsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.8 Vrev=-280m epsilon=10m revepsilon=10m noiseless) +.model DBIAS D(Ron=10g Roff=1T epsilon=.3 ilimit=.2p noiseless) +.model DP D(Ron=1k Roff=1g Vfwd=.5 epsilon=.1 ilimit=.545m noiseless) +.ends LTC6241 +* +.subckt LT6220 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.8p ink=38 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-523p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 .1f Rpar=100K noiseless +D4 3 N011 DBIAZ +M1 5 N012 4 4 NI temp=27 +C2 3 5 1p Rpar=1Meg noiseless +M2 5 N005 3 3 PI temp=27 +C3 3 N005 20f Rser=200Meg noiseless +A3 N006 N009 4 4 4 4 N005 4 OTA g=20n ref=-.078 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1Meg noiseless +C12 N012 4 1f Rser=700Meg noiseless +D10 1 N011 DBIA1 +D11 2 N011 DBIA1 +D6 N012 4 DLIMN1 +A4 0 N004 0 0 0 0 N007 0 OTA g=1u linear en=10n enk=38.6 cout=68f Vlow=-1e308 Vhigh=1e308 +C16 N009 5 110f +A5 N008 0 N006 N006 N006 N006 N009 N006 OTA g=52u iout=2.95u Rout=8Meg Vhigh=1e308 Vlow=-1e308 +D12 1 3 DESD +D13 2 3 DESD +G1 4 N012 N009 N006 4n +C5 N011 4 20p Rpar=22.7k noiseless +C7 3 1 1p Rpar=1G noiseless +C13 3 4 1000p +G4 0 N008 N007 0 1m +D14 3 N005 DLIMP1 +L1 N008 0 18.5µ Cpar=38f Rser=1.1k Rpar=11k noiseless +D15 1 2 DIN +D16 N011 1 DBIA2 +D3 N011 2 DBIA2 +D1 4 2 DESD +D2 4 1 DESD +C1 3 2 1p Rpar=1G noiseless +C6 1 4 1p Rpar=1G noiseless +C8 2 4 1p Rpar=1G noiseless +G2 0 N006 3 0 .5m +G3 0 N006 4 0 .5m +C14 N006 0 .2p Rpar=1K +D18 3 N005 DLIMP2 +D19 N012 4 DLIMN2 +D20 N007 0 DLIM +C4 N008 5 50f +.model DBIA1 D(Ron=100k Roff=1g Vfwd=0 ilimit=260n epsilon=.1 noiseless) +.model DBIA2 D(Ron=1Meg Roff=10g Vfwd=-.1 epsilon=.1 ilimit=10n noiseless) +.model DBIAZ D(Ron=100 Roff=100G Vfwd=1 epsilon=10m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model DLIMN1 D(Ron=1Meg Roff=10g Vfwd=1 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model DLIMN2 D(Ron=200Meg Roff=10g Vfwd=.6 epsilon=.6 noiseless) +.model DLIMP1 D(Ron=100k Roff=400Meg Vfwd=1 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DLIMP2 D(Ron=50Meg Roff=10G Vfwd=.7 epsilon=.6 noiseless) +.model PI VDMOS(Vto=-300m kp=80m pchan) +.model NI VDMOS(Vto=300m kp=80m) +.model DLIM D(Ron=1k Roff=1Meg Vfwd=52m epsilon=10m Vrev=52m revepsilon=10m noiseless) +.model DIN D(Ron=1k Roff=100Meg Vfwd=1.5 Vrev=1.5 epsilon=100m revepsilon=100m noiseless) +.ends LT6220 +* +.subckt LT6554 1 2 3 4 5 6 7 8 9 10 +B1 0 N003 I=10u*dnlim(uplim(V(5),V(3)-.1,.1), V(4)+.1, .1)+1n*V(5) +B2 N003 0 I=10u*dnlim(uplim(V(INMR),V(3)-.09,.1), V(4)+.09, .1)+1n*V(INMR) +C10 N003 0 .1f Rpar=100K noiseless +R2 3 N010 80Meg noiseless +R3 N010 4 80Meg noiseless +C6 3 5 .5p Rpar=10Meg noiseless +C7 5 4 .5p Rpar=10Meg noiseless +G1 0 N007 N010 0 1µ +G2 0 N010 N009 0 100µ +C14 N010 N014 330f Rser=810 noiseless +A2 1 2 0 0 0 N005 0 0 SCHMITT Vt=1.5 Vh=10m trise=50n tfall=300n Vlow=0 Vhigh=1 +M1 3 N006 8 8 N temp=27 +M2 4 N015 8 8 P temp=27 +D1 N006 8 YU +D9 8 N015 YD +A5 N005 0 N007 N007 N007 N007 N006 N007 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A7 N005 0 N007 N007 N007 N015 N007 N007 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C3 3 8 .9p +S2 3 4 N005 0 swPow +A3 0 N003 N005 0 0 0 N009 0 OTA g=10m linear Cout=1f en=19.9n enk=1.24k Vhigh=1e308 rout=1k Vlow=-1e308 +G3 N010 0 N010 3 500m dir=1 vto=-.71 +G4 0 N010 4 N010 500m dir=1 vto=-.71 +R1 8 INMR 480 +R5 3 1 49k +A4 INMR 5 0 0 0 0 0 0 OTA g=0 in=3.5p ink=400 +D3 N003 0 DSI temp=27 +D4 0 N003 DSI temp=27 +D6 N002 INMR DSI2 temp=27 +C1 INMR 5 .1p Rser=150 noiseless +I1 3 N008 7m +S1 N002 N008 N005 0 SW2 +G5 N008 3 3 5 10m +C2 3 N008 .1p Rpar=120 noiseless +I2 N013 4 7m +G6 4 N013 5 4 10m +C9 N013 4 .1p Rpar=120 noiseless +D5 INMR N004 DSI2 temp=27 +S3 N013 N004 N005 0 SW2 +G7 0 N014 4 0 .5m +G8 0 N014 3 0 .5m +C11 N014 0 200p Rpar=1K noiseless +C4 8 4 .9p +S4 5 3 N005 0 SWB +R6 2 4 1Meg +C12 8 N007 .25f Rser=400k noiseless +C5 N007 0 .139f Rpar=1Meg Rser=142.8k noiseless +B3 0 N020 I=10u*dnlim(uplim(V(6),V(3)-.1,.1), V(4)+.1, .1)+1n*V(6) +B4 N020 0 I=10u*dnlim(uplim(V(INMG),V(3)-.09,.1), V(4)+.09, .1)+1n*V(INMG) +C13 N020 0 .1f Rpar=100K noiseless +R8 3 N026 80Meg noiseless +R10 N026 4 80Meg noiseless +C15 3 6 .5p Rpar=10Meg noiseless +C16 6 4 .5p Rpar=10Meg noiseless +G9 0 N023 N026 0 1µ +G10 0 N026 N025 0 100µ +C17 N026 N030 330f Rser=810 noiseless +M3 3 N022 9 9 N temp=27 +M4 4 N031 9 9 P temp=27 +D2 N022 9 YU +D7 9 N031 YD +A6 N005 0 N023 N023 N023 N023 N022 N023 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A8 N005 0 N023 N023 N023 N031 N023 N023 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C18 3 9 .9p +A9 0 N020 N005 0 0 0 N025 0 OTA g=10m linear Cout=1f en=19.9n enk=1.24k Vhigh=1e308 rout=1k Vlow=-1e308 +G11 N026 0 N026 3 500m dir=1 vto=-.71 +G12 0 N026 4 N026 500m dir=1 vto=-.71 +R11 9 INMG 480 +A10 INMG 6 0 0 0 0 0 0 OTA g=0 in=3.5p ink=400 +D8 N020 0 DSI temp=27 +D10 0 N020 DSI temp=27 +D11 N019 INMG DSI2 temp=27 +C19 INMG 6 .1p Rser=150 noiseless +I3 3 N024 7m +S6 N019 N024 N005 0 SW2 +G13 N024 3 3 6 10m +C20 3 N024 .1p Rpar=120 noiseless +I4 N029 4 7m +G14 4 N029 6 4 10m +C21 N029 4 .1p Rpar=120 noiseless +D12 INMG N021 DSI2 temp=27 +S7 N029 N021 N005 0 SW2 +G15 0 N030 4 0 .5m +G16 0 N030 3 0 .5m +C22 N030 0 200p Rpar=1K noiseless +C23 9 4 .9p +S8 6 3 N005 0 SWB +C24 9 N023 .25f Rser=400k noiseless +B5 0 N033 I=10u*dnlim(uplim(V(7),V(3)-.1,.1), V(4)+.1, .1)+1n*V(7) +B6 N033 0 I=10u*dnlim(uplim(V(INMB),V(3)-.09,.1), V(4)+.09, .1)+1n*V(INMB) +C8 N033 0 .1f Rpar=100K noiseless +R12 3 N039 80Meg noiseless +R13 N039 4 80Meg noiseless +C26 3 7 .5p Rpar=10Meg noiseless +C27 7 4 .5p Rpar=10Meg noiseless +G17 0 N036 N039 0 1µ +G18 0 N039 N038 0 100µ +C28 N039 N043 330f Rser=810 noiseless +M5 3 N035 10 10 N temp=27 +M6 4 N044 10 10 P temp=27 +D13 N035 10 YU +D14 10 N044 YD +A1 N005 0 N036 N036 N036 N036 N035 N036 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A11 N005 0 N036 N036 N036 N044 N036 N036 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C29 3 10 .9p +A12 0 N033 N005 0 0 0 N038 0 OTA g=10m linear Cout=1f en=19.9n enk=1.24k Vhigh=1e308 rout=1k Vlow=-1e308 +G19 N039 0 N039 3 500m dir=1 vto=-.71 +G20 0 N039 4 N039 500m dir=1 vto=-.71 +R14 10 INMB 480 +A13 INMB 7 0 0 0 0 0 0 OTA g=0 in=3.5p ink=400 +D15 N033 0 DSI temp=27 +D16 0 N033 DSI temp=27 +D17 N032 INMB DSI2 temp=27 +C30 INMB 7 .1p Rser=150 noiseless +I5 3 N037 7m +S5 N032 N037 N005 0 SW2 +G21 N037 3 3 7 10m +C31 3 N037 .1p Rpar=120 noiseless +I6 N042 4 7m +G22 4 N042 7 4 10m +C32 N042 4 .1p Rpar=120 noiseless +D18 INMB N034 DSI2 temp=27 +S9 N042 N034 N005 0 SW2 +G23 0 N043 4 0 .5m +G24 0 N043 3 0 .5m +C33 N043 0 200p Rpar=1K noiseless +C34 10 4 .9p +S10 7 3 N005 0 SWB +C35 10 N036 .25f Rser=400k noiseless +C25 N023 0 .139f Rpar=1Meg Rser=142.8k noiseless +C36 N036 0 .139f Rpar=1Meg Rser=142.8k noiseless +.model YU D(Ron=100k Roff=1G Vfwd=1.56 epsilon=.2 noiseless) +.model YD D(Ron=100k Roff=1G Vfwd=1.6 epsilon=.3 noiseless) +.model N VDMOS(Vto=-150m Kp=50m) +.model P VDMOS(Vto=150m Kp=50m pchan) +.model swPow SW(level=2 Ron=100 Roff=1G vt=.5 vh=-50m ilimit=23.49m noiseless) +.model SWB SW(Ron=10k Roff=1g vt=.5 vh=-.3 ilimit=17u noiseless) +.model DSI D(Is=1e-19 TT=1p noiseless) +.model DGC D(Ron=10k Roff=1Meg Vfwd=3.2 Vrev=3.2 epsilon=100m revepsilon=100m noiseless) +.model DSI2 D(Is=1e-20 TT=100n cjo=1f noiseless) +.model SW2 SW(level=2 Ron=1 Roff=1G vt=.5 vh=-.3 ilimit=1m noiseless) +.ends LT6554 +* +.subckt LTC1992 1 2 3 4 5 6 7 8 +A1 1 8 0 0 0 0 0 0 OTA g=0 in=1f +C5 3 1 1.5p +C6 N008 0 50f Rpar=100K noiseless +G1 0 N011 N015 0 1m +M1 3 N007 4 4 N temp=27 +M2 6 N007 4 4 P temp=27 +C7 N007 0 2f +G4 0 N014 N006 0 200n +C8 N014 0 2f +M3 3 N014 5 5 N temp=27 +M4 6 N014 5 5 P temp=27 +G6 N014 0 N011 0 200n +D4 N014 5 Y +D5 5 N014 Y +D8 4 N007 Y +D9 N007 4 Y +G5 0 N007 N011 0 200n +G3 0 N007 N006 0 200n +R9 4 VCM 30K noiseless +R11 VCM 5 30K noiseless +B1 0 N008 I=10u*dnlim(uplim(V(8),V(3)-1.2,.1), V(6)-.2, .1)+1n*V(8) +B2 N008 0 I=10u*dnlim(uplim(V(1),V(3)-1.19,.1), V(6)-.21, .1)+1n*V(1) +C19 3 4 1p +C12 4 6 1p +C16 3 5 1p +C17 5 6 1p +D13 8 6 DBIAS +D14 1 6 DBIAS +A4 0 N005 0 0 0 0 N006 0 OTA G=18m Iout=900u en=30.9n enk=285 Cout=3n Rout=2.5Meg Vlow=-1e308 Vhigh=1e308 +A2 0 N009 0 0 0 0 N015 0 OTA g=10.1u cout=700f iout=10u Vlow=-1e308 Vhigh=1e308 +R2 3 7 200K +R4 7 6 200K +C10 N015 N019 60p noiseless +A3 0 N008 0 0 0 0 N009 0 OTA g=1u cout=40f en=30.9n enk=285 linear Rout=1Meg Vlow=-1e308 Vhigh=1e308 +C13 N011 0 1p Rpar=1k noiseless +R12 N015 0 500Meg noiseless +S1 N009 0 N018 0 swSlew +S2 0 N009 0 N018 swSlew +C18 N015 N018 10f +A5 N012 N019 N019 N019 N019 N019 N012 N019 OTA g=60u iout=1u Vlow=-1e308 Vhigh=1e308 +R14 N012 N019 500K noiseless +C14 N018 0 10f Rpar=780k noiseless +R15 2 6 500Meg noiseless +B3 0 N005 I=10u*dnlim(uplim(V(2),V(3)-1.2,.1), V(6)+.4, .1)+1n*V(2) +C1 N005 0 500f Rpar=100K noiseless +B4 N005 0 I=10u*dnlim(uplim(V(VCM),V(3)-1.19,.1), V(6)+.39, .1)+1n*V(VCM) +D1 3 6 DPOW +G7 0 N012 4 5 1m +C9 N012 0 100f Rpar=500 noiseless +R7 3 N007 10Meg noiseless +R10 N007 6 10Meg noiseless +R13 N014 6 10Meg noiseless +R6 3 N014 10Meg noiseless +D3 6 8 DCLP +D2 6 1 DCLP +D6 1 3 DCLP +D7 8 3 DCLP +C2 1 6 1.5p +C3 3 8 1.5p +C4 8 6 1.5p +G2 N015 0 N007 3 50m dir=1 vto=.19 +G8 0 N015 6 N007 50m dir=1 vto=.10 +G10 0 N015 N014 3 50m dir=1 vto=.19 +G9 N015 0 6 N014 50m dir=1 vto=.10 +G11 N006 0 N006 HI 50m dir=1 vto=3 +G12 0 N006 LO N006 50m dir=1 vto=3 +G13 0 HI 3 0 500µ +R16 HI 0 1K +G14 HI 0 6 0 500µ +G15 0 LO 6 0 500µ +R17 LO 0 1K +G17 LO 0 3 0 500µ +.model N VDMOS(Vto=-70m Kp=138m) +.model P VDMOS(Vto=70m Kp=138m pchan) +.model Y D(Ron=10K Roff=1T Vfwd=.6 epsilon=10m noiseless) +.model DBIAS D(Ron=5K ilimit=2p epsilon=.5 noiseless) +.model DPOW D(Ron=1k ilimit=60.8u epsilon=.1 noiseless) +.model DCLP D(Is=1e-18 Rs=500 noiseless) +.model swSlew SW(Ron=10k Roff=1G vt= 5m vh=-2m) +.ends LTC1992 +* +.subckt LTC1992-1 1 2 3 4 5 6 7 8 +A1 IN-A IN+A 0 0 0 0 0 0 OTA g=0 in=1f +C5 3 IN-A 1.5p +C6 N006 0 50f Rpar=100K noiseless +G1 0 N010 N013 0 1m +M1 3 N005 4 4 N temp=27 +M2 6 N005 4 4 P temp=27 +C7 N005 0 2f +G4 0 N012 N004 0 200n +C8 N012 0 2f +M3 3 N012 5 5 N temp=27 +M4 6 N012 5 5 P temp=27 +G6 N012 0 N010 0 200n +D4 N012 5 Y +D5 5 N012 Y +D8 4 N005 Y +D9 N005 4 Y +G5 0 N005 N010 0 200n +G3 0 N005 N004 0 200n +R9 4 VCM 30K noiseless +R11 VCM 5 30K noiseless +B1 0 N006 I=10u*dnlim(uplim(V(IN+A),V(3)-1.2,.1), V(6)-.2, .1)+1n*V(IN+A) +B2 N006 0 I=10u*dnlim(uplim(V(IN-A),V(3)-1.19,.1), V(6)-.21, .1)+1n*V(IN-A) +C19 3 4 1p +C12 4 6 1p +C16 3 5 1p +C17 5 6 1p +D13 IN+A 6 DBIAS +D14 IN-A 6 DBIAS +A2 0 N007 0 0 0 0 N013 0 OTA g=10.1u cout=700f iout=10u Vlow=-1e308 Vhigh=1e308 +R2 3 7 200K +R4 7 6 200K +C10 N013 N017 60p noiseless +A3 0 N006 0 0 0 0 N007 0 OTA g=1u cout=40f en=30.9n enk=285 linear Rout=1Meg Vlow=-1e308 Vhigh=1e308 +C13 N010 0 1p Rpar=1k noiseless +R12 N013 0 500Meg noiseless +S1 N007 0 N016 0 swSlew +S2 0 N007 0 N016 swSlew +C18 N013 N016 10f +A5 N011 N017 N017 N017 N017 N017 N011 N017 OTA g=60u iout=1u Vlow=-1e308 Vhigh=1e308 +R14 N011 N017 500K noiseless +C14 N016 0 10f Rpar=780k noiseless +R15 2 6 500Meg noiseless +B3 0 N003 I=10u*dnlim(uplim(V(2),V(3)-1.2,.1), V(6)+.4, .1)+1n*V(2) +C1 N003 0 500f Rpar=100K noiseless +B4 N003 0 I=10u*dnlim(uplim(V(VCM),V(3)-1.19,.1), V(6)+.39, .1)+1n*V(VCM) +D1 3 6 DPOW +G7 0 N011 4 5 1m +C9 N011 0 100f Rpar=500 noiseless +R7 3 N005 10Meg noiseless +R10 N005 6 10Meg noiseless +R13 N012 6 10Meg noiseless +R6 3 N012 10Meg noiseless +D3 6 8 DCLP +D2 6 1 DCLP +D6 1 3 DCLP +D7 8 3 DCLP +C2 IN-A 6 1.5p +C3 3 IN+A 1.5p +C4 IN+A 6 1.5p +R1 IN-A 1 30K +R3 IN+A 8 30K +R5 4 IN-A 30K +R8 5 IN+A 30K +G2 N013 0 N005 3 50m dir=1 vto=.19 +G8 0 N013 6 N005 50m dir=1 vto=.10 +G9 0 N013 N012 3 50m dir=1 vto=.19 +G10 N013 0 6 N012 50m dir=1 vto=.10 +A4 0 N003 0 0 0 0 N004 0 OTA G=18m Iout=900u en=30.9n enk=285 Cout=3n Rout=2.5Meg Vlow=-1e308 Vhigh=1e308 +G11 N004 0 N004 HI 50m dir=1 vto=3 +G12 0 N004 LO N004 50m dir=1 vto=3 +G13 0 HI 3 0 500µ +R16 HI 0 1K +G14 HI 0 6 0 500µ +G15 0 LO 6 0 500µ +R17 LO 0 1K +G16 LO 0 3 0 500µ +.model N VDMOS(Vto=-70m Kp=138m) +.model P VDMOS(Vto=70m Kp=138m pchan) +.model Y D(Ron=10K Roff=1T Vfwd=.6 epsilon=10m noiseless) +.model DBIAS D(Ron=5K ilimit=2p epsilon=.5 noiseless) +.model DPOW D(Ron=1k ilimit=60.8u epsilon=.1 noiseless) +.model DCLP D(Is=1e-18 Rs=500 noiseless) +.model swSlew SW(Ron=10k Roff=1G vt= 5m vh=-2m) +.ends LTC1992-1 +* +.subckt LTC1992-2 1 2 3 4 5 6 7 8 +A1 IN-A IN+A 0 0 0 0 0 0 OTA g=0 in=1f +C5 3 IN-A 1.5p +C6 N006 0 50f Rpar=100K noiseless +G1 0 N010 N013 0 1m +M1 3 N005 4 4 N temp=27 +M2 6 N005 4 4 P temp=27 +C7 N005 0 2f +G4 0 N012 N004 0 200n +C8 N012 0 2f +M3 3 N012 5 5 N temp=27 +M4 6 N012 5 5 P temp=27 +G6 N012 0 N010 0 200n +D4 N012 5 Y +D5 5 N012 Y +D8 4 N005 Y +D9 N005 4 Y +G5 0 N005 N010 0 200n +G3 0 N005 N004 0 200n +R9 4 VCM 30K noiseless +R11 VCM 5 30K noiseless +B1 0 N006 I=10u*dnlim(uplim(V(IN+A),V(3)-1.2,.1), V(6)-.2, .1)+1n*V(IN+A) +B2 N006 0 I=10u*dnlim(uplim(V(IN-A),V(3)-1.19,.1), V(6)-.21, .1)+1n*V(IN-A) +C19 3 4 1p +C12 4 6 1p +C16 3 5 1p +C17 5 6 1p +D13 IN+A 6 DBIAS +D14 IN-A 6 DBIAS +A2 0 N007 0 0 0 0 N013 0 OTA g=10.1u cout=700f iout=10u Vlow=-1e308 Vhigh=1e308 +R2 3 7 200K +R4 7 6 200K +C10 N013 N017 60p noiseless +A3 0 N006 0 0 0 0 N007 0 OTA g=1u cout=40f en=30.9n enk=285 linear Rout=1Meg Vlow=-1e308 Vhigh=1e308 +C13 N010 0 1p Rpar=1k noiseless +R12 N013 0 500Meg noiseless +S1 N007 0 N016 0 swSlew +S2 0 N007 0 N016 swSlew +C18 N013 N016 10f +A5 N011 N017 N017 N017 N017 N017 N011 N017 OTA g=60u iout=1u Vlow=-1e308 Vhigh=1e308 +R14 N011 N017 500K noiseless +C14 N016 0 10f Rpar=780k noiseless +R15 2 6 500Meg noiseless +B3 0 N003 I=10u*dnlim(uplim(V(2),V(3)-1.2,.1), V(6)+.4, .1)+1n*V(2) +C1 N003 0 500f Rpar=100K noiseless +B4 N003 0 I=10u*dnlim(uplim(V(VCM),V(3)-1.19,.1), V(6)+.39, .1)+1n*V(VCM) +D1 3 6 DPOW +G7 0 N011 4 5 1m +C9 N011 0 100f Rpar=500 noiseless +R7 3 N005 10Meg noiseless +R10 N005 6 10Meg noiseless +R13 N012 6 10Meg noiseless +R6 3 N012 10Meg noiseless +D3 6 8 DCLP +D2 6 1 DCLP +D6 1 3 DCLP +D7 8 3 DCLP +C2 IN-A 6 1.5p +C3 3 IN+A 1.5p +C4 IN+A 6 1.5p +R1 IN-A 1 30K +R3 IN+A 8 30K +R5 4 IN-A 60K +R8 5 IN+A 60K +G2 N013 0 N005 3 50m dir=1 vto=.19 +G8 0 N013 6 N005 50m dir=1 vto=.10 +G9 0 N013 N012 3 50m dir=1 vto=.19 +G10 N013 0 6 N012 50m dir=1 vto=.10 +A4 0 N003 0 0 0 0 N004 0 OTA G=18m Iout=900u en=30.9n enk=285 Cout=3n Rout=2.5Meg Vlow=-1e308 Vhigh=1e308 +G11 N004 0 N004 HI 50m dir=1 vto=3 +G12 0 N004 LO N004 50m dir=1 vto=3 +G13 0 HI 3 0 500µ +R16 HI 0 1K +G14 HI 0 6 0 500µ +G15 0 LO 6 0 500µ +R17 LO 0 1K +G16 LO 0 3 0 500µ +.model N VDMOS(Vto=-70m Kp=138m) +.model P VDMOS(Vto=70m Kp=138m pchan) +.model Y D(Ron=10K Roff=1T Vfwd=.6 epsilon=10m noiseless) +.model DBIAS D(Ron=5K ilimit=2p epsilon=.5 noiseless) +.model DPOW D(Ron=1k ilimit=60.8u epsilon=.1 noiseless) +.model DCLP D(Is=1e-18 Rs=500 noiseless) +.model swSlew SW(Ron=10k Roff=1G vt= 5m vh=-2m) +.ends LTC1992-2 +* +.subckt LTC1992-5 1 2 3 4 5 6 7 8 +A1 IN-A IN+A 0 0 0 0 0 0 OTA g=0 in=1f +C5 3 IN-A 1.5p +C6 N006 0 50f Rpar=100K noiseless +G1 0 N010 N013 0 1m +M1 3 N005 4 4 N temp=27 +M2 6 N005 4 4 P temp=27 +C7 N005 0 2f +G4 0 N012 N004 0 200n +C8 N012 0 2f +M3 3 N012 5 5 N temp=27 +M4 6 N012 5 5 P temp=27 +G6 N012 0 N010 0 200n +D4 N012 5 Y +D5 5 N012 Y +D8 4 N005 Y +D9 N005 4 Y +G5 0 N005 N010 0 200n +G3 0 N005 N004 0 200n +R9 4 VCM 30K noiseless +R11 VCM 5 30K noiseless +B1 0 N006 I=10u*dnlim(uplim(V(IN+A),V(3)-1.2,.1), V(6)-.2, .1)+1n*V(IN+A) +B2 N006 0 I=10u*dnlim(uplim(V(IN-A),V(3)-1.19,.1), V(6)-.21, .1)+1n*V(IN-A) +C19 3 4 1p +C12 4 6 1p +C16 3 5 1p +C17 5 6 1p +D13 IN+A 6 DBIAS +D14 IN-A 6 DBIAS +A2 0 N007 0 0 0 0 N013 0 OTA g=10.1u cout=700f iout=10u Vlow=-1e308 Vhigh=1e308 +R2 3 7 200K +R4 7 6 200K +C10 N013 N017 60p noiseless +A3 0 N006 0 0 0 0 N007 0 OTA g=1u cout=40f en=30.9n enk=285 linear Rout=1Meg Vlow=-1e308 Vhigh=1e308 +C13 N010 0 1p Rpar=1k noiseless +R12 N013 0 500Meg noiseless +S1 N007 0 N016 0 swSlew +S2 0 N007 0 N016 swSlew +C18 N013 N016 10f +A5 N011 N017 N017 N017 N017 N017 N011 N017 OTA g=60u iout=1u Vlow=-1e308 Vhigh=1e308 +R14 N011 N017 500K noiseless +C14 N016 0 10f Rpar=780k noiseless +R15 2 6 500Meg noiseless +B3 0 N003 I=10u*dnlim(uplim(V(2),V(3)-1.2,.1), V(6)+.4, .1)+1n*V(2) +C1 N003 0 500f Rpar=100K noiseless +B4 N003 0 I=10u*dnlim(uplim(V(VCM),V(3)-1.19,.1), V(6)+.39, .1)+1n*V(VCM) +D1 3 6 DPOW +G7 0 N011 4 5 1m +C9 N011 0 100f Rpar=500 noiseless +R7 3 N005 10Meg noiseless +R10 N005 6 10Meg noiseless +R13 N012 6 10Meg noiseless +R6 3 N012 10Meg noiseless +D3 6 8 DCLP +D2 6 1 DCLP +D6 1 3 DCLP +D7 8 3 DCLP +C2 IN-A 6 1.5p +C3 3 IN+A 1.5p +C4 IN+A 6 1.5p +R1 IN-A 1 30K +R3 IN+A 8 30K +R5 4 IN-A 150K +R8 5 IN+A 150K +G2 N013 0 N005 3 50m dir=1 vto=.19 +G8 0 N013 6 N005 50m dir=1 vto=.10 +G9 0 N013 N012 3 50m dir=1 vto=.19 +G10 N013 0 6 N012 50m dir=1 vto=.10 +A4 0 N003 0 0 0 0 N004 0 OTA G=18m Iout=900u en=30.9n enk=285 Cout=3n Rout=2.5Meg Vlow=-1e308 Vhigh=1e308 +G11 N004 0 N004 HI 50m dir=1 vto=3 +G12 0 N004 LO N004 50m dir=1 vto=3 +G13 0 HI 3 0 500µ +R16 HI 0 1K +G14 HI 0 6 0 500µ +G15 0 LO 6 0 500µ +R17 LO 0 1K +G16 LO 0 3 0 500µ +.model N VDMOS(Vto=-70m Kp=138m) +.model P VDMOS(Vto=70m Kp=138m pchan) +.model Y D(Ron=10K Roff=1T Vfwd=.6 epsilon=10m noiseless) +.model DBIAS D(Ron=5K ilimit=2p epsilon=.5 noiseless) +.model DPOW D(Ron=1k ilimit=60.8u epsilon=.1 noiseless) +.model DCLP D(Is=1e-18 Rs=500 noiseless) +.model swSlew SW(Ron=10k Roff=1G vt= 5m vh=-2m) +.ends LTC1992-5 +* +.subckt LTC1992-10 1 2 3 4 5 6 7 8 +A1 IN-A IN+A 0 0 0 0 0 0 OTA g=0 in=1f +C5 3 IN-A 1.5p +C6 N006 0 50f Rpar=100K noiseless +G1 0 N010 N013 0 1m +M1 3 N005 4 4 N temp=27 +M2 6 N005 4 4 P temp=27 +C7 N005 0 2f +G4 0 N012 N004 0 200n +C8 N012 0 2f +M3 3 N012 5 5 N temp=27 +M4 6 N012 5 5 P temp=27 +G6 N012 0 N010 0 200n +D4 N012 5 Y +D5 5 N012 Y +D8 4 N005 Y +D9 N005 4 Y +G5 0 N005 N010 0 200n +G3 0 N005 N004 0 200n +R9 4 VCM 30K noiseless +R11 VCM 5 30K noiseless +B1 0 N006 I=10u*dnlim(uplim(V(IN+A),V(3)-1.2,.1), V(6)-.2, .1)+1n*V(IN+A) +B2 N006 0 I=10u*dnlim(uplim(V(IN-A),V(3)-1.19,.1), V(6)-.21, .1)+1n*V(IN-A) +C19 3 4 1p +C12 4 6 1p +C16 3 5 1p +C17 5 6 1p +D13 IN+A 6 DBIAS +D14 IN-A 6 DBIAS +A2 0 N007 0 0 0 0 N013 0 OTA g=10.1u cout=700f iout=10u Vlow=-1e308 Vhigh=1e308 +R2 3 7 200K +R4 7 6 200K +C10 N013 N017 60p noiseless +A3 0 N006 0 0 0 0 N007 0 OTA g=1u cout=40f en=30.9n enk=285 linear Rout=1Meg Vlow=-1e308 Vhigh=1e308 +C13 N010 0 1p Rpar=1k noiseless +R12 N013 0 500Meg noiseless +S1 N007 0 N016 0 swSlew +S2 0 N007 0 N016 swSlew +C18 N013 N016 10f +A5 N011 N017 N017 N017 N017 N017 N011 N017 OTA g=60u iout=1u Vlow=-1e308 Vhigh=1e308 +R14 N011 N017 500K noiseless +C14 N016 0 10f Rpar=780k noiseless +R15 2 6 500Meg noiseless +B3 0 N003 I=10u*dnlim(uplim(V(2),V(3)-1.2,.1), V(6)+.4, .1)+1n*V(2) +C1 N003 0 500f Rpar=100K noiseless +B4 N003 0 I=10u*dnlim(uplim(V(VCM),V(3)-1.19,.1), V(6)+.39, .1)+1n*V(VCM) +D1 3 6 DPOW +G7 0 N011 4 5 1m +C9 N011 0 100f Rpar=500 noiseless +R7 3 N005 10Meg noiseless +R10 N005 6 10Meg noiseless +R13 N012 6 10Meg noiseless +R6 3 N012 10Meg noiseless +D3 6 8 DCLP +D2 6 1 DCLP +D6 1 3 DCLP +D7 8 3 DCLP +C2 IN-A 6 1.5p +C3 3 IN+A 1.5p +C4 IN+A 6 1.5p +R1 IN-A 1 15K +R3 IN+A 8 15K +R5 4 IN-A 150K +R8 5 IN+A 150K +G2 N013 0 N005 3 50m dir=1 vto=.19 +G8 0 N013 6 N005 50m dir=1 vto=.10 +G9 0 N013 N012 3 50m dir=1 vto=.19 +G10 N013 0 6 N012 50m dir=1 vto=.10 +A4 0 N003 0 0 0 0 N004 0 OTA G=18m Iout=900u en=30.9n enk=285 Cout=3n Rout=2.5Meg Vlow=-1e308 Vhigh=1e308 +G11 N004 0 N004 HI 50m dir=1 vto=3 +G12 0 N004 LO N004 50m dir=1 vto=3 +G13 0 HI 3 0 500µ +R16 HI 0 1K +G14 HI 0 6 0 500µ +G15 0 LO 6 0 500µ +R17 LO 0 1K +G16 LO 0 3 0 500µ +.model N VDMOS(Vto=-70m Kp=138m) +.model P VDMOS(Vto=70m Kp=138m pchan) +.model Y D(Ron=10K Roff=1T Vfwd=.6 epsilon=10m noiseless) +.model DBIAS D(Ron=5K ilimit=2p epsilon=.5 noiseless) +.model DPOW D(Ron=1k ilimit=60.8u epsilon=.1 noiseless) +.model DCLP D(Is=1e-18 Rs=500 noiseless) +.model swSlew SW(Ron=10k Roff=1G vt= 5m vh=-2m) +.ends LTC1992-10 +* +.subckt LTC6104 1 2 3 4 5 6 7 8 +M1 1 N009 7 7 P Temp=27 +M2 N013 N010 6 6 P Temp=27 +D1 N006 N005 X +D2 N007 N008 X +R1 8 N005 5K noiseless +D3 5 N006 Y +D4 5 N007 Y +D5 7 5 Z +D6 6 5 Z +Q3 N013 N013 4 0 N Temp=27 +Q4 1 N013 4 0 N Temp=27 +A2 N007 N008 6 6 6 6 N010 6 OTA Vhigh=0 Vlow=-2 g=10m Iout=100u Rout=1Meg +D7 4 1 Z +R2 7 N006 5K noiseless +R3 6 N007 5K noiseless +R4 5 N008 5K noiseless +A1 N006 N005 7 7 7 7 N009 7 OTA Vhigh=0 Vlow=-2 g=10m Iout=100u Rout=1Meg +D8 5 4 A +R9 5 4 420K +D10 6 4 B +D11 7 4 B +D12 8 4 B +.model X D(Ron=100 Roff=10G Vfwd=.6 Vrev=.6 epsilon=.1 Revepsilon=.1 noiseless) +.model Y D(Ron=100 Roff=1G Vfwd=1.8 epsilon=1 noiseless) +.model Z D(Ron=100 Roff=1G Vfwd=1 epsilon=1 Vrev=10 RevEpsilon=1 noiseless) +.model P VDMOS(Vto=-.3 Kp=10m Cgs=2.2n pchan) +.model N NPN(Cje=3p Cjc=3p) +.model A D(Ron=3.5K epsilon=1.2 Ilimit=500u noiseless) +.model B D(Ron=20Meg Ilimit=100n epsilon=2 noiseless) +.ends LTC6104 +* +.subckt LT1468-2 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=10f ink=7 +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C3 3 5 .5p +C4 5 4 .5p +B1 0 N006 I=10u*dnlim(uplim(V(1),V(3)-1.3,.1), V(4)+.5, .1)+1n*V(1) +B2 N006 0 I=10u*dnlim(uplim(V(2),V(3)-1.29,.1), V(4)+0.49, .1)+1n*V(2) +C6 3 1 2p Rser=100 Rpar=480Meg noiseless +C7 1 4 2p noiseless Rser=100 Rpar=480Meg +C8 2 4 2p Rser=100 Rpar=480Meg noiseless +C9 3 2 2p Rser=100 Rpar=480Meg noiseless +C10 N006 0 18.2f Rpar=100K noiseless +D1 N005 5 Y +D6 5 N005 Y +D7 3 4 DP +C11 2 1 1p Rpar=150k noiseless +A2 0 N006 0 0 0 0 N007 0 OTA g=42.1u Iout=1.045u Cout=33.3f en=5n enk=40 Vhigh=1e308 Vlow=-1e308 +D2 N007 3 XU +D3 4 N007 XD +G2 0 N004 N007 0 1m +L2 N004 0 24.65µ Rpar=6k Rser=1.2k Cpar=162f noiseless +G1 0 N005 N004 0 1µ +C1 N005 0 125.3f Rpar=1Meg +C2 5 N005 160f Rser=10k +D4 2 1 DI +.model XU D(Ron=1K Roff=100G Vfwd=-1.3 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=100G Vfwd=-1.3 epsilon=.1 noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=.28 epsilon=.1 noiseless) +.model N VDMOS(Vto=-50m Kp=550m) +.model P VDMOS(Vto=50m Kp=550m pchan) +.model DP D(Roff=1T Ron=1k Vfwd=0.5 ilimit=3.413m noiseless) +.model DI D(Ron=250 Roff=1T Vfwd=1 Vrev=1 noiseless) +.ends LT1468-2 +* +.subckt LT6210 1 2 3 4 5 6 +R2 N006 N008 10.03K noiseless +R3 N008 N012 10K noiseless +Q1 N005 N006 2 0 N temp=27 +Q2 N013 N012 2 0 P temp=27 +M1 3 N007 5 5 N temp=27 +M2 4 N007 5 5 P temp=27 +C4 3 5 1p +C5 5 4 1p +R4 3 N001 15K noiseless +R8 N001 6 8K noiseless +G2 3 N006 N001 6 30µ +G1 N012 4 N001 6 30µ +D1 3 N006 1uA m=60 +D2 N012 4 1uA m=60 +R19 3 N005 100 noiseless +R20 N013 4 100 noiseless +G5 3 N010 3 N005 10m +G6 N010 4 N013 4 10m +C3 N009 0 .75p +D3 N009 3 X +D4 4 N009 X +G3 0 N007 N009 0 10µ +C1 N007 0 7f Rpar=100K noiseless +R5 N010 0 1.6K noiseless +G4 0 N009 N010 0 625µ +A1 6 N001 N010 N010 N010 N010 0 N010 VARISTOR +C2 3 2 .15p +C6 3 1 1p +C7 2 4 .15p +C8 1 4 1p +G7 3 4 N001 6 table(0 0 39m 40u .506 2.3m .93 3.5m) +A2 0 0 1 1 1 1 N008 1 OTA G=.1 Rout=10 Linear Vhigh=100 Vlow=-100 en=14.4n-165u*I(R8)+.84*I(R8)*I(R8) enk=20 +A3 0 1 0 0 0 0 0 0 OTA in=1.2p ink=30 +A4 0 2 0 0 0 0 0 0 OTA in=16p ink=8 +.model N NPN(Cje=.56p Cjc=.15p noiseless) +.model P PNP(Cje=.56p Cjc=.15p noiseless) +.model N VDMOS(Vto=-50m Kp=150m) +.model P VDMOS(Vto=50m Kp=150m pchan) +.model 1uA D(Ron=100K vfwd=-.6 epsilon=.5 Ilimit=1u noiseless) +.model X D(Ron=1K Roff=100Meg epsilon=1 Vfwd=1 noiseless) +.param Rset=20K +.ends LT6210 +* +.subckt LTC6252 1 2 3 4 5 6 +B1 0 x0 I=10u*dnlim(uplim(V(3),V(6)+.51,.1), V(2)-.61, .1)+1n*V(3) +B2 x0 0 I=10u*dnlim(uplim(V(4),V(6)+.5,.1), V(2)-.6, .1)+1n*V(4) +C10 x0 0 .1f Rpar=100K noiseless +Q1 N012 N012 N011 0 PNP1 temp=27 +R3 6 N011 2.2K noiseless +R4 N013 N012 160 noiseless +Q2 1 N013 6 0 PNP2 M=3.5 temp=27 +Q3 N014 N014 N016 0 NPN1 temp=27 +Q4 1 N015 2 0 NPN2 M=3.5 temp=27 +C3 1 N012 700f Rser=1.8k noiseless +C15 1 N014 700f Rser=1.8k noiseless +B3 N012 2 I=uplim(dnlim(-1.12m*V(VFOLDP),0,92u),1m,.1m)*(.5+.5*tanh((V(ON)-.5)/100m)) +B4 6 N014 I=uplim(dnlim(1.12m*V(VFOLDP),0,92u),1.1m,.1m)*(.5+.5*tanh((V(ON)-.5)/100m)) +C19 N012 VFOLD 900f +A1 4 3 0 0 0 0 0 0 OTA g=0 in=4p ink=3k +C4 6 3 .2p Rpar=30Meg noiseless +C5 6 2 10p Rpar=125k noiseless +C6 2 5 500f Rpar=1g noiseless +D1 4 3 DIN +S1 5 6 2 5 SSHUT +S2 6 2 ON 0 SPOW +C7 4 3 1.7p +C8 6 4 .2p Rpar=30Meg noiseless +C9 3 2 .2p Rpar=30Meg noiseless +C13 4 2 .2p Rpar=30Meg noiseless +D2 6 N005 DBIAS1 +D3 4 N005 DBIAS2 +D4 3 N005 DBIAS2 +C17 N005 2 100f +S3 2 N005 N008 0 SBIAS +A2 5 2 0 0 0 0 N008 0 SCHMITT Vt=1.05 vh=.1 trise=6.2u tfall=2.8u +A5 0 x0 ON 0 0 0 X2 0 OTA g=1m iout=5m en=2.75n enk=1.45k vlow=-1e308 vhigh=1e308 +S4 6 N012 0 ON SOFF +S5 N014 2 0 ON SOFF +A3 N008 0 0 0 0 0 ON 0 BUF trise=1u +R5 N016 2 2.2K noiseless +R6 N015 N014 160 noiseless +C22 VFOLD VMid 10p Rpar=169K Rser=2k noiseless +G7 0 VFOLDP VFOLD VMid 1m +C23 VFOLDP 0 2p Rpar=1k Rser=1k noiseless +C24 VFOLD 1 1.2p Rser=2.2k noiseless +C12 6 1 4p Rpar=200Meg noiseless +C25 1 2 4p Rpar=200Meg noiseless +G1 0 VMid 6 0 5m +G5 0 VMid 2 0 5m +C1 VMid 0 200p Rpar=100 noiseless +G2 VFOLD VMid VFOLD 6 10m vto=0 dir=1 +G4 VMid VFOLD 2 VFOLD 10m vto=0 dir=1 +D5 X2 0 DSL1 +D8 X2 0 DSL2 +C16 N014 VFOLD 900f +G6 0 X2 N004 0 500m vto=640m dir=1 +G8 X2 0 0 N007 500m vto=640m dir=1 +G9 VMid VFOLD 0 X2 8m +A4 N007 x0 ON 0 0 0 N007 0 OTA g=60u iout=50u vlow=-1e308 vhigh=0 +C14 0 N007 500f Rpar=500k noiseless +A6 N004 x0 ON 0 0 0 N004 0 OTA g=60u iout=50u vlow=0 vhigh=1e308 +C18 0 N004 500f Rpar=500k noiseless +C20 X2 0 3.27p Rpar=1k Rser=81.1 noiseless +.model SSHUT SW(Ron=2.5e6 Roff=50Meg vt=-1.7 vh=-200m noiseless) +.model DIN D(Ron=100 Roff=32k Vfwd=1.6 epsilon=.1 Vrev=1.6 revepsilon=.1 noiseless) +.model DBIAS1 D(Ron=100 Roff=1g vfwd=3.5 epsilon=100m noiseless) +.model DBIAS2 D(Ron=100k Roff=10Meg vfwd=2.2 epsilon=100m ilimit=1u noiseless) +.model SBIAS SW(level=2 Ron=1.3k Roff=10G vt=.5 vh=-.1 noiseless ) +.model SPOW SW(Ron=100 Roff=1G vt=.5 vh=.1 ilimit=2m noiseless) +.model PNP1 PNP(BF=100 VAF=100 CJE=10f noiseless) +.model NPN1 NPN(BF=100 VAF=100 CJE=10f noiseless) +.model PNP2 PNP(BF=100 BR=.09 VAF=100 CJE=100f CJC=80f RC=15 TF=10p noiseless) +.model NPN2 NPN(BF=100 BR=.62 VAF=100 CJE=100f CJC=80f RC=6.5 TF=10p noiseless) +.model SOFF SW(Ron=100 Roff=1G vt=-.5 vh=-.3 noiseless) +.model DSL1 D(Ron=10 Roff=200k vfwd=30m epsilon=30m vrev=30m revepsilon=30m noiseless ) +.model DSL2 D(Ron=.1 Roff=200k vfwd=400m epsilon=50m vrev=400m revepsilon=50m noiseless ) +.ends LTC6252 +* +.subckt LTC6253 1 2 3 4 5 +B1 0 x0 I=10u*dnlim(uplim(V(3),V(5)+.51,.1), V(2)-.61, .1)+1n*V(3) +B2 x0 0 I=10u*dnlim(uplim(V(4),V(5)+.5,.1), V(2)-.6, .1)+1n*V(4) +C10 x0 0 .1f Rpar=100K noiseless +Q1 N010 N010 N009 0 PNP1 temp=27 +R3 5 N009 2.2K noiseless +R4 N011 N010 160 noiseless +Q2 1 N011 5 0 PNP2 M=3.5 temp=27 +Q3 N012 N012 N014 0 NPN1 temp=27 +Q4 1 N013 2 0 NPN2 M=3.5 temp=27 +C3 1 N010 700f Rser=1.8k noiseless +C15 1 N012 700f Rser=1.8k noiseless +B3 N010 2 I=uplim(dnlim(-1.12m*V(VFOLDP),0,92u),1m,.1m) +B4 5 N012 I=uplim(dnlim(1.12m*V(VFOLDP),0,92u),1.1m,.1m) +C19 N010 VFOLD 900f +A1 4 3 0 0 0 0 0 0 OTA g=0 in=4p ink=3k +C4 5 3 .2p Rpar=30Meg noiseless +C5 5 2 10p Rpar=125k noiseless +D1 4 3 DIN +C7 4 3 1.7p +C8 5 4 .2p Rpar=30Meg noiseless +C9 3 2 .2p Rpar=30Meg noiseless +C13 4 2 .2p Rpar=30Meg noiseless +D2 5 N005 DBIAS1 +D3 4 N005 DBIAS2 +D4 3 N005 DBIAS2 +A5 0 x0 0 0 0 0 X2 0 OTA g=1m iout=5m en=2.75n enk=1.45k vlow=-1e308 vhigh=1e308 +R5 N014 2 2.2K noiseless +R6 N013 N012 160 noiseless +C22 VFOLD VMid 10p Rpar=169K Rser=2k noiseless +G7 0 VFOLDP VFOLD VMid 1m +C23 VFOLDP 0 2p Rpar=1k Rser=1k noiseless +C24 VFOLD 1 1.2p Rser=2.2k noiseless +C12 5 1 4p Rpar=200Meg noiseless +C25 1 2 4p Rpar=200Meg noiseless +G1 0 VMid 5 0 5m +G5 0 VMid 2 0 5m +C1 VMid 0 200p Rpar=100 noiseless +G2 VFOLD VMid VFOLD 5 10m vto=0 dir=1 +G4 VMid VFOLD 2 VFOLD 10m vto=0 dir=1 +D5 X2 0 DSL1 +D8 X2 0 DSL2 +C16 N012 VFOLD 900f +G6 0 X2 N004 0 500m vto=640m dir=1 +G8 X2 0 0 N007 500m vto=640m dir=1 +G9 VMid VFOLD 0 X2 8m +A4 N007 x0 0 0 0 0 N007 0 OTA g=60u iout=50u vlow=-1e308 vhigh=0 +C14 0 N007 500f Rpar=500k noiseless +A6 N004 x0 0 0 0 0 N004 0 OTA g=60u iout=50u vlow=0 vhigh=1e308 +C18 0 N004 500f Rpar=500k noiseless +C20 X2 0 3.27p Rpar=1k Rser=81.1 noiseless +C2 N005 2 100f Rpar=3.5k noiseless +D6 5 2 DPOW +.model SSHUT SW(Ron=2.5e6 Roff=50Meg vt=-1.7 vh=-200m noiseless) +.model DIN D(Ron=100 Roff=32k Vfwd=1.6 epsilon=.1 Vrev=1.6 revepsilon=.1 noiseless) +.model DBIAS1 D(Ron=100 Roff=1g vfwd=3.5 epsilon=100m noiseless) +.model DBIAS2 D(Ron=100k Roff=10Meg vfwd=2.2 epsilon=100m ilimit=1u noiseless) +.model DPOW D(Ron=100 Vfwd=100m epsilon=50m ilimit=2m noiseless) +.model PNP1 PNP(BF=100 VAF=100 CJE=10f noiseless) +.model NPN1 NPN(BF=100 VAF=100 CJE=10f noiseless) +.model PNP2 PNP(BF=100 BR=.09 VAF=100 CJE=100f CJC=80f RC=15 TF=10p noiseless) +.model NPN2 NPN(BF=100 BR=.62 VAF=100 CJE=100f CJC=80f RC=6.5 TF=10p noiseless) +.model DSL1 D(Ron=10 Roff=200k vfwd=30m epsilon=30m vrev=30m revepsilon=30m noiseless ) +.model DSL2 D(Ron=.1 Roff=200k vfwd=400m epsilon=50m vrev=400m revepsilon=50m noiseless ) +.ends LTC6253 +* +.subckt LTC6253-7 1 2 3 4 5 6 +B1 0 x0 I=10u*dnlim(uplim(V(3),V(6)+.51,.1), V(2)-.61, .1)+1n*V(3) +B2 x0 0 I=10u*dnlim(uplim(V(4),V(6)+.5,.1), V(2)-.6, .1)+1n*V(4) +C10 x0 0 .1f Rpar=100K noiseless +Q1 N010 N010 N009 0 PNP1 temp=27 +R3 6 N009 2.2K noiseless +R4 N011 N010 160 noiseless +Q2 1 N011 6 0 PNP2 M=3.5 temp=27 +Q3 N013 N013 N015 0 NPN1 temp=27 +Q4 1 N014 2 0 NPN2 M=3.5 temp=27 +B3 N010 2 I=uplim(dnlim(-1.12m*V(VFOLDP),0,92u),1m,.1m)*(.5+.5*tanh((V(ON)-.5)/100m)) +B4 6 N013 I=uplim(dnlim(1.12m*V(VFOLDP),0,92u),1.1m,.1m)*(.5+.5*tanh((V(ON)-.5)/100m)) +C19 N010 VFOLD 900f +A1 4 3 0 0 0 0 0 0 OTA g=0 in=4p ink=3k +C4 6 3 .2p Rpar=30Meg noiseless +C5 6 2 10p Rpar=125k noiseless +C6 2 5 500f Rpar=1g noiseless +D1 4 3 DIN +S1 5 6 2 5 SSHUT +S2 6 2 ON 0 SPOW +C7 4 3 1.7p +C8 6 4 .2p Rpar=30Meg noiseless +C9 3 2 .2p Rpar=30Meg noiseless +C13 4 2 .2p Rpar=30Meg noiseless +D2 6 N004 DBIAS1 +D3 4 N004 DBIAS2 +D4 3 N004 DBIAS2 +C17 N004 2 100f +S3 2 N004 N006 0 SBIAS +A2 5 2 0 0 0 0 N006 0 SCHMITT Vt=1.05 vh=.1 trise=6.2u tfall=2.8u +A5 0 x0 ON 0 0 0 X2 0 OTA g=1m iout=5m en=2.75n enk=1.45k vlow=-1e308 vhigh=1e308 +S4 6 N010 0 ON SOFF +S5 N013 2 0 ON SOFF +A3 N006 0 0 0 0 0 ON 0 BUF trise=1u +R5 N015 2 2.2K noiseless +R6 N014 N013 160 noiseless +C22 VFOLD VMid 12p Rpar=169K Rser=1k noiseless +G7 0 VFOLDP VFOLD VMid 1m +C23 VFOLDP 0 1p Rpar=1k Rser=4k noiseless +C12 6 1 4p Rpar=200Meg noiseless +C25 1 2 4p Rpar=200Meg noiseless +G1 0 VMid 6 0 5m +G5 0 VMid 2 0 5m +C1 VMid 0 200p Rpar=100 noiseless +G2 VFOLD VMid VFOLD 6 10m vto=0 dir=1 +G4 VMid VFOLD 2 VFOLD 10m vto=0 dir=1 +D5 X2 0 DSL1 +D8 X2 0 DSL2 +C16 N013 VFOLD 900f +G6 0 X2 SBP 0 500m vto=172m dir=1 +G8 X2 0 0 SBN 500m vto=172m dir=1 +G9 VMid VFOLD 0 N012 8m +A4 SBN x0 ON 0 0 0 SBN 0 OTA g=60u iout=50u vlow=-1e308 vhigh=0 +C14 0 SBN 500f Rpar=500k noiseless +A6 SBP x0 ON 0 0 0 SBP 0 OTA g=60u iout=50u vlow=0 vhigh=1e308 +C18 0 SBP 500f Rpar=500k noiseless +C20 X2 0 3p Rpar=1k Rser=5k noiseless +C2 VFOLD 1 100f Rser=2.2k noiseless +C3 6 N010 100f +C11 N013 2 100f +G3 0 N012 X2 0 1m +C15 N012 0 300f Rpar=1k Rser=1 noiseless +.model SSHUT SW(Ron=2.5e6 Roff=50Meg vt=-1.7 vh=-200m noiseless) +.model DIN D(Ron=100 Roff=32k Vfwd=1.6 epsilon=.1 Vrev=1.6 revepsilon=.1 noiseless) +.model DBIAS1 D(Ron=100 Roff=1g vfwd=3.5 epsilon=100m noiseless) +.model DBIAS2 D(Ron=100k Roff=10Meg vfwd=2.2 epsilon=100m ilimit=1u noiseless) +.model SBIAS SW(level=2 Ron=1.3k Roff=10G vt=.5 vh=-.1 noiseless ) +.model SPOW SW(Ron=100 Roff=1G vt=.5 vh=.1 ilimit=2m noiseless) +.model PNP1 PNP(BF=100 VAF=100 CJE=10f noiseless) +.model NPN1 NPN(BF=100 VAF=100 CJE=10f noiseless) +.model PNP2 PNP(BF=100 BR=.09 VAF=100 CJE=500f CJC=120f RC=15 TF=10p noiseless) +.model NPN2 NPN(BF=100 BR=.62 VAF=100 CJE=500f CJC=120f RC=6.5 TF=10p noiseless) +.model SOFF SW(Ron=100 Roff=1G vt=-.5 vh=-.3 noiseless) +.model DSL1 D(Ron=10 Roff=200k vfwd=30m epsilon=30m vrev=30m revepsilon=30m noiseless ) +.model DSL2 D(Ron=.1 Roff=200k vfwd=400m epsilon=50m vrev=400m revepsilon=50m noiseless ) +.ends LTC6253-7 +* +.subckt LTC6255 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=70f ink=100k +C2 2 1 .1p Rpar=1Meg noiseless +B1 0 N005 I=10u*dnlim(uplim(V(1),V(3)+.3,.1), V(4)-.3, .1)+1n*V(1) +B2 N005 0 I=10u*dnlim(uplim(V(2),V(3)+.31,.1), V(4)-.31, .1)+1n*V(2) +C9 3 2 .15p +C10 N005 0 80f Rpar=100K noiseless +M1 3 N008 5 5 N temp=27 +M2 4 N013 5 5 P temp=27 +C3 3 5 1p Rpar=100Meg noiseless +D5 N008 5 YU +D6 5 N013 YD +D3 3 4 DC +R2 3 N004 5G noiseless +R3 N004 4 5G noiseless +A2 0 N005 N006 0 0 0 N012 0 OTA g=1u linear en=20n enk=140 Vlow=-1e308 Vhigh=1e308 +S5 N009 0 0 N010 swSlew +S6 0 N009 N010 0 swSlew +L3 N012 0 197m Cpar=.26f Rser=1.12Meg Rpar=9.333333333333333333Meg noiseless +S1 N009 0 5 N004 swLimD +S2 0 N009 N004 5 swLimU +G2 0 N011 N004 0 1µ +L2 N011 0 683.6 Rser=33.33Meg Rpar=1.030931023816888339Meg noiseless +G4 0 N004 N009 0 85µ +C12 N004 N010 1p +R1 N010 0 6.63k noiseless +G1 0 N009 N012 0 10µ +C14 N009 0 1.8p Rpar=100k noiseless +C11 N004 0 1.8p +C13 N004 5 40p Rser=10k noiseless +R4 3 6 5Meg noiseless +A3 6 4 0 0 0 0 N006 0 SCHMITT Vt=1 Vh=10m tau=1u +A4 N006 0 N011 N011 N011 N011 N008 N011 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-6 Rout=1k Cout=4p +A5 N006 0 N011 N011 N011 N013 N011 N011 SCHMITT Vt=.5 Vh=10m Vhigh=6 Vlow=0 Rout=1k Cout=4p +C1 2 4 .15p +C6 3 1 .15p +C7 1 4 .15p +D1 3 N015 DBIASU +D2 N015 4 DBIASD +R6 N015 4 200Meg noiseless +R8 3 N015 300Meg noiseless +D4 3 N007 DBIASU +D7 N007 4 DBIASD +R9 N007 4 200Meg noiseless +R10 3 N007 300Meg noiseless +S3 N015 1 N006 0 swBias +S8 2 N007 N006 0 swBias +S9 N004 5 N006 0 shutD +C4 5 4 1p Rpar=100Meg noiseless +D8 2 1 DINLIM +C8 N007 0 1f +C15 N015 0 1f +G3 4 N004 4 N004 500m dir=1 vto=370m +G5 N004 3 N004 3 500m dir=1 vto=54m +.model YU D(Ron=100 Roff=1T Vfwd=.67 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=1.06 epsilon=.1 noiseless) +.model N VDMOS(Vto=-35m Kp=100m) +.model P VDMOS(Vto=35m Kp=100m pchan) +.model DC D(Ron=100.0 Roff=1G Vfwd=1.0 ilimit=4u noiseless) +.model swSlew SW(Ron=1 Roff=100G vt=10m vh=-9m) +.model swLimU SW(Ron=1 Roff=100G vt=1 vh=-100m) +.model swLimD SW(Ron=1 Roff=100G vt=1 vh=-100m) +.model DBIASU D(Ron=1Meg Roff=1G Vfwd=-60m ilimit=50n noiseless) +.model DBIASD D(Ron=1Meg Roff=1G Vfwd=30m ilimit=50n noiseless) +.model DINLIM D(Ron=1k Roff=10Meg Vfwd=1.6 Vrev=1.6 noiseless) +.model swBias SW(Ron=100k Roff=1T vt=.5 vh=-.1) +.model shutD SW(Ron=1T Roff=10k vt=.5 vh=-.1) +.ends LTC6255 +* +.subckt LT1236-5 1 2 3 +A1 3 2 2 2 2 2 N005 2 OTA g=50u Iout=50u en=66n+34n/(dnlim(freq/10,.25,.1)**2) Cout=10p Rout=5G Ref=5 Vlow=-10 Vhigh=100 +M1 N002 N003 3 3 N temp=27 +M2 2 N003 3 3 P temp=27 +C7 N002 3 5p +C8 3 2 5p +D1 1 N002 1V +D2 2 N005 X +G1 2 N003 N005 2 10µ +C4 N003 2 2p Rser=20K Rpar=100K noiseless +D3 N003 3 Y +A2 1 2 2 2 2 2 N004 2 SCHMITT Vt=2.5 Vh=1m Trise=100n +S1 N003 3 2 N004 O +C2 N002 2 10p Rpar=250K noiseless +D5 N002 2 Q +C3 1 2 10p +G2 N005 2 N005 1 1m Vto=5 dir=1 +.model X D(Ron=10K Roff=1T Vfwd=-1 epsilon=.1 noiseless) +.model 1V D(Ron=10 Roff=1T Vfwd=.8 epsilon=.2 noiseless) +.model Y D(Ron=100 Roff=1G epsilon=.3 Vfwd=.6 Vrev=.6 revepsilon=.3 noiseless) +.model Q D(Ron=1K Roff=1K Ilimit=.8m noiseless) +.model N VDMOS(Vto=-3m Kp=.1 noiseless) +.model P VDMOS(Vto=3m Kp=.1 noiseless pchan) +.model O SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4 noiseless) +.ends LT1236-5 +* +.subckt LT1236-10 1 2 3 +A1 3 2 2 2 2 2 N005 2 OTA g=50u Iout=50u en=120n+60n/(dnlim(freq/10,.25,.1)**1.5) Cout=10p Rout=5G Ref=10 Vlow=-10 Vhigh=100 +M1 N002 N003 3 3 N temp=27 +M2 2 N003 3 3 P temp=27 +C7 N002 3 5p +C8 3 2 5p +D1 1 N002 1V +D2 2 N005 X +G1 2 N003 N005 2 10µ +C4 N003 2 2p Rser=20K Rpar=100K noiseless +D3 N003 3 Y +A2 1 2 2 2 2 2 N004 2 SCHMITT Vt=2.5 Vh=1m Trise=100n +S1 N003 3 2 N004 O +C2 N002 2 10p Rpar=250K noiseless +D5 N002 2 Q +C3 1 2 10p +G2 N005 2 N005 1 1m Vto=5 dir=1 +D4 3 1 Z +.model X D(Ron=10K Roff=1T Vfwd=-1 epsilon=.1 noiseless) +.model 1V D(Ron=10 Roff=1T Vfwd=.8 epsilon=.2 noiseless) +.model Y D(Ron=100 Roff=1G epsilon=.3 Vfwd=.6 Vrev=.6 revepsilon=.3 noiseless) +.model Z D(Ron=100 Roff=1G epsilon=1 noiseless) +.model Q D(Ron=1K Roff=1K Ilimit=.8m noiseless) +.model N VDMOS(Vto=-3m Kp=.1 noiseless) +.model P VDMOS(Vto=3m Kp=.1 noiseless pchan) +.model O SW(Ron=1 Roff=1G Vt=-.5 Vh=-.4 noiseless) +.ends LT1236-10 +* +.subckt LT1567 1 2 3 4 5 6 7 8 +A1 2 3 0 0 0 0 0 0 OTA g=0 in=1p ink=634 +B1 0 N003 I=10u*dnlim(uplim(V(3),V(8)-.9,.1), V(4)+.9, .1)+1n*V(3)-1.9506n +B2 N003 0 I=10u*dnlim(uplim(V(2),V(8)-.89,.1), V(4)+.89, .1)+1n*V(2) +C10 N003 0 .1f Rpar=100K noiseless +M1 1 N014 4 4 NI temp=27 +C2 8 1 1p Rpar=1g noiseless +M2 1 N007 8 8 PI temp=27 +C3 8 N007 1p Rser=200Meg noiseless +A3 N008 N011 4 4 4 4 N007 4 OTA g=35n ref=-.04 linear vlow=-1e308 vhigh=1e308 +C11 1 4 1p Rpar=1g noiseless +C12 N014 4 1p Rser=200Meg noiseless +D10 3 4 DBIA +D11 2 4 DBIA +D6 N014 4 DLIMN +A4 0 N003 0 0 0 0 N009 0 OTA g=1u linear en=1.4n enk=681 Vhigh=1e308 Vlow=-1e308 +C16 N011 1 140f +A5 N010 0 N008 N008 N008 N008 N011 N008 OTA g=150u iout=8u Rout=800k Vhigh=1e308 Vlow=-1e308 +G1 4 N014 N011 N008 5n +C13 8 4 1000p +D7 8 4 DP +C17 0 N009 15f Rpar=1Meg noiseless +G4 0 N010 N009 0 1m +D14 8 N007 DLIMP +L1 N010 0 7.24µ Cpar=25.9f Rser=1.14k Rpar=8.14k noiseless +C1 8 2 .9p Rpar=12Meg noiseless +C6 3 4 7p Rpar=12Meg noiseless +C8 2 4 .9p Rpar=12Meg noiseless +G2 0 N008 8 0 .5m +G3 0 N008 4 0 .5m +C14 N008 0 4p Rpar=1K +A2 INVM 3 0 0 0 0 0 0 OTA g=0 in=1p ink=634 +B3 0 N016 I=10u*dnlim(uplim(V(3),V(8)-.9,.1), V(4)+.9, .1)+1n*V(3)-1.9506n +B4 N016 0 I=10u*dnlim(uplim(V(INVM),V(8)-.89,.1), V(4)+.89, .1)+1n*V(INVM) +C4 N016 0 .1f Rpar=100K noiseless +M3 7 N021 4 4 NI temp=27 +C5 8 7 1p Rpar=1g noiseless +M4 7 N017 8 8 PI temp=27 +C15 8 N017 1p Rser=200Meg noiseless +A6 N008 N020 4 4 4 4 N017 4 OTA g=35n ref=-.04 linear vlow=-1e308 vhigh=1e308 +C18 7 4 1p Rpar=1g noiseless +C19 N021 4 1p Rser=200Meg noiseless +D1 3 4 DBIA +D2 INVM 4 DBIA +D3 N021 4 DLIMN +A7 0 N016 0 0 0 0 N018 0 OTA g=1u linear en=1.65n enk=681 Vhigh=1e308 Vlow=-1e308 +C20 N020 7 112f +A8 N019 0 N008 N008 N008 N008 N020 N008 OTA g=150u iout=10.4u Rout=800k Vhigh=1e308 Vlow=-1e308 +G5 4 N021 N020 N008 5n +C21 8 3 .9p Rpar=12Meg noiseless +C22 8 4 1000p Rpar=2.8k noiseless +C23 0 N018 15f Rpar=1Meg noiseless +G6 0 N019 N018 0 1m +D5 8 N017 DLIMP +L2 N019 0 7.24µ Cpar=25.9f Rser=1.14k Rpar=8.14k noiseless +C24 8 INVM .9p Rpar=12Meg noiseless +C26 INVM 4 .9p Rpar=12Meg noiseless +C27 N008 0 .2p Rpar=1K +R3 3 5 150 +C28 8 3 .9p Rpar=12Meg noiseless +R4 INVM 6 600 +R6 7 INVM 600 +.model DP D(Roff=1T Ron=100 Vfwd=0.5 ilimit=4.73m noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m kp=30m lambda=.01 pchan is=0) +.model DBIA D(Ron=10k Roff=10Meg Vfwd=.8 ilimit=3u epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=3 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DLIMN D(Ron=1Meg Roff=5g Vfwd=3.4 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model DIN D(Ron=1k Roff=100g Vfwd=.8 Vrev=.8 epsilon=100m revepsilon=100m noiseless) +.ends LT1567 +* +.subckt LTC1068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 +R1 7 N008 200Meg noiseless +R2 N008 18 200Meg noiseless +M1 7 N007 11 11 N temp=27 +M2 18 N007 11 11 P temp=27 +D1 N007 11 YU +D2 11 N007 YD +G3 0 N007 N008 0 1µ +G8 6A N015 8 6A 10 +C2 N014 N013 1p +R5 7 N014 100Meg noiseless +R6 N014 18 100Meg noiseless +G5 N014 0 N014 7 500m dir=1 vto=-1 +G11 0 N014 18 N014 500m dir=1 vto=-1 +M3 7 N016 10 10 N temp=27 +M4 18 N016 10 10 P temp=27 +D3 N016 10 YU +D4 10 N016 YD +G12 0 N016 N014 0 1µ +C3 N016 0 .4f Rpar=1Meg noiseless +G13 6A N020 6A 10 10 +R8 N021 N020 {Rint} noiseless +C4 N022 N021 1p +R9 7 N022 100Meg noiseless +R10 N022 18 100Meg noiseless +G14 N022 0 N022 7 500m dir=1 vto=-1 +G15 0 N022 18 N022 500m dir=1 vto=-1 +M5 7 N023 9 9 N temp=27 +M6 18 N023 9 9 P temp=27 +D5 N023 9 YU +D6 9 N023 YD +G16 0 N023 N022 0 1µ +C5 N007 0 10f Rpar=1Meg noiseless +A2 N013 6A N019 0 0 0 N014 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +S3 N024 7 7 18 SPV +B1 0 N006 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B2 N006 0 I=10u*dnlim(uplim(V(12),V(7)+.21,.1), V(18)-.21, .1)+1n*V(12) +C6 N006 0 .2f Rpar=100K noiseless +C7 12 18 200f +C8 7 12 200f +C9 18 8 200f +C10 N015 6A 100f Rpar=.1 noiseless +C11 N020 6A 100f Rpar=.1 noiseless +R3 7 N027 200Meg noiseless +R7 N027 18 200Meg noiseless +M7 7 N026 2 2 N temp=27 +M8 18 N026 2 2 P temp=27 +D8 N026 2 YU +D9 2 N026 YD +G19 0 N026 N027 0 1µ +R11 N030 N033 {Rint} noiseless +C12 N031 N030 1p +R18 7 N031 100Meg noiseless +R19 N031 18 100Meg noiseless +G25 N031 0 N031 7 500m dir=1 vto=-1 +G26 0 N031 18 N031 500m dir=1 vto=-1 +M9 7 N034 3 3 N temp=27 +M10 18 N034 3 3 P temp=27 +D10 N034 3 YU +D11 3 N034 YD +G27 0 N034 N031 0 1µ +C13 N034 0 .4f Rpar=1Meg noiseless +G28 6A N036 6A 3 10 +C14 N038 N037 1p +R21 7 N038 200Meg noiseless +R22 N038 18 200Meg noiseless +G29 N038 0 N038 7 500m dir=1 vto=-1 +G30 0 N038 18 N038 500m dir=1 vto=-1 +M11 7 N039 4 4 N temp=27 +M12 18 N039 4 4 P temp=27 +D12 N039 4 YU +D13 4 N039 YD +G31 0 N039 N038 0 1µ +C15 N039 0 .4f Rpar=1Meg noiseless +C16 N026 0 10f Rpar=1Meg noiseless +B3 0 N025 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B4 N025 0 I=10u*dnlim(uplim(V(1),V(7)+.21,.1), V(18)-.21, .1)+1n*V(1) +C17 N025 0 .2f Rpar=100K noiseless +C18 1 18 200f +C19 7 1 200f +C20 18 5 200f +C21 N033 6A 100f Rpar=.1 noiseless +C22 N036 6A 100f Rpar=.1 noiseless +R4 N013 N015 {Rint} noiseless +R14 N037 N036 {Rint} noiseless +C23 N024 18 10p +C27 N031 N030 .001f IC=0 Rser=1Meg noiseless +C28 N038 N037 .001f IC=0 Rser=1Meg noiseless +C24 7 6 1p Rpar=10k noiseless +C29 6 18 1p Rpar=10k noiseless +G1 N008 0 N008 7 500m dir=1 vto=-.15 +G2 0 N008 18 N008 500m dir=1 vto=.1 +G4 N027 0 N027 7 500m dir=1 vto=-.69 +G6 0 N027 18 N027 500m dir=1 vto=-.69 +C1 N023 0 .4f Rpar=1Meg noiseless +A3 N021 6A N019 0 0 0 N022 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +A5 N037 6A N019 0 0 0 N038 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A6 N030 6A N019 0 0 0 N031 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +D14 N024 18 DPV1 +R27 7 18 1.334k noiseless +G7 0 6A 6 0 10m +C31 6A 0 100µ Rpar=100 noiseless +C32 7 11 1p +C33 11 18 1p +C34 7 10 1p +C35 10 18 1p +C36 7 9 1p +C37 9 18 1p +C38 7 2 1p +C39 2 18 1p +C40 7 3 1p +C41 3 18 1p +C42 7 4 1p +C43 4 18 1p +C25 N022 N021 .001f IC=0 Rser=1G noiseless +C26 N014 N013 .001f IC=0 Rser=1G noiseless +G10 0 N019 N024 18 10m +C45 N019 0 100µ Rpar=100 noiseless +G18 N015 6A 11 6A 10 +G17 N033 6A 2 6A 10 +G9 6A N033 5 6A 10 +D7 N024 18 DPV2 +A1 0 N006 0 0 0 0 N008 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +A4 0 N025 0 0 0 0 N027 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +R38 N024 18 320k noiseless +R39 7 N043 200Meg noiseless +R40 N043 18 200Meg noiseless +M13 7 N042 22 22 N temp=27 +M14 18 N042 22 22 P temp=27 +D16 N042 22 YU +D17 22 N042 YD +G20 0 N042 N043 0 1µ +R41 N045 N049 {Rint} noiseless +C44 N046 N045 1p +R42 7 N046 100Meg noiseless +R43 N046 18 100Meg noiseless +G21 N046 0 N046 7 500m dir=1 vto=-1 +G22 0 N046 18 N046 500m dir=1 vto=-1 +M15 7 N050 21 21 N temp=27 +M16 18 N050 21 21 P temp=27 +D18 N050 21 YU +D19 21 N050 YD +G23 0 N050 N046 0 1µ +C46 N050 0 .4f Rpar=1Meg noiseless +G24 6A N052 6A 21 10 +C47 N054 N053 1p +R44 7 N054 200Meg noiseless +R45 N054 18 200Meg noiseless +G32 N054 0 N054 7 500m dir=1 vto=-1 +G33 0 N054 18 N054 500m dir=1 vto=-1 +M17 7 N055 20 20 N temp=27 +M18 18 N055 20 20 P temp=27 +D20 N055 20 YU +D21 20 N055 YD +G34 0 N055 N054 0 1µ +C48 N055 0 .4f Rpar=1Meg noiseless +C49 N042 0 10f Rpar=1Meg noiseless +B5 0 N040 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B6 N040 0 I=10u*dnlim(uplim(V(23),V(7)+.21,.1), V(18)-.21, .1)+1n*V(23) +C50 N040 0 .2f Rpar=100K noiseless +C51 23 18 200f +C52 7 23 200f +C53 18 19 200f +C54 N049 6A 100f Rpar=.1 noiseless +C55 N052 6A 100f Rpar=.1 noiseless +R46 N053 N052 {Rint} noiseless +C56 N046 N045 .001f IC=0 Rser=1Meg noiseless +C57 N054 N053 .001f IC=0 Rser=1Meg noiseless +G35 N043 0 N043 7 500m dir=1 vto=-.69 +G36 0 N043 18 N043 500m dir=1 vto=-.69 +A7 N053 6A N019 0 0 0 N054 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A8 N045 6A N019 0 0 0 N046 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +C58 7 22 1p +C59 22 18 1p +C60 7 21 1p +C61 21 18 1p +C62 7 20 1p +C63 20 18 1p +G37 N049 6A 22 6A 10 +G38 6A N049 19 6A 10 +A9 0 N040 0 0 0 0 N043 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +R47 7 N059 200Meg noiseless +R48 N059 18 200Meg noiseless +M19 7 N058 14 14 N temp=27 +M20 18 N058 14 14 P temp=27 +D22 N058 14 YU +D23 14 N058 YD +G39 0 N058 N059 0 1µ +R49 N061 N064 {Rint} noiseless +C64 N062 N061 1p +R50 7 N062 100Meg noiseless +R51 N062 18 100Meg noiseless +G40 N062 0 N062 7 500m dir=1 vto=-1 +G41 0 N062 18 N062 500m dir=1 vto=-1 +M21 7 N065 15 15 N temp=27 +M22 18 N065 15 15 P temp=27 +D24 N065 15 YU +D25 15 N065 YD +G42 0 N065 N062 0 1µ +C65 N065 0 .4f Rpar=1Meg noiseless +G43 6A N067 6A 15 10 +C66 N069 N068 1p +R52 7 N069 200Meg noiseless +R53 N069 18 200Meg noiseless +G44 N069 0 N069 7 500m dir=1 vto=-1 +G45 0 N069 18 N069 500m dir=1 vto=-1 +M23 7 N070 16 16 N temp=27 +M24 18 N070 16 16 P temp=27 +D26 N070 16 YU +D27 16 N070 YD +G46 0 N070 N069 0 1µ +C67 N070 0 .4f Rpar=1Meg noiseless +C68 N058 0 10f Rpar=1Meg noiseless +B7 0 N056 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B8 N056 0 I=10u*dnlim(uplim(V(13),V(7)+.21,.1), V(18)-.21, .1)+1n*V(13) +C69 N056 0 .2f Rpar=100K noiseless +C70 13 18 200f +C71 7 13 200f +C72 18 17 200f +C73 N064 6A 100f Rpar=.1 noiseless +C74 N067 6A 100f Rpar=.1 noiseless +R54 N068 N067 {Rint} noiseless +C75 N062 N061 .001f IC=0 Rser=1Meg noiseless +C76 N069 N068 .001f IC=0 Rser=1Meg noiseless +G47 N059 0 N059 7 500m dir=1 vto=-.69 +G48 0 N059 18 N059 500m dir=1 vto=-.69 +A10 N068 6A N019 0 0 0 N069 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A11 N061 6A N019 0 0 0 N062 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +C77 7 14 1p +C78 14 18 1p +C79 7 15 1p +C80 15 18 1p +C81 7 16 1p +C82 16 18 1p +G49 N064 6A 14 6A 10 +G50 6A N064 17 6A 10 +A12 0 N056 0 0 0 0 N059 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +.param Rint=1e14/(2.01*PI*fclk) +.model SBUF1 SW(Ron=.1 Roff=1Meg vt=-1 vh=-.2 noiseless) +.model SBUF2 SW(Ron=.1 Roff=1Meg vt=1 vh=-.2 noiseless) +.model YU D(Ron=1k Roff=1T Vfwd=1.53 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=1.3 epsilon=.1 noiseless) +.model N VDMOS(Vto=-140m Kp=14m) +.model P VDMOS(Vto=140m Kp=14m pchan) +.model SPV SW(Ron=720k Roff=10Meg vt=2.8 vh=-.7 noiseless) +.model DPV1 D(Ron=40k Roff=1Meg Vfwd=.26 epsilon=200m ilimit=2u noiseless) +.model DPV2 D(Ron=20k Roff=10Meg Vfwd=1.3 epsilon=200m noiseless) +.ends LTC1068 +* +.subckt LTC1068-25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 +R1 7 N008 200Meg noiseless +R2 N008 18 200Meg noiseless +M1 7 N007 11 11 N temp=27 +M2 18 N007 11 11 P temp=27 +D1 N007 11 YU +D2 11 N007 YD +G3 0 N007 N008 0 1µ +G8 6A N015 8 6A 10 +C2 N014 N013 1p +R5 7 N014 100Meg noiseless +R6 N014 18 100Meg noiseless +G5 N014 0 N014 7 500m dir=1 vto=-1 +G11 0 N014 18 N014 500m dir=1 vto=-1 +M3 7 N016 10 10 N temp=27 +M4 18 N016 10 10 P temp=27 +D3 N016 10 YU +D4 10 N016 YD +G12 0 N016 N014 0 1µ +C3 N016 0 .4f Rpar=1Meg noiseless +G13 6A N020 6A 10 10 +R8 N021 N020 {Rint} noiseless +C4 N022 N021 1p +R9 7 N022 100Meg noiseless +R10 N022 18 100Meg noiseless +G14 N022 0 N022 7 500m dir=1 vto=-1 +G15 0 N022 18 N022 500m dir=1 vto=-1 +M5 7 N023 9 9 N temp=27 +M6 18 N023 9 9 P temp=27 +D5 N023 9 YU +D6 9 N023 YD +G16 0 N023 N022 0 1µ +C5 N007 0 10f Rpar=1Meg noiseless +A2 N013 6A N019 0 0 0 N014 0 OTA g=10m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +S3 N024 7 7 18 SPV +B1 0 N006 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B2 N006 0 I=10u*dnlim(uplim(V(12),V(7)+.21,.1), V(18)-.21, .1)+1n*V(12) +C6 N006 0 .2f Rpar=100K noiseless +C7 12 18 200f +C8 7 12 200f +C9 18 8 200f +C10 N015 6A 100f Rpar=.1 noiseless +C11 N020 6A 100f Rpar=.1 noiseless +R3 7 N027 200Meg noiseless +R7 N027 18 200Meg noiseless +M7 7 N026 2 2 N temp=27 +M8 18 N026 2 2 P temp=27 +D8 N026 2 YU +D9 2 N026 YD +G19 0 N026 N027 0 1µ +R11 N030 N033 {Rint} noiseless +C12 N031 N030 1p +R18 7 N031 100Meg noiseless +R19 N031 18 100Meg noiseless +G25 N031 0 N031 7 500m dir=1 vto=-1 +G26 0 N031 18 N031 500m dir=1 vto=-1 +M9 7 N034 3 3 N temp=27 +M10 18 N034 3 3 P temp=27 +D10 N034 3 YU +D11 3 N034 YD +G27 0 N034 N031 0 1µ +C13 N034 0 .4f Rpar=1Meg noiseless +G28 6A N036 6A 3 10 +C14 N038 N037 1p +R21 7 N038 200Meg noiseless +R22 N038 18 200Meg noiseless +G29 N038 0 N038 7 500m dir=1 vto=-1 +G30 0 N038 18 N038 500m dir=1 vto=-1 +M11 7 N039 4 4 N temp=27 +M12 18 N039 4 4 P temp=27 +D12 N039 4 YU +D13 4 N039 YD +G31 0 N039 N038 0 1µ +C15 N039 0 .4f Rpar=1Meg noiseless +C16 N026 0 10f Rpar=1Meg noiseless +B3 0 N025 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B4 N025 0 I=10u*dnlim(uplim(V(1),V(7)+.21,.1), V(18)-.21, .1)+1n*V(1) +C17 N025 0 .2f Rpar=100K noiseless +C18 1 18 200f +C19 7 1 200f +C20 18 5 200f +C21 N033 6A 100f Rpar=.1 noiseless +C22 N036 6A 100f Rpar=.1 noiseless +R4 N013 N015 {Rint} noiseless +R14 N037 N036 {Rint} noiseless +C23 N024 18 10p +C27 N031 N030 .001f IC=0 Rser=1Meg noiseless +C28 N038 N037 .001f IC=0 Rser=1Meg noiseless +C24 7 6 1p Rpar=10k noiseless +C29 6 18 1p Rpar=10k noiseless +G1 N008 0 N008 7 500m dir=1 vto=-.15 +G2 0 N008 18 N008 500m dir=1 vto=.1 +G4 N027 0 N027 7 500m dir=1 vto=-.69 +G6 0 N027 18 N027 500m dir=1 vto=-.69 +C1 N023 0 .4f Rpar=1Meg noiseless +A3 N021 6A N019 0 0 0 N022 0 OTA g=10m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +A5 N037 6A N019 0 0 0 N038 0 OTA g=10m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A6 N030 6A N019 0 0 0 N031 0 OTA g=10m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +D14 N024 18 DPV1 +R27 7 18 1.36k noiseless +G7 0 6A 6 0 10m +C31 6A 0 100µ Rpar=100 noiseless +C32 7 11 1p +C33 11 18 1p +C34 7 10 1p +C35 10 18 1p +C36 7 9 1p +C37 9 18 1p +C38 7 2 1p +C39 2 18 1p +C40 7 3 1p +C41 3 18 1p +C42 7 4 1p +C43 4 18 1p +C25 N022 N021 .001f IC=0 Rser=1G noiseless +C26 N014 N013 .001f IC=0 Rser=1G noiseless +G10 0 N019 N024 18 10m +C45 N019 0 100µ Rpar=100 noiseless +G18 N015 6A 11 6A 10 +G17 N033 6A 2 6A 10 +G9 6A N033 5 6A 10 +D7 N024 18 DPV2 +A1 0 N006 0 0 0 0 N008 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +A4 0 N025 0 0 0 0 N027 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +R38 N024 18 400k noiseless +R39 7 N043 200Meg noiseless +R40 N043 18 200Meg noiseless +M13 7 N042 22 22 N temp=27 +M14 18 N042 22 22 P temp=27 +D16 N042 22 YU +D17 22 N042 YD +G20 0 N042 N043 0 1µ +R41 N045 N049 {Rint} noiseless +C44 N046 N045 1p +R42 7 N046 100Meg noiseless +R43 N046 18 100Meg noiseless +G21 N046 0 N046 7 500m dir=1 vto=-1 +G22 0 N046 18 N046 500m dir=1 vto=-1 +M15 7 N050 21 21 N temp=27 +M16 18 N050 21 21 P temp=27 +D18 N050 21 YU +D19 21 N050 YD +G23 0 N050 N046 0 1µ +C46 N050 0 .4f Rpar=1Meg noiseless +G24 6A N052 6A 21 10 +C47 N054 N053 1p +R44 7 N054 200Meg noiseless +R45 N054 18 200Meg noiseless +G32 N054 0 N054 7 500m dir=1 vto=-1 +G33 0 N054 18 N054 500m dir=1 vto=-1 +M17 7 N055 20 20 N temp=27 +M18 18 N055 20 20 P temp=27 +D20 N055 20 YU +D21 20 N055 YD +G34 0 N055 N054 0 1µ +C48 N055 0 .4f Rpar=1Meg noiseless +C49 N042 0 10f Rpar=1Meg noiseless +B5 0 N040 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B6 N040 0 I=10u*dnlim(uplim(V(23),V(7)+.21,.1), V(18)-.21, .1)+1n*V(23) +C50 N040 0 .2f Rpar=100K noiseless +C51 23 18 200f +C52 7 23 200f +C53 18 19 200f +C54 N049 6A 100f Rpar=.1 noiseless +C55 N052 6A 100f Rpar=.1 noiseless +R46 N053 N052 {Rint} noiseless +C56 N046 N045 .001f IC=0 Rser=1Meg noiseless +C57 N054 N053 .001f IC=0 Rser=1Meg noiseless +G35 N043 0 N043 7 500m dir=1 vto=-.69 +G36 0 N043 18 N043 500m dir=1 vto=-.69 +A7 N053 6A N019 0 0 0 N054 0 OTA g=10m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A8 N045 6A N019 0 0 0 N046 0 OTA g=10m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +C58 7 22 1p +C59 22 18 1p +C60 7 21 1p +C61 21 18 1p +C62 7 20 1p +C63 20 18 1p +G37 N049 6A 22 6A 10 +G38 6A N049 19 6A 10 +A9 0 N040 0 0 0 0 N043 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +R47 7 N059 200Meg noiseless +R48 N059 18 200Meg noiseless +M19 7 N058 14 14 N temp=27 +M20 18 N058 14 14 P temp=27 +D22 N058 14 YU +D23 14 N058 YD +G39 0 N058 N059 0 1µ +R49 N061 N064 {Rint} noiseless +C64 N062 N061 1p +R50 7 N062 100Meg noiseless +R51 N062 18 100Meg noiseless +G40 N062 0 N062 7 500m dir=1 vto=-1 +G41 0 N062 18 N062 500m dir=1 vto=-1 +M21 7 N065 15 15 N temp=27 +M22 18 N065 15 15 P temp=27 +D24 N065 15 YU +D25 15 N065 YD +G42 0 N065 N062 0 1µ +C65 N065 0 .4f Rpar=1Meg noiseless +G43 6A N067 6A 15 10 +C66 N069 N068 1p +R52 7 N069 200Meg noiseless +R53 N069 18 200Meg noiseless +G44 N069 0 N069 7 500m dir=1 vto=-1 +G45 0 N069 18 N069 500m dir=1 vto=-1 +M23 7 N070 16 16 N temp=27 +M24 18 N070 16 16 P temp=27 +D26 N070 16 YU +D27 16 N070 YD +G46 0 N070 N069 0 1µ +C67 N070 0 .4f Rpar=1Meg noiseless +C68 N058 0 10f Rpar=1Meg noiseless +B7 0 N056 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B8 N056 0 I=10u*dnlim(uplim(V(13),V(7)+.21,.1), V(18)-.21, .1)+1n*V(13) +C69 N056 0 .2f Rpar=100K noiseless +C70 13 18 200f +C71 7 13 200f +C72 18 17 200f +C73 N064 6A 100f Rpar=.1 noiseless +C74 N067 6A 100f Rpar=.1 noiseless +R54 N068 N067 {Rint} noiseless +C75 N062 N061 .001f IC=0 Rser=1Meg noiseless +C76 N069 N068 .001f IC=0 Rser=1Meg noiseless +G47 N059 0 N059 7 500m dir=1 vto=-.69 +G48 0 N059 18 N059 500m dir=1 vto=-.69 +A10 N068 6A N019 0 0 0 N069 0 OTA g=10m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A11 N061 6A N019 0 0 0 N062 0 OTA g=10m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +C77 7 14 1p +C78 14 18 1p +C79 7 15 1p +C80 15 18 1p +C81 7 16 1p +C82 16 18 1p +G49 N064 6A 14 6A 10 +G50 6A N064 17 6A 10 +A12 0 N056 0 0 0 0 N059 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +.param Rint=1e14/(8.06*PI*fclk) +.model SBUF1 SW(Ron=.1 Roff=1Meg vt=-1 vh=-.2 noiseless) +.model SBUF2 SW(Ron=.1 Roff=1Meg vt=1 vh=-.2 noiseless) +.model YU D(Ron=1k Roff=1T Vfwd=1.53 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=1.3 epsilon=.1 noiseless) +.model N VDMOS(Vto=-140m Kp=14m) +.model P VDMOS(Vto=140m Kp=14m pchan) +.model SPV SW(Ron=1Meg Roff=10Meg vt=2.8 vh=-.7 noiseless) +.model DPV1 D(Ron=20k Roff=1Meg Vfwd=.1 epsilon=200m ilimit=2u noiseless) +.model DPV2 D(Ron=20k Roff=10Meg Vfwd=1.5 epsilon=200m noiseless) +.ends LTC1068-25 +* +.subckt LTC1068-50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 +R1 7 N008 200Meg noiseless +R2 N008 18 200Meg noiseless +M1 7 N007 11 11 N temp=27 +M2 18 N007 11 11 P temp=27 +D1 N007 11 YU +D2 11 N007 YD +G3 0 N007 N008 0 1µ +G8 6A N015 8 6A 10 +C2 N014 N013 1p +R5 7 N014 100Meg noiseless +R6 N014 18 100Meg noiseless +G5 N014 0 N014 7 500m dir=1 vto=-1 +G11 0 N014 18 N014 500m dir=1 vto=-1 +M3 7 N016 10 10 N temp=27 +M4 18 N016 10 10 P temp=27 +D3 N016 10 YU +D4 10 N016 YD +G12 0 N016 N014 0 1µ +C3 N016 0 .4f Rpar=1Meg noiseless +G13 6A N020 6A 10 10 +R8 N021 N020 {Rint} noiseless +C4 N022 N021 1p +R9 7 N022 100Meg noiseless +R10 N022 18 100Meg noiseless +G14 N022 0 N022 7 500m dir=1 vto=-1 +G15 0 N022 18 N022 500m dir=1 vto=-1 +M5 7 N023 9 9 N temp=27 +M6 18 N023 9 9 P temp=27 +D5 N023 9 YU +D6 9 N023 YD +G16 0 N023 N022 0 1µ +C5 N007 0 10f Rpar=1Meg noiseless +A2 N013 6A N019 0 0 0 N014 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +S3 N024 7 7 18 SPV +B1 0 N006 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B2 N006 0 I=10u*dnlim(uplim(V(12),V(7)+.21,.1), V(18)-.21, .1)+1n*V(12) +C6 N006 0 .2f Rpar=100K noiseless +C7 12 18 200f +C8 7 12 200f +C9 18 8 200f +C10 N015 6A 100f Rpar=.1 noiseless +C11 N020 6A 100f Rpar=.1 noiseless +R3 7 N027 200Meg noiseless +R7 N027 18 200Meg noiseless +M7 7 N026 2 2 N temp=27 +M8 18 N026 2 2 P temp=27 +D8 N026 2 YU +D9 2 N026 YD +G19 0 N026 N027 0 1µ +R11 N030 N033 {Rint} noiseless +C12 N031 N030 1p +R18 7 N031 100Meg noiseless +R19 N031 18 100Meg noiseless +G25 N031 0 N031 7 500m dir=1 vto=-1 +G26 0 N031 18 N031 500m dir=1 vto=-1 +M9 7 N034 3 3 N temp=27 +M10 18 N034 3 3 P temp=27 +D10 N034 3 YU +D11 3 N034 YD +G27 0 N034 N031 0 1µ +C13 N034 0 .4f Rpar=1Meg noiseless +G28 6A N036 6A 3 10 +C14 N038 N037 1p +R21 7 N038 200Meg noiseless +R22 N038 18 200Meg noiseless +G29 N038 0 N038 7 500m dir=1 vto=-1 +G30 0 N038 18 N038 500m dir=1 vto=-1 +M11 7 N039 4 4 N temp=27 +M12 18 N039 4 4 P temp=27 +D12 N039 4 YU +D13 4 N039 YD +G31 0 N039 N038 0 1µ +C15 N039 0 .4f Rpar=1Meg noiseless +C16 N026 0 10f Rpar=1Meg noiseless +B3 0 N025 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B4 N025 0 I=10u*dnlim(uplim(V(1),V(7)+.21,.1), V(18)-.21, .1)+1n*V(1) +C17 N025 0 .2f Rpar=100K noiseless +C18 1 18 200f +C19 7 1 200f +C20 18 5 200f +C21 N033 6A 100f Rpar=.1 noiseless +C22 N036 6A 100f Rpar=.1 noiseless +R4 N013 N015 {Rint} noiseless +R14 N037 N036 {Rint} noiseless +C23 N024 18 10p +C27 N031 N030 .001f IC=0 Rser=1Meg noiseless +C28 N038 N037 .001f IC=0 Rser=1Meg noiseless +C24 7 6 1p Rpar=11.3k noiseless +C29 6 18 1p Rpar=8.6k noiseless +G1 N008 0 N008 7 500m dir=1 vto=-.15 +G2 0 N008 18 N008 500m dir=1 vto=.1 +G4 N027 0 N027 7 500m dir=1 vto=-.69 +G6 0 N027 18 N027 500m dir=1 vto=-.69 +C1 N023 0 .4f Rpar=1Meg noiseless +A3 N021 6A N019 0 0 0 N022 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +A5 N037 6A N019 0 0 0 N038 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A6 N030 6A N019 0 0 0 N031 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +D14 N024 18 DPV1 +R27 7 18 1.45k noiseless +G7 0 6A 6 0 10m +C31 6A 0 100µ Rpar=100 noiseless +C32 7 11 1p +C33 11 18 1p +C34 7 10 1p +C35 10 18 1p +C36 7 9 1p +C37 9 18 1p +C38 7 2 1p +C39 2 18 1p +C40 7 3 1p +C41 3 18 1p +C42 7 4 1p +C43 4 18 1p +C25 N022 N021 .001f IC=0 Rser=1G noiseless +C26 N014 N013 .001f IC=0 Rser=1G noiseless +G10 0 N019 N024 18 10m +C45 N019 0 100µ Rpar=100 noiseless +G18 N015 6A 11 6A 10 +G17 N033 6A 2 6A 10 +G9 6A N033 5 6A 10 +R38 N024 18 280k noiseless +R39 7 N043 200Meg noiseless +R40 N043 18 200Meg noiseless +M13 7 N042 22 22 N temp=27 +M14 18 N042 22 22 P temp=27 +D16 N042 22 YU +D17 22 N042 YD +G20 0 N042 N043 0 1µ +R41 N045 N049 {Rint} noiseless +C44 N046 N045 1p +R42 7 N046 100Meg noiseless +R43 N046 18 100Meg noiseless +G21 N046 0 N046 7 500m dir=1 vto=-1 +G22 0 N046 18 N046 500m dir=1 vto=-1 +M15 7 N050 21 21 N temp=27 +M16 18 N050 21 21 P temp=27 +D18 N050 21 YU +D19 21 N050 YD +G23 0 N050 N046 0 1µ +C46 N050 0 .4f Rpar=1Meg noiseless +G24 6A N052 6A 21 10 +C47 N054 N053 1p +R44 7 N054 200Meg noiseless +R45 N054 18 200Meg noiseless +G32 N054 0 N054 7 500m dir=1 vto=-1 +G33 0 N054 18 N054 500m dir=1 vto=-1 +M17 7 N055 20 20 N temp=27 +M18 18 N055 20 20 P temp=27 +D20 N055 20 YU +D21 20 N055 YD +G34 0 N055 N054 0 1µ +C48 N055 0 .4f Rpar=1Meg noiseless +C49 N042 0 10f Rpar=1Meg noiseless +B5 0 N040 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B6 N040 0 I=10u*dnlim(uplim(V(23),V(7)+.21,.1), V(18)-.21, .1)+1n*V(23) +C50 N040 0 .2f Rpar=100K noiseless +C51 23 18 200f +C52 7 23 200f +C53 18 19 200f +C54 N049 6A 100f Rpar=.1 noiseless +C55 N052 6A 100f Rpar=.1 noiseless +R46 N053 N052 {Rint} noiseless +C56 N046 N045 .001f IC=0 Rser=1Meg noiseless +C57 N054 N053 .001f IC=0 Rser=1Meg noiseless +G35 N043 0 N043 7 500m dir=1 vto=-.69 +G36 0 N043 18 N043 500m dir=1 vto=-.69 +A7 N053 6A N019 0 0 0 N054 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A8 N045 6A N019 0 0 0 N046 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +C58 7 22 1p +C59 22 18 1p +C60 7 21 1p +C61 21 18 1p +C62 7 20 1p +C63 20 18 1p +G37 N049 6A 22 6A 10 +G38 6A N049 19 6A 10 +R47 7 N059 200Meg noiseless +R48 N059 18 200Meg noiseless +M19 7 N058 14 14 N temp=27 +M20 18 N058 14 14 P temp=27 +D22 N058 14 YU +D23 14 N058 YD +G39 0 N058 N059 0 1µ +R49 N061 N064 {Rint} noiseless +C64 N062 N061 1p +R50 7 N062 100Meg noiseless +R51 N062 18 100Meg noiseless +G40 N062 0 N062 7 500m dir=1 vto=-1 +G41 0 N062 18 N062 500m dir=1 vto=-1 +M21 7 N065 15 15 N temp=27 +M22 18 N065 15 15 P temp=27 +D24 N065 15 YU +D25 15 N065 YD +G42 0 N065 N062 0 1µ +C65 N065 0 .4f Rpar=1Meg noiseless +G43 6A N067 6A 15 10 +C66 N069 N068 1p +R52 7 N069 200Meg noiseless +R53 N069 18 200Meg noiseless +G44 N069 0 N069 7 500m dir=1 vto=-1 +G45 0 N069 18 N069 500m dir=1 vto=-1 +M23 7 N070 16 16 N temp=27 +M24 18 N070 16 16 P temp=27 +D26 N070 16 YU +D27 16 N070 YD +G46 0 N070 N069 0 1µ +C67 N070 0 .4f Rpar=1Meg noiseless +C68 N058 0 10f Rpar=1Meg noiseless +B7 0 N056 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B8 N056 0 I=10u*dnlim(uplim(V(13),V(7)+.21,.1), V(18)-.21, .1)+1n*V(13) +C69 N056 0 .2f Rpar=100K noiseless +C70 13 18 200f +C71 7 13 200f +C72 18 17 200f +C73 N064 6A 100f Rpar=.1 noiseless +C74 N067 6A 100f Rpar=.1 noiseless +R54 N068 N067 {Rint} noiseless +C75 N062 N061 .001f IC=0 Rser=1Meg noiseless +C76 N069 N068 .001f IC=0 Rser=1Meg noiseless +G47 N059 0 N059 7 500m dir=1 vto=-.69 +G48 0 N059 18 N059 500m dir=1 vto=-.69 +A10 N068 6A N019 0 0 0 N069 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A11 N061 6A N019 0 0 0 N062 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +C77 7 14 1p +C78 14 18 1p +C79 7 15 1p +C80 15 18 1p +C81 7 16 1p +C82 16 18 1p +G49 N064 6A 14 6A 10 +G50 6A N064 17 6A 10 +A1 0 N006 0 0 0 0 N008 0 OTA g=179u iout=50.3u Cout=7p Vlow=-1e308 Vhigh=1e308 +A4 0 N025 0 0 0 0 N027 0 OTA g=179u iout=50.3u Cout=7p Vlow=-1e308 Vhigh=1e308 +A9 0 N040 0 0 0 0 N043 0 OTA g=179u iout=50.3u Cout=7p Vlow=-1e308 Vhigh=1e308 +A12 0 N056 0 0 0 0 N059 0 OTA g=179u iout=50.3u Cout=7p Vlow=-1e308 Vhigh=1e308 +.param Rint=1e14/(4.03*PI*fclk) +.model SBUF1 SW(Ron=.1 Roff=1Meg vt=-1 vh=-.2 noiseless) +.model SBUF2 SW(Ron=.1 Roff=1Meg vt=1 vh=-.2 noiseless) +.model YU D(Ron=1k Roff=1T Vfwd=1.53 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=1.3 epsilon=.1 noiseless) +.model N VDMOS(Vto=-140m Kp=14m) +.model P VDMOS(Vto=140m Kp=14m pchan) +.model SPV SW(Ron=720k Roff=10Meg vt=2.8 vh=-.7 noiseless) +.model DPV1 D(Ron=85k Roff=10Meg Vfwd=1 epsilon=200m noiseless) +.ends LTC1068-50 +* +.subckt LTC1068-200 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 +R1 7 N008 200Meg noiseless +R2 N008 18 200Meg noiseless +M1 7 N007 11 11 N temp=27 +M2 18 N007 11 11 P temp=27 +D1 N007 11 YU +D2 11 N007 YD +G3 0 N007 N008 0 1µ +G8 6A N015 8 6A 10 +C2 N014 N013 1p +R5 7 N014 100Meg noiseless +R6 N014 18 100Meg noiseless +G5 N014 0 N014 7 500m dir=1 vto=-1 +G11 0 N014 18 N014 500m dir=1 vto=-1 +M3 7 N016 10 10 N temp=27 +M4 18 N016 10 10 P temp=27 +D3 N016 10 YU +D4 10 N016 YD +G12 0 N016 N014 0 1µ +C3 N016 0 .4f Rpar=1Meg noiseless +G13 6A N020 6A 10 10 +R8 N021 N020 {Rint} noiseless +C4 N022 N021 1p +R9 7 N022 100Meg noiseless +R10 N022 18 100Meg noiseless +G14 N022 0 N022 7 500m dir=1 vto=-1 +G15 0 N022 18 N022 500m dir=1 vto=-1 +M5 7 N023 9 9 N temp=27 +M6 18 N023 9 9 P temp=27 +D5 N023 9 YU +D6 9 N023 YD +G16 0 N023 N022 0 1µ +C5 N007 0 10f Rpar=1Meg noiseless +A2 N013 6A N019 0 0 0 N014 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +S3 N024 7 7 18 SPV +B1 0 N006 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B2 N006 0 I=10u*dnlim(uplim(V(12),V(7)+.21,.1), V(18)-.21, .1)+1n*V(12) +C6 N006 0 .2f Rpar=100K noiseless +C7 12 18 200f +C8 7 12 200f +C9 18 8 200f +C10 N015 6A 100f Rpar=.1 noiseless +C11 N020 6A 100f Rpar=.1 noiseless +R3 7 N027 200Meg noiseless +R7 N027 18 200Meg noiseless +M7 7 N026 2 2 N temp=27 +M8 18 N026 2 2 P temp=27 +D8 N026 2 YU +D9 2 N026 YD +G19 0 N026 N027 0 1µ +R11 N030 N033 {Rint} noiseless +C12 N031 N030 1p +R18 7 N031 100Meg noiseless +R19 N031 18 100Meg noiseless +G25 N031 0 N031 7 500m dir=1 vto=-1 +G26 0 N031 18 N031 500m dir=1 vto=-1 +M9 7 N034 3 3 N temp=27 +M10 18 N034 3 3 P temp=27 +D10 N034 3 YU +D11 3 N034 YD +G27 0 N034 N031 0 1µ +C13 N034 0 .4f Rpar=1Meg noiseless +G28 6A N036 6A 3 10 +C14 N038 N037 1p +R21 7 N038 200Meg noiseless +R22 N038 18 200Meg noiseless +G29 N038 0 N038 7 500m dir=1 vto=-1 +G30 0 N038 18 N038 500m dir=1 vto=-1 +M11 7 N039 4 4 N temp=27 +M12 18 N039 4 4 P temp=27 +D12 N039 4 YU +D13 4 N039 YD +G31 0 N039 N038 0 1µ +C15 N039 0 .4f Rpar=1Meg noiseless +C16 N026 0 10f Rpar=1Meg noiseless +B3 0 N025 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B4 N025 0 I=10u*dnlim(uplim(V(1),V(7)+.21,.1), V(18)-.21, .1)+1n*V(1) +C17 N025 0 .2f Rpar=100K noiseless +C18 1 18 200f +C19 7 1 200f +C20 18 5 200f +C21 N033 6A 100f Rpar=.1 noiseless +C22 N036 6A 100f Rpar=.1 noiseless +R4 N013 N015 {Rint} noiseless +R14 N037 N036 {Rint} noiseless +C23 N024 18 10p +C27 N031 N030 .001f IC=0 Rser=1Meg noiseless +C28 N038 N037 .001f IC=0 Rser=1Meg noiseless +C24 7 6 1p Rpar=10k noiseless +C29 6 18 1p Rpar=10k noiseless +G1 N008 0 N008 7 500m dir=1 vto=-.15 +G2 0 N008 18 N008 500m dir=1 vto=.1 +G4 N027 0 N027 7 500m dir=1 vto=-.69 +G6 0 N027 18 N027 500m dir=1 vto=-.69 +C1 N023 0 .4f Rpar=1Meg noiseless +A3 N021 6A N019 0 0 0 N022 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +A5 N037 6A N019 0 0 0 N038 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A6 N030 6A N019 0 0 0 N031 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +D14 N024 18 DPV1 +R27 7 18 1.334k noiseless +G7 0 6A 6 0 10m +C31 6A 0 100µ Rpar=100 noiseless +C32 7 11 1p +C33 11 18 1p +C34 7 10 1p +C35 10 18 1p +C36 7 9 1p +C37 9 18 1p +C38 7 2 1p +C39 2 18 1p +C40 7 3 1p +C41 3 18 1p +C42 7 4 1p +C43 4 18 1p +C25 N022 N021 .001f IC=0 Rser=1G noiseless +C26 N014 N013 .001f IC=0 Rser=1G noiseless +G10 0 N019 N024 18 10m +C45 N019 0 100µ Rpar=100 noiseless +G18 N015 6A 11 6A 10 +G17 N033 6A 2 6A 10 +G9 6A N033 5 6A 10 +D7 N024 18 DPV2 +A1 0 N006 0 0 0 0 N008 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +A4 0 N025 0 0 0 0 N027 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +R38 N024 18 320k noiseless +R39 7 N043 200Meg noiseless +R40 N043 18 200Meg noiseless +M13 7 N042 22 22 N temp=27 +M14 18 N042 22 22 P temp=27 +D16 N042 22 YU +D17 22 N042 YD +G20 0 N042 N043 0 1µ +R41 N045 N049 {Rint} noiseless +C44 N046 N045 1p +R42 7 N046 100Meg noiseless +R43 N046 18 100Meg noiseless +G21 N046 0 N046 7 500m dir=1 vto=-1 +G22 0 N046 18 N046 500m dir=1 vto=-1 +M15 7 N050 21 21 N temp=27 +M16 18 N050 21 21 P temp=27 +D18 N050 21 YU +D19 21 N050 YD +G23 0 N050 N046 0 1µ +C46 N050 0 .4f Rpar=1Meg noiseless +G24 6A N052 6A 21 10 +C47 N054 N053 1p +R44 7 N054 200Meg noiseless +R45 N054 18 200Meg noiseless +G32 N054 0 N054 7 500m dir=1 vto=-1 +G33 0 N054 18 N054 500m dir=1 vto=-1 +M17 7 N055 20 20 N temp=27 +M18 18 N055 20 20 P temp=27 +D20 N055 20 YU +D21 20 N055 YD +G34 0 N055 N054 0 1µ +C48 N055 0 .4f Rpar=1Meg noiseless +C49 N042 0 10f Rpar=1Meg noiseless +B5 0 N040 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B6 N040 0 I=10u*dnlim(uplim(V(23),V(7)+.21,.1), V(18)-.21, .1)+1n*V(23) +C50 N040 0 .2f Rpar=100K noiseless +C51 23 18 200f +C52 7 23 200f +C53 18 19 200f +C54 N049 6A 100f Rpar=.1 noiseless +C55 N052 6A 100f Rpar=.1 noiseless +R46 N053 N052 {Rint} noiseless +C56 N046 N045 .001f IC=0 Rser=1Meg noiseless +C57 N054 N053 .001f IC=0 Rser=1Meg noiseless +G35 N043 0 N043 7 500m dir=1 vto=-.69 +G36 0 N043 18 N043 500m dir=1 vto=-.69 +A7 N053 6A N019 0 0 0 N054 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A8 N045 6A N019 0 0 0 N046 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +C58 7 22 1p +C59 22 18 1p +C60 7 21 1p +C61 21 18 1p +C62 7 20 1p +C63 20 18 1p +G37 N049 6A 22 6A 10 +G38 6A N049 19 6A 10 +A9 0 N040 0 0 0 0 N043 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +R47 7 N059 200Meg noiseless +R48 N059 18 200Meg noiseless +M19 7 N058 14 14 N temp=27 +M20 18 N058 14 14 P temp=27 +D22 N058 14 YU +D23 14 N058 YD +G39 0 N058 N059 0 1µ +R49 N061 N064 {Rint} noiseless +C64 N062 N061 1p +R50 7 N062 100Meg noiseless +R51 N062 18 100Meg noiseless +G40 N062 0 N062 7 500m dir=1 vto=-1 +G41 0 N062 18 N062 500m dir=1 vto=-1 +M21 7 N065 15 15 N temp=27 +M22 18 N065 15 15 P temp=27 +D24 N065 15 YU +D25 15 N065 YD +G42 0 N065 N062 0 1µ +C65 N065 0 .4f Rpar=1Meg noiseless +G43 6A N067 6A 15 10 +C66 N069 N068 1p +R52 7 N069 200Meg noiseless +R53 N069 18 200Meg noiseless +G44 N069 0 N069 7 500m dir=1 vto=-1 +G45 0 N069 18 N069 500m dir=1 vto=-1 +M23 7 N070 16 16 N temp=27 +M24 18 N070 16 16 P temp=27 +D26 N070 16 YU +D27 16 N070 YD +G46 0 N070 N069 0 1µ +C67 N070 0 .4f Rpar=1Meg noiseless +C68 N058 0 10f Rpar=1Meg noiseless +B7 0 N056 I=10u*dnlim(uplim(V(6A),V(7)+.2,.1), V(18)-.2, .1)+1n*V(6A) +B8 N056 0 I=10u*dnlim(uplim(V(13),V(7)+.21,.1), V(18)-.21, .1)+1n*V(13) +C69 N056 0 .2f Rpar=100K noiseless +C70 13 18 200f +C71 7 13 200f +C72 18 17 200f +C73 N064 6A 100f Rpar=.1 noiseless +C74 N067 6A 100f Rpar=.1 noiseless +R54 N068 N067 {Rint} noiseless +C75 N062 N061 .001f IC=0 Rser=1Meg noiseless +C76 N069 N068 .001f IC=0 Rser=1Meg noiseless +G47 N059 0 N059 7 500m dir=1 vto=-.69 +G48 0 N059 18 N059 500m dir=1 vto=-.69 +A10 N068 6A N019 0 0 0 N069 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A11 N061 6A N019 0 0 0 N062 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +C77 7 14 1p +C78 14 18 1p +C79 7 15 1p +C80 15 18 1p +C81 7 16 1p +C82 16 18 1p +G49 N064 6A 14 6A 10 +G50 6A N064 17 6A 10 +A12 0 N056 0 0 0 0 N059 0 OTA g=179u iout=37u Cout=3.7p Vlow=-1e308 Vhigh=1e308 +.param Rint=1e14/(1.005*PI*fclk) +.model SBUF1 SW(Ron=.1 Roff=1Meg vt=-1 vh=-.2 noiseless) +.model SBUF2 SW(Ron=.1 Roff=1Meg vt=1 vh=-.2 noiseless) +.model YU D(Ron=1k Roff=1T Vfwd=1.53 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=1.3 epsilon=.1 noiseless) +.model N VDMOS(Vto=-140m Kp=14m) +.model P VDMOS(Vto=140m Kp=14m pchan) +.model SPV SW(Ron=900k Roff=10Meg vt=2.8 vh=-.7 noiseless) +.model DPV1 D(Ron=40k Roff=1Meg Vfwd=.16 epsilon=200m ilimit=2u noiseless) +.model DPV2 D(Ron=20k Roff=10Meg Vfwd=1.3 epsilon=200m noiseless) +.ends LTC1068-200 diff --git a/spice/copy/sub/LTC4000-1.sub b/spice/copy/sub/LTC4000-1.sub new file mode 100755 index 0000000..05dac98 Binary files /dev/null and b/spice/copy/sub/LTC4000-1.sub differ diff --git a/spice/copy/sub/LTC4000.sub b/spice/copy/sub/LTC4000.sub new file mode 100755 index 0000000..74f8145 Binary files /dev/null and b/spice/copy/sub/LTC4000.sub differ diff --git a/spice/copy/sub/LTC4009-1.sub b/spice/copy/sub/LTC4009-1.sub new file mode 100755 index 0000000..d839381 Binary files /dev/null and b/spice/copy/sub/LTC4009-1.sub differ diff --git a/spice/copy/sub/LTC4009-2.sub b/spice/copy/sub/LTC4009-2.sub new file mode 100755 index 0000000..cfb58da Binary files /dev/null and b/spice/copy/sub/LTC4009-2.sub differ diff --git a/spice/copy/sub/LTC4009.sub b/spice/copy/sub/LTC4009.sub new file mode 100755 index 0000000..19b864b Binary files /dev/null and b/spice/copy/sub/LTC4009.sub differ diff --git a/spice/copy/sub/LTC4020.sub b/spice/copy/sub/LTC4020.sub new file mode 100755 index 0000000..75e4f68 Binary files /dev/null and b/spice/copy/sub/LTC4020.sub differ diff --git a/spice/copy/sub/LTC4053-4.2.sub b/spice/copy/sub/LTC4053-4.2.sub new file mode 100755 index 0000000..9e33809 Binary files /dev/null and b/spice/copy/sub/LTC4053-4.2.sub differ diff --git a/spice/copy/sub/LTC4054-4.2.sub b/spice/copy/sub/LTC4054-4.2.sub new file mode 100755 index 0000000..a25f5cd Binary files /dev/null and b/spice/copy/sub/LTC4054-4.2.sub differ diff --git a/spice/copy/sub/LTC4054L-4.2.sub b/spice/copy/sub/LTC4054L-4.2.sub new file mode 100755 index 0000000..b082e30 Binary files /dev/null and b/spice/copy/sub/LTC4054L-4.2.sub differ diff --git a/spice/copy/sub/LTC4054X-4.2.sub b/spice/copy/sub/LTC4054X-4.2.sub new file mode 100755 index 0000000..a0ef5ca Binary files /dev/null and b/spice/copy/sub/LTC4054X-4.2.sub differ diff --git a/spice/copy/sub/LTC4065.sub b/spice/copy/sub/LTC4065.sub new file mode 100755 index 0000000..3c52782 Binary files /dev/null and b/spice/copy/sub/LTC4065.sub differ diff --git a/spice/copy/sub/LTC4070.sub b/spice/copy/sub/LTC4070.sub new file mode 100755 index 0000000..98beada Binary files /dev/null and b/spice/copy/sub/LTC4070.sub differ diff --git a/spice/copy/sub/LTC4071.sub b/spice/copy/sub/LTC4071.sub new file mode 100755 index 0000000..431d23c Binary files /dev/null and b/spice/copy/sub/LTC4071.sub differ diff --git a/spice/copy/sub/LTC4077.sub b/spice/copy/sub/LTC4077.sub new file mode 100755 index 0000000..81447f5 Binary files /dev/null and b/spice/copy/sub/LTC4077.sub differ diff --git a/spice/copy/sub/LTC4079.sub b/spice/copy/sub/LTC4079.sub new file mode 100755 index 0000000..a03969b Binary files /dev/null and b/spice/copy/sub/LTC4079.sub differ diff --git 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a/spice/copy/sub/LTC4449.sub b/spice/copy/sub/LTC4449.sub new file mode 100755 index 0000000..2c646ab Binary files /dev/null and b/spice/copy/sub/LTC4449.sub differ diff --git a/spice/copy/sub/LTC5.lib b/spice/copy/sub/LTC5.lib new file mode 100755 index 0000000..30d0e93 --- /dev/null +++ b/spice/copy/sub/LTC5.lib @@ -0,0 +1,2200 @@ +* Copyright © Linear Technology Corp. 12/20/06. All rights reserved. + +.subckt LT6000 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=24.7f ink=22 +B1 0 X0 I=10u*dnlim(uplim(V(1),V(3)+.15,.1), V(4)-.15, .1)+1n*V(1)-90.33n +B2 X0 0 I=10u*dnlim(uplim(V(2),V(3)+16,.1), V(4)-.16, .1)+1n*V(2) +C10 X0 0 500f Rpar=100K noiseless +M1 5 N008 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 N008 4 DLIMN1 +M2 5 VP 3 3 PI temp=27 +D8 3 VP DLIMP +C3 3 VP 10p Rser=400k noiseless +A3 N005 N006 4 4 4 4 VP 4 OTA g=200n ref=-1.453 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C12 N008 4 100f Rser=250k noiseless +D6 N008 4 DLIMN2 +A4 0 X0 0 0 0 0 X1 0 OTA g=1m linear en=75n enk=.44 Vhigh=1e308 Vlow=-1e308 +C16 N006 5 6p +A5 X1 0 N005 N005 N005 N005 N006 N005 OTA g=2.3u asym isource=130n isink=-90n Vhigh=1e308 Vlow=-1e308 +D12 1 3 DPROT +D13 2 3 DPROT +G1 4 N008 N006 N005 14n +D9 N006 N005 DLIM +C14 VP 5 400f +B3 VP 4 I=2n*V(VP,5)/dnlim(V(3,4),2,.1) +C7 3 1 2.5p Rser=2k Rpar=7G noiseless +C13 3 4 1000p +C15 VP N008 1p Rser=250k noiseless +S1 N006 N005 0 N004 SHUT +S2 3 VP 0 N004 SHUT +S3 N008 4 0 N004 SHUT +C1 X1 0 100p Rpar=1k noiseless +C21 N004 0 12p +C17 3 6 100f Rpar=7Meg noiseless +G2 0 N005 4 0 .5m +G4 0 N005 3 0 .5m +C18 N005 0 200p Rpar=1K noiseless +C4 3 2 2.5p Rser=2k Rpar=7G noiseless +C6 1 4 2.5p Rser=2k Rpar=7G noiseless +C8 2 4 2.5p Rser=2k Rpar=7G noiseless +D1 2 1 DIN +S5 1 3 N004 0 SBIAS +S6 2 3 N004 0 SBIAS +S7 0 N004 N005 6 SHUTI +D2 4 6 DPROT +A6 4 3 0 0 0 0 N004 0 OTA g=60n iout=80n Vlow=-1e308 Vhigh=1e308 +.model DIN D(Ron=1k Roff=25Meg Vfwd=1.5 epsilon=.1 Vrev=1.5 revepsilon=.1 noiseless) +.model DPROT D(Ron=1k Roff=24G Vfwd=1 epsilon=10m noiseless) +.model SBIAS SW(level=2 Ron=50Meg Roff=100G vt=0.5 vh=-.1 ilimit 2n vser=.6 ) +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.3 noiseless) +.model SHUTI SW(Ron=100k Roff=20Meg vt=.2 vh=-50m noiseless) +.model NI VDMOS(Vto=300m kp=15m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=3 Vrev=1 epsilon=10m revepsilon=10m noiseless) +.model DSLIM D(Ron=100 Roff=1G Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.2 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=19.4n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.ends LT6000 +* +.subckt LT6002 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=24.7f ink=22 +B1 0 X0 I=10u*dnlim(uplim(V(1),V(3)+.15,.1), V(4)-.15, .1)+1n*V(1)-90.33n +B2 X0 0 I=10u*dnlim(uplim(V(2),V(3)+16,.1), V(4)-.16, .1)+1n*V(2) +C10 X0 0 500f Rpar=100K noiseless +M1 5 N008 4 4 NI temp=27 +C2 3 5 1p Rpar=1g noiseless +D5 N008 4 DLIMN1 +M2 5 VP 3 3 PI temp=27 +D8 3 VP DLIMP +C3 3 VP 10p Rser=400k noiseless +A3 N005 N006 4 4 4 4 VP 4 OTA g=200n ref=-1.453 linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=1g noiseless +C12 N008 4 100f Rser=250k noiseless +D6 N008 4 DLIMN2 +A4 0 X0 0 0 0 0 X1 0 OTA g=1m linear en=75n enk=.44 Vhigh=1e308 Vlow=-1e308 +C16 N006 5 6p +A5 X1 0 N005 N005 N005 N005 N006 N005 OTA g=2.3u asym isource=130n isink=-90n Vhigh=1e308 Vlow=-1e308 +D12 1 3 DPROT +D13 2 3 DPROT +G1 4 N008 N006 N005 14n +D9 N006 N005 DLIM +C14 VP 5 400f +B3 VP 4 I=2n*V(VP,5)/dnlim(V(3,4),2,.1) +C7 3 1 2.5p Rser=2k Rpar=7G noiseless +C13 3 4 1000p +C15 VP N008 1p Rser=250k noiseless +S1 N006 N005 0 N004 SHUT +S2 3 VP 0 N004 SHUT +S3 N008 4 0 N004 SHUT +C1 X1 0 100p Rpar=1k noiseless +C21 N004 0 12p Rpar=20Meg noiseless +G2 0 N005 4 0 .5m +G4 0 N005 3 0 .5m +C18 N005 0 200p Rpar=1K noiseless +C4 3 2 2.5p Rser=2k Rpar=7G noiseless +C6 1 4 2.5p Rser=2k Rpar=7G noiseless +C8 2 4 2.5p Rser=2k Rpar=7G noiseless +D1 2 1 DIN +S5 1 3 N004 0 SBIAS +S6 2 3 N004 0 SBIAS +D2 4 3 DPROT +A6 4 3 0 0 0 0 N004 0 OTA g=60n iout=80n Vlow=-1e308 Vhigh=1e308 +.model DIN D(Ron=1k Roff=25Meg Vfwd=1.5 epsilon=.1 Vrev=1.5 revepsilon=.1 noiseless) +.model DPROT D(Ron=1k Roff=24G Vfwd=1 epsilon=10m noiseless) +.model SBIAS SW(level=2 Ron=50Meg Roff=100G vt=0.5 vh=-.1 ilimit 2n vser=.6 ) +.model SHUT SW(Ron=1 Roff=100G vt=-1 vh=-.3 noiseless) +.model NI VDMOS(Vto=300m kp=15m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan is=0) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=3 Vrev=1 epsilon=10m revepsilon=10m noiseless) +.model DSLIM D(Ron=100 Roff=1G Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.2 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=19.4n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1 Vrev=-.3 epsilon=10m revepsilon=10m noiseless) +.ends LT6002 +* +.subckt LT6003 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=11.3f ink=12.8 +B1 0 X0 I=10u*dnlim(uplim(V(1),V(3)+.15,.1), V(4)-.15, .1)+1n*V(1)-1.89n +B2 X0 0 I=10u*dnlim(uplim(V(2),V(3)+16,.1), V(4)-.16, .1)+1n*V(2) +C10 X0 0 500f Rpar=100K noiseless +M1 5 N008 4 4 NI temp=27 +C2 3 5 1p Rpar=10G noiseless +D5 N008 4 DLIMN1 +M2 5 VP 3 3 PI temp=27 +C3 3 VP 70p Rser=100k noiseless +C11 5 4 1p Rpar=10G noiseless +C12 N008 4 1p Rser=250k noiseless +A4 0 X0 0 0 0 0 N004 0 OTA g=1u linear en=324.6n enk=.23 Vhigh=1e308 Vlow=-1e308 +C16 N006 5 220p +A5 N004 0 N005 N005 N005 N005 N006 N005 OTA g=4u iout=.29u Vhigh=1e308 Vlow=-1e308 +G1 4 N008 N006 N005 10n +D9 N006 N005 DLIM +B3 VP 4 I=2n*V(VP,5)/dnlim(V(3,4),1.7,.1) +C7 3 1 3p Rpar=4T noiseless +C13 3 4 1000p +C1 N004 0 60p Rpar=1Meg noiseless +G2 0 N005 4 0 .5m +G4 0 N005 3 0 .5m +C18 N005 0 500p Rpar=1k noiseless +D2 N008 4 DLIMN2 +C4 3 2 3p Rpar=4T noiseless +C5 1 4 3p Rpar=4T noiseless +C6 2 4 3p Rpar=4T noiseless +R3 2 1 10G noiseless +D1 2 4 DBIAS +D3 1 4 DBIAS +A2 N005 N006 4 4 4 4 VP 4 OTA g=350n ref=-.057 linear vlow=-1e308 vhigh=1e308 +D4 3 VP DLIMP1 +D6 3 VP DLIMP2 +D7 3 4 DP +C8 VP 5 400f +.model DLIMN1 D(Ron=20k Roff=1g Vfwd=1.2 Vrev=-280m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=600Meg Roff=2G Vfwd=200m epsilon=5m ilimit=150p noiseless) +.model DLIMP1 D(Ron=100k Roff=500Meg Vfwd=1 Vrev=-305m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(Ron=100Meg Roff=10g Vfwd=100m epsilon=10m ilimit=2.5n noiseless) +.model DP D(Ron=10k Roff=1G Vfwd=.7 epsilon=.1 ilimit=584n noiseless) +.model DBIAS D(Ron=10G Roff=4T epsilon=.3 ilimit=5p noiseless) +.model NI VDMOS(Vto=300m kp=20m) +.model PI VDMOS(Vto=-300m Kp=20m pchan) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=4 Vrev=2.5 epsilon=10m revepsilon=10m noiseless) +.ends LT6003 +* +.subckt LT6402-12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C1 INAMI INAPI 1f Rpar=100Meg noiseless +B1 0 N002 I=10u*dnlim(uplim(V(INAPI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INAPI) +B2 N002 0 I=10u*dnlim(uplim(V(INAMI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INAMI) +C3 N002 0 .1f Rpar=100K noiseless +R5 3 N009 100Meg noiseless +R6 N009 4 100Meg noiseless +M1 3 N007 5 5 N temp=27 +M2 4 N012 5 5 P temp=27 +C12 3 5 .4p +D6 N007 5 Y +D7 5 N012 Y +A3 N006 0 N009 N009 N009 N009 N007 N009 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A4 N006 0 N009 N009 N009 N012 N009 N009 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +C13 5 4 .4p Rpar=100Meg noiseless +G3 N009 0 N009 3 100m dir=1 vto=-1.15 +G4 0 N009 4 N009 100m dir=1 vto=0.01 +R2 INAMI 14 100 +R3 INAPI 16 100 +C4 INCMI 2 1f Rpar=100Meg noiseless +B3 0 N015 I=10u*dnlim(uplim(V(2),V(1)-1.3,.1), V(12)+1, .1)+1n*V(2) +B4 N015 0 I=10u*dnlim(uplim(V(INCMI),V(1)-1.29,.1), V(12)+.99, .1)+1n*V(INCMI) +C9 1 INCMI .15p Rpar=20Meg noiseless +C10 N015 0 1f Rpar=100K noiseless +R7 1 N016 100Meg noiseless +R8 N016 12 100Meg noiseless +C11 INCMI 12 .15p Rpar=20Meg noiseless +C14 1 2 .15p Rpar=20Meg noiseless +C15 2 12 .15p Rpar=20Meg noiseless +A7 0 N015 N006 0 0 0 N016 0 OTA g=1m iout=300u Cout=1.32p en=2n Vhigh=1e308 Vlow=-1e308 +G5 N016 0 N016 1 100m dir=1 vto=-1 +G6 0 N016 12 N016 100m dir=1 vto=0 +S2 3 4 N006 0 swPow +R1 INAPI INCMI 200 +A8 11 12 0 0 0 N006 0 0 SCHMITT Vt=.8 Vh=10m trise=40n tfall=500n Vlow=0 Vhigh=1 td=70n +R9 5 6 50 +C18 INBPI INBMI .1p Rpar=100Meg noiseless +B5 0 N022 I=10u*dnlim(uplim(V(INBMI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INBMI) +B6 N022 0 I=10u*dnlim(uplim(V(INBPI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INBPI) +C20 N022 0 .1f Rpar=100K noiseless +R10 10 N027 100Meg noiseless +R11 N027 9 100Meg noiseless +M3 10 N026 8 8 N temp=27 +M4 9 N029 8 8 P temp=27 +C25 10 8 .4p +D9 N026 8 Y +D10 8 N029 Y +A9 N006 0 N027 N027 N027 N027 N026 N027 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A10 N006 0 N027 N027 N027 N029 N027 N027 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +G9 N027 0 N027 10 100m dir=1 vto=-1.15 +G10 0 N027 9 N027 100m dir=1 vto=0.01 +R12 INBPI 15 100 +R13 INBMI 13 100 +C27 7 9 14p Rpar=1T noiseless +R16 8 7 50 +R15 INCMI INBMI 200 +C17 6 4 14p Rpar=1T noiseless +C28 6 7 14p Rpar=1T noiseless +C8 8 9 .4p Rpar=100Meg noiseless +A15 0 N004 0 0 0 0 N009 0 OTA g=1m iout=25u Cout=110f Vlow=-1e308 Vhigh=1e308 +A11 0 N024 0 0 0 0 N027 0 OTA g=1m iout=25u Cout=110f Vlow=-1e308 Vhigh=1e308 +R18 12 11 5Meg noiseless +S3 10 9 N006 0 swPow +S1 1 12 N006 0 swPow +S6 2 12 N006 0 swBias +G1 0 N003 N005 0 1m +C24 N003 0 110f Rpar=1k noiseless +G8 0 N004 N003 0 1m +C26 N004 0 110f Rpar=1k noiseless +C2 3 INAMI .15p Rpar=20Meg Rser=2k noiseless +C32 14 4 .5p Rser=5k noiseless +C5 INAMI 4 .15p Rpar=20Meg Rser=2k noiseless +C6 3 INAPI .15p Rpar=20Meg Rser=2k noiseless +C7 INAPI 4 .15p Rpar=20Meg Rser=2k noiseless +C31 16 4 .5p Rser=5k noiseless +C33 15 9 .5p Rser=5k noiseless +C34 13 9 .5p Rser=5k noiseless +C19 10 INBPI .15p Rpar=20Meg Rser=2k noiseless +C21 10 INBMI .15p Rpar=20Meg Rser=2k noiseless +C22 INBPI 9 .15p Rpar=20Meg Rser=2k noiseless +C23 INBMI 9 .15p Rpar=20Meg Rser=2k noiseless +R4 5 INAMI 200 +R14 8 INBPI 200 +C16 N019 INCMI 200f Rpar=10 noiseless +G2 0 N023 N025 0 1m +C29 N023 0 110f Rpar=1k noiseless +G11 0 N024 N023 0 1m +C30 N024 0 110f Rpar=1k noiseless +G7 N019 INCMI N016 12 100m +S4 12 N019 N006 0 swShut +C35 N019 12 1p +A1 0 N002 N006 0 0 0 N005 0 OTA g=1m linear en=2.1n+freq**2.52/(1.6e29+2.8e11*(freq-2e8)**2.2) Rout=1k Cout=150f Vlow=-64m Vhigh=64m +A2 0 N022 N006 0 0 0 N025 0 OTA g=1m linear en=2.1n+freq**2.52/(1.6e29+2.8e11*(freq-2e8)**2.2) Rout=1k Cout=150f Vlow=-64m Vhigh=64m +.model Y D(Ron=100 Roff=1T Vfwd=.7 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=100m) +.model P VDMOS(Vto=150m Kp=100m pchan) +.model swPow SW(level=2 Ron=50 Roff=76.5k vt=.5 vh=-50m ilimit=9.25m noiseless) +.model swBias SW(level=2 Ron=10k Roff=100G vt=.5 vh=-50m ilimit=5u noiseless) +.model swShut SW(level=2 Ron=1 Roff=100Meg vt=.5 vh=-.1 noiseless) +.ends LT6402-12 +* +.subckt LT6402-20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C1 INAMI INAPI 1f Rpar=100Meg noiseless +B1 0 N002 I=10u*dnlim(uplim(V(INAPI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INAPI) +B2 N002 0 I=10u*dnlim(uplim(V(INAMI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INAMI) +C3 N002 0 .1f Rpar=100K noiseless +R5 3 N009 100Meg noiseless +R6 N009 4 100Meg noiseless +M1 3 N007 5 5 N temp=27 +M2 4 N012 5 5 P temp=27 +C12 3 5 .4p +D6 N007 5 Y +D7 5 N012 Y +A3 N006 0 N009 N009 N009 N009 N007 N009 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A4 N006 0 N009 N009 N009 N012 N009 N009 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +C13 5 4 .4p Rpar=100Meg noiseless +G3 N009 0 N009 3 100m dir=1 vto=-1.15 +G4 0 N009 4 N009 100m dir=1 vto=0.01 +R2 INAMI 14 100 +R3 INAPI 16 100 +C4 INCMI 2 1f Rpar=100Meg noiseless +B3 0 N015 I=10u*dnlim(uplim(V(2),V(1)-1.3,.1), V(12)+1, .1)+1n*V(2) +B4 N015 0 I=10u*dnlim(uplim(V(INCMI),V(1)-1.29,.1), V(12)+.99, .1)+1n*V(INCMI) +C9 1 INCMI .15p Rpar=20Meg noiseless +C10 N015 0 1f Rpar=100K noiseless +R7 1 N016 100Meg noiseless +R8 N016 12 100Meg noiseless +C11 INCMI 12 .15p Rpar=20Meg noiseless +C14 1 2 .15p Rpar=20Meg noiseless +C15 2 12 .15p Rpar=20Meg noiseless +A7 0 N015 N006 0 0 0 N016 0 OTA g=1m iout=300u Cout=1.32p en=2n Vhigh=1e308 Vlow=-1e308 +G5 N016 0 N016 1 100m dir=1 vto=-1 +G6 0 N016 12 N016 100m dir=1 vto=0 +S2 3 4 N006 0 swPow +R1 INAPI INCMI 500 +A8 11 12 0 0 0 N006 0 0 SCHMITT Vt=.8 Vh=10m trise=40n tfall=500n Vlow=0 Vhigh=1 td=70n +R9 5 6 50 +C18 INBPI INBMI .1p Rpar=100Meg noiseless +B5 0 N022 I=10u*dnlim(uplim(V(INBMI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INBMI) +B6 N022 0 I=10u*dnlim(uplim(V(INBPI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INBPI) +C20 N022 0 .1f Rpar=100K noiseless +R10 10 N027 100Meg noiseless +R11 N027 9 100Meg noiseless +M3 10 N026 8 8 N temp=27 +M4 9 N029 8 8 P temp=27 +C25 10 8 .4p +D9 N026 8 Y +D10 8 N029 Y +A9 N006 0 N027 N027 N027 N027 N026 N027 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A10 N006 0 N027 N027 N027 N029 N027 N027 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +G9 N027 0 N027 10 100m dir=1 vto=-1.15 +G10 0 N027 9 N027 100m dir=1 vto=0.01 +R12 INBPI 15 100 +R13 INBMI 13 100 +C27 7 9 14p Rpar=1T noiseless +R16 8 7 50 +R15 INCMI INBMI 500 +C17 6 4 14p Rpar=1T noiseless +C28 6 7 14p Rpar=1T noiseless +C8 8 9 .4p Rpar=100Meg noiseless +A15 0 N004 0 0 0 0 N009 0 OTA g=1m iout=13u Cout=55f Vlow=-1e308 Vhigh=1e308 +A11 0 N024 0 0 0 0 N027 0 OTA g=1m iout=13u Cout=55f Vlow=-1e308 Vhigh=1e308 +R18 12 11 5Meg noiseless +S3 10 9 N006 0 swPow +S1 1 12 N006 0 swPow +S6 2 12 N006 0 swBias +G1 0 N003 N005 0 1m +C24 N003 0 110f Rpar=1k noiseless +G8 0 N004 N003 0 1m +C26 N004 0 110f Rpar=1k noiseless +C2 3 INAMI .15p Rpar=20Meg Rser=2k noiseless +C32 14 4 .5p Rser=5k noiseless +C5 INAMI 4 .15p Rpar=20Meg Rser=2k noiseless +C6 3 INAPI .15p Rpar=20Meg Rser=2k noiseless +C7 INAPI 4 .15p Rpar=20Meg Rser=2k noiseless +C31 16 4 .5p Rser=5k noiseless +C33 15 9 .5p Rser=5k noiseless +C34 13 9 .5p Rser=5k noiseless +C19 10 INBPI .15p Rpar=20Meg Rser=2k noiseless +C21 10 INBMI .15p Rpar=20Meg Rser=2k noiseless +C22 INBPI 9 .15p Rpar=20Meg Rser=2k noiseless +C23 INBMI 9 .15p Rpar=20Meg Rser=2k noiseless +R4 5 INAMI 500 +R14 8 INBPI 500 +C16 N019 INCMI 200f Rpar=10 noiseless +G2 0 N023 N025 0 1m +C29 N023 0 110f Rpar=1k noiseless +G11 0 N024 N023 0 1m +C30 N024 0 110f Rpar=1k noiseless +G7 N019 INCMI N016 12 100m +S4 12 N019 N006 0 swShut +C35 N019 12 1p +A1 0 N002 N006 0 0 0 N005 0 OTA g=1m linear en=1.7n+freq**2.52/(1.8e29+4e11*(freq-2e8)**2.2) Rout=1k Cout=150f Vlow=-64m Vhigh=64m +A2 0 N022 N006 0 0 0 N025 0 OTA g=1m linear en=1.7n+freq**2.52/(1.8e29+4e11*(freq-2e8)**2.2) Rout=1k Cout=150f Vlow=-64m Vhigh=64m +.model Y D(Ron=100 Roff=1T Vfwd=.7 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=100m) +.model P VDMOS(Vto=150m Kp=100m pchan) +.model swPow SW(level=2 Ron=50 Roff=76.5k vt=.5 vh=-50m ilimit=9.25m noiseless) +.model swBias SW(level=2 Ron=10k Roff=100G vt=.5 vh=-50m ilimit=5u noiseless) +.model swShut SW(level=2 Ron=1 Roff=100Meg vt=.5 vh=-.1 noiseless) +.ends LT6402-20 +* +.subckt LT6402-6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C1 INAMI INAPI 1f Rpar=100Meg noiseless +B1 0 N002 I=10u*dnlim(uplim(V(INAPI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INAPI) +B2 N002 0 I=10u*dnlim(uplim(V(INAMI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INAMI) +C3 N002 0 .1f Rpar=100K noiseless +R5 3 N009 100Meg noiseless +R6 N009 4 100Meg noiseless +M1 3 N007 5 5 N temp=27 +M2 4 N012 5 5 P temp=27 +C12 3 5 .4p +D6 N007 5 Y +D7 5 N012 Y +A3 N006 0 N009 N009 N009 N009 N007 N009 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A4 N006 0 N009 N009 N009 N012 N009 N009 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +C13 5 4 .4p Rpar=100Meg noiseless +G3 N009 0 N009 3 100m dir=1 vto=-1.15 +G4 0 N009 4 N009 100m dir=1 vto=0.01 +R2 INAMI 14 200 +R3 INAPI 16 200 +C4 INCMI 2 1f Rpar=100Meg noiseless +B3 0 N015 I=10u*dnlim(uplim(V(2),V(1)-1.3,.1), V(12)+1, .1)+1n*V(2) +B4 N015 0 I=10u*dnlim(uplim(V(INCMI),V(1)-1.29,.1), V(12)+.99, .1)+1n*V(INCMI) +C9 1 INCMI .15p Rpar=20Meg noiseless +C10 N015 0 1f Rpar=100K noiseless +R7 1 N016 100Meg noiseless +R8 N016 12 100Meg noiseless +C11 INCMI 12 .15p Rpar=20Meg noiseless +C14 1 2 .15p Rpar=20Meg noiseless +C15 2 12 .15p Rpar=20Meg noiseless +A7 0 N015 N006 0 0 0 N016 0 OTA g=1m iout=300u Cout=1.32p en=2n Vhigh=1e308 Vlow=-1e308 +G5 N016 0 N016 1 100m dir=1 vto=-1 +G6 0 N016 12 N016 100m dir=1 vto=0 +S2 3 4 N006 0 swPow +R1 INAPI INCMI 200 +A8 11 12 0 0 0 N006 0 0 SCHMITT Vt=.8 Vh=10m trise=40n tfall=500n Vlow=0 Vhigh=1 td=70n +R9 5 6 50 +C18 INBPI INBMI .1p Rpar=100Meg noiseless +B5 0 N022 I=10u*dnlim(uplim(V(INBMI),V(3)+.2,.1), V(4)-.2, .1)+1n*V(INBMI) +B6 N022 0 I=10u*dnlim(uplim(V(INBPI),V(3)+.21,.1), V(4)-.21, .1)+1n*V(INBPI) +C20 N022 0 .1f Rpar=100K noiseless +R10 10 N027 100Meg noiseless +R11 N027 9 100Meg noiseless +M3 10 N026 8 8 N temp=27 +M4 9 N029 8 8 P temp=27 +C25 10 8 .4p +D9 N026 8 Y +D10 8 N029 Y +A9 N006 0 N027 N027 N027 N027 N026 N027 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=1k Cout=1p +A10 N006 0 N027 N027 N027 N029 N027 N027 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=1k Cout=1p +G9 N027 0 N027 10 100m dir=1 vto=-1.15 +G10 0 N027 9 N027 100m dir=1 vto=0.01 +R12 INBPI 15 200 +R13 INBMI 13 200 +C27 7 9 14p Rpar=1T noiseless +R16 8 7 50 +R15 INCMI INBMI 200 +C17 6 4 14p Rpar=1T noiseless +C28 6 7 14p Rpar=1T noiseless +C8 8 9 .4p Rpar=100Meg noiseless +A15 0 N004 0 0 0 0 N009 0 OTA g=1m iout=38u Cout=150f Vlow=-1e308 Vhigh=1e308 +A11 0 N024 0 0 0 0 N027 0 OTA g=1m iout=38u Cout=150f Vlow=-1e308 Vhigh=1e308 +R18 12 11 5Meg noiseless +S3 10 9 N006 0 swPow +S1 1 12 N006 0 swPow +S6 2 12 N006 0 swBias +G1 0 N003 N005 0 1m +C24 N003 0 110f Rpar=1k noiseless +G8 0 N004 N003 0 1m +C26 N004 0 110f Rpar=1k noiseless +C2 3 INAMI .15p Rpar=20Meg Rser=2k noiseless +C32 14 4 .5p Rser=5k noiseless +C5 INAMI 4 .15p Rpar=20Meg Rser=2k noiseless +C6 3 INAPI .15p Rpar=20Meg Rser=2k noiseless +C7 INAPI 4 .15p Rpar=20Meg Rser=2k noiseless +C31 16 4 .5p Rser=5k noiseless +C33 15 9 .5p Rser=5k noiseless +C34 13 9 .5p Rser=5k noiseless +C19 10 INBPI .15p Rpar=20Meg Rser=2k noiseless +C21 10 INBMI .15p Rpar=20Meg Rser=2k noiseless +C22 INBPI 9 .15p Rpar=20Meg Rser=2k noiseless +C23 INBMI 9 .15p Rpar=20Meg Rser=2k noiseless +R4 5 INAMI 200 +R14 8 INBPI 200 +C16 N019 INCMI 200f Rpar=10 noiseless +A1 0 N002 N006 0 0 0 N005 0 OTA g=1m linear en=2n+freq**2.5/(5e28+9e5*(freq-2e8)**2.8) Rout=1k Cout=150f Vlow=-64m Vhigh=64m +A2 0 N022 N006 0 0 0 N025 0 OTA g=1m linear en=2n+freq**2.5/(5e28+9e5*(freq-2e8)**2.8) Rout=1k Cout=150f Vlow=-64m Vhigh=64m +G2 0 N023 N025 0 1m +C29 N023 0 110f Rpar=1k noiseless +G11 0 N024 N023 0 1m +C30 N024 0 110f Rpar=1k noiseless +G7 N019 INCMI N016 12 100m +S4 12 N019 N006 0 swShut +C35 N019 12 1p +.model Y D(Ron=100 Roff=1T Vfwd=.7 epsilon=.1 noiseless) +.model N VDMOS(Vto=-150m Kp=100m) +.model P VDMOS(Vto=150m Kp=100m pchan) +.model swPow SW(level=2 Ron=50 Roff=76.5k vt=.5 vh=-50m ilimit=9.25m noiseless) +.model swBias SW(level=2 Ron=10k Roff=100G vt=.5 vh=-50m ilimit=5u noiseless) +.model swShut SW(level=2 Ron=1 Roff=100Meg vt=.5 vh=-.1 noiseless) +.ends LT6402-6 +* +.subckt LT6552 1 2 3 4 5 6 7 8 +B2 N004 0 I=10u*dnlim(uplim(V(8),V(7)-1.91,.1), V(4)-.21, .1)+1n*V(8) +C10 N004 0 .1f Rpar=100K noiseless +M1 6 N015 4 4 NI temp=27 +C2 7 6 1p Rpar=100Meg noiseless +D5 N015 4 DLIMN +M2 6 N010 7 7 PI temp=27 +D8 7 N010 DLIMP +A3 N011 N012 4 4 4 4 N010 4 OTA g=100n ref=-70m linear vlow=-1e308 vhigh=1e308 +C11 6 4 1p Rpar=100Meg noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=51.3n enk=1.5k Vlow=-1.8 Vhigh=1.8 +A5 N006 0 N011 N011 N011 N011 N012 N011 OTA g=6.8u linear Vhigh=1e308 Vlow=-1e308 +G1 4 N015 N012 N011 200n +D9 N012 N011 DLIM +C13 7 4 1000p Rpar=18.28k noiseless +C1 N005 0 3p Rpar=1k noiseless +G2 0 N011 4 0 .5m +G4 0 N011 7 0 .5m +C18 N011 0 200p Rpar=1K noiseless +A1 2 3 0 0 0 0 0 0 OTA g=0 in=661f ink=1.22k +C8 N010 6 .1f Rser=40Meg noiseless +C9 6 N015 .1f Rser=40Meg noiseless +C3 7 N010 40f Rser=20Meg noiseless +C12 N015 4 40f Rser=20Meg noiseless +C14 N012 6 13f Rser=50k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(7)-1.9,.1), V(4)-.2, .1)+1n*V(1)-492p +G3 0 N006 N005 0 1m +C15 N006 0 200f Rpar=1k noiseless +S1 N007 7 N008 0 SBIAS +D1 2 7 DESD +D2 3 7 DESD +D4 1 7 DESD +D6 8 7 DESD +C4 7 2 3.5p Rser=100 Rpar=1G noiseless +D7 4 3 DESD +D10 4 1 DESD +D11 4 8 DESD +D12 4 2 DESD +R4 2 3 300k noiseless +R5 1 8 300k noiseless +A6 5 7 0 0 0 0 N008 0 SCHMITT trise=40n tfall=120n vt=-2.1 vh=10m +D13 7 5 DSHUT +D14 4 5 DESD +D15 5 7 DESD +S2 4 7 N008 0 SPOW +B5 N004 0 I=10u*dnlim(uplim(V(2),V(7)-1.91,.1), V(4)-.21, .1)+1n*V(2) +B6 0 N004 I=10u*dnlim(uplim(V(3),V(7)-1.9,.1), V(4)-.2, .1)+1n*V(3) +S3 N012 N011 0 N008 SHUT2 +S7 N010 7 0 N008 SHUT1 +S8 4 N015 0 N008 SHUT1 +D3 N007 2 DBIAS +D16 N007 3 DBIAS +D17 N007 1 DBIAS +D18 N007 8 DBIAS +D19 N007 4 DPOW2 +C5 7 3 3.5p Rser=100 Rpar=1G noiseless +C6 7 1 3.5p Rser=100 Rpar=1G noiseless +C16 7 8 3.5p Rser=100 Rpar=1G noiseless +C17 4 2 3.5p Rser=100 Rpar=1G noiseless +C19 4 3 3.5p Rser=100 Rpar=1G noiseless +C20 4 1 3.5p Rser=100 Rpar=1G noiseless +C21 4 8 3.5p Rser=100 Rpar=1G noiseless +A2 1 8 0 0 0 0 0 0 OTA g=0 in=661f ink=1.22k +.model SBIAS SW(level=2 Ron=10 Roff=1G vt=.5 vh=-.2 noiseless) +.model DBIAS D(Ron=620k Roff=1G vfwd=-6.3 epsilon=.2 noiseless) +.model DSHUT D(Ron=180k Roff=110k Vfwd=1.7 epsilon=.1 noiseless) +.model SPOW SW(level=2 Ron=10 Roff=1Meg vt=.5 vh=-.2 ilimit=12.55m noiseless) +.model DPOW1 D(Ron=100k Roff=1G vfwd=1 epsilon=.1 ilimit=225u noiseless) +.model DPOW2 D(Ron=22.1k Roff=1G Vfwd=.5 epsilon=.1 noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan) +.model DLIM D(Ron=1k Roff=70Meg Vfwd=10 Vrev=2 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=2 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=2 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.ends LT6552 +* +.subckt LT6557 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +B1 0 N003 I=10u*dnlim(uplim(V(3),V(13)-.1,.1), V(4)+.1, .1)+1n*V(3) +B2 N003 0 I=10u*dnlim(uplim(V(INMR),V(13)-.09,.1), V(4)+.09, .1)+1n*V(INMR) +C10 N003 0 .1f Rpar=100K noiseless +R2 13 N008 80Meg noiseless +R3 N008 4 80Meg noiseless +C6 13 3 .75p Rpar=10Meg noiseless +C7 3 4 .75p Rpar=10Meg noiseless +M1 13 N005 14 14 N temp=27 +M2 4 N014 14 14 P temp=27 +D1 N005 14 YU +D9 14 N014 YD +A5 N004 0 N009 N009 N009 N009 N005 N009 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A7 N004 0 N009 N009 N009 N014 N009 N009 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C3 13 14 .9p +S2 13 4 N004 0 swPow +A3 0 N003 N004 0 0 0 N008 0 OTA g=20m linear en=11.7n enk=5.7k Cout=8p Vlow=-1e308 Vhigh=1e308 +G3 N008 0 N008 13 500m dir=1 vto=-.78 +G4 0 N008 4 N008 500m dir=1 vto=-.84 +R1 14 INMR 500 +R5 15 1 40k +A4 INMR 3 0 0 0 0 0 0 OTA g=0 in=19p ink=90 +C1 INMR 3 1p Rser=150 noiseless +C4 14 4 .9p +S4 3 4 N004 0 SWB +C12 14 N009 12f Rser=90k noiseless +C5 N002 0 400f noiseless Rpar=1k +R4 INMR 4 500 +G2 0 N009 N002 0 10µ +L1 N009 0 182.8µ Cpar=.684f Rpar=219.047619047619047628k Rser=184K noiseless +G5 0 N002 N008 0 1m +R19 N013 16 19 +R20 3 2 200k +G1 N007 N011 N013 16 105m +S1 N011 3 N013 16 SWBVC1 +D2 N007 N011 DBIAS +S5 15 N007 N004 0 SWBVC2 +D3 N007 N013 DVBC1 +B3 0 N022 I=10u*dnlim(uplim(V(5),V(11)-.1,.1), V(6)+.1, .1)+1n*V(5) +B4 N022 0 I=10u*dnlim(uplim(V(INMG),V(11)-.09,.1), V(6)+.09, .1)+1n*V(INMG) +C8 N022 0 .1f Rpar=100K noiseless +R22 11 N025 80Meg noiseless +R23 N025 6 80Meg noiseless +C9 11 5 .75p Rpar=10Meg noiseless +C11 5 6 .75p Rpar=10Meg noiseless +M3 11 N023 12 12 N temp=27 +M4 6 N028 12 12 P temp=27 +D4 N023 12 YU +D5 12 N028 YD +A2 N004 0 N026 N026 N026 N026 N023 N026 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A6 N004 0 N026 N026 N026 N028 N026 N026 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C13 11 12 .9p +A8 0 N022 N004 0 0 0 N025 0 OTA g=20m linear en=11.7n enk=5.7k Cout=8p Vlow=-1e308 Vhigh=1e308 +G6 N025 0 N025 11 500m dir=1 vto=-.78 +G7 0 N025 6 N025 500m dir=1 vto=-.84 +R24 12 INMG 500 +A9 INMG 5 0 0 0 0 0 0 OTA g=0 in=19p ink=90 +C14 INMG 5 1p Rser=150 noiseless +C15 12 6 .9p +S6 5 6 N004 0 SWB +C16 12 N026 12f Rser=90k noiseless +C17 N021 0 400f noiseless Rpar=1k +R27 INMG 6 500 +G8 0 N026 N021 0 10µ +L2 N026 0 182.8µ Cpar=.684f Rpar=219.047619047619047628k Rser=184K noiseless +G9 0 N021 N025 0 1m +R31 5 2 200k +G10 N007 N024 N013 16 105m +S7 N024 5 N013 16 SWBVC1 +D6 N007 N024 DBIAS +B5 0 N035 I=10u*dnlim(uplim(V(7),V(9)-.1,.1), V(8)+.1, .1)+1n*V(7) +B6 N035 0 I=10u*dnlim(uplim(V(INMB),V(9)-.09,.1), V(8)+.09, .1)+1n*V(INMB) +C19 N035 0 .1f Rpar=100K noiseless +R7 9 N038 80Meg noiseless +R8 N038 8 80Meg noiseless +C20 9 7 .75p Rpar=10Meg noiseless +C21 7 8 .75p Rpar=10Meg noiseless +M5 9 N036 10 10 N temp=27 +M6 8 N041 10 10 P temp=27 +D7 N036 10 YU +D8 10 N041 YD +A10 N004 0 N039 N039 N039 N039 N036 N039 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A11 N004 0 N039 N039 N039 N041 N039 N039 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C22 9 10 .9p +A12 0 N035 N004 0 0 0 N038 0 OTA g=20m linear en=11.7n enk=5.7k Cout=8p Vlow=-1e308 Vhigh=1e308 +G11 N038 0 N038 9 500m dir=1 vto=-.78 +G12 0 N038 8 N038 500m dir=1 vto=-.84 +R10 10 INMB 500 +A13 INMB 7 0 0 0 0 0 0 OTA g=0 in=19p ink=90 +C23 INMB 7 1p Rser=150 noiseless +C24 10 8 .9p +S3 7 8 N004 0 SWB +C25 10 N039 12f Rser=90k noiseless +C26 N034 0 400f noiseless Rpar=1k +R13 INMB 8 500 +G13 0 N039 N034 0 10µ +L3 N039 0 182.8µ Cpar=.684f Rpar=219.047619047619047628k Rser=184K noiseless +G14 0 N034 N038 0 1m +R15 7 2 200k +G15 N007 N037 N013 16 105m +S8 N037 7 N013 16 SWBVC1 +D10 N007 N037 DBIAS +C29 16 2 10p +C30 N011 2 100f Rpar=5k noiseless +C31 N024 2 100f Rpar=5k noiseless +C32 N037 2 100f Rpar=5k noiseless +C33 N007 2 10p +D11 N013 2 DVBC2 +C28 N013 2 100f +S9 11 6 N004 0 swPow +S10 9 8 N004 0 swPow +A14 15 1 0 0 0 0 N004 0 SCHMITT Vt=1.5 Vh=10m trise=50n tfall=1u Vlow=0 Vhigh=1 +.model YU D(Ron=10k Roff=1G Vfwd=.39 epsilon=.1 noiseless) +.model YD D(Ron=10k Roff=1G Vfwd=.42 epsilon=.1 noiseless) +.model N VDMOS(Vto=-50m Kp=900m) +.model P VDMOS(Vto=50m Kp=900m pchan) +.model swPow SW(level=2 Ron=100 Roff=2.5Meg vt=.5 vh=-50m ilimit=21m noiseless) +.model SWB SW(Ron=10k Roff=1g vt=.5 vh=-.3 ilimit=35u noiseless) +.model SWBVC1 SW(level=2 Ron=10 Roff=1G vt=550u vh=-100u noiseless) +.model SWBVC2 SW(level=2 Ron=10 Roff=1G vt=.5 vh=-.2 noiseless) +.model DBIAS D(Ron=100 Roff=1G Vfwd=.1 epsilon=50m ilimit=35u noiseless) +.model DVBC1 D(Ron=1 Roff=1k Vfwd=.5 epsilon=100m ilimit=1.65m noiseless) +.model DVBC2 D(Ron=6 Roff=1Meg Vfwd=30m epsilon=10m noiseless) +.ends LT6557 +* +.subckt LT6558 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +B1 0 N003 I=10u*dnlim(uplim(V(3),V(13)-.1,.1), V(4)+.1, .1)+1n*V(3) +B2 N003 0 I=10u*dnlim(uplim(V(14),V(13)-.09,.1), V(4)+.09, .1)+1n*V(14) +C10 N003 0 .1f Rpar=100K noiseless +R2 13 N008 80Meg noiseless +R3 N008 4 80Meg noiseless +C6 13 3 .6p Rpar=10Meg noiseless +C7 3 4 .6p Rpar=10Meg noiseless +M1 13 N005 14 14 N temp=27 +M2 4 N014 14 14 P temp=27 +D1 N005 14 YU +D9 14 N014 YD +A5 N004 0 N009 N009 N009 N009 N005 N009 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A7 N004 0 N009 N009 N009 N014 N009 N009 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C3 13 14 .9p +S2 13 4 N004 0 swPow +A3 0 N003 N004 0 0 0 N008 0 OTA g=20m linear en=18n enk=300 Cout=12p Vlow=-1e308 Vhigh=1e308 +G3 N008 0 N008 13 500m dir=1 vto=-.78 +G4 0 N008 4 N008 500m dir=1 vto=-.84 +R5 15 1 40k +C1 14 3 1p Rser=150 noiseless +C4 14 4 .9p +S4 3 4 N004 0 SWB +C12 14 N009 10f Rser=150k noiseless +C5 N002 0 800f noiseless Rpar=1k +G2 0 N009 N002 0 10µ +L1 N009 0 151µ Cpar=.422f Rpar=263.9k Rser=161K noiseless +G5 0 N002 N008 0 1m +R20 3 2 200k +G1 N007 N011 N013 16 82m +S1 N011 3 N013 16 SWBVC1 +D2 N007 N011 DBIAS +S5 15 N007 N004 0 SWBVC2 +D3 N007 N013 DVBC1 +B3 0 N022 I=10u*dnlim(uplim(V(5),V(11)-.1,.1), V(6)+.1, .1)+1n*V(5) +B4 N022 0 I=10u*dnlim(uplim(V(12),V(11)-.09,.1), V(6)+.09, .1)+1n*V(12) +C8 N022 0 .1f Rpar=100K noiseless +R22 11 N025 80Meg noiseless +R23 N025 6 80Meg noiseless +C9 11 5 .6p Rpar=10Meg noiseless +C11 5 6 .6p Rpar=10Meg noiseless +M3 11 N023 12 12 N temp=27 +M4 6 N028 12 12 P temp=27 +D4 N023 12 YU +D5 12 N028 YD +A2 N004 0 N026 N026 N026 N026 N023 N026 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A6 N004 0 N026 N026 N026 N028 N026 N026 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C13 11 12 .9p +G6 N025 0 N025 11 500m dir=1 vto=-.78 +G7 0 N025 6 N025 500m dir=1 vto=-.84 +A9 12 5 0 0 0 0 0 0 OTA g=0 in=5p ink=36.4k +C14 12 5 1p Rser=150 noiseless +C15 12 6 .9p +S6 5 6 N004 0 SWB +C17 N021 0 800f noiseless Rpar=1k +G8 0 N026 N021 0 10µ +G9 0 N021 N025 0 1m +R31 5 2 200k +G10 N007 N024 N013 16 82m +S7 N024 5 N013 16 SWBVC1 +D6 N007 N024 DBIAS +B5 0 N035 I=10u*dnlim(uplim(V(7),V(9)-.1,.1), V(8)+.1, .1)+1n*V(7) +B6 N035 0 I=10u*dnlim(uplim(V(10),V(9)-.09,.1), V(8)+.09, .1)+1n*V(10) +C19 N035 0 .1f Rpar=100K noiseless +R7 9 N038 80Meg noiseless +R8 N038 8 80Meg noiseless +C20 9 7 .6p Rpar=10Meg noiseless +C21 7 8 .6p Rpar=10Meg noiseless +M5 9 N036 10 10 N temp=27 +M6 8 N041 10 10 P temp=27 +D7 N036 10 YU +D8 10 N041 YD +A10 N004 0 N039 N039 N039 N039 N036 N039 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A11 N004 0 N039 N039 N039 N041 N039 N039 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C22 9 10 .9p +G11 N038 0 N038 9 500m dir=1 vto=-.78 +G12 0 N038 8 N038 500m dir=1 vto=-.84 +C23 10 7 1p Rser=150 noiseless +C24 10 8 .9p +S3 7 8 N004 0 SWB +C26 N034 0 800f noiseless Rpar=1k +G13 0 N039 N034 0 10µ +G14 0 N034 N038 0 1m +R15 7 2 200k +G15 N007 N037 N013 16 82m +S8 N037 7 N013 16 SWBVC1 +D10 N007 N037 DBIAS +C29 16 2 10p +C30 N011 2 100f Rpar=5k noiseless +C31 N024 2 100f Rpar=5k noiseless +C32 N037 2 100f Rpar=5k noiseless +C33 N007 2 10p +D11 N013 2 DVBC2 +C28 N013 2 100f +S9 11 6 N004 0 swPow +S10 9 8 N004 0 swPow +A14 15 1 0 0 0 0 N004 0 SCHMITT Vt=1.5 Vh=10m trise=50n tfall=1u Vlow=0 Vhigh=1 +D12 N013 16 DVBC3 +L2 N026 0 151µ Cpar=.422f Rpar=263.9k Rser=161K noiseless +L3 N039 0 151µ Cpar=.422f Rpar=263.9k Rser=161K noiseless +C16 12 N026 10f Rser=150k noiseless +C25 10 N039 10f Rser=150k noiseless +A1 14 3 0 0 0 0 0 0 OTA g=0 in=5p ink=36.4k +A4 10 7 0 0 0 0 0 0 OTA g=0 in=5p ink=36.4k +A8 0 N022 N004 0 0 0 N025 0 OTA g=20m linear en=18n enk=300 Cout=12p Vlow=-1e308 Vhigh=1e308 +A12 0 N035 N004 0 0 0 N038 0 OTA g=20m linear en=18n enk=300 Cout=12p Vlow=-1e308 Vhigh=1e308 +.model YU D(Ron=10k Roff=1G Vfwd=.37 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1G Vfwd=.35 epsilon=.1 noiseless) +.model N VDMOS(Vto=-50m Kp=900m) +.model P VDMOS(Vto=50m Kp=900m pchan) +.model swPow SW(level=2 Ron=100 Roff=2.5Meg vt=.5 vh=-50m ilimit=21m noiseless) +.model SWB SW(Ron=10k Roff=1g vt=.5 vh=-.3 ilimit=35u noiseless) +.model SWBVC1 SW(level=2 Ron=10 Roff=1G vt=550u vh=-100u noiseless) +.model SWBVC2 SW(level=2 Ron=10 Roff=1G vt=.5 vh=-.2 noiseless) +.model DBIAS D(Ron=100 Roff=1G Vfwd=.1 epsilon=50m ilimit=35u noiseless) +.model DVBC1 D(Ron=1 Roff=1k Vfwd=.5 epsilon=100m ilimit=1.2m noiseless) +.model DVBC2 D(Ron=10 Roff=1Meg Vfwd=30m epsilon=10m noiseless) +.model DVBC3 D(Ron=10 Roff=22 Vfwd=6.3m epsilon=1m noiseless) +.ends LT6558 +* +.subckt LT6559 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-.9,.1), V(4)+.9, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-.89,.1), V(4)+.89, .1)+1n*V(2) +C10 N004 0 .1f Rpar=100k noiseless +R2 3 N010 8Meg noiseless +R3 N010 4 8Meg noiseless +C6 3 1 1p Rpar=10Meg Rser=100 noiseless +G1 0 N009 N010 0 10µ +G2 0 N010 N005 0 35µ +C14 N010 N013 21f +A2 6 4 0 0 0 N006 0 0 SCHMITT Vt=3 Vh=10m tau=40n Vlow=0 Vhigh=1 +M1 3 N007 5 5 N1 temp=27 +M2 4 N014 5 5 P1 temp=27 +D1 N007 5 Y +D9 5 N014 Y +A5 N006 0 N009 N009 N009 N009 N007 N009 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-7 Rout=1k Cout=.5p +A7 N006 0 N009 N009 N009 N014 N009 N009 SCHMITT Vt=.5 Vh=10m Vhigh=7 Vlow=0 Rout=1k Cout=.5p +C3 3 5 .1p +A3 0 N004 N006 0 0 0 N005 0 OTA g=12.6m iout=5m Cout=10f en=3.6n enk=234 Vhigh=1e308 rout=1k Vlow=-1e308 +G3 N010 0 N010 3 100m dir=1 vto=-.78 +G4 0 N010 4 N010 100m dir=1 vto=-.78 +A4 0 1 0 0 0 0 0 0 OTA g=0 in=4p ink=158 +D3 N005 0 DSI temp=27 +D4 0 N005 DSI temp=27 +I1 3 N008 23m +S1 N008 N011 N006 0 SW2 +G5 N008 3 3 1 33.3m +C2 3 N008 .1p Rpar=30 noiseless +I2 N016 4 23m +G6 4 N016 1 4 33.3m +C9 N016 4 .1p Rpar=30 noiseless +S3 N016 N012 N006 0 SW2 +G7 0 N013 3 0 .5m +G8 0 N013 4 0 .5m +C11 N013 0 200p Rpar=1K noiseless +C4 5 4 .1p +S4 4 1 N006 0 SWB +D2 N011 2 DSI2 temp=27 +D7 2 N012 DSI2 temp=27 +C1 3 2 .05p Rpar=10Meg noiseless +C5 2 4 .05p Rpar=10Meg noiseless +C8 N009 0 .53f noiseless Rser=500k Rpar=100k +C7 1 4 1p Rpar=10Meg Rser=100 noiseless +D5 3 6 DEN +A1 0 2 0 0 0 0 0 0 OTA g=0 in=20p ink=1.1k +.model Y D(Ron=1k Roff=1G Vfwd=1.5 epsilon=.2 noiseless) +.model N1 VDMOS(Vto=-394m Kp=50m) +.model P1 VDMOS(Vto=394m Kp=50m pchan) +.model DEN D(Ron=1k Roff=1G Vfwd=2 epsilon=.5 ilimit=30u noiseless) +.model SWB SW(Ron=10k Roff=1g vt=.5 vh=-.3 ilimit=9u noiseless) +.model DSI D(Is=5e-13 TT=.6n noiseless) +.model DSI2 D(Is=1e-14 TT=1u cjo=1p noiseless) +.model SW2 SW(level=2 Ron=1 Roff=1G vt=.5 vh=-.3 ilimit=1m noiseless) +.ends LT6559 +* +.subckt LTC6244 1 2 3 4 5 +A1 0 N009 0 0 0 0 N005 0 OTA g=4e-4 Iout=28u Cout=.79p Vhigh=1e308 Vlow=-1e308 +A2 2 1 0 0 0 0 0 0 OTA g=0 in=5.6e-16+9e-19*freq ink=70 +R1 3 N005 10G noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C4 2 1 2.975p +C5 1 4 .525p +C7 3 5 1p +C8 5 4 1p +C9 3 1 .525p +C10 3 2 .525p +C11 2 4 .525p +D3 5 N005 DX +R2 N005 4 10G noiseless +B1 0 N004 I=1m*dnlim(uplim(V(1),V(3)-1.4,0.1), V(4)-50m,.1)+1n*V(1) +B2 N004 0 I=1m*dnlim(uplim(V(2),V(3)-1.39,0.1), V(4)-51m,0.1)+1n*V(2) +G1 0 N008 N007 0 1m +L1 N008 0 65µ Rser=1.25K Rpar=5K noiseless +G2 0 N009 N008 0 1µ +C1 N009 0 150f Rpar=1Meg noiseless +C2 N007 0 30p Rser=1K Rpar=1K Cpar=2p noiseless +A3 0 N004 0 0 0 0 N007 0 OTA g=1m linear en=8n enk=200 Vhigh=1e308 Vlow=-1e308 +L3 0 N004 10µ Rser=1.25K Rpar=5K Cpar=.2p noiseless +.model DX D(Ron=1k Roff=1T Vfwd=1.6 Vrev=1.6 epsilon=0.5 revepsilon=0.5 noiseless) +.model N VDMOS(Vto=-1.05 Kp=10.5m) +.model P VDMOS(Vto=1.05 Kp=10.5m pchan) +.ends LTC6244 +* +.subckt LTC6244HV 1 2 3 4 5 +A1 0 N009 0 0 0 0 N005 0 OTA g=4e-4 Iout=32u Cout=.79p Vhigh=1e308 Vlow=-1e308 +A2 2 1 0 0 0 0 0 0 OTA g=0 in=5.6e-16+9e-19*freq ink=70 +R1 3 N005 10G noiseless +M1 3 N005 5 5 N temp=27 +M2 4 N005 5 5 P temp=27 +C4 2 1 2.975p +C5 1 4 .525p +C7 3 5 1p +C8 5 4 1p +C9 3 1 .525p +C10 3 2 .525p +C11 2 4 .525p +D3 5 N005 DX +R2 N005 4 10G noiseless +B1 0 N004 I=1m*dnlim(uplim(V(1),V(3)-.75,0.1), V(4)-50m,.1)+1n*V(1) +B2 N004 0 I=1m*dnlim(uplim(V(2),V(3)-.749,0.1), V(4)-51m,0.1)+1n*V(2) +G1 0 N008 N007 0 1m +L1 N008 0 65µ Rser=1.25K Rpar=5K noiseless +G2 0 N009 N008 0 1µ +C1 N009 0 150f Rpar=1Meg noiseless +C2 N007 0 30p Rser=1K Rpar=1K Cpar=2p noiseless +A3 0 N004 0 0 0 0 N007 0 OTA g=1m linear en=8n enk=200 Vhigh=1e308 Vlow=-1e308 +L3 0 N004 10µ Rser=1.25K Rpar=5K Cpar=.2p noiseless +.model DX D(Ron=1k Roff=1T Vfwd=1.6 Vrev=1.6 epsilon=0.5 revepsilon=0.5 noiseless) +.model N VDMOS(Vto=-1.05 Kp=10.5m) +.model P VDMOS(Vto=1.05 Kp=10.5m pchan) +.ends LTC6244HV +* +.subckt LTC6078 1 2 3 4 5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +C16 N005 N012 68p Rser=2k noiseless +A5 N007 0 0 0 0 0 N005 0 OTA g=384u iout=4.4u Vhigh=1e308 Vlow=-1e308 +D9 N005 0 DLIM +C7 3 1 9p Rser=100 Rpar=5T noiseless +C13 3 4 100p +C1 N006 0 4p Rpar=1Meg noiseless +G3 0 N007 N006 0 1m +L1 N007 0 1.8m Cpar=143f Rser=1.02k Rpar=51k noiseless +D6 2 3 DESD +D7 4 2 DESD +D10 1 3 DESD +D11 4 1 DESD +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.56f +D1 3 2 DBIAS +C4 3 2 9p Rser=100 Rpar=5T noiseless +C5 1 4 9p Rser=100 Rpar=5T noiseless +C6 2 4 9p Rser=100 Rpar=5T noiseless +C15 2 1 1p Rser=100 Rpar=5T noiseless +D2 3 4 DP +D3 3 1 DBIAS +A2 0 N004 0 0 0 0 N006 0 OTA g=1u linear en=16n + 50f*freq enk=20 Vlow=-20m Vhigh=20m +G5 0 N012 5 Mid 100m +C8 N012 0 1p Rpar=10 noiseless +M1 5 N010 4 4 NI temp=27 +C2 3 5 1p Rpar=10Meg noiseless +M2 5 N008 3 3 PI temp=27 +C9 5 4 1p Rpar=10Meg noiseless +D4 3 N008 DLIMP +D5 N010 4 DLIMN +D8 3 N010 DBIASO +D12 N008 4 DBIASO +C11 3 N008 150f Rser=400k noiseless +G1 4 N010 N005 0 500n +G7 3 N008 N005 0 500n +R3 3 Mid 10Meg noiseless +C3 N010 4 150f Rser=400k noiseless +R4 Mid 4 10Meg noiseless +.model NI VDMOS(Vto=300m kp=25m mtriode=.5 subthres=40u lambda=.01 noiseless) +.model PI VDMOS(Vto=-300m Kp=20m mtriode=.65 subthres=40u lambda=.01 pchan noiseless) +.model DLIM D(Ron=10k Roff=500Meg Vfwd=4 Vrev=4 epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DBIAS D(Ron=1g Roff=1T epsilon=.3 ilimit=.2p noiseless) +.model DP D(Ron=10k Roff=1g Vfwd=.5 epsilon=.1 ilimit=34.68u noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=1.8 epsilon=.1 noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=1.8 epsilon=10m noiseless) +.model DBIASO D(Ron=10k Roff=1G vfwd=1 epsilon=300m ilimit=303n noiseless) +.ends LTC6078 +* +.subckt LT6108-1 1 2 3 4 5 6 7 8 +M2 6 N005 N006 N006 P temp=27 +C3 7 6 .1p +C4 6 4 .1p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(7)+.5,.1), V(4)-.5, .1) +B2 N003 0 I=10u*dnlim(uplim(V(8),V(7)+.51,.1), V(4)-.51, .1) +C10 N003 0 10f Rpar=100K noiseless +D7 7 4 DP +A6 2 4 4 4 4 4 N013 4 SCHMITT Vt=1 Vh=10m trise=10n tfall=10n +R1 8 N006 100 +D1 8 1 DINCL +D4 8 7 DESD +D5 1 7 DESD +D9 N005 N006 DZ6 +D10 N005 7 DZ34 +D6 4 8 DESD +D8 4 1 DESD +D11 4 6 DESD +M3 3 N019 4 4 N temp=27 +C1 7 8 .2p +C2 8 4 .2p +C5 7 1 .2p +C6 1 4 .2p +A3 0 N025 0 0 0 0 N020 0 OTA g=2m asym isource=200u isink=-1u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D15 4 2 DESD +D12 7 2 DEN +A8 0 N003 N004 4 4 4 N010 4 OTA g=5u iout=5u Cout=300f Vlow=-1e308 Vhigh=1e308 +A9 0 N010 4 4 4 4 N005 4 OTA g=100u linear Cout=7p Rout=10k Vlow=-1e308 Vhigh=1e308 +C7 N019 4 100f Rpar=10Meg +C11 3 4 4p +A2 N013 4 4 4 4 4 N014 4 BUF td=16u trise=10n tfall=10n +A1 0 N020 N012 4 4 4 N019 4 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +D17 N019 4 DNLIM +C12 3 N019 6f +D3 4 5 DESD +D20 N026 5 DCBIAS +A13 7 4 4 4 4 4 N009 4 SCHMITT Vt=2.5 Vh=10m tau=10n IC=1 +S3 N010 7 4 N004 ISHD +A4 N009 N014 4 4 4 N016 N004 4 AND trise=100n tfall=100n vlow=1e-6 vhigh=1 td=10u +D24 N010 7 XU +D25 4 N010 XD +A15 N004 4 4 4 4 4 N012 4 BUF td=7u trise=1u tfall=1u +S2 7 4 N012 4 IQ +D16 8 N008 DABI +S1 N008 4 N012 4 SWB +S4 N026 4 N012 4 SWB +C18 4 2 2p +C19 4 5 2p +C22 N008 4 2p +D18 1 N008 DABI +R3 7 N008 457k +A12 4 N018 4 5 4 N021 4 4 OR Ref=.39 Trise=10n Tfall=1n IC=0 +C9 N025 0 1p Rpar=100k +G1 0 N025 5 4 10µ +I1 N025 0 3.947µ +A20 N009 N013 4 N012 4 4 N018 4 AND tfall=.1u trise=.1u +A19 N016 N021 4 4 4 4 N022 4 OR Trise=10n Tfall=10n +D2 0 N023 DLAT1 +C13 N023 0 150p +A5 0 N020 0 0 0 0 N023 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +A7 0 N023 0 0 0 0 N020 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +G3 N020 0 N022 4 1m +D14 0 N020 DLAT +S5 7 4 N019 4 SCB +.model DINCL D(Ron=6k Roff=100G Vfwd=.7 Vrev=.7 epsilon=.1 revepsilon=.1) +.model DESD D(Ron=500 Roff=100G Vfwd=.7 epsilon=.1) +.model DZ34 D(Ron=100 Roff=10Meg Vfwd=.7 Vrev=34.1 epsilon=.1 revepsilon=.1) +.model DZ6 D(Ron=100 Roff=100G Vfwd=.7 Vrev=6 epsilon=.1 revepsilon=.1) +.model DEN D(Ron=100k Vfwd=1 epsilon=.1 ilimit=200n) +.model DABI D(Ron=10k Roff=1g Vfwd=.3 epsilon=.1 ilimit=60n) +.model DCBIAS D(Ron=200k Roff=1T Vfwd=-.45 epsilon=.15 ilimit=12n) +.model SWB SW(Vt=.5 Vh=-.1 Ron=1k Roff=1T level=2) +.model SCB SW(level=2 Vt=.3 Vh=-.1 Ron=10K Roff=1G ilimit=75u) +.model DLAT D(Ron=1 Roff=100k Vfwd=1 Vrev=1 epsilon=90m revepsilon=90m) +.model DLAT1 D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1) +.model DNLIM D(Ron=100 Roff=1G Vfwd=1 Vrev=20m epsilon=.1 revepsilon=10m) +.model XU D(Ron=1K Roff=400G Vfwd=1 epsilon=.1) +.model XD D(Ron=1K Roff=200G Vfwd=1 epsilon=.1) +.model IQ SW(Vt=.5 Vh=-.3 Ron=100 Roff=1G ilimit= 420.8u level=2) +.model ISHD SW(Vt=-.5 Vh=-.3 Ron=1 Roff=400G) +.model N VDMOS(Vto=20m Kp=800m Rd=105) +.model P VDMOS(Vto=-1 Kp=100m Cgs=1f cgdmin=.1f cgdmax=.2f subthres=100u rds=1g pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 epsilon=.1 ilimit=2.7u) +.ends LT6108-1 +* +.subckt LT6108-2 1 2 3 4 5 6 7 8 +M2 6 N005 N006 N006 P temp=27 +C3 7 6 .1p +C4 6 4 .1p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(7)+.5,.1), V(4)-.5, .1) +B2 N003 0 I=10u*dnlim(uplim(V(8),V(7)+.51,.1), V(4)-.51, .1) +C10 N003 0 10f Rpar=100K noiseless +D7 7 4 DP +A6 2 4 4 4 4 4 N013 4 SCHMITT Vt=1 Vh=10m trise=10n tfall=10n +R1 8 N006 100 +D1 8 1 DINCL +D4 8 7 DESD +D5 1 7 DESD +D9 N005 N006 DZ6 +D10 N005 7 DZ34 +D6 4 8 DESD +D8 4 1 DESD +D11 4 6 DESD +M3 3 N017 4 4 N temp=27 +C1 7 8 .2p +C2 8 4 .2p +C5 7 1 .2p +C6 1 4 .2p +A3 0 N022 0 0 0 0 N018 0 OTA g=2m iout=200u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D15 4 2 DESD +D12 7 2 DEN +A8 0 N003 N004 4 4 4 N010 4 OTA g=5u iout=5u Cout=300f Vlow=-1e308 Vhigh=1e308 +A9 0 N010 4 4 4 4 N005 4 OTA g=100u linear Cout=7p Rout=10k Vlow=-1e308 Vhigh=1e308 +C7 N017 4 100f Rpar=10Meg +C11 3 4 4p +A2 N013 4 4 4 4 4 N014 4 BUF td=16u trise=10n tfall=10n +A1 0 N018 N012 4 4 4 N017 4 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +D17 N017 4 DNLIM +C12 3 N017 6f +D3 4 5 DESD +D20 N023 5 DCBIAS +A13 7 4 4 4 4 4 N009 4 SCHMITT Vt=2.5 Vh=10m tau=10n IC=1 +S3 N010 7 4 N004 ISHD +A4 N009 N014 4 4 4 4 N004 4 AND trise=100n tfall=100n vlow=1e-6 vhigh=1 td=10u +D24 N010 7 XU +D25 4 N010 XD +A15 N004 4 4 4 4 4 N012 4 BUF td=7u trise=1u tfall=1u +S2 7 4 N012 4 IQ +D16 8 N008 DABI +S1 N008 4 N012 4 SWB +S4 N023 4 N012 4 SWB +C18 4 2 2p +C19 4 5 2p +C22 N008 4 2p +D18 1 N008 DABI +R3 7 N008 457k +C9 N022 0 1p Rpar=100k +G1 0 N022 5 4 10µ +I1 N022 0 3.947µ +D14 0 N018 DLAT +D2 0 N019 DLAT1 +C8 N019 0 150p +A5 0 N018 0 0 0 0 N019 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +A7 0 N019 0 0 0 0 N018 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +G2 N018 0 N020 4 1m +A10 4 N012 4 5 4 N020 4 4 AND trise=700n tfall=100n Ref=.389 IC=0 +S5 7 4 N017 4 SCB +.model DINCL D(Ron=6k Roff=100G Vfwd=.7 Vrev=.7 epsilon=.1 revepsilon=.1) +.model DESD D(Ron=500 Roff=100G Vfwd=.7 epsilon=.1) +.model DZ34 D(Ron=100 Roff=10Meg Vfwd=.7 Vrev=34.1 epsilon=.1 revepsilon=.1) +.model DZ6 D(Ron=100 Roff=100G Vfwd=.7 Vrev=6 epsilon=.1 revepsilon=.1) +.model DEN D(Ron=100k Vfwd=1 epsilon=.1 ilimit=200n) +.model DABI D(Ron=10k Roff=1g Vfwd=.3 epsilon=.1 ilimit=60n) +.model DCBIAS D(Ron=200k Roff=1T Vfwd=-.45 epsilon=.15 ilimit=12n) +.model SWB SW(Vt=.5 Vh=-.1 Ron=1k Roff=1T level=2) +.model SCB SW(level=2 Vt=.3 Vh=-.1 Ron=10K Roff=1G ilimit=75u) +.model XU D(Ron=1K Roff=400G Vfwd=1 epsilon=.1) +.model XD D(Ron=1K Roff=200G Vfwd=1 epsilon=.1) +.model IQ SW(Vt=.5 Vh=-.3 Ron=100 Roff=1G ilimit= 420.8u level=2) +.model ISHD SW(Vt=-.5 Vh=-.3 Ron=1 Roff=400G) +.model N VDMOS(Vto=20m Kp=800m Rd=105) +.model P VDMOS(Vto=-1 Kp=100m Cgs=1f cgdmin=.1f cgdmax=.2f subthres=100u rds=1g pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 epsilon=.1 ilimit=2.7u) +.model DLAT D(Ron=1 Roff=100k Vfwd=1 Vrev=1 epsilon=90m revepsilon=90m) +.model DLAT1 D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1) +.model DNLIM D(Ron=100 Roff=1G Vfwd=1 Vrev=20m epsilon=.1 revepsilon=10m) +.ends LT6108-2 +* +.subckt LT6109-1 1 2 3 4 5 6 7 8 9 10 +M2 8 N005 N006 N006 P temp=27 +C3 9 8 .1p +C4 8 5 .1p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(9)+.5,.1), V(5)-.5, .1) +B2 N003 0 I=10u*dnlim(uplim(V(10),V(9)+.51,.1), V(5)-.51, .1) +C10 N003 0 10f Rpar=100K noiseless +D7 9 5 DP +A6 2 5 5 5 5 5 N013 5 SCHMITT Vt=1 Vh=10m trise=10n tfall=10n +R1 10 N006 100 +D1 10 1 DINCL +D4 10 9 DESD +D5 1 9 DESD +D9 N005 N006 DZ6 +D10 N005 9 DZ34 +D6 5 10 DESD +D8 5 1 DESD +D11 5 8 DESD +M3 4 N019 5 5 N temp=27 +C1 9 10 2p +C2 10 5 2p +C5 9 1 2p +C6 1 5 2p +A3 0 N031 0 0 0 0 N023 0 OTA g=2m asym isource=200u isink=-1u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D13 0 N023 DLAT +D14 0 N034 DLAT1 +C8 N034 0 150p +D15 5 2 DESD +D12 9 2 DEN +A8 0 N003 N004 5 5 5 N010 5 OTA g=5u iout=5u Cout=300f Vlow=-1e308 Vhigh=1e308 +A9 0 N010 5 5 5 5 N005 5 OTA g=100u linear Cout=7p Rout=10k Vlow=-1e308 Vhigh=1e308 +C7 N019 5 100f Rpar=10Meg +C11 4 5 4p +A2 N013 5 5 5 5 5 N014 5 BUF td=16u trise=10n tfall=10n +A1 0 N023 N012 5 5 5 N019 5 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +D17 N019 5 DNLIM +C12 4 N019 6f +D2 5 7 DESD +D3 5 6 DESD +D19 N027 7 DCBIAS +D20 N027 6 DCBIAS +M4 3 N032 5 5 N temp=27 +C15 N032 5 100f Rpar=10Meg +C16 3 5 4p +D23 N032 5 DNLIM +C17 3 N032 6f +A13 9 5 5 5 5 5 N009 5 SCHMITT Vt=2.5 Vh=10m tau=10n IC=1 +S3 N010 9 5 N004 ISHD +A4 N009 N014 5 5 5 N016 N004 5 AND trise=100n tfall=100n vlow=1e-6 vhigh=1 td=10u +D24 N010 9 XU +D25 5 N010 XD +A15 N004 5 5 5 5 5 N012 5 BUF td=7u trise=1u tfall=1u +S2 9 5 N012 5 IQ +D16 10 N008 DABI +S1 N008 5 N012 5 SWB +S4 N027 5 N012 5 SWB +C18 5 2 2p +C19 5 6 2p +C20 5 7 10f +C21 5 N027 10f +C22 N008 5 2p +D18 1 N008 DABI +R3 9 N008 457k +A12 5 N018 5 6 5 N021 5 5 OR Ref=.39 Trise=10n Tfall=1n IC=0 +A16 0 N023 0 0 0 0 N034 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +C9 N031 0 1p Rpar=100k +G1 0 N031 6 5 10µ +I1 N031 0 3.947µ +G2 N023 0 N022 5 1m +A7 0 N029 N012 5 5 5 N032 5 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +A10 0 N034 0 0 0 0 N023 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +A5 5 N025 5 7 5 5 N024 5 AND Ref=.41 Trise=1n Tfall=10n IC=1 +A11 0 N030 0 0 0 0 N029 0 OTA g=2m asym isource=200u isink=-1u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D21 0 N029 DLAT +C13 N030 0 1p Rpar=100k +I2 0 N030 4.053µ +G4 N029 0 N020 5 1m +G3 N030 0 7 5 10µ +D22 0 N035 DLAT1 +C14 N035 0 150p +A17 0 N029 0 0 0 0 N035 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +A18 0 N035 0 0 0 0 N029 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +A20 N009 N013 5 N012 5 N025 N018 5 AND tfall=.1u trise=.1u +A14 5 N016 5 N024 5 5 N020 5 OR Trise=10n Tfall=10n +A19 N016 N021 5 5 5 5 N022 5 OR Trise=10n Tfall=10n +S5 9 5 N019 5 SCB +S6 9 5 N032 5 SCB +.model XU D(Ron=1K Roff=400G Vfwd=1 epsilon=.1) +.model XD D(Ron=1K Roff=200G Vfwd=1 epsilon=.1) +.model IQ SW(Vt=.5 Vh=-.3 Ron=100 Roff=1G ilimit= 467u level=2) +.model ISHD SW(Vt=-.5 Vh=-.3 Ron=1 Roff=400G) +.model N VDMOS(Vto=20m Kp=800m Rd=105) +.model P VDMOS(Vto=-1 Kp=100m Cgs=1f cgdmin=.1f cgdmax=.2f subthres=100u rds=1g pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 epsilon=.1 ilimit=2.7u) +.model DINCL D(Ron=6k Roff=100G Vfwd=.7 Vrev=.7 epsilon=.1 revepsilon=.1) +.model DESD D(Ron=500 Roff=100G Vfwd=.7 epsilon=.1) +.model DZ34 D(Ron=100 Roff=10Meg Vfwd=.7 Vrev=34.1 epsilon=.1 revepsilon=.1) +.model DZ6 D(Ron=100 Roff=100G Vfwd=.7 Vrev=6 epsilon=.1 revepsilon=.1) +.model DEN D(Ron=100k Vfwd=1 epsilon=.1 ilimit=200n) +.model DLAT D(Ron=1 Roff=100k Vfwd=1 Vrev=1 epsilon=90m revepsilon=90m) +.model DLAT1 D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1) +.model DNLIM D(Ron=100 Roff=1G Vfwd=1 Vrev=20m epsilon=.1 revepsilon=10m) +.model DABI D(Ron=10k Roff=1g Vfwd=.3 epsilon=.1 ilimit=60n) +.model DCBIAS D(Ron=200k Roff=1T Vfwd=-.45 epsilon=.15 ilimit=12n) +.model SWB SW(Vt=.5 Vh=-.1 Ron=1k Roff=1T level=2) +.model SCB SW(level=2 Vt=.3 Vh=-.1 Ron=10K Roff=1G ilimit=75u) +.ends LT6109-1 +* +.subckt LT6109-2 1 2 3 4 5 6 7 8 9 10 +M2 8 N005 N006 N006 P temp=27 +C3 9 8 .1p +C4 8 5 .1p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(9)+.5,.1), V(5)-.5, .1) +B2 N003 0 I=10u*dnlim(uplim(V(10),V(9)+.51,.1), V(5)-.51, .1) +C10 N003 0 10f Rpar=100K noiseless +D7 9 5 DP +A6 2 5 5 5 5 5 N013 5 SCHMITT Vt=1 Vh=10m trise=10n tfall=10n +R1 10 N006 100 +D1 10 1 DINCL +D4 10 9 DESD +D5 1 9 DESD +D9 N005 N006 DZ6 +D10 N005 9 DZ34 +D6 5 10 DESD +D8 5 1 DESD +D11 5 8 DESD +M3 4 N019 5 5 N temp=27 +C1 9 10 .2p +C2 10 5 .2p +C5 9 1 .2p +C6 1 5 .2p +A3 0 N028 0 0 0 0 N022 0 OTA g=2m asym isource=200u isink=-1u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D13 0 N022 DLAT +D14 0 N033 DLAT1 +C8 N033 0 150p +D15 5 2 DESD +D12 9 2 DEN +A8 0 N003 N004 5 5 5 N010 5 OTA g=5u iout=5u Cout=300f Vlow=-1e308 Vhigh=1e308 +A9 0 N010 5 5 5 5 N005 5 OTA g=100u linear Cout=7p Rout=10k Vlow=-1e308 Vhigh=1e308 +C7 N019 5 100f Rpar=10Meg +C11 4 5 4p +A2 N013 5 5 5 5 5 N014 5 BUF td=16u trise=10n tfall=10n +A1 0 N022 N012 5 5 5 N019 5 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +D17 N019 5 DNLIM +C12 4 N019 6f +D2 5 7 DESD +D3 5 6 DESD +D19 N026 7 DCBIAS +D20 N026 6 DCBIAS +M4 3 N031 5 5 N temp=27 +C15 N031 5 100f Rpar=10Meg +C16 3 5 4p +D23 N031 5 DNLIM +C17 3 N031 6f +A13 9 5 5 5 5 5 N009 5 SCHMITT Vt=2.5 Vh=10m tau=10n IC=1 +S3 N010 9 5 N004 ISHD +A4 N009 N014 5 5 5 N016 N004 5 AND trise=100n tfall=100n vlow=1e-6 vhigh=1 td=10u +D24 N010 9 XU +D25 5 N010 XD +A15 N004 5 5 5 5 5 N012 5 BUF td=7u trise=1u tfall=1u +S2 9 5 N012 5 IQ +D16 10 N008 DABI +S1 N008 5 N012 5 SWB +S4 N026 5 N012 5 SWB +C18 5 2 2p +C19 5 6 2p +C20 5 7 10f +C21 5 N026 10f +C22 N008 5 2p +D18 1 N008 DABI +R3 9 N008 457k +A12 5 N018 5 6 5 N020 5 5 OR Ref=.39 Trise=10n Tfall=1n IC=0 +A16 0 N022 0 0 0 0 N033 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +C9 N028 0 1p Rpar=100k +G1 0 N028 6 5 10µ +I1 N028 0 3.947µ +G2 N022 0 N021 5 1m +A7 0 N029 N012 5 5 5 N031 5 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +A10 0 N033 0 0 0 0 N022 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +A20 N009 N013 5 N012 5 5 N018 5 AND tfall=.1u trise=.1u +A19 N016 N020 5 5 5 5 N021 5 OR Trise=10n Tfall=10n +A5 0 N030 0 0 0 0 N029 0 OTA g=2m asym isource=200u isink=-1u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D21 0 N029 DLAT +D22 0 N034 DLAT1 +C13 N034 0 150p +A11 5 N018 5 7 5 N024 5 5 OR Ref=.39 Trise=10n Tfall=1n IC=0 +A14 0 N029 0 0 0 0 N034 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +C14 N030 0 1p Rpar=100k +G3 0 N030 7 5 10µ +I2 N030 0 3.947µ +G4 N029 0 N025 5 1m +A17 0 N034 0 0 0 0 N029 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +A18 5 N024 5 5 5 5 N025 5 OR Trise=10n Tfall=10n +S5 9 5 N019 5 SCB +S6 9 5 N031 5 SCB +.model DINCL D(Ron=6k Roff=100G Vfwd=.7 Vrev=.7 epsilon=.1 revepsilon=.1) +.model DESD D(Ron=500 Roff=100G Vfwd=.7 epsilon=.1) +.model DZ34 D(Ron=100 Roff=10Meg Vfwd=.7 Vrev=34.1 epsilon=.1 revepsilon=.1) +.model DZ6 D(Ron=100 Roff=100G Vfwd=.7 Vrev=6 epsilon=.1 revepsilon=.1) +.model DEN D(Ron=100k Vfwd=1 epsilon=.1 ilimit=200n) +.model DABI D(Ron=10k Roff=1g Vfwd=.3 epsilon=.1 ilimit=60n) +.model DCBIAS D(Ron=200k Roff=1T Vfwd=-.45 epsilon=.15 ilimit=12n) +.model SWB SW(Vt=.5 Vh=-.1 Ron=1k Roff=1T level=2) +.model SCB SW(level=2 Vt=.3 Vh=-.1 Ron=10K Roff=1G ilimit=75u) +.model DLAT D(Ron=1 Roff=100k Vfwd=1 Vrev=1 epsilon=90m revepsilon=90m) +.model DLAT1 D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1) +.model DNLIM D(Ron=100 Roff=1G Vfwd=1 Vrev=20m epsilon=.1 revepsilon=10m) +.model XU D(Ron=1K Roff=400G Vfwd=1 epsilon=.1) +.model XD D(Ron=1K Roff=200G Vfwd=1 epsilon=.1) +.model IQ SW(Vt=.5 Vh=-.3 Ron=100 Roff=1G ilimit= 467u level=2) +.model ISHD SW(Vt=-.5 Vh=-.3 Ron=1 Roff=400G) +.model N VDMOS(Vto=20m Kp=800m Rd=105) +.model P VDMOS(Vto=-1 Kp=100m Cgs=1f cgdmin=.1f cgdmax=.2f subthres=100u rds=1g pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 epsilon=.1 ilimit=2.7u) +.ends LT6109-2 +* +.subckt LTC6090 1 2 3 4 5 6 7 8 +A1 2 3 0 0 0 0 0 0 OTA g=0 in=1f +B1 0 N004 I=10u*dnlim(uplim(V(3),V(7)-2,.1), V(4)+2, .1)+1n*V(3) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(7)-1.99,.1), V(4)+1.99, .1)+1n*V(2) +C10 N004 0 .5f Rpar=100K noiseless +M1 6 N016 4 4 NI temp=27 +C2 7 6 1p Rpar=1Meg noiseless +D5 N016 4 DLIMN1 +M2 6 N011 7 7 PI temp=27 +D8 7 N011 DLIMP1 +C3 7 N011 100f Rser=50Meg noiseless +A3 N012 N013 4 4 4 4 N011 4 OTA g=20n ref=-.45 linear vlow=-1e308 vhigh=1e308 +C11 6 4 1p Rpar=1Meg noiseless +C12 N016 4 100f Rser=50Meg noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=100u linear Rout=100k en=10.6n enk=739 Vlow=-1e308 Vhigh=1e308 +C16 N013 6 2p +A5 N007 0 N012 N012 N012 N012 N013 N012 OTA g=12u iout=75u ref=272.26u Vhigh=1e308 Vlow=-1e308 +G1 4 N016 N013 N012 20n +C7 7 3 4.5p Rser=200 noiseless +C13 7 4 1000p +S1 N013 N012 0 N009 SHUT2 +C1 N006 0 15p +S4 N011 7 0 N009 SHUT1 +S2 4 N016 0 N009 SHUT1 +C8 2 3 .5p Rser=100 noiseless +G3 0 N007 N006 0 1m +L1 N007 0 219µ Cpar=440f Rser=1.1k Rpar=11k noiseless +D7 N013 N012 DLIM2 +R3 7 1 2Meg +R5 N015 1 10k +R6 7 8 2Meg +A6 N021 N015 0 0 0 0 N022 0 SCHMITT vt=1.2 vh=25m trise=.5u +R7 N021 8 10k +C4 7 2 4.5p Rser=200 noiseless +C5 3 4 4.5p Rser=200 noiseless +C6 2 4 4.5p Rser=200 noiseless +D2 2 3 DIN temp=27 +D4 N006 N017 DSL1 +A2 0 N018 0 0 0 0 N017 0 OTA g=2m linear Rout=1k Cout=10p Vlow=600m Vhigh=10 +D6 N005 N018 DD1 +C9 N018 0 10p +D9 N005 N018 DD2 +D11 N010 N005 DD1 +C15 N010 0 10p +D12 N010 N005 DD2 +A7 0 N010 0 0 0 0 N008 0 OTA g=2m linear Rout=1k Cout=10p Vlow=-10 Vhigh=-600m +D14 N008 N006 DSL1 +G5 0 N005 N004 0 10m +C17 N005 0 10p Rpar=100 +G6 0 N012 4 0 .5m +G7 0 N012 7 0 .5m +C19 N012 0 200p Rpar=1K noiseless +D15 7 4 DPOW +S3 4 7 0 N009 SOFPOW +I1 0 Vtemp 1m +R10 Vtemp 0 500 tc=5e-3 +R8 5 N025 10k +D16 1 N025 SD +D17 1 N025 RZ +D18 N015 N021 CZ +A8 N022 0 0 0 N024 0 N009 0 AND trise=5u tfall=2u +A9 Vtemp 0 0 0 0 N024 0 0 SCHMITT vt=855m vh=18m +A10 Vtemp 0 0 0 0 0 N020 0 SCHMITT Vt=782m vh=13m +S5 N025 4 N020 0 SWTF +C18 4 N025 500f +C20 1 4 500f Rpar=2Meg noiseless +C21 4 N021 500f +C22 N015 4 500f +D3 2 3 ZIN +D20 4 8 DESD +D19 4 1 DESD +D21 4 6 DESD +D22 4 5 DESD +D23 3 2 DIN temp=27 +B3 7 2 I=(.5+.5*tanh(V(7,2)/100m))*(.3p +24.5f*dnlim(V(7,4)-30,0,1)) +B4 7 3 I=(.5+.5*tanh(V(7,3)/100m))*(.3p +24.5f*dnlim(V(7,4)-30,0,1)) +.model DBIAS D(Ron=1Meg Roff=1T vfwd=.5 epsilon=1 vrev=6.7 revepsilon=100m ilimit=2.5p noiseless) +.model DIN D(Is=4e-20 N=1.2 IKF=1u Rs=1k) +.model DPOW D(Ron=100 Roff=1g vfwd=1 epsilon=100m ilimit=242u noiseless) +.model SOFPOW SW(Ron=100 Roff=1g vt=-.5 vh=-.1 ilimit=405u noiseless) +.model DESD D(Ron=100 Roff=1g vfwd=700m epsilon=100m noiseless) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model DD1 D(Ron=1k Roff=1g vfwd=150m epsilon=50m vrev=150m revepsilon=50m ilimit=3u revilimit=.1u noiseless ) +.model DD2 D(Ron=10k Roff=1Meg vfwd=1.4 epsilon=50m noiseless) +.model DD3 D(Ron=100k vfwd=200m epsilon=50m noiseless) +.model DSL1 D(Ron=100 Roff=1g Vfwd=150m epsilon=50m noiseless) +.model CZ D(Ron=100 Roff=1G Vfwd=.7 epsilon=100m Vrev=6 revepsilon=100m noiseless) +.model ZIN D(Ron=100 Roff=10T Vfwd=12 epsilon=100m Vrev=12 revepsilon=100m noiseless) +.model RZ D(Ron=10k Roff=1G vfwd=.7 epsilon=100m vrev=6 revepsilon=100m noiseless) +.model SWTF SW(level=2 Ron=30k Roff=1G vt=.5 vh=-.2 ilimit=164u noiseless) +.model SD D(Ron=500 Roff=1G Vfwd=500m epsilon=100m noiseless) +.model NI VDMOS(Vto=300m kp=200m Rd=19.2) +.model PI VDMOS(Vto=-300m Kp=200m Rd=39 pchan) +.model DLIM2 D(Ron=1k Roff=70Meg Vfwd=25 epsilon=.1 Vrev=25 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=1.235 Vrev=-300m epsilon=100m revepsilon=10m noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=1.235 Vrev=-300m epsilon=300m revepsilon=10m noiseless) +.ends LTC6090 +* +.subckt LTC6090-5 1 2 3 4 5 6 7 8 +A1 2 3 0 0 0 0 0 0 OTA g=0 in=1f +B1 0 N004 I=10u*dnlim(uplim(V(3),V(7)-2,.1), V(4)+2, .1)+1n*V(3) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(7)-1.99,.1), V(4)+1.99, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +M1 6 N017 4 4 NI temp=27 +C2 7 6 1p Rpar=1Meg noiseless +D5 N017 4 DLIMN1 +M2 6 N012 7 7 PI temp=27 +D8 7 N012 DLIMP1 +C3 7 N012 100f Rser=50Meg noiseless +A3 N013 N014 4 4 4 4 N012 4 OTA g=20n ref=-.45 linear vlow=-1e308 vhigh=1e308 +C11 6 4 1p Rpar=1Meg noiseless +C12 N017 4 100f Rser=50Meg noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=100u linear Rout=100k en=10.6n enk=739 Vlow=-1e308 Vhigh=1e308 +C16 N014 6 780f +A5 N008 0 N013 N013 N013 N013 N014 N013 OTA g=12u iout=75u ref=272.26u Vhigh=1e308 Vlow=-1e308 +G1 4 N017 N014 N013 20n +C7 7 3 4.5p Rser=200 noiseless +C13 7 4 1000p +S1 N014 N013 0 N010 SHUT2 +C1 N006 0 18p +S4 N012 7 0 N010 SHUT1 +S2 4 N017 0 N010 SHUT1 +C8 2 3 .5p Rser=100 noiseless +G3 0 N007 N006 0 1m +D7 N014 N013 DLIM2 +R3 7 1 2Meg +R5 N016 1 10k +R6 7 8 2Meg +A6 N022 N016 0 0 0 0 N023 0 SCHMITT vt=1.2 vh=25m trise=.5u +R7 N022 8 10k +C4 7 2 4.5p Rser=200 noiseless +C5 3 4 4.5p Rser=200 noiseless +C6 2 4 4.5p Rser=200 noiseless +D4 N006 N018 DSL1 +A2 0 N019 0 0 0 0 N018 0 OTA g=1.6m linear Rout=1k Cout=10p Vlow=600m Vhigh=10 +D6 N005 N019 DD1 +C9 N019 0 10p +D9 N005 N019 DD2 +D11 N011 N005 DD1 +C15 N011 0 10p +D12 N011 N005 DD2 +A7 0 N011 0 0 0 0 N009 0 OTA g=1.6m linear Rout=1k Cout=10p Vlow=-10 Vhigh=-600m +D14 N009 N006 DSL1 +G5 0 N005 N004 0 10m +C17 N005 0 10p Rpar=100 +G6 0 N013 4 0 .5m +G7 0 N013 7 0 .5m +C19 N013 0 200p Rpar=1K noiseless +D15 7 4 DPOW +S3 4 7 0 N010 SOFPOW +I1 0 Vtemp 1m +R10 Vtemp 0 500 tc=5e-3 +R8 5 N026 10k +D16 1 N026 SD +D17 1 N026 RZ +D18 N016 N022 CZ +A8 N023 0 0 0 N025 0 N010 0 AND trise=5u tfall=2u +A9 Vtemp 0 0 0 0 N025 0 0 SCHMITT vt=855m vh=18m +A10 Vtemp 0 0 0 0 0 N021 0 SCHMITT Vt=782m vh=13m +S5 N026 4 N021 0 SWTF +C18 4 N026 500f +C20 1 4 500f Rpar=2Meg noiseless +C21 4 N022 500f +C22 N016 4 500f +D3 2 3 ZIN +D20 4 8 DESD +D19 4 1 DESD +D21 4 6 DESD +D22 4 5 DESD +G2 0 N008 N007 0 1m +C23 N008 0 10p Rpar=1K noiseless +L1 N007 0 555µ Cpar=282f Rser=1.05k Rpar=21k noiseless +D1 2 3 DIN temp=27 +D2 3 2 DIN temp=27 +B3 7 2 I=(.5+.5*tanh(V(7,2)/100m))*(.3p +24.5f*dnlim(V(7,4)-30,0,1)) +B4 7 3 I=(.5+.5*tanh(V(7,3)/100m))*(.3p +24.5f*dnlim(V(7,4)-30,0,1)) +.model DBIAS D(Ron=1Meg Roff=1T vfwd=.5 epsilon=1 vrev=6.7 revepsilon=100m ilimit=2.5p noiseless) +.model DIN D(Is=4e-20 N=1.2 IKF=1u Rs=1k) +.model DPOW D(Ron=100 Roff=1g vfwd=1 epsilon=100m ilimit=245u noiseless) +.model SOFPOW SW(Ron=100 Roff=1g vt=-.5 vh=-.1 ilimit=405u noiseless) +.model DESD D(Ron=100 Roff=1g vfwd=700m epsilon=100m noiseless) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SWTF SW(level=2 Ron=30k Roff=1G vt=.5 vh=-.2 ilimit=164u noiseless) +.model SD D(Ron=500 Roff=1G Vfwd=500m epsilon=100m noiseless) +.model NI VDMOS(Vto=300m kp=200m Rd=19.2) +.model PI VDMOS(Vto=-300m Kp=200m Rd=39 pchan) +.model DLIM2 D(Ron=1k Roff=70Meg Vfwd=25 epsilon=.1 Vrev=25 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=1.235 Vrev=-300m epsilon=100m revepsilon=10m noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=1.235 Vrev=-300m epsilon=300m revepsilon=10m noiseless) +.model DD1 D(Ron=1k Roff=1g vfwd=150m epsilon=50m vrev=150m revepsilon=50m ilimit=3u revilimit=.1u noiseless ) +.model DD2 D(Ron=10k Roff=1Meg vfwd=1.4 epsilon=50m noiseless) +.model DD3 D(Ron=100k vfwd=200m epsilon=50m noiseless) +.model DSL1 D(Ron=100 Roff=1g Vfwd=130m epsilon=50m noiseless) +.model CZ D(Ron=100 Roff=1G Vfwd=.7 epsilon=100m Vrev=6 revepsilon=100m noiseless) +.model ZIN D(Ron=100 Roff=10T Vfwd=12 epsilon=100m Vrev=12 revepsilon=100m noiseless) +.model RZ D(Ron=10k Roff=1G vfwd=.7 epsilon=100m vrev=6 revepsilon=100m noiseless) +.ends LTC6090-5 +* +.subckt LT6110 1 2 3 4 5 6 7 +C5 4 2 10f +C7 N004 0 200f Rpar=100K noiseless +B1 N004 0 I=10u*dnlim(uplim(V(4),V(2)+.05,.01), V(5)+1.5, .1) +B2 0 N004 I=10u*dnlim(uplim(V(1),V(2)+.05,.01), V(5)+1.5, .1) +D1 N003 0 DLIM +D2 2 5 DP2 +R4 3 2 20m +C8 N003 0 800p +D3 N002 N007 DMAC Temp=27 +C9 N007 0 10n Rpar=1 +C11 N002 0 1p Rpar=3 +C12 N002 N007 50p +A3 0 N003 0 0 0 0 N002 0 OTA g=26m iout=300m Vhigh=1e308 Vlow=-1e308 +C1 4 5 360f Rser=2k +A5 0 N004 0 0 0 0 N005 0 OTA g=14m linear Rout=1k Cout=10p ref=85u Vlow=-1e308 Vhigh=1e308 +G2 0 N003 N005 0 1m +D8 N005 N010 DSLW +C2 2 1 10f +C3 1 5 360f Rser=3k +D10 4 5 DBIAS1 +D11 1 5 DBIAS1 +D9 N005 0 DSLW2 +A2 0 N009 0 0 0 0 N003 0 OTA g=10m asym isource=1u isink=-12u Vhigh=1e308 Vlow=-1e308 +G5 0 N009 N005 0 1µ +C15 N009 0 20p Rpar=1Meg +C4 N012 N014 1p +R1 N014 0 1 +D6 N011 0 DDEG1 +C13 N011 0 .02f +G4 0 N010 N011 0 2.1 +C6 N010 0 100f Rpar=1 +D7 N011 0 DDEG2 +C14 N012 0 10f Rpar=100 +G6 0 N011 N014 0 450m +D13 4 5 DBIAS2 +D14 1 5 DBIAS2 +D15 2 5 DP1 +D5 0 N002 DLIM2 +Q2 N017 N015 6 0 NPN1 Temp=27 +Q4 7 N015 6 0 NPN1 Temp=27 +A7 N017 7 2 2 2 2 N017 2 OTA g=10m iout=20m Rout=1Meg Cout=100f Vlow=-1e308 Vhigh=1e308 +D12 N017 2 DLIMC +C10 1 7 100f +A10 0 N007 N019 2 2 2 N015 2 OTA g=30m iout=70u vlow=-1e308 vhigh=-300m +C18 N015 5 1p Rpar=100Meg +A11 N018 7 1 1 1 1 N018 1 OTA g=10m iout=20m Rout=1Meg Cout=100f Vlow=-1e308 Vhigh=1e308 +D17 N018 1 DLIMC +A12 0 N007 N019 2 2 2 5 2 OTA g=800m iout=5m vlow=-1e308 vhigh=1e308 +A13 2 5 2 2 2 2 N019 2 SCHMITT vt=1.95 vh=10m trise=100u +Q6 N018 N015 6 0 NPN1 Temp=27 +G1 0 N012 1 5 1 +D4 6 N015 DCLMP +D16 5 7 DCLMP +D18 5 4 DCLMP +D19 5 1 DCLMP +D20 5 2 DCLMP +D21 5 6 DCLMP +D23 7 6 DBRK +D22 7 1 DCLMP +S1 N015 6 6 7 SSAT +.model NPN1 NPN BF=100 Is=1e-16 ise=2e-20 ne=1.5 tf=100p tr=1n Rb=100 Cjc=350f Cje=200f nf=1 BR=10 ikf=10m vaf=280 +.model DLIMC D(Ron=1 Roff=1g vfwd=-20m epsilon=100m) +.model SSAT SW(level=2 Ron=2k Roff=1g vt=-780m vh=-250m) +.model DHRM D(Ron=100 Roff=1G vfwd=-1 epsilon=100m) +.model DMAC D(Is=1e-16 N=1) +.model DLIM D(Ron=100 Roff=5Meg Vfwd=100 Vrev=1.5 epsilon=10m revepsilon=100m) +.model DLIM2 D(Ron=1 Roff=1g vfwd=0 epsilon=100m) +.model DP1 D(Ron=1k Roff=1G Vfwd=1 epsilon=100m ilimit=14.5u) +.model DP2 D(Ron=2.7Meg Roff=1G Vfwd=1 epsilon=100m ilimit=20u) +.model DDEG1 D(Ron=1 Roff=200k vfwd=0 epsilon=100m vrev=10 revepsilon=100m) +.model DDEG2 D(Ron=1k Roff=200k vfwd=100m epsilon=100m vrev=7 revepsilon=100m) +.model DCLMP D(Ron=20 Roff=1G vfwd=.75 epsilon=100m) +.model DSLW D(Ron=1 Roff=1Meg vfwd=800m epsilon=50m) +.model DSLW2 D(Ron=1 Roff=1G vfwd=400m vrev=200m epsilon=100m revepsilon=50m) +.model DBIAS1 D(Ron=1k Roff=1T vfwd=.7 epsilon=100m ilimit=34n) +.model DBIAS2 D(Ron=2G Roff=1T vfwd=.7 epsilon=100m) +.model DBRK D(Ron=100 Roff=1g vfwd=36.1 epsilon=100m) +.ends LT6110 +* +.subckt LT6118 1 2 3 4 5 6 7 8 +M2 6 N005 N006 N006 P temp=27 +C3 7 6 .1p +C4 6 4 .1p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(7)+.5,.1), V(4)-.5, .1) +B2 N003 0 I=10u*dnlim(uplim(V(8),V(7)+.51,.1), V(4)-.51, .1) +C10 N003 0 10f Rpar=100K noiseless +D7 7 4 DP +R1 8 N006 100 +D1 8 1 DINCL +D4 8 7 DESD +D5 1 7 DESD +D9 N005 N006 DZ6 +D10 N005 7 DZ34 +D6 4 8 DESD +D8 4 1 DESD +D11 4 6 DESD +M3 3 N015 4 4 N temp=27 +C1 7 8 .2p +C2 8 4 .2p +C5 7 1 .2p +C6 1 4 .2p +A3 0 N020 0 0 0 0 N016 0 OTA g=2m iout=200u Cout=30.8p Vlow=-1e308 Vhigh=1e308 +D15 4 2 DESD +D12 7 2 DLE +A8 0 N003 N004 4 4 4 N009 4 OTA g=5u iout=5u Cout=300f Vlow=-1e308 Vhigh=1e308 +A9 0 N009 4 4 4 4 N005 4 OTA g=100u linear Cout=7p Rout=10k Vlow=-1e308 Vhigh=1e308 +C7 N015 4 100f Rpar=10Meg +C11 3 4 4p +A1 0 N016 N011 4 4 4 N015 4 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +D17 N015 4 DNLIM +C12 3 N015 6f +D3 4 5 DESD +D20 N021 5 DCBIAS +A13 7 4 4 4 4 4 N004 4 SCHMITT Vt=2.5 Vh=10m trise=10n +S3 N009 7 4 N004 ISHD +D24 N009 7 XU +D25 4 N009 XD +A15 N004 4 4 4 4 4 N011 4 BUF trise=30u +S2 7 4 N011 4 IQ +D16 8 N008 DABI +S1 N008 4 N011 4 SWB +S4 N021 4 N011 4 SWB +C18 4 2 2p +C19 4 5 2p +C22 N008 4 2p +D18 1 N008 DABI +R3 7 N008 457k +A12 4 N014 4 5 4 N017 4 4 OR Ref=.39 Trise=700n Tfall=100n +C9 N020 0 1p Rpar=100k +G1 0 N020 5 4 10µ +I1 N020 0 3.947µ +D2 0 N018 DLAT1 +C13 N018 0 150p +A5 0 N016 0 0 0 0 N018 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +G3 N016 0 N017 4 1m +D14 0 N016 DLAT +S5 7 4 N015 4 SCB +A2 2 4 4 4 4 4 N014 4 SCHMITT trise=500n vt=1 vh=.5 +A4 0 N018 0 0 0 0 N016 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +C8 N021 4 10f +.model DINCL D(Ron=6k Roff=100G Vfwd=.7 Vrev=.7 epsilon=.5 revepsilon=.5) +.model DESD D(Ron=500 Roff=100G Vfwd=.7 epsilon=.5) +.model DZ34 D(Ron=100 Roff=10Meg Vfwd=.7 Vrev=34.1 epsilon=.5 revepsilon=.5) +.model DZ6 D(Ron=100 Roff=100G Vfwd=.7 Vrev=6 epsilon=.5 revepsilon=.5) +.model DLE D(Ron=100k Vfwd=.5 epsilon=.3 ilimit=100n) +.model DABI D(Ron=10k Roff=1g Vfwd=.3 epsilon=.1 ilimit=60n) +.model DCBIAS D(Ron=200k Roff=1T Vfwd=-.45 epsilon=.15 ilimit=12n) +.model SWB SW(Vt=.5 Vh=-.1 Ron=1k Roff=1T level=2) +.model SCB SW(level=2 Vt=.3 Vh=-.1 Ron=10K Roff=1G ilimit=75u) +.model DLAT D(Ron=1 Roff=100k Vfwd=1 Vrev=1 epsilon=90m revepsilon=90m) +.model DLAT1 D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1) +.model DNLIM D(Ron=100 Roff=1G Vfwd=1 Vrev=20m epsilon=.1 revepsilon=10m) +.model XU D(Ron=1K Roff=400G Vfwd=1 epsilon=.1) +.model XD D(Ron=1K Roff=200G Vfwd=1 epsilon=.1) +.model IQ SW(Vt=.5 Vh=-.3 Ron=100 Roff=1G ilimit= 420.8u level=2) +.model ISHD SW(Vt=-.5 Vh=-.3 Ron=1 Roff=400G) +.model N VDMOS(Vto=20m Kp=800m Rd=105) +.model P VDMOS(Vto=-1 Kp=100m Cgs=1f cgdmin=.1f cgdmax=.2f subthres=100u rds=1g pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 epsilon=.5 ilimit=2.7u) +.ends LT6118 +* +.subckt LT6119-1 1 2 3 4 5 6 7 8 9 10 +M2 8 N005 N006 N006 P temp=27 +C3 9 8 .1p +C4 8 5 .1p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(9)+.5,.1), V(5)-.5, .1) +B2 N003 0 I=10u*dnlim(uplim(V(10),V(9)+.51,.1), V(5)-.51, .1) +C10 N003 0 10f Rpar=100K noiseless +D7 9 5 DP +R1 10 N006 100 +D1 10 1 DINCL +D4 10 9 DESD +D5 1 9 DESD +D9 N005 N006 DZ6 +D10 N005 9 DZ34 +D6 5 10 DESD +D8 5 1 DESD +D11 5 8 DESD +M3 4 N016 5 5 N temp=27 +C1 9 10 2p +C2 10 5 2p +C5 9 1 2p +C6 1 5 2p +A3 0 N025 0 0 0 0 N019 0 OTA g=2m asym isource=200u isink=-1u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D13 0 N019 DLAT +D14 0 N028 DLAT1 +C8 N028 0 150p +D15 5 2 DESD +D12 9 2 DLE +A8 0 N003 N004 5 5 5 N009 5 OTA g=5u iout=5u Cout=300f Vlow=-1e308 Vhigh=1e308 +A9 0 N009 5 5 5 5 N005 5 OTA g=100u linear Cout=7p Rout=10k Vlow=-1e308 Vhigh=1e308 +C7 N016 5 100f Rpar=10Meg +C11 4 5 4p +A1 0 N019 N011 5 5 5 N016 5 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +D17 N016 5 DNLIM +C12 4 N016 6f +D2 5 7 DESD +D3 5 6 DESD +D19 N021 7 DCBIAS +D20 N021 6 DCBIAS +M4 3 N026 5 5 N temp=27 +C15 N026 5 100f Rpar=10Meg +C16 3 5 4p +D23 N026 5 DNLIM +C17 3 N026 6f +A13 9 5 5 5 5 5 N004 5 SCHMITT Vt=2.5 Vh=10m trise=10n +S3 N009 9 5 N004 ISHD +D24 N009 9 XU +D25 5 N009 XD +A15 N004 5 5 5 5 5 N011 5 BUF trise=30u +S2 9 5 N011 5 IQ +D16 10 N008 DABI +S1 N008 5 N011 5 SWB +S4 N021 5 N011 5 SWB +C18 5 2 2p +C19 5 6 2p +C20 5 7 10f +C21 5 N021 10f +C22 N008 5 2p +D18 1 N008 DABI +R3 9 N008 457k +A12 N014 5 5 6 5 N018 5 5 OR Ref=.39 Trise=700n Tfall=100n +A16 0 N019 0 0 0 0 N028 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +C9 N025 0 1p Rpar=100k +G1 0 N025 6 5 10µ +I1 N025 0 3.947µ +G2 N019 0 N018 5 1m +A7 0 N023 N011 5 5 5 N026 5 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +A10 0 N028 0 0 0 0 N019 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +A11 0 N024 0 0 0 0 N023 0 OTA g=2m asym isource=200u isink=-1u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D21 0 N023 DLAT +C13 N024 0 1p Rpar=100k +I2 0 N024 4.053µ +G4 N023 0 N017 5 1m +G3 N024 0 7 5 10µ +D22 0 N029 DLAT1 +C14 N029 0 150p +A17 0 N023 0 0 0 0 N029 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +A18 0 N029 0 0 0 0 N023 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +S5 9 5 N016 5 SCB +S6 9 5 N026 5 SCB +A2 2 5 5 5 5 N015 N014 5 SCHMITT trise=500n vt=1 vh=.5 +A4 N015 5 5 7 5 5 N017 5 AND Ref=.41 Trise=1n Tfall=10n +.model XU D(Ron=1K Roff=400G Vfwd=1 epsilon=.1) +.model XD D(Ron=1K Roff=200G Vfwd=1 epsilon=.1) +.model IQ SW(Vt=.5 Vh=-.3 Ron=100 Roff=1G ilimit= 467u level=2) +.model ISHD SW(Vt=-.5 Vh=-.3 Ron=1 Roff=400G) +.model N VDMOS(Vto=20m Kp=800m Rd=105) +.model P VDMOS(Vto=-1 Kp=100m Cgs=1f cgdmin=.1f cgdmax=.2f subthres=100u rds=1g pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 epsilon=.5 ilimit=2.7u) +.model DLAT D(Ron=1 Roff=100k Vfwd=1 Vrev=1 epsilon=90m revepsilon=90m) +.model DLAT1 D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1) +.model DNLIM D(Ron=100 Roff=1G Vfwd=1 Vrev=20m epsilon=.1 revepsilon=10m) +.model DABI D(Ron=10k Roff=1g Vfwd=.3 epsilon=.1 ilimit=60n) +.model DCBIAS D(Ron=200k Roff=1T Vfwd=-.45 epsilon=.15 ilimit=12n) +.model SWB SW(Vt=.5 Vh=-.1 Ron=1k Roff=1T level=2) +.model SCB SW(level=2 Vt=.3 Vh=-.1 Ron=10K Roff=1G ilimit=75u) +.model DINCL D(Ron=6k Roff=100G Vfwd=.7 Vrev=.7 epsilon=.5 revepsilon=.5) +.model DESD D(Ron=500 Roff=100G Vfwd=.7 epsilon=.5) +.model DZ34 D(Ron=100 Roff=10Meg Vfwd=.7 Vrev=34.1 epsilon=.5 revepsilon=.5) +.model DZ6 D(Ron=100 Roff=100G Vfwd=.7 Vrev=6 epsilon=.5 revepsilon=.5) +.model DLE D(Ron=100k Vfwd=.5 epsilon=.3 ilimit=100n) +.ends LT6119-1 +* +.subckt LT6119-2 1 2 3 4 5 6 7 8 9 10 +M2 8 N005 N006 N006 P temp=27 +C3 9 8 .1p +C4 8 5 .1p +B1 0 N003 I=10u*dnlim(uplim(V(1),V(9)+.5,.1), V(5)-.5, .1) +B2 N003 0 I=10u*dnlim(uplim(V(10),V(9)+.51,.1), V(5)-.51, .1) +C10 N003 0 10f Rpar=100K noiseless +D7 9 5 DP +R1 10 N006 100 +D1 10 1 DINCL +D4 10 9 DESD +D5 1 9 DESD +D9 N005 N006 DZ6 +D10 N005 9 DZ34 +D6 5 10 DESD +D8 5 1 DESD +D11 5 8 DESD +M3 4 N015 5 5 N temp=27 +C1 9 10 .2p +C2 10 5 .2p +C5 9 1 .2p +C6 1 5 .2p +A3 0 N022 0 0 0 0 N017 0 OTA g=2m asym isource=200u isink=-1u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D13 0 N017 DLAT +D14 0 N027 DLAT1 +C8 N027 0 150p +D15 5 2 DESD +D12 9 2 DLE +A8 0 N003 N004 5 5 5 N009 5 OTA g=5u iout=5u Cout=300f Vlow=-1e308 Vhigh=1e308 +A9 0 N009 0 0 0 0 N005 0 OTA g=100u linear Cout=7p Rout=10k Vlow=-1e308 Vhigh=1e308 +C7 N015 5 100f Rpar=10Meg +C11 4 5 4p +A1 0 N017 N011 5 5 5 N015 5 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +D17 N015 5 DNLIM +C12 4 N015 6f +D2 5 7 DESD +D3 5 6 DESD +D19 N020 7 DCBIAS +D20 N020 6 DCBIAS +M4 3 N025 5 5 N temp=27 +C15 N025 5 100f Rpar=10Meg +C16 3 5 4p +D23 N025 5 DNLIM +C17 3 N025 6f +A13 9 5 5 5 5 5 N004 5 SCHMITT Vt=2.5 Vh=10m trise=10n +S3 N009 9 5 N004 ISHD +D24 N009 9 XU +D25 5 N009 XD +A15 N004 5 5 5 5 5 N011 5 BUF td=7u trise=30u +S2 9 5 N011 5 IQ +D16 10 N008 DABI +S1 N008 5 N011 5 SWB +S4 N020 5 N011 5 SWB +C18 5 2 2p +C19 5 6 2p +C20 5 7 10f +C21 5 N020 10f +C22 N008 5 2p +D18 1 N008 DABI +R3 9 N008 457k +A16 0 N017 0 0 0 0 N027 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +C9 N022 0 1p Rpar=100k +G1 0 N022 6 5 10µ +I1 N022 0 3.947µ +G2 N017 0 N016 5 1m +A7 0 N023 N011 5 5 5 N025 5 OTA g=2u ref=-90m asym isource=330n isink=-10u Vlow=-1e308 Vhigh=1e308 +A10 0 N027 0 0 0 0 N017 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +A5 0 N024 0 0 0 0 N023 0 OTA g=2m asym isource=200u isink=-1u Vlow=-1e308 Vhigh=1e308 Cout=30.8p +D21 0 N023 DLAT +D22 0 N028 DLAT1 +C13 N028 0 150p +A14 0 N023 0 0 0 0 N028 0 OTA g=20m asym isource=10m isink=-34u Vlow=-1e308 Vhigh=1e308 ref=-10m +C14 N024 0 1p Rpar=100k +G3 0 N024 7 5 10µ +I2 N024 0 3.947µ +G4 N023 0 N019 5 1m +A17 0 N028 0 0 0 0 N023 0 OTA g=10m asym isource=400u isink=-10u Vlow=-1e308 Vhigh=1e308 +A2 2 5 5 5 5 5 N012 5 SCHMITT trise=500n vt=1 vh=.5 +A4 N012 5 5 6 5 N016 5 5 OR Ref=.39 Trise=700n Tfall=100n +A6 N012 5 5 5 7 N019 5 5 OR Ref=.39 Trise=700n Tfall=100n +.model DINCL D(Ron=6k Roff=100G Vfwd=.7 Vrev=.7 epsilon=.5 revepsilon=.5) +.model DESD D(Ron=500 Roff=100G Vfwd=.7 epsilon=.5) +.model DZ34 D(Ron=100 Roff=10Meg Vfwd=.7 Vrev=34.1 epsilon=.5 revepsilon=.5) +.model DZ6 D(Ron=100 Roff=100G Vfwd=.7 Vrev=6 epsilon=.5 revepsilon=.5) +.model DLE D(Ron=100k Vfwd=.5 epsilon=.3 ilimit=100n) +.model DABI D(Ron=10k Roff=1g Vfwd=.3 epsilon=.1 ilimit=60n) +.model DCBIAS D(Ron=200k Roff=1T Vfwd=-.45 epsilon=.15 ilimit=12n) +.model SWB SW(Vt=.5 Vh=-.1 Ron=1k Roff=1T level=2) +.model SCB SW(level=2 Vt=.3 Vh=-.1 Ron=10K Roff=1G ilimit=75u) +.model DLAT D(Ron=1 Roff=100k Vfwd=1 Vrev=1 epsilon=90m revepsilon=90m) +.model DLAT1 D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1) +.model DNLIM D(Ron=100 Roff=1G Vfwd=1 Vrev=20m epsilon=.1 revepsilon=10m) +.model XU D(Ron=1K Roff=400G Vfwd=1 epsilon=.1) +.model XD D(Ron=1K Roff=200G Vfwd=1 epsilon=.1) +.model IQ SW(Vt=.5 Vh=-.3 Ron=100 Roff=1G ilimit= 467u level=2) +.model ISHD SW(Vt=-.5 Vh=-.3 Ron=1 Roff=400G) +.model N VDMOS(Vto=20m Kp=800m Rd=105) +.model P VDMOS(Vto=-1 Kp=100m Cgs=1f cgdmin=.1f cgdmax=.2f subthres=100u rds=1g pchan) +.model DP D(Roff=1T Ron=100 Vfwd=0.5 epsilon=.5 ilimit=2.7u) +.ends LT6119-2 +* +.subckt LTC2066 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +M1 5 NG 4 4 NI temp=27 M=10 +C2 3 5 10p Rpar=1G noiseless +D5 NG 4 DLIMNP +M2 5 PG 3 3 PI temp=27 M=10 +D9 XC 0 DLIM +C13 3 4 10p +C1 X1 0 900p Rpar=1k noiseless +C17 4 6 500f +S4 PG 3 0 N006 SHUT1 +S2 4 NG 0 N006 SHUT1 +S7 3 4 SS 0 SPOW +L1 X2 0 3.36m Cpar=61.9p Rser=1.48k Rpar=3.08k noiseless +A2 6 4 0 0 0 0 N006 0 SCHMITT trise=10u vt=.8 vh=10m +D2 3 6 DSHUT +D6 2 3 DESD +D7 4 2 DESD +D10 1 3 DESD +D11 4 1 DESD +A1 2 1 0 0 0 0 0 0 OTA g=0 in=35f*(1+freq/45k)**2.2/(1+freq/1Meg)**3 +A6 0 XC 4 4 4 4 NG 4 OTA g=80n linear ref=55.12m vlow=0 vhigh=2.5 +S1 XC 0 4 3 SNLG +G1 0 N009 5 Mid 10m +R3 N009 0 1K noiseless +C8 XC N009 173p +C12 2 1 3.3p Rser=100k noiseless +C3 NG 4 400f Rser=25Meg noiseless +D12 4 6 DESD2 +C6 2 4 1.75p Rser=100k noiseless +D1 6 3 DESD2 +A4 N004 0 0 0 0 0 X1 0 OTA g=1m linear en=85n*(1+freq/4k)**1.5/(((1+uplim(freq,50k,5k)/85k)**6)*(1+freq/110k)**2) Vhigh=1e308 Vlow=-1e308 +C4 1 4 1.75p Rser=100k noiseless +C5 3 1 1.75p Rser=100k noiseless +C7 3 2 1.75p Rser=100k noiseless +G4 3 PG 4 PG 1m vto= 0 dir=1 +G2 NG 4 NG 3 1m vto=0 dir=1 +A5 N006 0 0 0 0 0 SS 0 BUF Rout=10Meg Cout=20p +A7 0 X2 0 0 0 0 XC 0 OTA g=100u iout=5u Cout=1p Vhigh=1e308 Vlow=-1e308 +S3 0 XC 0 N006 SHUT2 +D3 3 4 DLK +A8 0 X1 0 0 0 0 X2 0 OTA g=1m iout=31u vlow=-1e308 vhigh=1e308 +B3 0 XC I=uplim(dnlim(1-dnlim(10*(V(XC)+200m),0,100m),0,100m)*dnlim(20u*(V(X1)-100m),0,.1u),10u,1u) +B4 XC 0 I=uplim(dnlim(1-dnlim(-10*(V(XC)-200m),0,100m),0,100m)*dnlim(20u*(-100m-V(X1)),0,.1u),15u,1u) +A3 N005 0 3 3 3 3 PG 3 OTA g=10n linear ref=-900m vlow=-3.5 vhigh=0 +G3 0 N005 4 NG 1µ +C9 N005 0 400f Rser=2Meg Rpar=1Meg noiseless +C11 5 4 10p Rpar=1G noiseless +C14 3 PG 50f Rser=60Meg noiseless +L2 N009 0 50µ Rser=100 noiseless +G5 0 Mid 3 0 .5m +G6 0 Mid 4 0 .5m +R4 Mid 0 1K noiseless +D4 3 PG DLIMNP +G8 3 PG NG 4 1m vto=550m dir=1 +.model DSHUT D(Ron=85k Roff=1G Vfwd=.1 epsilon=50m ilimit=50n noiseless) +.model SPOW SW(level=2 Ron=1k Roff=10G vt=.5 vh=-200m ilimit=5.883u noiseless) +.model DLK D(Ron=1Meg Roff=1Meg ilimit=35n noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m noiseless) +.model SHUT2 SW(Ron=1k Roff=10G vt=-.8 vh=-100m noiseless) +.model SNLG SW(level=2 Ron=19Meg Roff=455Meg vt=-1 vh=-1.5 noiseless) +.model SOD SW(level=2 Ron= 600k Roff=20Meg vt=2 vh=-1 noiseless) +.model PI VDMOS(kp=950u vto=-500m mtriode=1.5 ksubthres=50m pchan noiseless) +.model NI VDMOS(kp=1.8m vto=500m mtriode=1.5 ksubthres=50m noiseless) +.model DLIM D(Ron=1k Roff=1g Vfwd=4.2 Vrev=4.2 epsilon=100m revepsilon=100m noiseless) +.model DESD D(Ron=100 Roff=10T Vfwd=1.4 epsilon=200m noiseless) +.model DESD2 D(Ron=100 Roff=10T Vfwd=600m epsilon=200m noiseless) +.param vs=5 +.param RL=499k +.param CL=1f +.model DLIMNP D(Ron=800Meg Roff=100Meg vfwd=500m epsilon=50m noiseless) +.ends LTC2066 +* +.subckt LT6376 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +A1 INM INP 0 0 0 0 0 0 OTA g=0 in=300f ink=8 +C7 9 INP 2.5p Rser=1k Rpar=100G noiseless +D8 15 INP DESD +D10 15 INM DESD +GNOI INP INM N011 0 1µ +S9 0 N011 9 INM SNOI +A6 15 9 0 0 0 0 N018 0 OTA g=2u iout=1u ref=-2.5 Rout=1Meg Cout=100f vlow=-1e308 vhigh=1e308 +S4 N009 15 On 0 SBiasN +D13 9 N009 DBiasDrop +D14 INM N009 DBiasOTT +D15 INP N009 DBiasOTT +C14 N009 15 100f +D16 INM INP D1Meg +C17 8 INM 1p +R1 12 INM 19K +R2 11 INM 38K +R3 10 INM 23.75K +R4 INP 3 19K +R5 INP 4 38K +R6 INP 5 23.75K +A8 N018 0 0 N020 0 0 On 0 AND trise=35u +B1 0 X0 I=10u*dnlim(uplim(V(INP),V(15)+76.1,.1), V(15)-.15, .1)+1n*V(INP)-11.6548n +B2 X0 0 I=10u*dnlim(uplim(V(INM),V(15)+76.1,.1), V(15)-.16, .1)+1n*V(INM) +C1 X0 0 50f Rpar=100K noiseless +M1 N015 N014 15 15 NI temp=27 +C2 9 8 1p Rpar=1g noiseless +D1 N014 15 DLIMN1 +M2 8 N007 9 9 PI temp=27 +A3 N010 N012 15 15 15 15 N007 15 OTA g=2u ref=-.305 linear vlow=-1e308 vhigh=1e308 +C5 8 15 1p Rpar=1g noiseless +D2 N014 15 DLIMN2 +C11 N012 8 250f +A5 N005 0 N010 N010 N010 N010 N012 N010 OTA g=25u linear Vlow=-1e308 Vhigh=1e308 +G1 15 N014 N012 N010 140n +D3 N012 N010 DLIM +C12 9 15 10p +G2 0 N010 15 0 .5m +G3 0 N010 9 0 .5m +C15 N010 0 200p Rpar=1K noiseless +D5 9 N007 DLIMP +D6 N003 0 DLIM0 +D7 15 8 DESD +D9 8 N015 DNR +C18 N015 15 100f Rpar=10Meg noiseless +D11 N007 9 DLIMPR +S1 9 N007 0 On SHUT +S2 N014 15 0 On SHUT +G4 0 N004 N003 0 1µ +C20 N005 0 25f noiseless Rpar=1Meg +G5 0 N005 N004 0 1µ +S3 N010 N012 15 8 SGK +C4 9 INM 2.5p Rser=1k Rpar=100G noiseless +C6 INP 15 2.5p Rser=1k Rpar=100G noiseless +C8 INM 15 2.5p Rser=1k Rpar=100G noiseless +C21 15 10 500f +C29 15 INM 10p Rser=1k noiseless +C3 9 N007 1p Rser=300k noiseless +C10 N014 15 1p Rser=700k noiseless +C22 15 11 500f +C23 15 12 500f +C24 15 3 500f +C25 15 4 500f +C26 15 5 500f +C27 15 INP 10p Rser=1k noiseless +R7 N021 6 380K +R8 INP N021 380K +C28 N021 15 2p +C32 INM INP 2p +R10 N008 14 38K +R11 INM N008 38K +C33 N008 15 1.2p +R12 N017 1 38K +R15 INP N017 38K +C34 N017 15 1.2p +A2 N011 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=8 +S5 0 N006 9 INM SNOI +A9 N006 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=5 +GNOI_V1 X0 0 N006 0 10n +D18 9 7 DST +A10 7 9 0 0 0 0 N020 0 SCHMITT vt=-1.85 vh=-.4 trise=1u +A7 0 X0 On 0 0 0 N003 0 OTA g=1m linear en=17n enk=3 vlow=-1e308 vhigh=1e308 +B3 9 15 I=(.5+.5*tanh((V(On)-.5)/100m))*(41.5u-.762u*V(9,15)) +R16 9 15 5Meg noiseless +D4 9 15 DLK +C16 INP 6 1p +C35 6 15 1p +R13 N001 INM 380K +R14 8 N001 380K +C30 N001 15 2p +C19 N004 0 200f noiseless Rser=2.667Meg Rpar=1Meg +C13 N003 0 25f +.model DESD D(Ron=1k Roff=1G vfwd=700m epsilon=100m noiseless) +.model SNOI SW(Ron=1 Roff=1Meg vt=1.2 vh=-100m noiseless) +.model DST D(Ron=200 Roff=1G vfwd=100m epsilon=-100m ilimit=10u noiseless) +.model DLK D(Ron=10k Roff=1G vfwd=1 epsilon=500m ilimit=3.4u noiseless) +.model NI VDMOS(Vto=300m kp=60m Mtriode=.9 lambda=.01 noiseless) +.model PI VDMOS(Vto=-300m Kp=120m lambda=.01 mtriode=.17 pchan is=0 noiseless) +.model DLIM0 D(Ron=1 Roff=1.3k Vfwd=28m epsilon=10m Vrev=28m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=8Meg Vfwd=900m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.model SHUT SW(level=2 Ron=10k Roff=100G vt=-.5 vh=-.2 noiseless) +.model DNR D(Ron=10 Roff=1G Vfwd=2m epsilon=10m noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.2 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=44n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=840m epsilon=10m noiseless) +.model DLIMPR D(Ron=5Meg Roff=1G Vfwd=100m epsilon=10m noiseless) +.model SGK SW(level=2 Ron=65k Roff=100G vt=-260m vh=150m oneway epsilon=10m noiseless) +.model SBiasN SW(level=2 Ron=10k Roff=1g vt=.5 vh=-.2 ilimit=28u noiseless) +.model DBiasDrop D(Ron=1k Roff=1G vfwd=2.27 epsilon=500m noiseless) +.model DBiasOTT D(Ron=500 Roff=1G vfwd=700m epsilon=200m noiseless) +.model D1Meg D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=10n revilimit=10n noiseless) +.ends LT6376 +* +.subckt LTC6115 1 2 3 4 5 6 7 8 9 10 11 12 +D14 1 12 DINI +A1 0 X0 0 0 0 0 X1 0 OTA g=8m linear Vlow=-1e308 Vhigh=1e308 +D15 XGN 0 DLIM2 +M3 3 PG 1 1 PII temp=27 +C22 1 PG 10f Rpar=1Meg noiseless +C27 XGN 0 1.5n Rpar=100Meg noiseless +B3 X0 0 I=10u*dnlim(uplim(V(1),V(11)+.31,.1), V(11)-uplim(.4*V(11,4)-.59,1.91,.1), .1)+1n*V(1) +B4 0 X0 I=10u*dnlim(uplim(V(12),V(11)+.3,.1), V(11)-uplim(.4*V(11,4)-.6,1.9,.1), .1)+1n*V(12) +D17 1 11 D10Z +D16 11 1 D3D +D18 4 3 D10Z +C28 3 4 1p +G7 PG 1 N002 0 1µ +B5 0 N002 I=1u*uplim(-V(XGN)+60m,70m*V(11,4)+300m,10m) +C29 N002 0 1f Rpar=1Meg noiseless +B6 PG 1 I=290n + 1.1n*uplim(V(11,4),10,2) +C12 11 1 1p Rser=100 noiseless +C20 1 4 1p Rser=100 noiseless +C23 11 12 1p Rser=100 noiseless +C24 12 4 1p Rser=100 noiseless +D20 1 4 DBIAS +D21 12 4 DBIAS +D22 11 4 DPI1 +D23 11 4 DPI2 +C25 11 4 10p Rpar=635k noiseless +D24 3 1 DESD +C26 1 3 1p +C14 X1 0 300p Rpar=1k noiseless +A4 0 X0 0 0 0 0 X1A 0 OTA g=800m linear Vlow=-1e308 Vhigh=1e308 +R5 X1A 0 10 noiseless +A6 0 X1 0 0 0 0 XGN 0 OTA g=625u linear vlow=-1e308 vhigh=1e308 +D19 X1A X1 DLS +D25 X0 0 DSlewB1 +C19 X0 0 1f Rpar=1Meg noiseless +D26 X0 0 DSlewB2 +D27 1 PG DgainKill +D1 VINPV 7 DESD +D2 4 VINPV DESD +D3 5 7 DESD +D4 4 5 DESD +C1 VINPV 5 1p Rser=100 noiseless +R1 VINPV 9 975K +R2 VINPV 4 25K +C2 7 5 5p Rser=100 noiseless +D5 4 9 DFBBRK +D6 VINPV 5 DIN +C3 5 4 5p Rser=100 noiseless +C4 7 VINPV 5p Rser=100 noiseless +C5 VINPV 4 5p Rser=100 noiseless +D7 4 6 DOUTVBRK +D8 6 7 DESD +C6 7 4 100p +D9 7 4 DP +R4 7 Mid 10Meg noiseless +R7 Mid 4 10Meg noiseless +A2 N010 0 0 0 0 0 N008 0 OTA g=384u iout=5.3u Vhigh=1e308 Vlow=-1e308 +D10 N008 0 DLIM +C9 N009 0 4p Rpar=1Meg noiseless +G1 0 N010 N009 0 1m +L1 N010 0 1.8m Cpar=143f Rser=1.02k Rpar=51k noiseless +A3 0 N007 0 0 0 0 N009 0 OTA g=1u linear en=22.9n*(1+3.5/MAX(freq,.01))**.5 enk=40 Vlow=-22m Vhigh=22m +G2 0 N016 6 Mid 100m +C10 N016 0 1p Rpar=10 noiseless +M1 6 N015 4 4 NI temp=27 +C11 7 6 1p Rpar=10Meg noiseless +M2 6 N011 7 7 PI temp=27 +C13 6 4 1p Rpar=10Meg noiseless +D11 7 N011 DLIMP +D12 N015 4 DLIMN +D13 7 N015 DBIASO +D28 N011 4 DBIASO +C15 7 N011 150f Rser=400k noiseless +G3 4 N015 N008 0 500n +G4 7 N011 N008 0 500n +C16 N015 4 150f Rser=400k noiseless +B1 0 N007 I=10u*dnlim(uplim(V(VINPV),V(7)-1.2,.1), V(4)-.2, .1)+1n*V(VINPV) -49.76p +B2 N007 0 I=10u*dnlim(uplim(V(5),V(7)-1.19,.1), V(4)-.21, .1)+1n*V(5) +C7 N007 0 1f Rpar=100K noiseless +C17 N008 N016 80p Rser=1k noiseless +.model DFBBRK D(Ron=100 Roff=1G vfwd=600m epsilon=500m vrev=105.1 revepsilon=500m noiseless) +.model DOUTVBRK D(Ron=100 Roff=1G vfwd=600m epsilon=500m vrev=6.1 revepsilon=500m noiseless) +.model DIN D(Ron=100 Roff=10T vfwd=600m epsilon=500m vrev=600m revepsilon=500m noiseless) +.model D3D D(Ron=5k Roff=1G vfwd=1.8 epsilon=1.2 noiseless) +.model D10Z D(Ron=100 Roff=1G vfwd=600m epsilon=500m vrev=10.1 revepsilon=500m noiseless) +.model DBIAS D(Ron=1k Roff=1T vfwd=600m epsilon=500m ilimit=85n noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DPI1 D(Ron=500 Roff=1G vfwd=3 epsilon=500m ilimit=231.4u noiseless) +.model DPI2 D(Ron=50K vfwd=4.8 epsilon=500m ilimit=10.5u noiseless) +.model DINI D(Ron=10k Roff=10T vfwd=600m epsilon=500m vrev=600m revepsilon=500m noiseless) +.model DLS D(Ron=10 Roff=100Meg vfwd=50m epsilon=10n vrev=50m revepsilon=10m noiseless) +.model DLIM2 D(Ron=10 Roff=100Meg, vfwd=10m epsilon=20m vrev=990m revepsilon=100m noiseless) +.model PII VDMOS(Vto=-300m Kp=100m Is=0 Rs=50 pchan noiseless) +.model DSlewB1 D(Roff=125k Ron=200k vfwd=20m epsilon=3m vrev=20m revepsilon=3m noiseless) +.model DSlewB2 D(Roff=500k Ron=10K vfwd=200m epsilon=100m vrev=200m revepsilon=100m noiseless) +.model DgainKill D(Ron=1Meg Roff=2Meg vfwd=350m epsilon=100m noiseless) +.model NI VDMOS(Vto=300m kp=25m mtriode=.5 subthres=40u lambda=.01 noiseless) +.model PI VDMOS(Vto=-300m Kp=20m mtriode=.65 subthres=40u lambda=.01 pchan noiseless) +.model DLIM D(Ron=10k Roff=500Meg Vfwd=4 Vrev=4 epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DBIAS D(Ron=1g Roff=1T epsilon=.3 ilimit=.2p noiseless) +.model DP D(Ron=10k Roff=1g Vfwd=.5 epsilon=.1 ilimit=36.65u noiseless) +.model DLIMN D(Ron=1k Roff=1Meg Vfwd=1.8 epsilon=.1 noiseless) +.model DLIMP D(Ron=1k Roff=1Meg Vfwd=1.8 epsilon=10m noiseless) +.model DBIASO D(Ron=10k Roff=1G vfwd=1 epsilon=300m ilimit=303n noiseless) +.ends LTC6115 diff --git a/spice/copy/sub/LTC5505-1.sub b/spice/copy/sub/LTC5505-1.sub new file mode 100755 index 0000000..073a5d1 Binary files /dev/null and b/spice/copy/sub/LTC5505-1.sub differ diff --git a/spice/copy/sub/LTC5505-2.sub b/spice/copy/sub/LTC5505-2.sub new file mode 100755 index 0000000..6ef66c8 Binary files /dev/null and b/spice/copy/sub/LTC5505-2.sub differ diff --git a/spice/copy/sub/LTC5507.sub b/spice/copy/sub/LTC5507.sub new file mode 100755 index 0000000..d918a7e Binary files /dev/null and b/spice/copy/sub/LTC5507.sub differ diff --git a/spice/copy/sub/LTC5532.sub b/spice/copy/sub/LTC5532.sub new file mode 100755 index 0000000..e383145 Binary files /dev/null and b/spice/copy/sub/LTC5532.sub differ diff --git a/spice/copy/sub/LTC6.lib b/spice/copy/sub/LTC6.lib new file mode 100755 index 0000000..ee05af2 --- /dev/null +++ b/spice/copy/sub/LTC6.lib @@ -0,0 +1,2213 @@ +* Copyright © Linear Technology Corp. 2008, 2009, 2010. All rights reserved. +* +.subckt LT6703-2 1 2 3 4 +B2 N002 0 I=100u*dnlim(uplim(V(3),V(2)+18.6,.1), V(2)-.4, .1)- 424n*V(VINT) -39.568u -100u*V(2) +A1 0 N002 0 0 0 0 VINT 0 OTA g=4.7u asym isource=9u isink=-1.1u Vlow=-1e308 Vhigh=1e308 Cout=25p +C2 N006 0 500f +M1 N007 N006 2 2 NOUT temp=27 +C5 4 1 .5p +C6 1 2 5p +D5 0 VINT DLAT +D13 4 2 DP +R6 4 N006 590Meg +R7 N006 2 590Meg +G3 N006 0 N006 N004 100µ dir=1 vto=0 +G4 0 N006 2 N006 500m dir=1 vto=.3 +C10 2 3 .5p +R3 4 N004 600Meg +A5 VINT 0 0 0 0 0 N006 0 OTA g=2m asym Vlow=-1e308 Vhigh=1e308 isource=1u isink=-.115u +C14 N007 N006 50f +D8 N002 0 DINNLP +D9 0 N002 DINNLN +C7 0 N002 10f Rpar=40Meg +D1 N004 2 DNL +R1 N004 2 400Meg +R2 1 N007 1 +G1 4 2 1 N007 .1 +D2 N003 2 DBR +R4 4 N003 10Meg +D3 N003 3 DB1 +D4 N003 3 DB2 +C1 N003 2 10f +.model DINNLP D(Vfwd=200m Ron=300k Roff=400Meg epsilon=30m) +.model DINNLN D(Vfwd=40m epsilon=10m Ron=100k Roff=400Meg) +.model NOUT VDMOS(Vto=5m kp=150m mtriode=.8 rds=600g) +.model DNL D(Vfwd=.9 epsilon=.3 Ron=100k Roff=400Meg) +.model DP D(Ron=100 Roff=1G Vfwd=1 ilimit=6.04u) +.model DBR D(Ron=10K Roff=1G Vfwd=.55 epsilon=.1) +.model DB1 D(Ron=50Meg Roff=1T Vfwd=60m epsilon=100m ilimit=1.8n) +.model DB2 D(Ron=35Meg Roff=1T Vfwd=450m epsilon=50m) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=.5 Vrev=1 epsilon=.5 revepsilon=.5) +.ends LT6703-2 +* +.subckt LT6703-3 1 2 3 4 +A1 0 N002 0 0 0 0 VINT 0 OTA g=4.7u asym isource=3.5u isink=-1.5u Vlow=-1e308 Vhigh=1e308 Cout=25p +C2 N006 0 500f +M1 N007 N006 2 2 NOUT temp=27 +C5 4 1 .5p +C6 1 2 5p +D5 0 VINT DLAT +D13 4 2 DP +R6 4 N006 590Meg +R7 N006 2 590Meg +G3 N006 0 N006 N004 100µ dir=1 vto=0 +G4 0 N006 2 N006 500m dir=1 vto=.3 +C10 2 3 .5p +R3 4 N004 600Meg +A5 VINT 0 0 0 0 0 N006 0 OTA g=2m asym Vlow=-1e308 Vhigh=1e308 isource=1u isink=-.115u +C14 N007 N006 50f +D8 N002 0 DINNLP +D9 0 N002 DINNLN +C7 0 N002 10f Rpar=40Meg +D1 N004 2 DNL +R1 N004 2 400Meg +R2 1 N007 1 +G1 4 2 1 N007 .1 +B2 0 N002 I=100u*dnlim(uplim(V(3),V(2)+18.6,.1), V(2)-.4, .1)+322n*V(VINT) -39.658u-100u*V(2) +D2 N003 2 DBR +R4 4 N003 10Meg +D3 N003 3 DB1 +D4 N003 3 DB2 +C3 N003 2 10f +.model DINNLP D(Vfwd=10m Ron=200k Roff=400Meg epsilon=10m) +.model DINNLN D(Vfwd=350m epsilon=10m Ron=100k Roff=400Meg) +.model NOUT VDMOS(Vto=5m kp=150m mtriode=.8 rds=600g) +.model DNL D(Vfwd=.9 epsilon=.3 Ron=100k Roff=400Meg) +.model DP D(Ron=100 Roff=1G Vfwd=1 ilimit=6.04u) +.model DBR D(Ron=10K Roff=1G Vfwd=.55 epsilon=.1) +.model DB1 D(Ron=50Meg Roff=1T Vfwd=60m epsilon=100m ilimit=1.8n) +.model DB2 D(Ron=35Meg Roff=1T Vfwd=450m epsilon=50m) +.model DLAT D(Ron=1 Roff=10Meg Vfwd=1 Vrev=1 epsilon=.5 revepsilon=.5) +.ends LT6703-3 +* +.subckt LTC6084 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-67.7655p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +M1 5 N012 4 4 NI temp=27 +C2 3 5 1p Rpar=100Meg noiseless +D5 N012 4 DLIMN +M2 5 N008 3 3 PI temp=27 +D8 3 N008 DLIMP +C3 3 N008 28f Rser=5Meg noiseless +A3 N009 N010 4 4 4 4 N008 4 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=100Meg noiseless +C12 N012 4 28f Rser=5Meg noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=1u linear en=29.7n enk=88 Vhigh=1e308 Vlow=-1e308 +C16 N010 5 3.8p +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=36u iout=1.9u Vhigh=1e308 Vlow=-1e308 +G1 4 N012 N010 N009 200n +D9 N010 N009 DLIM +C7 3 1 4.5p Rser=10 Rpar=5T noiseless +C13 3 4 1000p +S1 N010 N009 0 N005 SHUT2 +C1 N006 0 800f Rpar=1Meg noiseless +C17 4 6 500f Rpar=1T noiseless +G2 0 N009 4 0 .5m +G4 0 N009 3 0 .5m +C18 N009 0 200p Rpar=1K noiseless +S4 N008 3 0 N005 SHUT1 +S2 4 N012 0 N005 SHUT1 +S7 3 4 N005 0 SPOW +G3 0 N007 N006 0 1m +L1 N007 0 431.7µ Cpar=637f Rser=1.06k Rpar=12.1k noiseless +C9 N008 5 5f Rser=8Meg noiseless +C8 5 N012 5f Rser=8Meg noiseless +A2 6 4 0 0 0 0 N005 0 SCHMITT trise=6u tfall=.8u vt=.8 vh=10m +D2 3 6 DSHUT +D6 2 3 DESD +D7 4 2 DESD +D10 1 3 DESD +D11 4 1 DESD +D1 1 4 DBIAS +D3 2 4 DBIAS +C4 3 2 4.5p Rser=10 Rpar=5T noiseless +C5 1 4 4.5p Rser=10 Rpar=5T noiseless +C6 2 4 4.5p Rser=10 Rpar=5T noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=-5.2184p+5.22p*exp(freq*9e-7) +.model DSHUT D(Ron=85k Roff=1Meg Vfwd=.1 epsilon=50m ilimit=1u noiseless) +.model DBIAS D(Ron=10G Roff=10T epsilon=.3 ilimit=1p noiseless) +.model SPOW SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=34.3u noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=200m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.1 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.3 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.ends LTC6084 +* +.subckt LTC6085 1 2 3 4 5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-67.7655p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +M1 5 N011 4 4 NI temp=27 +C2 3 5 1p Rpar=100Meg noiseless +D5 N011 4 DLIMN +M2 5 N007 3 3 PI temp=27 +D8 3 N007 DLIMP +C3 3 N007 28f Rser=5Meg noiseless +A3 N008 N009 4 4 4 4 N007 4 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=100Meg noiseless +C12 N011 4 28f Rser=5Meg noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear en=29.7n enk=88 Vhigh=1e308 Vlow=-1e308 +C16 N009 5 3.8p +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=36u iout=1.9u Vhigh=1e308 Vlow=-1e308 +G1 4 N011 N009 N008 200n +D9 N009 N008 DLIM +C7 3 1 4.5p Rser=10 Rpar=5T noiseless +C13 3 4 1000p +C1 N005 0 800f Rpar=1Meg noiseless +G2 0 N008 4 0 .5m +G4 0 N008 3 0 .5m +C18 N008 0 200p Rpar=1K noiseless +G3 0 N006 N005 0 1m +L1 N006 0 431.7µ Cpar=637f Rser=1.06k Rpar=12.1k noiseless +C9 N007 5 5f Rser=8Meg noiseless +C8 5 N011 5f Rser=8Meg noiseless +D6 2 3 DESD +D7 4 2 DESD +D10 1 3 DESD +D11 4 1 DESD +D1 1 4 DBIAS +D3 2 4 DBIAS +C4 3 2 4.5p Rser=10 Rpar=5T noiseless +C5 1 4 4.5p Rser=10 Rpar=5T noiseless +C6 2 4 4.5p Rser=10 Rpar=5T noiseless +A1 2 1 0 0 0 0 0 0 OTA g=0 in=-5.2184p+5.22p*exp(freq*9e-7) +D4 3 4 DPOW +.model DBIAS D(Ron=100G Roff=10T epsilon=.3 ilimit=1p noiseless) +.model DPOW D(Ron=1k Roff=1G Vfwd=.1 epsilon=50m ilimit=34.3u noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=200m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.1 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.3 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.ends LTC6085 +* +.subckt LTC6102 1 2 3 4 5 6 +M2 1 N004 6 6 P temp=27 +C3 6 1 .1p +C4 1 2 .1p +D1 3 4 DINCL +C5 3 2 .2p +C6 4 2 .2p +A1 0 N008 2 2 2 2 N006 2 OTA g=350u iout=50u cout=1pf Vlow=-1e308 Vhigh=1e308 +R1 N006 2 100G noiseless +G1 N006 2 N006 5 10µ dir=1 vto=-490m +D3 4 2 DBIAS +C1 N003 0 10f Rpar=200K noiseless +S1 N003 0 2 5 SWP1 +G4 2 N004 N006 2 1µ +C2 N004 2 10f Rpar=1Meg noiseless +S2 5 N006 2 5 SWP2 +D2 5 VMX DLIM1 +G6 VMX 5 5 2 1.9n +D4 5 VMX DLIM2 +C7 1 N006 5.8p +G2 2 N006 2 N006 10µ dir=1 vto=-400m +C8 5 VMX .1f Rpar=1g noiseless +S3 N006 5 VMX N006 SWLIM +D6 4 3 DINCL2 +B1 0 N003 I=10u*dnlim(uplim(V(4),V(5)+.1,.1), V(5)-2.1, .1) +B2 N003 0 I=10u*dnlim(uplim(V(3),V(5)+.1,.1), V(5)-2.1, .1) +D8 5 2 DP +D7 3 2 DBIAS +R4 5 2 373k noiseless +D11 2 1 DZ0 +D5 3 5 DZ2 +D12 3 5 DZ1 +D9 6 5 DZ2 +A2 0 N003 0 0 0 0 N008 0 OTA g=1u linear Rout=1Meg Cout=250f en=5n + 6u/dnlim(freq**.88,800,300) Vlow=-1e308 Vhigh=1e308 +D10 6 N004 DIMAX +.model DINCL D(Ron=10k Roff=100G Vfwd=.7 Vrev=.7 epsilon=.1 revepsilon=.1 noiseless) +.model DINCL2 D(Ron=100 Roff=100g Vfwd=.21 epsilon=.1 noiseless) +.model DBIAS D(Ron=200k Roff=1T Vfwd= .4 epsilon=.15 ilimit=60p) +.model SWP1 SW(Ron=1 Roff=200k vt=-3.9 vh=-100m noiseless) +.model SWP2 SW(Ron=10 Roff=200G vt=-3.9 vh=-100m noiseless) +.model DLIM1 D(Ron=25Meg Roff=1g vfwd=3 epsilon=.5 noiseless) +.model DLIM2 D(Ron=600Meg Roff=1g vfwd=.7 epsilon=.1 noiseless) +.model SWLIM SW(Ron=1k Roff=200G vt=50m vh=-10m noiseless) +.model DZ1 D(Ron=5k Roff=100G Vfwd=100 epsilon=100m Vrev=5.1 revepsilon=.1 noiseless) +.model DZ2 D(Ron=1 Roff=100G Vfwd=100 epsilon=100m Vrev=10.1 revepsilon=.1 noiseless) +.model DZ0 D(Ron=10 Roff=1g vfwd=700m epsilon=100m vrev=9.5 revepsilon=.1 noiseless) +.model P VDMOS(Vto=-500m Kp=1m Ksubthres=.1 rds=1g pchan) +.model DP D(Roff=1G Ron=100 Vfwd=0.5 epsilon=.1 ilimit=275u) +.model DIMAX D(Roff=1T Ron=10k vfwd=3.45 epsilon=200m) +.ends LTC6102 +* +.subckt LTC6103 1 2 3 4 5 6 7 +M2 1 N004 6 6 P temp=27 +C3 6 1 .1p +C4 1 3 .1p +D7 7 3 DP +D1 6 7 DINCL +C5 6 7 .2p +C6 7 3 .2p +A1 0 N003 3 3 3 3 N005 3 OTA g=200u iout=50u Cout=1p Vlow=-1e308 Vhigh=1e308 +R1 N005 3 100G noiseless +G1 N005 3 N005 6 10µ dir=1 vto=-490m +D3 7 3 DBIAS +G3 0 N003 7 6 10µ +C1 N003 0 10f Rpar=200K noiseless +S1 N003 0 3 6 SWP1 +G4 3 N004 N005 3 10µ +C2 N004 3 1p Rpar=100k noiseless +S2 6 N005 3 6 SWP2 +D2 6 N006 DLIM1 +G6 N006 6 6 3 1.9n +D4 6 N006 DLIM2 +C7 1 N005 3.8p +G2 3 N005 3 N005 10µ dir=1 vto=-400m +C8 6 N006 .1f Rpar=1g noiseless +S3 N005 6 N006 N005 SWLIM +D6 7 6 DINCL2 +M1 2 N011 5 5 P temp=27 +C9 5 2 .1p +C10 2 3 .1p +D8 4 3 DP +D9 5 4 DINCL +C11 5 4 .2p +C12 4 3 .2p +A2 0 N010 3 3 3 3 N012 3 OTA g=200u iout=50u Cout=1p Vlow=-1e308 Vhigh=1e308 +R10 N012 3 100G noiseless +G5 N012 3 N012 5 10µ dir=1 vto=-490m +D10 4 3 DBIAS +G7 0 N010 4 5 10µ +C13 N010 0 10f Rpar=200K noiseless +S4 N010 0 3 5 SWP1 +G8 3 N011 N012 3 10µ +C14 N011 3 1p Rpar=100k noiseless +S5 5 N012 3 5 SWP2 +D11 5 N013 DLIM1 +G9 N013 5 5 3 1.9n +D12 5 N013 DLIM2 +C15 2 N012 3.8p +G10 3 N012 3 N012 10µ dir=1 vto=-400m +C16 5 N013 .1f Rpar=1g noiseless +S6 N012 5 N013 N012 SWLIM +D14 4 5 DINCL2 +D15 3 2 DZB +D5 3 1 DZB +.model DINCL D(Ron=10k Roff=100G Vfwd=.7 Vrev=.7 epsilon=.1 revepsilon=.1 noiseless) +.model DINCL2 D(Ron=100 Roff=100g Vfwd=2.1 epsilon=.1 noiseless) +.model DBIAS D(Ron=200k Roff=1T Vfwd= .4 epsilon=.15 ilimit=100n) +.model SWP1 SW(Ron=1 Roff=200k vt=-3.9 vh=-100m noiseless) +.model SWP2 SW(Ron=10 Roff=200G vt=-3.9 vh=-100m noiseless) +.model DLIM1 D(Ron=25Meg Roff=1g vfwd=3 epsilon=.5 noiseless) +.model DLIM2 D(Ron=600Meg Roff=1g vfwd=.7 epsilon=.1 noiseless) +.model SWLIM SW(Ron=1k Roff=200G vt=50m vh=-10m noiseless) +.model DZB D(Ron=10 Roff=1g vfwd=.7 epsilon=.1 vrev=10.1 revepsilon=100m noiseless) +.model P VDMOS(Vto=-500m Kp=1m rds=1g pchan) +.model DP D(Roff=1G Ron=100 Vfwd=0.5 epsilon=.1 ilimit=220u) +.ends LTC6103 +* +.subckt LTC6400-8 1 2 3 4 5 6 7 8 9 10 +M1 N002 N013 6 6 NI temp=27 +D5 N013 6 DLIMN +M2 N002 N006 3 3 PI temp=27 +D8 3 N006 DLIMP +C3 3 N006 .01f Rser=100 noiseless +A3 N007 N009 6 6 6 6 N006 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 N005 0 N007 N007 N007 N007 N009 N007 OTA g=3m iout=2.4m cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N013 N009 N007 200n +D9 N009 N007 DLIM +C7 3 VINP 1p Rser=500 Rpar=2G noiseless +C13 3 6 1000p +S1 N009 N007 0 N011 SHUT2 +C17 6 7 500f +S4 N006 3 0 N011 SHUT1 +S2 6 N013 0 N011 SHUT1 +A2 6 7 0 0 0 0 N011 0 SCHMITT trise=70n tfall=180n vt=-.8 vh=10m +D6 VINM 3 DESD +D7 6 VINM DESD +D11 6 VINP DESD +M3 N020 N028 6 6 NI temp=27 +D3 N028 6 DLIMN +M4 N020 N024 3 3 PI temp=27 +D12 3 N024 DLIMP +A6 N007 N025 6 6 6 6 N024 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 N005 N007 N007 N007 N007 N025 N007 OTA g=3m iout=2.4m cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N028 N025 N007 200n +D13 N025 N007 DLIM +S3 N025 N007 0 N011 SHUT2 +S5 N024 3 0 N011 SHUT1 +S6 6 N028 0 N011 SHUT1 +R3 N002 N017 1Meg noiseless +R4 N020 N017 1Meg noiseless +G6 N007 N025 0 VCM 150µ +G7 N007 N009 0 VCM 150µ +C2 3 N002 .5p Rpar=1Meg noiseless +C8 N002 6 .5p Rpar=1Meg noiseless +C9 3 N020 .5p Rpar=1Meg noiseless +C11 N020 6 .5p Rpar=1Meg noiseless +C14 N009 N002 1p +C16 N020 N025 1p +D2 3 6 DPOWS +S7 6 3 N011 0 SPOWR +D1 Vocmf 3 DESD +D4 6 Vocmf DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N005 0 1.2p Rpar=70 noiseless +B1 0 N004 I=10u*dnlim(uplim(V(VINP),V(3)-1.1,.1), V(6)+.9, .1)+1n*V(VINP) +B2 N004 0 I=10u*dnlim(uplim(V(VINM),V(3)-1.09,.1), V(6)+.89, .1)+1n*V(VINM) +C20 N004 0 .1f Rpar=100K noiseless +G8 0 N007 6 0 .5m +G9 0 N007 3 0 .5m +C21 N007 0 200p Rpar=1K noiseless +R5 N002 10 50 +C24 10 9 2.7p +D16 VINP 3 DESD +C12 N013 6 .01f Rser=100 noiseless +C15 3 N024 .01f Rser=100 noiseless +C19 N028 6 .01f Rser=100 noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=100m linear en=1.3n enk=16.5k Vhigh=1e308 Vlow=-1e308 +R12 4 N002 12.5 +R6 9 N020 50 +R13 5 N020 12.5 +R2 VINM 1 200 +R8 VINP 8 200 +R1 N002 VINM 500 +R7 N020 VINP 500 +R14 Vocmf 2 2k +C18 6 Vocmf 5.3p Rpar=300k noiseless +D19 7 6 DEN +B3 0 N023 I=10u*dnlim(uplim(V(Vocmf),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(vocmf) +C27 N023 0 .1f Rpar=100K noiseless +G2 N023 0 N017 0 10µ +A8 0 N023 0 0 0 0 VCM 0 OTA g=1.7m iout=100u en=3n enk=16.5k ref=8.5m Vlow=-1e308 Vhigh=1e308 +S10 3 N006 N002 3 SUPLIM +S11 3 N024 N020 3 SUPLIM +C1 3 VINM 1p Rser=500 Rpar=2G noiseless +C4 VINP 6 1p Rser=500 Rpar=2G noiseless +C5 VINM 6 1p Rser=500 Rpar=2G noiseless +D10 N005 0 DLIM0 +C6 VCM 0 10f Rser=1k Rpar=10k noiseless +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=100k Roff=1G vt=-390m vh=-120m noiseless) +.model NI VDMOS(Vto=300m kp=200m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=200m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=.8 Vrev=-300m epsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=.8 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=10k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7k Vfwd=3 Vrev=3 epsilon=50m revepsilon=50m noiseless) +.model DSI D(IS=1e-20 TT=1p noiseless) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=1.05 Vrev=1.05 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model DEN D(Ron=1k Roff=100Meg Vfwd=.4 epsilon=.1 ilimit=12u noiseless) +.model DPOWS D(Ron=100 Roff=1G Vfwd=2 epsilon=.1 ilimit=.9m noiseless) +.model SPOWR SW(level=1 Ron=10 Roff=1g vt=.5 vh=-.1 ilimit=72.6m noiseless) +.ends LTC6400-8 +* +.subckt LTC6400-14 1 2 3 4 5 6 7 8 9 10 +M1 N002 N014 6 6 NI temp=27 +D5 N014 6 DLIMN +M2 N002 N006 3 3 PI temp=27 +D8 3 N006 DLIMP +C3 3 N006 .01f Rser=100 noiseless +A3 N007 N009 6 6 6 6 N006 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 N005 0 N007 N007 N007 N007 N009 N007 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N014 N009 N007 200n +D9 N009 N007 DLIM +C7 3 VINP 1p Rser=500 Rpar=2G noiseless +C13 3 6 1000p +S1 N009 N007 0 N011 SHUT2 +C17 6 7 500f +S4 N006 3 0 N011 SHUT1 +S2 6 N014 0 N011 SHUT1 +A2 6 7 0 0 0 0 N011 0 SCHMITT trise=70n tfall=180n vt=-.8 vh=10m +D6 VINM 3 DESD +D7 6 VINM DESD +D11 6 VINP DESD +M3 N021 N029 6 6 NI temp=27 +D3 N029 6 DLIMN +M4 N021 N025 3 3 PI temp=27 +D12 3 N025 DLIMP +A6 N007 N026 6 6 6 6 N025 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 N005 N007 N007 N007 N007 N026 N007 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N029 N026 N007 200n +D13 N026 N007 DLIM +S3 N026 N007 0 N011 SHUT2 +S5 N025 3 0 N011 SHUT1 +S6 6 N029 0 N011 SHUT1 +R3 N002 N018 1Meg noiseless +R4 N021 N018 1Meg noiseless +G6 N007 N026 0 VCM 150µ +G7 N007 N009 0 VCM 150µ +C2 3 N002 .5p Rpar=1Meg noiseless +C8 N002 6 .5p Rpar=1Meg noiseless +C9 3 N021 .5p Rpar=1Meg noiseless +C11 N021 6 .5p Rpar=1Meg noiseless +C14 N009 N002 500f +C16 N021 N026 500f +D2 3 6 DPOWS +S7 6 3 N011 0 SPOWR +D1 Vocmf 3 DESD +D4 6 Vocmf DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N005 0 1.4p Rpar=70 noiseless +B1 0 N004 I=10u*dnlim(uplim(V(VINP),V(3)-1.1,.1), V(6)+.9, .1)+1n*V(VINP) +B2 N004 0 I=10u*dnlim(uplim(V(VINM),V(3)-1.09,.1), V(6)+.89, .1)+1n*V(VINM) +C20 N004 0 .05f Rpar=100K noiseless +G8 0 N007 6 0 .5m +G9 0 N007 3 0 .5m +C21 N007 0 200p Rpar=1K noiseless +R5 N002 10 50 +C24 10 9 2.7p +D16 VINP 3 DESD +C12 N014 6 .01f Rser=100 noiseless +C15 3 N025 .01f Rser=100 noiseless +C19 N029 6 .01f Rser=100 noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=100m linear en=1.3n enk=15k Vhigh=1e308 Vlow=-1e308 +R12 4 N002 12.5 +R6 9 N021 50 +R13 5 N021 12.5 +R2 VINM 1 100 +R8 VINP 8 100 +R1 N002 VINM 500 +R7 N021 VINP 500 +R14 Vocmf 2 2k +C18 6 Vocmf 5.3p Rpar=300k noiseless +D19 7 6 DEN +B3 0 N024 I=10u*dnlim(uplim(V(Vocmf),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(vocmf) +C27 N024 0 .1f Rpar=100K noiseless +G2 N024 0 N018 0 10µ +A8 0 N024 0 0 0 0 VCM 0 OTA g=1.7m iout=100u en=3n enk=16.5k ref=8.5m Vlow=-1e308 Vhigh=1e308 +S10 3 N006 N002 3 SUPLIM +S11 3 N025 N021 3 SUPLIM +C1 3 VINM 1p Rser=500 Rpar=2G noiseless +C4 VINP 6 1p Rser=500 Rpar=2G noiseless +C5 VINM 6 1p Rser=500 Rpar=2G noiseless +D10 N005 0 DLIM0 +D14 N005 N013 DLIMI +C22 N013 0 1p Rpar=100k noiseless +C6 VCM 0 60f Rser=3k Rpar=10k noiseless +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=100k Roff=1G vt=-390m vh=-120m noiseless) +.model NI VDMOS(Vto=300m kp=200m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=200m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=.8 Vrev=-300m epsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=.8 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=10k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7k Vfwd=3 Vrev=3 epsilon=50m revepsilon=50m noiseless) +.model DSI D(IS=1e-20 TT=1p noiseless) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=473m Vrev=473m epsilon=50m revepsilon=50m noiseless) +.model DLIMI D(Ron=1 Roff=100Meg Vfwd=120m Vrev=120m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model DEN D(Ron=1k Roff=100Meg Vfwd=.4 epsilon=.1 ilimit=12u noiseless) +.model DPOWS D(Ron=100 Roff=1G Vfwd=2 epsilon=.1 ilimit=.9m noiseless) +.model SPOWR SW(level=1 Ron=10 Roff=1g vt=.5 vh=-.1 ilimit=72.6m noiseless) +.ends LTC6400-14 +* +.subckt LTC6400-20 1 2 3 4 5 6 7 8 9 10 +M1 N002 N015 6 6 NI temp=27 +D5 N015 6 DLIMN +M2 N002 N006 3 3 PI temp=27 +D8 3 N006 DLIMP +C3 3 N006 .01f Rser=100 noiseless +A3 N007 N009 6 6 6 6 N006 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 N005 0 N007 N007 N007 N007 N009 N007 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N015 N009 N007 200n +D9 N009 N007 DLIM +C7 3 VINP 1p Rser=500 Rpar=2G noiseless +C13 3 6 1000p +S1 N009 N007 0 N011 SHUT2 +C17 6 7 500f +S4 N006 3 0 N011 SHUT1 +S2 6 N015 0 N011 SHUT1 +A2 6 7 0 0 0 0 N011 0 SCHMITT trise=70n tfall=180n vt=-.8 vh=10m +D6 VINM 3 DESD +D7 6 VINM DESD +D11 6 VINP DESD +M3 N022 N030 6 6 NI temp=27 +D3 N030 6 DLIMN +M4 N022 N026 3 3 PI temp=27 +D12 3 N026 DLIMP +A6 N007 N027 6 6 6 6 N026 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 N005 N007 N007 N007 N007 N027 N007 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N030 N027 N007 200n +D13 N027 N007 DLIM +S3 N027 N007 0 N011 SHUT2 +S5 N026 3 0 N011 SHUT1 +S6 6 N030 0 N011 SHUT1 +R3 N002 N019 1Meg noiseless +R4 N022 N019 1Meg noiseless +G6 N007 N027 0 N013 100µ +G7 N007 N009 0 N013 100µ +C2 3 N002 .5p Rpar=1Meg noiseless +C8 N002 6 .5p Rpar=1Meg noiseless +C9 3 N022 .5p Rpar=1Meg noiseless +C11 N022 6 .5p Rpar=1Meg noiseless +C14 N009 N002 400f +C16 N022 N027 400f +D2 3 6 DPOWS +S7 6 3 N011 0 SPOWR +D1 Vocmf 3 DESD +D4 6 Vocmf DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N005 0 7f Rpar=7k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(VINP),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(VINP) +B2 N004 0 I=10u*dnlim(uplim(V(VINM),V(3)-1.29,.1), V(6)+.89, .1)+1n*V(VINM) +C20 N004 0 .1f Rpar=100K noiseless +G8 0 N007 6 0 .5m +G9 0 N007 3 0 .5m +C21 N007 0 200p Rpar=1K noiseless +R5 N002 10 50 +C24 10 9 1.7p +D16 VINP 3 DESD +C12 N015 6 .01f Rser=100 noiseless +C15 3 N026 .01f Rser=100 noiseless +C19 N030 6 .01f Rser=100 noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=1n+freq*2.5e-18 enk=10.5k Vhigh=1e308 Vlow=-1e308 +R12 4 N002 12.5 +R6 9 N022 50 +R13 5 N022 12.5 +R2 VINM 1 100 +R8 VINP 8 100 +R1 N002 VINM 1k +R7 N022 VINP 1k +R14 Vocmf 2 2k +C18 6 Vocmf 5.3p Rpar=300k noiseless +D19 7 6 DEN +B3 0 N025 I=10u*dnlim(uplim(V(Vocmf),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(vocmf) +C27 N025 0 .1f Rpar=100K noiseless +G2 N025 0 N019 0 10µ +A8 0 N025 0 0 0 0 N013 0 OTA g=1.7m iout=1m en=3n enk=10.5k ref=7.8m Vlow=-1e308 Vhigh=1e308 +C26 N013 0 30f Rser=1k Rpar=10k noiseless +S10 3 N006 N002 3 SUPLIM +S11 3 N026 N022 3 SUPLIM +C1 3 VINM 1p Rser=500 Rpar=2G noiseless +C4 VINP 6 1p Rser=500 Rpar=2G noiseless +C5 VINM 6 1p Rser=500 Rpar=2G noiseless +D10 N005 N014 DLIMI +C6 N014 0 22f Rpar=100k noiseless +D14 N005 0 DLIM0 +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=100k Roff=1G vt=-620m vh=-200m noiseless) +.model NI VDMOS(Vto=300m kp=200m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=200m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=.7 Vrev=-300m epsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=.7 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=10k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7k Vfwd=3 Vrev=3 epsilon=50m revepsilon=50m noiseless) +.model DLIM0 D(Ron=100 Roff=100Meg Vfwd=330m Vrev=330m epsilon=20m revepsilon=20m noiseless) +.model DLIMI D(Ron=1 Roff=100Meg Vfwd=50m Vrev=50m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model DEN D(Ron=1k Roff=100Meg Vfwd=.4 epsilon=.1 ilimit=12u noiseless) +.model DPOWS D(Ron=100 Roff=1G Vfwd=2 epsilon=.1 ilimit=1m noiseless) +.model SPOWR SW(level=1 Ron=10 Roff=1g vt=.5 vh=-.1 ilimit=80.17m noiseless) +.ends LTC6400-20 +* +.subckt LTC6400-26 1 2 3 4 5 6 7 8 9 10 +M1 N002 N014 6 6 NI temp=27 +D5 N014 6 DLIMN +M2 N002 N005 3 3 PI temp=27 +D8 3 N005 DLIMP +C3 3 N005 .01f Rser=100 noiseless +A3 N006 N008 6 6 6 6 N005 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 VLIMI 0 N006 N006 N006 N006 N008 N006 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N014 N008 N006 200n +D9 N008 N006 DLIM +C7 3 VINP 1p Rser=500 Rpar=2G noiseless +C13 3 6 1000p +S1 N008 N006 0 N010 SHUT2 +C17 6 7 500f +S4 N005 3 0 N010 SHUT1 +S2 6 N014 0 N010 SHUT1 +A2 6 7 0 0 0 0 N010 0 SCHMITT trise=70n tfall=180n vt=-.8 vh=10m +D6 VINM 3 DESD +D7 6 VINM DESD +D11 6 VINP DESD +M3 N021 N029 6 6 NI temp=27 +D3 N029 6 DLIMN +M4 N021 N025 3 3 PI temp=27 +D12 3 N025 DLIMP +A6 N006 N026 6 6 6 6 N025 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 VLIMI N006 N006 N006 N006 N026 N006 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N029 N026 N006 200n +D13 N026 N006 DLIM +S3 N026 N006 0 N010 SHUT2 +S5 N025 3 0 N010 SHUT1 +S6 6 N029 0 N010 SHUT1 +R3 N002 N018 1Meg noiseless +R4 N021 N018 1Meg noiseless +G6 N006 N026 0 N012 100µ +G7 N006 N008 0 N012 100µ +C2 3 N002 .5p Rpar=1Meg noiseless +C8 N002 6 .5p Rpar=1Meg noiseless +C9 3 N021 .5p Rpar=1Meg noiseless +C11 N021 6 .5p Rpar=1Meg noiseless +C14 N008 N002 300f +C16 N021 N026 300f +D2 3 6 DPOWS +S7 6 3 N010 0 SPOWR +D1 Vocmf 3 DESD +D4 6 Vocmf DESD +D17 7 3 DESD +D18 6 7 DESD +C10 VLIMI 0 10f Rpar=7k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(VINP),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(VINP) +B2 N004 0 I=10u*dnlim(uplim(V(VINM),V(3)-1.29,.1), V(6)+.89, .1)+1n*V(VINM) +C20 N004 0 .5f Rpar=100K noiseless +G8 0 N006 6 0 .5m +G9 0 N006 3 0 .5m +C21 N006 0 200p Rpar=1K noiseless +R5 N002 10 50 +C24 10 9 1.7p +D16 VINP 3 DESD +C12 N014 6 .01f Rser=100 noiseless +C15 3 N025 .01f Rser=100 noiseless +C19 N029 6 .01f Rser=100 noiseless +A4 0 N004 0 0 0 0 VLIMI 0 OTA g=1m linear en=1.1n/(1+1.5*freq**2/1e18) enk=13.9k Vhigh=1e308 Vlow=-1e308 +R12 4 N002 12.5 +R6 9 N021 50 +R13 5 N021 12.5 +R2 VINM 1 25 +R8 VINP 8 25 +R1 N002 VINM 500 +R7 N021 VINP 500 +R14 Vocmf 2 2k +C18 6 Vocmf 5.3p Rpar=300k noiseless +D19 7 6 DEN +B3 0 N024 I=10u*dnlim(uplim(V(Vocmf),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(vocmf) +C27 N024 0 .1f Rpar=100K noiseless +G2 N024 0 N018 0 10µ +A8 0 N024 0 0 0 0 N012 0 OTA g=1.7m iout=1m en=3n enk=13.9k ref=7.8m Vlow=-1e308 Vhigh=1e308 +S10 3 N005 N002 3 SUPLIM +S11 3 N025 N021 3 SUPLIM +C1 3 VINM 1p Rser=500 Rpar=2G noiseless +C4 VINP 6 1p Rser=500 Rpar=2G noiseless +C5 VINM 6 1p Rser=500 Rpar=2G noiseless +D10 VLIMI N013 DLIMI +C6 N013 0 18f Rpar=100k noiseless +D14 VLIMI 0 DLIM0 +C22 N012 0 70f Rser=5k Rpar=10k noiseless +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=100k Roff=1G vt=-430m vh=-120m noiseless) +.model NI VDMOS(Vto=300m kp=200m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=200m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=.9 Vrev=-300m epsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=.9 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=10k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7k Vfwd=3 Vrev=3 epsilon=50m revepsilon=50m noiseless) +.model DLIM0 D(Ron=100 Roff=100Meg Vfwd=370m Vrev=370m epsilon=20m revepsilon=20m noiseless) +.model DLIMI D(Ron=1 Roff=100Meg Vfwd=100m Vrev=100m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model DEN D(Ron=1k Roff=100Meg Vfwd=.4 epsilon=.1 ilimit=12u noiseless) +.model DPOWS D(Ron=100 Roff=1G Vfwd=2 epsilon=.1 ilimit=800u noiseless) +.model SPOWR SW(level=1 Ron=10 Roff=1g vt=.5 vh=-.1 ilimit=74.7m noiseless) +.ends LTC6400-26 +* +.subckt LTC6401-8 1 2 3 4 5 6 7 8 9 10 +M1 N002 N013 6 6 NI temp=27 +D5 N013 6 DLIMN +M2 N002 N005 3 3 PI temp=27 +D8 3 N005 DLIMP +C3 3 N005 .01f Rser=100 noiseless +A3 N006 N008 6 6 6 6 N005 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 VLIM0 0 N006 N006 N006 N006 N008 N006 OTA g=3m iout=2.15m Vhigh=1e308 Vlow=-1e308 +G1 6 N013 N008 N006 200n +D9 N008 N006 DLIM +C7 3 VINP 1p Rser=500 Rpar=2G noiseless +C13 3 6 1000p +S1 N008 N006 0 N010 SHUT2 +C17 6 7 500f +S4 N005 3 0 N010 SHUT1 +S2 6 N013 0 N010 SHUT1 +A2 6 7 0 0 0 0 N010 0 SCHMITT trise=70n tfall=180n vt=-.8 vh=10m +D6 VINM 3 DESD +D7 6 VINM DESD +D11 6 VINP DESD +M3 N020 N028 6 6 NI temp=27 +D3 N028 6 DLIMN +M4 N020 N024 3 3 PI temp=27 +D12 3 N024 DLIMP +A6 N006 N025 6 6 6 6 N024 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 VLIM0 N006 N006 N006 N006 N025 N006 OTA g=3m iout=2.15m Vhigh=1e308 Vlow=-1e308 +G5 6 N028 N025 N006 200n +D13 N025 N006 DLIM +S3 N025 N006 0 N010 SHUT2 +S5 N024 3 0 N010 SHUT1 +S6 6 N028 0 N010 SHUT1 +R3 N002 N017 1Meg noiseless +R4 N020 N017 1Meg noiseless +G6 N006 N025 0 VCM 150µ +G7 N006 N008 0 VCM 150µ +C2 3 N002 .5p Rpar=1Meg noiseless +C8 N002 6 .5p Rpar=1Meg noiseless +C9 3 N020 .5p Rpar=1Meg noiseless +C11 N020 6 .5p Rpar=1Meg noiseless +C14 N008 N002 1.1p +C16 N020 N025 1.1p +D2 3 6 DPOWS +S7 6 3 N010 0 SPOWR +D1 Vocmf 3 DESD +D4 6 Vocmf DESD +D17 7 3 DESD +D18 6 7 DESD +C10 VLIM0 0 1p Rpar=70 noiseless +B1 0 N004 I=10u*dnlim(uplim(V(VINP),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(VINP) +B2 N004 0 I=10u*dnlim(uplim(V(VINM),V(3)-1.29,.1), V(6)+.89, .1)+1n*V(VINM) +C20 N004 0 .1f Rpar=100K noiseless +G8 0 N006 6 0 .5m +G9 0 N006 3 0 .5m +C21 N006 0 200p Rpar=1K noiseless +R5 N002 10 50 +C24 10 9 2.7p +D16 VINP 3 DESD +A4 0 N004 0 0 0 0 VLIM0 0 OTA g=100m linear en=.9n enk=12.2k Vhigh=1e308 Vlow=-1e308 +R12 4 N002 12.5 +R6 9 N020 50 +R13 5 N020 12.5 +R2 VINM 1 200 +R8 VINP 8 200 +R1 N002 VINM 500 +R7 N020 VINP 500 +R14 Vocmf 2 2k +C18 6 Vocmf 5.3p Rpar=300k noiseless +D19 7 6 DEN +B3 0 N023 I=10u*dnlim(uplim(V(Vocmf),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(vocmf) +C27 N023 0 .1f Rpar=100K noiseless +G2 N023 0 N017 0 10µ +A8 0 N023 0 0 0 0 VCM 0 OTA g=1.7m iout=100u en=3n enk=12.2k ref=8.5m Vlow=-1e308 Vhigh=1e308 +S10 3 N005 N002 3 SUPLIM +S11 3 N024 N020 3 SUPLIM +C1 3 VINM 1p Rser=500 Rpar=2G noiseless +C4 VINP 6 1p Rser=500 Rpar=2G noiseless +C5 VINM 6 1p Rser=500 Rpar=2G noiseless +C6 VCM 0 10f Rser=1k Rpar=10k noiseless +C12 N013 6 .01f Rser=100 noiseless +C15 3 N024 .01f Rser=100 noiseless +C19 N028 6 .01f Rser=100 noiseless +D10 VLIM0 N012 DLIMI +C22 N012 0 2p Rpar=100k noiseless +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=100k Roff=1G vt=-500m vh=-120m noiseless) +.model NI VDMOS(Vto=300m kp=200m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=200m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=.7 Vrev=-300m epsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=.7 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=10k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7k Vfwd=3 Vrev=3 epsilon=50m revepsilon=50m noiseless) +.model DSI D(IS=1e-20 TT=1p noiseless) +.model DLIM0 D(Ron=1 Roff=10Meg Vfwd=1.05 Vrev=1.05 epsilon=50m revepsilon=50m noiseless) +.model DLIMI D(Ron=1 Roff=100Meg Vfwd=120m Vrev=120m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model DEN D(Ron=1k Roff=100Meg Vfwd=.4 epsilon=.1 ilimit=12u noiseless) +.model DPOWS D(Ron=100 Roff=1G Vfwd=2 epsilon=.1 ilimit=.8m noiseless) +.model SPOWR SW(level=1 Ron=10 Roff=1g vt=.5 vh=-.1 ilimit=32.7m noiseless) +.ends LTC6401-8 +* +.subckt LTC6401-14 1 2 3 4 5 6 7 8 9 10 +M1 N002 N014 6 6 NI temp=27 +D5 N014 6 DLIMN +M2 N002 N006 3 3 PI temp=27 +D8 3 N006 DLIMP +C3 3 N006 .01f Rser=100 noiseless +A3 N007 N009 6 6 6 6 N006 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 N005 0 N007 N007 N007 N007 N009 N007 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N014 N009 N007 200n +D9 N009 N007 DLIM +C7 3 VINP 1p Rser=500 Rpar=2G noiseless +C13 3 6 1000p +S1 N009 N007 0 N011 SHUT2 +C17 6 7 500f +S4 N006 3 0 N011 SHUT1 +S2 6 N014 0 N011 SHUT1 +A2 6 7 0 0 0 0 N011 0 SCHMITT trise=70n tfall=180n vt=-.8 vh=10m +D6 VINM 3 DESD +D7 6 VINM DESD +D11 6 VINP DESD +M3 N021 N029 6 6 NI temp=27 +D3 N029 6 DLIMN +M4 N021 N025 3 3 PI temp=27 +D12 3 N025 DLIMP +A6 N007 N026 6 6 6 6 N025 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 N005 N007 N007 N007 N007 N026 N007 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N029 N026 N007 200n +D13 N026 N007 DLIM +S3 N026 N007 0 N011 SHUT2 +S5 N025 3 0 N011 SHUT1 +S6 6 N029 0 N011 SHUT1 +R3 N002 N018 1Meg noiseless +R4 N021 N018 1Meg noiseless +G6 N007 N026 0 VCM 150µ +G7 N007 N009 0 VCM 150µ +C2 3 N002 .5p Rpar=1Meg noiseless +C8 N002 6 .5p Rpar=1Meg noiseless +C9 3 N021 .5p Rpar=1Meg noiseless +C11 N021 6 .5p Rpar=1Meg noiseless +C14 N009 N002 800f +C16 N021 N026 800f +D2 3 6 DPOWS +S7 6 3 N011 0 SPOWR +D1 Vocmf 3 DESD +D4 6 Vocmf DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N005 0 1.2p Rpar=70 noiseless +B1 0 N004 I=10u*dnlim(uplim(V(VINP),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(VINP) +B2 N004 0 I=10u*dnlim(uplim(V(VINM),V(3)-1.29,.1), V(6)+.89, .1)+1n*V(VINM) +C20 N004 0 .05f Rpar=100K noiseless +G8 0 N007 6 0 .5m +G9 0 N007 3 0 .5m +C21 N007 0 200p Rpar=1K noiseless +R5 N002 10 50 +C24 10 9 2.7p +D16 VINP 3 DESD +C12 N014 6 .01f Rser=100 noiseless +C15 3 N025 .01f Rser=100 noiseless +C19 N029 6 .01f Rser=100 noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=100m linear en=1.3n enk=15k Vhigh=1e308 Vlow=-1e308 +R12 4 N002 12.5 +R6 9 N021 50 +R13 5 N021 12.5 +R2 VINM 1 100 +R8 VINP 8 100 +R1 N002 VINM 500 +R7 N021 VINP 500 +R14 Vocmf 2 2k +C18 6 Vocmf 5.3p Rpar=300k noiseless +D19 7 6 DEN +B3 0 N024 I=10u*dnlim(uplim(V(Vocmf),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(vocmf) +C27 N024 0 .1f Rpar=100K noiseless +G2 N024 0 N018 0 10µ +A8 0 N024 0 0 0 0 VCM 0 OTA g=1.7m iout=100u en=3n enk=15k ref=8.5m Vlow=-1e308 Vhigh=1e308 +S10 3 N006 N002 3 SUPLIM +S11 3 N025 N021 3 SUPLIM +C1 3 VINM 1p Rser=500 Rpar=2G noiseless +C4 VINP 6 1p Rser=500 Rpar=2G noiseless +C5 VINM 6 1p Rser=500 Rpar=2G noiseless +D10 N005 0 DLIM0 +D14 N005 N013 DLIMI +C22 N013 0 3p Rpar=1k noiseless +C6 VCM 0 60f Rser=3k Rpar=10k noiseless +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=100k Roff=1G vt=-500m vh=-120m noiseless) +.model NI VDMOS(Vto=300m kp=200m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=200m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=.7 Vrev=-300m epsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=.7 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=10k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7k Vfwd=3 Vrev=3 epsilon=50m revepsilon=50m noiseless) +.model DSI D(IS=1e-20 TT=1p noiseless) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=435m Vrev=435m epsilon=50m revepsilon=50m noiseless) +.model DLIMI D(Ron=1 Roff=100Meg Vfwd=120m Vrev=120m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model DEN D(Ron=1k Roff=100Meg Vfwd=.4 epsilon=.1 ilimit=12u noiseless) +.model DPOWS D(Ron=100 Roff=1G Vfwd=2 epsilon=.1 ilimit=.8m noiseless) +.model SPOWR SW(level=1 Ron=10 Roff=1g vt=.5 vh=-.1 ilimit=32.7m noiseless) +.ends LTC6401-14 +* +.subckt LTC6401-20 1 2 3 4 5 6 7 8 9 10 +M1 N002 N015 6 6 NI temp=27 +D5 N015 6 DLIMN +M2 N002 N006 3 3 PI temp=27 +D8 3 N006 DLIMP +C3 3 N006 .01f Rser=100 noiseless +A3 N007 N009 6 6 6 6 N006 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 N005 0 N007 N007 N007 N007 N009 N007 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N015 N009 N007 200n +D9 N009 N007 DLIM +C7 3 VINP 1p Rser=500 Rpar=2G noiseless +C13 3 6 1000p +S1 N009 N007 0 N011 SHUT2 +C17 6 7 500f +S4 N006 3 0 N011 SHUT1 +S2 6 N015 0 N011 SHUT1 +A2 6 7 0 0 0 0 N011 0 SCHMITT trise=70n tfall=180n vt=-.8 vh=10m +D6 VINM 3 DESD +D7 6 VINM DESD +D11 6 VINP DESD +M3 N022 N030 6 6 NI temp=27 +D3 N030 6 DLIMN +M4 N022 N026 3 3 PI temp=27 +D12 3 N026 DLIMP +A6 N007 N027 6 6 6 6 N026 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 N005 N007 N007 N007 N007 N027 N007 OTA g=3m linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N030 N027 N007 200n +D13 N027 N007 DLIM +S3 N027 N007 0 N011 SHUT2 +S5 N026 3 0 N011 SHUT1 +S6 6 N030 0 N011 SHUT1 +R3 N002 N019 1Meg noiseless +R4 N022 N019 1Meg noiseless +G6 N007 N027 0 N013 100µ +G7 N007 N009 0 N013 100µ +C2 3 N002 .5p Rpar=1Meg noiseless +C8 N002 6 .5p Rpar=1Meg noiseless +C9 3 N022 .5p Rpar=1Meg noiseless +C11 N022 6 .5p Rpar=1Meg noiseless +C14 N009 N002 300f Rser=400 noiseless +D2 3 6 DPOWS +S7 6 3 N011 0 SPOWR +D1 Vocmf 3 DESD +D4 6 Vocmf DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N005 0 50f Rpar=7k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(VINP),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(VINP) +B2 N004 0 I=10u*dnlim(uplim(V(VINM),V(3)-1.29,.1), V(6)+.89, .1)+1n*V(VINM) +C20 N004 0 .1f Rpar=100K noiseless +G8 0 N007 6 0 .5m +G9 0 N007 3 0 .5m +C21 N007 0 200p Rpar=1K noiseless +R5 N002 10 50 +C24 10 9 1.7p +D16 VINP 3 DESD +C12 N015 6 .01f Rser=100 noiseless +C15 3 N026 .01f Rser=100 noiseless +C19 N030 6 .01f Rser=100 noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=1n+1.8e-27*freq**2 enk=12.5k Vhigh=1e308 Vlow=-1e308 +R12 4 N002 12.5 +R6 9 N022 50 +R13 5 N022 12.5 +R2 VINM 1 100 +R8 VINP 8 100 +R1 N002 VINM 1k +R7 N022 VINP 1k +R14 Vocmf 2 2k +C18 6 Vocmf 5.3p Rpar=300k noiseless +D19 7 6 DEN +B3 0 N025 I=10u*dnlim(uplim(V(Vocmf),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(vocmf) +C27 N025 0 .1f Rpar=100K noiseless +G2 N025 0 N019 0 10µ +A8 0 N025 0 0 0 0 N013 0 OTA g=1.7m iout=1m en=3n enk=12.5k ref=7.8m Vlow=-1e308 Vhigh=1e308 +C26 N013 0 30f Rser=1k Rpar=10k noiseless +S10 3 N006 N002 3 SUPLIM +S11 3 N026 N022 3 SUPLIM +C1 3 VINM 1p Rser=500 Rpar=2G noiseless +C4 VINP 6 1p Rser=500 Rpar=2G noiseless +C5 VINM 6 1p Rser=500 Rpar=2G noiseless +D10 N005 N014 DLIMI +C6 N014 0 70f Rpar=10k noiseless +D14 N005 0 DLIM0 +C16 N022 N027 300f Rser=400 noiseless +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=100k Roff=1G vt=-620m vh=-200m noiseless) +.model NI VDMOS(Vto=300m kp=200m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=200m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=.7 Vrev=-300m epsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=.7 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=10k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7k Vfwd=3 Vrev=3 epsilon=50m revepsilon=50m noiseless) +.model DLIM0 D(Ron=100 Roff=100Meg Vfwd=250m Vrev=250m epsilon=20m revepsilon=20m noiseless) +.model DLIMI D(Ron=1 Roff=100Meg Vfwd=50m Vrev=50m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model DEN D(Ron=1k Roff=100Meg Vfwd=.4 epsilon=.1 ilimit=12u noiseless) +.model DPOWS D(Ron=100 Roff=1G Vfwd=2 epsilon=.1 ilimit=1m noiseless) +.model SPOWR SW(level=1 Ron=10 Roff=1g vt=.5 vh=-.1 ilimit=39.9m noiseless) +.ends LTC6401-20 +* +.subckt LTC6401-26 1 2 3 4 5 6 7 8 9 10 +M1 N002 N015 6 6 NI temp=27 +D5 N015 6 DLIMN +M2 N002 N006 3 3 PI temp=27 +D8 3 N006 DLIMP +C3 3 N006 .012f Rser=100 noiseless +A3 N007 N009 6 6 6 6 N006 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 N005 0 N007 N007 N007 N007 N009 N007 OTA g=3m iout=950u cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N015 N009 N007 200n +D9 N009 N007 DLIM +C7 3 VINP 1p Rser=500 Rpar=2G noiseless +C13 3 6 1000p +S1 N009 N007 0 N011 SHUT2 +C17 6 7 500f +S4 N006 3 0 N011 SHUT1 +S2 6 N015 0 N011 SHUT1 +A2 6 7 0 0 0 0 N011 0 SCHMITT trise=70n tfall=180n vt=-.8 vh=10m +D6 VINM 3 DESD +D7 6 VINM DESD +D11 6 VINP DESD +M3 N022 N030 6 6 NI temp=27 +D3 N030 6 DLIMN +M4 N022 N026 3 3 PI temp=27 +D12 3 N026 DLIMP +A6 N007 N027 6 6 6 6 N026 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 N005 N007 N007 N007 N007 N027 N007 OTA g=3m iout=950u cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N030 N027 N007 200n +D13 N027 N007 DLIM +S3 N027 N007 0 N011 SHUT2 +S5 N026 3 0 N011 SHUT1 +S6 6 N030 0 N011 SHUT1 +R3 N002 N019 1Meg noiseless +R4 N022 N019 1Meg noiseless +G6 N007 N027 0 N013 100µ +G7 N007 N009 0 N013 100µ +C2 3 N002 .5p Rpar=1Meg noiseless +C8 N002 6 .5p Rpar=1Meg noiseless +C9 3 N022 .5p Rpar=1Meg noiseless +C11 N022 6 .5p Rpar=1Meg noiseless +C14 N009 N002 400f +C16 N022 N027 400f +D2 3 6 DPOWS +S7 6 3 N011 0 SPOWR +D1 Vocmf 3 DESD +D4 6 Vocmf DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N005 0 12f Rpar=7k noiseless +B1 0 N004 I=10u*dnlim(uplim(V(VINP),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(VINP) +B2 N004 0 I=10u*dnlim(uplim(V(VINM),V(3)-1.29,.1), V(6)+.89, .1)+1n*V(VINM) +C20 N004 0 .5f Rpar=100K noiseless +G8 0 N007 6 0 .5m +G9 0 N007 3 0 .5m +C21 N007 0 200p Rpar=1K noiseless +R5 N002 10 50 +C24 10 9 1.7p +D16 VINP 3 DESD +C12 N015 6 .012f Rser=100 noiseless +C15 3 N026 .012f Rser=100 noiseless +C19 N030 6 .012f Rser=100 noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=5.5e-6/(5e3+freq**2.5/8e17) enk=13.9k Vhigh=1e308 Vlow=-1e308 +R12 4 N002 12.5 +R6 9 N022 50 +R13 5 N022 12.5 +R2 VINM 1 25 +R8 VINP 8 25 +R1 N002 VINM 500 +R7 N022 VINP 500 +R14 Vocmf 2 2k +C18 6 Vocmf 5.3p Rpar=300k noiseless +D19 7 6 DEN +B3 0 N025 I=10u*dnlim(uplim(V(Vocmf),V(3)-1.3,.1), V(6)+.9, .1)+1n*V(vocmf) +C27 N025 0 .1f Rpar=100K noiseless +G2 N025 0 N019 0 10µ +A8 0 N025 0 0 0 0 N013 0 OTA g=1.7m iout=1m en=3n enk=13.9k ref=7.8m Vlow=-1e308 Vhigh=1e308 +S10 3 N006 N002 3 SUPLIM +S11 3 N026 N022 3 SUPLIM +C1 3 VINM 1p Rser=500 Rpar=2G noiseless +C4 VINP 6 1p Rser=500 Rpar=2G noiseless +C5 VINM 6 1p Rser=500 Rpar=2G noiseless +D10 N005 N014 DLIMI +C6 N014 0 50f Rpar=50k noiseless +C22 N013 0 50f Rser=8k Rpar=10k noiseless +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=100k Roff=1G vt=-390m vh=-120m noiseless) +.model NI VDMOS(Vto=300m kp=200m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=200m lambda=.1 pchan) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=.6 Vrev=-300m epsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=.8 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=10k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=7k Vfwd=3 Vrev=3 epsilon=50m revepsilon=50m noiseless) +.model DLIM0 D(Ron=100 Roff=100Meg Vfwd=210m Vrev=210m epsilon=20m revepsilon=20m noiseless) +.model DLIMI D(Ron=1 Roff=100Meg Vfwd=100m Vrev=100m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.model DEN D(Ron=1k Roff=100Meg Vfwd=.4 epsilon=.1 ilimit=12u noiseless) +.model DPOWS D(Ron=100 Roff=1G Vfwd=2 epsilon=.1 ilimit=800u noiseless) +.model SPOWR SW(level=1 Ron=10 Roff=1g vt=.5 vh=-.1 ilimit=36.2m noiseless) +.ends LTC6401-26 +* +.subckt LTC6081 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.5f +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-147.05p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 50f Rpar=100K noiseless +M1 5 N012 4 4 NI temp=27 +C2 3 5 1p Rpar=100Meg noiseless +D5 N012 4 DLIMN +M2 5 N008 3 3 PI temp=27 +D8 3 N008 DLIMP +C3 3 N008 10f Rser=1.5Meg noiseless +A3 N009 N010 4 4 4 4 N008 4 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=100Meg noiseless +C12 N012 4 10f Rser=1Meg noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=1u linear en=12.6n enk=55.4 Vhigh=1e308 Vlow=-1e308 +C16 N010 5 790f +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=18u iout=1.4u Vhigh=1e308 Vlow=-1e308 +G1 4 N012 N010 N009 200n +D9 N010 N009 DLIM +C7 3 1 3.5p Rser=100 Rpar=5T noiseless +C13 3 4 1000p +S1 N010 N009 0 N005 SHUT2 +C1 N006 0 105f Rpar=1Meg noiseless +C17 4 6 500f Rpar=1T noiseless +G2 0 N009 4 0 .5m +G4 0 N009 3 0 .5m +C18 N009 0 200p Rpar=1K noiseless +D1 2 1 DIN +S4 N008 3 0 N005 SHUT1 +S2 4 N012 0 N005 SHUT1 +S7 3 4 N005 0 SPOW +G3 0 N007 N006 0 1m +L1 N007 0 165.7µ Cpar=63.7f Rser=1.04k Rpar=26k noiseless +C9 N008 5 50f Rser=1.5Meg noiseless +C8 5 N012 50f Rser=1.5Meg noiseless +A2 6 4 0 0 0 0 N005 0 SCHMITT trise=8u tfall=1.5u vt=.8 vh=10m +D2 3 6 DSHUT +D3 3 2 DBIAS +D4 3 1 DBIAS +D6 2 3 DESD +D7 4 2 DESD +D10 1 3 DESD +D11 4 1 DESD +C4 3 2 3.5p Rser=100 Rpar=5T noiseless +C5 1 4 3.5p Rser=100 Rpar=5T noiseless +C6 2 4 3.5p Rser=100 Rpar=5T noiseless +.model DSHUT D(Ron=85k Roff=1Meg Vfwd=.1 epsilon=50m ilimit=1u noiseless) +.model DIN D(Ron=1k Roff=10T Vfwd=1.5 epsilon=.1 Vrev=1.5 revepsilon=.1 noiseless) +.model DBIAS D(Ron=1g Roff=1T epsilon=.3 ilimit=.2p noiseless) +.model SPOW SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=252.8u noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=200m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.65 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.55 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.param Cload=1f +.param Rload=100k +.ends LTC6081 +* +.subckt LTC6082 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=.5f +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-147.05p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 50f Rpar=100K noiseless +M1 5 N011 4 4 NI temp=27 +C2 3 5 1p Rpar=100Meg noiseless +D5 N011 4 DLIMN +M2 5 N007 3 3 PI temp=27 +D8 3 N007 DLIMP +C3 3 N007 10f Rser=1.5Meg noiseless +A3 N008 N009 4 4 4 4 N007 4 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=100Meg noiseless +C12 N011 4 10f Rser=1Meg noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1u linear en=12.6n enk=55.4 Vhigh=1e308 Vlow=-1e308 +C16 N009 5 790f +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=18u iout=1.4u Vhigh=1e308 Vlow=-1e308 +G1 4 N011 N009 N008 200n +D9 N009 N008 DLIM +C7 3 1 3.5p Rser=10 Rpar=5T noiseless +C13 3 4 1000p +C1 N005 0 105f Rpar=1Meg noiseless +G2 0 N008 4 0 .5m +G4 0 N008 3 0 .5m +C18 N008 0 200p Rpar=1K noiseless +D1 2 1 DIN +G3 0 N006 N005 0 1m +L1 N006 0 170µ Cpar=177f Rser=1.07k Rpar=15.28k noiseless +C9 N007 5 50f Rser=1.5Meg noiseless +C8 5 N011 50f Rser=1.5Meg noiseless +C4 3 2 3.5p Rser=10 Rpar=5T noiseless +C5 1 4 3.5p Rser=10 Rpar=5T noiseless +C6 2 4 3.5p Rser=10 Rpar=5T noiseless +D3 3 2 DBIAS +D4 3 1 DBIAS +D6 2 3 DESD +D7 4 2 DESD +D10 1 3 DESD +D11 4 1 DESD +D2 3 4 DPOW +.model DIN D(Ron=1k Roff=10T Vfwd=1.5 epsilon=.1 Vrev=1.5 revepsilon=.1 noiseless) +.model DBIAS D(Ron=1g Roff=1T epsilon=.3 ilimit=.2p noiseless) +.model DPOW D(Ron=1k Roff=1G Vfwd=.1 epsilon=50m ilimit=252.8u noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan) +.model DLIM D(Ron=100k Roff=70Meg Vfwd=200m Vrev=200m epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.65 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.55 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.ends LTC6082 +* +.subckt LTC6409 1 2 3 4 5 6 7 8 +A1 0 6 0 0 0 0 0 0 OTA g=0 in=8.8p ink=15k +C2 4 2 .5p Rpar=660K noiseless +C3 2 8 .5p noiseless Rpar=660K +C4 6 8 .5p Rpar=660K noiseless +C5 4 6 .5p Rpar=660K noiseless +C6 N015 0 .1f Rpar=100K noiseless +A3 0 N015 N005 0 0 0 N016 0 OTA g=34m Cout=1p en=1.09n enk=24k asym Isrc=1.8m Isink=-1.6m Vlow=-1e308 Vhigh=1e308 +G1 0 N012 N016 0 1m +D1 N016 0 NML +R2 4 3 150K noiseless +R4 4 5 160K noiseless +R10 5 8 53.33K noiseless +M1 4 N006 N009 N009 N temp=27 +M2 8 N014 N009 N009 P temp=27 +D2 N008 4 XU +D3 8 N008 XD +C7 N008 0 56e-18 +G4 0 N021 N011 0 200n +C8 N021 0 56e-18 +M3 4 N017 N019 N019 N temp=27 +M4 8 N022 N019 N019 P temp=27 +D6 N021 4 XU +D7 8 N021 XD +G6 N021 0 N012 0 200n +D4 N017 N019 Y +D5 N019 N022 Y +D8 N009 N014 Y +D9 N006 N009 Y +G5 0 N008 N012 0 200n +G3 0 N008 N011 0 200n +R9 7 N013 1Meg noiseless +R11 N013 1 1Meg noiseless +A8 3 8 0 0 0 0 N005 0 SCHMITT Vt=1 Vh=10m tau=100n +A5 N005 0 N008 N008 N008 N008 N006 N008 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=10Meg Cout=50f +A7 N005 0 N008 N008 N008 N014 N008 N008 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=10Meg Cout=50f +A4 N005 0 N021 N021 N021 N021 N017 N021 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=10Meg Cout=50f +A6 N005 0 N021 N021 N021 N022 N021 N021 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=10Meg Cout=50f +D11 N011 0 CML +A2 N013 5 N005 0 0 0 N011 0 OTA G=10m Iout=10m en=0 enk=12k Cout=50p Rout=100K Vlow=-1e308 Vhigh=1e308 +B1 0 N015 I=10u*dnlim(uplim(V(2),V(4)-1.4,.1), V(8)-0.2, .1)+1n*V(2) +B2 N015 0 I=10u*dnlim(uplim(V(6),V(4)-1.39,.1), V(8)-.21, .1)+1n*V(6) +D10 4 8 43uA +R6 6 2 860 noiseless +L1 N012 0 .1051µ Rser=1.5K Rpar=3K noiseless +L2 N009 7 1n Rpar=8.5 noiseless +C19 4 N009 .375p +C12 N009 8 .375p +C13 7 8 .375p +C14 4 7 .375p +C15 4 1 .375p +C16 4 N019 .375p +C17 N019 8 .375p +C18 1 8 .375p +D13 4 2 33uA +D14 4 6 33uA +L3 N019 1 1n Rpar=8.5 noiseless +A9 0 2 0 0 0 0 0 0 OTA g=0 in=8.8p ink=15k +G2 0 N011 5 4 table(-8,0,-1.49,0,-1.4,11m,0,15m) +G7 N011 0 8 5 table(-8,0,-490m,0,-400m,11m,0,15m) +S1 N012 0 8 5 SoffL +S2 0 N012 5 4 SoffH +.model N VDMOS(Vto=-55m Kp=16.7) +.model P VDMOS(Vto=55m Kp=16.7 pchan) +.model XU D(Ron=1K Roff=10Meg Vfwd=-1 epsilon=.1 noiseless) +.model XD D(Ron=1K Roff=10Meg Vfwd =-.002 epsilon=.1 noiseless) +.model Y D(Ron=10K Roff=1T Vfwd=30m epsilon=10m noiseless) +.model CML D(Ron=1 Roff=50K Vfwd=6 Vrev=6 revepsilon=1 epsilon=1 noiseless) +.model NML D(Ron=1 Roff=50K Vfwd=8 Vrev=8 revepsilon=1 epsilon=1 noiseless) +.model 43uA D(Ron=10K Ilimit=43u epsilon=.5 noiseless) +.model 33uA D(Ron=5K Ilimit=33u epsilon=.5 noiseless) +.model SoffL SW(Ron=10 Roff=1Meg vt=-.4 vh=-.1) +.model SoffH SW(Ron=10 Roff=1Meg vt=-1.4 vh=-.1) +.ends LTC6409 +* +.subckt LT1999-x 1 2 3 4 5 6 7 8 +D1 1 N012 A temp=27 +M3 N005 I1 5 5 NN temp=27 +M4 N004 I2 5 5 NN temp=27 +A2 N004 N005 N002 5 5 5 I1 5 OTA G=5m Cout=100p Rout=100K +A3 N005 N004 N002 5 5 5 I2 5 OTA G=5m Cout=100p Rout=100K +C2 N005 N004 .1p +R7 5 N005 40Meg noiseless +A4 8 5 5 5 5 5 N002 5 SCHMITT Vt=1 Vh=10m Tau=1u +C4 1 7 1p +C5 7 5 1p +C6 8 5 1p +C8 3 5 1p +C9 2 5 1p +D7 5 2 5V +D8 5 3 5V +M1 1 N006 7 7 N temp=27 +M2 5 N011 7 7 P temp=27 +D9 N006 7 XN +A5 N002 5 N008 N008 N008 N008 N006 N008 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-10 Rout=10Meg Cout=50f +A6 N002 5 N008 N008 N008 N011 N008 N008 SCHMITT Vt=.5 Vh=10m Vhigh=10 Vlow=0 Rout=10Meg Cout=50f +B1 0 X0 I=10u*dnlim(uplim(V(6),V(1)-{if(Gain<15,1.1,1)},.1), V(5)+{if(Gain<15,1.1,1)}, .1) +C7 X0 0 100f Rpar=100K noiseless +R2 1 N010 100Meg noiseless +R5 N010 5 100Meg noiseless +G5 0 N008 N010 0 1µ +C10 N008 0 90f Rpar=1Meg noiseless +A7 0 X0 N002 5 5 5 N010 5 OTA g=100u iout=37.5u en={Gain*97n} enk=8 Cout=12p Vlow=-1e308 Vhigh=1e308 +C12 N005 5 2p Rser=10k noiseless +S1 1 6 N002 5 160K +S2 6 5 N002 5 160K +C1 1 6 1p +C3 6 5 1p +G2 N010 5 N010 1 50µ dir=1 vto=-440m +G7 5 N010 5 N010 50µ dir=1 vto=-400m +S3 N005 2 N002 5 4K +S4 N004 3 N002 5 4K +G1 X0 0 N001 0 10µ +S6 N012 N005 N002 5 800 +S7 N004 N012 N002 5 800 +A1 N004 3 N002 5 5 5 N001 5 OTA G=250u iout=5m Cout=.1p Vlow=-1e308 Vhigh=1e308 +A8 2 N005 N002 5 5 5 N001 5 OTA G=250u iout=5m Cout=.1p Rout=1G Vlow=-1e308 Vhigh=1e308 +D2 1 8 DSHUT +R3 N004 5 40Meg noiseless +D3 7 N011 XP +R4 7 N001 {4k*Gain} noiseless +.model N VDMOS(Vto=-300m Kp=33m) +.model P VDMOS(Vto=300m Kp=33m pchan) +.model NN VDMOS(Vto=-52m Kp=100m) +.model XN D(Ron=1 Roff=1T Vfwd=1.06 epsilon=.1 noiseless) +.model XP D(Ron=1 Roff=1T Vfwd=1 epsilon=.1 noiseless) +.model Y D(Ron=1K Roff=1T Vfwd=1.85 Vrev=1.85 epsilon=2 revepsilon=2 noiseless) +.model A D(Cjo=2p noiseless) +.model 160K SW(Ron=160K Roff=920K Vt=.5 Vh=-.2 noiseless) +.model 4k SW(Ron=4k Roff=1G Vt=.5 Vh=-.4 noiseless) +.model 800 SW(Ron=4k Roff=1G Vt=.5 Vh=-.4 noiseless) +.model 5V D(Ron=10 Roff=1G Vfwd=5 epsilon=.5 noiseless) +.model DSHUT D(Ron=10k Roff=2Meg Vfwd=2.5 epsilon=.2 ilimit=.75u noiseless) +.ends LT1999-x +* +.subckt LTC6416 1 2 3 4 5 6 7 8 9 +Q1 9 N004 N002 0 NPN1 temp=27 +Q2 6 N006 N004 0 PNP1 temp=27 +D1 9 N004 DBIAS1 +D2 N002 6 DBIAS2 +G5 N004 6 N004 2 3 dir=1 vto=.67 +R1 9 N004 10Meg noiseless +G8 9 N004 5 N002 10 dir=1 vto=0 +Q3 9 N013 N011 0 NPN1 temp=27 +Q4 6 N015 N013 0 PNP1 temp=27 +D7 9 N013 DBIAS1 +D8 N011 6 DBIAS2 +G11 N013 6 N013 2 3 dir=1 vto=.67 +R2 9 N013 10Meg noiseless +R7 N003 3 6k noiseless +R8 N003 4 6k noiseless +R9 9 1 10.8k noiseless +R11 9 2 6k noiseless +C1 N002 6 .1p +C2 N011 6 .1p +C4 N004 N013 .2f +C5 8 6 1p Rpar=1Meg +C6 7 6 1p Rpar=1Meg noiseless +C7 1 6 1p Rpar=3.6k noiseless +D11 3 6 DBIASIN +D12 4 6 DBIASIN +A3 0 0 3 3 3 3 N006 3 OTA g=0 rout=10 linear en=1.27n enk=25k +A2 0 0 4 4 4 4 N015 4 OTA g=0 rout=10 linear en=1.27n enk=25k +A4 9 3 0 0 0 0 0 0 OTA g=0 in=6.5p +A5 9 4 0 0 0 0 0 0 OTA g=0 in=6.5p +C8 2 6 1p Rpar=13k noiseless +R5 9 5 13.5k noiseless +C9 5 6 1p Rpar=2.5k noiseless +G2 9 N004 6 N002 10 vto=-.2 dir=1 +G1 9 N013 6 N011 10 vto=-.2 dir=1 +G3 9 N013 5 N011 10 dir=1 vto=0 +G4 N004 6 N004 6 3 dir=1 vto=3 +G6 N013 6 N013 6 3 dir=1 vto=3 +A1 1 N003 N003 N003 N003 N003 9 N003 OTA g=2m iout=1.7m Rout=100Meg Cout=33p Vlow=-1e308 Vhigh=1e308 +R3 8 N002 9 noiseless +R4 7 N011 9 noiseless +.model NPN1 NPN(BF=1000 Is=1e-13 NF=1 TF=100p cje=1p cjc=2p noiseless) +.model PNP1 PNP(BF=177 Is=1e-14 TF=1n cje=1p cjc=1p Rc=20 noiseless) +.model DBIAS1 D(Ron=10 Roff=1Meg vfwd=.15 epsilon=.1 ilimit=4m noiseless) +.model DBIAS2 D(Ron=10 Roff=1Meg vfwd=.15 epsilon=.1 ilimit=16.8m noiseless) +.model DBIASIN D(Ron=10 Roff=1Meg vfwd=.1 epsilon=.1 ilimit=20u noiseless) +.model DCLHI D(Roff=1k Ron=1 Vfwd=2.5 epsilon=.1 Vrev=-.2 revepsilon=.1 noiseless) +.model DTRK D(Roff=1T Ron=1 Vfwd=-50m epsilon=50m noiseless) +.model Sout SW(Ron=1.5 Roff=100G Vt=0.5 vh=-.2 noiseless) +.model Spow SW(Ron=1 Roff=1Meg Vt=-.5 vh=-.2 noiseless) +.model Sbias SW(level=2 Ron=10 Roff=1Meg Vt=0.5 vh=-.2 ilimit=26m noiseless) +.model SvorL SW(Ron=1 Roff=1Meg vt=0 vh=-10m noiseless) +.model SvorH SW(Ron=1 Roff=1Meg vt=.67 vh=-10m noiseless) +.ends LTC6416 +* +.subckt LTC6417 1 2 3 4 5 6 7 8 9 10 11 +Q1 1 N005 N008 0 NPN1 temp=27 +Q2 2 N007 N005 0 PNP1 temp=27 +D1 1 N005 DBIAS1 +D2 N008 2 DBIAS2 +G1 0 N004 9 2 1m +D3 N004 0 DPWRADJ +G3 1 N005 N004 0 1.3m +G2 N008 2 N004 0 13m +G4 2 N012 8 2 1m +D4 N012 2 DCLHI +G5 N005 2 N005 N012 3 dir=1 vto=.67 +R1 1 N005 10Meg noiseless +D5 N003 2 DCLHI +D6 N003 N012 DTRK +G8 1 N005 N003 N008 10 dir=1 vto=0 +Q3 1 N016 N018 0 NPN1 temp=27 +Q4 2 N017 N016 0 PNP1 temp=27 +D7 1 N016 DBIAS1 +D8 N018 2 DBIAS2 +G9 1 N016 N004 0 1.3m +G10 N018 2 N004 0 13m +G11 N016 2 N016 N012 3 dir=1 vto=.67 +R2 1 N016 10Meg noiseless +G12 1 N016 N003 N018 10 dir=1 vto=0 +A1 10 2 0 0 0 N011 0 0 SCHMITT Vt=2.75 vh=10m trise=100n tfall=100n +S1 5 N008 N011 0 sout +S3 N004 0 0 N011 spow +S4 2 N008 N011 0 sbias +S2 6 N018 N011 0 sout +S5 2 N018 N011 0 sbias +R7 N002 3 9.25k noiseless +R8 N002 4 9.25k noiseless +R9 1 7 10.8k noiseless +R11 1 8 9.6k noiseless +R13 1 9 45.3k noiseless +D9 1 11 DBIAS3 +D10 11 2 DCLP +C1 N008 2 1p +C2 N018 2 1p +C4 N005 N016 .2p +C5 5 2 1p Rpar=1Meg noiseless +C6 6 2 1p Rpar=1Meg noiseless +C7 7 2 1p Rpar=3.6k noiseless +C8 9 2 1p Rpar=21.3k noiseless +C9 8 2 1p Rpar=9.6k noiseless +C10 10 2 1p Rpar=14k noiseless +C11 1 11 1p +C12 11 2 1p +C13 N003 2 1p +C14 N012 2 1p +C15 N004 0 1p +D11 3 2 DBIASIN +D12 4 2 DBIASIN +A3 0 0 3 3 3 3 N007 3 OTA g=0 rout=1 linear en=1.05n enk=25k +A2 0 0 4 4 4 4 N017 4 OTA g=0 rout=1 linear en=1.05n enk=25k +A4 1 3 0 0 0 0 0 0 OTA g=0 in=3.3p +A5 1 4 0 0 0 0 0 0 OTA g=0 in=3.3p +G13 N003 2 8 2 1m +G7 2 N003 7 2 2m +S10 2 11 N005 N012 svorh +S9 2 11 N003 N008 svorl +S8 2 11 N016 N012 svorh +S11 2 11 N003 N018 svorl +A6 7 N002 N002 N002 N002 N002 1 N002 OTA g=2m iout=88u Rout=100Meg Cout=42p Vlow=-1e308 Vhigh=1e308 +.model NPN1 NPN(BF=1000 Is=1e-13 NF=1 TF=50p cje=2p cjc=5p noiseless) +.model PNP1 PNP(BF=177 Is=1e-14 TF=5n cje=1p cjc=1p noiseless) +.model DBIAS1 D(Ron=10 Roff=1Meg vfwd=.15 epsilon=.1 ilimit=2.5m noiseless) +.model DBIAS2 D(Ron=10 Roff=1Meg vfwd=.15 epsilon=.1 ilimit=10.6m noiseless) +.model DBIAS3 D(Ron=10 Roff=1Meg vfwd=.7 epsilon=.1 ilimit=2m noiseless) +.model DBIASIN D(Ron=10 Roff=1Meg vfwd=.1 epsilon=.1 ilimit=28u noiseless) + .model DCLP D(Ron=1 Roff=20k vfwd=3.4 epsilon=.1 noiseless) +.model DPWRADJ D(Roff=850 Ron=2 Vfwd=1.78 epsilon=1.9 Vrev=0 revepsilon=100m noiseless) +.model DCLHI D(Roff=1k Ron=1 Vfwd=2.5 epsilon=.1 Vrev=-.2 revepsilon=.1 noiseless) +.model DTRK D(Roff=1T Ron=1 Vfwd=-50m epsilon=50m noiseless) +.model Sout SW(Ron=1.5 Roff=100G Vt=0.5 vh=-.2 noiseless) +.model Spow SW(Ron=1 Roff=1Meg Vt=-.5 vh=-.2 noiseless) +.model Sbias SW(level=2 Ron=10 Roff=1Meg Vt=0.5 vh=-.2 ilimit=26m noiseless) +.model SvorL SW(Ron=1 Roff=1Meg vt=0 vh=-10m noiseless) +.model SvorH SW(Ron=1 Roff=1Meg vt=.67 vh=-10m noiseless) +.ends LTC6417 +* +.subckt LT6105 1 2 3 4 5 6 +C1 2 6 1p +C2 6 3 1p +C3 2 1 1p +C4 1 3 1p +A2B N001 0 0 0 0 0 N006 0 OTA g=200u iout=5u Cout=20p Vhigh=1e308 Vlow=-1e308 +D2 N006 0 DLIM +D3 1 3 DBIAS +D4 6 3 DBIAS +D5 2 3 DP +C8 N001 0 20p Rpar=100K noiseless +B3 N001 0 I=10u*dnlim(uplim(V(1),V(3)+44.11,.1), V(3)-.41, .1) + 1p*V(1) +B4 0 N001 I=10u*dnlim(uplim(V(6),V(3)+44.1,.1), V(3)-.4, .1)+ 1p*V(6) +A1B N001 0 0 0 0 0 N003 0 OTA g=200u iout=5u Cout=20p Vhigh=1e308 Vlow=-1e308 +D8 N003 0 DLIM +S1 N006 0 3 1 SWH +S2 0 N003 1 3 SWL +C5 1 3 100f Rpar=1G +Q1 N004 N002 2 0 P temp=27 +Q2 1 N002 2 0 P temp=27 +Q3 3 N009 6 0 P temp=27 +C6 N002 3 1f +C7 N009 3 1f +G3 N002 3 0 N003 10µ dir=1 vto=0 +G1 N009 3 0 N006 10µ dir=1 vto=0 +Q4 N004 N010 2 0 P temp=27 +C13 N010 3 1f +G2 N010 3 0 N006 10µ dir=1 vto=0 +C11 N004 3 100f Rpar=1G +C12 N003 N004 4p Rser=100k +D1 N004 4 DDROP +C10 4 3 100f Rpar=1G +C9 N004 N006 4p Rser=100k +C14 6 1 10f +.model SWL SW(Ron=1 Roff=1g vt=1.6 vh=-10m noiseless) +.model SWH SW(Ron=1 Roff=1g vt=-1.59 vh=-10m noiseless) +.model DLIM D(Ron=100 Roff=600g Vfwd=.8 Vrev=.8 epsilon=10m revepsilon=10m) +.model DBIAS D(Ron=1Meg Roff=1G Vfwd=1.4 epsilon=100m ilimit=20u) +.model DP D(Ron=1k Roff=1G Vfwd=.5 epsilon=100m ilimit=199.9u) +.model P PNP(BF=500 BR=1 Cjc=2f Cje=10f) +.model DDROP D(Ron=1 Roff=1Meg Vfwd=.9 epsilon=.3) +.ends LT6105 +* +.subckt LTC2057 1 2 3 4 5 6 7 +M1 6 N008 5 5 N temp=27 +M2 4 N003 5 5 P temp=27 +R2 6 N012 2G noiseless +A3 N011 N021 0 0 0 0 N020 0 SCHMITT Vt=1.5 Vh=100m trise=4u tfall=2u +C14 0 N010 50p Rpar=6k noiseless +G3 0 N010 0 N006 584µ +C2 6 5 1p Rpar=1G noiseless +A2 0 N007 0 0 0 0 N006 0 OTA g=1m linear en= 1.0e-8*(12k+ 4.3*uplim((freq-1.5k)**.8,4k,100))/(dnlim((freq+50k)**.8,10k,2k)) Rout=1k Cout=10p Vlow=-1e308 Vhigh=1e308 +S2 6 4 ON 0 SPOW2 +C3 N012 0 3n Rser=60 Lser=200n cpar=100f noiseless +C4 6 3 1.5p Rser=1k noiseless +R6 N011 1 10k noiseless +R8 N021 7 10k noiseless +A1 6 4 0 0 0 0 N014 0 SCHMITT Vt=4.75 Vh=50m tau=50u +A6 N014 0 0 0 N020 0 ON 0 AND trise=30u tfall=1u +C7 4 N011 100f +C8 4 N021 100f +D8 4 1 DESDL +D9 4 7 DESDL +D10 1 6 DESDL +D11 7 6 DESDL +D12 2 3 DIN +D13 N006 0 DLIMF +G4 0 X4 N012 0 1µ +L1 X4 0 459.3m Rser=2.6Meg Rpar=1.625Meg Cpar=23.87f noiseless +D14 N009 N006 DLIMR1 +C11 N009 0 45n +A8 N009 0 0 0 0 0 N010 0 OTA g=2m iout=3u vlow=-1e308 vhigh=1e308 +D15 0 N009 DLIMR2 +C13 5 4 1p Rpar=1G noiseless +S5 6 4 ON 0 SPOW1 +C16 4 1 100f +C17 4 7 100f +I2 0 N015 42n +S7 0 N015 3 4 SB1 +C20 N015 0 1p Rpar=1k noiseless +C21 N005 0 1p Rpar=1k noiseless +G14 2 3 N015 0 1µ +G15 3 4 N005 0 1µ +G16 0 N005 3 4 35p vto=35 dir=1 +G12 2 4 N005 0 1µ +G7 0 N005 2 4 35p vto=35 dir=1 +S6 0 N015 2 4 SB1 +C1 3 4 1.5p Rser=1k noiseless +C6 6 2 1.5p Rser=1k noiseless +C9 2 4 1.5p Rser=1k noiseless +D16 6 4 DPOW +C18 6 4 100p +R4 6 N011 100Meg noiseless +R9 4 N021 100Meg noiseless +D1 3 6 DESDH +D3 4 3 DESDH +D4 2 6 DESDH +D7 4 2 DESDH +S10 0 VInoi 6 4 Snoise +GInoi 2 3 VInoi 0 1µ +R3 N012 4 2G noiseless +C22 6 N003 .1f Rpar=1Meg noiseless +D17 N003 6 DLOF +D18 4 N008 DLOF +D5 5 N003 Y +D6 N008 5 Y +C12 N008 4 .1f Rpar=1Meg noiseless +C15 N003 N008 100f +A5 6 X4 N013 6 6 6 N003 6 OTA g=1u linear vlow=-1e308 vhigh=1e308 +A9 4 X4 N018 4 4 4 N008 4 OTA g=1u linear vlow=-1e308 vhigh=1e308 +A10 ON 0 4 4 4 4 N018 4 SCHMITT vt=.5 vh=.1 trise=5u +A4 ON 0 6 6 6 6 N013 6 SCHMITT vt=.5 vh=.1 trise=5u +G8 0 N012 0 N010 10m +G5 6 N003 0 ON 5µ vto=-.5 dir=1 +G6 N008 4 0 ON 5µ vto=-.5 dir=1 +G1 N007 0 N012 6 500µ dir=1 vto=830m +G2 0 N007 4 N012 500µ dir=1 vto=830m +G9 X4 0 X4 6 80µ dir=1 vto=-48m +G10 0 X4 4 X4 80µ dir=1 vto=-43m +B1 0 N007 I=dnlim(uplim(10u*(dnlim(uplim(V(3),V(6)-1.4,.1),V(4)-.2, .1)+1n*V(3) -dnlim(uplim(V(2),V(6)-1.39,.1),V(4)-.2, .1)+1n*V(2)),5u,1u),-5u,1u) +S11 0 N007 N012 6 SVLIMU +S12 N007 0 4 N012 SVLIMD +S4 0 N007 0 ON Soff +C19 N007 0 1f +D19 6 N011 DP5U +D20 N021 4 DP5U +G11 N011 N021 N011 N021 1m dir=1 vto=4.5 +G13 N021 N011 N021 N011 1m dir=1 vto=700m +.model SPOW1 SW(level=2 Ron=500 Roff=1G vt=.5 vh=-.1 ilimit=.5m noiseless) +.model SPOW2 SW(level=2 Ron=550k Roff=1G vt=.5 vh=-.1 noiseless) +.model DPOW D(Ron=10k Roff=1G vfwd=2 epsilon=500m ilimit=2.46u noiseless) +.model DP5U D(Ron=1k Roff=100Meg vfwd=100m epsilon=100m ilimit=.5u noiseless) +.model Snoise SW(level=2 ron=900k Roff=2.2meg vt=25 vh=-20) +.model DESDH D(Ron=100 Roff=500T vfwd=700m epsilon=700m noiseless) +.model DESDL D(Ron=100 Roff=1G vfwd=700m epsilon=700m noiseless) +.model Y D(Ron=1k Roff=1T Vfwd=.8 epsilon=100m noiseless) +.model N VDMOS(Vto=-80m Kp=95m ) +.model P VDMOS(Vto=80m Kp=75m pchan) +.model DIN D(Ron=1.6k Roff=1g vfwd=.7 vrev=.7 epsilon=200m revepsilon=200m noiseless) +.model DLIMF D(Ron=.1 Roff=1Meg vfwd=115m epsilon=100m noiseless) +.model DLIMR1 D(Ron=.1 Roff=1Meg vfwd=24m epsilon=100m noiseless) +.model DLIMR2 D(Ron=.1 Roff=100 vfwd=5m epsilon=100m noiseless) +.model sb1 sw(level=2 ron=1k Roff=20k vt=1 vh=-2 ilimit=40n noiseless) +.model Soff SW(level=2 Roff=130k Ron=.1 vt=-.5 vh=10m noiseless) +.model DLOF D(Ron=1 Roff=1g vfwd=1 epsilon=500m noiseless) +.model SVLIMU SW(Ron=1 Roff=1Meg vt=900m vh=-.2 noiseless) +.model SVLIMD SW(Ron=1 Roff=1Meg vt=900m vh=-.2 noiseless) +.ends LTC2057 +* +.subckt LTC2875 1 2 3 4 5 6 7 8 +C2 on1 0 1p Rpar=1k +A1 on1 0 0 0 0 0 trigoff 0 BUF trise=4m tfall=100n +R1 state 0 1k +C1 shutdown 0 1p Rpar=1k +R3 3 8 250k +G1 2 VREF powOK 0 11m +D1 VREF 8 DR +B1 0 SG I= uplim( dnlim(2.5e-4*V(VREF,8),3u+2u*V(VCCHIB),3u) ,42u-7u*V(VCCHIB),10u) +A2 3 2 0 0 0 0 powOK 0 SCHMITT vt=2.525 vh=75m trise=10u tfall=100n +M4 N009 N007 LSEN LSEN NDRV +M3 7 N004 HSEN HSEN PDRV +M1 N004 N004 HSEN HSEN PDRV M=1e-3 +M6 N007 N007 2 2 NDRV M=1e-3 +R6 3 N007 1G +R7 N004 2 1G +C4 N009 N007 1f +G2 3 N007 NU 0 14µ +G3 N004 2 PD 0 14µ +D2 6 N009 DNout +C7 6 N009 100f +G4 N007 2 N007 3 10m vto=0 dir=1 +G5 3 N004 2 N004 10m vto=0 dir=1 +C10 6 2 8p +C11 7 2 10p +M2 7 N005 HSEN HSEN PDRV2 +M5 N009 N012 LSEN LSEN NDRV2 +G6 0 N013 6 0 1m +L1 N013 0 1m +G7 0 N014 7 0 1m +L2 N014 0 1m +B3 0 NU I=1u*(.5+.5*tanh(V(ON)/50m))*(.3-.7*tanh((-V(SL)-(3+2*tanh((V(6,CMG)-100m)/100m))*V(SG))/.75))*(1-.9*tanh(V(CMG,CMFBO)/20m)) +C12 NU 0 1f Rpar=10Meg +B4 0 PD I=1u*(.5+.5*tanh(V(ON)/50m))*(.3-.7*tanh((V(SH)-(3+2*tanh((V(CMG,7)-100m)/100m))*V(SG))/.75))*(1+.9*tanh(V(CMG,CMFBO)/20m)) +C13 PD 0 1f Rpar=10Meg +D5 0 NU DLIM2 +D6 0 PD DLIM2 +B7 NU 0 I=1u*(.5+.5*tanh(-V(ON)/50m))*(1+dnlim(uplim(V(ON3)*60*V(SG,SL),10,.1),-10,.1)) +B5 PD 0 I=1u*(.5+.5*tanh(-V(ON)/50m))*(1+V(ON3)*60*dnlim(uplim(V(SH)+V(SG),10,.1),-10,.1)) +G9 0 CMG 2 0 .5m +G8 0 CMG 3 0 .5m +A3 3 2 0 0 0 VCCHIB 0 0 SCHMITT vt=4.1 vh=100m trise=1u +G10 0 CMG VCCHIB 0 300µ +C17 CMG 0 1p Rpar=1k +G11 3 N007 2 N007 10m vto=0 dir=1 +G12 N004 2 N004 HSEN 10m vto=0 dir=1 +S1 N004 N005 VCCHIB 0 SGN +S2 N005 HSEN 0 VCCHIB SGI +S3 LSEN N012 0 VCCHIB SGI +S4 N007 N012 VCCHIB 0 SGN +R14 LSEN 2 1 +C18 N005 7 1f +C19 N009 N012 1f +A4 6 2 0 0 0 0 ImaxSnk 0 OTA g=2.2u iout=90u ref=47 Rout=1Meg Cout=10p vlow=7 vhigh=200 +A6 2 7 0 0 0 0 ImaxSrc 0 OTA g=2.2u iout=90u ref=51 Rout=1Meg Cout=10p vlow=10 vhigh=200 +S5 0 PD N022 ImaxSrc SCL +G14 0 N021 LSEN 2 1 +C21 N021 0 100f Rpar=1k +S6 0 NU N021 ImaxSnk SCL +R11 3 1 500k +C22 1 2 100f +M7 N023 N028 2 2 NI temp=27 +C23 3 N023 1p Rpar=10Meg noiseless +M8 N023 N024 3 3 PI temp=27 +C24 3 N024 .01f Rpar=100Meg Rser=50k noiseless +C25 N023 2 1p Rpar=10Meg noiseless +A9 N023 CMG_R 0 0 0 0 N026 0 OTA g=1m linear Rout=1k Cout=50p Vlow=-.5 Vhigh=.5 +A10 N025 0 CMG_R CMG_R CMG_R CMG_R N027 CMG_R OTA g=28u linear rout=700k Vlow=-1e308 Vhigh=1e308 +A11 CMG_R N027 2 2 2 2 N028 2 OTA g=10n ref=350m iout=20n vlow=-1e308 vhigh=1e308 +C27 N028 2 .1f Rpar=100Meg Rser=50k noiseless +G15 3 N024 3 N024 45n vto=890m dir=1 +G16 N028 2 N028 2 45n vto=890m dir=1 +C30 N023 N027 1.2p Rser=180k +A12 0 N026 0 0 0 0 N025 0 OTA g=1m linear Rout=1k Cout=1p Vlow=-1e308 Vhigh=1e308 +G17 0 N017 N018 0 1µ +A13 N015 CMG_R _SHDN 0 0 0 N018 0 OTA g=80n Iout=20u vlow=-1e308 vhigh=1e308 +M9 3 N016 N015 N015 N temp=27 +M10 2 N019 N015 N015 P temp=27 +C26 3 N015 1p Rpar=1G noiseless +D3 N016 N015 Y +D4 N015 N019 Y +A14 _SHDN 0 N017 N017 N017 N017 N016 N017 SCHMITT Vt=.5 Vh=10m Vhigh=0 Vlow=-18 Rout=1k Cout=5p +A15 _SHDN 0 N017 N017 N017 N019 N017 N017 SCHMITT Vt=.5 Vh=10m Vhigh=18 Vlow=0 Rout=1k Cout=5p +C31 N015 2 1p Rpar=1G noiseless +C32 N017 0 12f Rpar=1Meg +A16 shutdown 0 0 0 0 _SHDN 0 0 BUF trise=63.2u tfall=286n +S7 6 N010 _SHDN 0 SW40k +R8 N010 N015 1.4k +S8 7 N011 _SHDN 0 SW40k +R9 N011 N015 1.4k +C35 N010 2 1p +C36 3 N018 5f Rpar=10G +C37 N018 2 5f Rpar=10G +A5 0 on1 SRG2 0 0 0 On 0 OTA g=3u asym isource=9.5u isink=-9u Rout=5Meg Cout=420f ref=-.275 vlow=-1 vhigh=1 +C33 SG 0 100f Rpar=500k +B6 0 SRG2 I= uplim( dnlim(2.5e-4*V(VREF,8),1.3u-.3u*V(VCCHIB),1.5u) ,42u-28u*V(VCCHIB),10u)*(.5+.5*tanh(V(powOK)/100m)) +C38 SRG2 0 100f Rpar=500k +C9 7 6 8.4p +C39 N015 2 1p +S14 NU 0 0 _SHDN SCSD +S15 PD 0 0 _SHDN SCSD +S16 3 N024 0 _SHDN SCSD +S17 N028 2 0 _SHDN SCSD +S18 N027 CMG_R 0 _SHDN SCSD +G19 on1 2 VCCHIB 0 50µ +S19 2 3 _SHDN 0 SBURN1 +S20 2 3 on1 0 SBURN2 +A7 shutdown 0 0 0 0 0 SHDN 0 BUF trise=286n tfall=63.2u +C28 4 2 100f +S10 2 4 N020 SHDN SRXD +S11 4 3 _SHDN N020 SRXD +C29 8 2 100f +C40 VREF 2 100f Rpar=100 +S12 N015 2 0 _SHDN SDR +A18 7 6 0 0 0 0 N020 0 SCHMITT vt=700m vh=75m trise=88n tfall=98n +C8 5 2 100f +D7 3 HSEN D1OHM +A17 HSEN 3 0 0 0 0 N022 0 OTA g=1m linear ref=-150m Rout=1Meg Cout=.1f vlow=-1e308 vhigh=1e308 +C3 HSEN 2 1p +D10 HSEN 2 DLEAK +C14 N011 2 1p +R4 7 CMFBO 1.2Meg +R5 CMFBO 6 1.2Meg +A19 ON 0 0 0 0 0 ON3 0 SCHMITT vt=-.9 vh=0 trise=100n tripdt=10n IC=0 +C5 N004 7 1f +G13 0 SH N014 0 100m +G18 0 SL N013 0 100m +C15 SL 0 1e-18 Rpar=10 IC=0 +C6 SH 0 1e-18 Rpar=10 IC=0 +D8 N023 5 DCURL +D11 4 3 DRXDH +D9 2 4 DRXDL +D13 2 N011 DESDC +D12 2 N010 DESDC +A20 shutnowin 0 0 0 0 0 shutnowout 0 BUF trise=100n +C20 shutnowin 0 1p Rpar=1k +R10 3 4 500k +A21 CMG_R N027 2 2 2 2 N024 2 OTA g=10n ref=-350m iout=20n vlow=-1e308 vhigh=1e308 +G20 2 CMG_R CMG 0 1m +C34 CMG_R 2 1p Rpar=1k +.machine +.state shutdown -1 +.state off 0 +.state rdy 0 +.state on 1 +.rule * shutdown V(shutnowout) > .6 | V(PowOK) < .5 +.rule shutdown off V(shutnowout) < .4 & V(PowOK) >.6 +.rule off rdy V(1,2) > .66*V(3,2) & V(_SHDN) > .7 +.rule rdy on V(1,2) < .33*V(3,2) +.rule on off V(1,2) > .67*V(3,2) | V(trigoff) > .5 +.output (on1) state > .5 +.output (shutdown) state < -.5 +.output (state) state +.endmachine +.model SBURN1 SW(Ron=10 Roff=1G vt=.5 vh=-.3 ilimit=1.52m) +.model SBURN2 SW(Ron=10 Roff=1g vt=.5 vh=-.3 ilimit=4.2m) +.model SGN SW(level=2 Ron=100 Roff=1G vt=.5 vh=-.2) +.model SGI SW(level=2 Ron=100 Roff=1G vt=-.5 vh=-.2 ) +.model SCL SW(level=2 Ron=1k Roff=1G vt=0 vh=1) +.model Y D(Ron=10k Roff=1T Vfwd=4 epsilon=.1 noiseless) +.model N VDMOS(Vto=-360m Kp=4m) +.model P VDMOS(Vto=360m Kp=4m pchan) +.model SW40k SW(Ron=40k Roff=1G vt=.5 vh=-.2) +.model SDR SW(Ron=1k Roff=1G vt=-.5 vh=-.2) +.model SCSD SW(Ron=1k Roff=1G vt=-.5 vh=-.2) +.model SRXD SW(Ron=45 Roff=1G vt=.5 vh=-100m ilimit=11m) +.model DLEAK D(Ron=1k Roff=1G vfwd=1 epsilon=500m ilimit=100n) +.model D1OHM D(Ron=1 Roff=1G vfwd=100m epsilon=100m) +.model DCURL D(Ron=500 Roff=500 vfwd=0 vrev=0 ilimit=1m revilimit=1m) +.model DRXDH D(Ron=16 Roff=1G vfwd=600m epsilon=500m) +.model DRXDL D(Ron=14.5 Roff=1G vfwd=600m epsilon=500m) +.model DESDC D(Ron=100 Roff=1G vfwd=300m epsilon=500m Vrev=10 revepsilon=500m) +.model DR D(Ron=1k Roff=1g vfwd=-50m epsilon=100m ilimit=100u) +.model DLIM2 D(Ron=10 Roff=1G vfwd=20m epsilon=100m vrev=20 revepsilon=1) +.model DNout D(Ron=1 Roff=1g vfwd=500m epsilon=500m) +.model PDRV VDMOS(vto=-1.2 kp=7.5m mtriode=2 lambda=.05 is=0 rds=1g pchan) +.model NDRV VDMOS(vto=1.2 kp=7.5m mtriode=2 lambda=.05 rds=1g is=0) +.model PDRV2 VDMOS(vto=-1.2 kp=30m mtriode=2 lambda=.05 is=0 pchan) +.model NDRV2 VDMOS(vto=1.2 kp=28m mtriode=1.3 lambda=.05 is=0) +.model PI VDMOS(Vto=-300m Kp=2m lambda=.01 pchan) +.model NI VDMOS(Vto=300m kp=2m lambda=.01) +.machine +.state low 0 +.state high 1 +.rule low high V(8,2) > .9*V(3,2) +.rule high low V(8,2) < .5*V(3,2) +.output (shutnowin) state +.endmachine +.ends LTC2875 +* +.subckt LTC6261 1 2 3 4 5 6 +A1 2 0 0 0 0 0 0 0 OTA g=0 in=600f +B1 0 N005 I=10u*dnlim(uplim(V(1),V(4)+.2,.1), V(5)-.2, .1)+1n*V(1) +B2 N005 0 I=10u*dnlim(uplim(V(2),V(4)+.21,.1), V(5)-.21, .1)+1n*V(2) +C10 N005 0 .1f Rpar=100K noiseless +M1 N012 N010 5 5 NI temp=27 +C2 4 3 10f +M2 N006 N004 4 4 PI temp=27 +C11 3 5 10f +D6 N010 5 DLIMN +A4 0 N005 0 0 0 0 N008 0 OTA g=1m linear en=10.25n*(1+freq/4.3Meg) enk=600 Rout=1k Cout=2p Vlow=-1e308 Vhigh=1e308 +C16 N009 3 1.5p +C7 4 1 150f +D14 4 N004 DLIMP +C4 2 1 325f Rpar=1Meg noiseless +A6 N008 0 N014 N007 N007 N007 N009 N007 OTA g=520u asym isource=600u isink=-750u Vlow=-1e308 Vhigh=1e308 +A5 N007 N009 N014 N007 N007 N007 N004 N007 OTA g=12n ref=-280m linear Vlow=-1e308 Vhigh=1e308 +C14 4 5 20p Rpar=1.25Meg noiseless +S4 4 5 N014 N007 SWP +C13 4 5 10p +A3 6 5 N007 N007 N007 N007 N014 N007 SCHMITT vt=1 vh=.2 trise=18u tfall=6u +G2 0 REF 4 0 50m +G3 0 REF 5 0 50m +C19 REF 0 100p Rpar=10 noiseless +GESD1 2 4 2 4 1 vto=600m dir=1 +GESD2 5 2 5 2 1 vto=600m dir=1 +GESD3 1 4 1 4 1 vto=600m dir=1 +GESD4 5 1 5 1 1 vto=600m dir=1 +D1 3 4 DESD +D2 5 3 DESD +C1 4 2 225f +C5 1 5 150f +C6 2 5 225f +A8 N007 N009 N014 N007 N007 N007 N010 N007 OTA g=12n ref=280m vlow=-1e308 vhigh=1e308 +C3 N004 3 .35f Rser=60Meg noiseless +C12 N009 N007 28p Rser=15k noiseless +C15 4 N004 .02f Rser=80Meg noiseless +C20 N009 N007 4p +D3 N009 N007 DANTISAT +R3 N006 3 10 noiseless +I1 3 N006 6m +D4 3 N012 DSAT +I2 N012 3 10n +R4 N007 REF 10 noiseless +A7 N007 REF 4 4 4 4 0 4 OTA g=100m asym isource=10m isink=-1u vlow=-1e308 vhigh=1e308 +A9 REF N007 0 0 0 0 5 0 OTA g=100m asym isource=10m isink=-1u vlow=-1e308 vhigh=1e308 +R5 4 6 5Meg noiseless +C18 N010 5 .02f Rser=80Meg noiseless +C9 3 N010 .35f Rser=60Meg noiseless +S1 2 5 4 2 Sbias +S2 1 5 4 1 Sbias +D5 2 1 DIN +A2 1 0 0 0 0 0 0 0 OTA g=0 in=600f +.model SWP SW(Roff=1G Ron=3k vt=.5 vh=-.1 ilimit=206.88u noiseless) +.model Sbias SW(Ron=50Meg Roff=1G vt=850m vh=-100m noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model NI VDMOS(Vto=300m kp=50m mtriode=1 lambda=.01 noiseless) +.model PI VDMOS(Vto=-300m kp=50m mtriode=.55 lambda=.01 pchan is=0 noiseless) +.model DIN D(Ron=110 Roff=100g Vfwd=1.4 Vrev=1.4 epsilon=800m revepsilon=800m noiseless) +.model DLIMP D(Ron=10k Roff=100Meg Vfwd=1.7 Vrev=340m epsilon=200m revepsilon=100m noiseless) +.model DLIMN D(Ron=10k Roff=100Meg Vfwd=1.5 Vrev=340m epsilon=200m revepsilon=100m noiseless) +.model DANTISAT D(Ron=1k Roff=9Meg vfwd=2 epsilon=100m vrev=2.5 revepsilon=100m noiseless) +.model DSAT D(Ron=10 Roff=10Meg vfwd=35m epsilon=100m noiseless) +.ends LTC6261 +* +.subckt LT1997-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C10 Odb 0 50f Rpar=100K noiseless +M1 N014 NG 8 8 NI m=1.3 temp=27 +C2 11 9 1p Rpar=1G noiseless +D5 NG 8 DLIMN1 +M2 9 PG 11 11 PI m=1.3 temp=27 +A3 N011 N012 8 8 8 8 PG 8 OTA g=2u ref=-.305 linear Vlow=-1e308 Vhigh=1e308 +C11 9 8 1p Rpar=1G noiseless +C16 N012 9 .72p +A5 N009 0 N011 N011 N011 N011 N012 N011 OTA g=25u asym isource=1.4u isink=-2.15u Vlow=-1e308 Vhigh=1e308 +G1 8 NG N012 N011 140n +D9 N012 N011 DLIM +C7 11 INP 2.5p Rser=1k Rpar=100G noiseless +C13 11 8 10p +C1 N007 0 25f +G2 0 N011 8 0 .5m +G4 0 N011 11 0 .5m +C18 N011 0 200p Rpar=1K noiseless +C4 11 INM 2.5p Rser=1k Rpar=100G noiseless +C6 INP 8 2.5p Rser=1k Rpar=100G noiseless +C8 INM 8 2.5p Rser=1k Rpar=100G noiseless +D4 11 PG DLIMP +D2 N007 0 DLIM0 +D1 8 9 DESD +D8 8 INP DESD +D10 8 INM DESD +A2 N003 0 0 0 0 0 0 0 OTA g=0 in=11.4p ink=15 +D11 9 N014 DNR +C15 N014 8 100f Rpar=10Meg noiseless +D7 PG 11 DLIMPR +D12 11 8 DP +S4 N010 8 N004 0 SBiasN +D13 11 N010 DBiasDrop +C14 N010 8 100f +S2 11 PG 0 N004 SHUT +S3 NG 8 0 N004 SHUT +D16 INM INP D1Meg +C17 N008 0 54.26f noiseless Rser=2.667Meg Rpar=1Meg +G3 0 N008 N007 0 1µ +D17 0 N007 DNLIN +C19 N009 0 25f noiseless Rpar=1Meg +G5 0 N009 N008 0 1µ +S5 N011 N012 8 9 SGK +C3 11 PG 600f Rser=200k noiseless +D14 INM N010 DBiasOTT +D15 INP N010 DBiasOTT +S1 0 N006 11 INM SNOI +A7 N006 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=5 +A1 INM INP 0 0 0 0 0 0 OTA g=0 in=100f ink=255 +GNOI INP INM N003 0 1µ +S6 0 N003 11 INM SNOI +A4 0 Odb 0 0 0 0 N007 0 OTA g=1u linear en=18n enk=3 Vhigh=1e308 Vlow=-1e308 +GNOI_V Odb 0 N006 0 10n +R2 INM 12 3K +R3 INM 14 7.5K +C9 9 INM 1.14p Rpar=150K +R1 INM 16 15K +C20 8 12 1p +C21 14 8 3p +C22 16 8 3p +R4 INP 5 3K +R5 INP 3 7.5K +R6 INP 1 15K +C23 8 1 3p +C24 3 8 3p +C25 5 8 1p +C26 7 INP .57p Rpar=300K +C27 6 INP .57p Rpar=300K +C28 8 INM 10p +C29 INP 8 10p +C30 INM INP 10p +D3 11 10 DS +A8 11 10 0 0 0 N018 0 0 SCHMITT trise=24u +A9 0 N015 0 N018 0 0 N004 0 AND trise=1u +A6 11 8 0 0 0 0 N015 0 SCHMITT Vt=2.5 Vh=0 trise=1u +S7 11 8 N004 0 SP +D6 NG 8 DLIMN2 +C5 NG 8 50f Rser=3Meg noiseless +B1 Odb 0 I=10u*dnlim(uplim(V(INM), V(8)+76.21,.1), V(8)-.16, .1)+1n*V(INM) +B2 0 Odb I=10u*dnlim(uplim(V(INP), V(8)+76.2,.1), V(8)-.15, .1)+1n*V(INP) - 10.72n +.model DP D(Ron=1k Roff=1G Vfwd=2.5 epsilon=100m ilimit=10.1u noiseless) +.model SP SW(Ron=1k Roff=1G vt=.5 vh=-200m ilimit=36.7u) +.model DESD D(Ron=1k Roff=1G vfwd=700m epsilon=100m noiseless) +.model SNOI SW(Ron=1 Roff=1Meg vt=1.2 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m Mtriode=.9 lambda=.01) +.model PI VDMOS(Vto=-300m Kp=120m lambda=.01 Rd=74 pchan is=0) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=1 epsilon=100m Vrev=1 epsilon=100m noiseless) +.model DNLIN D(Roff=1.8Meg Ron=800k vfwd=0 epsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=8Meg Vfwd=500m Vrev=100m epsilon=10m revepsilon=10m noiseless) +.model SHUT SW(level=2 Ron=10k Roff=100G vt=-.5 vh=-.2 noiseless) +.model DNR D(Ron=10 Roff=1G epsilon=300m noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.0904 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=44n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=800m epsilon=10m noiseless) +.model DLIMPR D(Ron=5Meg Roff=1G Vfwd=100m epsilon=10m noiseless) +.model SGK SW(level=2 Ron=65k Roff=100G vt=-260m vh=150m oneway epsilon=10m noiseless) +.model SBiasN SW(level=2 Ron=10k Roff=1g vt=.5 vh=-.2 ilimit=28u noiseless) +.model DBiasDrop D(Ron=1k Roff=1G vfwd=1.6 epsilon=500m noiseless) +.model DBiasOTT D(Ron=500 Roff=1G vfwd=700m epsilon=200m noiseless) +.model D1Meg D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=10n revilimit=10n noiseless) +.model DS D(Ron=1k Roff=1G vfwd=0 epsilon=100m ilimit=10u noiseless) +.ends LT1997-1 +* +.subckt LT1997-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C10 N003 0 50f Rpar=100K noiseless +M1 N015 NG 8 8 NI temp=27 +C2 11 9 1p Rpar=1g noiseless +D5 NG 8 DLIMN1 +M2 9 PG 11 11 PI temp=27 +A3 N010 N012 8 8 8 8 PG 8 OTA g=2u ref=-.305 linear vlow=-1e308 vhigh=1e308 +C11 9 8 1p Rpar=1g noiseless +C16 N012 9 1.8p +A5 N008 0 N010 N010 N010 N010 N012 N010 OTA g=25u asym isource=1.4u isink=-2.15u Vlow=-1e308 Vhigh=1e308 +G1 8 NG N012 N010 140n +D9 N012 N010 DLIM +C7 11 INP 2.5p Rser=1k Rpar=100G noiseless +C13 11 8 10p +C1 N006 0 25f +G2 0 N010 8 0 .5m +G4 0 N010 11 0 .5m +C18 N010 0 200p Rpar=1K noiseless +C4 11 INM 2.5p Rser=1k Rpar=100G noiseless +C6 INP 8 2.5p Rser=1k Rpar=100G noiseless +C8 INM 8 2.5p Rser=1k Rpar=100G noiseless +D4 11 PG DLIMP +D2 N006 0 DLIM0 +D1 8 9 DESD +D8 8 INP DESD +D10 8 INM DESD +A2 N011 0 0 0 0 0 0 0 OTA g=0 in=11.4p ink=15 +D11 9 N015 DNR +C15 N015 8 100f Rpar=10Meg noiseless +D7 PG 11 DLIMPR +D12 11 8 DP +S4 N009 8 N002 0 SBiasN +D13 11 N009 DBiasDrop +C14 N009 8 100f +S2 11 PG 0 N002 SHUT +S3 NG 8 0 N002 SHUT +D16 INM INP D1Meg +C17 N007 0 54.26f noiseless Rser=2.667Meg Rpar=1Meg +G3 0 N007 N006 0 1µ +D17 0 N006 DNLIN +C19 N008 0 25f noiseless Rpar=1Meg +G5 0 N008 N007 0 1µ +S5 N010 N012 8 9 SGK +C3 11 PG 600f Rser=200k noiseless +D14 INM N009 DBiasOTT +D15 INP N009 DBiasOTT +S1 0 N005 11 INM SNOI +A7 N005 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=5 +A1 INM INP 0 0 0 0 0 0 OTA g=0 in=100f*(255/dnlim(freq,5,2))**.5 +GNOI_I INP INM N011 0 1µ +S6 0 N011 11 INM SNOI +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear en=18.2n enk=3 Vhigh=1e308 Vlow=-1e308 +GNOI_V N003 0 N005 0 10n +R2 INM 12 100K +R3 INM 14 125K +C9 9 INM 8p Rpar=25k +R1 INM 16 250K +C20 8 12 1p +C21 14 8 3p +C22 16 8 3p +R4 INP 5 100K +R5 INP 3 125K +R6 INP 1 250K +C23 8 1 3p +C24 3 8 3p +C25 5 8 1p +C26 7 INP 4p Rpar=50k +C27 6 INP 4p Rpar=50k +C28 8 INM 10p +C29 INP 8 10p +C30 INM INP 5p +D3 11 10 DS +A8 11 10 0 0 0 N016 0 0 SCHMITT trise=24u +A9 N014 0 N016 0 0 0 N002 0 AND trise=1u +A6 11 8 0 0 0 0 N014 0 SCHMITT vt=2.5 vh=0 trise=1u +S7 11 8 N002 0 SP +D6 NG 8 DLIMN2 +C5 NG 8 50f Rser=3Meg noiseless +B1 N003 0 I=10u*dnlim(uplim(V(INM), V(8)+76.21,.1), V(8)-.16, .1)+1n*V(INM) +B2 0 N003 I=10u*dnlim(uplim(V(INP), V(8)+76.2,.1), V(8)-.15, .1)+1n*V(INP) - 10.72n +.model DP D(Ron=1k Roff=1G Vfwd=2.5 epsilon=100m ilimit=10.1u noiseless) +.model SP SW(Ron=1k Roff=1G vt=.5 vh=-200m ilimit=36.7u) +.model DESD D(Ron=1k Roff=1G vfwd=700m epsilon=100m noiseless) +.model SNOI SW(Ron=1 Roff=1Meg vt=1.2 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m Mtriode=.9 lambda=.01) +.model PI VDMOS(Vto=-300m Kp=120m lambda=.01 Rd=74 pchan is=0) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=1 epsilon=100m Vrev=1 epsilon=100m noiseless) +.model DNLIN D(Roff=1.8Meg Ron=800k vfwd=0 epsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=8Meg Vfwd=500m Vrev=100m epsilon=10m revepsilon=10m noiseless) +.model SHUT SW(level=2 Ron=10k Roff=100G vt=-.5 vh=-.2 noiseless) +.model DNR D(Ron=10 Roff=1G Vfwd=1m epsilon=300m noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.16 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=44n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=850m epsilon=10m noiseless) +.model DLIMPR D(Ron=5Meg Roff=1G Vfwd=100m epsilon=10m noiseless) +.model SGK SW(level=2 Ron=65k Roff=100G vt=-260m vh=150m oneway epsilon=10m noiseless) +.model SBiasN SW(level=2 Ron=10k Roff=1g vt=.5 vh=-.2 ilimit=28u noiseless) +.model DBiasDrop D(Ron=1k Roff=1G vfwd=1.6 epsilon=500m noiseless) +.model DBiasOTT D(Ron=500 Roff=1G vfwd=700m epsilon=200m noiseless) +.model D1Meg D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=10n revilimit=10n noiseless) +.model DS D(Ron=1k Roff=1G vfwd=0 epsilon=100m ilimit=10u noiseless) +.ends LT1997-2 +* +.subckt LT1997-3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C10 N003 0 50f Rpar=100K noiseless +M1 N015 NG 8 8 NI temp=27 +C2 11 9 1p Rpar=1g noiseless +D5 NG 8 DLIMN1 +M2 9 PG 11 11 PI temp=27 +A3 N010 N012 8 8 8 8 PG 8 OTA g=2u ref=-.305 linear vlow=-1e308 vhigh=1e308 +C11 9 8 1p Rpar=1g noiseless +C16 N012 9 1.8p +A5 N008 0 N010 N010 N010 N010 N012 N010 OTA g=25u asym isource=1.4u isink=-2.15u Vlow=-1e308 Vhigh=1e308 +G1 8 NG N012 N010 140n +D9 N012 N010 DLIM +C7 11 INP 2.5p Rser=1k Rpar=100G noiseless +C13 11 8 10p +C1 N006 0 25f +G2 0 N010 8 0 .5m +G4 0 N010 11 0 .5m +C18 N010 0 200p Rpar=1K noiseless +C4 11 INM 2.5p Rser=1k Rpar=100G noiseless +C6 INP 8 2.5p Rser=1k Rpar=100G noiseless +C8 INM 8 2.5p Rser=1k Rpar=100G noiseless +D4 11 PG DLIMP +D2 N006 0 DLIM0 +D1 8 9 DESD +D8 8 INP DESD +D10 8 INM DESD +A2 N011 0 0 0 0 0 0 0 OTA g=0 in=11.4p ink=15 +D11 9 N015 DNR +C15 N015 8 100f Rpar=10Meg noiseless +D7 PG 11 DLIMPR +D12 11 8 DP +S4 N009 8 N002 0 SBiasN +D13 11 N009 DBiasDrop +C14 N009 8 100f +S2 11 PG 0 N002 SHUT +S3 NG 8 0 N002 SHUT +D16 INM INP D1Meg +C17 N007 0 54.26f noiseless Rser=2.667Meg Rpar=1Meg +G3 0 N007 N006 0 1µ +D17 0 N006 DNLIN +C19 N008 0 25f noiseless Rpar=1Meg +G5 0 N008 N007 0 1µ +S5 N010 N012 8 9 SGK +C3 11 PG 600f Rser=200k noiseless +D14 INM N009 DBiasOTT +D15 INP N009 DBiasOTT +S1 0 N005 11 INM SNOI +A7 N005 0 0 0 0 0 0 0 OTA g=0 in=17.25p ink=5 +A1 INM INP 0 0 0 0 0 0 OTA g=0 in=100f ink=255 +GNOI_I INP INM N011 0 1µ +S6 0 N011 11 INM SNOI +A4 0 N003 0 0 0 0 N006 0 OTA g=1u linear en=18n enk=3 Vhigh=1e308 Vlow=-1e308 +GNOI_V N003 0 N005 0 10n +R2 INM 12 2.5K +R3 INM 14 7.5K +C9 9 INM 8p Rpar=22.5k +R1 INM 16 22.5K +C20 8 12 1p +C21 14 8 3p +C22 16 8 3p +R4 INP 5 2.5K +R5 INP 3 7.5K +R6 INP 1 22.5K +C23 8 1 3p +C24 3 8 3p +C25 5 8 1p +C26 7 INP 4p Rpar=45k +C27 6 INP 4p Rpar=45k +C28 8 INM 10p +C29 INP 8 10p +C30 INM INP 5p +D3 11 10 DS +A8 11 10 0 0 0 N016 0 0 SCHMITT trise=24u +A9 N014 0 N016 0 0 0 N002 0 AND trise=1u +A6 11 8 0 0 0 0 N014 0 SCHMITT vt=2.5 vh=0 trise=1u +S7 11 8 N002 0 SP +D6 NG 8 DLIMN2 +C5 NG 8 50f Rser=3Meg noiseless +B1 N003 0 I=10u*dnlim(uplim(V(INM), V(8)+76.21,.1), V(8)-.16, .1)+1n*V(INM) +B2 0 N003 I=10u*dnlim(uplim(V(INP), V(8)+76.2,.1), V(8)-.15, .1)+1n*V(INP) - 10.72n +.model DP D(Ron=1k Roff=1G Vfwd=2.5 epsilon=100m ilimit=10.1u noiseless) +.model SP SW(Ron=1k Roff=1G vt=.5 vh=-200m ilimit=36.7u) +.model DESD D(Ron=1k Roff=1G vfwd=700m epsilon=100m noiseless) +.model SNOI SW(Ron=1 Roff=1Meg vt=1.2 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m Mtriode=.9 lambda=.01) +.model PI VDMOS(Vto=-300m Kp=120m lambda=.01 Rd=74 pchan is=0) +.model DLIM0 D(Ron=10 Roff=10Meg Vfwd=1 epsilon=100m Vrev=1 epsilon=100m noiseless) +.model DNLIN D(Roff=1.8Meg Ron=800k vfwd=0 epsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=8Meg Vfwd=500m Vrev=100m epsilon=10m revepsilon=10m noiseless) +.model SHUT SW(level=2 Ron=10k Roff=100G vt=-.5 vh=-.2 noiseless) +.model DNR D(Ron=10 Roff=1G Vfwd=1m epsilon=300m noiseless) +.model DLIMN1 D(Ron=200k Roff=415Meg Vfwd=1.16 Vrev=-330m epsilon=.1 noiseless) +.model DLIMN2 D(Ron=5Meg Roff=1G Vfwd=-20m epsilon=50m ilimit=44n noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=850m epsilon=10m noiseless) +.model DLIMPR D(Ron=5Meg Roff=1G Vfwd=100m epsilon=10m noiseless) +.model SGK SW(level=2 Ron=65k Roff=100G vt=-260m vh=150m oneway epsilon=10m noiseless) +.model SBiasN SW(level=2 Ron=10k Roff=1g vt=.5 vh=-.2 ilimit=28u noiseless) +.model DBiasDrop D(Ron=1k Roff=1G vfwd=1.6 epsilon=500m noiseless) +.model DBiasOTT D(Ron=500 Roff=1G vfwd=700m epsilon=200m noiseless) +.model D1Meg D(Ron=1Meg Roff=1Meg vfwd=0 vrev=0 ilimit=10n revilimit=10n noiseless) +.model DS D(Ron=1k Roff=1G vfwd=0 epsilon=100m ilimit=10u noiseless) +.ends LT1997-3 + diff --git a/spice/copy/sub/LTC6226.sub b/spice/copy/sub/LTC6226.sub new file mode 100755 index 0000000..a12eb79 Binary files /dev/null and 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All rights reserved. + +.subckt LT6106 1 2 3 4 5 +C1 5 3 .2p +C2 3 2 .2p +C3 5 4 .2p +C4 4 2 .2p +C5 N002 0 20f Rpar=100K noiseless +C12 1 2 100f Rpar=1G +B1 N002 0 I=10u*dnlim(uplim(V(3),V(5)+.11,.1), V(5)-.71, .1) + 10n*V(3) +B2 0 N002 I=10u*dnlim(uplim(V(4),V(5)+.1,.1), V(5)-.7, .1)+ 10n*V(4) +M1 1 N004 3 3 POUT Temp=27 +D1 5 N004 DLIMP +C6 5 N004 100f Rser=1Meg +A1 0 N005 0 0 0 0 N004 0 OTA g=200n ref=-17m linear vlow=-1e308 vhigh=1e308 +A2 0 N006 0 0 0 0 N005 0 OTA g=200u linear Vhigh=1e308 Vlow=-1e308 +C7 N005 1 3p +D2 N005 0 DLIM +A3 0 N002 0 0 0 0 N006 0 OTA g=1u linear rout=1Meg Cout=200f Vhigh=15m Vlow=-30m +D3 4 2 DBIAS +D4 3 2 DBIAS +D5 5 2 DP +D6 3 4 DIN +.model DLIM D(Ron=100 Roff=700k Vfwd=400m Vrev=600m epsilon=10m revepsilon=10m) +.model DLIMP D(Ron=1k Roff=100Meg Vfwd=4 Vrev=-310m epsilon=10m revepsilon=10m) +.model POUT VDMOS(Vto=-300m Kp=30m mtriode=10 rs=1k pchan) +.model DBIAS D(Ron=1Meg Roff=1G Vfwd=.5 epsilon=100m ilimit=15n) +.model DP D(Ron=1k Roff=1G Vfwd=.5 epsilon=100m ilimit=60u) +.model DIN D(Ron=28k Roff=100G Vfwd=1 epsilon=100m Vrev=1 epsilon=100m) +.ends LT6106 +* +.subckt LTC6403-1 1 2 3 4 5 6 7 8 9 10 +M1 4 N015 6 6 NI temp=27 +D5 N015 6 DLIMN +M2 4 N008 3 3 PI temp=27 +D8 3 N008 DLIMP +C3 3 N008 .05f Rser=7Meg noiseless +A3 N009 N011 6 6 6 6 N008 6 OTA g=200n ref=-53m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N009 N009 N009 N009 N011 N009 OTA g=22u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N015 N011 N009 200n +D9 N011 N009 DLIM +C7 3 8 500f Rser=800 Rpar=3.4Meg noiseless +C13 3 6 1000p +S1 N011 N009 0 N007 SHUT2 +C17 6 7 500f +S4 N008 3 0 N007 SHUT1 +S2 6 N015 0 N007 SHUT1 +A2 7 3 0 0 0 0 N007 0 SCHMITT trise=3u tfall=.2u vt=-1.6 vh=10m +D6 1 3 DESD +D7 6 1 DESD +D10 8 1 DIN +D11 6 8 DESD +A1 0 8 0 0 0 0 0 0 OTA g=0 in=1.78p ink=78k +M3 5 N026 6 6 NI temp=27 +D3 N026 6 DLIMN +M4 5 N023 3 3 PI temp=27 +D12 3 N023 DLIMP +A6 N009 N024 6 6 6 6 N023 6 OTA g=200n ref=-53m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N009 N009 N009 N009 N024 N009 OTA g=22u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N026 N024 N009 200n +D13 N024 N009 DLIM +S3 N024 N009 0 N007 SHUT2 +S5 N023 3 0 N007 SHUT1 +S6 6 N026 0 N007 SHUT1 +R3 4 N018 1Meg noiseless +R4 5 N018 1Meg noiseless +A8 N018 2 0 0 0 0 N013 0 OTA g=10m iout=5m en=5n enk=50k Rout=1k Cout=2p ref=-586u Vlow=-1e308 Vhigh=1e308 +G6 N009 N024 0 N013 20µ +G7 N009 N011 0 N013 20µ +D14 N013 0 DCML +C2 3 4 .1p Rpar=100Meg noiseless +C8 4 6 .1p Rpar=100Meg noiseless +C9 3 5 .1p Rpar=100Meg noiseless +C11 5 6 .1p Rpar=100Meg noiseless +C14 N011 4 153f +C16 5 N024 153f +R10 3 7 66k noiseless +D2 3 6 DPOWS +S7 6 3 N007 0 SPOWR +A10 0 1 0 0 0 0 0 0 OTA g=0 in=1.78p ink=78k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N006 0 2f Rpar=60k noiseless +B1 0 N005 I=10u*dnlim(uplim(V(8),V(3)-1.3,.1), V(6)-.3, .1)+1n*V(8) +B2 N005 0 I=10u*dnlim(uplim(V(1),V(3)-1.29,.1), V(6)-.31, .1)+1n*V(1) +C20 N005 0 2f Rpar=100K noiseless +G8 0 N009 6 0 .5m +G9 0 N009 3 0 .5m +C21 N009 0 200p Rpar=1K noiseless +R5 4 9 100 +C24 9 10 12p +R6 10 5 100 +C18 9 6 12p +C29 10 6 12p +D16 8 3 DESD +C12 N015 6 .05f Rser=7Meg noiseless +C15 3 N023 .05f Rser=7Meg noiseless +C19 N026 6 .05f Rser=7Meg noiseless +R9 2 6 46k +R11 3 2 46k +S8 3 1 N007 0 SBIAS +S9 3 8 N007 0 SBIAS +A4 0 N005 0 0 0 0 N006 0 OTA g=100u linear en=2.79n enk=31.9k Vhigh=1e308 Vlow=-1e308 +C4 3 1 500f Rser=800 Rpar=3.4Meg noiseless +C5 8 6 500f Rser=800 Rpar=3.4Meg noiseless +C6 1 6 500f Rser=800 Rpar=3.4Meg noiseless +D15 N006 0 DSI Temp=27 +D19 0 N006 DSI Temp=27 +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=91u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=6.6m noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=7.5u noiseless) +.model DIN D(Ron=100 Roff=14k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.1 pchan) +.model DLS D(Ron=10k Roff=1G Vfwd=.4 Vrev=.4 epsilon=50m revepsilon=50m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=3.3 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=2.15 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=52k Vfwd=2 Vrev=2 epsilon=100m revepsilon=100m noiseless) +.model DSI D(IS=1e-17 TT=1.2e-9 noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.ends LTC6403-1 +* +.subckt LTC6404-1 1 2 3 4 5 6 7 8 9 10 +M1 4 N015 6 6 NI temp=27 +D5 N015 6 DLIMN +M2 4 N008 3 3 PI temp=27 +D8 3 N008 DLIMP +C3 3 N008 .03f Rser=7Meg noiseless +A3 N009 N011 6 6 6 6 N008 6 OTA g=200n ref=-53m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N009 N009 N009 N009 N011 N009 OTA g=300u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N015 N011 N009 200n +D9 N011 N009 DLIM +C7 3 8 1p Rser=800 Rpar=2Meg noiseless +C13 3 6 1000p +S1 N011 N009 0 N007 SHUT2 +C17 6 7 500f +S4 N008 3 0 N007 SHUT1 +S2 6 N015 0 N007 SHUT1 +A2 7 3 0 0 0 0 N007 0 SCHMITT trise=.5u tfall=.5u vt=-2.05 vh=10m +D6 1 3 DESD +D7 6 1 DESD +D10 8 1 DIN +D11 6 8 DESD +A1 0 8 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +M3 5 N026 6 6 NI temp=27 +D3 N026 6 DLIMN +M4 5 N023 3 3 PI temp=27 +D12 3 N023 DLIMP +A6 N009 N024 6 6 6 6 N023 6 OTA g=200n ref=-53m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N009 N009 N009 N009 N024 N009 OTA g=300u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N026 N024 N009 200n +D13 N024 N009 DLIM +S3 N024 N009 0 N007 SHUT2 +S5 N023 3 0 N007 SHUT1 +S6 6 N026 0 N007 SHUT1 +R3 4 N018 1Meg noiseless +R4 5 N018 1Meg noiseless +A8 N018 2 0 0 0 0 N013 0 OTA g=10m linear en=9n enk=20k Rout=1k Cout=2p ref=-586u Vlow=-1e308 Vhigh=1e308 +G6 N009 N024 0 N013 100µ +G7 N009 N011 0 N013 100µ +D14 N013 0 DCML +C2 3 4 .5p Rpar=1Meg noiseless +C8 4 6 .5p Rpar=1Meg noiseless +C9 3 5 .5p Rpar=1Meg noiseless +C11 5 6 .5p Rpar=1Meg noiseless +C14 N011 4 1.1p noiseless +C16 5 N024 1.1p noiseless +R10 3 7 66k noiseless +D2 3 6 DPOWS +S7 6 3 N007 0 SPOWR +A10 0 1 0 0 0 0 0 0 OTA g=0 in=3p ink=30k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N006 0 8f Rpar=1Meg noiseless +B1 0 N005 I=10u*dnlim(uplim(V(8),V(3)-1.3,.1), V(6)-.3, .1)+1n*V(8) +B2 N005 0 I=10u*dnlim(uplim(V(1),V(3)-1.29,.1), V(6)-.31, .1)+1n*V(1) +C20 N005 0 2f Rpar=100K noiseless +G8 0 N009 6 0 .5m +G9 0 N009 3 0 .5m +C21 N009 0 200p Rpar=1K noiseless +D15 0 N006 DLIMI +R5 4 10 50 +C24 10 9 12p +R6 9 5 50 +C18 10 6 12p +C29 9 6 12p +C4 3 1 1p Rser=800 Rpar=2Meg noiseless +C5 8 6 1p Rser=800 Rpar=2Meg noiseless +C6 1 6 1p Rser=800 Rpar=2Meg noiseless +D16 8 3 DESD +C1 N008 4 .01f Rser=20Meg noiseless +C22 4 N015 .01f Rser=20Meg noiseless +C23 N023 5 .01f Rser=20Meg noiseless +C25 5 N026 .01f Rser=20Meg noiseless +C12 N015 6 .03f Rser=7Meg noiseless +C15 3 N023 .03f Rser=7Meg noiseless +C19 N026 6 .03f Rser=7Meg noiseless +R9 2 6 47k +R11 3 2 47k +S8 3 1 N007 0 SBIAS +S9 3 8 N007 0 SBIAS +A4 0 N005 0 0 0 0 N006 0 OTA g=1m linear en=1.5n enk=20k Vhigh=1e308 Vlow=-1e308 +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=169u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=23.4m noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=23u noiseless) +.model DIN D(Ron=100 Roff=3k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=60m lambda=.1 pchan) +.model DLS D(Ron=10k Roff=1G Vfwd=.4 Vrev=.4 epsilon=50m revepsilon=50m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.66 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.66 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=70k Vfwd=400m Vrev=400m epsilon=100m revepsilon=100m noiseless) +.model DLIMI D(Ron=1 Roff=10k Vfwd=.68 Vrev=.68 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.ends LTC6404-1 +* +.subckt LTC6404-2 1 2 3 4 5 6 7 8 9 10 +M1 4 XPN 6 6 NI temp=27 +D5 XPN 6 DLIMN +M2 4 XPP 3 3 PI temp=27 +D8 3 XPP DLIMP +C3 3 XPP .03f Rser=7Meg noiseless +A3 N008 N010 6 6 6 6 XPP 6 OTA g=200n ref=-53m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N008 N008 N008 N008 N010 N008 OTA g=300u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 XPN N010 N008 200n +D9 N010 N008 DLIM +C7 3 8 1p Rser=800 Rpar=2Meg noiseless +C13 3 6 1000p +S1 N010 N008 0 N007 SHUT2 +C17 6 7 500f +S4 XPP 3 0 N007 SHUT1 +S2 6 XPN 0 N007 SHUT1 +A2 7 3 0 0 0 0 N007 0 SCHMITT trise=.5u tfall=.5u vt=-2.05 vh=10m +D6 1 3 DESD +D7 6 1 DESD +D10 8 1 DIN +D11 6 8 DESD +A1 0 8 0 0 0 0 0 0 OTA g=0 in=3p +M3 5 XNN 6 6 NI temp=27 +D3 XNN 6 DLIMN +M4 5 XNP 3 3 PI temp=27 +D12 3 XNP DLIMP +A6 N008 N021 6 6 6 6 XNP 6 OTA g=200n ref=-53m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N008 N008 N008 N008 N021 N008 OTA g=300u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 XNN N021 N008 200n +D13 N021 N008 DLIM +S3 N021 N008 0 N007 SHUT2 +S5 XNP 3 0 N007 SHUT1 +S6 6 XNN 0 N007 SHUT1 +R3 4 N016 1Meg noiseless +R4 5 N016 1Meg noiseless +A8 N016 2 0 0 0 0 N012 0 OTA g=10m linear en=10n enk=20k Rout=1k Cout=2p ref=-586u Vlow=-1e308 Vhigh=1e308 +G6 N008 N021 0 N012 100µ +G7 N008 N010 0 N012 100µ +D14 N012 0 DCML +C2 3 4 .5p Rpar=1Meg noiseless +C8 4 6 .5p Rpar=1Meg noiseless +C9 3 5 .5p Rpar=1Meg noiseless +C11 5 6 .5p Rpar=1Meg noiseless +C14 N010 4 .55p noiseless +C16 5 N021 .55p noiseless +R10 3 7 66k noiseless +D2 3 6 DPOWS +S7 6 3 N007 0 SPOWR +A10 0 1 0 0 0 0 0 0 OTA g=0 in=3p +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N006 0 8f Rpar=1Meg noiseless +B1 0 N005 I=10u*dnlim(uplim(V(8),V(3)-1.3,.1), V(6)-.3, .1)+1n*V(8) +B2 N005 0 I=10u*dnlim(uplim(V(1),V(3)-1.29,.1), V(6)-.31, .1)+1n*V(1) +C20 N005 0 2f Rpar=100K noiseless +G8 0 N008 6 0 .5m +G9 0 N008 3 0 .5m +C21 N008 0 200p Rpar=1K noiseless +D15 0 N006 DLIMI +R5 4 10 50 +C24 10 9 12p +R6 9 5 50 +C18 10 6 12p +C29 9 6 12p +C4 3 1 1p Rser=800 Rpar=2Meg noiseless +C5 8 6 1p Rser=800 Rpar=2Meg noiseless +C6 1 6 1p Rser=800 Rpar=2Meg noiseless +D16 8 3 DESD +C1 XPP 4 .01f Rser=20Meg noiseless +C22 4 XPN .01f Rser=20Meg noiseless +C23 XNP 5 .01f Rser=20Meg noiseless +C25 5 XNN .01f Rser=20Meg noiseless +C12 XPN 6 .03f Rser=7Meg noiseless +C15 3 XNP .03f Rser=7Meg noiseless +C19 XNN 6 .03f Rser=7Meg noiseless +R9 2 6 28k +R11 3 2 28k +S8 3 1 N007 0 SBIAS +S9 3 8 N007 0 SBIAS +A4 0 N005 0 0 0 0 N006 0 OTA g=1m linear en=1.5n enk=20k Vhigh=1e308 Vlow=-1e308 +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=147.5u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=25.9m noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=23u noiseless) +.model DIN D(Ron=100 Roff=3k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=60m lambda=.1 pchan) +.model DLS D(Ron=10k Roff=1G Vfwd=.4 Vrev=.4 epsilon=50m revepsilon=50m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.66 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.66 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=70k Vfwd=400m Vrev=400m epsilon=100m revepsilon=100m noiseless) +.model DLIMI D(Ron=1 Roff=10k Vfwd=.62 Vrev=.62 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.ends LTC6404-2 +* +.subckt LTC6404-4 1 2 3 4 5 6 7 8 9 10 +M1 4 N015 6 6 NI temp=27 +D5 N015 6 DLIMN +M2 4 N008 3 3 PI temp=27 +D8 3 N008 DLIMP +C3 3 N008 .03f Rser=7Meg noiseless +A3 N009 N011 6 6 6 6 N008 6 OTA g=200n ref=-53m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N009 N009 N009 N009 N011 N009 OTA g=300u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N015 N011 N009 200n +D9 N011 N009 DLIM +C7 3 8 2p Rser=800 Rpar=2Meg noiseless +C13 3 6 1000p +S1 N011 N009 0 N007 SHUT2 +C17 6 7 500f +S4 N008 3 0 N007 SHUT1 +S2 6 N015 0 N007 SHUT1 +A2 7 3 0 0 0 0 N007 0 SCHMITT trise=.5u tfall=.5u vt=-2.05 vh=10m +D6 1 3 DESD +D7 6 1 DESD +D10 8 1 DIN +D11 6 8 DESD +A1 0 8 0 0 0 0 0 0 OTA g=0 in=3p ink=20k +M3 5 N026 6 6 NI temp=27 +D3 N026 6 DLIMN +M4 5 N023 3 3 PI temp=27 +D12 3 N023 DLIMP +A6 N009 N024 6 6 6 6 N023 6 OTA g=200n ref=-53m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N009 N009 N009 N009 N024 N009 OTA g=300u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N026 N024 N009 200n +D13 N024 N009 DLIM +S3 N024 N009 0 N007 SHUT2 +S5 N023 3 0 N007 SHUT1 +S6 6 N026 0 N007 SHUT1 +R3 4 N018 1Meg noiseless +R4 5 N018 1Meg noiseless +A8 N018 2 0 0 0 0 N013 0 OTA g=10m linear en=20n enk=20k Rout=1k Cout=2p ref=-586u Vlow=-1e308 Vhigh=1e308 +G6 N009 N024 0 N013 100µ +G7 N009 N011 0 N013 100µ +D14 N013 0 DCML +C2 3 4 .5p Rpar=1Meg noiseless +C8 4 6 .5p Rpar=1Meg noiseless +C9 3 5 .5p Rpar=1Meg noiseless +C11 5 6 .5p Rpar=1Meg noiseless +C14 N011 4 .4p noiseless +C16 5 N024 .4p noiseless +R10 3 7 66k noiseless +D2 3 6 DPOWS +S7 6 3 N007 0 SPOWR +A10 0 1 0 0 0 0 0 0 OTA g=0 in=3p ink=20k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N006 0 8f Rpar=1Meg noiseless +B1 0 N005 I=10u*dnlim(uplim(V(8),V(3)-1.3,.1), V(6)-.3, .1)+1n*V(8) +B2 N005 0 I=10u*dnlim(uplim(V(1),V(3)-1.29,.1), V(6)-.31, .1)+1n*V(1) +C20 N005 0 2f Rpar=100K noiseless +G8 0 N009 6 0 .5m +G9 0 N009 3 0 .5m +C21 N009 0 200p Rpar=1K noiseless +D15 0 N006 DLIMI +R5 4 10 50 +C24 10 9 12p +R6 9 5 50 +C18 10 6 12p +C29 9 6 12p +D16 8 3 DESD +C1 N008 4 .01f Rser=20Meg noiseless +C22 4 N015 .01f Rser=20Meg noiseless +C23 N023 5 .01f Rser=20Meg noiseless +C25 5 N026 .01f Rser=20Meg noiseless +C12 N015 6 .03f Rser=7Meg noiseless +C15 3 N023 .03f Rser=7Meg noiseless +C19 N026 6 .03f Rser=7Meg noiseless +R9 2 6 14k +R11 3 2 14k +S8 3 1 N007 0 SBIAS +S9 3 8 N007 0 SBIAS +C4 3 1 2p Rser=800 Rpar=2Meg noiseless +C5 8 6 2p Rser=800 Rpar=2Meg noiseless +C6 1 6 2p Rser=800 Rpar=2Meg noiseless +A4 0 N005 0 0 0 0 N006 0 OTA g=1m linear en=1.5n enk=20k Vhigh=1e308 Vlow=-1e308 +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=147.5u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=26.26m noiseless) +.model SBIAS SW(level=2 Ron=1k Roff=1G vt=.5 vh=-.1 ilimit=23u noiseless) +.model DIN D(Ron=100 Roff=3k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=60m lambda=.1 pchan) +.model DLS D(Ron=10k Roff=1G Vfwd=.4 Vrev=.4 epsilon=50m revepsilon=50m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.66 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.66 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=70k Vfwd=400m Vrev=400m epsilon=100m revepsilon=100m noiseless) +.model DLIMI D(Ron=1 Roff=10k Vfwd=.68 Vrev=.68 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.ends LTC6404-4 +* +.subckt LTC6405 1 2 3 4 5 6 7 8 9 10 +M1 4 N015 6 6 NI temp=27 +D5 N015 6 DLIMN +M2 4 N008 3 3 PI temp=27 +D8 3 N008 DLIMP +C3 3 N008 .1f Rser=7Meg noiseless +A3 N009 N011 6 6 6 6 N008 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N009 N009 N009 N009 N011 N009 OTA g=22u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N015 N011 N009 200n +D9 N011 N009 DLIM +C7 3 8 1p Rser=80 Rpar=460k noiseless +C13 3 6 1000p +S1 N011 N009 0 N007 SHUT2 +C17 6 7 500f +S4 N008 3 0 N007 SHUT1 +S2 6 N015 0 N007 SHUT1 +A2 7 3 0 0 0 0 N007 0 SCHMITT trise=150n tfall=40n vt=-3 vh=10m +D6 1 3 DESD +D7 6 1 DESD +D10 8 1 DIN +D11 6 8 DESD +A1 0 8 0 0 0 0 0 0 OTA g=0 in=2.3p ink=91k +M3 5 N026 6 6 NI temp=27 +D3 N026 6 DLIMN +M4 5 N023 3 3 PI temp=27 +D12 3 N023 DLIMP +A6 N009 N024 6 6 6 6 N023 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N009 N009 N009 N009 N024 N009 OTA g=22u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N026 N024 N009 200n +D13 N024 N009 DLIM +S3 N024 N009 0 N007 SHUT2 +S5 N023 3 0 N007 SHUT1 +S6 6 N026 0 N007 SHUT1 +R3 4 N018 1Meg noiseless +A8 N018 2 0 0 0 0 N013 0 OTA g=8m iout=300u en=9.5n enk=18k Rout=1k ref=-6.6m Vlow=-1e308 Vhigh=1e308 +G6 N009 N024 0 N013 20µ +G7 N009 N011 0 N013 20µ +D14 N013 0 DCML +C2 3 4 .1p Rpar=1Meg noiseless +C8 4 6 .1p Rpar=1Meg noiseless +C9 3 5 .1p Rpar=1Meg noiseless +C11 5 6 .1p Rpar=1Meg noiseless +C14 N011 4 8f noiseless +C16 5 N024 8f noiseless +R10 3 7 50k noiseless +D2 3 6 DPOWS +S7 6 3 N007 0 SPOWR +A10 0 1 0 0 0 0 0 0 OTA g=0 in=2.3p ink=91k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +B1 0 N005 I=10u*dnlim(uplim(V(8),V(3)+.3,.1), V(6)-.3, .1)+1n*V(8) +B2 N005 0 I=10u*dnlim(uplim(V(1),V(3)+.31,.1), V(6)-.31, .1)+1n*V(1) +C20 N005 0 .3f Rpar=100K noiseless +G8 0 N009 6 0 .5m +G9 0 N009 3 0 .5m +C21 N009 0 200p Rpar=1K noiseless +R5 4 10 50 +C24 10 9 1.25p +R6 9 5 50 +C18 10 6 1.25p +C29 9 6 1.25p +C4 3 1 1p Rser=80 Rpar=460k noiseless +C5 8 6 1p Rser=80 Rpar=460k noiseless +C6 1 6 1p Rser=80 Rpar=460k noiseless +D16 8 3 DESD +C1 N008 4 .01f Rser=20Meg noiseless +C22 4 N015 .01f Rser=20Meg noiseless +C23 N023 5 .01f Rser=20Meg noiseless +C25 5 N026 .01f Rser=20Meg noiseless +C12 N015 6 .1f Rser=7Meg noiseless +C15 3 N023 .1f Rser=7Meg noiseless +C19 N026 6 .1f Rser=7Meg noiseless +R9 2 6 37k +R11 3 2 37k +S8 1 3 N007 0 SBIAS +S9 8 3 N007 0 SBIAS +A4 0 N005 0 0 0 0 N006 0 OTA g=125u linear en=1.58n enk=18.5k Vhigh=1e308 Vlow=-1e308 +D15 N006 0 DSI temp=27 +D19 0 N006 DSI temp=27 +C10 N006 0 6.2f noiseless Rser=25.7k Rpar=60k +S10 3 N008 4 3 SUPLIM +S11 3 N023 5 3 SUPLIM +S12 N015 6 6 4 SDWLIM +S13 N026 6 6 5 SDWLIM +C26 N013 0 1.8p Rser=200 noiseless +R4 5 N018 1Meg noiseless +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=217u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=16.3m noiseless) +.model SBIAS SW(level=2 Ron=10k Roff=1G vt=.5 vh=-.1 ilimit=7u Vser=1.5 noiseless) +.model DIN D(Ron=100 Roff=3.5k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=1k Roff=1G vt=-950m vh=-500m noiseless) +.model SDWLIM SW(Ron=3Meg Roff=1G vt=-400m vh=-50m noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.1 pchan) +.model DLS D(Ron=10k Roff=1G Vfwd=.4 Vrev=.4 epsilon=50m revepsilon=50m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.9 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.9 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=52k Vfwd=2 Vrev=2 epsilon=100m revepsilon=100m noiseless) +.model DSI D(IS=1e-8 TT=5e-10 noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.ends LTC6405 +* +.subckt LTC6406 1 2 3 4 5 6 7 8 9 10 +M1 4 N+ 6 6 NI temp=27 +D5 N+ 6 DLIMN +M2 4 P+ 3 3 PI temp=27 +D8 3 P+ DLIMP +C3 3 P+ .1f Rser=4Meg noiseless +A3 N008 N010 6 6 6 6 P+ 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A5 N006 0 N008 N008 N008 N008 N010 N008 OTA g=22u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G1 6 N+ N010 N008 200n +D9 N010 N008 DLIM +C7 3 8 1p Rser=80 Rpar=200k noiseless +C13 3 6 1000p +S1 N010 N008 0 N007 SHUT2 +C17 6 7 500f +S4 P+ 3 0 N007 SHUT1 +S2 6 N+ 0 N007 SHUT1 +A2 7 3 0 0 0 0 N007 0 SCHMITT trise=150n tfall=40n vt=-1 vh=10m +D6 1 3 DESD +D7 6 1 DESD +D10 8 1 DIN +D11 6 8 DESD +A1 0 8 0 0 0 0 0 0 OTA g=0 in=2.3p ink=91k +M3 5 N- 6 6 NI temp=27 +D3 N- 6 DLIMN +M4 5 P- 3 3 PI temp=27 +D12 3 P- DLIMP +A6 N008 N021 6 6 6 6 P- 6 OTA g=200n ref=-55m linear vlow=-1e308 vhigh=1e308 +A7 0 N006 N008 N008 N008 N008 N021 N008 OTA g=22u linear cout=1f Vhigh=1e308 Vlow=-1e308 +G5 6 N- N021 N008 200n +D13 N021 N008 DLIM +S3 N021 N008 0 N007 SHUT2 +S5 P- 3 0 N007 SHUT1 +S6 6 N- 0 N007 SHUT1 +R3 4 5 2Meg noiseless +G6 N008 N021 0 N012 20µ +G7 N008 N010 0 N012 20µ +D14 N012 0 DCML +C2 3 4 .1p Rpar=1Meg noiseless +C8 4 6 .1p Rpar=1Meg noiseless +C9 3 5 .1p Rpar=1Meg noiseless +C11 5 6 .1p Rpar=1Meg noiseless +C14 N010 4 8f Rser=10k noiseless +C16 5 N021 8f Rser=10k noiseless +R10 3 7 100k noiseless +D2 3 6 DPOWS +S7 6 3 N007 0 SPOWR +A10 0 1 0 0 0 0 0 0 OTA g=0 in=2.4p ink=54k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +B1 0 N005 I=10u*dnlim(uplim(V(8),V(3)+.3,.1), V(6)-.3, .1)+1n*V(8) +B2 N005 0 I=10u*dnlim(uplim(V(1),V(3)+.31,.1), V(6)-.31, .1)+1n*V(1) +C20 N005 0 .6f Rpar=100K noiseless +G8 0 N008 6 0 .5m +G9 0 N008 3 0 .5m +C21 N008 0 200p Rpar=1K noiseless +R5 4 10 50 +C24 10 9 1.25p +R6 9 5 50 +C18 10 6 1.25p +C29 9 6 1.25p +C4 3 1 1p Rser=80 Rpar=200k noiseless +C5 8 6 1p Rser=80 Rpar=300k noiseless +C6 1 6 1p Rser=80 Rpar=300k noiseless +D16 8 3 DESD +C1 P+ 4 .01f Rser=20Meg noiseless +C22 4 N+ .01f Rser=20Meg noiseless +C23 P- 5 .01f Rser=20Meg noiseless +C25 5 N- .01f Rser=20Meg noiseless +C12 N+ 6 .1f Rser=4Meg noiseless +C15 3 P- .1f Rser=4Meg noiseless +C19 N- 6 .1f Rser=4Meg noiseless +R9 2 6 30.714k +R11 3 2 43k +S8 1 3 N007 0 SBIAS +S9 8 3 N007 0 SBIAS +A4 0 N005 0 0 0 0 N006 0 OTA g=125u linear en=1.59n enk=8.1k Vhigh=1e308 Vlow=-1e308 +D15 N006 0 DSI temp=27 +D19 0 N006 DSI temp=27 +S10 3 P+ 4 3 SUPLIM +S11 3 P- 5 3 SUPLIM +S12 N+ 6 6 4 SDWLIM +S13 N- 6 6 5 SDWLIM +A8 0 N020 0 0 0 0 N012 0 OTA g=8m iout=300u en=9.5n enk=18k Rout=1k ref=-6.6m Vlow=-1e308 Vhigh=1e308 +C26 N012 0 1.8p Rser=200 noiseless +C10 N006 0 11.79f Rser=90k Rpar=60k noiseless +B3 0 N020 I=10u*dnlim(uplim(V(2),V(3)-.9,.1), V(6)+.42, .1) +B4 N020 0 I=5u*(V(4)+V(5)) +C27 N020 0 .1f Rpar=100K noiseless +.model DPOWS D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=117u noiseless) +.model SPOWR SW(level=1 Ron=100 Roff=1g vt=.5 vh=-.1 ilimit=16.3m noiseless) +.model SBIAS SW(level=2 Ron=10k Roff=1G vt=.5 vh=-.1 ilimit=3u Vser=-.2 noiseless) +.model DIN D(Ron=100 Roff=3k Vfwd=1.4 epsilon=.1 Vrev=1.4 epsilon=.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model SUPLIM SW(Ron=1k Roff=1G vt=-720m vh=-50m noiseless) +.model SDWLIM SW(Ron=1Meg Roff=1G vt=-241m vh=-50m noiseless) +.model NI VDMOS(Vto=300m kp=30m lambda=.1) +.model PI VDMOS(Vto=-300m Kp=30m lambda=.1 pchan) +.model DLS D(Ron=10k Roff=1G Vfwd=.4 Vrev=.4 epsilon=50m revepsilon=50m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.9 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.9 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=100 Roff=52k Vfwd=2 Vrev=2 epsilon=100m revepsilon=100m noiseless) +.model DSI D(IS=2e-8 TT=5e-10 noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.ends LTC6406 +* +.subckt LT1995 1 2 3 4 5 6 7 8 9 10 +A1 VINM VINP 0 0 0 0 0 0 OTA g=0 in=.9p ink=90 +C2 VINM VINP 1p Rpar=5Meg noiseless +B1 0 N003 I=10u*dnlim(uplim(V(VINP),V(7)-1.4,.1), V(4)+1.6, .1)+1n*V(VINP) +B2 N003 0 I=10u*dnlim(uplim(V(VINM),V(7)-1.39,.1), V(4)+1.59, .1)+1n*V(VINM) +C9 7 VINM 1.5p Rpar=100Meg noiseless +C10 N003 0 7f Rpar=100K noiseless +M1 7 N005 6 6 N temp=27 +M2 4 N005 6 6 P temp=27 +C3 7 6 1p +D5 N005 6 YU +D6 6 N005 YD +R2 7 N006 42Meg noiseless +R3 N006 4 42Meg noiseless +C13 N006 6 2p Rser=5k noiseless +C4 6 4 1p +C1 VINM 4 1.5p Rpar=100Meg noiseless +C6 7 VINP 1.5p Rpar=100Meg noiseless +C7 VINP 4 1.5p Rpar=100Meg noiseless +A6 0 N003 0 0 0 0 N008 0 OTA g=1u linear Cout=1.3f en=9n enk=110 Vhigh=1e308 Vlow=-1e308 +D2 VINM 4 DBIAS +D4 VINP 4 DBIAS +A3 0 N008 0 0 0 0 N006 0 OTA g=534u iout=10m Cout=1.7p Vlow=-1e308 Vhigh=1e308 +D1 N008 0 DSlewLim +G1 0 N005 N006 0 1µ +C8 0 N005 1f Rpar=1Meg noiseless +D3 7 4 DC +RM1 VINM 10 4k +RM2 VINM 9 2k +RM4 VINM 8 1k +C11 VINM 9 .5p +RP1 VINP 1 4k +RP2 VINP 2 2k +RP4 VINP 3 1k +C12 VINP 2 .5p +R11 6 VINM 4k +C14 6 VINM .3p +R12 VINP 5 4k +C15 VINP 5 .3p +C5 N006 6 30p Rser=200k noiseless +G2 N006 0 N006 7 100m dir=1 vto=-.814 +G3 4 N006 4 N006 100m dir=1 vto=-.814 +.model YU D(Ron=100 Roff=1T Vfwd=.805 epsilon=.1 noiseless) +.model YD D(Ron=100 Roff=1T Vfwd=.785 epsilon=.1 noiseless) +.model N VDMOS(Vto=-130m Kp=120m) +.model P VDMOS(Vto=130m Kp=120m pchan) +.model DBIAS D(Ron=1Meg Roff=1G Vfwd=.6 ilimit=80n noiseless) +.model DSlewLim D(Ron=550k Roff=1Meg Vfwd=1 Vrev=1 epsilon=.1 revepsilon=.1 noiseless) +.model DC D(Ron=2k Roff=1G Vfwd=1 epsilon=.1 ilimit=2.99m noiseless) +.ends LT1995 +* +.subckt LTC6087 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-34.37p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +M1 5 N012 4 4 NI temp=27 +C2 3 5 1p Rpar=100Meg noiseless +D5 N012 4 DLIMN +M2 5 N008 3 3 PI temp=27 +D8 3 N008 DLIMP +C3 3 N008 50p Rser=4Meg noiseless +A3 N009 N010 4 4 4 4 N008 4 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=100Meg noiseless +C12 N012 4 50p Rser=4Meg noiseless +A4 0 N004 0 0 0 0 N006 0 OTA g=1m linear en=9.6n enk=768 Vhigh=130m Vlow=-130m +C16 N010 5 650f +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=68u iout=5u Vhigh=1e308 Vlow=-1e308 +G1 4 N012 N010 N009 200n +D9 N010 N009 DLIM +C7 3 1 2.1p Rser=1k Rpar=5T noiseless +C13 3 4 1000p +S1 N010 N009 0 N005 SHUT2 +C1 N006 0 120p Rpar=1k noiseless +C17 4 6 500f Rpar=1T noiseless +G2 0 N009 4 0 .5m +G4 0 N009 3 0 .5m +C18 N009 0 200p Rpar=1K noiseless +S4 N008 3 0 N005 SHUT1 +S2 4 N012 0 N005 SHUT1 +S7 3 4 N005 0 SPOW +G3 0 N007 N006 0 1m +L1 N007 0 59.4µ Cpar=159f Rser=1.12k Rpar=9.33k noiseless +A2 6 4 0 0 0 0 N005 0 SCHMITT trise=5u tfall=1u vt=.8 vh=10m +D2 3 6 DSHUT +D4 1 4 DBIAS +D6 2 3 DESD +D7 4 2 DESD +D10 1 3 DESD +D11 4 1 DESD +D1 2 4 DBIAS +C8 N008 5 1f Rser=1Meg noiseless +C9 5 N012 1f Rser=1Meg noiseless +C4 3 2 2.1p Rser=1k Rpar=5T noiseless +C5 1 4 2.1p Rser=1k Rpar=5T noiseless +C6 2 4 2.1p Rser=1k Rpar=5T noiseless +A6 2 0 0 0 0 0 0 0 OTA IN=.39f*table(freq,0,.5,1,.5, 10,1.5,100,4.9,500,11,1000,15.9,3000,28.9,10000 ,60.8,20000,99.9,30000,137.3,40000,174.2,50000,210.7,100000, 392, 500k,1.6e3,1e6,1.6e3) +A7 2 1 0 0 0 0 0 0 OTA INCM=.919f*table(freq,0,.5,1,.5, 10,1.5,100,4.9,500,11,1000,15.9,3000,28.9,10000 ,60.8,20000,99.9,30000,137.3,40000,174.2,50000,210.7,100000, 392, 500k,1.6e3,1e6,1.6e3) +A1 1 0 0 0 0 0 0 0 OTA IN=.39f*table(freq,0,.5,1,.5, 10,1.5,100,4.9,500,11,1000,15.9,3000,28.9,10000 ,60.8,20000,99.9,30000,137.3,40000,174.2,50000,210.7,100000, 392, 500k,1.6e3,1e6,1.6e3) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=40m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=40m lambda=.01 pchan) +.model DLIM D(Ron=10k Roff=70Meg Vfwd=2 Vrev=2 epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.8 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.8 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DSHUT D(Ron=85k Roff=1Meg Vfwd=.1 epsilon=50m ilimit=.1u noiseless) +.model DBIAS D(Ron=10G Roff=10T epsilon=.3 ilimit=1p noiseless) +.model SPOW SW(level=2 Ron=400 Roff=1G vt=.5 vh=-.1 ilimit=.948m noiseless) +.ends LTC6087 +* +.subckt LTC6088 1 2 3 4 5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-34.37p +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2) +C10 N004 0 1f Rpar=100K noiseless +M1 5 N011 4 4 NI temp=27 +C2 3 5 1p Rpar=100Meg noiseless +D5 N011 4 DLIMN +M2 5 N007 3 3 PI temp=27 +D8 3 N007 DLIMP +C3 3 N007 50p Rser=4Meg noiseless +A3 N008 N009 4 4 4 4 N007 4 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308 +C11 5 4 1p Rpar=100Meg noiseless +C12 N011 4 50p Rser=4Meg noiseless +A4 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=9.6n enk=768 Vhigh=130m Vlow=-130m +C16 N009 5 650f +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=68u iout=5u Vhigh=1e308 Vlow=-1e308 +G1 4 N011 N009 N008 200n +D9 N009 N008 DLIM +C7 3 1 2.1p Rser=1k Rpar=5T noiseless +C13 3 4 1000p +C1 N005 0 120p Rpar=1k noiseless +G2 0 N008 4 0 .5m +G4 0 N008 3 0 .5m +C18 N008 0 200p Rpar=1K noiseless +G3 0 N006 N005 0 1m +L1 N006 0 59.4µ Cpar=159f Rser=1.12k Rpar=9.33k noiseless +D4 1 4 DBIAS +D6 2 3 DESD +D7 4 2 DESD +D10 1 3 DESD +D11 4 1 DESD +A1 2 1 0 0 0 0 0 0 OTA g=0 in=-4.1684p+4.17p*exp(freq*9e-7) +D1 2 4 DBIAS +C8 N007 5 1f Rser=1Meg noiseless +C9 5 N011 1f Rser=1Meg noiseless +C4 3 2 2.1p Rser=1k Rpar=5T noiseless +C5 1 4 2.1p Rser=1k Rpar=5T noiseless +C6 2 4 2.1p Rser=1k Rpar=5T noiseless +D3 3 4 DPOW +.model DSHUT D(Ron=85k Roff=1Meg Vfwd=.1 epsilon=50m ilimit=.1u noiseless) +.model DBIAS D(Ron=10G Roff=10T epsilon=.3 ilimit=1p noiseless) +.model DPOW D(Ron=100 Roff=1G Vfwd=.6 epsilon=.1 ilimit=.948m noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=40m lambda=.01) +.model PI VDMOS(Vto=-300m Kp=40m lambda=.01 pchan) +.model DLIM D(Ron=10k Roff=70Meg Vfwd=2 Vrev=2 epsilon=10m revepsilon=10m noiseless) +.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.8 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.8 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.ends LTC6088 +* +.subckt LTC6246 1 2 3 4 5 6 +B1 0 N004 I=10u*dnlim(uplim(V(3),V(6)+.51,.1), V(2)-.61, .1)+1n*V(3) +B2 N004 0 I=10u*dnlim(uplim(V(4),V(6)+.5,.1), V(2)-.6, .1)+1n*V(4) +C10 N004 0 .1f Rpar=100K noiseless +Q1 N014 N014 N013 0 PNP1 temp=27 +R3 6 N013 2.2K noiseless +R4 N015 N014 160 noiseless +Q2 1 N015 6 0 PNP2 M=3.5 temp=27 +Q3 N016 N016 N018 0 NPN1 temp=27 +Q4 1 N017 2 0 NPN2 M=3.5 temp=27 +C3 1 N014 700f Rser=1.8k noiseless +C15 1 N016 700f Rser=1.8k noiseless +B3 N014 2 I=uplim(dnlim(-430u*V(VFOLDP),0,92u),1m,.1m)*(.5+.5*tanh((V(ON)-.5)/100m)) +B4 6 N016 I=uplim(dnlim(430u*V(VFOLDP),0,92u),1.1m,.1m)*(.5+.5*tanh((V(ON)-.5)/100m)) +C19 N014 VFOLD 800f +A1 4 3 0 0 0 0 0 0 OTA g=0 in=2p ink=628 +C4 6 3 .4p Rpar=25Meg noiseless +C5 6 2 10p Rpar=125k noiseless +C6 2 5 500f Rpar=1g noiseless +D1 4 3 DIN +S1 5 6 2 5 SSHUT +S2 6 2 ON 0 SPOW +C7 4 3 400f +C8 6 4 .4p Rpar=25Meg noiseless +C9 3 2 .4p Rpar=35Meg noiseless +C13 4 2 .4p Rpar=35Meg noiseless +D2 6 N006 DBIAS1 +D3 4 N006 DBIAS2 +D4 3 N006 DBIAS2 +C17 N006 2 100f +S3 2 N006 N010 0 SBIAS +A2 5 2 0 0 0 0 N010 0 SCHMITT Vt=1.05 vh=.1 trise=9.6u tfall=2.4u +C20 N016 VFOLD 800f +G3 0 x2 N005 0 1m +C21 x2 0 400f Rpar=1k noiseless +A5 0 N004 ON 0 0 0 N005 0 OTA g=1m linear en=4.2n enk=569 Rout=1k Cout=2p vlow=-2 vhigh=2 +S4 6 N014 0 ON SOFF +S5 N016 2 0 ON SOFF +A3 N010 0 0 0 0 0 ON 0 BUF trise=1u +R5 N018 2 2.2K noiseless +R6 N017 N016 160 noiseless +C22 VFOLD VMid 5p Rpar=1.407Meg Rser=1.5k noiseless +G7 0 VFOLDP VFOLD VMid 1µ +C23 VFOLDP 0 .5f Rpar=1Meg noiseless +C24 VFOLD 1 1.2p Rser=2.2k noiseless +C12 6 1 4p Rpar=200Meg noiseless +C25 1 2 4p Rpar=200Meg noiseless +G1 0 VMid 6 0 5m +G5 0 VMid 2 0 5m +C1 VMid 0 200p Rpar=100 noiseless +G2 VFOLD VMid VFOLD 6 10m vto=0 dir=1 +G4 VMid VFOLD 2 VFOLD 10m vto=0 dir=1 +G6 VMid VFOLD 0 X2 1.9m +D7 x2 0 DSL1 +D8 x2 0 DSL2 +G10 0 x2 N007 0 100m vto=520m dir=1 +G11 x2 0 0 N009 100m vto=520m dir=1 +C14 0 N009 500f Rpar=500k noiseless +A6 N007 N005 ON 0 0 0 N007 0 OTA g=1m asym isource=20u isink=-1m vlow=0 vhigh=2 +C16 0 N007 500f Rpar=500k noiseless +A8 N009 N005 ON 0 0 0 N009 0 OTA g=1m asym isource=1m isink=-20u vlow=-2 vhigh=0 +.model SSHUT SW(Ron=2.5e6 Roff=50Meg vt=-1.7 vh=-200m noiseless) +.model DIN D(Ron=100 Roff=32k Vfwd=1.6 epsilon=.1 Vrev=1.6 revepsilon=.1 noiseless) +.model DBIAS1 D(Ron=100 Roff=1g vfwd=4 epsilon=100m noiseless) +.model DBIAS2 D(Ron=100k Roff=200Meg vfwd=3 epsilon=100m ilimit=250n noiseless) +.model SBIAS SW(level=2 Ron=10k Roff=10G vt=.5 vh=-.1 noiseless ) +.model SPOW SW(Ron=1k Roff=1G vt=.5 vh=.1 ilimit=3.6u noiseless) +.model PNP1 PNP(BF=100 VAF=100 CJE=100f noiseless) +.model NPN1 NPN(BF=100 VAF=100 CJE=100f noiseless) +.model PNP2 PNP(BF=100 BR=.07 VAF=100 CJE=200f CJC=80f RC=15 TF=100p noiseless) +.model NPN2 NPN(BF=100 BR=.65 VAF=100 CJE=200f CJC=80f RC=5 TF=100p noiseless) +.model SOFF SW(Ron=100 Roff=1G vt=-.5 vh=-.3 noiseless) +.model DSL1 D(Ron=10 Roff=200k vfwd=70m epsilon=10m vrev=70m revepsilon=10m noiseless ) +.model DSL2 D(Ron=.1 Roff=200k vfwd=800m epsilon=50m vrev=800m revepsilon=50m noiseless ) +.ends LTC6246 +* +.subckt LTC6247 1 2 3 4 5 +B1 0 N004 I=10u*dnlim(uplim(V(3),V(5)+.51,.1), V(2)-.61, .1)+1n*V(3) +B2 N004 0 I=10u*dnlim(uplim(V(4),V(5)+.5,.1), V(2)-.6, .1)+1n*V(4) +C10 N004 0 .1f Rpar=100K noiseless +Q1 N012 N012 N011 0 PNP1 temp=27 +R3 5 N011 2.2K noiseless +R4 N013 N012 160 noiseless +Q2 1 N013 5 0 PNP2 M=3.5 temp=27 +Q3 N014 N014 N016 0 NPN1 temp=27 +Q4 1 N015 2 0 NPN2 M=3.5 temp=27 +C3 1 N012 700f Rser=1.8k noiseless +C15 1 N014 700f Rser=1.8k noiseless +B3 N012 2 I=uplim(dnlim(-430u*V(VFOLDP),0,92u),1m,.1m) +B4 5 N014 I=uplim(dnlim(430u*V(VFOLDP),0,92u),1.1m,.1m) +C19 N012 VFOLD 800f +A1 4 3 0 0 0 0 0 0 OTA g=0 in=2p ink=628 +C4 5 3 .4p Rpar=25Meg noiseless +C5 5 2 10p Rpar=125k noiseless +D1 4 3 DIN +C7 4 3 400f +C8 5 4 .4p Rpar=25Meg noiseless +C9 3 2 .4p Rpar=35Meg noiseless +C13 4 2 .4p Rpar=35Meg noiseless +D2 5 N006 DBIAS1 +D3 4 N006 DBIAS2 +D4 3 N006 DBIAS2 +C20 N014 VFOLD 800f +G3 0 x2 N005 0 1m +C21 x2 0 400f Rpar=1k noiseless +A5 0 N004 0 0 0 0 N005 0 OTA g=1m linear en=4.2n enk=569 Rout=1k Cout=2p vlow=-2 vhigh=2 +R5 N016 2 2.2K noiseless +R6 N015 N014 160 noiseless +C22 VFOLD VMid 5p Rpar=1.407Meg Rser=1.5k noiseless +G7 0 VFOLDP VFOLD VMid 1µ +C23 VFOLDP 0 .5f Rpar=1Meg noiseless +C24 VFOLD 1 1.2p Rser=2.2k noiseless +C12 5 1 4p Rpar=200Meg noiseless +C25 1 2 4p Rpar=200Meg noiseless +G1 0 VMid 5 0 5m +G5 0 VMid 2 0 5m +C1 VMid 0 200p Rpar=100 noiseless +G2 VFOLD VMid VFOLD 5 10m vto=0 dir=1 +G4 VMid VFOLD 2 VFOLD 10m vto=0 dir=1 +G6 VMid VFOLD 0 X2 1.9m +D7 x2 0 DSL1 +D8 x2 0 DSL2 +G10 0 x2 N007 0 100m vto=520m dir=1 +G11 x2 0 0 N009 100m vto=520m dir=1 +C14 0 N009 500f Rpar=500k noiseless +A6 N007 N005 0 0 0 0 N007 0 OTA g=1m asym isource=20u isink=-1m vlow=0 vhigh=2 +C16 0 N007 500f Rpar=500k noiseless +A8 N009 N005 0 0 0 0 N009 0 OTA g=1m asym isource=1m isink=-20u vlow=-2 vhigh=0 +D5 5 2 DPOW +C2 N006 2 100f Rpar=10k noiseless +.model SSHUT SW(Ron=2.5e6 Roff=50Meg vt=-1.7 vh=-200m noiseless) +.model DIN D(Ron=100 Roff=32k Vfwd=1.6 epsilon=.1 Vrev=1.6 revepsilon=.1 noiseless) +.model DBIAS1 D(Ron=100 Roff=1g vfwd=4 epsilon=100m noiseless) +.model DBIAS2 D(Ron=100k Roff=200Meg vfwd=3 epsilon=100m ilimit=250n noiseless) +.model DPOW D(Ron=1K Roff=1g vfwd=.5 epsilon=10m ilimit=3.6u noiseless) +.model PNP1 PNP(BF=100 VAF=100 CJE=100f noiseless) +.model NPN1 NPN(BF=100 VAF=100 CJE=100f noiseless) +.model PNP2 PNP(BF=100 BR=.07 VAF=100 CJE=200f CJC=80f RC=15 TF=100p noiseless) +.model NPN2 NPN(BF=100 BR=.65 VAF=100 CJE=200f CJC=80f RC=5 TF=100p noiseless) +.model DSL1 D(Ron=10 Roff=200k vfwd=70m epsilon=10m vrev=70m revepsilon=10m noiseless ) +.model DSL2 D(Ron=.1 Roff=200k vfwd=800m epsilon=50m vrev=800m revepsilon=50m noiseless ) +.ends LTC6247 +* +.subckt LT6350 1 2 3 4 5 6 7 8 +A1 1 8 0 0 0 0 0 0 OTA g=0 in=1.1p ink=5 +B1 0 N007 I=10u*dnlim(uplim(V(8),V(3)+.2,.1), V(6)-.2, .1)+1n*V(8)-2.031n +B2 N007 0 I=10u*dnlim(uplim(V(1),V(3)+.21,.1), V(6)-.21, .1)+1n*V(1) +C10 N007 0 .1f Rpar=100K noiseless +M1 4 N013 6 6 NI temp=27 +C2 3 4 1p Rpar=1g noiseless +M2 4 N009 3 3 PI temp=27 +C3 3 N009 10f Rser=75Meg noiseless +C11 4 6 1p Rpar=1g noiseless +C12 N013 6 10f Rser=75Meg noiseless +D6 N013 6 DLIMN +A4 0 N007 0 0 0 0 N008 0 OTA g=1u linear en=1.9n enk=35 Cout=20f Vlow=-1e308 Vhigh=1e308 +C16 N011 4 1.05p Rser=400 +D12 8 3 DESD +D13 1 3 DESD +C7 3 8 .9p Rpar=25Meg noiseless +G4 0 N006 N008 0 1m +D14 3 N009 DLIMP +L1 N006 0 11.4µ Cpar=14.9f Rser=1.08k Rpar=13.5k noiseless +D16 N014 8 DBIA2 +D3 N014 1 DBIA2 +D1 6 1 DESD +D2 6 8 DESD +C1 3 1 .9p Rpar=25Meg noiseless +C6 8 6 .9p Rpar=25Meg noiseless +C8 1 6 .9p Rpar=25Meg noiseless +D5 N014 8 DBIA3 +D8 N014 1 DBIA3 +A6 N006 0 N010 N005 N005 N005 N011 N005 OTA g=600u linear Rout=80k Vlow=-1e308 Vhigh=1e308 +D9 3 7 DSHUT +A5 N005 N011 N010 N005 N005 N005 N009 N005 OTA g=52.5n ref=-.019 linear Vlow=-1e308 Vhigh=1e308 +D17 1 N003 DBIA1 +D18 8 N003 DBIA1 +C5 N014 6 20p Rpar=1Meg noiseless +D7 3 N004 DBIAZ +C14 3 N004 20p Rpar=10meg noiseless +C15 N005 0 100p Rpar=10 +S3 N004 N003 N010 N005 SWB2 +S4 3 6 N010 N005 SWP +C13 3 6 1000p +G2 0 N005 3 0 50m +G3 0 N005 6 0 50m +A3 INM2 2 0 0 0 0 0 0 OTA g=0 in=1p ink=5 +B3 0 N017 I=10u*dnlim(uplim(V(2),V(3)+.2,.1), V(6)-.2, .1)+1n*V(2)-2.028n +B4 N017 0 I=10u*dnlim(uplim(V(INM2),V(3)+.21,.1), V(6)-.21, .1)+1n*V(INM2) +C9 N017 0 .1f Rpar=100K noiseless +M3 5 N024 6 6 NI temp=27 +C18 3 5 1p Rpar=1g noiseless +M4 5 N019 3 3 PI temp=27 +C19 3 N019 10f Rser=75Meg noiseless +C20 5 6 1p Rpar=1g noiseless +C21 N024 6 10f Rser=75Meg noiseless +D10 N024 6 DLIMN +A7 0 N017 0 0 0 0 N020 0 OTA g=1u linear en=2.1n enk=35 Vhigh=80m Vlow=-80m +C22 N021 5 150f +D11 2 3 DESD +D19 INM2 3 DESD +G5 6 N024 N021 N005 10n +C23 3 2 .9p Rpar=20Meg noiseless +C24 0 N020 2f Rpar=1Meg noiseless +D20 3 N019 DLIMP +D24 6 INM2 DESD +D25 6 2 DESD +C25 3 INM2 .9p Rpar=20Meg noiseless +C26 2 6 .9p Rpar=20Meg noiseless +C27 INM2 6 .9p Rpar=20Meg noiseless +A8 N020 0 N010 N005 N005 N005 N021 N005 OTA g=60u linear Rout=800k Vlow=-1e308 Vhigh=1e308 +A9 N005 N021 N010 N005 N005 N005 N019 N005 OTA g=52.5n ref=-.019 linear Vlow=-1e308 Vhigh=1e308 +S5 6 2 N010 N005 SWBOP2 +R1 4 INM2 1k +S6 6 INM2 N010 N005 SWBOP2 +A10 7 6 N005 N005 N005 N005 N010 N005 SCHMITT Vt=300m vh=10m trise=50n tfall=100n +D22 0 N008 DLIM1 +D23 0 N008 DLIM2 +G1 6 N013 N011 N005 10n +R3 INM2 5 1k +S1 N014 3 N010 N005 SWB +D4 3 6 DP +C4 N004 6 1p Rpar=695k noiseless +D15 1 8 DSI temp=27 +D21 8 1 DSI temp=27 +D26 INM2 2 DSI temp=27 +D27 2 INM2 DSI temp=27 +.model DBIA1 D(Ron=10k Roff=6Meg Vfwd=0 ilimit=1.4u epsilon=.1 noiseless) +.model DBIA2 D(Ron=10k Roff=1g Vfwd=-.1 epsilon=.2 ilimit=.9u noiseless) +.model DBIA3 D(Ron=1k Roff=1g Vfwd=3 epsilon=.1 ilimit=1.3u noiseless) +.model DBIAZ D(Ron=100 Roff=100G Vfwd=.95 epsilon=50m noiseless) +.model DP D(Ron=1k Roff=1G Vfwd=1 epsilon=.1 ilimit=35.9u noiseless) +.model DESD D(Ron=100 Roff=100T Vfwd=1 epsilon=50m noiseless) +.model NI VDMOS(Vto=300m kp=55m lambda=.01) +.model PI VDMOS(Vto=-300m kp=55m lambda=.01 pchan) +.model DSHUT D(Ron=10k Roff=1g Vfwd=.6 epsilon=100m ilimit=20u noiseless) +.model DSI D(Is=1.4e-16 N=1 Rs=7.8 noiseless) +.model DLIM1 D(Ron=20k Roff=2Meg Vfwd=20m epsilon=2m Vrev=25m revepsilon=2m noiseless) +.model DLIM2 D(Ron=1k Roff=2Meg Vfwd=60m epsilon=10m Vrev=60m revepsilon=10m noiseless) +.model DLIMP D(Ron=100k Roff=1g Vfwd=1.5 Vrev=340m epsilon=500m revepsilon=100m noiseless) +.model DLIMN D(Ron=1Meg Roff=5g Vfwd=1.5 Vrev=340m epsilon=700m revepsilon=100m noiseless) +.model SWP SW(Roff=1G Ron=900 vt=.5 vh=-.1 ilimit=2.3m noiseless) +.model SWB SW(Ron=10k Roff=5G vt=.5 vh=-.1 vser=.95 noiseless) +.model SWB2 SW(Ron=1k Roff=100g vt=.5 vh=-.1 noiseless) +.model SWBOP2 SW(level=2 Ron=10k Roff=1G vt=.5 vh=-.1 ilimit=2.5u vser=.95 noiseless) +.ends LT6350 +* +.subckt LTC6362 1 2 3 4 5 6 7 8 +M1 4 N020 6 6 NI temp=27 +D5 N020 6 DLIMN +M2 4 N009 3 3 PI temp=27 +D8 3 N009 DLIMP +C3 3 N009 40f Rser=10Meg noiseless +A3 N010 N013 6 6 6 6 N009 6 OTA g=200n ref=-17m linear vlow=-1e308 vhigh=1e308 +A5 N011 0 N010 N010 N010 N010 N013 N010 OTA g=300u linear cout=1f Vhigh=1e308 Vlow=-1e308 +D9 N013 N010 DLIM +C7 3 8 .1p Rser=1k Rpar=28Meg noiseless +C13 3 6 100p Rpar=500k noiseless +S1 N013 N010 0 N008 SHUT2 +C17 6 7 500f +S4 N009 3 0 N008 SHUT1 +S2 6 N020 0 N008 SHUT1 +A2 7 6 0 0 0 0 N008 0 SCHMITT trise=2u tfall=2u vt=.8 vh=10m +D6 1 3 DESD +D7 6 1 DESD +D10 8 3 DESD +D11 6 8 DESD +A1 0 8 0 0 0 0 0 0 OTA g=0 in=795f ink=1.27k +M3 5 N028 6 6 NI temp=27 +D3 N028 6 DLIMN +M4 5 N025 3 3 PI temp=27 +D12 3 N025 DLIMP +A6 N010 XNP 6 6 6 6 N025 6 OTA g=200n ref=-17m linear vlow=-1e308 vhigh=1e308 +A7 0 N011 N010 N010 N010 N010 XNP N010 OTA g=300u linear cout=1f Vhigh=1e308 Vlow=-1e308 +D13 XNP N010 DLIM +S3 XNP N010 0 N008 SHUT2 +S5 N025 3 0 N008 SHUT1 +S6 6 N028 0 N008 SHUT1 +R3 4 5 2Meg noiseless +A8 0 N027 0 0 0 0 N018 0 OTA g=10m linear en=14.3n enk=1.1k Rout=1k Cout=100p ref=0 Vlow=-1e308 Vhigh=1e308 +R5 3 2 340K +R6 2 6 340K +G6 N010 XNP 0 N018 100µ +G7 N010 N013 0 N018 100µ +D14 N018 0 DCML +A4 0 N007 0 0 0 0 N005 0 OTA g=1m linear en=3.9n enk=1.05k Vhigh=1e308 Vlow=-1e308 +C23 N006 0 40p Rpar=1k noiseless +C1 1 8 500f Rser=2k Rpar=32k noiseless +C2 3 4 1p Rpar=100Meg noiseless +C8 4 6 1p Rpar=100Meg noiseless +C9 3 5 1p Rpar=100Meg noiseless +C11 5 6 1p Rpar=100Meg noiseless +C14 N013 4 8p Rser=6k noiseless +C16 5 XNP 8p Rser=6k noiseless +R10 3 7 225K noiseless +D2 3 6 DPOW +S7 6 3 N008 0 SPOWR2 +A10 0 1 0 0 0 0 0 0 OTA g=0 in=795f ink=1.27k +D1 2 3 DESD +D4 6 2 DESD +D17 7 3 DESD +D18 6 7 DESD +C10 N005 0 50f Rpar=1Meg noiseless +G3 0 N006 N005 0 1m +B1 0 N007 I=10u*dnlim(uplim(V(8),V(3)+.3,.1), V(6)-.3, .1)+1n*V(8) +B2 N007 0 I=10u*dnlim(uplim(V(1),V(3)+.31,.1), V(6)-.31, .1)+1n*V(1) +C20 N007 0 1f Rpar=100K noiseless +G8 0 N010 6 0 .5m +G9 0 N010 3 0 .5m +C21 N010 0 200p Rpar=1K noiseless +D15 0 N005 DLIMI +C4 3 1 .1p Rser=1k Rpar=28Meg noiseless +C5 8 6 .1p Rser=1k Rpar=28Meg noiseless +C6 1 6 .1p Rser=1k Rpar=28Meg noiseless +B3 0 N027 I=10u*dnlim(uplim(V(2),V(3)-.4,.1), V(6)+.42, .1) +B4 N027 0 I=5u*(V(4)+V(5)) +C24 N027 0 .1f Rpar=100K noiseless +C18 N005 N016 5p noiseless +R4 N016 0 8K noiseless +G17 8 1 N014 0 100µ +G15 0 N014 N016 0 1m +C29 N014 0 4p Rser=500 Rpar=1k noiseless +C12 N020 6 40f Rser=10Meg noiseless +C15 3 N025 40f Rser=10Meg noiseless +C19 N028 6 40f Rser=10Meg noiseless +C26 N017 0 4p Rser=100 Rpar=1k noiseless +G4 0 N017 N006 0 1m +C27 N011 0 2p Rpar=1k Rser=100 noiseless +G10 0 N011 N017 0 1m +S8 6 3 N008 0 SPOWR1 +A11 N010 N013 6 6 6 6 N020 6 OTA linear g=200n ref=17m vlow=-1e308 vhigh=1e308 +A12 N010 XNP 6 6 6 6 N028 6 OTA linear g=200n ref=17m vlow=-1e308 vhigh=1e308 +.model DPOW D(Ron=1k Roff=1G Vfwd=2 epsilon=.1 ilimit=30u noiseless) +.model SPOWR1 SW(level=2 Ron=1k Roff=1g vt=.5 vh=-.1 ilimit=609u noiseless) +.model SPOWR2 SW(Ron=20k Roff=1g vt=.5 vh=-.1 noiseless) +.model SHUT1 SW(Ron=100k Roff=100G vt=-.8 vh=-100m Vser=300m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=60m mtriode=.55 lambda=.0001 noiseless) +.model PI VDMOS(Vto=-300m Kp=60m mtriode=.8 lambda=.0001 pchan noiseless) +.model DLS D(Ron=10k Roff=1G Vfwd=.4 Vrev=.4 epsilon=50m revepsilon=50m noiseless) +.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.45 Vrev=-300m epsilon=.1 noiseless) +.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.45 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DCML D(Ron=10 Roff=1k Vfwd=500m epsilon=10m Vrev=500m revepsilon=10m noiseless) +.model DLIM D(Ron=700 Roff=70k Vfwd=400m Vrev=400m epsilon=10m revepsilon=10m noiseless) +.model DLIMI D(Ron=1 Roff=10k Vfwd=.615 Vrev=.615 epsilon=50m revepsilon=50m noiseless) +.model DESD D(Ron=100 Roff=1G Vfwd=.7 epsilon=.1 noiseless) +.ends LTC6362 +* +.subckt LTC1060 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +A1 0 N004 0 0 0 0 N006 0 OTA g=177u iout=98u Cout=14p Vlow=-1e308 Vhigh=1e308 +R1 7 N006 200Meg noiseless +R2 N006 10 200Meg noiseless +G1 N006 0 N006 7 500m dir=1 vto=.1 +G2 0 N006 10 N006 500m dir=1 vto=.1 +M1 7 N005 3 3 N temp=27 +M2 10 N005 3 3 P temp=27 +D1 N005 3 YU +D2 3 N005 YD +G3 0 N005 N006 0 1µ +G8 11 N011 5 11 10 +G9 11 N011 N017 0 10 +G7 0 N017 1 11 1µ +C2 N013 N012 1p +R5 7 N013 100Meg noiseless +R6 N013 10 100Meg noiseless +G5 N013 0 N013 7 500m dir=1 vto=-1 +G11 0 N013 10 N013 500m dir=1 vto=-1 +M3 7 N014 2 2 N temp=27 +M4 10 N014 2 2 P temp=27 +D3 N014 2 YU +D4 2 N014 YD +G12 0 N014 N013 0 1µ +C3 N014 0 .4f Rpar=1Meg noiseless +G13 11 N018 11 2 10 +R8 N019 N018 {RintA} noiseless +C4 N020 N019 1p +R9 7 N020 100Meg noiseless +R10 N020 10 100Meg noiseless +G14 N020 0 N020 7 500m dir=1 vto=-1 +G15 0 N020 10 N020 500m dir=1 vto=-1 +M5 7 N021 1 1 N temp=27 +M6 10 N021 1 1 P temp=27 +D5 N021 1 YU +D6 1 N021 YD +G16 0 N021 N020 0 1µ +C1 N021 0 .4f Rpar=1Meg noiseless +C5 N005 0 10f Rpar=1Meg noiseless +A2 N012 11 N023 0 0 0 N013 0 OTA g=2m iout=98u Cout=350p Vlow=-1e308 Vhigh=1e308 +A3 N019 11 N023 0 0 0 N020 0 OTA g=2m iout=98u Cout=350p Vlow=-1e308 Vhigh=1e308 +D7 N024 10 DPV +S3 N024 7 7 10 SPV +B1 0 N004 I=10u*dnlim(uplim(V(11),V(7)-.9,.1), V(10)+.9, .1)+1n*V(11) +B2 N004 0 I=10u*dnlim(uplim(V(4),V(7)-.89,.1), V(10)+.89, .1)+1n*V(4) +C6 N004 0 .2f Rpar=100K noiseless +C7 4 10 200f +C8 7 4 200f +C9 10 5 200f +C10 N011 11 100f Rpar=.1 noiseless +C11 N018 11 100f Rpar=.1 noiseless +A4 0 N026 0 0 0 0 N029 0 OTA g=177u iout=98u Cout=14p Vlow=-1e308 Vhigh=1e308 +R3 7 N029 200Meg noiseless +R7 N029 10 200Meg noiseless +G10 N029 0 N029 7 500m dir=1 vto=.1 +G18 0 N029 10 N029 500m dir=1 vto=.1 +M7 7 N028 14 14 N temp=27 +M8 10 N028 14 14 P temp=27 +D8 N028 14 YU +D9 14 N028 YD +G19 0 N028 N029 0 1µ +R11 N031 N033 {RintB} noiseless +C12 N032 N031 1p +R18 7 N032 100Meg noiseless +R19 N032 10 100Meg noiseless +G25 N032 0 N032 7 500m dir=1 vto=-1 +G26 0 N032 10 N032 500m dir=1 vto=-1 +M9 7 N034 15 15 N temp=27 +M10 10 N034 15 15 P temp=27 +D10 N034 15 YU +D11 15 N034 YD +G27 0 N034 N032 0 1µ +C13 N034 0 .4f Rpar=1Meg noiseless +G28 11 N037 11 15 10 +C14 N039 N038 1p +R21 7 N039 200Meg noiseless +R22 N039 10 200Meg noiseless +G29 N039 0 N039 7 500m dir=1 vto=-1 +G30 0 N039 10 N039 500m dir=1 vto=-1 +M11 7 N040 16 16 N temp=27 +M12 10 N040 16 16 P temp=27 +D12 N040 16 YU +D13 16 N040 YD +G31 0 N040 N039 0 1µ +C15 N040 0 .4f Rpar=1Meg noiseless +C16 N028 0 10f Rpar=1Meg noiseless +A5 N031 11 N023 0 0 0 N032 0 OTA g=2m iout=98u Cout=350p Vlow=-1e308 Vhigh=1e308 +A6 N038 11 N023 0 0 0 N039 0 OTA g=2m iout=98u Rout=100Meg Cout=350p Vlow=-1e308 Vhigh=1e308 +B3 0 N026 I=10u*dnlim(uplim(V(11),V(7)-.9,.1), V(10)+.9, .1)+1n*V(11) +B4 N026 0 I=10u*dnlim(uplim(V(13),V(7)-.89,.1), V(10)+.89, .1)+1n*V(13) +C17 N026 0 .2f Rpar=100K noiseless +C18 13 10 200f +C19 7 13 200f +C20 10 12 200f +C22 N037 11 100f Rpar=.1 noiseless +R12 10 6 10Meg noiseless +R4 N012 N011 {RintA} noiseless +R14 N038 N037 {RintB} noiseless +C23 N024 10 10p +C24 8 9 100f Rpar=34k noiseless +C25 N013 N012 .001f IC=0 Rser=1g noiseless +C26 N020 N019 .001f IC=0 Rser=1g noiseless +C27 N032 N031 .001f IC=0 Rser=1G noiseless +C28 N039 N038 .001f IC=0 Rser=1G noiseless +G4 0 N023 N024 10 10m +C29 N023 0 100µ Rpar=100 noiseless +G17 N011 11 3 11 10 +G6 11 N033 12 11 10 +G20 11 N033 N036 0 10 +G21 0 N036 16 11 1µ +C21 N033 11 100f Rpar=.1 noiseless +S2 N036 0 8 6 SBUF +G22 N033 11 14 11 10 +S1 N017 0 8 6 SBUF +.model YU D(Ron=1k Roff=1T Vfwd=.6 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=.1 epsilon=.1 noiseless) +.model N VDMOS(Vto=-140m Kp=80m) +.model P VDMOS(Vto=140m Kp=80m pchan) +.param dividerInt = table(divider,0,50,75,50,76,100) +.param RintA=1e12*dividerInt/(2*PI*fclka) +.param RintB=1e12*dividerInt/(2*PI*fclkb) +.model SBUF SW(Ron=.1 Roff=1Meg vt=1 vh=-.8 noiseless) +.model SPV SW(Ron=400k Roff=1Meg vt=11 vh=-3 noiseless) +.model DPV D(Ron=50k Roff=200k Vfwd=.744 epsilon=.1 noiseless) +.ends LTC1060 +* +.subckt LTC1067 1 2 3 4 5 6 7 8 9 10 11 12 13 +R1 1 N006 200Meg noiseless +R2 N006 12 200Meg noiseless +M1 1 N005 5 5 N temp=27 +M2 12 N005 5 5 P temp=27 +D1 N005 5 YU +D2 5 N005 YD +G3 0 N005 N006 0 1µ +G8 13A N014 2 13A 10 +C2 N012 N011 1p +R5 1 N012 100Meg noiseless +R6 N012 12 100Meg noiseless +G5 N012 0 N012 1 500m dir=1 vto=-.15 +G11 0 N012 12 N012 500m dir=1 vto=.1 +M3 1 N015 4 4 N temp=27 +M4 12 N015 4 4 P temp=27 +D3 N015 4 YU +D4 4 N015 YD +G12 0 N015 N012 0 1µ +C3 N015 0 .4f Rpar=1Meg noiseless +G13 13A N018 13A 4 10 +R8 N019 N018 {Rint} noiseless +C4 N020 N019 1p +R9 1 N020 100Meg noiseless +R10 N020 12 100Meg noiseless +G14 N020 0 N020 1 500m dir=1 vto=-.15 +G15 0 N020 12 N020 500m dir=1 vto=.1 +M5 1 N021 3 3 N temp=27 +M6 12 N021 3 3 P temp=27 +D5 N021 3 YU +D6 3 N021 YD +G16 0 N021 N020 0 1µ +C5 N005 0 20f Rpar=1Meg noiseless +A2 N011 13A N017 0 0 0 N012 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +S3 N023 1 1 12 SPV +B1 0 N004 I=10u*dnlim(uplim(V(13A),V(1)+.2,.1), V(12)-.2, .1)+1n*V(13A) +B2 N004 0 I=10u*dnlim(uplim(V(6),V(1)+.21,.1), V(12)-.21, .1)+1n*V(6) +C6 N004 0 .2f Rpar=100K noiseless +C7 6 12 200f +C8 1 6 200f +C9 12 2 200f +C10 N014 13A 100f Rpar=.1 noiseless +C11 N018 13A 100f Rpar=.1 noiseless +R3 1 N026 200Meg noiseless +R7 N026 12 200Meg noiseless +M7 1 N025 8 8 N temp=27 +M8 12 N025 8 8 P temp=27 +D8 N025 8 YU +D9 8 N025 YD +G19 0 N025 N026 0 1µ +R11 N028 N030 {Rint} noiseless +C12 N029 N028 1p +R18 1 N029 100Meg noiseless +R19 N029 12 100Meg noiseless +G25 N029 0 N029 1 500m dir=1 vto=-.15 +G26 0 N029 12 N029 500m dir=1 vto=.1 +M9 1 N031 9 9 N temp=27 +M10 12 N031 9 9 P temp=27 +D10 N031 9 YU +D11 9 N031 YD +G27 0 N031 N029 0 1µ +C13 N031 0 .4f Rpar=1Meg noiseless +G28 13A N033 13A 9 10 +C14 N035 N034 1p +R21 1 N035 200Meg noiseless +R22 N035 12 200Meg noiseless +G29 N035 0 N035 1 500m dir=1 vto=-.15 +G30 0 N035 12 N035 500m dir=1 vto=.1 +M11 1 N036 10 10 N temp=27 +M12 12 N036 10 10 P temp=27 +D12 N036 10 YU +D13 10 N036 YD +G31 0 N036 N035 0 1µ +C15 N036 0 .4f Rpar=1Meg noiseless +C16 N025 0 20f Rpar=1Meg noiseless +B3 0 N024 I=10u*dnlim(uplim(V(13A),V(1)+.2,.1), V(12)-.2, .1)+1n*V(13A) +B4 N024 0 I=10u*dnlim(uplim(V(7),V(1)+.21,.1), V(12)-.21, .1)+1n*V(7) +C17 N024 0 .2f Rpar=100K noiseless +C18 7 12 200f +C19 1 7 200f +C20 12 11 200f +C21 N030 13A 100f Rpar=.1 noiseless +C22 N033 13A 100f Rpar=.1 noiseless +R4 N011 N014 {Rint} noiseless +R14 N034 N033 {Rint} noiseless +C23 N023 12 10p +C27 N029 N028 .001f IC=0 Rser=1Meg noiseless +C28 N035 N034 .001f IC=0 Rser=1Meg noiseless +C24 1 13 1p Rpar=15k +C29 13 12 1p Rpar=15k +G1 N006 0 N006 1 500m dir=1 vto=-.15 +G2 0 N006 12 N006 500m dir=1 vto=.1 +A1 0 N004 0 0 0 0 N006 0 OTA g=318u iout=38.5u Cout=17p Vlow=-1e308 Vhigh=1e308 +G4 N026 0 N026 1 500m dir=1 vto=-.15 +G6 0 N026 12 N026 500m dir=1 vto=.1 +C1 N021 0 .4f Rpar=1Meg noiseless +A3 N019 13A N017 0 0 0 N020 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +A5 N034 13A N017 0 0 0 N035 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A6 N028 13A N017 0 0 0 N029 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +D14 N023 12 DPV1 +R27 1 12 3.8k noiseless +A4 0 N024 0 0 0 0 N026 0 OTA g=318u iout=38.5u Cout=17p Vlow=-1e308 Vhigh=1e308 +G7 0 13A 13 0 10m +C31 13A 0 100µ Rpar=100 noiseless +C32 1 5 1p +C33 5 12 1p +C34 1 4 1p +C35 4 12 1p +C36 1 3 1p +C37 3 12 1p +C38 1 8 1p +C39 8 12 1p +C40 1 9 1p +C41 9 12 1p +C42 1 10 1p +C43 10 12 1p +C25 N020 N019 .001f IC=0 Rser=1G noiseless +C26 N012 N011 .001f IC=0 Rser=1G noiseless +G10 0 N017 N023 12 10m +C45 N017 0 100µ Rpar=100 noiseless +G18 N014 13A 5 13A 10 +G17 N030 13A 8 13A 10 +G9 13A N030 11 13A 10 +D7 N023 12 DPV2 +D15 1 12 DP +.param Rint=1e14/(2.007*PI*fclk) +.model YU D(Ron=1k Roff=1T Vfwd=3.01 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=1 epsilon=.1 noiseless) +.model N VDMOS(Vto=-140m Kp=14m) +.model P VDMOS(Vto=140m Kp=14m pchan) +.model SBUF1 SW(Ron=.1 Roff=1Meg vt=-1 vh=-.2 noiseless) +.model SBUF2 SW(Ron=.1 Roff=1Meg vt=1 vh=-.2 noiseless) +.model DP D(Ron=100 Roff=1Meg vfwd=2 epsilon=.1 ilimit=.55m noiseless) +.model SPV SW(Ron=500k Roff=10Meg vt=2.3 vh=-.7 noiseless) +.model DPV1 D(Ron=400k Roff=63k Vfwd=.45 epsilon=1 noiseless) +.model DPV2 D(Ron=500 Roff=1Meg Vfwd=.35 epsilon=80m ilimit=2.5u noiseless) +.ends LTC1067 +* +.subckt LTC1067-50 1 2 3 4 5 6 7 8 9 10 11 12 13 +R1 1 N006 200Meg noiseless +R2 N006 12 200Meg noiseless +M1 1 N005 5 5 N temp=27 +M2 12 N005 5 5 P temp=27 +D1 N005 5 YU +D2 5 N005 YD +G3 0 N005 N006 0 1µ +G8 13A N014 2 13A 10 +C2 N012 N011 1p +R5 1 N012 100Meg noiseless +R6 N012 12 100Meg noiseless +G5 N012 0 N012 1 500m dir=1 vto=-.15 +G11 0 N012 12 N012 500m dir=1 vto=.1 +M3 1 N015 4 4 N temp=27 +M4 12 N015 4 4 P temp=27 +D3 N015 4 YU +D4 4 N015 YD +G12 0 N015 N012 0 1µ +C3 N015 0 .4f Rpar=1Meg noiseless +G13 13A N018 13A 4 10 +R8 N019 N018 {Rint} noiseless +C4 N020 N019 1p +R9 1 N020 100Meg noiseless +R10 N020 12 100Meg noiseless +G14 N020 0 N020 1 500m dir=1 vto=-.15 +G15 0 N020 12 N020 500m dir=1 vto=.1 +M5 1 N021 3 3 N temp=27 +M6 12 N021 3 3 P temp=27 +D5 N021 3 YU +D6 3 N021 YD +G16 0 N021 N020 0 1µ +C5 N005 0 20f Rpar=1Meg noiseless +A2 N011 13A N017 0 0 0 N012 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +S3 N023 1 1 12 SPV +B1 0 N004 I=10u*dnlim(uplim(V(13A),V(1)+.2,.1), V(12)-.2, .1)+1n*V(13A) +B2 N004 0 I=10u*dnlim(uplim(V(6),V(1)+.21,.1), V(12)-.21, .1)+1n*V(6) +C6 N004 0 .2f Rpar=100K noiseless +C7 6 12 200f +C8 1 6 200f +C9 12 2 200f +C10 N014 13A 100f Rpar=.1 noiseless +C11 N018 13A 100f Rpar=.1 noiseless +R3 1 N026 200Meg noiseless +R7 N026 12 200Meg noiseless +M7 1 N025 8 8 N temp=27 +M8 12 N025 8 8 P temp=27 +D8 N025 8 YU +D9 8 N025 YD +G19 0 N025 N026 0 1µ +R11 N028 N030 {Rint} noiseless +C12 N029 N028 1p +R18 1 N029 100Meg noiseless +R19 N029 12 100Meg noiseless +G25 N029 0 N029 1 500m dir=1 vto=-.15 +G26 0 N029 12 N029 500m dir=1 vto=.1 +M9 1 N031 9 9 N temp=27 +M10 12 N031 9 9 P temp=27 +D10 N031 9 YU +D11 9 N031 YD +G27 0 N031 N029 0 1µ +C13 N031 0 .4f Rpar=1Meg noiseless +G28 13A N033 13A 9 10 +C14 N035 N034 1p +R21 1 N035 200Meg noiseless +R22 N035 12 200Meg noiseless +G29 N035 0 N035 1 500m dir=1 vto=-.15 +G30 0 N035 12 N035 500m dir=1 vto=.1 +M11 1 N036 10 10 N temp=27 +M12 12 N036 10 10 P temp=27 +D12 N036 10 YU +D13 10 N036 YD +G31 0 N036 N035 0 1µ +C15 N036 0 .4f Rpar=1Meg noiseless +C16 N025 0 20f Rpar=1Meg noiseless +B3 0 N024 I=10u*dnlim(uplim(V(13A),V(1)+.2,.1), V(12)-.2, .1)+1n*V(13A) +B4 N024 0 I=10u*dnlim(uplim(V(7),V(1)+.21,.1), V(12)-.21, .1)+1n*V(7) +C17 N024 0 .2f Rpar=100K noiseless +C18 7 12 200f +C19 1 7 200f +C20 12 11 200f +C21 N030 13A 100f Rpar=.1 noiseless +C22 N033 13A 100f Rpar=.1 noiseless +R4 N011 N014 {Rint} noiseless +R14 N034 N033 {Rint} noiseless +C23 N023 12 10p +C27 N029 N028 .001f IC=0 Rser=1Meg noiseless +C28 N035 N034 .001f IC=0 Rser=1Meg noiseless +C24 1 13 1p Rpar=15k +C29 13 12 1p Rpar=15k +G1 N006 0 N006 1 500m dir=1 vto=-.15 +G2 0 N006 12 N006 500m dir=1 vto=.1 +A1 0 N004 0 0 0 0 N006 0 OTA g=318u iout=20.1u Cout=25p Vlow=-1e308 Vhigh=1e308 +G4 N026 0 N026 1 500m dir=1 vto=-.15 +G6 0 N026 12 N026 500m dir=1 vto=.1 +C1 N021 0 .4f Rpar=1Meg noiseless +A3 N019 13A N017 0 0 0 N020 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +A5 N034 13A N017 0 0 0 N035 0 OTA g=2.43m iout=98u Rout=100Meg Cout=200p Vlow=-1e308 Vhigh=1e308 +A6 N028 13A N017 0 0 0 N029 0 OTA g=2.43m iout=98u Cout=200p Vlow=-1e308 Vhigh=1e308 +D14 N023 12 DPV1 +R27 1 12 8.3k noiseless +A4 0 N024 0 0 0 0 N026 0 OTA g=318u iout=20.1u Cout=25p Vlow=-1e308 Vhigh=1e308 +R28 N023 12 320k noiseless +G7 0 13A 13 0 10m +C31 13A 0 100µ Rpar=100 noiseless +C32 1 5 1p +C33 5 12 1p +C34 1 4 1p +C35 4 12 1p +C36 1 3 1p +C37 3 12 1p +C38 1 8 1p +C39 8 12 1p +C40 1 9 1p +C41 9 12 1p +C42 1 10 1p +C43 10 12 1p +C25 N020 N019 .001f IC=0 Rser=1G noiseless +C26 N012 N011 .001f IC=0 Rser=1G noiseless +G10 0 N017 N023 12 10m +C45 N017 0 100µ Rpar=100 noiseless +G18 N014 13A 5 13A 10 +G17 N030 13A 8 13A 10 +G9 13A N030 11 13A 10 +.param Rint=1e14/(4.007*PI*fclk) +.model SBUF1 SW(Ron=.1 Roff=1Meg vt=-1 vh=-.2 noiseless) +.model SBUF2 SW(Ron=.1 Roff=1Meg vt=1 vh=-.2 noiseless) +.model YU D(Ron=1k Roff=1T Vfwd=3.01 epsilon=.1 noiseless) +.model YD D(Ron=1k Roff=1T Vfwd=1 epsilon=.1 noiseless) +.model N VDMOS(Vto=-140m Kp=14m) +.model P VDMOS(Vto=140m Kp=14m pchan) +.model SPV SW(Ron=720k Roff=10Meg vt=2.63 vh=-.7 noiseless) +.model DPV1 D(Ron=50k Roff=1Meg Vfwd=1 epsilon=200m noiseless) +.ends LTC1067-50 +* +.subckt LT6236 1 2 3 4 5 6 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=1p ink=33.5 incm=2.2p incmk=33.5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.9,.1), V(5)+1.4, .1)+1n*V(1)-1.1n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.89,.1), V(5)+1.39, .1)+1n*V(2) +C10 N004 0 .5f Rpar=100K noiseless +M1 3 N012 5 5 NI temp=27 +C2 4 3 1p Rpar=200Meg noiseless +D5 N012 5 DLIMN1 +M2 3 N008 4 4 PI temp=27 +D8 4 N008 DLIMP1 +C3 4 N008 1f Rser=50Meg noiseless +A3 N009 N010 5 5 5 5 N008 5 OTA g=20n ref=-.94 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=200Meg noiseless +C12 N012 5 1f Rser=50Meg noiseless +C16 N010 3 50f +A5 N007 0 N009 N009 N009 N009 N010 N009 OTA g=65u iout=3.78u Vhigh=1e308 Vlow=-1e308 +G1 5 N012 N010 N009 20n +C7 4 1 1.45p Rser=200 Rpar=40Meg noiseless +C13 4 5 1000p Rpar=190Meg noiseless +S1 N010 N009 0 N005 SHUT2 +C1 N006 0 17p +C17 5 6 500f Rpar=100Meg noiseless +G2 0 N009 5 0 .5m +G4 0 N009 4 0 .5m +C18 N009 0 200p Rpar=1K noiseless +D1 2 1 DIN +D3 4 6 DSHUT +S4 N008 4 0 N005 SHUT1 +S2 5 N012 0 N005 SHUT1 +S3 5 2 N005 0 SBIAS +S5 5 1 N005 0 SBIAS +S7 4 5 N005 0 SPOW +D2 4 N008 DLIMP2 +D4 N012 5 DLIMN2 +C8 2 1 6.25p Rser=100 noiseless +G3 0 N007 N006 0 1m +L1 N007 0 8.6µ Cpar=12.7f Rser=1.09k Rpar=12.1k noiseless +D6 N006 0 DLIM1 +C4 4 2 1.45p Rser=200 Rpar=40Meg noiseless +C5 1 5 1.45p Rser=200 Rpar=40Meg noiseless +C6 2 5 1.45p Rser=200 Rpar=40Meg noiseless +C9 N007 3 15f +D7 N010 N009 DLIM2 +A2 6 4 0 0 0 N005 0 0 SCHMITT Vt=-.4 trise=1u tfall=90u +A4 0 N004 0 0 0 0 N006 0 OTA g=1m linear enk=201 en=1.09n+.25n*(1+tanh(log(freq/1e6)))/(dnlim(freq-40Meg,10Meg,10Meg)/10Meg) enk=201 Vlow=-1e308 Vhigh=1e308 +.model DSHUT D(Ron=170k Roff=1G Vfwd=2 epsilon=100m noiseless) +.model DIN D(Ron=100 Roff=7.5k Vfwd=.8 epsilon=.1 Vrev=.8 revepsilon=.1 noiseless) +.model SBIAS SW(level=2 Ron=5k Roff=10G vt=.5 vh=-.1 ilimit=5u vser=.8 noiseless ) +.model SPOW SW(Ron=92.6k Roff=1G vt=.5 vh=.1 noiseless) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m Vser=295m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=120m Rd=8) +.model PI VDMOS(Vto=-300m Kp=120m Rd=8 pchan) +.model DSLIM D(Ron=100 Roff=1k Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIM1 D(Ron=1 Roff=1k Vfwd=70m epsilon=10m Vrev=70m revepsilon=10m noiseless) +.model DLIM2 D(Ron=1k Roff=70Meg Vfwd=2.1 epsilon=.1 Vrev=1.9 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.ends LT6236 +* +.subckt LT6237 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=2.4p ink=33.5 +B1 0 N004 I=10u*dnlim(uplim(V(1),V(4)-.9,.1), V(5)+1.4, .1)+1n*V(1)-1.033327545n +B2 N004 0 I=10u*dnlim(uplim(V(2),V(4)-.89,.1), V(5)+1.39, .1)+1n*V(2) +C10 N004 0 .5f Rpar=100K noiseless +M1 3 N011 5 5 NI temp=27 +C2 4 3 1p Rpar=200Meg noiseless +D5 N011 5 DLIMN1 +M2 3 N007 4 4 PI temp=27 +D8 4 N007 DLIMP1 +C3 4 N007 1f Rser=50Meg noiseless +A3 N008 N009 5 5 5 5 N007 5 OTA g=20n ref=-.94 linear vlow=-1e308 vhigh=1e308 +C11 3 5 1p Rpar=200Meg noiseless +C12 N011 5 1f Rser=50Meg noiseless +C16 N009 3 50f +A5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=65u iout=3.78u Vhigh=1e308 Vlow=-1e308 +G1 5 N011 N009 N008 20n +C7 4 1 1.45p Rser=200 Rpar=40Meg noiseless +C13 4 5 1000p Rpar=92.6k noiseless +C1 N005 0 17p +G2 0 N008 5 0 .5m +G4 0 N008 4 0 .5m +C18 N008 0 200p Rpar=1K noiseless +D1 2 1 DIN +D2 4 N007 DLIMP2 +D4 N011 5 DLIMN2 +C8 2 1 6.25p Rser=100 noiseless +G3 0 N006 N005 0 1m +L1 N006 0 8.6µ Cpar=12.7f Rser=1.09k Rpar=12.1k noiseless +D6 N005 0 DLIM1 +C4 4 2 1.45p Rser=200 Rpar=40Meg noiseless +C5 1 5 1.45p Rser=200 Rpar=40Meg noiseless +C6 2 5 1.45p Rser=200 Rpar=40Meg noiseless +C9 N006 3 15f +D7 N009 N008 DLIM2 +D3 2 5 DBIAS +D9 1 5 DBIAS +A2 0 N004 0 0 0 0 N005 0 OTA g=1m linear enk=201 en=1.09n+.25n*(1+tanh(log(freq/1e6)))/(dnlim(freq-40Meg,10Meg,10Meg)/10Meg) enk=201 Vlow=-1e308 Vhigh=1e308 +.model DSHUT D(Ron=170k Roff=1G Vfwd=2 epsilon=100m noiseless) +.model DIN D(Ron=100 Roff=7.5k Vfwd=.8 epsilon=.1 Vrev=.8 revepsilon=.1 noiseless) +.model DBIAS D(Ron=5k Roff=1G Vfwd=.75 epsilon=50m ilimit=5u noiseless) +.model SHUT1 SW(Ron=10k Roff=100G vt=-.8 vh=-100m Vser=295m noiseless) +.model SHUT2 SW(Ron=1k Roff=100G vt=-.8 vh=-100m noiseless) +.model NI VDMOS(Vto=300m kp=120m Rd=8) +.model PI VDMOS(Vto=-300m Kp=120m Rd=8 pchan) +.model DSLIM D(Ron=100 Roff=1k Vfwd=1.5 Vrev=.1 epsilon=.1 revepsilon=.1 noiseless) +.model DLIM1 D(Ron=1 Roff=1k Vfwd=70m epsilon=10m Vrev=70m revepsilon=10m noiseless) +.model DLIM2 D(Ron=1k Roff=70Meg Vfwd=2.1 epsilon=.1 Vrev=1.9 revepsilon=.1 noiseless) +.model DLIMN1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=.1 revepsilon=10m noiseless) +.model DLIMN2 D(Ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.model DLIMP1 D(Ron=1k Roff=100Meg Vfwd=1.05 Vrev=-300m epsilon=10m revepsilon=10m noiseless) +.model DLIMP2 D(ron=30Meg Vfwd=.3 epsilon=.2 noiseless) +.ends LT6237 +* +.subckt LTC6752 1 2 3 4 5 +B1 0 N001 I=10u*dnlim(uplim(V(1),V(3)+.15,.1), V(4)-.2 ,.1)+1n*V(1) +B2 N001 0 I=10u*dnlim(uplim(V(2),V(3)+.15,.1), V(4)-.21, .1)+1n*V(2) +C1 N001 0 1f Rpar=1Meg +D5 0 VDH DLAT +C4 2 4 .55p +C10 1 4 .55p +M3 5 N0 4 4 NI temp=27 +M4 5 P0 3 3 PI temp=27 +C7 3 5 1p +C8 5 4 1p +C5 3 2 .55p Rpar=10Meg +B3 0 N001 I=29n*tanh(V(VDH)/1m) +C9 3 P0 4.9f Rpar=1Meg +G2 N0 4 N0 3 10m vto=0 dir=1 +G3 3 P0 4 P0 10m vto=-482m dir=1 +C2 N0 4 5f Rpar=1Meg +B4 P0 4 I=1.18*uplim(12u*(V(VDH)+90m),1.19u*V(VILIM) ,1u)*(.5+.5*tanh(V(3,P0)/100m)) +B5 3 N0 I=1.18*uplim(15u*(90m-V(VDH)),1u*V(VILIMF),1u)*(.5+.5*tanh(V(N0,4)/100m)) +C12 VILIM 0 100p Rpar=1k +G5 0 VILIM 3 4 table(1.6 6.5m 1.8 6m 2 6.2m 2.4 8m 2.6 8m 3.2 9m 3.6 9m) +D1 N001 0 DVGAIN +C13 VILIMF 0 100p Rpar=1k +G6 0 VILIMF 3 4 table(1.6 6m 1.8 6.8m 2 7.9m 2.2 9m 2.4 10m 3.0 11m 3.6 10m) +D2 3 2 DBIASR +D4 2 4 DBIASF +D7 3 1 DBIASR +D8 1 4 DBIASF +D11 3 4 DBURN +A2 0 N001 0 0 0 0 VDH 0 OTA g=1.8m iout=100u Cout=56f Vlow=-1e308 Vhigh=1e308 +D14 5 3 DESD +D15 4 5 DESD +D17 2 3 DESD +D16 4 2 DESD +D18 2 1 DBIASC +C19 3 1 .55p Rpar=10Meg +D9 1 3 DESD +D19 4 1 DESD +R2 3 4 2.67k +.model DVGAIN D(Ron=100k Roff=500k vfwd=15m epsilon=15m vrev=15m revepsilon=15m) +.model DLAT D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9) +.model DBURN D(Ron=100 Roff=1Meg vfwd=600m epsilon=500m ilimit=3.56m) +.model DBIASC D(Ron=1k Roff=100Meg Ron=57k vfwd=10u vrev=10u epsilon=10u revepsilon=10u ilimit=.8u revilimit=.8u) +.model NI VDMOS(Vto=600m kp=12m mtriode= 3 lambda=.1 Rs=8) +.model PI VDMOS(Vto=-600m Kp=24m mtriode=1.9 lambda=.08 pchan) +.model DBIASF D(Ron=300k Roff=1G vfwd=1.3 epsilon=200m ilimit=.33u ) +.model DBIASR D(Ron=100k Roff=1G vfwd=1 epsilon=200m ilimit=1.2u ) +.model DESD D(Ron=100 Roff=1G vfwd=650m epsilon=500m) +.ends LTC6752 +* +.subckt LTC6752-2 1 2 3 4 5 6 7 8 +B1 0 N003 I=10u*dnlim(uplim(V(4),V(2)+.15,.1), V(3)-.2 ,.1)+1n*V(4) +B2 N003 0 I=10u*dnlim(uplim(V(5),V(2)+.15,.1), V(3)-.21, .1)+1n*V(5) +C1 N003 0 1f Rpar=1Meg +D5 0 VDH DLAT +C4 5 3 .55p +C10 4 3 .55p +M3 8 N0 3 3 NI temp=27 +M4 8 P0 1 1 PI temp=27 +C7 1 8 1p +C8 8 3 1p +C5 2 5 .55p Rpar=10Meg +R3 2 6 350k +A6 N007 0 N008 0 0 0 VDH 0 OTA g=500u linear Vlow=-1e308 Vhigh=1e308 +D6 0 N007 DLAT +C3 N007 0 1p +G1 0 N007 0 VDH 500µ +R4 N005 7 20k +A8 7 3 0 0 0 N002 0 0 SCHMITT vt=.3 vh=0 trise=7.2n tfall=6n +S5 N005 2 3 N005 SW1p25 +C11 VH 0 1p Rpar=2k +B3 0 N003 I=5u*V(VH)*tanh(V(VDH)/1m) +G4 0 VH 7 3 Table(750m 47u 917m 25u 1 15u 1.06 10u 1.08 8.5u 1.167 5.2u 1.227 5u 1.47 0) +S6 0 VH 7 3 SHYOFF +C9 1 P0 4.9f Rpar=1Meg +S1 N0 3 0 ON SoffN +S7 1 P0 0 ON SoffP +G2 N0 3 N0 Vmax 10m vto=0 dir=1 +G3 1 P0 Vmin P0 10m vto=0 dir=1 +C2 N0 3 5f Rpar=1Meg +B4 P0 3 I=1.18*uplim(12u*(V(VDH)+90m),1.2u* (.234*V(Vmin,3)+.88) *V(VILIM) ,1u)*(.5+.5*tanh(V(1,P0)/100m)) +B5 1 N0 I=1.18*uplim(15u*(90m-V(VDH)),1u*(1+.2*V(Vmax,1))*V(VILIMF),1u)*(.5+.5*tanh(V(N0,3)/100m)) +C12 VILIM 0 100p Rpar=1k +G5 0 VILIM 1 3 table(1.6 6.5m 1.8 6m 2 6.2m 2.4 8m 2.6 8m 3.2 9m 3.6 9m) +D1 N003 0 DVGAIN +C13 VILIMF 0 100p Rpar=1k +G6 0 VILIMF 1 3 table(1.6 6m 1.8 6.8m 2 7.9m 2.2 9m 2.4 10m 3.0 11m 3.6 10m) +D3 7 3 DBLE +D2 2 5 DBIASR +D4 5 3 DBIASF +S2 3 2 ON 0 SVCCP +D7 2 4 DBIASR +D8 4 3 DBIASF +C14 N005 3 1p Rpar=100k +A5 N002 0 0 0 0 0 N008 0 BUF trise=2n tfall=2n +A4 1 2 1 1 1 1 Vmax 1 OTA g=550u iout=550u Rout=1k Cout=10p vlow=0 vhigh=1e308 +A3 2 3 3 3 3 3 Vmin 3 OTA g=400u iout=500u ref=5 Rout=1k Cout=10p vlow=0 vhigh=1e308 +D10 2 3 DBURNSD +R1 2 3 28.8k +D11 1 3 DBURNSD2 +S8 3 1 ON 0 SVDDP +S9 3 1 ON 0 SVDDP2 +A2 0 N003 0 0 0 0 VDH 0 OTA g=1.8m iout=100u Cout=56f Vlow=-1e308 Vhigh=1e308 +S10 0 VDH 0 ON SOFF +A1 3 6 0 0 0 0 ON 0 OTA g=21u iout=7u ref=-.9 Rout=200k Cout=750f vlow=-1 vhigh=1 +D14 8 1 DESD +D15 3 8 DESD +D17 5 2 DESD +D16 3 5 DESD +D18 5 4 DBIASC +C19 2 4 .55p Rpar=10Meg +D9 4 2 DESD +D19 3 4 DESD +D20 6 2 DESD +D21 3 6 DESD +C6 6 3 500f +R2 1 3 55k +.model SVCCP SW(level=2 Ron=50 Roff=1Meg Vt=.5 Vh=-.2 ilimit=1.52m) +.model SVDDP SW(level=2 Ron=10 Roff=1Meg vt=.5 vh=-.2 ilimit=1.86m) +.model SVDDP2 SW(Ron=3.75k Roff=1Meg vt=.5 vh=-.2) +.model DBURNSD D(Ron=100 Roff=1Meg vfwd=1.6 epsilon=500m ilimit=274u) +.model DVGAIN D(Ron=100k Roff=500k vfwd=15m epsilon=15m vrev=15m revepsilon=15m) +.model DBURNSD2 D(Ron=1k Roff=1Meg vfwd=750m epsilon=500m ilimit=129u) +.model SW1p25 SW(Ron=100 Roff=1g vt=-1.2515 vh=-10m) +.model SHYOFF SW(Ron=1 Roff=2k vt=1.65 vh=-100m) +.model DBLE D(Ron=34k Roff=1Meg vfwd=1.3 epsilon=100m) +.model SoffN SW(level=2 Ron=10k Roff=100Meg vt=-.2 vh=-.2 ) +.model SoffP SW(level=2 Ron=10k Roff=100Meg vt=-.2 vh=-.2 ) +.model DLAT D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9) +.model NI VDMOS(Vto=600m kp=12m mtriode= 3 lambda=.1 Rs=8) +.model PI VDMOS(Vto=-600m Kp=24m mtriode=1.9 lambda=.08 pchan) +.model DBIASF D(Ron=300k Roff=1G vfwd=1.3 epsilon=200m ilimit=.33u ) +.model DBIASR D(Ron=100k Roff=1G vfwd=1 epsilon=200m ilimit=1.2u ) +.model SOFF SW(Ron=1 Roff=100Meg vt=0 vh=-.2) +.model DESD D(Ron=100 Roff=1G vfwd=650m epsilon=500m) +.model DBIASC D(Ron=1k Roff=100Meg Ron=57k vfwd=10u vrev=10u epsilon=10u revepsilon=10u ilimit=.8u revilimit=.8u) +.ends LTC6752-2 +* +.subckt LTC6752-3 1 2 3 4 5 6 7 8 9 +B1 0 N003 I=10u*dnlim(uplim(V(4),V(2)+.15,.1), V(3)-.2 ,.1)+1n*V(4) +B2 N003 0 I=10u*dnlim(uplim(V(5),V(2)+.15,.1), V(3)-.21, .1)+1n*V(5) +C1 N003 0 1f Rpar=1Meg +D5 0 VDH DLAT +C4 5 3 .55p +C10 4 3 .55p +M3 9 N0 3 3 NI temp=27 +M4 9 P0 1 1 PI temp=27 +C7 1 9 1p +C8 9 3 1p +C5 2 5 .55p Rpar=10Meg +R3 2 6 350k +A6 N007 0 N008 0 0 0 VDH 0 OTA g=500u linear Vlow=-1e308 Vhigh=1e308 +D6 0 N007 DLAT +C3 N007 0 1p +G1 0 N007 0 VDH 500µ +R4 N005 7 20k +A8 7 3 0 0 0 N002 0 0 SCHMITT vt=.3 vh=0 trise=7.2n tfall=6n +S5 N005 2 3 N005 SW1p25 +C11 VH 0 1p Rpar=2k +B3 0 N003 I=5u*V(VH)*tanh(V(VDH)/1m) +G4 0 VH 7 3 Table(750m 47u 917m 25u 1 15u 1.06 10u 1.08 8.5u 1.167 5.2u 1.227 5u 1.47 0) +S6 0 VH 7 3 SHYOFF +C9 1 P0 4.9f Rpar=1Meg +S1 N0 3 0 ON SoffN +S7 1 P0 0 ON SoffP +G2 N0 3 N0 Vmax 10m vto=0 dir=1 +G3 1 P0 Vmin P0 10m vto=0 dir=1 +C2 N0 3 5f Rpar=1Meg +B4 P0 3 I=uplim(12u*(V(VDH)+90m),1.2u* (.234*V(Vmin,3)+.88) *V(VILIM) ,1u)*(.5+.5*tanh(V(1,P0)/100m)) +B5 1 N0 I=uplim(15u*(90m-V(VDH)),1u*(1+.2*V(Vmax,1))*V(VILIMF),1u)*(.5+.5*tanh(V(N0,3)/100m)) +C12 VILIM 0 100p Rpar=1k +G5 0 VILIM 1 3 table(1.6 6.5m 1.8 6m 2 6.2m 2.4 8m 2.6 8m 3.2 9m 3.6 9m) +D1 N003 0 DVGAIN +C13 VILIMF 0 100p Rpar=1k +G6 0 VILIMF 1 3 table(1.6 6m 1.8 6.8m 2 7.9m 2.2 9m 2.4 10m 3.0 11m 3.6 10m) +D3 7 3 DBLE +D2 2 5 DBIASR +D4 5 3 DBIASF +S2 3 2 ON 0 SVCCP +D7 2 4 DBIASR +D8 4 3 DBIASF +C14 N005 3 1p Rpar=100k +A5 N002 0 0 0 0 0 N008 0 BUF trise=2n tfall=2n +A4 1 2 1 1 1 1 Vmax 1 OTA g=550u iout=550u Rout=1k Cout=10p vlow=0 vhigh=1e308 +A3 2 3 3 3 3 3 Vmin 3 OTA g=400u iout=500u ref=5 Rout=1k Cout=10p vlow=0 vhigh=1e308 +M1 8 N0B 3 3 NI temp=27 +M2 8 P0B 1 1 PI temp=27 +C15 1 8 1p +C16 8 3 1p +C17 1 P0B 4.9f Rpar=1Meg +S3 N0B 3 0 ON SoffN +S4 1 P0B 0 ON SoffP +G7 N0B 3 N0B Vmax 10m vto=0 dir=1 +G8 1 P0B Vmin P0B 10m vto=0 dir=1 +C18 N0B 3 5f Rpar=1Meg +B6 P0B 3 I=uplim(12u*(90m-V(VDH)),1.2u* (.234*V(Vmin,3)+.88) *V(VILIM) ,1u)*(.5+.5*tanh(V(1,P0B)/100m)) +B7 1 N0B I=uplim(15u*(V(VDH)+90m),1u*(1+.2*V(Vmax,1))*V(VILIMF),1u)*(.5+.5*tanh(V(N0B,3)/100m)) +D10 2 3 DBURNSD +R1 2 3 28.8k +D11 1 3 DBURNSD2 +S8 3 1 ON 0 SVDDP +S9 3 1 ON 0 SVDDP2 +A2 0 N003 0 0 0 0 VDH 0 OTA g=1.8m iout=100u Cout=40f Vlow=-1e308 Vhigh=1e308 +S10 0 VDH 0 ON SOFF +A1 3 6 0 0 0 0 ON 0 OTA g=21u iout=7u ref=-.9 Rout=200k Cout=750f vlow=-1 vhigh=1 +D12 3 8 DESD +D13 8 1 DESD +D14 9 1 DESD +D15 3 9 DESD +D17 5 2 DESD +D16 3 5 DESD +D18 5 4 DBIASC +C19 2 4 .55p Rpar=10Meg +D9 4 2 DESD +D19 3 4 DESD +D20 6 2 DESD +D21 3 6 DESD +C6 6 3 500f +.model SVCCP SW(level=2 Ron=50 Roff=1Meg Vt=.5 Vh=-.2 ilimit=1.52m) +.model SVDDP SW(level=2 Ron=10 Roff=1Meg vt=.5 vh=-.2 ilimit=1.66m) +.model SVDDP2 SW(Ron=1.15k Roff=1Meg vt=.5 vh=-.2) +.model DBURNSD D(Ron=100 Roff=1Meg vfwd=1.6 epsilon=500m ilimit=274u) +.model DVGAIN D(Ron=100k Roff=500k vfwd=15m epsilon=15m vrev=15m revepsilon=15m) +.model DBURNSD2 D(Ron=4.2k Roff=1Meg vfwd=750m epsilon=500m ilimit=300u) +.model SW1p25 SW(Ron=100 Roff=1g vt=-1.2515 vh=-10m) +.model SHYOFF SW(Ron=1 Roff=2k vt=1.65 vh=-100m) +.model DBLE D(Ron=34k Roff=1Meg vfwd=1.3 epsilon=100m) +.model SoffN SW(level=2 Ron=10k Roff=100Meg vt=-.2 vh=-.2 ) +.model SoffP SW(level=2 Ron=10k Roff=100Meg vt=-.2 vh=-.2 ) +.model DLAT D(Ron=1 Roff=10k Vfwd=1 Vrev=1 epsilon=.9 revepsilon=.9) +.model NI VDMOS(Vto=600m kp=12m mtriode= 3 lambda=.1 Rs=8) +.model PI VDMOS(Vto=-600m Kp=24m mtriode=1.9 lambda=.08 pchan) +.model DBIASF D(Ron=300k Roff=1G vfwd=1.3 epsilon=200m ilimit=.33u ) +.model DBIASR D(Ron=100k Roff=1G vfwd=1 epsilon=200m ilimit=1.2u ) +.model SOFF SW(Ron=1 Roff=100Meg vt=0 vh=-.2) +.model DESD D(Ron=100 Roff=1G vfwd=650m epsilon=500m) +.model DBIASC D(Ron=1k Roff=100Meg Ron=57k vfwd=10u vrev=10u epsilon=10u revepsilon=10u ilimit=.8u revilimit=.8u) +.ends LTC6752-3 +* +.subckt LT6275 1 2 3 4 5 +A1 2 1 0 0 0 0 0 0 OTA g=0 in=484f ink=67 +C2 2 1 400f Rser=150 Rpar=20Meg noiseless +B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.5,.1), V(4)+1.7, .1)+1n*V(1) +B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.49,.1), V(4)+1.69, .1)+1n*V(2) +C10 N004 0 6f Rpar=100K noiseless +C13 N005 5 3p Rser=2k noiseless +C6 3 1 1.5p Rpar=1.4G Rser=500 noiseless +G2 0 XX N007 0 1µ +D5 N007 0 DNLSlew1 +M1 N006 N005 N008 N008 N temp=27 +M2 N011 N005 N008 N008 P temp=27 +C4 3 N008 500f +C5 N008 4 500f +C8 3 N005 1.2p Rpar=100Meg noiseless +C11 N005 4 1.2p Rpar=100Meg noiseless +G4 XX 0 N005 3 100µ vto=-1.055 dir=1 +G5 0 XX 4 N005 100µ vto=-1.055 dir=1 +R1 5 N008 8 noiseless +S1 4 N005 N005 5 Soutfb +S2 N005 3 5 N005 Soutfb +D1 N007 0 DNLSlew2 +C19 N005 5 25p Rser=8k noiseless +C12 3 5 500f +C18 5 4 500f +C20 N005 5 1p Rser=10k noiseless +B3 3 N005 I=dnlim(632u*V(XX),100u,50u) +B4 N005 4 I=-632u*V(XX)+dnlim(632u*V(XX),100u,50u) +C7 3 2 1.5p Rpar=1.4G Rser=500 noiseless +C1 1 4 1.5p Rpar=1.4G Rser=500 noiseless +C9 2 4 1.5p Rpar=1.4G Rser=500 noiseless +D2 3 N006 DN +D4 N011 4 DP +A2 0 N004 0 0 0 0 N007 0 OTA g=1m linear en=9.76n enk=45 Rout=2.4k vlow=-1e308 vhigh=1e308 +C3 N007 N010 120f +A3 N007 0 0 0 0 0 N010 0 OTA g=1 iout=200m Rout=20 vlow=-1e308 vhigh=1e308 +R2 XX 0 1Meg noiseless +C14 3 4 10p Rpar=215K noiseless +A4 3 N006 3 3 3 3 N005 3 OTA g=108n iout=1u vlow=-1e308 vhigh=1e308 +A5 4 N011 4 4 4 4 N005 4 OTA g=72n iout=1u vlow=-1e308 vhigh=1e308 +D3 N007 0 DNLSlew3 +.model N VDMOS(Vto=-55m Kp=900m noiseless) +.model P VDMOS(Vto=55m Kp=900m pchan noiseless +.model DLS D(Ron=10 Roff=100Meg vfwd=200m epsilon=100m vrev=200m revepsilon=100m noiseless) +.model DN D(Roff=60 Ron=60 ilimit=90m noiseless) +.model DP D(Roff=90 Ron=90 ilimit=90m noiseless) +.model Soutfb SW(level=2 Ron=15M Roff=100G vt=710m vh=-100m ilimit=400u noiseless) +.model DNLSlew1 d(ron=4.33k roff=4.33k vfwd=0 vrev=0 ilimit=700u revilimit=700u noiseless) +.model DNLSlew2 d(ron=2.84k roff=2.84k vfwd=0 vrev=0 revilimit=1m noiseless) +.model DNLSlew3 d(ron=100 roff=50k vfwd=8.2 vrev=10 epsilon=200m revepsilon=200m noiseless) +.ends LT6275 +* +.subckt LTC6561 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +C6 MID1 0 900f Rpar=1k noiseless +B2 0 MID1 I=1m*(V(ch1_st1_out,8)-1.70086)*(.5+.5*tanh((V(ch1_on)-.5)/10m)) +C14 6 8 1p Rpar=1.4K noiseless +C15 2 8 1.5p Rpar=29k noiseless +A8 2 8 0 0 0 _Chsel0 Chsel0 0 SCHMITT vt=1.15 vh=350m trise=5n +A5 _Chsel0 0 _Chsel1 0 _HiZ 0 ch1_on 0 AND trise=1n +A9 Chsel0 0 _Chsel1 0 _HiZ 0 ch2_on 0 AND trise=1n +A10 _Chsel0 0 Chsel1 0 _HiZ 0 ch3_on 0 AND trise=1n +A11 Chsel0 0 Chsel1 0 _HiZ 0 ch4_on 0 AND trise=1n +C26 7 8 1p Rpar=1.4K noiseless +R2 ch1_st1_out 9 7.86K +C30 N004 9 440f +C31 3 N004 6p Rser=15 Rpar=29.5 noiseless +G7 0 X1 3 N004 1m +C32 X1 0 12f Rpar=30.3k noiseless +A13 0 N005 PowOK 8 8 8 N004 8 OTA g=28m asym ref=-79.1m isource=1u isink=-4.4m in=1p/(1+freq/300Meg) vlow=0 vhigh=1e308 +G8 0 N005 4 9 1m +C33 N005 0 30f Rpar=1k noiseless +C34 9 8 400f Rser=1.75k Rpar=1Meg noiseless +D4 9 8 Din +C36 4 8 1p Rpar=1.4K noiseless +C46 5 8 1p Rpar=1.4K noiseless +B9 0 MID1 I=1m*(V(ch2_st1_out,8)-1.70086)*(.5+.5*tanh((V(ch2_on)-.5)/10m)) +B10 0 MID1 I=1m*(V(ch3_st1_out,8)-1.70086)*(.5+.5*tanh((V(ch3_on)-.5)/10m)) +B11 0 MID1 I=1m*(V(ch4_st1_out,8)-1.70086)*(.5+.5*tanh((V(ch4_on)-.5)/10m)) +B12 8 PowOK I= uplim(dnlim(400n*V(3,8)-.71u,0,10n)+dnlim(10n*V(3,8),0,10n),1u,10n) +C50 PowOK 8 1p Rpar=1Meg noiseless +B14 8 4 I=1.057148m*dnlim(uplim(.8*(V(3,8)-.8),.25,100m)+uplim(.235*(V(3,8)-1),.75,10m),0,.1)+uplim(dnlim(30u*V(3,8),0,1u),50u,1u) +C52 1 8 5p +C53 3 8 5p Rpar=3k noiseless +A14 0 N004 0 0 0 0 0 0 OTA in=12.5p +A2 0 9 0 0 0 0 0 0 OTA in= 4.9p/dnlim((freq/1e6)**.12,.5,.1) +800f*(1+freq/600Meg) +C3 N010 10 440f +C5 3 N010 6p Rser=15 Rpar=29.5 noiseless +G2 0 X2 3 N010 1m +C7 X2 0 12f Rpar=30.3k noiseless +G3 0 N011 5 10 1m +C8 N011 0 30f Rpar=1k noiseless +C9 10 8 400f Rser=1.75k Rpar=1Meg noiseless +D1 10 8 Din +C12 N017 11 440f +C13 3 N017 6p Rser=15 Rpar=29.5 noiseless +G4 0 X3 3 N017 1m +C17 X3 0 12f Rpar=30.3k noiseless +G5 0 N019 6 11 1m +C18 N019 0 30f Rpar=1k noiseless +C19 11 8 400f Rser=1.75k Rpar=1Meg noiseless +D3 11 8 Din +C23 N024 12 440f +C24 3 N024 6p Rser=15 Rpar=29.5 noiseless +G6 0 X4 3 N024 1m +C25 X4 0 12f Rpar=30.3k noiseless +G9 0 N026 7 12 1m +C29 N026 0 30f Rpar=1k noiseless +C35 12 8 400f Rser=1.75k Rpar=1Meg noiseless +D5 12 8 Din +D10 1 8 Dleak1 +B16 3 8 I=uplim(5m*MAX(V(3,8)-1.5,0)**1.5,20m,1m) +D6 3 8 Dleak0 +G14 0 MID1BUF MID1 0 1 +R12 MID1BUF 0 10 noiseless +D8 MID1BUF MID1DECAY DSAT +C44 MID1DECAY 0 1p Rpar=100k noiseless +S1 MID1DECAY N016 0 Sat SSAT2 +C45 GainLoss 0 1p Rpar=1k noiseless +B23 0 GainLoss0 I=1m*uplim(dnlim(250m*(.1*dnlim(V(MID1BUF),V(MID1DECAY),.1)-111m),0,10m),700m,10m) +G1 0 GainLoss GainLoss0 0 1m +I1 N016 0 200m +C51 N016 0 10p Rpar=10 noiseless +B28 0 GainlossM1 I=1u*dnlim(V(GainLoss0,GainLoss),0,100u) +C55 mid_out 0 300f Rpar=1k noiseless +S3 0 GainLoss0 0 MID1 SGLLin +B19 0 Sat I=1m*dnlim(V(MID1)-100m,0,10m) +C4 Sat 0 2.5p Rpar=1k noiseless +I2 0 N015 200m +C43 N015 0 10p Rpar=10 noiseless +S4 N015 MID1DECAY 0 Sat SSAT1 +C42 GainLoss0 0 100f Rpar=1k noiseless +R11 OutPreBuf 8 1Meg noiseless +D9 15 8 DI0 +M3 1 N021 15 15 NOUT temp=27 +C61 1 N021 10f Rpar=20Meg noiseless +C62 N021 8 10f Rpar=20Meg noiseless +S5 1 N021 15 N021 SlimOL +D11 N021 15 DCL +C63 16 8 100f noiseless +R13 15 16 50 +A19 15 OutPreBuf PowOK 8 8 8 N021 8 OTA g=100u iout=1m vlow=0 vhigh=5 +C1 GainlossM1 0 12f Rpar=2Meg Rser=10k noiseless +B3 0 GainlossM0 I=1m*dnlim(V(GainLoss0,GainLoss),0,100u) +C41 GainlossM0 0 100f Rpar=1k noiseless +G15 0 N008 mid_out 0 100m +R7 N008 0 100 noiseless +C54 N008 SlimSensA 1p +R8 SlimSensA 0 100 noiseless +C57 slewfac 0 1p Rpar=1k noiseless +B18 0 slewfac I=3m+2m*tanh((V(mid1)-1)/400m) +B17 0 mid_out I=dnlim(5m*uplim(.1*dnlim(V(MID1BUF),V(MID1DECAY),.1)-dnlim(.95*(.1*dnlim(V(MID1BUF),V(MID1DECAY),.1)-200m),0,20m),200m,30m)*(.5+.5*tanh((400m-V(SlimSensA))/10m)),-100u,10u) +S2 GainlossM1 0 0 mid_out SGLKILL +G16 mid_out 0 GainlossM1 0 2m +R1 ch2_st1_out 10 7.86K +R4 ch3_st1_out 11 7.86K +R5 ch4_st1_out 12 7.86K +B1 8 5 I=1.057148m*dnlim(uplim(.8*(V(3,8)-.8),.25,100m)+uplim(.235*(V(3,8)-1),.75,10m),0,.1)+uplim(dnlim(30u*V(3,8),0,1u),50u,1u) +B13 8 6 I=1.057148m*dnlim(uplim(.8*(V(3,8)-.8),.25,100m)+uplim(.235*(V(3,8)-1),.75,10m),0,.1)+uplim(dnlim(30u*V(3,8),0,1u),50u,1u) +B15 8 7 I=1.057148m*dnlim(uplim(.8*(V(3,8)-.8),.25,100m)+uplim(.235*(V(3,8)-1),.75,10m),0,.1)+uplim(dnlim(30u*V(3,8),0,1u),50u,1u) +C59 8 ch1_st1_out 10f Rpar=2k noiseless +D2 8 N007 DSUB +R9 9 N007 10 noiseless +C39 Inode1 0 10p Rpar=100 noiseless +G13 0 Inode1 9 N007 100m +I6 Inode1 0 10µ +C58 N007 8 10f +B21 9 8 I=dnlim(45m*V(Inode1),0,5u) +C2 8 ch2_st1_out 10f Rpar=2k noiseless +B20 10 8 I=dnlim(45m*V(Inode2),0,5u) +B22 11 8 I=dnlim(45m*V(Inode3),0,5u) +B24 12 8 I=dnlim(45m*V(Inode4),0,5u) +C10 8 ch3_st1_out 10f Rpar=2k noiseless +C20 8 ch4_st1_out 10f Rpar=2k noiseless +D7 8 N013 DSUB +R3 10 N013 10 noiseless +C40 Inode2 0 10p Rpar=100 noiseless +G10 0 Inode2 10 N013 100m +I3 Inode2 0 10µ +C56 N013 8 10f +D13 8 N020 DSUB +R10 11 N020 10 noiseless +C60 Inode3 0 10p Rpar=100 noiseless +G17 0 Inode3 11 N020 100m +I8 Inode3 0 10µ +C64 N020 8 10f +D14 8 N028 DSUB +R14 12 N028 10 noiseless +C65 Inode4 0 10p Rpar=100 noiseless +G18 0 Inode4 12 N028 100m +I10 Inode4 0 10µ +C66 N028 8 10f +C16 14 8 1.5p Rpar=29k noiseless +C49 13 8 1.5p Rpar=29k noiseless +A4 14 8 0 0 0 _Chsel1 Chsel1 0 SCHMITT vt=1.15 vh=350m trise=5n +A20 13 8 0 0 0 _HiZ HiZ 0 SCHMITT vt=1.15 vh=350m trise=10n +G19 8 OutPreBuf PowOK 8 .6µ +B5 8 OutPreBuf I=(.5+.5*tanh((V(_Hiz)-.5)/100m ))*1u*uplim(.5 + 2*V(mid_out) + 2*V(glitch2),2.5,50m) +A1 0 N011 PowOK 8 8 8 N010 8 OTA g=28m asym ref=-79.1m isource=1u isink=-4.4m in=1p/(1+freq/300Meg) vlow=0 vhigh=1e308 +A3 0 N019 PowOK 8 8 8 N017 8 OTA g=28m asym ref=-79.1m isource=1u isink=-4.4m in=1p/(1+freq/300Meg) vlow=0 vhigh=1e308 +A12 0 N026 PowOK 8 8 8 N024 8 OTA g=28m asym ref=-79.1m isource=1u isink=-4.4m in=1p/(1+freq/300Meg) vlow=0 vhigh=1e308 +B7 3 ch1_st1_out I=(.5+.5*tanh((V(3,ch1_st1_out)/10m)))*(468.7u+2.2313m*V(ch1_on)-1m*V(X1))*V(PowOK,8) +B4 3 ch2_st1_out I=(.5+.5*tanh((V(3,ch2_st1_out)/10m)))*(468.7u+2.2313m*V(ch2_on)-1m*V(X2))*V(PowOK,8) +B6 3 ch3_st1_out I=(.5+.5*tanh((V(3,ch3_st1_out)/10m)))*(468.7u+2.2313m*V(ch3_on)-1m*V(X3))*V(PowOK,8) +B8 3 ch4_st1_out I=(.5+.5*tanh((V(3,ch4_st1_out)/10m)))*(468.7u+2.2313m*V(ch4_on)-1m*V(X4))*V(PowOK,8) +D15 GainlossM0 GainlossM1 DGLSPD +C67 15 8 100f Rpar=1Meg noiseless +A25 0 0 hiztran 0 N030 0 glitch_OMUX 0 DFLOP trise=3n tfall=1n +G20 0 glitch2 glitch_OMUX 0 1µ +C68 glitch2 0 1f Rpar=1Meg Rser=500k noiseless +R6 chsw 0 1K +A26 0 0 chsw 0 N032 0 swglitch 0 DFLOP trise=3n tfall=1n +A27 swglitch 0 0 0 0 0 N032 0 BUF trise=25n +R17 hiztran 0 1K +A28 glitch_OMUX 0 0 0 0 0 N030 0 BUF trise=10n +G21 0 MID1 swglitch 0 1m +A6 0 N010 0 0 0 0 0 0 OTA in=12.5p +A15 0 N017 0 0 0 0 0 0 OTA in=12.5p +A17 0 N024 0 0 0 0 0 0 OTA in=12.5p +A7 0 10 0 0 0 0 0 0 OTA in= 4.9p/dnlim((freq/1e6)**.12,.5,.1) +800f*(1+freq/600Meg) +A16 0 11 0 0 0 0 0 0 OTA in= 4.9p/dnlim((freq/1e6)**.12,.5,.1) +800f*(1+freq/600Meg) +A18 0 12 0 0 0 0 0 0 OTA in= 4.9p/dnlim((freq/1e6)**.12,.5,.1) +800f*(1+freq/600Meg) +.model Din D(Roff=1G Ron=8k vfwd=1.1 epsilon=700m noiseless) +.model Dleak0 D(ron=1k Roff=100k vfwd=4 epsilon=200m noiseless) +.model Dleak1 D(ron=100 Roff=1Meg vfwd=2.5 epsilon=200m ilimit=500u revilimit=100u noiseless) +.model DSUB D(IS=1e-16 TT=100n noiseless) +.model DSAT D(Ron=100 Roff=1G vfwd=200m epsilon=200m noiseless) +.model SSAT1 SW(level=2 Ron=20, Roff=1Meg, vt=-.5 vh=-.2 ilimit=50m oneway epsilon=100m noiseless) +.model SSAT2 SW(level=2 Ron=100, Roff=1Meg, vt=-.5 vh=-.2 ilimit=5m noiseless) +.model SGLLin SW(Ron=100 Roff=10Meg vt=-225m vh=-30m noiseless) +.model DI0 D(Ron=100 Roff=1Meg vfwd=0 epsilon=300m ilimit=420u noiseless) +.model SlimOL SW(Ron=100k Roff=400Meg vt=0 vh=-100m noiseless) +.model DCL D(Ron=1k Roff=1G vfwd=1.88 epsilon=20m noiseless) +.model DGLSPD D(Ron=100 Roff=10Meg vfwd=20m epsilon=50m noiseless) +.model SGLKILL SW(Ron=1 Roff=2Meg vt=-100m vh=-50m noiseless) +.model NOUT VDMOS(Vto=1 Kp=100m noiseless) +.machine +.state notrans 0 +.state trans 1 +.rule * notrans ( V(Chsel0) > .9 | V(Chsel0) < .1) & ( V(Chsel1) > .9 | V(Chsel1) < .1 ) +.rule notrans trans ( V(Chsel0) < .8 & V(Chsel0) > .2) | ( V(Chsel1) < .8 & V(Chsel1) > .2) +.output (chsw) state +.endmachine +.machine +.state notrans 0 +.state trans 1 +.rule * notrans V(Hiz) > .9 | V(Hiz) < .1 +.rule notrans trans V(Hiz) < .8 & V(Hiz) > .2 +.output (hiztran) state +.endmachine +.ends LTC6561 diff --git a/spice/copy/sub/LTC7000-1.sub b/spice/copy/sub/LTC7000-1.sub new file mode 100755 index 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All rights reserved. +* +.subckt LTZ1000 1 2 3 4 5 6 7 8 +Q1 5 N003 7 0 N temp=27 +D1 4 N001 Z temp=27 +D2 4 1 S +D3 4 2 S +D4 2 1 S m=10m +R1 1 2 300 noiseless +C1 1 4 1p +C2 2 4 1p +C3 3 4 1p +C4 5 4 1p +C5 6 4 1p +C6 7 4 1p +C7 8 4 1p +C8 T1 CASE 6µ Rpar=10Meg +R2 CASE 0 300.15K tc={1/(273.15+27)} +I1 0 CASE 1m +Q2 8 N002 7 0 N temp=27 +B1 4 N003 I=270u*(V(T1)-300.15) Rpar=5 +B2 6 N002 I=270u*(V(T1)-300.15) Rpar=5 +B4 CASE T1 I=57n*V(1,2)**2 +A1 0 T2 N001 N001 N001 N001 3 N001 OTA en=14u+440n/(300u+I(D1)**2) G=.1375m Rout=20 Cout=.1u Ref=-333 Iout=100m Vhigh=.5 Vlow=-.5 epsilon=1 +G1 CASE T2 T1 CASE 10µ +C10 T2 CASE 1n Rpar={100K+245} +B3 T2 CASE I=100p*(V(case)-280)**2 +.model N NPN(Is=8.5e-14 Bf=300 Cjc=4p Cje=8p noiseless) +.model S D(Ron=2 Vfwd=.55 epsilon=.5 noiseless) +.model Z D(Is=1e-14 Cjo=100p BV=6.4 Ibv=1m Kf=3e-14) +.ends LTZ1000 +* +.subckt LTZ1000A 1 2 3 4 5 6 7 8 +Q1 5 N004 7 0 N temp=27 +D1 4 N001 Z temp=27 +D2 4 1 S +D3 4 2 S +D4 2 1 S m=10m +R1 1 2 300 noiseless +C1 1 4 1p +C2 2 4 1p +C3 3 4 1p +C4 5 4 1p +C5 6 4 1p +C6 7 4 1p +C7 8 4 1p +R2 CASE 0 300.15K tc={1/(273.15+27)} +I1 0 CASE 1m +Q2 8 N003 7 0 N temp=27 +B1 4 N004 I=270u*(V(T1)-300.15) Rpar=5 +B2 6 N003 I=270u*(V(T1)-300.15) Rpar=5 +A1 0 T1 N001 N001 N001 N001 3 N001 OTA en=14u+440n/(300u+I(D1)**2) G=.1375m Rout=20 Cout=.1u Ref=-333 Iout=100m Vhigh=.5 Vlow=-.5 epsilon=1 +C9 T1 N002 10µ Rpar=10Meg +C10 N002 N005 .1µ Rpar=10Meg +B3 N002 T1 I=46n*V(1,2)**2 +B5 N005 N002 I=46n*V(1,2)**2 +C8 N005 CASE .025µ Rpar=10Meg +B4 CASE N005 I=46n*V(1,2)**2 +.model N NPN(Is=8.5e-14 Bf=300 Cjc=4p Cje=8p noiseless) +.model S D(Ron=2 Vfwd=.55 epsilon=.5 noiseless) +.model Z D(Is=1e-14 Cjo=100p BV=6.4 Ibv=1m Kf=3e-14) +.ends LTZ1000A diff --git a/spice/copy/sub/MOC205.sub b/spice/copy/sub/MOC205.sub new file mode 100755 index 0000000..84d0f10 --- /dev/null +++ b/spice/copy/sub/MOC205.sub @@ -0,0 +1,11 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000. All rights reserved. +* +.subckt MOC205 1 2 3 4 5 +R1 N003 2 2 +D1 1 N003 LD +G1 3 5 N003 2 {Igain} +C1 1 2 18p +Q1 3 5 4 [4] NP +.model LD D(Is=1e-20 Cjo=18p) +.model NP NPN(Bf=610 Vaf=140 Ikf=15m Rc=1 Cjc=19p Cje=7p Cjs=7p C2=1e-15) +.ends MOC205 diff --git a/spice/copy/sub/NE555.sub b/spice/copy/sub/NE555.sub new file mode 100755 index 0000000..39a7d53 --- /dev/null +++ b/spice/copy/sub/NE555.sub @@ -0,0 +1,26 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2008. All rights reserved. +* +.subckt NE555 1 2 3 4 5 6 7 8 +A1 N001 2 1 1 1 1 N003 1 SCHMITT Vt=0 Vh=1m +R1 N001 1 5K +R2 5 N001 5K +R3 8 5 5K +S1 1 7 N007 1 D +A2 N011 N003 1 1 1 1 N008 1 SRFLOP Trise=100n tripdt=10n +A3 6 5 1 1 1 1 N012 1 SCHMITT Vt=0 Vh=1m +S2 8 3 N009 1 O +S3 3 1 1 N009 O +A6 1 N006 1 N008 1 1 N007 1 OR Ref=.5 Vlow=-1 Trise=100n +R7 8 1 4K +R9 2 1 1G +R10 6 1 1G +A4 1 N008 1 N006 1 N009 1 1 OR ref=.5 Vlow=-1 Trise=100n +A5 4 1 1 1 1 N006 1 1 SCHMITT Vt=.7 Vh=1m +D1 4 1 DR +A7 1 N006 1 N012 1 1 N011 1 OR +D2 8 4 400uA +.model DR D(Ron=150K Roff=1T Vfwd=1.6) +.model O SW(Ron=6 Roff=1Meg Vt=0 Vh=-.8) +.model D SW(Ron=6 Roff=.75G Vt=.5 Vh=-.4) +.model 400uA D(Ron=1K Ilimit=400u epsilon=.5) +.ends NE555 diff --git a/spice/copy/sub/PC817.sub b/spice/copy/sub/PC817.sub new file mode 100755 index 0000000..c3795bd --- /dev/null +++ b/spice/copy/sub/PC817.sub @@ -0,0 +1,11 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000. All rights reserved. +* +.subckt PC817 1 2 3 4 +R1 N003 2 2 +D1 1 N003 LD +G1 3 N004 N003 2 {Igain} +C1 1 2 18p +Q1 3 N004 4 [4] NP +.model LD D(Is=1e-20 Cjo=18p) +.model NP NPN(Bf=1200 Vaf=140 Ikf=100m Rc=1 Cjc=19p Cje=7p Cjs=7p C2=3e-15) +.ends PC817 diff --git a/spice/copy/sub/SOAtherm-HeatSink.lib b/spice/copy/sub/SOAtherm-HeatSink.lib new file mode 100755 index 0000000..21bb554 --- /dev/null +++ b/spice/copy/sub/SOAtherm-HeatSink.lib @@ -0,0 +1,88 @@ +* Copyright (c) 2016 Linear Technology Corporation. All rights reserved. +* Author: Dan Eddleman +* +*SOAtherm Heat Sink Model +*************************************************************** + +.subckt copper Tc Tinterface Tfin +R_theta Tfin Ambient {Rtheta} +V1 Ambient 0 {Tambient} +R_interface Tinterface Tc {Rinterface} +*O§HeatSink Tinterface 0 Tfin 0 Copper +.param depth_mm={Volume_mm3/Area_Contact_mm2} +.param r_per_mm={2.5/Area_Contact_mm2} +.param c_per_mm={400*8.96e-6*Area_Contact_mm2} +.param depth0=depth_mm/pow(2,10) +.param depth1=depth0*2 +.param depth2=depth1*2 +.param depth3=depth2*2 +.param depth4=depth3*2 +.param depth5=depth4*2 +.param depth6=depth5*2 +.param depth7=depth6*2 +.param depth8=depth7*2 +.param depth9=depth8*2+depth0 +r0 Tinterface n0 {r_per_mm*depth0} +c0 n0 0 {c_per_mm*depth0} +r1 n0 n1 {r_per_mm*depth1} +c1 n1 0 {c_per_mm*depth1} +r2 n1 n2 {r_per_mm*depth2} +c2 n2 0 {c_per_mm*depth2} +r3 n2 n3 {r_per_mm*depth3} +c3 n3 0 {c_per_mm*depth3} +r4 n3 n4 {r_per_mm*depth4} +c4 n4 0 {c_per_mm*depth4} +r5 n4 n5 {r_per_mm*depth5} +c5 n5 0 {c_per_mm*depth5} +r6 n5 n6 {r_per_mm*depth6} +c6 n6 0 {c_per_mm*depth6} +r7 n6 n7 {r_per_mm*depth7} +c7 n7 0 {c_per_mm*depth7} +r8 n7 n8 {r_per_mm*depth8} +c8 n8 0 {c_per_mm*depth8} +r9 n8 Tfin {r_per_mm*depth9} +c9 Tfin 0 {c_per_mm*depth9} + +.param Tambient=85 Depth_mm=10 Area_Contact_mm2=100 Rtheta=10 Rinterface={100/Area_Contact_mm2} +.ends copper_test + +.subckt aluminum Tc Tinterface Tfin +R_theta Tfin Ambient {Rtheta} +V1 Ambient 0 {Tambient} +R_interface Tinterface Tc {Rinterface} +.param depth_mm={Volume_mm3/Area_Contact_mm2} +.param r_per_mm={1/(0.22*Area_Contact_mm2)} +.param c_per_mm={896*2.7e-6*Area_Contact_mm2} +.param depth0=depth_mm/pow(2,10) +.param depth1=depth0*2 +.param depth2=depth1*2 +.param depth3=depth2*2 +.param depth4=depth3*2 +.param depth5=depth4*2 +.param depth6=depth5*2 +.param depth7=depth6*2 +.param depth8=depth7*2 +.param depth9=depth8*2+depth0 +r0 Tinterface n0 {r_per_mm*depth0} +c0 n0 0 {c_per_mm*depth0} +r1 n0 n1 {r_per_mm*depth1} +c1 n1 0 {c_per_mm*depth1} +r2 n1 n2 {r_per_mm*depth2} +c2 n2 0 {c_per_mm*depth2} +r3 n2 n3 {r_per_mm*depth3} +c3 n3 0 {c_per_mm*depth3} +r4 n3 n4 {r_per_mm*depth4} +c4 n4 0 {c_per_mm*depth4} +r5 n4 n5 {r_per_mm*depth5} +c5 n5 0 {c_per_mm*depth5} +r6 n5 n6 {r_per_mm*depth6} +c6 n6 0 {c_per_mm*depth6} +r7 n6 n7 {r_per_mm*depth7} +c7 n7 0 {c_per_mm*depth7} +r8 n7 n8 {r_per_mm*depth8} +c8 n8 0 {c_per_mm*depth8} +r9 n8 Tfin {r_per_mm*depth9} +c9 Tfin 0 {c_per_mm*depth9} + +.param Tambient=85 Depth_mm=10 Area_Contact_mm2=100 Rtheta=10 Rinterface={100/Area_Contact_mm2} +.ends aluminum \ No newline at end of file diff --git a/spice/copy/sub/SOAtherm-PCB.lib b/spice/copy/sub/SOAtherm-PCB.lib new file mode 100755 index 0000000..e0e1017 --- /dev/null +++ b/spice/copy/sub/SOAtherm-PCB.lib @@ -0,0 +1,196 @@ +* Copyright (c) 2016 Linear Technology Corporation. All rights reserved. +* Author: Dan Eddleman +* +*SOAtherm PCB Thermal Model +*************************************************************** + +.subckt TopsideCopper Tcenter + +*****PARAMETERS THAT SHOULD BE OVERRIDDEN BY PASSED VALUES******* +.param Area_Contact_mm2=100 +.param Area_PCB_mm2=10000 +.param Copper_Thickness_oz=1 +.param PCB_FR4_Thickness_mm=1.5 +.param lfm=0 +***************************************************************** + +.param Enable_Radiation=1 + +.param TambientRadiation={Tambient} +.param TambientConvection={Tambient} + +.param Tambient=85 +.param emissivity=0.8 +.param hconv0=1.1625E-5 + +R0 N001 Tcenter {r0} +R1 N002 N001 {r1} +R2 N003 N002 {r2} +R3 N004 N003 {r3} +R4 N005 N004 {r4} +R5 N006 N005 {r5} +R6 N007 N006 {r6} +R7 N008 N007 {r7} +R8 N009 N008 {r8} +R9 Tedge N009 {r9} +C1 N001 0 {c1} +C2 N002 0 {c2} +C3 N003 0 {c3} +C4 N004 0 {c4} +C5 N005 0 {c5} +C6 N006 0 {c6} +C7 N007 0 {c7} +C8 N008 0 {c8} +C9 N009 0 {c9} +C10 Tedge 0 {c10} +C0 Tcenter 0 {c0} +V1 TambientConvection 0 {TambientConvection} +XXtopRad0 TambientRadiation N001 radiation params: Area_mm2=a10 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopRad1 TambientRadiation N002 radiation params: Area_mm2=a21 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopRad2 TambientRadiation N003 radiation params: Area_mm2=a32 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopRad3 TambientRadiation N004 radiation params: Area_mm2=a43 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopRad4 TambientRadiation N005 radiation params: Area_mm2=a54 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopRad5 TambientRadiation N006 radiation params: Area_mm2=a65 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopRad6 TambientRadiation N007 radiation params: Area_mm2=a76 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopRad7 TambientRadiation N008 radiation params: Area_mm2=a87 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopRad8 TambientRadiation N009 radiation params: Area_mm2=a98 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopRad9 TambientRadiation Tedge radiation params: Area_mm2=a109 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXtopConv0 TambientConvection N001 convection params: Area_mm2=a10 lfm={lfm} hconv0={hconv0} +XXtopConv1 TambientConvection N002 convection params: Area_mm2=a21 lfm={lfm} hconv0={hconv0} +XXtopConv2 TambientConvection N003 convection params: Area_mm2=a32 lfm={lfm} hconv0={hconv0} +XXtopConv3 TambientConvection N004 convection params: Area_mm2=a43 lfm={lfm} hconv0={hconv0} +XXtopConv4 TambientConvection N005 convection params: Area_mm2=a54 lfm={lfm} hconv0={hconv0} +XXtopConv5 TambientConvection N006 convection params: Area_mm2=a65 lfm={lfm} hconv0={hconv0} +XXtopConv6 TambientConvection N007 convection params: Area_mm2=a76 lfm={lfm} hconv0={hconv0} +XXtopConv7 TambientConvection N008 convection params: Area_mm2=a87 lfm={lfm} hconv0={hconv0} +XXtopConv8 TambientConvection N009 convection params: Area_mm2=a98 lfm={lfm} hconv0={hconv0} +XXtopConv9 TambientConvection Tedge convection params: Area_mm2=a109 lfm={lfm} hconv0={hconv0} +rFR4_0 N001 N010 {4k*PCB_FR4_Thickness_mm/a10} +rFR4_1 N002 N011 {4k*PCB_FR4_Thickness_mm/a21} +rFR4_2 N003 N012 {4k*PCB_FR4_Thickness_mm/a32} +rFR4_3 N004 N013 {4k*PCB_FR4_Thickness_mm/a43} +rFR4_4 N005 N014 {4k*PCB_FR4_Thickness_mm/a54} +rFR4_5 N006 N015 {4k*PCB_FR4_Thickness_mm/a65} +rFR4_6 N007 N016 {4k*PCB_FR4_Thickness_mm/a76} +rFR4_7 N008 N017 {4k*PCB_FR4_Thickness_mm/a10} +rFR4_8 N009 N018 {4k*PCB_FR4_Thickness_mm/a87} +rFR4_9 Tedge N019 {4k*PCB_FR4_Thickness_mm/a98} +XXbottomRad0 TambientRadiation N010 radiation params: Area_mm2=a10 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomRad1 TambientRadiation N011 radiation params: Area_mm2=a21 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomRad2 TambientRadiation N012 radiation params: Area_mm2=a32 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomRad3 TambientRadiation N013 radiation params: Area_mm2=a43 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomRad4 TambientRadiation N014 radiation params: Area_mm2=a54 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomRad5 TambientRadiation N015 radiation params: Area_mm2=a65 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomRad6 TambientRadiation N016 radiation params: Area_mm2=a76 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomRad7 TambientRadiation N017 radiation params: Area_mm2=a87 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomRad8 TambientRadiation N018 radiation params: Area_mm2=a98 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomRad9 TambientRadiation N019 radiation params: Area_mm2=a109 Enable_Radiation={Enable_Radiation} emissivity={emissivity} +XXbottomConv0 TambientConvection N010 convection params: Area_mm2=a10 lfm={lfm} hconv0={hconv0} +XXbottomConv1 TambientConvection N011 convection params: Area_mm2=a21 lfm={lfm} hconv0={hconv0} +XXbottomConv2 TambientConvection N012 convection params: Area_mm2=a32 lfm={lfm} hconv0={hconv0} +XXbottomConv3 TambientConvection N013 convection params: Area_mm2=a43 lfm={lfm} hconv0={hconv0} +XXbottomConv4 TambientConvection N014 convection params: Area_mm2=a54 lfm={lfm} hconv0={hconv0} +XXbottomConv5 TambientConvection N015 convection params: Area_mm2=a65 lfm={lfm} hconv0={hconv0} +XXbottomConv6 TambientConvection N016 convection params: Area_mm2=a76 lfm={lfm} hconv0={hconv0} +XXbottomConv7 TambientConvection N017 convection params: Area_mm2=a87 lfm={lfm} hconv0={hconv0} +XXbottomConv8 TambientConvection N018 convection params: Area_mm2=a98 lfm={lfm} hconv0={hconv0} +XXbottomConv9 TambientConvection N019 convection params: Area_mm2=a109 lfm={lfm} hconv0={hconv0} +V2 TambientRadiation 0 {TambientRadiation} +C11 N010 0 {c1_FR4} +C12 N011 0 {c2_FR4} +C13 N012 0 {c3_FR4} +C14 N013 0 {c4_FR4} +C15 N014 0 {c5_FR4} +C16 N015 0 {c6_FR4} +C17 N016 0 {c7_FR4} +C18 N017 0 {c8_FR4} +C19 N018 0 {c9_FR4} +C20 N019 0 {c10_FR4} + +.param Rcopper_PCB_per_square=1/(0.391*0.035*Copper_Thickness_oz) +.param Ccopper_PCB_per_mm2=400*8.96E-6*0.035*Copper_Thickness_oz +.param Cfr4_PCB_per_mm2=600*2E-6*PCB_FR4_Thickness_mm + +.param radius0=SQRT(Area_Contact_mm2/pi) +.param radius10=SQRT(Area_PCB_mm2/pi) +.param radius9=radius0+(radius10-radius0)/2 +.param radius8=radius0+(radius9-radius0)/2 +.param radius7=radius0+(radius8-radius0)/2 +.param radius6=radius0+(radius7-radius0)/2 +.param radius5=radius0+(radius6-radius0)/2 +.param radius4=radius0+(radius5-radius0)/2 +.param radius3=radius0+(radius4-radius0)/2 +.param radius2=radius0+(radius3-radius0)/2 +.param radius1=radius0+(radius2-radius0)/2 + +.func Area(radius_outer,radius_inner) {pi*pow(radius_outer,2)-pi*pow(radius_inner,2)} +.param a0=Area(radius0,0) +.param a10=Area(radius1,radius0) +.param a21=Area(radius2,radius1) +.param a32=Area(radius3,radius2) +.param a43=Area(radius4,radius3) +.param a54=Area(radius5,radius4) +.param a65=Area(radius6,radius5) +.param a76=Area(radius7,radius6) +.param a87=Area(radius8,radius7) +.param a98=Area(radius9,radius8) +.param a109=Area(radius10,radius9) + +.param c0=Ccopper_PCB_per_mm2*a0 +.param c1=Ccopper_PCB_per_mm2*a10 +.param c2=Ccopper_PCB_per_mm2*a21 +.param c3=Ccopper_PCB_per_mm2*a32 +.param c4=Ccopper_PCB_per_mm2*a43 +.param c5=Ccopper_PCB_per_mm2*a54 +.param c6=Ccopper_PCB_per_mm2*a65 +.param c7=Ccopper_PCB_per_mm2*a76 +.param c8=Ccopper_PCB_per_mm2*a87 +.param c9=Ccopper_PCB_per_mm2*a98 +.param c10=Ccopper_PCB_per_mm2*a109 + +.param c1_FR4=Cfr4_PCB_per_mm2*a10 +.param c2_FR4=Cfr4_PCB_per_mm2*a21 +.param c3_FR4=Cfr4_PCB_per_mm2*a32 +.param c4_FR4=Cfr4_PCB_per_mm2*a43 +.param c5_FR4=Cfr4_PCB_per_mm2*a54 +.param c6_FR4=Cfr4_PCB_per_mm2*a65 +.param c7_FR4=Cfr4_PCB_per_mm2*a76 +.param c8_FR4=Cfr4_PCB_per_mm2*a87 +.param c9_FR4=Cfr4_PCB_per_mm2*a98 +.param c10_FR4=Cfr4_PCB_per_mm2*a109 + +.func Squares(radius_outer,radius_inner) {(radius_outer-radius_inner)/(2*pi*(radius_outer+radius_inner)/2)} +.param r0=Squares(radius1,radius0)*Rcopper_PCB_per_square +.param r1=Squares(radius2,radius1)*Rcopper_PCB_per_square +.param r2=Squares(radius3,radius2)*Rcopper_PCB_per_square +.param r3=Squares(radius4,radius3)*Rcopper_PCB_per_square +.param r4=Squares(radius5,radius4)*Rcopper_PCB_per_square +.param r5=Squares(radius6,radius5)*Rcopper_PCB_per_square +.param r6=Squares(radius7,radius6)*Rcopper_PCB_per_square +.param r7=Squares(radius8,radius7)*Rcopper_PCB_per_square +.param r8=Squares(radius9,radius8)*Rcopper_PCB_per_square +.param r9=Squares(radius10,radius9)*Rcopper_PCB_per_square + +.ends TopsideCopper + +* block symbol definitions + +.subckt radiation Tamb_C Tsurf_C +B1 Tsurf_C Tamb_C I=IF(Enable_Radiation>0,emissivity*sigma_mm2*{Area_mm2}*(Pow(V(Tsurf_C)+273,4)-Pow(V(Tamb_C)+273,4)),0) +.param emissivity=0.8 +.param sigma_mm2=5.6703E-14 +.param Enable_Radiation=1 +.ends radiation + + +.subckt convection Tamb_C Tsurf_C +Rair Tsurf_C Tamb_C {1/(hconv*Area_mm2)} +.param LFM=0 +.param PCB_FR4_Thickness_mm=1.5 +.param hconv0=1.1625e-5 +.param hconv={hconv0*(1+0.013*POW(LFM,0.8))} +.ends convection + + + + diff --git a/spice/copy/sub/TowTom2.sub b/spice/copy/sub/TowTom2.sub new file mode 100755 index 0000000..2a47893 --- /dev/null +++ b/spice/copy/sub/TowTom2.sub @@ -0,0 +1,27 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000. All rights reserved. +* +.subckt TowTom2 1 2 3 +C1 1 3 {C} +C3 N001 1 3p +C4 N002 N001 .3p +C7 2 N003 {C} +C6 2 3 .25p +R2 N001 1 10K +R3 N002 N001 10K +R5 N003 N002 {R} +R1 1 0 1. +C2 1 0 {Aol/GBW1/6.28318530717959} +G1 0 1 0 N005 {Aol} +R6 2 0 1. +C8 2 0 {Aol/GBW1/6.28318530717959} +G3 0 2 0 N007 {Aol} +R4 N002 0 1. +C5 N002 0 {Aol/GBW2/6.28318530717959} +G2 0 N002 0 N006 {Aol} +R10 N005 3 {RN1} +R11 N006 N001 {RN2} +R12 N007 N003 {RN3} +.params R=10K C=160p GBW1=10Meg GBW2=15Meg +.params Aol=100K +.param RN1=1 RN2=1 RN3=1 +.ends TowTom2 diff --git a/spice/copy/sub/UniversalOpAmps.sub b/spice/copy/sub/UniversalOpAmps.sub new file mode 100755 index 0000000..b918297 --- /dev/null +++ b/spice/copy/sub/UniversalOpAmps.sub @@ -0,0 +1,95 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006. All rights reserved. +* +.subckt level1 1 2 3 4 5 +A1 2 1 0 0 0 0 5 0 OTA G={Avol/Rout} ref={Vos} linear Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 Rout={Rout} +R5 2 3 {2*Rin} noiseless +R6 1 4 {2*Rin} noiseless +R1 3 1 {2*Rin} noiseless +R2 2 4 {2*Rin} noiseless +.param Rout=.1 +.param Cout={Avol/GBW/2/pi/Rout} +.param Avol=1Meg GBW=10Meg Slew=10Meg ilimit=25m rail=0 Vos=0 +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G +.ends level1 +* +.subckt level2 1 2 3 4 5 +S1 5 3 N002 5 Q +S2 4 5 5 N002 Q +A1 2 1 0 0 0 0 N002 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 +C3 5 4 1p +C4 3 5 1p +R2 N002 4 {2*Rout} noiseless +R1 3 N002 {2*Rout} noiseless +R3 3 1 {2*Rin} noiseless +R4 3 2 {2*Rin} noiseless +R5 2 4 {2*Rin} noiseless +R6 1 4 {2*Rin} noiseless +G1 0 N002 4 N002 table(0 0 10 {2*slew*Cout}) +G2 N002 0 N002 3 table(0 0 10 {2*slew*Cout}) +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless) +.param Avol=1Meg GBW=10Meg Slew=10Meg ilimit=25m rail=0 Vos=0 +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G +.ends level2 +* +.subckt level3a 1 2 3 4 5 +S1 5 3 N003 5 Q +S2 4 5 5 N003 Q +A1 2 1 0 0 0 0 N002 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 +C3 5 4 1p +C4 3 5 1p +R3 3 2 {2*Rin} noiseless +G1 0 N003 N002 0 {1/Rout} +R2 N003 0 {Rout} noiseless +C1 N003 0 {X*Cout/Avol} +R4 3 1 {2*Rin} noiseless +R5 1 4 {2*Rin} noiseless +R6 2 4 {2*Rin} noiseless +G2 0 N002 4 N002 table(0 0 10 {2*slew*Cout}) +G3 N002 0 N002 3 table(0 0 10 {2*slew*Cout}) +R1 N002 4 {2*Rout} noiseless +R7 3 N002 {2*Rout} noiseless +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless) +.param Avol=1Meg GBW=10Meg Slew=10Meg rail=0 Vos=0 ilimit=25m +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G phimargin=45 +.param X table(phimargin,29.4,3.5,32.1,2.9,33.8,2.6,35.8,2.3,38.1,2,40.9,1.7,43.2,1.5,45.9,1.3,49.2,1.1,53.2,0.9,58.2,0.7,64.7,0.5,73,0.3,86.1,0.05) +.ends level3a +* +.subckt level3b 1 2 3 4 5 +S1 5 3 N007 5 Q +S2 4 5 5 N007 Q +A1 2 1 0 0 0 0 N002 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 +C3 5 4 1p +C4 3 5 1p +R3 3 2 {2*Rin} noiseless +R4 3 1 {2*Rin} noiseless +R5 1 4 {2*Rin} noiseless +R6 2 4 {2*Rin} noiseless +G2 0 N007 N006 0 10µ +R9 0 N007 100K noiseless +G1 0 N003 N002 0 {2/Rz} +C1 N003 0 {.768*Cd} +L1 N003 N004 41.2µ +R1 N003 0 {Rz} noiseless +R2 N006 0 {Rz} noiseless +L2 N004 N005 23.8µ +L3 N005 N006 11.04µ +C2 N004 0 {.294*Cd} +C5 N005 0 {.178*Cd} +C6 N006 0 {.0375*Cd} +G3 0 N002 4 N002 table(0 0 10 {2*slew*Cout}) +G4 N002 0 N002 3 table(0 0 10 {2*slew*Cout}) +R7 3 N002 {2*Rout} noiseless +R8 N002 4 {2*Rout} noiseless +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless) +.param Avol=1Meg GBW=10Meg Slew=10Meg rail=0 Vos=0 ilimit=25m +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G phimargin=45 +.param delay=(90-MIN(phimargin,89))/360/GBW +.param Rz=sqrt(100u/Cd) +.param Cd=delay*delay/100u +.ends level3b diff --git a/spice/copy/sub/UniversalOpAmps2.sub b/spice/copy/sub/UniversalOpAmps2.sub new file mode 100755 index 0000000..361360c --- /dev/null +++ b/spice/copy/sub/UniversalOpAmps2.sub @@ -0,0 +1,95 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006. All rights reserved. +* +.subckt level.1 1 2 3 4 5 +A1 2 1 0 0 0 0 5 0 OTA G={Avol/Rout} ref={Vos} linear Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 Rout={Rout} +R5 2 3 {2*Rin} noiseless +R6 1 4 {2*Rin} noiseless +R1 3 1 {2*Rin} noiseless +R2 2 4 {2*Rin} noiseless +.param Rout=.1 +.param Cout={Avol/GBW/2/pi/Rout} +.param Avol=1Meg GBW=10Meg Slew=10Meg ilimit=25m rail=0 Vos=0 +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G +.ends level.1 +* +.subckt level.2 1 2 3 4 5 +S1 5 3 N002 5 Q +S2 4 5 5 N002 Q +A1 2 1 0 0 0 0 N002 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 +C3 5 4 1p +C4 3 5 1p +R2 N002 4 {2*Rout} noiseless +R1 3 N002 {2*Rout} noiseless +R3 3 1 {2*Rin} noiseless +R4 3 2 {2*Rin} noiseless +R5 2 4 {2*Rin} noiseless +R6 1 4 {2*Rin} noiseless +G1 0 N002 4 N002 table(0 0 10 {2*slew*Cout}) +G2 N002 0 N002 3 table(0 0 10 {2*slew*Cout}) +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless level=2 epsilon={Rail/10}) +.param Avol=1Meg GBW=10Meg Slew=10Meg ilimit=25m rail=0 Vos=0 +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G +.ends level.2 +* +.subckt level.3a 1 2 3 4 5 +S1 5 3 N003 5 Q +S2 4 5 5 N003 Q +A1 2 1 0 0 0 0 N002 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 +C3 5 4 1p +C4 3 5 1p +R3 3 2 {2*Rin} noiseless +G1 0 N003 N002 0 {1/Rout} +R2 N003 0 {Rout} noiseless +C1 N003 0 {X*Cout/Avol} +R4 3 1 {2*Rin} noiseless +R5 1 4 {2*Rin} noiseless +R6 2 4 {2*Rin} noiseless +G2 0 N002 4 N002 table(0 0 10 {2*slew*Cout}) +G3 N002 0 N002 3 table(0 0 10 {2*slew*Cout}) +R1 N002 4 {2*Rout} noiseless +R7 3 N002 {2*Rout} noiseless +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless level=2 epsilon={Rail/10}) +.param Avol=1Meg GBW=10Meg Slew=10Meg rail=0 Vos=0 ilimit=25m +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G phimargin=45 +.param X table(phimargin,29.4,3.5,32.1,2.9,33.8,2.6,35.8,2.3,38.1,2,40.9,1.7,43.2,1.5,45.9,1.3,49.2,1.1,53.2,0.9,58.2,0.7,64.7,0.5,73,0.3,86.1,0.05) +.ends level.3a +* +.subckt level.3b 1 2 3 4 5 +S1 5 3 N007 5 Q +S2 4 5 5 N007 Q +A1 2 1 0 0 0 0 N002 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 +C3 5 4 1p +C4 3 5 1p +R3 3 2 {2*Rin} noiseless +R4 3 1 {2*Rin} noiseless +R5 1 4 {2*Rin} noiseless +R6 2 4 {2*Rin} noiseless +G2 0 N007 N006 0 10µ +R9 0 N007 100K noiseless +G1 0 N003 N002 0 {2/Rz} +C1 N003 0 {.768*Cd} +L1 N003 N004 41.2µ +R1 N003 0 {Rz} noiseless +R2 N006 0 {Rz} noiseless +L2 N004 N005 23.8µ +L3 N005 N006 11.04µ +C2 N004 0 {.294*Cd} +C5 N005 0 {.178*Cd} +C6 N006 0 {.0375*Cd} +G3 0 N002 4 N002 table(0 0 10 {2*slew*Cout}) +G4 N002 0 N002 3 table(0 0 10 {2*slew*Cout}) +R7 3 N002 {2*Rout} noiseless +R8 N002 4 {2*Rout} noiseless +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless level=2 epsilon={Rail/10}) +.param Avol=1Meg GBW=10Meg Slew=10Meg rail=0 Vos=0 ilimit=25m +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G phimargin=45 +.param delay=(90-MIN(phimargin,89))/360/GBW +.param Rz=sqrt(100u/Cd) +.param Cd=delay*delay/100u +.ends level.3b diff --git a/spice/copy/sub/UniversalOpAmps3.sub b/spice/copy/sub/UniversalOpAmps3.sub new file mode 100755 index 0000000..98d337f --- /dev/null +++ b/spice/copy/sub/UniversalOpAmps3.sub @@ -0,0 +1,104 @@ +* Copyright © Linear Technology Corp. 2007. All rights reserved. +* +.subckt level_1 1 2 3 4 5 +A1 2 1 0 0 0 0 5 0 OTA G={Avol/Rout} ref={Vos} linear Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 Rout={Rout} +R5 2 3 {2*Rin} noiseless +R6 1 4 {2*Rin} noiseless +R1 3 1 {2*Rin} noiseless +R2 2 4 {2*Rin} noiseless +.param Rout=.1 +.param Cout={Avol/GBW/2/pi/Rout} +.param Avol=1Meg GBW=10Meg Slew=10Meg ilimit=25m rail=0 Vos=0 +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G +.ends level_1 +* +.subckt level_2 1 2 3 4 5 +S1 5 3 X 5 Q +S2 4 5 5 X Q +A1 2 1 0 0 0 0 X 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 +C3 5 4 1p +C4 3 5 1p +R2 X 4 {2*Rout} noiseless +R1 3 X {2*Rout} noiseless +R3 3 1 {2*Rin} noiseless +R4 3 2 {2*Rin} noiseless +R5 2 4 {2*Rin} noiseless +R6 1 4 {2*Rin} noiseless +B1 X 0 I=if(V(x,3)<0,0,({2*slew*Cout}*V(x,3))**2) +B2 0 X I=if(V(x,4)>0,0,({2*slew*Cout}*V(4,x))**2) +D1 5 3 X +D2 4 5 X +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless level=2 epsilon={Rail/10}) +.param Avol=1Meg GBW=10Meg Slew=10Meg ilimit=25m rail=0 Vos=0 +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G +.model X D(Ron=1 epsilon=10 noiseless) +.ends level_2 +* +.subckt level_3a 1 2 3 4 5 +S1 5 3 N002 5 Q +S2 4 5 5 N002 Q +A1 2 1 0 0 0 0 X 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 +C3 5 4 1p +C4 3 5 1p +R3 3 2 {2*Rin} noiseless +G1 0 N002 X 0 {1/Rout} +R2 N002 0 {Rout} noiseless +C1 N002 0 {X*Cout/Avol} +R4 3 1 {2*Rin} noiseless +R5 1 4 {2*Rin} noiseless +R6 2 4 {2*Rin} noiseless +R1 X 4 {2*Rout} noiseless +R7 3 X {2*Rout} noiseless +B1 X 0 I=if(V(x,3)<0,0,({2*slew*Cout}*V(x,3))**2) +B2 0 X I=if(V(x,4)>0,0,({2*slew*Cout}*V(4,x))**2) +D1 5 3 X +D2 4 5 X +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless level=2 epsilon={Rail/10}) +.param Avol=1Meg GBW=10Meg Slew=10Meg rail=0 Vos=0 ilimit=25m +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G phimargin=45 +.param X table(phimargin,29.4,3.5,32.1,2.9,33.8,2.6,35.8,2.3,38.1,2,40.9,1.7,43.2,1.5,45.9,1.3,49.2,1.1,53.2,0.9,58.2,0.7,64.7,0.5,73,0.3,86.1,0.05) +.model X D(Ron=1 epsilon=10 noiseless) +.ends level_3a +* +.subckt level_3b 1 2 3 4 5 +S1 5 3 N002 5 Q +S2 4 5 5 N002 Q +A1 2 1 0 0 0 0 X 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} incm={incm} incmk={incmk} Vhigh=1e308 Vlow=-1e308 +C3 5 4 1p +C4 3 5 1p +R3 3 2 {2*Rin} noiseless +R4 3 1 {2*Rin} noiseless +R5 1 4 {2*Rin} noiseless +R6 2 4 {2*Rin} noiseless +G2 0 N002 N006 0 10µ +R9 0 N002 100K noiseless +G1 0 N003 X 0 {2/Rz} +C1 N003 0 {.768*Cd} +L1 N003 N004 41.2µ +R1 N003 0 {Rz} noiseless +R2 N006 0 {Rz} noiseless +L2 N004 N005 23.8µ +L3 N005 N006 11.04µ +C2 N004 0 {.294*Cd} +C5 N005 0 {.178*Cd} +C6 N006 0 {.0375*Cd} +R7 3 X {2*Rout} noiseless +R8 X 4 {2*Rout} noiseless +B1 X 0 I=if(V(x,3)<0,0,({2*slew*Cout}*V(x,3))**2) +B2 0 X I=if(V(x,4)>0,0,({2*slew*Cout}*V(4,x))**2) +D1 5 3 X +D2 4 5 X +.param Rout=100Meg +.param Cout={Avol/GBW/2/pi/Rout} +.model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless level=2 epsilon={Rail/10}) +.param Avol=1Meg GBW=10Meg Slew=10Meg rail=0 Vos=0 ilimit=25m +.param en=0 enk=0 in=0 ink=0 incm=0 incmk=0 Rin=1G phimargin=45 +.param delay=(90-MIN(phimargin,89))/360/GBW +.param Rz=sqrt(100u/Cd) +.param Cd=delay*delay/100u +.model X D(Ron=1 epsilon=10 noiseless) +.ends level_3b diff --git a/spice/copy/sub/capometer.sub b/spice/copy/sub/capometer.sub new file mode 100755 index 0000000..39e5e6a --- /dev/null +++ b/spice/copy/sub/capometer.sub @@ -0,0 +1,37 @@ +* Copyright © Linear Technology Corp. 1998, 1999. All rights reserved. +* +.subckt capometer 1 2 3 4 5 +B1 2 1 I={current}*cos(2*pi*{freq}*time)*min(time*2e5, 1.) Rpar=1G +R1 N001 0 1. +C2 N001 0 {C} +B2 0 N001 I=sin(2*pi*{freq}*time)*V(x)*min(time*2e5, 1.) +G1 0 N002 N001 0 1. +G2 0 im N002 0 1. +R4 N002 0 1. +C5 N002 0 {C} +R5 im 0 1. +C6 im 0 {C} +R2 N003 0 1. +C3 N003 0 {C} +B3 0 N003 I=cos(2*pi*{freq}*time)*V(x)*min(time*2e5, 1.) +G3 0 N004 N003 0 1. +G4 0 re N004 0 1. +R6 N004 0 1. +C7 N004 0 {C} +R7 re 0 1. +C8 re 0 {C} +R3 5 0 1. +C4 5 0 {C} +B4 0 5 I=if(time<10u, 0., max(0.,.5*V(im)*{current}/(2*pi*{freq})/(V(im)*V(im)+V(re)*V(re)))) +R10 4 0 1. +C10 4 0 {C} +B6 0 4 I=if(time<10u, 0., 2./{current}*(V(re)+V(im)*V(im)/V(re))) +G5 0 x N005 2 1. +R8 x 0 1. +R9 3 0 1G +G6 N005 1 3 0 1. +R12 1 N005 1. +*C9 x 0 {1/(4*pi*freq/Q)} +*L1 0 x {1/(Q*pi*freq)} +.param current=10u freq=3Meg C=1µ Q=.25 +.ends capometer diff --git a/spice/copy/sub/neonbulb.sub b/spice/copy/sub/neonbulb.sub new file mode 100755 index 0000000..dbe388e --- /dev/null +++ b/spice/copy/sub/neonbulb.sub @@ -0,0 +1,10 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000, 2001, 2002, 2003. All rights reserved. +* +.subckt neonbulb 1 2 +S1 1 2 2 N001 G +S2 2 1 N001 2 G +R1 1 N001 100Meg +C1 N001 2 {Tau/100Meg} +.model G SW(Ron={Zon} Roff=1T Vt={.5*(Vstrike+Vhold)} Vh={.5*(Vstrike-Vhold)} Vser={Vhold-Ihold*Zon}) +.param Vstrike=100 Vhold=50 Zon=2K Ihold=200u Tau=100u +.ends neonbulb diff --git a/spice/copy/sub/opamp.sub b/spice/copy/sub/opamp.sub new file mode 100755 index 0000000..8d28894 --- /dev/null +++ b/spice/copy/sub/opamp.sub @@ -0,0 +1,7 @@ +* Copyright © Linear Technology Corp. 1998, 1999, 2000. All rights reserved. +* +.subckt opamp 1 2 3 +G1 0 3 2 1 {Aol} +R3 3 0 1. +C3 3 0 {Aol/GBW/6.28318530717959} +.ends opamp diff --git a/spice/copy/sym/ADC/AD4002.asy b/spice/copy/sym/ADC/AD4002.asy new file mode 100755 index 0000000..6a79e0d --- /dev/null +++ b/spice/copy/sym/ADC/AD4002.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -224 208 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value AD4002 +SYMATTR Prefix X +SYMATTR SpiceModel AD4002.sub +SYMATTR Value2 AD4002 +SYMATTR Description 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential SAR ADCs +PIN 208 0 RIGHT 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN 0 -224 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -208 -144 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN 208 112 RIGHT 8 +PINATTR PinName IN_SlewAlarm +PINATTR SpiceOrder 4 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -208 48 LEFT 8 +PINATTR PinName CNV +PINATTR SpiceOrder 6 +PIN -208 -48 LEFT 8 +PINATTR PinName EN_PreChrg +PINATTR SpiceOrder 7 +PIN -208 144 LEFT 8 +PINATTR PinName Reset +PINATTR SpiceOrder 8 +PIN 208 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/ADC/AD4003.asy b/spice/copy/sym/ADC/AD4003.asy new file mode 100755 index 0000000..aff9878 --- /dev/null +++ b/spice/copy/sym/ADC/AD4003.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -224 208 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value AD4003 +SYMATTR Prefix X +SYMATTR SpiceModel AD4003.sub +SYMATTR Value2 AD4003 +SYMATTR Description 18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Differential SAR ADCs +PIN 208 0 RIGHT 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN 0 -224 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -208 -160 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN 208 112 RIGHT 8 +PINATTR PinName IN_SlewAlarm +PINATTR SpiceOrder 4 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -208 80 LEFT 8 +PINATTR PinName CNV +PINATTR SpiceOrder 6 +PIN -208 0 LEFT 8 +PINATTR PinName EN_PreChrg +PINATTR SpiceOrder 7 +PIN -208 160 LEFT 8 +PINATTR PinName Reset +PINATTR SpiceOrder 8 +PIN 208 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 9 +PIN -208 -80 LEFT 8 +PINATTR PinName IN- +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/ADC/LTC2311-12.asy b/spice/copy/sym/ADC/LTC2311-12.asy new file mode 100755 index 0000000..0764832 --- /dev/null +++ b/spice/copy/sym/ADC/LTC2311-12.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2311-12 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2311-12.sub +SYMATTR Value2 LTC2311-12 +SYMATTR Description 12-Bit + Sign, 5Msps Diff Input ADC with Wide Input CM Range +PIN -64 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -176 -112 LEFT 8 +PINATTR PinName Ain+ +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName Ain- +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName REFin +PINATTR SpiceOrder 4 +PIN 176 -80 RIGHT 8 +PINATTR PinName REFout +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName _CNV +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 64 -160 TOP 8 +PINATTR PinName OVdd +PINATTR SpiceOrder 10 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/ADC/LTC2311-14.asy b/spice/copy/sym/ADC/LTC2311-14.asy new file mode 100755 index 0000000..5829b48 --- /dev/null +++ b/spice/copy/sym/ADC/LTC2311-14.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2311-14 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2311-14.sub +SYMATTR Value2 LTC2311-14 +SYMATTR Description 14-Bit + Sign, 5Msps Diff Input ADC with Wide Input CM Range +PIN -64 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -176 -112 LEFT 8 +PINATTR PinName Ain+ +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName Ain- +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName REFin +PINATTR SpiceOrder 4 +PIN 176 -80 RIGHT 8 +PINATTR PinName REFout +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName _CNV +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 64 -160 TOP 8 +PINATTR PinName OVdd +PINATTR SpiceOrder 10 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/ADC/LTC2311-16.asy b/spice/copy/sym/ADC/LTC2311-16.asy new file mode 100755 index 0000000..120c36a --- /dev/null +++ b/spice/copy/sym/ADC/LTC2311-16.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2311-16 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2311-16.sub +SYMATTR Value2 LTC2311-16 +SYMATTR Description 16-Bit, 5Msps Diff Input ADC with Wide Input CM Range +PIN -64 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -176 -112 LEFT 8 +PINATTR PinName Ain+ +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName Ain- +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName REFin +PINATTR SpiceOrder 4 +PIN 176 -80 RIGHT 8 +PINATTR PinName REFout +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName _CNV +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 64 -160 TOP 8 +PINATTR PinName OVdd +PINATTR SpiceOrder 10 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/ADC/LTC2323-12.asy b/spice/copy/sym/ADC/LTC2323-12.asy new file mode 100755 index 0000000..05c31ad --- /dev/null +++ b/spice/copy/sym/ADC/LTC2323-12.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2323-12 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2323-12.sub +SYMATTR Value2 LTC2323-12 +SYMATTR Description Dual (single channel model), 12-Bit + Sign, 5Msps Diff Input ADC with Wide Input CM Range +PIN -64 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -176 -112 LEFT 8 +PINATTR PinName Ain+ +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName Ain- +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName REFint +PINATTR SpiceOrder 4 +PIN 176 -80 RIGHT 8 +PINATTR PinName REFout1 +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName _CNV +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 8 +PIN 176 96 RIGHT 8 +PINATTR PinName SCLKout +PINATTR SpiceOrder 9 +PIN 64 -160 TOP 8 +PINATTR PinName OVdd +PINATTR SpiceOrder 10 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/ADC/LTC2323-14.asy b/spice/copy/sym/ADC/LTC2323-14.asy new file mode 100755 index 0000000..3d68030 --- /dev/null +++ b/spice/copy/sym/ADC/LTC2323-14.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2323-14 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2323-14.sub +SYMATTR Value2 LTC2323-14 +SYMATTR Description Dual (single channel model), 14-Bit + Sign, 5Msps Diff Input ADC with Wide Input CM Range +PIN -64 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -176 -112 LEFT 8 +PINATTR PinName Ain+ +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName Ain- +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName REFint +PINATTR SpiceOrder 4 +PIN 176 -80 RIGHT 8 +PINATTR PinName REFout1 +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName _CNV +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 8 +PIN 176 96 RIGHT 8 +PINATTR PinName SCLKout +PINATTR SpiceOrder 9 +PIN 64 -160 TOP 8 +PINATTR PinName OVdd +PINATTR SpiceOrder 10 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/ADC/LTC2323-16.asy b/spice/copy/sym/ADC/LTC2323-16.asy new file mode 100755 index 0000000..e47bcc7 --- /dev/null +++ b/spice/copy/sym/ADC/LTC2323-16.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2323-16 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2323-16.sub +SYMATTR Value2 LTC2323-16 +SYMATTR Description Dual (single channel model), 16-Bit + Sign, 5Msps Diff Input ADC with Wide Input CM Range +PIN -64 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -176 -112 LEFT 8 +PINATTR PinName Ain+ +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName Ain- +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName REFint +PINATTR SpiceOrder 4 +PIN 176 -80 RIGHT 8 +PINATTR PinName REFout1 +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName _CNV +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 8 +PIN 176 96 RIGHT 8 +PINATTR PinName SCLKout +PINATTR SpiceOrder 9 +PIN 64 -160 TOP 8 +PINATTR PinName OVdd +PINATTR SpiceOrder 10 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/ADC/LTC2325-12.asy b/spice/copy/sym/ADC/LTC2325-12.asy new file mode 100755 index 0000000..35c1682 --- /dev/null +++ b/spice/copy/sym/ADC/LTC2325-12.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2325-12 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2325-12.sub +SYMATTR Value2 LTC2325-12 +SYMATTR Description Quad (single channel model), 12-Bit + Sign, 5Msps/Ch Simultaneous Sampling ADC +PIN -64 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -176 -112 LEFT 8 +PINATTR PinName Ain+ +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName Ain- +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 4 +PIN 176 -80 RIGHT 8 +PINATTR PinName REFout1 +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName _CNV +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 8 +PIN 176 96 RIGHT 8 +PINATTR PinName SCLKout +PINATTR SpiceOrder 9 +PIN 64 -160 TOP 8 +PINATTR PinName OVdd +PINATTR SpiceOrder 10 +PIN -64 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 64 176 BOTTOM 8 +PINATTR PinName RefBufEN +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/ADC/LTC2325-14.asy b/spice/copy/sym/ADC/LTC2325-14.asy new file mode 100755 index 0000000..88766bf --- /dev/null +++ b/spice/copy/sym/ADC/LTC2325-14.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2325-14 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2325-14.sub +SYMATTR Value2 LTC2325-14 +SYMATTR Description Quad (single channel model), 14-Bit + Sign, 5Msps/Ch Simultaneous Sampling ADC +PIN -64 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -176 -112 LEFT 8 +PINATTR PinName Ain+ +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName Ain- +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 4 +PIN 176 -80 RIGHT 8 +PINATTR PinName REFout1 +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName _CNV +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 8 +PIN 176 96 RIGHT 8 +PINATTR PinName SCLKout +PINATTR SpiceOrder 9 +PIN 64 -160 TOP 8 +PINATTR PinName OVdd +PINATTR SpiceOrder 10 +PIN -64 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 64 176 BOTTOM 8 +PINATTR PinName RefBufEN +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/ADC/LTC2386-16.asy b/spice/copy/sym/ADC/LTC2386-16.asy new file mode 100755 index 0000000..c0fc6b6 --- /dev/null +++ b/spice/copy/sym/ADC/LTC2386-16.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +LINE Normal 96 144 96 -144 +LINE Normal -128 -144 -272 0 +LINE Normal 96 -144 -128 -144 +LINE Normal 96 144 -127 144 +LINE Normal -272 0 -127 144 +TEXT -66 -1 Center 2 ADI +WINDOW 3 -56 -59 Center 3 +WINDOW 0 -84 -34 Left 2 +SYMATTR Value LTC2386-16 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2386-16.sub +SYMATTR Value2 LTC2386-16 +SYMATTR Description 16-Bit, 10Msps SAR ADC +PIN -256 -16 LEFT 16 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN 96 -96 RIGHT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 96 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -32 -144 TOP 8 +PINATTR PinName REFBUF +PINATTR SpiceOrder 5 +PIN 96 96 RIGHT 8 +PINATTR PinName CNV +PINATTR SpiceOrder 6 +PIN -256 16 LEFT 16 +PINATTR PinName IN- +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/ADC/LTC2386-18.asy b/spice/copy/sym/ADC/LTC2386-18.asy new file mode 100755 index 0000000..886c1a7 --- /dev/null +++ b/spice/copy/sym/ADC/LTC2386-18.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +LINE Normal 96 144 96 -144 +LINE Normal -128 -144 -272 0 +LINE Normal 96 -144 -128 -144 +LINE Normal 96 144 -127 144 +LINE Normal -272 0 -127 144 +TEXT -66 -1 Center 2 ADI +WINDOW 3 -56 -59 Center 3 +WINDOW 0 -84 -34 Left 2 +SYMATTR Value LTC2386-18 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2386-18.sub +SYMATTR Value2 LTC2386-18 +SYMATTR Description 18-Bit, 10Msps SAR ADC +PIN -256 -16 LEFT 16 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN 96 -96 RIGHT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 96 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -32 -144 TOP 8 +PINATTR PinName REFBUF +PINATTR SpiceOrder 5 +PIN 96 96 RIGHT 8 +PINATTR PinName CNV +PINATTR SpiceOrder 6 +PIN -256 16 LEFT 16 +PINATTR PinName IN- +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/ADC/LTC2387-18.asy b/spice/copy/sym/ADC/LTC2387-18.asy new file mode 100755 index 0000000..46f6176 --- /dev/null +++ b/spice/copy/sym/ADC/LTC2387-18.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +LINE Normal 96 144 96 -144 +LINE Normal -128 -144 -272 0 +LINE Normal 96 -144 -128 -144 +LINE Normal 96 144 -127 144 +LINE Normal -272 0 -127 144 +TEXT -66 -1 Center 2 ADI +WINDOW 3 -56 -59 Center 3 +WINDOW 0 -84 -34 Left 2 +SYMATTR Value LTC2387-18 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2387-18.sub +SYMATTR Value2 LTC2387-18 +SYMATTR Description 18-Bit, 15Msps SAR ADC +PIN -256 -16 LEFT 16 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN 96 -96 RIGHT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 96 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -32 -144 TOP 8 +PINATTR PinName REFBUF +PINATTR SpiceOrder 5 +PIN 96 96 RIGHT 8 +PINATTR PinName CNV +PINATTR SpiceOrder 6 +PIN -256 16 LEFT 16 +PINATTR PinName IN- +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/Comparators/LT1011.asy b/spice/copy/sym/Comparators/LT1011.asy new file mode 100755 index 0000000..298e850 --- /dev/null +++ b/spice/copy/sym/Comparators/LT1011.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -29 +LINE Normal 0 48 0 29 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal 16 48 16 19 +LINE Normal 12 12 20 12 +LINE Normal 12 12 12 8 +LINE Normal 20 16 12 16 +LINE Normal 20 16 20 12 +LINE Normal 12 8 20 8 +LINE Normal -4 22 4 22 +LINE Normal -16 38 -16 48 +LINE Normal -16 30 -12 30 +LINE Normal -20 34 -20 26 +LINE Normal -12 34 -20 34 +LINE Normal -12 34 -12 30 +LINE Normal -20 26 -12 26 +LINE Normal 16 -48 16 -19 +LINE Normal 13 -16 13 -8 +LINE Normal 18 -16 13 -16 +LINE Normal 18 -16 20 -14 +LINE Normal 18 -12 13 -12 +LINE Normal 18 -12 20 -14 +LINE Normal 18 -8 13 -8 +LINE Normal 18 -8 20 -10 +LINE Normal 18 -12 20 -10 +WINDOW 0 32 -32 Left 2 +WINDOW 3 32 32 Left 2 +SYMATTR Value LT1011 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1011 +SYMATTR Description Voltage Comparator +PIN -16 48 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 2 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 16 -48 NONE 0 +PINATTR PinName BAL +PINATTR SpiceOrder 5 +PIN 16 48 NONE 0 +PINATTR PinName STROBE +PINATTR SpiceOrder 6 +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1015.asy b/spice/copy/sym/Comparators/LT1015.asy new file mode 100755 index 0000000..960b888 --- /dev/null +++ b/spice/copy/sym/Comparators/LT1015.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -28 +LINE Normal 0 48 0 28 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal 16 48 16 20 +LINE Normal 13 16 13 7 +LINE Normal 19 16 13 16 +LINE Normal -4 22 4 22 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT1015 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1015 +SYMATTR Description High Speed Dual Line Receiver(1 of 2) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 48 0 NONE 0 +PINATTR PinName OUT+ +PINATTR SpiceOrder 5 +PIN 16 48 NONE 0 +PINATTR PinName LATCH +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Comparators/LT1016.asy b/spice/copy/sym/Comparators/LT1016.asy new file mode 100755 index 0000000..7002bb4 --- /dev/null +++ b/spice/copy/sym/Comparators/LT1016.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +LINE Normal -32 16 48 64 +LINE Normal -32 112 48 64 +LINE Normal -32 16 -32 112 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 16 0 36 +LINE Normal 0 112 0 92 +LINE Normal -4 44 4 44 +LINE Normal 0 40 0 48 +LINE Normal -20 96 -12 96 +LINE Normal -16 112 -16 104 +LINE Normal 16 112 16 84 +LINE Normal 48 48 24 48 +LINE Normal 36 80 48 80 +LINE Normal -4 76 -4 88 +LINE Normal 4 88 -4 88 +LINE Normal 16 76 20 76 +LINE Normal 20 80 20 76 +LINE Normal 20 80 12 80 +LINE Normal 12 80 12 72 +LINE Normal 12 72 20 72 +CIRCLE Normal 28 76 36 84 +WINDOW 0 32 24 Left 2 +WINDOW 3 32 104 Left 2 +SYMATTR Value LT1016 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1016 +SYMATTR Description Ultra Fast Precision Comparator +PIN 0 16 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 2 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -16 112 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 0 112 NONE 0 +PINATTR PinName LATCH +PINATTR SpiceOrder 5 +PIN 16 112 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 48 48 NONE 0 +PINATTR PinName OUT+ +PINATTR SpiceOrder 7 +PIN 48 80 NONE 0 +PINATTR PinName OUT- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1017.asy b/spice/copy/sym/Comparators/LT1017.asy new file mode 100755 index 0000000..50de7cd --- /dev/null +++ b/spice/copy/sym/Comparators/LT1017.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1017 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1017 +SYMATTR Description µPower Dual Comparator(1 of 2) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Comparators/LT1018.asy b/spice/copy/sym/Comparators/LT1018.asy new file mode 100755 index 0000000..25063cb --- /dev/null +++ b/spice/copy/sym/Comparators/LT1018.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1018 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1018 +SYMATTR Description µPower Dual Comparator(1 of 2) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Comparators/LT1116.asy b/spice/copy/sym/Comparators/LT1116.asy new file mode 100755 index 0000000..be07de5 --- /dev/null +++ b/spice/copy/sym/Comparators/LT1116.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +LINE Normal -32 16 48 64 +LINE Normal -32 112 48 64 +LINE Normal -32 16 -32 112 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 16 0 36 +LINE Normal 0 112 0 92 +LINE Normal -4 44 4 44 +LINE Normal 0 40 0 48 +LINE Normal -20 96 -12 96 +LINE Normal -16 112 -16 104 +LINE Normal 16 112 16 84 +LINE Normal 48 48 24 48 +LINE Normal 36 80 48 80 +LINE Normal -4 76 -4 88 +LINE Normal 4 88 -4 88 +LINE Normal 16 76 20 76 +LINE Normal 20 80 20 76 +LINE Normal 20 80 12 80 +LINE Normal 12 80 12 72 +LINE Normal 12 72 20 72 +CIRCLE Normal 28 76 36 84 +WINDOW 0 32 24 Left 2 +WINDOW 3 32 104 Left 2 +SYMATTR Value LT1116 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1116 +SYMATTR Description 12ns, Single Supply Ground-Sensing Comparator +PIN 0 16 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 2 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -16 112 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 0 112 NONE 0 +PINATTR PinName LATCH +PINATTR SpiceOrder 5 +PIN 16 112 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 48 48 NONE 0 +PINATTR PinName OUT+ +PINATTR SpiceOrder 7 +PIN 48 80 NONE 0 +PINATTR PinName OUT- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1394.asy b/spice/copy/sym/Comparators/LT1394.asy new file mode 100755 index 0000000..b54b6ce --- /dev/null +++ b/spice/copy/sym/Comparators/LT1394.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1394 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1394 +SYMATTR Description 7ns, Low Power Single Supply, Ground-Sensing Comparator +PIN -128 -96 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName LE +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName _Q +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1671.asy b/spice/copy/sym/Comparators/LT1671.asy new file mode 100755 index 0000000..c71b486 --- /dev/null +++ b/spice/copy/sym/Comparators/LT1671.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1671 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1671 +SYMATTR Description 60ns, Low Power, Single Supply, Ground-Sensing Comparator +PIN -128 -96 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName LE +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName _Q +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1711.asy b/spice/copy/sym/Comparators/LT1711.asy new file mode 100755 index 0000000..7e2f6ba --- /dev/null +++ b/spice/copy/sym/Comparators/LT1711.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -28 +LINE Normal 0 48 0 28 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal -20 32 -12 32 +LINE Normal -16 48 -16 40 +LINE Normal 16 48 16 20 +LINE Normal 48 -16 24 -16 +LINE Normal 36 16 48 16 +LINE Normal -3 12 -3 24 +LINE Normal 3 24 -3 24 +LINE Normal 16 11 19 11 +LINE Normal 19 16 19 11 +LINE Normal 19 16 13 16 +LINE Normal 13 16 13 5 +LINE Normal 13 5 19 5 +CIRCLE Normal 28 12 36 20 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT1711 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1711 +SYMATTR Description 4.5ns, 3V/5V/±5V Rail-to-Rail Comparator +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 16 48 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 48 -16 NONE 0 +PINATTR PinName OUT+ +PINATTR SpiceOrder 6 +PIN 48 16 NONE 0 +PINATTR PinName OUT- +PINATTR SpiceOrder 7 +PIN 0 48 NONE 0 +PINATTR PinName LATCH +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1712.asy b/spice/copy/sym/Comparators/LT1712.asy new file mode 100755 index 0000000..7054bdc --- /dev/null +++ b/spice/copy/sym/Comparators/LT1712.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -28 +LINE Normal 0 48 0 28 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal -20 32 -12 32 +LINE Normal -16 48 -16 40 +LINE Normal 16 48 16 20 +LINE Normal 48 -16 24 -16 +LINE Normal 36 16 48 16 +LINE Normal -3 12 -3 24 +LINE Normal 3 24 -3 24 +LINE Normal 16 11 19 11 +LINE Normal 19 16 19 11 +LINE Normal 19 16 13 16 +LINE Normal 13 16 13 5 +LINE Normal 13 5 19 5 +CIRCLE Normal 28 12 36 20 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT1712 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1711 +SYMATTR Description Dual 4.5ns, 3V/5V/±5V Rail-to-Rail Comparator(1 of 2) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 16 48 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 48 -16 NONE 0 +PINATTR PinName OUT+ +PINATTR SpiceOrder 6 +PIN 48 16 NONE 0 +PINATTR PinName OUT- +PINATTR SpiceOrder 7 +PIN 0 48 NONE 0 +PINATTR PinName LATCH +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1713.asy b/spice/copy/sym/Comparators/LT1713.asy new file mode 100755 index 0000000..b11ea2d --- /dev/null +++ b/spice/copy/sym/Comparators/LT1713.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -28 +LINE Normal 0 48 0 28 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal -20 32 -12 32 +LINE Normal -16 48 -16 40 +LINE Normal 16 48 16 20 +LINE Normal 48 -16 24 -16 +LINE Normal 36 16 48 16 +LINE Normal -3 12 -3 24 +LINE Normal 3 24 -3 24 +LINE Normal 16 11 19 11 +LINE Normal 19 16 19 11 +LINE Normal 19 16 13 16 +LINE Normal 13 16 13 5 +LINE Normal 13 5 19 5 +CIRCLE Normal 28 12 36 20 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT1713 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1713 +SYMATTR Description 7ns, Low Power, 3V/5V/±5V Rail-to-Rail Comparator +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 16 48 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 48 -16 NONE 0 +PINATTR PinName OUT+ +PINATTR SpiceOrder 6 +PIN 48 16 NONE 0 +PINATTR PinName OUT- +PINATTR SpiceOrder 7 +PIN 0 48 NONE 0 +PINATTR PinName LATCH +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1714.asy b/spice/copy/sym/Comparators/LT1714.asy new file mode 100755 index 0000000..f6393fe --- /dev/null +++ b/spice/copy/sym/Comparators/LT1714.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -28 +LINE Normal 0 48 0 28 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal -20 32 -12 32 +LINE Normal -16 48 -16 40 +LINE Normal 16 48 16 20 +LINE Normal 48 -16 24 -16 +LINE Normal 36 16 48 16 +LINE Normal -3 12 -3 24 +LINE Normal 3 24 -3 24 +LINE Normal 16 11 19 11 +LINE Normal 19 16 19 11 +LINE Normal 19 16 13 16 +LINE Normal 13 16 13 5 +LINE Normal 13 5 19 5 +CIRCLE Normal 28 12 36 20 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT1714 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1713 +SYMATTR Description Dual 7ns, Low Power, 3V/5V/±5V Rail-to-Rail Comparator(1 of 2) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 16 48 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 48 -16 NONE 0 +PINATTR PinName OUT+ +PINATTR SpiceOrder 6 +PIN 48 16 NONE 0 +PINATTR PinName OUT- +PINATTR SpiceOrder 7 +PIN 0 48 NONE 0 +PINATTR PinName LATCH +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1715.asy b/spice/copy/sym/Comparators/LT1715.asy new file mode 100755 index 0000000..6642836 --- /dev/null +++ b/spice/copy/sym/Comparators/LT1715.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -48 -16 -38 +LINE Normal -20 -29 -12 -29 +LINE Normal -16 -33 -16 -25 +LINE Normal -20 32 -12 32 +LINE Normal -16 48 -16 38 +LINE Normal 16 48 16 19 +LINE Normal 16 11 19 11 +LINE Normal 19 16 19 11 +LINE Normal 19 16 13 16 +LINE Normal 13 16 13 5 +LINE Normal 13 5 19 5 +LINE Normal 16 -19 16 -48 +LINE Normal 12 -12 20 -12 +LINE Normal 16 -16 16 -8 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT1715 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1715 +SYMATTR Description 7ns, Low Power, 3V/5V/±5V Rail-to-Rail Comparator +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -48 NONE 0 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -16 48 NONE 0 +PINATTR PinName Vee +PINATTR SpiceOrder 4 +PIN 16 -48 NONE 0 +PINATTR PinName VS+ +PINATTR SpiceOrder 5 +PIN 16 48 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/Comparators/LT1716.asy b/spice/copy/sym/Comparators/LT1716.asy new file mode 100755 index 0000000..fb16ee2 --- /dev/null +++ b/spice/copy/sym/Comparators/LT1716.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1716 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1716 +SYMATTR Description SOT-23, 44V, Over-the-Top, µPower, Precision, Rail-to-Rail Comparator +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Comparators/LT1719.asy b/spice/copy/sym/Comparators/LT1719.asy new file mode 100755 index 0000000..bbe0e78 --- /dev/null +++ b/spice/copy/sym/Comparators/LT1719.asy @@ -0,0 +1,67 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -30 48 -22 48 +LINE Normal -30 80 -22 80 +LINE Normal -26 84 -26 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal -4 56 4 56 +LINE Normal 0 52 0 60 +LINE Normal -4 75 4 75 +LINE Normal 16 72 16 96 +LINE Normal 22 72 24 74 +LINE Normal 20 72 22 72 +LINE Normal 18 74 20 72 +LINE Normal 18 79 18 74 +LINE Normal 20 81 18 79 +LINE Normal 22 81 20 81 +LINE Normal 24 79 22 81 +LINE Normal 24 77 24 79 +LINE Normal 22 77 24 77 +LINE Normal -16 88 -16 96 +LINE Normal -15 76 -14 78 +LINE Normal -17 76 -15 76 +LINE Normal -18 78 -17 76 +LINE Normal -17 85 -18 83 +LINE Normal -15 85 -17 85 +LINE Normal -14 83 -15 85 +LINE Normal -18 79 -18 78 +LINE Normal -14 82 -18 79 +LINE Normal -14 83 -14 82 +LINE Normal 16 56 16 32 +LINE Normal 18 53 26 53 +LINE Normal 22 49 22 57 +WINDOW 0 27 45 Left 2 +WINDOW 3 27 87 Left 2 +SYMATTR Value LT1719 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1719 +SYMATTR Description 4.5ns, Single Supply 3V/5V Comparator with Rail-to-Rail Outputs +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 2 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 16 96 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -16 96 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 16 32 NONE 0 +PINATTR PinName VS+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LT1720.asy b/spice/copy/sym/Comparators/LT1720.asy new file mode 100755 index 0000000..e7c58c6 --- /dev/null +++ b/spice/copy/sym/Comparators/LT1720.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1720 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1720 +SYMATTR Description Dual 4.5ns, Single Supply 3V/5V Comparator with Rail-to-Rail Outputs +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Comparators/LT1721.asy b/spice/copy/sym/Comparators/LT1721.asy new file mode 100755 index 0000000..094535b --- /dev/null +++ b/spice/copy/sym/Comparators/LT1721.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1721 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1720 +SYMATTR Description Quad 4.5ns, Single Supply 3V/5V Comparator with Rail-to-Rail Outputs +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Comparators/LT6700-1.asy b/spice/copy/sym/Comparators/LT6700-1.asy new file mode 100755 index 0000000..3ace8d7 --- /dev/null +++ b/spice/copy/sym/Comparators/LT6700-1.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +LINE Normal -8 -72 -12 -56 +LINE Normal -4 -72 -8 -56 +LINE Normal -8 -72 0 -72 +LINE Normal -8 -56 -16 -56 +LINE Normal 32 -64 64 -64 +LINE Normal -32 -96 32 -64 +LINE Normal -32 -32 32 -64 +LINE Normal -32 -96 -32 -32 +LINE Normal -28 -47 -20 -47 +LINE Normal -28 -80 -20 -80 +LINE Normal -24 -43 -24 -51 +LINE Normal -64 -80 -32 -80 +LINE Normal -8 56 -12 72 +LINE Normal -4 56 -8 72 +LINE Normal -8 56 0 56 +LINE Normal -8 72 -16 72 +LINE Normal 32 64 64 64 +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -51 48 -32 48 +LINE Normal -64 80 -32 80 +LINE Normal -51 -47 -32 -47 +LINE Normal -51 48 -51 -47 +LINE Normal -32 0 -51 0 +LINE Normal -32 -16 -32 16 +LINE Normal 32 -16 -32 -16 +LINE Normal 32 16 32 -16 +LINE Normal -32 16 32 16 +LINE Normal 40 -69 40 -81 +LINE Normal 45 -81 40 -81 +LINE Normal 47 -79 45 -81 +LINE Normal 47 -77 47 -79 +LINE Normal 45 -75 47 -77 +LINE Normal 40 -75 45 -75 +LINE Normal 47 -73 45 -75 +LINE Normal 47 -71 47 -73 +LINE Normal 45 -69 47 -71 +LINE Normal 40 -69 45 -69 +LINE Normal 47 48 45 46 +LINE Normal 47 58 47 48 +LINE Normal 40 48 42 46 +LINE Normal 45 46 42 46 +LINE Normal 40 58 40 48 +LINE Normal 47 52 40 52 +LINE Normal -24 84 -24 76 +RECTANGLE Normal -64 -128 64 128 +CIRCLE Normal -50 1 -52 -1 +CIRCLE Normal -49 2 -53 -2 +CIRCLE Normal -48 3 -54 -3 +TEXT 1 0 Center 2 Ref +WINDOW 0 8 -144 Left 2 +WINDOW 3 13 144 Left 2 +SYMATTR Value LT6700-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT6700-1 +SYMATTR Description µPower, Low Voltage, SOT-23, Dual Comparator with 400mV Reference +PIN 64 64 NONE 0 +PINATTR PinName OUTA +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 2 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -64 80 NONE 0 +PINATTR PinName +INA +PINATTR SpiceOrder 3 +PIN -64 -80 NONE 0 +PINATTR PinName -INB +PINATTR SpiceOrder 4 +PIN 0 -128 TOP 2 +PINATTR PinName Vs +PINATTR SpiceOrder 5 +PIN 64 -64 NONE 0 +PINATTR PinName OUTB +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Comparators/LT6700-2.asy b/spice/copy/sym/Comparators/LT6700-2.asy new file mode 100755 index 0000000..43fadbf --- /dev/null +++ b/spice/copy/sym/Comparators/LT6700-2.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +LINE Normal -8 -72 -12 -56 +LINE Normal -4 -72 -8 -56 +LINE Normal -8 -72 0 -72 +LINE Normal -8 -56 -16 -56 +LINE Normal 32 -64 64 -64 +LINE Normal -32 -96 32 -64 +LINE Normal -32 -32 32 -64 +LINE Normal -32 -96 -32 -32 +LINE Normal -28 -47 -20 -47 +LINE Normal -28 -80 -20 -80 +LINE Normal -24 -43 -24 -51 +LINE Normal -64 -80 -32 -80 +LINE Normal -8 56 -12 72 +LINE Normal -4 56 -8 72 +LINE Normal -8 56 0 56 +LINE Normal -8 72 -16 72 +LINE Normal 32 64 64 64 +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -51 48 -32 48 +LINE Normal -64 80 -32 80 +LINE Normal -51 -47 -32 -47 +LINE Normal -51 48 -51 -47 +LINE Normal -32 0 -51 0 +LINE Normal -32 -16 -32 16 +LINE Normal 32 -16 -32 -16 +LINE Normal 32 16 32 -16 +LINE Normal -32 16 32 16 +LINE Normal 40 -69 40 -81 +LINE Normal 45 -81 40 -81 +LINE Normal 47 -79 45 -81 +LINE Normal 47 -77 47 -79 +LINE Normal 45 -75 47 -77 +LINE Normal 40 -75 45 -75 +LINE Normal 47 -73 45 -75 +LINE Normal 47 -71 47 -73 +LINE Normal 45 -69 47 -71 +LINE Normal 40 -69 45 -69 +LINE Normal 47 48 45 46 +LINE Normal 47 58 47 48 +LINE Normal 40 48 42 46 +LINE Normal 45 46 42 46 +LINE Normal 40 58 40 48 +LINE Normal 47 52 40 52 +LINE Normal -24 52 -24 44 +RECTANGLE Normal -64 -128 64 128 +CIRCLE Normal -50 1 -52 -1 +CIRCLE Normal -49 2 -53 -2 +CIRCLE Normal -48 3 -54 -3 +TEXT 1 0 Center 2 Ref +WINDOW 0 8 -144 Left 2 +WINDOW 3 13 144 Left 2 +SYMATTR Value LT6700-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT6700-2 +SYMATTR Description µPower, Low Voltage, SOT-23, Dual Comparator with 400mV Reference +PIN 64 64 NONE 0 +PINATTR PinName OUTA +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 2 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -64 80 NONE 0 +PINATTR PinName -INA +PINATTR SpiceOrder 3 +PIN -64 -80 NONE 0 +PINATTR PinName -INB +PINATTR SpiceOrder 4 +PIN 0 -128 TOP 2 +PINATTR PinName Vs +PINATTR SpiceOrder 5 +PIN 64 -64 NONE 0 +PINATTR PinName OUTB +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Comparators/LT6700-3.asy b/spice/copy/sym/Comparators/LT6700-3.asy new file mode 100755 index 0000000..ef6b2c6 --- /dev/null +++ b/spice/copy/sym/Comparators/LT6700-3.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +LINE Normal -8 -72 -12 -56 +LINE Normal -4 -72 -8 -56 +LINE Normal -8 -72 0 -72 +LINE Normal -8 -56 -16 -56 +LINE Normal 32 -64 64 -64 +LINE Normal -32 -96 32 -64 +LINE Normal -32 -32 32 -64 +LINE Normal -32 -96 -32 -32 +LINE Normal -28 -47 -20 -47 +LINE Normal -28 -80 -20 -80 +LINE Normal -24 -76 -24 -84 +LINE Normal -64 -80 -32 -80 +LINE Normal -8 56 -12 72 +LINE Normal -4 56 -8 72 +LINE Normal -8 56 0 56 +LINE Normal -8 72 -16 72 +LINE Normal 32 64 64 64 +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal -51 48 -32 48 +LINE Normal -64 80 -32 80 +LINE Normal -51 -47 -32 -47 +LINE Normal -51 48 -51 -47 +LINE Normal -32 0 -51 0 +LINE Normal -32 -16 -32 16 +LINE Normal 32 -16 -32 -16 +LINE Normal 32 16 32 -16 +LINE Normal -32 16 32 16 +LINE Normal 40 -69 40 -81 +LINE Normal 45 -81 40 -81 +LINE Normal 47 -79 45 -81 +LINE Normal 47 -77 47 -79 +LINE Normal 45 -75 47 -77 +LINE Normal 40 -75 45 -75 +LINE Normal 47 -73 45 -75 +LINE Normal 47 -71 47 -73 +LINE Normal 45 -69 47 -71 +LINE Normal 40 -69 45 -69 +LINE Normal 47 48 45 46 +LINE Normal 47 58 47 48 +LINE Normal 40 48 42 46 +LINE Normal 45 46 42 46 +LINE Normal 40 58 40 48 +LINE Normal 47 52 40 52 +RECTANGLE Normal -64 -128 64 128 +CIRCLE Normal -50 1 -52 -1 +CIRCLE Normal -49 2 -53 -2 +CIRCLE Normal -48 3 -54 -3 +TEXT 1 0 Center 2 Ref +WINDOW 0 8 -144 Left 2 +WINDOW 3 13 144 Left 2 +SYMATTR Value LT6700-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT6700-3 +SYMATTR Description µPower, Low Voltage, SOT-23, Dual Comparator with 400mV Reference +PIN 64 64 NONE 0 +PINATTR PinName OUTA +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 2 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -64 80 NONE 0 +PINATTR PinName +INA +PINATTR SpiceOrder 3 +PIN -64 -80 NONE 0 +PINATTR PinName +INB +PINATTR SpiceOrder 4 +PIN 0 -128 TOP 2 +PINATTR PinName Vs +PINATTR SpiceOrder 5 +PIN 64 -64 NONE 0 +PINATTR PinName OUTB +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Comparators/LT6703-2.asy b/spice/copy/sym/Comparators/LT6703-2.asy new file mode 100755 index 0000000..d55d8e5 --- /dev/null +++ b/spice/copy/sym/Comparators/LT6703-2.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -8 8 -12 -8 +LINE Normal -4 8 -8 -8 +LINE Normal -8 8 0 8 +LINE Normal -8 -8 -16 -8 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 32 0 +LINE Normal -32 32 -32 -32 +LINE Normal -28 16 -20 16 +LINE Normal -28 -16 -20 -16 +LINE Normal -51 16 -32 16 +LINE Normal -32 64 -51 64 +LINE Normal -32 80 -32 48 +LINE Normal 32 80 -32 80 +LINE Normal 32 48 32 80 +LINE Normal -32 48 32 48 +LINE Normal -51 64 -51 16 +LINE Normal -24 11 -24 20 +LINE Normal 80 0 32 0 +LINE Normal -80 -16 -32 -16 +RECTANGLE Normal 80 112 -80 -64 +TEXT 1 64 Center 2 Ref +TEXT 43 24 Center 2 LT +WINDOW 0 10 -24 Left 2 +WINDOW 3 13 125 Left 2 +SYMATTR Value LT6703-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LT6703-2 +SYMATTR Description µPower, Low Voltage, SOT-23, Dual Comparator with 400mV Reference +PIN 80 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 2 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -80 -16 NONE 4 +PINATTR PinName -IN +PINATTR SpiceOrder 3 +PIN 0 -64 TOP 2 +PINATTR PinName Vs +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Comparators/LT6703-3.asy b/spice/copy/sym/Comparators/LT6703-3.asy new file mode 100755 index 0000000..7aeff9c --- /dev/null +++ b/spice/copy/sym/Comparators/LT6703-3.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -8 8 -12 -8 +LINE Normal -4 8 -8 -8 +LINE Normal -8 8 0 8 +LINE Normal -8 -8 -16 -8 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 32 0 +LINE Normal -32 32 -32 -32 +LINE Normal -28 16 -20 16 +LINE Normal -28 -16 -20 -16 +LINE Normal -51 16 -32 16 +LINE Normal -32 64 -51 64 +LINE Normal -32 80 -32 48 +LINE Normal 32 80 -32 80 +LINE Normal 32 48 32 80 +LINE Normal -32 48 32 48 +LINE Normal -24 -20 -24 -12 +LINE Normal -51 64 -51 16 +LINE Normal -80 -16 -32 -16 +LINE Normal 80 0 32 0 +RECTANGLE Normal 80 112 -80 -64 +TEXT 1 64 Center 2 Ref +TEXT 45 23 Center 2 LT +WINDOW 0 11 -26 Left 2 +WINDOW 3 13 128 Left 2 +SYMATTR Value LT6703-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LT6703-3 +SYMATTR Description µPower, Low Voltage, SOT-23, Dual Comparator with 400mV Reference +PIN 80 0 NONE 3 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 2 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -80 -16 NONE 5 +PINATTR PinName +IN +PINATTR SpiceOrder 3 +PIN 0 -64 TOP 2 +PINATTR PinName Vs +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Comparators/LTC1040.asy b/spice/copy/sym/Comparators/LTC1040.asy new file mode 100755 index 0000000..59710bd --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1040.asy @@ -0,0 +1,105 @@ +Version 4 +SymbolType BLOCK +LINE Normal -96 -32 -96 -192 +LINE Normal 15 -112 -96 -32 +LINE Normal -96 -192 15 -112 +LINE Normal -84 -176 -92 -176 +LINE Normal -88 -172 -88 -180 +LINE Normal -84 -144 -92 -144 +LINE Normal -96 -144 -176 -144 +LINE Normal 176 -112 15 -112 +LINE Normal -84 -80 -92 -80 +LINE Normal -88 -76 -88 -84 +LINE Normal -84 -48 -92 -48 +LINE Normal -96 -176 -176 -176 +LINE Normal -96 -80 -176 -80 +LINE Normal -96 -48 -176 -48 +LINE Normal -96 160 -96 0 +LINE Normal 15 80 -96 160 +LINE Normal -96 0 15 80 +LINE Normal -84 16 -92 16 +LINE Normal -88 20 -88 12 +LINE Normal -84 48 -92 48 +LINE Normal -96 48 -176 48 +LINE Normal 176 80 15 80 +LINE Normal -84 112 -92 112 +LINE Normal -88 116 -88 108 +LINE Normal -84 144 -92 144 +LINE Normal -96 16 -176 16 +LINE Normal -96 112 -176 112 +LINE Normal -96 144 -176 144 +RECTANGLE Normal 176 240 -176 -240 +TEXT -33 -112 Center 2 A +TEXT 174 -128 Right 2 AOUT +TEXT -174 -192 Left 2 A1+ +TEXT -174 -161 Left 2 A1- +TEXT -174 -95 Left 2 A2+ +TEXT -174 -63 Left 2 A2- +TEXT -33 80 Center 2 B +TEXT 174 64 Right 2 BOUT +TEXT -174 0 Left 2 B1+ +TEXT -174 31 Left 2 B1- +TEXT -174 97 Left 2 B2+ +TEXT -174 129 Left 2 B2- +TEXT 0 0 Center 2 LT +WINDOW 3 32 184 Center 2 +WINDOW 0 32 -160 Center 2 +SYMATTR Value LTC1040 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1040.sub +SYMATTR Value2 LTC1040 +SYMATTR Description Dual Micropower Comparator +PIN -112 240 BOTTOM 4 +PINATTR PinName STROBE +PINATTR SpiceOrder 1 +PIN 176 -48 RIGHT 8 +PINATTR PinName ON/_OFF +PINATTR SpiceOrder 2 +PIN 176 16 RIGHT 8 +PINATTR PinName _A+B +PINATTR SpiceOrder 3 +PIN 176 -112 NONE 8 +PINATTR PinName AOUT +PINATTR SpiceOrder 4 +PIN -176 -176 NONE 8 +PINATTR PinName A1+ +PINATTR SpiceOrder 5 +PIN -176 -144 NONE 8 +PINATTR PinName A1- +PINATTR SpiceOrder 6 +PIN -176 -80 NONE 8 +PINATTR PinName A2+ +PINATTR SpiceOrder 7 +PIN -176 -48 NONE 8 +PINATTR PinName A2- +PINATTR SpiceOrder 8 +PIN -16 240 BOTTOM 4 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 80 240 BOTTOM 4 +PINATTR PinName V- +PINATTR SpiceOrder 10 +PIN -176 144 NONE 8 +PINATTR PinName B2- +PINATTR SpiceOrder 11 +PIN -176 112 NONE 8 +PINATTR PinName B2+ +PINATTR SpiceOrder 12 +PIN -176 48 NONE 8 +PINATTR PinName B1- +PINATTR SpiceOrder 13 +PIN -176 16 NONE 8 +PINATTR PinName B1+ +PINATTR SpiceOrder 14 +PIN 176 80 NONE 8 +PINATTR PinName +OUT1 +PINATTR SpiceOrder 15 +PIN 176 144 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 16 +PIN 176 -176 RIGHT 8 +PINATTR PinName VP-P +PINATTR SpiceOrder 17 +PIN -16 -240 TOP 4 +PINATTR PinName V+ +PINATTR SpiceOrder 18 diff --git a/spice/copy/sym/Comparators/LTC1041.asy b/spice/copy/sym/Comparators/LTC1041.asy new file mode 100755 index 0000000..e6672ef --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1041.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC1041 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1041.sub +SYMATTR Value2 LTC1041 +SYMATTR Description BANG-BANG Controller +PIN -128 -96 LEFT 8 +PINATTR PinName ON/_OFF +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName SetPnt +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Delta +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vpp +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LTC1042.asy b/spice/copy/sym/Comparators/LTC1042.asy new file mode 100755 index 0000000..32dd9b9 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1042.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC1042 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1042.sub +SYMATTR Value2 LTC1042 +SYMATTR Description Window Comparator +PIN -128 -96 LEFT 8 +PINATTR PinName Within +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Center +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Width/2 +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Above +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LTC1440.asy b/spice/copy/sym/Comparators/LTC1440.asy new file mode 100755 index 0000000..0883ae9 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1440.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -8 56 -12 72 +LINE Normal -4 56 -8 72 +LINE Normal -8 56 0 56 +LINE Normal -8 72 -16 72 +LINE Normal 32 64 64 64 +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal -8 4 -4 16 +LINE Normal 0 4 -4 16 +LINE Normal 4 8 4 16 +LINE Normal 0 12 8 12 +LINE Normal 0 80 0 112 +LINE Normal -64 112 0 112 +LINE Normal -64 48 -32 48 +LINE Normal -64 80 -32 80 +LINE Normal -32 192 -32 168 +LINE Normal -40 168 -24 168 +LINE Normal -32 156 -24 168 +LINE Normal -32 156 -40 168 +LINE Normal -40 156 -24 156 +LINE Normal -40 156 -44 160 +LINE Normal -20 152 -24 156 +LINE Normal -32 156 -32 144 +LINE Normal -64 144 -32 144 +LINE Normal -28 176 -24 188 +LINE Normal -20 176 -24 188 +LINE Normal -20 184 -12 184 +LINE Normal 36 176 32 176 +LINE Normal 36 176 36 184 +LINE Normal 36 184 28 184 +LINE Normal 28 168 28 184 +LINE Normal 28 168 36 168 +RECTANGLE Normal -64 0 64 192 +WINDOW 0 8 -16 Left 2 +WINDOW 3 40 208 Left 2 +SYMATTR Value LTC1440 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1440 +SYMATTR Description Ultralow Power Comparator with Reference +PIN -64 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -64 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 0 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -32 192 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 32 192 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -64 144 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 7 +PIN -64 112 NONE 0 +PINATTR PinName HYST +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LTC1441.asy b/spice/copy/sym/Comparators/LTC1441.asy new file mode 100755 index 0000000..69dd060 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1441.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1441 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1441 +SYMATTR Description Dual Ultralow Power Comparator with Reference +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 2 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 3 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Comparators/LTC1442.asy b/spice/copy/sym/Comparators/LTC1442.asy new file mode 100755 index 0000000..e2d7a07 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1442.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC1442 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1442 +SYMATTR Description Dual Ultralow Power Comparator with Reference +PIN -128 -96 LEFT 8 +PINATTR PinName OUT A +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName InA+ +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName InB- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName HYST +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName OUT B +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LTC1443.asy b/spice/copy/sym/Comparators/LTC1443.asy new file mode 100755 index 0000000..c7dd93c --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1443.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType CELL +LINE Normal 32 64 64 64 +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal -8 4 -4 16 +LINE Normal 0 4 -4 16 +LINE Normal 4 8 4 16 +LINE Normal 0 12 8 12 +LINE Normal -64 48 -32 48 +LINE Normal -64 80 -32 80 +LINE Normal -32 192 -32 168 +LINE Normal -40 168 -24 168 +LINE Normal -32 156 -24 168 +LINE Normal -32 156 -40 168 +LINE Normal -40 156 -24 156 +LINE Normal -40 156 -44 160 +LINE Normal -20 152 -24 156 +LINE Normal -32 156 -32 144 +LINE Normal -64 144 -32 144 +LINE Normal -28 176 -24 188 +LINE Normal -20 176 -24 188 +LINE Normal -20 184 -12 184 +LINE Normal 36 176 32 176 +LINE Normal 36 176 36 184 +LINE Normal 36 184 28 184 +LINE Normal 28 168 28 184 +LINE Normal 28 168 36 168 +RECTANGLE Normal -64 0 64 192 +WINDOW 0 8 -16 Left 2 +WINDOW 3 40 208 Left 2 +SYMATTR Value LTC1443 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1443 +SYMATTR Description Quad Ultralow Power Comparator with Reference +PIN 64 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 0 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 2 +PIN -64 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -64 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 4 +PIN -64 144 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 5 +PIN -32 192 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN 32 192 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/Comparators/LTC1444.asy b/spice/copy/sym/Comparators/LTC1444.asy new file mode 100755 index 0000000..5738c7f --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1444.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +LINE Normal -8 56 -12 72 +LINE Normal -4 56 -8 72 +LINE Normal -8 56 0 56 +LINE Normal -8 72 -16 72 +LINE Normal 32 64 64 64 +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal -8 4 -4 16 +LINE Normal 0 4 -4 16 +LINE Normal 4 8 4 16 +LINE Normal 0 12 8 12 +LINE Normal -64 48 -32 48 +LINE Normal -64 80 -32 80 +LINE Normal -32 192 -32 168 +LINE Normal -40 168 -24 168 +LINE Normal -32 156 -24 168 +LINE Normal -32 156 -40 168 +LINE Normal -40 156 -24 156 +LINE Normal -40 156 -44 160 +LINE Normal -20 152 -24 156 +LINE Normal -32 156 -32 144 +LINE Normal -64 144 -32 144 +LINE Normal -28 176 -24 188 +LINE Normal -20 176 -24 188 +LINE Normal -20 184 -12 184 +LINE Normal -64 112 0 112 +LINE Normal 0 80 0 112 +RECTANGLE Normal -64 0 64 192 +WINDOW 0 8 -16 Left 2 +WINDOW 3 -16 208 Left 2 +SYMATTR Value LTC1444 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1444 +SYMATTR Description Quad Ultralow Power Comparator with Reference +PIN 64 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 0 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 2 +PIN -64 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -64 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 4 +PIN -64 144 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 5 +PIN -32 192 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 112 NONE 0 +PINATTR PinName HYST +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/Comparators/LTC1445.asy b/spice/copy/sym/Comparators/LTC1445.asy new file mode 100755 index 0000000..61c1a6f --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1445.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +LINE Normal -8 56 -12 72 +LINE Normal -4 56 -8 72 +LINE Normal -8 56 0 56 +LINE Normal -8 72 -16 72 +LINE Normal 32 64 64 64 +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal -8 4 -4 16 +LINE Normal 0 4 -4 16 +LINE Normal 4 8 4 16 +LINE Normal 0 12 8 12 +LINE Normal -64 48 -32 48 +LINE Normal -64 80 -32 80 +LINE Normal -32 192 -32 168 +LINE Normal -40 168 -24 168 +LINE Normal -32 156 -24 168 +LINE Normal -32 156 -40 168 +LINE Normal -40 156 -24 156 +LINE Normal -40 156 -44 160 +LINE Normal -20 152 -24 156 +LINE Normal -32 156 -32 144 +LINE Normal -64 144 -32 144 +LINE Normal -28 176 -24 188 +LINE Normal -20 176 -24 188 +LINE Normal -20 184 -12 184 +LINE Normal -64 112 0 112 +LINE Normal 0 80 0 112 +RECTANGLE Normal -64 0 64 192 +WINDOW 0 8 -16 Left 2 +WINDOW 3 -16 208 Left 2 +SYMATTR Value LTC1445 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1445 +SYMATTR Description Quad Ultralow Power Comparator with Reference +PIN 64 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 0 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 2 +PIN -64 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -64 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 4 +PIN -64 144 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 5 +PIN -32 192 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 112 NONE 0 +PINATTR PinName HYST +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/Comparators/LTC1540.asy b/spice/copy/sym/Comparators/LTC1540.asy new file mode 100755 index 0000000..c33d398 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1540.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -8 56 -12 72 +LINE Normal -4 56 -8 72 +LINE Normal -8 56 0 56 +LINE Normal -8 72 -16 72 +LINE Normal 32 64 64 64 +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal -8 4 -4 16 +LINE Normal 0 4 -4 16 +LINE Normal 4 8 4 16 +LINE Normal 0 12 8 12 +LINE Normal 0 80 0 112 +LINE Normal -64 112 0 112 +LINE Normal -64 48 -32 48 +LINE Normal -64 80 -32 80 +LINE Normal -32 192 -32 168 +LINE Normal -40 168 -24 168 +LINE Normal -32 156 -24 168 +LINE Normal -32 156 -40 168 +LINE Normal -40 156 -24 156 +LINE Normal -40 156 -44 160 +LINE Normal -20 152 -24 156 +LINE Normal -32 156 -32 144 +LINE Normal -64 144 -32 144 +LINE Normal -28 176 -24 188 +LINE Normal -20 176 -24 188 +LINE Normal -20 184 -12 184 +LINE Normal 36 176 32 176 +LINE Normal 36 176 36 184 +LINE Normal 36 184 28 184 +LINE Normal 28 168 28 184 +LINE Normal 28 168 36 168 +RECTANGLE Normal -64 0 64 192 +WINDOW 0 8 -16 Left 2 +WINDOW 3 40 208 Left 2 +SYMATTR Value LTC1540 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1540 +SYMATTR Description Nanopower Comparator with Reference +PIN 32 192 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -32 192 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 2 +PIN -64 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 3 +PIN -64 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 4 +PIN -64 112 NONE 0 +PINATTR PinName HYST +PINATTR SpiceOrder 5 +PIN -64 144 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 0 0 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 64 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LTC1841.asy b/spice/copy/sym/Comparators/LTC1841.asy new file mode 100755 index 0000000..5e6ba3b --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1841.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC1841 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LTC1841 +SYMATTR Description Ultralow Power Dual Comparator(1 of 2) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Comparators/LTC1842.asy b/spice/copy/sym/Comparators/LTC1842.asy new file mode 100755 index 0000000..3e00e71 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1842.asy @@ -0,0 +1,89 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -72 -24 -56 +LINE Normal -16 -72 -20 -56 +LINE Normal -20 -72 -12 -72 +LINE Normal -20 -56 -28 -56 +LINE Normal 20 -64 80 -64 +LINE Normal -44 -96 20 -64 +LINE Normal -44 -32 20 -64 +LINE Normal -44 -96 -44 -32 +LINE Normal -40 -47 -32 -47 +LINE Normal -40 -80 -32 -80 +LINE Normal -36 -76 -36 -84 +LINE Normal -80 -80 -44 -80 +LINE Normal -20 8 -24 24 +LINE Normal -16 8 -20 24 +LINE Normal -20 8 -12 8 +LINE Normal -20 24 -28 24 +LINE Normal 20 16 80 16 +LINE Normal -44 -16 20 16 +LINE Normal -44 48 20 16 +LINE Normal -44 -16 -44 48 +LINE Normal -40 32 -32 32 +LINE Normal -40 0 -32 0 +LINE Normal -67 32 -44 32 +LINE Normal -80 0 -44 0 +LINE Normal -67 -47 -44 -47 +LINE Normal -67 64 -67 -47 +LINE Normal -22 64 -80 64 +LINE Normal -22 48 -22 80 +LINE Normal 35 48 -22 48 +LINE Normal 35 80 35 48 +LINE Normal -22 80 35 80 +LINE Normal 40 -69 40 -81 +LINE Normal 45 -81 40 -81 +LINE Normal 47 -79 45 -81 +LINE Normal 47 -77 47 -79 +LINE Normal 45 -75 47 -77 +LINE Normal 40 -75 45 -75 +LINE Normal 47 -73 45 -75 +LINE Normal 47 -71 47 -73 +LINE Normal 45 -69 47 -71 +LINE Normal 40 -69 45 -69 +LINE Normal 47 0 45 -2 +LINE Normal 47 10 47 0 +LINE Normal 40 0 42 -2 +LINE Normal 45 -2 42 -2 +LINE Normal 40 10 40 0 +LINE Normal 47 4 40 4 +LINE Normal -36 4 -36 -4 +RECTANGLE Normal -80 -128 80 144 +CIRCLE Normal -66 33 -68 31 +CIRCLE Normal -65 34 -69 30 +CIRCLE Normal -64 35 -70 29 +CIRCLE Normal -66 65 -68 63 +CIRCLE Normal -65 66 -69 62 +CIRCLE Normal -64 67 -70 61 +TEXT 4 64 Center 2 Ref +WINDOW 0 8 -138 Left 2 +WINDOW 3 0 99 Center 2 +SYMATTR Value LTC1842 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LTC1842 +SYMATTR Description Ultralow Power Dual Comparator with Reference +PIN 80 16 NONE 0 +PINATTR PinName OUTA +PINATTR SpiceOrder 1 +PIN -48 144 BOTTOM 2 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -80 0 NONE 0 +PINATTR PinName INA+ +PINATTR SpiceOrder 3 +PIN -80 -80 NONE 0 +PINATTR PinName INB+ +PINATTR SpiceOrder 4 +PIN 48 144 BOTTOM 2 +PINATTR PinName Hyst +PINATTR SpiceOrder 5 +PIN -80 64 NONE 0 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN 0 -128 TOP 2 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN 80 -64 NONE 0 +PINATTR PinName OUTB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LTC1843.asy b/spice/copy/sym/Comparators/LTC1843.asy new file mode 100755 index 0000000..81b33a1 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1843.asy @@ -0,0 +1,89 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -72 -24 -56 +LINE Normal -16 -72 -20 -56 +LINE Normal -20 -72 -12 -72 +LINE Normal -20 -56 -28 -56 +LINE Normal 20 -64 80 -64 +LINE Normal -44 -96 20 -64 +LINE Normal -44 -32 20 -64 +LINE Normal -44 -96 -44 -32 +LINE Normal -40 -47 -32 -47 +LINE Normal -40 -80 -32 -80 +LINE Normal -36 -43 -36 -51 +LINE Normal -80 -80 -44 -80 +LINE Normal -20 8 -24 24 +LINE Normal -16 8 -20 24 +LINE Normal -20 8 -12 8 +LINE Normal -20 24 -28 24 +LINE Normal 20 16 80 16 +LINE Normal -44 -16 20 16 +LINE Normal -44 48 20 16 +LINE Normal -44 -16 -44 48 +LINE Normal -40 32 -32 32 +LINE Normal -40 0 -32 0 +LINE Normal -67 32 -44 32 +LINE Normal -80 0 -44 0 +LINE Normal -67 -47 -44 -47 +LINE Normal -67 64 -67 -47 +LINE Normal -22 64 -80 64 +LINE Normal -22 48 -22 80 +LINE Normal 35 48 -22 48 +LINE Normal 35 80 35 48 +LINE Normal -22 80 35 80 +LINE Normal 40 -69 40 -81 +LINE Normal 45 -81 40 -81 +LINE Normal 47 -79 45 -81 +LINE Normal 47 -77 47 -79 +LINE Normal 45 -75 47 -77 +LINE Normal 40 -75 45 -75 +LINE Normal 47 -73 45 -75 +LINE Normal 47 -71 47 -73 +LINE Normal 45 -69 47 -71 +LINE Normal 40 -69 45 -69 +LINE Normal 47 0 45 -2 +LINE Normal 47 10 47 0 +LINE Normal 40 0 42 -2 +LINE Normal 45 -2 42 -2 +LINE Normal 40 10 40 0 +LINE Normal 47 4 40 4 +LINE Normal -36 4 -36 -4 +RECTANGLE Normal -80 -128 80 144 +CIRCLE Normal -66 33 -68 31 +CIRCLE Normal -65 34 -69 30 +CIRCLE Normal -64 35 -70 29 +CIRCLE Normal -66 65 -68 63 +CIRCLE Normal -65 66 -69 62 +CIRCLE Normal -64 67 -70 61 +TEXT 4 64 Center 2 Ref +WINDOW 0 8 -138 Left 2 +WINDOW 3 0 99 Center 2 +SYMATTR Value LTC1843 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LTC1843 +SYMATTR Description Ultralow Power Dual Comparator with Reference +PIN 80 16 NONE 0 +PINATTR PinName OUTA +PINATTR SpiceOrder 1 +PIN -48 144 BOTTOM 2 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -80 0 NONE 0 +PINATTR PinName INA+ +PINATTR SpiceOrder 3 +PIN -80 -80 NONE 0 +PINATTR PinName INB- +PINATTR SpiceOrder 4 +PIN 48 144 BOTTOM 2 +PINATTR PinName Hyst +PINATTR SpiceOrder 5 +PIN -80 64 NONE 0 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN 0 -128 TOP 2 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN 80 -64 NONE 0 +PINATTR PinName OUTB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LTC1998.asy b/spice/copy/sym/Comparators/LTC1998.asy new file mode 100755 index 0000000..75f2178 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC1998.asy @@ -0,0 +1,42 @@ +Version 4 +SymbolType CELL +LINE Normal 56 24 52 40 +LINE Normal 60 24 56 40 +LINE Normal 56 24 64 24 +LINE Normal 56 40 48 40 +LINE Normal 96 32 128 32 +LINE Normal 32 0 96 32 +LINE Normal 32 64 96 32 +LINE Normal 32 0 32 64 +LINE Normal 0 -96 0 16 +LINE Normal -6 48 32 48 +LINE Normal 32 16 0 16 +RECTANGLE Normal -128 -96 128 96 +RECTANGLE Normal -6 32 -54 64 +TEXT -52 48 Left 2 REF +TEXT 0 -36 Center 2 ADI +WINDOW 0 56 -112 Left 2 +WINDOW 3 40 208 Left 2 +SYMATTR Value LTC1998 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1998.sub +SYMATTR Value2 LTC1998 +SYMATTR Description 2.5µA, 1% Accurate SOT-23 Comparator and Voltage Reference for Battery Monitoring +PIN 0 -96 TOP 0 +PINATTR PinName BATT +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 0 +PINATTR PinName VL +PINATTR SpiceOrder 5 +PIN 128 32 NONE 0 +PINATTR PinName BATTLO +PINATTR SpiceOrder 6 +PIN 0 96 BOTTOM 0 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 0 +PINATTR PinName VTHA +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 0 +PINATTR PinName VHA +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Comparators/LTC6702.asy b/spice/copy/sym/Comparators/LTC6702.asy new file mode 100755 index 0000000..f95b6c1 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC6702.asy @@ -0,0 +1,39 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -4 -19 4 -19 +LINE Normal 0 -23 0 -15 +LINE Normal 0 18 3 18 +LINE Normal 3 23 3 18 +LINE Normal 3 23 -3 23 +LINE Normal -3 23 -3 12 +LINE Normal -3 12 3 12 +LINE Normal 0 -29 0 -48 +LINE Normal 0 29 0 48 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LTC6702 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6702 +SYMATTR Description Tiny µPower Low Voltage Comparator +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Comparators/LTC6752-2.asy b/spice/copy/sym/Comparators/LTC6752-2.asy new file mode 100755 index 0000000..b1e4f44 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC6752-2.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 16 -32 -80 +LINE Normal 48 -32 -32 16 +LINE Normal -32 -80 48 -32 +LINE Normal -22 -48 -30 -48 +LINE Normal -32 -48 -128 -48 +LINE Normal 128 -32 48 -32 +LINE Normal -22 -16 -30 -16 +LINE Normal -26 -12 -26 -20 +LINE Normal -32 -16 -128 -16 +RECTANGLE Normal 128 112 -128 -112 +WINDOW 3 48 32 Center 2 +WINDOW 0 30 -62 Left 2 +SYMATTR Value LTC6752-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6752-2 +SYMATTR Description 280MHz, 2.9ns Comparator with Rail-to-Rail Inputs and CMOS Outputs +PIN 48 -112 TOP 4 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -48 -112 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 48 112 BOTTOM 4 +PINATTR PinName Vee +PINATTR SpiceOrder 3 +PIN -128 -16 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN -128 -48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 5 +PIN -128 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -128 80 LEFT 8 +PINATTR PinName _LE/HYST +PINATTR SpiceOrder 7 +PIN 128 -32 NONE 8 +PINATTR PinName Q +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/LTC6752-3.asy b/spice/copy/sym/Comparators/LTC6752-3.asy new file mode 100755 index 0000000..eda72c0 --- /dev/null +++ b/spice/copy/sym/Comparators/LTC6752-3.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 16 -32 -80 +LINE Normal 48 -32 -32 16 +LINE Normal -32 -80 48 -32 +LINE Normal -22 -48 -30 -48 +LINE Normal -32 -48 -128 -48 +LINE Normal 128 -48 21 -48 +LINE Normal -22 -16 -30 -16 +LINE Normal -26 -12 -26 -20 +LINE Normal -32 -16 -128 -16 +LINE Normal 128 -16 37 -16 +RECTANGLE Normal 128 112 -128 -112 +CIRCLE Normal 37 -10 26 -21 +WINDOW 3 48 32 Center 2 +WINDOW 0 25 -65 Left 2 +SYMATTR Value LTC6752-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6752-3 +SYMATTR Description 280MHz, 2.9ns Comparator with Rail-to-Rail Inputs and CMOS Outputs +PIN 48 -112 TOP 4 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -48 -112 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 48 112 BOTTOM 4 +PINATTR PinName Vee +PINATTR SpiceOrder 3 +PIN -128 -16 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN -128 -48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 5 +PIN -128 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -128 80 LEFT 8 +PINATTR PinName _LE/HYST +PINATTR SpiceOrder 7 +PIN 128 -16 NONE 8 +PINATTR PinName _Q +PINATTR SpiceOrder 8 +PIN 128 -48 NONE 8 +PINATTR PinName Q +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Comparators/LTC6752.asy b/spice/copy/sym/Comparators/LTC6752.asy new file mode 100755 index 0000000..9dd434f --- /dev/null +++ b/spice/copy/sym/Comparators/LTC6752.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC6752 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6752 +SYMATTR Description 280MHz, 2.9ns Comparator with Rail-to-Rail Inputs and CMOS Outputs +PIN -32 80 NONE 0 +PINATTR PinName +In +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName -In +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Comparators/LTC6754.asy b/spice/copy/sym/Comparators/LTC6754.asy new file mode 100755 index 0000000..d360b6c --- /dev/null +++ b/spice/copy/sym/Comparators/LTC6754.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 16 -32 -80 +LINE Normal 48 -32 -32 16 +LINE Normal -32 -80 48 -32 +LINE Normal -22 -48 -30 -48 +LINE Normal -32 -48 -128 -48 +LINE Normal 128 -48 21 -48 +LINE Normal -22 -16 -30 -16 +LINE Normal -26 -12 -26 -20 +LINE Normal -32 -16 -128 -16 +LINE Normal 128 -16 37 -16 +RECTANGLE Normal 128 112 -128 -112 +CIRCLE Normal 37 -10 26 -21 +WINDOW 3 48 32 Center 2 +SYMATTR Value LTC6754 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LTC6754 +SYMATTR Description High Speed Rail-to-Rail Input Comparator with LVDS Compatible Outputs +PIN 48 -112 TOP 4 +PINATTR PinName VccO +PINATTR SpiceOrder 1 +PIN -48 -112 TOP 4 +PINATTR PinName VccI +PINATTR SpiceOrder 2 +PIN 48 112 BOTTOM 4 +PINATTR PinName Vee +PINATTR SpiceOrder 3 +PIN -128 -16 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN -128 -48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 5 +PIN -128 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -128 80 LEFT 8 +PINATTR PinName _LE/HYST +PINATTR SpiceOrder 7 +PIN 128 -16 NONE 8 +PINATTR PinName _Q +PINATTR SpiceOrder 8 +PIN 128 -48 NONE 8 +PINATTR PinName Q +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Comparators/RH1016.asy b/spice/copy/sym/Comparators/RH1016.asy new file mode 100755 index 0000000..09ac29f --- /dev/null +++ b/spice/copy/sym/Comparators/RH1016.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +LINE Normal -32 16 48 64 +LINE Normal -32 112 48 64 +LINE Normal -32 16 -32 112 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 16 0 36 +LINE Normal 0 112 0 92 +LINE Normal -4 44 4 44 +LINE Normal 0 40 0 48 +LINE Normal -20 96 -12 96 +LINE Normal -16 112 -16 104 +LINE Normal 16 112 16 84 +LINE Normal 48 48 24 48 +LINE Normal 36 80 48 80 +LINE Normal -4 76 -4 88 +LINE Normal 4 88 -4 88 +LINE Normal 16 76 20 76 +LINE Normal 20 80 20 76 +LINE Normal 20 80 12 80 +LINE Normal 12 80 12 72 +LINE Normal 12 72 20 72 +CIRCLE Normal 28 76 36 84 +WINDOW 0 32 24 Left 2 +WINDOW 3 32 104 Left 2 +SYMATTR Value RH1016 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1016 +SYMATTR Description Ultra Fast Precision Comparator +PIN 0 16 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 2 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -16 112 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 0 112 NONE 0 +PINATTR PinName LATCH +PINATTR SpiceOrder 5 +PIN 16 112 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 48 48 NONE 0 +PINATTR PinName OUT+ +PINATTR SpiceOrder 7 +PIN 48 80 NONE 0 +PINATTR PinName OUT- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Comparators/RH111.asy b/spice/copy/sym/Comparators/RH111.asy new file mode 100755 index 0000000..4f1e4da --- /dev/null +++ b/spice/copy/sym/Comparators/RH111.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -29 +LINE Normal 0 48 0 29 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal 16 48 16 19 +LINE Normal 12 12 20 12 +LINE Normal 12 12 12 8 +LINE Normal 20 16 12 16 +LINE Normal 20 16 20 12 +LINE Normal 12 8 20 8 +LINE Normal -4 22 4 22 +LINE Normal -16 38 -16 48 +LINE Normal -16 30 -12 30 +LINE Normal -20 34 -20 26 +LINE Normal -12 34 -20 34 +LINE Normal -12 34 -12 30 +LINE Normal -20 26 -12 26 +LINE Normal 16 -48 16 -19 +LINE Normal 13 -16 13 -8 +LINE Normal 18 -16 13 -16 +LINE Normal 18 -16 20 -14 +LINE Normal 18 -12 13 -12 +LINE Normal 18 -12 20 -14 +LINE Normal 18 -8 13 -8 +LINE Normal 18 -8 20 -10 +LINE Normal 18 -12 20 -10 +WINDOW 0 32 -32 Left 2 +WINDOW 3 32 32 Left 2 +SYMATTR Value RH111 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 RH111 +SYMATTR Description Voltage Comparator +PIN -16 48 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 2 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 16 -48 NONE 0 +PINATTR PinName BAL +PINATTR SpiceOrder 5 +PIN 16 48 NONE 0 +PINATTR PinName STROBE +PINATTR SpiceOrder 6 +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/2SK1828.asy b/spice/copy/sym/Contrib/Toshiba/nmos/2SK1828.asy new file mode 100755 index 0000000..7caa35c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/2SK1828.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_2SK1828 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/2SK1828.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/2SK2009.asy b/spice/copy/sym/Contrib/Toshiba/nmos/2SK2009.asy new file mode 100755 index 0000000..feaad24 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/2SK2009.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_2SK2009 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/2SK2009.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/2SK2313.asy b/spice/copy/sym/Contrib/Toshiba/nmos/2SK2313.asy new file mode 100755 index 0000000..7cd27e2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/2SK2313.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_2SK2313 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/2SK2313.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/2SK3564.asy b/spice/copy/sym/Contrib/Toshiba/nmos/2SK3564.asy new file mode 100755 index 0000000..015ddf2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/2SK3564.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_2SK3564 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/2SK3564.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K09FU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K09FU.asy new file mode 100755 index 0000000..9903a85 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K09FU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K09FU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K09FU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K121TU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K121TU.asy new file mode 100755 index 0000000..520f049 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K121TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K121TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K121TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15ACT.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15ACT.asy new file mode 100755 index 0000000..cde5d47 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15ACT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K15ACT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K15ACT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15ACTC.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15ACTC.asy new file mode 100755 index 0000000..1c44a6e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15ACTC.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K15ACTC +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K15ACTC.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15AFS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15AFS.asy new file mode 100755 index 0000000..d9ac114 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15AFS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K15AFS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K15AFS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15AFU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15AFU.asy new file mode 100755 index 0000000..994dc56 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15AFU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K15AFU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K15AFU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15AMFV.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15AMFV.asy new file mode 100755 index 0000000..692f04e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15AMFV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K15AMFV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K15AMFV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15CT.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15CT.asy new file mode 100755 index 0000000..b4b6685 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15CT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K15CT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K15CT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15F.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15F.asy new file mode 100755 index 0000000..1ef9839 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K15F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K15F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15FS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15FS.asy new file mode 100755 index 0000000..ea2dd8d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K15FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K15FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15FU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15FU.asy new file mode 100755 index 0000000..ca746ba --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K15FU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K15FU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K15FU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16CT.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16CT.asy new file mode 100755 index 0000000..3dc2077 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16CT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K16CT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K16CT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16CTC.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16CTC.asy new file mode 100755 index 0000000..65d02d9 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16CTC.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K16CTC +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K16CTC.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16FS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16FS.asy new file mode 100755 index 0000000..29e0700 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K16FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K16FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16FU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16FU.asy new file mode 100755 index 0000000..0ddd574 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16FU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K16FU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K16FU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16FV.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16FV.asy new file mode 100755 index 0000000..3f98530 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K16FV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K16FV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K16FV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K318R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K318R.asy new file mode 100755 index 0000000..4f869ba --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K318R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K318R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K318R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K324R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K324R.asy new file mode 100755 index 0000000..3ab06d4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K324R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K324R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K324R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K329R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K329R.asy new file mode 100755 index 0000000..7c97911 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K329R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K329R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K329R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K333R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K333R.asy new file mode 100755 index 0000000..3a23f9b --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K333R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K333R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K333R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K335R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K335R.asy new file mode 100755 index 0000000..b964a96 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K335R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K335R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K335R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K336R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K336R.asy new file mode 100755 index 0000000..8610e08 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K336R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K336R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K336R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K339R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K339R.asy new file mode 100755 index 0000000..81c82bd --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K339R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K339R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K339R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K341R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K341R.asy new file mode 100755 index 0000000..9091878 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K341R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K341R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K341R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K341TU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K341TU.asy new file mode 100755 index 0000000..cac96ff --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K341TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K341TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K341TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K344R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K344R.asy new file mode 100755 index 0000000..ce2ddfd --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K344R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K344R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K344R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K345R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K345R.asy new file mode 100755 index 0000000..0f141b3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K345R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K345R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K345R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35CT.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35CT.asy new file mode 100755 index 0000000..3fe1d3e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35CT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K35CT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K35CT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35CTC.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35CTC.asy new file mode 100755 index 0000000..418e94b --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35CTC.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K35CTC +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K35CTC.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35FS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35FS.asy new file mode 100755 index 0000000..095d457 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K35FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K35FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35MFV.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35MFV.asy new file mode 100755 index 0000000..b145c58 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K35MFV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K35MFV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K35MFV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K361R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K361R.asy new file mode 100755 index 0000000..a0b80f7 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K361R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K361R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K361R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K361TU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K361TU.asy new file mode 100755 index 0000000..07025f6 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K361TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K361TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K361TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K36FS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K36FS.asy new file mode 100755 index 0000000..102fa91 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K36FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K36FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K36FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K36MFV.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K36MFV.asy new file mode 100755 index 0000000..e52e059 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K36MFV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K36MFV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K36MFV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K36TU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K36TU.asy new file mode 100755 index 0000000..e0d8803 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K36TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K36TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K36TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K376R.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K376R.asy new file mode 100755 index 0000000..2f28e22 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K376R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K376R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K376R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K37CT.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K37CT.asy new file mode 100755 index 0000000..95d37ed --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K37CT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K37CT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K37CT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K37FS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K37FS.asy new file mode 100755 index 0000000..3a8605d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K37FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K37FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K37FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K37MFV.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K37MFV.asy new file mode 100755 index 0000000..db4a010 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K37MFV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K37MFV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K37MFV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K43FS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K43FS.asy new file mode 100755 index 0000000..f2548fc --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K43FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K43FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K43FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K44FS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K44FS.asy new file mode 100755 index 0000000..4c43b3c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K44FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K44FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K44FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K44MFV.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K44MFV.asy new file mode 100755 index 0000000..385fcb3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K44MFV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K44MFV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K44MFV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K48FU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K48FU.asy new file mode 100755 index 0000000..23e1851 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K48FU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K48FU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K48FU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56ACT.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56ACT.asy new file mode 100755 index 0000000..dc51466 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56ACT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K56ACT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K56ACT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56CT.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56CT.asy new file mode 100755 index 0000000..4559bd2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56CT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K56CT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K56CT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56FS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56FS.asy new file mode 100755 index 0000000..1f5f2b4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K56FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K56FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56MFV.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56MFV.asy new file mode 100755 index 0000000..474996e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K56MFV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K56MFV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K56MFV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K59CTB.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K59CTB.asy new file mode 100755 index 0000000..2acb7b7 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K59CTB.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K59CTB +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K59CTB.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K62TU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K62TU.asy new file mode 100755 index 0000000..a62aee6 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K62TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K62TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K62TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K7002KF.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K7002KF.asy new file mode 100755 index 0000000..7327bfc --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K7002KF.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K7002KF +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K7002KF.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K7002KFU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K7002KFU.asy new file mode 100755 index 0000000..aa9a910 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K7002KFU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K7002KFU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K7002KFU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K72KCT.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K72KCT.asy new file mode 100755 index 0000000..0a96b55 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K72KCT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K72KCT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K72KCT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K72KFS.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K72KFS.asy new file mode 100755 index 0000000..3546d84 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM3K72KFS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM3K72KFS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM3K72KFS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K202FE.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K202FE.asy new file mode 100755 index 0000000..f7fe863 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K202FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K202FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K202FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K204FE.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K204FE.asy new file mode 100755 index 0000000..7ea0f96 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K204FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K204FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K204FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K208FE.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K208FE.asy new file mode 100755 index 0000000..866fef9 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K208FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K208FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K208FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K211FE.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K211FE.asy new file mode 100755 index 0000000..c6ebcc6 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K211FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K211FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K211FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K217FE.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K217FE.asy new file mode 100755 index 0000000..b37eef4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K217FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K217FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K217FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K24FE.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K24FE.asy new file mode 100755 index 0000000..3ade90a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K24FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K24FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K24FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K341NU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K341NU.asy new file mode 100755 index 0000000..23c8515 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K341NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K341NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K341NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K361NU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K361NU.asy new file mode 100755 index 0000000..ea3ca23 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K361NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K361NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K361NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K403TU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K403TU.asy new file mode 100755 index 0000000..305c7e1 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K403TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K403TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K403TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K504NU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K504NU.asy new file mode 100755 index 0000000..838e55e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K504NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K504NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K504NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K513NU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K513NU.asy new file mode 100755 index 0000000..f5fec39 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K513NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K513NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K513NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K514NU.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K514NU.asy new file mode 100755 index 0000000..6059c50 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K514NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K514NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K514NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K781G.asy b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K781G.asy new file mode 100755 index 0000000..e361ec8 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/SSM6K781G.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_SSM6K781G +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/SSM6K781G.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/T2N7002BK.asy b/spice/copy/sym/Contrib/Toshiba/nmos/T2N7002BK.asy new file mode 100755 index 0000000..b5c3707 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/T2N7002BK.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_T2N7002BK +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/T2N7002BK.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK040N65Z.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK040N65Z.asy new file mode 100755 index 0000000..0337084 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK040N65Z.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK040N65Z +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK040N65Z.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK100L60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK100L60W_G0_00.asy new file mode 100755 index 0000000..1b0e6f7 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK100L60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK100L60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK100L60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10A50W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10A50W.asy new file mode 100755 index 0000000..4e29659 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10A50W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10A50W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10A50W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10A60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10A60W.asy new file mode 100755 index 0000000..d735de4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10A60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10A60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10A60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10A60W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10A60W5_G0_00.asy new file mode 100755 index 0000000..c70b4c6 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10A60W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10A60W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10A60W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10A80W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10A80W.asy new file mode 100755 index 0000000..8007fc5 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10A80W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10A80W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10A80W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10E60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10E60W.asy new file mode 100755 index 0000000..07e8de6 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10E60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10E60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10E60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10E80W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10E80W.asy new file mode 100755 index 0000000..9e9dfc6 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10E80W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10E80W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10E80W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10P50W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10P50W.asy new file mode 100755 index 0000000..0320e5e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10P50W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10P50W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10P50W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10P60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10P60W.asy new file mode 100755 index 0000000..e074bdd --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10P60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10P60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10P60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10Q60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10Q60W.asy new file mode 100755 index 0000000..b0f4e5c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10Q60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10Q60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10Q60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK10V60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK10V60W.asy new file mode 100755 index 0000000..b9b95b0 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK10V60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK10V60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK10V60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK11A65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK11A65W.asy new file mode 100755 index 0000000..d94b1c9 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK11A65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK11A65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK11A65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK11P65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK11P65W.asy new file mode 100755 index 0000000..c9d966d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK11P65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK11P65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK11P65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK11Q65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK11Q65W.asy new file mode 100755 index 0000000..82fa927 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK11Q65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK11Q65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK11Q65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12A50W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12A50W.asy new file mode 100755 index 0000000..b43807f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12A50W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12A50W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12A50W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12A60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12A60W_G0_00.asy new file mode 100755 index 0000000..0d8d853 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12A60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12A60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12A60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12A80W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12A80W.asy new file mode 100755 index 0000000..4785ffb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12A80W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12A80W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12A80W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12E60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12E60W.asy new file mode 100755 index 0000000..12f175f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12E60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12E60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12E60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12E80W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12E80W.asy new file mode 100755 index 0000000..625ff1e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12E80W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12E80W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12E80W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12J60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12J60W.asy new file mode 100755 index 0000000..9ccdc2d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12J60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12J60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12J60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12P50W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12P50W.asy new file mode 100755 index 0000000..ef98f92 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12P50W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12P50W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12P50W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12P60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12P60W.asy new file mode 100755 index 0000000..b1dc78a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12P60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12P60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12P60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12Q60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12Q60W.asy new file mode 100755 index 0000000..197e24d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12Q60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12Q60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12Q60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK12V60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK12V60W.asy new file mode 100755 index 0000000..faaa7c4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK12V60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK12V60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK12V60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK14A65W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK14A65W5.asy new file mode 100755 index 0000000..142752f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK14A65W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK14A65W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK14A65W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK14A65W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK14A65W_G0_00.asy new file mode 100755 index 0000000..5d5110c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK14A65W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK14A65W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK14A65W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK14E65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK14E65W.asy new file mode 100755 index 0000000..8842f75 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK14E65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK14E65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK14E65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK14E65W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK14E65W5.asy new file mode 100755 index 0000000..703809a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK14E65W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK14E65W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK14E65W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK14G65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK14G65W.asy new file mode 100755 index 0000000..8d27e17 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK14G65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK14G65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK14G65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK14G65W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK14G65W5.asy new file mode 100755 index 0000000..fcd54a0 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK14G65W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK14G65W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK14G65W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK14N65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK14N65W.asy new file mode 100755 index 0000000..8091725 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK14N65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK14N65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK14N65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK14N65W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK14N65W5.asy new file mode 100755 index 0000000..8928c69 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK14N65W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK14N65W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK14N65W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK14V65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK14V65W.asy new file mode 100755 index 0000000..73343e8 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK14V65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK14V65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK14V65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16A60W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16A60W5_G0_00.asy new file mode 100755 index 0000000..3815e5d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16A60W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16A60W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16A60W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16A60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16A60W_G0_00.asy new file mode 100755 index 0000000..732e66e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16A60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16A60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16A60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16E60W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16E60W5_G0_00.asy new file mode 100755 index 0000000..7e77b38 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16E60W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16E60W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16E60W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16E60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16E60W_G0_00.asy new file mode 100755 index 0000000..1ae2853 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16E60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16E60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16E60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16G60W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16G60W5_G0_00.asy new file mode 100755 index 0000000..2937d3e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16G60W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16G60W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16G60W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16G60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16G60W_G0_00.asy new file mode 100755 index 0000000..d14b2cc --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16G60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16G60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16G60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16J60W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16J60W5_G0_00.asy new file mode 100755 index 0000000..91c80db --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16J60W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16J60W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16J60W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16J60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16J60W_G0_00.asy new file mode 100755 index 0000000..a7afb72 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16J60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16J60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16J60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16N60W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16N60W5_G0_00.asy new file mode 100755 index 0000000..5ecf0e2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16N60W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16N60W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16N60W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16N60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16N60W_G0_00.asy new file mode 100755 index 0000000..440a8ea --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16N60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16N60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16N60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16V60W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16V60W5_G0_00.asy new file mode 100755 index 0000000..7d44057 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16V60W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16V60W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16V60W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK16V60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK16V60W_G0_00.asy new file mode 100755 index 0000000..3696f1a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK16V60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK16V60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK16V60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK17A65W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK17A65W5_G0_00.asy new file mode 100755 index 0000000..4540c14 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK17A65W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK17A65W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK17A65W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK17A80W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK17A80W.asy new file mode 100755 index 0000000..d1c3024 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK17A80W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK17A80W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK17A80W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK17E65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK17E65W.asy new file mode 100755 index 0000000..41aeb35 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK17E65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK17E65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK17E65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK17E80W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK17E80W.asy new file mode 100755 index 0000000..0492dd8 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK17E80W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK17E80W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK17E80W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK17N65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK17N65W.asy new file mode 100755 index 0000000..2df87fd --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK17N65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK17N65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK17N65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK19A50W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK19A50W.asy new file mode 100755 index 0000000..06067bb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK19A50W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK19A50W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK19A50W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK1K0A60F.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK1K0A60F.asy new file mode 100755 index 0000000..ec7c625 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK1K0A60F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK1K0A60F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK1K0A60F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK1K2A60F.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK1K2A60F.asy new file mode 100755 index 0000000..6262221 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK1K2A60F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK1K2A60F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK1K2A60F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK1K7A60F.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK1K7A60F.asy new file mode 100755 index 0000000..01b7b48 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK1K7A60F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK1K7A60F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK1K7A60F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK1K9A60F.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK1K9A60F.asy new file mode 100755 index 0000000..8651e0c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK1K9A60F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK1K9A60F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK1K9A60F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20A60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20A60W5.asy new file mode 100755 index 0000000..1a9ac7a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20A60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20A60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20A60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20A60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20A60W_G0_00.asy new file mode 100755 index 0000000..a4eb5ee --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20A60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20A60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20A60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20E60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20E60W5.asy new file mode 100755 index 0000000..dc94b2e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20E60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20E60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20E60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20E60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20E60W_G0_00.asy new file mode 100755 index 0000000..4cbe7fc --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20E60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20E60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20E60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20G60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20G60W_G0_00.asy new file mode 100755 index 0000000..7bbdece --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20G60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20G60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20G60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20J60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20J60W5.asy new file mode 100755 index 0000000..ecd1701 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20J60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20J60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20J60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20J60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20J60W_G0_00.asy new file mode 100755 index 0000000..1c1d875 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20J60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20J60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20J60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20N60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20N60W5.asy new file mode 100755 index 0000000..13e72ea --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20N60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20N60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20N60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20N60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20N60W_G0_00.asy new file mode 100755 index 0000000..392e36f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20N60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20N60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20N60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20V60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20V60W5.asy new file mode 100755 index 0000000..72fbbc0 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20V60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20V60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20V60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK20V60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK20V60W_G0_00.asy new file mode 100755 index 0000000..be6cfab --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK20V60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK20V60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK20V60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK22A65X.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK22A65X.asy new file mode 100755 index 0000000..62d7145 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK22A65X.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK22A65X +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK22A65X.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK22A65X5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK22A65X5.asy new file mode 100755 index 0000000..a7ab2d4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK22A65X5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK22A65X5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK22A65X5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK22V65X5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK22V65X5.asy new file mode 100755 index 0000000..29ed294 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK22V65X5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK22V65X5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK22V65X5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK25A60X5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK25A60X5_G0_00.asy new file mode 100755 index 0000000..db83916 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK25A60X5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK25A60X5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK25A60X5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK25A60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK25A60X_G0_00.asy new file mode 100755 index 0000000..1cfbb67 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK25A60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK25A60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK25A60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK25E60X5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK25E60X5_G0_00.asy new file mode 100755 index 0000000..f9139df --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK25E60X5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK25E60X5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK25E60X5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK25E60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK25E60X_G0_00.asy new file mode 100755 index 0000000..570956d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK25E60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK25E60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK25E60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK25N60X5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK25N60X5_G0_00.asy new file mode 100755 index 0000000..029e37b --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK25N60X5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK25N60X5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK25N60X5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK25N60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK25N60X_G0_00.asy new file mode 100755 index 0000000..c5ae36f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK25N60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK25N60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK25N60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK25V60X5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK25V60X5_G0_00.asy new file mode 100755 index 0000000..99f239a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK25V60X5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK25V60X5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK25V60X5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK25V60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK25V60X_G0_00.asy new file mode 100755 index 0000000..f4bd36b --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK25V60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK25V60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK25V60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK25Z60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK25Z60X_G0_00.asy new file mode 100755 index 0000000..59f7537 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK25Z60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK25Z60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK25Z60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK28A65W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK28A65W_G0_00.asy new file mode 100755 index 0000000..b050103 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK28A65W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK28A65W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK28A65W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK28E65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK28E65W.asy new file mode 100755 index 0000000..db24030 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK28E65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK28E65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK28E65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK28N65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK28N65W.asy new file mode 100755 index 0000000..284b695 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK28N65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK28N65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK28N65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK28N65W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK28N65W5_G0_00.asy new file mode 100755 index 0000000..092d025 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK28N65W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK28N65W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK28N65W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK28V65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK28V65W.asy new file mode 100755 index 0000000..3dd8329 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK28V65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK28V65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK28V65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK28V65W5_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK28V65W5_G0_00.asy new file mode 100755 index 0000000..c323106 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK28V65W5_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK28V65W5_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK28V65W5_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK290A60Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK290A60Y.asy new file mode 100755 index 0000000..a39a67c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK290A60Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK290A60Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK290A60Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK290A65Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK290A65Y.asy new file mode 100755 index 0000000..7e64424 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK290A65Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK290A65Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK290A65Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK290P60Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK290P60Y.asy new file mode 100755 index 0000000..f0261bb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK290P60Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK290P60Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK290P60Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK290P65Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK290P65Y.asy new file mode 100755 index 0000000..af5a854 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK290P65Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK290P65Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK290P65Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK2K2A60F.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK2K2A60F.asy new file mode 100755 index 0000000..9583d9b --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK2K2A60F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK2K2A60F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK2K2A60F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31A60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31A60W_G0_00.asy new file mode 100755 index 0000000..14b5799 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31A60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31A60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31A60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31E60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31E60W_G0_00.asy new file mode 100755 index 0000000..204f0e3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31E60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31E60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31E60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31E60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31E60X_G0_00.asy new file mode 100755 index 0000000..129350e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31E60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31E60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31E60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31J60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31J60W5.asy new file mode 100755 index 0000000..12351f3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31J60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31J60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31J60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31J60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31J60W_G0_00.asy new file mode 100755 index 0000000..8c44c2d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31J60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31J60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31J60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31N60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31N60W5.asy new file mode 100755 index 0000000..b50e6fa --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31N60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31N60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31N60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31N60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31N60W_G0_00.asy new file mode 100755 index 0000000..c6f25bc --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31N60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31N60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31N60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31N60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31N60X_G0_00.asy new file mode 100755 index 0000000..d26b473 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31N60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31N60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31N60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31V60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31V60W5.asy new file mode 100755 index 0000000..c2aa990 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31V60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31V60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31V60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31V60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31V60W_G0_00.asy new file mode 100755 index 0000000..29d9ca0 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31V60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31V60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31V60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31V60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31V60X_G0_00.asy new file mode 100755 index 0000000..905ba65 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31V60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31V60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31V60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK31Z60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK31Z60X_G0_00.asy new file mode 100755 index 0000000..bcf8ad4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK31Z60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK31Z60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK31Z60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK32A12N1.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK32A12N1.asy new file mode 100755 index 0000000..4d791e3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK32A12N1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK32A12N1 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK32A12N1.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK32E12N1.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK32E12N1.asy new file mode 100755 index 0000000..36af8e7 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK32E12N1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK32E12N1 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK32E12N1.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK35A65W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK35A65W5.asy new file mode 100755 index 0000000..c6d65a1 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK35A65W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK35A65W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK35A65W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK35A65W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK35A65W_G0_00.asy new file mode 100755 index 0000000..d8f6fb4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK35A65W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK35A65W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK35A65W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK35N65W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK35N65W5.asy new file mode 100755 index 0000000..aff92da --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK35N65W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK35N65W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK35N65W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK35N65W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK35N65W_G0_00.asy new file mode 100755 index 0000000..c402099 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK35N65W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK35N65W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK35N65W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK380A60Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK380A60Y.asy new file mode 100755 index 0000000..584ca75 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK380A60Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK380A60Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK380A60Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK380A65Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK380A65Y.asy new file mode 100755 index 0000000..17a91ab --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK380A65Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK380A65Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK380A65Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK380P60Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK380P60Y.asy new file mode 100755 index 0000000..414de86 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK380P60Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK380P60Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK380P60Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK380P65Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK380P65Y.asy new file mode 100755 index 0000000..5697efc --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK380P65Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK380P65Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK380P65Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK39A60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK39A60W_G0_00.asy new file mode 100755 index 0000000..fcf0fa8 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK39A60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK39A60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK39A60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK39J60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK39J60W5.asy new file mode 100755 index 0000000..befca60 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK39J60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK39J60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK39J60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK39J60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK39J60W_G0_00.asy new file mode 100755 index 0000000..84e9a38 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK39J60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK39J60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK39J60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK39N60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK39N60W5.asy new file mode 100755 index 0000000..f388773 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK39N60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK39N60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK39N60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK39N60W_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK39N60W_G0_00.asy new file mode 100755 index 0000000..f61893f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK39N60W_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK39N60W_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK39N60W_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK39N60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK39N60X_G0_00.asy new file mode 100755 index 0000000..01c3aa4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK39N60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK39N60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK39N60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK39Z60X_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK39Z60X_G0_00.asy new file mode 100755 index 0000000..47b9b45 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK39Z60X_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK39Z60X_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK39Z60X_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK3R1A04PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R1A04PL_G0_00.asy new file mode 100755 index 0000000..f955def --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R1A04PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK3R1A04PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK3R1A04PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK3R1E04PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R1E04PL_G0_00.asy new file mode 100755 index 0000000..ddb23ac --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R1E04PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK3R1E04PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK3R1E04PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK3R1P04PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R1P04PL.asy new file mode 100755 index 0000000..531002f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R1P04PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK3R1P04PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK3R1P04PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK3R2E06PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R2E06PL.asy new file mode 100755 index 0000000..0ef569f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R2E06PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK3R2E06PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK3R2E06PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK3R3A06PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R3A06PL.asy new file mode 100755 index 0000000..cc9d351 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK3R3A06PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK3R3A06PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK3R3A06PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK42A12N1.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK42A12N1.asy new file mode 100755 index 0000000..ab1ad43 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK42A12N1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK42A12N1 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK42A12N1.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK42E12N1.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK42E12N1.asy new file mode 100755 index 0000000..ca578a3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK42E12N1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK42E12N1 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK42E12N1.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK49N65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK49N65W.asy new file mode 100755 index 0000000..6df5c12 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK49N65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK49N65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK49N65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK49N65W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK49N65W5.asy new file mode 100755 index 0000000..374d713 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK49N65W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK49N65W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK49N65W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK4K1A60F.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK4K1A60F.asy new file mode 100755 index 0000000..4727e0e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK4K1A60F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK4K1A60F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK4K1A60F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK4R3A06PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK4R3A06PL.asy new file mode 100755 index 0000000..905f3e3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK4R3A06PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK4R3A06PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK4R3A06PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK4R3E06PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK4R3E06PL.asy new file mode 100755 index 0000000..0501c24 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK4R3E06PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK4R3E06PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK4R3E06PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK4R4P06PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK4R4P06PL.asy new file mode 100755 index 0000000..ce98ad3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK4R4P06PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK4R4P06PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK4R4P06PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK560A60Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK560A60Y.asy new file mode 100755 index 0000000..09fa80a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK560A60Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK560A60Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK560A60Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK560A65Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK560A65Y.asy new file mode 100755 index 0000000..6a5623d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK560A65Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK560A65Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK560A65Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK560P60Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK560P60Y.asy new file mode 100755 index 0000000..18c724e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK560P60Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK560P60Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK560P60Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK560P65Y.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK560P65Y.asy new file mode 100755 index 0000000..bf29251 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK560P65Y.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK560P65Y +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK560P65Y.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK56A12N1.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK56A12N1.asy new file mode 100755 index 0000000..5165c50 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK56A12N1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK56A12N1 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK56A12N1.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK56E12N1.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK56E12N1.asy new file mode 100755 index 0000000..1ffa5e9 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK56E12N1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK56E12N1 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK56E12N1.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK5R1E06PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK5R1E06PL.asy new file mode 100755 index 0000000..12aaf7f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK5R1E06PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK5R1E06PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK5R1E06PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK5R3A06PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK5R3A06PL.asy new file mode 100755 index 0000000..66caeb5 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK5R3A06PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK5R3A06PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK5R3A06PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK62J60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK62J60W.asy new file mode 100755 index 0000000..2404672 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK62J60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK62J60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK62J60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK62J60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK62J60W5.asy new file mode 100755 index 0000000..06d1368 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK62J60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK62J60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK62J60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK62N60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK62N60W.asy new file mode 100755 index 0000000..d777198 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK62N60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK62N60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK62N60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK62N60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK62N60W5.asy new file mode 100755 index 0000000..7ec7c62 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK62N60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK62N60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK62N60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK62N60X.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK62N60X.asy new file mode 100755 index 0000000..1167061 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK62N60X.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK62N60X +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK62N60X.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK62Z60X.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK62Z60X.asy new file mode 100755 index 0000000..37d2612 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK62Z60X.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK62Z60X +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK62Z60X.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK650A60F.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK650A60F.asy new file mode 100755 index 0000000..237e979 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK650A60F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK650A60F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK650A60F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK6A60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK6A60W.asy new file mode 100755 index 0000000..77240ef --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK6A60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK6A60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK6A60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK6A65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK6A65W.asy new file mode 100755 index 0000000..de16620 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK6A65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK6A65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK6A65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK6P60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK6P60W.asy new file mode 100755 index 0000000..81fee4d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK6P60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK6P60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK6P60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK6P65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK6P65W.asy new file mode 100755 index 0000000..6dd2ad4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK6P65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK6P65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK6P65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK6Q60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK6Q60W.asy new file mode 100755 index 0000000..42cbcdd --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK6Q60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK6Q60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK6Q60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK6Q65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK6Q65W.asy new file mode 100755 index 0000000..03debeb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK6Q65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK6Q65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK6Q65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK6R7P06PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK6R7P06PL.asy new file mode 100755 index 0000000..bce63b8 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK6R7P06PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK6R7P06PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK6R7P06PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK72A12N1.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK72A12N1.asy new file mode 100755 index 0000000..6acb708 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK72A12N1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK72A12N1 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK72A12N1.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK72E12N1.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK72E12N1.asy new file mode 100755 index 0000000..d5f28b8 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK72E12N1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK72E12N1 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK72E12N1.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK750A60F.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK750A60F.asy new file mode 100755 index 0000000..a671ddd --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK750A60F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK750A60F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK750A60F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7A60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7A60W.asy new file mode 100755 index 0000000..2cb238c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7A60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7A60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7A60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7A60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7A60W5.asy new file mode 100755 index 0000000..c0505f5 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7A60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7A60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7A60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7A65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7A65W.asy new file mode 100755 index 0000000..d9995f7 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7A65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7A65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7A65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7A80W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7A80W.asy new file mode 100755 index 0000000..8369552 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7A80W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7A80W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7A80W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7E80W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7E80W.asy new file mode 100755 index 0000000..edcc414 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7E80W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7E80W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7E80W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7P60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7P60W.asy new file mode 100755 index 0000000..cb23642 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7P60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7P60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7P60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7P60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7P60W5.asy new file mode 100755 index 0000000..d7bdf80 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7P60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7P60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7P60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7P65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7P65W.asy new file mode 100755 index 0000000..427ccdb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7P65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7P65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7P65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7Q60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7Q60W.asy new file mode 100755 index 0000000..e5e6347 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7Q60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7Q60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7Q60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK7Q65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK7Q65W.asy new file mode 100755 index 0000000..72a8f2a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK7Q65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK7Q65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK7Q65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK8A60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK8A60W.asy new file mode 100755 index 0000000..2d69c8b --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK8A60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK8A60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK8A60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK8A60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK8A60W5.asy new file mode 100755 index 0000000..dad576c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK8A60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK8A60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK8A60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK8A65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK8A65W.asy new file mode 100755 index 0000000..06f8057 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK8A65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK8A65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK8A65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK8P60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK8P60W.asy new file mode 100755 index 0000000..b6a73e8 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK8P60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK8P60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK8P60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK8P60W5.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK8P60W5.asy new file mode 100755 index 0000000..e5bd8cd --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK8P60W5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK8P60W5 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK8P60W5.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK8P65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK8P65W.asy new file mode 100755 index 0000000..cd5bf20 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK8P65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK8P65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK8P65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK8Q60W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK8Q60W.asy new file mode 100755 index 0000000..156991f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK8Q60W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK8Q60W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK8Q60W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK8Q65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK8Q65W.asy new file mode 100755 index 0000000..b936f00 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK8Q65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK8Q65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK8Q65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK8R2E06PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK8R2E06PL.asy new file mode 100755 index 0000000..997c851 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK8R2E06PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK8R2E06PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK8R2E06PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK9A65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK9A65W.asy new file mode 100755 index 0000000..d9fdf9b --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK9A65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK9A65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK9A65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK9P65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK9P65W.asy new file mode 100755 index 0000000..d9a4245 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK9P65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK9P65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK9P65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TK9Q65W.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TK9Q65W.asy new file mode 100755 index 0000000..8804db7 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TK9Q65W.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TK9Q65W +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TK9Q65W.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH1110ENH_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1110ENH_G0_00.asy new file mode 100755 index 0000000..20a9745 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1110ENH_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH1110ENH_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH1110ENH_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH1110FNH_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1110FNH_G0_00.asy new file mode 100755 index 0000000..14cebe4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1110FNH_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH1110FNH_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH1110FNH_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH1500CNH_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1500CNH_G0_00.asy new file mode 100755 index 0000000..0f3f398 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1500CNH_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH1500CNH_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH1500CNH_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R005PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R005PL_G0_00.asy new file mode 100755 index 0000000..ac1d27a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R005PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH1R005PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH1R005PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R204PB_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R204PB_G0_00.asy new file mode 100755 index 0000000..42cafa4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R204PB_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH1R204PB_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH1R204PB_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R204PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R204PL_G0_00.asy new file mode 100755 index 0000000..bbbf43c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R204PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH1R204PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH1R204PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R306P1_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R306P1_G0_00.asy new file mode 100755 index 0000000..07f8ef7 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R306P1_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH1R306P1_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH1R306P1_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R405PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R405PL_G0_00.asy new file mode 100755 index 0000000..d3170bf --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH1R405PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH1R405PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH1R405PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH2010FNH_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2010FNH_G0_00.asy new file mode 100755 index 0000000..3be90e4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2010FNH_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH2010FNH_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH2010FNH_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH2900ENH_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2900ENH_G0_00.asy new file mode 100755 index 0000000..2c27176 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2900ENH_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH2900ENH_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH2900ENH_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R003PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R003PL_G0_00.asy new file mode 100755 index 0000000..46f38ac --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R003PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH2R003PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH2R003PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R104PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R104PL_G0_00.asy new file mode 100755 index 0000000..b92d3e5 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R104PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH2R104PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH2R104PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R506PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R506PL_G0_00.asy new file mode 100755 index 0000000..fc3d84a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R506PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH2R506PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH2R506PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R805PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R805PL_G0_00.asy new file mode 100755 index 0000000..21e9578 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R805PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH2R805PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH2R805PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R903PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R903PL_G0_00.asy new file mode 100755 index 0000000..4359807 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH2R903PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH2R903PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH2R903PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH3300CNH.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3300CNH.asy new file mode 100755 index 0000000..abae6b4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3300CNH.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH3300CNH +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH3300CNH.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R003PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R003PL_G0_00.asy new file mode 100755 index 0000000..8dbec0e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R003PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH3R003PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH3R003PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R506PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R506PL_G0_00.asy new file mode 100755 index 0000000..fb0f017 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R506PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH3R506PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH3R506PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R704PC_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R704PC_G0_00.asy new file mode 100755 index 0000000..38ddaf7 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R704PC_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH3R704PC_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH3R704PC_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R704PL.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R704PL.asy new file mode 100755 index 0000000..ee30c2f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R704PL.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH3R704PL +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH3R704PL.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R70APL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R70APL_G0_00.asy new file mode 100755 index 0000000..1821395 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH3R70APL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH3R70APL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH3R70APL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH4R803PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH4R803PL_G0_00.asy new file mode 100755 index 0000000..0ce1e5f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH4R803PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH4R803PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH4R803PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH5200FNH_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH5200FNH_G0_00.asy new file mode 100755 index 0000000..2f5569a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH5200FNH_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH5200FNH_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH5200FNH_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH5900CNH.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH5900CNH.asy new file mode 100755 index 0000000..a2549c1 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH5900CNH.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH5900CNH +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH5900CNH.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH5R60APL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH5R60APL_G0_00.asy new file mode 100755 index 0000000..e711376 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH5R60APL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH5R60APL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH5R60APL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH6400ENH_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH6400ENH_G0_00.asy new file mode 100755 index 0000000..71ff35e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH6400ENH_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH6400ENH_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH6400ENH_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH6R004PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH6R004PL_G0_00.asy new file mode 100755 index 0000000..9b35c53 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH6R004PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH6R004PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH6R004PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH7R006PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH7R006PL_G0_00.asy new file mode 100755 index 0000000..c139632 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH7R006PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH7R006PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH7R006PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH7R204PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH7R204PL_G0_00.asy new file mode 100755 index 0000000..2eedda0 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH7R204PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH7R204PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH7R204PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPH9R506PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPH9R506PL_G0_00.asy new file mode 100755 index 0000000..8e9c0cc --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPH9R506PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPH9R506PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPH9R506PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPHR6503PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPHR6503PL_G0_00.asy new file mode 100755 index 0000000..309ceb2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPHR6503PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPHR6503PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPHR6503PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPHR8504PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPHR8504PL_G0_00.asy new file mode 100755 index 0000000..06f8823 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPHR8504PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPHR8504PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPHR8504PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPHR9203PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPHR9203PL_G0_00.asy new file mode 100755 index 0000000..39058d0 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPHR9203PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPHR9203PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPHR9203PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN11006PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN11006PL_G0_00.asy new file mode 100755 index 0000000..9f73344 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN11006PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN11006PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN11006PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN1110ENH_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN1110ENH_G0_00.asy new file mode 100755 index 0000000..2099ebb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN1110ENH_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN1110ENH_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN1110ENH_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN1200APL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN1200APL_G0_00.asy new file mode 100755 index 0000000..9cb3543 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN1200APL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN1200APL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN1200APL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN1R603PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN1R603PL_G0_00.asy new file mode 100755 index 0000000..eeac738 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN1R603PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN1R603PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN1R603PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN2010FNH_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN2010FNH_G0_00.asy new file mode 100755 index 0000000..1d936b8 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN2010FNH_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN2010FNH_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN2010FNH_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN2R304PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN2R304PL_G0_00.asy new file mode 100755 index 0000000..9379e72 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN2R304PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN2R304PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN2R304PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN2R805PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN2R805PL_G0_00.asy new file mode 100755 index 0000000..18045cb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN2R805PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN2R805PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN2R805PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN2R903PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN2R903PL_G0_00.asy new file mode 100755 index 0000000..3f24160 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN2R903PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN2R903PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN2R903PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN3R704PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN3R704PL_G0_00.asy new file mode 100755 index 0000000..8cf7283 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN3R704PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN3R704PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN3R704PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN4R806PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN4R806PL_G0_00.asy new file mode 100755 index 0000000..17664c2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN4R806PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN4R806PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN4R806PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN5900CNH.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN5900CNH.asy new file mode 100755 index 0000000..ec5dc14 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN5900CNH.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN5900CNH +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN5900CNH.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN5R203PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN5R203PL_G0_00.asy new file mode 100755 index 0000000..970516c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN5R203PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN5R203PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN5R203PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN7R006PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN7R006PL_G0_00.asy new file mode 100755 index 0000000..3702e84 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN7R006PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN7R006PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN7R006PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPN7R504PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPN7R504PL_G0_00.asy new file mode 100755 index 0000000..4317ce5 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPN7R504PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPN7R504PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPN7R504PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPW1500CNH.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPW1500CNH.asy new file mode 100755 index 0000000..4e9d8d2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPW1500CNH.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPW1500CNH +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPW1500CNH.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPW1R005PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPW1R005PL_G0_00.asy new file mode 100755 index 0000000..eec6189 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPW1R005PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPW1R005PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPW1R005PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPW1R306PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPW1R306PL_G0_00.asy new file mode 100755 index 0000000..6af95c3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPW1R306PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPW1R306PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPW1R306PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPW2900ENH.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPW2900ENH.asy new file mode 100755 index 0000000..379b2ee --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPW2900ENH.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPW2900ENH +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPW2900ENH.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPW3R70APL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPW3R70APL_G0_00.asy new file mode 100755 index 0000000..f10a0c4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPW3R70APL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPW3R70APL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPW3R70APL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPW5200FNH.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPW5200FNH.asy new file mode 100755 index 0000000..10e7dac --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPW5200FNH.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPW5200FNH +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPW5200FNH.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPWR6003PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPWR6003PL_G0_00.asy new file mode 100755 index 0000000..95558df --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPWR6003PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPWR6003PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPWR6003PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPWR7904PB_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPWR7904PB_G0_00.asy new file mode 100755 index 0000000..aac3ff2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPWR7904PB_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPWR7904PB_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPWR7904PB_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/nmos/TPWR8004PL_G0_00.asy b/spice/copy/sym/Contrib/Toshiba/nmos/TPWR8004PL_G0_00.asy new file mode 100755 index 0000000..32c1027 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/nmos/TPWR8004PL_G0_00.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel NMOS_TPWR8004PL_G0_00 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/nmos/TPWR8004PL_G0_00_LTspice_rev1_unenc.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/2SJ168.asy b/spice/copy/sym/Contrib/Toshiba/pmos/2SJ168.asy new file mode 100755 index 0000000..4b0624d --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/2SJ168.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_2SJ168 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/2SJ168.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/2SJ305.asy b/spice/copy/sym/Contrib/Toshiba/pmos/2SJ305.asy new file mode 100755 index 0000000..f82b567 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/2SJ305.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_2SJ305 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/2SJ305.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J09FU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J09FU.asy new file mode 100755 index 0000000..31430fd --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J09FU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J09FU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J09FU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J117TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J117TU.asy new file mode 100755 index 0000000..25aaeec --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J117TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J117TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J117TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J118TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J118TU.asy new file mode 100755 index 0000000..de5d383 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J118TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J118TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J118TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J120TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J120TU.asy new file mode 100755 index 0000000..f9b7780 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J120TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J120TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J120TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J130TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J130TU.asy new file mode 100755 index 0000000..e8f068a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J130TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J130TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J130TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J132TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J132TU.asy new file mode 100755 index 0000000..fbb53e3 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J132TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J132TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J132TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J133TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J133TU.asy new file mode 100755 index 0000000..09918a2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J133TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J133TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J133TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J134TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J134TU.asy new file mode 100755 index 0000000..83380c9 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J134TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J134TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J134TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J135TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J135TU.asy new file mode 100755 index 0000000..e3f7804 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J135TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J135TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J135TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15CT.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15CT.asy new file mode 100755 index 0000000..ec59d3c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15CT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J15CT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J15CT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15F.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15F.asy new file mode 100755 index 0000000..c78a7f5 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J15F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J15F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15FS.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15FS.asy new file mode 100755 index 0000000..1fe70bb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J15FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J15FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15FU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15FU.asy new file mode 100755 index 0000000..069b9b1 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15FU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J15FU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J15FU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15FV.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15FV.asy new file mode 100755 index 0000000..6f0dee5 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J15FV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J15FV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J15FV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J168F.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J168F.asy new file mode 100755 index 0000000..d3b0ed0 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J168F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J168F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J168F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16CT.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16CT.asy new file mode 100755 index 0000000..836f291 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16CT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J16CT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J16CT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16FS.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16FS.asy new file mode 100755 index 0000000..f65fabb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J16FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J16FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16FU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16FU.asy new file mode 100755 index 0000000..6537b7e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16FU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J16FU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J16FU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16FV.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16FV.asy new file mode 100755 index 0000000..871fd3b --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J16FV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J16FV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J16FV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J325F.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J325F.asy new file mode 100755 index 0000000..c83ef34 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J325F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J325F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J325F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J327R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J327R.asy new file mode 100755 index 0000000..7ff449e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J327R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J327R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J327R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J328R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J328R.asy new file mode 100755 index 0000000..ef173aa --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J328R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J328R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J328R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J331R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J331R.asy new file mode 100755 index 0000000..9fdf1ae --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J331R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J331R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J331R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J332R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J332R.asy new file mode 100755 index 0000000..a395497 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J332R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J332R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J332R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J334R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J334R.asy new file mode 100755 index 0000000..14dd7d1 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J334R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J334R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J334R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J338R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J338R.asy new file mode 100755 index 0000000..c847359 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J338R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J338R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J338R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J340R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J340R.asy new file mode 100755 index 0000000..7651994 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J340R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J340R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J340R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J351R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J351R.asy new file mode 100755 index 0000000..362f757 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J351R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J351R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J351R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J352F.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J352F.asy new file mode 100755 index 0000000..2f67b58 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J352F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J352F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J352F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J353F.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J353F.asy new file mode 100755 index 0000000..760e087 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J353F.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J353F +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J353F.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J355R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J355R.asy new file mode 100755 index 0000000..93aa014 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J355R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J355R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J355R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J356R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J356R.asy new file mode 100755 index 0000000..c32da8c --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J356R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J356R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J356R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J358R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J358R.asy new file mode 100755 index 0000000..0e788fb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J358R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J358R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J358R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J35CT.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J35CT.asy new file mode 100755 index 0000000..6d09494 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J35CT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J35CT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J35CT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J35FS.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J35FS.asy new file mode 100755 index 0000000..91b92bf --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J35FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J35FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J35FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J35MFV.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J35MFV.asy new file mode 100755 index 0000000..2efa297 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J35MFV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J35MFV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J35MFV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J36FS.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J36FS.asy new file mode 100755 index 0000000..c14a04b --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J36FS.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J36FS +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J36FS.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J36TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J36TU.asy new file mode 100755 index 0000000..d736cc4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J36TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J36TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J36TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J374R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J374R.asy new file mode 100755 index 0000000..a7f8c2a --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J374R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J374R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J374R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J46CTB.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J46CTB.asy new file mode 100755 index 0000000..80ced59 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J46CTB.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J46CTB +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J46CTB.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J56ACT.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J56ACT.asy new file mode 100755 index 0000000..4e94ef8 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J56ACT.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J56ACT +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J56ACT.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J56MFV.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J56MFV.asy new file mode 100755 index 0000000..9e8a8cb --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J56MFV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J56MFV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J56MFV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J64CTC.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J64CTC.asy new file mode 100755 index 0000000..6471e75 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J64CTC.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J64CTC +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J64CTC.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J65CTC.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J65CTC.asy new file mode 100755 index 0000000..93b3520 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J65CTC.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J65CTC +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J65CTC.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J66MFV.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J66MFV.asy new file mode 100755 index 0000000..7d67a6e --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM3J66MFV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM3J66MFV +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM3J66MFV.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J212FE.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J212FE.asy new file mode 100755 index 0000000..ccd7a31 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J212FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J212FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J212FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J213FE.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J213FE.asy new file mode 100755 index 0000000..291a8e1 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J213FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J213FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J213FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J214FE.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J214FE.asy new file mode 100755 index 0000000..262fddd --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J214FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J214FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J214FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J215FE.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J215FE.asy new file mode 100755 index 0000000..f7faa97 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J215FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J215FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J215FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J216FE.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J216FE.asy new file mode 100755 index 0000000..288fbee --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J216FE.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J216FE +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J216FE.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J402TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J402TU.asy new file mode 100755 index 0000000..b3171e7 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J402TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J402TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J402TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J410TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J410TU.asy new file mode 100755 index 0000000..39e30df --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J410TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J410TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J410TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J412TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J412TU.asy new file mode 100755 index 0000000..cfad1bc --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J412TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J412TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J412TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J414TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J414TU.asy new file mode 100755 index 0000000..db4a291 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J414TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J414TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J414TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J422TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J422TU.asy new file mode 100755 index 0000000..2ed0a9f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J422TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J422TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J422TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J424TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J424TU.asy new file mode 100755 index 0000000..d715990 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J424TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J424TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J424TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J501NU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J501NU.asy new file mode 100755 index 0000000..d96c8de --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J501NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J501NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J501NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J502NU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J502NU.asy new file mode 100755 index 0000000..7943453 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J502NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J502NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J502NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J503NU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J503NU.asy new file mode 100755 index 0000000..de48712 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J503NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J503NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J503NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J505NU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J505NU.asy new file mode 100755 index 0000000..fc020f9 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J505NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J505NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J505NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J507NU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J507NU.asy new file mode 100755 index 0000000..04a1bd2 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J507NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J507NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J507NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J50TU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J50TU.asy new file mode 100755 index 0000000..fe231ef --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J50TU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J50TU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J50TU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J511NU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J511NU.asy new file mode 100755 index 0000000..4ba85a4 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J511NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J511NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J511NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J512NU.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J512NU.asy new file mode 100755 index 0000000..4ac497f --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J512NU.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J512NU +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J512NU.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J771G.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J771G.asy new file mode 100755 index 0000000..a7508f1 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J771G.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J771G +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J771G.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J801R.asy b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J801R.asy new file mode 100755 index 0000000..0c56b81 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/SSM6J801R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_SSM6J801R +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/SSM6J801R.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/TJ15S10M3.asy b/spice/copy/sym/Contrib/Toshiba/pmos/TJ15S10M3.asy new file mode 100755 index 0000000..85db9ec --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/TJ15S10M3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_TJ15S10M3 +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/TJ15S10M3.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/TPH1R712MD.asy b/spice/copy/sym/Contrib/Toshiba/pmos/TPH1R712MD.asy new file mode 100755 index 0000000..60d0e38 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/TPH1R712MD.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_TPH1R712MD +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/TPH1R712MD.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Toshiba/pmos/TPN4R712MD.asy b/spice/copy/sym/Contrib/Toshiba/pmos/TPN4R712MD.asy new file mode 100755 index 0000000..9f647d6 --- /dev/null +++ b/spice/copy/sym/Contrib/Toshiba/pmos/TPN4R712MD.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 38 56 72 Left 2 +SYMATTR SpiceModel PMOS_TPN4R712MD +SYMATTR Prefix X +SYMATTR ModelFile Contrib/Toshiba/pmos/TPN4R712MD.lib +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Contrib/Wurth/EMC-Components/CommonModeChokes/WE-CCMF.asy b/spice/copy/sym/Contrib/Wurth/EMC-Components/CommonModeChokes/WE-CCMF.asy new file mode 100755 index 0000000..8fcbe52 --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/EMC-Components/CommonModeChokes/WE-CCMF.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -48 -96 -48 +LINE Normal -64 48 -96 48 +LINE Normal 64 -48 96 -48 +LINE Normal 64 48 96 48 +LINE Normal 64 -64 -64 -64 +LINE Normal 64 64 64 -64 +LINE Normal -64 64 64 64 +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 -64 -64 +LINE Normal 32 5 -32 5 +LINE Normal 32 -5 -32 -5 +LINE Normal -32 -48 -64 -48 +LINE Normal -32 -24 -32 -48 +LINE Normal 32 -48 64 -48 +LINE Normal 32 -24 32 -48 +LINE Normal -32 48 -64 48 +LINE Normal -32 24 -32 48 +LINE Normal 32 48 64 48 +LINE Normal 32 24 32 48 +CIRCLE Normal -37 -24 -43 -30 +CIRCLE Normal -38 30 -44 24 +ARC Normal -32 -32 -16 -16 -32 -24 -16 -24 +ARC Normal -16 -32 0 -16 -16 -24 0 -24 +ARC Normal 0 -32 16 -16 0 -24 16 -24 +ARC Normal 16 -32 32 -16 16 -24 32 -24 +ARC Normal -32 16 -16 32 -16 24 -32 24 +ARC Normal -16 16 0 32 0 24 -16 24 +ARC Normal 0 16 16 32 16 24 0 24 +ARC Normal 16 16 32 32 32 24 16 24 +WINDOW 0 -17 -77 Left 2 +WINDOW 38 -127 81 Left 2 +SYMATTR SpiceModel WE_CCMF_748020024 +SYMATTR Prefix X +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-CCMF.lib +PIN -96 -48 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 48 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 96 48 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/EMC-Components/CommonModeChokes/WE-CMB.asy b/spice/copy/sym/Contrib/Wurth/EMC-Components/CommonModeChokes/WE-CMB.asy new file mode 100755 index 0000000..b632fa2 --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/EMC-Components/CommonModeChokes/WE-CMB.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -48 -96 -48 +LINE Normal -64 48 -96 48 +LINE Normal 64 -48 96 -48 +LINE Normal 64 48 96 48 +LINE Normal 64 -64 -64 -64 +LINE Normal 64 64 64 -64 +LINE Normal -64 64 64 64 +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 -64 -64 +LINE Normal 32 5 -32 5 +LINE Normal 32 -5 -32 -5 +LINE Normal -32 -48 -64 -48 +LINE Normal -32 -24 -32 -48 +LINE Normal 32 -48 64 -48 +LINE Normal 32 -24 32 -48 +LINE Normal -32 48 -64 48 +LINE Normal -32 24 -32 48 +LINE Normal 32 48 64 48 +LINE Normal 32 24 32 48 +CIRCLE Normal -37 -24 -43 -30 +CIRCLE Normal -38 30 -44 24 +ARC Normal -32 -32 -16 -16 -32 -24 -16 -24 +ARC Normal -16 -32 0 -16 -16 -24 0 -24 +ARC Normal 0 -32 16 -16 0 -24 16 -24 +ARC Normal 16 -32 32 -16 16 -24 32 -24 +ARC Normal -32 16 -16 32 -16 24 -32 24 +ARC Normal -16 16 0 32 0 24 -16 24 +ARC Normal 0 16 16 32 16 24 0 24 +ARC Normal 16 16 32 32 32 24 16 24 +WINDOW 0 -17 -77 Left 2 +WINDOW 38 -131 81 Left 2 +SYMATTR SpiceModel XS_744821201_1m +SYMATTR Prefix X +SYMATTR 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PinName Port_3 +PINATTR SpiceOrder 3 +PIN 80 -48 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 80 0 NONE 8 +PINATTR PinName Port_5 +PINATTR SpiceOrder 5 +PIN 80 48 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Contrib/Wurth/EMC-Components/CommonModeChokes/WE-UCF.asy b/spice/copy/sym/Contrib/Wurth/EMC-Components/CommonModeChokes/WE-UCF.asy new file mode 100755 index 0000000..4685305 --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/EMC-Components/CommonModeChokes/WE-UCF.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -48 -96 -48 +LINE Normal -64 48 -96 48 +LINE Normal 64 -48 96 -48 +LINE Normal 64 48 96 48 +LINE Normal 64 -64 -64 -64 +LINE Normal 64 64 64 -64 +LINE Normal -64 64 64 64 +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 -64 -64 +LINE Normal 32 5 -32 5 +LINE Normal 32 -5 -32 -5 +LINE Normal -32 -48 -64 -48 +LINE Normal -32 -24 -32 -48 +LINE Normal 32 -48 64 -48 +LINE Normal 32 -24 32 -48 +LINE Normal -32 48 -64 48 +LINE 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file mode 100755 index 0000000..30f7062 --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-CFWI.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 1 35 Center 2 +WINDOW 0 0 -37 Center 2 +SYMATTR SpiceModel 1310_74485540080_0.8u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-CFWI.lib +PIN -48 -16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 48 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DCT.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DCT.asy new file mode 100755 index 0000000..bd08aec --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DCT.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 1 35 Center 2 +WINDOW 0 0 -37 Center 2 +SYMATTR SpiceModel SH_744851016_0.16u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-DCT.lib +PIN -48 -16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 48 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DD.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DD.asy new file mode 100755 index 0000000..53444cb --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DD.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 4 40 Center 2 +WINDOW 0 -13 -40 Left 2 +SYMATTR SpiceModel 7448700015 +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-DD.lib +PIN -48 -16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 48 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DPC.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DPC.asy new file mode 100755 index 0000000..d499d43 --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DPC.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 1 35 Center 2 +WINDOW 0 0 -37 Center 2 +SYMATTR SpiceModel 5838_7448844010_1u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-DPC.lib +PIN -48 -16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 48 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DPC_HV.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DPC_HV.asy new file mode 100755 index 0000000..904b86f --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-DPC_HV.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 1 35 Center 2 +WINDOW 0 0 -37 Center 2 +SYMATTR SpiceModel 5030_7448841010_1u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-DPC_HV.lib +PIN -48 -16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 48 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-EHPI.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-EHPI.asy new file mode 100755 index 0000000..946f239 --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-EHPI.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 1 35 Center 2 +WINDOW 0 0 -37 Center 2 +SYMATTR SpiceModel 5838_74488540250_25u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-EHPI.lib +PIN -48 -16 RIGHT 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN 48 -16 LEFT 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 LEFT 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -48 16 RIGHT 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-MCRI.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-MCRI.asy new file mode 100755 index 0000000..3ab0edc --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-MCRI.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 1 35 Center 2 +WINDOW 0 0 -37 Center 2 +SYMATTR SpiceModel 1090_7448990010_1u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-MCRI.lib +PIN -48 -16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 48 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-MTCI.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-MTCI.asy new file mode 100755 index 0000000..39abac8 --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-MTCI.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 1 35 Center 2 +WINDOW 0 0 -37 Center 2 +SYMATTR SpiceModel 5030_744889015100_10u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-MTCI.lib +PIN -48 -16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 48 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-TDC.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-TDC.asy new file mode 100755 index 0000000..25a26c0 --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-TDC.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 1 35 Center 2 +WINDOW 0 0 -37 Center 2 +SYMATTR SpiceModel 8018_744894300033_0.33u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-TDC.lib +PIN -48 -16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 48 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-TDC_HV.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-TDC_HV.asy new file mode 100755 index 0000000..6cac56f --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/Coupled/WE-TDC_HV.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 3 32 3 +LINE Normal -32 -2 32 -2 +LINE Normal -48 -16 -24 -16 +LINE Normal -48 16 -24 16 +LINE Normal 24 16 48 16 +LINE Normal 24 -16 48 -16 +CIRCLE Normal -30 9 -26 13 +CIRCLE Normal -30 -9 -26 -13 +ARC Normal 24 8 8 24 24 16 8 16 +ARC Normal 8 8 -8 24 8 16 -8 16 +ARC Normal -8 8 -24 24 -8 16 -24 16 +ARC Normal 24 -8 8 -24 8 -16 24 -16 +ARC Normal 8 -8 -8 -24 -8 -16 8 -16 +ARC Normal -8 -8 -24 -24 -24 -16 -8 -16 +WINDOW 38 1 35 Center 2 +WINDOW 0 0 -37 Center 2 +SYMATTR SpiceModel 8018_76889430056_5.6u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-TDC_HV.lib +PIN -48 -16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 48 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 48 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/DualCoil/WE-HIDA_DUAL.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/DualCoil/WE-HIDA_DUAL.asy new file mode 100755 index 0000000..90fffa5 --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/DualCoil/WE-HIDA_DUAL.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 -32 -64 -32 +LINE Normal 32 -32 16 -32 +LINE Normal 32 0 16 0 +LINE Normal -64 0 -48 0 +LINE Normal -32 -48 -48 -48 +LINE Normal 16 -48 0 -48 +LINE Normal -32 -16 -48 -16 +LINE Normal 16 -16 0 -16 +ARC Normal -32 -16 -48 -43 -32 -32 -48 -32 +ARC Normal -16 -16 -32 -43 -16 -32 -32 -32 +ARC Normal 0 -16 -16 -43 0 -32 -16 -32 +ARC Normal 16 -16 0 -43 16 -32 0 -32 +ARC Normal -32 16 -48 -11 -32 0 -48 0 +ARC Normal -16 16 -32 -11 -16 0 -32 0 +ARC Normal 0 16 -16 -11 0 0 -16 0 +ARC Normal 16 16 0 -11 16 0 0 0 +WINDOW 38 -19 24 Center 0 +SYMATTR SpiceModel 1415_7444211415082_8.2u +SYMATTR ModelFile Contrib/Wurth/WE-HIDA_DUAL.lib +SYMATTR Prefix x +SYMATTR InstName L +PIN -64 -32 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -64 0 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 32 0 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 32 -32 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Contrib/Wurth/PowerMagnetics/DualCoil/WE-LHMD.asy b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/DualCoil/WE-LHMD.asy new file mode 100755 index 0000000..0ecdaeb --- /dev/null +++ b/spice/copy/sym/Contrib/Wurth/PowerMagnetics/DualCoil/WE-LHMD.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +LINE Normal 64 -32 32 -32 +LINE Normal -64 -32 -32 -32 +LINE Normal -7 -48 -32 -48 +LINE Normal 32 -48 7 -48 +LINE Normal 31 -16 6 -16 +LINE Normal -7 -16 -32 -16 +LINE Normal -64 0 -32 0 +LINE Normal 64 0 32 0 +ARC Normal -32 -16 -16 -44 -16 -32 -32 -32 +ARC Normal -16 -16 0 -44 0 -32 -16 -32 +ARC Normal 0 -16 16 -44 16 -32 0 -32 +ARC Normal 16 -16 32 -44 32 -32 16 -32 +ARC Normal -32 16 -16 -12 -16 0 -32 0 +ARC Normal -16 16 0 -12 0 0 -16 0 +ARC Normal 0 16 16 -12 16 0 0 0 +ARC Normal 16 16 32 -12 32 0 16 0 +WINDOW 38 -7 26 Center 0 +SYMATTR SpiceModel 1008_74434301008082_8.2u +SYMATTR Prefix x +SYMATTR InstName L +SYMATTR ModelFile Contrib/Wurth/WE-LHMD.lib +PIN -64 -32 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN 64 -32 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN -64 0 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 64 0 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/DAC/AD5535Bopamp.asy b/spice/copy/sym/DAC/AD5535Bopamp.asy new file mode 100755 index 0000000..816d901 --- /dev/null +++ b/spice/copy/sym/DAC/AD5535Bopamp.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -159 -143 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +SYMATTR Value AD5535Bopamp +SYMATTR Prefix X +SYMATTR Value2 AD5535Bopamp +SYMATTR Description 32-Channel, 14-Bit DAC (one channel, output stage modelled) +SYMATTR ModelFile AD5535Bopamp.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vpp +PINATTR SpiceOrder 1 +PIN 160 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5671R.asy b/spice/copy/sym/DAC/AD5671R.asy new file mode 100755 index 0000000..8244c40 --- /dev/null +++ b/spice/copy/sym/DAC/AD5671R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5671R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5671R +SYMATTR Description 16-Channel, 16Bit nanaDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5671R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5672R.asy b/spice/copy/sym/DAC/AD5672R.asy new file mode 100755 index 0000000..7214e45 --- /dev/null +++ b/spice/copy/sym/DAC/AD5672R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5672R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5672R +SYMATTR Description 16-Channel, 16Bit nanaDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5672R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5673R.asy b/spice/copy/sym/DAC/AD5673R.asy new file mode 100755 index 0000000..5a8f0f3 --- /dev/null +++ b/spice/copy/sym/DAC/AD5673R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5673R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5673R +SYMATTR Description 16-Channel, 16Bit nanaDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5673R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5674R.asy b/spice/copy/sym/DAC/AD5674R.asy new file mode 100755 index 0000000..d1015aa --- /dev/null +++ b/spice/copy/sym/DAC/AD5674R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5674R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5674R +SYMATTR Description 16-Channel, 16Bit nanaDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5674R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5675R.asy b/spice/copy/sym/DAC/AD5675R.asy new file mode 100755 index 0000000..5e32060 --- /dev/null +++ b/spice/copy/sym/DAC/AD5675R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5675R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5675R +SYMATTR Description 16-Channel, 16Bit nanaDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5675R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5676R.asy b/spice/copy/sym/DAC/AD5676R.asy new file mode 100755 index 0000000..4ecfada --- /dev/null +++ b/spice/copy/sym/DAC/AD5676R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5676R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5676R +SYMATTR Description 16-Channel, 16Bit nanaDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5676R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5677R.asy b/spice/copy/sym/DAC/AD5677R.asy new file mode 100755 index 0000000..c808eb7 --- /dev/null +++ b/spice/copy/sym/DAC/AD5677R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5677R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5677R +SYMATTR Description 16-Channel, 16Bit nanaDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5677R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5679R.asy b/spice/copy/sym/DAC/AD5679R.asy new file mode 100755 index 0000000..a1238d0 --- /dev/null +++ b/spice/copy/sym/DAC/AD5679R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5679R +SYMATTR Prefix X +SYMATTR Value2 AD5679R +SYMATTR Description 16-Channel, 16Bit nanaDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5679R.sub +SYMATTR SpiceLine Gain=2 +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5681R.asy b/spice/copy/sym/DAC/AD5681R.asy new file mode 100755 index 0000000..5182602 --- /dev/null +++ b/spice/copy/sym/DAC/AD5681R.asy @@ -0,0 +1,30 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5681R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR SpiceModel AD5681R.sub +SYMATTR Value2 AD5681R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5681R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5682R.asy b/spice/copy/sym/DAC/AD5682R.asy new file mode 100755 index 0000000..be88722 --- /dev/null +++ b/spice/copy/sym/DAC/AD5682R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5682R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5682R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5682R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5683R.asy b/spice/copy/sym/DAC/AD5683R.asy new file mode 100755 index 0000000..d49d579 --- /dev/null +++ b/spice/copy/sym/DAC/AD5683R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5683R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5683R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5683R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5684R.asy b/spice/copy/sym/DAC/AD5684R.asy new file mode 100755 index 0000000..d5205b9 --- /dev/null +++ b/spice/copy/sym/DAC/AD5684R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5684R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5684R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5684R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5685R.asy b/spice/copy/sym/DAC/AD5685R.asy new file mode 100755 index 0000000..fa45a14 --- /dev/null +++ b/spice/copy/sym/DAC/AD5685R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5685R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5685R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5685R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5686R.asy b/spice/copy/sym/DAC/AD5686R.asy new file mode 100755 index 0000000..91a01f4 --- /dev/null +++ b/spice/copy/sym/DAC/AD5686R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5686R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5686R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5686R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5687R.asy b/spice/copy/sym/DAC/AD5687R.asy new file mode 100755 index 0000000..7fc1901 --- /dev/null +++ b/spice/copy/sym/DAC/AD5687R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5687R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5687R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5687R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5689R.asy b/spice/copy/sym/DAC/AD5689R.asy new file mode 100755 index 0000000..ce4ed93 --- /dev/null +++ b/spice/copy/sym/DAC/AD5689R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5689R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5689R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5689R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5691R.asy b/spice/copy/sym/DAC/AD5691R.asy new file mode 100755 index 0000000..2fec637 --- /dev/null +++ b/spice/copy/sym/DAC/AD5691R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5691R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5691R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5691R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5692R.asy b/spice/copy/sym/DAC/AD5692R.asy new file mode 100755 index 0000000..4fb293b --- /dev/null +++ b/spice/copy/sym/DAC/AD5692R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5692R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5692R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5692R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5693R.asy b/spice/copy/sym/DAC/AD5693R.asy new file mode 100755 index 0000000..9c0a905 --- /dev/null +++ b/spice/copy/sym/DAC/AD5693R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5693R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5693R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5693R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5694R.asy b/spice/copy/sym/DAC/AD5694R.asy new file mode 100755 index 0000000..24d30ff --- /dev/null +++ b/spice/copy/sym/DAC/AD5694R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5694R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5694R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5694R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5695R.asy b/spice/copy/sym/DAC/AD5695R.asy new file mode 100755 index 0000000..50225eb --- /dev/null +++ b/spice/copy/sym/DAC/AD5695R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5695R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5695R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5695R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5696R.asy b/spice/copy/sym/DAC/AD5696R.asy new file mode 100755 index 0000000..252fed7 --- /dev/null +++ b/spice/copy/sym/DAC/AD5696R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5696R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5696R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5696R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5697R.asy b/spice/copy/sym/DAC/AD5697R.asy new file mode 100755 index 0000000..86a3bd6 --- /dev/null +++ b/spice/copy/sym/DAC/AD5697R.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 3 74 Center 1 +SYMATTR Value AD5697R +SYMATTR SpiceLine Gain=2 +SYMATTR Prefix X +SYMATTR Value2 AD5697R +SYMATTR Description 16Bit nanoDAC+ (one channel, output stage modeled) +SYMATTR ModelFile AD5697R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -32 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -32 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/DAC/AD5766.asy b/spice/copy/sym/DAC/AD5766.asy new file mode 100755 index 0000000..3fddc18 --- /dev/null +++ b/spice/copy/sym/DAC/AD5766.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -47 Center 2 +WINDOW 3 6 42 Center 2 +WINDOW 39 7 74 Center 0 +WINDOW 40 7 86 Center 0 +WINDOW 123 6 63 Center 0 +SYMATTR Value AD5766 +SYMATTR SpiceLine dither_scale=0 +SYMATTR SpiceLine2 dither_inv=0 +SYMATTR Value2 Range=8 +SYMATTR Prefix X +SYMATTR Description 16-Channel, 16Bit Voltage Output denseDACs (one channel, output stage modeled) +SYMATTR ModelFile AD5766.sub +PIN -160 -64 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN -160 80 LEFT 8 +PINATTR PinName NO +PINATTR SpiceOrder 2 +PIN 32 -144 TOP 8 +PINATTR PinName AVdd +PINATTR SpiceOrder 3 +PIN 32 144 BOTTOM 8 +PINATTR PinName AVss +PINATTR SpiceOrder 4 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN -80 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/DAC/AD5770R.asy b/spice/copy/sym/DAC/AD5770R.asy new file mode 100755 index 0000000..07f9c77 --- /dev/null +++ b/spice/copy/sym/DAC/AD5770R.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 0 86 Center 1 +SYMATTR Value AD5770R +SYMATTR SpiceLine Range=1 +SYMATTR Prefix X +SYMATTR Value2 AD5770R +SYMATTR Description 6-Channel, 14Bit Current Output DACs (one channel, output stage modeled) +SYMATTR ModelFile AD5770R.sub +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN 208 0 RIGHT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 2 +PIN -32 -144 TOP 8 +PINATTR PinName PVdd +PINATTR SpiceOrder 3 +PIN 32 144 BOTTOM 8 +PINATTR PinName PVee +PINATTR SpiceOrder 4 +PIN -96 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/DAC/AD5772R.asy b/spice/copy/sym/DAC/AD5772R.asy new file mode 100755 index 0000000..151b9a8 --- /dev/null +++ b/spice/copy/sym/DAC/AD5772R.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType CELL +LINE Normal -160 144 -160 -144 +LINE Normal 96 144 -160 144 +LINE Normal 209 -1 96 144 +LINE Normal 96 -144 209 -1 +LINE Normal -160 -144 96 -144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 4 42 Center 2 +WINDOW 39 1 66 Center 1 +WINDOW 40 -3 89 Center 1 +SYMATTR Value AD5772R +SYMATTR SpiceLine Range=1 +SYMATTR Prefix X +SYMATTR Value2 AD5772R +SYMATTR Description 7-Channel, 14/16Bit Current Output DACs (one channel, output stage modeled) +SYMATTR SpiceModel AD5772R.sub +SYMATTR SpiceLine2 isink_en=0 +PIN -160 0 LEFT 8 +PINATTR PinName Vdac +PINATTR SpiceOrder 1 +PIN 208 0 RIGHT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 2 +PIN -32 -144 TOP 8 +PINATTR PinName PVdd +PINATTR SpiceOrder 3 +PIN 32 144 BOTTOM 8 +PINATTR PinName PVee +PINATTR SpiceOrder 4 +PIN -96 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Digital/and.asy b/spice/copy/sym/Digital/and.asy new file mode 100755 index 0000000..59c946c --- /dev/null +++ b/spice/copy/sym/Digital/and.asy @@ -0,0 +1,37 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -12 32 +LINE Normal -32 96 -12 96 +LINE Normal -32 96 -32 32 +LINE Normal 16 48 32 48 +CIRCLE Normal 32 88 16 72 +ARC Normal -44 96 20 32 -12 96 -12 32 +WINDOW 0 16 24 Left 2 +WINDOW 3 16 112 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel AND +SYMATTR Description Behavioral AND gate +PIN -32 32 NONE 0 +PINATTR PinName a +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName b +PINATTR SpiceOrder 2 +PIN -32 64 NONE 0 +PINATTR PinName c +PINATTR SpiceOrder 3 +PIN -32 80 NONE 0 +PINATTR PinName d +PINATTR SpiceOrder 4 +PIN -32 96 NONE 0 +PINATTR PinName e +PINATTR SpiceOrder 5 +PIN 32 80 NONE 0 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 32 48 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN -16 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/buf.asy b/spice/copy/sym/Digital/buf.asy new file mode 100755 index 0000000..e56d4a1 --- /dev/null +++ b/spice/copy/sym/Digital/buf.asy @@ -0,0 +1,25 @@ +Version 4 +SymbolType CELL +LINE Normal 0 32 64 64 +LINE Normal 0 96 64 64 +LINE Normal 32 48 64 48 +LINE Normal 0 96 0 32 +LINE Normal 64 80 60 80 +CIRCLE Normal 60 88 44 72 +WINDOW 0 8 16 Left 2 +WINDOW 3 8 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel BUF +SYMATTR Description Behavioral buffer with complementary outputs +PIN 0 64 NONE 0 +PINATTR PinName in +PINATTR SpiceOrder 1 +PIN 64 80 NONE 0 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 64 48 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN 0 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/buf1.asy b/spice/copy/sym/Digital/buf1.asy new file mode 100755 index 0000000..7e6cd12 --- /dev/null +++ b/spice/copy/sym/Digital/buf1.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 0 48 40 64 +LINE Normal 0 80 40 64 +LINE Normal 0 80 0 48 +LINE Normal 40 64 64 64 +WINDOW 0 8 32 Left 2 +WINDOW 3 8 104 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel BUF +SYMATTR Description Behavioral buffer +PIN 0 64 NONE 0 +PINATTR PinName in +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN 0 80 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/counter.asy b/spice/copy/sym/Digital/counter.asy new file mode 100755 index 0000000..43375c1 --- /dev/null +++ b/spice/copy/sym/Digital/counter.asy @@ -0,0 +1,25 @@ +Version 4 +SymbolType CELL +LINE Normal -80 24 -72 32 +LINE Normal -80 40 -72 32 +LINE Normal -80 -64 144 -64 +LINE Normal -80 -64 -80 128 +LINE Normal -80 128 144 128 +LINE Normal 144 128 144 -64 +WINDOW 0 -64 -80 Left 2 +WINDOW 3 -64 152 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel COUNTER +SYMATTR Description Behavioral counter +PIN -80 32 LEFT 12 +PINATTR PinName CLK +PINATTR SpiceOrder 1 +PIN 144 64 RIGHT 8 +PINATTR PinName Phi2 +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName Phi1 +PINATTR SpiceOrder 7 +PIN -80 128 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/dflop.asy b/spice/copy/sym/Digital/dflop.asy new file mode 100755 index 0000000..db80d13 --- /dev/null +++ b/spice/copy/sym/Digital/dflop.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -80 0 80 0 +LINE Normal -80 0 -80 144 +LINE Normal -80 144 80 144 +LINE Normal 80 144 80 0 +LINE Normal -80 88 -72 96 +LINE Normal -80 104 -72 96 +CIRCLE Normal 96 104 80 88 +WINDOW 0 8 -16 Left 2 +WINDOW 3 8 168 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel DFLOP +SYMATTR Description Behavioral D-flipflop +PIN -80 48 LEFT 8 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN -80 96 LEFT 8 +PINATTR PinName CLK +PINATTR SpiceOrder 3 +PIN 0 0 TOP 4 +PINATTR PinName PRE +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 4 +PINATTR PinName CLR +PINATTR SpiceOrder 5 +PIN 96 96 RIGHT 20 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 80 48 RIGHT 4 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN -80 144 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/diffschmitt.asy b/spice/copy/sym/Digital/diffschmitt.asy new file mode 100755 index 0000000..56a5d91 --- /dev/null +++ b/spice/copy/sym/Digital/diffschmitt.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal 8 72 16 72 +LINE Normal 12 56 20 56 +LINE Normal 12 72 12 56 +LINE Normal 16 72 16 56 +LINE Normal 0 32 64 64 +LINE Normal 0 96 64 64 +LINE Normal 32 48 64 48 +LINE Normal 0 96 0 32 +LINE Normal 64 80 60 80 +LINE Normal 4 48 12 48 +LINE Normal 8 44 8 52 +LINE Normal 4 80 12 80 +CIRCLE Normal 60 88 44 72 +WINDOW 0 8 16 Left 2 +WINDOW 3 8 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel SCHMITT +SYMATTR Description Behavioral Schmitt-Triggered Buffer with Complementary Outs and Differential Input +PIN 0 48 NONE 0 +PINATTR PinName in+ +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName in- +PINATTR SpiceOrder 2 +PIN 64 80 NONE 0 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 64 48 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN 0 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/diffschmtbuf.asy b/spice/copy/sym/Digital/diffschmtbuf.asy new file mode 100755 index 0000000..029ea27 --- /dev/null +++ b/spice/copy/sym/Digital/diffschmtbuf.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 8 72 16 72 +LINE Normal 12 56 20 56 +LINE Normal 12 72 12 56 +LINE Normal 16 72 16 56 +LINE Normal 0 32 64 64 +LINE Normal 0 96 64 64 +LINE Normal 0 96 0 32 +LINE Normal 4 48 12 48 +LINE Normal 8 44 8 52 +LINE Normal 4 80 12 80 +WINDOW 0 8 16 Left 2 +WINDOW 3 8 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel SCHMITT +SYMATTR Description Behavioral Schmitt-Triggered Buffer with Differential Input +PIN 0 48 NONE 0 +PINATTR PinName in+ +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName in- +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN 0 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/diffschmtinv.asy b/spice/copy/sym/Digital/diffschmtinv.asy new file mode 100755 index 0000000..97eb0f3 --- /dev/null +++ b/spice/copy/sym/Digital/diffschmtinv.asy @@ -0,0 +1,31 @@ +Version 4 +SymbolType CELL +LINE Normal 8 72 16 72 +LINE Normal 12 56 20 56 +LINE Normal 12 72 12 56 +LINE Normal 16 72 16 56 +LINE Normal 0 32 44 64 +LINE Normal 0 96 44 64 +LINE Normal 60 64 64 64 +LINE Normal 0 96 0 32 +LINE Normal 4 48 12 48 +LINE Normal 8 44 8 52 +LINE Normal 4 80 12 80 +CIRCLE Normal 60 72 44 56 +WINDOW 0 8 16 Left 2 +WINDOW 3 8 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel SCHMITT +SYMATTR Description Behavioral Schmitt-Triggered Inverter with Differential Input +PIN 0 48 NONE 0 +PINATTR PinName in+ +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName in- +PINATTR SpiceOrder 2 +PIN 64 64 NONE 0 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 0 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/inv.asy b/spice/copy/sym/Digital/inv.asy new file mode 100755 index 0000000..7a3eff8 --- /dev/null +++ b/spice/copy/sym/Digital/inv.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType CELL +LINE Normal 0 48 40 64 +LINE Normal 0 80 40 64 +LINE Normal 0 80 0 48 +LINE Normal 56 64 64 64 +CIRCLE Normal 56 72 40 56 +WINDOW 0 8 32 Left 2 +WINDOW 3 8 104 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel BUF +SYMATTR Description Behavioral Inverter +PIN 0 64 NONE 0 +PINATTR PinName in +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 0 80 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/or.asy b/spice/copy/sym/Digital/or.asy new file mode 100755 index 0000000..7416fe7 --- /dev/null +++ b/spice/copy/sym/Digital/or.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -28 32 +LINE Normal -32 96 -28 96 +LINE Normal 12 48 32 48 +LINE Normal -32 80 -24 80 +LINE Normal -32 64 -20 64 +LINE Normal -32 48 -24 48 +CIRCLE Normal 32 88 16 72 +ARC Normal -132 8 -20 120 -32 96 -32 32 +ARC Normal -80 -12 28 96 -28 96 24 64 +ARC Normal -80 32 28 140 24 64 -28 32 +WINDOW 0 -8 8 Left 2 +WINDOW 3 -8 128 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel OR +SYMATTR Description Behavioral OR gate with complementary outputs +PIN -32 32 NONE 0 +PINATTR PinName a +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName b +PINATTR SpiceOrder 2 +PIN -32 64 NONE 0 +PINATTR PinName c +PINATTR SpiceOrder 3 +PIN -32 80 NONE 0 +PINATTR PinName d +PINATTR SpiceOrder 4 +PIN -32 96 NONE 0 +PINATTR PinName e +PINATTR SpiceOrder 5 +PIN 32 80 NONE 0 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 32 48 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN -16 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/phidet.asy b/spice/copy/sym/Digital/phidet.asy new file mode 100755 index 0000000..46e598a --- /dev/null +++ b/spice/copy/sym/Digital/phidet.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -24 -24 -16 +LINE Normal -32 -8 -24 -16 +LINE Normal -32 24 -24 16 +LINE Normal -32 8 -24 16 +LINE Normal -32 -48 -32 48 +LINE Normal -32 -48 32 -48 +LINE Normal -32 48 32 48 +LINE Normal 32 48 64 12 +LINE Normal 32 -48 64 -12 +LINE Normal -4 -16 28 16 +LINE Normal -4 16 28 -16 +CIRCLE Normal -12 -24 36 24 +CIRCLE Normal 80 12 56 -12 +CIRCLE Normal 96 12 72 -12 +WINDOW 0 8 -64 Center 2 +WINDOW 3 0 64 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel PHASEDET +SYMATTR Description Behavioral Type 3/4 Phase Detector (phase/frequency detector). NOTE: Limit input rise times +PIN -32 -16 NONE 0 +PINATTR PinName a +PINATTR SpiceOrder 1 +PIN -32 16 NONE 0 +PINATTR PinName b +PINATTR SpiceOrder 2 +PIN 96 0 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN -32 48 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/schmitt.asy b/spice/copy/sym/Digital/schmitt.asy new file mode 100755 index 0000000..7412537 --- /dev/null +++ b/spice/copy/sym/Digital/schmitt.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 8 72 16 72 +LINE Normal 12 56 20 56 +LINE Normal 12 72 12 56 +LINE Normal 16 72 16 56 +LINE Normal 0 32 64 64 +LINE Normal 0 96 64 64 +LINE Normal 32 48 64 48 +LINE Normal 0 96 0 32 +LINE Normal 64 80 60 80 +CIRCLE Normal 60 88 44 72 +WINDOW 0 8 16 Left 2 +WINDOW 3 8 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel SCHMITT +SYMATTR Description Behavioral Schmitt-Triggered buffer with complementary outs +PIN 0 64 NONE 0 +PINATTR PinName in +PINATTR SpiceOrder 1 +PIN 64 80 NONE 0 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 64 48 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN 0 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/schmtbuf.asy b/spice/copy/sym/Digital/schmtbuf.asy new file mode 100755 index 0000000..39f5256 --- /dev/null +++ b/spice/copy/sym/Digital/schmtbuf.asy @@ -0,0 +1,24 @@ +Version 4 +SymbolType CELL +LINE Normal 4 68 12 68 +LINE Normal 8 60 16 60 +LINE Normal 8 60 8 68 +LINE Normal 12 68 12 60 +LINE Normal 0 48 40 64 +LINE Normal 0 80 40 64 +LINE Normal 0 80 0 48 +LINE Normal 40 64 64 64 +WINDOW 0 8 32 Left 2 +WINDOW 3 8 104 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel SCHMITT +SYMATTR Description Behavioral Schmitt-Triggered buffer +PIN 0 64 NONE 0 +PINATTR PinName in +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN 0 80 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/schmtinv.asy b/spice/copy/sym/Digital/schmtinv.asy new file mode 100755 index 0000000..c449e53 --- /dev/null +++ b/spice/copy/sym/Digital/schmtinv.asy @@ -0,0 +1,25 @@ +Version 4 +SymbolType CELL +LINE Normal 4 68 12 68 +LINE Normal 8 60 16 60 +LINE Normal 8 60 8 68 +LINE Normal 12 68 12 60 +LINE Normal 0 48 40 64 +LINE Normal 0 80 40 64 +LINE Normal 0 80 0 48 +LINE Normal 56 64 64 64 +CIRCLE Normal 56 72 40 56 +WINDOW 0 8 32 Left 2 +WINDOW 3 8 104 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel SCHMITT +SYMATTR Description Behavioral Schmitt-Triggered inverter +PIN 0 64 NONE 0 +PINATTR PinName in +PINATTR SpiceOrder 1 +PIN 64 64 NONE 0 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 0 80 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/srflop.asy b/spice/copy/sym/Digital/srflop.asy new file mode 100755 index 0000000..02b1bcd --- /dev/null +++ b/spice/copy/sym/Digital/srflop.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType CELL +LINE Normal -48 16 48 16 +LINE Normal -48 16 -48 128 +LINE Normal -48 128 48 128 +LINE Normal 48 128 48 16 +CIRCLE Normal 64 104 48 88 +WINDOW 0 -40 0 Left 2 +WINDOW 3 -40 152 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel SRFLOP +SYMATTR Description Behavioral Set-Reset Flipflop +PIN -48 48 LEFT 4 +PINATTR PinName S +PINATTR SpiceOrder 1 +PIN -48 96 LEFT 4 +PINATTR PinName R +PINATTR SpiceOrder 2 +PIN 64 96 RIGHT 20 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 48 48 RIGHT 4 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN -48 128 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Digital/xor.asy b/spice/copy/sym/Digital/xor.asy new file mode 100755 index 0000000..9519a92 --- /dev/null +++ b/spice/copy/sym/Digital/xor.asy @@ -0,0 +1,42 @@ +Version 4 +SymbolType CELL +LINE Normal -36 96 -28 96 +LINE Normal -36 32 -28 32 +LINE Normal 12 48 16 48 +LINE Normal -48 80 -40 80 +LINE Normal -48 64 -36 64 +LINE Normal -48 48 -40 48 +CIRCLE Normal 32 88 16 72 +ARC Normal -148 8 -36 120 -48 96 -48 32 +ARC Normal -136 8 -24 120 -36 96 -36 32 +ARC Normal -80 -12 28 96 -28 96 24 64 +ARC Normal -80 32 28 140 24 64 -28 32 +WINDOW 0 16 24 Left 2 +WINDOW 3 16 112 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel XOR +SYMATTR Description Behavioral XOR gate +PIN -48 32 NONE 0 +PINATTR PinName a +PINATTR SpiceOrder 1 +PIN -48 48 NONE 0 +PINATTR PinName b +PINATTR SpiceOrder 2 +PIN -48 64 NONE 0 +PINATTR PinName c +PINATTR SpiceOrder 3 +PIN -48 80 NONE 0 +PINATTR PinName d +PINATTR SpiceOrder 4 +PIN -48 96 NONE 0 +PINATTR PinName e +PINATTR SpiceOrder 5 +PIN 32 80 NONE 0 +PINATTR PinName _Q +PINATTR SpiceOrder 6 +PIN 16 48 NONE 0 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN -16 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/FerriteBead.asy b/spice/copy/sym/FerriteBead.asy new file mode 100755 index 0000000..13cfae9 --- /dev/null +++ b/spice/copy/sym/FerriteBead.asy @@ -0,0 +1,18 @@ +Version 4 +SymbolType BLOCK +LINE Normal -16 8 -16 -8 +LINE Normal 0 -8 0 -32 +LINE Normal 0 12 0 32 +LINE Normal 16 8 16 -8 +CIRCLE Normal -16 -4 16 -12 +CIRCLE Normal -7 -7 7 -9 +ARC Normal 16 4 -16 12 -16 8 16 8 +WINDOW 0 25 0 Left 2 +SYMATTR Prefix L_Ferrite_Bead +SYMATTR Description A Ferrite Bead +PIN 0 -32 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/FerriteBead2.asy b/spice/copy/sym/FerriteBead2.asy new file mode 100755 index 0000000..24d5322 --- /dev/null +++ b/spice/copy/sym/FerriteBead2.asy @@ -0,0 +1,52 @@ +Version 4 +SymbolType BLOCK +LINE Normal 0 -9 0 -32 +LINE Normal 0 9 0 32 +LINE Normal -9 8 9 8 +LINE Normal -9 7 9 7 +LINE Normal -9 6 9 6 +LINE Normal -9 6 9 6 +LINE Normal -9 5 9 5 +LINE Normal -9 4 9 4 +LINE Normal -9 3 9 3 +LINE Normal -9 3 9 3 +LINE Normal -9 2 9 2 +LINE Normal -9 1 9 1 +LINE Normal -9 0 9 0 +LINE Normal -9 0 9 0 +LINE Normal -9 -1 9 -1 +LINE Normal -9 -4 9 -4 +LINE Normal -9 -5 9 -5 +LINE Normal -9 -6 9 -6 +LINE Normal -9 -6 9 -6 +LINE Normal -9 -7 9 -7 +LINE Normal -9 -8 9 -8 +LINE Normal -9 -3 9 -3 +LINE Normal -9 -2 9 -2 +LINE Normal 7 9 7 -9 +LINE Normal 8 9 8 -9 +LINE Normal 5 9 5 -9 +LINE Normal 6 9 6 -9 +LINE Normal 3 9 3 -9 +LINE Normal 4 9 4 -9 +LINE Normal 1 9 1 -9 +LINE Normal 2 9 2 -9 +LINE Normal -1 9 -1 -9 +LINE Normal 0 9 0 -9 +LINE Normal -3 9 -3 -9 +LINE Normal -2 9 -2 -9 +LINE Normal -5 9 -5 -9 +LINE Normal -4 9 -4 -9 +LINE Normal -7 9 -7 -9 +LINE Normal -6 9 -6 -9 +LINE Normal -8 9 -8 -9 +RECTANGLE Normal -9 -9 9 9 +WINDOW 0 21 0 Left 2 +SYMATTR Prefix L_Ferrite_Bead +SYMATTR Description A Ferrite Bead(Alternate symbol) +PIN 0 -32 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/FilterProducts/LT1567.asy b/spice/copy/sym/FilterProducts/LT1567.asy new file mode 100755 index 0000000..5144140 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LT1567.asy @@ -0,0 +1,101 @@ +Version 4 +SymbolType CELL +LINE Normal 80 32 144 0 +LINE Normal 80 -32 144 0 +LINE Normal 80 32 80 -32 +LINE Normal 84 16 92 16 +LINE Normal 84 -16 92 -16 +LINE Normal 88 12 88 20 +LINE Normal -144 -16 -80 -48 +LINE Normal -144 -80 -80 -48 +LINE Normal -144 -16 -144 -80 +LINE Normal -140 -32 -132 -32 +LINE Normal -140 -64 -132 -64 +LINE Normal -136 -36 -136 -28 +LINE Normal 176 0 144 0 +LINE Normal 96 -48 48 -48 +LINE Normal 160 -48 128 -48 +LINE Normal -176 0 -96 0 +LINE Normal -176 0 -176 0 +LINE Normal -144 -32 -160 -32 +LINE Normal -64 -96 -64 -48 +LINE Normal -176 -64 -144 -64 +LINE Normal 64 -16 80 -16 +LINE Normal 64 -48 64 -16 +LINE Normal -176 64 -151 64 +LINE Normal -96 64 -119 64 +LINE Normal -66 74 -66 53 +LINE Normal -71 74 -71 53 +LINE Normal 0 -96 0 -48 +LINE Normal -64 -48 -80 -48 +LINE Normal -96 64 -71 64 +LINE Normal -96 64 -96 0 +LINE Normal 20 -56 16 -48 +LINE Normal 28 -40 20 -56 +LINE Normal 28 -40 36 -56 +LINE Normal 44 -40 36 -56 +LINE Normal 48 -48 44 -40 +LINE Normal 124 -40 128 -48 +LINE Normal 116 -56 124 -40 +LINE Normal 116 -56 108 -40 +LINE Normal 100 -56 108 -40 +LINE Normal 96 -48 100 -56 +LINE Normal -147 56 -151 64 +LINE Normal -139 72 -147 56 +LINE Normal -139 72 -131 56 +LINE Normal -123 72 -131 56 +LINE Normal -119 64 -123 72 +LINE Normal 160 -48 160 0 +LINE Normal 16 -48 0 -48 +LINE Normal -160 0 -160 -32 +LINE Normal 32 64 -66 64 +LINE Normal 64 96 32 64 +LINE Normal -96 16 80 16 +RECTANGLE Normal 176 96 -176 -96 +CIRCLE Normal 63 -47 65 -49 +CIRCLE Normal 62 -46 66 -50 +CIRCLE Normal 61 -45 67 -51 +CIRCLE Normal -161 1 -159 -1 +CIRCLE Normal -162 2 -158 -2 +CIRCLE Normal -163 3 -157 -3 +CIRCLE Normal -97 17 -95 15 +CIRCLE Normal -98 18 -94 14 +CIRCLE Normal -99 19 -93 13 +CIRCLE Normal 159 1 161 -1 +CIRCLE Normal 158 2 162 -2 +CIRCLE Normal 157 3 163 -3 +CIRCLE Normal -97 65 -95 63 +CIRCLE Normal -98 66 -94 62 +CIRCLE Normal -99 67 -93 61 +TEXT 0 -16 Center 2 LT +WINDOW 0 128 -96 Bottom 2 +WINDOW 3 0 37 Center 2 +SYMATTR Value LT1567 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LT1567 +SYMATTR Description 1.4nV per root(Hz) 180MHz Filter Building Block +PIN -64 -96 NONE 8 +PINATTR PinName OAOUT +PINATTR SpiceOrder 1 +PIN -176 -64 NONE 8 +PINATTR PinName GAIN +PINATTR SpiceOrder 2 +PIN -176 0 NONE 8 +PINATTR PinName BYPASS +PINATTR SpiceOrder 3 +PIN 64 96 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN -176 64 NONE 8 +PINATTR PinName DCBIAS +PINATTR SpiceOrder 5 +PIN 0 -96 NONE 8 +PINATTR PinName INVIN +PINATTR SpiceOrder 6 +PIN 176 0 NONE 8 +PINATTR PinName INVOUT +PINATTR SpiceOrder 7 +PIN 64 -96 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/FilterProducts/LT1568.asy b/spice/copy/sym/FilterProducts/LT1568.asy new file mode 100755 index 0000000..dbe1deb --- /dev/null +++ b/spice/copy/sym/FilterProducts/LT1568.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 191 176 -192 -448 +TEXT 1 -339 Center 2 LT +WINDOW 0 3 -458 Center 2 +WINDOW 3 0 -283 Center 2 +SYMATTR Value LT1568 +SYMATTR Prefix X +SYMATTR SpiceModel LT1568.sub +SYMATTR Value2 LT1568 +SYMATTR Description Very Low Noise, High Frequency Active RC, Filter Building Block +PIN -192 -416 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -192 -336 LEFT 8 +PINATTR PinName INVA +PINATTR SpiceOrder 2 +PIN -192 -256 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 3 +PIN -192 -176 LEFT 8 +PINATTR PinName OUTA +PINATTR SpiceOrder 4 +PIN -192 -96 LEFT 8 +PINATTR PinName _OUTA +PINATTR SpiceOrder 5 +PIN -192 -16 LEFT 8 +PINATTR PinName GNDA +PINATTR SpiceOrder 6 +PIN -192 64 LEFT 8 +PINATTR PinName NC +PINATTR SpiceOrder 7 +PIN -192 144 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 8 +PIN 192 144 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 9 +PIN 192 64 RIGHT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 10 +PIN 192 -16 RIGHT 8 +PINATTR PinName GNDB +PINATTR SpiceOrder 11 +PIN 192 -96 RIGHT 8 +PINATTR PinName _OUTB +PINATTR SpiceOrder 12 +PIN 192 -176 RIGHT 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 13 +PIN 192 -256 RIGHT 8 +PINATTR PinName SB +PINATTR SpiceOrder 14 +PIN 192 -336 RIGHT 8 +PINATTR PinName INVB +PINATTR SpiceOrder 15 +PIN 192 -416 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/FilterProducts/LT6600-10.asy b/spice/copy/sym/FilterProducts/LT6600-10.asy new file mode 100755 index 0000000..2a098ad --- /dev/null +++ b/spice/copy/sym/FilterProducts/LT6600-10.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 111 160 -111 -176 +TEXT 0 0 Center 2 LT +WINDOW 3 1 73 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value LT6600-10 +SYMATTR Prefix X +SYMATTR SpiceModel LT6600-10.sub +SYMATTR Value2 LT6600-10 +SYMATTR Description Very Low Noise, Differential Amplifier and 10MHz Lowpass Filter +PIN -112 -128 LEFT 8 +PINATTR PinName IM +PINATTR SpiceOrder 1 +PIN -112 -48 LEFT 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN -112 112 LEFT 8 +PINATTR PinName OP +PINATTR SpiceOrder 4 +PIN 112 112 RIGHT 8 +PINATTR PinName OM +PINATTR SpiceOrder 5 +PIN 112 32 RIGHT 8 +PINATTR PinName VEE +PINATTR SpiceOrder 6 +PIN 112 -48 RIGHT 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN 112 -128 RIGHT 8 +PINATTR PinName IP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/FilterProducts/LT6600-15.asy b/spice/copy/sym/FilterProducts/LT6600-15.asy new file mode 100755 index 0000000..ba86d2c --- /dev/null +++ b/spice/copy/sym/FilterProducts/LT6600-15.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 111 160 -111 -176 +TEXT 0 0 Center 2 LT +WINDOW 3 1 73 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value LT6600-15 +SYMATTR Prefix X +SYMATTR SpiceModel LT6600-15.sub +SYMATTR Value2 LT6600-15 +SYMATTR Description Very Low Noise, Differential Amplifier and 15MHz Lowpass Filter +PIN -112 -128 LEFT 8 +PINATTR PinName IM +PINATTR SpiceOrder 1 +PIN -112 -48 LEFT 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN -112 112 LEFT 8 +PINATTR PinName OP +PINATTR SpiceOrder 4 +PIN 112 112 RIGHT 8 +PINATTR PinName OM +PINATTR SpiceOrder 5 +PIN 112 32 RIGHT 8 +PINATTR PinName VEE +PINATTR SpiceOrder 6 +PIN 112 -48 RIGHT 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN 112 -128 RIGHT 8 +PINATTR PinName IP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/FilterProducts/LT6600-2.5.asy b/spice/copy/sym/FilterProducts/LT6600-2.5.asy new file mode 100755 index 0000000..4f59cd0 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LT6600-2.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 111 160 -111 -176 +TEXT 0 0 Center 2 LT +WINDOW 3 3 77 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value LT6600-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6600-2.5.sub +SYMATTR Value2 LT6600-2.5 +SYMATTR Description Very Low Noise, Differential Amplifier and 2.5MHz Lowpass Filter +PIN -112 -128 LEFT 8 +PINATTR PinName IM +PINATTR SpiceOrder 1 +PIN -112 -48 LEFT 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN -112 112 LEFT 8 +PINATTR PinName OP +PINATTR SpiceOrder 4 +PIN 112 112 RIGHT 8 +PINATTR PinName OM +PINATTR SpiceOrder 5 +PIN 112 32 RIGHT 8 +PINATTR PinName VEE +PINATTR SpiceOrder 6 +PIN 112 -48 RIGHT 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN 112 -128 RIGHT 8 +PINATTR PinName IP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/FilterProducts/LT6600-20.asy b/spice/copy/sym/FilterProducts/LT6600-20.asy new file mode 100755 index 0000000..7a6f248 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LT6600-20.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 111 160 -111 -176 +TEXT 0 0 Center 2 LT +WINDOW 3 0 74 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value LT6600-20 +SYMATTR Prefix X +SYMATTR SpiceModel LT6600-20.sub +SYMATTR Value2 LT6600-20 +SYMATTR Description Very Low Noise, Differential Amplifier and 20MHz Lowpass Filter +PIN -112 -128 LEFT 8 +PINATTR PinName IM +PINATTR SpiceOrder 1 +PIN -112 -48 LEFT 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN -112 112 LEFT 8 +PINATTR PinName OP +PINATTR SpiceOrder 4 +PIN 112 112 RIGHT 8 +PINATTR PinName OM +PINATTR SpiceOrder 5 +PIN 112 32 RIGHT 8 +PINATTR PinName VEE +PINATTR SpiceOrder 6 +PIN 112 -48 RIGHT 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN 112 -128 RIGHT 8 +PINATTR PinName IP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/FilterProducts/LT6600-5.asy b/spice/copy/sym/FilterProducts/LT6600-5.asy new file mode 100755 index 0000000..025f2b2 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LT6600-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 111 160 -111 -176 +TEXT 0 0 Center 2 LT +WINDOW 3 3 77 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value LT6600-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6600-5.sub +SYMATTR Value2 LT6600-5 +SYMATTR Description Very Low Noise, Differential Amplifier and 5MHz Lowpass Filter +PIN -112 -128 LEFT 8 +PINATTR PinName IM +PINATTR SpiceOrder 1 +PIN -112 -48 LEFT 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN -112 112 LEFT 8 +PINATTR PinName OP +PINATTR SpiceOrder 4 +PIN 112 112 RIGHT 8 +PINATTR PinName OM +PINATTR SpiceOrder 5 +PIN 112 32 RIGHT 8 +PINATTR PinName VEE +PINATTR SpiceOrder 6 +PIN 112 -48 RIGHT 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN 112 -128 RIGHT 8 +PINATTR PinName IP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/FilterProducts/LTC1060.asy b/spice/copy/sym/FilterProducts/LTC1060.asy new file mode 100755 index 0000000..8b4f6a4 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1060.asy @@ -0,0 +1,67 @@ +Version 4 +SymbolType CELL +LINE Normal 177 224 -175 224 +RECTANGLE Normal -176 -320 176 384 +TEXT 0 -80 Center 2 LT +TEXT -166 257 Left 2 (Lsh) +TEXT -165 320 Left 2 (CLKA) +TEXT 165 257 Right 2 (50/100) +TEXT 166 321 Right 2 (CLKB) +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 360 Center 2 +WINDOW 123 -11 257 Center 2 +WINDOW 38 0 32 Center 2 +SYMATTR Value fclka=1k fclkb=1k +SYMATTR Value2 divider=50 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1060 +SYMATTR Description Universal Dual Filter Building Block +SYMATTR ModelFile LTC7.lib +PIN -176 -256 LEFT 8 +PINATTR PinName LPA +PINATTR SpiceOrder 1 +PIN -176 -192 LEFT 8 +PINATTR PinName BPA +PINATTR SpiceOrder 2 +PIN -176 -128 LEFT 8 +PINATTR PinName HPA/NA +PINATTR SpiceOrder 3 +PIN -176 -64 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName SA/B +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName VA+ +PINATTR SpiceOrder 7 +PIN -176 192 LEFT 8 +PINATTR PinName VD+ +PINATTR SpiceOrder 8 +PIN 176 192 RIGHT 8 +PINATTR PinName VD- +PINATTR SpiceOrder 9 +PIN 176 128 RIGHT 8 +PINATTR PinName VA- +PINATTR SpiceOrder 10 +PIN 176 64 RIGHT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 11 +PIN 176 0 RIGHT 8 +PINATTR PinName SB +PINATTR SpiceOrder 12 +PIN 176 -64 RIGHT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 13 +PIN 176 -128 RIGHT 8 +PINATTR PinName HPB/NB +PINATTR SpiceOrder 14 +PIN 176 -192 RIGHT 8 +PINATTR PinName BPB +PINATTR SpiceOrder 15 +PIN 176 -256 RIGHT 8 +PINATTR PinName LPB +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/FilterProducts/LTC1067-50.asy b/spice/copy/sym/FilterProducts/LTC1067-50.asy new file mode 100755 index 0000000..9e4a516 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1067-50.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -320 176 256 +TEXT 160 -256 Right 2 (CLK) +TEXT 0 -64 Center 2 LT +TEXT -159 -192 Left 2 NC +TEXT -159 -127 Left 2 V+ +WINDOW 0 0 -128 Center 2 +WINDOW 3 1 -256 Center 2 +WINDOW 38 0 16 Center 2 +SYMATTR Value fclk=500k +SYMATTR SpiceModel LTC1067-50 +SYMATTR Prefix X +SYMATTR Description Rail to Rail, Very Low Noise Universal Dual Filter Building Block\n\nNote: This model is an active RC approximation of a switched capacitor filter. A more accurate LTspice simulation requires use of FilterCAD's LTC1064 100:1 circuit circuit and resistors. +SYMATTR ModelFile LTC7.lib +PIN -176 -256 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN -176 0 LEFT 8 +PINATTR PinName LPA +PINATTR SpiceOrder 3 +PIN -176 64 LEFT 8 +PINATTR PinName BPA +PINATTR SpiceOrder 4 +PIN -176 128 LEFT 8 +PINATTR PinName HPA/NA +PINATTR SpiceOrder 5 +PIN -176 192 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 6 +PIN 176 192 RIGHT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 7 +PIN 176 128 RIGHT 8 +PINATTR PinName HPB/NB +PINATTR SpiceOrder 8 +PIN 176 64 RIGHT 8 +PINATTR PinName BPB +PINATTR SpiceOrder 9 +PIN 176 0 RIGHT 8 +PINATTR PinName LPB +PINATTR SpiceOrder 10 +PIN 176 -64 RIGHT 8 +PINATTR PinName SB +PINATTR SpiceOrder 11 +PIN 176 -128 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 12 +PIN 176 -192 RIGHT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/FilterProducts/LTC1067.asy b/spice/copy/sym/FilterProducts/LTC1067.asy new file mode 100755 index 0000000..d9a83b8 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1067.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -320 176 256 +TEXT 160 -256 Right 2 (CLK) +TEXT 0 -64 Center 2 LT +TEXT -159 -192 Left 2 NC +TEXT -159 -127 Left 2 V+ +WINDOW 0 0 -128 Center 2 +WINDOW 3 1 -256 Center 2 +WINDOW 38 0 16 Center 2 +SYMATTR Value fclk=500k +SYMATTR SpiceModel LTC1067 +SYMATTR Prefix X +SYMATTR Description Rail to Rail, Very Low Noise Universal Dual Filter Building Block\n\nNote: This model is an active RC approximation of a switched capacitor filter. A more accurate LTspice simulation requires use of FilterCAD's LTC1064 100:1 circuit circuit and resistors. +SYMATTR ModelFile LTC7.lib +PIN -176 -256 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN -176 0 LEFT 8 +PINATTR PinName LPA +PINATTR SpiceOrder 3 +PIN -176 64 LEFT 8 +PINATTR PinName BPA +PINATTR SpiceOrder 4 +PIN -176 128 LEFT 8 +PINATTR PinName HPA/NA +PINATTR SpiceOrder 5 +PIN -176 192 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 6 +PIN 176 192 RIGHT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 7 +PIN 176 128 RIGHT 8 +PINATTR PinName HPB/NB +PINATTR SpiceOrder 8 +PIN 176 64 RIGHT 8 +PINATTR PinName BPB +PINATTR SpiceOrder 9 +PIN 176 0 RIGHT 8 +PINATTR PinName LPB +PINATTR SpiceOrder 10 +PIN 176 -64 RIGHT 8 +PINATTR PinName SB +PINATTR SpiceOrder 11 +PIN 176 -128 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 12 +PIN 176 -192 RIGHT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/FilterProducts/LTC1068-200.asy b/spice/copy/sym/FilterProducts/LTC1068-200.asy new file mode 100755 index 0000000..b1232cd --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1068-200.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -320 176 640 +TEXT 160 192 Right 2 (CLK) +TEXT 0 -64 Center 2 LT +TEXT -160 64 Left 2 NC +TEXT -160 256 Left 2 NC +TEXT 160 128 Right 2 NC +TEXT 160 256 Right 2 NC +WINDOW 0 0 -128 Center 2 +WINDOW 3 1 -256 Center 2 +WINDOW 38 0 16 Center 2 +SYMATTR Value Fclk=500K +SYMATTR SpiceModel LTC1068-200 +SYMATTR Prefix X +SYMATTR Description Clock-Tunable, Quad Second Order, Filter Building Blocks\n\nNote: This model is an active RC approximation of a switched capacitor filter. A more accurate LTspice simulation requires use of FilterCAD's LTC1064 100:1 circuit and resistors. +SYMATTR ModelFile LTC4.lib +PIN -176 -256 LEFT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 1 +PIN -176 -192 LEFT 8 +PINATTR PinName HPB/NB +PINATTR SpiceOrder 2 +PIN -176 -128 LEFT 8 +PINATTR PinName BPB +PINATTR SpiceOrder 3 +PIN -176 -64 LEFT 8 +PINATTR PinName LPB +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName SB +PINATTR SpiceOrder 5 +PIN -176 128 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 6 +PIN -176 192 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN -176 320 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 8 +PIN -176 384 LEFT 8 +PINATTR PinName LPA +PINATTR SpiceOrder 9 +PIN -176 448 LEFT 8 +PINATTR PinName BPA +PINATTR SpiceOrder 10 +PIN -176 512 LEFT 8 +PINATTR PinName HPA/NA +PINATTR SpiceOrder 11 +PIN -176 576 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 12 +PIN 176 576 RIGHT 8 +PINATTR PinName INV D +PINATTR SpiceOrder 13 +PIN 176 512 RIGHT 8 +PINATTR PinName HPD/ND +PINATTR SpiceOrder 14 +PIN 176 448 RIGHT 8 +PINATTR PinName BPD +PINATTR SpiceOrder 15 +PIN 176 384 RIGHT 8 +PINATTR PinName LPD +PINATTR SpiceOrder 16 +PIN 176 320 RIGHT 8 +PINATTR PinName SD +PINATTR SpiceOrder 17 +PIN 176 64 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 18 +PIN 176 0 RIGHT 8 +PINATTR PinName SC +PINATTR SpiceOrder 19 +PIN 176 -64 RIGHT 8 +PINATTR PinName LPC +PINATTR SpiceOrder 20 +PIN 176 -128 RIGHT 8 +PINATTR PinName BPC +PINATTR SpiceOrder 21 +PIN 176 -192 RIGHT 8 +PINATTR PinName HPC/NC +PINATTR SpiceOrder 22 +PIN 176 -256 RIGHT 8 +PINATTR PinName INV C +PINATTR SpiceOrder 23 diff --git a/spice/copy/sym/FilterProducts/LTC1068-25.asy b/spice/copy/sym/FilterProducts/LTC1068-25.asy new file mode 100755 index 0000000..93a69e5 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1068-25.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -320 176 640 +TEXT 160 192 Right 2 (CLK) +TEXT 0 -64 Center 2 LT +TEXT -160 64 Left 2 NC +TEXT -160 256 Left 2 NC +TEXT 160 128 Right 2 NC +TEXT 160 256 Right 2 NC +WINDOW 0 0 -128 Center 2 +WINDOW 3 1 -256 Center 2 +WINDOW 38 0 16 Center 2 +SYMATTR Value Fclk=500K +SYMATTR SpiceModel LTC1068-25 +SYMATTR Prefix X +SYMATTR Description Clock-Tunable, Quad Second Order, Filter Building Blocks\n\nNote: This model is an active RC approximation of a switched capacitor filter. A more accurate LTspice simulation requires use of FilterCAD's LTC1064 100:1 circuit and resistors. +SYMATTR ModelFile LTC4.lib +PIN -176 -256 LEFT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 1 +PIN -176 -192 LEFT 8 +PINATTR PinName HPB/NB +PINATTR SpiceOrder 2 +PIN -176 -128 LEFT 8 +PINATTR PinName BPB +PINATTR SpiceOrder 3 +PIN -176 -64 LEFT 8 +PINATTR PinName LPB +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName SB +PINATTR SpiceOrder 5 +PIN -176 128 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 6 +PIN -176 192 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN -176 320 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 8 +PIN -176 384 LEFT 8 +PINATTR PinName LPA +PINATTR SpiceOrder 9 +PIN -176 448 LEFT 8 +PINATTR PinName BPA +PINATTR SpiceOrder 10 +PIN -176 512 LEFT 8 +PINATTR PinName HPA/NA +PINATTR SpiceOrder 11 +PIN -176 576 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 12 +PIN 176 576 RIGHT 8 +PINATTR PinName INV D +PINATTR SpiceOrder 13 +PIN 176 512 RIGHT 8 +PINATTR PinName HPD/ND +PINATTR SpiceOrder 14 +PIN 176 448 RIGHT 8 +PINATTR PinName BPD +PINATTR SpiceOrder 15 +PIN 176 384 RIGHT 8 +PINATTR PinName LPD +PINATTR SpiceOrder 16 +PIN 176 320 RIGHT 8 +PINATTR PinName SD +PINATTR SpiceOrder 17 +PIN 176 64 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 18 +PIN 176 0 RIGHT 8 +PINATTR PinName SC +PINATTR SpiceOrder 19 +PIN 176 -64 RIGHT 8 +PINATTR PinName LPC +PINATTR SpiceOrder 20 +PIN 176 -128 RIGHT 8 +PINATTR PinName BPC +PINATTR SpiceOrder 21 +PIN 176 -192 RIGHT 8 +PINATTR PinName HPC/NC +PINATTR SpiceOrder 22 +PIN 176 -256 RIGHT 8 +PINATTR PinName INV C +PINATTR SpiceOrder 23 diff --git a/spice/copy/sym/FilterProducts/LTC1068-50.asy b/spice/copy/sym/FilterProducts/LTC1068-50.asy new file mode 100755 index 0000000..0b9468a --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1068-50.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -320 176 640 +TEXT 160 192 Right 2 (CLK) +TEXT 0 -64 Center 2 LT +TEXT -160 64 Left 2 NC +TEXT -160 256 Left 2 NC +TEXT 160 128 Right 2 NC +TEXT 160 256 Right 2 NC +WINDOW 0 0 -128 Center 2 +WINDOW 3 1 -256 Center 2 +WINDOW 38 0 16 Center 2 +SYMATTR Value Fclk=500K +SYMATTR SpiceModel LTC1068-50 +SYMATTR Prefix X +SYMATTR Description Clock-Tunable, Quad Second Order, Filter Building Blocks\n\nNote: This model is an active RC approximation of a switched capacitor filter. A more accurate LTspice simulation requires use of FilterCAD's LTC1064 100:1 circuit and resistors. +SYMATTR ModelFile LTC4.lib +PIN -176 -256 LEFT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 1 +PIN -176 -192 LEFT 8 +PINATTR PinName HPB/NB +PINATTR SpiceOrder 2 +PIN -176 -128 LEFT 8 +PINATTR PinName BPB +PINATTR SpiceOrder 3 +PIN -176 -64 LEFT 8 +PINATTR PinName LPB +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName SB +PINATTR SpiceOrder 5 +PIN -176 128 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 6 +PIN -176 192 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN -176 320 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 8 +PIN -176 384 LEFT 8 +PINATTR PinName LPA +PINATTR SpiceOrder 9 +PIN -176 448 LEFT 8 +PINATTR PinName BPA +PINATTR SpiceOrder 10 +PIN -176 512 LEFT 8 +PINATTR PinName HPA/NA +PINATTR SpiceOrder 11 +PIN -176 576 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 12 +PIN 176 576 RIGHT 8 +PINATTR PinName INV D +PINATTR SpiceOrder 13 +PIN 176 512 RIGHT 8 +PINATTR PinName HPD/ND +PINATTR SpiceOrder 14 +PIN 176 448 RIGHT 8 +PINATTR PinName BPD +PINATTR SpiceOrder 15 +PIN 176 384 RIGHT 8 +PINATTR PinName LPD +PINATTR SpiceOrder 16 +PIN 176 320 RIGHT 8 +PINATTR PinName SD +PINATTR SpiceOrder 17 +PIN 176 64 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 18 +PIN 176 0 RIGHT 8 +PINATTR PinName SC +PINATTR SpiceOrder 19 +PIN 176 -64 RIGHT 8 +PINATTR PinName LPC +PINATTR SpiceOrder 20 +PIN 176 -128 RIGHT 8 +PINATTR PinName BPC +PINATTR SpiceOrder 21 +PIN 176 -192 RIGHT 8 +PINATTR PinName HPC/NC +PINATTR SpiceOrder 22 +PIN 176 -256 RIGHT 8 +PINATTR PinName INV C +PINATTR SpiceOrder 23 diff --git a/spice/copy/sym/FilterProducts/LTC1068.asy b/spice/copy/sym/FilterProducts/LTC1068.asy new file mode 100755 index 0000000..81e489f --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1068.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -320 176 640 +TEXT 160 192 Right 2 (CLK) +TEXT 0 -64 Center 2 LT +TEXT -160 64 Left 2 NC +TEXT -160 256 Left 2 NC +TEXT 160 128 Right 2 NC +TEXT 160 256 Right 2 NC +WINDOW 0 0 -128 Center 2 +WINDOW 3 1 -256 Center 2 +WINDOW 38 0 16 Center 2 +SYMATTR Value Fclk=500K +SYMATTR SpiceModel LTC1068 +SYMATTR Prefix X +SYMATTR Description Clock-Tunable, Quad Second Order, Filter Building Blocks\n\nNote: This model is an active RC approximation of a switched capacitor filter. A more accurate LTspice simulation requires use of FilterCAD's LTC1064 100:1 circuit and resistors. +SYMATTR ModelFile LTC4.lib +PIN -176 -256 LEFT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 1 +PIN -176 -192 LEFT 8 +PINATTR PinName HPB/NB +PINATTR SpiceOrder 2 +PIN -176 -128 LEFT 8 +PINATTR PinName BPB +PINATTR SpiceOrder 3 +PIN -176 -64 LEFT 8 +PINATTR PinName LPB +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName SB +PINATTR SpiceOrder 5 +PIN -176 128 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 6 +PIN -176 192 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN -176 320 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 8 +PIN -176 384 LEFT 8 +PINATTR PinName LPA +PINATTR SpiceOrder 9 +PIN -176 448 LEFT 8 +PINATTR PinName BPA +PINATTR SpiceOrder 10 +PIN -176 512 LEFT 8 +PINATTR PinName HPA/NA +PINATTR SpiceOrder 11 +PIN -176 576 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 12 +PIN 176 576 RIGHT 8 +PINATTR PinName INV D +PINATTR SpiceOrder 13 +PIN 176 512 RIGHT 8 +PINATTR PinName HPD/ND +PINATTR SpiceOrder 14 +PIN 176 448 RIGHT 8 +PINATTR PinName BPD +PINATTR SpiceOrder 15 +PIN 176 384 RIGHT 8 +PINATTR PinName LPD +PINATTR SpiceOrder 16 +PIN 176 320 RIGHT 8 +PINATTR PinName SD +PINATTR SpiceOrder 17 +PIN 176 64 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 18 +PIN 176 0 RIGHT 8 +PINATTR PinName SC +PINATTR SpiceOrder 19 +PIN 176 -64 RIGHT 8 +PINATTR PinName LPC +PINATTR SpiceOrder 20 +PIN 176 -128 RIGHT 8 +PINATTR PinName BPC +PINATTR SpiceOrder 21 +PIN 176 -192 RIGHT 8 +PINATTR PinName HPC/NC +PINATTR SpiceOrder 22 +PIN 176 -256 RIGHT 8 +PINATTR PinName INV C +PINATTR SpiceOrder 23 diff --git a/spice/copy/sym/FilterProducts/LTC1562-2.asy b/spice/copy/sym/FilterProducts/LTC1562-2.asy new file mode 100755 index 0000000..9b20888 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1562-2.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -256 176 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1562-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1562-2.sub +SYMATTR Value2 LTC1562-2 +SYMATTR Description Very Low Noise, Low Distortion Active RC Quad Universal Filter NOTE: GBW, slew rate and noise are modeled in this otherwise highly idealized macromodel. +PIN -176 -224 LEFT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 1 +PIN -176 -160 LEFT 8 +PINATTR PinName V1 B +PINATTR SpiceOrder 2 +PIN -176 -96 LEFT 8 +PINATTR PinName V2 B +PINATTR SpiceOrder 3 +PIN -176 -32 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN -176 96 LEFT 8 +PINATTR PinName V2 A +PINATTR SpiceOrder 8 +PIN -176 160 LEFT 8 +PINATTR PinName V1 A +PINATTR SpiceOrder 9 +PIN -176 224 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName INV D +PINATTR SpiceOrder 11 +PIN 176 160 RIGHT 8 +PINATTR PinName V1 D +PINATTR SpiceOrder 12 +PIN 176 96 RIGHT 8 +PINATTR PinName V2 D +PINATTR SpiceOrder 13 +PIN 176 32 RIGHT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 15 +PIN 176 -32 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 16 +PIN 176 -96 RIGHT 8 +PINATTR PinName V2 C +PINATTR SpiceOrder 18 +PIN 176 -160 RIGHT 8 +PINATTR PinName V1 C +PINATTR SpiceOrder 19 +PIN 176 -224 RIGHT 8 +PINATTR PinName INV C +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/FilterProducts/LTC1562.asy b/spice/copy/sym/FilterProducts/LTC1562.asy new file mode 100755 index 0000000..ae0057a --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1562.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -256 176 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1562 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1562.sub +SYMATTR Value2 LTC1562 +SYMATTR Description Very Low Noise, Low Distortion Active RC Quad Universal Filter NOTE: GBW, slew rate and noise are modeled in this otherwise highly idealized macromodel. +PIN -176 -224 LEFT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 1 +PIN -176 -160 LEFT 8 +PINATTR PinName V1 B +PINATTR SpiceOrder 2 +PIN -176 -96 LEFT 8 +PINATTR PinName V2 B +PINATTR SpiceOrder 3 +PIN -176 -32 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN -176 96 LEFT 8 +PINATTR PinName V2 A +PINATTR SpiceOrder 8 +PIN -176 160 LEFT 8 +PINATTR PinName V1 A +PINATTR SpiceOrder 9 +PIN -176 224 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName INV D +PINATTR SpiceOrder 11 +PIN 176 160 RIGHT 8 +PINATTR PinName V1 D +PINATTR SpiceOrder 12 +PIN 176 96 RIGHT 8 +PINATTR PinName V2 D +PINATTR SpiceOrder 13 +PIN 176 32 RIGHT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 15 +PIN 176 -32 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 16 +PIN 176 -96 RIGHT 8 +PINATTR PinName V2 C +PINATTR SpiceOrder 18 +PIN 176 -160 RIGHT 8 +PINATTR PinName V1 C +PINATTR SpiceOrder 19 +PIN 176 -224 RIGHT 8 +PINATTR PinName INV C +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/FilterProducts/LTC1562A.asy b/spice/copy/sym/FilterProducts/LTC1562A.asy new file mode 100755 index 0000000..7734226 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1562A.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -256 176 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1562A +SYMATTR Prefix X +SYMATTR SpiceModel LTC1562.sub +SYMATTR Value2 LTC1562 +SYMATTR Description Very Low Noise, Low Distortion Active RC Quad Universal Filter NOTE: GBW, slew rate and noise are modeled in this otherwise highly idealized macromodel. +PIN -176 -224 LEFT 8 +PINATTR PinName INV B +PINATTR SpiceOrder 1 +PIN -176 -160 LEFT 8 +PINATTR PinName V1 B +PINATTR SpiceOrder 2 +PIN -176 -96 LEFT 8 +PINATTR PinName V2 B +PINATTR SpiceOrder 3 +PIN -176 -32 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN -176 96 LEFT 8 +PINATTR PinName V2 A +PINATTR SpiceOrder 8 +PIN -176 160 LEFT 8 +PINATTR PinName V1 A +PINATTR SpiceOrder 9 +PIN -176 224 LEFT 8 +PINATTR PinName INV A +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName INV D +PINATTR SpiceOrder 11 +PIN 176 160 RIGHT 8 +PINATTR PinName V1 D +PINATTR SpiceOrder 12 +PIN 176 96 RIGHT 8 +PINATTR PinName V2 D +PINATTR SpiceOrder 13 +PIN 176 32 RIGHT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 15 +PIN 176 -32 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 16 +PIN 176 -96 RIGHT 8 +PINATTR PinName V2 C +PINATTR SpiceOrder 18 +PIN 176 -160 RIGHT 8 +PINATTR PinName V1 C +PINATTR SpiceOrder 19 +PIN 176 -224 RIGHT 8 +PINATTR PinName INV C +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/FilterProducts/LTC1563-2.asy b/spice/copy/sym/FilterProducts/LTC1563-2.asy new file mode 100755 index 0000000..c1ef2a9 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1563-2.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 143 96 -144 -368 +TEXT 0 -215 Center 2 LT +WINDOW 0 -1 -296 Center 2 +WINDOW 3 1 -48 Center 2 +SYMATTR Value LTC1563-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LTC1563-2 +SYMATTR Description Active RC, 4th Order Lowpass Filter +PIN -144 -336 LEFT 8 +PINATTR PinName _LP +PINATTR SpiceOrder 1 +PIN -144 -256 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN -144 -176 LEFT 8 +PINATTR PinName INVA +PINATTR SpiceOrder 3 +PIN -144 -96 LEFT 8 +PINATTR PinName LPA +PINATTR SpiceOrder 4 +PIN -144 -16 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN -144 64 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SB +PINATTR SpiceOrder 8 +PIN 144 -176 RIGHT 8 +PINATTR PinName INVB +PINATTR SpiceOrder 9 +PIN 144 -256 RIGHT 8 +PINATTR PinName LPB +PINATTR SpiceOrder 10 +PIN 144 -336 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/FilterProducts/LTC1563-3.asy b/spice/copy/sym/FilterProducts/LTC1563-3.asy new file mode 100755 index 0000000..95db905 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1563-3.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 143 96 -144 -368 +TEXT 0 -216 Center 2 LT +WINDOW 0 0 -296 Center 2 +WINDOW 3 0 -55 Center 2 +SYMATTR Value LTC1563-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LTC1563-3 +SYMATTR Description Active RC, 4th Order Lowpass Filter +PIN -144 -336 LEFT 8 +PINATTR PinName _LP +PINATTR SpiceOrder 1 +PIN -144 -256 LEFT 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN -144 -176 LEFT 8 +PINATTR PinName INVA +PINATTR SpiceOrder 3 +PIN -144 -96 LEFT 8 +PINATTR PinName LPA +PINATTR SpiceOrder 4 +PIN -144 -16 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN -144 64 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SB +PINATTR SpiceOrder 8 +PIN 144 -176 RIGHT 8 +PINATTR PinName INVB +PINATTR SpiceOrder 9 +PIN 144 -256 RIGHT 8 +PINATTR PinName LPB +PINATTR SpiceOrder 10 +PIN 144 -336 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/FilterProducts/LTC1565.asy b/spice/copy/sym/FilterProducts/LTC1565.asy new file mode 100755 index 0000000..bb0604d --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC1565.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 161 -144 -144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 1 86 Center 2 +SYMATTR Value LTC1565 +SYMATTR Description Linear Phase, High Frequency Lowpass Filter +SYMATTR Prefix X +SYMATTR ModelFile LTC1565.sub +SYMATTR SpiceLine vvar=0 fvar=0 gvar=0 +PIN -144 -112 LEFT 8 +PINATTR PinName +IN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName -IN +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 128 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 144 128 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName -OUT +PINATTR SpiceOrder 7 +PIN 144 -112 RIGHT 8 +PINATTR PinName +OUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/FilterProducts/LTC6601-1.asy b/spice/copy/sym/FilterProducts/LTC6601-1.asy new file mode 100755 index 0000000..0da7cfa --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC6601-1.asy @@ -0,0 +1,82 @@ +Version 4 +SymbolType BLOCK +LINE Normal 80 64 80 -64 +LINE Normal 192 0 80 64 +LINE Normal 80 -64 192 0 +LINE Normal 87 -32 105 -32 +LINE Normal 96 -41 96 -23 +LINE Normal 87 32 105 32 +LINE Normal 131 -8 106 -8 +LINE Normal 146 6 131 -8 +LINE Normal 137 32 208 32 +LINE Normal 157 -32 208 -32 +RECTANGLE Normal 208 224 -224 -224 +CIRCLE Normal 157 -25 143 -39 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC6601-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6601-1 +SYMATTR Description Low Noise, 0.5% Tolerance, 5MHz to 28MHz, Pin Configurable Filter/ADC Driver +PIN -224 -128 LEFT 8 +PINATTR PinName IN2+ +PINATTR SpiceOrder 1 +PIN -224 -64 LEFT 8 +PINATTR PinName IN1+ +PINATTR SpiceOrder 2 +PIN -224 0 LEFT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 3 +PIN -224 64 LEFT 8 +PINATTR PinName IN1- +PINATTR SpiceOrder 4 +PIN -224 128 LEFT 8 +PINATTR PinName IN2- +PINATTR SpiceOrder 5 +PIN -224 192 LEFT 8 +PINATTR PinName IN4- +PINATTR SpiceOrder 6 +PIN -112 224 BOTTOM 8 +PINATTR PinName C1 +PINATTR SpiceOrder 7 +PIN -48 224 BOTTOM 8 +PINATTR PinName C2 +PINATTR SpiceOrder 8 +PIN 16 224 BOTTOM 8 +PINATTR PinName C3 +PINATTR SpiceOrder 9 +PIN 80 224 BOTTOM 8 +PINATTR PinName C4 +PINATTR SpiceOrder 10 +PIN 208 32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 11 +PIN 208 128 RIGHT 8 +PINATTR PinName Vocm +PINATTR SpiceOrder 12 +PIN 144 224 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 13 +PIN 144 -224 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 14 +PIN 208 -32 NONE 8 +PINATTR PinName OUT-1 +PINATTR SpiceOrder 15 +PIN 80 -224 TOP 8 +PINATTR PinName C8 +PINATTR SpiceOrder 16 +PIN 16 -224 TOP 8 +PINATTR PinName C7 +PINATTR SpiceOrder 17 +PIN -48 -224 TOP 8 +PINATTR PinName C6 +PINATTR SpiceOrder 18 +PIN -112 -224 TOP 8 +PINATTR PinName C5 +PINATTR SpiceOrder 19 +PIN -224 -192 LEFT 8 +PINATTR PinName IN4+ +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/FilterProducts/LTC6601-2.asy b/spice/copy/sym/FilterProducts/LTC6601-2.asy new file mode 100755 index 0000000..86304a9 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC6601-2.asy @@ -0,0 +1,82 @@ +Version 4 +SymbolType BLOCK +LINE Normal 80 64 80 -64 +LINE Normal 192 0 80 64 +LINE Normal 80 -64 192 0 +LINE Normal 87 -32 105 -32 +LINE Normal 96 -41 96 -23 +LINE Normal 87 32 105 32 +LINE Normal 131 -8 106 -8 +LINE Normal 146 6 131 -8 +LINE Normal 137 32 208 32 +LINE Normal 157 -32 208 -32 +RECTANGLE Normal 208 224 -224 -224 +CIRCLE Normal 157 -25 143 -39 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC6601-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6601-1 +SYMATTR Description Low Power, Low Distortion, Low Power, Low Distortion, 5MHz to 27MHz, Pin Configurable Filter/ADC Driver +PIN -224 -128 LEFT 8 +PINATTR PinName IN2+ +PINATTR SpiceOrder 1 +PIN -224 -64 LEFT 8 +PINATTR PinName IN1+ +PINATTR SpiceOrder 2 +PIN -224 0 LEFT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 3 +PIN -224 64 LEFT 8 +PINATTR PinName IN1- +PINATTR SpiceOrder 4 +PIN -224 128 LEFT 8 +PINATTR PinName IN2- +PINATTR SpiceOrder 5 +PIN -224 192 LEFT 8 +PINATTR PinName IN4- +PINATTR SpiceOrder 6 +PIN -112 224 BOTTOM 8 +PINATTR PinName C1 +PINATTR SpiceOrder 7 +PIN -48 224 BOTTOM 8 +PINATTR PinName C2 +PINATTR SpiceOrder 8 +PIN 16 224 BOTTOM 8 +PINATTR PinName C3 +PINATTR SpiceOrder 9 +PIN 80 224 BOTTOM 8 +PINATTR PinName C4 +PINATTR SpiceOrder 10 +PIN 208 32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 11 +PIN 208 128 RIGHT 8 +PINATTR PinName Vocm +PINATTR SpiceOrder 12 +PIN 144 224 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 13 +PIN 144 -224 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 14 +PIN 208 -32 NONE 8 +PINATTR PinName OUT-1 +PINATTR SpiceOrder 15 +PIN 80 -224 TOP 8 +PINATTR PinName C8 +PINATTR SpiceOrder 16 +PIN 16 -224 TOP 8 +PINATTR PinName C7 +PINATTR SpiceOrder 17 +PIN -48 -224 TOP 8 +PINATTR PinName C6 +PINATTR SpiceOrder 18 +PIN -112 -224 TOP 8 +PINATTR PinName C5 +PINATTR SpiceOrder 19 +PIN -224 -192 LEFT 8 +PINATTR PinName IN4+ +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/FilterProducts/LTC6605-10.asy b/spice/copy/sym/FilterProducts/LTC6605-10.asy new file mode 100755 index 0000000..d48c588 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC6605-10.asy @@ -0,0 +1,52 @@ +Version 4 +SymbolType BLOCK +LINE Normal 48 64 48 -64 +LINE Normal 160 0 48 64 +LINE Normal 48 -64 160 0 +LINE Normal 55 -32 73 -32 +LINE Normal 64 -41 64 -23 +LINE Normal 55 32 73 32 +LINE Normal 99 -8 74 -8 +LINE Normal 114 6 99 -8 +LINE Normal 104 32 176 32 +LINE Normal 125 -32 176 -32 +RECTANGLE Normal 176 160 -192 -160 +CIRCLE Normal 125 -25 111 -39 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC6605-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6605-10 +SYMATTR Description Dual Matched 10MHz Filter with Low Noise, Low Distortion Differential Amplifier +PIN -192 -128 LEFT 8 +PINATTR PinName IN4+ +PINATTR SpiceOrder 1 +PIN -192 -64 LEFT 8 +PINATTR PinName IN1+ +PINATTR SpiceOrder 2 +PIN -192 0 LEFT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 3 +PIN -192 64 LEFT 8 +PINATTR PinName IN1- +PINATTR SpiceOrder 4 +PIN -192 128 LEFT 8 +PINATTR PinName IN4- +PINATTR SpiceOrder 5 +PIN 176 32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 6 +PIN 176 96 RIGHT 8 +PINATTR PinName Vocm +PINATTR SpiceOrder 7 +PIN 80 160 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 8 +PIN 80 -160 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN 176 -32 NONE 8 +PINATTR PinName OUT-1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/FilterProducts/LTC6605-14.asy b/spice/copy/sym/FilterProducts/LTC6605-14.asy new file mode 100755 index 0000000..4074bf2 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC6605-14.asy @@ -0,0 +1,52 @@ +Version 4 +SymbolType BLOCK +LINE Normal 48 64 48 -64 +LINE Normal 160 0 48 64 +LINE Normal 48 -64 160 0 +LINE Normal 55 -32 73 -32 +LINE Normal 64 -41 64 -23 +LINE Normal 55 32 73 32 +LINE Normal 99 -8 74 -8 +LINE Normal 114 6 99 -8 +LINE Normal 104 32 176 32 +LINE Normal 125 -32 176 -32 +RECTANGLE Normal 176 160 -192 -160 +CIRCLE Normal 125 -25 111 -39 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC6605-14 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6605-14 +SYMATTR Description Dual Matched 14MHz Filter with Low Noise, Low Distortion Differential Amplifier +PIN -192 -128 LEFT 8 +PINATTR PinName IN4+ +PINATTR SpiceOrder 1 +PIN -192 -64 LEFT 8 +PINATTR PinName IN1+ +PINATTR SpiceOrder 2 +PIN -192 0 LEFT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 3 +PIN -192 64 LEFT 8 +PINATTR PinName IN1- +PINATTR SpiceOrder 4 +PIN -192 128 LEFT 8 +PINATTR PinName IN4- +PINATTR SpiceOrder 5 +PIN 176 32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 6 +PIN 176 96 RIGHT 8 +PINATTR PinName Vocm +PINATTR SpiceOrder 7 +PIN 80 160 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 8 +PIN 80 -160 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN 176 -32 NONE 8 +PINATTR PinName OUT-1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/FilterProducts/LTC6605-7.asy b/spice/copy/sym/FilterProducts/LTC6605-7.asy new file mode 100755 index 0000000..3f9bcf2 --- /dev/null +++ b/spice/copy/sym/FilterProducts/LTC6605-7.asy @@ -0,0 +1,52 @@ +Version 4 +SymbolType BLOCK +LINE Normal 48 64 48 -64 +LINE Normal 160 0 48 64 +LINE Normal 48 -64 160 0 +LINE Normal 55 -32 73 -32 +LINE Normal 64 -41 64 -23 +LINE Normal 55 32 73 32 +LINE Normal 99 -8 74 -8 +LINE Normal 114 6 99 -8 +LINE Normal 104 32 176 32 +LINE Normal 125 -32 176 -32 +RECTANGLE Normal 176 160 -192 -160 +CIRCLE Normal 125 -25 111 -39 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 97 Center 2 +SYMATTR Value LTC6605-7 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6605-7 +SYMATTR Description Dual Matched 7MHz Filter with Low Noise, Low Distortion Differential Amplifier +PIN -192 -128 LEFT 8 +PINATTR PinName IN4+ +PINATTR SpiceOrder 1 +PIN -192 -64 LEFT 8 +PINATTR PinName IN1+ +PINATTR SpiceOrder 2 +PIN -192 0 LEFT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 3 +PIN -192 64 LEFT 8 +PINATTR PinName IN1- +PINATTR SpiceOrder 4 +PIN -192 128 LEFT 8 +PINATTR PinName IN4- +PINATTR SpiceOrder 5 +PIN 176 32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 6 +PIN 176 96 RIGHT 8 +PINATTR PinName Vocm +PINATTR SpiceOrder 7 +PIN 80 160 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 8 +PIN 80 -160 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN 176 -32 NONE 8 +PINATTR PinName OUT-1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/ISO16750-2.asy b/spice/copy/sym/ISO16750-2.asy new file mode 100755 index 0000000..a251db3 --- /dev/null +++ b/spice/copy/sym/ISO16750-2.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType CELL +LINE Normal 0 80 0 72 +LINE Normal 0 0 0 8 +LINE Normal -8 55 -8 18 +LINE Normal -18 55 -8 55 +CIRCLE Normal -32 8 32 72 +ARC Normal -8 -18 50 55 -8 18 20 55 +WINDOW 0 48 16 Left 2 +WINDOW 38 48 64 Left 2 +WINDOW 1 48 40 Left 2 +SYMATTR SpiceModel 4-6-3_12V_StartingProfile +SYMATTR Description ISO-16750-2 Transients +SYMATTR Prefix X +SYMATTR ModelFile ISO16750-2.lib +PIN 0 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/ISO7637-2.asy b/spice/copy/sym/ISO7637-2.asy new file mode 100755 index 0000000..9036169 --- /dev/null +++ b/spice/copy/sym/ISO7637-2.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType CELL +LINE Normal 0 80 0 72 +LINE Normal 0 0 0 8 +LINE Normal -8 55 -8 18 +LINE Normal -18 55 -8 55 +CIRCLE Normal -32 8 32 72 +ARC Normal -8 -18 50 55 -8 18 20 55 +WINDOW 0 48 16 Left 2 +WINDOW 38 48 64 Left 2 +WINDOW 1 48 40 Left 2 +SYMATTR SpiceModel Pulse1_12V +SYMATTR Description ISO-7637-2 Transeints +SYMATTR Prefix X +SYMATTR ModelFile ISO7637-2.lib +PIN 0 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/LED.asy b/spice/copy/sym/LED.asy new file mode 100755 index 0000000..07b460e --- /dev/null +++ b/spice/copy/sym/LED.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType CELL +LINE Normal 0 44 32 44 +LINE Normal 0 20 32 20 +LINE Normal 32 20 16 44 +LINE Normal 0 20 16 44 +LINE Normal 16 0 16 20 +LINE Normal 16 44 16 64 +LINE Normal 72 32 68 40 +LINE Normal 72 32 64 32 +LINE Normal 72 48 68 56 +LINE Normal 72 48 64 48 +ARC Normal 40 20 56 36 56 28 40 24 +ARC Normal 56 20 72 36 56 28 72 32 +ARC Normal 40 36 56 52 56 44 40 40 +ARC Normal 56 36 72 52 56 44 72 48 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 64 Left 2 +SYMATTR Value D +SYMATTR Prefix D +SYMATTR Description Light Emitting Diode +PIN 16 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/DIAC.asy b/spice/copy/sym/Misc/DIAC.asy new file mode 100755 index 0000000..c506f3b --- /dev/null +++ b/spice/copy/sym/Misc/DIAC.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 0 44 36 44 +LINE Normal 0 20 36 20 +LINE Normal 36 20 20 44 +LINE Normal 4 20 20 44 +LINE Normal 32 0 32 20 +LINE Normal 32 44 32 64 +LINE Normal 28 44 64 44 +LINE Normal 28 44 44 20 +LINE Normal 44 20 60 44 +LINE Normal 36 20 64 20 +WINDOW 0 48 0 Left 2 +WINDOW 3 48 72 Left 2 +SYMATTR Value DIAC +SYMATTR Prefix X +SYMATTR Description Generic Bi-directional Trigger Device symbol for use with a model that you supply +PIN 32 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 32 64 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/DIP10.asy b/spice/copy/sym/Misc/DIP10.asy new file mode 100755 index 0000000..ddf02a3 --- /dev/null +++ b/spice/copy/sym/Misc/DIP10.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 192 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 32 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 216 Center 2 +SYMATTR Prefix X +SYMATTR Description Generic Symbol for use with subcircuts that you supply. +PIN -144 -96 LEFT 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 144 160 RIGHT 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 144 96 RIGHT 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 144 32 RIGHT 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 144 -32 RIGHT 8 +PINATTR PinName 9 +PINATTR SpiceOrder 9 +PIN 144 -96 RIGHT 8 +PINATTR PinName 10 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/Misc/DIP14.asy b/spice/copy/sym/Misc/DIP14.asy new file mode 100755 index 0000000..5b88376 --- /dev/null +++ b/spice/copy/sym/Misc/DIP14.asy @@ -0,0 +1,55 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 320 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 96 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 336 Center 2 +SYMATTR Prefix X +SYMATTR Description Generic Symbol for use with subcircuts that you supply. +PIN -144 -96 LEFT 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN -144 224 LEFT 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN -144 288 LEFT 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 144 288 RIGHT 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 144 224 RIGHT 8 +PINATTR PinName 9 +PINATTR SpiceOrder 9 +PIN 144 160 RIGHT 8 +PINATTR PinName 10 +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName 11 +PINATTR SpiceOrder 11 +PIN 144 32 RIGHT 8 +PINATTR PinName 12 +PINATTR SpiceOrder 12 +PIN 144 -32 RIGHT 8 +PINATTR PinName 13 +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName 14 +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/Misc/DIP16.asy b/spice/copy/sym/Misc/DIP16.asy new file mode 100755 index 0000000..7fb31e8 --- /dev/null +++ b/spice/copy/sym/Misc/DIP16.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 384 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 96 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 400 Center 2 +SYMATTR Prefix X +SYMATTR Description Generic Symbol for use with subcircuts that you supply. +PIN -144 -96 LEFT 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN -144 224 LEFT 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN -144 288 LEFT 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN -144 352 LEFT 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 144 352 RIGHT 8 +PINATTR PinName 9 +PINATTR SpiceOrder 9 +PIN 144 288 RIGHT 8 +PINATTR PinName 10 +PINATTR SpiceOrder 10 +PIN 144 224 RIGHT 8 +PINATTR PinName 11 +PINATTR SpiceOrder 11 +PIN 144 160 RIGHT 8 +PINATTR PinName 12 +PINATTR SpiceOrder 12 +PIN 144 96 RIGHT 8 +PINATTR PinName 13 +PINATTR SpiceOrder 13 +PIN 144 32 RIGHT 8 +PINATTR PinName 14 +PINATTR SpiceOrder 14 +PIN 144 -32 RIGHT 8 +PINATTR PinName 15 +PINATTR SpiceOrder 15 +PIN 144 -96 RIGHT 8 +PINATTR PinName 16 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/Misc/DIP20.asy b/spice/copy/sym/Misc/DIP20.asy new file mode 100755 index 0000000..c567ad5 --- /dev/null +++ b/spice/copy/sym/Misc/DIP20.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 512 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 96 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 528 Center 2 +SYMATTR Prefix X +SYMATTR Description Generic Symbol for use with subcircuts that you supply. +PIN -144 -96 LEFT 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN -144 224 LEFT 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN -144 288 LEFT 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN -144 352 LEFT 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN -144 416 LEFT 8 +PINATTR PinName 9 +PINATTR SpiceOrder 9 +PIN -144 480 LEFT 8 +PINATTR PinName 10 +PINATTR SpiceOrder 10 +PIN 144 480 RIGHT 8 +PINATTR PinName 11 +PINATTR SpiceOrder 11 +PIN 144 416 RIGHT 8 +PINATTR PinName 12 +PINATTR SpiceOrder 12 +PIN 144 352 RIGHT 8 +PINATTR PinName 13 +PINATTR SpiceOrder 13 +PIN 144 288 RIGHT 8 +PINATTR PinName 14 +PINATTR SpiceOrder 14 +PIN 144 224 RIGHT 8 +PINATTR PinName 15 +PINATTR SpiceOrder 15 +PIN 144 160 RIGHT 8 +PINATTR PinName 16 +PINATTR SpiceOrder 16 +PIN 144 96 RIGHT 8 +PINATTR PinName 17 +PINATTR SpiceOrder 17 +PIN 144 32 RIGHT 8 +PINATTR PinName 18 +PINATTR SpiceOrder 18 +PIN 144 -32 RIGHT 8 +PINATTR PinName 19 +PINATTR SpiceOrder 19 +PIN 144 -96 RIGHT 8 +PINATTR PinName 20 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/Misc/DIP8.asy b/spice/copy/sym/Misc/DIP8.asy new file mode 100755 index 0000000..f13bc7a --- /dev/null +++ b/spice/copy/sym/Misc/DIP8.asy @@ -0,0 +1,37 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -112 -128 112 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Prefix X +SYMATTR Description Generic Symbol for use with subcircuts that you supply. +PIN -112 -96 LEFT 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -112 -32 LEFT 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -112 96 LEFT 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 112 96 RIGHT 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 112 32 RIGHT 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 112 -32 RIGHT 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 112 -96 RIGHT 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Misc/Epoly.asy b/spice/copy/sym/Misc/Epoly.asy new file mode 100755 index 0000000..c74f926 --- /dev/null +++ b/spice/copy/sym/Misc/Epoly.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +LINE Normal 0 16 0 24 +LINE Normal 0 96 0 88 +LINE Normal -4 72 4 72 +LINE Normal -4 40 4 40 +LINE Normal 0 36 0 44 +CIRCLE Normal -32 24 32 88 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 104 Left 2 +SYMATTR Value POLY() +SYMATTR Prefix E +SYMATTR Description Voltage dependent voltage source with two terminals. Useful for drafting schematic generating archaic voltage controlled syntax. +PIN 0 16 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/EuropeanCap.asy b/spice/copy/sym/Misc/EuropeanCap.asy new file mode 100755 index 0000000..4410efe --- /dev/null +++ b/spice/copy/sym/Misc/EuropeanCap.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +LINE Normal 16 44 16 64 +LINE Normal 16 0 16 20 +RECTANGLE Normal 0 36 32 44 +RECTANGLE Normal 0 20 32 28 +WINDOW 0 24 4 Left 2 +WINDOW 3 24 64 Left 2 +SYMATTR Value C +SYMATTR Prefix C +SYMATTR Description Polarized Capacitor +PIN 16 0 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/EuropeanPolcap.asy b/spice/copy/sym/Misc/EuropeanPolcap.asy new file mode 100755 index 0000000..7998e70 --- /dev/null +++ b/spice/copy/sym/Misc/EuropeanPolcap.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType CELL +LINE Normal 16 44 16 64 +LINE Normal 16 0 16 20 +LINE Normal 0 28 32 28 +LINE Normal 0 20 32 20 +LINE Normal 32 28 32 20 +LINE Normal 0 28 0 20 +LINE Normal 32 37 0 37 +LINE Normal 32 38 0 38 +LINE Normal 32 39 0 39 +LINE Normal 32 40 0 40 +LINE Normal 32 41 0 41 +LINE Normal 32 42 0 42 +LINE Normal 32 43 0 43 +RECTANGLE Normal 0 36 32 44 +WINDOW 0 24 4 Left 2 +WINDOW 3 24 64 Left 2 +SYMATTR Value C +SYMATTR Prefix C +SYMATTR Description Polarized Capacitor +PIN 16 0 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/EuropeanResistor.asy b/spice/copy/sym/Misc/EuropeanResistor.asy new file mode 100755 index 0000000..ebb676f --- /dev/null +++ b/spice/copy/sym/Misc/EuropeanResistor.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +LINE Normal 16 88 16 96 +LINE Normal 16 16 16 24 +LINE Normal 27 24 5 24 +LINE Normal 5 88 5 24 +LINE Normal 5 88 27 88 +LINE Normal 27 24 27 88 +WINDOW 0 31 40 Left 2 +WINDOW 3 31 76 Left 2 +SYMATTR Value R +SYMATTR Prefix R +SYMATTR Description A Resistor(European style graphic) +PIN 16 16 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 96 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/Gpoly.asy b/spice/copy/sym/Misc/Gpoly.asy new file mode 100755 index 0000000..39fa1d4 --- /dev/null +++ b/spice/copy/sym/Misc/Gpoly.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 0 16 0 24 +LINE Normal 0 96 0 88 +LINE Normal 4 52 0 40 +LINE Normal -4 52 0 40 +LINE Normal -4 52 4 52 +LINE Normal 0 52 0 72 +CIRCLE Normal -32 24 32 88 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 104 Left 2 +SYMATTR Value POLY() +SYMATTR Prefix G +SYMATTR Description Voltage dependent current source with two terminals. Useful for drafting schematic generating archaic voltage controlled syntax. +PIN 0 96 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 16 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/LT5400-1.asy b/spice/copy/sym/Misc/LT5400-1.asy new file mode 100755 index 0000000..f1a11fa --- /dev/null +++ b/spice/copy/sym/Misc/LT5400-1.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -96 -96 -96 +LINE Normal 16 -96 12 -88 +LINE Normal -12 -104 -4 -88 +LINE Normal 4 -104 -4 -88 +LINE Normal 4 -104 12 -88 +LINE Normal 96 -96 16 -96 +LINE Normal -12 -104 -16 -96 +LINE Normal 96 -32 16 -32 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 32 -96 32 +LINE Normal 96 32 16 32 +LINE Normal 96 96 16 96 +LINE Normal -16 96 -96 96 +LINE Normal 16 -32 12 -24 +LINE Normal -12 -40 -4 -24 +LINE Normal 4 -40 -4 -24 +LINE Normal 4 -40 12 -24 +LINE Normal -12 -40 -16 -32 +LINE Normal 16 32 12 40 +LINE Normal -12 24 -4 40 +LINE Normal 4 24 -4 40 +LINE Normal 4 24 12 40 +LINE Normal -12 24 -16 32 +LINE Normal 16 96 12 104 +LINE Normal -12 88 -4 104 +LINE Normal 4 88 -4 104 +LINE Normal 4 88 12 104 +LINE Normal -12 88 -16 96 +RECTANGLE Normal -96 -144 96 144 +TEXT 64 -64 Center 2 LT +TEXT 2 -102 Bottom 2 10K +TEXT 1 -39 Bottom 2 10K +TEXT 1 26 Bottom 2 10K +TEXT 1 89 Bottom 2 10K +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 16 160 Left 2 +SYMATTR Value LT5400-1 +SYMATTR Prefix X +SYMATTR Description Quad Matched Resistor Network +SYMATTR SpiceModel LT5400.lib +SYMATTR Value2 LT5400-1 +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 -32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -96 32 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -96 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 96 32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 96 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName PAD +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Misc/LT5400-2.asy b/spice/copy/sym/Misc/LT5400-2.asy new file mode 100755 index 0000000..4fa0507 --- /dev/null +++ b/spice/copy/sym/Misc/LT5400-2.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -96 -96 -96 +LINE Normal 16 -96 12 -88 +LINE Normal -12 -104 -4 -88 +LINE Normal 4 -104 -4 -88 +LINE Normal 4 -104 12 -88 +LINE Normal 96 -96 16 -96 +LINE Normal -12 -104 -16 -96 +LINE Normal 96 -32 16 -32 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 32 -96 32 +LINE Normal 96 32 16 32 +LINE Normal 96 96 16 96 +LINE Normal -16 96 -96 96 +LINE Normal 16 -32 12 -24 +LINE Normal -12 -40 -4 -24 +LINE Normal 4 -40 -4 -24 +LINE Normal 4 -40 12 -24 +LINE Normal -12 -40 -16 -32 +LINE Normal 16 32 12 40 +LINE Normal -12 24 -4 40 +LINE Normal 4 24 -4 40 +LINE Normal 4 24 12 40 +LINE Normal -12 24 -16 32 +LINE Normal 16 96 12 104 +LINE Normal -12 88 -4 104 +LINE Normal 4 88 -4 104 +LINE Normal 4 88 12 104 +LINE Normal -12 88 -16 96 +RECTANGLE Normal -96 -144 96 144 +TEXT 64 -64 Center 2 LT +TEXT 2 -102 Bottom 2 100K +TEXT 1 -39 Bottom 2 100K +TEXT 1 26 Bottom 2 100K +TEXT 1 89 Bottom 2 100K +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 16 160 Left 2 +SYMATTR Value LT5400-2 +SYMATTR Prefix X +SYMATTR Description Quad Matched Resistor Network +SYMATTR SpiceModel LT5400.lib +SYMATTR Value2 LT5400-2 +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 -32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -96 32 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -96 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 96 32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 96 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName PAD +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Misc/LT5400-3.asy b/spice/copy/sym/Misc/LT5400-3.asy new file mode 100755 index 0000000..2855c18 --- /dev/null +++ b/spice/copy/sym/Misc/LT5400-3.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -96 -96 -96 +LINE Normal 16 -96 12 -88 +LINE Normal -12 -104 -4 -88 +LINE Normal 4 -104 -4 -88 +LINE Normal 4 -104 12 -88 +LINE Normal 96 -96 16 -96 +LINE Normal -12 -104 -16 -96 +LINE Normal 96 -32 16 -32 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 32 -96 32 +LINE Normal 96 32 16 32 +LINE Normal 96 96 16 96 +LINE Normal -16 96 -96 96 +LINE Normal 16 -32 12 -24 +LINE Normal -12 -40 -4 -24 +LINE Normal 4 -40 -4 -24 +LINE Normal 4 -40 12 -24 +LINE Normal -12 -40 -16 -32 +LINE Normal 16 32 12 40 +LINE Normal -12 24 -4 40 +LINE Normal 4 24 -4 40 +LINE Normal 4 24 12 40 +LINE Normal -12 24 -16 32 +LINE Normal 16 96 12 104 +LINE Normal -12 88 -4 104 +LINE Normal 4 88 -4 104 +LINE Normal 4 88 12 104 +LINE Normal -12 88 -16 96 +RECTANGLE Normal -96 -144 96 144 +TEXT 64 -64 Center 2 LT +TEXT 2 -102 Bottom 2 100K +TEXT 1 -39 Bottom 2 10K +TEXT 1 26 Bottom 2 10K +TEXT 1 89 Bottom 2 100K +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 16 160 Left 2 +SYMATTR Value LT5400-3 +SYMATTR Prefix X +SYMATTR Description Quad Matched Resistor Network +SYMATTR SpiceModel LT5400.lib +SYMATTR Value2 LT5400-3 +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 -32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -96 32 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -96 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 96 32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 96 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName PAD +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Misc/LT5400-4.asy b/spice/copy/sym/Misc/LT5400-4.asy new file mode 100755 index 0000000..35293f0 --- /dev/null +++ b/spice/copy/sym/Misc/LT5400-4.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -96 -96 -96 +LINE Normal 16 -96 12 -88 +LINE Normal -12 -104 -4 -88 +LINE Normal 4 -104 -4 -88 +LINE Normal 4 -104 12 -88 +LINE Normal 96 -96 16 -96 +LINE Normal -12 -104 -16 -96 +LINE Normal 96 -32 16 -32 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 32 -96 32 +LINE Normal 96 32 16 32 +LINE Normal 96 96 16 96 +LINE Normal -16 96 -96 96 +LINE Normal 16 -32 12 -24 +LINE Normal -12 -40 -4 -24 +LINE Normal 4 -40 -4 -24 +LINE Normal 4 -40 12 -24 +LINE Normal -12 -40 -16 -32 +LINE Normal 16 32 12 40 +LINE Normal -12 24 -4 40 +LINE Normal 4 24 -4 40 +LINE Normal 4 24 12 40 +LINE Normal -12 24 -16 32 +LINE Normal 16 96 12 104 +LINE Normal -12 88 -4 104 +LINE Normal 4 88 -4 104 +LINE Normal 4 88 12 104 +LINE Normal -12 88 -16 96 +RECTANGLE Normal -96 -144 96 144 +TEXT 64 -64 Center 2 LT +TEXT 2 -102 Bottom 2 1K +TEXT 1 -39 Bottom 2 1K +TEXT 1 26 Bottom 2 1K +TEXT 1 89 Bottom 2 1K +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 16 160 Left 2 +SYMATTR Value LT5400-4 +SYMATTR Prefix X +SYMATTR Description Quad Matched Resistor Network +SYMATTR SpiceModel LT5400.lib +SYMATTR Value2 LT5400-4 +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 -32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -96 32 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -96 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 96 32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 96 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName PAD +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Misc/LT5400-5.asy b/spice/copy/sym/Misc/LT5400-5.asy new file mode 100755 index 0000000..6ac7044 --- /dev/null +++ b/spice/copy/sym/Misc/LT5400-5.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -96 -96 -96 +LINE Normal 16 -96 12 -88 +LINE Normal -12 -104 -4 -88 +LINE Normal 4 -104 -4 -88 +LINE Normal 4 -104 12 -88 +LINE Normal 96 -96 16 -96 +LINE Normal -12 -104 -16 -96 +LINE Normal 96 -32 16 -32 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 32 -96 32 +LINE Normal 96 32 16 32 +LINE Normal 96 96 16 96 +LINE Normal -16 96 -96 96 +LINE Normal 16 -32 12 -24 +LINE Normal -12 -40 -4 -24 +LINE Normal 4 -40 -4 -24 +LINE Normal 4 -40 12 -24 +LINE Normal -12 -40 -16 -32 +LINE Normal 16 32 12 40 +LINE Normal -12 24 -4 40 +LINE Normal 4 24 -4 40 +LINE Normal 4 24 12 40 +LINE Normal -12 24 -16 32 +LINE Normal 16 96 12 104 +LINE Normal -12 88 -4 104 +LINE Normal 4 88 -4 104 +LINE Normal 4 88 12 104 +LINE Normal -12 88 -16 96 +RECTANGLE Normal -96 -144 96 144 +TEXT 64 -64 Center 2 LT +TEXT 2 -102 Bottom 2 1Meg +TEXT 1 -39 Bottom 2 1Meg +TEXT 1 26 Bottom 2 1Meg +TEXT 1 89 Bottom 2 1Meg +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 16 160 Left 2 +SYMATTR Value LT5400-5 +SYMATTR Prefix X +SYMATTR Description Quad Matched Resistor Network +SYMATTR SpiceModel LT5400.lib +SYMATTR Value2 LT5400-5 +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 -32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -96 32 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -96 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 96 32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 96 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName PAD +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Misc/LT5400-6.asy b/spice/copy/sym/Misc/LT5400-6.asy new file mode 100755 index 0000000..43e0bcd --- /dev/null +++ b/spice/copy/sym/Misc/LT5400-6.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -96 -96 -96 +LINE Normal 16 -96 12 -88 +LINE Normal -12 -104 -4 -88 +LINE Normal 4 -104 -4 -88 +LINE Normal 4 -104 12 -88 +LINE Normal 96 -96 16 -96 +LINE Normal -12 -104 -16 -96 +LINE Normal 96 -32 16 -32 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 32 -96 32 +LINE Normal 96 32 16 32 +LINE Normal 96 96 16 96 +LINE Normal -16 96 -96 96 +LINE Normal 16 -32 12 -24 +LINE Normal -12 -40 -4 -24 +LINE Normal 4 -40 -4 -24 +LINE Normal 4 -40 12 -24 +LINE Normal -12 -40 -16 -32 +LINE Normal 16 32 12 40 +LINE Normal -12 24 -4 40 +LINE Normal 4 24 -4 40 +LINE Normal 4 24 12 40 +LINE Normal -12 24 -16 32 +LINE Normal 16 96 12 104 +LINE Normal -12 88 -4 104 +LINE Normal 4 88 -4 104 +LINE Normal 4 88 12 104 +LINE Normal -12 88 -16 96 +RECTANGLE Normal -96 -144 96 144 +TEXT 64 -64 Center 2 LT +TEXT 2 -102 Bottom 2 5K +TEXT 1 -39 Bottom 2 1K +TEXT 1 26 Bottom 2 1K +TEXT 1 89 Bottom 2 5K +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 16 160 Left 2 +SYMATTR Value LT5400-6 +SYMATTR Prefix X +SYMATTR Description Quad Matched Resistor Network +SYMATTR SpiceModel LT5400.lib +SYMATTR Value2 LT5400-6 +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 -32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -96 32 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -96 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 96 32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 96 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName PAD +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Misc/LT5400-7.asy b/spice/copy/sym/Misc/LT5400-7.asy new file mode 100755 index 0000000..492e820 --- /dev/null +++ b/spice/copy/sym/Misc/LT5400-7.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -96 -96 -96 +LINE Normal 16 -96 12 -88 +LINE Normal -12 -104 -4 -88 +LINE Normal 4 -104 -4 -88 +LINE Normal 4 -104 12 -88 +LINE Normal 96 -96 16 -96 +LINE Normal -12 -104 -16 -96 +LINE Normal 96 -32 16 -32 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 32 -96 32 +LINE Normal 96 32 16 32 +LINE Normal 96 96 16 96 +LINE Normal -16 96 -96 96 +LINE Normal 16 -32 12 -24 +LINE Normal -12 -40 -4 -24 +LINE Normal 4 -40 -4 -24 +LINE Normal 4 -40 12 -24 +LINE Normal -12 -40 -16 -32 +LINE Normal 16 32 12 40 +LINE Normal -12 24 -4 40 +LINE Normal 4 24 -4 40 +LINE Normal 4 24 12 40 +LINE Normal -12 24 -16 32 +LINE Normal 16 96 12 104 +LINE Normal -12 88 -4 104 +LINE Normal 4 88 -4 104 +LINE Normal 4 88 12 104 +LINE Normal -12 88 -16 96 +RECTANGLE Normal -96 -144 96 144 +TEXT 64 -64 Center 2 LT +TEXT 2 -102 Bottom 2 5K +TEXT 1 -39 Bottom 2 1.25K +TEXT 1 26 Bottom 2 1.25K +TEXT 1 89 Bottom 2 5K +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 16 160 Left 2 +SYMATTR Value LT5400-7 +SYMATTR Prefix X +SYMATTR Description Quad Matched Resistor Network +SYMATTR SpiceModel LT5400.lib +SYMATTR Value2 LT5400-7 +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 -32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -96 32 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -96 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 96 32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 96 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName PAD +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Misc/LT5400-8.asy b/spice/copy/sym/Misc/LT5400-8.asy new file mode 100755 index 0000000..454e9d2 --- /dev/null +++ b/spice/copy/sym/Misc/LT5400-8.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -96 -96 -96 +LINE Normal 16 -96 12 -88 +LINE Normal -12 -104 -4 -88 +LINE Normal 4 -104 -4 -88 +LINE Normal 4 -104 12 -88 +LINE Normal 96 -96 16 -96 +LINE Normal -12 -104 -16 -96 +LINE Normal 96 -32 16 -32 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 32 -96 32 +LINE Normal 96 32 16 32 +LINE Normal 96 96 16 96 +LINE Normal -16 96 -96 96 +LINE Normal 16 -32 12 -24 +LINE Normal -12 -40 -4 -24 +LINE Normal 4 -40 -4 -24 +LINE Normal 4 -40 12 -24 +LINE Normal -12 -40 -16 -32 +LINE Normal 16 32 12 40 +LINE Normal -12 24 -4 40 +LINE Normal 4 24 -4 40 +LINE Normal 4 24 12 40 +LINE Normal -12 24 -16 32 +LINE Normal 16 96 12 104 +LINE Normal -12 88 -4 104 +LINE Normal 4 88 -4 104 +LINE Normal 4 88 12 104 +LINE Normal -12 88 -16 96 +RECTANGLE Normal -96 -144 96 144 +TEXT 64 -64 Center 2 LT +TEXT 2 -102 Bottom 2 9K +TEXT 1 -39 Bottom 2 1K +TEXT 1 26 Bottom 2 1K +TEXT 1 89 Bottom 2 9K +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 16 160 Left 2 +SYMATTR Value LT5400-8 +SYMATTR Prefix X +SYMATTR Description Quad Matched Resistor Network +SYMATTR SpiceModel LT5400.lib +SYMATTR Value2 LT5400-8 +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 -32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -96 32 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -96 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN 96 32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN 96 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName PAD +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/Misc/LT5401.asy b/spice/copy/sym/Misc/LT5401.asy new file mode 100755 index 0000000..32581d2 --- /dev/null +++ b/spice/copy/sym/Misc/LT5401.asy @@ -0,0 +1,128 @@ +Version 4 +SymbolType CELL +LINE Normal 16 -80 16 -112 +LINE Normal 16 -48 8 -52 +LINE Normal 24 -76 8 -68 +LINE Normal 24 -60 8 -68 +LINE Normal 24 -60 8 -52 +LINE Normal 16 -32 16 -48 +LINE Normal 24 -76 16 -80 +LINE Normal 80 -32 -16 -32 +LINE Normal -48 -32 -80 -32 +LINE Normal -48 32 -80 32 +LINE Normal 80 32 -16 32 +LINE Normal 80 224 16 224 +LINE Normal -16 -32 -20 -24 +LINE Normal -44 -40 -36 -24 +LINE Normal -28 -40 -36 -24 +LINE Normal -28 -40 -20 -24 +LINE Normal -44 -40 -48 -32 +LINE Normal -16 32 -20 40 +LINE Normal -44 24 -36 40 +LINE Normal -28 24 -36 40 +LINE Normal -28 24 -20 40 +LINE Normal -44 24 -48 32 +LINE Normal 16 -144 16 -176 +LINE Normal 16 -112 8 -116 +LINE Normal 24 -140 8 -132 +LINE Normal 24 -124 8 -132 +LINE Normal 24 -124 8 -116 +LINE Normal 16 -96 80 -96 +LINE Normal 24 -140 16 -144 +LINE Normal 16 -208 16 -224 +LINE Normal 16 -176 8 -180 +LINE Normal 24 -204 8 -196 +LINE Normal 24 -188 8 -196 +LINE Normal 24 -188 8 -180 +LINE Normal 16 -160 80 -160 +LINE Normal 24 -204 16 -208 +LINE Normal 80 -224 16 -224 +LINE Normal 16 176 16 144 +LINE Normal 16 208 8 204 +LINE Normal 24 180 8 188 +LINE Normal 24 196 8 188 +LINE Normal 24 196 8 204 +LINE Normal 16 224 16 208 +LINE Normal 24 180 16 176 +LINE Normal 16 112 16 80 +LINE Normal 16 144 8 140 +LINE Normal 24 116 8 124 +LINE Normal 24 132 8 124 +LINE Normal 24 132 8 140 +LINE Normal 16 160 80 160 +LINE Normal 24 116 16 112 +LINE Normal 16 48 16 32 +LINE Normal 16 80 8 76 +LINE Normal 24 52 8 60 +LINE Normal 24 68 8 60 +LINE Normal 24 68 8 76 +LINE Normal 80 96 16 96 +LINE Normal 24 52 16 48 +RECTANGLE Normal -80 -256 80 272 +CIRCLE Normal 17 -31 15 -33 +CIRCLE Normal 18 -30 14 -34 +CIRCLE Normal 19 -29 13 -35 +CIRCLE Normal 17 -95 15 -97 +CIRCLE Normal 18 -94 14 -98 +CIRCLE Normal 19 -93 13 -99 +CIRCLE Normal 17 -159 15 -161 +CIRCLE Normal 18 -158 14 -162 +CIRCLE Normal 19 -157 13 -163 +CIRCLE Normal 17 33 15 31 +CIRCLE Normal 18 34 14 30 +CIRCLE Normal 19 35 13 29 +CIRCLE Normal 17 97 15 95 +CIRCLE Normal 18 98 14 94 +CIRCLE Normal 19 99 13 93 +CIRCLE Normal 17 161 15 159 +CIRCLE Normal 18 162 14 158 +CIRCLE Normal 19 163 13 157 +TEXT -32 -160 Center 2 LT +TEXT 22 -62 VTop 2 350 +TEXT -31 -39 Bottom 2 700 +TEXT -31 26 Bottom 2 700 +TEXT 22 -126 VTop 2 350 +TEXT 22 -190 VTop 2 700 +TEXT 22 194 VTop 2 700 +TEXT 22 130 VTop 2 350 +TEXT 22 66 VTop 2 350 +WINDOW 0 0 -256 Bottom 2 +WINDOW 3 17 288 Left 2 +SYMATTR Value LT5401 +SYMATTR Prefix X +SYMATTR Description Matched Resistor Network for Precision Amplifiers +SYMATTR SpiceModel LT5400.lib +SYMATTR Value2 LT5401 +PIN -80 -32 NONE 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN 80 -224 NONE 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 2 +PIN 80 -160 NONE 8 +PINATTR PinName T1C +PINATTR SpiceOrder 3 +PIN 80 -96 NONE 8 +PINATTR PinName T1B +PINATTR SpiceOrder 4 +PIN 80 -32 NONE 8 +PINATTR PinName T1A +PINATTR SpiceOrder 5 +PIN 80 32 NONE 8 +PINATTR PinName T2A +PINATTR SpiceOrder 6 +PIN 80 96 NONE 8 +PINATTR PinName T2B +PINATTR SpiceOrder 7 +PIN 80 160 NONE 8 +PINATTR PinName T2C +PINATTR SpiceOrder 8 +PIN 80 224 NONE 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 9 +PIN -80 32 NONE 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 10 +PIN 0 272 BOTTOM 8 +PINATTR PinName PAD +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/Misc/NE555.asy b/spice/copy/sym/Misc/NE555.asy new file mode 100755 index 0000000..9478166 --- /dev/null +++ b/spice/copy/sym/Misc/NE555.asy @@ -0,0 +1,39 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -112 -128 112 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value NE555 +SYMATTR Prefix X +SYMATTR SpiceModel NE555.sub +SYMATTR Value2 NE555 +SYMATTR Description An idealized 555 timer model. +PIN -112 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 -32 LEFT 8 +PINATTR PinName TRIG +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -112 96 LEFT 8 +PINATTR PinName RST +PINATTR SpiceOrder 4 +PIN 112 96 RIGHT 8 +PINATTR PinName CV +PINATTR SpiceOrder 5 +PIN 112 32 RIGHT 8 +PINATTR PinName THRS +PINATTR SpiceOrder 6 +PIN 112 -32 RIGHT 8 +PINATTR PinName DIS +PINATTR SpiceOrder 7 +PIN 112 -96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Misc/NIGBT.asy b/spice/copy/sym/Misc/NIGBT.asy new file mode 100755 index 0000000..387e374 --- /dev/null +++ b/spice/copy/sym/Misc/NIGBT.asy @@ -0,0 +1,30 @@ +Version 4 +SymbolType CELL +LINE Normal 16 80 32 88 +LINE Normal 48 96 28 92 +LINE Normal 48 96 32 84 +LINE Normal 28 92 32 84 +LINE Normal 16 48 40 56 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 0 32 8 +LINE Normal 16 16 36 12 +LINE Normal 16 16 32 4 +LINE Normal 36 12 32 4 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 72 Left 2 +SYMATTR Value NIGBT +SYMATTR Prefix Z +SYMATTR Description N-Channel IGBT symbol for a model you supply. +PIN 48 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Misc/PIGBT.asy b/spice/copy/sym/Misc/PIGBT.asy new file mode 100755 index 0000000..468cac7 --- /dev/null +++ b/spice/copy/sym/Misc/PIGBT.asy @@ -0,0 +1,30 @@ +Version 4 +SymbolType CELL +LINE Normal 16 80 36 84 +LINE Normal 16 80 32 92 +LINE Normal 36 84 32 92 +LINE Normal 48 96 32 88 +LINE Normal 16 48 40 56 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 16 16 32 8 +LINE Normal 28 4 48 0 +LINE Normal 32 12 48 0 +LINE Normal 32 12 28 4 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 72 Left 2 +SYMATTR Value PIGBT +SYMATTR Prefix Z +SYMATTR Description P-Channel IGBT symbol for a model you supply. +PIN 48 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Misc/SCR.asy b/spice/copy/sym/Misc/SCR.asy new file mode 100755 index 0000000..ece6774 --- /dev/null +++ b/spice/copy/sym/Misc/SCR.asy @@ -0,0 +1,24 @@ +Version 4 +SymbolType CELL +LINE Normal 0 44 32 44 +LINE Normal 0 20 32 20 +LINE Normal 32 20 16 44 +LINE Normal 0 20 16 44 +LINE Normal 16 0 16 20 +LINE Normal 16 44 16 64 +LINE Normal -12 64 -32 64 +LINE Normal -12 64 8 44 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 72 Left 2 +SYMATTR Value SCR +SYMATTR Prefix X +SYMATTR Description Generic SCR symbol for use with a model that you supply. +PIN 16 0 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -32 64 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 16 64 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Misc/TRIAC.asy b/spice/copy/sym/Misc/TRIAC.asy new file mode 100755 index 0000000..964955d --- /dev/null +++ b/spice/copy/sym/Misc/TRIAC.asy @@ -0,0 +1,28 @@ +Version 4 +SymbolType CELL +LINE Normal 0 44 36 44 +LINE Normal 0 20 36 20 +LINE Normal 36 20 20 44 +LINE Normal 4 20 20 44 +LINE Normal 32 0 32 20 +LINE Normal 32 44 32 64 +LINE Normal 28 44 64 44 +LINE Normal 28 44 44 20 +LINE Normal 44 20 60 44 +LINE Normal 36 20 64 20 +LINE Normal 0 64 -16 64 +LINE Normal 0 64 20 44 +WINDOW 0 48 0 Left 2 +WINDOW 3 48 72 Left 2 +SYMATTR Value TRIAC +SYMATTR Prefix X +SYMATTR Description Generic TRIAC symbol for use with a model that you supply. +PIN 32 0 NONE 0 +PINATTR PinName MT2 +PINATTR SpiceOrder 1 +PIN -16 64 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 32 64 NONE 0 +PINATTR PinName MT1 +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Misc/TowTom2.asy b/spice/copy/sym/Misc/TowTom2.asy new file mode 100755 index 0000000..2aeb8fc --- /dev/null +++ b/spice/copy/sym/Misc/TowTom2.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 64 -64 64 192 +LINE Normal -32 -64 64 -64 +LINE Normal -32 192 64 192 +LINE Normal -32 -64 -32 192 +WINDOW 0 -32 -80 Left 2 +WINDOW 3 -32 208 Left 2 +SYMATTR Value TowTom2 +SYMATTR Prefix X +SYMATTR Description 2nd Order Tow-Thomas Filter building block. Needs .lib TowTom2.sub & .params R=10K C=160p GBW1=10Meg GBW2=15Meg Aol=100K +PIN -32 64 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -32 -32 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 2 +PIN -32 160 LEFT 8 +PINATTR PinName INV +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Misc/battery.asy b/spice/copy/sym/Misc/battery.asy new file mode 100755 index 0000000..dbdcad3 --- /dev/null +++ b/spice/copy/sym/Misc/battery.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType CELL +LINE Normal -32 36 32 36 +LINE Normal -32 60 32 60 +LINE Normal 0 96 0 76 +LINE Normal 0 16 0 36 +LINE Normal -20 24 -12 24 +LINE Normal -16 20 -16 28 +RECTANGLE Normal -16 44 16 52 +RECTANGLE Normal -16 68 16 76 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 104 Left 2 +SYMATTR Value V +SYMATTR Prefix V +SYMATTR Description Voltage Source, either DC, AC, PULSE, SINE, PWL, EXP, or SFFM +PIN 0 16 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/cell.asy b/spice/copy/sym/Misc/cell.asy new file mode 100755 index 0000000..f15c012 --- /dev/null +++ b/spice/copy/sym/Misc/cell.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +LINE Normal 0 40 0 64 +LINE Normal -32 24 32 24 +LINE Normal 0 0 0 24 +LINE Normal -20 12 -12 12 +LINE Normal -16 8 -16 16 +RECTANGLE Normal -16 32 16 40 +WINDOW 0 24 8 Left 2 +WINDOW 3 24 56 Left 2 +SYMATTR Value V +SYMATTR Prefix V +SYMATTR Description Voltage Source, either DC, AC, PULSE, SINE, PWL, EXP, or SFFM +PIN 0 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 64 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/fixedind.asy b/spice/copy/sym/Misc/fixedind.asy new file mode 100755 index 0000000..e441912 --- /dev/null +++ b/spice/copy/sym/Misc/fixedind.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +ARC Normal 0 40 32 72 4 68 4 44 +ARC Normal 0 64 32 96 16 96 4 68 +ARC Normal 0 16 32 48 4 44 16 16 +WINDOW 0 36 40 Left 2 +WINDOW 3 36 80 Left 2 +SYMATTR Value L +SYMATTR Prefix L +SYMATTR Description An inductor that cannot be edited. Typically used with the 1533/1534 +SYMATTR Def_Sub noedit +PIN 16 16 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 96 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/jumper.asy b/spice/copy/sym/Misc/jumper.asy new file mode 100755 index 0000000..20dcc2f --- /dev/null +++ b/spice/copy/sym/Misc/jumper.asy @@ -0,0 +1,16 @@ +Version 4 +SymbolType CELL +LINE Normal 24 64 32 64 +LINE Normal -24 64 -32 64 +CIRCLE Normal -16 60 -24 68 +CIRCLE Normal 16 60 24 68 +ARC Normal -20 44 20 84 20 60 -20 60 +WINDOW 0 0 40 Bottom 2 +SYMATTR Prefix J +SYMATTR Description A wire jumper. This component lets you give the same net two different names +PIN -32 64 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 32 64 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/neonbulb.asy b/spice/copy/sym/Misc/neonbulb.asy new file mode 100755 index 0000000..af0f1a0 --- /dev/null +++ b/spice/copy/sym/Misc/neonbulb.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 0 -48 0 -21 +LINE Normal 0 48 0 21 +LINE Normal 20 8 12 8 +LINE Normal 16 12 16 4 +LINE Normal 19 11 13 5 +LINE Normal 13 11 19 5 +CIRCLE Normal 32 32 -32 -32 +CIRCLE Normal 5 -11 -5 -21 +CIRCLE Normal 5 21 -5 11 +CIRCLE Normal 17 9 15 7 +CIRCLE Normal 18 10 14 6 +CIRCLE Normal 19 11 13 5 +CIRCLE Normal 20 12 12 4 +WINDOW 0 16 -48 Left 2 +SYMATTR Prefix X +SYMATTR Description Parameterized Neon Bulb +SYMATTR Value2 Vstrike=100 Vhold=50 +SYMATTR ModelFile neonbulb.sub +SYMATTR SpiceModel neonbulb +SYMATTR SpiceLine Zon=2K Ihold=200u +SYMATTR SpiceLine2 Tau=100u +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN 0 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/pentode.asy b/spice/copy/sym/Misc/pentode.asy new file mode 100755 index 0000000..8432a7a --- /dev/null +++ b/spice/copy/sym/Misc/pentode.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -48 -16 -48 16 +LINE Normal 48 -16 48 16 +LINE Normal 0 -64 0 -32 +LINE Normal -20 -32 20 -32 +LINE Normal -20 -28 20 -28 +LINE Normal -20 -32 -20 -28 +LINE Normal 20 -32 20 -28 +LINE Normal 20 -16 12 -16 +LINE Normal 4 -16 -4 -16 +LINE Normal -12 -16 -20 -16 +LINE Normal -28 -16 -48 -16 +LINE Normal 48 0 28 0 +LINE Normal 20 0 12 0 +LINE Normal 4 0 -4 0 +LINE Normal -12 0 -20 0 +LINE Normal -48 16 -28 16 +LINE Normal -20 16 -12 16 +LINE Normal -4 16 4 16 +LINE Normal 12 16 20 16 +LINE Normal -24 28 24 28 +LINE Normal -32 64 -32 36 +LINE Normal -24 28 -32 36 +LINE Normal 24 28 32 36 +LINE Normal -28 32 28 32 +ARC Normal -48 -64 48 32 48 -16 -48 -16 +ARC Normal -48 -32 48 64 -48 16 48 16 +WINDOW 0 8 -80 Left 2 +WINDOW 3 -24 80 Left 2 +SYMATTR Value Pentrode +SYMATTR Prefix X +SYMATTR Description This symbol is for use with a subcircuit macromodel that you supply. +PIN -32 64 NONE 0 +PINATTR PinName Cathode +PINATTR SpiceOrder 1 +PIN -48 16 NONE 0 +PINATTR PinName G1 +PINATTR SpiceOrder 2 +PIN 48 0 NONE 0 +PINATTR PinName G2 +PINATTR SpiceOrder 3 +PIN -48 -16 NONE 0 +PINATTR PinName G3 +PINATTR SpiceOrder 4 +PIN 0 -64 NONE 0 +PINATTR PinName Anode +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Misc/signal.asy b/spice/copy/sym/Misc/signal.asy new file mode 100755 index 0000000..b0ab86f --- /dev/null +++ b/spice/copy/sym/Misc/signal.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType CELL +LINE Normal -4 32 4 32 +LINE Normal -4 80 4 80 +LINE Normal 0 28 0 36 +LINE Normal 0 96 0 88 +LINE Normal 0 16 0 24 +CIRCLE Normal -32 24 32 88 +ARC Normal 0 44 24 68 0 56 24 56 +ARC Normal -24 44 0 68 0 56 -24 56 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 104 Left 2 +SYMATTR Value SINE(0 1 1K) +SYMATTR Prefix V +SYMATTR Description Voltage Source, either DC, AC, PULSE, SINE, PWL, EXP, or SFFM +PIN 0 16 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/tetrode.asy b/spice/copy/sym/Misc/tetrode.asy new file mode 100755 index 0000000..2b3ee36 --- /dev/null +++ b/spice/copy/sym/Misc/tetrode.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -48 0 -48 16 +LINE Normal 48 0 48 16 +LINE Normal 0 -48 0 -16 +LINE Normal -20 -16 20 -16 +LINE Normal -20 -12 20 -12 +LINE Normal -20 -16 -20 -12 +LINE Normal 20 -16 20 -12 +LINE Normal 48 0 28 0 +LINE Normal 20 0 12 0 +LINE Normal 4 0 -4 0 +LINE Normal -12 0 -20 0 +LINE Normal -28 0 -36 0 +LINE Normal -48 16 -28 16 +LINE Normal -20 16 -12 16 +LINE Normal -4 16 4 16 +LINE Normal 12 16 20 16 +LINE Normal 28 16 36 16 +LINE Normal -24 28 24 28 +LINE Normal -32 64 -32 36 +LINE Normal -24 28 -32 36 +LINE Normal 24 28 32 36 +LINE Normal -28 32 28 32 +ARC Normal -48 -48 48 48 48 0 -48 0 +ARC Normal -48 -32 48 64 -48 16 48 16 +WINDOW 0 8 -64 Left 2 +WINDOW 3 -24 80 Left 2 +SYMATTR Value Tetrode +SYMATTR Prefix X +SYMATTR Description This symbol is for use with a subcircuit macromodel that you supply. +PIN 0 -48 NONE 0 +PINATTR PinName Anode +PINATTR SpiceOrder 1 +PIN 48 0 NONE 0 +PINATTR PinName Screen +PINATTR SpiceOrder 2 +PIN -48 16 NONE 0 +PINATTR PinName Grid +PINATTR SpiceOrder 3 +PIN -32 64 NONE 0 +PINATTR PinName Cathode +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Misc/triode.asy b/spice/copy/sym/Misc/triode.asy new file mode 100755 index 0000000..f4658fc --- /dev/null +++ b/spice/copy/sym/Misc/triode.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal -48 0 -28 0 +LINE Normal -20 0 -12 0 +LINE Normal -4 0 4 0 +LINE Normal 12 0 20 0 +LINE Normal 28 0 36 0 +LINE Normal 0 -48 0 -16 +LINE Normal -20 -16 20 -16 +LINE Normal -20 -12 20 -12 +LINE Normal -20 -16 -20 -12 +LINE Normal 20 -16 20 -12 +LINE Normal -24 12 24 12 +LINE Normal -32 48 -32 20 +LINE Normal -24 12 -32 20 +LINE Normal 24 12 32 20 +LINE Normal -28 16 28 16 +CIRCLE Normal -48 -48 48 48 +WINDOW 0 8 -64 Left 2 +WINDOW 3 -24 64 Left 2 +SYMATTR Value Triode +SYMATTR Prefix X +SYMATTR Description This symbol is for use with a subcircuit macromodel that you supply. +PIN 0 -48 NONE 0 +PINATTR PinName Plate +PINATTR SpiceOrder 1 +PIN -48 0 NONE 0 +PINATTR PinName Grid +PINATTR SpiceOrder 2 +PIN -32 48 NONE 0 +PINATTR PinName Cathode +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Misc/urc.asy b/spice/copy/sym/Misc/urc.asy new file mode 100755 index 0000000..a080743 --- /dev/null +++ b/spice/copy/sym/Misc/urc.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 0 72 16 80 +LINE Normal 32 56 0 72 +LINE Normal 0 40 32 56 +LINE Normal 32 24 0 40 +LINE Normal 16 16 32 24 +LINE Normal -8 16 -8 80 +LINE Normal -8 48 -16 48 +WINDOW 0 36 32 Left 2 +WINDOW 3 36 72 Left 2 +SYMATTR Value URC +SYMATTR Prefix U +SYMATTR Description Uniform RC-line. Intended for interconnection on IC's but rarely used. +PIN 16 16 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 80 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN -16 48 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Misc/urc2.asy b/spice/copy/sym/Misc/urc2.asy new file mode 100755 index 0000000..c8274f2 --- /dev/null +++ b/spice/copy/sym/Misc/urc2.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType CELL +LINE Normal 16 0 32 4 +LINE Normal 0 12 32 4 +LINE Normal 0 12 32 20 +LINE Normal 0 28 32 20 +LINE Normal 0 28 32 36 +LINE Normal 0 44 32 36 +LINE Normal 0 44 32 52 +LINE Normal 0 60 32 52 +LINE Normal 0 60 16 64 +LINE Normal -16 32 -8 32 +LINE Normal -8 4 -8 60 +WINDOW 0 36 16 Left 2 +WINDOW 3 36 56 Left 2 +SYMATTR Value URC +SYMATTR Prefix U +SYMATTR Description Uniform RC-line. Intended for interconnection on IC's but rarely used. +PIN 16 0 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN -16 32 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Misc/xtal.asy b/spice/copy/sym/Misc/xtal.asy new file mode 100755 index 0000000..8ea9e97 --- /dev/null +++ b/spice/copy/sym/Misc/xtal.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType CELL +LINE Normal 16 44 16 64 +LINE Normal 16 20 16 0 +LINE Normal 0 20 32 20 +LINE Normal 0 44 32 44 +LINE Normal 8 36 24 36 +LINE Normal 24 36 24 28 +LINE Normal 24 28 8 28 +LINE Normal 8 28 8 36 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 72 Left 2 +SYMATTR Value C +SYMATTR Prefix C +SYMATTR Description Piezoelectric crystal. Set C, Lser and Cpar to set series and parallel resonances. This is actually the same as a capacitor. +PIN 16 0 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/Misc/xvaristor.asy b/spice/copy/sym/Misc/xvaristor.asy new file mode 100755 index 0000000..2b90915 --- /dev/null +++ b/spice/copy/sym/Misc/xvaristor.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 16 80 16 96 +LINE Normal 8 32 8 80 +LINE Normal 24 32 8 32 +LINE Normal 16 16 16 32 +LINE Normal 0 16 0 24 +LINE Normal 0 24 32 84 +LINE Normal 32 92 32 84 +LINE Normal 24 80 24 32 +LINE Normal 8 80 24 80 +WINDOW 0 36 40 Left 2 +WINDOW 3 36 76 Left 2 +SYMATTR Value varistor +SYMATTR Prefix X +SYMATTR Description Generic varistor symbol for use with a model that you supply. +PIN 16 16 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 96 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/OpAmps/AD549.asy b/spice/copy/sym/OpAmps/AD549.asy new file mode 100755 index 0000000..5e138eb --- /dev/null +++ b/spice/copy/sym/OpAmps/AD549.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD549 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD549 +SYMATTR Description Precision Low-Cost HS BiFET Dual Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD711.asy b/spice/copy/sym/OpAmps/AD711.asy new file mode 100755 index 0000000..ad3ecb7 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD711.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD711 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD712 +SYMATTR Description Precision Low-Cost HS BiFET Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD712.asy b/spice/copy/sym/OpAmps/AD712.asy new file mode 100755 index 0000000..aea4f4a --- /dev/null +++ b/spice/copy/sym/OpAmps/AD712.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD712 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD712 +SYMATTR Description Precision Low-Cost HS BiFET Dual Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD713.asy b/spice/copy/sym/OpAmps/AD713.asy new file mode 100755 index 0000000..a5a9560 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD713.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD713 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD712 +SYMATTR Description Precision Low-Cost HS BiFET Quad Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD744.asy b/spice/copy/sym/OpAmps/AD744.asy new file mode 100755 index 0000000..1e69fe6 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD744.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD744 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD746 +SYMATTR Description Precision, 500ns Settling BiFET Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD746.asy b/spice/copy/sym/OpAmps/AD746.asy new file mode 100755 index 0000000..4285013 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD746.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD746 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD746 +SYMATTR Description Dual Precision, 500ns Settling BiFET Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD795.asy b/spice/copy/sym/OpAmps/AD795.asy new file mode 100755 index 0000000..b6a803e --- /dev/null +++ b/spice/copy/sym/OpAmps/AD795.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD795 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD795 +SYMATTR Description Low Power Low Noise Precision FET Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8029.asy b/spice/copy/sym/OpAmps/AD8029.asy new file mode 100755 index 0000000..8c4b747 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8029.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 26 -4 26 +LINE Normal 16 32 16 8 +LINE Normal 7 14 13 14 +LINE Normal 7 16 12 16 +LINE Normal 7 16 7 26 +LINE Normal 13 25 12 26 +LINE Normal 12 26 7 26 +LINE Normal 13 17 12 16 +LINE Normal 13 25 13 17 +WINDOW 0 5 -28 Left 2 +WINDOW 3 21 19 Left 2 +SYMATTR Value AD8029 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8029 +SYMATTR Description High-Speed Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/AD8030.asy b/spice/copy/sym/OpAmps/AD8030.asy new file mode 100755 index 0000000..b081818 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8030.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8030 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8040 +SYMATTR Description Dual High-Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8031.asy b/spice/copy/sym/OpAmps/AD8031.asy new file mode 100755 index 0000000..62e4315 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8031.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8031 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8031 +SYMATTR Description 2.7V 80 MHz rail-rail op amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8032.asy b/spice/copy/sym/OpAmps/AD8032.asy new file mode 100755 index 0000000..a3e3f04 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8032.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8032 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8031 +SYMATTR Description Dual 2.7V 80 MHz rail-rail op amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8033.asy b/spice/copy/sym/OpAmps/AD8033.asy new file mode 100755 index 0000000..83df324 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8033.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8033 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8033 +SYMATTR Description 85MHz FET Input Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8034.asy b/spice/copy/sym/OpAmps/AD8034.asy new file mode 100755 index 0000000..2d8c608 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8034.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8034 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8033 +SYMATTR Description Dual 85MHz FET Input Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8038.asy b/spice/copy/sym/OpAmps/AD8038.asy new file mode 100755 index 0000000..fdb183a --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8038.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8038 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8038 +SYMATTR Description Low-Power 350MHz op amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8039.asy b/spice/copy/sym/OpAmps/AD8039.asy new file mode 100755 index 0000000..1d1b5ac --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8039.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8039 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8038 +SYMATTR Description Dual Low-Power 350MHz op amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8040.asy b/spice/copy/sym/OpAmps/AD8040.asy new file mode 100755 index 0000000..4ca742a --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8040.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8040 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8040 +SYMATTR Description Quad High-Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8041.asy b/spice/copy/sym/OpAmps/AD8041.asy new file mode 100755 index 0000000..11ce9e9 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8041.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 26 -4 26 +LINE Normal 16 32 16 8 +LINE Normal 7 14 13 14 +LINE Normal 7 16 12 16 +LINE Normal 7 16 7 26 +LINE Normal 13 25 12 26 +LINE Normal 12 26 7 26 +LINE Normal 13 17 12 16 +LINE Normal 13 25 13 17 +WINDOW 0 5 -28 Left 2 +WINDOW 3 21 19 Left 2 +SYMATTR Value AD8041 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8041 +SYMATTR Description 160MHz Rail-to-Rail Amplifier with Disable +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/AD8047.asy b/spice/copy/sym/OpAmps/AD8047.asy new file mode 100755 index 0000000..2410ee1 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8047.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8047 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8047 +SYMATTR Description 250MHz (G=1) voltage feedback op amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8065.asy b/spice/copy/sym/OpAmps/AD8065.asy new file mode 100755 index 0000000..0b2981a --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8065.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8065 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8065 +SYMATTR Description Single 135MHz low noise FET Input Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8066.asy b/spice/copy/sym/OpAmps/AD8066.asy new file mode 100755 index 0000000..e000fb9 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8066.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8066 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8066 +SYMATTR Description Dual low-cost high-speed FET input amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8067.asy b/spice/copy/sym/OpAmps/AD8067.asy new file mode 100755 index 0000000..00d4831 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8067.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8067 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8067 +SYMATTR Description 250MHz Precision FastFET Op-Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8091.asy b/spice/copy/sym/OpAmps/AD8091.asy new file mode 100755 index 0000000..5627a75 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8091.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8091 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8091 +SYMATTR Description Single 110MHz rail-to-rail op amp 2.7V +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8092.asy b/spice/copy/sym/OpAmps/AD8092.asy new file mode 100755 index 0000000..5b19e2d --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8092.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8092 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8092 +SYMATTR Description Dual 110MHz rail-to-rail op amp 2.7V +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD811.asy b/spice/copy/sym/OpAmps/AD811.asy new file mode 100755 index 0000000..3143263 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD811.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD811 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD811 +SYMATTR Description High Performance Video Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD820.asy b/spice/copy/sym/OpAmps/AD820.asy new file mode 100755 index 0000000..8f569e1 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD820.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD820 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD820 +SYMATTR Description Single/Dual Supply Rail to Rail output Low Power FET Input Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8205.asy b/spice/copy/sym/OpAmps/AD8205.asy new file mode 100755 index 0000000..18e9cd5 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8205.asy @@ -0,0 +1,131 @@ +Version 4 +SymbolType BLOCK +LINE Normal -16 0 -16 -128 +LINE Normal 96 -64 -16 0 +LINE Normal -16 -128 96 -64 +LINE Normal -160 -96 -140 -96 +LINE Normal -9 -32 9 -32 +LINE Normal 0 -105 0 -87 +LINE Normal -9 -96 9 -96 +LINE Normal -136 -104 -140 -96 +LINE Normal -128 -88 -136 -104 +LINE Normal -128 -88 -120 -104 +LINE Normal -112 -88 -120 -104 +LINE Normal -108 -96 -112 -88 +LINE Normal -108 -96 -16 -96 +LINE Normal -136 -40 -140 -32 +LINE Normal -128 -24 -136 -40 +LINE Normal -128 -24 -120 -40 +LINE Normal -112 -24 -120 -40 +LINE Normal -108 -32 -112 -24 +LINE Normal -108 -32 -16 -32 +LINE Normal -160 -32 -140 -32 +LINE Normal 152 36 144 32 +LINE Normal 136 44 152 36 +LINE Normal 136 44 152 52 +LINE Normal 136 60 152 52 +LINE Normal 144 64 136 60 +LINE Normal 112 -64 112 48 +LINE Normal -96 -96 -96 0 +LINE Normal -96 80 -24 80 +LINE Normal -20 72 -24 80 +LINE Normal -12 88 -20 72 +LINE Normal -12 88 -4 72 +LINE Normal 4 88 -4 72 +LINE Normal 8 80 4 88 +LINE Normal 8 80 144 80 +LINE Normal 136 124 144 128 +LINE Normal 152 116 136 124 +LINE Normal 152 116 136 108 +LINE Normal 152 100 136 108 +LINE Normal 144 96 152 100 +LINE Normal 144 16 144 32 +LINE Normal 176 144 144 144 +LINE Normal 144 96 144 64 +LINE Normal 176 -64 96 -64 +LINE Normal -88 4 -96 0 +LINE Normal -104 12 -88 4 +LINE Normal -104 12 -88 20 +LINE Normal -104 28 -88 20 +LINE Normal -96 32 -104 28 +LINE Normal -104 125 -96 129 +LINE Normal -88 117 -104 125 +LINE Normal -88 117 -104 109 +LINE Normal -88 101 -104 109 +LINE Normal -96 97 -88 101 +LINE Normal -48 -32 -48 0 +LINE Normal -96 144 -96 129 +LINE Normal -96 97 -96 32 +LINE Normal -40 4 -48 0 +LINE Normal -56 12 -40 4 +LINE Normal -56 12 -40 20 +LINE Normal -56 28 -40 20 +LINE Normal -48 32 -56 28 +LINE Normal -56 125 -48 129 +LINE Normal -40 117 -56 125 +LINE Normal -40 117 -56 109 +LINE Normal -40 101 -56 109 +LINE Normal -48 97 -40 101 +LINE Normal -48 160 -48 129 +LINE Normal -48 97 -48 32 +LINE Normal 144 128 144 144 +LINE Normal 176 16 144 16 +LINE Normal -48 48 24 48 +LINE Normal 28 40 24 48 +LINE Normal 36 56 28 40 +LINE Normal 36 56 44 40 +LINE Normal 52 56 44 40 +LINE Normal 56 48 52 56 +LINE Normal 56 48 112 48 +LINE Normal -48 144 -96 144 +RECTANGLE Normal 176 160 -160 -176 +CIRCLE Normal -95 -95 -97 -97 +CIRCLE Normal -94 -94 -98 -98 +CIRCLE Normal -93 -93 -99 -99 +CIRCLE Normal -47 -31 -49 -33 +CIRCLE Normal -46 -30 -50 -34 +CIRCLE Normal -45 -29 -51 -35 +CIRCLE Normal 145 81 143 79 +CIRCLE Normal 146 82 142 78 +CIRCLE Normal 147 83 141 77 +CIRCLE Normal -47 143 -49 145 +CIRCLE Normal -46 142 -50 146 +CIRCLE Normal -45 141 -51 147 +CIRCLE Normal 113 -65 111 -63 +CIRCLE Normal 114 -66 110 -62 +CIRCLE Normal 115 -67 109 -61 +CIRCLE Normal -95 79 -97 81 +CIRCLE Normal -94 78 -98 82 +CIRCLE Normal -93 77 -99 83 +CIRCLE Normal -47 47 -49 49 +CIRCLE Normal -46 46 -50 50 +CIRCLE Normal -45 45 -51 51 +TEXT 48 128 Center 2 ADI +WINDOW 0 -16 -192 Left 2 +WINDOW 3 -16 176 Left 2 +SYMATTR Value AD8205 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8205 +SYMATTR Description Single-Supply 42V System Difference Amplifier +PIN -160 -32 NONE 8 +PINATTR PinName -IN +PINATTR SpiceOrder 1 +PIN -48 160 NONE 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 176 144 NONE 8 +PINATTR PinName Vref2 +PINATTR SpiceOrder 3 +PIN 176 -64 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -48 -176 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 6 +PIN 176 16 NONE 8 +PINATTR PinName Vref1 +PINATTR SpiceOrder 7 +PIN -160 -96 NONE 8 +PINATTR PinName +IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD822.asy b/spice/copy/sym/OpAmps/AD822.asy new file mode 100755 index 0000000..3d48412 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD822.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD822 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD820 +SYMATTR Description Dual Single/Dual Supply Rail to Rail output Low Power FET Input Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8220.asy b/spice/copy/sym/OpAmps/AD8220.asy new file mode 100755 index 0000000..3c23e6e --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8220.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -96 144 0 +LINE Normal -32 96 144 0 +LINE Normal -32 -96 -32 96 +LINE Normal -25 80 -17 80 +LINE Normal -25 -80 -17 -80 +LINE Normal -21 -76 -21 -84 +LINE Normal 0 -96 0 -78 +LINE Normal 0 96 0 78 +LINE Normal 4 -84 12 -84 +LINE Normal 8 -88 8 -80 +LINE Normal 4 84 12 84 +LINE Normal 80 64 80 35 +TEXT -24 -48 Left 2 RG +TEXT -24 48 Left 2 RG +TEXT 80 16 Center 2 REF +WINDOW 0 80 -48 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value AD8220 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8220 +SYMATTR Description JFET Input In-Amp with R-R Out in MSOP pkg +PIN -32 80 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -32 -48 NONE 8 +PINATTR PinName RG1 +PINATTR SpiceOrder 2 +PIN -32 48 NONE 8 +PINATTR PinName RG2 +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 80 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -96 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD8221.asy b/spice/copy/sym/OpAmps/AD8221.asy new file mode 100755 index 0000000..f6230af --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8221.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -96 144 0 +LINE Normal -32 96 144 0 +LINE Normal -32 -96 -32 96 +LINE Normal -25 80 -17 80 +LINE Normal -25 -80 -17 -80 +LINE Normal -21 -76 -21 -84 +LINE Normal 0 -96 0 -78 +LINE Normal 0 96 0 78 +LINE Normal 4 -84 12 -84 +LINE Normal 8 -88 8 -80 +LINE Normal 4 84 12 84 +LINE Normal 80 64 80 35 +TEXT -24 -48 Left 2 RG +TEXT -24 48 Left 2 RG +TEXT 80 16 Center 2 REF +WINDOW 0 80 -48 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value AD8221 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8221 +SYMATTR Description Precision In-Amp +PIN -32 80 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -32 -48 NONE 8 +PINATTR PinName RG1 +PINATTR SpiceOrder 2 +PIN -32 48 NONE 8 +PINATTR PinName RG2 +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 80 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -96 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD8222.asy b/spice/copy/sym/OpAmps/AD8222.asy new file mode 100755 index 0000000..1674088 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8222.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -96 144 0 +LINE Normal -32 96 144 0 +LINE Normal -32 -96 -32 96 +LINE Normal -25 80 -17 80 +LINE Normal -25 -80 -17 -80 +LINE Normal -21 -76 -21 -84 +LINE Normal 0 -96 0 -78 +LINE Normal 0 96 0 78 +LINE Normal 4 -84 12 -84 +LINE Normal 8 -88 8 -80 +LINE Normal 4 84 12 84 +LINE Normal 80 64 80 35 +TEXT -24 -48 Left 2 RG +TEXT -24 48 Left 2 RG +TEXT 80 16 Center 2 REF +WINDOW 0 80 -48 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value AD8222 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8222 +SYMATTR Description Precision Dual Channel In-Amp +PIN -32 80 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -32 -48 NONE 8 +PINATTR PinName RG1 +PINATTR SpiceOrder 2 +PIN -32 48 NONE 8 +PINATTR PinName RG2 +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 80 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -96 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD8224.asy b/spice/copy/sym/OpAmps/AD8224.asy new file mode 100755 index 0000000..c1d1b23 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8224.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -96 144 0 +LINE Normal -32 96 144 0 +LINE Normal -32 -96 -32 96 +LINE Normal -25 80 -17 80 +LINE Normal -25 -80 -17 -80 +LINE Normal -21 -76 -21 -84 +LINE Normal 0 -96 0 -78 +LINE Normal 0 96 0 78 +LINE Normal 4 -84 12 -84 +LINE Normal 8 -88 8 -80 +LINE Normal 4 84 12 84 +LINE Normal 80 64 80 35 +TEXT -24 -48 Left 2 RG +TEXT -24 48 Left 2 RG +TEXT 80 16 Center 2 REF +WINDOW 0 80 -48 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value AD8224 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8224 +SYMATTR Description Precision Dual Channel JFET R-R in In-Amp +PIN -32 80 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -32 -48 NONE 8 +PINATTR PinName RG1 +PINATTR SpiceOrder 2 +PIN -32 48 NONE 8 +PINATTR PinName RG2 +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 80 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -96 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD8226.asy b/spice/copy/sym/OpAmps/AD8226.asy new file mode 100755 index 0000000..c2c1e45 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8226.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -96 144 0 +LINE Normal -32 96 144 0 +LINE Normal -32 -96 -32 96 +LINE Normal -25 80 -17 80 +LINE Normal -25 -80 -17 -80 +LINE Normal -21 -76 -21 -84 +LINE Normal 0 -96 0 -78 +LINE Normal 0 96 0 78 +LINE Normal 4 -84 12 -84 +LINE Normal 8 -88 8 -80 +LINE Normal 4 84 12 84 +LINE Normal 80 64 80 35 +TEXT -24 -48 Left 2 RG +TEXT -24 48 Left 2 RG +TEXT 80 16 Center 2 REF +WINDOW 0 80 -48 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value AD8226 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8226 +SYMATTR Description Wide Supply Range R-R output In-Amp +PIN -32 80 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -32 -48 NONE 8 +PINATTR PinName RG1 +PINATTR SpiceOrder 2 +PIN -32 48 NONE 8 +PINATTR PinName RG2 +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 80 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -96 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD8227.asy b/spice/copy/sym/OpAmps/AD8227.asy new file mode 100755 index 0000000..f94e6e5 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8227.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -96 144 0 +LINE Normal -32 96 144 0 +LINE Normal -32 -96 -32 96 +LINE Normal -25 80 -17 80 +LINE Normal -25 -80 -17 -80 +LINE Normal -21 -76 -21 -84 +LINE Normal 0 -96 0 -78 +LINE Normal 0 96 0 78 +LINE Normal 4 -84 12 -84 +LINE Normal 8 -88 8 -80 +LINE Normal 4 84 12 84 +LINE Normal 80 64 80 35 +TEXT -24 -48 Left 2 RG +TEXT -24 48 Left 2 RG +TEXT 80 16 Center 2 REF +WINDOW 0 80 -48 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value AD8227 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8227 +SYMATTR Description Wide Supply Range R-R output In-Amp +PIN -32 80 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -32 -48 NONE 8 +PINATTR PinName RG1 +PINATTR SpiceOrder 2 +PIN -32 48 NONE 8 +PINATTR PinName RG2 +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 80 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -96 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD823.asy b/spice/copy/sym/OpAmps/AD823.asy new file mode 100755 index 0000000..5150cc4 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD823.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD823 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD823 +SYMATTR Description Dual 16 MHz Rail-toRail FET Input Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8235.asy b/spice/copy/sym/OpAmps/AD8235.asy new file mode 100755 index 0000000..7a5590b --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8235.asy @@ -0,0 +1,64 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal 0 -64 0 -32 +LINE Normal -32 64 -32 48 +LINE Normal -48 -48 -56 -48 +LINE Normal -52 -44 -52 -52 +LINE Normal -48 48 -56 48 +LINE Normal -29 -56 -21 -56 +LINE Normal -25 -52 -25 -60 +LINE Normal -28 56 -20 56 +LINE Normal 32 64 32 16 +LINE Normal -56 -24 -56 -8 +LINE Normal -56 -24 -52 -24 +LINE Normal -48 -20 -52 -24 +LINE Normal -48 -20 -52 -16 +LINE Normal -56 -16 -52 -16 +LINE Normal -48 -12 -52 -16 +LINE Normal -48 -12 -48 -8 +LINE Normal -56 8 -56 24 +LINE Normal -56 8 -52 8 +LINE Normal -48 12 -52 8 +LINE Normal -48 12 -52 16 +LINE Normal -56 16 -52 16 +LINE Normal -48 20 -52 16 +LINE Normal -48 20 -48 24 +LINE Normal -32 -64 -32 -48 +LINE Normal -32 -80 -32 -64 +WINDOW 0 20 -44 Left 2 +WINDOW 3 40 48 Left 2 +SYMATTR Value AD8235 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8235 +SYMATTR Description µPower Precision Instrumentation Amplifier +PIN -64 48 NONE 0 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -64 16 NONE 0 +PINATTR PinName RG2 +PINATTR SpiceOrder 2 +PIN -64 -16 NONE 0 +PINATTR PinName RG1 +PINATTR SpiceOrder 3 +PIN -64 -48 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 4 +PIN 0 -64 NONE 0 +PINATTR PinName SDN +PINATTR SpiceOrder 5 +PIN -32 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN 32 64 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 7 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 8 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/OpAmps/AD8236.asy b/spice/copy/sym/OpAmps/AD8236.asy new file mode 100755 index 0000000..5e2ba2d --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8236.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal 0 -64 0 -32 +LINE Normal -32 64 -32 48 +LINE Normal -48 -48 -56 -48 +LINE Normal -52 -44 -52 -52 +LINE Normal -48 48 -56 48 +LINE Normal 8 -40 16 -40 +LINE Normal 12 -36 12 -44 +LINE Normal -28 56 -20 56 +LINE Normal 32 64 32 16 +LINE Normal -56 -24 -56 -8 +LINE Normal -56 -24 -52 -24 +LINE Normal -48 -20 -52 -24 +LINE Normal -48 -20 -52 -16 +LINE Normal -56 -16 -52 -16 +LINE Normal -48 -12 -52 -16 +LINE Normal -48 -12 -48 -8 +LINE Normal -56 8 -56 24 +LINE Normal -56 8 -52 8 +LINE Normal -48 12 -52 8 +LINE Normal -48 12 -52 16 +LINE Normal -56 16 -52 16 +LINE Normal -48 20 -52 16 +LINE Normal -48 20 -48 24 +WINDOW 0 20 -44 Left 2 +WINDOW 3 40 48 Left 2 +SYMATTR Value AD8236 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8236 +SYMATTR Description 40 µA µPower Instrumentation Amplifier w/zero Crossover Distortion +PIN -64 48 NONE 0 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -64 16 NONE 0 +PINATTR PinName RG2 +PINATTR SpiceOrder 2 +PIN -64 -16 NONE 0 +PINATTR PinName RG1 +PINATTR SpiceOrder 3 +PIN -64 -48 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 4 +PIN -32 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 5 +PIN 32 64 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD823A.asy b/spice/copy/sym/OpAmps/AD823A.asy new file mode 100755 index 0000000..5150cc4 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD823A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD823 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD823 +SYMATTR Description Dual 16 MHz Rail-toRail FET Input Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD824.asy b/spice/copy/sym/OpAmps/AD824.asy new file mode 100755 index 0000000..229cebf --- /dev/null +++ b/spice/copy/sym/OpAmps/AD824.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD824 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD820 +SYMATTR Description Quad Single/Dual Supply Rail to Rail output Low Power FET Input Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8310.asy b/spice/copy/sym/OpAmps/AD8310.asy new file mode 100755 index 0000000..4b4797a --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8310.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value AD8310 +SYMATTR Prefix X +SYMATTR Description Fast, Voltage-Out, DC to 440MHz, 95dB Logartihmic Amplifier +SYMATTR SpiceModel AD8310.lib +SYMATTR Value2 AD8310 +PIN -160 48 LEFT 8 +PINATTR PinName INLO +PINATTR SpiceOrder 1 +PIN -160 144 LEFT 8 +PINATTR PinName COMM +PINATTR SpiceOrder 2 +PIN 160 144 RIGHT 8 +PINATTR PinName OFLT +PINATTR SpiceOrder 3 +PIN 160 48 RIGHT 8 +PINATTR PinName VOUT +PINATTR SpiceOrder 4 +PIN -160 -144 LEFT 8 +PINATTR PinName VPOS +PINATTR SpiceOrder 5 +PIN 160 -48 RIGHT 8 +PINATTR PinName BFIN +PINATTR SpiceOrder 6 +PIN 160 -144 RIGHT 8 +PINATTR PinName ENBL +PINATTR SpiceOrder 7 +PIN -160 -48 LEFT 8 +PINATTR PinName INHI +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD8418A.asy b/spice/copy/sym/OpAmps/AD8418A.asy new file mode 100755 index 0000000..993efe4 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8418A.asy @@ -0,0 +1,78 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal -16 -36 -16 -28 +LINE Normal 25 -16 25 -31 +LINE Normal 29 -31 25 -31 +LINE Normal 30 -27 29 -31 +LINE Normal 28 -24 30 -27 +LINE Normal 25 -24 28 -24 +LINE Normal 30 -16 25 -24 +LINE Normal 32 -16 32 -31 +LINE Normal 36 -16 32 -16 +LINE Normal 35 -24 32 -24 +LINE Normal 36 -31 32 -31 +LINE Normal 38 -16 38 -31 +LINE Normal 42 -31 38 -31 +LINE Normal 41 -24 38 -24 +LINE Normal 42 -28 44 -31 +LINE Normal 44 -16 44 -31 +LINE Normal 46 -16 42 -16 +LINE Normal 25 31 25 16 +LINE Normal 29 16 25 16 +LINE Normal 30 20 29 16 +LINE Normal 28 23 30 20 +LINE Normal 30 31 25 23 +LINE Normal 25 23 28 23 +LINE Normal 32 31 32 16 +LINE Normal 36 16 32 16 +LINE Normal 35 23 32 23 +LINE Normal 36 31 32 31 +LINE Normal 39 31 39 16 +LINE Normal 43 16 39 16 +LINE Normal 42 23 39 23 +LINE Normal 45 16 45 17 +LINE Normal 48 16 45 16 +LINE Normal 48 23 48 16 +LINE Normal 45 23 48 23 +LINE Normal 45 31 45 23 +LINE Normal 48 31 45 31 +LINE Normal 32 -45 32 -80 +LINE Normal 32 44 32 80 +LINE Normal 32 -44 32 -45 +WINDOW 0 48 -48 Left 2 +WINDOW 3 48 48 Left 2 +SYMATTR Value AD8418A +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8418A +SYMATTR Description Bidirectional G of 20 Current Sense Amplifier +PIN -32 32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 32 80 NONE 0 +PINATTR PinName REF2 +PINATTR SpiceOrder 3 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 0 -80 NONE 0 +PINATTR PinName VS +PINATTR SpiceOrder 5 +PIN 32 -80 NONE 8 +PINATTR PinName REF1 +PINATTR SpiceOrder 6 +PIN -32 -32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/AD8421.asy b/spice/copy/sym/OpAmps/AD8421.asy new file mode 100755 index 0000000..77121db Binary files /dev/null and b/spice/copy/sym/OpAmps/AD8421.asy differ diff --git a/spice/copy/sym/OpAmps/AD8422.asy b/spice/copy/sym/OpAmps/AD8422.asy new file mode 100755 index 0000000..6193409 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8422.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -96 144 0 +LINE Normal -32 96 144 0 +LINE Normal -32 -96 -32 96 +LINE Normal -25 80 -17 80 +LINE Normal -25 -80 -17 -80 +LINE Normal -21 -76 -21 -84 +LINE Normal 0 -96 0 -78 +LINE Normal 0 96 0 78 +LINE Normal 4 -84 12 -84 +LINE Normal 8 -88 8 -80 +LINE Normal 4 84 12 84 +LINE Normal 80 64 80 35 +TEXT -24 -48 Left 2 RG +TEXT -24 48 Left 2 RG +TEXT 80 16 Center 2 REF +WINDOW 0 80 -48 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value AD8422 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8422 +SYMATTR Description High Performance, Low Power, R-R Precision In-Amp +PIN -32 80 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -32 -48 NONE 8 +PINATTR PinName RG1 +PINATTR SpiceOrder 2 +PIN -32 48 NONE 8 +PINATTR PinName RG2 +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 80 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -96 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/AD8429.asy b/spice/copy/sym/OpAmps/AD8429.asy new file mode 100755 index 0000000..ab60c6e Binary files /dev/null and b/spice/copy/sym/OpAmps/AD8429.asy differ diff --git a/spice/copy/sym/OpAmps/AD8479.asy b/spice/copy/sym/OpAmps/AD8479.asy new file mode 100755 index 0000000..f1e9486 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8479.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -144 -32 -128 -32 +LINE Normal -42 -32 -24 -32 +LINE Normal -32 23 -32 41 +LINE Normal -41 32 -23 32 +LINE Normal -124 -40 -128 -32 +LINE Normal -116 -24 -124 -40 +LINE Normal -116 -24 -108 -40 +LINE Normal -100 -24 -108 -40 +LINE Normal -96 -32 -100 -24 +LINE Normal -96 -32 -48 -32 +LINE Normal -124 24 -128 32 +LINE Normal -116 40 -124 24 +LINE Normal -116 40 -108 24 +LINE Normal -100 40 -108 24 +LINE Normal -96 32 -100 40 +LINE Normal -96 32 -48 32 +LINE Normal -144 32 -128 32 +LINE Normal 80 0 80 -96 +LINE Normal -80 96 -8 96 +LINE Normal -4 88 -8 96 +LINE Normal 4 104 -4 88 +LINE Normal 4 104 12 88 +LINE Normal 20 104 12 88 +LINE Normal 24 96 20 104 +LINE Normal 128 0 64 0 +LINE Normal -4 -104 -8 -96 +LINE Normal 4 -88 -4 -104 +LINE Normal 4 -88 12 -104 +LINE Normal 20 -88 12 -104 +LINE Normal 24 -96 20 -88 +LINE Normal 24 -96 80 -96 +LINE Normal -80 -96 -8 -96 +LINE Normal -144 -96 -128 -96 +LINE Normal -124 -104 -128 -96 +LINE Normal -116 -88 -124 -104 +LINE Normal -116 -88 -108 -104 +LINE Normal -100 -88 -108 -104 +LINE Normal -96 -96 -100 -88 +LINE Normal -80 -96 -96 -96 +LINE Normal -80 96 -80 32 +LINE Normal 128 96 24 96 +LINE Normal -80 -96 -80 -80 +LINE Normal -80 -32 -80 -48 +LINE Normal -72 -76 -80 -80 +LINE Normal -88 -68 -72 -76 +LINE Normal -88 -68 -72 -60 +LINE Normal -88 -52 -72 -60 +LINE Normal -80 -48 -88 -52 +RECTANGLE Normal 128 144 -144 -144 +CIRCLE Normal -79 33 -81 31 +CIRCLE Normal -78 34 -82 30 +CIRCLE Normal -77 35 -83 29 +CIRCLE Normal 81 -1 79 1 +CIRCLE Normal 82 -2 78 2 +CIRCLE Normal 83 -3 77 3 +CIRCLE Normal -79 -31 -81 -33 +CIRCLE Normal -78 -30 -82 -34 +CIRCLE Normal -77 -29 -83 -35 +CIRCLE Normal -79 -95 -81 -97 +CIRCLE Normal -78 -94 -82 -98 +CIRCLE Normal -77 -93 -83 -99 +TEXT 65 57 Center 2 ADI +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 64 144 Top 2 +SYMATTR Value AD8479 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8479 +SYMATTR Description Very High Common-Mode Voltage Precision Difference Amplifier +PIN -144 -96 NONE 8 +PINATTR PinName REF- +PINATTR SpiceOrder 1 +PIN -144 -32 NONE 8 +PINATTR PinName -IN +PINATTR SpiceOrder 2 +PIN -144 32 NONE 8 +PINATTR PinName +IN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName -V +PINATTR SpiceOrder 4 +PIN 128 96 NONE 8 +PINATTR PinName REF+ +PINATTR SpiceOrder 5 +PIN 128 0 NONE 8 +PINATTR PinName OUTPUT +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName +V +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/AD8505.asy b/spice/copy/sym/OpAmps/AD8505.asy new file mode 100755 index 0000000..65dda59 Binary files /dev/null and b/spice/copy/sym/OpAmps/AD8505.asy differ diff --git a/spice/copy/sym/OpAmps/AD8506.asy b/spice/copy/sym/OpAmps/AD8506.asy new file mode 100755 index 0000000..e26e73c Binary files /dev/null and b/spice/copy/sym/OpAmps/AD8506.asy differ diff --git a/spice/copy/sym/OpAmps/AD8508.asy b/spice/copy/sym/OpAmps/AD8508.asy new file mode 100755 index 0000000..4de6ed7 Binary files /dev/null and b/spice/copy/sym/OpAmps/AD8508.asy differ diff --git a/spice/copy/sym/OpAmps/AD8510.asy b/spice/copy/sym/OpAmps/AD8510.asy new file mode 100755 index 0000000..5ace498 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8510.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8510 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8510 +SYMATTR Description Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8512.asy b/spice/copy/sym/OpAmps/AD8512.asy new file mode 100755 index 0000000..4b51f34 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8512.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8512 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8510 +SYMATTR Description Dual Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8513.asy b/spice/copy/sym/OpAmps/AD8513.asy new file mode 100755 index 0000000..1b033be --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8513.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8513 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8510 +SYMATTR Description Quad Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8515.asy b/spice/copy/sym/OpAmps/AD8515.asy new file mode 100755 index 0000000..6c966ed --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8515.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8515 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8515 +SYMATTR Description 1.8/5V CMOS OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8538.asy b/spice/copy/sym/OpAmps/AD8538.asy new file mode 100755 index 0000000..80a8392 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8538.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8538 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8538 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Single +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8539.asy b/spice/copy/sym/OpAmps/AD8539.asy new file mode 100755 index 0000000..817698b --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8539.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8539 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8539 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Dual +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8541.asy b/spice/copy/sym/OpAmps/AD8541.asy new file mode 100755 index 0000000..540f9e6 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8541.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8541 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8541 +SYMATTR Description 2.7/5V CMOS OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8542.asy b/spice/copy/sym/OpAmps/AD8542.asy new file mode 100755 index 0000000..1febb47 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8542.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8542 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8542 +SYMATTR Description 2.7/5V CMOS OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8544.asy b/spice/copy/sym/OpAmps/AD8544.asy new file mode 100755 index 0000000..33c04b9 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8544.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8544 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8544 +SYMATTR Description 2.7/5V CMOS OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8546.asy b/spice/copy/sym/OpAmps/AD8546.asy new file mode 100755 index 0000000..83ecb13 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8546.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8546 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8546 +SYMATTR Description 3/18V CMOS OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8548.asy b/spice/copy/sym/OpAmps/AD8548.asy new file mode 100755 index 0000000..526994f --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8548.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8548 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8548 +SYMATTR Description 3/18V CMOS OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8551.asy b/spice/copy/sym/OpAmps/AD8551.asy new file mode 100755 index 0000000..70c4ed2 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8551.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8551 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8551 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Single +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8552.asy b/spice/copy/sym/OpAmps/AD8552.asy new file mode 100755 index 0000000..9b7eb3b --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8552.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8552 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8552 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Dual +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8554.asy b/spice/copy/sym/OpAmps/AD8554.asy new file mode 100755 index 0000000..4fdc41d --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8554.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8554 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8554 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Quad +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8565.asy b/spice/copy/sym/OpAmps/AD8565.asy new file mode 100755 index 0000000..8258b06 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8565.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8565 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8565 +SYMATTR Description 16 V Rail-to-Rail Operational Amplifier (Single) +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8571.asy b/spice/copy/sym/OpAmps/AD8571.asy new file mode 100755 index 0000000..6e10945 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8571.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8571 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8571 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Single +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8572.asy b/spice/copy/sym/OpAmps/AD8572.asy new file mode 100755 index 0000000..de3727b --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8572.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8572 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8572 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Dual +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8574.asy b/spice/copy/sym/OpAmps/AD8574.asy new file mode 100755 index 0000000..1635191 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8574.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8574 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8574 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Quad +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8601.asy b/spice/copy/sym/OpAmps/AD8601.asy new file mode 100755 index 0000000..6cd45c6 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8601.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8601 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8601 +SYMATTR Description 2.7/5V CMOS OP Low Vos RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8602.asy b/spice/copy/sym/OpAmps/AD8602.asy new file mode 100755 index 0000000..ed71dba --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8602.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8602 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8602 +SYMATTR Description 2.7/5V CMOS OP Low Vos RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8604.asy b/spice/copy/sym/OpAmps/AD8604.asy new file mode 100755 index 0000000..bb34686 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8604.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8604 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8604 +SYMATTR Description 2.7/5V CMOS OP Low Vos RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8605.asy b/spice/copy/sym/OpAmps/AD8605.asy new file mode 100755 index 0000000..71a12ee --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8605.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8605 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8605 +SYMATTR Description 2.7/5V CMOS OP Low Noise RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8606.asy b/spice/copy/sym/OpAmps/AD8606.asy new file mode 100755 index 0000000..f77ee69 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8606.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8606 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8606 +SYMATTR Description 7/5V CMOS OP Low Noise RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8608.asy b/spice/copy/sym/OpAmps/AD8608.asy new file mode 100755 index 0000000..09607f3 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8608.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8608 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8608 +SYMATTR Description 2.7/5V CMOS OP Low Noise RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8613.asy b/spice/copy/sym/OpAmps/AD8613.asy new file mode 100755 index 0000000..086dd87 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8613.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8613 +SYMATTR Value2 AD8613 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description Low Cost Micropower, Low Noise CMOS Rail-to-Rail, Input/Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8614.asy b/spice/copy/sym/OpAmps/AD8614.asy new file mode 100755 index 0000000..735ae2a --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8614.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8614 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8614 +SYMATTR Description Single high-voltage LCD driver +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8617.asy b/spice/copy/sym/OpAmps/AD8617.asy new file mode 100755 index 0000000..b33b4f3 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8617.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8617 +SYMATTR Value2 AD8617 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description Dual Low Cost Micropower, Low Noise CMOS Rail-to-Rail, Input/Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8618.asy b/spice/copy/sym/OpAmps/AD8618.asy new file mode 100755 index 0000000..05787f7 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8618.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8618 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8618 +SYMATTR Description 2.7/5V CMOS OP Fast RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8619.asy b/spice/copy/sym/OpAmps/AD8619.asy new file mode 100755 index 0000000..517387f --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8619.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8619 +SYMATTR Value2 AD8619 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description Quad Low Cost Micropower, Low Noise CMOS Rail-to-Rail, Input/Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8624.asy b/spice/copy/sym/OpAmps/AD8624.asy new file mode 100755 index 0000000..3aca497 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8624.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8624 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8624 +SYMATTR Description 5/30V BIP OP Low Noise RRO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8628.asy b/spice/copy/sym/OpAmps/AD8628.asy new file mode 100755 index 0000000..9831311 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8628.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8628 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8628 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Single +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8629.asy b/spice/copy/sym/OpAmps/AD8629.asy new file mode 100755 index 0000000..e784a4a --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8629.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8629 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8629 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Dual +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8630.asy b/spice/copy/sym/OpAmps/AD8630.asy new file mode 100755 index 0000000..c627546 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8630.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8630 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8630 +SYMATTR Description 2.7/5V, CMOS, OP, Zero Drift, RRIO, Quad +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8634.asy b/spice/copy/sym/OpAmps/AD8634.asy new file mode 100755 index 0000000..d56a947 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8634.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8634 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8634 +SYMATTR Description High Temp Low Power Dual Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8641.asy b/spice/copy/sym/OpAmps/AD8641.asy new file mode 100755 index 0000000..8c8f70c --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8641.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8641 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8641 +SYMATTR Description 5/26V JFET OP RRO Single Supply +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8642.asy b/spice/copy/sym/OpAmps/AD8642.asy new file mode 100755 index 0000000..207ed75 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8642.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8642 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8642 +SYMATTR Description 5/26V JFET OP RRO Single Supply +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8643.asy b/spice/copy/sym/OpAmps/AD8643.asy new file mode 100755 index 0000000..792ee17 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8643.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8643 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8643 +SYMATTR Description 5/26V JFET OP RRO Single Supply +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8648.asy b/spice/copy/sym/OpAmps/AD8648.asy new file mode 100755 index 0000000..aa0dd6a --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8648.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8648 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8648 +SYMATTR Description 2.7/5V CMOS OP Fast RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8657.asy b/spice/copy/sym/OpAmps/AD8657.asy new file mode 100755 index 0000000..836d05f Binary files /dev/null and b/spice/copy/sym/OpAmps/AD8657.asy differ diff --git a/spice/copy/sym/OpAmps/AD8662.asy b/spice/copy/sym/OpAmps/AD8662.asy new file mode 100755 index 0000000..5967fc4 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8662.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8662 +SYMATTR Value2 AD8662 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description Dual Low Noise, Precision 16 V CMOS, Rail-to-Rail Operational Amplifiers +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8663.asy b/spice/copy/sym/OpAmps/AD8663.asy new file mode 100755 index 0000000..2c5cc4a --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8663.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8663 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8663 +SYMATTR Description 5/16V CMOS OP Low Noise Single Supply +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8664.asy b/spice/copy/sym/OpAmps/AD8664.asy new file mode 100755 index 0000000..86d3862 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8664.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8664 +SYMATTR Value2 AD8664 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description Quad Low Noise, Precision 16 V CMOS, Rail-to-Rail Operational Amplifiers +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8665.asy b/spice/copy/sym/OpAmps/AD8665.asy new file mode 100755 index 0000000..57e6f15 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8665.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8665 +SYMATTR Value2 AD8665 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description 16 V, 4 MHz RR0 Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8666.asy b/spice/copy/sym/OpAmps/AD8666.asy new file mode 100755 index 0000000..6dc87d6 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8666.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8666 +SYMATTR Value2 AD8666 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description Dual 16 V, 4 MHz RR0 Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8667.asy b/spice/copy/sym/OpAmps/AD8667.asy new file mode 100755 index 0000000..6a75257 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8667.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8667 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8667 +SYMATTR Description 5/16V CMOS OP Low Noise Single Supply +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8668.asy b/spice/copy/sym/OpAmps/AD8668.asy new file mode 100755 index 0000000..8cb303e --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8668.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8668 +SYMATTR Value2 AD8668 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description Quad 16 V, 4 MHz RR0 Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8669.asy b/spice/copy/sym/OpAmps/AD8669.asy new file mode 100755 index 0000000..8846c20 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8669.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8669 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8669 +SYMATTR Description 5/16V CMOS OP Low Noise Single Supply +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8671.asy b/spice/copy/sym/OpAmps/AD8671.asy new file mode 100755 index 0000000..094ee74 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8671.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8671 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8671 +SYMATTR Description 10/30V BIP OP Low Noise Low Ib +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8672.asy b/spice/copy/sym/OpAmps/AD8672.asy new file mode 100755 index 0000000..c556c79 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8672.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8672 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8672 +SYMATTR Description 10/30V BIP OP Low Noise Low Ib +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8674.asy b/spice/copy/sym/OpAmps/AD8674.asy new file mode 100755 index 0000000..a1a4a7c --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8674.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8674 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8674 +SYMATTR Description 10/30V BIP OP Low Noise Low Ib +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8675.asy b/spice/copy/sym/OpAmps/AD8675.asy new file mode 100755 index 0000000..cf1a2d5 Binary files /dev/null and b/spice/copy/sym/OpAmps/AD8675.asy differ diff --git a/spice/copy/sym/OpAmps/AD8682.asy b/spice/copy/sym/OpAmps/AD8682.asy new file mode 100755 index 0000000..708f593 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8682.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8682 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8682 +SYMATTR Description Dual Low Power High Speed JFET Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8684.asy b/spice/copy/sym/OpAmps/AD8684.asy new file mode 100755 index 0000000..89bd506 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8684.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8684 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 AD8684 +SYMATTR Description Quad Low Power High Speed JFET Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/AD8691.asy b/spice/copy/sym/OpAmps/AD8691.asy new file mode 100755 index 0000000..27732a4 --- /dev/null +++ b/spice/copy/sym/OpAmps/AD8691.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value AD8691 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 AD8691 +SYMATTR Description 2.7/5V CMOS OP Low Noise Single Supply +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4000-1.asy b/spice/copy/sym/OpAmps/ADA4000-1.asy new file mode 100755 index 0000000..770d769 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4000-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4000-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4000 +SYMATTR Description Low Cost, Precision JFET Input Operational Amplifiers +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4000-2.asy b/spice/copy/sym/OpAmps/ADA4000-2.asy new file mode 100755 index 0000000..62f96ec --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4000-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4000-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4000 +SYMATTR Description Dual Low Cost, Precision JFET Input Operational Amplifiers +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4000-4.asy b/spice/copy/sym/OpAmps/ADA4000-4.asy new file mode 100755 index 0000000..b07ec74 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4000-4.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4000-4 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4000 +SYMATTR Description Quad Low Cost, Precision JFET Input Operational Amplifiers +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4051.asy b/spice/copy/sym/OpAmps/ADA4051.asy new file mode 100755 index 0000000..a0bc2ce --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4051.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4051 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4051 +SYMATTR Description 1.8/5V, CMOS, OP, Zero Drift, RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4077-2.asy b/spice/copy/sym/OpAmps/ADA4077-2.asy new file mode 100755 index 0000000..4c076e2 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4077-2.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4077-2 +SYMATTR SpiceModel ADA4077-2 +SYMATTR Prefix X +SYMATTR ModelFile ADI.lib +SYMATTR Value2 ADA4077-2 +SYMATTR Description 5/30V, BIP, OP, Low Vos, Low Drift +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4091.asy b/spice/copy/sym/OpAmps/ADA4091.asy new file mode 100755 index 0000000..9c8e07b --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4091.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4091 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4091 +SYMATTR Description 2.7/30V BIP OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4092.asy b/spice/copy/sym/OpAmps/ADA4092.asy new file mode 100755 index 0000000..1391cc6 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4092.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4092 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4092 +SYMATTR Description 2.7/30V BIP OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4096.asy b/spice/copy/sym/OpAmps/ADA4096.asy new file mode 100755 index 0000000..754515b --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4096.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4096 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4096 +SYMATTR Description 3/30V BIP OP OVP RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4098-1.asy b/spice/copy/sym/OpAmps/ADA4098-1.asy new file mode 100755 index 0000000..d805661 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4098-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal -16 -32 -16 -23 +LINE Normal -16 25 -16 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal -2 -26 -12 -26 +LINE Normal -7 -21 -7 -31 +LINE Normal 16 8 16 32 +LINE Normal -2 27 -11 27 +TEXT 13 21 Right 1 S +WINDOW 3 22 32 Left 2 +WINDOW 0 6 -25 Left 2 +SYMATTR Value ADA4098-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADA4098-1.lib +SYMATTR Value2 ADA4098-1 +SYMATTR Description Over-The-Top Rail-to-Rail Input and Output Operational Amplifier with Shutdown +PIN -32 16 NONE 8 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 8 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 8 +PINATTR PinName SD +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/ADA4099-1.asy b/spice/copy/sym/OpAmps/ADA4099-1.asy new file mode 100755 index 0000000..c0f28af --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4099-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal -16 -32 -16 -23 +LINE Normal -16 25 -16 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal -2 -26 -12 -26 +LINE Normal -7 -21 -7 -31 +LINE Normal 16 8 16 32 +LINE Normal -2 27 -11 27 +TEXT 13 21 Right 1 S +WINDOW 3 22 32 Left 2 +WINDOW 0 6 -25 Left 2 +SYMATTR Value ADA4099-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADA4099-1.lib +SYMATTR Value2 ADA4099-1 +SYMATTR Description Over-The-Top Rail-to-Rail Input and Output Operational Amplifier with Shutdown +PIN -32 16 NONE 8 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 8 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 8 +PINATTR PinName SD +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/ADA4177-1.asy b/spice/copy/sym/OpAmps/ADA4177-1.asy new file mode 100755 index 0000000..2297fd8 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4177-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value ADA4177-1 +SYMATTR Value2 ADA4177-1 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description OVP and EMI Protected, Precision, Low Noise and Bias Op Amp +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4177-2.asy b/spice/copy/sym/OpAmps/ADA4177-2.asy new file mode 100755 index 0000000..d2db4d3 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4177-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value ADA4177-2 +SYMATTR Value2 ADA4177-1 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description Dual OVP and EMI Protected, Precision, Low Noise and Bias Op Amp +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4177-4.asy b/spice/copy/sym/OpAmps/ADA4177-4.asy new file mode 100755 index 0000000..8e3c78f --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4177-4.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value ADA4177-4 +SYMATTR Value2 ADA4177-1 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description Quad OVP and EMI Protected, Precision, Low Noise and Bias Op Amp +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4177.asy b/spice/copy/sym/OpAmps/ADA4177.asy new file mode 100755 index 0000000..2297fd8 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4177.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value ADA4177-1 +SYMATTR Value2 ADA4177-1 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description OVP and EMI Protected, Precision, Low Noise and Bias Op Amp +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4254.asy b/spice/copy/sym/OpAmps/ADA4254.asy new file mode 100755 index 0000000..53dfd79 Binary files /dev/null and b/spice/copy/sym/OpAmps/ADA4254.asy differ diff --git a/spice/copy/sym/OpAmps/ADA4500.asy b/spice/copy/sym/OpAmps/ADA4500.asy new file mode 100755 index 0000000..51a9ef8 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4500.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4500 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4500 +SYMATTR Description 2.7/5V CMOS OP ZCO RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4505.asy b/spice/copy/sym/OpAmps/ADA4505.asy new file mode 100755 index 0000000..02d104d --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4505.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4505 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4505 +SYMATTR Description 1.8/5V CMOS OP ZCO RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4522-1.asy b/spice/copy/sym/OpAmps/ADA4522-1.asy new file mode 100755 index 0000000..e90bb90 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4522-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4522-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4522-1 +SYMATTR Description Single 55V Low Noise Zero Drift OpAmp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4522-2.asy b/spice/copy/sym/OpAmps/ADA4522-2.asy new file mode 100755 index 0000000..2375698 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4522-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4522-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4522-1 +SYMATTR Description Dual 55V Low Noise Zero Drift OpAmps +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4522-4.asy b/spice/copy/sym/OpAmps/ADA4522-4.asy new file mode 100755 index 0000000..001798a --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4522-4.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4522-4 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4522-1 +SYMATTR Description Quad 55V Low Noise Zero Drift OpAmps +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4522.asy b/spice/copy/sym/OpAmps/ADA4522.asy new file mode 100755 index 0000000..e90bb90 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4522.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4522-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4522-1 +SYMATTR Description Single 55V Low Noise Zero Drift OpAmp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4523-1.asy b/spice/copy/sym/OpAmps/ADA4523-1.asy new file mode 100755 index 0000000..3c6b85c --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4523-1.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal -16 -32 -16 -23 +LINE Normal -16 25 -16 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal -2 -26 -12 -26 +LINE Normal -7 -21 -7 -31 +LINE Normal 16 8 16 32 +LINE Normal -2 27 -11 27 +LINE Normal 16 -32 16 -8 +TEXT 25 -19 Left 1 _SD +TEXT 25 19 Left 1 SDCOM +WINDOW 3 -47 60 Left 2 +WINDOW 0 -34 -65 Left 2 +SYMATTR Value ADA4523-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADA4523-1.sub +SYMATTR Value2 ADA4523-1 +SYMATTR Description 36V, Low Noise, Zero Drift Op Amp +PIN 16 -32 NONE 6 +PINATTR PinName _SD +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -32 16 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -16 -32 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 6 +PIN 16 32 NONE 6 +PINATTR PinName SDCOM +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/ADA4528-2.asy b/spice/copy/sym/OpAmps/ADA4528-2.asy new file mode 100755 index 0000000..aacf25b --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4528-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4528-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4528 +SYMATTR Description Dual Precision, Ultralow Noise, RRIO, Zero Drift Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4530-1.asy b/spice/copy/sym/OpAmps/ADA4530-1.asy new file mode 100755 index 0000000..4557ff4 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4530-1.asy @@ -0,0 +1,60 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal 0 -64 0 -32 +LINE Normal 0 64 0 32 +LINE Normal -48 48 -56 48 +LINE Normal -52 52 -52 44 +LINE Normal -48 -48 -56 -48 +LINE Normal 8 -40 16 -40 +LINE Normal 12 -36 12 -44 +LINE Normal 8 40 16 40 +LINE Normal -35 -8 -35 8 +LINE Normal -35 -8 -30 -8 +LINE Normal -26 -4 -30 -8 +LINE Normal -26 -4 -30 0 +LINE Normal -35 0 -30 0 +LINE Normal -26 4 -30 0 +LINE Normal -26 4 -26 8 +LINE Normal -53 -4 -49 -8 +LINE Normal -49 -8 -45 -8 +LINE Normal -53 4 -49 8 +LINE Normal -53 4 -53 -4 +LINE Normal -49 8 -45 8 +LINE Normal -41 4 -45 8 +LINE Normal -41 4 -41 0 +LINE Normal -45 0 -41 0 +LINE Normal -20 -8 -20 8 +LINE Normal -9 -4 -13 -8 +LINE Normal -13 -8 -20 -8 +LINE Normal -9 4 -13 8 +LINE Normal -9 4 -9 -4 +LINE Normal -13 8 -20 8 +LINE Normal -45 -8 -43 -6 +WINDOW 0 20 -44 Left 2 +WINDOW 3 40 48 Left 2 +SYMATTR Value ADA4530-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4530-1 +SYMATTR Description Femtoampere Input Bias Current Electrometer Amplifier +PIN -64 0 NONE 0 +PINATTR PinName GRD +PINATTR SpiceOrder 6 +PIN -64 48 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -64 -48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 0 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/OpAmps/ADA4530.asy b/spice/copy/sym/OpAmps/ADA4530.asy new file mode 100755 index 0000000..4557ff4 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4530.asy @@ -0,0 +1,60 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal 0 -64 0 -32 +LINE Normal 0 64 0 32 +LINE Normal -48 48 -56 48 +LINE Normal -52 52 -52 44 +LINE Normal -48 -48 -56 -48 +LINE Normal 8 -40 16 -40 +LINE Normal 12 -36 12 -44 +LINE Normal 8 40 16 40 +LINE Normal -35 -8 -35 8 +LINE Normal -35 -8 -30 -8 +LINE Normal -26 -4 -30 -8 +LINE Normal -26 -4 -30 0 +LINE Normal -35 0 -30 0 +LINE Normal -26 4 -30 0 +LINE Normal -26 4 -26 8 +LINE Normal -53 -4 -49 -8 +LINE Normal -49 -8 -45 -8 +LINE Normal -53 4 -49 8 +LINE Normal -53 4 -53 -4 +LINE Normal -49 8 -45 8 +LINE Normal -41 4 -45 8 +LINE Normal -41 4 -41 0 +LINE Normal -45 0 -41 0 +LINE Normal -20 -8 -20 8 +LINE Normal -9 -4 -13 -8 +LINE Normal -13 -8 -20 -8 +LINE Normal -9 4 -13 8 +LINE Normal -9 4 -9 -4 +LINE Normal -13 8 -20 8 +LINE Normal -45 -8 -43 -6 +WINDOW 0 20 -44 Left 2 +WINDOW 3 40 48 Left 2 +SYMATTR Value ADA4530-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4530-1 +SYMATTR Description Femtoampere Input Bias Current Electrometer Amplifier +PIN -64 0 NONE 0 +PINATTR PinName GRD +PINATTR SpiceOrder 6 +PIN -64 48 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -64 -48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 0 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/OpAmps/ADA4610.asy b/spice/copy/sym/OpAmps/ADA4610.asy new file mode 100755 index 0000000..8632e29 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4610.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4610 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4610 +SYMATTR Description Low Noise Precision Rail to Rail Output JFET Single/Dual/Quad Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4622.asy b/spice/copy/sym/OpAmps/ADA4622.asy new file mode 100755 index 0000000..52f26ae --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4622.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4622 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4622 +SYMATTR Description 30V 8 MHz Low Bias Current Single-Supply RRO Precision Single/Dual/Quad Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4625-1.asy b/spice/copy/sym/OpAmps/ADA4625-1.asy new file mode 100755 index 0000000..51bd5e9 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4625-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4625-1 +SYMATTR Prefix X +SYMATTR Description 36V, 18MHz, Low Noise, Fast Settling Single Supply, RRO, JFET Op Amp +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4625-1 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4625-2.asy b/spice/copy/sym/OpAmps/ADA4625-2.asy new file mode 100755 index 0000000..c7308aa --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4625-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4625-2 +SYMATTR Prefix X +SYMATTR Description Dual 36V, 18MHz, Low Noise, Fast Settling Single Supply, RRO, JFET Op Amp +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4625-2 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4625.asy b/spice/copy/sym/OpAmps/ADA4625.asy new file mode 100755 index 0000000..51bd5e9 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4625.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4625-1 +SYMATTR Prefix X +SYMATTR Description 36V, 18MHz, Low Noise, Fast Settling Single Supply, RRO, JFET Op Amp +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4625-1 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4627.asy b/spice/copy/sym/OpAmps/ADA4627.asy new file mode 100755 index 0000000..72ebcb1 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4627.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4627 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4627 +SYMATTR Description 30V High Speed Low Bias Current JFET OP Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4637.asy b/spice/copy/sym/OpAmps/ADA4637.asy new file mode 100755 index 0000000..b6faf56 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4637.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4637 +SYMATTR Value2 ADA4637 +SYMATTR SpiceModel ADI1.lib +SYMATTR Prefix X +SYMATTR Description 30 V, High Speed, Low Noise, Low Bias Current, JFET Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4661-2.asy b/spice/copy/sym/OpAmps/ADA4661-2.asy new file mode 100755 index 0000000..4f56c1f Binary files /dev/null and b/spice/copy/sym/OpAmps/ADA4661-2.asy differ diff --git a/spice/copy/sym/OpAmps/ADA4665.asy b/spice/copy/sym/OpAmps/ADA4665.asy new file mode 100755 index 0000000..4afabde --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4665.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4665 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4665 +SYMATTR Description 5/16V CMOS OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4666-2.asy b/spice/copy/sym/OpAmps/ADA4666-2.asy new file mode 100755 index 0000000..1192f60 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4666-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4666-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4666-2 +SYMATTR Description Dual 18 V, 725 µA, 4 MHz CMOS RRIO Operational Amplifie +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4700-1.asy b/spice/copy/sym/OpAmps/ADA4700-1.asy new file mode 100755 index 0000000..41deaf0 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4700-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4700-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4700-1 +SYMATTR Description High Voltage, Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4805.asy b/spice/copy/sym/OpAmps/ADA4805.asy new file mode 100755 index 0000000..2aa97e4 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4805.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 8 17 13 17 +LINE Normal 8 21 8 17 +LINE Normal 13 21 8 21 +LINE Normal 13 26 13 21 +LINE Normal 8 26 13 26 +LINE Normal -16 -32 -16 -23 +LINE Normal -16 25 -16 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal -2 -26 -12 -26 +LINE Normal -7 -21 -7 -31 +LINE Normal 16 8 16 32 +LINE Normal -2 27 -11 27 +LINE Normal 8 14 13 14 +WINDOW 3 22 32 Left 2 +WINDOW 0 6 -25 Left 2 +SYMATTR Value ADA4805 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4805 +SYMATTR Description Ultra Low Power 120Mhz High Sp R/R Amp +PIN -32 16 NONE 8 +PINATTR PinName 100 +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 8 +PINATTR PinName 101 +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 8 +PINATTR PinName 102 +PINATTR SpiceOrder 3 +PIN -16 32 NONE 8 +PINATTR PinName 103 +PINATTR SpiceOrder 4 +PIN 32 0 NONE 8 +PINATTR PinName 104 +PINATTR SpiceOrder 5 +PIN 16 32 NONE 8 +PINATTR PinName 106 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/ADA4807-1.asy b/spice/copy/sym/OpAmps/ADA4807-1.asy new file mode 100755 index 0000000..4e531c4 Binary files /dev/null and b/spice/copy/sym/OpAmps/ADA4807-1.asy differ diff --git a/spice/copy/sym/OpAmps/ADA4807-2.asy b/spice/copy/sym/OpAmps/ADA4807-2.asy new file mode 100755 index 0000000..70eb4c9 Binary files /dev/null and b/spice/copy/sym/OpAmps/ADA4807-2.asy differ diff --git a/spice/copy/sym/OpAmps/ADA4807-4.asy b/spice/copy/sym/OpAmps/ADA4807-4.asy new file mode 100755 index 0000000..32a8963 Binary files /dev/null and b/spice/copy/sym/OpAmps/ADA4807-4.asy differ diff --git a/spice/copy/sym/OpAmps/ADA4807.asy b/spice/copy/sym/OpAmps/ADA4807.asy new file mode 100755 index 0000000..4e531c4 Binary files /dev/null and b/spice/copy/sym/OpAmps/ADA4807.asy differ diff --git a/spice/copy/sym/OpAmps/ADA4830.asy b/spice/copy/sym/OpAmps/ADA4830.asy new file mode 100755 index 0000000..93aac69 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4830.asy @@ -0,0 +1,88 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -32 -56 -32 +LINE Normal -45 32 -55 32 +LINE Normal -50 37 -50 27 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal 16 -41 16 -64 +LINE Normal 144 0 96 0 +LINE Normal -27 54 -37 54 +LINE Normal 16 80 16 41 +LINE Normal -51 6 -54 -6 +LINE Normal -48 -6 -51 6 +LINE Normal -44 6 -44 -6 +LINE Normal -38 -6 -44 -6 +LINE Normal -38 -1 -38 -6 +LINE Normal -44 -1 -38 -1 +LINE Normal -38 6 -44 -1 +LINE Normal -34 6 -34 -6 +LINE Normal -28 6 -34 6 +LINE Normal -28 -6 -34 -6 +LINE Normal -28 -1 -34 -1 +LINE Normal -24 6 -24 -6 +LINE Normal -18 -6 -24 -6 +LINE Normal -20 -1 -24 -1 +LINE Normal 1 -32 7 -32 +LINE Normal 1 -28 1 -32 +LINE Normal 7 -28 1 -28 +LINE Normal 7 -24 7 -28 +LINE Normal 1 -24 7 -24 +LINE Normal 17 -32 11 -32 +LINE Normal 14 -32 17 -32 +LINE Normal 14 -24 14 -32 +LINE Normal 21 -24 21 -32 +LINE Normal 26 -32 21 -32 +LINE Normal 26 -28 26 -32 +LINE Normal 21 -28 26 -28 +LINE Normal 26 -24 21 -24 +LINE Normal 26 -24 26 -28 +LINE Normal 1 26 7 26 +LINE Normal 1 30 1 26 +LINE Normal 7 30 1 30 +LINE Normal 1 30 7 30 +LINE Normal 1 34 1 30 +LINE Normal 7 34 1 34 +LINE Normal 11 26 11 34 +LINE Normal 15 34 11 26 +LINE Normal 15 26 15 34 +LINE Normal 19 34 21 26 +LINE Normal 21 26 19 34 +LINE Normal 23 34 21 26 +LINE Normal 22 30 20 30 +WINDOW 3 48 64 Left 2 +WINDOW 0 32 -64 Left 2 +SYMATTR Value ADA4830 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4830 +SYMATTR Description 10GHz GBW, 1.1nV/ Hz½ Differential Amplifier/ADC Driver +PIN -64 0 NONE 8 +PINATTR PinName VREF +PINATTR SpiceOrder 1 +PIN -64 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 2 +PIN -64 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 4 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 5 +PIN 16 80 NONE 8 +PINATTR PinName ENA +PINATTR SpiceOrder 6 +PIN 16 -64 NONE 8 +PINATTR PinName STB +PINATTR SpiceOrder 7 +PIN 144 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/ADA4841.asy b/spice/copy/sym/OpAmps/ADA4841.asy new file mode 100755 index 0000000..1a9ee90 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4841.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 8 17 13 17 +LINE Normal 8 21 8 17 +LINE Normal 13 21 8 21 +LINE Normal 13 26 13 21 +LINE Normal 8 26 13 26 +LINE Normal -16 -32 -16 -23 +LINE Normal -16 25 -16 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal -2 -26 -12 -26 +LINE Normal -7 -21 -7 -31 +LINE Normal 16 8 16 32 +LINE Normal -2 27 -11 27 +LINE Normal 8 14 13 14 +WINDOW 3 22 32 Left 2 +WINDOW 0 6 -25 Left 2 +SYMATTR Value ADA4841 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4841 +SYMATTR Description Low Power Low Noise OpAmp +PIN -32 16 NONE 8 +PINATTR PinName NI +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 8 +PINATTR PinName +V +PINATTR SpiceOrder 3 +PIN -16 32 NONE 8 +PINATTR PinName -V +PINATTR SpiceOrder 4 +PIN 32 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 8 +PINATTR PinName _D +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/ADA4857.asy b/spice/copy/sym/OpAmps/ADA4857.asy new file mode 100755 index 0000000..a8d66c6 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4857.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 8 17 13 17 +LINE Normal 8 21 8 17 +LINE Normal 13 21 8 21 +LINE Normal 13 26 13 21 +LINE Normal 8 26 13 26 +LINE Normal -16 -32 -16 -23 +LINE Normal -16 25 -16 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal -2 -26 -12 -26 +LINE Normal -7 -21 -7 -31 +LINE Normal 16 8 16 32 +LINE Normal -2 27 -11 27 +LINE Normal 8 14 13 14 +WINDOW 3 22 32 Left 2 +WINDOW 0 6 -25 Left 2 +SYMATTR Value ADA4857 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4857 +SYMATTR Description Ultralow Distortion, Low Power, Low Noise, High Speed Op Amp, Single/Dual +PIN -32 16 NONE 8 +PINATTR PinName 100 +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 8 +PINATTR PinName 101 +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 8 +PINATTR PinName 102 +PINATTR SpiceOrder 3 +PIN -16 32 NONE 8 +PINATTR PinName 103 +PINATTR SpiceOrder 4 +PIN 32 0 NONE 8 +PINATTR PinName 104 +PINATTR SpiceOrder 5 +PIN 16 32 NONE 8 +PINATTR PinName 106 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/ADA4860.asy b/spice/copy/sym/OpAmps/ADA4860.asy new file mode 100755 index 0000000..734d820 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4860.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 8 17 13 17 +LINE Normal 8 21 8 17 +LINE Normal 13 21 8 21 +LINE Normal 13 26 13 21 +LINE Normal 8 26 13 26 +LINE Normal -16 -32 -16 -23 +LINE Normal -16 25 -16 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal -2 -26 -12 -26 +LINE Normal -7 -21 -7 -31 +LINE Normal 16 8 16 32 +LINE Normal -2 27 -11 27 +LINE Normal 8 14 13 14 +WINDOW 3 22 32 Left 2 +WINDOW 0 6 -25 Left 2 +SYMATTR Value ADA4860 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 ADA4860 +SYMATTR Description High Speed, Low Cost,Op Amp +PIN -32 16 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -16 32 NONE 8 +PINATTR PinName Vee +PINATTR SpiceOrder 4 +PIN 32 0 NONE 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 16 32 NONE 8 +PINATTR PinName PD +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/ADA4891.asy b/spice/copy/sym/OpAmps/ADA4891.asy new file mode 100755 index 0000000..8c57126 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4891.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4891 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4891 +SYMATTR Description Low Cost CMOS High Speed R-R Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADA4895.asy b/spice/copy/sym/OpAmps/ADA4895.asy new file mode 100755 index 0000000..b7f9731 Binary files /dev/null and b/spice/copy/sym/OpAmps/ADA4895.asy differ diff --git a/spice/copy/sym/OpAmps/ADA4896.asy b/spice/copy/sym/OpAmps/ADA4896.asy new file mode 100755 index 0000000..ed85912 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADA4896.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADA4896 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADA4896 +SYMATTR Description Low Noise Low Power R/R Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADHV4702-1.asy b/spice/copy/sym/OpAmps/ADHV4702-1.asy new file mode 100755 index 0000000..8cc5da7 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADHV4702-1.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType CELL +LINE Normal -48 -80 96 0 +LINE Normal -48 80 96 0 +LINE Normal -48 -80 -48 80 +LINE Normal -32 80 -32 71 +LINE Normal -32 -80 -32 -71 +LINE Normal 0 80 0 53 +LINE Normal -41 -32 -33 -32 +LINE Normal -41 32 -33 32 +LINE Normal -37 28 -37 36 +LINE Normal -36 -60 -28 -60 +LINE Normal -32 -56 -32 -64 +LINE Normal -36 64 -28 64 +LINE Normal 44 10 52 10 +LINE Normal 44 10 44 4 +LINE Normal 52 4 44 4 +LINE Normal 52 16 52 10 +LINE Normal 44 16 52 16 +LINE Normal -20 31 -20 25 +LINE Normal -15 25 -20 25 +LINE Normal -20 37 -20 31 +LINE Normal -20 37 -15 37 +LINE Normal -12 28 -15 25 +LINE Normal -15 37 -12 34 +LINE Normal -12 34 -12 28 +LINE Normal -5 25 0 25 +LINE Normal 0 37 -5 37 +LINE Normal -8 28 -5 25 +LINE Normal -5 37 -8 34 +LINE Normal -8 34 -8 28 +LINE Normal 0 32 0 37 +LINE Normal -3 32 0 32 +LINE Normal 4 37 4 25 +LINE Normal 12 37 12 25 +LINE Normal 12 37 4 25 +LINE Normal 16 31 16 25 +LINE Normal 21 25 16 25 +LINE Normal 16 37 16 31 +LINE Normal 16 37 21 37 +LINE Normal 24 28 21 25 +LINE Normal 21 37 24 34 +LINE Normal 24 34 24 28 +LINE Normal 48 80 48 27 +LINE Normal 52 0 44 0 +WINDOW 0 64 -32 Left 2 +WINDOW 3 64 32 Left 2 +SYMATTR Value ADHV4702-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADHV4702-1 +SYMATTR Description 24V to 220V Precision Operational Amplifier +PIN -48 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -48 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 96 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 4 +PIN -32 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 5 +PIN 0 80 NONE 20 +PINATTR PinName DGND +PINATTR SpiceOrder 6 +PIN 48 80 NONE 20 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/ADTL082.asy b/spice/copy/sym/OpAmps/ADTL082.asy new file mode 100755 index 0000000..3247fe9 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADTL082.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADTL082 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADTL082 +SYMATTR Description Dual Low Cost JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/ADTL084.asy b/spice/copy/sym/OpAmps/ADTL084.asy new file mode 100755 index 0000000..3ff6a29 --- /dev/null +++ b/spice/copy/sym/OpAmps/ADTL084.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value ADTL084 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 ADTL082 +SYMATTR Description Quad Low Cost JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LM108A.asy b/spice/copy/sym/OpAmps/LM108A.asy new file mode 100755 index 0000000..f96cc17 --- /dev/null +++ b/spice/copy/sym/OpAmps/LM108A.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 20 44 28 44 +LINE Normal 24 40 24 48 +LINE Normal 4 84 12 84 +LINE Normal 16 32 16 56 +LINE Normal -16 32 -16 40 +WINDOW 0 32 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LM108A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1008 +SYMATTR Description Picoamp Input Current, µVolt Offset, Low Noise Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 16 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -16 32 NONE 0 +PINATTR PinName COMP1 +PINATTR SpiceOrder 6 +PIN 0 32 NONE 0 +PINATTR PinName COMP2 +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LM308.asy b/spice/copy/sym/OpAmps/LM308.asy new file mode 100755 index 0000000..73ae9c1 --- /dev/null +++ b/spice/copy/sym/OpAmps/LM308.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 20 44 28 44 +LINE Normal 24 40 24 48 +LINE Normal 4 84 12 84 +LINE Normal 16 32 16 56 +LINE Normal -16 32 -16 40 +WINDOW 0 32 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LM308 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1008 +SYMATTR Description Picoamp Input Current, µVolt Offset, Low Noise Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 16 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -16 32 NONE 0 +PINATTR PinName COMP1 +PINATTR SpiceOrder 6 +PIN 0 32 NONE 0 +PINATTR PinName COMP2 +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LT1001.asy b/spice/copy/sym/OpAmps/LT1001.asy new file mode 100755 index 0000000..f5bf339 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1001.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1001 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1001 +SYMATTR Description Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1001A.asy b/spice/copy/sym/OpAmps/LT1001A.asy new file mode 100755 index 0000000..d708085 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1001A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1001A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1001 +SYMATTR Description Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1001S8.asy b/spice/copy/sym/OpAmps/LT1001S8.asy new file mode 100755 index 0000000..a1b52c5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1001S8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1001S8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1001 +SYMATTR Description Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1002.asy b/spice/copy/sym/OpAmps/LT1002.asy new file mode 100755 index 0000000..baa871a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1002.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1002 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1001 +SYMATTR Description Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1002A.asy b/spice/copy/sym/OpAmps/LT1002A.asy new file mode 100755 index 0000000..55ce6d3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1002A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1002A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1001 +SYMATTR Description Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1006.asy b/spice/copy/sym/OpAmps/LT1006.asy new file mode 100755 index 0000000..b2df6e2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1006.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1006 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1006 +SYMATTR Description Precision Single Supply Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1006A.asy b/spice/copy/sym/OpAmps/LT1006A.asy new file mode 100755 index 0000000..2daab61 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1006A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1006A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1006 +SYMATTR Description Precision Single Supply Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1006S8.asy b/spice/copy/sym/OpAmps/LT1006S8.asy new file mode 100755 index 0000000..72bc6a2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1006S8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1006S8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1006 +SYMATTR Description Precision Single Supply Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1007.asy b/spice/copy/sym/OpAmps/LT1007.asy new file mode 100755 index 0000000..6be7d32 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1007.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1007 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1007 +SYMATTR Description Low noise, High Speed Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1007A.asy b/spice/copy/sym/OpAmps/LT1007A.asy new file mode 100755 index 0000000..2984883 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1007A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1007A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1007 +SYMATTR Description Low noise, High Speed Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1007CS.asy b/spice/copy/sym/OpAmps/LT1007CS.asy new file mode 100755 index 0000000..2ffe0fb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1007CS.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1007CS +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1007 +SYMATTR Description Low noise, High Speed Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1008.asy b/spice/copy/sym/OpAmps/LT1008.asy new file mode 100755 index 0000000..7d0bfbe --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1008.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 20 44 28 44 +LINE Normal 24 40 24 48 +LINE Normal 4 84 12 84 +LINE Normal 16 32 16 56 +LINE Normal -16 32 -16 40 +WINDOW 0 32 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1008 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1008 +SYMATTR Description Picoamp Input Current, µVolt Offset, Low Noise Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 16 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -16 32 NONE 0 +PINATTR PinName COMP1 +PINATTR SpiceOrder 6 +PIN 0 32 NONE 0 +PINATTR PinName COMP2 +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LT1010.asy b/spice/copy/sym/OpAmps/LT1010.asy new file mode 100755 index 0000000..3fc34c3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1010.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -16 32 -16 40 +LINE Normal 0 96 0 80 +LINE Normal -12 36 -4 36 +LINE Normal -8 32 -8 40 +LINE Normal 4 84 12 84 +LINE Normal 16 32 16 56 +WINDOW 0 24 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1010 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1010 +SYMATTR Description Fast +/-150mA Power Buffer +PIN -32 64 NONE 0 +PINATTR PinName In +PINATTR SpiceOrder 1 +PIN -16 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 2 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 3 +PIN 16 32 NONE 0 +PINATTR PinName Bias +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1012.asy b/spice/copy/sym/OpAmps/LT1012.asy new file mode 100755 index 0000000..ab85f5f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1012.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1012 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1012 +SYMATTR Description Picoamp Input Current, µVolt Offset, Low noise Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1012A.asy b/spice/copy/sym/OpAmps/LT1012A.asy new file mode 100755 index 0000000..db64ea4 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1012A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1012A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1012 +SYMATTR Description Picoamp Input Current, µVolt Offset, Low noise Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1012D.asy b/spice/copy/sym/OpAmps/LT1012D.asy new file mode 100755 index 0000000..a2e63f5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1012D.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1012D +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1012 +SYMATTR Description Picoamp Input Current, µVolt Offset, Low noise Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1012S8.asy b/spice/copy/sym/OpAmps/LT1012S8.asy new file mode 100755 index 0000000..27d25eb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1012S8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1012S8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1012 +SYMATTR Description Picoamp Input Current, µVolt Offset, Low noise Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1013.asy b/spice/copy/sym/OpAmps/LT1013.asy new file mode 100755 index 0000000..1ec1026 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1013.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1013 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1013 +SYMATTR Description Dual Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1013A.asy b/spice/copy/sym/OpAmps/LT1013A.asy new file mode 100755 index 0000000..0eb960b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1013A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1013A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1013 +SYMATTR Description Dual Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1013D.asy b/spice/copy/sym/OpAmps/LT1013D.asy new file mode 100755 index 0000000..5cbcf3f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1013D.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1013D +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1013 +SYMATTR Description Dual Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1014.asy b/spice/copy/sym/OpAmps/LT1014.asy new file mode 100755 index 0000000..63830fe --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1014.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1014 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1013 +SYMATTR Description Quad Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1014A.asy b/spice/copy/sym/OpAmps/LT1014A.asy new file mode 100755 index 0000000..4d9f53f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1014A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1014A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1013 +SYMATTR Description Quad Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1014D.asy b/spice/copy/sym/OpAmps/LT1014D.asy new file mode 100755 index 0000000..79d7bbc --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1014D.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1014D +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1013 +SYMATTR Description Quad Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1022.asy b/spice/copy/sym/OpAmps/LT1022.asy new file mode 100755 index 0000000..3de7075 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1022.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1022 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1022 +SYMATTR Description High Speed, Precision JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1022A.asy b/spice/copy/sym/OpAmps/LT1022A.asy new file mode 100755 index 0000000..c4132fc --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1022A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1022A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1022 +SYMATTR Description High Speed, Precision JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1024.asy b/spice/copy/sym/OpAmps/LT1024.asy new file mode 100755 index 0000000..f097f45 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1024.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1024 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1012 +SYMATTR Description Dual, Matched Picoamp µVolt Input, Low Noise Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1024A.asy b/spice/copy/sym/OpAmps/LT1024A.asy new file mode 100755 index 0000000..cd1ee94 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1024A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1024A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1012 +SYMATTR Description Dual, Matched Picoamp µVolt Input, Low Noise Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1028.asy b/spice/copy/sym/OpAmps/LT1028.asy new file mode 100755 index 0000000..692d140 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1028.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 19 43 Left 2 +WINDOW 3 19 93 Left 2 +SYMATTR Value LT1028 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1028 +SYMATTR Description Ultra-Low Noise Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1028A.asy b/spice/copy/sym/OpAmps/LT1028A.asy new file mode 100755 index 0000000..b54690c --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1028A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1028A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1028 +SYMATTR Description Ultra Low Noise Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1028CS.asy b/spice/copy/sym/OpAmps/LT1028CS.asy new file mode 100755 index 0000000..2a5b609 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1028CS.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1028CS +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1028 +SYMATTR Description Ultra Low Noise Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1037.asy b/spice/copy/sym/OpAmps/LT1037.asy new file mode 100755 index 0000000..16f463d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1037.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1037 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1037 +SYMATTR Description Low Noise, High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1037A.asy b/spice/copy/sym/OpAmps/LT1037A.asy new file mode 100755 index 0000000..b783cb6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1037A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1037A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1037 +SYMATTR Description Low Noise, High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1037CS.asy b/spice/copy/sym/OpAmps/LT1037CS.asy new file mode 100755 index 0000000..3c468e6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1037CS.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1037CS +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1037 +SYMATTR Description Low Noise, High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1055.asy b/spice/copy/sym/OpAmps/LT1055.asy new file mode 100755 index 0000000..7d2c5d6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1055.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1055 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1055 +SYMATTR Description Precision, High Speed, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1055A.asy b/spice/copy/sym/OpAmps/LT1055A.asy new file mode 100755 index 0000000..94293cf --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1055A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1055A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1055 +SYMATTR Description Precision, High Speed, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1055S8.asy b/spice/copy/sym/OpAmps/LT1055S8.asy new file mode 100755 index 0000000..5b96651 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1055S8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1055S8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1055 +SYMATTR Description Precision, High Speed, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1056.asy b/spice/copy/sym/OpAmps/LT1056.asy new file mode 100755 index 0000000..bed4a0e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1056.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1056 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1056 +SYMATTR Description Precision, High Speed, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1056A.asy b/spice/copy/sym/OpAmps/LT1056A.asy new file mode 100755 index 0000000..f015db4 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1056A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1056A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1056 +SYMATTR Description Precision, High Speed, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1056S8.asy b/spice/copy/sym/OpAmps/LT1056S8.asy new file mode 100755 index 0000000..38814a6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1056S8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1056S8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1056 +SYMATTR Description Precision, High Speed, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1057.asy b/spice/copy/sym/OpAmps/LT1057.asy new file mode 100755 index 0000000..c63cd17 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1057.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1057 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1057 +SYMATTR Description Dual JFET Input Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1057A.asy b/spice/copy/sym/OpAmps/LT1057A.asy new file mode 100755 index 0000000..65c385b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1057A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1057A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1057 +SYMATTR Description Dual JFET Input Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1057S.asy b/spice/copy/sym/OpAmps/LT1057S.asy new file mode 100755 index 0000000..2889ffa --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1057S.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1057S +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1057 +SYMATTR Description Dual JFET Input Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1058.asy b/spice/copy/sym/OpAmps/LT1058.asy new file mode 100755 index 0000000..44e35a3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1058.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1058 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1057 +SYMATTR Description Quad JFET Input Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1058A.asy b/spice/copy/sym/OpAmps/LT1058A.asy new file mode 100755 index 0000000..485065d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1058A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1058A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1057 +SYMATTR Description Quad JFET Input Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1077.asy b/spice/copy/sym/OpAmps/LT1077.asy new file mode 100755 index 0000000..2873084 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1077.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1077 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description µPower, Single Supply, Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1077A.asy b/spice/copy/sym/OpAmps/LT1077A.asy new file mode 100755 index 0000000..a151d2b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1077A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1077A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description µPower, Single Supply, Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1078.asy b/spice/copy/sym/OpAmps/LT1078.asy new file mode 100755 index 0000000..23cd75c --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1078.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1078 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description µPower, Dual, Single Supply, Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1078A.asy b/spice/copy/sym/OpAmps/LT1078A.asy new file mode 100755 index 0000000..072a775 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1078A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1078A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description µPower, Dual, Single Supply, Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1079.asy b/spice/copy/sym/OpAmps/LT1079.asy new file mode 100755 index 0000000..8574bac --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1079.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1079 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description µPower, Quad, Single Supply, Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1079A.asy b/spice/copy/sym/OpAmps/LT1079A.asy new file mode 100755 index 0000000..16800dd --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1079A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1079A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description µPower, Quad, Single Supply, Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1097.asy b/spice/copy/sym/OpAmps/LT1097.asy new file mode 100755 index 0000000..66be56e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1097.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1097 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1097 +SYMATTR Description Low Cost, Low Power Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1101.asy b/spice/copy/sym/OpAmps/LT1101.asy new file mode 100755 index 0000000..36ea18c --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1101.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1101 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1101 +SYMATTR Description Precision, µPower, Single Supply Instrumentation Amplifier(Fixed Gain = 10 or 100) +PIN -128 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Tap1 +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Tap2 +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1101A.asy b/spice/copy/sym/OpAmps/LT1101A.asy new file mode 100755 index 0000000..12c38b4 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1101A.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1101A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1101 +SYMATTR Description Precision, µPower, Single Supply Instrumentation Amplifier(Fixed Gain = 10 or 100) +PIN -128 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Tap1 +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Tap2 +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1102.asy b/spice/copy/sym/OpAmps/LT1102.asy new file mode 100755 index 0000000..e42cd0f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1102.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1102 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1102 +SYMATTR Description High Speed, Precision, JFET Input Instrumentation Amplifier(Fixed Gain = 10 or 100) +PIN -128 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Tap1 +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Tap2 +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1102A.asy b/spice/copy/sym/OpAmps/LT1102A.asy new file mode 100755 index 0000000..682d1a9 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1102A.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1102A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1102 +SYMATTR Description High Speed, Precision, JFET Input Instrumentation Amplifier(Fixed Gain = 10 or 100) +PIN -128 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Tap1 +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Tap2 +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1112.asy b/spice/copy/sym/OpAmps/LT1112.asy new file mode 100755 index 0000000..9f36a59 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1112.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1112 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1112 +SYMATTR Description Dual Low Power Precision, Picoamp Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1113.asy b/spice/copy/sym/OpAmps/LT1113.asy new file mode 100755 index 0000000..bddc815 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1113.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1113 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1113 +SYMATTR Description Dual Low Noise, Precision, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1114.asy b/spice/copy/sym/OpAmps/LT1114.asy new file mode 100755 index 0000000..306cb1a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1114.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1114 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1112 +SYMATTR Description Quad Low Power Precision, Picoamp Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1115.asy b/spice/copy/sym/OpAmps/LT1115.asy new file mode 100755 index 0000000..cf1a2c5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1115.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1115 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1028 +SYMATTR Description Ultra-Low Noise, Low Distortion, Audio Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1122.asy b/spice/copy/sym/OpAmps/LT1122.asy new file mode 100755 index 0000000..ba83f85 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1122.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1122 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1122 +SYMATTR Description Fast Settling, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1124.asy b/spice/copy/sym/OpAmps/LT1124.asy new file mode 100755 index 0000000..991565a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1124.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1124 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1124 +SYMATTR Description Operational Amplifier Dual Low Noise, High Speed Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1125.asy b/spice/copy/sym/OpAmps/LT1125.asy new file mode 100755 index 0000000..596f9b7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1125.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1125 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1124 +SYMATTR Description Operational Amplifier Quad Low Noise, High Speed Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1126.asy b/spice/copy/sym/OpAmps/LT1126.asy new file mode 100755 index 0000000..74fc25a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1126.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1126 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1126 +SYMATTR Description Dual Decompensated Low Noise High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1127.asy b/spice/copy/sym/OpAmps/LT1127.asy new file mode 100755 index 0000000..928d8cd --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1127.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1127 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1126 +SYMATTR Description Quad Decompensated Low Noise High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1128.asy b/spice/copy/sym/OpAmps/LT1128.asy new file mode 100755 index 0000000..a21398c --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1128.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 19 43 Left 2 +WINDOW 3 20 89 Left 2 +SYMATTR Value LT1128 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1128 +SYMATTR Description Ultra-Low Noise Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1167.asy b/spice/copy/sym/OpAmps/LT1167.asy new file mode 100755 index 0000000..945bb06 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1167.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1167 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1167 +SYMATTR Description Single Resistor Gain Programmable, Precision Instrumentation Amplifier +PIN -128 -96 LEFT 8 +PINATTR PinName Rg +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Rg +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1168.asy b/spice/copy/sym/OpAmps/LT1168.asy new file mode 100755 index 0000000..5ef8a62 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1168.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal 0 -64 0 -32 +LINE Normal -32 64 -32 48 +LINE Normal -48 -48 -56 -48 +LINE Normal -52 -44 -52 -52 +LINE Normal -48 48 -56 48 +LINE Normal 8 -40 16 -40 +LINE Normal 12 -36 12 -44 +LINE Normal -28 56 -20 56 +LINE Normal 32 64 32 16 +LINE Normal -56 -24 -56 -8 +LINE Normal -56 -24 -52 -24 +LINE Normal -48 -20 -52 -24 +LINE Normal -48 -20 -52 -16 +LINE Normal -56 -16 -52 -16 +LINE Normal -48 -12 -52 -16 +LINE Normal -48 -12 -48 -8 +LINE Normal -56 8 -56 24 +LINE Normal -56 8 -52 8 +LINE Normal -48 12 -52 8 +LINE Normal -48 12 -52 16 +LINE Normal -56 16 -52 16 +LINE Normal -48 20 -52 16 +LINE Normal -48 20 -48 24 +WINDOW 0 20 -44 Left 2 +WINDOW 3 40 48 Left 2 +SYMATTR Value LT1168 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1168 +SYMATTR Description µPower, Single Resistor Gain Programmable, Precision Instrumentation Amplifier +PIN -64 -16 NONE 0 +PINATTR PinName RG1 +PINATTR SpiceOrder 1 +PIN -64 48 NONE 0 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -64 -48 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 3 +PIN -32 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 5 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 0 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN -64 16 NONE 0 +PINATTR PinName RG2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1169.asy b/spice/copy/sym/OpAmps/LT1169.asy new file mode 100755 index 0000000..98e3ee9 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1169.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1169 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1169 +SYMATTR Description Dual Low Noise, Picoampere Bias Current, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1178.asy b/spice/copy/sym/OpAmps/LT1178.asy new file mode 100755 index 0000000..cbc9aac --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1178.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1178 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1178 +SYMATTR Description 17mA Max, Dual Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1178A.asy b/spice/copy/sym/OpAmps/LT1178A.asy new file mode 100755 index 0000000..d6b2bcd --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1178A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1178A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1178 +SYMATTR Description 17mA Max, Dual Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1179.asy b/spice/copy/sym/OpAmps/LT1179.asy new file mode 100755 index 0000000..1383292 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1179.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1179 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1178 +SYMATTR Description 17mA Max, Quad Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1179A.asy b/spice/copy/sym/OpAmps/LT1179A.asy new file mode 100755 index 0000000..bc4efe5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1179A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1179A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1178 +SYMATTR Description 17mA Max, Quad Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1187.asy b/spice/copy/sym/OpAmps/LT1187.asy new file mode 100755 index 0000000..77bd188 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1187.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal 0 -64 0 -32 +LINE Normal 0 64 0 32 +LINE Normal -48 -48 -56 -48 +LINE Normal -52 -44 -52 -52 +LINE Normal -48 -16 -56 -16 +LINE Normal -48 16 -56 16 +LINE Normal -52 12 -52 20 +LINE Normal -48 48 -56 48 +LINE Normal 8 -40 16 -40 +LINE Normal 12 -36 12 -44 +LINE Normal 8 40 16 40 +LINE Normal -32 -48 -32 -64 +WINDOW 0 20 -44 Left 2 +WINDOW 3 20 48 Left 2 +SYMATTR Value LT1187 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1187 +SYMATTR Description Low Power Video Difference Amplifier +PIN -64 -48 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -64 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -64 16 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN -64 48 NONE 0 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -32 -64 NONE 0 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1189.asy b/spice/copy/sym/OpAmps/LT1189.asy new file mode 100755 index 0000000..9db3e1a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1189.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal 0 -64 0 -32 +LINE Normal 0 64 0 32 +LINE Normal -48 -48 -56 -48 +LINE Normal -52 -44 -52 -52 +LINE Normal -48 -16 -56 -16 +LINE Normal -48 16 -56 16 +LINE Normal -52 12 -52 20 +LINE Normal -48 48 -56 48 +LINE Normal 8 -40 16 -40 +LINE Normal 12 -36 12 -44 +LINE Normal 8 40 16 40 +LINE Normal -32 -48 -32 -64 +WINDOW 0 20 -44 Left 2 +WINDOW 3 20 48 Left 2 +SYMATTR Value LT1189 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1189 +SYMATTR Description Low Power Video Difference Amplifier +PIN -64 -48 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -64 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -64 16 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN -64 48 NONE 0 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -32 -64 NONE 0 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT118A.asy b/spice/copy/sym/OpAmps/LT118A.asy new file mode 100755 index 0000000..a392cad --- /dev/null +++ b/spice/copy/sym/OpAmps/LT118A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT118A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT118A +SYMATTR Description High Speed Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1190.asy b/spice/copy/sym/OpAmps/LT1190.asy new file mode 100755 index 0000000..292d0f1 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1190.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 26 -4 26 +LINE Normal 16 32 16 8 +LINE Normal 7 17 8 16 +LINE Normal 7 14 13 14 +LINE Normal 8 16 13 16 +LINE Normal 7 20 8 21 +LINE Normal 7 17 7 20 +LINE Normal 13 25 12 26 +LINE Normal 12 26 7 26 +LINE Normal 13 22 12 21 +LINE Normal 13 25 13 22 +LINE Normal 12 21 8 21 +WINDOW 0 5 -28 Left 2 +WINDOW 3 21 19 Left 2 +SYMATTR Value LT1190 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1190 +SYMATTR Description Ultra High Speed Operational Amplifier(Av >= 1) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1191.asy b/spice/copy/sym/OpAmps/LT1191.asy new file mode 100755 index 0000000..9bb923e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1191.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 26 -4 26 +LINE Normal 16 32 16 8 +LINE Normal 7 17 8 16 +LINE Normal 7 14 13 14 +LINE Normal 8 16 13 16 +LINE Normal 7 20 8 21 +LINE Normal 7 17 7 20 +LINE Normal 13 25 12 26 +LINE Normal 12 26 7 26 +LINE Normal 13 22 12 21 +LINE Normal 13 25 13 22 +LINE Normal 12 21 8 21 +WINDOW 0 5 -28 Left 2 +WINDOW 3 21 19 Left 2 +SYMATTR Value LT1191 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1191 +SYMATTR Description Ultra High Speed Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1192.asy b/spice/copy/sym/OpAmps/LT1192.asy new file mode 100755 index 0000000..4d33906 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1192.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 26 -4 26 +LINE Normal 16 32 16 8 +LINE Normal 7 17 8 16 +LINE Normal 7 14 13 14 +LINE Normal 8 16 13 16 +LINE Normal 7 20 8 21 +LINE Normal 7 17 7 20 +LINE Normal 13 25 12 26 +LINE Normal 12 26 7 26 +LINE Normal 13 22 12 21 +LINE Normal 13 25 13 22 +LINE Normal 12 21 8 21 +WINDOW 0 5 -28 Left 2 +WINDOW 3 21 19 Left 2 +SYMATTR Value LT1192 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1192 +SYMATTR Description Ultra High Speed Operational Amplifier(Av >= 5) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1193.asy b/spice/copy/sym/OpAmps/LT1193.asy new file mode 100755 index 0000000..58e66b2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1193.asy @@ -0,0 +1,55 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal 0 -64 0 -32 +LINE Normal 0 64 0 32 +LINE Normal -48 -48 -56 -48 +LINE Normal -52 -44 -52 -52 +LINE Normal -48 -16 -56 -16 +LINE Normal -48 16 -56 16 +LINE Normal -52 12 -52 20 +LINE Normal -48 48 -56 48 +LINE Normal 8 -40 16 -40 +LINE Normal 12 -36 12 -44 +LINE Normal 8 40 16 40 +LINE Normal -32 -48 -32 -64 +LINE Normal -32 -48 -32 -48 +LINE Normal -25 -38 -37 -38 +LINE Normal -27 -32 -35 -32 +LINE Normal -35 -24 -35 -32 +LINE Normal -27 -24 -35 -24 +LINE Normal -27 -16 -27 -24 +LINE Normal -27 -16 -35 -16 +WINDOW 0 20 -44 Left 2 +WINDOW 3 20 48 Left 2 +SYMATTR Value LT1193 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1193 +SYMATTR Description Video Difference Amplifier, Adjustable Gain +PIN -64 -48 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -64 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -64 16 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN -64 48 NONE 0 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -32 -64 NONE 0 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1194.asy b/spice/copy/sym/OpAmps/LT1194.asy new file mode 100755 index 0000000..6f80f7f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1194.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal 0 -64 0 -32 +LINE Normal 0 64 0 32 +LINE Normal -48 -32 -56 -32 +LINE Normal -52 -28 -52 -36 +LINE Normal -48 0 -56 0 +LINE Normal -48 32 -56 32 +LINE Normal -52 28 -52 36 +LINE Normal 8 -40 16 -40 +LINE Normal 12 -36 12 -44 +LINE Normal 40 40 48 40 +LINE Normal 32 64 32 16 +LINE Normal -32 64 -32 48 +WINDOW 0 20 -44 Left 2 +WINDOW 3 40 56 Left 2 +SYMATTR Value LT1194 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1194 +SYMATTR Description Video Difference Amplifier, Gain of 10 +PIN -64 -32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -64 0 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 32 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -64 32 NONE 0 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN -32 64 NONE 0 +PINATTR PinName VOS1 +PINATTR SpiceOrder 7 +PIN 0 64 NONE 0 +PINATTR PinName VOS2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1195.asy b/spice/copy/sym/OpAmps/LT1195.asy new file mode 100755 index 0000000..402e05c --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1195.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 26 -4 26 +LINE Normal 16 32 16 8 +LINE Normal 7 17 8 16 +LINE Normal 7 14 13 14 +LINE Normal 8 16 13 16 +LINE Normal 7 20 8 21 +LINE Normal 7 17 7 20 +LINE Normal 13 25 12 26 +LINE Normal 12 26 7 26 +LINE Normal 13 22 12 21 +LINE Normal 13 25 13 22 +LINE Normal 12 21 8 21 +WINDOW 0 5 -28 Left 2 +WINDOW 3 21 19 Left 2 +SYMATTR Value LT1195 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1195 +SYMATTR Description Low Power, Ultra High Speed Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1206.asy b/spice/copy/sym/OpAmps/LT1206.asy new file mode 100755 index 0000000..feaf4df --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1206.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal -16 96 -16 88 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal -12 92 -4 92 +LINE Normal 16 96 16 72 +LINE Normal 11 65 11 70 +LINE Normal 14 71 15 70 +LINE Normal 14 64 12 64 +LINE Normal 14 71 12 71 +LINE Normal 14 64 15 65 +LINE Normal 11 65 12 64 +LINE Normal 11 70 12 71 +WINDOW 0 16 32 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value LT1206 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1206 +SYMATTR Description 250mA/60MHz Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 96 NONE 0 +PINATTR PinName COMP +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1207.asy b/spice/copy/sym/OpAmps/LT1207.asy new file mode 100755 index 0000000..6de774b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1207.asy @@ -0,0 +1,39 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal -16 96 -16 88 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal -12 92 -4 92 +LINE Normal 16 96 16 72 +WINDOW 0 16 32 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value LT1207 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1206 +SYMATTR Description Dual 250mA/60MHz Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 96 NONE 0 +PINATTR PinName COMP +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1208.asy b/spice/copy/sym/OpAmps/LT1208.asy new file mode 100755 index 0000000..80f81d3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1208.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1208 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1208 +SYMATTR Description Dual 45MHz, 400V/µs Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1209.asy b/spice/copy/sym/OpAmps/LT1209.asy new file mode 100755 index 0000000..bcbede4 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1209.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1209 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1208 +SYMATTR Description Quad 45MHz, 400V/µs Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1210.asy b/spice/copy/sym/OpAmps/LT1210.asy new file mode 100755 index 0000000..f567df8 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1210.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 46 30 44 28 +LINE Normal 44 16 44 28 +LINE Normal 44 16 46 14 +LINE Normal -21 -32 -9 -32 +LINE Normal -15 26 -15 38 +LINE Normal -21 32 -9 32 +LINE Normal 53 16 51 14 +LINE Normal 51 30 53 28 +LINE Normal 51 14 46 14 +LINE Normal 51 30 46 30 +LINE Normal 11 -73 11 -61 +LINE Normal 5 -67 17 -67 +LINE Normal 5 68 17 68 +WINDOW 0 32 -54 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1210 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1210 +SYMATTR Description 1.1A, 35MHz Current Feedback Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName CMP +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1211.asy b/spice/copy/sym/OpAmps/LT1211.asy new file mode 100755 index 0000000..9139fd7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1211.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1211 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1211 +SYMATTR Description 14MHz, 7V/µs, Single Supply Dual Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1212.asy b/spice/copy/sym/OpAmps/LT1212.asy new file mode 100755 index 0000000..caf5fe3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1212.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1212 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1211 +SYMATTR Description 14MHz, 7V/µs, Single Supply Quad Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1213.asy b/spice/copy/sym/OpAmps/LT1213.asy new file mode 100755 index 0000000..02be085 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1213.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1213 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1213 +SYMATTR Description 28MHz, 12V/µs, Single Supply Dual Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1214.asy b/spice/copy/sym/OpAmps/LT1214.asy new file mode 100755 index 0000000..1c8cd7b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1214.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1214 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1213 +SYMATTR Description 28MHz, 12V/µs, Single Supply Quad Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1215.asy b/spice/copy/sym/OpAmps/LT1215.asy new file mode 100755 index 0000000..0f4c675 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1215.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1215 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1215 +SYMATTR Description 23MHz, 50V/µs, Single Supply Dual Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1216.asy b/spice/copy/sym/OpAmps/LT1216.asy new file mode 100755 index 0000000..b41bd4d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1216.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1216 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1215 +SYMATTR Description 23MHz, 50V/µs, Single Supply Quad Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1217.asy b/spice/copy/sym/OpAmps/LT1217.asy new file mode 100755 index 0000000..ae6d1b5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1217.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1217 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1217 +SYMATTR Description Low Power High Speed Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1218.asy b/spice/copy/sym/OpAmps/LT1218.asy new file mode 100755 index 0000000..ccefe51 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1218.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 26 -4 26 +LINE Normal 16 32 16 8 +LINE Normal 7 17 8 16 +LINE Normal 7 14 13 14 +LINE Normal 8 16 13 16 +LINE Normal 7 20 8 21 +LINE Normal 7 17 7 20 +LINE Normal 13 25 12 26 +LINE Normal 12 26 7 26 +LINE Normal 13 22 12 21 +LINE Normal 13 25 13 22 +LINE Normal 12 21 8 21 +WINDOW 0 5 -28 Left 2 +WINDOW 3 21 19 Left 2 +SYMATTR Value LT1218 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1218 +SYMATTR Description Precision Rail-to-Rail Input and Output Op Amp +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1219.asy b/spice/copy/sym/OpAmps/LT1219.asy new file mode 100755 index 0000000..8a36f0b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1219.asy @@ -0,0 +1,42 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 52 9 44 9 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1219 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1219 +SYMATTR Description Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1220.asy b/spice/copy/sym/OpAmps/LT1220.asy new file mode 100755 index 0000000..cf242cc --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1220.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1220 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1220 +SYMATTR Description Very High Speed Operational Amplifier(Av >= 1) +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1221.asy b/spice/copy/sym/OpAmps/LT1221.asy new file mode 100755 index 0000000..47bb4de --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1221.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1221 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1221 +SYMATTR Description Very High Speed Operational Amplifier(Av >= 4) +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1222.asy b/spice/copy/sym/OpAmps/LT1222.asy new file mode 100755 index 0000000..7ec0bc0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1222.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 25 -4 25 +LINE Normal 16 32 16 8 +LINE Normal 7 16 12 16 +LINE Normal 7 26 12 26 +LINE Normal 5 18 7 16 +LINE Normal 5 24 7 26 +LINE Normal 5 24 5 18 +WINDOW 0 0 -30 Left 2 +WINDOW 3 23 18 Left 2 +SYMATTR Value LT1222 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1222 +SYMATTR Description Low Noise, Very High Speed Operational Amplifier(Av >= 10) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName Comp +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1223.asy b/spice/copy/sym/OpAmps/LT1223.asy new file mode 100755 index 0000000..8e1872a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1223.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1223 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1223 +SYMATTR Description 100MHz Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1224.asy b/spice/copy/sym/OpAmps/LT1224.asy new file mode 100755 index 0000000..7ee1161 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1224.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1224 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1224 +SYMATTR Description Very High Speed Operational Amplifier(Av >= 1) +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1225.asy b/spice/copy/sym/OpAmps/LT1225.asy new file mode 100755 index 0000000..ec451c1 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1225.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1225 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1225 +SYMATTR Description Very High Speed Operational Amplifier(Av >= 5) +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1226.asy b/spice/copy/sym/OpAmps/LT1226.asy new file mode 100755 index 0000000..8528822 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1226.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1226 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1226 +SYMATTR Description Very High Speed Operational Amplifier(Av >= 25) +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1227.asy b/spice/copy/sym/OpAmps/LT1227.asy new file mode 100755 index 0000000..a0c36bd --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1227.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1227 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1227 +SYMATTR Description 140MHz Video Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1228.asy b/spice/copy/sym/OpAmps/LT1228.asy new file mode 100755 index 0000000..6f82776 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1228.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1228 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1228 +SYMATTR Description 100MHz Current Feedback Amplifier with DC Gain Control +PIN -128 -96 LEFT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Iset +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Gain +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1229.asy b/spice/copy/sym/OpAmps/LT1229.asy new file mode 100755 index 0000000..7aa8284 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1229.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1229 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1229 +SYMATTR Description Dual 100MHz Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1230.asy b/spice/copy/sym/OpAmps/LT1230.asy new file mode 100755 index 0000000..9ba5e80 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1230.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1230 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1229 +SYMATTR Description Quad 100MHz Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1251.asy b/spice/copy/sym/OpAmps/LT1251.asy new file mode 100755 index 0000000..4508e4e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1251.asy @@ -0,0 +1,58 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 320 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 96 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 336 Center 2 +SYMATTR Value LT1251 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1251 +SYMATTR Description 40MHz Video Fader and DC Gain Controlled Amplifier +PIN -144 -96 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Ic +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName Rc +PINATTR SpiceOrder 5 +PIN -144 224 LEFT 8 +PINATTR PinName NULL +PINATTR SpiceOrder 6 +PIN -144 288 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 7 +PIN 144 288 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 144 224 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN 144 160 RIGHT 8 +PINATTR PinName Rfs +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName Ifs +PINATTR SpiceOrder 11 +PIN 144 32 RIGHT 8 +PINATTR PinName Vfs +PINATTR SpiceOrder 12 +PIN 144 -32 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/OpAmps/LT1252.asy b/spice/copy/sym/OpAmps/LT1252.asy new file mode 100755 index 0000000..fc7e689 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1252.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1252 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1252 +SYMATTR Description Low Cost Video Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1253.asy b/spice/copy/sym/OpAmps/LT1253.asy new file mode 100755 index 0000000..8bcd294 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1253.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1253 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1253 +SYMATTR Description Dual Low Cost Video Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1254.asy b/spice/copy/sym/OpAmps/LT1254.asy new file mode 100755 index 0000000..64347fe --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1254.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1254 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1254 +SYMATTR Description Quad Low Cost Video Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1256.asy b/spice/copy/sym/OpAmps/LT1256.asy new file mode 100755 index 0000000..cb2ba64 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1256.asy @@ -0,0 +1,58 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 320 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 96 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 336 Center 2 +SYMATTR Value LT1256 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1256 +SYMATTR Description 40MHz Video Fader and DC Gain Controlled Amplifier +PIN -144 -96 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Ic +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName Rc +PINATTR SpiceOrder 5 +PIN -144 224 LEFT 8 +PINATTR PinName NULL +PINATTR SpiceOrder 6 +PIN -144 288 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 7 +PIN 144 288 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 144 224 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN 144 160 RIGHT 8 +PINATTR PinName Rfs +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName Ifs +PINATTR SpiceOrder 11 +PIN 144 32 RIGHT 8 +PINATTR PinName Vfs +PINATTR SpiceOrder 12 +PIN 144 -32 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/OpAmps/LT1259.asy b/spice/copy/sym/OpAmps/LT1259.asy new file mode 100755 index 0000000..841561a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1259.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1259 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1259 +SYMATTR Description Low Cost Dual 130MHz Current Feedback Amplifier with Shutdown +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1260.asy b/spice/copy/sym/OpAmps/LT1260.asy new file mode 100755 index 0000000..a23dcb8 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1260.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1260 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1259 +SYMATTR Description Low Cost Triple 130MHz Current Feedback Amplifier with Shutdown +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1328.asy b/spice/copy/sym/OpAmps/LT1328.asy new file mode 100755 index 0000000..b9d01eb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1328.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1328 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1328 +SYMATTR Description 4Mbps IrDA Infrared Receiver -- simulate with LT1328PD, the IR diode +PIN -128 -96 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName FIL +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName DATA +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName MODE +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1328PD.asy b/spice/copy/sym/OpAmps/LT1328PD.asy new file mode 100755 index 0000000..b8662a1 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1328PD.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType CELL +LINE Normal 0 44 32 44 +LINE Normal 0 20 32 20 +LINE Normal 16 20 32 44 +LINE Normal 16 20 0 44 +LINE Normal 16 0 16 20 +LINE Normal 16 44 16 64 +LINE Normal -32 32 -4 32 +LINE Normal -4 32 -12 24 +LINE Normal -4 32 -12 40 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 72 Left 2 +SYMATTR Value LT1328PD +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1328PD +SYMATTR Description A photodiode similar to a SFH-205 for testing the LT1328, drive the light input with a current source +PIN 16 64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 2 +PIN -32 32 NONE 0 +PINATTR PinName L +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/OpAmps/LT1351.asy b/spice/copy/sym/OpAmps/LT1351.asy new file mode 100755 index 0000000..92506bf --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1351.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 26 -4 26 +LINE Normal 16 32 16 8 +LINE Normal 7 17 8 16 +LINE Normal 7 14 13 14 +LINE Normal 8 16 13 16 +LINE Normal 7 20 8 21 +LINE Normal 7 17 7 20 +LINE Normal 13 25 12 26 +LINE Normal 12 26 7 26 +LINE Normal 13 22 12 21 +LINE Normal 13 25 13 22 +LINE Normal 12 21 8 21 +WINDOW 0 5 -28 Left 2 +WINDOW 3 21 19 Left 2 +SYMATTR Value LT1351 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1351 +SYMATTR Description 250µA, 3MHz, 200V/µs, Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1352.asy b/spice/copy/sym/OpAmps/LT1352.asy new file mode 100755 index 0000000..481d6fd --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1352.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1352 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1352 +SYMATTR Description Dual 250mA, 3MHz, 200V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1353.asy b/spice/copy/sym/OpAmps/LT1353.asy new file mode 100755 index 0000000..2ae67fa --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1353.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1353 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1352 +SYMATTR Description Quad 250mA, 3MHz, 200V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1354.asy b/spice/copy/sym/OpAmps/LT1354.asy new file mode 100755 index 0000000..83122f4 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1354.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1354 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1354 +SYMATTR Description 12MHz, 400V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1355.asy b/spice/copy/sym/OpAmps/LT1355.asy new file mode 100755 index 0000000..1bfa391 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1355.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1355 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1354 +SYMATTR Description Dual 12MHz, 400V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1356.asy b/spice/copy/sym/OpAmps/LT1356.asy new file mode 100755 index 0000000..d62a29d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1356.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1356 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1354 +SYMATTR Description Quad 12MHz, 400V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1357.asy b/spice/copy/sym/OpAmps/LT1357.asy new file mode 100755 index 0000000..3d63db5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1357.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1357 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1357 +SYMATTR Description 25MHz, 600V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1358.asy b/spice/copy/sym/OpAmps/LT1358.asy new file mode 100755 index 0000000..5ad6c9e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1358.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1358 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1357 +SYMATTR Description Dual 25MHz, 600V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1359.asy b/spice/copy/sym/OpAmps/LT1359.asy new file mode 100755 index 0000000..2544a04 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1359.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1359 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1357 +SYMATTR Description Quad 25MHz, 600V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1360.asy b/spice/copy/sym/OpAmps/LT1360.asy new file mode 100755 index 0000000..e2bb098 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1360.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1360 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1360 +SYMATTR Description 50MHz, 800V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1361.asy b/spice/copy/sym/OpAmps/LT1361.asy new file mode 100755 index 0000000..0cb9656 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1361.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1361 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1360 +SYMATTR Description Dual 50MHz, 800V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1362.asy b/spice/copy/sym/OpAmps/LT1362.asy new file mode 100755 index 0000000..92c2055 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1362.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1362 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1360 +SYMATTR Description Quad 50MHz, 800V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1363.asy b/spice/copy/sym/OpAmps/LT1363.asy new file mode 100755 index 0000000..7957487 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1363.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1363 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1363 +SYMATTR Description 70MHz, 1000V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1364.asy b/spice/copy/sym/OpAmps/LT1364.asy new file mode 100755 index 0000000..e520ff2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1364.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1364 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1363 +SYMATTR Description Dual 70MHz, 1000V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1365.asy b/spice/copy/sym/OpAmps/LT1365.asy new file mode 100755 index 0000000..b56d348 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1365.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1365 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1363 +SYMATTR Description Quad 70MHz, 1000V/µs, Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1366.asy b/spice/copy/sym/OpAmps/LT1366.asy new file mode 100755 index 0000000..de80464 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1366.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1366 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1366 +SYMATTR Description Dual Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1367.asy b/spice/copy/sym/OpAmps/LT1367.asy new file mode 100755 index 0000000..6488e57 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1367.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1367 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1366 +SYMATTR Description Quad Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1368.asy b/spice/copy/sym/OpAmps/LT1368.asy new file mode 100755 index 0000000..7d1c2e6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1368.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1368 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1368 +SYMATTR Description Dual Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1369.asy b/spice/copy/sym/OpAmps/LT1369.asy new file mode 100755 index 0000000..58c9985 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1369.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1369 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1368 +SYMATTR Description Quad Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1395.asy b/spice/copy/sym/OpAmps/LT1395.asy new file mode 100755 index 0000000..982961d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1395.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1395 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1395 +SYMATTR Description 400MHz Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1396.asy b/spice/copy/sym/OpAmps/LT1396.asy new file mode 100755 index 0000000..d4cc45a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1396.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1396 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1395 +SYMATTR Description Dual 400MHz Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1397.asy b/spice/copy/sym/OpAmps/LT1397.asy new file mode 100755 index 0000000..47eaf15 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1397.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1397 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1395 +SYMATTR Description Quad 400MHz Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1398.asy b/spice/copy/sym/OpAmps/LT1398.asy new file mode 100755 index 0000000..e83a238 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1398.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 8 -72 16 -72 +LINE Normal 12 -68 12 -76 +LINE Normal 8 72 16 72 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1398 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1398 +SYMATTR Description Dual Low Cost 300MHz Current Feedback Amplifier with Shutdown +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1399.asy b/spice/copy/sym/OpAmps/LT1399.asy new file mode 100755 index 0000000..60ab85a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1399.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1399 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1398 +SYMATTR Description Triple Low Cost 300MHz Current Feedback Amplifier with Shutdown +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1413.asy b/spice/copy/sym/OpAmps/LT1413.asy new file mode 100755 index 0000000..2addd3b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1413.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1413 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1413 +SYMATTR Description Single Supply, Dual Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1413A.asy b/spice/copy/sym/OpAmps/LT1413A.asy new file mode 100755 index 0000000..1273ea1 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1413A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1413A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1413 +SYMATTR Description Single Supply, Dual Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1457.asy b/spice/copy/sym/OpAmps/LT1457.asy new file mode 100755 index 0000000..9a3c61f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1457.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1457 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1457 +SYMATTR Description Dual Precision JFET Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1462.asy b/spice/copy/sym/OpAmps/LT1462.asy new file mode 100755 index 0000000..206d9ef --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1462.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1462 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1462 +SYMATTR Description Dual µPower, 260µW C-Load Picoampere Bias Current JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1463.asy b/spice/copy/sym/OpAmps/LT1463.asy new file mode 100755 index 0000000..bbe1eee --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1463.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1463 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1462 +SYMATTR Description Quad µPower, 260µW C-Load Picoampere Bias Current JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1464.asy b/spice/copy/sym/OpAmps/LT1464.asy new file mode 100755 index 0000000..ca5cac3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1464.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1464 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1464 +SYMATTR Description Dual µPower, 1MHz C-Load Picoampere Bias Current JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1465.asy b/spice/copy/sym/OpAmps/LT1465.asy new file mode 100755 index 0000000..b8e51c6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1465.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1465 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1464 +SYMATTR Description Quad µPower, 1MHz C-Load Picoampere Bias Current JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1466.asy b/spice/copy/sym/OpAmps/LT1466.asy new file mode 100755 index 0000000..76ecab0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1466.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1466 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1466 +SYMATTR Description Dual µPower, Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1466L.asy b/spice/copy/sym/OpAmps/LT1466L.asy new file mode 100755 index 0000000..23504b0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1466L.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1466L +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1466 +SYMATTR Description Dual µPower, Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1467.asy b/spice/copy/sym/OpAmps/LT1467.asy new file mode 100755 index 0000000..1129c93 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1467.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1467 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1466 +SYMATTR Description Quad µPower, Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1467L.asy b/spice/copy/sym/OpAmps/LT1467L.asy new file mode 100755 index 0000000..e7d35ed --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1467L.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1467L +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1466 +SYMATTR Description Quad µPower, Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1468-2.asy b/spice/copy/sym/OpAmps/LT1468-2.asy new file mode 100755 index 0000000..309ae3f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1468-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1468-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LT1468-2 +SYMATTR Description 200MHz, 22V/µs, 16-Bit Accurate Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1468.asy b/spice/copy/sym/OpAmps/LT1468.asy new file mode 100755 index 0000000..59f1c03 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1468.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1468 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1468 +SYMATTR Description 90MHz, 22V/µs, 16-Bit Accurate Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1469-2.asy b/spice/copy/sym/OpAmps/LT1469-2.asy new file mode 100755 index 0000000..8e44842 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1469-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1469-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LT1468-2 +SYMATTR Description Dual 90MHz, 22V/µs, 16-Bit Accurate Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1469.asy b/spice/copy/sym/OpAmps/LT1469.asy new file mode 100755 index 0000000..ffe3adc --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1469.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1469 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1468 +SYMATTR Description Dual 90MHz, 22V/µs, 16-Bit Accurate Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1490.asy b/spice/copy/sym/OpAmps/LT1490.asy new file mode 100755 index 0000000..6844331 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1490.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1490 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1490A +SYMATTR Description Dual µPower Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1490A.asy b/spice/copy/sym/OpAmps/LT1490A.asy new file mode 100755 index 0000000..ec0c39e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1490A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1490A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1490A +SYMATTR Description Dual µPower Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1491.asy b/spice/copy/sym/OpAmps/LT1491.asy new file mode 100755 index 0000000..187af28 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1491.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1491 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1490A +SYMATTR Description Quad µPower Precision Rail-to-Rail Input and Output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1492.asy b/spice/copy/sym/OpAmps/LT1492.asy new file mode 100755 index 0000000..e6b69bb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1492.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1492 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1492 +SYMATTR Description Dual 5MHz, 3V/µs Low Power Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1493.asy b/spice/copy/sym/OpAmps/LT1493.asy new file mode 100755 index 0000000..10ef6af --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1493.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1493 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1492 +SYMATTR Description Quad 5MHz, 3V/µs Low Power Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1494.asy b/spice/copy/sym/OpAmps/LT1494.asy new file mode 100755 index 0000000..1222930 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1494.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1494 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1494 +SYMATTR Description 1.5µA Max Over-the-Top Precision Rail-to-Rail Input and Output Opamp +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1495.asy b/spice/copy/sym/OpAmps/LT1495.asy new file mode 100755 index 0000000..78bc70c --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1495.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1495 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1494 +SYMATTR Description Dual 1.5µA Max Over-the-Top Precision Rail-to-Rail Input and Output Opamp(1 of 2) +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1496.asy b/spice/copy/sym/OpAmps/LT1496.asy new file mode 100755 index 0000000..c3d47b2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1496.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1496 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1494 +SYMATTR Description Quad 1.5µA Max, Precision Rail-to-Rail Input and Output Operational Amplifier(1 of 4) +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1497.asy b/spice/copy/sym/OpAmps/LT1497.asy new file mode 100755 index 0000000..be94fa2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1497.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1497 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1497 +SYMATTR Description Dual 125mA, 50MHz, Current Feedback Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1498.asy b/spice/copy/sym/OpAmps/LT1498.asy new file mode 100755 index 0000000..880618f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1498.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1498 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1498 +SYMATTR Description Dual 10MHz, 6V/µs, Rail-to-Rail Input and Output Precision C-Load Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1499.asy b/spice/copy/sym/OpAmps/LT1499.asy new file mode 100755 index 0000000..523290f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1499.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1499 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1498 +SYMATTR Description Quad 10MHz, 6V/µs, Rail-to-Rail Input and Output Precision C-Load Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1630.asy b/spice/copy/sym/OpAmps/LT1630.asy new file mode 100755 index 0000000..4ee453e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1630.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1630 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1630 +SYMATTR Description Dual 30MHz, 10V/µs, Rail-to-Rail Input and Output Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1631.asy b/spice/copy/sym/OpAmps/LT1631.asy new file mode 100755 index 0000000..afe4d34 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1631.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1631 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1630 +SYMATTR Description Quad 30MHz, 10V/µs, Rail-to-Rail Input and Output Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1632.asy b/spice/copy/sym/OpAmps/LT1632.asy new file mode 100755 index 0000000..4942d84 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1632.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1632 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1632 +SYMATTR Description Dual 45MHz, 45V/µs, Rail-to-Rail Input and Output Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1633.asy b/spice/copy/sym/OpAmps/LT1633.asy new file mode 100755 index 0000000..7c2c3bf --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1633.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1633 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1632 +SYMATTR Description Quad 45MHz, 45V/µs, Rail-to-Rail Input and Output Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1635.asy b/spice/copy/sym/OpAmps/LT1635.asy new file mode 100755 index 0000000..e843db0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1635.asy @@ -0,0 +1,113 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 32 80 32 44 +LINE Normal 64 80 64 27 +LINE Normal -22 -32 -12 -32 +LINE Normal -22 32 -12 32 +LINE Normal -17 27 -17 37 +LINE Normal 5 38 -5 38 +LINE Normal -5 34 -5 38 +LINE Normal 0 36 0 38 +LINE Normal 5 32 -5 32 +LINE Normal -5 29 -5 32 +LINE Normal 5 29 5 32 +LINE Normal 1 28 0 29 +LINE Normal 0 32 0 29 +LINE Normal 1 28 4 28 +LINE Normal 4 28 5 29 +LINE Normal -4 28 -5 29 +LINE Normal -4 28 -1 28 +LINE Normal -1 28 0 29 +LINE Normal 70 32 80 32 +LINE Normal 5 -68 15 -68 +LINE Normal 10 -73 10 -63 +LINE Normal 5 58 -5 58 +LINE Normal -5 54 -5 58 +LINE Normal 1 53 0 54 +LINE Normal 0 58 0 54 +LINE Normal 1 53 5 53 +LINE Normal -4 53 -5 54 +LINE Normal -4 53 -1 53 +LINE Normal -1 53 0 54 +LINE Normal 0 47 -1 48 +LINE Normal 0 51 -1 50 +LINE Normal -1 48 -1 50 +LINE Normal 0 51 4 51 +LINE Normal 4 51 5 50 +LINE Normal 4 47 5 48 +LINE Normal 5 50 5 48 +LINE Normal 2 51 2 47 +LINE Normal 0 47 2 47 +LINE Normal 5 44 -4 44 +LINE Normal -5 43 -4 44 +LINE Normal 0 42 0 46 +LINE Normal -5 41 -5 43 +LINE Normal 27 17 27 20 +LINE Normal 28 16 27 17 +LINE Normal 36 16 28 16 +LINE Normal 37 17 36 16 +LINE Normal 37 20 37 17 +LINE Normal 36 21 37 20 +LINE Normal 28 21 36 21 +LINE Normal 27 20 28 21 +LINE Normal 36 10 32 10 +LINE Normal 37 11 36 10 +LINE Normal 37 13 37 11 +LINE Normal 36 14 37 13 +LINE Normal 32 14 36 14 +LINE Normal 37 6 27 6 +LINE Normal 31 3 31 9 +LINE Normal 37 40 27 40 +LINE Normal 27 36 27 40 +LINE Normal 33 35 32 36 +LINE Normal 32 40 32 36 +LINE Normal 33 35 37 35 +LINE Normal 28 35 27 36 +LINE Normal 28 35 31 35 +LINE Normal 31 35 32 36 +LINE Normal 32 29 31 30 +LINE Normal 32 33 31 32 +LINE Normal 31 30 31 32 +LINE Normal 32 33 36 33 +LINE Normal 36 33 37 32 +LINE Normal 36 29 37 30 +LINE Normal 37 32 37 30 +LINE Normal 34 33 34 29 +LINE Normal 32 29 34 29 +LINE Normal 37 26 28 26 +LINE Normal 27 25 28 26 +LINE Normal 32 24 32 28 +LINE Normal 27 23 27 25 +WINDOW 0 18 -59 Left 2 +WINDOW 3 72 56 Left 2 +SYMATTR Value LT1635 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1635 +SYMATTR Description µPower Rail-to-Rail Operational Amplifier and Reference +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 64 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 32 80 NONE 0 +PINATTR PinName RefOut +PINATTR SpiceOrder 6 +PIN 0 80 NONE 0 +PINATTR PinName RefFB +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LT1636.asy b/spice/copy/sym/OpAmps/LT1636.asy new file mode 100755 index 0000000..cb6afff --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1636.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 8 -72 16 -72 +LINE Normal 12 -68 12 -76 +LINE Normal 8 72 16 72 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1636 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1636 +SYMATTR Description Over-The-Top µPower Rail-to-Rail Input and Output Operational Amplifier with Shutdown +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1637.asy b/spice/copy/sym/OpAmps/LT1637.asy new file mode 100755 index 0000000..ba52623 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1637.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1637 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1637 +SYMATTR Description 1.1MHz, 0.4V/µs Over-The-Top µPower Rail-to-Rail Input and Output Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1638.asy b/spice/copy/sym/OpAmps/LT1638.asy new file mode 100755 index 0000000..09dd796 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1638.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1638 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1638 +SYMATTR Description Dual 1.2MHz, 0.4V/µs, Over-The-Top µPower Rail-to-Rail input and output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1639.asy b/spice/copy/sym/OpAmps/LT1639.asy new file mode 100755 index 0000000..fc88728 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1639.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1639 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1638 +SYMATTR Description Dual 1.2MHz, 0.4V/µs, Over-The-Top µPower Rail-to-Rail input and output Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1672.asy b/spice/copy/sym/OpAmps/LT1672.asy new file mode 100755 index 0000000..ed0ae57 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1672.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1672 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1672 +SYMATTR Description Single 2 µA, Av > 5 Over-The-Top Precision Rail-to-Rail Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1673.asy b/spice/copy/sym/OpAmps/LT1673.asy new file mode 100755 index 0000000..2746588 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1673.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1673 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1672 +SYMATTR Description Dual 2 µA, Av > 5 Over-The-Top Precision Rail-to-Rail Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1674.asy b/spice/copy/sym/OpAmps/LT1674.asy new file mode 100755 index 0000000..c9ee173 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1674.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1674 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1672 +SYMATTR Description Quad 2 µA, Av > 5 Over-The-Top Precision Rail-to-Rail Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1677.asy b/spice/copy/sym/OpAmps/LT1677.asy new file mode 100755 index 0000000..241d98d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1677.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1677 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1677 +SYMATTR Description Low Noise, Rail-to-Rail Input and Output Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1678.asy b/spice/copy/sym/OpAmps/LT1678.asy new file mode 100755 index 0000000..80aa727 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1678.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1678 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1678 +SYMATTR Description Low Noise, Rail-to-Rail, Precision Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1679.asy b/spice/copy/sym/OpAmps/LT1679.asy new file mode 100755 index 0000000..f19f939 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1679.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1679 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1678 +SYMATTR Description Low Noise, Rail-to-Rail, Precision Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1722.asy b/spice/copy/sym/OpAmps/LT1722.asy new file mode 100755 index 0000000..fc610f6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1722.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1722 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1722 +SYMATTR Description 200MHz Low Noise Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1723.asy b/spice/copy/sym/OpAmps/LT1723.asy new file mode 100755 index 0000000..cbad9a1 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1723.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1723 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1722 +SYMATTR Description Dual 200MHz Low Noise Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1724.asy b/spice/copy/sym/OpAmps/LT1724.asy new file mode 100755 index 0000000..2c90d6b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1724.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1724 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1722 +SYMATTR Description Quad 200MHz Low Noise Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1782.asy b/spice/copy/sym/OpAmps/LT1782.asy new file mode 100755 index 0000000..b549cf5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1782.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1782 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1782 +SYMATTR Description µPower Over-The-Top, SOT-23, Rail-to-Rail Input and Output Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1783.asy b/spice/copy/sym/OpAmps/LT1783.asy new file mode 100755 index 0000000..c73cfdc --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1783.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1783 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1783 +SYMATTR Description 1.2MHz µPower Over-The-Top, SOT-23, Rail-to-Rail Input and Output Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1784.asy b/spice/copy/sym/OpAmps/LT1784.asy new file mode 100755 index 0000000..d46d916 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1784.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1784 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1784 +SYMATTR Description 2.5MHz Over-The-Top Rail-to-Rail Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1787.asy b/spice/copy/sym/OpAmps/LT1787.asy new file mode 100755 index 0000000..2dd710f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1787.asy @@ -0,0 +1,37 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1787 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1787 +SYMATTR Description Precision, High Side Current Sense Amplifier +PIN -128 -96 LEFT 8 +PINATTR PinName FIL- +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Vs- +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName VEE +PINATTR SpiceOrder 3 +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 5 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vs+ +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName FIL+ +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LT1789-1.asy b/spice/copy/sym/OpAmps/LT1789-1.asy new file mode 100755 index 0000000..068392f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1789-1.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -96 144 0 +LINE Normal -32 96 144 0 +LINE Normal -32 -96 -32 96 +LINE Normal -25 80 -17 80 +LINE Normal -25 -80 -17 -80 +LINE Normal -21 -76 -21 -84 +LINE Normal 0 -96 0 -78 +LINE Normal 0 96 0 78 +LINE Normal 4 -84 12 -84 +LINE Normal 8 -88 8 -80 +LINE Normal 4 84 12 84 +LINE Normal 80 64 80 35 +TEXT -24 -48 Left 2 G1 +TEXT -24 48 Left 2 G2 +TEXT 80 16 Center 2 REF +WINDOW 0 80 -64 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value LT1789-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1789-1 +SYMATTR Description µPower, Single Supply Rail-to-Rail Output Instrumentation Amplifier +PIN -32 -48 NONE 8 +PINATTR PinName RG1 +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 80 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 5 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 0 -96 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 7 +PIN -32 48 NONE 8 +PINATTR PinName RG2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1789-10.asy b/spice/copy/sym/OpAmps/LT1789-10.asy new file mode 100755 index 0000000..ca78c90 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1789-10.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -96 144 0 +LINE Normal -32 96 144 0 +LINE Normal -32 -96 -32 96 +LINE Normal -25 80 -17 80 +LINE Normal -25 -80 -17 -80 +LINE Normal -21 -76 -21 -84 +LINE Normal 0 -96 0 -78 +LINE Normal 0 96 0 78 +LINE Normal 4 -84 12 -84 +LINE Normal 8 -88 8 -80 +LINE Normal 4 84 12 84 +LINE Normal 80 64 80 35 +TEXT -24 -48 Left 2 G1 +TEXT -24 48 Left 2 G2 +TEXT 80 16 Center 2 REF +WINDOW 0 80 -64 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value LT1789-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1789-10 +SYMATTR Description µPower, Single Supply Rail-to-Rail Output Instrumentation Amplifier +PIN -32 -48 NONE 8 +PINATTR PinName RG1 +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 80 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 5 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 0 -96 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 7 +PIN -32 48 NONE 8 +PINATTR PinName RG2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1792.asy b/spice/copy/sym/OpAmps/LT1792.asy new file mode 100755 index 0000000..5b82cb9 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1792.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1792 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1792 +SYMATTR Description Low Noise, Precision, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1793.asy b/spice/copy/sym/OpAmps/LT1793.asy new file mode 100755 index 0000000..cb72f26 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1793.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1793 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1793 +SYMATTR Description Low Noise, Picoampere Bias Current, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1795.asy b/spice/copy/sym/OpAmps/LT1795.asy new file mode 100755 index 0000000..dc0d2a1 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1795.asy @@ -0,0 +1,66 @@ +Version 4 +SymbolType CELL +LINE Normal -64 -64 -64 64 +LINE Normal -64 -64 64 0 +LINE Normal -64 64 64 0 +LINE Normal -32 -64 -32 -48 +LINE Normal -32 64 -32 48 +LINE Normal -48 -32 -56 -32 +LINE Normal -52 28 -52 36 +LINE Normal -48 32 -56 32 +LINE Normal -28 -56 -20 -56 +LINE Normal -24 -52 -24 -60 +LINE Normal -28 56 -20 56 +LINE Normal 32 64 32 16 +LINE Normal 32 -64 32 -16 +LINE Normal 0 64 0 32 +LINE Normal 40 -20 44 -20 +LINE Normal 40 -20 40 -28 +LINE Normal 44 -28 40 -28 +LINE Normal 44 20 40 20 +LINE Normal 40 24 40 20 +LINE Normal 40 24 44 24 +LINE Normal 44 28 44 24 +LINE Normal 44 28 40 28 +LINE Normal 8 44 4 44 +LINE Normal 8 40 8 44 +LINE Normal 8 40 4 40 +LINE Normal 4 36 4 40 +LINE Normal 4 36 8 36 +LINE Normal 12 36 12 44 +LINE Normal 12 36 16 36 +LINE Normal 16 40 16 36 +LINE Normal 16 40 16 36 +LINE Normal 16 40 12 40 +LINE Normal 16 44 12 40 +WINDOW 0 40 -44 Left 2 +WINDOW 3 40 48 Left 2 +SYMATTR Value LT1795 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1795 +SYMATTR Description Dual 500mA/50MHz Current Feedback Amplifier/xDSL Line Driver +PIN -64 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -64 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -32 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -32 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 0 64 NONE 0 +PINATTR PinName SHDNREF +PINATTR SpiceOrder 6 +PIN 32 64 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 +PIN 32 -64 NONE 0 +PINATTR PinName COMP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1797.asy b/spice/copy/sym/OpAmps/LT1797.asy new file mode 100755 index 0000000..a06bea7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1797.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1797 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1797 +SYMATTR Description 10MHz, Rail-to-Rail Input and Output Op Amp in SOT-23 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1800.asy b/spice/copy/sym/OpAmps/LT1800.asy new file mode 100755 index 0000000..4b0dc4a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1800.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1800 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1800 +SYMATTR Description 80MHz, 25V/µs Low Power Rail-to-Rail Input and Output Precision Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1801.asy b/spice/copy/sym/OpAmps/LT1801.asy new file mode 100755 index 0000000..3892ec6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1801.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1801 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1800 +SYMATTR Description Dual 80MHz, 25V/µs Low Power Rail-to-Rail Input and Output Precision Op Amp(1 of 2) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1802.asy b/spice/copy/sym/OpAmps/LT1802.asy new file mode 100755 index 0000000..b3bca8e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1802.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1802 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1800 +SYMATTR Description Quad 80MHz, 25V/µs Low Power Rail-to-Rail Input and Output Precision Op Amp(1 of 4) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1803.asy b/spice/copy/sym/OpAmps/LT1803.asy new file mode 100755 index 0000000..f526564 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1803.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1803 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1803 +SYMATTR Description 100V/µs, 85MHz Rail-to-Rail Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1804.asy b/spice/copy/sym/OpAmps/LT1804.asy new file mode 100755 index 0000000..a3da59a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1804.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1804 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1803 +SYMATTR Description Dual 100V/µs, 85MHz Rail-to-Rail Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1805.asy b/spice/copy/sym/OpAmps/LT1805.asy new file mode 100755 index 0000000..b6b7ad8 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1805.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1805 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1803 +SYMATTR Description Quad 100V/µs, 85MHz Rail-to-Rail Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1806.asy b/spice/copy/sym/OpAmps/LT1806.asy new file mode 100755 index 0000000..4d5c938 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1806.asy @@ -0,0 +1,42 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 52 8 44 8 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1806 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1806 +SYMATTR Description 325MHz, Single Rail-to-Rail Input and Output, Low Distortion, Low Noise Precision Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1807.asy b/spice/copy/sym/OpAmps/LT1807.asy new file mode 100755 index 0000000..9a623a7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1807.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1807 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1807 +SYMATTR Description 325MHz, Dual Rail-to-Rail Input and Output, Low Distortion, Low Noise Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1809.asy b/spice/copy/sym/OpAmps/LT1809.asy new file mode 100755 index 0000000..00261ff --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1809.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1809 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1809 +SYMATTR Description Single 180MHz, 350V/µs, Rail-to-Rail Input and Output, Low Distortion, Low Noise Precision Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1810.asy b/spice/copy/sym/OpAmps/LT1810.asy new file mode 100755 index 0000000..d7c6ee3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1810.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1810 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1810 +SYMATTR Description Dual 180MHz, 350V/µs, Rail-to-Rail Input and Output, Low Distortion, Low Noise Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1812.asy b/spice/copy/sym/OpAmps/LT1812.asy new file mode 100755 index 0000000..f0cd0a2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1812.asy @@ -0,0 +1,42 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 52 8 44 8 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT1812 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1812 +SYMATTR Description 325MHz, Single Rail-to-Rail Input and Output, Low Distortion, Low Noise Precision Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT1813.asy b/spice/copy/sym/OpAmps/LT1813.asy new file mode 100755 index 0000000..11294b2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1813.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1813 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1813 +SYMATTR Description Dual 3mA, 100MHz, 750V/µs Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1814.asy b/spice/copy/sym/OpAmps/LT1814.asy new file mode 100755 index 0000000..e5a3a58 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1814.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1814 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1813 +SYMATTR Description Quad 3mA, 100MHz, 750V/µs Operational Amplifier(1 of 4) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1815.asy b/spice/copy/sym/OpAmps/LT1815.asy new file mode 100755 index 0000000..b1e4a62 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1815.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1815 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1815 +SYMATTR Description 220MHz, 1500V/µs Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1816.asy b/spice/copy/sym/OpAmps/LT1816.asy new file mode 100755 index 0000000..792ce0e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1816.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1816 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1815 +SYMATTR Description Dual 220MHz, 1500V/µs Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1817.asy b/spice/copy/sym/OpAmps/LT1817.asy new file mode 100755 index 0000000..29304e0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1817.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1817 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1815 +SYMATTR Description Quad 220MHz, 1500V/µs Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1818.asy b/spice/copy/sym/OpAmps/LT1818.asy new file mode 100755 index 0000000..6c8e8c4 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1818.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1818 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1818 +SYMATTR Description 400MHz, 2500V/µs, 9mA Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1819.asy b/spice/copy/sym/OpAmps/LT1819.asy new file mode 100755 index 0000000..66e0050 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1819.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1819 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT1818 +SYMATTR Description Dual 400MHz, 2500V/µs, 9mA Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1880.asy b/spice/copy/sym/OpAmps/LT1880.asy new file mode 100755 index 0000000..9615a74 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1880.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1880 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1880 +SYMATTR Description Rail-to-Rail Output pA Input Precision Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1881.asy b/spice/copy/sym/OpAmps/LT1881.asy new file mode 100755 index 0000000..bf060e3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1881.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1881 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1881 +SYMATTR Description Dual Rail-to-Rail Output pA Input Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1882.asy b/spice/copy/sym/OpAmps/LT1882.asy new file mode 100755 index 0000000..842dd9b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1882.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1882 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1881 +SYMATTR Description Quad Rail-to-Rail Output pA Input Precision Operational Amplifier(1 of 4) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1884.asy b/spice/copy/sym/OpAmps/LT1884.asy new file mode 100755 index 0000000..f4716ef --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1884.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1884 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1884 +SYMATTR Description Dual Rail-to-Rail Output pA Input Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1885.asy b/spice/copy/sym/OpAmps/LT1885.asy new file mode 100755 index 0000000..7d27f36 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1885.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT1885 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1884 +SYMATTR Description Quad Rail-to-Rail Output pA Input Precision Operational Amplifier(1 of 4) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1886.asy b/spice/copy/sym/OpAmps/LT1886.asy new file mode 100755 index 0000000..56e7eab --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1886.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1886 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1886 +SYMATTR Description Dual 700MHz, Av >= 10, 200mA Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT1920.asy b/spice/copy/sym/OpAmps/LT1920.asy new file mode 100755 index 0000000..9da73bb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1920.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1920 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1920 +SYMATTR Description Single Resistor Gain Programmable, Precision Instrumentation Amplifier +PIN -128 -96 LEFT 8 +PINATTR PinName Rg +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Rg +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1970.asy b/spice/copy/sym/OpAmps/LT1970.asy new file mode 100755 index 0000000..1ff1f7d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1970.asy @@ -0,0 +1,63 @@ +Version 4 +SymbolType CELL +LINE Normal 160 0 -80 -240 +LINE Normal -48 208 160 0 +LINE Normal -160 208 -160 -240 +LINE Normal -48 208 -160 208 +LINE Normal -80 -240 -160 -240 +TEXT -64 0 Center 2 LT +WINDOW 0 -64 -48 Center 2 +WINDOW 3 -64 48 Center 2 +SYMATTR Value LT1970 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1970 +SYMATTR Description 500mA Power Op Amp with Adjustable Precision Current Limit +PIN 0 160 RIGHT 12 +PINATTR PinName Vee +PINATTR SpiceOrder 1 +PIN 32 128 RIGHT 12 +PINATTR PinName V- +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 16 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 96 64 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 12 +PINATTR PinName Filter +PINATTR SpiceOrder 5 +PIN 64 96 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 6 +PIN -64 -224 RIGHT 12 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN -160 128 LEFT 12 +PINATTR PinName -IN +PINATTR SpiceOrder 8 +PIN -160 -160 LEFT 12 +PINATTR PinName +IN +PINATTR SpiceOrder 9 +PIN 0 -160 RIGHT 12 +PINATTR PinName VCsnk +PINATTR SpiceOrder 12 +PIN 32 -128 RIGHT 12 +PINATTR PinName VCsrc +PINATTR SpiceOrder 13 +PIN -32 192 RIGHT 12 +PINATTR PinName COM +PINATTR SpiceOrder 14 +PIN -160 -96 LEFT 8 +PINATTR PinName Enable +PINATTR SpiceOrder 15 +PIN 64 -96 RIGHT 16 +PINATTR PinName _Isrc +PINATTR SpiceOrder 16 +PIN 96 -64 RIGHT 16 +PINATTR PinName _Isnk +PINATTR SpiceOrder 17 +PIN -32 -192 RIGHT 12 +PINATTR PinName V+ +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/OpAmps/LT1990.asy b/spice/copy/sym/OpAmps/LT1990.asy new file mode 100755 index 0000000..aaaed12 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1990.asy @@ -0,0 +1,160 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 128 -48 112 +LINE Normal -32 32 -32 -32 +LINE Normal 32 0 -32 32 +LINE Normal -32 -32 32 0 +LINE Normal -32 -16 -106 -16 +LINE Normal -32 16 -106 16 +LINE Normal -80 -16 -80 80 +LINE Normal -48 16 -48 80 +LINE Normal -48 -80 -48 -16 +LINE Normal 6 -80 -48 -80 +LINE Normal 80 -80 38 -80 +LINE Normal 80 -59 80 -80 +LINE Normal 80 0 80 -27 +LINE Normal 32 0 80 0 +LINE Normal 120 -80 80 -80 +LINE Normal 176 -80 152 -80 +LINE Normal 176 0 80 0 +LINE Normal 6 48 -48 48 +LINE Normal 80 48 38 48 +LINE Normal 80 70 80 48 +LINE Normal 80 128 80 102 +LINE Normal 120 48 80 48 +LINE Normal 176 48 152 48 +LINE Normal 80 128 -80 128 +LINE Normal -80 160 -80 112 +LINE Normal -16 160 -16 24 +LINE Normal -16 -128 -16 -24 +LINE Normal -176 -16 -138 -16 +LINE Normal -176 16 -138 16 +LINE Normal -18 16 -26 16 +LINE Normal -22 20 -22 12 +LINE Normal -26 -16 -18 -16 +LINE Normal -32 -108 -35 -119 +LINE Normal -29 -119 -32 -108 +LINE Normal -21 -113 -27 -113 +LINE Normal -24 -110 -24 -116 +LINE Normal -33 154 -36 143 +LINE Normal -30 143 -33 154 +LINE Normal -22 149 -28 149 +LINE Normal -126 -8 -118 -24 +LINE Normal -126 -8 -134 -24 +LINE Normal -134 -24 -138 -16 +LINE Normal -110 -8 -118 -24 +LINE Normal -106 -16 -110 -8 +LINE Normal -126 24 -118 8 +LINE Normal -126 24 -134 8 +LINE Normal -134 8 -138 16 +LINE Normal -110 24 -118 8 +LINE Normal -106 16 -110 24 +LINE Normal -56 92 -40 100 +LINE Normal -56 92 -40 84 +LINE Normal -40 84 -48 80 +LINE Normal -56 108 -40 100 +LINE Normal -48 112 -56 108 +LINE Normal -88 92 -72 100 +LINE Normal -88 92 -72 84 +LINE Normal -72 84 -80 80 +LINE Normal -88 108 -72 100 +LINE Normal -80 112 -88 108 +LINE Normal 18 56 26 40 +LINE Normal 18 56 10 40 +LINE Normal 10 40 6 48 +LINE Normal 34 56 26 40 +LINE Normal 38 48 34 56 +LINE Normal 72 82 88 90 +LINE Normal 72 82 88 74 +LINE Normal 88 74 80 70 +LINE Normal 72 98 88 90 +LINE Normal 80 102 72 98 +LINE Normal 72 -47 88 -39 +LINE Normal 72 -47 88 -55 +LINE Normal 88 -55 80 -59 +LINE Normal 72 -31 88 -39 +LINE Normal 80 -27 72 -31 +LINE Normal 18 -72 26 -88 +LINE Normal 18 -72 10 -88 +LINE Normal 10 -88 6 -80 +LINE Normal 34 -72 26 -88 +LINE Normal 38 -80 34 -72 +LINE Normal 132 -72 140 -88 +LINE Normal 132 -72 124 -88 +LINE Normal 124 -88 120 -80 +LINE Normal 148 -72 140 -88 +LINE Normal 152 -80 148 -72 +LINE Normal 132 56 140 40 +LINE Normal 132 56 124 40 +LINE Normal 124 40 120 48 +LINE Normal 148 56 140 40 +LINE Normal 152 48 148 56 +RECTANGLE Normal 176 160 -176 -128 +CIRCLE Normal -79 -15 -81 -17 +CIRCLE Normal -78 -14 -82 -18 +CIRCLE Normal -77 -13 -83 -19 +CIRCLE Normal -47 -15 -49 -17 +CIRCLE Normal -46 -14 -50 -18 +CIRCLE Normal -45 -13 -51 -19 +CIRCLE Normal -47 17 -49 15 +CIRCLE Normal -46 18 -50 14 +CIRCLE Normal -45 19 -51 13 +CIRCLE Normal -47 49 -49 47 +CIRCLE Normal -46 50 -50 46 +CIRCLE Normal -45 51 -51 45 +CIRCLE Normal -47 129 -49 127 +CIRCLE Normal -46 130 -50 126 +CIRCLE Normal -45 131 -51 125 +CIRCLE Normal -79 129 -81 127 +CIRCLE Normal -78 130 -82 126 +CIRCLE Normal -77 131 -83 125 +CIRCLE Normal 81 1 79 -1 +CIRCLE Normal 82 2 78 -2 +CIRCLE Normal 83 3 77 -3 +CIRCLE Normal 81 49 79 47 +CIRCLE Normal 82 50 78 46 +CIRCLE Normal 83 51 77 45 +CIRCLE Normal 81 -79 79 -81 +CIRCLE Normal 82 -78 78 -82 +CIRCLE Normal 83 -77 77 -83 +TEXT -120 -24 Bottom 2 1Meg +TEXT -123 24 Top 2 1Meg +TEXT -93 97 Right 2 40k +TEXT -31 97 Left 2 40k +TEXT 24 54 Top 2 900k +TEXT 136 -87 Bottom 2 10k +TEXT 90 86 Left 2 100k +TEXT 136 43 Bottom 2 10k +TEXT 90 -42 Left 2 100k +TEXT 24 -86 Bottom 2 900k +WINDOW 3 0 176 Left 2 +WINDOW 0 0 -144 Left 2 +SYMATTR Value LT1990 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1990 +SYMATTR Description ±250V Input Range G=1,10 µPower Difference Amplifier +PIN -80 160 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN -176 -16 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -176 16 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -16 160 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 176 48 NONE 8 +PINATTR PinName GAIN2 +PINATTR SpiceOrder 5 +PIN 176 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN -16 -128 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 7 +PIN 176 -80 NONE 8 +PINATTR PinName GAIN1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1991.asy b/spice/copy/sym/OpAmps/LT1991.asy new file mode 100755 index 0000000..9b85be6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1991.asy @@ -0,0 +1,140 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -27 16 -19 16 +LINE Normal -23 20 -23 12 +LINE Normal 0 -128 0 -16 +LINE Normal 0 128 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +LINE Normal -108 -62 -112 -56 +LINE Normal -80 -56 -84 -50 +LINE Normal -84 -50 -92 -62 +LINE Normal -100 -50 -92 -62 +LINE Normal -100 -50 -108 -62 +LINE Normal -92 -102 -96 -96 +LINE Normal -64 -96 -68 -90 +LINE Normal -68 -90 -76 -102 +LINE Normal -84 -90 -76 -102 +LINE Normal -84 -90 -92 -102 +LINE Normal -124 -22 -128 -16 +LINE Normal -96 -16 -100 -10 +LINE Normal -100 -10 -108 -22 +LINE Normal -116 -10 -108 -22 +LINE Normal -116 -10 -124 -22 +LINE Normal -124 10 -128 16 +LINE Normal -96 16 -100 22 +LINE Normal -100 22 -108 10 +LINE Normal -116 22 -108 10 +LINE Normal -116 22 -124 10 +LINE Normal -108 50 -112 56 +LINE Normal -80 56 -84 62 +LINE Normal -84 62 -92 50 +LINE Normal -100 62 -92 50 +LINE Normal -100 62 -108 50 +LINE Normal -92 90 -96 96 +LINE Normal -64 96 -68 102 +LINE Normal -68 102 -76 90 +LINE Normal -84 102 -76 90 +LINE Normal -84 102 -92 90 +LINE Normal -96 16 -32 16 +LINE Normal -58 96 -64 96 +LINE Normal -58 16 -58 96 +LINE Normal -96 -16 -32 -16 +LINE Normal -58 -96 -58 -16 +LINE Normal -58 -96 -64 -96 +LINE Normal 31 -62 27 -56 +LINE Normal 59 -56 55 -50 +LINE Normal 55 -50 47 -62 +LINE Normal 39 -50 47 -62 +LINE Normal 39 -50 31 -62 +LINE Normal 27 -56 -80 -56 +LINE Normal 80 -56 59 -56 +LINE Normal 80 128 80 56 +LINE Normal 32 0 80 0 +LINE Normal 33 56 -80 56 +LINE Normal 37 50 33 56 +LINE Normal 65 56 61 62 +LINE Normal 61 62 53 50 +LINE Normal 45 62 53 50 +LINE Normal 45 62 37 50 +LINE Normal 80 56 65 56 +LINE Normal -96 -96 -112 -96 +LINE Normal -112 -96 -112 -128 +LINE Normal -144 -56 -112 -56 +LINE Normal -144 -128 -144 -56 +LINE Normal -176 -128 -176 -16 +LINE Normal -176 -16 -128 -16 +LINE Normal -176 16 -128 16 +LINE Normal -176 16 -176 128 +LINE Normal -144 56 -144 128 +LINE Normal -112 128 -112 96 +LINE Normal -144 56 -112 56 +LINE Normal -96 96 -112 96 +LINE Normal 80 -128 80 0 +RECTANGLE Normal 96 128 -192 -128 +CIRCLE Normal -57 17 -59 15 +CIRCLE Normal -56 18 -60 14 +CIRCLE Normal -55 19 -61 13 +CIRCLE Normal -57 -15 -59 -17 +CIRCLE Normal -56 -14 -60 -18 +CIRCLE Normal -55 -13 -61 -19 +CIRCLE Normal -57 -55 -59 -57 +CIRCLE Normal -56 -54 -60 -58 +CIRCLE Normal -55 -53 -61 -59 +CIRCLE Normal -57 57 -59 55 +CIRCLE Normal -56 58 -60 54 +CIRCLE Normal -55 59 -61 53 +CIRCLE Normal 81 -55 79 -57 +CIRCLE Normal 82 -54 78 -58 +CIRCLE Normal 83 -53 77 -59 +TEXT -81 -98 Bottom 2 50K +TEXT -97 -61 Bottom 2 150K +TEXT -112 -18 Bottom 2 450K +TEXT -112 18 Top 2 450K +TEXT -96 59 Top 2 150K +TEXT -78 99 Top 2 50K +TEXT 43 -59 Bottom 2 450K +TEXT 47 55 Bottom 2 450K +TEXT 40 93 Center 2 LT +WINDOW 0 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-33 1 -33 6 +LINE Normal -31 4 -33 1 +LINE Normal -29 1 -31 4 +LINE Normal -29 6 -29 1 +LINE Normal 6 22 -6 22 +CIRCLE Normal 55 39 41 25 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LT1994 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1994 +SYMATTR Description Low Noise, Low Distortion Fully Differential I/O Amplifier/Driver +PIN -64 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -64 0 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN 0 80 NONE 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 +PIN -64 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1995.asy b/spice/copy/sym/OpAmps/LT1995.asy new file mode 100755 index 0000000..5570b9b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1995.asy @@ -0,0 +1,140 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -27 16 -19 16 +LINE Normal -23 20 -23 12 +LINE Normal 0 -128 0 -16 +LINE Normal 0 128 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +LINE Normal -108 -62 -112 -56 +LINE Normal -80 -56 -84 -50 +LINE Normal -84 -50 -92 -62 +LINE Normal -100 -50 -92 -62 +LINE Normal -100 -50 -108 -62 +LINE Normal -92 -102 -96 -96 +LINE Normal -64 -96 -68 -90 +LINE Normal -68 -90 -76 -102 +LINE Normal -84 -90 -76 -102 +LINE Normal -84 -90 -92 -102 +LINE Normal -124 -22 -128 -16 +LINE Normal -96 -16 -100 -10 +LINE Normal -100 -10 -108 -22 +LINE Normal -116 -10 -108 -22 +LINE Normal -116 -10 -124 -22 +LINE Normal -124 10 -128 16 +LINE Normal -96 16 -100 22 +LINE Normal -100 22 -108 10 +LINE Normal -116 22 -108 10 +LINE Normal -116 22 -124 10 +LINE Normal -108 50 -112 56 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LT1995 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LT1995 +SYMATTR Description 30MHz, 1000V/µs Gain Selectable Amplifier +PIN -176 128 NONE 0 +PINATTR PinName P1 +PINATTR SpiceOrder 1 +PIN -144 128 NONE 0 +PINATTR PinName P2 +PINATTR SpiceOrder 2 +PIN -112 128 NONE 0 +PINATTR PinName P4 +PINATTR SpiceOrder 3 +PIN 0 128 NONE 0 +PINATTR PinName Vee +PINATTR SpiceOrder 4 +PIN 80 128 NONE 0 +PINATTR PinName Ref +PINATTR SpiceOrder 5 +PIN 80 -128 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 0 -128 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 7 +PIN -112 -128 NONE 0 +PINATTR PinName M4 +PINATTR SpiceOrder 8 +PIN -144 -128 NONE 0 +PINATTR PinName M2 +PINATTR SpiceOrder 9 +PIN -176 -128 NONE 0 +PINATTR PinName M1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LT1996.asy b/spice/copy/sym/OpAmps/LT1996.asy new file mode 100755 index 0000000..5243dbb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1996.asy @@ -0,0 +1,140 @@ +Version 4 +SymbolType CELL +LINE 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+SYMATTR Description Precision, 100µA Gain Selectable Amplifier +PIN -176 128 NONE 0 +PINATTR PinName P9 +PINATTR SpiceOrder 1 +PIN -144 128 NONE 0 +PINATTR PinName P27 +PINATTR SpiceOrder 2 +PIN -112 128 NONE 0 +PINATTR PinName P81 +PINATTR SpiceOrder 3 +PIN 0 128 NONE 0 +PINATTR PinName Vee +PINATTR SpiceOrder 4 +PIN 80 128 NONE 0 +PINATTR PinName Ref +PINATTR SpiceOrder 5 +PIN 80 -128 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 0 -128 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 7 +PIN -112 -128 NONE 0 +PINATTR PinName M81 +PINATTR SpiceOrder 8 +PIN -144 -128 NONE 0 +PINATTR PinName M27 +PINATTR SpiceOrder 9 +PIN -176 -128 NONE 0 +PINATTR PinName M9 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LT1997-1.asy b/spice/copy/sym/OpAmps/LT1997-1.asy new file mode 100755 index 0000000..526698d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1997-1.asy @@ -0,0 +1,169 @@ +Version 4 +SymbolType CELL +LINE Normal 96 -32 160 0 +LINE Normal 96 32 160 0 +LINE Normal 96 -32 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8 +PINATTR PinName OUT +PINATTR SpiceOrder 9 +PIN 80 128 BOTTOM 4 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 +PIN 128 -128 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 11 +PIN -48 -128 NONE 0 +PINATTR PinName -INC +PINATTR SpiceOrder 12 +PIN -128 -128 NONE 0 +PINATTR PinName -INB +PINATTR SpiceOrder 14 +PIN -224 -128 NONE 0 +PINATTR PinName -INA +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/OpAmps/LT1997-2.asy b/spice/copy/sym/OpAmps/LT1997-2.asy new file mode 100755 index 0000000..da8ce5d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1997-2.asy @@ -0,0 +1,166 @@ +Version 4 +SymbolType CELL +LINE Normal 96 -32 160 0 +LINE Normal 96 32 160 0 +LINE Normal 96 -32 96 32 +LINE Normal 100 -16 108 -16 +LINE Normal 101 16 109 16 +LINE Normal 105 20 105 12 +LINE Normal 128 -128 128 -16 +LINE Normal 128 128 128 16 +LINE Normal 132 -20 140 -20 +LINE Normal 136 -24 136 -16 +LINE Normal 132 20 140 20 +LINE Normal -188 20 -192 26 +LINE Normal -160 26 -164 32 +LINE Normal -164 32 -172 20 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193 128 Top 2 +SYMATTR Value LT1997-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LT1997-2 +SYMATTR Description Precision, Wide Voltage Range Gain Selectable Funnel Amplifier +PIN -224 128 NONE 0 +PINATTR PinName +INA +PINATTR SpiceOrder 1 +PIN -128 128 NONE 0 +PINATTR PinName +INB +PINATTR SpiceOrder 3 +PIN -48 128 NONE 0 +PINATTR PinName +INC +PINATTR SpiceOrder 5 +PIN 224 80 NONE 8 +PINATTR PinName REF1 +PINATTR SpiceOrder 6 +PIN 224 48 NONE 8 +PINATTR PinName REF2 +PINATTR SpiceOrder 7 +PIN 128 128 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 8 +PIN 224 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 9 +PIN 80 128 BOTTOM 4 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 +PIN 128 -128 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 11 +PIN -48 -128 NONE 0 +PINATTR PinName -INC +PINATTR SpiceOrder 12 +PIN -128 -128 NONE 0 +PINATTR PinName -INB +PINATTR SpiceOrder 14 +PIN -224 -128 NONE 0 +PINATTR PinName -INA +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/OpAmps/LT1997-3.asy b/spice/copy/sym/OpAmps/LT1997-3.asy new file mode 100755 index 0000000..bc08f16 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1997-3.asy @@ -0,0 +1,166 @@ +Version 4 +SymbolType CELL +LINE Normal 96 -32 160 0 +LINE Normal 96 32 160 0 +LINE Normal 96 -32 96 32 +LINE Normal 100 -16 108 -16 +LINE Normal 101 16 109 16 +LINE Normal 105 20 105 12 +LINE Normal 128 -128 128 -16 +LINE Normal 128 128 128 16 +LINE Normal 132 -20 140 -20 +LINE Normal 136 -24 136 -16 +LINE Normal 132 20 140 20 +LINE Normal -188 20 -192 26 +LINE Normal -160 26 -164 32 +LINE Normal -164 32 -172 20 +LINE Normal -180 32 -172 20 +LINE Normal -180 32 -188 20 +LINE Normal 72 -64 72 -16 +LINE Normal 149 -70 145 -64 +LINE Normal 177 -64 173 -58 +LINE Normal 173 -58 165 -70 +LINE Normal 157 -58 165 -70 +LINE Normal 157 -58 149 -70 +LINE Normal 145 -64 72 -64 +LINE Normal 208 -64 177 -64 +LINE Normal 160 0 224 0 +LINE Normal 150 48 71 48 +LINE Normal 224 48 182 48 +LINE Normal -224 26 -192 26 +LINE Normal 208 -64 208 0 +LINE Normal 150 80 71 80 +LINE Normal 71 80 71 48 +LINE Normal 154 42 150 48 +LINE Normal 182 48 178 54 +LINE Normal 178 54 170 42 +LINE Normal 162 54 170 42 +LINE Normal 162 54 154 42 +LINE Normal 154 74 150 80 +LINE Normal 182 80 178 86 +LINE Normal 178 86 170 74 +LINE Normal 162 86 170 74 +LINE Normal 162 86 154 74 +LINE Normal 224 80 182 80 +LINE Normal -224 26 -224 128 +LINE Normal -92 52 -96 58 +LINE Normal -64 58 -68 64 +LINE Normal -68 64 -76 52 +LINE Normal -84 64 -76 52 +LINE Normal -84 64 -92 52 +LINE Normal -12 84 -16 90 +LINE Normal 16 90 12 96 +LINE Normal 12 96 4 84 +LINE Normal -4 96 4 84 +LINE Normal -4 96 -12 84 +LINE Normal 48 90 48 26 +LINE Normal 16 90 48 90 +LINE Normal -64 58 48 58 +LINE Normal -128 58 -96 58 +LINE Normal -128 128 -128 58 +LINE Normal -48 90 -16 90 +LINE Normal -48 128 -48 90 +LINE Normal -188 -32 -192 -26 +LINE Normal -160 -26 -164 -20 +LINE Normal -164 -20 -172 -32 +LINE Normal -180 -20 -172 -32 +LINE Normal -180 -20 -188 -32 +LINE Normal -224 -26 -192 -26 +LINE Normal -224 -128 -224 -26 +LINE Normal -128 -58 -128 -128 +LINE Normal -128 -58 -96 -58 +LINE Normal -92 -64 -96 -58 +LINE Normal -64 -58 -68 -52 +LINE Normal -68 -52 -76 -64 +LINE Normal -84 -52 -76 -64 +LINE Normal -84 -52 -92 -64 +LINE Normal -64 -58 48 -58 +LINE Normal -12 -96 -16 -90 +LINE Normal 16 -90 12 -84 +LINE Normal 12 -84 4 -96 +LINE Normal -4 -84 4 -96 +LINE Normal -4 -84 -12 -96 +LINE Normal 16 -90 48 -90 +LINE Normal -48 -90 -16 -90 +LINE Normal -48 -90 -48 -128 +LINE Normal 72 -26 -160 -26 +LINE Normal 71 26 -160 26 +LINE Normal 71 16 96 16 +LINE Normal 71 48 71 16 +LINE Normal 48 -26 48 -90 +LINE Normal 96 -16 72 -16 +RECTANGLE Normal 224 128 -256 -128 +CIRCLE Normal 209 1 207 -1 +CIRCLE Normal 210 2 206 -2 +CIRCLE Normal 211 3 205 -3 +CIRCLE Normal 49 27 47 25 +CIRCLE Normal 50 28 46 24 +CIRCLE Normal 51 29 45 23 +CIRCLE Normal 72 27 70 25 +CIRCLE Normal 73 28 69 24 +CIRCLE Normal 74 29 68 23 +CIRCLE Normal 73 -25 71 -27 +CIRCLE Normal 74 -24 70 -28 +CIRCLE Normal 75 -23 69 -29 +CIRCLE Normal 49 -25 47 -27 +CIRCLE Normal 50 -24 46 -28 +CIRCLE Normal 51 -23 45 -29 +CIRCLE Normal 49 -57 47 -59 +CIRCLE Normal 50 -56 46 -60 +CIRCLE Normal 51 -55 45 -61 +CIRCLE Normal 49 59 47 57 +CIRCLE Normal 50 60 46 56 +CIRCLE Normal 51 61 45 55 +TEXT -172 32 Top 2 22.5K +TEXT 165 -70 Bottom 2 22.5K +TEXT 0 0 Center 2 LT +TEXT 170 42 Bottom 2 45K +TEXT 170 86 Top 2 45K +TEXT -76 64 Top 2 7.5K +TEXT 4 96 Top 2 2.5K +TEXT -172 -32 Bottom 2 22.5K +TEXT -76 -64 Bottom 2 7.5K +TEXT 4 -96 Bottom 2 2.5K +WINDOW 0 192 -128 Bottom 2 +WINDOW 3 193 128 Top 2 +SYMATTR Value LT1997-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LT1997-3 +SYMATTR Description Precision, Wide Voltage Range Gain Selectable Amplifier +PIN -224 128 NONE 0 +PINATTR PinName +INA +PINATTR SpiceOrder 1 +PIN -128 128 NONE 0 +PINATTR PinName +INB +PINATTR SpiceOrder 3 +PIN -48 128 NONE 0 +PINATTR PinName +INC +PINATTR SpiceOrder 5 +PIN 224 80 NONE 8 +PINATTR PinName REF1 +PINATTR SpiceOrder 6 +PIN 224 48 NONE 8 +PINATTR PinName REF2 +PINATTR SpiceOrder 7 +PIN 128 128 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 8 +PIN 224 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 9 +PIN 80 128 BOTTOM 4 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 +PIN 128 -128 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 11 +PIN -48 -128 NONE 0 +PINATTR PinName -INC +PINATTR SpiceOrder 12 +PIN -128 -128 NONE 0 +PINATTR PinName -INB +PINATTR SpiceOrder 14 +PIN -224 -128 NONE 0 +PINATTR PinName -INA +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/OpAmps/LT1999-10.asy b/spice/copy/sym/OpAmps/LT1999-10.asy new file mode 100755 index 0000000..f0eda65 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1999-10.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 48 Center 2 +SYMATTR Value LT1999-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LT1999-x Gain=10 +SYMATTR Description High Voltage, Bidirectional Current Sense Amplifier +PIN 0 -128 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 -80 LEFT 8 +PINATTR PinName +IN +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName -IN +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 112 80 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN 112 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 112 -80 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1999-20.asy b/spice/copy/sym/OpAmps/LT1999-20.asy new file mode 100755 index 0000000..d37cfcb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1999-20.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 48 Center 2 +SYMATTR Value LT1999-20 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LT1999-x Gain=20 +SYMATTR Description High Voltage, Bidirectional Current Sense Amplifier +PIN 0 -128 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 -80 LEFT 8 +PINATTR PinName +IN +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName -IN +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 112 80 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN 112 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 112 -80 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT1999-50.asy b/spice/copy/sym/OpAmps/LT1999-50.asy new file mode 100755 index 0000000..6a0b197 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT1999-50.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 48 Center 2 +SYMATTR Value LT1999-50 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LT1999-x Gain=50 +SYMATTR Description High Voltage, Bidirectional Current Sense Amplifier +PIN 0 -128 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 -80 LEFT 8 +PINATTR PinName +IN +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName -IN +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 112 80 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN 112 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 112 -80 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT2078.asy b/spice/copy/sym/OpAmps/LT2078.asy new file mode 100755 index 0000000..21176d2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT2078.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT2078 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description Dual µPower, Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT2078A.asy b/spice/copy/sym/OpAmps/LT2078A.asy new file mode 100755 index 0000000..b66d7ba --- /dev/null +++ b/spice/copy/sym/OpAmps/LT2078A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT2078A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description Dual µPower, Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT2079.asy b/spice/copy/sym/OpAmps/LT2079.asy new file mode 100755 index 0000000..5ac8cf1 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT2079.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT2079 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description Quad µPower, Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT2079A.asy b/spice/copy/sym/OpAmps/LT2079A.asy new file mode 100755 index 0000000..ea66b32 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT2079A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT2079A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1078 +SYMATTR Description Quad µPower, Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT2178.asy b/spice/copy/sym/OpAmps/LT2178.asy new file mode 100755 index 0000000..a6d4142 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT2178.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT2178 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1178 +SYMATTR Description Quad 17mA Max, Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT2178A.asy b/spice/copy/sym/OpAmps/LT2178A.asy new file mode 100755 index 0000000..fcd4500 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT2178A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT2178A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1178 +SYMATTR Description Quad 17mA Max, Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT2179.asy b/spice/copy/sym/OpAmps/LT2179.asy new file mode 100755 index 0000000..7cd44b7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT2179.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT2179 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1178 +SYMATTR Description Quad 17mA Max, Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT2179A.asy b/spice/copy/sym/OpAmps/LT2179A.asy new file mode 100755 index 0000000..fd4add2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT2179A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT2179A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1178 +SYMATTR Description Quad 17mA Max, Single Supply Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT318A.asy b/spice/copy/sym/OpAmps/LT318A.asy new file mode 100755 index 0000000..ddb4e87 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT318A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT318A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT118A +SYMATTR Description High Speed Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6000.asy b/spice/copy/sym/OpAmps/LT6000.asy new file mode 100755 index 0000000..c6bf189 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6000.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -48 64 0 +LINE Normal -16 48 64 0 +LINE Normal -16 -48 -16 48 +LINE Normal 0 48 0 38 +LINE Normal 0 -48 0 -38 +LINE Normal 32 48 32 19 +LINE Normal 36 15 28 15 +LINE Normal 36 15 36 7 +LINE Normal 28 7 36 7 +LINE Normal 28 7 28 -1 +LINE Normal 36 -1 28 -1 +LINE Normal -8 -16 0 -16 +LINE Normal -8 16 0 16 +LINE Normal -4 12 -4 20 +LINE Normal 4 -40 12 -40 +LINE Normal 8 -36 8 -44 +LINE Normal 4 40 12 40 +LINE Normal 37 -5 27 -5 +WINDOW 0 33 -33 Left 2 +WINDOW 3 40 30 Left 2 +SYMATTR Value LT6000 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6000 +SYMATTR Description 1.8V, 13µA Precision Rail-to-Rail Op Amp +PIN -16 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -16 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 32 48 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6001.asy b/spice/copy/sym/OpAmps/LT6001.asy new file mode 100755 index 0000000..a647960 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6001.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -16 -48 64 0 +LINE Normal -16 48 64 0 +LINE Normal -16 -48 -16 48 +LINE Normal 0 48 0 38 +LINE Normal 0 -48 0 -38 +LINE Normal 32 48 32 19 +LINE Normal 36 15 28 15 +LINE Normal 36 15 36 7 +LINE Normal 28 7 36 7 +LINE Normal 28 7 28 -1 +LINE Normal 36 -1 28 -1 +LINE Normal -8 -16 0 -16 +LINE Normal -8 16 0 16 +LINE Normal -4 12 -4 20 +LINE Normal 4 -40 12 -40 +LINE Normal 8 -36 8 -44 +LINE Normal 4 40 12 40 +LINE Normal 37 -5 27 -5 +WINDOW 0 33 -33 Left 2 +WINDOW 3 40 30 Left 2 +SYMATTR Value LT6001 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6000 +SYMATTR Description Dual 1.8V, 13µA Precision Rail-to-Rail Op Amp +PIN -16 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -16 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 32 48 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6002.asy b/spice/copy/sym/OpAmps/LT6002.asy new file mode 100755 index 0000000..feab637 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6002.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6002 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6002 +SYMATTR Description Quad 1.8V, 13µA Precision Rail-to-Rail Op Amps +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6003.asy b/spice/copy/sym/OpAmps/LT6003.asy new file mode 100755 index 0000000..f6cb03e --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6003.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6003 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6003 +SYMATTR Description 1.6V, 1µA Precision Rail-to-Rail Input and Output Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6004.asy b/spice/copy/sym/OpAmps/LT6004.asy new file mode 100755 index 0000000..b0d652f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6004.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6004 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6003 +SYMATTR Description Dual 1.6V, 1µA Precision Rail-to-Rail Input and Output Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6005.asy b/spice/copy/sym/OpAmps/LT6005.asy new file mode 100755 index 0000000..6cd2612 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6005.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6005 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6003 +SYMATTR Description Quad 1.6V, 1µA Precision Rail-to-Rail Input and Output Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6010.asy b/spice/copy/sym/OpAmps/LT6010.asy new file mode 100755 index 0000000..a0ea523 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6010.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6010 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6010 +SYMATTR Description 135µA, 14nV/rtHz, Rail-to-Rail Precision Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6011.asy b/spice/copy/sym/OpAmps/LT6011.asy new file mode 100755 index 0000000..f5eb0e1 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6011.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6011 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6011 +SYMATTR Description Dual 135µA, 14nV/rtHz, Rail-to-Rail Precision Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6012.asy b/spice/copy/sym/OpAmps/LT6012.asy new file mode 100755 index 0000000..5a55592 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6012.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6012 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6011 +SYMATTR Description Quad 135µA, 14nV/rtHz, Rail-to-Rail Precision Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6013.asy b/spice/copy/sym/OpAmps/LT6013.asy new file mode 100755 index 0000000..17232ac --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6013.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6013 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6013 +SYMATTR Description 145µA, 9.5nV/rtHz, Av > 5, Rail-to-Rail Precision Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6014.asy b/spice/copy/sym/OpAmps/LT6014.asy new file mode 100755 index 0000000..5b33416 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6014.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6014 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6013 +SYMATTR Description Dual 145µA, 9.5nV/rtHz, Av > 5, Rail-to-Rail Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6015.asy b/spice/copy/sym/OpAmps/LT6015.asy new file mode 100755 index 0000000..1fb220f --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6015.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6015 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6016 +SYMATTR Description 3.2MHz, 0.8 V/µs Low Power, Over-The-Top Precision Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6016.asy b/spice/copy/sym/OpAmps/LT6016.asy new file mode 100755 index 0000000..3b5c696 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6016.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6016 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6016 +SYMATTR Description 3.2MHz, 0.8 V/µs Low Power, Over-The-Top Precision Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6017.asy b/spice/copy/sym/OpAmps/LT6017.asy new file mode 100755 index 0000000..8b73d38 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6017.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6017 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6016 +SYMATTR Description 3.2MHz, 0.8 V/µs Low Power, Over-The-Top Precision Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6018.asy b/spice/copy/sym/OpAmps/LT6018.asy new file mode 100755 index 0000000..cb67b28 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6018.asy @@ -0,0 +1,75 @@ +Version 4 +SymbolType CELL +LINE Normal -48 -64 64 0 +LINE Normal -48 64 64 0 +LINE Normal -48 -64 -48 64 +LINE Normal -32 64 -32 55 +LINE Normal -32 -64 -32 -55 +LINE Normal 0 48 0 37 +LINE Normal -41 -16 -33 -16 +LINE Normal -41 16 -33 16 +LINE Normal -37 12 -37 20 +LINE Normal -36 -43 -28 -43 +LINE Normal -32 -39 -32 -47 +LINE Normal -36 44 -28 44 +LINE Normal -12 -20 -4 -20 +LINE Normal -12 -20 -12 -26 +LINE Normal -4 -26 -12 -26 +LINE Normal -12 -14 -12 -20 +LINE Normal -12 -14 -4 -14 +LINE Normal 2 -14 2 -26 +LINE Normal 10 -14 10 -26 +LINE Normal 10 -14 2 -26 +LINE Normal 0 -48 0 -37 +LINE Normal -21 15 -21 9 +LINE Normal -16 9 -21 9 +LINE Normal -21 21 -21 15 +LINE Normal -21 21 -16 21 +LINE Normal -13 12 -16 9 +LINE Normal -16 21 -13 18 +LINE Normal -13 18 -13 12 +LINE Normal -6 9 -1 9 +LINE Normal -1 21 -6 21 +LINE Normal -9 12 -6 9 +LINE Normal -6 21 -9 18 +LINE Normal -9 18 -9 12 +LINE Normal -1 16 -1 21 +LINE Normal -4 16 -1 16 +LINE Normal 3 21 3 9 +LINE Normal 11 21 11 9 +LINE Normal 11 21 3 9 +LINE Normal 15 15 15 9 +LINE Normal 20 9 15 9 +LINE Normal 15 21 15 15 +LINE Normal 15 21 20 21 +LINE Normal 23 12 20 9 +LINE Normal 20 21 23 18 +LINE Normal 23 18 23 12 +WINDOW 0 32 -32 Left 2 +WINDOW 3 32 32 Left 2 +SYMATTR Value LT6018 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT6018 +SYMATTR Description 36V, Ultralow Noise, Precision Op Amp +PIN -48 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -48 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -32 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -32 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 0 -48 NONE 20 +PINATTR PinName EN +PINATTR SpiceOrder 6 +PIN 0 48 NONE 20 +PINATTR PinName DGND +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LT6020-1.asy b/spice/copy/sym/OpAmps/LT6020-1.asy new file mode 100755 index 0000000..ff8b471 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6020-1.asy @@ -0,0 +1,75 @@ +Version 4 +SymbolType CELL +LINE Normal -48 -64 64 0 +LINE Normal -48 64 64 0 +LINE Normal -48 -64 -48 64 +LINE Normal -32 64 -32 55 +LINE Normal -32 -64 -32 -55 +LINE Normal 0 48 0 37 +LINE Normal -41 -16 -33 -16 +LINE Normal -41 16 -33 16 +LINE Normal -37 12 -37 20 +LINE Normal -36 -43 -28 -43 +LINE Normal -32 -39 -32 -47 +LINE Normal -36 44 -28 44 +LINE Normal -12 -20 -4 -20 +LINE Normal -12 -20 -12 -26 +LINE Normal -4 -26 -12 -26 +LINE Normal -12 -14 -12 -20 +LINE Normal -12 -14 -4 -14 +LINE Normal 2 -14 2 -26 +LINE Normal 10 -14 10 -26 +LINE Normal 10 -14 2 -26 +LINE Normal 0 -48 0 -37 +LINE Normal -21 15 -21 9 +LINE Normal -16 9 -21 9 +LINE Normal -21 21 -21 15 +LINE Normal -21 21 -16 21 +LINE Normal -13 12 -16 9 +LINE Normal -16 21 -13 18 +LINE Normal -13 18 -13 12 +LINE Normal -6 9 -1 9 +LINE Normal -1 21 -6 21 +LINE Normal -9 12 -6 9 +LINE Normal -6 21 -9 18 +LINE Normal -9 18 -9 12 +LINE Normal -1 16 -1 21 +LINE Normal -4 16 -1 16 +LINE Normal 3 21 3 9 +LINE Normal 11 21 11 9 +LINE Normal 11 21 3 9 +LINE Normal 15 15 15 9 +LINE Normal 20 9 15 9 +LINE Normal 15 21 15 15 +LINE Normal 15 21 20 21 +LINE Normal 23 12 20 9 +LINE Normal 20 21 23 18 +LINE Normal 23 18 23 12 +WINDOW 0 32 -32 Left 2 +WINDOW 3 32 32 Left 2 +SYMATTR Value LT6020-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT6020-1 +SYMATTR Description Dual µPower, 5V/µs Precision Rail-to-Rail Output Amplifier +PIN -48 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -48 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -32 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -32 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 0 -48 NONE 20 +PINATTR PinName EN +PINATTR SpiceOrder 6 +PIN 0 48 NONE 20 +PINATTR PinName DGND +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LT6020.asy b/spice/copy/sym/OpAmps/LT6020.asy new file mode 100755 index 0000000..fd90f0a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6020.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -48 -48 48 0 +LINE Normal -48 48 48 0 +LINE Normal -48 -48 -48 48 +LINE Normal -16 48 -16 32 +LINE Normal -16 -48 -16 -32 +LINE Normal -41 -16 -33 -16 +LINE Normal -41 16 -33 16 +LINE Normal -37 12 -37 20 +LINE Normal -20 -21 -12 -21 +LINE Normal -16 -17 -16 -25 +LINE Normal -20 22 -12 22 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6020 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT6020 +SYMATTR Description Dual µPower, 5V/µs Precision Rail-to-Rail Output Amplifier +PIN -48 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -48 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -16 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6100.asy b/spice/copy/sym/OpAmps/LT6100.asy new file mode 100755 index 0000000..6da85e3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6100.asy @@ -0,0 +1,138 @@ +Version 4 +SymbolType BLOCK +LINE Normal -67 -16 -67 -48 +LINE Normal -35 -32 -67 -16 +LINE Normal -67 -48 -35 -32 +LINE Normal -24 -24 -24 -40 +LINE Normal -16 -40 -24 -35 +LINE Normal -16 -24 -24 -29 +LINE Normal -17 -27 -16 -24 +LINE Normal -18 -23 -16 -24 +LINE Normal -24 -32 -35 -32 +LINE Normal -16 -64 -16 -40 +LINE Normal -76 -64 -16 -64 +LINE Normal -76 -40 -76 -64 +LINE Normal -67 -40 -76 -40 +LINE Normal -76 -25 -67 -25 +LINE Normal -76 0 -76 -25 +LINE Normal -93 0 -76 0 +LINE Normal -93 -64 -76 -64 +LINE Normal -107 -72 -109 -64 +LINE Normal -103 -57 -107 -72 +LINE Normal -99 -72 -103 -57 +LINE Normal -95 -57 -99 -72 +LINE Normal -93 -64 -95 -57 +LINE Normal -128 -64 -109 -64 +LINE Normal -128 0 -109 0 +LINE Normal -16 -24 -16 -3 +LINE Normal -16 32 -16 13 +LINE Normal -16 -14 1 -14 +LINE Normal 32 -14 17 -14 +LINE Normal 32 32 32 -14 +LINE Normal 44 -16 44 -48 +LINE Normal 76 -32 44 -16 +LINE Normal 44 -48 76 -32 +LINE Normal 32 -40 32 -64 +LINE Normal 44 -40 32 -40 +LINE Normal 32 -25 44 -25 +LINE Normal 32 -14 32 -25 +LINE Normal 73 -64 91 -64 +LINE Normal 32 -64 57 -64 +LINE Normal 91 -32 91 -64 +LINE Normal 76 -32 91 -32 +LINE Normal 112 -32 91 -32 +LINE Normal 32 -64 32 -83 +LINE Normal 32 -128 32 -99 +LINE Normal 0 -128 0 -99 +LINE Normal 0 -64 0 -83 +LINE Normal 32 -64 0 -64 +LINE Normal -107 -8 -109 0 +LINE Normal -103 7 -107 -8 +LINE Normal -99 -8 -103 7 +LINE Normal -95 7 -99 -8 +LINE Normal -93 0 -95 7 +LINE Normal 8 -97 0 -99 +LINE Normal -7 -93 8 -97 +LINE Normal 8 -89 -7 -93 +LINE Normal -7 -85 8 -89 +LINE Normal 0 -83 -7 -85 +LINE Normal 40 -97 32 -99 +LINE Normal 25 -93 40 -97 +LINE Normal 40 -89 25 -93 +LINE Normal 25 -85 40 -89 +LINE Normal 32 -83 25 -85 +LINE Normal 59 -72 57 -64 +LINE Normal 63 -57 59 -72 +LINE Normal 67 -72 63 -57 +LINE Normal 71 -57 67 -72 +LINE Normal 73 -64 71 -57 +LINE Normal 3 -22 1 -14 +LINE Normal 7 -7 3 -22 +LINE Normal 11 -22 7 -7 +LINE Normal 15 -7 11 -22 +LINE Normal 17 -14 15 -7 +LINE Normal -8 -1 -16 -3 +LINE Normal -23 3 -8 -1 +LINE Normal -8 7 -23 3 +LINE Normal -23 11 -8 7 +LINE Normal -16 13 -23 11 +LINE Normal -59 -40 -63 -40 +LINE Normal -61 -23 -61 -27 +LINE Normal -59 -25 -63 -25 +LINE Normal 52 -40 48 -40 +LINE Normal 50 -23 50 -27 +LINE Normal 52 -25 48 -25 +RECTANGLE Normal 112 32 -128 -128 +CIRCLE Normal -75 -63 -77 -65 +CIRCLE Normal -74 -62 -78 -66 +CIRCLE Normal -73 -61 -79 -67 +CIRCLE Normal -15 -13 -17 -15 +CIRCLE Normal -14 -12 -18 -16 +CIRCLE Normal -13 -11 -19 -17 +CIRCLE Normal 33 -13 31 -15 +CIRCLE Normal 34 -12 30 -16 +CIRCLE Normal 35 -11 29 -17 +CIRCLE Normal 33 -63 31 -65 +CIRCLE Normal 34 -62 30 -66 +CIRCLE Normal 35 -61 29 -67 +CIRCLE Normal 92 -31 90 -33 +CIRCLE Normal 93 -30 89 -34 +CIRCLE Normal 94 -29 88 -35 +TEXT -119 -75 Center 2 + +TEXT -119 -11 Center 2 - +TEXT -80 -112 Center 2 V+ +TEXT -48 16 Left 2 V- +TEXT -34 -112 Left 2 A4 +TEXT 38 -112 Left 2 A2 +TEXT 78 11 Center 2 LT +WINDOW 3 48 48 Left 2 +WINDOW 0 48 -144 Left 2 +SYMATTR Value LT6100 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT6100 +SYMATTR Description Precision, Gain Selectable High Side Current Sense Amplifier +PIN -128 0 NONE 8 +PINATTR PinName VS- +PINATTR SpiceOrder 1 +PIN -80 -128 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 2 +PIN 32 32 NONE 8 +PINATTR PinName FIL +PINATTR SpiceOrder 3 +PIN -16 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 112 -32 NONE 8 +PINATTR PinName VOUT +PINATTR SpiceOrder 5 +PIN 32 -128 NONE 8 +PINATTR PinName A2 +PINATTR SpiceOrder 6 +PIN 0 -128 NONE 8 +PINATTR PinName A4 +PINATTR SpiceOrder 7 +PIN -128 -64 NONE 8 +PINATTR PinName VS+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT6106.asy b/spice/copy/sym/OpAmps/LT6106.asy new file mode 100755 index 0000000..ab34cfb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6106.asy @@ -0,0 +1,55 @@ +Version 4 +SymbolType BLOCK +LINE Normal 48 -48 -48 -48 +LINE Normal 0 32 48 -48 +LINE Normal -48 -48 0 32 +LINE Normal -9 -35 -23 -35 +LINE Normal 23 -35 9 -35 +LINE Normal 0 64 0 32 +LINE Normal 32 64 0 64 +LINE Normal 96 112 64 112 +LINE Normal -96 -16 -29 -16 +LINE Normal 96 -16 29 -16 +LINE Normal -16 -64 -16 -48 +LINE Normal 16 -64 16 -48 +LINE Normal 96 -64 16 -64 +LINE Normal -16 -64 -96 -64 +LINE Normal -16 -28 -16 -42 +LINE Normal -32 0 -46 0 +LINE Normal 46 0 32 0 +LINE Normal 39 7 39 -7 +LINE Normal 32 41 32 87 +LINE Normal 64 34 32 53 +LINE Normal 64 98 32 75 +LINE Normal 47 39 32 53 +LINE Normal 51 46 47 39 +LINE Normal 32 53 51 46 +LINE Normal 64 -64 64 34 +LINE Normal 64 112 64 98 +RECTANGLE Normal 96 128 -96 -80 +CIRCLE Normal 65 -63 63 -65 +CIRCLE Normal 66 -62 62 -66 +CIRCLE Normal 67 -61 61 -67 +TEXT -54 53 Center 2 LT +WINDOW 3 -1 105 Center 2 +WINDOW 0 0 -80 Bottom 2 +SYMATTR Value LT6106 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LT6106 +SYMATTR Description High Voltage, High-Side Current Sense in SOT-23 +PIN 96 112 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -96 -16 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 3 +PIN -96 -64 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 96 -16 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6107.asy b/spice/copy/sym/OpAmps/LT6107.asy new file mode 100755 index 0000000..6cc35a7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6107.asy @@ -0,0 +1,55 @@ +Version 4 +SymbolType BLOCK +LINE Normal 48 -48 -48 -48 +LINE Normal 0 32 48 -48 +LINE Normal -48 -48 0 32 +LINE Normal -9 -35 -23 -35 +LINE Normal 23 -35 9 -35 +LINE Normal 0 64 0 32 +LINE Normal 32 64 0 64 +LINE Normal 96 112 64 112 +LINE Normal -96 -16 -29 -16 +LINE Normal 96 -16 29 -16 +LINE Normal -16 -64 -16 -48 +LINE Normal 16 -64 16 -48 +LINE Normal 96 -64 16 -64 +LINE Normal -16 -64 -96 -64 +LINE Normal -16 -28 -16 -42 +LINE Normal -32 0 -46 0 +LINE Normal 46 0 32 0 +LINE Normal 39 7 39 -7 +LINE Normal 32 41 32 87 +LINE Normal 64 34 32 53 +LINE Normal 64 98 32 75 +LINE Normal 47 39 32 53 +LINE Normal 51 46 47 39 +LINE Normal 32 53 51 46 +LINE Normal 64 -64 64 34 +LINE Normal 64 112 64 98 +RECTANGLE Normal 96 128 -96 -80 +CIRCLE Normal 65 -63 63 -65 +CIRCLE Normal 66 -62 62 -66 +CIRCLE Normal 67 -61 61 -67 +TEXT -54 53 Center 2 LT +WINDOW 3 -1 105 Center 2 +WINDOW 0 0 -80 Bottom 2 +SYMATTR Value LT6107 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LT6106 +SYMATTR Description High Voltage, High-Side Current Sense in SOT-23 +PIN 96 112 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -96 -16 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 3 +PIN -96 -64 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 96 -16 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6108-1.asy b/spice/copy/sym/OpAmps/LT6108-1.asy new file mode 100755 index 0000000..07b5090 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6108-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 112 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 1 21 Center 2 +SYMATTR Value LT6108-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6108-1 +SYMATTR Description High Side Current Sense Amplifier with Reference and Comparators\n\nNote: The reset signal must be applied on startup. Model does not reflect this. +PIN 160 -160 RIGHT 8 +PINATTR PinName SenseLo +PINATTR SpiceOrder 1 +PIN -160 -48 LEFT 8 +PINATTR PinName EN/_RST +PINATTR SpiceOrder 2 +PIN -160 64 LEFT 8 +PINATTR PinName OutC +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 160 64 RIGHT 8 +PINATTR PinName INC +PINATTR SpiceOrder 5 +PIN 160 -48 RIGHT 8 +PINATTR PinName OutA +PINATTR SpiceOrder 6 +PIN -160 -160 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 0 -208 TOP 8 +PINATTR PinName SenseHi +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT6108-2.asy b/spice/copy/sym/OpAmps/LT6108-2.asy new file mode 100755 index 0000000..afdc135 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6108-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 112 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 1 21 Center 2 +SYMATTR Value LT6108-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6108-2 +SYMATTR Description High Side Current Sense Amplifier with Reference and Comparators +PIN 160 -160 RIGHT 8 +PINATTR PinName SenseLo +PINATTR SpiceOrder 1 +PIN -160 -48 LEFT 8 +PINATTR PinName EN/_RST +PINATTR SpiceOrder 2 +PIN -160 64 LEFT 8 +PINATTR PinName OutC +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 160 64 RIGHT 8 +PINATTR PinName INC +PINATTR SpiceOrder 5 +PIN 160 -48 RIGHT 8 +PINATTR PinName OutA +PINATTR SpiceOrder 6 +PIN -160 -160 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 0 -208 TOP 8 +PINATTR PinName SenseHi +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT6109-1.asy b/spice/copy/sym/OpAmps/LT6109-1.asy new file mode 100755 index 0000000..7c984cb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6109-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 208 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 105 Center 2 +SYMATTR Value LT6109-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6109-1 +SYMATTR Description High Side Current Sense Amplifier with Reference and Comparators\n\nNote: The reset signal must be applied on startup. Model does not reflect this. +PIN 160 -176 RIGHT 8 +PINATTR PinName SenseLo +PINATTR SpiceOrder 1 +PIN -160 -64 LEFT 8 +PINATTR PinName EN/_RST +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName OutC2 +PINATTR SpiceOrder 3 +PIN -160 160 LEFT 8 +PINATTR PinName OutC1 +PINATTR SpiceOrder 4 +PIN 0 208 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName INC1 +PINATTR SpiceOrder 6 +PIN 160 160 RIGHT 8 +PINATTR PinName INC2 +PINATTR SpiceOrder 7 +PIN 160 -64 RIGHT 8 +PINATTR PinName OutA +PINATTR SpiceOrder 8 +PIN -160 -176 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN 0 -224 TOP 8 +PINATTR PinName SenseHi +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LT6109-2.asy b/spice/copy/sym/OpAmps/LT6109-2.asy new file mode 100755 index 0000000..758a019 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6109-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 224 +TEXT 0 8 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 104 Center 2 +SYMATTR Value LT6109-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6109-2 +SYMATTR Description High Side Current Sense Amplifier with Reference and Comparators\n\nNote: The reset signal must be applied on startup. Model does not reflect this. +PIN 160 -160 RIGHT 8 +PINATTR PinName SenseLo +PINATTR SpiceOrder 1 +PIN -160 -48 LEFT 8 +PINATTR PinName EN/_RST +PINATTR SpiceOrder 2 +PIN -160 64 LEFT 8 +PINATTR PinName OutC2 +PINATTR SpiceOrder 3 +PIN -160 176 LEFT 8 +PINATTR PinName OutC1 +PINATTR SpiceOrder 4 +PIN 0 224 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 5 +PIN 160 176 RIGHT 8 +PINATTR PinName INC1 +PINATTR SpiceOrder 6 +PIN 160 64 RIGHT 8 +PINATTR PinName INC2 +PINATTR SpiceOrder 7 +PIN 160 -48 RIGHT 8 +PINATTR PinName OutA +PINATTR SpiceOrder 8 +PIN -160 -160 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN 0 -208 TOP 8 +PINATTR PinName SenseHi +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LT6118.asy b/spice/copy/sym/OpAmps/LT6118.asy new file mode 100755 index 0000000..a2fff2a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6118.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 112 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 1 21 Center 2 +SYMATTR Value LT6118 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6118 +SYMATTR Description Current Sense Amplifier Reference and Comparator with POR +PIN 160 -160 RIGHT 8 +PINATTR PinName SenseLo +PINATTR SpiceOrder 1 +PIN -160 -48 LEFT 8 +PINATTR PinName LE +PINATTR SpiceOrder 2 +PIN -160 64 LEFT 8 +PINATTR PinName OutC +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 160 64 RIGHT 8 +PINATTR PinName INC +PINATTR SpiceOrder 5 +PIN 160 -48 RIGHT 8 +PINATTR PinName OutA +PINATTR SpiceOrder 6 +PIN -160 -160 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 0 -208 TOP 8 +PINATTR PinName SenseHi +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT6119-1.asy b/spice/copy/sym/OpAmps/LT6119-1.asy new file mode 100755 index 0000000..d32a298 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6119-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 208 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 105 Center 2 +SYMATTR Value LT6119-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6119-1 +SYMATTR Description Current Sense Amplifier, Reference and Comparators with POR +PIN 160 -176 RIGHT 8 +PINATTR PinName SenseLo +PINATTR SpiceOrder 1 +PIN -160 -64 LEFT 8 +PINATTR PinName LE +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName OutC2 +PINATTR SpiceOrder 3 +PIN -160 160 LEFT 8 +PINATTR PinName OutC1 +PINATTR SpiceOrder 4 +PIN 0 208 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName INC1 +PINATTR SpiceOrder 6 +PIN 160 160 RIGHT 8 +PINATTR PinName INC2 +PINATTR SpiceOrder 7 +PIN 160 -64 RIGHT 8 +PINATTR PinName OutA +PINATTR SpiceOrder 8 +PIN -160 -176 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN 0 -224 TOP 8 +PINATTR PinName SenseHi +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LT6119-2.asy b/spice/copy/sym/OpAmps/LT6119-2.asy new file mode 100755 index 0000000..13cda98 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6119-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 224 +TEXT 0 8 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 104 Center 2 +SYMATTR Value LT6119-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6119-2 +SYMATTR Description Current Sense Amplifier, Reference and Comparators with POR +PIN 160 -160 RIGHT 8 +PINATTR PinName SenseLo +PINATTR SpiceOrder 1 +PIN -160 -48 LEFT 8 +PINATTR PinName LE +PINATTR SpiceOrder 2 +PIN -160 64 LEFT 8 +PINATTR PinName OutC2 +PINATTR SpiceOrder 3 +PIN -160 176 LEFT 8 +PINATTR PinName OutC1 +PINATTR SpiceOrder 4 +PIN 0 224 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 5 +PIN 160 176 RIGHT 8 +PINATTR PinName INC1 +PINATTR SpiceOrder 6 +PIN 160 64 RIGHT 8 +PINATTR PinName INC2 +PINATTR SpiceOrder 7 +PIN 160 -48 RIGHT 8 +PINATTR PinName OutA +PINATTR SpiceOrder 8 +PIN -160 -160 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN 0 -208 TOP 8 +PINATTR PinName SenseHi +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LT6200-10.asy b/spice/copy/sym/OpAmps/LT6200-10.asy new file mode 100755 index 0000000..2870c53 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6200-10.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6200-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6200-10 +SYMATTR Description 1600MHz, Av=10 Rail-to-Rail Low Noise Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6200-5.asy b/spice/copy/sym/OpAmps/LT6200-5.asy new file mode 100755 index 0000000..11b41c5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6200-5.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6200-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6200-5 +SYMATTR Description 800MHz, Av=5 Rail-to-Rail Low Noise Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6200.asy b/spice/copy/sym/OpAmps/LT6200.asy new file mode 100755 index 0000000..6aded11 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6200.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6200 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6200 +SYMATTR Description 165 MHz, Rail-to-Rail Input and Output, 0.95nV/rtHz Low Noise Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6201.asy b/spice/copy/sym/OpAmps/LT6201.asy new file mode 100755 index 0000000..7e69efe --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6201.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6201 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6201 +SYMATTR Description Dual 165 MHz, Rail-to-Rail, 0.95 nV/rtHz Low Noise Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6202.asy b/spice/copy/sym/OpAmps/LT6202.asy new file mode 100755 index 0000000..92c4792 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6202.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6202 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6202 +SYMATTR Description 100 MHz, Rail-to-Rail, 1.9nV/rtHz Low Power Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6203.asy b/spice/copy/sym/OpAmps/LT6203.asy new file mode 100755 index 0000000..ff5dae0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6203.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6203 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6202 +SYMATTR Description Dual 100 MHz, Rail-to-Rail, 1.9nV/rtHz Low Power Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6204.asy b/spice/copy/sym/OpAmps/LT6204.asy new file mode 100755 index 0000000..4998f00 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6204.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6204 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6202 +SYMATTR Description Quad 100 MHz, Rail-to-Rail, 1.9nV/rtHz Low Power Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6205.asy b/spice/copy/sym/OpAmps/LT6205.asy new file mode 100755 index 0000000..57b84be --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6205.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6205 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6205 +SYMATTR Description Single Supply 3V, 100MHz Video Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6206.asy b/spice/copy/sym/OpAmps/LT6206.asy new file mode 100755 index 0000000..ab9fbc7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6206.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6206 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6205 +SYMATTR Description Dual Single Supply 3V, 100MHz Video Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6207.asy b/spice/copy/sym/OpAmps/LT6207.asy new file mode 100755 index 0000000..53209d2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6207.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6207 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6205 +SYMATTR Description Quad Single Supply 3V, 100MHz Video Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6210.asy b/spice/copy/sym/OpAmps/LT6210.asy new file mode 100755 index 0000000..ddfd120 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6210.asy @@ -0,0 +1,57 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 64 0 +LINE Normal -32 48 64 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -32 -20 -32 +LINE Normal -28 32 -20 32 +LINE Normal -24 36 -24 28 +LINE Normal -16 -64 -16 -40 +LINE Normal -16 64 -16 40 +LINE Normal -12 -44 -4 -44 +LINE Normal -8 -48 -8 -40 +LINE Normal -12 44 -4 44 +LINE Normal 16 64 16 24 +LINE Normal 8 5 14 5 +LINE Normal 8 12 14 12 +LINE Normal 8 5 8 20 +LINE Normal 15 11 14 12 +LINE Normal 15 6 14 5 +LINE Normal 15 6 15 11 +LINE Normal 12 12 15 20 +LINE Normal 22 13 21 12 +LINE Normal 18 13 19 12 +LINE Normal 21 12 19 12 +LINE Normal 18 19 19 20 +LINE Normal 22 19 21 20 +LINE Normal 19 20 21 20 +LINE Normal 19 16 21 16 +LINE Normal 21 16 22 17 +LINE Normal 18 15 19 16 +LINE Normal 18 13 18 15 +LINE Normal 22 17 22 19 +WINDOW 0 16 -39 Left 2 +WINDOW 3 27 32 Left 2 +SYMATTR Value LT6210 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LT6210 +SYMATTR Description Programmable Supply Current, R-R Output, Current Feedback Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 64 NONE 0 +PINATTR PinName V-1 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6211.asy b/spice/copy/sym/OpAmps/LT6211.asy new file mode 100755 index 0000000..57691e7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6211.asy @@ -0,0 +1,57 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 64 0 +LINE Normal -32 48 64 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -32 -20 -32 +LINE Normal -28 32 -20 32 +LINE Normal -24 36 -24 28 +LINE Normal -16 -64 -16 -40 +LINE Normal -16 64 -16 40 +LINE Normal -12 -44 -4 -44 +LINE Normal -8 -48 -8 -40 +LINE Normal -12 44 -4 44 +LINE Normal 16 64 16 24 +LINE Normal 8 5 14 5 +LINE Normal 8 12 14 12 +LINE Normal 8 5 8 20 +LINE Normal 15 11 14 12 +LINE Normal 15 6 14 5 +LINE Normal 15 6 15 11 +LINE Normal 12 12 15 20 +LINE Normal 22 13 21 12 +LINE Normal 18 13 19 12 +LINE Normal 21 12 19 12 +LINE Normal 18 19 19 20 +LINE Normal 22 19 21 20 +LINE Normal 19 20 21 20 +LINE Normal 19 16 21 16 +LINE Normal 21 16 22 17 +LINE Normal 18 15 19 16 +LINE Normal 18 13 18 15 +LINE Normal 22 17 22 19 +WINDOW 0 16 -39 Left 2 +WINDOW 3 27 32 Left 2 +SYMATTR Value LT6211 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LT6210 +SYMATTR Description Dual Programmable Supply Current, R-R Output, Current Feedback Amplifier +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -64 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 64 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 64 NONE 0 +PINATTR PinName V-1 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6220.asy b/spice/copy/sym/OpAmps/LT6220.asy new file mode 100755 index 0000000..5869d11 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6220.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6220 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.LIB +SYMATTR Value2 LT6220 +SYMATTR Description 60MHz, 20V/µs, Low Power, RRIO Precision Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6221.asy b/spice/copy/sym/OpAmps/LT6221.asy new file mode 100755 index 0000000..8da7dbe --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6221.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6221 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.LIB +SYMATTR Value2 LT6220 +SYMATTR Description Dual 60MHz, 20V/µs, Low Power, RRIO Precision Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6222.asy b/spice/copy/sym/OpAmps/LT6222.asy new file mode 100755 index 0000000..d9dd052 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6222.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6222 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.LIB +SYMATTR Value2 LT6220 +SYMATTR Description Quad 60MHz, 20V/µs, Low Power, RRIO Precision Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6230-10.asy b/spice/copy/sym/OpAmps/LT6230-10.asy new file mode 100755 index 0000000..28ea746 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6230-10.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 44 28 44 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 56 8 40 8 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6230-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6230-10 +SYMATTR Description 1.45GHz, Av=10, Rail-to-Rail Output, Low Noise, 3.4mA Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName EN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6230.asy b/spice/copy/sym/OpAmps/LT6230.asy new file mode 100755 index 0000000..26a1439 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6230.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6230 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6230 +SYMATTR Description 215 MHz, Rail-to-Rail Output, 1.1nV/rtHz, 3.4mA Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6231.asy b/spice/copy/sym/OpAmps/LT6231.asy new file mode 100755 index 0000000..e9b819d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6231.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6231 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6231 +SYMATTR Description Dual 215 MHz, Rail-to-Rail Output, 1.1nV/rtHz, 3.4mA Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6232.asy b/spice/copy/sym/OpAmps/LT6232.asy new file mode 100755 index 0000000..baeb652 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6232.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6232 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6231 +SYMATTR Description Quad 215 MHz, Rail-to-Rail Output, 1.1nV/rtHz, 3.4mA Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6233-10.asy b/spice/copy/sym/OpAmps/LT6233-10.asy new file mode 100755 index 0000000..f8db40d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6233-10.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 44 28 44 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 56 8 40 8 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6233-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6233-10 +SYMATTR Description 375MHz, AV=10, Rail-to-Rail Output, 1.9nV/rtHz, 1.2mA Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName EN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6233.asy b/spice/copy/sym/OpAmps/LT6233.asy new file mode 100755 index 0000000..94d3f11 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6233.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 44 28 44 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 56 8 40 8 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6233 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6233 +SYMATTR Description 60MHz, Rail-to-Rail Output, 1.9nV/rtHz, 1.2mA Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName EN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6234.asy b/spice/copy/sym/OpAmps/LT6234.asy new file mode 100755 index 0000000..8460c1b --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6234.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6234 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6234 +SYMATTR Description Dual 60MHz, Rail-to-Rail Output, 1.9nV/rtHz, 1.2mA Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6235.asy b/spice/copy/sym/OpAmps/LT6235.asy new file mode 100755 index 0000000..0e1fbe4 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6235.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6235 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6234 +SYMATTR Description Quad 60MHz, Rail-to-Rail Output, 1.9nV/rtHz, 1.2mA Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6236.asy b/spice/copy/sym/OpAmps/LT6236.asy new file mode 100755 index 0000000..a9be6c6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6236.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LT6236 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LT6236 +SYMATTR Description 215 MHz, Rail-to-Rail Output, 1.1nV/rtHz Op Amp/SAR ADC Driver +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LT6237.asy b/spice/copy/sym/OpAmps/LT6237.asy new file mode 100755 index 0000000..aeb8b4d --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6237.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6237 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LT6237 +SYMATTR Description Dual 215 MHz, Rail-to-Rail Output, 1.1nV/rtHz Op Amp/SAR ADC Driver +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6238.asy b/spice/copy/sym/OpAmps/LT6238.asy new file mode 100755 index 0000000..72db029 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6238.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6238 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LT6237 +SYMATTR Description Quad 215 MHz, Rail-to-Rail Output, 1.1nV/rtHz Op Amp/SAR ADC Driver +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6274.asy b/spice/copy/sym/OpAmps/LT6274.asy new file mode 100755 index 0000000..8911fec --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6274.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6274 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LT6275 +SYMATTR Description 90MHz, 2200V/µs 30V Low Power Op Amp +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6275.asy b/spice/copy/sym/OpAmps/LT6275.asy new file mode 100755 index 0000000..cac4971 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6275.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LT6275 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LT6275 +SYMATTR Description Dual 90MHz, 2200V/µs 30V Low Power Op Amp +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6300.asy b/spice/copy/sym/OpAmps/LT6300.asy new file mode 100755 index 0000000..d8278a3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6300.asy @@ -0,0 +1,60 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -29 +LINE Normal 0 48 0 29 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal -16 48 -16 38 +LINE Normal 16 48 16 19 +LINE Normal 9 10 13 10 +LINE Normal 13 15 13 10 +LINE Normal 13 15 9 15 +LINE Normal 9 5 9 10 +LINE Normal 9 5 13 5 +LINE Normal -18 29 -14 29 +LINE Normal -14 34 -14 29 +LINE Normal -14 34 -18 34 +LINE Normal -18 24 -18 29 +LINE Normal -18 24 -14 24 +LINE Normal 16 15 16 5 +LINE Normal 18 5 16 5 +LINE Normal 20 6 18 5 +LINE Normal 20 10 20 6 +LINE Normal 18 11 20 10 +LINE Normal 20 15 18 11 +LINE Normal 16 11 18 11 +LINE Normal -4 21 4 21 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT6300 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1794 +SYMATTR Description 500mA, 200MHz xDSL Line Driver in 16-Lead SSOP Package +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -16 48 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 6 +PIN 16 48 NONE 0 +PINATTR PinName SR +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LT6301.asy b/spice/copy/sym/OpAmps/LT6301.asy new file mode 100755 index 0000000..2393aaa --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6301.asy @@ -0,0 +1,60 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -29 +LINE Normal 0 48 0 29 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal -16 48 -16 38 +LINE Normal 16 48 16 19 +LINE Normal 9 10 13 10 +LINE Normal 13 15 13 10 +LINE Normal 13 15 9 15 +LINE Normal 9 5 9 10 +LINE Normal 9 5 13 5 +LINE Normal -18 29 -14 29 +LINE Normal -14 34 -14 29 +LINE Normal -14 34 -18 34 +LINE Normal -18 24 -18 29 +LINE Normal -18 24 -14 24 +LINE Normal 16 15 16 5 +LINE Normal 18 5 16 5 +LINE Normal 20 6 18 5 +LINE Normal 20 10 20 6 +LINE Normal 18 11 20 10 +LINE Normal 20 15 18 11 +LINE Normal 16 11 18 11 +LINE Normal -4 21 4 21 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT6301 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1794 +SYMATTR Description Dual 500mA, Differential xDSL Line Driver in 28-Lead TSSOP Package +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -16 48 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 6 +PIN 16 48 NONE 0 +PINATTR PinName SR +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LT6350.asy b/spice/copy/sym/OpAmps/LT6350.asy new file mode 100755 index 0000000..fde501a --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6350.asy @@ -0,0 +1,93 @@ +Version 4 +SymbolType BLOCK +LINE Normal 112 25 128 25 +LINE Normal 128 -112 128 25 +LINE Normal -32 41 64 41 +LINE Normal 78 9 68 9 +LINE Normal 78 41 68 41 +LINE Normal 73 36 73 46 +LINE Normal 112 25 112 25 +LINE Normal 112 25 112 25 +LINE Normal -32 128 -32 41 +LINE Normal -112 -7 -96 -7 +LINE Normal -112 -7 -112 -7 +LINE Normal -112 128 -112 -7 +LINE Normal -112 -39 -96 -39 +LINE Normal -112 -39 -112 -39 +LINE Normal -112 -112 -112 -39 +LINE Normal 64 -7 112 25 +LINE Normal 112 25 64 57 +LINE Normal 64 57 64 -7 +LINE Normal 64 -23 48 -23 +LINE Normal 100 -31 92 -15 +LINE Normal 100 -31 108 -15 +LINE Normal 84 -31 76 -15 +LINE Normal 84 -31 92 -15 +LINE Normal 68 -31 76 -15 +LINE Normal 68 -31 64 -23 +LINE Normal 112 -23 108 -15 +LINE Normal 128 -23 112 -23 +LINE Normal 64 9 48 9 +LINE Normal 48 9 48 -23 +LINE Normal -16 -23 -48 -23 +LINE Normal 20 -31 12 -15 +LINE Normal 20 -31 28 -15 +LINE Normal 4 -31 -4 -15 +LINE Normal 4 -31 12 -15 +LINE Normal -12 -31 -4 -15 +LINE Normal -12 -31 -16 -23 +LINE Normal 32 -23 28 -15 +LINE Normal 48 -23 32 -23 +LINE Normal -92 -7 -82 -7 +LINE Normal -92 -39 -82 -39 +LINE Normal -87 -34 -87 -44 +LINE Normal -48 -23 -48 -23 +LINE Normal -48 -23 -48 -23 +LINE Normal -96 -55 -48 -23 +LINE Normal -48 -23 -96 9 +LINE Normal -96 9 -96 -55 +LINE Normal 128 128 128 64 +LINE Normal -40 64 128 64 +LINE Normal -40 64 -40 -23 +RECTANGLE Normal 160 -112 -144 128 +CIRCLE Normal -39 -22 -41 -24 +CIRCLE Normal -38 -21 -42 -25 +CIRCLE Normal -37 -20 -43 -26 +CIRCLE Normal 49 -22 47 -24 +CIRCLE Normal 50 -21 46 -25 +CIRCLE Normal 51 -20 45 -26 +CIRCLE Normal 129 -22 127 -24 +CIRCLE Normal 130 -21 126 -25 +CIRCLE Normal 131 -20 125 -26 +TEXT -71 96 Center 2 LT +WINDOW 0 9 -56 Center 2 +WINDOW 3 45 80 Center 2 +SYMATTR Value LT6350 +SYMATTR Prefix X +SYMATTR Value2 LT6350 +SYMATTR Description Single-Ended to Differential Converter/ADC Driver +SYMATTR SpiceModel LTC7.lib +PIN -112 128 NONE 5 +PINATTR PinName -IN1 +PINATTR SpiceOrder 1 +PIN -32 128 NONE 5 +PINATTR PinName +IN2 +PINATTR SpiceOrder 2 +PIN 48 -112 TOP 5 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 128 NONE 5 +PINATTR PinName OUT1 +PINATTR SpiceOrder 4 +PIN 128 -112 NONE 5 +PINATTR PinName OUT2 +PINATTR SpiceOrder 5 +PIN 48 128 BOTTOM 5 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -32 -112 TOP 9 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -112 -112 NONE 5 +PINATTR PinName +IN1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT6370.asy b/spice/copy/sym/OpAmps/LT6370.asy new file mode 100755 index 0000000..72b3690 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6370.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -144 144 0 +LINE Normal -32 144 144 0 +LINE Normal -32 -144 -32 144 +LINE Normal -25 112 -17 112 +LINE Normal -25 -112 -17 -112 +LINE Normal -21 -108 -21 -116 +LINE Normal 0 -144 0 -118 +LINE Normal 0 144 0 118 +LINE Normal 4 -124 12 -124 +LINE Normal 8 -128 8 -120 +LINE Normal 4 124 12 124 +LINE Normal 80 80 80 52 +TEXT -24 -64 Left 2 Rg +TEXT -24 64 Left 2 Rg +TEXT 80 37 Bottom 2 Ref +WINDOW 0 64 -80 Left 2 +WINDOW 3 96 64 Left 2 +SYMATTR Value LT6370 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT6370 +SYMATTR Description Precision, Low Drift, Low Noise, Instrumentation Amplifier +PIN -32 64 NONE 8 +PINATTR PinName -RG +PINATTR SpiceOrder 1 +PIN -32 112 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -32 -112 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN 0 144 NONE 0 +PINATTR PinName -V +PINATTR SpiceOrder 4 +PIN 80 80 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 5 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 0 -144 NONE 0 +PINATTR PinName +V +PINATTR SpiceOrder 7 +PIN -32 -64 NONE 8 +PINATTR PinName +RG +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT6372-0.2.asy b/spice/copy/sym/OpAmps/LT6372-0.2.asy new file mode 100755 index 0000000..5405c28 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6372-0.2.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +LINE Normal -144 -144 144 0 +LINE Normal -144 144 144 0 +LINE Normal -144 -144 -144 144 +LINE Normal -137 112 -129 112 +LINE Normal -137 -112 -129 -112 +LINE Normal -133 -108 -133 -116 +LINE Normal -80 -128 -80 -112 +LINE Normal -80 128 -80 112 +LINE Normal -76 -116 -68 -116 +LINE Normal -72 -120 -72 -112 +LINE Normal -75 116 -67 116 +LINE Normal -16 112 -16 80 +LINE Normal 48 80 48 48 +LINE Normal -16 -112 -16 -80 +LINE Normal 48 -80 48 -48 +TEXT -136 -64 Left 2 Rgf +TEXT -136 64 Left 2 Rgf +TEXT -16 55 Center 2 Ref1 +TEXT -136 -32 Left 2 Rgs +TEXT -136 32 Left 2 Rgs +TEXT 48 25 Center 2 Cllo +TEXT -16 -55 Center 2 Ref2 +TEXT 48 -25 Center 2 Clhi +WINDOW 0 80 -48 Left 2 +WINDOW 3 96 48 Left 2 +SYMATTR Value LT6372-0.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT6372-0.2.sub +SYMATTR Value2 LT6372-0.2 +SYMATTR Description Precision, Low Drift, Low Noise, Funneling Instrumentation Amplifier +PIN -144 64 NONE 8 +PINATTR PinName -RGF +PINATTR SpiceOrder 1 +PIN -144 112 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -144 -112 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -80 128 NONE 0 +PINATTR PinName -V +PINATTR SpiceOrder 4 +PIN -16 112 NONE 8 +PINATTR PinName REF1 +PINATTR SpiceOrder 5 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN -80 -128 NONE 0 +PINATTR PinName +V +PINATTR SpiceOrder 7 +PIN -144 -64 NONE 8 +PINATTR PinName +RGF +PINATTR SpiceOrder 8 +PIN -144 32 NONE 8 +PINATTR PinName -RGS +PINATTR SpiceOrder 9 +PIN -144 -32 NONE 8 +PINATTR PinName +RGS +PINATTR SpiceOrder 10 +PIN -16 -112 NONE 8 +PINATTR PinName REF2 +PINATTR SpiceOrder 11 +PIN 48 -80 NONE 0 +PINATTR PinName CLHI +PINATTR SpiceOrder 12 +PIN 48 80 NONE 8 +PINATTR PinName CLLO +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/OpAmps/LT6372-1.asy b/spice/copy/sym/OpAmps/LT6372-1.asy new file mode 100755 index 0000000..24a3656 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6372-1.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +LINE Normal -144 -144 144 0 +LINE Normal -144 144 144 0 +LINE Normal -144 -144 -144 144 +LINE Normal -137 112 -129 112 +LINE Normal -137 -112 -129 -112 +LINE Normal -133 -108 -133 -116 +LINE Normal -80 -128 -80 -112 +LINE Normal -80 128 -80 112 +LINE Normal -76 -116 -68 -116 +LINE Normal -72 -120 -72 -112 +LINE Normal -75 116 -67 116 +LINE Normal -16 112 -16 80 +LINE Normal 48 80 48 48 +LINE Normal -16 -112 -16 -80 +LINE Normal 48 -80 48 -48 +TEXT -136 -64 Left 2 Rgf +TEXT -136 64 Left 2 Rgf +TEXT -16 55 Center 2 Ref1 +TEXT -136 -32 Left 2 Rgs +TEXT -136 32 Left 2 Rgs +TEXT 48 25 Center 2 Cllo +TEXT -16 -55 Center 2 Ref2 +TEXT 48 -25 Center 2 Clhi +WINDOW 0 80 -48 Left 2 +WINDOW 3 80 48 Left 2 +SYMATTR Value LT6372-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LT6372-1 +SYMATTR Description Precision, Low Drift, Low Noise, Instrumentation Amplifier +PIN -144 64 NONE 8 +PINATTR PinName -RGF +PINATTR SpiceOrder 1 +PIN -144 112 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -144 -112 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -80 128 NONE 0 +PINATTR PinName -V +PINATTR SpiceOrder 4 +PIN -16 112 NONE 8 +PINATTR PinName REF1 +PINATTR SpiceOrder 5 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN -80 -128 NONE 0 +PINATTR PinName +V +PINATTR SpiceOrder 7 +PIN -144 -64 NONE 8 +PINATTR PinName +RGF +PINATTR SpiceOrder 8 +PIN -144 32 NONE 8 +PINATTR PinName -RGS +PINATTR SpiceOrder 9 +PIN -144 -32 NONE 8 +PINATTR PinName +RGS +PINATTR SpiceOrder 10 +PIN -16 -112 NONE 8 +PINATTR PinName REF2 +PINATTR SpiceOrder 11 +PIN 48 -80 NONE 0 +PINATTR PinName CLHI +PINATTR SpiceOrder 12 +PIN 48 80 NONE 8 +PINATTR PinName CLLO +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/OpAmps/LT6375.asy b/spice/copy/sym/OpAmps/LT6375.asy new file mode 100755 index 0000000..67dd7eb --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6375.asy @@ -0,0 +1,174 @@ +Version 4 +SymbolType CELL +LINE Normal 96 -32 160 0 +LINE Normal 96 32 160 0 +LINE Normal 96 -32 96 32 +LINE Normal 100 -16 108 -16 +LINE Normal 101 16 109 16 +LINE Normal 105 20 105 12 +LINE Normal 128 -128 128 -16 +LINE Normal 128 128 128 16 +LINE Normal 132 -20 140 -20 +LINE Normal 136 -24 136 -16 +LINE Normal 132 20 140 20 +LINE Normal -124 -22 -128 -16 +LINE Normal -96 -16 -100 -10 +LINE Normal -100 -10 -108 -22 +LINE Normal -116 -10 -108 -22 +LINE Normal -116 -10 -124 -22 +LINE Normal -124 10 -128 16 +LINE Normal -96 16 -100 22 +LINE Normal -100 22 -108 10 +LINE Normal -116 22 -108 10 +LINE Normal -116 22 -124 10 +LINE Normal -96 16 96 16 +LINE Normal -96 -16 96 -16 +LINE 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Left 2 19K +WINDOW 0 192 -128 Bottom 2 +WINDOW 3 193 128 Top 2 +SYMATTR Value LT6375 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT6375 +SYMATTR Description +/-270 Volt Common Mode Voltage Difference Amplifier +PIN -256 16 NONE 8 +PINATTR PinName +IN +PINATTR SpiceOrder 1 +PIN -224 128 NONE 0 +PINATTR PinName +REFA +PINATTR SpiceOrder 3 +PIN -144 128 NONE 0 +PINATTR PinName +REFB +PINATTR SpiceOrder 4 +PIN -64 128 NONE 0 +PINATTR PinName +REFC +PINATTR SpiceOrder 5 +PIN 224 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 80 128 BOTTOM 4 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 224 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 8 +PIN 128 -128 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN -64 -128 NONE 0 +PINATTR PinName -REFC +PINATTR SpiceOrder 10 +PIN -144 -128 NONE 0 +PINATTR PinName -REFB +PINATTR SpiceOrder 11 +PIN -224 -128 NONE 0 +PINATTR PinName -REFA +PINATTR SpiceOrder 12 +PIN -256 -16 NONE 8 +PINATTR PinName -IN +PINATTR SpiceOrder 14 +PIN 128 128 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/OpAmps/LT6376.asy b/spice/copy/sym/OpAmps/LT6376.asy new file mode 100755 index 0000000..99baa73 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6376.asy @@ -0,0 +1,168 @@ +Version 4 +SymbolType CELL +LINE Normal 96 -32 160 0 +LINE Normal 96 32 160 0 +LINE Normal 96 -32 96 32 +LINE Normal 100 -16 108 -16 +LINE Normal 101 16 109 16 +LINE Normal 105 20 105 12 +LINE Normal 128 -128 128 -16 +LINE Normal 128 128 128 16 +LINE Normal 132 -20 140 -20 +LINE Normal 136 -24 136 -16 +LINE Normal 132 20 140 20 +LINE Normal -124 -22 -128 -16 +LINE Normal -96 -16 -100 -10 +LINE Normal -100 -10 -108 -22 +LINE Normal -116 -10 -108 -22 +LINE Normal -116 -10 -124 -22 +LINE Normal -124 10 -128 16 +LINE Normal -96 16 -100 22 +LINE Normal -100 22 -108 10 +LINE Normal -116 22 -108 10 +LINE Normal -116 22 -124 10 +LINE Normal -96 16 96 16 +LINE Normal -96 -16 96 -16 +LINE Normal 63 -64 63 -16 +LINE Normal 148 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Normal 65 18 61 14 +CIRCLE Normal 66 19 60 13 +CIRCLE Normal -63 -15 -65 -17 +CIRCLE Normal -62 -14 -66 -18 +CIRCLE Normal -61 -13 -67 -19 +CIRCLE Normal 209 1 207 -1 +CIRCLE Normal 210 2 206 -2 +CIRCLE Normal 211 3 205 -3 +CIRCLE Normal -63 -55 -65 -57 +CIRCLE Normal -62 -54 -66 -58 +CIRCLE Normal -61 -53 -67 -59 +CIRCLE Normal -63 17 -65 15 +CIRCLE Normal -62 18 -66 14 +CIRCLE Normal -61 19 -67 13 +CIRCLE Normal -63 57 -65 55 +CIRCLE Normal -62 58 -66 54 +CIRCLE Normal -61 59 -67 53 +TEXT -108 -22 Bottom 2 76K +TEXT -108 22 Top 2 76K +TEXT 164 -70 Bottom 2 760K +TEXT 0 -48 Center 2 LT +TEXT -56 -96 Left 2 23.75K +TEXT -136 -96 Left 2 38K +TEXT -216 -96 Left 2 19K +TEXT -56 96 Left 2 23.75K +TEXT -136 96 Left 2 38K +TEXT -216 96 Left 2 19K +TEXT 164 58 Bottom 2 760K +WINDOW 0 192 -128 Bottom 2 +WINDOW 3 193 128 Top 2 +SYMATTR Value LT6376 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6376 +SYMATTR Description +/-110 Volt Common Mode Voltage G=10 Difference Amplifier +PIN -256 16 NONE 8 +PINATTR PinName +IN +PINATTR SpiceOrder 1 +PIN -224 128 NONE 0 +PINATTR PinName +REFA +PINATTR SpiceOrder 3 +PIN -144 128 NONE 0 +PINATTR PinName +REFB +PINATTR SpiceOrder 4 +PIN -64 128 NONE 0 +PINATTR PinName +REFC +PINATTR SpiceOrder 5 +PIN 224 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 6 +PIN 80 128 BOTTOM 4 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 224 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 8 +PIN 128 -128 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 9 +PIN -64 -128 NONE 0 +PINATTR PinName -REFC +PINATTR SpiceOrder 10 +PIN -144 -128 NONE 0 +PINATTR PinName -REFB +PINATTR SpiceOrder 11 +PIN -224 -128 NONE 0 +PINATTR PinName -REFA +PINATTR SpiceOrder 12 +PIN -256 -16 NONE 8 +PINATTR PinName -IN +PINATTR SpiceOrder 14 +PIN 128 128 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/OpAmps/LT6402-12.asy b/spice/copy/sym/OpAmps/LT6402-12.asy new file mode 100755 index 0000000..7b849b3 --- /dev/null +++ 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3 +PIN 0 96 BOTTOM 8 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 96 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LT6551.asy b/spice/copy/sym/OpAmps/LT6551.asy new file mode 100755 index 0000000..77f27c3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6551.asy @@ -0,0 +1,75 @@ +Version 4 +SymbolType BLOCK +LINE Normal -16 32 -16 -32 +LINE Normal 49 0 -16 32 +LINE Normal -16 -32 49 0 +LINE Normal -16 -16 -112 -16 +LINE Normal -38 16 -16 16 +LINE Normal -43 25 -38 16 +LINE Normal -50 8 -43 25 +LINE Normal -59 25 -50 8 +LINE Normal -67 8 -59 25 +LINE Normal -71 16 -67 8 +LINE Normal -80 16 -71 16 +LINE Normal -28 46 -2 46 +LINE Normal 57 46 31 46 +LINE Normal -28 46 -28 16 +LINE Normal 57 0 57 46 +LINE Normal 49 0 57 0 +LINE Normal 96 0 57 0 +LINE Normal -1 -16 -11 -16 +LINE Normal -6 -11 -6 -21 +LINE Normal -1 16 -11 16 +LINE Normal -80 38 -80 16 +LINE Normal -70 38 -90 38 +LINE Normal -80 47 -70 38 +LINE Normal -90 38 -80 47 +LINE Normal -25 15 -31 15 +LINE Normal -25 14 -31 14 +LINE Normal -25 13 -31 13 +LINE Normal -25 17 -31 17 +LINE Normal -25 18 -31 18 +LINE Normal -25 19 -31 19 +LINE Normal 60 -1 54 -1 +LINE Normal 60 -2 54 -2 +LINE Normal 60 -3 54 -3 +LINE Normal 60 1 54 1 +LINE Normal 60 2 54 2 +LINE Normal 60 3 54 3 +LINE Normal -27 19 -27 13 +LINE Normal -26 19 -26 13 +LINE Normal -25 19 -25 13 +LINE Normal -29 19 -29 13 +LINE Normal -30 19 -30 13 +LINE Normal -31 19 -31 13 +LINE Normal 58 3 58 -3 +LINE Normal 59 3 59 -3 +LINE Normal 60 3 60 -3 +LINE Normal 56 3 56 -3 +LINE Normal 55 3 55 -3 +LINE Normal 54 3 54 -3 +LINE Normal 26 55 31 46 +LINE Normal 19 38 26 55 +LINE Normal 10 55 19 38 +LINE Normal 2 38 10 55 +LINE Normal -2 46 2 38 +RECTANGLE Normal 96 96 -112 -80 +WINDOW 3 18 107 Left 2 +WINDOW 0 16 -91 Left 2 +SYMATTR Value LT6551 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6551 +SYMATTR Description 3.3V Quad Video Amplifier +PIN -112 -16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 0 -80 TOP 8 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 96 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/OpAmps/LT6552.asy b/spice/copy/sym/OpAmps/LT6552.asy new file mode 100755 index 0000000..413ebca --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6552.asy @@ -0,0 +1,51 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 -80 48 -36 +LINE Normal 52 -7 44 -7 +LINE Normal 52 -7 52 -15 +LINE Normal 44 -15 52 -15 +LINE Normal 44 -15 44 -23 +LINE Normal 52 -23 44 -23 +LINE Normal -20 -16 -12 -16 +LINE Normal -20 -48 -12 -48 +LINE Normal -16 -52 -16 -44 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 55 -28 41 -28 +WINDOW 0 63 -49 Left 2 +WINDOW 3 44 54 Left 2 +SYMATTR Value LT6552 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6552 +SYMATTR Description 3.3V Single Supply Video Difference Amplifier +PIN -32 16 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -32 -48 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 48 -80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 5 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 7 +PIN -32 48 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LT6553.asy b/spice/copy/sym/OpAmps/LT6553.asy new file mode 100755 index 0000000..8269112 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6553.asy @@ -0,0 +1,145 @@ +Version 4 +SymbolType BLOCK +LINE Normal -16 9 -16 -44 +LINE Normal 41 -16 -16 9 +LINE Normal -16 -44 41 -16 +LINE Normal -8 -32 -14 -32 +LINE Normal -11 -29 -11 -35 +LINE Normal -8 -3 -14 -3 +LINE Normal -24 -3 -16 -3 +LINE Normal -24 16 -24 -3 +LINE Normal 48 16 17 16 +LINE Normal 48 -16 48 16 +LINE Normal 41 -16 48 -16 +LINE Normal -66 16 -52 16 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 52 -16 110 +LINE Normal 41 80 -16 52 +LINE Normal -16 110 41 80 +LINE Normal -8 96 -14 96 +LINE Normal -11 93 -11 99 +LINE Normal -8 67 -14 67 +LINE Normal -24 67 -16 67 +LINE Normal -24 48 -24 67 +LINE Normal 48 48 17 48 +LINE Normal 48 80 48 48 +LINE Normal 41 80 48 80 +LINE Normal -66 48 -52 48 +LINE Normal -16 96 -96 96 +LINE Normal -16 132 -16 190 +LINE Normal 41 160 -16 132 +LINE Normal -16 190 41 160 +LINE Normal -8 176 -14 176 +LINE Normal -11 173 -11 179 +LINE Normal -8 147 -14 147 +LINE Normal -24 147 -16 147 +LINE Normal -24 128 -24 147 +LINE Normal 48 128 17 128 +LINE Normal 48 160 48 128 +LINE Normal 41 160 48 160 +LINE Normal -96 128 -52 128 +LINE Normal -16 176 -96 176 +LINE Normal -66 48 -66 16 +LINE Normal -96 32 -66 32 +LINE Normal 96 -16 48 -16 +LINE Normal 96 80 48 80 +LINE Normal 96 160 48 160 +LINE Normal -50 44 -46 52 +LINE Normal -42 44 -46 52 +LINE Normal -42 44 -38 52 +LINE Normal -36 48 -38 52 +LINE Normal -50 44 -52 48 +LINE Normal 3 12 7 20 +LINE Normal 11 12 7 20 +LINE Normal 11 12 15 20 +LINE Normal 17 16 15 20 +LINE Normal 3 12 1 16 +LINE Normal -36 16 1 16 +LINE Normal -36 48 1 48 +LINE Normal 3 44 7 52 +LINE Normal 11 44 7 52 +LINE Normal 11 44 15 52 +LINE Normal 17 48 15 52 +LINE Normal 3 44 1 48 +LINE Normal -50 12 -46 20 +LINE Normal -42 12 -46 20 +LINE Normal -42 12 -38 20 +LINE Normal -36 16 -38 20 +LINE Normal -50 12 -52 16 +LINE Normal 3 124 7 132 +LINE Normal 11 124 7 132 +LINE Normal 11 124 15 132 +LINE Normal 17 128 15 132 +LINE Normal 3 124 1 128 +LINE Normal -36 128 1 128 +LINE Normal -50 124 -46 132 +LINE Normal -42 124 -46 132 +LINE Normal -42 124 -38 132 +LINE Normal -36 128 -38 132 +LINE Normal -50 124 -52 128 +RECTANGLE Normal 96 224 -96 -80 +CIRCLE Normal 49 -15 47 -17 +CIRCLE Normal 50 -14 46 -18 +CIRCLE Normal 51 -13 45 -19 +CIRCLE Normal -23 17 -25 15 +CIRCLE Normal -22 18 -26 14 +CIRCLE Normal -21 19 -27 13 +CIRCLE Normal 49 81 47 79 +CIRCLE Normal 50 82 46 78 +CIRCLE Normal 51 83 45 77 +CIRCLE Normal -23 49 -25 47 +CIRCLE Normal -22 50 -26 46 +CIRCLE Normal -21 51 -27 45 +CIRCLE Normal -23 129 -25 127 +CIRCLE Normal -22 130 -26 126 +CIRCLE Normal -21 131 -27 125 +CIRCLE Normal 49 161 47 159 +CIRCLE Normal 50 162 46 158 +CIRCLE Normal 51 163 45 157 +TEXT 61 -57 Center 2 LT +TEXT -5 -18 Left 2 R +TEXT -5 81 Left 2 G +TEXT -3 161 Left 2 B +WINDOW 3 12 -91 Left 2 +WINDOW 0 -17 -92 Right 2 +SYMATTR Value LT6553 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LT6553 +SYMATTR Description 650MHz Gain of 2 Triple Video Amplifier +PIN -64 224 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 1 +PIN 0 224 BOTTOM 4 +PINATTR PinName DGND +PINATTR SpiceOrder 2 +PIN -96 -32 NONE 8 +PINATTR PinName INR +PINATTR SpiceOrder 3 +PIN -96 32 NONE 8 +PINATTR PinName AGND1 +PINATTR SpiceOrder 4 +PIN -96 96 NONE 8 +PINATTR PinName ING +PINATTR SpiceOrder 5 +PIN -96 128 NONE 8 +PINATTR PinName AGND2 +PINATTR SpiceOrder 6 +PIN -96 176 NONE 8 +PINATTR PinName INB +PINATTR SpiceOrder 7 +PIN 64 224 BOTTOM 4 +PINATTR PinName V- +PINATTR SpiceOrder 8 +PIN 96 160 NONE 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 9 +PIN 0 -80 TOP 4 +PINATTR PinName V+ +PINATTR SpiceOrder 10 +PIN 96 80 NONE 8 +PINATTR PinName OUTG +PINATTR SpiceOrder 11 +PIN 96 -16 NONE 8 +PINATTR PinName OUTR +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/OpAmps/LT6554.asy b/spice/copy/sym/OpAmps/LT6554.asy new file mode 100755 index 0000000..5319da2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6554.asy @@ -0,0 +1,110 @@ +Version 4 +SymbolType BLOCK +LINE Normal -16 9 -16 -44 +LINE Normal 41 -16 -16 9 +LINE Normal -16 -44 41 -16 +LINE Normal -8 -32 -14 -32 +LINE Normal -11 -29 -11 -35 +LINE Normal -8 -3 -14 -3 +LINE Normal -24 -3 -16 -3 +LINE Normal -24 16 -24 -3 +LINE Normal 3 16 -24 16 +LINE Normal 48 16 19 16 +LINE Normal 48 -16 48 16 +LINE Normal 41 -16 48 -16 +LINE Normal -16 -32 -96 -32 +LINE Normal -16 52 -16 110 +LINE Normal 41 80 -16 52 +LINE Normal -16 110 41 80 +LINE Normal -8 96 -14 96 +LINE Normal -11 93 -11 99 +LINE Normal -8 67 -14 67 +LINE Normal -24 67 -16 67 +LINE Normal -24 48 -24 67 +LINE Normal 3 48 -24 48 +LINE Normal 48 80 48 48 +LINE Normal 41 80 48 80 +LINE Normal -16 96 -96 96 +LINE Normal -16 148 -16 206 +LINE Normal 41 176 -16 148 +LINE Normal -16 206 41 176 +LINE Normal -8 192 -14 192 +LINE Normal -11 189 -11 195 +LINE Normal -8 163 -14 163 +LINE Normal -24 163 -16 163 +LINE Normal -24 144 -24 163 +LINE Normal 3 144 -24 144 +LINE Normal 48 176 48 144 +LINE Normal 41 176 48 176 +LINE Normal -16 192 -96 192 +LINE Normal 96 -16 48 -16 +LINE Normal 96 80 48 80 +LINE Normal 96 176 48 176 +LINE Normal 17 148 13 140 +LINE Normal 9 148 13 140 +LINE Normal 9 148 5 140 +LINE Normal 5 140 3 144 +LINE Normal 19 144 17 148 +LINE Normal 17 20 13 12 +LINE Normal 9 20 13 12 +LINE Normal 9 20 5 12 +LINE Normal 5 12 3 16 +LINE Normal 19 16 17 20 +LINE Normal 48 48 19 48 +LINE Normal 17 52 13 44 +LINE Normal 9 52 13 44 +LINE Normal 9 52 5 44 +LINE Normal 5 44 3 48 +LINE Normal 19 48 17 52 +LINE Normal 48 144 19 144 +RECTANGLE Normal 96 240 -96 -80 +CIRCLE Normal 49 -15 47 -17 +CIRCLE Normal 50 -14 46 -18 +CIRCLE Normal 51 -13 45 -19 +CIRCLE Normal 49 81 47 79 +CIRCLE Normal 50 82 46 78 +CIRCLE Normal 51 83 45 77 +CIRCLE Normal 49 177 47 175 +CIRCLE Normal 50 178 46 174 +CIRCLE Normal 51 179 45 173 +TEXT 61 -57 Center 2 LT +TEXT 4 -18 Center 2 R +TEXT 5 81 Center 2 G +TEXT 5 177 Center 2 B +WINDOW 3 11 -93 Left 2 +WINDOW 0 -11 -93 Right 2 +SYMATTR Value LT6554 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LT6554 +SYMATTR Description 650MHz Gain of 1 Triple Video Buffer +PIN -64 240 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 1 +PIN 0 240 BOTTOM 4 +PINATTR PinName DGND +PINATTR SpiceOrder 2 +PIN 0 -80 TOP 4 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 64 240 BOTTOM 4 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN -96 -32 NONE 8 +PINATTR PinName INR +PINATTR SpiceOrder 5 +PIN -96 96 NONE 8 +PINATTR PinName ING +PINATTR SpiceOrder 6 +PIN -96 192 NONE 8 +PINATTR PinName INB +PINATTR SpiceOrder 7 +PIN 96 -16 NONE 8 +PINATTR PinName OUTR +PINATTR SpiceOrder 8 +PIN 96 80 NONE 8 +PINATTR PinName OUTG +PINATTR SpiceOrder 9 +PIN 96 176 NONE 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LT6557.asy b/spice/copy/sym/OpAmps/LT6557.asy new file mode 100755 index 0000000..686f770 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6557.asy @@ -0,0 +1,179 @@ +Version 4 +SymbolType BLOCK +LINE Normal -16 -71 -16 -124 +LINE Normal 41 -96 -16 -71 +LINE Normal -16 -124 41 -96 +LINE Normal -8 -112 -14 -112 +LINE Normal -11 -109 -11 -115 +LINE Normal -8 -83 -14 -83 +LINE Normal -24 -83 -16 -83 +LINE Normal -24 -64 -24 -83 +LINE Normal 17 -64 -24 -64 +LINE Normal -43 -64 -24 -64 +LINE Normal 64 -64 33 -64 +LINE Normal 64 -96 64 -64 +LINE Normal -96 -64 -59 -64 +LINE Normal -16 -112 -96 -112 +LINE Normal 96 -96 41 -96 +LINE Normal 0 -48 0 -78 +LINE Normal -80 -48 0 -48 +LINE Normal -80 -64 -80 -48 +LINE Normal 9 -128 9 -112 +LINE Normal 96 -128 9 -128 +LINE Normal -16 -16 -96 -16 +LINE Normal 96 -32 9 -32 +LINE Normal 96 0 41 0 +LINE Normal -16 25 -16 -28 +LINE Normal 41 0 -16 25 +LINE Normal -16 -28 41 0 +LINE Normal -8 -16 -14 -16 +LINE Normal -11 -13 -11 -19 +LINE Normal -8 13 -14 13 +LINE Normal -24 13 -16 13 +LINE Normal -24 32 -24 13 +LINE Normal 18 32 -24 32 +LINE Normal -43 32 -24 32 +LINE Normal 20 28 18 32 +LINE Normal 64 32 34 32 +LINE Normal 64 0 64 32 +LINE Normal 0 48 0 18 +LINE Normal -80 48 0 48 +LINE Normal -80 32 -80 48 +LINE Normal 9 -32 9 -16 +LINE Normal -96 32 -59 32 +LINE Normal -16 80 -96 80 +LINE Normal 96 64 9 64 +LINE Normal 96 96 41 96 +LINE Normal -16 121 -16 68 +LINE Normal 41 96 -16 121 +LINE Normal -16 68 41 96 +LINE Normal -8 80 -14 80 +LINE Normal -11 83 -11 77 +LINE Normal -8 109 -14 109 +LINE Normal -24 109 -16 109 +LINE Normal -24 128 -24 109 +LINE Normal 17 128 -24 128 +LINE Normal -43 128 -24 128 +LINE Normal 64 128 33 128 +LINE Normal 64 96 64 128 +LINE Normal 0 144 0 114 +LINE Normal -80 144 0 144 +LINE Normal -80 128 -80 144 +LINE Normal 9 64 9 80 +LINE Normal -96 128 -59 128 +LINE Normal 34 32 32 36 +LINE Normal 20 28 24 36 +LINE Normal 28 28 24 36 +LINE Normal 28 28 32 36 +LINE Normal 19 -68 17 -64 +LINE Normal 33 -64 31 -60 +LINE Normal 19 -68 23 -60 +LINE Normal 27 -68 23 -60 +LINE Normal 27 -68 31 -60 +LINE Normal 19 124 17 128 +LINE Normal 33 128 31 132 +LINE Normal 19 124 23 132 +LINE Normal 27 124 23 132 +LINE Normal 27 124 31 132 +LINE Normal -57 -68 -59 -64 +LINE Normal -43 -64 -45 -60 +LINE Normal -57 -68 -53 -60 +LINE Normal -49 -68 -53 -60 +LINE Normal -49 -68 -45 -60 +LINE Normal -57 28 -59 32 +LINE Normal -43 32 -45 36 +LINE Normal -57 28 -53 36 +LINE Normal -49 28 -53 36 +LINE Normal -49 28 -45 36 +LINE Normal -57 124 -59 128 +LINE Normal -43 128 -45 132 +LINE Normal -57 124 -53 132 +LINE Normal -49 124 -53 132 +LINE Normal -49 124 -45 132 +RECTANGLE Normal 96 192 -96 -160 +CIRCLE Normal 65 -95 63 -97 +CIRCLE Normal 66 -94 62 -98 +CIRCLE Normal 67 -93 61 -99 +CIRCLE Normal 65 1 63 -1 +CIRCLE Normal 66 2 62 -2 +CIRCLE Normal 67 3 61 -3 +CIRCLE Normal 65 97 63 95 +CIRCLE Normal 66 98 62 94 +CIRCLE Normal 67 99 61 93 +CIRCLE Normal -23 -63 -25 -65 +CIRCLE Normal -22 -62 -26 -66 +CIRCLE Normal -21 -61 -27 -67 +CIRCLE Normal -79 -63 -81 -65 +CIRCLE Normal -78 -62 -82 -66 +CIRCLE Normal -77 -61 -83 -67 +CIRCLE Normal -23 33 -25 31 +CIRCLE Normal -22 34 -26 30 +CIRCLE Normal -21 35 -27 29 +CIRCLE Normal -79 33 -81 31 +CIRCLE Normal -78 34 -82 30 +CIRCLE Normal -77 35 -83 29 +CIRCLE Normal -23 129 -25 127 +CIRCLE Normal -22 130 -26 126 +CIRCLE Normal -21 131 -27 125 +CIRCLE Normal -79 129 -81 127 +CIRCLE Normal -78 130 -82 126 +CIRCLE Normal -77 131 -83 125 +TEXT -62 -137 Center 2 LT +TEXT -5 -96 Left 2 R +TEXT -5 0 Left 2 G +TEXT -5 96 Left 2 B +WINDOW 3 100 174 Left 2 +WINDOW 0 0 -176 Left 2 +SYMATTR Value LT6557 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6557 +SYMATTR Description 500MHz, 2200V/µs Gain of 2, Single Supply Triple Video Amplifier with Input Bias Control +PIN -64 192 BOTTOM 8 +PINATTR PinName _EN +PINATTR SpiceOrder 1 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 -112 NONE 8 +PINATTR PinName INR +PINATTR SpiceOrder 3 +PIN -96 -64 NONE 8 +PINATTR PinName AGND1 +PINATTR SpiceOrder 4 +PIN -96 -16 NONE 8 +PINATTR PinName ING +PINATTR SpiceOrder 5 +PIN -96 32 NONE 8 +PINATTR PinName GNDG +PINATTR SpiceOrder 6 +PIN -96 80 NONE 8 +PINATTR PinName INB +PINATTR SpiceOrder 7 +PIN -96 128 NONE 8 +PINATTR PinName GNDB +PINATTR SpiceOrder 8 +PIN 96 64 NONE 8 +PINATTR PinName V+B +PINATTR SpiceOrder 9 +PIN 96 96 NONE 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 10 +PIN 96 -32 NONE 8 +PINATTR PinName V+G +PINATTR SpiceOrder 11 +PIN 96 0 NONE 8 +PINATTR PinName OUTG +PINATTR SpiceOrder 12 +PIN 96 -128 NONE 8 +PINATTR PinName V+R +PINATTR SpiceOrder 13 +PIN 96 -96 NONE 8 +PINATTR PinName OUTR +PINATTR SpiceOrder 14 +PIN -16 -160 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 15 +PIN 64 192 BOTTOM 8 +PINATTR PinName BCV +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/OpAmps/LT6558.asy b/spice/copy/sym/OpAmps/LT6558.asy new file mode 100755 index 0000000..437a405 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6558.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType BLOCK +LINE Normal -16 -71 -16 -124 +LINE Normal 41 -96 -16 -71 +LINE Normal -16 -124 41 -96 +LINE Normal -8 -112 -14 -112 +LINE Normal -11 -109 -11 -115 +LINE Normal -8 -83 -14 -83 +LINE Normal -24 -83 -16 -83 +LINE Normal -24 -48 -24 -83 +LINE Normal 64 -48 -24 -48 +LINE Normal 64 -96 64 -48 +LINE Normal -16 -112 -96 -112 +LINE Normal 96 -96 41 -96 +LINE Normal 0 -64 0 -78 +LINE Normal -96 -64 0 -64 +LINE Normal 9 -128 9 -112 +LINE Normal 96 -128 9 -128 +LINE Normal -16 -16 -96 -16 +LINE Normal 96 -32 9 -32 +LINE Normal 96 0 41 0 +LINE Normal -16 25 -16 -28 +LINE Normal 41 0 -16 25 +LINE Normal -16 -28 41 0 +LINE Normal -8 -16 -14 -16 +LINE Normal -11 -13 -11 -19 +LINE Normal -8 13 -14 13 +LINE Normal -24 13 -16 13 +LINE Normal -24 48 -24 13 +LINE Normal 64 48 -24 48 +LINE Normal 64 0 64 48 +LINE Normal 0 32 0 18 +LINE Normal -96 32 0 32 +LINE Normal 9 -32 9 -16 +LINE Normal -16 80 -96 80 +LINE Normal 96 64 9 64 +LINE Normal 96 96 41 96 +LINE Normal -16 121 -16 68 +LINE Normal 41 96 -16 121 +LINE Normal -16 68 41 96 +LINE Normal -8 80 -14 80 +LINE Normal -11 83 -11 77 +LINE Normal -8 109 -14 109 +LINE Normal -24 109 -16 109 +LINE Normal -24 144 -24 109 +LINE Normal 64 144 -24 144 +LINE Normal 64 96 64 144 +LINE Normal 0 128 0 114 +LINE Normal -96 128 0 128 +LINE Normal 9 64 9 80 +RECTANGLE Normal 96 192 -96 -160 +CIRCLE Normal 65 -95 63 -97 +CIRCLE Normal 66 -94 62 -98 +CIRCLE Normal 67 -93 61 -99 +CIRCLE Normal 65 1 63 -1 +CIRCLE Normal 66 2 62 -2 +CIRCLE Normal 67 3 61 -3 +CIRCLE Normal 65 97 63 95 +CIRCLE Normal 66 98 62 94 +CIRCLE Normal 67 99 61 93 +TEXT -62 -137 Center 2 LT +TEXT -5 -96 Left 2 R +TEXT -5 0 Left 2 G +TEXT -5 96 Left 2 B +WINDOW 3 79 207 Left 2 +WINDOW 0 2 -171 Left 2 +SYMATTR Value LT6558 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6558 +SYMATTR Description 550MHz, 2200V/µs Gain of 1, Single Supply Triple Video Amplifier with Input Bias Control +PIN -64 192 BOTTOM 8 +PINATTR PinName _EN +PINATTR SpiceOrder 1 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 -112 NONE 8 +PINATTR PinName INR +PINATTR SpiceOrder 3 +PIN -96 -64 NONE 8 +PINATTR PinName AGND1 +PINATTR SpiceOrder 4 +PIN -96 -16 NONE 8 +PINATTR PinName ING +PINATTR SpiceOrder 5 +PIN -96 32 NONE 8 +PINATTR PinName GNDG +PINATTR SpiceOrder 6 +PIN -96 80 NONE 8 +PINATTR PinName INB +PINATTR SpiceOrder 7 +PIN -96 128 NONE 8 +PINATTR PinName GNDB +PINATTR SpiceOrder 8 +PIN 96 64 NONE 8 +PINATTR PinName V+B +PINATTR SpiceOrder 9 +PIN 96 96 NONE 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 10 +PIN 96 -32 NONE 8 +PINATTR PinName V+G +PINATTR SpiceOrder 11 +PIN 96 0 NONE 8 +PINATTR PinName OUTG +PINATTR SpiceOrder 12 +PIN 96 -128 NONE 8 +PINATTR PinName V+R +PINATTR SpiceOrder 13 +PIN 96 -96 NONE 8 +PINATTR PinName OUTR +PINATTR SpiceOrder 14 +PIN -16 -160 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 15 +PIN 64 192 BOTTOM 8 +PINATTR PinName BCV +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/OpAmps/LT6559.asy b/spice/copy/sym/OpAmps/LT6559.asy new file mode 100755 index 0000000..4d4ea11 --- /dev/null +++ b/spice/copy/sym/OpAmps/LT6559.asy @@ -0,0 +1,42 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 44 28 44 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 52 8 44 8 +WINDOW 0 48 -48 Left 2 +WINDOW 3 57 48 Left 2 +SYMATTR Value LT6559 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6559 +SYMATTR Description Low Cost 5V/±5V 300MHz Triple Video Amplifier in QFN +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC1043.asy b/spice/copy/sym/OpAmps/LTC1043.asy new file mode 100755 index 0000000..8a45fc8 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1043.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 16 -176 Left 2 +WINDOW 3 16 176 Left 2 +SYMATTR Value LTC1043 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1043 +SYMATTR Description Dual Instrumentation Switched Capacitor Building Block +PIN -128 -96 LEFT 8 +PINATTR PinName S1A +PINATTR SpiceOrder 1 +PIN 128 -96 RIGHT 8 +PINATTR PinName S2A +PINATTR SpiceOrder 2 +PIN 128 32 RIGHT 8 +PINATTR PinName Ca+ +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName S3A +PINATTR SpiceOrder 4 +PIN 128 -32 RIGHT 8 +PINATTR PinName S4A +PINATTR SpiceOrder 5 +PIN 128 96 RIGHT 8 +PINATTR PinName Ca- +PINATTR SpiceOrder 6 +PIN -128 96 LEFT 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 +PIN 0 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/OpAmps/LTC1047.asy b/spice/copy/sym/OpAmps/LTC1047.asy new file mode 100755 index 0000000..252ea58 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1047.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1047 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1047 +SYMATTR Description Dual µPower Chopper Stabilized Operational Amplifier with Internal Capacitors +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1049.asy b/spice/copy/sym/OpAmps/LTC1049.asy new file mode 100755 index 0000000..77b4afe --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1049.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1049 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1049 +SYMATTR Description Precision Low Power Zero-Drift Operational Amplifier with Internal Capacitors +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1050.asy b/spice/copy/sym/OpAmps/LTC1050.asy new file mode 100755 index 0000000..19aa0b0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1050.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1050 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1050 +SYMATTR Description Precision Zero-Drift Operational Amplifier with Internal Capacitors +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1050A.asy b/spice/copy/sym/OpAmps/LTC1050A.asy new file mode 100755 index 0000000..0d2e993 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1050A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1050A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1050 +SYMATTR Description Precision Zero-Drift Operational Amplifier with Internal Capacitors +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1051.asy b/spice/copy/sym/OpAmps/LTC1051.asy new file mode 100755 index 0000000..7441705 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1051.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1051 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1051 +SYMATTR Description Dual Precision Zero-Drift Operational Amplifier with Internal Capacitors +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1051A.asy b/spice/copy/sym/OpAmps/LTC1051A.asy new file mode 100755 index 0000000..ec03984 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1051A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1051A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1051 +SYMATTR Description Dual Precision Zero-Drift Operational Amplifier with Internal Capacitors +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1052.asy b/spice/copy/sym/OpAmps/LTC1052.asy new file mode 100755 index 0000000..186c996 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1052.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1052 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1052 +SYMATTR Description Chopper-Stabilized Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1052CS.asy b/spice/copy/sym/OpAmps/LTC1052CS.asy new file mode 100755 index 0000000..c225581 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1052CS.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1052CS +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1052 +SYMATTR Description Chopper-Stabilized Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1053.asy b/spice/copy/sym/OpAmps/LTC1053.asy new file mode 100755 index 0000000..f1ac81c --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1053.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1053 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1052 +SYMATTR Description Quad Precision Zero-Drift Operational Amplifier with Internal Capacitors +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1100.asy b/spice/copy/sym/OpAmps/LTC1100.asy new file mode 100755 index 0000000..d31e905 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1100.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC1100 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1100 +SYMATTR Description Precision, Chopper-Stabilized Instrumentation Amplifier +PIN -128 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName CMRR +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC1100A.asy b/spice/copy/sym/OpAmps/LTC1100A.asy new file mode 100755 index 0000000..db96276 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1100A.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC1100A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1100 +SYMATTR Description Precision, Chopper-Stabilized Instrumentation Amplifier +PIN -128 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName CMRR +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC1100CS.asy b/spice/copy/sym/OpAmps/LTC1100CS.asy new file mode 100755 index 0000000..58ad5f5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1100CS.asy @@ -0,0 +1,131 @@ +Version 4 +SymbolType BLOCK +LINE Normal -114 -96 -208 -96 +LINE Normal -17 -96 -48 -96 +LINE Normal -17 -48 -17 -112 +LINE Normal 63 -80 -17 -48 +LINE Normal -17 -112 63 -80 +LINE Normal -32 -176 -32 -96 +LINE Normal 15 -128 -32 -128 +LINE Normal 80 -128 39 -128 +LINE Normal 80 -80 80 -128 +LINE Normal -3 -64 -11 -64 +LINE Normal -7 -60 -7 -68 +LINE Normal -3 -96 -11 -96 +LINE Normal -17 -64 -208 -64 +LINE Normal 93 -80 80 -80 +LINE Normal 208 -80 117 -80 +LINE Normal -51 -88 -48 -96 +LINE Normal -51 -88 -57 -104 +LINE Normal -63 -88 -57 -104 +LINE Normal -63 -88 -69 -104 +LINE Normal -72 -96 -69 -104 +LINE Normal 36 -120 39 -128 +LINE Normal 36 -120 30 -136 +LINE Normal 24 -120 30 -136 +LINE Normal 24 -120 18 -136 +LINE Normal 15 -128 18 -136 +LINE Normal 114 -72 117 -80 +LINE Normal 114 -72 108 -88 +LINE Normal 102 -72 108 -88 +LINE Normal 102 -72 96 -88 +LINE Normal 93 -80 96 -88 +LINE Normal -93 -88 -90 -96 +LINE Normal -93 -88 -99 -104 +LINE Normal -105 -88 -99 -104 +LINE Normal -105 -88 -111 -104 +LINE Normal -114 -96 -111 -104 +LINE Normal -72 -96 -90 -96 +LINE Normal 80 -80 63 -80 +LINE Normal -17 64 -32 64 +LINE Normal -17 112 -17 48 +LINE Normal 63 80 -17 112 +LINE Normal -17 48 63 80 +LINE Normal -8 32 -32 32 +LINE Normal 80 32 65 32 +LINE Normal 80 80 80 32 +LINE Normal -3 96 -11 96 +LINE Normal -7 100 -7 92 +LINE Normal -3 64 -11 64 +LINE Normal 62 40 65 32 +LINE Normal 62 40 56 24 +LINE Normal 50 40 56 24 +LINE Normal 50 40 44 24 +LINE Normal 41 32 44 24 +LINE Normal 208 80 63 80 +LINE Normal 13 40 16 32 +LINE Normal 13 40 7 24 +LINE Normal 1 40 7 24 +LINE Normal 1 40 -5 24 +LINE Normal -8 32 -5 24 +LINE Normal 41 32 16 32 +LINE Normal 128 -32 -32 -32 +LINE Normal -32 -32 -32 64 +LINE Normal 128 -80 128 -32 +LINE Normal -80 -176 -80 -96 +LINE Normal 28 0 28 32 +LINE Normal 208 0 28 0 +LINE Normal -17 96 -207 96 +RECTANGLE Normal 208 176 -208 -176 +CIRCLE Normal -30 -94 -34 -98 +CIRCLE Normal -29 -93 -35 -99 +CIRCLE Normal -31 -95 -33 -97 +CIRCLE Normal 82 -78 78 -82 +CIRCLE Normal 83 -77 77 -83 +CIRCLE Normal 81 -79 79 -81 +CIRCLE Normal -30 34 -34 30 +CIRCLE Normal -29 35 -35 29 +CIRCLE Normal -31 33 -33 31 +CIRCLE Normal 82 82 78 78 +CIRCLE Normal 83 83 77 77 +CIRCLE Normal 81 81 79 79 +CIRCLE Normal 130 -78 126 -82 +CIRCLE Normal 131 -77 125 -83 +CIRCLE Normal 129 -79 127 -81 +CIRCLE Normal 30 34 26 30 +CIRCLE Normal 31 35 25 29 +CIRCLE Normal 29 33 27 31 +CIRCLE Normal -78 -94 -82 -98 +CIRCLE Normal -77 -93 -83 -99 +CIRCLE Normal -79 -95 -81 -97 +CIRCLE Normal -30 -126 -34 -130 +CIRCLE Normal -29 -125 -35 -131 +CIRCLE Normal -31 -127 -33 -129 +TEXT 206 -95 Right 2 COMP +TEXT -206 -117 Left 2 GND +TEXT -206 -78 Left 2 -IN +TEXT -81 -164 Right 2 G10(3) +TEXT 206 67 Right 2 OUT +TEXT 206 -16 Right 2 G10(14) +TEXT -207 81 Left 2 +IN +TEXT -30 -164 Left 2 CMRR +WINDOW 3 96 192 Left 2 +WINDOW 0 144 -192 Left 2 +SYMATTR Value LTC1100CS +SYMATTR Prefix X +SYMATTR SpiceModel LTC1100CS.sub +SYMATTR Value2 LTC1100CS +SYMATTR Description Precision, Zero-Drift Instrumentation Amplifier +PIN -208 -96 NONE 8 +PINATTR PinName -INA +PINATTR SpiceOrder 2 +PIN -80 -176 TOP 4 +PINATTR SpiceOrder 3 +PIN -32 -176 TOP 4 +PINATTR SpiceOrder 4 +PIN -208 -64 NONE 8 +PINATTR SpiceOrder 6 +PIN 80 176 BOTTOM 4 +PINATTR PinName V- +PINATTR SpiceOrder 7 +PIN 80 -176 TOP 4 +PINATTR PinName V+ +PINATTR SpiceOrder 10 +PIN -208 96 NONE 8 +PINATTR SpiceOrder 11 +PIN 208 -80 RIGHT 8 +PINATTR SpiceOrder 13 +PIN 208 0 NONE 8 +PINATTR SpiceOrder 14 +PIN 208 80 NONE 8 +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/OpAmps/LTC1150.asy b/spice/copy/sym/OpAmps/LTC1150.asy new file mode 100755 index 0000000..6562392 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1150.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1150 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1150 +SYMATTR Description +-15V Zero-Drift Operational Amplifier with Internal Capacitors +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1151.asy b/spice/copy/sym/OpAmps/LTC1151.asy new file mode 100755 index 0000000..9a68823 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1151.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1151 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1151 +SYMATTR Description Dual +-15V Zero-Drift Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1152.asy b/spice/copy/sym/OpAmps/LTC1152.asy new file mode 100755 index 0000000..52c8876 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1152.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC1152 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1152 +SYMATTR Description Rail-to-Rail Input and Output Zero-Drift Operational Amplifier +PIN -128 32 LEFT 8 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 128 -32 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 5 +PIN 128 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 6 +PIN -128 -96 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Cp +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC1250.asy b/spice/copy/sym/OpAmps/LTC1250.asy new file mode 100755 index 0000000..5eb080b --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1250.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC1250 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1250 +SYMATTR Description Very Low Noise Zero-Drift Bridge Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC1541.asy b/spice/copy/sym/OpAmps/LTC1541.asy new file mode 100755 index 0000000..b775993 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1541.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -176 -128 176 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC1541 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1541 +SYMATTR Description µPower Operational Amplifier, Comparator and Reference +PIN -176 -96 LEFT 8 +PINATTR PinName AMPOUT +PINATTR SpiceOrder 1 +PIN -176 -32 LEFT 8 +PINATTR PinName AMPIN- +PINATTR SpiceOrder 2 +PIN -176 32 LEFT 8 +PINATTR PinName AMPIN+ +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 176 96 RIGHT 8 +PINATTR PinName COMPIN+ +PINATTR SpiceOrder 5 +PIN 176 32 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN 176 -32 RIGHT 8 +PINATTR PinName COMPOUT +PINATTR SpiceOrder 7 +PIN 176 -96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC1542.asy b/spice/copy/sym/OpAmps/LTC1542.asy new file mode 100755 index 0000000..af0fcbd --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1542.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -176 -128 176 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC1542 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1542 +SYMATTR Description µPower Operational Amplifier and Comparator +PIN -176 -96 LEFT 8 +PINATTR PinName AMPOUT +PINATTR SpiceOrder 1 +PIN -176 -32 LEFT 8 +PINATTR PinName AMPIN- +PINATTR SpiceOrder 2 +PIN -176 32 LEFT 8 +PINATTR PinName AMPIN+ +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 176 96 RIGHT 8 +PINATTR PinName COMPIN+ +PINATTR SpiceOrder 5 +PIN 176 32 RIGHT 8 +PINATTR PinName COMPIN- +PINATTR SpiceOrder 6 +PIN 176 -32 RIGHT 8 +PINATTR PinName COMPOUT +PINATTR SpiceOrder 7 +PIN 176 -96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC1992-1.asy b/spice/copy/sym/OpAmps/LTC1992-1.asy new file mode 100755 index 0000000..d029357 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1992-1.asy @@ -0,0 +1,69 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -48 -56 -48 +LINE Normal -45 48 -55 48 +LINE Normal -50 53 -50 43 +LINE Normal 32 -32 96 -32 +LINE Normal 58 32 96 32 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal -27 55 -37 55 +LINE Normal -52 22 -56 8 +LINE Normal -48 8 -52 22 +LINE Normal -47 22 -47 17 +LINE Normal -43 22 -47 22 +LINE Normal -43 17 -43 22 +LINE Normal -47 17 -43 17 +LINE Normal -40 17 -36 17 +LINE Normal -40 22 -40 17 +LINE Normal -36 22 -40 22 +LINE Normal -33 17 -33 22 +LINE Normal -31 20 -33 17 +LINE Normal -29 17 -31 20 +LINE Normal -29 22 -29 17 +LINE Normal -52 -10 -56 -24 +LINE Normal -48 -24 -52 -10 +LINE Normal -47 -15 -47 -10 +LINE Normal -45 -12 -47 -15 +LINE Normal -43 -15 -45 -12 +LINE Normal -43 -10 -43 -15 +LINE Normal -40 -10 -40 -15 +LINE Normal -37 -10 -37 -15 +CIRCLE Normal 58 40 42 24 +ARC Normal -34 -15 -39 -10 -37 -10 -37 -15 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LTC1992-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.LIB +SYMATTR Value2 LTC1992-1 +SYMATTR Description Low Power, Fully Differential I/O Amplifier +PIN -64 -48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -64 16 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 -16 NONE 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN -64 48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC1992-10.asy b/spice/copy/sym/OpAmps/LTC1992-10.asy new file mode 100755 index 0000000..70afa1b --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1992-10.asy @@ -0,0 +1,69 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -48 -56 -48 +LINE Normal -45 48 -55 48 +LINE Normal -50 53 -50 43 +LINE Normal 32 -32 96 -32 +LINE Normal 58 32 96 32 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal -27 55 -37 55 +LINE Normal -52 22 -56 8 +LINE Normal -48 8 -52 22 +LINE Normal -47 22 -47 17 +LINE Normal -43 22 -47 22 +LINE Normal -43 17 -43 22 +LINE Normal -47 17 -43 17 +LINE Normal -40 17 -36 17 +LINE Normal -40 22 -40 17 +LINE Normal -36 22 -40 22 +LINE Normal -33 17 -33 22 +LINE Normal -31 20 -33 17 +LINE Normal -29 17 -31 20 +LINE Normal -29 22 -29 17 +LINE Normal -52 -10 -56 -24 +LINE Normal -48 -24 -52 -10 +LINE Normal -47 -15 -47 -10 +LINE Normal -45 -12 -47 -15 +LINE Normal -43 -15 -45 -12 +LINE Normal -43 -10 -43 -15 +LINE Normal -40 -10 -40 -15 +LINE Normal -37 -10 -37 -15 +CIRCLE Normal 58 40 42 24 +ARC Normal -34 -15 -39 -10 -37 -10 -37 -15 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LTC1992-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.LIB +SYMATTR Value2 LTC1992-10 +SYMATTR Description Low Power, Fully Differential I/O Amplifier +PIN -64 -48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -64 16 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 -16 NONE 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN -64 48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC1992-2.asy b/spice/copy/sym/OpAmps/LTC1992-2.asy new file mode 100755 index 0000000..056c9f0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1992-2.asy @@ -0,0 +1,69 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -48 -56 -48 +LINE Normal -45 48 -55 48 +LINE Normal -50 53 -50 43 +LINE Normal 32 -32 96 -32 +LINE Normal 58 32 96 32 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal -27 55 -37 55 +LINE Normal -52 22 -56 8 +LINE Normal -48 8 -52 22 +LINE Normal -47 22 -47 17 +LINE Normal -43 22 -47 22 +LINE Normal -43 17 -43 22 +LINE Normal -47 17 -43 17 +LINE Normal -40 17 -36 17 +LINE Normal -40 22 -40 17 +LINE Normal -36 22 -40 22 +LINE Normal -33 17 -33 22 +LINE Normal -31 20 -33 17 +LINE Normal -29 17 -31 20 +LINE Normal -29 22 -29 17 +LINE Normal -52 -10 -56 -24 +LINE Normal -48 -24 -52 -10 +LINE Normal -47 -15 -47 -10 +LINE Normal -45 -12 -47 -15 +LINE Normal -43 -15 -45 -12 +LINE Normal -43 -10 -43 -15 +LINE Normal -40 -10 -40 -15 +LINE Normal -37 -10 -37 -15 +CIRCLE Normal 58 40 42 24 +ARC Normal -34 -15 -39 -10 -37 -10 -37 -15 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LTC1992-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.LIB +SYMATTR Value2 LTC1992-2 +SYMATTR Description Low Power, Fully Differential I/O Amplifier +PIN -64 -48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -64 16 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 -16 NONE 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN -64 48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC1992-5.asy b/spice/copy/sym/OpAmps/LTC1992-5.asy new file mode 100755 index 0000000..1bb65b2 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1992-5.asy @@ -0,0 +1,69 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -48 -56 -48 +LINE Normal -45 48 -55 48 +LINE Normal -50 53 -50 43 +LINE Normal 32 -32 96 -32 +LINE Normal 58 32 96 32 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal -27 55 -37 55 +LINE Normal -52 22 -56 8 +LINE Normal -48 8 -52 22 +LINE Normal -47 22 -47 17 +LINE Normal -43 22 -47 22 +LINE Normal -43 17 -43 22 +LINE Normal -47 17 -43 17 +LINE Normal -40 17 -36 17 +LINE Normal -40 22 -40 17 +LINE Normal -36 22 -40 22 +LINE Normal -33 17 -33 22 +LINE Normal -31 20 -33 17 +LINE Normal -29 17 -31 20 +LINE Normal -29 22 -29 17 +LINE Normal -52 -10 -56 -24 +LINE Normal -48 -24 -52 -10 +LINE Normal -47 -15 -47 -10 +LINE Normal -45 -12 -47 -15 +LINE Normal -43 -15 -45 -12 +LINE Normal -43 -10 -43 -15 +LINE Normal -40 -10 -40 -15 +LINE Normal -37 -10 -37 -15 +CIRCLE Normal 58 40 42 24 +ARC Normal -34 -15 -39 -10 -37 -10 -37 -15 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LTC1992-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.LIB +SYMATTR Value2 LTC1992-5 +SYMATTR Description Low Power, Fully Differential I/O Amplifier +PIN -64 -48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -64 16 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 -16 NONE 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN -64 48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC1992.asy b/spice/copy/sym/OpAmps/LTC1992.asy new file mode 100755 index 0000000..7434775 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC1992.asy @@ -0,0 +1,69 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -48 -56 -48 +LINE Normal -45 48 -55 48 +LINE Normal -50 53 -50 43 +LINE Normal 32 -32 96 -32 +LINE Normal 58 32 96 32 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal -27 55 -37 55 +LINE Normal -52 22 -56 8 +LINE Normal -48 8 -52 22 +LINE Normal -47 22 -47 17 +LINE Normal -43 22 -47 22 +LINE Normal -43 17 -43 22 +LINE Normal -47 17 -43 17 +LINE Normal -40 17 -36 17 +LINE Normal -40 22 -40 17 +LINE Normal -36 22 -40 22 +LINE Normal -33 17 -33 22 +LINE Normal -31 20 -33 17 +LINE Normal -29 17 -31 20 +LINE Normal -29 22 -29 17 +LINE Normal -52 -10 -56 -24 +LINE Normal -48 -24 -52 -10 +LINE Normal -47 -15 -47 -10 +LINE Normal -45 -12 -47 -15 +LINE Normal -43 -15 -45 -12 +LINE Normal -43 -10 -43 -15 +LINE Normal -40 -10 -40 -15 +LINE Normal -37 -10 -37 -15 +CIRCLE Normal 58 40 42 24 +ARC Normal -34 -15 -39 -10 -37 -10 -37 -15 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LTC1992 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.LIB +SYMATTR Value2 LTC1992 +SYMATTR Description Low Power, Fully Differential I/O Amplifier +PIN -64 -48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -64 16 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 -16 NONE 8 +PINATTR PinName VMID +PINATTR SpiceOrder 7 +PIN -64 48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC2050.asy b/spice/copy/sym/OpAmps/LTC2050.asy new file mode 100755 index 0000000..614c8cb --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2050.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 52 6 44 6 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC2050 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC2050 +SYMATTR Description Low Noise, Zero-Drift Operational Amplifier in SOT-23 +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC2050HV.asy b/spice/copy/sym/OpAmps/LTC2050HV.asy new file mode 100755 index 0000000..42617c7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2050HV.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 52 6 44 6 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC2050HV +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC2050 +SYMATTR Description Low Noise, Zero-Drift Operational Amplifier in SOT-23 +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC2051.asy b/spice/copy/sym/OpAmps/LTC2051.asy new file mode 100755 index 0000000..db3bc46 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2051.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 52 6 44 6 +WINDOW 0 16 -64 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC2051 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC2050 +SYMATTR Description Low Noise, Zero-Drift Operational Amplifier in SOT-23 +PIN -32 32 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC2052.asy b/spice/copy/sym/OpAmps/LTC2052.asy new file mode 100755 index 0000000..cfce5ff --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2052.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC2052 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LTC2052 +SYMATTR Description Quad Zero-Drift Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC2053.asy b/spice/copy/sym/OpAmps/LTC2053.asy new file mode 100755 index 0000000..9cefada --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2053.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType BLOCK +LINE Normal -69 -3 -69 -10 +LINE Normal -62 -3 -76 -3 +LINE Normal -62 3 -76 3 +LINE Normal -69 10 -69 3 +LINE Normal -77 -16 -112 -16 +LINE Normal -77 16 -112 16 +LINE Normal -75 -16 -69 -10 +LINE Normal -75 -13 -75 -16 +LINE Normal -72 -16 -75 -16 +LINE Normal -75 16 -69 10 +LINE Normal -75 13 -75 16 +LINE Normal -72 16 -75 16 +LINE Normal 0 -16 -61 -16 +LINE Normal -32 -3 -32 -16 +LINE Normal -25 -3 -39 -3 +LINE Normal -25 3 -39 3 +LINE Normal -32 16 -32 3 +LINE Normal -32 16 -61 16 +LINE Normal 0 32 0 -32 +LINE Normal 64 0 0 32 +LINE Normal 0 -32 64 0 +LINE Normal 8 -16 4 -16 +LINE Normal 6 -14 6 -18 +LINE Normal 8 16 4 16 +LINE Normal -32 64 -32 16 +LINE Normal -16 16 0 16 +LINE Normal -16 64 -16 16 +LINE Normal 80 0 64 0 +LINE Normal 16 24 16 64 +LINE Normal 16 -24 16 -64 +LINE Normal 23 -55 19 -55 +LINE Normal 21 -53 21 -57 +LINE Normal 24 57 20 57 +LINE Normal -48 59 -48 53 +LINE Normal -34 59 -48 59 +LINE Normal -41 47 -41 50 +LINE Normal -41 53 -41 59 +LINE Normal -41 53 -48 53 +LINE Normal -34 53 -41 57 +LINE Normal -34 50 -48 50 +LINE Normal -48 44 -48 50 +LINE Normal -34 44 -34 50 +LINE Normal -41 37 -41 41 +LINE Normal -34 41 -48 41 +LINE Normal -48 34 -48 41 +RECTANGLE Normal 80 64 -112 -64 +CIRCLE Normal -31 17 -33 15 +CIRCLE Normal -30 18 -34 14 +CIRCLE Normal -29 19 -35 13 +CIRCLE Normal -31 -15 -33 -17 +CIRCLE Normal -30 -14 -34 -18 +CIRCLE Normal -29 -13 -35 -19 +TEXT 48 -45 Center 2 LT +WINDOW 3 -51 -44 Center 2 +WINDOW 0 30 -75 Left 2 +SYMATTR Value LTC2053 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC2053 +SYMATTR Description Precision, Rail-to-Rail, Zero-Drift Instrumentation Amplifier with Resistor-Programmable Gain +PIN 48 64 BOTTOM 4 +PINATTR PinName _E +PINATTR SpiceOrder 1 +PIN -112 16 NONE 8 +PINATTR PinName -IN +PINATTR SpiceOrder 2 +PIN -112 -16 NONE 8 +PINATTR PinName +IN +PINATTR SpiceOrder 3 +PIN 16 64 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN -32 64 NONE 8 +PINATTR PinName REF +PINATTR SpiceOrder 5 +PIN -16 64 NONE 8 +PINATTR PinName RG +PINATTR SpiceOrder 6 +PIN 80 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 16 -64 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC2054.asy b/spice/copy/sym/OpAmps/LTC2054.asy new file mode 100755 index 0000000..0f9a590 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2054.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC2054 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LTC2054 +SYMATTR Description Low Power Zero-Drift Op Amp in SOT-23 +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC2055.asy b/spice/copy/sym/OpAmps/LTC2055.asy new file mode 100755 index 0000000..c0982df --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2055.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC2055 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LTC2054 +SYMATTR Description Dual Low Power Zero-Drift Op Amp in SOT-23 +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC2057.asy b/spice/copy/sym/OpAmps/LTC2057.asy new file mode 100755 index 0000000..a4b5e70 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2057.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType BLOCK +LINE Normal -160 144 -160 -144 +LINE Normal 96 0 -160 144 +LINE Normal -160 -144 96 0 +LINE Normal 96 0 112 0 +LINE Normal -128 144 -128 126 +LINE Normal -128 -126 -128 -143 +LINE Normal -64 112 -64 90 +LINE Normal -64 -90 -64 -112 +WINDOW 3 16 80 Left 2 +WINDOW 0 16 -80 Left 2 +SYMATTR Value LTC2057 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC2057 +SYMATTR Description High Voltage, Low Noise Zero-Drift Operation Amplifier +PIN -64 -112 VRIGHT 30 +PINATTR PinName _SD +PINATTR SpiceOrder 1 +PIN -160 -32 LEFT 8 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -160 32 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -128 144 VLEFT 40 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 50 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -128 -144 VRIGHT 30 +PINATTR PinName V+ +PINATTR SpiceOrder 6 +PIN -64 112 VLEFT 30 +PINATTR PinName SDCOM +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LTC2057HV.asy b/spice/copy/sym/OpAmps/LTC2057HV.asy new file mode 100755 index 0000000..7ad6e72 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2057HV.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType BLOCK +LINE Normal -160 144 -160 -144 +LINE Normal 96 0 -160 144 +LINE Normal -160 -144 96 0 +LINE Normal 96 0 112 0 +LINE Normal -128 144 -128 126 +LINE Normal -128 -126 -128 -143 +LINE Normal -64 112 -64 90 +LINE Normal -64 -90 -64 -112 +WINDOW 3 16 80 Left 2 +WINDOW 0 16 -80 Left 2 +SYMATTR Value LTC2057HV +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC2057 +SYMATTR Description High Voltage, Low Noise Zero-Drift Operation Amplifier +PIN -64 -112 VRIGHT 30 +PINATTR PinName _SD +PINATTR SpiceOrder 1 +PIN -160 -32 LEFT 8 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -160 32 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -128 144 VLEFT 40 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 50 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -128 -144 VRIGHT 30 +PINATTR PinName V+ +PINATTR SpiceOrder 6 +PIN -64 112 VLEFT 30 +PINATTR PinName SDCOM +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LTC2058.asy b/spice/copy/sym/OpAmps/LTC2058.asy new file mode 100755 index 0000000..e2f5260 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2058.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType BLOCK +LINE Normal -160 144 -160 -144 +LINE Normal 96 0 -160 144 +LINE Normal -160 -144 96 0 +LINE Normal 96 0 112 0 +LINE Normal -128 144 -128 126 +LINE Normal -128 -126 -128 -143 +LINE Normal -64 112 -64 90 +LINE Normal -64 -90 -64 -112 +WINDOW 3 16 80 Left 2 +WINDOW 0 16 -80 Left 2 +SYMATTR Value LTC2058 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC2058 +SYMATTR Description Dual 36V, Low Noise Zero-Drift Operational Amplifier +PIN -64 -112 VRIGHT 30 +PINATTR PinName _SD +PINATTR SpiceOrder 1 +PIN -160 -32 LEFT 8 +PINATTR PinName -IN +PINATTR SpiceOrder 2 +PIN -160 32 LEFT 8 +PINATTR PinName +IN +PINATTR SpiceOrder 3 +PIN -128 144 VLEFT 40 +PINATTR PinName -V +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 50 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -128 -144 VRIGHT 30 +PINATTR PinName +V +PINATTR SpiceOrder 6 +PIN -64 112 VLEFT 30 +PINATTR PinName SDCOM +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LTC2063.asy b/spice/copy/sym/OpAmps/LTC2063.asy new file mode 100755 index 0000000..c319cbc --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2063.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 7 43 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC2063 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC2063 +SYMATTR Description 2µA Supply Current, Low Ib, Zero-Drift Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC2064.asy b/spice/copy/sym/OpAmps/LTC2064.asy new file mode 100755 index 0000000..1388540 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2064.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 7 43 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC2064 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC2063 +SYMATTR Description Dual 2µA Supply Current, Low Ib, Zero-Drift Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC2065.asy b/spice/copy/sym/OpAmps/LTC2065.asy new file mode 100755 index 0000000..a73d39e --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2065.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -16 32 -16 24 +LINE Normal -16 -32 -16 -24 +LINE Normal 16 32 16 8 +LINE Normal -27 -16 -19 -16 +LINE Normal -27 16 -19 16 +LINE Normal -23 12 -23 20 +LINE Normal -8 -32 0 -32 +LINE Normal -4 -28 -4 -36 +LINE Normal -8 32 0 32 +TEXT 18 20 Left 1 _S +WINDOW 0 14 -25 Left 2 +WINDOW 3 30 39 Left 2 +SYMATTR Value LTC2065 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC2063 +SYMATTR Description Quad 2µA Supply Current, Low Ib, Zero-Drift Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -16 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN -16 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC2066.asy b/spice/copy/sym/OpAmps/LTC2066.asy new file mode 100755 index 0000000..a05dc11 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2066.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 4 42 4 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC2066 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC2066 +SYMATTR Description 10µA Supply Current, Low IB, Zero-Drift Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC2067.asy b/spice/copy/sym/OpAmps/LTC2067.asy new file mode 100755 index 0000000..f00fd23 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2067.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 4 42 4 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC2067 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC2066 +SYMATTR Description Dual 10µA Supply Current, Low IB, Zero-Drift Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC2068.asy b/spice/copy/sym/OpAmps/LTC2068.asy new file mode 100755 index 0000000..061e3ac --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC2068.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -16 32 -16 24 +LINE Normal -16 -32 -16 -24 +LINE Normal 16 32 16 8 +LINE Normal -27 -16 -19 -16 +LINE Normal -27 16 -19 16 +LINE Normal -23 12 -23 20 +LINE Normal -8 -32 0 -32 +LINE Normal -4 -28 -4 -36 +LINE Normal -8 32 0 32 +TEXT 18 20 Left 1 _S +WINDOW 0 14 -25 Left 2 +WINDOW 3 30 39 Left 2 +SYMATTR Value LTC2068 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC2066 +SYMATTR Description Quad 10µA Supply Current, Low IB, Zero-Drift Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6078.asy b/spice/copy/sym/OpAmps/LTC6078.asy new file mode 100755 index 0000000..f101592 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6078.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6078 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC6078 +SYMATTR Description Dual µPower Precision, CMOS Rail-to-Rail Amplifier +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6079.asy b/spice/copy/sym/OpAmps/LTC6079.asy new file mode 100755 index 0000000..ad17939 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6079.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6079 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC6078 +SYMATTR Description Quad µPower Precision, CMOS Rail-to-Rail Amplifier +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6081.asy b/spice/copy/sym/OpAmps/LTC6081.asy new file mode 100755 index 0000000..7b1d0be --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6081.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 4 42 4 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6081 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6081 +SYMATTR Description Dual µPower Precision, CMOS Rail-to-Rail Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6082.asy b/spice/copy/sym/OpAmps/LTC6082.asy new file mode 100755 index 0000000..9438c28 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6082.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6082 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6082 +SYMATTR Description Quad µPower Precision, CMOS Rail-to-Rail Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6084.asy b/spice/copy/sym/OpAmps/LTC6084.asy new file mode 100755 index 0000000..025a51a --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6084.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 4 42 4 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6084 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6084 +SYMATTR Description Dual 1.5MHz, Rail-to-Rail, CMOS Operational Amplifier +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6085.asy b/spice/copy/sym/OpAmps/LTC6085.asy new file mode 100755 index 0000000..1acefad --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6085.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6085 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6085 +SYMATTR Description Quad 1.5MHz, Rail-to-Rail, CMOS Operational Amplifier +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6087.asy b/spice/copy/sym/OpAmps/LTC6087.asy new file mode 100755 index 0000000..104e2f0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6087.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 4 42 4 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6087 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6087 +SYMATTR Description Dual 14MHz, Rail-to-Rail, CMOS Amplifiers +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6088.asy b/spice/copy/sym/OpAmps/LTC6088.asy new file mode 100755 index 0000000..b4f0de6 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6088.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6088 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Description QUAD 14MHz, Rail-to-Rail, CMOS Amplifiers +SYMATTR Value2 LTC6088 +PIN -32 16 NONE 0 +PINATTR PinName 3 +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName 7 +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName 1 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6090-5.asy b/spice/copy/sym/OpAmps/LTC6090-5.asy new file mode 100755 index 0000000..6310a6b --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6090-5.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -32 -56 -32 +LINE Normal -45 32 -55 32 +LINE Normal -50 37 -50 27 +LINE Normal -2 28 2 28 +LINE Normal -5 31 -2 28 +LINE Normal -5 39 -5 31 +LINE Normal -2 42 2 42 +LINE Normal 0 80 0 48 +LINE Normal -48 80 -48 72 +LINE Normal -48 -72 -48 -80 +LINE Normal -43 -59 -53 -59 +LINE Normal -48 -54 -48 -64 +LINE Normal -43 64 -53 64 +LINE Normal -2 42 -5 39 +LINE Normal 0 -48 0 -80 +LINE Normal 48 -24 48 -80 +LINE Normal 37 -13 41 -13 +LINE Normal 34 -10 37 -13 +LINE Normal 34 -2 34 -10 +LINE Normal 37 1 41 1 +LINE Normal 60 -16 33 -16 +LINE Normal 37 1 34 -2 +LINE Normal 41 -13 44 -10 +LINE Normal 41 1 44 -2 +LINE Normal 44 -2 44 -10 +LINE Normal 50 -13 57 -13 +LINE Normal 50 1 50 -13 +LINE Normal 50 1 57 1 +LINE Normal 57 -13 60 -10 +LINE Normal 57 1 60 -2 +LINE Normal 60 -2 60 -10 +LINE Normal 11 -39 -18 -39 +LINE Normal -11 -22 -11 -36 +LINE Normal -18 -36 -5 -36 +LINE Normal 2 -22 2 -36 +LINE Normal 2 -36 11 -36 +LINE Normal 8 -29 2 -29 +WINDOW 3 37 44 Left 2 +WINDOW 0 71 -25 Left 2 +SYMATTR Value LTC6090-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC6090-5 +SYMATTR Description 140V CMOS Rail-to-Rail Output, Picoamp Input Current Op Amp Gain>=5 +PIN 0 80 NONE 8 +PINATTR PinName COM +PINATTR SpiceOrder 1 +PIN -64 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -64 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -48 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 0 -80 NONE 8 +PINATTR PinName _TF +PINATTR SpiceOrder 5 +PIN 96 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN -48 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 48 -80 NONE 8 +PINATTR PinName _OD +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6090.asy b/spice/copy/sym/OpAmps/LTC6090.asy new file mode 100755 index 0000000..d5f739a --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6090.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -32 -56 -32 +LINE Normal -45 32 -55 32 +LINE Normal -50 37 -50 27 +LINE Normal -2 28 2 28 +LINE Normal -5 31 -2 28 +LINE Normal -5 39 -5 31 +LINE Normal -2 42 2 42 +LINE Normal 0 80 0 48 +LINE Normal -48 80 -48 72 +LINE Normal -48 -72 -48 -80 +LINE Normal -43 -59 -53 -59 +LINE Normal -48 -54 -48 -64 +LINE Normal -43 64 -53 64 +LINE Normal -2 42 -5 39 +LINE Normal 0 -48 0 -80 +LINE Normal 48 -24 48 -80 +LINE Normal 37 -13 41 -13 +LINE Normal 34 -10 37 -13 +LINE Normal 34 -2 34 -10 +LINE Normal 37 1 41 1 +LINE Normal 60 -16 33 -16 +LINE Normal 37 1 34 -2 +LINE Normal 41 -13 44 -10 +LINE Normal 41 1 44 -2 +LINE Normal 44 -2 44 -10 +LINE Normal 50 -13 57 -13 +LINE Normal 50 1 50 -13 +LINE Normal 50 1 57 1 +LINE Normal 57 -13 60 -10 +LINE Normal 57 1 60 -2 +LINE Normal 60 -2 60 -10 +LINE Normal 11 -39 -18 -39 +LINE Normal -11 -22 -11 -36 +LINE Normal -18 -36 -5 -36 +LINE Normal 2 -22 2 -36 +LINE Normal 2 -36 11 -36 +LINE Normal 8 -29 2 -29 +WINDOW 3 37 44 Left 2 +WINDOW 0 71 -25 Left 2 +SYMATTR Value LTC6090 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC6090 +SYMATTR Description 140V CMOS Rail-to-Rail Output, Picoamp Input Current Op Amp +PIN 0 80 NONE 8 +PINATTR PinName COM +PINATTR SpiceOrder 1 +PIN -64 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN -64 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -48 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 0 -80 NONE 8 +PINATTR PinName _TF +PINATTR SpiceOrder 5 +PIN 96 0 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN -48 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 48 -80 NONE 8 +PINATTR PinName _OD +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6101.asy b/spice/copy/sym/OpAmps/LTC6101.asy new file mode 100755 index 0000000..134a62e --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6101.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType BLOCK +LINE Normal 64 96 64 64 +LINE Normal 74 106 74 52 +LINE Normal 96 57 74 57 +LINE Normal 96 101 74 101 +LINE Normal 96 80 74 80 +LINE Normal 89 73 96 80 +LINE Normal 89 86 96 80 +LINE Normal 96 -128 96 80 +LINE Normal 96 144 96 101 +LINE Normal 48 -64 -48 -64 +LINE Normal 0 48 48 -64 +LINE Normal -48 -64 0 48 +LINE Normal -9 -51 -23 -51 +LINE Normal 23 -51 9 -51 +LINE Normal 0 80 0 48 +LINE Normal 64 80 0 80 +LINE Normal 128 144 96 144 +LINE Normal -128 -16 -28 -16 +LINE Normal 128 -16 28 -16 +LINE Normal -16 -128 -16 -64 +LINE Normal 16 -128 16 -64 +LINE Normal 128 -128 16 -128 +LINE Normal -16 -128 -128 -128 +LINE Normal -16 -44 -16 -58 +LINE Normal 98 -130 94 -130 +LINE Normal 98 -129 94 -129 +LINE Normal 98 -128 94 -128 +LINE Normal 98 -127 94 -127 +LINE Normal 98 -126 94 -126 +LINE Normal 98 -126 98 -130 +LINE Normal 97 -126 97 -130 +LINE Normal 96 -126 96 -130 +LINE Normal 95 -126 95 -130 +LINE Normal 94 -126 94 -130 +LINE Normal 98 55 94 55 +LINE Normal 98 56 94 56 +LINE Normal 98 57 94 57 +LINE Normal 98 58 94 58 +LINE Normal 98 59 94 59 +LINE Normal 98 59 98 55 +LINE Normal 97 59 97 55 +LINE Normal 96 59 96 55 +LINE Normal 95 59 95 55 +LINE Normal 94 59 94 55 +LINE Normal -32 0 -46 0 +LINE Normal 46 0 32 0 +LINE Normal 39 7 39 -7 +RECTANGLE Normal 128 176 -128 -160 +TEXT -80 71 Center 2 LT +WINDOW 3 1 145 Center 2 +WINDOW 0 0 -160 Bottom 2 +SYMATTR Value LTC6101 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6101 +SYMATTR Description High Voltage, High-Side Current Sense in SOT-23 +PIN 128 144 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -128 -16 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 +PIN 128 -128 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 3 +PIN -128 -128 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 128 -16 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6102.asy b/spice/copy/sym/OpAmps/LTC6102.asy new file mode 100755 index 0000000..aa4d400 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6102.asy @@ -0,0 +1,63 @@ +Version 4 +SymbolType CELL +LINE Normal 38 96 38 64 +LINE Normal 64 57 42 57 +LINE Normal 64 101 42 101 +LINE Normal 64 80 42 80 +LINE Normal 48 77 64 80 +LINE Normal 64 144 64 101 +LINE Normal 48 -64 -48 -64 +LINE Normal 0 48 48 -64 +LINE Normal -48 -64 0 48 +LINE Normal -9 -51 -23 -51 +LINE Normal 23 -51 9 -51 +LINE Normal 0 80 0 48 +LINE Normal 38 80 0 80 +LINE Normal 96 144 64 144 +LINE Normal -96 -16 -28 -16 +LINE Normal 97 -16 28 -16 +LINE Normal -16 -112 -16 -64 +LINE Normal 16 -112 16 -64 +LINE Normal 96 -112 16 -112 +LINE Normal -16 -112 -96 -112 +LINE Normal -16 -44 -16 -58 +LINE Normal 64 -64 64 80 +LINE Normal 97 -64 64 -64 +LINE Normal 43 -4 29 -4 +LINE Normal 36 3 36 -11 +LINE Normal -31 -1 -45 -1 +LINE Normal 48 83 64 80 +LINE Normal 42 65 42 49 +LINE Normal 42 87 42 72 +LINE Normal 42 109 42 93 +LINE Normal 48 83 48 77 +RECTANGLE Normal 96 160 -96 -128 +CIRCLE Normal 65 58 63 56 +CIRCLE Normal 66 59 62 55 +CIRCLE Normal 67 60 61 54 +TEXT -56 54 Center 2 LT +WINDOW 3 -1 129 Center 2 +WINDOW 0 0 -128 Bottom 2 +SYMATTR Value LTC6102 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6102 +SYMATTR Description Precision Zero Drift Current Sense Amplifier +PIN 96 144 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -96 -16 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 +PIN 96 -112 NONE 8 +PINATTR PinName -INS +PINATTR SpiceOrder 3 +PIN -96 -112 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 4 +PIN 96 -16 NONE 4 +PINATTR PinName VCC +PINATTR SpiceOrder 5 +PIN 96 -64 NONE 4 +PINATTR PinName -INF +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6103.asy b/spice/copy/sym/OpAmps/LTC6103.asy new file mode 100755 index 0000000..88572a0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6103.asy @@ -0,0 +1,113 @@ +Version 4 +SymbolType BLOCK +LINE Normal -76 96 -76 64 +LINE Normal -48 57 -70 57 +LINE Normal -48 101 -70 101 +LINE Normal -48 80 -70 80 +LINE Normal -64 -64 -192 -64 +LINE Normal -128 48 -64 -64 +LINE Normal -192 -64 -128 48 +LINE Normal -153 -51 -167 -51 +LINE Normal -89 -51 -103 -51 +LINE Normal -128 80 -128 48 +LINE Normal -76 80 -128 80 +LINE Normal -208 -16 -165 -16 +LINE Normal 91 -16 -92 -16 +LINE Normal -160 -112 -160 -64 +LINE Normal -96 -80 -96 -64 +LINE Normal -160 -80 -208 -80 +LINE Normal -160 -44 -160 -58 +LINE Normal 76 96 76 64 +LINE Normal 48 57 70 57 +LINE Normal 48 101 70 101 +LINE Normal 48 80 70 80 +LINE Normal 63 76 48 80 +LINE Normal 48 -112 48 80 +LINE Normal 64 -64 192 -64 +LINE Normal 128 48 64 -64 +LINE Normal 192 -64 128 48 +LINE Normal 153 -51 167 -51 +LINE Normal 89 -51 103 -51 +LINE Normal 128 80 128 48 +LINE Normal 76 80 128 80 +LINE Normal 160 -112 160 -64 +LINE Normal 96 -80 96 -64 +LINE Normal 160 -44 160 -58 +LINE Normal -208 -16 -208 -80 +LINE Normal 208 -16 208 -80 +LINE Normal 160 -80 208 -80 +LINE Normal 165 -16 208 -16 +LINE Normal -48 -80 -96 -80 +LINE Normal 48 -80 96 -80 +LINE Normal -48 -112 -48 80 +LINE Normal 91 -8 83 -8 +LINE Normal 173 -8 165 -8 +LINE Normal 169 -4 169 -12 +LINE Normal -169 -2 -169 -10 +LINE Normal -173 -6 -165 -6 +LINE Normal -91 -7 -83 -7 +LINE Normal 0 144 0 -16 +LINE Normal -48 144 -48 101 +LINE Normal 48 144 48 101 +LINE Normal 70 64 70 50 +LINE Normal 70 87 70 73 +LINE Normal 70 108 70 94 +LINE Normal -70 65 -70 51 +LINE Normal -70 88 -70 74 +LINE Normal -70 109 -70 95 +LINE Normal 63 84 48 80 +LINE Normal 63 84 63 76 +LINE Normal -63 76 -48 80 +LINE Normal -63 84 -48 80 +LINE Normal -63 84 -63 76 +RECTANGLE Normal 225 145 -223 -111 +CIRCLE Normal 49 58 47 56 +CIRCLE Normal 50 59 46 55 +CIRCLE Normal 51 60 45 54 +CIRCLE Normal -47 58 -49 56 +CIRCLE Normal -46 59 -50 55 +CIRCLE Normal -45 60 -51 54 +CIRCLE Normal 1 -15 -1 -17 +CIRCLE Normal 2 -14 -2 -18 +CIRCLE Normal 3 -13 -3 -19 +CIRCLE Normal -47 -79 -49 -81 +CIRCLE Normal -46 -78 -50 -82 +CIRCLE Normal -45 -77 -51 -83 +CIRCLE Normal 49 -79 47 -81 +CIRCLE Normal 50 -78 46 -82 +CIRCLE Normal 51 -77 45 -83 +CIRCLE Normal 161 -79 159 -81 +CIRCLE Normal 162 -78 158 -82 +CIRCLE Normal 163 -77 157 -83 +CIRCLE Normal -159 -79 -161 -81 +CIRCLE Normal -158 -78 -162 -82 +CIRCLE Normal -157 -77 -163 -83 +TEXT -176 112 Center 2 LT +WINDOW 3 214 119 Right 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value LTC6103 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6103 +SYMATTR Description Dual High Voltage, High-Side Current Sense in SOT-23 +PIN -48 144 NONE 8 +PINATTR PinName OUTA +PINATTR SpiceOrder 1 +PIN 48 144 NONE 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 2 +PIN 0 144 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 3 +PIN 160 -112 NONE 8 +PINATTR PinName +INB +PINATTR SpiceOrder 4 +PIN 48 -112 NONE 8 +PINATTR PinName -INB +PINATTR SpiceOrder 5 +PIN -48 -112 NONE 8 +PINATTR PinName -INA +PINATTR SpiceOrder 6 +PIN -160 -112 NONE 8 +PINATTR PinName +INA +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/LTC6104.asy b/spice/copy/sym/OpAmps/LTC6104.asy new file mode 100755 index 0000000..4b681d4 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6104.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 128 -192 -128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 48 Center 2 +SYMATTR Value LTC6104 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC6104 +SYMATTR Description High Voltage, High Side, Bi-Directional Current Sense Amplifier +PIN 192 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 144 -128 TOP 8 +PINATTR PinName INB+ +PINATTR SpiceOrder 5 +PIN 48 -128 TOP 8 +PINATTR PinName INB- +PINATTR SpiceOrder 6 +PIN -48 -128 TOP 8 +PINATTR PinName INA- +PINATTR SpiceOrder 7 +PIN -144 -128 TOP 8 +PINATTR PinName INA+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6115.asy b/spice/copy/sym/OpAmps/LTC6115.asy new file mode 100755 index 0000000..2eaeb05 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6115.asy @@ -0,0 +1,117 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 -48 -32 -112 +LINE Normal -32 -112 32 -80 +LINE Normal 32 -80 32 -80 +LINE Normal -20 -96 -26 -96 +LINE Normal -128 0 -128 10 +LINE Normal 80 -80 64 -80 +LINE Normal 160 -32 96 -32 +LINE Normal -32 -96 -64 -96 +LINE Normal 96 -96 80 -96 +LINE Normal 96 -64 80 -64 +LINE Normal 96 -128 96 -96 +LINE Normal 96 -32 96 -64 +LINE Normal 80 -104 80 -80 +LINE Normal 80 -80 80 -56 +LINE Normal 32 -80 -32 -48 +LINE Normal 80 -80 96 -80 +LINE Normal 88 -83 96 -80 +LINE Normal 96 -80 88 -77 +LINE Normal 88 -77 88 -83 +LINE Normal 96 -96 96 -80 +LINE Normal 32 -80 64 -80 +LINE Normal -139 27 -117 16 +LINE Normal -117 38 -139 27 +LINE Normal -117 16 -128 10 +LINE Normal -139 49 -117 38 +LINE Normal -128 55 -139 49 +LINE Normal 0 -96 0 -160 +LINE Normal -64 -128 96 -128 +LINE Normal -64 -96 -64 -128 +LINE Normal -160 0 -128 0 +LINE Normal -32 128 -32 64 +LINE Normal -32 64 32 96 +LINE Normal 32 96 32 96 +LINE Normal 32 96 -32 128 +LINE Normal 0 160 0 112 +LINE Normal -139 90 -117 79 +LINE Normal -117 101 -139 90 +LINE Normal -117 79 -128 73 +LINE Normal -139 112 -117 101 +LINE Normal -128 118 -139 112 +LINE Normal -56 64 -128 64 +LINE Normal -56 80 -31 80 +LINE Normal -128 144 -128 118 +LINE Normal -56 64 -56 80 +LINE Normal 160 96 32 96 +LINE Normal 0 32 160 32 +LINE Normal 0 32 0 80 +LINE Normal 0 -41 0 -64 +LINE Normal -160 -128 -64 -128 +LINE Normal -64 -32 -64 -64 +LINE Normal -32 -64 -64 -64 +LINE Normal -160 -32 -64 -32 +LINE Normal 12 -41 0 -41 +LINE Normal -57 112 -32 112 +LINE Normal -57 112 -57 128 +LINE Normal -57 128 -160 128 +LINE Normal -128 64 -128 73 +LINE Normal -128 55 -128 64 +LINE Normal 0 144 -128 144 +LINE Normal -26 112 -20 112 +LINE Normal -26 80 -20 80 +LINE Normal -23 77 -23 83 +LINE Normal -20 -64 -26 -64 +LINE Normal -23 -61 -23 -67 +RECTANGLE Normal 160 160 -160 -160 +CIRCLE Normal -63 -127 -65 -129 +CIRCLE Normal -62 -126 -66 -130 +CIRCLE Normal -61 -125 -67 -131 +CIRCLE Normal -127 65 -129 63 +CIRCLE Normal -126 66 -130 62 +CIRCLE Normal -125 67 -131 61 +CIRCLE Normal 1 145 -1 143 +CIRCLE Normal 2 146 -2 142 +CIRCLE Normal 3 147 -3 141 +TEXT 0 0 Center 2 LT +TEXT -112 27 Left 2 975K +TEXT -112 89 Left 2 25K +TEXT 12 -41 Left 2 Gnd +TEXT 8 134 Left 2 Gnd +TEXT 0 -144 Left 2 +V +TEXT 118 32 Bottom 2 Vs +WINDOW 3 96 160 Top 2 +WINDOW 0 96 -160 Bottom 2 +SYMATTR Value LTC6115 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC6115 +SYMATTR Description High Voltage High Side Current and Voltage Sense +PIN -160 -128 NONE 8 +PINATTR PinName -IN +PINATTR SpiceOrder 1 +PIN 160 -32 NONE 8 +PINATTR PinName OUTI +PINATTR SpiceOrder 3 +PIN 0 160 NONE 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -160 128 NONE 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 160 96 NONE 8 +PINATTR PinName OUTV +PINATTR SpiceOrder 6 +PIN 160 32 NONE 8 +PINATTR PinName VS +PINATTR SpiceOrder 7 +PIN -160 0 NONE 8 +PINATTR PinName VIN +PINATTR SpiceOrder 9 +PIN 0 -160 NONE 8 +PINATTR PinName +V +PINATTR SpiceOrder 11 +PIN -160 -32 NONE 8 +PINATTR PinName +IN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/OpAmps/LTC6226.asy b/spice/copy/sym/OpAmps/LTC6226.asy new file mode 100755 index 0000000..0af23eb --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6226.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6226 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6226.sub +SYMATTR Value2 LTC6226 +SYMATTR Description 1nV/rHz 420 MHz, 180V/us, Low Distortion Rail-to-Rail Output Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6227.asy b/spice/copy/sym/OpAmps/LTC6227.asy new file mode 100755 index 0000000..2965479 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6227.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6227 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6226.sub +SYMATTR Value2 LTC6226 +SYMATTR Description 1nV/rHz 420 MHz, 180V/us, Low Distortion Rail-to-Rail Output Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6228.asy b/spice/copy/sym/OpAmps/LTC6228.asy new file mode 100755 index 0000000..abffc7a --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6228.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 52 7 44 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6228 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LTC6228 +SYMATTR Description 0.88nV/rHz 730 MHz, 500V/us, Low Distortion Rail-to-Rail Output Op Amp with Shutdown +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6240.asy b/spice/copy/sym/OpAmps/LTC6240.asy new file mode 100755 index 0000000..6c9eccb --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6240.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6240 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC6241 +SYMATTR Description 18MHz Low Noise, Rail-to-Rail, CMOS Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6241.asy b/spice/copy/sym/OpAmps/LTC6241.asy new file mode 100755 index 0000000..3cfd4d0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6241.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6241 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC6241 +SYMATTR Description Dual 18MHz Low Noise, Rail-to-Rail, CMOS Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6242.asy b/spice/copy/sym/OpAmps/LTC6242.asy new file mode 100755 index 0000000..e708c27 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6242.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6242 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC6241 +SYMATTR Description Quad 18MHz Low Noise, Rail-to-Rail, CMOS Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6244.asy b/spice/copy/sym/OpAmps/LTC6244.asy new file mode 100755 index 0000000..02be4ff --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6244.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6244 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC6244 +SYMATTR Description 50MHz Low Noise, Rail-to-Rail, CMOS Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6244HV.asy b/spice/copy/sym/OpAmps/LTC6244HV.asy new file mode 100755 index 0000000..7edebca --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6244HV.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value LTC6244HV +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LTC6244HV +SYMATTR Description 50MHz Low Noise, Rail-to-Rail, CMOS Op Amp +PIN -32 16 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6246.asy b/spice/copy/sym/OpAmps/LTC6246.asy new file mode 100755 index 0000000..4f80cfd --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6246.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 22 9 27 9 +LINE Normal 22 13 22 9 +LINE Normal 27 13 22 13 +LINE Normal 27 18 27 13 +LINE Normal 22 18 27 18 +LINE Normal 0 -32 0 -16 +LINE Normal 0 17 0 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal 12 23 3 23 +LINE Normal 13 -20 4 -20 +LINE Normal 8 -15 8 -24 +LINE Normal 16 9 16 16 +LINE Normal 27 7 22 7 +WINDOW 3 16 32 Left 2 +WINDOW 0 16 -32 Left 2 +SYMATTR Value LTC6246 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6246 +SYMATTR Description 180MHz, 1mA, R_R I/O Op Amp +PIN 32 0 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 2 +PIN -32 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -32 -16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 4 +PIN 16 16 NONE 8 +PINATTR PinName 9 +PINATTR SpiceOrder 5 +PIN 0 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6247.asy b/spice/copy/sym/OpAmps/LTC6247.asy new file mode 100755 index 0000000..b84f491 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6247.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 0 -32 0 -16 +LINE Normal 0 17 0 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal 12 23 3 23 +LINE Normal 13 -20 4 -20 +LINE Normal 8 -15 8 -24 +WINDOW 3 16 32 Left 2 +WINDOW 0 16 -32 Left 2 +SYMATTR Value LTC6247 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6247 +SYMATTR Description Dual, 180MHz, 1mA, R-R I/O Op Amp +PIN 32 0 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 2 +PIN -32 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -32 -16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 4 +PIN 0 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6248.asy b/spice/copy/sym/OpAmps/LTC6248.asy new file mode 100755 index 0000000..6739fa9 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6248.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 0 -32 0 -16 +LINE Normal 0 17 0 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal 12 23 3 23 +LINE Normal 13 -20 4 -20 +LINE Normal 8 -15 8 -24 +WINDOW 3 16 32 Left 2 +WINDOW 0 16 -32 Left 2 +SYMATTR Value LTC6248 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6247 +SYMATTR Description Quad, 180MHz, 1mA, R-R I/O Op Amp +PIN 32 0 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 2 +PIN -32 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -32 -16 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 4 +PIN 0 -32 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6252.asy b/spice/copy/sym/OpAmps/LTC6252.asy new file mode 100755 index 0000000..aff2935 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6252.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 8 17 13 17 +LINE Normal 8 21 8 17 +LINE Normal 13 21 8 21 +LINE Normal 13 26 13 21 +LINE Normal 8 26 13 26 +LINE Normal -16 -32 -16 -23 +LINE Normal -16 25 -16 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal -2 -26 -12 -26 +LINE Normal -7 -21 -7 -31 +LINE Normal 16 8 16 32 +LINE Normal -2 27 -11 27 +LINE Normal 8 14 13 14 +WINDOW 3 22 32 Left 2 +WINDOW 0 6 -25 Left 2 +SYMATTR Value LTC6252 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC6252 +SYMATTR Description 720MHz, 3.5mA, R_R I/O Op Amp +PIN 32 0 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -16 32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -32 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -32 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 16 32 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN -16 -32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6253-7.asy b/spice/copy/sym/OpAmps/LTC6253-7.asy new file mode 100755 index 0000000..745bfe5 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6253-7.asy @@ -0,0 +1,46 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 8 17 13 17 +LINE Normal 8 21 8 17 +LINE Normal 13 21 8 21 +LINE Normal 13 26 13 21 +LINE Normal 8 26 13 26 +LINE Normal -16 -32 -16 -23 +LINE Normal -16 25 -16 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal -2 -26 -12 -26 +LINE Normal -7 -21 -7 -31 +LINE Normal 16 8 16 32 +LINE Normal -2 27 -11 27 +LINE Normal 8 14 13 14 +WINDOW 3 22 32 Left 2 +WINDOW 0 6 -25 Left 2 +SYMATTR Value LTC6253-7 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC6253-7 +SYMATTR Description 2GHz, 3.5mA Gain of 7 Stable Rail-to-Rail I/O Dual Op Amp +PIN 32 0 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -16 32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -32 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -32 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 16 32 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN -16 -32 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6253.asy b/spice/copy/sym/OpAmps/LTC6253.asy new file mode 100755 index 0000000..bf8b965 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6253.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 0 -32 0 -16 +LINE Normal 0 17 0 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal 12 23 3 23 +LINE Normal 13 -20 4 -20 +LINE Normal 8 -15 8 -24 +WINDOW 3 16 32 Left 2 +WINDOW 0 16 -32 Left 2 +SYMATTR Value LTC6253 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC6253 +SYMATTR Description Dual, 720MHz, 3.5mA, R-R I/O Op Amp +PIN 32 0 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -32 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -32 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 0 -32 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6254.asy b/spice/copy/sym/OpAmps/LTC6254.asy new file mode 100755 index 0000000..a7474ed --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6254.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +LINE Normal -32 0 -32 33 +LINE Normal -32 -31 -32 0 +LINE Normal 32 0 -32 -31 +LINE Normal -32 33 32 0 +LINE Normal 0 -32 0 -16 +LINE Normal 0 17 0 32 +LINE Normal -20 -16 -29 -16 +LINE Normal -19 16 -29 16 +LINE Normal -24 21 -24 12 +LINE Normal 12 23 3 23 +LINE Normal 13 -20 4 -20 +LINE Normal 8 -15 8 -24 +WINDOW 3 16 32 Left 2 +WINDOW 0 16 -32 Left 2 +SYMATTR Value LTC6254 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC6253 +SYMATTR Description Quad, 720MHz, 3.5mA, R-R I/O Op Amp +PIN 32 0 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN -32 16 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN -32 -16 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 0 -32 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/LTC6255.asy b/spice/copy/sym/OpAmps/LTC6255.asy new file mode 100755 index 0000000..7a61f1f --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6255.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal -16 -32 -16 -24 +LINE Normal -16 32 -16 24 +LINE Normal -12 -26 -4 -26 +LINE Normal -8 -30 -8 -22 +LINE Normal -12 26 -4 26 +LINE Normal 16 32 16 8 +LINE Normal 7 17 8 16 +LINE Normal 7 14 13 14 +LINE Normal 8 16 13 16 +LINE Normal 7 20 8 21 +LINE Normal 7 17 7 20 +LINE Normal 13 25 12 26 +LINE Normal 12 26 7 26 +LINE Normal 13 22 12 21 +LINE Normal 13 25 13 22 +LINE Normal 12 21 8 21 +WINDOW 0 5 -28 Left 2 +WINDOW 3 21 19 Left 2 +SYMATTR Value LTC6255 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LTC6255 +SYMATTR Description 6.5MHz, 65µA Power Efficient Rail-to-Rail I/O Op Amp +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -16 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -16 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6258.asy b/spice/copy/sym/OpAmps/LTC6258.asy new file mode 100755 index 0000000..e9a3364 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6258.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 7 43 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6258 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6258 +SYMATTR Description 1.3MHz, 20µA Power Efficient Rail-to-Rail I/O Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6259.asy b/spice/copy/sym/OpAmps/LTC6259.asy new file mode 100755 index 0000000..e03a1d3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6259.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 7 43 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6259 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6258 +SYMATTR Description Dual 1.3MHz, 20µA Power Efficient Rail-to-Rail I/O Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6260.asy b/spice/copy/sym/OpAmps/LTC6260.asy new file mode 100755 index 0000000..9a2437a --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6260.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 53 7 43 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6260 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LTC6258 +SYMATTR Description Quad 1.3MHz, 20µA Power Efficient Rail-to-Rail I/O Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6261.asy b/spice/copy/sym/OpAmps/LTC6261.asy new file mode 100755 index 0000000..8be396f --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6261.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6261 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6261 +SYMATTR Description 30MHz, 240µA Power Efficient Rail-to-Rail I/O Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6262.asy b/spice/copy/sym/OpAmps/LTC6262.asy new file mode 100755 index 0000000..a29a21f --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6262.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6262 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6261 +SYMATTR Description Dual 30MHz, 240µA Power Efficient Rail-to-Rail I/O Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6263.asy b/spice/copy/sym/OpAmps/LTC6263.asy new file mode 100755 index 0000000..764bab9 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6263.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6263 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6261 +SYMATTR Description Quad 30MHz, 240µA Power Efficient Rail-to-Rail I/O Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6268-10.asy b/spice/copy/sym/OpAmps/LTC6268-10.asy new file mode 100755 index 0000000..62db1a3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6268-10.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6268-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC6268-10 +SYMATTR Description 4GHz Ultra-Low Bias Current FET Input Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6268.asy b/spice/copy/sym/OpAmps/LTC6268.asy new file mode 100755 index 0000000..058a891 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6268.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6268 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC6268 +SYMATTR Description 500 MHz Ultra-Low Bias Current FET Input Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6269-10.asy b/spice/copy/sym/OpAmps/LTC6269-10.asy new file mode 100755 index 0000000..3988cfd --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6269-10.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6269-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC6268-10 +SYMATTR Description 4GHz Ultra-Low Bias Current FET Input Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6269.asy b/spice/copy/sym/OpAmps/LTC6269.asy new file mode 100755 index 0000000..036303d --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6269.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 60 +LINE Normal 0 -80 0 -60 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value LTC6269 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC6268 +SYMATTR Description 500 MHz Ultra-Low Bias Current FET Input Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/LTC6360.asy b/spice/copy/sym/OpAmps/LTC6360.asy new file mode 100755 index 0000000..a18b881 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6360.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +LINE Normal -144 32 -80 0 +LINE Normal -144 -32 -144 32 +LINE Normal -133 16 -139 16 +LINE Normal -137 -13 -137 -19 +LINE Normal -140 -16 -134 -16 +LINE Normal -160 -15 -160 -112 +LINE Normal -144 -15 -160 -15 +LINE Normal -160 16 -145 16 +LINE Normal -160 112 -160 16 +LINE Normal -64 0 -64 112 +LINE Normal -80 0 -64 0 +LINE Normal -80 0 -144 -32 +RECTANGLE Normal -192 -112 192 112 +TEXT 32 0 Center 2 LT +WINDOW 0 32 -40 Center 2 +WINDOW 3 32 38 Center 2 +SYMATTR Value LTC6360 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6360.sub +SYMATTR Value2 LTC6360 +SYMATTR Description Very Low Noise Single-Ended SAR ADC Driver with True Zero Output +PIN -160 112 NONE 8 +PINATTR PinName -IN +PINATTR SpiceOrder 1 +PIN -64 112 NONE 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 112 -112 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 4 +PIN 192 48 RIGHT 8 +PINATTR PinName CPO +PINATTR SpiceOrder 5 +PIN 192 -48 RIGHT 8 +PINATTR PinName CPI +PINATTR SpiceOrder 6 +PIN 112 112 BOTTOM 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -160 -112 NONE 8 +PINATTR PinName +IN +PINATTR SpiceOrder 8 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/OpAmps/LTC6362.asy b/spice/copy/sym/OpAmps/LTC6362.asy new file mode 100755 index 0000000..57a3ef7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6362.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -32 -56 -32 +LINE Normal -45 32 -55 32 +LINE Normal -50 37 -50 27 +LINE Normal 32 -32 96 -32 +LINE Normal 55 32 96 32 +LINE Normal 2 25 5 28 +LINE Normal -2 25 2 25 +LINE Normal -5 28 -2 25 +LINE Normal -5 32 -5 28 +LINE Normal -2 34 -5 32 +LINE Normal 2 34 -2 34 +LINE Normal 5 36 2 34 +LINE Normal 5 40 5 36 +LINE Normal 2 42 5 40 +LINE Normal -2 42 2 42 +LINE Normal -5 39 -2 42 +LINE Normal 0 80 0 48 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal -27 55 -37 55 +LINE Normal -52 6 -56 -8 +LINE Normal -48 -8 -52 6 +LINE Normal -47 6 -47 1 +LINE Normal -43 6 -47 6 +LINE Normal -43 1 -43 6 +LINE Normal -47 1 -43 1 +LINE Normal -40 1 -36 1 +LINE Normal -40 6 -40 1 +LINE Normal -36 6 -40 6 +LINE Normal -33 1 -33 6 +LINE Normal -31 4 -33 1 +LINE Normal -29 1 -31 4 +LINE Normal -29 6 -29 1 +LINE Normal 6 22 -6 22 +CIRCLE Normal 55 39 41 25 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LTC6362 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6362 +SYMATTR Description Precision Low Power Rail-to-Rail Input/Output Differential Op Amp/SAR ADC Driver +PIN -64 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -64 0 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN 0 80 NONE 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 +PIN -64 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6363-.5.asy b/spice/copy/sym/OpAmps/LTC6363-.5.asy new file mode 100755 index 0000000..7be483f --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6363-.5.asy @@ -0,0 +1,93 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 64 -32 -64 +LINE Normal 80 0 -32 64 +LINE Normal -32 -64 80 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -25 32 -7 32 +LINE Normal -16 23 -16 41 +LINE Normal -25 -32 -7 -32 +LINE Normal 0 -46 0 -112 +LINE Normal 0 128 0 46 +LINE Normal 14 52 32 52 +LINE Normal 14 -52 32 -52 +LINE Normal 23 -61 23 -43 +LINE Normal -104 -40 -108 -32 +LINE Normal -96 -24 -104 -40 +LINE Normal -96 -24 -88 -40 +LINE Normal -80 -24 -88 -40 +LINE Normal -76 -32 -80 -24 +LINE Normal -76 -32 -32 -32 +LINE Normal -104 24 -108 32 +LINE Normal -96 40 -104 24 +LINE Normal -96 40 -88 24 +LINE Normal -80 40 -88 24 +LINE Normal -76 32 -80 40 +LINE Normal -76 32 -32 32 +LINE Normal -128 32 -108 32 +LINE Normal 24 -32 128 -32 +LINE Normal 42 32 128 32 +LINE Normal 20 -88 16 -80 +LINE Normal 28 -72 20 -88 +LINE Normal 28 -72 36 -88 +LINE Normal 44 -72 36 -88 +LINE Normal 48 -80 44 -72 +LINE Normal 80 -80 48 -80 +LINE Normal 80 -32 80 -80 +LINE Normal -56 -80 16 -80 +LINE Normal -56 -32 -56 -80 +LINE Normal 20 72 16 80 +LINE Normal 28 88 20 72 +LINE Normal 28 88 36 72 +LINE Normal 44 88 36 72 +LINE Normal 48 80 44 88 +LINE Normal 80 80 48 80 +LINE Normal 80 32 80 80 +LINE Normal -56 80 16 80 +LINE Normal -56 32 -56 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal 42 38 30 26 +CIRCLE Normal -55 -31 -57 -33 +CIRCLE Normal -54 -30 -58 -34 +CIRCLE Normal -53 -29 -59 -35 +CIRCLE Normal -55 33 -57 31 +CIRCLE Normal -54 34 -58 30 +CIRCLE Normal -53 35 -59 29 +CIRCLE Normal 81 -31 79 -33 +CIRCLE Normal 82 -30 78 -34 +CIRCLE Normal 83 -29 77 -35 +CIRCLE Normal 81 33 79 31 +CIRCLE Normal 82 34 78 30 +CIRCLE Normal 83 35 77 29 +TEXT -93 -90 Center 2 LT +WINDOW 3 64 144 Left 2 +WINDOW 0 16 -128 Left 2 +SYMATTR Value LTC6363-.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC6363-.5 +SYMATTR Description Precision, Low Power Differential Amplifier +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 48 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN 0 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -32 NONE 8 +PINATTR PinName +OUT +PINATTR SpiceOrder 4 +PIN 128 32 NONE 8 +PINATTR PinName -OUT +PINATTR SpiceOrder 5 +PIN 0 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6363-1.asy b/spice/copy/sym/OpAmps/LTC6363-1.asy new file mode 100755 index 0000000..956c3cc --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6363-1.asy @@ -0,0 +1,93 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 64 -32 -64 +LINE Normal 80 0 -32 64 +LINE Normal -32 -64 80 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -25 32 -7 32 +LINE Normal -16 23 -16 41 +LINE Normal -25 -32 -7 -32 +LINE Normal 0 -46 0 -112 +LINE Normal 0 128 0 46 +LINE Normal 14 52 32 52 +LINE Normal 14 -52 32 -52 +LINE Normal 23 -61 23 -43 +LINE Normal -104 -40 -108 -32 +LINE Normal -96 -24 -104 -40 +LINE Normal -96 -24 -88 -40 +LINE Normal -80 -24 -88 -40 +LINE Normal -76 -32 -80 -24 +LINE Normal -76 -32 -32 -32 +LINE Normal -104 24 -108 32 +LINE Normal -96 40 -104 24 +LINE Normal -96 40 -88 24 +LINE Normal -80 40 -88 24 +LINE Normal -76 32 -80 40 +LINE Normal -76 32 -32 32 +LINE Normal -128 32 -108 32 +LINE Normal 24 -32 128 -32 +LINE Normal 42 32 128 32 +LINE Normal 20 -88 16 -80 +LINE Normal 28 -72 20 -88 +LINE Normal 28 -72 36 -88 +LINE Normal 44 -72 36 -88 +LINE Normal 48 -80 44 -72 +LINE Normal 80 -80 48 -80 +LINE Normal 80 -32 80 -80 +LINE Normal -56 -80 16 -80 +LINE Normal -56 -32 -56 -80 +LINE Normal 20 72 16 80 +LINE Normal 28 88 20 72 +LINE Normal 28 88 36 72 +LINE Normal 44 88 36 72 +LINE Normal 48 80 44 88 +LINE Normal 80 80 48 80 +LINE Normal 80 32 80 80 +LINE Normal -56 80 16 80 +LINE Normal -56 32 -56 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal 42 38 30 26 +CIRCLE Normal -54 -30 -58 -34 +CIRCLE Normal -53 -29 -59 -35 +CIRCLE Normal -52 -28 -60 -36 +CIRCLE Normal -54 34 -58 30 +CIRCLE Normal -53 35 -59 29 +CIRCLE Normal -52 36 -60 28 +CIRCLE Normal 82 -30 78 -34 +CIRCLE Normal 83 -29 77 -35 +CIRCLE Normal 84 -28 76 -36 +CIRCLE Normal 82 34 78 30 +CIRCLE Normal 83 35 77 29 +CIRCLE Normal 84 36 76 28 +TEXT -93 -90 Center 2 LT +WINDOW 3 64 144 Left 2 +WINDOW 0 16 -128 Left 2 +SYMATTR Value LTC6363-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC6363-1 +SYMATTR Description Precision, Low Power Differential Amplifier +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 48 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN 0 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -32 NONE 8 +PINATTR PinName +OUT +PINATTR SpiceOrder 4 +PIN 128 32 NONE 8 +PINATTR PinName -OUT +PINATTR SpiceOrder 5 +PIN 0 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6363-2.asy b/spice/copy/sym/OpAmps/LTC6363-2.asy new file mode 100755 index 0000000..ac33fdd --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6363-2.asy @@ -0,0 +1,93 @@ +Version 4 +SymbolType BLOCK +LINE Normal -32 64 -32 -64 +LINE Normal 80 0 -32 64 +LINE Normal -32 -64 80 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -25 32 -7 32 +LINE Normal -16 23 -16 41 +LINE Normal -25 -32 -7 -32 +LINE Normal 0 -46 0 -112 +LINE Normal 0 128 0 46 +LINE Normal 14 52 32 52 +LINE Normal 14 -52 32 -52 +LINE Normal 23 -61 23 -43 +LINE Normal -104 -40 -108 -32 +LINE Normal -96 -24 -104 -40 +LINE Normal -96 -24 -88 -40 +LINE Normal -80 -24 -88 -40 +LINE Normal -76 -32 -80 -24 +LINE Normal -76 -32 -32 -32 +LINE Normal -104 24 -108 32 +LINE Normal -96 40 -104 24 +LINE Normal -96 40 -88 24 +LINE Normal -80 40 -88 24 +LINE Normal -76 32 -80 40 +LINE Normal -76 32 -32 32 +LINE Normal -128 32 -108 32 +LINE Normal 24 -32 128 -32 +LINE Normal 42 32 128 32 +LINE Normal 20 -88 16 -80 +LINE Normal 28 -72 20 -88 +LINE Normal 28 -72 36 -88 +LINE Normal 44 -72 36 -88 +LINE Normal 48 -80 44 -72 +LINE Normal 80 -80 48 -80 +LINE Normal 80 -32 80 -80 +LINE Normal -56 -80 16 -80 +LINE Normal -56 -32 -56 -80 +LINE Normal 20 72 16 80 +LINE Normal 28 88 20 72 +LINE Normal 28 88 36 72 +LINE Normal 44 88 36 72 +LINE Normal 48 80 44 88 +LINE Normal 80 80 48 80 +LINE Normal 80 32 80 80 +LINE Normal -56 80 16 80 +LINE Normal -56 32 -56 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal 42 38 30 26 +CIRCLE Normal -55 -31 -57 -33 +CIRCLE Normal -54 -30 -58 -34 +CIRCLE Normal -53 -29 -59 -35 +CIRCLE Normal -55 33 -57 31 +CIRCLE Normal -54 34 -58 30 +CIRCLE Normal -53 35 -59 29 +CIRCLE Normal 81 -31 79 -33 +CIRCLE Normal 82 -30 78 -34 +CIRCLE Normal 83 -29 77 -35 +CIRCLE Normal 81 33 79 31 +CIRCLE Normal 82 34 78 30 +CIRCLE Normal 83 35 77 29 +TEXT -93 -90 Center 2 LT +WINDOW 3 64 144 Left 2 +WINDOW 0 16 -128 Left 2 +SYMATTR Value LTC6363-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC6363-2 +SYMATTR Description Precision, Low Power Differential Amplifier +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 48 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN 0 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -32 NONE 8 +PINATTR PinName +OUT +PINATTR SpiceOrder 4 +PIN 128 32 NONE 8 +PINATTR PinName -OUT +PINATTR SpiceOrder 5 +PIN 0 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6363.asy b/spice/copy/sym/OpAmps/LTC6363.asy new file mode 100755 index 0000000..3835824 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6363.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -32 -56 -32 +LINE Normal -45 32 -55 32 +LINE Normal -50 37 -50 27 +LINE Normal 32 -32 96 -32 +LINE Normal 55 32 96 32 +LINE Normal 2 25 5 28 +LINE Normal -2 25 2 25 +LINE Normal -5 28 -2 25 +LINE Normal -5 32 -5 28 +LINE Normal -2 34 -5 32 +LINE Normal 2 34 -2 34 +LINE Normal 5 36 2 34 +LINE Normal 5 40 5 36 +LINE Normal 2 42 5 40 +LINE Normal -2 42 2 42 +LINE Normal -5 39 -2 42 +LINE Normal 0 80 0 48 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal -27 55 -37 55 +LINE Normal -52 6 -56 -8 +LINE Normal -48 -8 -52 6 +LINE Normal -47 6 -47 1 +LINE Normal -43 6 -47 6 +LINE Normal -43 1 -43 6 +LINE Normal -47 1 -43 1 +LINE Normal -40 1 -36 1 +LINE Normal -40 6 -40 1 +LINE Normal -36 6 -40 6 +LINE Normal -33 1 -33 6 +LINE Normal -31 4 -33 1 +LINE Normal -29 1 -31 4 +LINE Normal -29 6 -29 1 +LINE Normal 6 22 -6 22 +CIRCLE Normal 55 39 41 25 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LTC6363 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC6363 +SYMATTR Description Precision, Low Power Rail-to-Rail Output Differential Op Amp +PIN -64 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -64 0 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 2 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN 0 80 NONE 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 +PIN -64 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6373.asy b/spice/copy/sym/OpAmps/LTC6373.asy new file mode 100755 index 0000000..144d876 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6373.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +LINE Normal -144 240 -144 -240 +LINE Normal 336 0 -144 240 +LINE Normal -144 -240 336 0 +LINE Normal 272 -32 336 -32 +LINE Normal 290 48 336 48 +LINE Normal -80 240 -80 208 +LINE Normal -80 -208 -80 -240 +LINE Normal 112 144 112 112 +LINE Normal 16 192 16 160 +LINE Normal -80 -96 -112 -96 +LINE Normal -80 -96 -80 -96 +LINE Normal -80 96 -112 96 +LINE Normal -80 96 -80 96 +LINE Normal -96 112 -96 80 +LINE Normal -96 112 -96 112 +LINE Normal -16 -176 -16 -208 +LINE Normal 48 -144 48 -176 +LINE Normal 176 -80 176 -112 +LINE Normal 112 -112 112 -144 +CIRCLE Normal 290 64 258 33 +WINDOW 3 224 96 Left 2 +WINDOW 0 224 -112 Left 2 +SYMATTR Value LTC6373 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6373.sub +SYMATTR Value2 LTC6373 +SYMATTR Description 36V Fully Differential Programmable-Gain Instrumentation Amplifier with 20pA Input Bias Current +PIN -144 -96 NONE 8 +PINATTR PinName -IN +PINATTR SpiceOrder 1 +PIN 176 -112 VRIGHT 40 +PINATTR PinName A0 +PINATTR SpiceOrder 2 +PIN 112 -144 VRIGHT 40 +PINATTR PinName A1 +PINATTR SpiceOrder 3 +PIN -80 -240 VRIGHT 40 +PINATTR PinName V+ +PINATTR SpiceOrder 4 +PIN -16 -208 VRIGHT 40 +PINATTR PinName V+ OUT +PINATTR SpiceOrder 5 +PIN 336 -32 NONE 50 +PINATTR PinName +OUT +PINATTR SpiceOrder 6 +PIN 336 48 NONE 50 +PINATTR PinName -OUT +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 8 +PIN 16 192 VLEFT 40 +PINATTR PinName CAP +PINATTR SpiceOrder 9 +PIN 112 144 VLEFT 40 +PINATTR PinName DGND +PINATTR SpiceOrder 10 +PIN 48 -176 VRIGHT 40 +PINATTR PinName A2 +PINATTR SpiceOrder 11 +PIN -144 96 NONE 8 +PINATTR PinName +IN +PINATTR SpiceOrder 12 +PIN -80 240 VLEFT 40 +PINATTR PinName V- +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/OpAmps/LTC6400-14.asy b/spice/copy/sym/OpAmps/LTC6400-14.asy new file mode 100755 index 0000000..7b67b40 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6400-14.asy @@ -0,0 +1,142 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -41 32 -23 32 +LINE Normal -32 23 -32 41 +LINE Normal -41 -32 -23 -32 +LINE Normal -16 -46 -16 -112 +LINE Normal -16 128 -16 46 +LINE Normal -2 52 16 52 +LINE Normal -2 -52 16 -52 +LINE Normal 7 -61 7 -43 +LINE Normal -104 -40 -108 -32 +LINE Normal -96 -24 -104 -40 +LINE Normal -96 -24 -88 -40 +LINE Normal -80 -24 -88 -40 +LINE Normal -76 -32 -80 -24 +LINE Normal -76 -32 -48 -32 +LINE Normal -104 24 -108 32 +LINE Normal -96 40 -104 24 +LINE Normal -96 40 -88 24 +LINE Normal -80 40 -88 24 +LINE Normal -76 32 -80 40 +LINE Normal -76 32 -48 32 +LINE Normal -128 32 -108 32 +LINE Normal 10 -88 6 -80 +LINE Normal 18 -72 10 -88 +LINE Normal 18 -72 26 -88 +LINE Normal 34 -72 26 -88 +LINE Normal 38 -80 34 -72 +LINE Normal -64 -80 -64 -32 +LINE Normal 6 -80 -64 -80 +LINE Normal -64 32 -64 80 +LINE Normal 8 -32 62 -32 +LINE Normal 26 32 62 32 +LINE Normal 6 80 -64 80 +LINE Normal 10 72 6 80 +LINE Normal 18 88 10 72 +LINE Normal 18 88 26 72 +LINE Normal 34 88 26 72 +LINE Normal 38 80 34 88 +LINE Normal 66 -40 62 -32 +LINE Normal 74 -24 66 -40 +LINE Normal 74 -24 82 -40 +LINE Normal 90 -24 82 -40 +LINE Normal 94 -32 90 -24 +LINE Normal 94 -32 110 -32 +LINE Normal 110 -32 110 -4 +LINE Normal 128 -32 110 -32 +LINE Normal 99 -72 103 -80 +LINE Normal 91 -88 99 -72 +LINE Normal 91 -88 83 -72 +LINE Normal 75 -88 83 -72 +LINE Normal 71 -80 75 -88 +LINE Normal 48 -80 71 -80 +LINE Normal 128 -80 103 -80 +LINE Normal 48 -32 48 -80 +LINE Normal 48 -80 38 -80 +LINE Normal 48 80 48 32 +LINE Normal 38 80 48 80 +LINE Normal 66 40 62 32 +LINE Normal 74 24 66 40 +LINE Normal 74 24 82 40 +LINE Normal 90 24 82 40 +LINE Normal 94 32 90 24 +LINE Normal 94 32 128 32 +LINE Normal 110 32 110 4 +LINE Normal 122 4 98 4 +LINE Normal 122 -4 98 -4 +LINE Normal 99 88 103 80 +LINE Normal 91 72 99 88 +LINE Normal 91 72 83 88 +LINE Normal 75 72 83 88 +LINE Normal 71 80 75 72 +LINE Normal 48 80 71 80 +LINE Normal 128 80 103 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal -63 -31 -65 -33 +CIRCLE Normal -62 -30 -66 -34 +CIRCLE Normal -61 -29 -67 -35 +CIRCLE Normal -63 33 -65 31 +CIRCLE Normal -62 34 -66 30 +CIRCLE Normal -61 35 -67 29 +CIRCLE Normal 49 -81 47 -79 +CIRCLE Normal 50 -82 46 -78 +CIRCLE Normal 51 -83 45 -77 +CIRCLE Normal 111 -33 109 -31 +CIRCLE Normal 112 -34 108 -30 +CIRCLE Normal 113 -35 107 -29 +CIRCLE Normal 26 38 14 26 +CIRCLE Normal 49 -31 47 -33 +CIRCLE Normal 50 -30 46 -34 +CIRCLE Normal 51 -29 45 -35 +CIRCLE Normal 49 33 47 31 +CIRCLE Normal 50 34 46 30 +CIRCLE Normal 51 35 45 29 +CIRCLE Normal 111 33 109 31 +CIRCLE Normal 112 34 108 30 +CIRCLE Normal 113 35 107 29 +CIRCLE Normal 49 79 47 81 +CIRCLE Normal 50 78 46 82 +CIRCLE Normal 51 77 45 83 +TEXT -93 -90 Center 2 LT +WINDOW 3 48 144 Left 2 +WINDOW 0 0 -128 Left 2 +SYMATTR Value LTC6400-14 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6400-14 +SYMATTR Description 2.4GHz Low Noise, Low Distortion Differential ADC Driver for 300MHz IF\n\nNote: Distortion is not modeled. +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 32 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -80 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 128 80 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 128 32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 128 -32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6400-20.asy b/spice/copy/sym/OpAmps/LTC6400-20.asy new file mode 100755 index 0000000..2af9232 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6400-20.asy @@ -0,0 +1,142 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -41 32 -23 32 +LINE Normal -32 23 -32 41 +LINE Normal -41 -32 -23 -32 +LINE Normal -16 -46 -16 -112 +LINE Normal -16 128 -16 46 +LINE Normal -2 52 16 52 +LINE Normal -2 -52 16 -52 +LINE Normal 7 -61 7 -43 +LINE Normal -104 -40 -108 -32 +LINE Normal -96 -24 -104 -40 +LINE Normal -96 -24 -88 -40 +LINE Normal -80 -24 -88 -40 +LINE Normal -76 -32 -80 -24 +LINE Normal -76 -32 -48 -32 +LINE Normal -104 24 -108 32 +LINE Normal -96 40 -104 24 +LINE Normal -96 40 -88 24 +LINE Normal -80 40 -88 24 +LINE Normal -76 32 -80 40 +LINE Normal -76 32 -48 32 +LINE Normal -128 32 -108 32 +LINE Normal 10 -88 6 -80 +LINE Normal 18 -72 10 -88 +LINE Normal 18 -72 26 -88 +LINE Normal 34 -72 26 -88 +LINE Normal 38 -80 34 -72 +LINE Normal -64 -80 -64 -32 +LINE Normal 6 -80 -64 -80 +LINE Normal -64 32 -64 80 +LINE Normal 8 -32 62 -32 +LINE Normal 26 32 62 32 +LINE Normal 6 80 -64 80 +LINE Normal 10 72 6 80 +LINE Normal 18 88 10 72 +LINE Normal 18 88 26 72 +LINE Normal 34 88 26 72 +LINE Normal 38 80 34 88 +LINE Normal 66 -40 62 -32 +LINE Normal 74 -24 66 -40 +LINE Normal 74 -24 82 -40 +LINE Normal 90 -24 82 -40 +LINE Normal 94 -32 90 -24 +LINE Normal 94 -32 110 -32 +LINE Normal 110 -32 110 -4 +LINE Normal 128 -32 110 -32 +LINE Normal 99 -72 103 -80 +LINE Normal 91 -88 99 -72 +LINE Normal 91 -88 83 -72 +LINE Normal 75 -88 83 -72 +LINE Normal 71 -80 75 -88 +LINE Normal 48 -80 71 -80 +LINE Normal 128 -80 103 -80 +LINE Normal 48 -32 48 -80 +LINE Normal 48 -80 38 -80 +LINE Normal 48 80 48 32 +LINE Normal 38 80 48 80 +LINE Normal 66 40 62 32 +LINE Normal 74 24 66 40 +LINE Normal 74 24 82 40 +LINE Normal 90 24 82 40 +LINE Normal 94 32 90 24 +LINE Normal 94 32 128 32 +LINE Normal 110 32 110 4 +LINE Normal 122 4 98 4 +LINE Normal 122 -4 98 -4 +LINE Normal 99 88 103 80 +LINE Normal 91 72 99 88 +LINE Normal 91 72 83 88 +LINE Normal 75 72 83 88 +LINE Normal 71 80 75 72 +LINE Normal 48 80 71 80 +LINE Normal 128 80 103 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal -63 -31 -65 -33 +CIRCLE Normal -62 -30 -66 -34 +CIRCLE Normal -61 -29 -67 -35 +CIRCLE Normal -63 33 -65 31 +CIRCLE Normal -62 34 -66 30 +CIRCLE Normal -61 35 -67 29 +CIRCLE Normal 49 -81 47 -79 +CIRCLE Normal 50 -82 46 -78 +CIRCLE Normal 51 -83 45 -77 +CIRCLE Normal 111 -33 109 -31 +CIRCLE Normal 112 -34 108 -30 +CIRCLE Normal 113 -35 107 -29 +CIRCLE Normal 26 38 14 26 +CIRCLE Normal 49 -31 47 -33 +CIRCLE Normal 50 -30 46 -34 +CIRCLE Normal 51 -29 45 -35 +CIRCLE Normal 49 33 47 31 +CIRCLE Normal 50 34 46 30 +CIRCLE Normal 51 35 45 29 +CIRCLE Normal 111 33 109 31 +CIRCLE Normal 112 34 108 30 +CIRCLE Normal 113 35 107 29 +CIRCLE Normal 49 79 47 81 +CIRCLE Normal 50 78 46 82 +CIRCLE Normal 51 77 45 83 +TEXT -93 -90 Center 2 LT +WINDOW 3 48 144 Left 2 +WINDOW 0 0 -128 Left 2 +SYMATTR Value LTC6400-20 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6400-20 +SYMATTR Description 1.8GHz Low Noise, Low Distortion Differential ADC Driver for 300MHz IF\n\nNote: Distortion is not modeled. +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 32 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -80 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 128 80 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 128 32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 128 -32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6400-26.asy b/spice/copy/sym/OpAmps/LTC6400-26.asy new file mode 100755 index 0000000..09a2ee3 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6400-26.asy @@ -0,0 +1,142 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -41 32 -23 32 +LINE Normal -32 23 -32 41 +LINE Normal -41 -32 -23 -32 +LINE Normal -16 -46 -16 -112 +LINE Normal -16 128 -16 46 +LINE Normal -2 52 16 52 +LINE Normal -2 -52 16 -52 +LINE Normal 7 -61 7 -43 +LINE Normal -104 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Normal 99 -72 103 -80 +LINE Normal 91 -88 99 -72 +LINE Normal 91 -88 83 -72 +LINE Normal 75 -88 83 -72 +LINE Normal 71 -80 75 -88 +LINE Normal 48 -80 71 -80 +LINE Normal 128 -80 103 -80 +LINE Normal 48 -32 48 -80 +LINE Normal 48 -80 38 -80 +LINE Normal 48 80 48 32 +LINE Normal 38 80 48 80 +LINE Normal 66 40 62 32 +LINE Normal 74 24 66 40 +LINE Normal 74 24 82 40 +LINE Normal 90 24 82 40 +LINE Normal 94 32 90 24 +LINE Normal 94 32 128 32 +LINE Normal 110 32 110 4 +LINE Normal 122 4 98 4 +LINE Normal 122 -4 98 -4 +LINE Normal 99 88 103 80 +LINE Normal 91 72 99 88 +LINE Normal 91 72 83 88 +LINE Normal 75 72 83 88 +LINE Normal 71 80 75 72 +LINE Normal 48 80 71 80 +LINE Normal 128 80 103 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal -63 -31 -65 -33 +CIRCLE Normal -62 -30 -66 -34 +CIRCLE Normal -61 -29 -67 -35 +CIRCLE Normal -63 33 -65 31 +CIRCLE Normal -62 34 -66 30 +CIRCLE Normal -61 35 -67 29 +CIRCLE Normal 49 -81 47 -79 +CIRCLE Normal 50 -82 46 -78 +CIRCLE Normal 51 -83 45 -77 +CIRCLE Normal 111 -33 109 -31 +CIRCLE Normal 112 -34 108 -30 +CIRCLE Normal 113 -35 107 -29 +CIRCLE Normal 26 38 14 26 +CIRCLE Normal 49 -31 47 -33 +CIRCLE Normal 50 -30 46 -34 +CIRCLE Normal 51 -29 45 -35 +CIRCLE Normal 49 33 47 31 +CIRCLE Normal 50 34 46 30 +CIRCLE Normal 51 35 45 29 +CIRCLE Normal 111 33 109 31 +CIRCLE Normal 112 34 108 30 +CIRCLE Normal 113 35 107 29 +CIRCLE Normal 49 79 47 81 +CIRCLE Normal 50 78 46 82 +CIRCLE Normal 51 77 45 83 +TEXT -93 -90 Center 2 LT +WINDOW 3 48 144 Left 2 +WINDOW 0 0 -128 Left 2 +SYMATTR Value LTC6400-26 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6400-26 +SYMATTR Description 1.9GHz Low Noise, Low Distortion Differential ADC Driver for DC-300MHz\n\nNote: Distortion is not modeled. +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 32 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -80 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 128 80 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 128 32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 128 -32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6400-8.asy b/spice/copy/sym/OpAmps/LTC6400-8.asy new file mode 100755 index 0000000..5eccf6b --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6400-8.asy @@ -0,0 +1,142 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -41 32 -23 32 +LINE Normal -32 23 -32 41 +LINE Normal -41 -32 -23 -32 +LINE Normal -16 -46 -16 -112 +LINE Normal -16 128 -16 46 +LINE Normal -2 52 16 52 +LINE Normal -2 -52 16 -52 +LINE Normal 7 -61 7 -43 +LINE Normal -104 -40 -108 -32 +LINE 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+LINE Normal 91 -88 99 -72 +LINE Normal 91 -88 83 -72 +LINE Normal 75 -88 83 -72 +LINE Normal 71 -80 75 -88 +LINE Normal 48 -80 71 -80 +LINE Normal 128 -80 103 -80 +LINE Normal 48 -32 48 -80 +LINE Normal 48 -80 38 -80 +LINE Normal 48 80 48 32 +LINE Normal 38 80 48 80 +LINE Normal 66 40 62 32 +LINE Normal 74 24 66 40 +LINE Normal 74 24 82 40 +LINE Normal 90 24 82 40 +LINE Normal 94 32 90 24 +LINE Normal 94 32 128 32 +LINE Normal 110 32 110 4 +LINE Normal 122 4 98 4 +LINE Normal 122 -4 98 -4 +LINE Normal 99 88 103 80 +LINE Normal 91 72 99 88 +LINE Normal 91 72 83 88 +LINE Normal 75 72 83 88 +LINE Normal 71 80 75 72 +LINE Normal 48 80 71 80 +LINE Normal 128 80 103 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal -63 -31 -65 -33 +CIRCLE Normal -62 -30 -66 -34 +CIRCLE Normal -61 -29 -67 -35 +CIRCLE Normal -63 33 -65 31 +CIRCLE Normal -62 34 -66 30 +CIRCLE Normal -61 35 -67 29 +CIRCLE Normal 49 -81 47 -79 +CIRCLE Normal 50 -82 46 -78 +CIRCLE Normal 51 -83 45 -77 +CIRCLE Normal 111 -33 109 -31 +CIRCLE Normal 112 -34 108 -30 +CIRCLE Normal 113 -35 107 -29 +CIRCLE Normal 26 38 14 26 +CIRCLE Normal 49 -31 47 -33 +CIRCLE Normal 50 -30 46 -34 +CIRCLE Normal 51 -29 45 -35 +CIRCLE Normal 49 33 47 31 +CIRCLE Normal 50 34 46 30 +CIRCLE Normal 51 35 45 29 +CIRCLE Normal 111 33 109 31 +CIRCLE Normal 112 34 108 30 +CIRCLE Normal 113 35 107 29 +CIRCLE Normal 49 79 47 81 +CIRCLE Normal 50 78 46 82 +CIRCLE Normal 51 77 45 83 +TEXT -93 -90 Center 2 LT +WINDOW 3 48 144 Left 2 +WINDOW 0 0 -128 Left 2 +SYMATTR Value LTC6400-8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6400-8 +SYMATTR Description 2.2GHz Low Noise, Low Distortion Differential ADC Driver for DC-300MHz\n\nNote: Distortion is not modeled. +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 32 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -80 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 128 80 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 128 32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 128 -32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6401-14.asy b/spice/copy/sym/OpAmps/LTC6401-14.asy new file mode 100755 index 0000000..3fdc1f8 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6401-14.asy @@ -0,0 +1,142 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -41 32 -23 32 +LINE Normal -32 23 -32 41 +LINE Normal -41 -32 -23 -32 +LINE Normal -16 -46 -16 -112 +LINE Normal -16 128 -16 46 +LINE Normal -2 52 16 52 +LINE Normal -2 -52 16 -52 +LINE Normal 7 -61 7 -43 +LINE Normal -104 -40 -108 -32 +LINE Normal -96 -24 -104 -40 +LINE Normal -96 -24 -88 -40 +LINE Normal -80 -24 -88 -40 +LINE Normal -76 -32 -80 -24 +LINE Normal -76 -32 -48 -32 +LINE Normal -104 24 -108 32 +LINE Normal -96 40 -104 24 +LINE Normal -96 40 -88 24 +LINE Normal -80 40 -88 24 +LINE Normal -76 32 -80 40 +LINE Normal -76 32 -48 32 +LINE Normal -128 32 -108 32 +LINE Normal 10 -88 6 -80 +LINE Normal 18 -72 10 -88 +LINE Normal 18 -72 26 -88 +LINE Normal 34 -72 26 -88 +LINE Normal 38 -80 34 -72 +LINE Normal -64 -80 -64 -32 +LINE Normal 6 -80 -64 -80 +LINE Normal -64 32 -64 80 +LINE Normal 8 -32 62 -32 +LINE Normal 26 32 62 32 +LINE Normal 6 80 -64 80 +LINE Normal 10 72 6 80 +LINE Normal 18 88 10 72 +LINE Normal 18 88 26 72 +LINE Normal 34 88 26 72 +LINE Normal 38 80 34 88 +LINE Normal 66 -40 62 -32 +LINE Normal 74 -24 66 -40 +LINE Normal 74 -24 82 -40 +LINE Normal 90 -24 82 -40 +LINE Normal 94 -32 90 -24 +LINE Normal 94 -32 110 -32 +LINE Normal 110 -32 110 -4 +LINE Normal 128 -32 110 -32 +LINE Normal 99 -72 103 -80 +LINE Normal 91 -88 99 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112 -34 108 -30 +CIRCLE Normal 113 -35 107 -29 +CIRCLE Normal 26 38 14 26 +CIRCLE Normal 49 -31 47 -33 +CIRCLE Normal 50 -30 46 -34 +CIRCLE Normal 51 -29 45 -35 +CIRCLE Normal 49 33 47 31 +CIRCLE Normal 50 34 46 30 +CIRCLE Normal 51 35 45 29 +CIRCLE Normal 111 33 109 31 +CIRCLE Normal 112 34 108 30 +CIRCLE Normal 113 35 107 29 +CIRCLE Normal 49 79 47 81 +CIRCLE Normal 50 78 46 82 +CIRCLE Normal 51 77 45 83 +TEXT -93 -90 Center 2 LT +WINDOW 3 48 144 Left 2 +WINDOW 0 0 -128 Left 2 +SYMATTR Value LTC6401-14 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6401-14 +SYMATTR Description 2GHz Low Noise, Low Distortion Differential ADC Driver for DC-140MHz IF\n\nNote: Distortion is not modeled. +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 32 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -80 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 128 80 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 128 32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 128 -32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6401-20.asy b/spice/copy/sym/OpAmps/LTC6401-20.asy new file mode 100755 index 0000000..b53de0b --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6401-20.asy @@ -0,0 +1,142 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -41 32 -23 32 +LINE Normal -32 23 -32 41 +LINE Normal -41 -32 -23 -32 +LINE Normal -16 -46 -16 -112 +LINE Normal -16 128 -16 46 +LINE Normal -2 52 16 52 +LINE Normal -2 -52 16 -52 +LINE Normal 7 -61 7 -43 +LINE Normal -104 -40 -108 -32 +LINE Normal -96 -24 -104 -40 +LINE Normal -96 -24 -88 -40 +LINE Normal -80 -24 -88 -40 +LINE Normal -76 -32 -80 -24 +LINE Normal -76 -32 -48 -32 +LINE Normal -104 24 -108 32 +LINE Normal -96 40 -104 24 +LINE Normal -96 40 -88 24 +LINE Normal -80 40 -88 24 +LINE Normal -76 32 -80 40 +LINE Normal -76 32 -48 32 +LINE Normal -128 32 -108 32 +LINE Normal 10 -88 6 -80 +LINE Normal 18 -72 10 -88 +LINE Normal 18 -72 26 -88 +LINE Normal 34 -72 26 -88 +LINE Normal 38 -80 34 -72 +LINE Normal -64 -80 -64 -32 +LINE Normal 6 -80 -64 -80 +LINE Normal -64 32 -64 80 +LINE Normal 8 -32 62 -32 +LINE Normal 26 32 62 32 +LINE Normal 6 80 -64 80 +LINE Normal 10 72 6 80 +LINE Normal 18 88 10 72 +LINE Normal 18 88 26 72 +LINE Normal 34 88 26 72 +LINE Normal 38 80 34 88 +LINE Normal 66 -40 62 -32 +LINE Normal 74 -24 66 -40 +LINE Normal 74 -24 82 -40 +LINE Normal 90 -24 82 -40 +LINE Normal 94 -32 90 -24 +LINE Normal 94 -32 110 -32 +LINE Normal 110 -32 110 -4 +LINE Normal 128 -32 110 -32 +LINE Normal 99 -72 103 -80 +LINE Normal 91 -88 99 -72 +LINE Normal 91 -88 83 -72 +LINE Normal 75 -88 83 -72 +LINE Normal 71 -80 75 -88 +LINE Normal 48 -80 71 -80 +LINE Normal 128 -80 103 -80 +LINE Normal 48 -32 48 -80 +LINE Normal 48 -80 38 -80 +LINE Normal 48 80 48 32 +LINE Normal 38 80 48 80 +LINE Normal 66 40 62 32 +LINE Normal 74 24 66 40 +LINE Normal 74 24 82 40 +LINE Normal 90 24 82 40 +LINE Normal 94 32 90 24 +LINE Normal 94 32 128 32 +LINE Normal 110 32 110 4 +LINE Normal 122 4 98 4 +LINE Normal 122 -4 98 -4 +LINE Normal 99 88 103 80 +LINE Normal 91 72 99 88 +LINE Normal 91 72 83 88 +LINE Normal 75 72 83 88 +LINE Normal 71 80 75 72 +LINE Normal 48 80 71 80 +LINE Normal 128 80 103 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal -63 -31 -65 -33 +CIRCLE Normal -62 -30 -66 -34 +CIRCLE Normal -61 -29 -67 -35 +CIRCLE Normal -63 33 -65 31 +CIRCLE Normal -62 34 -66 30 +CIRCLE Normal -61 35 -67 29 +CIRCLE Normal 49 -81 47 -79 +CIRCLE Normal 50 -82 46 -78 +CIRCLE Normal 51 -83 45 -77 +CIRCLE Normal 111 -33 109 -31 +CIRCLE Normal 112 -34 108 -30 +CIRCLE Normal 113 -35 107 -29 +CIRCLE Normal 26 38 14 26 +CIRCLE Normal 49 -31 47 -33 +CIRCLE Normal 50 -30 46 -34 +CIRCLE Normal 51 -29 45 -35 +CIRCLE Normal 49 33 47 31 +CIRCLE Normal 50 34 46 30 +CIRCLE Normal 51 35 45 29 +CIRCLE Normal 111 33 109 31 +CIRCLE Normal 112 34 108 30 +CIRCLE Normal 113 35 107 29 +CIRCLE Normal 49 79 47 81 +CIRCLE Normal 50 78 46 82 +CIRCLE Normal 51 77 45 83 +TEXT -93 -90 Center 2 LT +WINDOW 3 48 144 Left 2 +WINDOW 0 0 -128 Left 2 +SYMATTR Value LTC6401-20 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6401-20 +SYMATTR Description 1.3GHz Low Noise, Low Distortion Differential ADC Driver for DC-140MHz IF\n\nNote: Distortion is not modeled. +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 32 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -80 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 128 80 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 128 32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 128 -32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6401-26.asy b/spice/copy/sym/OpAmps/LTC6401-26.asy new file mode 100755 index 0000000..d772112 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6401-26.asy @@ -0,0 +1,142 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -41 32 -23 32 +LINE Normal -32 23 -32 41 +LINE Normal -41 -32 -23 -32 +LINE Normal -16 -46 -16 -112 +LINE Normal -16 128 -16 46 +LINE Normal -2 52 16 52 +LINE Normal -2 -52 16 -52 +LINE Normal 7 -61 7 -43 +LINE Normal -104 -40 -108 -32 +LINE Normal -96 -24 -104 -40 +LINE Normal -96 -24 -88 -40 +LINE Normal -80 -24 -88 -40 +LINE Normal -76 -32 -80 -24 +LINE Normal -76 -32 -48 -32 +LINE Normal -104 24 -108 32 +LINE Normal -96 40 -104 24 +LINE Normal -96 40 -88 24 +LINE Normal -80 40 -88 24 +LINE Normal -76 32 -80 40 +LINE Normal -76 32 -48 32 +LINE Normal -128 32 -108 32 +LINE Normal 10 -88 6 -80 +LINE Normal 18 -72 10 -88 +LINE Normal 18 -72 26 -88 +LINE Normal 34 -72 26 -88 +LINE Normal 38 -80 34 -72 +LINE Normal -64 -80 -64 -32 +LINE Normal 6 -80 -64 -80 +LINE Normal -64 32 -64 80 +LINE Normal 8 -32 62 -32 +LINE Normal 26 32 62 32 +LINE Normal 6 80 -64 80 +LINE Normal 10 72 6 80 +LINE Normal 18 88 10 72 +LINE Normal 18 88 26 72 +LINE Normal 34 88 26 72 +LINE Normal 38 80 34 88 +LINE Normal 66 -40 62 -32 +LINE Normal 74 -24 66 -40 +LINE Normal 74 -24 82 -40 +LINE Normal 90 -24 82 -40 +LINE Normal 94 -32 90 -24 +LINE Normal 94 -32 110 -32 +LINE Normal 110 -32 110 -4 +LINE Normal 128 -32 110 -32 +LINE Normal 99 -72 103 -80 +LINE Normal 91 -88 99 -72 +LINE Normal 91 -88 83 -72 +LINE Normal 75 -88 83 -72 +LINE Normal 71 -80 75 -88 +LINE Normal 48 -80 71 -80 +LINE Normal 128 -80 103 -80 +LINE Normal 48 -32 48 -80 +LINE Normal 48 -80 38 -80 +LINE Normal 48 80 48 32 +LINE Normal 38 80 48 80 +LINE Normal 66 40 62 32 +LINE Normal 74 24 66 40 +LINE Normal 74 24 82 40 +LINE Normal 90 24 82 40 +LINE Normal 94 32 90 24 +LINE Normal 94 32 128 32 +LINE Normal 110 32 110 4 +LINE Normal 122 4 98 4 +LINE Normal 122 -4 98 -4 +LINE Normal 99 88 103 80 +LINE Normal 91 72 99 88 +LINE Normal 91 72 83 88 +LINE Normal 75 72 83 88 +LINE Normal 71 80 75 72 +LINE Normal 48 80 71 80 +LINE Normal 128 80 103 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal -63 -31 -65 -33 +CIRCLE Normal -62 -30 -66 -34 +CIRCLE Normal -61 -29 -67 -35 +CIRCLE Normal -63 33 -65 31 +CIRCLE Normal -62 34 -66 30 +CIRCLE Normal -61 35 -67 29 +CIRCLE Normal 49 -81 47 -79 +CIRCLE Normal 50 -82 46 -78 +CIRCLE Normal 51 -83 45 -77 +CIRCLE Normal 111 -33 109 -31 +CIRCLE Normal 112 -34 108 -30 +CIRCLE Normal 113 -35 107 -29 +CIRCLE Normal 26 38 14 26 +CIRCLE Normal 49 -31 47 -33 +CIRCLE Normal 50 -30 46 -34 +CIRCLE Normal 51 -29 45 -35 +CIRCLE Normal 49 33 47 31 +CIRCLE Normal 50 34 46 30 +CIRCLE Normal 51 35 45 29 +CIRCLE Normal 111 33 109 31 +CIRCLE Normal 112 34 108 30 +CIRCLE Normal 113 35 107 29 +CIRCLE Normal 49 79 47 81 +CIRCLE Normal 50 78 46 82 +CIRCLE Normal 51 77 45 83 +TEXT -93 -90 Center 2 LT +WINDOW 3 48 144 Left 2 +WINDOW 0 0 -128 Left 2 +SYMATTR Value LTC6401-26 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6401-26 +SYMATTR Description 1.6GHz Low Noise, Low Distortion Differential ADC Driver for DC-140MHz IF\n\nNote: Distortion is not modeled. +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 32 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -80 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 128 80 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 128 32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 128 -32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6401-8.asy b/spice/copy/sym/OpAmps/LTC6401-8.asy new file mode 100755 index 0000000..c24d249 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6401-8.asy @@ -0,0 +1,142 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -32 -108 -32 +LINE Normal -41 32 -23 32 +LINE Normal -32 23 -32 41 +LINE Normal -41 -32 -23 -32 +LINE Normal -16 -46 -16 -112 +LINE Normal -16 128 -16 46 +LINE Normal -2 52 16 52 +LINE Normal -2 -52 16 -52 +LINE Normal 7 -61 7 -43 +LINE Normal -104 -40 -108 -32 +LINE Normal -96 -24 -104 -40 +LINE Normal -96 -24 -88 -40 +LINE Normal -80 -24 -88 -40 +LINE Normal -76 -32 -80 -24 +LINE Normal -76 -32 -48 -32 +LINE Normal -104 24 -108 32 +LINE Normal -96 40 -104 24 +LINE Normal -96 40 -88 24 +LINE Normal -80 40 -88 24 +LINE Normal -76 32 -80 40 +LINE Normal -76 32 -48 32 +LINE Normal -128 32 -108 32 +LINE Normal 10 -88 6 -80 +LINE Normal 18 -72 10 -88 +LINE Normal 18 -72 26 -88 +LINE Normal 34 -72 26 -88 +LINE Normal 38 -80 34 -72 +LINE Normal -64 -80 -64 -32 +LINE Normal 6 -80 -64 -80 +LINE Normal -64 32 -64 80 +LINE Normal 8 -32 62 -32 +LINE Normal 26 32 62 32 +LINE Normal 6 80 -64 80 +LINE Normal 10 72 6 80 +LINE Normal 18 88 10 72 +LINE Normal 18 88 26 72 +LINE Normal 34 88 26 72 +LINE Normal 38 80 34 88 +LINE Normal 66 -40 62 -32 +LINE Normal 74 -24 66 -40 +LINE Normal 74 -24 82 -40 +LINE Normal 90 -24 82 -40 +LINE Normal 94 -32 90 -24 +LINE Normal 94 -32 110 -32 +LINE Normal 110 -32 110 -4 +LINE Normal 128 -32 110 -32 +LINE Normal 99 -72 103 -80 +LINE Normal 91 -88 99 -72 +LINE Normal 91 -88 83 -72 +LINE Normal 75 -88 83 -72 +LINE Normal 71 -80 75 -88 +LINE Normal 48 -80 71 -80 +LINE Normal 128 -80 103 -80 +LINE Normal 48 -32 48 -80 +LINE Normal 48 -80 38 -80 +LINE Normal 48 80 48 32 +LINE Normal 38 80 48 80 +LINE Normal 66 40 62 32 +LINE Normal 74 24 66 40 +LINE Normal 74 24 82 40 +LINE Normal 90 24 82 40 +LINE Normal 94 32 90 24 +LINE Normal 94 32 128 32 +LINE Normal 110 32 110 4 +LINE Normal 122 4 98 4 +LINE Normal 122 -4 98 -4 +LINE Normal 99 88 103 80 +LINE Normal 91 72 99 88 +LINE Normal 91 72 83 88 +LINE Normal 75 72 83 88 +LINE Normal 71 80 75 72 +LINE Normal 48 80 71 80 +LINE Normal 128 80 103 80 +RECTANGLE Normal 128 128 -128 -112 +CIRCLE Normal -63 -31 -65 -33 +CIRCLE Normal -62 -30 -66 -34 +CIRCLE Normal -61 -29 -67 -35 +CIRCLE Normal -63 33 -65 31 +CIRCLE Normal -62 34 -66 30 +CIRCLE Normal -61 35 -67 29 +CIRCLE Normal 49 -81 47 -79 +CIRCLE Normal 50 -82 46 -78 +CIRCLE Normal 51 -83 45 -77 +CIRCLE Normal 111 -33 109 -31 +CIRCLE Normal 112 -34 108 -30 +CIRCLE Normal 113 -35 107 -29 +CIRCLE Normal 26 38 14 26 +CIRCLE Normal 49 -31 47 -33 +CIRCLE Normal 50 -30 46 -34 +CIRCLE Normal 51 -29 45 -35 +CIRCLE Normal 49 33 47 31 +CIRCLE Normal 50 34 46 30 +CIRCLE Normal 51 35 45 29 +CIRCLE Normal 111 33 109 31 +CIRCLE Normal 112 34 108 30 +CIRCLE Normal 113 35 107 29 +CIRCLE Normal 49 79 47 81 +CIRCLE Normal 50 78 46 82 +CIRCLE Normal 51 77 45 83 +TEXT -93 -90 Center 2 LT +WINDOW 3 48 144 Left 2 +WINDOW 0 0 -128 Left 2 +SYMATTR Value LTC6401-8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6401-8 +SYMATTR Description 2.2GHz Low Noise, Low Distortion Differential ADC Driver for DC-140MHz IF\n\nNote: Distortion is not modeled. +PIN -128 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN 32 128 BOTTOM 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -112 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 128 -80 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 128 80 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 4 +PINATTR PinName _EN +PINATTR SpiceOrder 7 +PIN -128 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 128 32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 128 -32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6403-1.asy b/spice/copy/sym/OpAmps/LTC6403-1.asy new file mode 100755 index 0000000..4bd71e7 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6403-1.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -48 -48 -48 +LINE Normal -41 -32 -23 -32 +LINE Normal -32 -41 -32 -23 +LINE Normal -41 32 -23 32 +LINE Normal -16 144 -16 46 +LINE Normal -9 56 9 56 +LINE Normal -9 -58 9 -58 +LINE Normal 0 -67 0 -49 +LINE Normal -128 48 -48 48 +LINE Normal 64 -96 64 -32 +LINE Normal 99 -75 91 -79 +LINE Normal 83 -67 99 -75 +LINE Normal 83 -67 99 -59 +LINE Normal 83 -51 99 -59 +LINE Normal 91 -47 83 -51 +LINE Normal 91 -96 91 -79 +LINE Normal 91 79 91 96 +LINE Normal 99 51 91 47 +LINE Normal 83 59 99 51 +LINE Normal 83 59 99 67 +LINE Normal 83 75 99 67 +LINE Normal 91 79 83 75 +LINE Normal 91 4 91 47 +LINE Normal 91 -47 91 -4 +LINE Normal 103 -4 79 -4 +LINE Normal 103 4 79 4 +LINE Normal 176 -32 91 -32 +LINE Normal 150 -20 126 -20 +LINE Normal 150 -12 126 -12 +LINE Normal 150 12 126 12 +LINE Normal 150 20 126 20 +LINE Normal 138 -32 138 -20 +LINE Normal 138 32 138 20 +LINE Normal 138 32 138 32 +LINE Normal 138 32 138 32 +LINE Normal -63 -48 -63 -48 +LINE Normal 176 -96 176 -96 +LINE Normal 138 12 138 -12 +LINE Normal 116 112 -16 112 +LINE Normal 138 0 116 0 +LINE Normal 176 32 91 32 +LINE Normal 176 -96 64 -96 +LINE Normal 26 -32 64 -32 +LINE Normal 9 32 64 32 +LINE Normal 64 96 64 32 +LINE Normal 116 112 116 0 +LINE Normal -16 -45 -16 -144 +LINE Normal 64 96 176 96 +LINE Normal 138 -32 138 -32 +LINE Normal 138 -32 138 -32 +RECTANGLE Normal 176 144 -128 -144 +CIRCLE Normal 26 -26 14 -38 +CIRCLE Normal 139 1 137 -1 +CIRCLE Normal 140 2 136 -2 +CIRCLE Normal 141 3 135 -3 +CIRCLE Normal 92 -31 90 -33 +CIRCLE Normal 93 -30 89 -34 +CIRCLE Normal 94 -29 88 -35 +CIRCLE Normal 92 33 90 31 +CIRCLE Normal 93 34 89 30 +CIRCLE Normal 94 35 88 29 +CIRCLE Normal 139 33 137 31 +CIRCLE Normal 140 34 136 30 +CIRCLE Normal 141 35 135 29 +CIRCLE Normal 139 -31 137 -33 +CIRCLE Normal 140 -30 136 -34 +CIRCLE Normal 141 -29 135 -35 +CIRCLE Normal 92 -95 90 -97 +CIRCLE Normal 93 -94 89 -98 +CIRCLE Normal 94 -93 88 -99 +CIRCLE Normal 92 97 90 95 +CIRCLE Normal 93 98 89 94 +CIRCLE Normal 94 99 88 93 +CIRCLE Normal -15 113 -17 111 +CIRCLE Normal -14 114 -18 110 +CIRCLE Normal -13 115 -19 109 +TEXT -80 104 Center 2 LT +WINDOW 3 80 128 Center 2 +WINDOW 0 80 -128 Center 2 +SYMATTR Value LTC6403-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6403-1 +SYMATTR Description 200MHz, Low Noise, Low Power Fully Differential Input/Output Amplifier/Driver\n\nNote: Distortion is not modeled. +PIN -128 48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -144 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 176 96 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 176 -96 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 144 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -80 -144 TOP 10 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 -48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 176 32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 9 +PIN 176 -32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6404-1.asy b/spice/copy/sym/OpAmps/LTC6404-1.asy new file mode 100755 index 0000000..76007ab --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6404-1.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -48 -48 -48 +LINE Normal -41 -32 -23 -32 +LINE Normal -32 -41 -32 -23 +LINE Normal -41 32 -23 32 +LINE Normal -16 144 -16 46 +LINE Normal -9 56 9 56 +LINE Normal -9 -58 9 -58 +LINE Normal 0 -67 0 -49 +LINE Normal -128 48 -48 48 +LINE Normal 64 -96 64 -32 +LINE Normal 99 -75 91 -79 +LINE Normal 83 -67 99 -75 +LINE Normal 83 -67 99 -59 +LINE Normal 83 -51 99 -59 +LINE Normal 91 -47 83 -51 +LINE Normal 91 -96 91 -79 +LINE Normal 91 79 91 96 +LINE Normal 99 51 91 47 +LINE Normal 83 59 99 51 +LINE Normal 83 59 99 67 +LINE Normal 83 75 99 67 +LINE Normal 91 79 83 75 +LINE Normal 91 4 91 47 +LINE Normal 91 -47 91 -4 +LINE Normal 103 -4 79 -4 +LINE Normal 103 4 79 4 +LINE Normal 176 -32 91 -32 +LINE Normal 150 -20 126 -20 +LINE Normal 150 -12 126 -12 +LINE Normal 150 12 126 12 +LINE Normal 150 20 126 20 +LINE Normal 138 -32 138 -20 +LINE Normal 138 32 138 20 +LINE Normal 138 32 138 32 +LINE Normal 138 32 138 32 +LINE Normal -63 -48 -63 -48 +LINE Normal 176 -96 176 -96 +LINE Normal 138 12 138 -12 +LINE Normal 116 112 -16 112 +LINE Normal 138 0 116 0 +LINE Normal 176 32 91 32 +LINE Normal 176 -96 64 -96 +LINE Normal 26 -32 64 -32 +LINE Normal 9 32 64 32 +LINE Normal 64 96 64 32 +LINE Normal 116 112 116 0 +LINE Normal -16 -45 -16 -144 +LINE Normal 64 96 176 96 +LINE Normal 138 -32 138 -32 +LINE Normal 138 -32 138 -32 +RECTANGLE Normal 176 144 -128 -144 +CIRCLE Normal 26 -26 14 -38 +CIRCLE Normal 139 1 137 -1 +CIRCLE Normal 140 2 136 -2 +CIRCLE Normal 141 3 135 -3 +CIRCLE Normal 92 -31 90 -33 +CIRCLE Normal 93 -30 89 -34 +CIRCLE Normal 94 -29 88 -35 +CIRCLE Normal 92 33 90 31 +CIRCLE Normal 93 34 89 30 +CIRCLE Normal 94 35 88 29 +CIRCLE Normal 139 33 137 31 +CIRCLE Normal 140 34 136 30 +CIRCLE Normal 141 35 135 29 +CIRCLE Normal 139 -31 137 -33 +CIRCLE Normal 140 -30 136 -34 +CIRCLE Normal 141 -29 135 -35 +CIRCLE Normal 92 -95 90 -97 +CIRCLE Normal 93 -94 89 -98 +CIRCLE Normal 94 -93 88 -99 +CIRCLE Normal 92 97 90 95 +CIRCLE Normal 93 98 89 94 +CIRCLE Normal 94 99 88 93 +CIRCLE Normal -15 113 -17 111 +CIRCLE Normal -14 114 -18 110 +CIRCLE Normal -13 115 -19 109 +TEXT -80 104 Center 2 LT +WINDOW 3 80 128 Center 2 +WINDOW 0 80 -128 Center 2 +SYMATTR Value LTC6404-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6404-1 +SYMATTR Description 600MHz, Low Noise, High Precision Fully Differential Input/Output Amplifier/Driver\n\nNote: Distortion is not modeled. +PIN -128 48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -144 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 176 96 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 176 -96 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 144 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -80 -144 TOP 10 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 -48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 176 -32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 176 32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6404-2.asy b/spice/copy/sym/OpAmps/LTC6404-2.asy new file mode 100755 index 0000000..aa93a57 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6404-2.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -48 -48 -48 +LINE Normal -41 -32 -23 -32 +LINE Normal -32 -41 -32 -23 +LINE Normal -41 32 -23 32 +LINE Normal -16 144 -16 46 +LINE Normal -9 56 9 56 +LINE Normal -9 -58 9 -58 +LINE Normal 0 -67 0 -49 +LINE Normal -128 48 -48 48 +LINE Normal 64 -96 64 -32 +LINE Normal 99 -75 91 -79 +LINE Normal 83 -67 99 -75 +LINE Normal 83 -67 99 -59 +LINE Normal 83 -51 99 -59 +LINE Normal 91 -47 83 -51 +LINE Normal 91 -96 91 -79 +LINE Normal 91 79 91 96 +LINE Normal 99 51 91 47 +LINE Normal 83 59 99 51 +LINE Normal 83 59 99 67 +LINE Normal 83 75 99 67 +LINE Normal 91 79 83 75 +LINE Normal 91 4 91 47 +LINE Normal 91 -47 91 -4 +LINE Normal 103 -4 79 -4 +LINE Normal 103 4 79 4 +LINE Normal 176 -32 91 -32 +LINE Normal 150 -20 126 -20 +LINE Normal 150 -12 126 -12 +LINE Normal 150 12 126 12 +LINE Normal 150 20 126 20 +LINE Normal 138 -32 138 -20 +LINE Normal 138 32 138 20 +LINE Normal 138 32 138 32 +LINE Normal 138 32 138 32 +LINE Normal -63 -48 -63 -48 +LINE Normal 176 -96 176 -96 +LINE Normal 138 12 138 -12 +LINE Normal 116 112 -16 112 +LINE Normal 138 0 116 0 +LINE Normal 176 32 91 32 +LINE Normal 176 -96 64 -96 +LINE Normal 26 -32 64 -32 +LINE Normal 9 32 64 32 +LINE Normal 64 96 64 32 +LINE Normal 116 112 116 0 +LINE Normal -16 -45 -16 -144 +LINE Normal 64 96 176 96 +LINE Normal 138 -32 138 -32 +LINE Normal 138 -32 138 -32 +RECTANGLE Normal 176 144 -128 -144 +CIRCLE Normal 26 -26 14 -38 +CIRCLE Normal 139 1 137 -1 +CIRCLE Normal 140 2 136 -2 +CIRCLE Normal 141 3 135 -3 +CIRCLE Normal 92 -31 90 -33 +CIRCLE Normal 93 -30 89 -34 +CIRCLE Normal 94 -29 88 -35 +CIRCLE Normal 92 33 90 31 +CIRCLE Normal 93 34 89 30 +CIRCLE Normal 94 35 88 29 +CIRCLE Normal 139 33 137 31 +CIRCLE Normal 140 34 136 30 +CIRCLE Normal 141 35 135 29 +CIRCLE Normal 139 -31 137 -33 +CIRCLE Normal 140 -30 136 -34 +CIRCLE Normal 141 -29 135 -35 +CIRCLE Normal 92 -95 90 -97 +CIRCLE Normal 93 -94 89 -98 +CIRCLE Normal 94 -93 88 -99 +CIRCLE Normal 92 97 90 95 +CIRCLE Normal 93 98 89 94 +CIRCLE Normal 94 99 88 93 +CIRCLE Normal -15 113 -17 111 +CIRCLE Normal -14 114 -18 110 +CIRCLE Normal -13 115 -19 109 +TEXT -80 104 Center 2 LT +WINDOW 3 80 128 Center 2 +WINDOW 0 80 -128 Center 2 +SYMATTR Value LTC6404-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6404-2 +SYMATTR Description 600MHz, Low Noise, High Precision Fully Differential Input/Output Amplifier/Driver\n\nNote: Distortion is not modeled. +PIN -128 48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -144 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 176 96 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 176 -96 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 144 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -80 -144 TOP 10 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 -48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 176 -32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 176 32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6404-4.asy b/spice/copy/sym/OpAmps/LTC6404-4.asy new file mode 100755 index 0000000..8166adc --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6404-4.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -48 -48 -48 +LINE Normal -41 -32 -23 -32 +LINE Normal -32 -41 -32 -23 +LINE Normal -41 32 -23 32 +LINE Normal -16 144 -16 46 +LINE Normal -9 56 9 56 +LINE Normal -9 -58 9 -58 +LINE Normal 0 -67 0 -49 +LINE Normal -128 48 -48 48 +LINE Normal 64 -96 64 -32 +LINE Normal 99 -75 91 -79 +LINE Normal 83 -67 99 -75 +LINE Normal 83 -67 99 -59 +LINE Normal 83 -51 99 -59 +LINE Normal 91 -47 83 -51 +LINE Normal 91 -96 91 -79 +LINE Normal 91 79 91 96 +LINE Normal 99 51 91 47 +LINE Normal 83 59 99 51 +LINE Normal 83 59 99 67 +LINE Normal 83 75 99 67 +LINE Normal 91 79 83 75 +LINE Normal 91 4 91 47 +LINE Normal 91 -47 91 -4 +LINE Normal 103 -4 79 -4 +LINE Normal 103 4 79 4 +LINE Normal 176 -32 91 -32 +LINE Normal 150 -20 126 -20 +LINE Normal 150 -12 126 -12 +LINE Normal 150 12 126 12 +LINE Normal 150 20 126 20 +LINE Normal 138 -32 138 -20 +LINE Normal 138 32 138 20 +LINE Normal 138 32 138 32 +LINE Normal 138 32 138 32 +LINE Normal -63 -48 -63 -48 +LINE Normal 176 -96 176 -96 +LINE Normal 138 12 138 -12 +LINE Normal 116 112 -16 112 +LINE Normal 138 0 116 0 +LINE Normal 176 32 91 32 +LINE Normal 176 -96 64 -96 +LINE Normal 26 -32 64 -32 +LINE Normal 9 32 64 32 +LINE Normal 64 96 64 32 +LINE Normal 116 112 116 0 +LINE Normal -16 -45 -16 -144 +LINE Normal 64 96 176 96 +LINE Normal 138 -32 138 -32 +LINE Normal 138 -32 138 -32 +RECTANGLE Normal 176 144 -128 -144 +CIRCLE Normal 26 -26 14 -38 +CIRCLE Normal 139 1 137 -1 +CIRCLE Normal 140 2 136 -2 +CIRCLE Normal 141 3 135 -3 +CIRCLE Normal 92 -31 90 -33 +CIRCLE Normal 93 -30 89 -34 +CIRCLE Normal 94 -29 88 -35 +CIRCLE Normal 92 33 90 31 +CIRCLE Normal 93 34 89 30 +CIRCLE Normal 94 35 88 29 +CIRCLE Normal 139 33 137 31 +CIRCLE Normal 140 34 136 30 +CIRCLE Normal 141 35 135 29 +CIRCLE Normal 139 -31 137 -33 +CIRCLE Normal 140 -30 136 -34 +CIRCLE Normal 141 -29 135 -35 +CIRCLE Normal 92 -95 90 -97 +CIRCLE Normal 93 -94 89 -98 +CIRCLE Normal 94 -93 88 -99 +CIRCLE Normal 92 97 90 95 +CIRCLE Normal 93 98 89 94 +CIRCLE Normal 94 99 88 93 +CIRCLE Normal -15 113 -17 111 +CIRCLE Normal -14 114 -18 110 +CIRCLE Normal -13 115 -19 109 +TEXT -80 104 Center 2 LT +WINDOW 3 80 128 Center 2 +WINDOW 0 80 -128 Center 2 +SYMATTR Value LTC6404-4 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6404-4 +SYMATTR Description 600MHz, Low Noise, High Precision Fully Differential Input/Output Amplifier/Driver\n\nNote: Distortion is not modeled. +PIN -128 48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -144 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 176 96 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 176 -96 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 144 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -80 -144 TOP 10 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 -48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 176 -32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 176 32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6405.asy b/spice/copy/sym/OpAmps/LTC6405.asy new file mode 100755 index 0000000..2b7db53 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6405.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -48 -48 -48 +LINE Normal -41 -32 -23 -32 +LINE Normal -32 -41 -32 -23 +LINE Normal -41 32 -23 32 +LINE Normal -16 144 -16 46 +LINE Normal -9 56 9 56 +LINE Normal -9 -58 9 -58 +LINE Normal 0 -67 0 -49 +LINE Normal -128 48 -48 48 +LINE Normal 64 -96 64 -32 +LINE Normal 99 -75 91 -79 +LINE Normal 83 -67 99 -75 +LINE Normal 83 -67 99 -59 +LINE Normal 83 -51 99 -59 +LINE Normal 91 -47 83 -51 +LINE Normal 91 -96 91 -79 +LINE Normal 91 79 91 96 +LINE Normal 99 51 91 47 +LINE Normal 83 59 99 51 +LINE Normal 83 59 99 67 +LINE Normal 83 75 99 67 +LINE Normal 91 79 83 75 +LINE Normal 91 4 91 47 +LINE Normal 91 -47 91 -4 +LINE Normal 103 -4 79 -4 +LINE Normal 103 4 79 4 +LINE Normal 176 -32 91 -32 +LINE Normal 150 -20 126 -20 +LINE Normal 150 -12 126 -12 +LINE Normal 150 12 126 12 +LINE Normal 150 20 126 20 +LINE Normal 138 -32 138 -20 +LINE Normal 138 32 138 20 +LINE Normal 138 32 138 32 +LINE Normal 138 32 138 32 +LINE Normal -63 -48 -63 -48 +LINE Normal 176 -96 176 -96 +LINE Normal 138 12 138 -12 +LINE Normal 116 112 -16 112 +LINE Normal 138 0 116 0 +LINE Normal 176 32 91 32 +LINE Normal 176 -96 64 -96 +LINE Normal 26 -32 64 -32 +LINE Normal 9 32 64 32 +LINE Normal 64 96 64 32 +LINE Normal 116 112 116 0 +LINE Normal -16 -45 -16 -144 +LINE Normal 64 96 176 96 +LINE Normal 138 -32 138 -32 +LINE Normal 138 -32 138 -32 +RECTANGLE Normal 176 144 -128 -144 +CIRCLE Normal 26 -26 14 -38 +CIRCLE Normal 139 1 137 -1 +CIRCLE Normal 140 2 136 -2 +CIRCLE Normal 141 3 135 -3 +CIRCLE Normal 92 -31 90 -33 +CIRCLE Normal 93 -30 89 -34 +CIRCLE Normal 94 -29 88 -35 +CIRCLE Normal 92 33 90 31 +CIRCLE Normal 93 34 89 30 +CIRCLE Normal 94 35 88 29 +CIRCLE Normal 139 33 137 31 +CIRCLE Normal 140 34 136 30 +CIRCLE Normal 141 35 135 29 +CIRCLE Normal 139 -31 137 -33 +CIRCLE Normal 140 -30 136 -34 +CIRCLE Normal 141 -29 135 -35 +CIRCLE Normal 92 -95 90 -97 +CIRCLE Normal 93 -94 89 -98 +CIRCLE Normal 94 -93 88 -99 +CIRCLE Normal 92 97 90 95 +CIRCLE Normal 93 98 89 94 +CIRCLE Normal 94 99 88 93 +CIRCLE Normal -15 113 -17 111 +CIRCLE Normal -14 114 -18 110 +CIRCLE Normal -13 115 -19 109 +TEXT -80 104 Center 2 LT +WINDOW 3 80 128 Center 2 +WINDOW 0 80 -128 Center 2 +SYMATTR Value LTC6405 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6405 +SYMATTR Description 2.7GHz, 5V, Low Noise, Rail-to-Rail Input Differential Input/Output Amplifier/Driver\n\nNote: Distortion is not modeled. +PIN -128 48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -144 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 176 96 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 176 -96 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 144 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -80 -144 TOP 10 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 -48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 176 -32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 9 +PIN 176 32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6406.asy b/spice/copy/sym/OpAmps/LTC6406.asy new file mode 100755 index 0000000..69a272f --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6406.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType BLOCK +LINE Normal -48 64 -48 -64 +LINE Normal 64 0 -48 64 +LINE Normal -48 -64 64 0 +LINE Normal -128 -48 -48 -48 +LINE Normal -41 -32 -23 -32 +LINE Normal -32 -41 -32 -23 +LINE Normal -41 32 -23 32 +LINE Normal -16 144 -16 46 +LINE Normal -9 56 9 56 +LINE Normal -9 -58 9 -58 +LINE Normal 0 -67 0 -49 +LINE Normal -128 48 -48 48 +LINE Normal 64 -96 64 -32 +LINE Normal 99 -75 91 -79 +LINE Normal 83 -67 99 -75 +LINE Normal 83 -67 99 -59 +LINE Normal 83 -51 99 -59 +LINE Normal 91 -47 83 -51 +LINE Normal 91 -96 91 -79 +LINE Normal 91 79 91 96 +LINE Normal 99 51 91 47 +LINE Normal 83 59 99 51 +LINE Normal 83 59 99 67 +LINE Normal 83 75 99 67 +LINE Normal 91 79 83 75 +LINE Normal 91 4 91 47 +LINE Normal 91 -47 91 -4 +LINE Normal 103 -4 79 -4 +LINE Normal 103 4 79 4 +LINE Normal 176 -32 91 -32 +LINE Normal 150 -20 126 -20 +LINE Normal 150 -12 126 -12 +LINE Normal 150 12 126 12 +LINE Normal 150 20 126 20 +LINE Normal 138 -32 138 -20 +LINE Normal 138 32 138 20 +LINE Normal 138 32 138 32 +LINE Normal 138 32 138 32 +LINE Normal -63 -48 -63 -48 +LINE Normal 176 -96 176 -96 +LINE Normal 138 12 138 -12 +LINE Normal 116 112 -16 112 +LINE Normal 138 0 116 0 +LINE Normal 176 32 91 32 +LINE Normal 176 -96 64 -96 +LINE Normal 26 -32 64 -32 +LINE Normal 9 32 64 32 +LINE Normal 64 96 64 32 +LINE Normal 116 112 116 0 +LINE Normal -16 -45 -16 -144 +LINE Normal 64 96 176 96 +LINE Normal 138 -32 138 -32 +LINE Normal 138 -32 138 -32 +RECTANGLE Normal 176 144 -128 -144 +CIRCLE Normal 26 -26 14 -38 +CIRCLE Normal 139 1 137 -1 +CIRCLE Normal 140 2 136 -2 +CIRCLE Normal 141 3 135 -3 +CIRCLE Normal 92 -31 90 -33 +CIRCLE Normal 93 -30 89 -34 +CIRCLE Normal 94 -29 88 -35 +CIRCLE Normal 92 33 90 31 +CIRCLE Normal 93 34 89 30 +CIRCLE Normal 94 35 88 29 +CIRCLE Normal 139 33 137 31 +CIRCLE Normal 140 34 136 30 +CIRCLE Normal 141 35 135 29 +CIRCLE Normal 139 -31 137 -33 +CIRCLE Normal 140 -30 136 -34 +CIRCLE Normal 141 -29 135 -35 +CIRCLE Normal 92 -95 90 -97 +CIRCLE Normal 93 -94 89 -98 +CIRCLE Normal 94 -93 88 -99 +CIRCLE Normal 92 97 90 95 +CIRCLE Normal 93 98 89 94 +CIRCLE Normal 94 99 88 93 +CIRCLE Normal -15 113 -17 111 +CIRCLE Normal -14 114 -18 110 +CIRCLE Normal -13 115 -19 109 +TEXT -80 104 Center 2 LT +WINDOW 3 80 128 Center 2 +WINDOW 0 80 -128 Center 2 +SYMATTR Value LTC6406 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Value2 LTC6406 +SYMATTR Description 3GHz, Low Noise, Rail-to-Rail Differential Amplifier/Driver\n\nNote: Distortion is not modeled. +PIN -128 48 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 4 +PINATTR PinName Vocm +PINATTR SpiceOrder 2 +PIN -16 -144 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 176 96 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 4 +PIN 176 -96 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 5 +PIN -16 144 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 6 +PIN -80 -144 TOP 10 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 -48 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 +PIN 176 -32 NONE 8 +PINATTR PinName OUTF+ +PINATTR SpiceOrder 9 +PIN 176 32 NONE 8 +PINATTR PinName OUTF- +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6409.asy b/spice/copy/sym/OpAmps/LTC6409.asy new file mode 100755 index 0000000..7ca42c0 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6409.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -32 -56 -32 +LINE Normal -45 32 -55 32 +LINE Normal -50 37 -50 27 +LINE Normal 32 -32 96 -32 +LINE Normal 55 32 96 32 +LINE Normal 2 25 5 28 +LINE Normal -2 25 2 25 +LINE Normal -5 28 -2 25 +LINE Normal -5 32 -5 28 +LINE Normal -2 34 -5 32 +LINE Normal 2 34 -2 34 +LINE Normal 5 36 2 34 +LINE Normal 5 40 5 36 +LINE Normal 2 42 5 40 +LINE Normal -2 42 2 42 +LINE Normal -5 39 -2 42 +LINE Normal 0 80 0 48 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal -27 55 -37 55 +LINE Normal -52 6 -56 -8 +LINE Normal -48 -8 -52 6 +LINE Normal -47 6 -47 1 +LINE Normal -43 6 -47 6 +LINE Normal -43 1 -43 6 +LINE Normal -47 1 -43 1 +LINE Normal -40 1 -36 1 +LINE Normal -40 6 -40 1 +LINE Normal -36 6 -40 6 +LINE Normal -33 1 -33 6 +LINE Normal -31 4 -33 1 +LINE Normal -29 1 -31 4 +LINE Normal -29 6 -29 1 +LINE Normal 6 22 -6 22 +CIRCLE Normal 55 39 41 25 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LTC6409 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6409 +SYMATTR Description 10GHz GBW, 1.1nV/ Hz½ Differential Amplifier/ADC Driver +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 1 +PIN -64 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 2 +PIN 0 80 NONE 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 4 +PIN -64 0 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 5 +PIN -64 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 7 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6416.asy b/spice/copy/sym/OpAmps/LTC6416.asy new file mode 100755 index 0000000..fa0f71e --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6416.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType BLOCK +LINE Normal -192 176 -192 -176 +LINE Normal 96 0 -192 176 +LINE Normal -192 -176 96 0 +LINE Normal 44 -32 80 -32 +LINE Normal 44 32 80 32 +LINE Normal -64 112 -64 98 +LINE Normal -64 -98 -64 -112 +TEXT -80 0 Center 2 LT +WINDOW 3 -16 96 Left 2 +WINDOW 0 -16 -96 Left 2 +SYMATTR Value LTC6416 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6416 +SYMATTR Description 2GHz Low Noise Differential 16-Bit ADC Buffer +PIN -192 -128 LEFT 8 +PINATTR PinName VCM +PINATTR SpiceOrder 1 +PIN -192 -64 LEFT 8 +PINATTR PinName CLHI +PINATTR SpiceOrder 2 +PIN -192 0 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -192 64 LEFT 8 +PINATTR PinName IN- +PINATTR SpiceOrder 4 +PIN -192 128 LEFT 8 +PINATTR PinName CLLO +PINATTR SpiceOrder 5 +PIN -64 112 VLEFT 24 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 80 32 RIGHT 48 +PINATTR PinName OUT- +PINATTR SpiceOrder 7 +PIN 80 -32 RIGHT 46 +PINATTR PinName OUT+ +PINATTR SpiceOrder 8 +PIN -64 -112 VRIGHT 20 +PINATTR PinName V+ +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/OpAmps/LTC6417.asy b/spice/copy/sym/OpAmps/LTC6417.asy new file mode 100755 index 0000000..f009b57 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6417.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +LINE Normal -160 256 -160 -256 +LINE Normal 240 0 -160 256 +LINE Normal -160 -256 240 0 +LINE Normal 165 -48 208 -48 +LINE Normal 165 48 208 48 +LINE Normal -128 256 -128 236 +LINE Normal -128 -236 -128 -256 +LINE Normal 64 128 64 113 +LINE Normal -32 192 -32 174 +LINE Normal -32 -174 -32 -192 +TEXT 0 0 Center 2 LT +WINDOW 3 112 96 Left 2 +WINDOW 0 112 -112 Left 2 +SYMATTR Value LTC6417 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6417 +SYMATTR Description 1.6GHz Low Noise High Linearity Differential Buffer/ 16-Bit ADC Driver with Fast Clamp +PIN -128 -256 VRIGHT 30 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -128 256 VLEFT 30 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName IN- +PINATTR SpiceOrder 4 +PIN 208 -48 RIGHT 50 +PINATTR PinName OUT+ +PINATTR SpiceOrder 5 +PIN 208 48 RIGHT 50 +PINATTR PinName OUT- +PINATTR SpiceOrder 6 +PIN -160 144 LEFT 8 +PINATTR PinName VCM +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName CLHI +PINATTR SpiceOrder 8 +PIN -32 -192 VRIGHT 30 +PINATTR PinName PWRADJ +PINATTR SpiceOrder 9 +PIN -32 192 VLEFT 30 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 +PIN 64 128 VLEFT 30 +PINATTR PinName V _OR +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/OpAmps/LTC6419.asy b/spice/copy/sym/OpAmps/LTC6419.asy new file mode 100755 index 0000000..0f3b119 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6419.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType BLOCK +LINE Normal -64 80 -64 -80 +LINE Normal 96 0 -64 80 +LINE Normal -64 -80 96 0 +LINE Normal -46 -32 -56 -32 +LINE Normal -45 32 -55 32 +LINE Normal -50 37 -50 27 +LINE Normal 32 -32 96 -32 +LINE Normal 55 32 96 32 +LINE Normal 2 25 5 28 +LINE Normal -2 25 2 25 +LINE Normal -5 28 -2 25 +LINE Normal -5 32 -5 28 +LINE Normal -2 34 -5 32 +LINE Normal 2 34 -2 34 +LINE Normal 5 36 2 34 +LINE Normal 5 40 5 36 +LINE Normal 2 42 5 40 +LINE Normal -2 42 2 42 +LINE Normal -5 39 -2 42 +LINE Normal 0 80 0 48 +LINE Normal -32 80 -32 64 +LINE Normal -32 -64 -32 -80 +LINE Normal -27 -55 -37 -55 +LINE Normal -32 -50 -32 -60 +LINE Normal -27 55 -37 55 +LINE Normal -52 6 -56 -8 +LINE Normal -48 -8 -52 6 +LINE Normal -47 6 -47 1 +LINE Normal -43 6 -47 6 +LINE Normal -43 1 -43 6 +LINE Normal -47 1 -43 1 +LINE Normal -40 1 -36 1 +LINE Normal -40 6 -40 1 +LINE Normal -36 6 -40 6 +LINE Normal -33 1 -33 6 +LINE Normal -31 4 -33 1 +LINE Normal -29 1 -31 4 +LINE Normal -29 6 -29 1 +LINE Normal 6 22 -6 22 +CIRCLE Normal 55 39 41 25 +WINDOW 3 16 64 Left 2 +WINDOW 0 16 -64 Left 2 +SYMATTR Value LTC6419 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC6409 +SYMATTR Description Dual 10GHz GBW, 1.1nV/ Hz½ Differential Amplifier/ADC Driver +PIN 96 32 NONE 8 +PINATTR PinName OUT- +PINATTR SpiceOrder 1 +PIN -64 32 NONE 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 2 +PIN 0 80 NONE 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN -32 -80 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 4 +PIN -64 0 NONE 8 +PINATTR PinName VOCM +PINATTR SpiceOrder 5 +PIN -64 -32 NONE 8 +PINATTR PinName IN- +PINATTR SpiceOrder 6 +PIN 96 -32 NONE 8 +PINATTR PinName OUT+ +PINATTR SpiceOrder 7 +PIN -32 80 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6560.asy b/spice/copy/sym/OpAmps/LTC6560.asy new file mode 100755 index 0000000..c344823 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6560.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 95 Center 2 +SYMATTR Value LTC6560 +SYMATTR Value2 LTC6560 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Description Single Channel Transimpedance Amplifier with Output Multiplexing +PIN 96 -160 TOP 8 +PINATTR PinName Vcco +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 5 +PIN -176 64 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 6 +PIN -64 -160 TOP 8 +PINATTR PinName Vcci +PINATTR SpiceOrder 11 +PIN 96 160 BOTTOM 8 +PINATTR PinName O_Mux +PINATTR SpiceOrder 12 +PIN 176 64 RIGHT 8 +PINATTR PinName OutTerm +PINATTR SpiceOrder 14 +PIN 176 -64 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 15 +PIN -64 160 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/OpAmps/LTC6561.asy b/spice/copy/sym/OpAmps/LTC6561.asy new file mode 100755 index 0000000..c8663d9 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6561.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -304 240 368 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 89 Center 2 +SYMATTR Value LTC6561 +SYMATTR Value2 LTC6561 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7.lib +SYMATTR Description Four-Channel Multiplexed Transimpedance Amplifier with Output Multiplexing +PIN 144 -304 TOP 8 +PINATTR PinName Vcco +PINATTR SpiceOrder 1 +PIN 48 368 BOTTOM 8 +PINATTR PinName chsel0 +PINATTR SpiceOrder 2 +PIN -144 -304 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -256 -176 LEFT 8 +PINATTR PinName Vref1 +PINATTR SpiceOrder 4 +PIN -256 -16 LEFT 8 +PINATTR PinName Vref2 +PINATTR SpiceOrder 5 +PIN -256 144 LEFT 8 +PINATTR PinName Vref3 +PINATTR SpiceOrder 6 +PIN -256 304 LEFT 8 +PINATTR PinName Vref4 +PINATTR SpiceOrder 7 +PIN -144 368 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 8 +PIN -256 -256 LEFT 8 +PINATTR PinName In1 +PINATTR SpiceOrder 9 +PIN -256 -96 LEFT 8 +PINATTR PinName In2 +PINATTR SpiceOrder 10 +PIN -256 64 LEFT 8 +PINATTR PinName In3 +PINATTR SpiceOrder 11 +PIN -256 224 LEFT 8 +PINATTR PinName In4 +PINATTR SpiceOrder 12 +PIN 144 368 BOTTOM 8 +PINATTR PinName O_Mux +PINATTR SpiceOrder 13 +PIN -48 368 BOTTOM 8 +PINATTR PinName chsel1 +PINATTR SpiceOrder 14 +PIN 240 -96 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 15 +PIN 240 144 RIGHT 8 +PINATTR PinName OutTerm +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/OpAmps/LTC6910-1.asy b/spice/copy/sym/OpAmps/LTC6910-1.asy new file mode 100755 index 0000000..25afc56 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6910-1.asy @@ -0,0 +1,39 @@ +Version 4 +SymbolType CELL +LINE Normal -112 -96 -112 96 +LINE Normal 80 -96 -112 -96 +LINE Normal 144 0 80 -96 +LINE Normal 144 0 80 96 +LINE Normal 80 96 -112 96 +TEXT -8 0 Center 2 LT +WINDOW 0 -8 -40 Center 2 +WINDOW 3 -8 42 Center 2 +SYMATTR Value LTC6910-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.LIB +SYMATTR Value2 LTC6910-1 +SYMATTR Description Digitally Controlled Programmable Gain Amplifiers in SOT-23 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -48 96 BOTTOM 4 +PINATTR PinName AGND +PINATTR SpiceOrder 2 +PIN -112 0 LEFT 4 +PINATTR PinName IN +PINATTR SpiceOrder 3 +PIN 64 96 BOTTOM 4 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName G0 +PINATTR SpiceOrder 5 +PIN -32 -96 TOP 4 +PINATTR PinName G1 +PINATTR SpiceOrder 6 +PIN 16 -96 TOP 4 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 64 -96 TOP 4 +PINATTR PinName V+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6910-2.asy b/spice/copy/sym/OpAmps/LTC6910-2.asy new file mode 100755 index 0000000..58e2071 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6910-2.asy @@ -0,0 +1,39 @@ +Version 4 +SymbolType CELL +LINE Normal -112 -96 -112 96 +LINE Normal 80 -96 -112 -96 +LINE Normal 144 0 80 -96 +LINE Normal 144 0 80 96 +LINE Normal 80 96 -112 96 +TEXT -8 0 Center 2 LT +WINDOW 0 -8 -40 Center 2 +WINDOW 3 -8 42 Center 2 +SYMATTR Value LTC6910-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.LIB +SYMATTR Value2 LTC6910-2 +SYMATTR Description Digitally Controlled Programmable Gain Amplifiers in SOT-23 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -48 96 BOTTOM 4 +PINATTR PinName AGND +PINATTR SpiceOrder 2 +PIN -112 0 LEFT 4 +PINATTR PinName IN +PINATTR SpiceOrder 3 +PIN 64 96 BOTTOM 4 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName G0 +PINATTR SpiceOrder 5 +PIN -32 -96 TOP 4 +PINATTR PinName G1 +PINATTR SpiceOrder 6 +PIN 16 -96 TOP 4 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 64 -96 TOP 4 +PINATTR PinName V+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6910-3.asy b/spice/copy/sym/OpAmps/LTC6910-3.asy new file mode 100755 index 0000000..bff4c15 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6910-3.asy @@ -0,0 +1,39 @@ +Version 4 +SymbolType CELL +LINE Normal -112 -96 -112 96 +LINE Normal 80 -96 -112 -96 +LINE Normal 144 0 80 -96 +LINE Normal 144 0 80 96 +LINE Normal 80 96 -112 96 +TEXT -8 0 Center 2 LT +WINDOW 0 -8 -40 Center 2 +WINDOW 3 -8 42 Center 2 +SYMATTR Value LTC6910-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.LIB +SYMATTR Value2 LTC6910-3 +SYMATTR Description Digitally Controlled Programmable Gain Amplifiers in SOT-23 +PIN 144 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -48 96 BOTTOM 4 +PINATTR PinName AGND +PINATTR SpiceOrder 2 +PIN -112 0 LEFT 4 +PINATTR PinName IN +PINATTR SpiceOrder 3 +PIN 64 96 BOTTOM 4 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName G0 +PINATTR SpiceOrder 5 +PIN -32 -96 TOP 4 +PINATTR PinName G1 +PINATTR SpiceOrder 6 +PIN 16 -96 TOP 4 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 64 -96 TOP 4 +PINATTR PinName V+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/OpAmps/LTC6911-1.asy b/spice/copy/sym/OpAmps/LTC6911-1.asy new file mode 100755 index 0000000..c3d20e9 --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6911-1.asy @@ -0,0 +1,51 @@ +Version 4 +SymbolType CELL +LINE Normal -48 -32 -48 -96 +LINE Normal 16 -64 -48 -32 +LINE Normal -48 -96 16 -64 +LINE Normal 80 -64 16 -64 +LINE Normal -47 -64 -112 -64 +LINE Normal -48 96 -48 32 +LINE Normal 16 64 -48 96 +LINE Normal -48 32 16 64 +LINE Normal 80 64 16 64 +LINE Normal -47 64 -112 64 +RECTANGLE Normal 80 160 -112 -128 +TEXT 28 0 Center 2 LT +WINDOW 0 -16 -105 Center 2 +WINDOW 3 -16 111 Center 2 +SYMATTR Value LTC6911-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.LIB +SYMATTR Value2 LTC6911-1 +SYMATTR Description Dual Matched Amplifiers with Digitally Programmable Gain in MSOP +PIN -112 -64 NONE 4 +PINATTR PinName INA +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 6 +PINATTR PinName AGND +PINATTR SpiceOrder 2 +PIN -112 64 NONE 4 +PINATTR PinName INB +PINATTR SpiceOrder 3 +PIN -80 160 BOTTOM 4 +PINATTR PinName G0 +PINATTR SpiceOrder 4 +PIN -16 160 BOTTOM 4 +PINATTR PinName G1 +PINATTR SpiceOrder 5 +PIN 48 160 BOTTOM 4 +PINATTR PinName G2 +PINATTR SpiceOrder 6 +PIN -64 -128 TOP 4 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 80 64 NONE 0 +PINATTR PinName OUTB +PINATTR SpiceOrder 8 +PIN 32 -128 TOP 4 +PINATTR PinName V- +PINATTR SpiceOrder 9 +PIN 80 -64 NONE 0 +PINATTR PinName OUTA +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC6911-2.asy b/spice/copy/sym/OpAmps/LTC6911-2.asy new file mode 100755 index 0000000..14a485b --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC6911-2.asy @@ -0,0 +1,51 @@ +Version 4 +SymbolType CELL +LINE Normal -48 -32 -48 -96 +LINE Normal 16 -64 -48 -32 +LINE Normal -48 -96 16 -64 +LINE Normal 80 -64 16 -64 +LINE Normal -47 -64 -112 -64 +LINE Normal -48 96 -48 32 +LINE Normal 16 64 -48 96 +LINE Normal -48 32 16 64 +LINE Normal 80 64 16 64 +LINE Normal -47 64 -112 64 +RECTANGLE Normal 80 160 -112 -128 +TEXT 28 0 Center 2 LT +WINDOW 0 -16 -105 Center 2 +WINDOW 3 -16 111 Center 2 +SYMATTR Value LTC6911-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.LIB +SYMATTR Value2 LTC6911-2 +SYMATTR Description Dual Matched Amplifiers with Digitally Programmable Gain in MSOP +PIN -112 -64 NONE 4 +PINATTR PinName INA +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 6 +PINATTR PinName AGND +PINATTR SpiceOrder 2 +PIN -112 64 NONE 4 +PINATTR PinName INB +PINATTR SpiceOrder 3 +PIN -80 160 BOTTOM 4 +PINATTR PinName G0 +PINATTR SpiceOrder 4 +PIN -16 160 BOTTOM 4 +PINATTR PinName G1 +PINATTR SpiceOrder 5 +PIN 48 160 BOTTOM 4 +PINATTR PinName G2 +PINATTR SpiceOrder 6 +PIN -64 -128 TOP 4 +PINATTR PinName V+ +PINATTR SpiceOrder 7 +PIN 80 64 NONE 0 +PINATTR PinName OUTB +PINATTR SpiceOrder 8 +PIN 32 -128 TOP 4 +PINATTR PinName V- +PINATTR SpiceOrder 9 +PIN 80 -64 NONE 0 +PINATTR PinName OUTA +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/OpAmps/LTC7652.asy b/spice/copy/sym/OpAmps/LTC7652.asy new file mode 100755 index 0000000..94bbfdd --- /dev/null +++ b/spice/copy/sym/OpAmps/LTC7652.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LTC7652 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LTC1052 +SYMATTR Description Chopper-Stabilized Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP07.asy b/spice/copy/sym/OpAmps/OP07.asy new file mode 100755 index 0000000..61382e9 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP07.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP07 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1001 +SYMATTR Description Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP113.asy b/spice/copy/sym/OpAmps/OP113.asy new file mode 100755 index 0000000..fd2636b --- /dev/null +++ b/spice/copy/sym/OpAmps/OP113.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP113 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP113 +SYMATTR Description 4/30V BIP OP Low Noise Low Drift +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP1177.asy b/spice/copy/sym/OpAmps/OP1177.asy new file mode 100755 index 0000000..c0666a7 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP1177.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP1177 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 OP1177 +SYMATTR Description Precision, Low Noise, Low Input Bias Current Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP177A.asy b/spice/copy/sym/OpAmps/OP177A.asy new file mode 100755 index 0000000..1a0edcd --- /dev/null +++ b/spice/copy/sym/OpAmps/OP177A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP177A +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP177A +SYMATTR Description Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP191.asy b/spice/copy/sym/OpAmps/OP191.asy new file mode 100755 index 0000000..1a06222 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP191.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP191 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP191 +SYMATTR Description 2.7/12V BIP OP RRIO OVP +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP213.asy b/spice/copy/sym/OpAmps/OP213.asy new file mode 100755 index 0000000..6476f56 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP213.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP213 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP213 +SYMATTR Description 4/30V BIP OP Low Noise Low Drift +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP2177.asy b/spice/copy/sym/OpAmps/OP2177.asy new file mode 100755 index 0000000..2557a6e --- /dev/null +++ b/spice/copy/sym/OpAmps/OP2177.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP2177 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 OP2177 +SYMATTR Description Dual Precision Low Noise Low Input Bias Current Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP227.asy b/spice/copy/sym/OpAmps/OP227.asy new file mode 100755 index 0000000..3bc2fd1 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP227.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP227 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP27 +SYMATTR Description Dual Low Noise, Precision, High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP27.asy b/spice/copy/sym/OpAmps/OP27.asy new file mode 100755 index 0000000..c72e118 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP27.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP27 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP27 +SYMATTR Description Low Noise, Precision, High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP284.asy b/spice/copy/sym/OpAmps/OP284.asy new file mode 100755 index 0000000..328061a --- /dev/null +++ b/spice/copy/sym/OpAmps/OP284.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP284 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 OP284 +SYMATTR Description Precision Rail to Rail I/O Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP291.asy b/spice/copy/sym/OpAmps/OP291.asy new file mode 100755 index 0000000..f5d805d --- /dev/null +++ b/spice/copy/sym/OpAmps/OP291.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP291 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP291 +SYMATTR Description 2.7/12V BIP OP RRIO OVP +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP292.asy b/spice/copy/sym/OpAmps/OP292.asy new file mode 100755 index 0000000..84104c0 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP292.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP292 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 OP292 +SYMATTR Description Dual Single-Supply Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP296.asy b/spice/copy/sym/OpAmps/OP296.asy new file mode 100755 index 0000000..ae338a0 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP296.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP296 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP296 +SYMATTR Description 3/15V BIP OP Low Pwr RRIO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP37.asy b/spice/copy/sym/OpAmps/OP37.asy new file mode 100755 index 0000000..330cddc --- /dev/null +++ b/spice/copy/sym/OpAmps/OP37.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP37 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP37 +SYMATTR Description Low Noise, Precision, High Speed Operational Amplifier(Avcl > -5) +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP413.asy b/spice/copy/sym/OpAmps/OP413.asy new file mode 100755 index 0000000..7d19971 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP413.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP413 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP413 +SYMATTR Description 4/30V BIP OP Low Noise Low Drift +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP4177.asy b/spice/copy/sym/OpAmps/OP4177.asy new file mode 100755 index 0000000..943d3a1 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP4177.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP4177 +SYMATTR Prefix X +SYMATTR SpiceModel ADI1.lib +SYMATTR Value2 OP4177 +SYMATTR Description Quad Precision Low Noise Low Input Bias Current Op Amp +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP491.asy b/spice/copy/sym/OpAmps/OP491.asy new file mode 100755 index 0000000..5498021 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP491.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP491 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP491 +SYMATTR Description 2.7/12V BIP OP RRIO OVP +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP492.asy b/spice/copy/sym/OpAmps/OP492.asy new file mode 100755 index 0000000..5dd591f --- /dev/null +++ b/spice/copy/sym/OpAmps/OP492.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP492 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP492 +SYMATTR Description 4.5/33V BIP OP Low Cost Single Supply +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP495.asy b/spice/copy/sym/OpAmps/OP495.asy new file mode 100755 index 0000000..0c6dad1 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP495.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP495 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP495 +SYMATTR Description 3/30V BIP OP RRO Single Supply +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP727.asy b/spice/copy/sym/OpAmps/OP727.asy new file mode 100755 index 0000000..b35ee5e --- /dev/null +++ b/spice/copy/sym/OpAmps/OP727.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP727 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP727 +SYMATTR Description 2.7/30V BIP OP Single Supply RRO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP747.asy b/spice/copy/sym/OpAmps/OP747.asy new file mode 100755 index 0000000..347ab36 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP747.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP747 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP747 +SYMATTR Description 2.7/30V BIP OP Single Supply RRO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP77.asy b/spice/copy/sym/OpAmps/OP77.asy new file mode 100755 index 0000000..45266bb --- /dev/null +++ b/spice/copy/sym/OpAmps/OP77.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP77 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP77 +SYMATTR Description Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/OP777.asy b/spice/copy/sym/OpAmps/OP777.asy new file mode 100755 index 0000000..9320d41 --- /dev/null +++ b/spice/copy/sym/OpAmps/OP777.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value OP777 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 OP777 +SYMATTR Description 2.7/30V BIP OP Single Supply RRO +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/RH101A.asy b/spice/copy/sym/OpAmps/RH101A.asy new file mode 100755 index 0000000..3e4269c --- /dev/null +++ b/spice/copy/sym/OpAmps/RH101A.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 20 44 28 44 +LINE Normal 24 40 24 48 +LINE Normal 4 84 12 84 +LINE Normal 16 32 16 56 +LINE Normal -16 32 -16 40 +WINDOW 0 32 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value RH101A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 RH101A +SYMATTR Description Operational Amplifier\n\nNOTE: Model is best effort of typical performance at room temperature. +PIN -16 32 NONE 0 +PINATTR PinName COMP1 +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN 16 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 6 +PIN 0 32 NONE 0 +PINATTR PinName COMP2 +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/RH1028.asy b/spice/copy/sym/OpAmps/RH1028.asy new file mode 100755 index 0000000..65533d1 --- /dev/null +++ b/spice/copy/sym/OpAmps/RH1028.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 19 43 Left 2 +WINDOW 3 19 93 Left 2 +SYMATTR Value RH1028 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1028 +SYMATTR Description Ultra-Low Noise Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/RH1056A.asy b/spice/copy/sym/OpAmps/RH1056A.asy new file mode 100755 index 0000000..fc14be5 --- /dev/null +++ b/spice/copy/sym/OpAmps/RH1056A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value RH1056A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1056 +SYMATTR Description Precision, High Speed, JFET Input Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/RH1128.asy b/spice/copy/sym/OpAmps/RH1128.asy new file mode 100755 index 0000000..4ecc0e2 --- /dev/null +++ b/spice/copy/sym/OpAmps/RH1128.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 19 43 Left 2 +WINDOW 3 20 89 Left 2 +SYMATTR Value RH1128 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1128 +SYMATTR Description Ultra-Low Noise Precision High Speed Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/RH1498.asy b/spice/copy/sym/OpAmps/RH1498.asy new file mode 100755 index 0000000..d500abe --- /dev/null +++ b/spice/copy/sym/OpAmps/RH1498.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value RH1498 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1498 +SYMATTR Description Dual 10MHz, 6V/µs, Rail-to-Rail Input and Output Precision C-Load Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/RH1814.asy b/spice/copy/sym/OpAmps/RH1814.asy new file mode 100755 index 0000000..3b58c67 --- /dev/null +++ b/spice/copy/sym/OpAmps/RH1814.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Value RH1814 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1813 +SYMATTR Description Quad 3mA, 100MHz, 750V/µs Operational Amplifier(1 of 4) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/RH27C.asy b/spice/copy/sym/OpAmps/RH27C.asy new file mode 100755 index 0000000..01c8027 --- /dev/null +++ b/spice/copy/sym/OpAmps/RH27C.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value RH27C +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 RH27C +SYMATTR Description Low noise High Speed Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/RH37C.asy b/spice/copy/sym/OpAmps/RH37C.asy new file mode 100755 index 0000000..88ccce3 --- /dev/null +++ b/spice/copy/sym/OpAmps/RH37C.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value RH37C +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 RH37C +SYMATTR Description Low noise High Speed Precision Operational Amplifier +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/RH6200.asy b/spice/copy/sym/OpAmps/RH6200.asy new file mode 100755 index 0000000..6995f78 --- /dev/null +++ b/spice/copy/sym/OpAmps/RH6200.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -80 112 0 +LINE Normal -32 80 112 0 +LINE Normal -32 -80 -32 80 +LINE Normal 0 80 0 62 +LINE Normal 0 -80 0 -62 +LINE Normal 48 80 48 36 +LINE Normal 52 28 44 28 +LINE Normal 52 28 52 20 +LINE Normal 44 20 52 20 +LINE Normal 44 20 44 12 +LINE Normal 52 12 44 12 +LINE Normal -20 -32 -12 -32 +LINE Normal -20 32 -12 32 +LINE Normal -16 28 -16 36 +LINE Normal 4 -72 12 -72 +LINE Normal 8 -68 8 -76 +LINE Normal 4 72 12 72 +LINE Normal 57 7 39 7 +WINDOW 0 52 -63 Left 2 +WINDOW 3 56 56 Left 2 +SYMATTR Value RH6200 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.LIB +SYMATTR Value2 LT6200 +SYMATTR Description 165 MHz, Rail-to-Rail Input and Output, 0.95nV/rtHz Low Noise Op Amp +PIN -32 32 NONE 0 +PINATTR PinName IN+ +PINATTR SpiceOrder 1 +PIN -32 -32 NONE 0 +PINATTR PinName IN- +PINATTR SpiceOrder 2 +PIN 112 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -80 NONE 0 +PINATTR PinName VCC +PINATTR SpiceOrder 4 +PIN 0 80 NONE 0 +PINATTR PinName VEE +PINATTR SpiceOrder 5 +PIN 48 80 NONE 0 +PINATTR PinName SHDN_L +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/OpAmps/SSM2141.asy b/spice/copy/sym/OpAmps/SSM2141.asy new file mode 100755 index 0000000..734205c --- /dev/null +++ b/spice/copy/sym/OpAmps/SSM2141.asy @@ -0,0 +1,89 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -27 16 -19 16 +LINE Normal -23 20 -23 12 +LINE Normal 0 -112 0 -16 +LINE Normal 0 112 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +LINE Normal -92 -70 -96 -64 +LINE Normal -64 -64 -68 -58 +LINE Normal -68 -58 -76 -70 +LINE Normal -84 -58 -76 -70 +LINE Normal -84 -58 -92 -70 +LINE Normal -92 58 -96 64 +LINE Normal -64 64 -68 70 +LINE Normal -68 70 -76 58 +LINE Normal -84 70 -76 58 +LINE Normal -84 70 -92 58 +LINE Normal -48 16 -32 16 +LINE Normal -48 16 -48 64 +LINE Normal -48 -16 -32 -16 +LINE Normal -48 -64 -48 -16 +LINE Normal 20 -70 16 -64 +LINE Normal 48 -64 44 -58 +LINE Normal 44 -58 36 -70 +LINE Normal 28 -58 36 -70 +LINE Normal 28 -58 20 -70 +LINE Normal 16 -64 -64 -64 +LINE Normal 64 -64 48 -64 +LINE Normal 32 0 64 0 +LINE Normal 16 64 -64 64 +LINE Normal 20 58 16 64 +LINE Normal 48 64 44 70 +LINE Normal 44 70 36 58 +LINE Normal 28 70 36 58 +LINE Normal 28 70 20 58 +LINE Normal 64 64 48 64 +LINE Normal -128 -64 -96 -64 +LINE Normal -128 64 -96 64 +RECTANGLE Normal 64 112 -128 -112 +CIRCLE Normal -47 65 -49 63 +CIRCLE Normal -46 66 -50 62 +CIRCLE Normal -45 67 -51 61 +CIRCLE Normal -47 -63 -49 -65 +CIRCLE Normal -46 -62 -50 -66 +CIRCLE Normal -45 -61 -51 -67 +CIRCLE Normal -47 -63 -49 -65 +CIRCLE Normal -46 -62 -50 -66 +CIRCLE Normal -45 -61 -51 -67 +CIRCLE Normal -47 65 -49 63 +CIRCLE Normal -46 66 -50 62 +CIRCLE Normal -45 67 -51 61 +TEXT -79 -70 Bottom 1 25K +TEXT -78 58 Bottom 1 25K +TEXT 33 -70 Bottom 1 25K +TEXT 33 58 Bottom 1 25K +TEXT -64 90 Center 2 ADI +WINDOW 3 -10 128 Right 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADI.lib +SYMATTR Value2 SSM2141 +SYMATTR Description High Common-Mode Rejection Differential Line Receiver +SYMATTR Value SSM2141 +PIN 64 64 NONE 0 +PINATTR PinName Ref +PINATTR SpiceOrder 1 +PIN -128 -64 NONE 0 +PINATTR PinName -IN +PINATTR SpiceOrder 2 +PIN -128 64 NONE 0 +PINATTR PinName +IN +PINATTR SpiceOrder 3 +PIN 0 112 NONE 0 +PINATTR PinName Vee +PINATTR SpiceOrder 4 +PIN 64 -64 NONE 0 +PINATTR PinName SENSE +PINATTR SpiceOrder 5 +PIN 64 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 0 -112 NONE 0 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/OpAmps/UniversalOpamp2.asy b/spice/copy/sym/OpAmps/UniversalOpamp2.asy new file mode 100755 index 0000000..f3f74a5 --- /dev/null +++ b/spice/copy/sym/OpAmps/UniversalOpamp2.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 32 0 +LINE Normal -32 32 32 0 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -32 0 -16 +LINE Normal 0 32 0 16 +LINE Normal 4 -20 12 -20 +LINE Normal 8 -24 8 -16 +LINE Normal 4 20 12 20 +WINDOW 0 16 -32 Left 2 +SYMATTR SpiceModel level.2 +SYMATTR Prefix X +SYMATTR Description Universal Opamp model that allows 4 different levels of simulation accuracy. See ./examples/Educational/UniversalOpamp2.asc for details. En and in are equivalent voltage and current noises. Enk and ink are the respective corner frequencies. Phimargin is used to set the 2nd pole or delay to the approximate phase margin for level.3a and level.3b. This version uses the new, experimental level 2 switch as the output devices. +SYMATTR Value2 Avol=1Meg GBW=10Meg Slew=10Meg +SYMATTR SpiceLine ilimit=25m rail=0 Vos=0 phimargin=45 +SYMATTR SpiceLine2 en=0 enk=0 in=0 ink=0 Rin=500Meg +SYMATTR ModelFile UniversalOpamps2.sub +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 32 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/OpAmps/opamp.asy b/spice/copy/sym/OpAmps/opamp.asy new file mode 100755 index 0000000..61933b7 --- /dev/null +++ b/spice/copy/sym/OpAmps/opamp.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +WINDOW 0 0 32 Left 2 +SYMATTR Prefix X +SYMATTR Description Ideal single-pole operational amplifier. You must .lib opamp.sub +SYMATTR Value opamp +SYMATTR SpiceLine Aol=100K +SYMATTR SpiceLine2 GBW=10Meg +PIN -32 48 NONE 0 +PINATTR PinName invin +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName noninvin +PINATTR SpiceOrder 2 +PIN 32 64 NONE 0 +PINATTR PinName out +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/OpAmps/opamp2.asy b/spice/copy/sym/OpAmps/opamp2.asy new file mode 100755 index 0000000..02c06be --- /dev/null +++ b/spice/copy/sym/OpAmps/opamp2.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 32 64 +LINE Normal -32 96 32 64 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 0 32 0 48 +LINE Normal 0 96 0 80 +LINE Normal 4 44 12 44 +LINE Normal 8 40 8 48 +LINE Normal 4 84 12 84 +WINDOW 0 16 32 Left 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value opamp2 +SYMATTR Prefix X +SYMATTR Description Basic Operational Amplifier symbol for use with subcircuits in the file ./lib/sub/LTC.lib. You must give the value a name and include this file. +PIN -32 80 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 96 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 32 64 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/4N25.asy b/spice/copy/sym/Optos/4N25.asy new file mode 100755 index 0000000..3247a91 --- /dev/null +++ b/spice/copy/sym/Optos/4N25.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value 4N25 +SYMATTR Prefix X +SYMATTR SpiceModel 4N25.sub +SYMATTR Value2 4N25 +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/4N25A.asy b/spice/copy/sym/Optos/4N25A.asy new file mode 100755 index 0000000..965d7e1 --- /dev/null +++ b/spice/copy/sym/Optos/4N25A.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value 4N25A +SYMATTR Prefix X +SYMATTR SpiceModel 4N25.sub +SYMATTR Value2 4N25 +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/4N26.asy b/spice/copy/sym/Optos/4N26.asy new file mode 100755 index 0000000..92f23e9 --- /dev/null +++ b/spice/copy/sym/Optos/4N26.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value 4N26 +SYMATTR Prefix X +SYMATTR SpiceModel 4N25.sub +SYMATTR Value2 4N25 +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/4N27.asy b/spice/copy/sym/Optos/4N27.asy new file mode 100755 index 0000000..03e8359 --- /dev/null +++ b/spice/copy/sym/Optos/4N27.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value 4N27 +SYMATTR Prefix X +SYMATTR SpiceModel 4N27.sub +SYMATTR Value2 4N27 +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/4N28.asy b/spice/copy/sym/Optos/4N28.asy new file mode 100755 index 0000000..2a825f9 --- /dev/null +++ b/spice/copy/sym/Optos/4N28.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value 4N28 +SYMATTR Prefix X +SYMATTR SpiceModel 4N27.sub +SYMATTR Value2 4N27 +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/CNY17-1.asy b/spice/copy/sym/Optos/CNY17-1.asy new file mode 100755 index 0000000..2c1ee82 --- /dev/null +++ b/spice/copy/sym/Optos/CNY17-1.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value CNY17-1 +SYMATTR Prefix X +SYMATTR SpiceModel CNY17.sub +SYMATTR Value2 CNY17 Igain=.724m +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/CNY17-2.asy b/spice/copy/sym/Optos/CNY17-2.asy new file mode 100755 index 0000000..b5767b1 --- /dev/null +++ b/spice/copy/sym/Optos/CNY17-2.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value CNY17-2 +SYMATTR Prefix X +SYMATTR SpiceModel CNY17.sub +SYMATTR Value2 CNY17 Igain=1.39m +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/CNY17-3.asy b/spice/copy/sym/Optos/CNY17-3.asy new file mode 100755 index 0000000..9eac6da --- /dev/null +++ b/spice/copy/sym/Optos/CNY17-3.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value CNY17-3 +SYMATTR Prefix X +SYMATTR SpiceModel CNY17.sub +SYMATTR Value2 CNY17 Igain=2.44m +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/MOC205.asy b/spice/copy/sym/Optos/MOC205.asy new file mode 100755 index 0000000..3203572 --- /dev/null +++ b/spice/copy/sym/Optos/MOC205.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value MOC205 +SYMATTR Prefix X +SYMATTR SpiceModel MOC205.sub +SYMATTR Value2 MOC205 Igain=.724m +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/MOC206.asy b/spice/copy/sym/Optos/MOC206.asy new file mode 100755 index 0000000..c73435c --- /dev/null +++ b/spice/copy/sym/Optos/MOC206.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value MOC206 +SYMATTR Prefix X +SYMATTR SpiceModel MOC205.sub +SYMATTR Value2 MOC205 Igain=1.28m +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/MOC207.asy b/spice/copy/sym/Optos/MOC207.asy new file mode 100755 index 0000000..8cbf59b --- /dev/null +++ b/spice/copy/sym/Optos/MOC207.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -64 -56 -64 +LINE Normal -56 -32 -56 -64 +LINE Normal -56 -8 -56 32 +LINE Normal -96 32 -56 32 +LINE Normal -72 -32 -40 -32 +LINE Normal -56 -8 -40 -32 +LINE Normal -56 -8 -72 -32 +LINE Normal -72 -8 -40 -8 +LINE Normal 96 -64 68 -64 +LINE Normal 96 0 72 0 +LINE Normal 40 -32 68 -64 +LINE Normal 40 -32 60 -12 +LINE Normal 40 -48 40 -16 +LINE Normal 72 0 56 -8 +LINE Normal 72 0 64 -16 +LINE Normal 56 -8 64 -16 +LINE Normal 40 -32 32 -32 +LINE Normal 32 32 32 -32 +LINE Normal 32 32 96 32 +LINE Normal 24 -32 12 -36 +LINE Normal 24 -32 20 -44 +LINE Normal 20 -36 24 -32 +RECTANGLE Normal -96 -80 96 48 +ARC Normal -4 -20 20 -44 16 -36 -4 -32 +ARC Normal -28 -20 -4 -44 -28 -28 -4 -32 +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value MOC207 +SYMATTR Prefix X +SYMATTR SpiceModel MOC205.sub +SYMATTR Value2 MOC205 Igain=2.44m +SYMATTR Description Optoisolator, Transistor Output +PIN -96 -64 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 32 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -64 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 0 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 +PIN 96 32 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Optos/PC817A.asy b/spice/copy/sym/Optos/PC817A.asy new file mode 100755 index 0000000..cd01f1d --- /dev/null +++ b/spice/copy/sym/Optos/PC817A.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -48 -56 -48 +LINE Normal -56 -16 -56 -48 +LINE Normal -56 16 -56 48 +LINE Normal -96 48 -56 48 +LINE Normal -80 -16 -32 -16 +LINE Normal -56 16 -32 -16 +LINE Normal -56 16 -80 -16 +LINE Normal -80 16 -32 16 +LINE Normal 96 -48 72 -48 +LINE Normal 32 0 72 -48 +LINE Normal 32 0 68 36 +LINE Normal 32 -28 32 28 +LINE Normal 96 48 80 48 +LINE Normal 80 48 64 40 +LINE Normal 80 48 72 32 +LINE Normal 64 40 72 32 +LINE Normal 24 0 12 -4 +LINE Normal 24 0 20 -12 +LINE Normal 20 -4 24 0 +RECTANGLE Normal -96 -64 96 64 +ARC Normal -4 12 20 -12 16 -4 -4 0 +ARC Normal -28 12 -4 -12 -28 4 -4 0 +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value PC817A +SYMATTR Prefix X +SYMATTR SpiceModel PC817.sub +SYMATTR Value2 PC817 Igain=1m +SYMATTR Description High Density Mounting Type Photocoupler +PIN -96 -48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 48 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 48 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Optos/PC817B.asy b/spice/copy/sym/Optos/PC817B.asy new file mode 100755 index 0000000..f39a0cf --- /dev/null +++ b/spice/copy/sym/Optos/PC817B.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -48 -56 -48 +LINE Normal -56 -16 -56 -48 +LINE Normal -56 16 -56 48 +LINE Normal -96 48 -56 48 +LINE Normal -80 -16 -32 -16 +LINE Normal -56 16 -32 -16 +LINE Normal -56 16 -80 -16 +LINE Normal -80 16 -32 16 +LINE Normal 96 -48 72 -48 +LINE Normal 32 0 72 -48 +LINE Normal 32 0 68 36 +LINE Normal 32 -28 32 28 +LINE Normal 96 48 80 48 +LINE Normal 80 48 64 40 +LINE Normal 80 48 72 32 +LINE Normal 64 40 72 32 +LINE Normal 24 0 12 -4 +LINE Normal 24 0 20 -12 +LINE Normal 20 -4 24 0 +RECTANGLE Normal -96 -64 96 64 +ARC Normal -4 12 20 -12 16 -4 -4 0 +ARC Normal -28 12 -4 -12 -28 4 -4 0 +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value PC817B +SYMATTR Prefix X +SYMATTR SpiceModel PC817.sub +SYMATTR Value2 PC817 Igain=1.5m +SYMATTR Description High Density Mounting Type Photocoupler +PIN -96 -48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 48 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 48 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Optos/PC817C.asy b/spice/copy/sym/Optos/PC817C.asy new file mode 100755 index 0000000..32568ea --- /dev/null +++ b/spice/copy/sym/Optos/PC817C.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -48 -56 -48 +LINE Normal -56 -16 -56 -48 +LINE Normal -56 16 -56 48 +LINE Normal -96 48 -56 48 +LINE Normal -80 -16 -32 -16 +LINE Normal -56 16 -32 -16 +LINE Normal -56 16 -80 -16 +LINE Normal -80 16 -32 16 +LINE Normal 96 -48 72 -48 +LINE Normal 32 0 72 -48 +LINE Normal 32 0 68 36 +LINE Normal 32 -28 32 28 +LINE Normal 96 48 80 48 +LINE Normal 80 48 64 40 +LINE Normal 80 48 72 32 +LINE Normal 64 40 72 32 +LINE Normal 24 0 12 -4 +LINE Normal 24 0 20 -12 +LINE Normal 20 -4 24 0 +RECTANGLE Normal -96 -64 96 64 +ARC Normal -4 12 20 -12 16 -4 -4 0 +ARC Normal -28 12 -4 -12 -28 4 -4 0 +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value PC817C +SYMATTR Prefix X +SYMATTR SpiceModel PC817.sub +SYMATTR Value2 PC817 Igain=2.3m +SYMATTR Description High Density Mounting Type Photocoupler +PIN -96 -48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 48 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 48 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/Optos/PC817D.asy b/spice/copy/sym/Optos/PC817D.asy new file mode 100755 index 0000000..4f1cadb --- /dev/null +++ b/spice/copy/sym/Optos/PC817D.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal -96 -48 -56 -48 +LINE Normal -56 -16 -56 -48 +LINE Normal -56 16 -56 48 +LINE Normal -96 48 -56 48 +LINE Normal -80 -16 -32 -16 +LINE Normal -56 16 -32 -16 +LINE Normal -56 16 -80 -16 +LINE Normal -80 16 -32 16 +LINE Normal 96 -48 72 -48 +LINE Normal 32 0 72 -48 +LINE Normal 32 0 68 36 +LINE Normal 32 -28 32 28 +LINE Normal 96 48 80 48 +LINE Normal 80 48 64 40 +LINE Normal 80 48 72 32 +LINE Normal 64 40 72 32 +LINE Normal 24 0 12 -4 +LINE Normal 24 0 20 -12 +LINE Normal 20 -4 24 0 +RECTANGLE Normal -96 -64 96 64 +ARC Normal -4 12 20 -12 16 -4 -4 0 +ARC Normal -28 12 -4 -12 -28 4 -4 0 +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value PC817D +SYMATTR Prefix X +SYMATTR SpiceModel PC817.sub +SYMATTR Value2 PC817 Igain=3.4m +SYMATTR Description High Density Mounting Type Photocoupler +PIN -96 -48 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN -96 48 NONE 0 +PINATTR PinName K +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 3 +PIN 96 48 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADM7150-1.8.asy b/spice/copy/sym/PowerProducts/ADM7150-1.8.asy new file mode 100755 index 0000000..bbc3ae8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7150-1.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7150-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7150_1.sub +SYMATTR Value2 ADM7150_1 Vreg=3.5 Vref=1.812 +SYMATTR Description 800 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7150-2.8.asy b/spice/copy/sym/PowerProducts/ADM7150-2.8.asy new file mode 100755 index 0000000..0617d9a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7150-2.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7150-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7150_1.sub +SYMATTR Value2 ADM7150_1 Vreg=3.5 Vref=2.812 +SYMATTR Description 800 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7150-3.0.asy b/spice/copy/sym/PowerProducts/ADM7150-3.0.asy new file mode 100755 index 0000000..26f9f56 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7150-3.0.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7150-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7150_1.sub +SYMATTR Value2 ADM7150_1 Vreg=3.6 Vref=3.012 +SYMATTR Description 800 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7150-3.3.asy b/spice/copy/sym/PowerProducts/ADM7150-3.3.asy new file mode 100755 index 0000000..d4654fb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7150-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7150-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7150_1.sub +SYMATTR Value2 ADM7150_1 Vreg=3.9 Vref=3.312 +SYMATTR Description 800 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7150-4.5.asy b/spice/copy/sym/PowerProducts/ADM7150-4.5.asy new file mode 100755 index 0000000..1b692e7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7150-4.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7150-4.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7150_1.sub +SYMATTR Value2 ADM7150_1 Vreg=5.1 Vref=4.512 +SYMATTR Description 800 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7150-4.8.asy b/spice/copy/sym/PowerProducts/ADM7150-4.8.asy new file mode 100755 index 0000000..3d5b3da --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7150-4.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7150-4.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7150_1.sub +SYMATTR Value2 ADM7150_1 Vreg=5.4 Vref=4.812 +SYMATTR Description 800 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7150-5.0.asy b/spice/copy/sym/PowerProducts/ADM7150-5.0.asy new file mode 100755 index 0000000..f4ba7d1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7150-5.0.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7150-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7150_1.sub +SYMATTR Value2 ADM7150_1 Vreg=5.55 Vref=5.012 +SYMATTR Description 800 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7151-02.asy b/spice/copy/sym/PowerProducts/ADM7151-02.asy new file mode 100755 index 0000000..b47a814 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7151-02.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 224 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 105 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7151-02 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7150_1.sub +SYMATTR Value2 ADM7150_1 Vreg=4.5 Vref=1.512 +SYMATTR Description 800 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 160 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 160 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7151-04.asy b/spice/copy/sym/PowerProducts/ADM7151-04.asy new file mode 100755 index 0000000..d02d21c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7151-04.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 224 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 105 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7151-04 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7150_1.sub +SYMATTR Value2 ADM7150_1 Vreg=5.55 Vref=1.512 +SYMATTR Description 800 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 160 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 160 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7154-1.2.asy b/spice/copy/sym/PowerProducts/ADM7154-1.2.asy new file mode 100755 index 0000000..7600b6d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7154-1.2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7154-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7154_5.sub +SYMATTR Value2 ADM7154_5 Vreg=2.1022 Vref=1.2152 +SYMATTR Description 600 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7154-1.8.asy b/spice/copy/sym/PowerProducts/ADM7154-1.8.asy new file mode 100755 index 0000000..ecd12d6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7154-1.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7154-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7154_5.sub +SYMATTR Value2 ADM7154_5 Vreg=2.6022 Vref=1.8154 +SYMATTR Description 600 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7154-2.5.asy b/spice/copy/sym/PowerProducts/ADM7154-2.5.asy new file mode 100755 index 0000000..5264c04 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7154-2.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7154-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7154_5.sub +SYMATTR Value2 ADM7154_5 Vreg=3.2022 Vref=2.5157 +SYMATTR Description 600 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7154-3.0.asy b/spice/copy/sym/PowerProducts/ADM7154-3.0.asy new file mode 100755 index 0000000..27f54ab --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7154-3.0.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7154-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7154_5.sub +SYMATTR Value2 ADM7154_5 Vreg=3.6022 Vref=3.0158 +SYMATTR Description 600 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7154-3.3.asy b/spice/copy/sym/PowerProducts/ADM7154-3.3.asy new file mode 100755 index 0000000..e655277 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7154-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7154-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7154_5.sub +SYMATTR Value2 ADM7154_5 Vreg=3.6022 Vref=3.3160 +SYMATTR Description 600 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7155-01.asy b/spice/copy/sym/PowerProducts/ADM7155-01.asy new file mode 100755 index 0000000..990c756 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7155-01.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 224 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 105 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7155-01 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7154_5.sub +SYMATTR Value2 ADM7154_5 Vreg=2.1022 Vref=1.2152 +SYMATTR Description 600 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 160 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 160 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7155-02.asy b/spice/copy/sym/PowerProducts/ADM7155-02.asy new file mode 100755 index 0000000..d09228a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7155-02.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 224 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 105 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7155-02 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7154_5.sub +SYMATTR Value2 ADM7154_5 Vreg=2.6022 Vref=1.2152 +SYMATTR Description 600 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 160 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 160 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7155-03.asy b/spice/copy/sym/PowerProducts/ADM7155-03.asy new file mode 100755 index 0000000..9637a75 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7155-03.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 224 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 105 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7155-03 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7154_5.sub +SYMATTR Value2 ADM7154_5 Vreg=3.2022 Vref=1.2152 +SYMATTR Description 600 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 160 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 160 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7155-04.asy b/spice/copy/sym/PowerProducts/ADM7155-04.asy new file mode 100755 index 0000000..ede2719 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7155-04.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 224 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 105 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADM7155-04 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7154_5.sub +SYMATTR Value2 ADM7154_5 Vreg=3.6022 Vref=1.2152 +SYMATTR Description 600 mA, Ultralow Noise, High PSRR, RF Linear Regulator +PIN -160 160 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 3 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 160 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADM7160-1.8.asy b/spice/copy/sym/PowerProducts/ADM7160-1.8.asy new file mode 100755 index 0000000..60053ba --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7160-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADM7160-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7160-x.x.sub +SYMATTR Value2 ADM7160-x.x T=800K +SYMATTR Description Ultralow Noise, 200mA Linear Regulator, Fixed 1.8V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADM7160-2.5.asy b/spice/copy/sym/PowerProducts/ADM7160-2.5.asy new file mode 100755 index 0000000..77ce115 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7160-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADM7160-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7160-x.x.sub +SYMATTR Value2 ADM7160-x.x T=1.5Meg +SYMATTR Description Ultralow Noise, 200mA Linear Regulator, Fixed 2.5V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADM7160-3.3.asy b/spice/copy/sym/PowerProducts/ADM7160-3.3.asy new file mode 100755 index 0000000..f720e11 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7160-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADM7160-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7160-x.x.sub +SYMATTR Value2 ADM7160-x.x T=2.3Meg +SYMATTR Description Ultralow Noise, 200mA Linear Regulator, Fixed 3.3V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADM7170-1.3.asy b/spice/copy/sym/PowerProducts/ADM7170-1.3.asy new file mode 100755 index 0000000..9a292f1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7170-1.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7170-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7170.sub +SYMATTR Value2 ADM7170 Vref=1.3 +SYMATTR Description 6.5V, 500mA, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 1.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7170-1.8.asy b/spice/copy/sym/PowerProducts/ADM7170-1.8.asy new file mode 100755 index 0000000..84f2edb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7170-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7170-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7170.sub +SYMATTR Value2 ADM7170 Vref=1.8 +SYMATTR Description 6.5V, 500mA, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 1.8V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7170-2.5.asy b/spice/copy/sym/PowerProducts/ADM7170-2.5.asy new file mode 100755 index 0000000..79d8716 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7170-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7170-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7170.sub +SYMATTR Value2 ADM7170 Vref=2.5 +SYMATTR Description 6.5V, 500mA, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 2.5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7170-3.0.asy b/spice/copy/sym/PowerProducts/ADM7170-3.0.asy new file mode 100755 index 0000000..b1c8b2b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7170-3.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7170-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7170.sub +SYMATTR Value2 ADM7170 Vref=3 +SYMATTR Description 6.5V, 500mA, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7170-3.3.asy b/spice/copy/sym/PowerProducts/ADM7170-3.3.asy new file mode 100755 index 0000000..5f920c7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7170-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7170-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7170.sub +SYMATTR Value2 ADM7170 Vref=3.3 +SYMATTR Description 6.5V, 500mA, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 3.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7170-4.2.asy b/spice/copy/sym/PowerProducts/ADM7170-4.2.asy new file mode 100755 index 0000000..410c4c6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7170-4.2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7170-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7170.sub +SYMATTR Value2 ADM7170 Vref=4.2 +SYMATTR Description 6.5V, 500mA, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 4.2V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7170-5.0.asy b/spice/copy/sym/PowerProducts/ADM7170-5.0.asy new file mode 100755 index 0000000..0b38fbe --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7170-5.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7170-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7170.sub +SYMATTR Value2 ADM7170 Vref=5 +SYMATTR Description 6.5V, 500mA, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7170.asy b/spice/copy/sym/PowerProducts/ADM7170.asy new file mode 100755 index 0000000..90c0cec --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7170.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7170 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7170.sub +SYMATTR Value2 ADM7170 Vref=1.2 +SYMATTR Description 6.5V, 500mA, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Adjustable Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7171-1.3.asy b/spice/copy/sym/PowerProducts/ADM7171-1.3.asy new file mode 100755 index 0000000..2452b6c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7171-1.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7171-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7171.sub +SYMATTR Value2 ADM7171 Vref=1.3 +SYMATTR Description 6.5V, 1A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 1.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7171-1.8.asy b/spice/copy/sym/PowerProducts/ADM7171-1.8.asy new file mode 100755 index 0000000..923e048 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7171-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7171-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7171.sub +SYMATTR Value2 ADM7171 Vref=1.8 +SYMATTR Description 6.5V, 1A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 1.8V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7171-2.5.asy b/spice/copy/sym/PowerProducts/ADM7171-2.5.asy new file mode 100755 index 0000000..7f99bc3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7171-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7171-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7171.sub +SYMATTR Value2 ADM7171 Vref=2.5 +SYMATTR Description 6.5V, 1A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 2.5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7171-3.0.asy b/spice/copy/sym/PowerProducts/ADM7171-3.0.asy new file mode 100755 index 0000000..2b3b27a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7171-3.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7171-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7171.sub +SYMATTR Value2 ADM7171 Vref=3 +SYMATTR Description 6.5V, 1A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7171-3.3.asy b/spice/copy/sym/PowerProducts/ADM7171-3.3.asy new file mode 100755 index 0000000..194088d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7171-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7171-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7171.sub +SYMATTR Value2 ADM7171 Vref=3.3 +SYMATTR Description 6.5V, 1A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 3.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7171-4.2.asy b/spice/copy/sym/PowerProducts/ADM7171-4.2.asy new file mode 100755 index 0000000..91a9493 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7171-4.2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7171-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7171.sub +SYMATTR Value2 ADM7171 Vref=4.2 +SYMATTR Description 6.5V, 1A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 4.2V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7171-5.0.asy b/spice/copy/sym/PowerProducts/ADM7171-5.0.asy new file mode 100755 index 0000000..9f63672 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7171-5.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7171-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7171.sub +SYMATTR Value2 ADM7171 Vref=5 +SYMATTR Description 6.5V, 1A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7171.asy b/spice/copy/sym/PowerProducts/ADM7171.asy new file mode 100755 index 0000000..2433f17 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7171.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7171 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7171.sub +SYMATTR Value2 ADM7171 Vref=1.2 +SYMATTR Description 6.5V, 1A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Adjustable Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7172-1.3.asy b/spice/copy/sym/PowerProducts/ADM7172-1.3.asy new file mode 100755 index 0000000..f1ebd13 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7172-1.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7172-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7172.sub +SYMATTR Value2 ADM7172 Vref=1.3 +SYMATTR Description 6.5V, 2A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 1.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7172-1.8.asy b/spice/copy/sym/PowerProducts/ADM7172-1.8.asy new file mode 100755 index 0000000..27da8d0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7172-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7172-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7172.sub +SYMATTR Value2 ADM7172 Vref=1.8 +SYMATTR Description 6.5V, 2A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 1.8V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7172-2.5.asy b/spice/copy/sym/PowerProducts/ADM7172-2.5.asy new file mode 100755 index 0000000..cb300f4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7172-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7172-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7172.sub +SYMATTR Value2 ADM7172 Vref=2.5 +SYMATTR Description 6.5V, 2A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 2.5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7172-3.0.asy b/spice/copy/sym/PowerProducts/ADM7172-3.0.asy new file mode 100755 index 0000000..adb6d99 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7172-3.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7172-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7172.sub +SYMATTR Value2 ADM7172 Vref=3 +SYMATTR Description 6.5V, 2A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7172-3.3.asy b/spice/copy/sym/PowerProducts/ADM7172-3.3.asy new file mode 100755 index 0000000..b9b10ea --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7172-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7172-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7172.sub +SYMATTR Value2 ADM7172 Vref=3.3 +SYMATTR Description 6.5V, 2A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 3.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7172-4.2.asy b/spice/copy/sym/PowerProducts/ADM7172-4.2.asy new file mode 100755 index 0000000..84989fc --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7172-4.2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7172-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7172.sub +SYMATTR Value2 ADM7172 Vref=4.2 +SYMATTR Description 6.5V, 2A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 4.2V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7172-5.0.asy b/spice/copy/sym/PowerProducts/ADM7172-5.0.asy new file mode 100755 index 0000000..0488d99 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7172-5.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7172-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7172.sub +SYMATTR Value2 ADM7172 Vref=5 +SYMATTR Description 6.5V, 2A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Fixed 5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADM7172.asy b/spice/copy/sym/PowerProducts/ADM7172.asy new file mode 100755 index 0000000..8ac3d0d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADM7172.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADM7172 +SYMATTR Prefix X +SYMATTR SpiceModel ADM7172.sub +SYMATTR Value2 ADM7172 Vref=1.2 +SYMATTR Description 6.5V, 2A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO, Adjustable Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADN8834.asy b/spice/copy/sym/PowerProducts/ADN8834.asy new file mode 100755 index 0000000..b9c4983 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADN8834.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -304 -352 288 480 +TEXT -1 0 Center 2 ADI +WINDOW 0 -1 -169 Center 2 +WINDOW 3 -1 152 Center 2 +SYMATTR Value ADN8834 +SYMATTR Prefix X +SYMATTR SpiceModel ADN8834.sub +SYMATTR Value2 ADN8834 +SYMATTR Description Ultracompact, 1.5A Thermoelectric Cooler (TEC) Controller\n\n Average Model +PIN -160 480 BOTTOM 8 +PINATTR PinName PGNDL +PINATTR SpiceOrder 1 +PIN 288 -272 RIGHT 8 +PINATTR PinName TMPGD +PINATTR SpiceOrder 2 +PIN -304 128 LEFT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 3 +PIN -304 -64 LEFT 8 +PINATTR PinName IN1P +PINATTR SpiceOrder 4 +PIN -304 224 LEFT 8 +PINATTR PinName IN2P +PINATTR SpiceOrder 5 +PIN 288 224 RIGHT 8 +PINATTR PinName LDR +PINATTR SpiceOrder 6 +PIN -304 32 LEFT 8 +PINATTR PinName IN1N +PINATTR SpiceOrder 7 +PIN -304 320 LEFT 8 +PINATTR PinName IN2N +PINATTR SpiceOrder 8 +PIN -304 -272 LEFT 8 +PINATTR PinName VLIM/SD +PINATTR SpiceOrder 9 +PIN -160 -352 TOP 8 +PINATTR PinName VREF +PINATTR SpiceOrder 10 +PIN 288 -64 RIGHT 8 +PINATTR PinName PVINL +PINATTR SpiceOrder 11 +PIN 288 32 RIGHT 8 +PINATTR PinName PVINS +PINATTR SpiceOrder 12 +PIN 160 -352 TOP 8 +PINATTR PinName ITEC +PINATTR SpiceOrder 13 +PIN -304 416 LEFT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 14 +PIN -304 -160 LEFT 8 +PINATTR PinName ILIM +PINATTR SpiceOrder 15 +PIN 288 320 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 16 +PIN 0 -352 TOP 8 +PINATTR PinName VTEC +PINATTR SpiceOrder 17 +PIN 288 128 RIGHT 8 +PINATTR PinName EN/SY +PINATTR SpiceOrder 18 +PIN 288 -160 RIGHT 8 +PINATTR PinName VDD +PINATTR SpiceOrder 19 +PIN 160 480 BOTTOM 8 +PINATTR PinName PGNDS +PINATTR SpiceOrder 20 +PIN 288 416 RIGHT 8 +PINATTR PinName SFB +PINATTR SpiceOrder 21 +PIN 0 480 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 22 diff --git a/spice/copy/sym/PowerProducts/ADP1071-1.asy b/spice/copy/sym/PowerProducts/ADP1071-1.asy new file mode 100755 index 0000000..b63b380 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1071-1.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value ADP1071-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1071-1.sub +SYMATTR Value2 ADP1071-1 +SYMATTR Description Isolated Synchronous Flyback Controller with Integrated iCoupler, Programmable LLM or Forced CCM Operation +PIN -176 -160 LEFT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 1 +PIN -64 288 BOTTOM 8 +PINATTR PinName Agnd1 +PINATTR SpiceOrder 2 +PIN -176 -80 LEFT 8 +PINATTR PinName Vreg1 +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 4 +PIN -176 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -176 -240 LEFT 8 +PINATTR PinName CS +PINATTR SpiceOrder 6 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 7 +PIN -176 240 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 +PIN 176 240 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 9 +PIN 176 160 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN 176 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 176 0 RIGHT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 12 +PIN 176 -80 RIGHT 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 13 +PIN 176 -160 RIGHT 8 +PINATTR PinName Vreg2 +PINATTR SpiceOrder 14 +PIN 64 288 BOTTOM 8 +PINATTR PinName Agnd2 +PINATTR SpiceOrder 15 +PIN 176 -240 RIGHT 8 +PINATTR PinName SR +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/ADP1071-2.asy b/spice/copy/sym/PowerProducts/ADP1071-2.asy new file mode 100755 index 0000000..45485c7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1071-2.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value ADP1071-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1071-2.sub +SYMATTR Value2 ADP1071-2 +SYMATTR Description Isolated Synchronous Flyback Controller with Integrated iCoupler, forced CCM operation +PIN -176 -160 LEFT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 1 +PIN -64 288 BOTTOM 8 +PINATTR PinName Agnd1 +PINATTR SpiceOrder 2 +PIN -176 -80 LEFT 8 +PINATTR PinName Vreg1 +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -176 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -176 -240 LEFT 8 +PINATTR PinName CS +PINATTR SpiceOrder 6 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 7 +PIN -176 240 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 +PIN 176 240 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 9 +PIN 176 160 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN 176 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 176 0 RIGHT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 12 +PIN 176 -80 RIGHT 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 13 +PIN 176 -160 RIGHT 8 +PINATTR PinName Vreg2 +PINATTR SpiceOrder 14 +PIN 64 288 BOTTOM 8 +PINATTR PinName Agnd2 +PINATTR SpiceOrder 15 +PIN 176 -240 RIGHT 8 +PINATTR PinName SR +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/ADP1074.asy b/spice/copy/sym/PowerProducts/ADP1074.asy new file mode 100755 index 0000000..ec45cbb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1074.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -416 176 496 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -169 Center 2 +WINDOW 3 0 152 Center 2 +SYMATTR Value ADP1074 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1074.sub +SYMATTR Value2 ADP1074 +SYMATTR Description Isolated, Synchronous Forward Controller with Active Clamp and iCoupler +PIN -176 -288 LEFT 8 +PINATTR PinName Ngate +PINATTR SpiceOrder 1 +PIN -176 432 LEFT 8 +PINATTR PinName Pgnd1 +PINATTR SpiceOrder 2 +PIN -176 -208 LEFT 8 +PINATTR PinName Pgate +PINATTR SpiceOrder 3 +PIN -64 496 BOTTOM 8 +PINATTR PinName Agnd1 +PINATTR SpiceOrder 4 +PIN -176 -128 LEFT 8 +PINATTR PinName Vreg1 +PINATTR SpiceOrder 5 +PIN -176 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -176 32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -176 -368 LEFT 8 +PINATTR PinName CS +PINATTR SpiceOrder 8 +PIN -176 352 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 9 +PIN -176 112 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 10 +PIN -176 192 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 11 +PIN -176 272 LEFT 8 +PINATTR PinName Dmax +PINATTR SpiceOrder 12 +PIN 176 352 RIGHT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 13 +PIN 176 -48 RIGHT 8 +PINATTR PinName _Pgood +PINATTR SpiceOrder 14 +PIN 176 432 RIGHT 8 +PINATTR PinName Pgnd2 +PINATTR SpiceOrder 15 +PIN 176 192 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 17 +PIN 176 112 RIGHT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 18 +PIN 176 -208 RIGHT 8 +PINATTR PinName VDD2 +PINATTR SpiceOrder 19 +PIN 176 -128 RIGHT 8 +PINATTR PinName Vreg2 +PINATTR SpiceOrder 20 +PIN 176 272 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 21 +PIN 64 496 BOTTOM 8 +PINATTR PinName Agnd2 +PINATTR SpiceOrder 22 +PIN 176 -288 RIGHT 8 +PINATTR PinName SR2 +PINATTR SpiceOrder 23 +PIN 176 -368 RIGHT 8 +PINATTR PinName SR1 +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/ADP121-1.2.asy b/spice/copy/sym/PowerProducts/ADP121-1.2.asy new file mode 100755 index 0000000..169393d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-1.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-1.2 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=1/1500 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP121-1.5.asy b/spice/copy/sym/PowerProducts/ADP121-1.5.asy new file mode 100755 index 0000000..c693a88 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-1.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-1.5 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=1/1875 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP121-1.65.asy b/spice/copy/sym/PowerProducts/ADP121-1.65.asy new file mode 100755 index 0000000..29bc3f4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-1.65.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-1.65 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=2/4125 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP121-1.8.asy b/spice/copy/sym/PowerProducts/ADP121-1.8.asy new file mode 100755 index 0000000..761a925 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-1.8 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=1/2250 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP121-1.875.asy b/spice/copy/sym/PowerProducts/ADP121-1.875.asy new file mode 100755 index 0000000..530305a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-1.875.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-1.875 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=4/9375 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP121-2.0.asy b/spice/copy/sym/PowerProducts/ADP121-2.0.asy new file mode 100755 index 0000000..54aa378 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-2.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-2.0 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=1/2500 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP121-2.5.asy b/spice/copy/sym/PowerProducts/ADP121-2.5.asy new file mode 100755 index 0000000..97e022e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-2.5 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=1/3125 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP121-2.8.asy b/spice/copy/sym/PowerProducts/ADP121-2.8.asy new file mode 100755 index 0000000..5294c8d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-2.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-2.8 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=1/3500 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP121-3.0.asy b/spice/copy/sym/PowerProducts/ADP121-3.0.asy new file mode 100755 index 0000000..0fb7ade --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-3.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-3.0 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=1/3750 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP121-3.3.asy b/spice/copy/sym/PowerProducts/ADP121-3.3.asy new file mode 100755 index 0000000..0132fc6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP121-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP121-3.3 +SYMATTR Description 150 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP121 K=1/4125 +SYMATTR SpiceModel ADP121.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-1.8.asy b/spice/copy/sym/PowerProducts/ADP122-1.8.asy new file mode 100755 index 0000000..57b6623 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-1.8 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/3600 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-2.0.asy b/spice/copy/sym/PowerProducts/ADP122-2.0.asy new file mode 100755 index 0000000..f456f25 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-2.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-2.0 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/4000 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-2.5.asy b/spice/copy/sym/PowerProducts/ADP122-2.5.asy new file mode 100755 index 0000000..f298d0d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-2.5 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/5000 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-2.6.asy b/spice/copy/sym/PowerProducts/ADP122-2.6.asy new file mode 100755 index 0000000..7888655 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-2.6.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-2.6 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/5200 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-2.7.asy b/spice/copy/sym/PowerProducts/ADP122-2.7.asy new file mode 100755 index 0000000..d94a74a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-2.7.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-2.7 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/5400 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-2.8.asy b/spice/copy/sym/PowerProducts/ADP122-2.8.asy new file mode 100755 index 0000000..763899e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-2.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-2.8 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/5600 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-2.85.asy b/spice/copy/sym/PowerProducts/ADP122-2.85.asy new file mode 100755 index 0000000..f1616d0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-2.85.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-2.85 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/5700 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-2.9.asy b/spice/copy/sym/PowerProducts/ADP122-2.9.asy new file mode 100755 index 0000000..e7201a9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-2.9.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-2.9 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/5800 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-3.0.asy b/spice/copy/sym/PowerProducts/ADP122-3.0.asy new file mode 100755 index 0000000..6c59ae2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-3.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-3.0 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/6000 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP122-3.3.asy b/spice/copy/sym/PowerProducts/ADP122-3.3.asy new file mode 100755 index 0000000..aa5576e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP122-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP122-3.3 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP122 K=1/6600 +SYMATTR SpiceModel ADP122.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP123.asy b/spice/copy/sym/PowerProducts/ADP123.asy new file mode 100755 index 0000000..ee84324 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP123.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP123 +SYMATTR Description 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP123 +SYMATTR SpiceModel ADP123.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 96 0 RIGHT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 2 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 4 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP124-1.8.asy b/spice/copy/sym/PowerProducts/ADP124-1.8.asy new file mode 100755 index 0000000..42303bb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP124-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP124-1.8 +SYMATTR Description 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP124 K=76923 +SYMATTR SpiceModel ADP124.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 96 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/ADP124-2.5.asy b/spice/copy/sym/PowerProducts/ADP124-2.5.asy new file mode 100755 index 0000000..7140c3d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP124-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP124-2.5 +SYMATTR Description 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP124 K=50000 +SYMATTR SpiceModel ADP124.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 96 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/ADP124-2.7.asy b/spice/copy/sym/PowerProducts/ADP124-2.7.asy new file mode 100755 index 0000000..e93d5df --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP124-2.7.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP124-2.7 +SYMATTR Description 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP124 K=45454.5 +SYMATTR SpiceModel ADP124.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 96 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/ADP124-2.8.asy b/spice/copy/sym/PowerProducts/ADP124-2.8.asy new file mode 100755 index 0000000..3f93854 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP124-2.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP124-2.8 +SYMATTR Description 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP124 K=43478 +SYMATTR SpiceModel ADP124.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 96 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/ADP124-2.85.asy b/spice/copy/sym/PowerProducts/ADP124-2.85.asy new file mode 100755 index 0000000..8c3cd1f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP124-2.85.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP124-2.85 +SYMATTR Description 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP124 K=42553.2 +SYMATTR SpiceModel ADP124.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 96 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/ADP124-2.9.asy b/spice/copy/sym/PowerProducts/ADP124-2.9.asy new file mode 100755 index 0000000..17245d9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP124-2.9.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP124-2.9 +SYMATTR Description 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP124 K=41666.67 +SYMATTR SpiceModel ADP124.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 96 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/ADP124-3.0.asy b/spice/copy/sym/PowerProducts/ADP124-3.0.asy new file mode 100755 index 0000000..da8e22a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP124-3.0.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP124-3.0 +SYMATTR Description 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP124 K=40000 +SYMATTR SpiceModel ADP124.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 96 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/ADP124-3.3.asy b/spice/copy/sym/PowerProducts/ADP124-3.3.asy new file mode 100755 index 0000000..c5e3208 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP124-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP124-3.3 +SYMATTR Description 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP124 K=35714.3 +SYMATTR SpiceModel ADP124.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 96 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/ADP125.asy b/spice/copy/sym/PowerProducts/ADP125.asy new file mode 100755 index 0000000..0bb0d70 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP125.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP125 +SYMATTR Description 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP125 +SYMATTR SpiceModel ADP125.sub +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 96 0 RIGHT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 3 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP150-1.8.asy b/spice/copy/sym/PowerProducts/ADP150-1.8.asy new file mode 100755 index 0000000..22309b9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP150-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP150-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP150-x.x.sub +SYMATTR Value2 ADP150-x.x T=.6Meg +SYMATTR Description 150mA CMOS Linear Regulator, Fixed 1.8V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP150-2.5.asy b/spice/copy/sym/PowerProducts/ADP150-2.5.asy new file mode 100755 index 0000000..4502388 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP150-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP150-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP150-x.x.sub +SYMATTR Value2 ADP150-x.x T=1.3Meg +SYMATTR Description 150mA CMOS Linear Regulator, Fixed 2.5V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP150-2.6.asy b/spice/copy/sym/PowerProducts/ADP150-2.6.asy new file mode 100755 index 0000000..cc617b4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP150-2.6.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP150-2.6 +SYMATTR Prefix X +SYMATTR SpiceModel ADP150-x.x.sub +SYMATTR Value2 ADP150-x.x T=1.4Meg +SYMATTR Description 150mA CMOS Linear Regulator, Fixed 2.6V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP150-2.75.asy b/spice/copy/sym/PowerProducts/ADP150-2.75.asy new file mode 100755 index 0000000..436d0d3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP150-2.75.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP150-2.75 +SYMATTR Prefix X +SYMATTR SpiceModel ADP150-x.x.sub +SYMATTR Value2 ADP150-x.x T=1.55Meg +SYMATTR Description 150mA CMOS Linear Regulator, Fixed 2.75V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP150-2.8.asy b/spice/copy/sym/PowerProducts/ADP150-2.8.asy new file mode 100755 index 0000000..a7a367f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP150-2.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP150-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP150-x.x.sub +SYMATTR Value2 ADP150-x.x T=1.6Meg +SYMATTR Description 150mA CMOS Linear Regulator, Fixed 2.8V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP150-2.85.asy b/spice/copy/sym/PowerProducts/ADP150-2.85.asy new file mode 100755 index 0000000..62b22f5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP150-2.85.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP150-2.85 +SYMATTR Prefix X +SYMATTR SpiceModel ADP150-x.x.sub +SYMATTR Value2 ADP150-x.x T=1.65Meg +SYMATTR Description 150mA CMOS Linear Regulator, Fixed 2.85V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP150-3.0.asy b/spice/copy/sym/PowerProducts/ADP150-3.0.asy new file mode 100755 index 0000000..b802c19 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP150-3.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP150-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP150-x.x.sub +SYMATTR Value2 ADP150-x.x T=1.8Meg +SYMATTR Description 150mA CMOS Linear Regulator, Fixed 3.0V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP150-3.3.asy b/spice/copy/sym/PowerProducts/ADP150-3.3.asy new file mode 100755 index 0000000..dafffe2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP150-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP150-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP150-x.x.sub +SYMATTR Value2 ADP150-x.x T=2.1Meg +SYMATTR Description 150mA CMOS Linear Regulator, Fixed 3.3V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-1.1.asy b/spice/copy/sym/PowerProducts/ADP151-1.1.asy new file mode 100755 index 0000000..39f39ce --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-1.1.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-1.1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=100K +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 1.1V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-1.2.asy b/spice/copy/sym/PowerProducts/ADP151-1.2.asy new file mode 100755 index 0000000..723e445 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-1.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=200K +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 1.2V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-1.5.asy b/spice/copy/sym/PowerProducts/ADP151-1.5.asy new file mode 100755 index 0000000..d31ce19 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-1.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=500K +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 1.5V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-1.8.asy b/spice/copy/sym/PowerProducts/ADP151-1.8.asy new file mode 100755 index 0000000..b1b0fb1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=800K +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 1.8V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-2.5.asy b/spice/copy/sym/PowerProducts/ADP151-2.5.asy new file mode 100755 index 0000000..23430d3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=1.5Meg +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 2.5V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-2.6.asy b/spice/copy/sym/PowerProducts/ADP151-2.6.asy new file mode 100755 index 0000000..3d9fe9e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-2.6.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-2.6 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=1.6Meg +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 2.6V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-2.75.asy b/spice/copy/sym/PowerProducts/ADP151-2.75.asy new file mode 100755 index 0000000..9e08343 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-2.75.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-2.75 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=1.75Meg +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 2.75V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-2.8.asy b/spice/copy/sym/PowerProducts/ADP151-2.8.asy new file mode 100755 index 0000000..72ff642 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-2.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=1.8Meg +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 2.9V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-2.85.asy b/spice/copy/sym/PowerProducts/ADP151-2.85.asy new file mode 100755 index 0000000..39f39ce --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-2.85.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-1.1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=100K +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 1.1V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-3.0.asy b/spice/copy/sym/PowerProducts/ADP151-3.0.asy new file mode 100755 index 0000000..2455560 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-3.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=2Meg +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 3.0V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP151-3.3.asy b/spice/copy/sym/PowerProducts/ADP151-3.3.asy new file mode 100755 index 0000000..9056fd7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP151-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP151-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP151-x.x.sub +SYMATTR Value2 ADP151-x.x T=2.3Meg +SYMATTR Description Ultralow Noise, 200mA, CMOS Linear Regulator, Fixed 3.3V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP160-1.2.asy b/spice/copy/sym/PowerProducts/ADP160-1.2.asy new file mode 100755 index 0000000..de7d938 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-1.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-1.2 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=833.3u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-1.5.asy b/spice/copy/sym/PowerProducts/ADP160-1.5.asy new file mode 100755 index 0000000..58abd0e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-1.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-1.5 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=666.7u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-1.8.asy b/spice/copy/sym/PowerProducts/ADP160-1.8.asy new file mode 100755 index 0000000..e14819f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-1.8 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=555.6u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-2.1.asy b/spice/copy/sym/PowerProducts/ADP160-2.1.asy new file mode 100755 index 0000000..b602213 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-2.1.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-2.1 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=476.2u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-2.3.asy b/spice/copy/sym/PowerProducts/ADP160-2.3.asy new file mode 100755 index 0000000..db343be --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-2.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-2.3 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=434.8u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-2.5.asy b/spice/copy/sym/PowerProducts/ADP160-2.5.asy new file mode 100755 index 0000000..5a5b802 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-2.5 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=400u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-2.7.asy b/spice/copy/sym/PowerProducts/ADP160-2.7.asy new file mode 100755 index 0000000..3addc85 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-2.7.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-2.7 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=370.4u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-2.75.asy b/spice/copy/sym/PowerProducts/ADP160-2.75.asy new file mode 100755 index 0000000..5edba8a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-2.75.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-2.75 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=363.6u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-2.8.asy b/spice/copy/sym/PowerProducts/ADP160-2.8.asy new file mode 100755 index 0000000..747f7f7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-2.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-2.8 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=357.1u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-2.85.asy b/spice/copy/sym/PowerProducts/ADP160-2.85.asy new file mode 100755 index 0000000..038d8a9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-2.85.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-2.85 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=350.9u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-3.0.asy b/spice/copy/sym/PowerProducts/ADP160-3.0.asy new file mode 100755 index 0000000..61e796e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-3.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-3.0 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=333.3u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-3.3.asy b/spice/copy/sym/PowerProducts/ADP160-3.3.asy new file mode 100755 index 0000000..1f6ecd3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-3.3 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=303u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP160-4.2.asy b/spice/copy/sym/PowerProducts/ADP160-4.2.asy new file mode 100755 index 0000000..aef56d4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP160-4.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP160-4.2 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=238.1u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP1606.asy b/spice/copy/sym/PowerProducts/ADP1606.asy new file mode 100755 index 0000000..9e344e1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1606.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 128 128 -128 -128 +TEXT 0 0 Center 2 ADI +TEXT 0 48 Center 2 ADP1606 +WINDOW 0 0 -48 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1606.sub +SYMATTR Value ADP1606 +SYMATTR Description Extreme Low Voltage 2 MHz Synchronous Boost Converter +SYMATTR Value2 ADP1606 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 2 +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -128 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP1607-001.asy b/spice/copy/sym/PowerProducts/ADP1607-001.asy new file mode 100755 index 0000000..b777abb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1607-001.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 128 128 -128 -128 +TEXT 0 0 Center 2 ADI +TEXT 0 48 Center 2 ADP1607 +WINDOW 0 0 -48 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1607-001.sub +SYMATTR Value ADP1607-001 +SYMATTR Description Extreme Low Voltage 2 MHz Synchronous Boost Converter Forced PWM +SYMATTR Value2 ADP1607-001 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -128 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP1607.asy b/spice/copy/sym/PowerProducts/ADP1607.asy new file mode 100755 index 0000000..18ac066 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1607.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 128 128 -128 -128 +TEXT 0 0 Center 2 ADI +TEXT 0 48 Center 2 ADP1607 +WINDOW 0 0 -48 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1607.sub +SYMATTR Value ADP1607 +SYMATTR Description Extreme Low Voltage 2 MHz Synchronous Boost Converter PFM enabled at low load +SYMATTR Value2 ADP1607 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN -128 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP161.asy b/spice/copy/sym/PowerProducts/ADP161.asy new file mode 100755 index 0000000..e41072b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP161.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP161 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xad +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP1612.asy b/spice/copy/sym/PowerProducts/ADP1612.asy new file mode 100755 index 0000000..b6fc20d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1612.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 176 -144 -176 +TEXT 0 8 Center 2 ADI +TEXT 0 89 Center 2 ADP1612 +WINDOW 0 0 -72 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1612.sub +SYMATTR Value ADP1612 +SYMATTR Description 650kHz /1.3MHz, 1.4A, Step-Up PWM DC-to-DC Switching Regulator\n\nNote: SS pin is not modeled. +SYMATTR Value2 ADP1612 +PIN -144 112 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -176 TOP 8 +PINATTR PinName VIN +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/ADP1613.asy b/spice/copy/sym/PowerProducts/ADP1613.asy new file mode 100755 index 0000000..6f84ed7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1613.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 176 -144 -176 +TEXT 0 8 Center 2 ADI +TEXT 0 89 Center 2 ADP1613 +WINDOW 0 0 -72 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1613.sub +SYMATTR Value ADP1613 +SYMATTR Description 650kHz /1.3MHz, 2A, Step-Up PWM DC-to-DC Switching Regulator\n\nNote: SS pin is not modeled. +SYMATTR Value2 ADP1613 +PIN -144 112 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -176 TOP 8 +PINATTR PinName VIN +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/ADP1614-1.3.asy b/spice/copy/sym/PowerProducts/ADP1614-1.3.asy new file mode 100755 index 0000000..4619bb0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1614-1.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 176 -144 -176 +TEXT 0 8 Center 2 ADI +TEXT 0 89 Center 2 ADP1614-1.3 +WINDOW 0 0 -72 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1614-1.3.sub +SYMATTR Value ADP1614-1.3 +SYMATTR Description 1.3MHz, Adjustable up to 4A, Step-Up PWM DC-to-DC Switching Regulator. +SYMATTR Value2 ADP1614-1.3 +PIN 144 112 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 0 176 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 4 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -144 0 LEFT 8 +PINATTR PinName Clres +PINATTR SpiceOrder 9 +PIN -144 112 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1614-650.asy b/spice/copy/sym/PowerProducts/ADP1614-650.asy new file mode 100755 index 0000000..a496e19 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1614-650.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 176 -144 -176 +TEXT 0 8 Center 2 ADI +TEXT 0 75 Center 2 ADP1614-650 +WINDOW 0 0 -72 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1614-650.sub +SYMATTR Value ADP1614-650 +SYMATTR Description 650kHz, Adjustable up to 4A, Step-Up PWM DC-to-DC Switching Regulator\n\nNote: SS pin is not modeled. +SYMATTR Value2 ADP1614-650 +PIN 144 112 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 0 176 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 4 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -144 0 LEFT 8 +PINATTR PinName Clres +PINATTR SpiceOrder 9 +PIN -144 112 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1614.asy b/spice/copy/sym/PowerProducts/ADP1614.asy new file mode 100755 index 0000000..f03c547 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1614.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 176 -144 -176 +TEXT 0 8 Center 2 ADI +TEXT 0 89 Center 2 ADP1614 +WINDOW 0 0 -72 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1614.sub +SYMATTR Value ADP1614_verify +SYMATTR Description 650kHz /1.3MHz, 3A, Step-Up PWM DC-to-DC Switching Regulator +SYMATTR Value2 ADP1614 +PIN 144 112 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 0 176 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 4 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -144 0 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 9 +PIN -144 112 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP162-1.2.asy b/spice/copy/sym/PowerProducts/ADP162-1.2.asy new file mode 100755 index 0000000..b75f034 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP162-1.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP162-1.2 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=833.3u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP162-1.8.asy b/spice/copy/sym/PowerProducts/ADP162-1.8.asy new file mode 100755 index 0000000..c9061c8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP162-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP162-1.8 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=555.6u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP162-2.1.asy b/spice/copy/sym/PowerProducts/ADP162-2.1.asy new file mode 100755 index 0000000..cf3454c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP162-2.1.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP162-2.1 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=476.2u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP162-2.3.asy b/spice/copy/sym/PowerProducts/ADP162-2.3.asy new file mode 100755 index 0000000..810614b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP162-2.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP162-2.3 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=434.8u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP162-2.8.asy b/spice/copy/sym/PowerProducts/ADP162-2.8.asy new file mode 100755 index 0000000..a05c208 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP162-2.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP162-2.8 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=357.1u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP162-3.0.asy b/spice/copy/sym/PowerProducts/ADP162-3.0.asy new file mode 100755 index 0000000..87d1e69 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP162-3.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP162-3.0 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=333.3u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP162-3.1.asy b/spice/copy/sym/PowerProducts/ADP162-3.1.asy new file mode 100755 index 0000000..4ac3e7d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP162-3.1.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP162-3.1 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=322.6u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP162-3.3.asy b/spice/copy/sym/PowerProducts/ADP162-3.3.asy new file mode 100755 index 0000000..a5c9010 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP162-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP162-3.3 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=303u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP162-4.2.asy b/spice/copy/sym/PowerProducts/ADP162-4.2.asy new file mode 100755 index 0000000..832513f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP162-4.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP162-4.2 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=238.1u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP1621.asy b/spice/copy/sym/PowerProducts/ADP1621.asy new file mode 100755 index 0000000..d6806c1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1621.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 176 -144 -176 +TEXT 0 8 Center 2 ADI +TEXT 0 89 Center 2 ADP1621 +WINDOW 0 0 -72 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP1621.sub +SYMATTR Value ADP1621 +SYMATTR Description Constant-Frequency, Current-Mode Step-Up DC-to-DC Controller +SYMATTR Value2 ADP1621 +PIN -144 128 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 1 +PIN -144 -112 LEFT 8 +PINATTR PinName SDSN +PINATTR SpiceOrder 2 +PIN -64 -176 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 +PIN 80 -176 TOP 8 +PINATTR PinName Pin +PINATTR SpiceOrder 4 +PIN 144 -112 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 5 +PIN 144 -32 RIGHT 8 +PINATTR PinName CS +PINATTR SpiceOrder 6 +PIN -144 48 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN 144 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP163.asy b/spice/copy/sym/PowerProducts/ADP163.asy new file mode 100755 index 0000000..e6f1aa1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP163.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP163 +SYMATTR Description Ultralow Quiescent Current, 150mA CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xa +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP165-1.2.asy b/spice/copy/sym/PowerProducts/ADP165-1.2.asy new file mode 100755 index 0000000..0c995cc --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP165-1.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP165-1.2 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=833.3u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP165-1.8.asy b/spice/copy/sym/PowerProducts/ADP165-1.8.asy new file mode 100755 index 0000000..ab48828 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP165-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP165-1.8 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=555.6u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP165-2.2.asy b/spice/copy/sym/PowerProducts/ADP165-2.2.asy new file mode 100755 index 0000000..39c027e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP165-2.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP165-2.2 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=454.5u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP165-2.3.asy b/spice/copy/sym/PowerProducts/ADP165-2.3.asy new file mode 100755 index 0000000..212a046 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP165-2.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP165-2.3 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=434.8u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP165-2.85.asy b/spice/copy/sym/PowerProducts/ADP165-2.85.asy new file mode 100755 index 0000000..55f8e02 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP165-2.85.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP165-2.85 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=350.9u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP165-3.0.asy b/spice/copy/sym/PowerProducts/ADP165-3.0.asy new file mode 100755 index 0000000..7beeecd --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP165-3.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP165-3.0 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=333.3u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP165-3.3.asy b/spice/copy/sym/PowerProducts/ADP165-3.3.asy new file mode 100755 index 0000000..718d74d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP165-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP165-3.3 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xfd K=303.0u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP165-ADJ.asy b/spice/copy/sym/PowerProducts/ADP165-ADJ.asy new file mode 100755 index 0000000..50a9d53 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP165-ADJ.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP165-ADJ +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xad +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP166-1.2.asy b/spice/copy/sym/PowerProducts/ADP166-1.2.asy new file mode 100755 index 0000000..ef82053 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP166-1.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP166-1.2 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=833.3u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP166-1.8.asy b/spice/copy/sym/PowerProducts/ADP166-1.8.asy new file mode 100755 index 0000000..be0405a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP166-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP166-1.8 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=555.6u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP166-2.2.asy b/spice/copy/sym/PowerProducts/ADP166-2.2.asy new file mode 100755 index 0000000..c5fb2c0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP166-2.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP166-2.2 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=454.5u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP166-2.3.asy b/spice/copy/sym/PowerProducts/ADP166-2.3.asy new file mode 100755 index 0000000..c163d3b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP166-2.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP166-2.3 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=434.8u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP166-2.85.asy b/spice/copy/sym/PowerProducts/ADP166-2.85.asy new file mode 100755 index 0000000..4e7f887 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP166-2.85.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP166-2.85 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=350.9u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP166-3.0.asy b/spice/copy/sym/PowerProducts/ADP166-3.0.asy new file mode 100755 index 0000000..6279b8e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP166-3.0.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP166-3.0 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=333.3u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP166-3.3.asy b/spice/copy/sym/PowerProducts/ADP166-3.3.asy new file mode 100755 index 0000000..3e2e0ff --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP166-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP166-3.3 +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xf K=303.0u +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP166-ADJ.asy b/spice/copy/sym/PowerProducts/ADP166-ADJ.asy new file mode 100755 index 0000000..f978d0f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP166-ADJ.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 48 -96 -144 +TEXT 0 -72 Center 2 ADI +WINDOW 0 0 -144 Bottom 2 +WINDOW 3 0 -32 Center 2 +SYMATTR Value ADP166-ADJ +SYMATTR Description Very Low Quiescent Current, 150mA, LDO Regulator +SYMATTR Prefix X +SYMATTR SpiceModel ADP16x.lib +SYMATTR Value2 ADP16xa +PIN -96 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 48 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 0 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN 96 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP1708.asy b/spice/copy/sym/PowerProducts/ADP1708.asy new file mode 100755 index 0000000..4d45347 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1708.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 95 96 -96 -112 +TEXT 0 -23 Center 2 ADI +WINDOW 0 -66 -112 Bottom 2 +WINDOW 3 -2 16 Center 2 +SYMATTR Value ADP1708 +SYMATTR Description 1A, Low Dropout, CMOS Linear Regulator +SYMATTR Prefix X +SYMATTR Value2 ADP1708 +SYMATTR SpiceModel ADP1708.sub +PIN 96 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 -112 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 96 48 RIGHT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 3 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -96 48 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 5 +PIN -96 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP1761-0.9.asy b/spice/copy/sym/PowerProducts/ADP1761-0.9.asy new file mode 100755 index 0000000..9810705 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1761-0.9.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1761-0.9 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1761 Radj=6K +SYMATTR Description 1A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.9V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1761-0.95.asy b/spice/copy/sym/PowerProducts/ADP1761-0.95.asy new file mode 100755 index 0000000..e9388e8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1761-0.95.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1761-0.95 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1761 Radj=6333.33 +SYMATTR Description 1A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.95V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1761-1.0.asy b/spice/copy/sym/PowerProducts/ADP1761-1.0.asy new file mode 100755 index 0000000..47c3c0b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1761-1.0.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1761-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1761 Radj=6666.67 +SYMATTR Description 1A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.0V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1761-1.1.asy b/spice/copy/sym/PowerProducts/ADP1761-1.1.asy new file mode 100755 index 0000000..2a8051d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1761-1.1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1761-1.1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1761 Radj=7333.33 +SYMATTR Description 1A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.1V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1761-1.2.asy b/spice/copy/sym/PowerProducts/ADP1761-1.2.asy new file mode 100755 index 0000000..039245a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1761-1.2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1761-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1761 Radj=8K +SYMATTR Description 1A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.2V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1761-1.25.asy b/spice/copy/sym/PowerProducts/ADP1761-1.25.asy new file mode 100755 index 0000000..ee3d510 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1761-1.25.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1761-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1761 Radj=8333.33 +SYMATTR Description 1A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.25V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1761-1.3.asy b/spice/copy/sym/PowerProducts/ADP1761-1.3.asy new file mode 100755 index 0000000..f0933f3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1761-1.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1761-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1761 Radj=8666.67 +SYMATTR Description 1A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.3V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1761-1.5.asy b/spice/copy/sym/PowerProducts/ADP1761-1.5.asy new file mode 100755 index 0000000..8ebf27a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1761-1.5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1761-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1761 Radj=10K +SYMATTR Description 1A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.5V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1761.asy b/spice/copy/sym/PowerProducts/ADP1761.asy new file mode 100755 index 0000000..93eb49b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1761.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1761 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1761 Radj=1T +SYMATTR Description 1A, Low Vin, Low Noise, CMOS Linear Regulator +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1762-0.9.asy b/spice/copy/sym/PowerProducts/ADP1762-0.9.asy new file mode 100755 index 0000000..1c6bfa1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1762-0.9.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1762-0.9 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1762 Radj=6K +SYMATTR Description 2A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.9V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1762-0.95.asy b/spice/copy/sym/PowerProducts/ADP1762-0.95.asy new file mode 100755 index 0000000..c1e6317 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1762-0.95.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1762-0.95 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1762 Radj=6333.33 +SYMATTR Description 2A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.95V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1762-1.0.asy b/spice/copy/sym/PowerProducts/ADP1762-1.0.asy new file mode 100755 index 0000000..a4f2e6f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1762-1.0.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1762-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1762 Radj=6666.67 +SYMATTR Description 2A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.0V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1762-1.1.asy b/spice/copy/sym/PowerProducts/ADP1762-1.1.asy new file mode 100755 index 0000000..47fc94f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1762-1.1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1762-1.1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1762 Radj=7333.33 +SYMATTR Description 2A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.1V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1762-1.2.asy b/spice/copy/sym/PowerProducts/ADP1762-1.2.asy new file mode 100755 index 0000000..af1dade --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1762-1.2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1762-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1762 Radj=8K +SYMATTR Description 2A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.2V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1762-1.25.asy b/spice/copy/sym/PowerProducts/ADP1762-1.25.asy new file mode 100755 index 0000000..8616c1b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1762-1.25.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1762-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1762 Radj=8333.33 +SYMATTR Description 2A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.25V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1762-1.3.asy b/spice/copy/sym/PowerProducts/ADP1762-1.3.asy new file mode 100755 index 0000000..74071eb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1762-1.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1762-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1762 Radj=8666.67 +SYMATTR Description 2A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.3V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1762-1.5.asy b/spice/copy/sym/PowerProducts/ADP1762-1.5.asy new file mode 100755 index 0000000..4a06a4f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1762-1.5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1762-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1762 Radj=10K +SYMATTR Description 2A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.5V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1762.asy b/spice/copy/sym/PowerProducts/ADP1762.asy new file mode 100755 index 0000000..ecfdc18 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1762.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1762 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1762 Radj=1T +SYMATTR Description 2A, Low Vin, Low Noise, CMOS Linear Regulator +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1763-0.9.asy b/spice/copy/sym/PowerProducts/ADP1763-0.9.asy new file mode 100755 index 0000000..b4832cc --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1763-0.9.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1763-0.9 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1763 Radj=6K +SYMATTR Description 3A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.9V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1763-0.95.asy b/spice/copy/sym/PowerProducts/ADP1763-0.95.asy new file mode 100755 index 0000000..dc7a16d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1763-0.95.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1763-0.95 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1763 Radj=6333.33 +SYMATTR Description 3A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.95V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1763-1.0.asy b/spice/copy/sym/PowerProducts/ADP1763-1.0.asy new file mode 100755 index 0000000..7b4dc3c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1763-1.0.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1763-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1763 Radj=6666.67 +SYMATTR Description 3A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.0V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1763-1.1.asy b/spice/copy/sym/PowerProducts/ADP1763-1.1.asy new file mode 100755 index 0000000..0db9cf7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1763-1.1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1763-1.1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1763 Radj=7333.33 +SYMATTR Description 3A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.1V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1763-1.2.asy b/spice/copy/sym/PowerProducts/ADP1763-1.2.asy new file mode 100755 index 0000000..019f292 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1763-1.2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1763-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1763 Radj=8K +SYMATTR Description 3A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.2V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1763-1.25.asy b/spice/copy/sym/PowerProducts/ADP1763-1.25.asy new file mode 100755 index 0000000..4f7aed0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1763-1.25.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1763-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1763 Radj=8333.33 +SYMATTR Description 3A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.25V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1763-1.3.asy b/spice/copy/sym/PowerProducts/ADP1763-1.3.asy new file mode 100755 index 0000000..866f03a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1763-1.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1763-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1763 Radj=8666.67 +SYMATTR Description 3A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.3V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1763-1.5.asy b/spice/copy/sym/PowerProducts/ADP1763-1.5.asy new file mode 100755 index 0000000..f370dd0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1763-1.5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1763-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1763 Radj=10K +SYMATTR Description 3A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.5V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1763.asy b/spice/copy/sym/PowerProducts/ADP1763.asy new file mode 100755 index 0000000..12b609e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1763.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1763 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1763 Radj=1T +SYMATTR Description 3A, Low Vin, Low Noise, CMOS Linear Regulator +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764-0.55.asy b/spice/copy/sym/PowerProducts/ADP1764-0.55.asy new file mode 100755 index 0000000..ddaf860 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764-0.55.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764-0.55 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=3678.93 +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.55V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764-0.9.asy b/spice/copy/sym/PowerProducts/ADP1764-0.9.asy new file mode 100755 index 0000000..9d27f19 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764-0.9.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764-0.9 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=6020.07 +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.9V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764-0.95.asy b/spice/copy/sym/PowerProducts/ADP1764-0.95.asy new file mode 100755 index 0000000..f36af10 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764-0.95.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764-0.95 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=6354.52 +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.95V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764-1.0.asy b/spice/copy/sym/PowerProducts/ADP1764-1.0.asy new file mode 100755 index 0000000..7f9e7f2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764-1.0.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=6688.96 +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.0V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764-1.1.asy b/spice/copy/sym/PowerProducts/ADP1764-1.1.asy new file mode 100755 index 0000000..bde7e67 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764-1.1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764-1.1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=7357.86 +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.1V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764-1.2.asy b/spice/copy/sym/PowerProducts/ADP1764-1.2.asy new file mode 100755 index 0000000..015b969 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764-1.2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=8026.76 +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.2V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764-1.25.asy b/spice/copy/sym/PowerProducts/ADP1764-1.25.asy new file mode 100755 index 0000000..921eab0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764-1.25.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=8361.2 +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.25V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764-1.3.asy b/spice/copy/sym/PowerProducts/ADP1764-1.3.asy new file mode 100755 index 0000000..14b4308 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764-1.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=8695.65 +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.3V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764-1.5.asy b/spice/copy/sym/PowerProducts/ADP1764-1.5.asy new file mode 100755 index 0000000..b60fdcb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764-1.5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=10033.44 +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.5V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1764.asy b/spice/copy/sym/PowerProducts/ADP1764.asy new file mode 100755 index 0000000..ed9452c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1764.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1764 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1764 Radj=1T +SYMATTR Description 4A, Low Vin, Low Noise, CMOS Linear Regulator +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765-0.55.asy b/spice/copy/sym/PowerProducts/ADP1765-0.55.asy new file mode 100755 index 0000000..7d00b8e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765-0.55.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765-0.55 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=3678.93 +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.55V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765-0.9.asy b/spice/copy/sym/PowerProducts/ADP1765-0.9.asy new file mode 100755 index 0000000..77d95fe --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765-0.9.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765-0.9 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=6020.07 +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.9V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765-0.95.asy b/spice/copy/sym/PowerProducts/ADP1765-0.95.asy new file mode 100755 index 0000000..c602ebc --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765-0.95.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765-0.95 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=6354.52 +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 0.95V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765-1.0.asy b/spice/copy/sym/PowerProducts/ADP1765-1.0.asy new file mode 100755 index 0000000..d642225 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765-1.0.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=6688.96 +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.0V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765-1.1.asy b/spice/copy/sym/PowerProducts/ADP1765-1.1.asy new file mode 100755 index 0000000..5cb58be --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765-1.1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765-1.1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=7357.86 +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.1V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765-1.2.asy b/spice/copy/sym/PowerProducts/ADP1765-1.2.asy new file mode 100755 index 0000000..fd5756e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765-1.2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=8026.76 +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.2V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765-1.25.asy b/spice/copy/sym/PowerProducts/ADP1765-1.25.asy new file mode 100755 index 0000000..1975c5b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765-1.25.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=8361.2 +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.25V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765-1.3.asy b/spice/copy/sym/PowerProducts/ADP1765-1.3.asy new file mode 100755 index 0000000..4189d83 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765-1.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=8695.65 +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.3V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765-1.5.asy b/spice/copy/sym/PowerProducts/ADP1765-1.5.asy new file mode 100755 index 0000000..5d0eb2c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765-1.5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=10033.44 +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator, Fixed 1.5V Output +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1765.asy b/spice/copy/sym/PowerProducts/ADP1765.asy new file mode 100755 index 0000000..700438d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1765.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value ADP1765 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP1765 Radj=1T +SYMATTR Description 5A, Low Vin, Low Noise, CMOS Linear Regulator +PIN -128 48 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 6 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName RefCap +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP1850.asy b/spice/copy/sym/PowerProducts/ADP1850.asy new file mode 100755 index 0000000..2420e23 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1850.asy @@ -0,0 +1,106 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 160 832 -160 -816 +TEXT 0 8 Center 2 ADI +TEXT 0 344 Center 2 ADP1850 +WINDOW 0 0 -216 Center 2 +SYMATTR Prefix X +SYMATTR Value ADP1850 +SYMATTR Description Wide Range Input, Dual/Two-Phase, DC-to-DC Channel Synchronous Buck Controller +SYMATTR ModelFile ADP1850.sub +PIN -160 -496 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 2 +PIN -160 176 LEFT 8 +PINATTR PinName VccO +PINATTR SpiceOrder 3 +PIN 160 -496 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 4 +PIN -64 832 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN 160 -160 RIGHT 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 6 +PIN 160 -608 RIGHT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 7 +PIN 64 -816 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -160 -720 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 9 +PIN -160 -384 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 10 +PIN -160 -272 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -64 -816 TOP 8 +PINATTR PinName Ramp1 +PINATTR SpiceOrder 12 +PIN -160 -608 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 13 +PIN -160 -48 LEFT 8 +PINATTR PinName TRK1 +PINATTR SpiceOrder 14 +PIN 160 -272 RIGHT 8 +PINATTR PinName DL1 +PINATTR SpiceOrder 15 +PIN 160 -720 RIGHT 8 +PINATTR PinName DH1 +PINATTR SpiceOrder 16 +PIN -160 64 LEFT 8 +PINATTR PinName VDL +PINATTR SpiceOrder 17 +PIN -160 -160 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 18 +PIN 160 -384 RIGHT 8 +PINATTR PinName ILIM1 +PINATTR SpiceOrder 19 +PIN 160 288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 23 +PIN -160 736 LEFT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 26 +PIN 160 736 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 27 +PIN -160 512 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 28 +PIN 160 176 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 29 +PIN -160 400 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 30 +PIN 160 624 RIGHT 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 31 +PIN -160 624 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 34 +PIN 64 832 BOTTOM 8 +PINATTR PinName Ramp2 +PINATTR SpiceOrder 35 +PIN 160 512 RIGHT 8 +PINATTR PinName DL2 +PINATTR SpiceOrder 36 +PIN 160 64 RIGHT 8 +PINATTR PinName DH2 +PINATTR SpiceOrder 37 +PIN 160 400 RIGHT 8 +PINATTR PinName ILIM2 +PINATTR SpiceOrder 40 +PIN -160 288 LEFT 8 +PINATTR PinName TRK2 +PINATTR SpiceOrder 42 diff --git a/spice/copy/sym/PowerProducts/ADP1851.asy b/spice/copy/sym/PowerProducts/ADP1851.asy new file mode 100755 index 0000000..18d2a3f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1851.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 159 384 -160 -384 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 1 160 Center 2 +SYMATTR Value ADP1851 +SYMATTR Prefix X +SYMATTR Description Wide Range Input, Synchronous, Step-Down DC-to-DC Controller +SYMATTR SpiceModel ADP1851.sub +SYMATTR Value2 ADP1851 +PIN 160 336 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN -160 336 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -160 -224 LEFT 8 +PINATTR PinName VccO +PINATTR SpiceOrder 3 +PIN 160 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 384 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN 160 224 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 160 -224 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN 48 -384 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -160 -336 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 9 +PIN -160 224 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 10 +PIN -160 0 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -64 -384 TOP 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 12 +PIN -160 112 LEFT 8 +PINATTR PinName SS/TRK +PINATTR SpiceOrder 13 +PIN 160 112 RIGHT 8 +PINATTR PinName DL +PINATTR SpiceOrder 14 +PIN 160 -336 RIGHT 8 +PINATTR PinName DH +PINATTR SpiceOrder 15 +PIN -160 -112 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 16 +PIN 160 0 RIGHT 8 +PINATTR PinName ILIM +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/ADP1853.asy b/spice/copy/sym/PowerProducts/ADP1853.asy new file mode 100755 index 0000000..b0ea1b5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP1853.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 160 496 -160 -496 +TEXT 0 0 Center 2 ADI +TEXT -1 168 Center 2 ADP1853 +WINDOW 0 0 -169 Center 2 +SYMATTR Prefix X +SYMATTR Value ADP1853 +SYMATTR Description Synchronous, Step-Down DC-to-DC Controller with Voltage Tracking and Synchronization +SYMATTR ModelFile ADP1853.sub +PIN 160 336 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 160 448 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -160 -224 LEFT 8 +PINATTR PinName Vcco +PINATTR SpiceOrder 3 +PIN 160 -224 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -160 448 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN 160 224 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 160 -336 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN 48 -496 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -160 -448 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 9 +PIN -160 336 LEFT 8 +PINATTR PinName PGOOD +PINATTR SpiceOrder 10 +PIN -160 0 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -64 -496 TOP 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 12 +PIN -160 112 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 13 +PIN -160 -336 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 14 +PIN 160 112 RIGHT 8 +PINATTR PinName DL +PINATTR SpiceOrder 15 +PIN 160 -448 RIGHT 8 +PINATTR PinName DH +PINATTR SpiceOrder 16 +PIN 160 -112 RIGHT 8 +PINATTR PinName CS +PINATTR SpiceOrder 17 +PIN -160 -112 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 18 +PIN 160 0 RIGHT 8 +PINATTR PinName ILIM +PINATTR SpiceOrder 19 +PIN -160 224 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/ADP2108-1.0.asy b/spice/copy/sym/PowerProducts/ADP2108-1.0.asy new file mode 100755 index 0000000..d210e21 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-1.0.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=80K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 1.0V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-1.1.asy b/spice/copy/sym/PowerProducts/ADP2108-1.1.asy new file mode 100755 index 0000000..75b864a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-1.1.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-1.1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=96K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 1.1V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-1.2.asy b/spice/copy/sym/PowerProducts/ADP2108-1.2.asy new file mode 100755 index 0000000..fd0a2c6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-1.2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=112K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 1.2V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-1.3.asy b/spice/copy/sym/PowerProducts/ADP2108-1.3.asy new file mode 100755 index 0000000..1b602ef --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-1.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=128K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 1.3V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-1.5.asy b/spice/copy/sym/PowerProducts/ADP2108-1.5.asy new file mode 100755 index 0000000..9a98c00 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=160K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 1.5V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-1.8.asy b/spice/copy/sym/PowerProducts/ADP2108-1.8.asy new file mode 100755 index 0000000..ad641df --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=208K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 1.8V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-1.82.asy b/spice/copy/sym/PowerProducts/ADP2108-1.82.asy new file mode 100755 index 0000000..5ca46de --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-1.82.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-1.82 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=211.2K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 1.82V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-2.3.asy b/spice/copy/sym/PowerProducts/ADP2108-2.3.asy new file mode 100755 index 0000000..8cb09fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-2.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-2.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=288K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 2.3V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-2.5.asy b/spice/copy/sym/PowerProducts/ADP2108-2.5.asy new file mode 100755 index 0000000..3555ddd --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=320K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 2.5V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-3.0.asy b/spice/copy/sym/PowerProducts/ADP2108-3.0.asy new file mode 100755 index 0000000..90eb4df --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-3.0.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=400K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 3.0V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2108-3.3.asy b/spice/copy/sym/PowerProducts/ADP2108-3.3.asy new file mode 100755 index 0000000..4145628 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2108-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2108-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2108-x.x.sub +SYMATTR Value2 ADP2108-x.x Rtop=448K +SYMATTR Description Compact, 3MHz, 600mA, Synchronous Step-Down Regulator, Fixed 3.3V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-1.0.asy b/spice/copy/sym/PowerProducts/ADP2109-1.0.asy new file mode 100755 index 0000000..c71fb2b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-1.0.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=80K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.0V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-1.1.asy b/spice/copy/sym/PowerProducts/ADP2109-1.1.asy new file mode 100755 index 0000000..811f5fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-1.1.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-1.1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=96K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.1V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-1.2.asy b/spice/copy/sym/PowerProducts/ADP2109-1.2.asy new file mode 100755 index 0000000..b80d580 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-1.2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=112K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.2V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-1.3.asy b/spice/copy/sym/PowerProducts/ADP2109-1.3.asy new file mode 100755 index 0000000..07c9443 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-1.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-1.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=128K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.3V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-1.5.asy b/spice/copy/sym/PowerProducts/ADP2109-1.5.asy new file mode 100755 index 0000000..82367e7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=160K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.5V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-1.8.asy b/spice/copy/sym/PowerProducts/ADP2109-1.8.asy new file mode 100755 index 0000000..f709355 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=208K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.8V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-1.82.asy b/spice/copy/sym/PowerProducts/ADP2109-1.82.asy new file mode 100755 index 0000000..d244099 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-1.82.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-1.82 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=211.2K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.82V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-2.3.asy b/spice/copy/sym/PowerProducts/ADP2109-2.3.asy new file mode 100755 index 0000000..baf6c50 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-2.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-2.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=288K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 2.3V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-2.5.asy b/spice/copy/sym/PowerProducts/ADP2109-2.5.asy new file mode 100755 index 0000000..e18e7ad --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=320K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 2.5V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-3.0.asy b/spice/copy/sym/PowerProducts/ADP2109-3.0.asy new file mode 100755 index 0000000..6abb924 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-3.0.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=400K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 3.0V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2109-3.3.asy b/spice/copy/sym/PowerProducts/ADP2109-3.3.asy new file mode 100755 index 0000000..411dc3d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2109-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2109-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2109-x.x.sub +SYMATTR Value2 ADP2109-x.x Rtop=448K +SYMATTR Description Compact 3MHz, 600mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 3.3V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/ADP2118-1.0.asy b/spice/copy/sym/PowerProducts/ADP2118-1.0.asy new file mode 100755 index 0000000..1d5607e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2118-1.0.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 144 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2118-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2118-x.x.sub +SYMATTR Description 3A 1.2MHz/600kHz High Efficiency Synchronous Step-Down DC-DC Regulator, Fixed 1.0V Output +SYMATTR Value2 ADP2118-x.x Rtop=400k Rbot=600k Ctop=4p +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN -128 112 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2118-1.2.asy b/spice/copy/sym/PowerProducts/ADP2118-1.2.asy new file mode 100755 index 0000000..c427b2f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2118-1.2.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 144 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2118-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2118-x.x.sub +SYMATTR Description 3A 1.2MHz/600kHz High Efficiency Synchronous Step-Down DC-DC Regulator, Fixed 1.2V Output +SYMATTR Value2 ADP2118-x.x Rtop=500k Rbot=500k Ctop=4p +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN -128 112 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2118-1.5.asy b/spice/copy/sym/PowerProducts/ADP2118-1.5.asy new file mode 100755 index 0000000..8766e90 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2118-1.5.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 144 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2118-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2118-x.x.sub +SYMATTR Description 3A 1.2MHz/600kHz High Efficiency Synchronous Step-Down DC-DC Regulator, Fixed 1.5V Output +SYMATTR Value2 ADP2118-x.x Rtop=600k Rbot=400k Ctop=4p +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN -128 112 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2118-1.8.asy b/spice/copy/sym/PowerProducts/ADP2118-1.8.asy new file mode 100755 index 0000000..8596ccb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2118-1.8.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 144 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2118-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2118-x.x.sub +SYMATTR Description 3A 1.2MHz/600kHz High Efficiency Synchronous Step-Down DC-DC Regulator, Fixed 1.8V Output +SYMATTR Value2 ADP2118-x.x Rtop=666.7k Rbot=333.3k Ctop=4p +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN -128 112 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2118-2.5.asy b/spice/copy/sym/PowerProducts/ADP2118-2.5.asy new file mode 100755 index 0000000..917b1d1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2118-2.5.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 144 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2118-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2118-x.x.sub +SYMATTR Description 3A 1.2MHz/600kHz High Efficiency Synchronous Step-Down DC-DC Regulator, Fixed 2.5V Output +SYMATTR Value2 ADP2118-x.x Rtop=760k Rbot=240k Ctop=4p +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN -128 112 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2118-3.3.asy b/spice/copy/sym/PowerProducts/ADP2118-3.3.asy new file mode 100755 index 0000000..09131ef --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2118-3.3.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 144 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2118-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2118-x.x.sub +SYMATTR Description 3A 1.2MHz/600kHz High Efficiency Synchronous Step-Down DC-DC Regulator, Fixed 3.3V Output +SYMATTR Value2 ADP2118-x.x Rtop=818.2k Rbot=181.8k Ctop=4p +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN -128 112 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2118-ADJ.asy b/spice/copy/sym/PowerProducts/ADP2118-ADJ.asy new file mode 100755 index 0000000..e1d929f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2118-ADJ.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 144 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2118-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel ADP2118-x.x.sub +SYMATTR Description 3A 1.2MHz/600kHz High Efficiency Synchronous Step-Down DC-DC Regulator, Fixed 1.0V Output +SYMATTR Value2 ADP2118-x.x Rtop=10 Rbot=1T Ctop=4p +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN -128 112 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2119-1.0.asy b/spice/copy/sym/PowerProducts/ADP2119-1.0.asy new file mode 100755 index 0000000..9d12aeb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2119-1.0.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2119-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2119-1.0.sub +SYMATTR Description 1.0V Fixed Output 2A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2119-1.0 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2119-1.2.asy b/spice/copy/sym/PowerProducts/ADP2119-1.2.asy new file mode 100755 index 0000000..f718aa5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2119-1.2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2119-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2119-1.2.sub +SYMATTR Description 1.2V Fixed Output 2A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2119-1.2 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2119-1.5.asy b/spice/copy/sym/PowerProducts/ADP2119-1.5.asy new file mode 100755 index 0000000..565124b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2119-1.5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2119-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2119-1.5.sub +SYMATTR Description 1.5V Fixed Output 2A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2119-1.5 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2119-1.8.asy b/spice/copy/sym/PowerProducts/ADP2119-1.8.asy new file mode 100755 index 0000000..f3646fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2119-1.8.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2119-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2119-1.8.sub +SYMATTR Description 1.8V Fixed Output 2A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2119-1.8 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2119-2.5.asy b/spice/copy/sym/PowerProducts/ADP2119-2.5.asy new file mode 100755 index 0000000..40ecb38 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2119-2.5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2119-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2119-2.5.sub +SYMATTR Description 2.5V Fixed Output 2A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2119-2.5 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2119-3.3.asy b/spice/copy/sym/PowerProducts/ADP2119-3.3.asy new file mode 100755 index 0000000..77cad30 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2119-3.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2119-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2119-3.3.sub +SYMATTR Description 3.3V Fixed Output 2A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2119-3.3 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2119-ADJ.asy b/spice/copy/sym/PowerProducts/ADP2119-ADJ.asy new file mode 100755 index 0000000..d8d10c8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2119-ADJ.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -240 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2119-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel ADP2119-ADJ.sub +SYMATTR Description Adjustable Output 2A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2119-ADJ +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2120-1.0.asy b/spice/copy/sym/PowerProducts/ADP2120-1.0.asy new file mode 100755 index 0000000..532529d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2120-1.0.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -256 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2120-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2120-1.0.sub +SYMATTR Description 1.0V Fixed Output 1.25A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2120-1.0 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2120-1.2.asy b/spice/copy/sym/PowerProducts/ADP2120-1.2.asy new file mode 100755 index 0000000..d74101e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2120-1.2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -256 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2120-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2120-1.2.sub +SYMATTR Description 1.2V Fixed Output 1.25A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2120-1.2 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2120-1.5.asy b/spice/copy/sym/PowerProducts/ADP2120-1.5.asy new file mode 100755 index 0000000..ada39bc --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2120-1.5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -256 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2120-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2120-1.5.sub +SYMATTR Description 1.5V Fixed Output 1.25A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2120-1.5 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2120-1.8.asy b/spice/copy/sym/PowerProducts/ADP2120-1.8.asy new file mode 100755 index 0000000..215f2cd --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2120-1.8.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -256 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2120-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2120-1.8.sub +SYMATTR Description 1.8V Fixed Output 1.25A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2120-1.8 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2120-2.5.asy b/spice/copy/sym/PowerProducts/ADP2120-2.5.asy new file mode 100755 index 0000000..c0a9287 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2120-2.5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -256 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2120-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2120-2.5.sub +SYMATTR Description 2.5V Fixed Output 1.25A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2120-2.5 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2120-3.3.asy b/spice/copy/sym/PowerProducts/ADP2120-3.3.asy new file mode 100755 index 0000000..0ade02e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2120-3.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -256 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2120-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2120-3.3.sub +SYMATTR Description 3.3V Fixed Output 1.25A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2120-3.3 +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2120-ADJ.asy b/spice/copy/sym/PowerProducts/ADP2120-ADJ.asy new file mode 100755 index 0000000..0225983 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2120-ADJ.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -256 128 80 +TEXT 0 -88 Center 2 ADI +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 -8 Center 2 +SYMATTR Value ADP2120-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel ADP2120-ADJ.sub +SYMATTR Description Adjustable Output 1.25A 1.2MHz Synchronous Step-Down DC-DC Regulator +SYMATTR Value2 ADP2120-ADJ +PIN -128 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 7 +PIN 128 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -128 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 9 +PIN -128 -128 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP2138-0.8.asy b/spice/copy/sym/PowerProducts/ADP2138-0.8.asy new file mode 100755 index 0000000..e573601 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2138-0.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2138-0.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2138-x.x.sub +SYMATTR Value2 ADP2138-x.x Rtop=48K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator, Fixed 0.8V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2138-1.0.asy b/spice/copy/sym/PowerProducts/ADP2138-1.0.asy new file mode 100755 index 0000000..2af5d65 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2138-1.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2138-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2138-x.x.sub +SYMATTR Value2 ADP2138-x.x Rtop=80K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator, Fixed 1.0V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2138-1.2.asy b/spice/copy/sym/PowerProducts/ADP2138-1.2.asy new file mode 100755 index 0000000..26eb6fd --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2138-1.2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2138-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2138-x.x.sub +SYMATTR Value2 ADP2138-x.x Rtop=112K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator, Fixed 1.2V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2138-1.5.asy b/spice/copy/sym/PowerProducts/ADP2138-1.5.asy new file mode 100755 index 0000000..1f14ae5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2138-1.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2138-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2138-x.x.sub +SYMATTR Value2 ADP2138-x.x Rtop=160K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator, Fixed 1.5V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2138-1.8.asy b/spice/copy/sym/PowerProducts/ADP2138-1.8.asy new file mode 100755 index 0000000..97538a5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2138-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2138-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2138-x.x.sub +SYMATTR Value2 ADP2138-x.x Rtop=208K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator, Fixed 1.8V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2138-2.5.asy b/spice/copy/sym/PowerProducts/ADP2138-2.5.asy new file mode 100755 index 0000000..6f2e4fb --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2138-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2138-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2138-x.x.sub +SYMATTR Value2 ADP2138-x.x Rtop=320K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator, Fixed 2.5V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2138-2.8.asy b/spice/copy/sym/PowerProducts/ADP2138-2.8.asy new file mode 100755 index 0000000..32bf95b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2138-2.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2138-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2138-x.x.sub +SYMATTR Value2 ADP2138-x.x Rtop=368K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator, Fixed 2.8V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2138-3.0.asy b/spice/copy/sym/PowerProducts/ADP2138-3.0.asy new file mode 100755 index 0000000..22823b7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2138-3.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2138-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2138-x.x.sub +SYMATTR Value2 ADP2138-x.x Rtop=400K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator, Fixed 3.0V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2138-3.3.asy b/spice/copy/sym/PowerProducts/ADP2138-3.3.asy new file mode 100755 index 0000000..bf9a29a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2138-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2138-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2138-x.x.sub +SYMATTR Value2 ADP2138-x.x Rtop=448K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator, Fixed 3.3V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2139-0.8.asy b/spice/copy/sym/PowerProducts/ADP2139-0.8.asy new file mode 100755 index 0000000..48d6c4a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2139-0.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2139-0.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2139-x.x.sub +SYMATTR Value2 ADP2139-x.x Rtop=48K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 0.8V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2139-1.0.asy b/spice/copy/sym/PowerProducts/ADP2139-1.0.asy new file mode 100755 index 0000000..c079051 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2139-1.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2139-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2139-x.x.sub +SYMATTR Value2 ADP2139-x.x Rtop=80K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.0V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2139-1.2.asy b/spice/copy/sym/PowerProducts/ADP2139-1.2.asy new file mode 100755 index 0000000..e4b340b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2139-1.2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2139-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2139-x.x.sub +SYMATTR Value2 ADP2139-x.x Rtop=112K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.2V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2139-1.5.asy b/spice/copy/sym/PowerProducts/ADP2139-1.5.asy new file mode 100755 index 0000000..bb8ea5e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2139-1.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2139-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2139-x.x.sub +SYMATTR Value2 ADP2139-x.x Rtop=160K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.5V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2139-1.8.asy b/spice/copy/sym/PowerProducts/ADP2139-1.8.asy new file mode 100755 index 0000000..0731350 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2139-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2139-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2139-x.x.sub +SYMATTR Value2 ADP2139-x.x Rtop=208K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 1.8V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2139-2.5.asy b/spice/copy/sym/PowerProducts/ADP2139-2.5.asy new file mode 100755 index 0000000..07c7f0e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2139-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2139-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2139-x.x.sub +SYMATTR Value2 ADP2139-x.x Rtop=320K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 2.5V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2139-2.8.asy b/spice/copy/sym/PowerProducts/ADP2139-2.8.asy new file mode 100755 index 0000000..aa61e54 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2139-2.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2139-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2139-x.x.sub +SYMATTR Value2 ADP2139-x.x Rtop=368K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 2.8V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2139-3.0.asy b/spice/copy/sym/PowerProducts/ADP2139-3.0.asy new file mode 100755 index 0000000..5d5f36d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2139-3.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2139-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2139-x.x.sub +SYMATTR Value2 ADP2139-x.x Rtop=400K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 3.0V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2139-3.3.asy b/spice/copy/sym/PowerProducts/ADP2139-3.3.asy new file mode 100755 index 0000000..9ecc922 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2139-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP2139-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2139-x.x.sub +SYMATTR Value2 ADP2139-x.x Rtop=448K +SYMATTR Description Compact, 3MHz, 800mA, Synchronous Step-Down Regulator with Output Discharge, Fixed 3.3V Output +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2164-1.0.asy b/spice/copy/sym/PowerProducts/ADP2164-1.0.asy new file mode 100755 index 0000000..651c207 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2164-1.0.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 -2 -165 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value ADP2164-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2164-x.x.sub +SYMATTR Value2 ADP2164-x.x Rtop=400K Rbot=600K +SYMATTR Description 6.5 V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator, Fixed 1.0V output +PIN -176 32 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -176 176 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 176 -192 RIGHT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -272 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -176 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 176 176 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2164-1.2.asy b/spice/copy/sym/PowerProducts/ADP2164-1.2.asy new file mode 100755 index 0000000..952caf3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2164-1.2.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 -2 -165 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value ADP2164-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2164-x.x.sub +SYMATTR Value2 ADP2164-x.x Rtop=500K Rbot=500K +SYMATTR Description 6.5 V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator, Fixed 1.2V output +PIN -176 32 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -176 176 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 176 -192 RIGHT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -272 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -176 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 176 176 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2164-1.5.asy b/spice/copy/sym/PowerProducts/ADP2164-1.5.asy new file mode 100755 index 0000000..511a251 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2164-1.5.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 -2 -165 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value ADP2164-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2164-x.x.sub +SYMATTR Value2 ADP2164-x.x Rtop=600K Rbot=400K +SYMATTR Description 6.5 V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator, Fixed 1.5V output +PIN -176 32 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -176 176 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 176 -192 RIGHT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -272 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -176 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 176 176 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2164-1.8.asy b/spice/copy/sym/PowerProducts/ADP2164-1.8.asy new file mode 100755 index 0000000..42b4e92 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2164-1.8.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 -2 -165 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value ADP2164-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2164-x.x.sub +SYMATTR Value2 ADP2164-x.x Rtop=667K Rbot=333K +SYMATTR Description 6.5 V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator, Fixed 1.8V output +PIN -176 32 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -176 176 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 176 -192 RIGHT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -272 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -176 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 176 176 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2164-2.5.asy b/spice/copy/sym/PowerProducts/ADP2164-2.5.asy new file mode 100755 index 0000000..1feac38 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2164-2.5.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 -2 -165 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value ADP2164-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2164-x.x.sub +SYMATTR Value2 ADP2164-x.x Rtop=776K Rbot=240K +SYMATTR Description 6.5 V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator, Fixed 2.5V output +PIN -176 32 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -176 176 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 176 -192 RIGHT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -272 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -176 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 176 176 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2164-3.3.asy b/spice/copy/sym/PowerProducts/ADP2164-3.3.asy new file mode 100755 index 0000000..7e2f95a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2164-3.3.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 -2 -165 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value ADP2164-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2164-x.x.sub +SYMATTR Value2 ADP2164-x.x Rtop=818K Rbot=182K +SYMATTR Description 6.5 V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator, Fixed 3.3V output +PIN -176 32 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -176 176 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 176 -192 RIGHT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -272 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -176 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 176 176 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2164.asy b/spice/copy/sym/PowerProducts/ADP2164.asy new file mode 100755 index 0000000..9272411 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2164.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 -2 -165 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value ADP2164 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2164.sub +SYMATTR Value2 ADP2164 +SYMATTR Description 6.5 V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator +PIN -176 32 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -176 176 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 176 -192 RIGHT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -272 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -176 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 176 176 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/ADP2165-1.0.asy b/spice/copy/sym/PowerProducts/ADP2165-1.0.asy new file mode 100755 index 0000000..6ba4dc4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2165-1.0.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 167 Center 2 +SYMATTR Value ADP2165-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2165-x.x.sub +SYMATTR Value2 ADP2165-x.x Rtop=400K Rbot=600K +SYMATTR Description 5.5V, 5A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 1.0V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2165-1.2.asy b/spice/copy/sym/PowerProducts/ADP2165-1.2.asy new file mode 100755 index 0000000..9f441b5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2165-1.2.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2165-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2165-x.x.sub +SYMATTR Value2 ADP2165-x.x Rtop=500K Rbot=500K +SYMATTR Description 5.5V, 5A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 1.2V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2165-1.5.asy b/spice/copy/sym/PowerProducts/ADP2165-1.5.asy new file mode 100755 index 0000000..38e9be1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2165-1.5.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2165-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2165-x.x.sub +SYMATTR Value2 ADP2165-x.x Rtop=600K Rbot=400K +SYMATTR Description 5.5V, 5A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 1.5V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2165-1.8.asy b/spice/copy/sym/PowerProducts/ADP2165-1.8.asy new file mode 100755 index 0000000..f7c6c9f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2165-1.8.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2165-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2165-x.x.sub +SYMATTR Value2 ADP2165-x.x Rtop=667K Rbot=333K +SYMATTR Description 5.5V, 5A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 1.8V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2165-2.5.asy b/spice/copy/sym/PowerProducts/ADP2165-2.5.asy new file mode 100755 index 0000000..6fa190f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2165-2.5.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2165-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2165-x.x.sub +SYMATTR Value2 ADP2165-x.x Rtop=760K Rbot=240K +SYMATTR Description 5.5V, 5A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 2.5V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2165-3.3.asy b/spice/copy/sym/PowerProducts/ADP2165-3.3.asy new file mode 100755 index 0000000..354d70f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2165-3.3.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2165-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2165-x.x.sub +SYMATTR Value2 ADP2165-x.x Rtop=818K Rbot=182K +SYMATTR Description 5.5V, 5A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 3.3V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2165.asy b/spice/copy/sym/PowerProducts/ADP2165.asy new file mode 100755 index 0000000..21f36b4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2165.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2165 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2165.sub +SYMATTR Value2 ADP2165 +SYMATTR Description 5.5V, 5A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Adjustable Output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2166-1.0.asy b/spice/copy/sym/PowerProducts/ADP2166-1.0.asy new file mode 100755 index 0000000..3e0b30f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2166-1.0.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2166-1.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2166-x.x.sub +SYMATTR Value2 ADP2166-x.x Rtop=400K Rbot=600K +SYMATTR Description 5.5V, 6A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 1.0V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2166-1.2.asy b/spice/copy/sym/PowerProducts/ADP2166-1.2.asy new file mode 100755 index 0000000..c5265d9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2166-1.2.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2166-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2166-x.x.sub +SYMATTR Value2 ADP2166-x.x Rtop=500K Rbot=500K +SYMATTR Description 5.5V, 6A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 1.2V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2166-1.5.asy b/spice/copy/sym/PowerProducts/ADP2166-1.5.asy new file mode 100755 index 0000000..3bf788c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2166-1.5.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2166-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2166-x.x.sub +SYMATTR Value2 ADP2166-x.x Rtop=600K Rbot=400K +SYMATTR Description 5.5V, 6A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 1.5V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2166-1.8.asy b/spice/copy/sym/PowerProducts/ADP2166-1.8.asy new file mode 100755 index 0000000..c3a1df8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2166-1.8.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -153 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2166-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2166-x.x.sub +SYMATTR Value2 ADP2166-x.x Rtop=667K Rbot=333K +SYMATTR Description 5.5V, 6A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 1.8V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2166-2.5.asy b/spice/copy/sym/PowerProducts/ADP2166-2.5.asy new file mode 100755 index 0000000..60b1ebd --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2166-2.5.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -153 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2166-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2166-x.x.sub +SYMATTR Value2 ADP2166-x.x Rtop=760K Rbot=240K +SYMATTR Description 5.5V, 6A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 2.5V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2166-3.3.asy b/spice/copy/sym/PowerProducts/ADP2166-3.3.asy new file mode 100755 index 0000000..b7e6c6a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2166-3.3.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2166-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2166-x.x.sub +SYMATTR Value2 ADP2166-x.x Rtop=818K Rbot=182K +SYMATTR Description 5.5V, 6A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Fixed 3.3V output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2166.asy b/spice/copy/sym/PowerProducts/ADP2166.asy new file mode 100755 index 0000000..475967c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2166.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -152 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value ADP2166 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2166.sub +SYMATTR Value2 ADP2166 +SYMATTR Description 5.5V, 6A, High Efficiency, Synchronous Buck Regulator with Output Tracking, Adjustable Output +PIN -160 -32 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 1 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName TRK +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 5 +PIN -48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 48 -256 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 8 +PIN -48 -256 TOP 8 +PINATTR PinName Avin +PINATTR SpiceOrder 9 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN 160 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 208 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 13 +PIN 160 -112 RIGHT 8 +PINATTR PinName Bst +PINATTR SpiceOrder 14 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2300.asy b/spice/copy/sym/PowerProducts/ADP2300.asy new file mode 100755 index 0000000..42f0b13 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2300.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP2300 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2300_1.sub +SYMATTR Value2 ADP2300_1 FREQ=0 CSGain=0.25 +SYMATTR Description 1.2 A, 20 V, 700kHz Nonsynchronous Step-Down Regulator +PIN -128 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2301.asy b/spice/copy/sym/PowerProducts/ADP2301.asy new file mode 100755 index 0000000..ce8d33a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2301.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP2301 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2300_1.sub +SYMATTR Value2 ADP2300_1 FREQ=1 CSGain=0.25 +SYMATTR Description 1.2A, 20V, 1.4MHz Nonsynchronous Step-Down Regulator +PIN -128 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP2302.asy b/spice/copy/sym/PowerProducts/ADP2302.asy new file mode 100755 index 0000000..b63b475 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2302.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP2302 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2302.sub +SYMATTR Value2 ADP2302 FREQ=0 CSGain=0.12 CL=0.42 +SYMATTR Description 2 A, 20 V, 700kHz Nonsynchronous Step-Down Regulator +PIN -128 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -128 128 LEFT 8 +PINATTR PinName PGood +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/ADP2303.asy b/spice/copy/sym/PowerProducts/ADP2303.asy new file mode 100755 index 0000000..21d8b5f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2303.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP2303 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2303.sub +SYMATTR Value2 ADP2303 FREQ=0 CSGain=0.12 CL=0.66 +SYMATTR Description 3 A, 20 V, 700kHz Nonsynchronous Step-Down Regulator +PIN -128 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 128 -128 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -128 128 LEFT 8 +PINATTR PinName PGood +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/ADP2360-3.3.asy b/spice/copy/sym/PowerProducts/ADP2360-3.3.asy new file mode 100755 index 0000000..a84d965 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2360-3.3.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP2360-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2360-3.3.sub +SYMATTR Value2 ADP2360-3.3 +SYMATTR Description 60V 50mA High Efficiency Buck Regulator, Fixed 3.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN 48 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -48 144 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP2360-5.0.asy b/spice/copy/sym/PowerProducts/ADP2360-5.0.asy new file mode 100755 index 0000000..3c7f3b8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2360-5.0.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP2360-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2360-5.0.sub +SYMATTR Value2 ADP2360-5.0 +SYMATTR Description 60V 50mA High Efficiency Buck Regulator, Fixed 5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN 48 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -48 144 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP2360.asy b/spice/copy/sym/PowerProducts/ADP2360.asy new file mode 100755 index 0000000..06dffa5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2360.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value ADP2360 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2360.sub +SYMATTR Value2 ADP2360 +SYMATTR Description 60V 50mA High Efficiency Buck Regulator +PIN -128 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN 48 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -48 144 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP2370-1.2.asy b/spice/copy/sym/PowerProducts/ADP2370-1.2.asy new file mode 100755 index 0000000..2c98ce6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2370-1.2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 -1 -72 Center 2 +WINDOW 3 1 88 Center 2 +SYMATTR Value ADP2370-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=320m Rt=166.6667k Rb=333.33333k C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=0 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 1.2V Output +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2370-1.5.asy b/spice/copy/sym/PowerProducts/ADP2370-1.5.asy new file mode 100755 index 0000000..2ff736d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2370-1.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 -1 -72 Center 2 +WINDOW 3 1 88 Center 2 +SYMATTR Value ADP2370-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=400m Rt=233333.3 Rb=266666.7 C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=0 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 1.5V Output +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2370-1.8.asy b/spice/copy/sym/PowerProducts/ADP2370-1.8.asy new file mode 100755 index 0000000..c3b98b9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2370-1.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 -1 -72 Center 2 +WINDOW 3 1 88 Center 2 +SYMATTR Value ADP2370-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=400m Rt=277777.8 Rb=222222.2 C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=0 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 1.8V Output +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2370-2.5.asy b/spice/copy/sym/PowerProducts/ADP2370-2.5.asy new file mode 100755 index 0000000..2c1b7ab --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2370-2.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 1 88 Center 2 +SYMATTR Value ADP2370-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=420m Rt=340000 Rb=160000 C1=1.6p Rc1=300k R3=5.92k Rshort=100MEG PD=0 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 2.5V Output +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2370-3.0.asy b/spice/copy/sym/PowerProducts/ADP2370-3.0.asy new file mode 100755 index 0000000..ae6c970 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2370-3.0.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value ADP2370-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=440m Rt=366.6666k Rb=133.3333k C1=1.6p Rc1=300k R3=5.92k Rshort=100MEG PD=0 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 3.0V Output +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2370-3.3.asy b/spice/copy/sym/PowerProducts/ADP2370-3.3.asy new file mode 100755 index 0000000..4280314 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2370-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 -1 -72 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value ADP2370-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=440m Rt=378787.879 Rb=121212.121 C1=1.6p Rc1=300k R3=5.92k Rshort=100MEG PD=0 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 3.3V Output +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2370-5.0.asy b/spice/copy/sym/PowerProducts/ADP2370-5.0.asy new file mode 100755 index 0000000..59cad9f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2370-5.0.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 1 88 Center 2 +SYMATTR Value ADP2370-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=440m Rt=420000 Rb=80000 C1=1.6p Rc1=300k R3=5.92k Rshort=100MEG PD=0 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 5.0V Output +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2370-ADJ.asy b/spice/copy/sym/PowerProducts/ADP2370-ADJ.asy new file mode 100755 index 0000000..2c9f094 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2370-ADJ.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 -1 88 Center 2 +SYMATTR Value ADP2370-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=400m Rt=100MEG Rb=100MEG C1=1.6p Rc1=100k R3=5.92k Rshort=100m PD=0 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2371-1.2.asy b/spice/copy/sym/PowerProducts/ADP2371-1.2.asy new file mode 100755 index 0000000..903213c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2371-1.2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 -1 -72 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value ADP2371-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=320m Rt=166666 Rb=333333 C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=1 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 1.2V Output with Quick Output Discharge(QOD) +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2371-1.8.asy b/spice/copy/sym/PowerProducts/ADP2371-1.8.asy new file mode 100755 index 0000000..a0d5e5e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2371-1.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 -1 88 Center 2 +SYMATTR Value ADP2371-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=400m Rt=277777.8 Rb=222222.2 C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=1 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 1.8V Output with Quick Output Discharge(QOD) +PIN -128 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -128 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2371-3.3.asy b/spice/copy/sym/PowerProducts/ADP2371-3.3.asy new file mode 100755 index 0000000..0c6bab5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2371-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value ADP2371-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=440m Rt=378787.879 Rb=121212.121 C1=1.6p Rc1=300k R3=5.92k Rshort=100MEG PD=1 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator, Fixed 3.3V Output with Quick Output Discharge(QOD) +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2371-ADJ.asy b/spice/copy/sym/PowerProducts/ADP2371-ADJ.asy new file mode 100755 index 0000000..ef1a564 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2371-ADJ.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value ADP2371-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel ADP2370.sub +SYMATTR Value2 ADP2370 IPSM=400m Rt=100MEG Rb=100MEG C1=1.6p Rc1=100k R3=5.92k Rshort=100m PD=1 +SYMATTR Description High Voltage, 1.2MHz/600kHz, 800mA Low Quiescent Current Buck Regulator with Quick Output Discharge(QOD) +PIN -112 48 LEFT 8 +PINATTR PinName FSEL +PINATTR SpiceOrder 1 +PIN -112 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -112 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 112 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN 112 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2384.asy b/spice/copy/sym/PowerProducts/ADP2384.asy new file mode 100755 index 0000000..1a27809 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2384.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -272 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -169 Center 2 +WINDOW 3 -1 167 Center 2 +SYMATTR Value ADP2384 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2384.sub +SYMATTR Value2 ADP2384 +SYMATTR Description 20V, 4A, Synchronous, Step-Down DC-to-DC Regulator +PIN 160 224 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN 0 -272 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -160 112 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -160 -224 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 6 +PIN 160 -112 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -160 224 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 0 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -160 0 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 10 +PIN 160 -224 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/ADP2386.asy b/spice/copy/sym/PowerProducts/ADP2386.asy new file mode 100755 index 0000000..643196c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2386.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -272 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -169 Center 2 +WINDOW 3 -1 167 Center 2 +SYMATTR Value ADP2386 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2386.sub +SYMATTR Value2 ADP2386 +SYMATTR Description 20V, 6A, Synchronous, Step-Down DC-to-DC Regulator +PIN 160 224 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN 0 -272 TOP 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -160 112 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -160 -224 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 6 +PIN 160 -112 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -160 224 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 0 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -160 0 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 10 +PIN 160 -224 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/ADP2387.asy b/spice/copy/sym/PowerProducts/ADP2387.asy new file mode 100755 index 0000000..7c5d9c3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2387.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -272 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -169 Center 2 +WINDOW 3 -1 167 Center 2 +SYMATTR Value ADP2387 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2387.sub +SYMATTR Value2 ADP2387 +SYMATTR Description 20V, 6A, Programmable current-limit, Synchronous, Step-Down DC-to-DC Regulator +PIN 160 224 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN 0 -272 TOP 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -160 112 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -160 -224 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 6 +PIN 160 -112 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -160 224 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 0 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -160 0 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 10 +PIN 160 -224 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/ADP2389.asy b/spice/copy/sym/PowerProducts/ADP2389.asy new file mode 100755 index 0000000..fcc1638 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2389.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -272 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -169 Center 2 +WINDOW 3 -1 167 Center 2 +SYMATTR Value ADP2389 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2389.sub +SYMATTR Value2 ADP2389 +SYMATTR Description 18V, 12A, Programmable current limit, Synchronous Buck Regulator with Enhanced transient response +PIN 160 208 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN 48 -272 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -160 128 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 6 +PIN 160 -112 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -160 208 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 9 +PIN -160 48 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 12 +PIN -160 -32 LEFT 8 +PINATTR PinName Ftw +PINATTR SpiceOrder 13 +PIN -48 -272 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 14 +PIN 48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2390.asy b/spice/copy/sym/PowerProducts/ADP2390.asy new file mode 100755 index 0000000..70fd5ed --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2390.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -272 160 272 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -169 Center 2 +WINDOW 3 -1 167 Center 2 +SYMATTR Value ADP2390 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2390.sub +SYMATTR Value2 ADP2390 +SYMATTR Description 18V, 12A, Programmable current limit, PFM, Synchronous Buck Regulator with Enhanced transient response +PIN 160 208 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN 48 -272 TOP 8 +PINATTR PinName Pvin +PINATTR SpiceOrder 2 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -160 128 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 6 +PIN 160 -112 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -160 208 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -48 272 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 9 +PIN -160 48 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 11 +PIN -160 -112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 12 +PIN -160 -32 LEFT 8 +PINATTR PinName Ftw +PINATTR SpiceOrder 13 +PIN -48 -272 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 14 +PIN 48 272 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP2441.asy b/spice/copy/sym/PowerProducts/ADP2441.asy new file mode 100755 index 0000000..32e97f6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2441.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -169 Center 2 +WINDOW 3 -1 167 Center 2 +SYMATTR Value ADP2441 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2441.sub +SYMATTR Value2 ADP2441 +SYMATTR Description 1A, 36V, Synchronous, Step-Down DC-to-DC Regulator +PIN -176 224 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 176 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 176 112 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 176 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -176 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -176 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 9 +PIN 176 224 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 10 +PIN -176 112 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -176 0 LEFT 8 +PINATTR PinName SS/TRK +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/ADP2442.asy b/spice/copy/sym/PowerProducts/ADP2442.asy new file mode 100755 index 0000000..00a5d86 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2442.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +TEXT -167 20 Left 2 Mode +WINDOW 0 0 -169 Center 2 +WINDOW 3 -1 167 Center 2 +SYMATTR Value ADP2442 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2442.sub +SYMATTR Value2 ADP2442 +SYMATTR Description 1A, 36V, Synchronous, Step-Down DC-to-DC Regulator with External Clock Synchronization +PIN -176 224 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 176 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 176 112 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 176 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -176 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -176 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 9 +PIN 176 224 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 10 +PIN -176 112 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -176 0 LEFT 8 +PINATTR PinName Sync/ +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/ADP2443.asy b/spice/copy/sym/PowerProducts/ADP2443.asy new file mode 100755 index 0000000..477aeba --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2443.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -272 176 288 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -169 Center 2 +WINDOW 3 -1 167 Center 2 +SYMATTR Value ADP2443 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2443.sub +SYMATTR Value2 ADP2443 +SYMATTR Description 3A, 36V, Synchronous, Step-Down DC-to-DC Regulator +PIN -176 224 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 176 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 176 112 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -64 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 176 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 +PIN 176 -224 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 15 +PIN 0 -272 TOP 8 +PINATTR PinName PVin +PINATTR SpiceOrder 16 +PIN -176 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 20 +PIN 176 224 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 21 +PIN -176 112 LEFT 8 +PINATTR PinName Rt/SYNC +PINATTR SpiceOrder 22 +PIN -176 -224 LEFT 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 23 +PIN -176 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/ADP2503-2.8.asy b/spice/copy/sym/PowerProducts/ADP2503-2.8.asy new file mode 100755 index 0000000..fe7901e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2503-2.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2503-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=2.8 Limit=1.2 R2=100k +SYMATTR Description 600mA, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2503-3.3.asy b/spice/copy/sym/PowerProducts/ADP2503-3.3.asy new file mode 100755 index 0000000..59d5252 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2503-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2503-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=3.3 Limit=1.2 R2=100k +SYMATTR Description 600mA, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2503-3.5.asy b/spice/copy/sym/PowerProducts/ADP2503-3.5.asy new file mode 100755 index 0000000..cf7461e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2503-3.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2503-3.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=3.5 Limit=1.2 R2=100k +SYMATTR Description 600mA, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2503-4.2.asy b/spice/copy/sym/PowerProducts/ADP2503-4.2.asy new file mode 100755 index 0000000..9f7f3e4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2503-4.2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2503-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=4.2 Limit=1.2 R2=100k +SYMATTR Description 600mA, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2503-4.5.asy b/spice/copy/sym/PowerProducts/ADP2503-4.5.asy new file mode 100755 index 0000000..0c6b06e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2503-4.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2503-4.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=4.5 Limit=1.2 R2=100k +SYMATTR Description 600mA, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2503-5.0.asy b/spice/copy/sym/PowerProducts/ADP2503-5.0.asy new file mode 100755 index 0000000..6c31950 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2503-5.0.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2503-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=5.0 Limit=1.2 R2=100k +SYMATTR Description 600mA, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2503-ADJ.asy b/spice/copy/sym/PowerProducts/ADP2503-ADJ.asy new file mode 100755 index 0000000..18c71ff --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2503-ADJ.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2503-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=0.5001 Limit=1.2 R2=1G +SYMATTR Description 600mA, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2504-2.8.asy b/spice/copy/sym/PowerProducts/ADP2504-2.8.asy new file mode 100755 index 0000000..86729f0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2504-2.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2504-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=2.8 Limit=1.65 R2=100k +SYMATTR Description 1A, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2504-3.3.asy b/spice/copy/sym/PowerProducts/ADP2504-3.3.asy new file mode 100755 index 0000000..68690ec --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2504-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2504-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=3.3 Limit=1.65 R2=100k +SYMATTR Description 1A, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2504-3.5.asy b/spice/copy/sym/PowerProducts/ADP2504-3.5.asy new file mode 100755 index 0000000..22f268d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2504-3.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2504-3.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=3.5 Limit=1.65 R2=100k +SYMATTR Description 1A, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2504-4.2.asy b/spice/copy/sym/PowerProducts/ADP2504-4.2.asy new file mode 100755 index 0000000..34d718b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2504-4.2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2504-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=4.2 Limit=1.65 R2=100k +SYMATTR Description 1A, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2504-4.5.asy b/spice/copy/sym/PowerProducts/ADP2504-4.5.asy new file mode 100755 index 0000000..bb3a670 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2504-4.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2504-4.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=4.5 Limit=1.65 R2=100k +SYMATTR Description 1A, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2504-5.0.asy b/spice/copy/sym/PowerProducts/ADP2504-5.0.asy new file mode 100755 index 0000000..e14e240 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2504-5.0.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2504-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=5.0 Limit=1.65 R2=100k +SYMATTR Description 1A, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP2504-ADJ.asy b/spice/copy/sym/PowerProducts/ADP2504-ADJ.asy new file mode 100755 index 0000000..6aecbb5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP2504-ADJ.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 92 Center 2 +SYMATTR Value ADP2504-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel ADP2503_4.sub +SYMATTR Value2 ADP2503_4 Vout=0.5001 Limit=1.65 R2=1G +SYMATTR Description 1A, 2.5MHz Buck-Boost DC to DC Converters +PIN 128 -112 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 128 -32 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 128 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN -128 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADP3654.asy b/spice/copy/sym/PowerProducts/ADP3654.asy new file mode 100755 index 0000000..5ab2d1f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP3654.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -49 Center 2 +WINDOW 3 0 50 Center 2 +SYMATTR Value ADP3654 +SYMATTR Prefix X +SYMATTR SpiceModel ADP3654.sub +SYMATTR Value2 ADP3654 +SYMATTR Description High Speed, Dual, 4A MOSFET Driver +PIN 128 96 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN -128 -96 LEFT 8 +PINATTR PinName INA +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName INB +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName OUTA +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 5 +PIN -128 96 LEFT 8 +PINATTR PinName VDD +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP5003.asy b/spice/copy/sym/PowerProducts/ADP5003.asy new file mode 100755 index 0000000..76eb21b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5003.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 512 -176 -368 +TEXT 0 64 Center 2 ADI +WINDOW 3 -5 210 Center 2 +WINDOW 0 -1 -73 Center 2 +SYMATTR Value ADP5003 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5003.sub +SYMATTR Value2 ADP5003 +SYMATTR Description Low Noise Micro PMU,3 A Buck Regulator with 3 A LDO +PIN 176 64 RIGHT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN 176 -224 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 2 +PIN 64 -368 TOP 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 3 +PIN -176 -320 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 4 +PIN -64 512 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 5 +PIN 64 512 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 6 +PIN -176 -128 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 7 +PIN 176 160 RIGHT 8 +PINATTR PinName Pvin2 +PINATTR SpiceOrder 8 +PIN 176 256 RIGHT 8 +PINATTR PinName Pvout2 +PINATTR SpiceOrder 9 +PIN -176 -32 LEFT 8 +PINATTR PinName Pvinsys +PINATTR SpiceOrder 10 +PIN 176 -320 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 11 +PIN 176 352 RIGHT 8 +PINATTR PinName Vfb2p +PINATTR SpiceOrder 12 +PIN 176 448 RIGHT 8 +PINATTR PinName Vfb2n +PINATTR SpiceOrder 13 +PIN -176 352 LEFT 8 +PINATTR PinName Vbuf +PINATTR SpiceOrder 14 +PIN -64 -368 TOP 8 +PINATTR PinName Pvin1 +PINATTR SpiceOrder 15 +PIN -176 448 LEFT 8 +PINATTR PinName Vreg_ldo +PINATTR SpiceOrder 16 +PIN -176 256 LEFT 8 +PINATTR PinName Vset2 +PINATTR SpiceOrder 17 +PIN -176 160 LEFT 8 +PINATTR PinName Refout +PINATTR SpiceOrder 18 +PIN -176 64 LEFT 8 +PINATTR PinName Vset1 +PINATTR SpiceOrder 19 +PIN 176 -32 RIGHT 8 +PINATTR PinName Pwrgd +PINATTR SpiceOrder 20 +PIN -176 -224 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 21 +PIN 176 -128 RIGHT 8 +PINATTR PinName RT +PINATTR SpiceOrder 22 diff --git a/spice/copy/sym/PowerProducts/ADP5014_chan1_2.asy b/spice/copy/sym/PowerProducts/ADP5014_chan1_2.asy new file mode 100755 index 0000000..ebc465b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5014_chan1_2.asy @@ -0,0 +1,81 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 160 592 -160 -592 +TEXT 0 0 Center 2 ADI +TEXT 0 281 Center 2 ADP5014_chan1_2 +WINDOW 0 0 -336 Center 2 +WINDOW 39 -1 407 Center 2 +WINDOW 40 0 377 Center 2 +SYMATTR SpiceLine CL1=6.9 CL2=6.9 PSM=0 +SYMATTR SpiceLine2 timer=1 parallel=0 +SYMATTR Prefix X +SYMATTR Value ADP5014 +SYMATTR Description Switcher model of channels 1 and 2 of ADP5014 +SYMATTR ModelFile ADP5014.sub +SYMATTR Value2 RP=49m RN=37m CS=0.06 +PIN -160 336 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -160 448 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -160 -224 LEFT 8 +PINATTR PinName Vset1 +PINATTR SpiceOrder 3 +PIN -160 -560 LEFT 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 4 +PIN 160 -560 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 5 +PIN 160 -336 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 6 +PIN 160 -224 RIGHT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 7 +PIN -160 -336 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 8 +PIN -160 224 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 9 +PIN 160 -448 RIGHT 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 10 +PIN 160 0 RIGHT 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 11 +PIN -160 -448 LEFT 8 +PINATTR PinName AVin +PINATTR SpiceOrder 12 +PIN 160 336 RIGHT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 13 +PIN 160 448 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 14 +PIN -160 560 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 15 +PIN 160 560 RIGHT 8 +PINATTR PinName UVO +PINATTR SpiceOrder 16 +PIN 160 -112 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 160 224 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 18 +PIN 160 112 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 19 +PIN -160 0 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 20 +PIN -160 -112 LEFT 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 21 +PIN -160 112 LEFT 8 +PINATTR PinName Vset2 +PINATTR SpiceOrder 22 diff --git a/spice/copy/sym/PowerProducts/ADP5014_chan3_4.asy b/spice/copy/sym/PowerProducts/ADP5014_chan3_4.asy new file mode 100755 index 0000000..e37db33 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5014_chan3_4.asy @@ -0,0 +1,81 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 160 592 -160 -592 +TEXT 0 0 Center 2 ADI +TEXT 0 281 Center 2 ADP5014_chan3_4 +WINDOW 0 0 -336 Center 2 +WINDOW 39 0 409 Center 2 +WINDOW 40 -1 376 Center 2 +SYMATTR SpiceLine CL1=3.5 CL2=3.5 PSM=0 +SYMATTR SpiceLine2 timer=1 parallel=0 +SYMATTR Prefix X +SYMATTR Value ADP5014 +SYMATTR Description Switcher model of channels 3 and 4 of ADP5014 +SYMATTR ModelFile ADP5014.sub +SYMATTR Value2 RP=95m RN=73m CS=0.12 +PIN -160 336 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -160 448 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 2 +PIN -160 -224 LEFT 8 +PINATTR PinName Vset1 +PINATTR SpiceOrder 3 +PIN -160 -560 LEFT 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 4 +PIN 160 -560 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 5 +PIN 160 -336 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 6 +PIN 160 -224 RIGHT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 7 +PIN -160 -336 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 8 +PIN -160 224 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 9 +PIN 160 -448 RIGHT 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 10 +PIN 160 0 RIGHT 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 11 +PIN -160 -448 LEFT 8 +PINATTR PinName AVin +PINATTR SpiceOrder 12 +PIN 160 336 RIGHT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 13 +PIN 160 448 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 14 +PIN -160 560 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 15 +PIN 160 560 RIGHT 8 +PINATTR PinName UVO +PINATTR SpiceOrder 16 +PIN 160 -112 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 160 224 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 18 +PIN 160 112 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 19 +PIN -160 0 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 20 +PIN -160 -112 LEFT 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 21 +PIN -160 112 LEFT 8 +PINATTR PinName Vset2 +PINATTR SpiceOrder 22 diff --git a/spice/copy/sym/PowerProducts/ADP5050_chan1_2.asy b/spice/copy/sym/PowerProducts/ADP5050_chan1_2.asy new file mode 100755 index 0000000..cabaa7a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5050_chan1_2.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 304 -144 -336 +TEXT 0 -9 Center 2 ADI +TEXT 0 104 Center 2 ADP5050_chan1_2 +WINDOW 0 -1 -220 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP505x_chan1_2.sub +SYMATTR Value ADP505x_chan1_2 +SYMATTR Description Channel 1 and 2 Switcher model for the ADP5050, ADP5051, ADP5052, and ADP5053. +SYMATTR Value2 ADP505x_chan1_2 +PIN -144 272 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 160 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 272 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -176 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -288 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -176 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 144 -64 RIGHT 8 +PINATTR PinName DL +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 -64 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 10 +PIN -144 48 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 144 160 RIGHT 8 +PINATTR PinName Rlim +PINATTR SpiceOrder 13 +PIN -144 224 LEFT 8 +PINATTR PinName SS12 +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP5050_chan3_4.asy b/spice/copy/sym/PowerProducts/ADP5050_chan3_4.asy new file mode 100755 index 0000000..f0f49f7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5050_chan3_4.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 256 -144 -272 +TEXT 0 0 Center 2 ADI +TEXT 0 56 Center 2 ADP5050_chan3_4 +WINDOW 0 0 -56 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP505x_chan3_4.sub +SYMATTR Value ADP505x_chan3_4 +SYMATTR Description Channel 3 and 4 Switcher model for the ADP5050, ADP5051, ADP5052, and ADP5053. +SYMATTR Value2 ADP505x_chan3_4 +PIN -144 224 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 112 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 224 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -224 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 0 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN 144 112 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN -144 160 LEFT 8 +PINATTR PinName SS34 +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP5051_chan1_2.asy b/spice/copy/sym/PowerProducts/ADP5051_chan1_2.asy new file mode 100755 index 0000000..e1e758d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5051_chan1_2.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 304 -144 -336 +TEXT 0 -9 Center 2 ADI +TEXT 0 104 Center 2 ADP5051_chan1_2 +WINDOW 0 -1 -220 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP505x_chan1_2.sub +SYMATTR Value ADP505x_chan1_2 +SYMATTR Description Channel 1 and 2 Switcher model for the ADP5050, ADP5051, ADP5052, and ADP5053. +SYMATTR Value2 ADP505x_chan1_2 +PIN -144 272 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 160 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 272 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -176 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -288 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -176 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 144 -64 RIGHT 8 +PINATTR PinName DL +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 -64 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 10 +PIN -144 48 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 144 160 RIGHT 8 +PINATTR PinName Rlim +PINATTR SpiceOrder 13 +PIN -144 224 LEFT 8 +PINATTR PinName SS12 +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP5051_chan3_4.asy b/spice/copy/sym/PowerProducts/ADP5051_chan3_4.asy new file mode 100755 index 0000000..0b0bd94 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5051_chan3_4.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 256 -144 -272 +TEXT 0 0 Center 2 ADI +TEXT 0 56 Center 2 ADP5051_chan3_4 +WINDOW 0 0 -56 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP505x_chan3_4.sub +SYMATTR Value ADP505x_chan3_4 +SYMATTR Description Channel 3 and 4 Switcher model for the ADP5050, ADP5051, ADP5052, and ADP5053. +SYMATTR Value2 ADP505x_chan3_4 +PIN -144 224 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 112 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 224 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -224 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 0 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN 144 112 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN -144 160 LEFT 8 +PINATTR PinName SS34 +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP5052_chan1_2.asy b/spice/copy/sym/PowerProducts/ADP5052_chan1_2.asy new file mode 100755 index 0000000..53e8851 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5052_chan1_2.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 304 -144 -336 +TEXT 0 -9 Center 2 ADI +TEXT 0 104 Center 2 ADP5052_chan1_2 +WINDOW 0 -1 -220 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP505x_chan1_2.sub +SYMATTR Value ADP505x_chan1_2 +SYMATTR Description Channel 1 and 2 Switcher model for the ADP5050, ADP5051, ADP5052, and ADP5053. +SYMATTR Value2 ADP505x_chan1_2 +PIN -144 272 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 160 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 272 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -176 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -288 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -176 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 144 -64 RIGHT 8 +PINATTR PinName DL +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 -64 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 10 +PIN -144 48 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 144 160 RIGHT 8 +PINATTR PinName Rlim +PINATTR SpiceOrder 13 +PIN -144 224 LEFT 8 +PINATTR PinName SS12 +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP5052_chan3_4.asy b/spice/copy/sym/PowerProducts/ADP5052_chan3_4.asy new file mode 100755 index 0000000..78659ae --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5052_chan3_4.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 256 -144 -272 +TEXT 0 0 Center 2 ADI +TEXT 0 56 Center 2 ADP5052_chan3_4 +WINDOW 0 0 -56 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP505x_chan3_4.sub +SYMATTR Value ADP505x_chan3_4 +SYMATTR Description Channel 3 and 4 Switcher model for the ADP5050, ADP5051, ADP5052, and ADP5053. +SYMATTR Value2 ADP505x_chan3_4 +PIN -144 224 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 112 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 224 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -224 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 0 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN 144 112 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN -144 160 LEFT 8 +PINATTR PinName SS34 +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP5053_chan1_2.asy b/spice/copy/sym/PowerProducts/ADP5053_chan1_2.asy new file mode 100755 index 0000000..3c64b52 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5053_chan1_2.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 304 -144 -336 +TEXT 0 -9 Center 2 ADI +TEXT 0 104 Center 2 ADP5053_chan1_2 +WINDOW 0 -1 -220 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP505x_chan1_2.sub +SYMATTR Value ADP505x_chan1_2 +SYMATTR Description Channel 1 and 2 Switcher model for the ADP5050, ADP5051, ADP5052, and ADP5053. +SYMATTR Value2 ADP505x_chan1_2 +PIN -144 272 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 160 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 272 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -176 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -288 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -176 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 144 -64 RIGHT 8 +PINATTR PinName DL +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 -64 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 10 +PIN -144 48 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 144 160 RIGHT 8 +PINATTR PinName Rlim +PINATTR SpiceOrder 13 +PIN -144 224 LEFT 8 +PINATTR PinName SS12 +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP5053_chan3_4.asy b/spice/copy/sym/PowerProducts/ADP5053_chan3_4.asy new file mode 100755 index 0000000..324ce8b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5053_chan3_4.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 256 -144 -272 +TEXT 0 0 Center 2 ADI +TEXT 0 56 Center 2 ADP5053_chan3_4 +WINDOW 0 0 -56 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP505x_chan3_4.sub +SYMATTR Value ADP505x_chan3_4 +SYMATTR Description Channel 3 and 4 Switcher model for the ADP5050, ADP5051, ADP5052, and ADP5053. +SYMATTR Value2 ADP505x_chan3_4 +PIN -144 224 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 112 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 224 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -224 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 0 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN 144 112 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN -144 160 LEFT 8 +PINATTR PinName SS34 +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/ADP5054_chan1_2.asy b/spice/copy/sym/PowerProducts/ADP5054_chan1_2.asy new file mode 100755 index 0000000..78815de --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5054_chan1_2.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 304 -144 -336 +TEXT 0 -9 Center 2 ADI +TEXT 0 104 Center 2 ADP5054_chan1_2 +WINDOW 0 -1 -220 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5054_chan1_2.sub +SYMATTR Value ADP5054_chan1_2 +SYMATTR Description Channel 1 and 2 Switcher model for the ADP5054. +SYMATTR Value2 ADP5054_chan1_2 +PIN -144 272 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 160 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 272 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -176 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -288 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -176 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 144 -64 RIGHT 8 +PINATTR PinName DL +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 -64 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 10 +PIN -144 48 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 144 160 RIGHT 8 +PINATTR PinName Rlim +PINATTR SpiceOrder 13 +PIN 144 224 RIGHT 8 +PINATTR PinName CFG12 +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/ADP5054_chan3_4.asy b/spice/copy/sym/PowerProducts/ADP5054_chan3_4.asy new file mode 100755 index 0000000..6a6467d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5054_chan3_4.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 256 -144 -272 +TEXT 0 0 Center 2 ADI +TEXT 0 56 Center 2 ADP5054_chan3_4 +WINDOW 0 0 -56 Center 2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5054_chan3_4.sub +SYMATTR Value ADP5054_chan3_4 +SYMATTR Description Channel 3 and 4 Switcher model for the ADP5054 +SYMATTR Value2 ADP5054_chan3_4 +PIN -144 224 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 112 LEFT 8 +PINATTR PinName Sync_Mode +PINATTR SpiceOrder 2 +PIN 144 224 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 3 +PIN -144 -112 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -144 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -224 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 6 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN -144 176 LEFT 8 +PINATTR PinName CFG34 +PINATTR SpiceOrder 8 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 0 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN 144 112 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN 0 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/ADP5055.asy b/spice/copy/sym/PowerProducts/ADP5055.asy new file mode 100755 index 0000000..08076cf --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5055.asy @@ -0,0 +1,104 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 224 640 -240 -624 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +WINDOW 39 -10 319 Center 2 +WINDOW 40 -11 344 Center 2 +SYMATTR Value ADP5055 +SYMATTR SpiceLine Vref1=.6 Vref2=.6 Vref3=.6 +SYMATTR SpiceLine2 FT1=3 FT2=3 FT3=3 +SYMATTR Prefix X +SYMATTR Description Integrated Power Solution with Triple Buck Regulators and PMBus Interface +SYMATTR ModelFile ADP5055.sub +PIN 224 480 RIGHT 8 +PINATTR PinName Cfg1 +PINATTR SpiceOrder 1 +PIN 224 576 RIGHT 8 +PINATTR PinName Cfg2 +PINATTR SpiceOrder 2 +PIN -240 -384 LEFT 8 +PINATTR PinName Ramp1 +PINATTR SpiceOrder 3 +PIN 224 -192 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN -240 -192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 5 +PIN -240 576 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 6 +PIN -240 -288 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 7 +PIN 80 640 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN -240 -480 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 9 +PIN 224 -576 RIGHT 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 10 +PIN -240 480 LEFT 8 +PINATTR PinName Mode/Sync +PINATTR SpiceOrder 11 +PIN 224 -384 RIGHT 8 +PINATTR PinName Bst1 +PINATTR SpiceOrder 12 +PIN 224 192 RIGHT 8 +PINATTR PinName Bst3 +PINATTR SpiceOrder 13 +PIN -96 640 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 14 +PIN 224 288 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 15 +PIN 80 -624 TOP 8 +PINATTR PinName Pvin3 +PINATTR SpiceOrder 16 +PIN 224 -96 RIGHT 8 +PINATTR PinName Bst2 +PINATTR SpiceOrder 17 +PIN -240 288 LEFT 8 +PINATTR PinName EN3 +PINATTR SpiceOrder 18 +PIN -240 192 LEFT 8 +PINATTR PinName Ramp3 +PINATTR SpiceOrder 19 +PIN 224 384 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 20 +PIN -240 384 LEFT 8 +PINATTR PinName Comp3 +PINATTR SpiceOrder 21 +PIN 224 -480 RIGHT 8 +PINATTR PinName Pwrgd +PINATTR SpiceOrder 22 +PIN -240 0 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 23 +PIN -240 96 LEFT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 24 +PIN 224 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 25 +PIN -240 -96 LEFT 8 +PINATTR PinName Ramp2 +PINATTR SpiceOrder 26 +PIN -96 -624 TOP 8 +PINATTR PinName Pvin2 +PINATTR SpiceOrder 27 +PIN 224 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 28 +PIN 224 -288 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 29 +PIN -240 -576 LEFT 8 +PINATTR PinName Pvin1 +PINATTR SpiceOrder 30 diff --git a/spice/copy/sym/PowerProducts/ADP5056.asy b/spice/copy/sym/PowerProducts/ADP5056.asy new file mode 100755 index 0000000..3657b5d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5056.asy @@ -0,0 +1,101 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 640 -240 -624 +TEXT 0 1 Center 2 ADI +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value ADP5056 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5056.sub +SYMATTR Value2 ADP5056 +SYMATTR Description Integrated Power Solution with Triple Buck Regulators +PIN 224 480 RIGHT 8 +PINATTR PinName Cfg1 +PINATTR SpiceOrder 1 +PIN 224 576 RIGHT 8 +PINATTR PinName Cfg2 +PINATTR SpiceOrder 2 +PIN -240 -384 LEFT 8 +PINATTR PinName Ramp1 +PINATTR SpiceOrder 3 +PIN 224 -192 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN -240 -192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 5 +PIN -240 576 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 6 +PIN -240 -288 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 7 +PIN 80 640 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN -240 -480 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 9 +PIN 224 -576 RIGHT 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 10 +PIN -240 480 LEFT 8 +PINATTR PinName Mode/Sync +PINATTR SpiceOrder 11 +PIN 224 -384 RIGHT 8 +PINATTR PinName Bst1 +PINATTR SpiceOrder 12 +PIN 224 192 RIGHT 8 +PINATTR PinName Bst3 +PINATTR SpiceOrder 13 +PIN -96 640 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 14 +PIN 224 288 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 15 +PIN 80 -624 TOP 8 +PINATTR PinName Pvin3 +PINATTR SpiceOrder 16 +PIN 224 -96 RIGHT 8 +PINATTR PinName Bst2 +PINATTR SpiceOrder 17 +PIN -240 288 LEFT 8 +PINATTR PinName EN3 +PINATTR SpiceOrder 18 +PIN -240 192 LEFT 8 +PINATTR PinName Ramp3 +PINATTR SpiceOrder 19 +PIN 224 384 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 20 +PIN -240 384 LEFT 8 +PINATTR PinName Comp3 +PINATTR SpiceOrder 21 +PIN 224 -480 RIGHT 8 +PINATTR PinName Pwrgd +PINATTR SpiceOrder 22 +PIN -240 0 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 23 +PIN -240 96 LEFT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 24 +PIN 224 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 25 +PIN -240 -96 LEFT 8 +PINATTR PinName Ramp2 +PINATTR SpiceOrder 26 +PIN -96 -624 TOP 8 +PINATTR PinName Pvin2 +PINATTR SpiceOrder 27 +PIN 224 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 28 +PIN 224 -288 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 29 +PIN -240 -576 LEFT 8 +PINATTR PinName Pvin1 +PINATTR SpiceOrder 30 diff --git a/spice/copy/sym/PowerProducts/ADP5070.asy b/spice/copy/sym/PowerProducts/ADP5070.asy new file mode 100755 index 0000000..b570a45 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5070.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -496 144 496 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -280 Center 2 +WINDOW 3 0 279 Center 2 +SYMATTR Value ADP5070 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5070_1.sub +SYMATTR Value2 ADP5070_1 CL1=1.1 CS1=151.83m Ron1=175m CL2=0.6 CS2=151.83m Ron2=350m IQ=3.5m SS=1 CL_INBK1=1 CL_INBK2=2 +SYMATTR Description 1A/0.6A, DC to DC Switching Regulator with Independent Positive and Negative Outputs +PIN -144 336 LEFT 8 +PINATTR PinName Sync/Freq +PINATTR SpiceOrder 1 +PIN -144 -112 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 2 +PIN 144 448 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 3 +PIN -144 -224 LEFT 8 +PINATTR PinName PVinSys +PINATTR SpiceOrder 4 +PIN 144 -336 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 5 +PIN -144 -448 LEFT 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 6 +PIN 144 -112 RIGHT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 7 +PIN 144 -224 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 8 +PIN 144 112 RIGHT 8 +PINATTR PinName Slew +PINATTR SpiceOrder 9 +PIN 0 496 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN -144 112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 11 +PIN -144 224 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 144 224 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 13 +PIN -144 448 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 14 +PIN 144 -448 RIGHT 8 +PINATTR PinName INBK +PINATTR SpiceOrder 15 +PIN -144 0 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 16 +PIN -144 -336 LEFT 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 17 +PIN 144 336 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 18 +PIN 144 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/ADP5071.asy b/spice/copy/sym/PowerProducts/ADP5071.asy new file mode 100755 index 0000000..f9366a0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5071.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -496 144 496 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -280 Center 2 +WINDOW 3 -1 279 Center 2 +SYMATTR Value ADP5071 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5070_1.sub +SYMATTR Value2 ADP5070_1 CL1=2.2 CS1=80m Ron1=175m CL2=1.32 CS2=80m Ron2=350m IQ=3.5m SS=1 CL_INBK1=2 CL_INBK2=3 +SYMATTR Description 2A/1.2A, DC to DC Switching Regulator with Independent Positive and Negative Outputs +PIN -144 336 LEFT 8 +PINATTR PinName Sync/Freq +PINATTR SpiceOrder 1 +PIN -144 -112 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 2 +PIN 144 448 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 3 +PIN -144 -224 LEFT 8 +PINATTR PinName PVinSys +PINATTR SpiceOrder 4 +PIN 144 -336 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 5 +PIN -144 -448 LEFT 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 6 +PIN 144 -112 RIGHT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 7 +PIN 144 -224 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 8 +PIN 144 112 RIGHT 8 +PINATTR PinName Slew +PINATTR SpiceOrder 9 +PIN 0 496 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN -144 112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 11 +PIN -144 224 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 144 224 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 13 +PIN -144 448 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 14 +PIN 144 -448 RIGHT 8 +PINATTR PinName INBK +PINATTR SpiceOrder 15 +PIN -144 0 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 16 +PIN -144 -336 LEFT 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 17 +PIN 144 336 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 18 +PIN 144 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/ADP5072.asy b/spice/copy/sym/PowerProducts/ADP5072.asy new file mode 100755 index 0000000..89cee3f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5072.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -448 144 432 +TEXT 1 -9 Center 2 ADI +WINDOW 0 0 -231 Center 2 +WINDOW 3 0 215 Center 2 +SYMATTR Value ADP5072 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5072.sub +SYMATTR Value2 ADP5072 CL1=1.1 CS1=151.83m Ron1=175m CL2=0.6 CS2=151.83m Ron2=350m SS=1 +SYMATTR Description 1A/0.6A, DC to DC Switching Regulator with Independent Positive and Negative Outputs +PIN -144 160 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -144 -176 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 2 +PIN 144 384 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 3 +PIN -144 -288 LEFT 8 +PINATTR PinName AVin +PINATTR SpiceOrder 4 +PIN 144 -400 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 5 +PIN 144 -176 RIGHT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 7 +PIN 144 -288 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName Slew +PINATTR SpiceOrder 9 +PIN -144 384 LEFT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN -144 48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 144 160 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 13 +PIN -144 272 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 14 +PIN -144 -64 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 16 +PIN -144 -400 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 17 +PIN 144 272 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 18 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/ADP5073.asy b/spice/copy/sym/PowerProducts/ADP5073.asy new file mode 100755 index 0000000..87d9002 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5073.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -320 144 336 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value ADP5073 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5073_4.sub +SYMATTR Value2 ADP5073_4 CL=1.375 CS=151.83m Ron=220m IQ=2.5m +SYMATTR Description 1.2A, DC to DC Inverting Regulator +PIN -144 288 LEFT 8 +PINATTR PinName Sync/Freq +PINATTR SpiceOrder 1 +PIN -144 -160 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -144 -272 LEFT 8 +PINATTR PinName AVin +PINATTR SpiceOrder 4 +PIN 144 -272 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -320 TOP 8 +PINATTR PinName PVin +PINATTR SpiceOrder 6 +PIN -144 -48 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -144 64 LEFT 8 +PINATTR PinName Slew +PINATTR SpiceOrder 9 +PIN 144 -160 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 144 176 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 11 +PIN -144 176 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 144 288 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/ADP5074.asy b/spice/copy/sym/PowerProducts/ADP5074.asy new file mode 100755 index 0000000..53c77ad --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5074.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -320 144 336 +TEXT 0 9 Center 2 ADI +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value ADP5074 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5073_4.sub +SYMATTR Value2 ADP5073_4 CL=2.75 CS=80m Ron=220m IQ=2.5m +SYMATTR Description 2.4A, DC to DC Inverting Regulator +PIN -144 288 LEFT 8 +PINATTR PinName Sync/Freq +PINATTR SpiceOrder 1 +PIN -144 -160 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -144 -272 LEFT 8 +PINATTR PinName AVin +PINATTR SpiceOrder 4 +PIN 144 -272 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -320 TOP 8 +PINATTR PinName PVin +PINATTR SpiceOrder 6 +PIN -144 -48 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -144 64 LEFT 8 +PINATTR PinName Slew +PINATTR SpiceOrder 9 +PIN 144 -160 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 144 176 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 11 +PIN -144 176 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 144 288 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/ADP5075.asy b/spice/copy/sym/PowerProducts/ADP5075.asy new file mode 100755 index 0000000..2481f37 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5075.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -320 144 336 +TEXT 0 8 Center 2 ADI +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 119 Center 2 +SYMATTR Value ADP5075 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5075.sub +SYMATTR Value2 ADP5075 CL=880m CS=153.85m Ron=330m IQ=1.8m +SYMATTR Description 800mA DC to DC Inverting Regulator +PIN -144 288 LEFT 8 +PINATTR PinName Sync/Freq +PINATTR SpiceOrder 1 +PIN -144 -160 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN 144 176 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -144 -272 LEFT 8 +PINATTR PinName AVin +PINATTR SpiceOrder 4 +PIN 144 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 144 -272 RIGHT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 6 +PIN -144 -48 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -144 64 LEFT 8 +PINATTR PinName Slew +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 144 288 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 11 +PIN -144 176 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/ADP5138-1.asy b/spice/copy/sym/PowerProducts/ADP5138-1.asy new file mode 100755 index 0000000..55e7b2c --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5138-1.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 544 -240 -624 +TEXT 0 -48 Center 2 ADI +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value ADP5138-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5138-1.sub +SYMATTR Value2 ADP5138-1 +SYMATTR Description Quad, 1A, 5.5V, Synchronous Step-Down Regulators with One RF LDO, Fixed Output Version \n\nNote: Enable delay time in the model is reduced toTssD/3 +PIN -240 -480 LEFT 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 1 +PIN 224 -480 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 2 +PIN -144 544 BOTTOM 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 3 +PIN 224 464 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 224 -288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 5 +PIN -240 -288 LEFT 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 6 +PIN 224 -192 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 7 +PIN -240 -192 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 8 +PIN 224 -560 RIGHT 8 +PINATTR PinName POR +PINATTR SpiceOrder 9 +PIN -240 288 LEFT 8 +PINATTR PinName PVin5 +PINATTR SpiceOrder 10 +PIN 224 384 RIGHT 8 +PINATTR PinName FB5 +PINATTR SpiceOrder 11 +PIN 224 288 RIGHT 8 +PINATTR PinName Vout5 +PINATTR SpiceOrder 12 +PIN -240 384 LEFT 8 +PINATTR PinName EN5 +PINATTR SpiceOrder 13 +PIN -240 0 LEFT 8 +PINATTR PinName EN3 +PINATTR SpiceOrder 14 +PIN 224 0 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 15 +PIN -240 -96 LEFT 8 +PINATTR PinName PVin3 +PINATTR SpiceOrder 16 +PIN 224 -96 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 17 +PIN 48 544 BOTTOM 8 +PINATTR PinName PGND3 +PINATTR SpiceOrder 18 +PIN 144 544 BOTTOM 8 +PINATTR PinName PGND4 +PINATTR SpiceOrder 19 +PIN 224 96 RIGHT 8 +PINATTR PinName SW4 +PINATTR SpiceOrder 20 +PIN -240 96 LEFT 8 +PINATTR PinName PVin4 +PINATTR SpiceOrder 21 +PIN 224 192 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 22 +PIN -240 192 LEFT 8 +PINATTR PinName EN4 +PINATTR SpiceOrder 23 +PIN -48 544 BOTTOM 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 24 +PIN -240 464 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 25 +PIN -240 -560 LEFT 8 +PINATTR PinName AVin +PINATTR SpiceOrder 26 +PIN -240 -384 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 27 +PIN 224 -384 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/ADP5138-2.asy b/spice/copy/sym/PowerProducts/ADP5138-2.asy new file mode 100755 index 0000000..a5edadd --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5138-2.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 544 -240 -624 +TEXT 0 -48 Center 2 ADI +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value ADP5138-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5138-2.sub +SYMATTR Value2 ADP5138-2 +SYMATTR Description Quad, 1A, 5.5V, Synchronous Step-Down Regulators with One RF LDO\n\nNote: Enable delay time in the model is reduced toTssD/3 +PIN -240 -480 LEFT 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 1 +PIN 224 -480 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 2 +PIN -144 544 BOTTOM 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 3 +PIN 224 464 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 224 -288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 5 +PIN -240 -288 LEFT 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 6 +PIN 224 -192 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 7 +PIN -240 -192 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 8 +PIN 224 -560 RIGHT 8 +PINATTR PinName POR +PINATTR SpiceOrder 9 +PIN -240 288 LEFT 8 +PINATTR PinName PVin5 +PINATTR SpiceOrder 10 +PIN 224 384 RIGHT 8 +PINATTR PinName FB5 +PINATTR SpiceOrder 11 +PIN 224 288 RIGHT 8 +PINATTR PinName Vout5 +PINATTR SpiceOrder 12 +PIN -240 384 LEFT 8 +PINATTR PinName EN5 +PINATTR SpiceOrder 13 +PIN -240 0 LEFT 8 +PINATTR PinName EN3 +PINATTR SpiceOrder 14 +PIN 224 0 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 15 +PIN -240 -96 LEFT 8 +PINATTR PinName PVin3 +PINATTR SpiceOrder 16 +PIN 224 -96 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 17 +PIN 48 544 BOTTOM 8 +PINATTR PinName PGND3 +PINATTR SpiceOrder 18 +PIN 144 544 BOTTOM 8 +PINATTR PinName PGND4 +PINATTR SpiceOrder 19 +PIN 224 96 RIGHT 8 +PINATTR PinName SW4 +PINATTR SpiceOrder 20 +PIN -240 96 LEFT 8 +PINATTR PinName PVin4 +PINATTR SpiceOrder 21 +PIN 224 192 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 22 +PIN -240 192 LEFT 8 +PINATTR PinName EN4 +PINATTR SpiceOrder 23 +PIN -48 544 BOTTOM 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 24 +PIN -240 464 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 25 +PIN -240 -560 LEFT 8 +PINATTR PinName AVin +PINATTR SpiceOrder 26 +PIN -240 -384 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 27 +PIN 224 -384 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/ADP5300-1.asy b/spice/copy/sym/PowerProducts/ADP5300-1.asy new file mode 100755 index 0000000..05d4507 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5300-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 71 Center 2 +SYMATTR Value ADP5300-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5300-1.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 with Output Discharge +SYMATTR Value2 ADP5300-1 OVO=0 OD=0 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN 128 112 RIGHT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VoutOK +PINATTR SpiceOrder 6 +PIN -48 176 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 48 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN -128 32 LEFT 8 +PINATTR PinName Stop +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP5300-2.asy b/spice/copy/sym/PowerProducts/ADP5300-2.asy new file mode 100755 index 0000000..92756c8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5300-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value ADP5300-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5300-1.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 without Output Discharge +SYMATTR Value2 ADP5300-1 OVO=0 OD=1 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN 128 112 RIGHT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VoutOK +PINATTR SpiceOrder 6 +PIN -48 176 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 48 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN -128 32 LEFT 8 +PINATTR PinName Stop +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP5300-3.asy b/spice/copy/sym/PowerProducts/ADP5300-3.asy new file mode 100755 index 0000000..0d637de --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5300-3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value ADP5300-3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5300-1.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option1 without Output Discharge +SYMATTR Value2 ADP5300-1 OVO=1 OD=1 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN 128 112 RIGHT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VoutOK +PINATTR SpiceOrder 6 +PIN -48 176 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 48 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN -128 32 LEFT 8 +PINATTR PinName Stop +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP5300-4.asy b/spice/copy/sym/PowerProducts/ADP5300-4.asy new file mode 100755 index 0000000..93f0004 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5300-4.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value ADP5300-4 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5300-4.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\n3.6V Fixed Output without Output Discharge, 2.8ms Soft Start Timer +SYMATTR Value2 ADP5300-4 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN 128 112 RIGHT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VoutOK +PINATTR SpiceOrder 6 +PIN -48 176 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 48 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN -128 32 LEFT 8 +PINATTR PinName Stop +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP5301-1.asy b/spice/copy/sym/PowerProducts/ADP5301-1.asy new file mode 100755 index 0000000..01f3fd1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5301-1.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value ADP5301-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5301.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 with Output Discharge +SYMATTR Value2 ADP5301 OVO=0 OD=0 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN -128 32 LEFT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VoutOK +PINATTR SpiceOrder 6 +PIN 128 112 RIGHT 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP5301-2.asy b/spice/copy/sym/PowerProducts/ADP5301-2.asy new file mode 100755 index 0000000..e34de8f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5301-2.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 71 Center 2 +SYMATTR Value ADP5301-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5301.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 without Output Discharge +SYMATTR Value2 ADP5301 OVO=0 OD=1 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN -128 32 LEFT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VoutOK +PINATTR SpiceOrder 6 +PIN 128 112 RIGHT 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP5301-3.asy b/spice/copy/sym/PowerProducts/ADP5301-3.asy new file mode 100755 index 0000000..85b70fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5301-3.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value ADP5301-3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5301.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 without Output Discharge +SYMATTR Value2 ADP5301 OVO=1 OD=1 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN -128 32 LEFT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VoutOK +PINATTR SpiceOrder 6 +PIN 128 112 RIGHT 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP5302-1.asy b/spice/copy/sym/PowerProducts/ADP5302-1.asy new file mode 100755 index 0000000..0e3463d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5302-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 71 Center 2 +SYMATTR Value ADP5302-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5302.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 with Output Discharge +SYMATTR Value2 ADP5302 OD=0 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN 128 112 RIGHT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VoutOK +PINATTR SpiceOrder 6 +PIN -48 176 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 48 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN -128 32 LEFT 8 +PINATTR PinName Stop +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP5302-2.asy b/spice/copy/sym/PowerProducts/ADP5302-2.asy new file mode 100755 index 0000000..e6c2983 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5302-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 -1 72 Center 2 +SYMATTR Value ADP5302-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5302.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 without Output Discharge +SYMATTR Value2 ADP5302 OD=1 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN 128 112 RIGHT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VoutOK +PINATTR SpiceOrder 6 +PIN -48 176 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 48 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN -128 32 LEFT 8 +PINATTR PinName Stop +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP5303-1.asy b/spice/copy/sym/PowerProducts/ADP5303-1.asy new file mode 100755 index 0000000..1681202 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5303-1.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value ADP5303-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5303-1.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 with Output Discharge +SYMATTR Value2 ADP5303-1 OD=0 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN -128 32 LEFT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VinOK +PINATTR SpiceOrder 6 +PIN 128 112 RIGHT 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP5303-2.asy b/spice/copy/sym/PowerProducts/ADP5303-2.asy new file mode 100755 index 0000000..8fe4a2f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5303-2.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value ADP5303-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5303-1.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 without Output Discharge +SYMATTR Value2 ADP5303-1 OD=1 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN -128 32 LEFT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VinOK +PINATTR SpiceOrder 6 +PIN 128 112 RIGHT 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP5303-3.asy b/spice/copy/sym/PowerProducts/ADP5303-3.asy new file mode 100755 index 0000000..ecf82ec --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5303-3.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value ADP5303-3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5303-3.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\nOutput Voltage Option0 with Output Discharge, 2.8ms Soft Start Timer +SYMATTR Value2 ADP5303-3 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 3 +PIN -128 32 LEFT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VinOK +PINATTR SpiceOrder 6 +PIN 128 112 RIGHT 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP5304-1.asy b/spice/copy/sym/PowerProducts/ADP5304-1.asy new file mode 100755 index 0000000..9cee237 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5304-1.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 71 Center 2 +SYMATTR Value ADP5304-1 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5304-1.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\n3V VINOK Threshold +SYMATTR Value2 ADP5304-1 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 3 +PIN -128 32 LEFT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VinOK +PINATTR SpiceOrder 6 +PIN 128 112 RIGHT 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP5304-2.asy b/spice/copy/sym/PowerProducts/ADP5304-2.asy new file mode 100755 index 0000000..c53be75 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP5304-2.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 71 Center 2 +SYMATTR Value ADP5304-2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP5304-2.sub +SYMATTR Description 50mA/500mA High Efficiency Ultralow Power Step-Down Regulator\n\n4V VINOK Threshold +SYMATTR Value2 ADP5304-2 +PIN -128 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN -128 -128 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 3 +PIN -128 32 LEFT 8 +PINATTR PinName VID +PINATTR SpiceOrder 4 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 -128 RIGHT 8 +PINATTR PinName VinOK +PINATTR SpiceOrder 6 +PIN 128 112 RIGHT 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 8 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/ADP7102-1.5.asy b/spice/copy/sym/PowerProducts/ADP7102-1.5.asy new file mode 100755 index 0000000..8fdcb43 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7102-1.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7102-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7102 Vref=1.5 +SYMATTR Description 20V, 300mA, Low Noise, CMOS LDO, 1.5V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7102-1.8.asy b/spice/copy/sym/PowerProducts/ADP7102-1.8.asy new file mode 100755 index 0000000..329e15d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7102-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7102-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7102 Vref=1.8 +SYMATTR Description 20V, 300mA, Low Noise, CMOS LDO, 1.8V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7102-2.5.asy b/spice/copy/sym/PowerProducts/ADP7102-2.5.asy new file mode 100755 index 0000000..e30a1f2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7102-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7102-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7102 Vref=2.5 +SYMATTR Description 20V, 300mA, Low Noise, CMOS LDO, 2.5V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7102-3.0.asy b/spice/copy/sym/PowerProducts/ADP7102-3.0.asy new file mode 100755 index 0000000..7f7443a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7102-3.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7102-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7102 Vref=3 +SYMATTR Description 20V, 300mA, Low Noise, CMOS LDO, 3V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7102-3.3.asy b/spice/copy/sym/PowerProducts/ADP7102-3.3.asy new file mode 100755 index 0000000..259dbf1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7102-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7102-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7102 Vref=3.3 +SYMATTR Description 20V, 300mA, Low Noise, CMOS LDO, 3.3V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7102-5.0.asy b/spice/copy/sym/PowerProducts/ADP7102-5.0.asy new file mode 100755 index 0000000..8875214 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7102-5.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7102-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7102 Vref=5 +SYMATTR Description 20V, 300mA, Low Noise, CMOS LDOt, 5V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7102-9.0.asy b/spice/copy/sym/PowerProducts/ADP7102-9.0.asy new file mode 100755 index 0000000..9ad30d3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7102-9.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7102-9.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7102 Vref=9 +SYMATTR Description 20V, 300mA, Low Noise, CMOS LDO, 9V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7102.asy b/spice/copy/sym/PowerProducts/ADP7102.asy new file mode 100755 index 0000000..2a69bb4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7102.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7102 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7102 Vref=1.22 +SYMATTR Description 20V, 300mA, Low Noise, CMOS LDO, Adjustable Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7104-1.5.asy b/spice/copy/sym/PowerProducts/ADP7104-1.5.asy new file mode 100755 index 0000000..0e8145e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7104-1.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7104-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7104 Vref=1.5 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO, 1.5V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7104-1.8.asy b/spice/copy/sym/PowerProducts/ADP7104-1.8.asy new file mode 100755 index 0000000..f5f64ca --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7104-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7104-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7104 Vref=1.8 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO, 1.8V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7104-2.5.asy b/spice/copy/sym/PowerProducts/ADP7104-2.5.asy new file mode 100755 index 0000000..ccecd39 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7104-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7104-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7104 Vref=2.5 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO, 2.5V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7104-3.0.asy b/spice/copy/sym/PowerProducts/ADP7104-3.0.asy new file mode 100755 index 0000000..b5ca380 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7104-3.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7104-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7104 Vref=3 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO, 3V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP7104-3.3.asy b/spice/copy/sym/PowerProducts/ADP7104-3.3.asy new file mode 100755 index 0000000..e628673 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7104-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7104-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7104 Vref=3.3 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO, 3.3V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP7104-5.0.asy b/spice/copy/sym/PowerProducts/ADP7104-5.0.asy new file mode 100755 index 0000000..804ea6e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7104-5.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7104-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7104 Vref=5 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDOt, 5V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7104-9.0.asy b/spice/copy/sym/PowerProducts/ADP7104-9.0.asy new file mode 100755 index 0000000..c4e3991 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7104-9.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7104-9.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7104 Vref=9 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO, 9V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7104.asy b/spice/copy/sym/PowerProducts/ADP7104.asy new file mode 100755 index 0000000..ac83b07 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7104.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7104 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7104 Vref=1.22 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO, Adjustable Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN -128 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/ADP7105-1.8.asy b/spice/copy/sym/PowerProducts/ADP7105-1.8.asy new file mode 100755 index 0000000..7b6f5e3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7105-1.8.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7105-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7105 Vref=1.8 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO with Soft Start, 1.8V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/ADP7105-3.3.asy b/spice/copy/sym/PowerProducts/ADP7105-3.3.asy new file mode 100755 index 0000000..cf93cf6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7105-3.3.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7105-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7105 Vref=3.3 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO with Soft Start, 3.3V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/ADP7105-5.0.asy b/spice/copy/sym/PowerProducts/ADP7105-5.0.asy new file mode 100755 index 0000000..6740111 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7105-5.0.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7105-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7105 Vref=5 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO with Soft Start, 5V Fixed Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/ADP7105.asy b/spice/copy/sym/PowerProducts/ADP7105.asy new file mode 100755 index 0000000..88b61ae --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7105.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7105 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7105 Vref=1.22 +SYMATTR Description 20V, 500mA, Low Noise, CMOS LDO with Soft Start, Adjustable Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/ADP7112-1.8.asy b/spice/copy/sym/PowerProducts/ADP7112-1.8.asy new file mode 100755 index 0000000..3485ea4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7112-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7112-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=1.8 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Fixed 1.8V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7112-2.5.asy b/spice/copy/sym/PowerProducts/ADP7112-2.5.asy new file mode 100755 index 0000000..34f8578 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7112-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7112-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=2.5 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Fixed 2.5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7112-3.3.asy b/spice/copy/sym/PowerProducts/ADP7112-3.3.asy new file mode 100755 index 0000000..627eef2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7112-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7112-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=3.3 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Fixed 3.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7112-5.0.asy b/spice/copy/sym/PowerProducts/ADP7112-5.0.asy new file mode 100755 index 0000000..f010044 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7112-5.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7112-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=5 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Fixed 5.0V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7112.asy b/spice/copy/sym/PowerProducts/ADP7112.asy new file mode 100755 index 0000000..d523ead --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7112.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7112 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=1.2 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Adjustable Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7118-1.8.asy b/spice/copy/sym/PowerProducts/ADP7118-1.8.asy new file mode 100755 index 0000000..511dc76 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7118-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7118-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=1.8 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Fixed 1.8V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7118-2.5.asy b/spice/copy/sym/PowerProducts/ADP7118-2.5.asy new file mode 100755 index 0000000..b8ec43a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7118-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7118-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=2.5 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Fixed 2.5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7118-3.3.asy b/spice/copy/sym/PowerProducts/ADP7118-3.3.asy new file mode 100755 index 0000000..a928a1e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7118-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7118-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=3.3 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Fixed 3.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7118-4.5.asy b/spice/copy/sym/PowerProducts/ADP7118-4.5.asy new file mode 100755 index 0000000..089479b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7118-4.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7118-4.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=4.5 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Fixed 4.5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7118-5.0.asy b/spice/copy/sym/PowerProducts/ADP7118-5.0.asy new file mode 100755 index 0000000..f1183ca --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7118-5.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7118-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=5 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Fixed 5.0V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7118.asy b/spice/copy/sym/PowerProducts/ADP7118.asy new file mode 100755 index 0000000..2499db0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7118.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7118 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=1.2 +SYMATTR Description 20V, 200mA, Low Noise, CMOS LDO, Adjustable Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7142-1.8.asy b/spice/copy/sym/PowerProducts/ADP7142-1.8.asy new file mode 100755 index 0000000..9537b57 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7142-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7142-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=1.8 +SYMATTR Description 40V, 200mA, Low Noise, CMOS LDO, Fixed 1.8V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7142-2.5.asy b/spice/copy/sym/PowerProducts/ADP7142-2.5.asy new file mode 100755 index 0000000..d118f0a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7142-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7142-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=2.5 +SYMATTR Description 40V, 200mA, Low Noise, CMOS LDO, Fixed 2.5V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7142-3.3.asy b/spice/copy/sym/PowerProducts/ADP7142-3.3.asy new file mode 100755 index 0000000..3b0b44e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7142-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7142-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=3.3 +SYMATTR Description 40V, 200mA, Low Noise, CMOS LDO, Fixed 3.3V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7142-5.0.asy b/spice/copy/sym/PowerProducts/ADP7142-5.0.asy new file mode 100755 index 0000000..35787b7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7142-5.0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7142-5.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=5 +SYMATTR Description 40V, 200mA, Low Noise, CMOS LDO, Fixed 5.0V Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7142.asy b/spice/copy/sym/PowerProducts/ADP7142.asy new file mode 100755 index 0000000..5758739 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7142.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 160 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value ADP7142 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7102.lib +SYMATTR Value2 ADP7118 Vref=1.2 +SYMATTR Description 40V, 200mA, Low Noise, CMOS LDO, Adjustable Output +PIN -128 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADP7156-1.2.asy b/spice/copy/sym/PowerProducts/ADP7156-1.2.asy new file mode 100755 index 0000000..e004ba4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7156-1.2.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7156-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=2.111 Vref=1.216 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7156-1.8.asy b/spice/copy/sym/PowerProducts/ADP7156-1.8.asy new file mode 100755 index 0000000..fe6ba03 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7156-1.8.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 176 -160 -208 +TEXT 0 -32 Center 2 ADI +WINDOW 3 0 64 Center 2 +WINDOW 0 0 -128 Center 2 +SYMATTR Value ADP7156-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=2.111 Vref=1.816 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -176 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -80 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 16 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 112 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 16 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -176 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7156-2.0.asy b/spice/copy/sym/PowerProducts/ADP7156-2.0.asy new file mode 100755 index 0000000..03d8b07 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7156-2.0.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7156-2.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=2.611 Vref=2.016 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7156-2.5.asy b/spice/copy/sym/PowerProducts/ADP7156-2.5.asy new file mode 100755 index 0000000..8c34f39 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7156-2.5.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7156-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=3.211 Vref=2.516 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7156-2.8.asy b/spice/copy/sym/PowerProducts/ADP7156-2.8.asy new file mode 100755 index 0000000..66c8ee2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7156-2.8.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7156-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=3.211 Vref=2.816 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7156-3.0.asy b/spice/copy/sym/PowerProducts/ADP7156-3.0.asy new file mode 100755 index 0000000..7939e7e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7156-3.0.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7156-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=3.611 Vref=3.016 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7156-3.3.asy b/spice/copy/sym/PowerProducts/ADP7156-3.3.asy new file mode 100755 index 0000000..8d734fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7156-3.3.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7156-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=3.611 Vref=3.316 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7157-01.asy b/spice/copy/sym/PowerProducts/ADP7157-01.asy new file mode 100755 index 0000000..6ca3672 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7157-01.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7157-01 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=2.111 Vref=1.216 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7157-02.asy b/spice/copy/sym/PowerProducts/ADP7157-02.asy new file mode 100755 index 0000000..2596cf4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7157-02.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7157-02 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=2.611 Vref=1.216 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7157-03.asy b/spice/copy/sym/PowerProducts/ADP7157-03.asy new file mode 100755 index 0000000..bcf9e3f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7157-03.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7157-03 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=3.211 Vref=1.216 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7157-04.asy b/spice/copy/sym/PowerProducts/ADP7157-04.asy new file mode 100755 index 0000000..1e5931f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7157-04.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7157-04 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7156-1.2.sub +SYMATTR Value2 ADP7156_7 Vreg=3.611 Vref=1.216 +SYMATTR Description 1.2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7158-1.2.asy b/spice/copy/sym/PowerProducts/ADP7158-1.2.asy new file mode 100755 index 0000000..897c93a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7158-1.2.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7158-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=2.111 Vref=1.216 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7158-1.8.asy b/spice/copy/sym/PowerProducts/ADP7158-1.8.asy new file mode 100755 index 0000000..9757f51 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7158-1.8.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 176 -160 -208 +TEXT 0 -32 Center 2 ADI +WINDOW 3 0 64 Center 2 +WINDOW 0 0 -128 Center 2 +SYMATTR Value ADP7158-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=2.111 Vref=1.816 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -176 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -80 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 16 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 112 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 16 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 112 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -176 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7158-2.0.asy b/spice/copy/sym/PowerProducts/ADP7158-2.0.asy new file mode 100755 index 0000000..46903b1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7158-2.0.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7158-2.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=2.611 Vref=2.016 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7158-2.5.asy b/spice/copy/sym/PowerProducts/ADP7158-2.5.asy new file mode 100755 index 0000000..7b1205e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7158-2.5.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7158-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=3.211 Vref=2.516 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7158-2.8.asy b/spice/copy/sym/PowerProducts/ADP7158-2.8.asy new file mode 100755 index 0000000..0814855 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7158-2.8.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7158-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=3.211 Vref=2.816 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7158-3.0.asy b/spice/copy/sym/PowerProducts/ADP7158-3.0.asy new file mode 100755 index 0000000..d4b8ccc --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7158-3.0.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7158-3.0 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=3.611 Vref=3.016 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7158-3.3.asy b/spice/copy/sym/PowerProducts/ADP7158-3.3.asy new file mode 100755 index 0000000..dc5af3a --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7158-3.3.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7158-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=3.611 Vref=3.316 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7159-01.asy b/spice/copy/sym/PowerProducts/ADP7159-01.asy new file mode 100755 index 0000000..ff94bea --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7159-01.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7159-01 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=2.111 Vref=1.216 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7159-02.asy b/spice/copy/sym/PowerProducts/ADP7159-02.asy new file mode 100755 index 0000000..494236e --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7159-02.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7159-02 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=2.611 Vref=1.216 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7159-03.asy b/spice/copy/sym/PowerProducts/ADP7159-03.asy new file mode 100755 index 0000000..8b1b170 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7159-03.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7159-03 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=3.211 Vref=1.216 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7159-04.asy b/spice/copy/sym/PowerProducts/ADP7159-04.asy new file mode 100755 index 0000000..6bf9ec3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADP7159-04.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -176 +TEXT 0 0 Center 2 ADI +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value ADP7159-04 +SYMATTR Prefix X +SYMATTR SpiceModel ADP7158_9.sub +SYMATTR Value2 ADP7158_9 Vreg=3.611 Vref=1.216 +SYMATTR Description 2A, Ultralow Noise, High PSRR, RF Linear Regulator +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout_Sense +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Byp +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Ref_Sense +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/ADP7182-1.2.asy b/spice/copy/sym/PowerProducts/ADP7182-1.2.asy new file mode 100755 index 0000000..c5d5645 Binary files /dev/null and b/spice/copy/sym/PowerProducts/ADP7182-1.2.asy differ diff --git a/spice/copy/sym/PowerProducts/ADP7182-1.5.asy b/spice/copy/sym/PowerProducts/ADP7182-1.5.asy new file mode 100755 index 0000000..9aa7866 Binary files /dev/null and b/spice/copy/sym/PowerProducts/ADP7182-1.5.asy differ diff --git a/spice/copy/sym/PowerProducts/ADP7182-1.8.asy b/spice/copy/sym/PowerProducts/ADP7182-1.8.asy new file mode 100755 index 0000000..1442408 Binary files /dev/null and b/spice/copy/sym/PowerProducts/ADP7182-1.8.asy differ diff --git a/spice/copy/sym/PowerProducts/ADP7182-2.5.asy b/spice/copy/sym/PowerProducts/ADP7182-2.5.asy new file mode 100755 index 0000000..5b12f8f Binary files /dev/null and b/spice/copy/sym/PowerProducts/ADP7182-2.5.asy differ diff --git a/spice/copy/sym/PowerProducts/ADP7182-3.0.asy b/spice/copy/sym/PowerProducts/ADP7182-3.0.asy new file mode 100755 index 0000000..f3e4b07 Binary files /dev/null and b/spice/copy/sym/PowerProducts/ADP7182-3.0.asy differ diff --git a/spice/copy/sym/PowerProducts/ADP7182-5.0.asy b/spice/copy/sym/PowerProducts/ADP7182-5.0.asy new file mode 100755 index 0000000..2f7c55c Binary files /dev/null and b/spice/copy/sym/PowerProducts/ADP7182-5.0.asy differ diff --git a/spice/copy/sym/PowerProducts/ADP7182.asy b/spice/copy/sym/PowerProducts/ADP7182.asy new file mode 100755 index 0000000..cfc6f8b Binary files /dev/null and b/spice/copy/sym/PowerProducts/ADP7182.asy differ diff --git a/spice/copy/sym/PowerProducts/ADuM4120-1A.asy b/spice/copy/sym/PowerProducts/ADuM4120-1A.asy new file mode 100755 index 0000000..3700fde --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4120-1A.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal -48 0 -32 0 +LINE Normal 48 0 32 0 +RECTANGLE Normal 128 112 -128 -112 +TEXT 0 -56 Center 2 ADI +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value ADuM4120-1A +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4120xx.sub +SYMATTR Description Isolated, Precision Gate Driver with 2A Output +SYMATTR Value2 ADuM4120xx Glitch=0 Vrun2=4.3 +PIN -80 -112 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -80 112 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 80 112 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 80 -112 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADuM4120-1B.asy b/spice/copy/sym/PowerProducts/ADuM4120-1B.asy new file mode 100755 index 0000000..dd969f5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4120-1B.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal -48 0 -32 0 +LINE Normal 48 0 32 0 +RECTANGLE Normal 128 112 -128 -112 +TEXT 0 -56 Center 2 ADI +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value ADuM4120-1B +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4120xx.sub +SYMATTR Description Isolated, Precision Gate Driver with 2A Output +SYMATTR Value2 ADuM4120xx Glitch=0 Vrun2=7.2 +PIN -80 -112 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -80 112 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 80 112 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 80 -112 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADuM4120-1C.asy b/spice/copy/sym/PowerProducts/ADuM4120-1C.asy new file mode 100755 index 0000000..c9cbcd3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4120-1C.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal -48 0 -32 0 +LINE Normal 48 0 32 0 +RECTANGLE Normal 128 112 -128 -112 +TEXT 0 -56 Center 2 ADI +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value ADuM4120-1C +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4120xx.sub +SYMATTR Description Isolated, Precision Gate Driver with 2A Output +SYMATTR Value2 ADuM4120xx Glitch=0 Vrun2=11.2 +PIN -80 -112 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -80 112 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 80 112 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 80 -112 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADuM4120A.asy b/spice/copy/sym/PowerProducts/ADuM4120A.asy new file mode 100755 index 0000000..bc0fa36 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4120A.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal -48 0 -32 0 +LINE Normal 48 0 32 0 +RECTANGLE Normal 128 112 -128 -112 +TEXT 0 -56 Center 2 ADI +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value ADuM4120A +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4120xx.sub +SYMATTR Description Isolated, Precision Gate Driver with 2A Output +SYMATTR Value2 ADuM4120xx Glitch=1 Vrun2=4.3 +PIN -80 -112 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -80 112 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 80 112 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 80 -112 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADuM4120B.asy b/spice/copy/sym/PowerProducts/ADuM4120B.asy new file mode 100755 index 0000000..11956b9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4120B.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal -48 0 -32 0 +LINE Normal 48 0 32 0 +RECTANGLE Normal 128 112 -128 -112 +TEXT 0 -56 Center 2 ADI +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value ADuM4120B +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4120xx.sub +SYMATTR Description Isolated, Precision Gate Driver with 2A Output +SYMATTR Value2 ADuM4120xx Glitch=1 Vrun2=7.2 +PIN -80 -112 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -80 112 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 80 112 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 80 -112 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADuM4120C.asy b/spice/copy/sym/PowerProducts/ADuM4120C.asy new file mode 100755 index 0000000..856dc4f --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4120C.asy @@ -0,0 +1,48 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal -48 0 -32 0 +LINE Normal 48 0 32 0 +RECTANGLE Normal 128 112 -128 -112 +TEXT 0 -56 Center 2 ADI +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value ADuM4120C +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4120xx.sub +SYMATTR Description Isolated, Precision Gate Driver with 2A Output +SYMATTR Value2 ADuM4120xx Glitch=1 Vrun2=11.2 +PIN -80 -112 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -80 112 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 80 112 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 80 -112 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/ADuM4121A.asy b/spice/copy/sym/PowerProducts/ADuM4121A.asy new file mode 100755 index 0000000..ba986ca --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4121A.asy @@ -0,0 +1,60 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal 56 0 32 0 +LINE Normal -22 -16 -28 -16 +LINE Normal -25 -13 -25 -19 +LINE Normal -23 16 -28 16 +LINE Normal 22 32 22 5 +LINE Normal 42 32 22 32 +LINE Normal -48 -16 -32 -16 +LINE Normal -48 16 -32 16 +RECTANGLE Normal 128 96 -128 -96 +TEXT 0 -56 Center 1 ADI +WINDOW 0 0 -96 Bottom 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value ADuM4121A +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4121xx.sub +SYMATTR Description High Voltage Isolated Gate Driver with Internal Miller Clamp, 2A Output +SYMATTR Value2 ADuM4121xx Vrun2=4.3 +PIN -80 -96 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName VI+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName VI- +PINATTR SpiceOrder 3 +PIN -80 96 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 4 +PIN 80 96 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Clamp +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 80 -96 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADuM4121B.asy b/spice/copy/sym/PowerProducts/ADuM4121B.asy new file mode 100755 index 0000000..6419d7b --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4121B.asy @@ -0,0 +1,60 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal 56 0 32 0 +LINE Normal -22 -16 -28 -16 +LINE Normal -25 -13 -25 -19 +LINE Normal -23 16 -28 16 +LINE Normal 22 32 22 5 +LINE Normal 42 32 22 32 +LINE Normal -48 -16 -32 -16 +LINE Normal -48 16 -32 16 +RECTANGLE Normal 128 96 -128 -96 +TEXT 0 -56 Center 1 ADI +WINDOW 0 0 -96 Bottom 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value ADuM4121B +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4121xx.sub +SYMATTR Description High Voltage Isolated Gate Driver with Internal Miller Clamp, 2A Output +SYMATTR Value2 ADuM4121xx Vrun2=7.2 +PIN -80 -96 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName VI+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName VI- +PINATTR SpiceOrder 3 +PIN -80 96 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 4 +PIN 80 96 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Clamp +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 80 -96 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADuM4121C.asy b/spice/copy/sym/PowerProducts/ADuM4121C.asy new file mode 100755 index 0000000..440591d --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4121C.asy @@ -0,0 +1,60 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal 56 0 32 0 +LINE Normal -22 -16 -28 -16 +LINE Normal -25 -13 -25 -19 +LINE Normal -23 16 -28 16 +LINE Normal 22 32 22 5 +LINE Normal 42 32 22 32 +LINE Normal -48 -16 -32 -16 +LINE Normal -48 16 -32 16 +RECTANGLE Normal 128 96 -128 -96 +TEXT 0 -56 Center 1 ADI +WINDOW 0 0 -96 Bottom 2 +WINDOW 3 0 54 Center 2 +SYMATTR Value ADuM4121C +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4121xx.sub +SYMATTR Description High Voltage Isolated Gate Driver with Internal Miller Clamp, 2A Output +SYMATTR Value2 ADuM4121xx Vrun2=11.2 +PIN -80 -96 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName VI+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName VI- +PINATTR SpiceOrder 3 +PIN -80 96 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 4 +PIN 80 96 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Clamp +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 80 -96 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADuM4122A.asy b/spice/copy/sym/PowerProducts/ADuM4122A.asy new file mode 100755 index 0000000..1fbeb88 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4122A.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal -48 0 -32 0 +LINE Normal 48 0 32 0 +RECTANGLE Normal 128 176 -128 -112 +TEXT 0 -56 Center 2 ADI +WINDOW 0 0 -112 Bottom 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value ADuM4122A +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4122x.sub +SYMATTR Description Single Gate Adjustable Slew Rate Isolated Gate Driver, 3A Short Circuit +SYMATTR Value2 ADuM4122x Vrun2=4.3 +PIN -80 -112 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -80 176 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 80 176 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 80 -112 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 6 +PIN -128 80 LEFT 8 +PINATTR PinName _SRC +PINATTR SpiceOrder 7 +PIN 128 80 RIGHT 8 +PINATTR PinName Vout_SRC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADuM4122B.asy b/spice/copy/sym/PowerProducts/ADuM4122B.asy new file mode 100755 index 0000000..321f824 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4122B.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal -48 0 -32 0 +LINE Normal 48 0 32 0 +RECTANGLE Normal 128 176 -128 -112 +TEXT 0 -56 Center 2 ADI +WINDOW 0 0 -112 Bottom 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value ADuM4122B +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4122x.sub +SYMATTR Description Single Gate Adjustable Slew Rate Isolated Gate Driver, 3A Short Circuit +SYMATTR Value2 ADuM4122x Vrun2=7.2 +PIN -80 -112 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -80 176 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 80 176 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 80 -112 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 6 +PIN -128 80 LEFT 8 +PINATTR PinName _SRC +PINATTR SpiceOrder 7 +PIN 128 80 RIGHT 8 +PINATTR PinName Vout_SRC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADuM4122C.asy b/spice/copy/sym/PowerProducts/ADuM4122C.asy new file mode 100755 index 0000000..bc042b5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4122C.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 -32 -32 +LINE Normal -5 18 -32 32 +LINE Normal -5 -19 -32 -32 +LINE Normal 32 0 0 -17 +LINE Normal 0 16 32 0 +LINE Normal -9 -15 0 -25 +LINE Normal 0 -9 -9 -15 +LINE Normal -9 -2 0 -9 +LINE Normal 0 6 -9 -2 +LINE Normal -9 14 0 6 +LINE Normal 0 23 -9 14 +LINE Normal -2 -15 7 -25 +LINE Normal 7 -9 -2 -15 +LINE Normal -2 -2 7 -9 +LINE Normal 7 6 -2 -2 +LINE Normal -2 14 7 6 +LINE Normal 7 23 -2 14 +LINE Normal -48 0 -32 0 +LINE Normal 48 0 32 0 +RECTANGLE Normal 128 176 -128 -112 +TEXT 0 -56 Center 2 ADI +WINDOW 0 0 -112 Bottom 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value ADuM4122C +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4122x.sub +SYMATTR Description Single Gate Adjustable Slew Rate Isolated Gate Driver, 3A Short Circuit +SYMATTR Value2 ADuM4122x Vrun2=11.2 +PIN -80 -112 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -80 176 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 80 176 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 80 -112 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 6 +PIN -128 80 LEFT 8 +PINATTR PinName _SRC +PINATTR SpiceOrder 7 +PIN 128 80 RIGHT 8 +PINATTR PinName Vout_SRC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/ADuM4135.asy b/spice/copy/sym/PowerProducts/ADuM4135.asy new file mode 100755 index 0000000..a67b470 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4135.asy @@ -0,0 +1,78 @@ +Version 4 +SymbolType CELL +LINE Normal -32 80 -32 16 +LINE Normal -5 66 -32 80 +LINE Normal -5 29 -32 16 +LINE Normal 32 48 0 31 +LINE Normal 0 64 32 48 +LINE Normal -9 33 0 23 +LINE Normal 0 39 -9 33 +LINE Normal -9 46 0 39 +LINE Normal 0 54 -9 46 +LINE Normal -9 62 0 54 +LINE Normal 0 71 -9 62 +LINE Normal -2 33 7 23 +LINE Normal 7 39 -2 33 +LINE Normal -2 46 7 39 +LINE Normal 7 54 -2 46 +LINE Normal -2 62 7 54 +LINE Normal 7 71 -2 62 +LINE Normal -22 32 -28 32 +LINE Normal -25 35 -25 29 +LINE Normal -23 64 -28 64 +LINE Normal -59 32 -32 32 +LINE Normal -59 64 -32 64 +LINE Normal 48 55 28 55 +LINE Normal 19 41 48 41 +RECTANGLE Normal 160 304 -144 -144 +CIRCLE Normal 28 59 21 52 +TEXT 0 112 Center 2 ADI +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 201 Center 2 +SYMATTR Value ADuM4135 +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4135.sub +SYMATTR Description Single/Dual Supply, High Voltage Isolated IGBT Gate Driver with Miller Clamp +SYMATTR Value2 ADuM4135 +PIN -48 304 BOTTOM 8 +PINATTR PinName Vss1 +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName VI+ +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName VI- +PINATTR SpiceOrder 3 +PIN -144 160 LEFT 8 +PINATTR PinName Ready +PINATTR SpiceOrder 4 +PIN -144 240 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 6 +PIN -48 -144 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 7 +PIN 48 304 BOTTOM 8 +PINATTR PinName Vss2 +PINATTR SpiceOrder 8 +PIN 160 -80 RIGHT 8 +PINATTR PinName DeSat +PINATTR SpiceOrder 9 +PIN 160 240 RIGHT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 10 +PIN 160 80 RIGHT 8 +PINATTR PinName Vout_OFF +PINATTR SpiceOrder 11 +PIN 48 -144 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 12 +PIN 160 0 RIGHT 8 +PINATTR PinName Vout_ON +PINATTR SpiceOrder 13 +PIN 160 160 RIGHT 8 +PINATTR PinName GATE_SENSE +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/ADuM4136.asy b/spice/copy/sym/PowerProducts/ADuM4136.asy new file mode 100755 index 0000000..48e8f08 --- /dev/null +++ b/spice/copy/sym/PowerProducts/ADuM4136.asy @@ -0,0 +1,70 @@ +Version 4 +SymbolType CELL +LINE Normal -31 0 -31 -64 +LINE Normal -4 -14 -31 0 +LINE Normal -4 -51 -31 -64 +LINE Normal 33 -32 1 -49 +LINE Normal 1 -16 33 -32 +LINE Normal -8 -47 1 -57 +LINE Normal 1 -41 -8 -47 +LINE Normal -8 -34 1 -41 +LINE Normal 1 -26 -8 -34 +LINE Normal -8 -18 1 -26 +LINE Normal 1 -9 -8 -18 +LINE Normal -1 -47 8 -57 +LINE Normal 8 -41 -1 -47 +LINE Normal -1 -34 8 -41 +LINE Normal 8 -26 -1 -34 +LINE Normal -1 -18 8 -26 +LINE Normal 8 -9 -1 -18 +LINE Normal 80 -32 33 -32 +LINE Normal -21 -48 -27 -48 +LINE Normal -24 -45 -24 -51 +LINE Normal -22 -16 -27 -16 +LINE Normal -74 -48 -31 -48 +LINE Normal -74 -16 -31 -16 +RECTANGLE Normal 160 240 -176 -208 +TEXT 0 48 Center 2 ADI +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 124 Center 2 +SYMATTR Value ADuM4136 +SYMATTR Prefix X +SYMATTR SpiceModel ADuM4136.sub +SYMATTR Description Single/Dual Supply, High Voltage Isolated IGBT Gate Driver +SYMATTR Value2 ADuM4136 +PIN -176 -64 LEFT 8 +PINATTR PinName VI+ +PINATTR SpiceOrder 1 +PIN -176 16 LEFT 8 +PINATTR PinName VI- +PINATTR SpiceOrder 2 +PIN -64 -208 TOP 8 +PINATTR PinName Vdd1 +PINATTR SpiceOrder 3 +PIN -64 240 BOTTOM 8 +PINATTR PinName Vss1 +PINATTR SpiceOrder 4 +PIN -176 -144 LEFT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 5 +PIN -176 176 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 6 +PIN -176 96 LEFT 8 +PINATTR PinName Ready +PINATTR SpiceOrder 7 +PIN 48 240 BOTTOM 8 +PINATTR PinName Vss2 +PINATTR SpiceOrder 8 +PIN 160 -32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 9 +PIN 48 -208 TOP 8 +PINATTR PinName Vdd2 +PINATTR SpiceOrder 10 +PIN 160 -144 RIGHT 8 +PINATTR PinName Desat +PINATTR SpiceOrder 11 +PIN 160 176 RIGHT 8 +PINATTR PinName Gnd2 +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT1026.asy b/spice/copy/sym/PowerProducts/LT1026.asy new file mode 100755 index 0000000..5a9b82c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1026.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1026 +SYMATTR Prefix X +SYMATTR SpiceModel LT1026.sub +SYMATTR Value2 LT1026 +SYMATTR Description Switched Capacitor Voltage Converter +PIN -128 -96 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName -Vout +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName +Vout +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1054.asy b/spice/copy/sym/PowerProducts/LT1054.asy new file mode 100755 index 0000000..4fb2752 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1054.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1054 +SYMATTR Prefix X +SYMATTR SpiceModel LT1054.sub +SYMATTR Value2 LT1054 +SYMATTR Description Switched-Capacitor Voltage Converter with Regulator +PIN -128 -96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Cap+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName Cap- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1054L.asy b/spice/copy/sym/PowerProducts/LT1054L.asy new file mode 100755 index 0000000..5155d32 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1054L.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1054L +SYMATTR Prefix X +SYMATTR SpiceModel LT1054L.sub +SYMATTR Value2 LT1054L +SYMATTR Description Switched-Capacitor Voltage Converter with Regulator +PIN -128 -96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Cap+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName Cap- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1070.asy b/spice/copy/sym/PowerProducts/LT1070.asy new file mode 100755 index 0000000..f84691f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1070.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1070 +SYMATTR Prefix X +SYMATTR SpiceModel LT1070.sub +SYMATTR Value2 LT1070 +SYMATTR Description 5A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1070HV.asy b/spice/copy/sym/PowerProducts/LT1070HV.asy new file mode 100755 index 0000000..529ad65 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1070HV.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1070HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1070.sub +SYMATTR Value2 LT1070 +SYMATTR Description 5A High Efficiency Switching Regulator(High Voltage version) +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1071.asy b/spice/copy/sym/PowerProducts/LT1071.asy new file mode 100755 index 0000000..f9eb4f7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1071.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1071 +SYMATTR Prefix X +SYMATTR SpiceModel LT1071.sub +SYMATTR Value2 LT1071 +SYMATTR Description 2.5A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1071HV.asy b/spice/copy/sym/PowerProducts/LT1071HV.asy new file mode 100755 index 0000000..d64b4d5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1071HV.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1071HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1071.sub +SYMATTR Value2 LT1071 +SYMATTR Description 2.5A High Efficiency Switching Regulator(High Voltage version) +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1072.asy b/spice/copy/sym/PowerProducts/LT1072.asy new file mode 100755 index 0000000..360b597 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1072.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1072 +SYMATTR Prefix X +SYMATTR SpiceModel LT1072.sub +SYMATTR Value2 LT1072 +SYMATTR Description 1.25A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1072HV.asy b/spice/copy/sym/PowerProducts/LT1072HV.asy new file mode 100755 index 0000000..450ac01 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1072HV.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1072HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1072.sub +SYMATTR Value2 LT1072 +SYMATTR Description 1.25A High Efficiency Switching Regulator(High Voltage version) +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1073-12.asy b/spice/copy/sym/PowerProducts/LT1073-12.asy new file mode 100755 index 0000000..ccb3c0c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1073-12.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT1073-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1073.sub +SYMATTR Value2 LT1073 top=904K bot=16.3K +SYMATTR Description 12 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1073-5.asy b/spice/copy/sym/PowerProducts/LT1073-5.asy new file mode 100755 index 0000000..03f8404 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1073-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 89 Center 2 +SYMATTR Value LT1073-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1073.sub +SYMATTR Value2 LT1073 top=904K bot=40K +SYMATTR Description 5 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1073.asy b/spice/copy/sym/PowerProducts/LT1073.asy new file mode 100755 index 0000000..cd581f6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1073.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT1073 +SYMATTR Prefix X +SYMATTR SpiceModel LT1073.sub +SYMATTR Value2 LT1073 top=1K bot=1T +SYMATTR Description 5 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1074.asy b/spice/copy/sym/PowerProducts/LT1074.asy new file mode 100755 index 0000000..913fbef --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1074.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1074 +SYMATTR Value2 LT1074 +SYMATTR Prefix X +SYMATTR SpiceModel LT1074.sub +SYMATTR Description 5A Step-Down Switching Regulator +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -128 64 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -128 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1074HV.asy b/spice/copy/sym/PowerProducts/LT1074HV.asy new file mode 100755 index 0000000..f51a071 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1074HV.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 1 89 Center 2 +SYMATTR Value LT1074HV +SYMATTR Value2 LT1074 +SYMATTR Prefix X +SYMATTR SpiceModel LT1074.sub +SYMATTR Description 5A Step-Down Switching Regulator +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -128 64 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -128 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1076-5.asy b/spice/copy/sym/PowerProducts/LT1076-5.asy new file mode 100755 index 0000000..b006114 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1076-5.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1076-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1076-5.sub +SYMATTR Value2 LT1076-5 +SYMATTR Description 2A Step-Down Switching Regulator +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -128 80 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN 128 80 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -128 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1076.asy b/spice/copy/sym/PowerProducts/LT1076.asy new file mode 100755 index 0000000..42e7d72 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1076.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1076 +SYMATTR Prefix X +SYMATTR SpiceModel LT1076.sub +SYMATTR Value2 LT1076 +SYMATTR Description 2A Step-Down Switching Regulator +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -128 48 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 64 RIGHT 8 +PINATTR PinName VC +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1076HV.asy b/spice/copy/sym/PowerProducts/LT1076HV.asy new file mode 100755 index 0000000..e07c19a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1076HV.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT1076HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1076.sub +SYMATTR Value2 LT1076 +SYMATTR Description 2A Step-Down Switching Regulator +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -128 48 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 128 64 RIGHT 8 +PINATTR PinName VC +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1082.asy b/spice/copy/sym/PowerProducts/LT1082.asy new file mode 100755 index 0000000..3d18fae --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1082.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 89 Center 2 +SYMATTR Value LT1082 +SYMATTR Prefix X +SYMATTR SpiceModel LT1082.sub +SYMATTR Value2 LT1082 +SYMATTR Description 1A High Voltage, Efficiency Switching Voltage Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1083-12.asy b/spice/copy/sym/PowerProducts/LT1083-12.asy new file mode 100755 index 0000000..a4ebc0d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1083-12.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1083-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1083-12 +SYMATTR Description 7.5A Low Dropout Positive Regulator, Fixed 12V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1083-5.asy b/spice/copy/sym/PowerProducts/LT1083-5.asy new file mode 100755 index 0000000..623395f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1083-5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1083-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1083-5 +SYMATTR Description 7.5A Low Dropout Positive Regulator, Fixed 5V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1083.asy b/spice/copy/sym/PowerProducts/LT1083.asy new file mode 100755 index 0000000..b260cd5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1083.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1083 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1083 +SYMATTR Description 7.5A Low Dropout Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1084-12.asy b/spice/copy/sym/PowerProducts/LT1084-12.asy new file mode 100755 index 0000000..03d6925 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1084-12.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1084-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1084-12 +SYMATTR Description 5A Low Dropout Positive Regulator, Fixed 12V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1084-3.3.asy b/spice/copy/sym/PowerProducts/LT1084-3.3.asy new file mode 100755 index 0000000..04e957c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1084-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1084-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1084-3.3 +SYMATTR Description 5A Low Dropout Positive Regulator, Fixed 3.3V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1084-5.asy b/spice/copy/sym/PowerProducts/LT1084-5.asy new file mode 100755 index 0000000..194a64d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1084-5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1084-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1084-5 +SYMATTR Description 5A Low Dropout Positive Regulator, Fixed 5V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1084.asy b/spice/copy/sym/PowerProducts/LT1084.asy new file mode 100755 index 0000000..239edd1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1084.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1084 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1084 +SYMATTR Description 5A Low Dropout Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1085-12.asy b/spice/copy/sym/PowerProducts/LT1085-12.asy new file mode 100755 index 0000000..0e9bf76 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1085-12.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1085-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1085-12 +SYMATTR Description 3A Low Dropout Positive Regulator, Fixed 12V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1085-3.3.asy b/spice/copy/sym/PowerProducts/LT1085-3.3.asy new file mode 100755 index 0000000..0d050e6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1085-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1085-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1085-3.3 +SYMATTR Description 3A Low Dropout Positive Regulator, Fixed 3.3V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1085-3.6.asy b/spice/copy/sym/PowerProducts/LT1085-3.6.asy new file mode 100755 index 0000000..bdc827d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1085-3.6.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1085-3.6 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1085-3.6 +SYMATTR Description 3A Low Dropout Positive Regulator, Fixed 3.6V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1085-5.asy b/spice/copy/sym/PowerProducts/LT1085-5.asy new file mode 100755 index 0000000..f42ded3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1085-5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1085-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1085-5 +SYMATTR Description 3A Low Dropout Positive Regulator, Fixed 5V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1085.asy b/spice/copy/sym/PowerProducts/LT1085.asy new file mode 100755 index 0000000..4ffa350 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1085.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1085 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1085 +SYMATTR Description 3A Low Dropout Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1086-12.asy b/spice/copy/sym/PowerProducts/LT1086-12.asy new file mode 100755 index 0000000..93dc1c7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1086-12.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1086-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1086-12 +SYMATTR Description 1.5A Low Dropout Positive Regulator, Fixed 12V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1086-2.85.asy b/spice/copy/sym/PowerProducts/LT1086-2.85.asy new file mode 100755 index 0000000..a1aa6b5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1086-2.85.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1086-2.85 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1086-2.85 +SYMATTR Description 1.5A Low Dropout Positive Regulator, Fixed 2.85V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1086-3.3.asy b/spice/copy/sym/PowerProducts/LT1086-3.3.asy new file mode 100755 index 0000000..2a68e54 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1086-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1086-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1086-3.3 +SYMATTR Description 1.5A Low Dropout Positive Regulator, Fixed 3.3V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1086-3.6.asy b/spice/copy/sym/PowerProducts/LT1086-3.6.asy new file mode 100755 index 0000000..553825d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1086-3.6.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1086-3.6 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1086-3.6 +SYMATTR Description 1.5A Low Dropout Positive Regulator, Fixed 3.6V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1086-5.asy b/spice/copy/sym/PowerProducts/LT1086-5.asy new file mode 100755 index 0000000..b4eb2c8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1086-5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1086-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1086-5 +SYMATTR Description 1.5A Low Dropout Positive Regulator, Fixed 5V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1086.asy b/spice/copy/sym/PowerProducts/LT1086.asy new file mode 100755 index 0000000..254c003 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1086.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1086 +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1086 +SYMATTR Description 1.5A Low Dropout Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1086H.asy b/spice/copy/sym/PowerProducts/LT1086H.asy new file mode 100755 index 0000000..57f8f62 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1086H.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1086H +SYMATTR Prefix X +SYMATTR SpiceModel LT1083.lib +SYMATTR Value2 LT1086H +SYMATTR Description 0.7A Low Dropout Positive Adjustable Regulator +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1103.asy b/spice/copy/sym/PowerProducts/LT1103.asy new file mode 100755 index 0000000..48576e7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1103.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1103 +SYMATTR Prefix X +SYMATTR SpiceModel LT1103.sub +SYMATTR Value2 LT1103 +SYMATTR Description Offline Switching Regulator +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 3 +PIN 64 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -64 144 BOTTOM 8 +PINATTR PinName OSC +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 80 RIGHT 8 +PINATTR PinName 15V +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1105.asy b/spice/copy/sym/PowerProducts/LT1105.asy new file mode 100755 index 0000000..e4e9a37 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1105.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1105 +SYMATTR Prefix X +SYMATTR SpiceModel LT1105.sub +SYMATTR Value2 LT1105 +SYMATTR Description Offline Switching Regulator +PIN 64 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 4 +PIN -64 144 BOTTOM 8 +PINATTR PinName OSC +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -80 RIGHT 8 +PINATTR PinName 15V +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1106.asy b/spice/copy/sym/PowerProducts/LT1106.asy new file mode 100755 index 0000000..b711ec0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1106.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -192 208 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1106 +SYMATTR Prefix X +SYMATTR SpiceModel LT1106.sub +SYMATTR Value2 LT1106 +SYMATTR Description µPower Step-Up DC/DC Converter for PCMCIA Card Flash Memory +PIN 208 128 RIGHT 8 +PINATTR PinName SEL 12/5 +PINATTR SpiceOrder 1 +PIN 208 64 RIGHT 8 +PINATTR PinName Soft Start +PINATTR SpiceOrder 2 +PIN -80 -192 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName 3/5 Detect +PINATTR SpiceOrder 5 +PIN 80 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 80 -192 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN -80 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 13 +PIN 208 -64 RIGHT 8 +PINATTR PinName _Vpp Valid +PINATTR SpiceOrder 14 +PIN -208 64 LEFT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 15 +PIN -208 -64 LEFT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 16 +PIN -208 0 LEFT 8 +PINATTR PinName Vpp2 +PINATTR SpiceOrder 17 +PIN -208 -128 LEFT 8 +PINATTR PinName Vpp1 +PINATTR SpiceOrder 18 +PIN 208 -128 RIGHT 8 +PINATTR PinName AVpp +PINATTR SpiceOrder 19 +PIN -208 128 LEFT 8 +PINATTR PinName ON/OFF +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT1107-12.asy b/spice/copy/sym/PowerProducts/LT1107-12.asy new file mode 100755 index 0000000..9702884 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1107-12.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1107-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1107.sub +SYMATTR Value2 LT1107 top=220K bot=25.5K +SYMATTR Description 12 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName AO +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1107-5.asy b/spice/copy/sym/PowerProducts/LT1107-5.asy new file mode 100755 index 0000000..c407646 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1107-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 -1 66 Center 2 +SYMATTR Value LT1107-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1107.sub +SYMATTR Value2 LT1107 top=220K bot=73.5K +SYMATTR Description 5 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName AO +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1107.asy b/spice/copy/sym/PowerProducts/LT1107.asy new file mode 100755 index 0000000..9671abb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1107.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1107 +SYMATTR Prefix X +SYMATTR SpiceModel LT1107.sub +SYMATTR Value2 LT1107 top=1K bot=1T +SYMATTR Description Adjustable µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName AO +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1108-12.asy b/spice/copy/sym/PowerProducts/LT1108-12.asy new file mode 100755 index 0000000..691e80f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1108-12.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 65 Center 2 +SYMATTR Value LT1108-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1108.sub +SYMATTR Value2 LT1108 top=753K bot=87.4K +SYMATTR Description 12Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName AO +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1108-5.asy b/spice/copy/sym/PowerProducts/LT1108-5.asy new file mode 100755 index 0000000..cdc7dbf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1108-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1108-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1108.sub +SYMATTR Value2 LT1108 top=753K bot=250K +SYMATTR Description 5Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName AO +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1108.asy b/spice/copy/sym/PowerProducts/LT1108.asy new file mode 100755 index 0000000..bfb595d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1108.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1108 +SYMATTR Prefix X +SYMATTR SpiceModel LT1108.sub +SYMATTR Value2 LT1108 top=1K bot=1T +SYMATTR Description Adjustable µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName AO +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1109-12.asy b/spice/copy/sym/PowerProducts/LT1109-12.asy new file mode 100755 index 0000000..ed35d68 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1109-12.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 16 -96 Left 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1109-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1109.sub +SYMATTR Value2 LT1109 top=250K bot=29K +SYMATTR Description µPower Low Cost DC/DC Converter, Fixed 12V +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 16 LEFT 8 +PINATTR PinName _SDN +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1109-5.asy b/spice/copy/sym/PowerProducts/LT1109-5.asy new file mode 100755 index 0000000..dfee226 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1109-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 16 -96 Left 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1109-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1109.sub +SYMATTR Value2 LT1109 top=250K bot=83K +SYMATTR Description µPower Low Cost DC/DC Converter, Fixed 5V +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 16 LEFT 8 +PINATTR PinName _SDN +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1109.asy b/spice/copy/sym/PowerProducts/LT1109.asy new file mode 100755 index 0000000..0c2ef6d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1109.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 16 -96 Left 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1109 +SYMATTR Prefix X +SYMATTR SpiceModel LT1109.sub +SYMATTR Value2 LT1109 top=1k bot=1T +SYMATTR Description µPower Low Cost DC/DC Converter, Adjustable Output Voltage +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 16 LEFT 8 +PINATTR PinName _SDN +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1109A-12.asy b/spice/copy/sym/PowerProducts/LT1109A-12.asy new file mode 100755 index 0000000..8e12919 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1109A-12.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 16 -96 Left 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1109A-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1109A.sub +SYMATTR Value2 LT1109A top=250K bot=29K +SYMATTR Description µPower DC/DC Converter Flash Memory VPP Generator, Fixed 12V +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 16 LEFT 8 +PINATTR PinName _SDN +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1109A-5.asy b/spice/copy/sym/PowerProducts/LT1109A-5.asy new file mode 100755 index 0000000..6211076 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1109A-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 16 -96 Left 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1109A-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1109A.sub +SYMATTR Value2 LT1109A top=250K bot=83K +SYMATTR Description µPower DC/DC Converter Flash Memory VPP Generator, Fixed 5V +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 16 LEFT 8 +PINATTR PinName _SDN +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1109A.asy b/spice/copy/sym/PowerProducts/LT1109A.asy new file mode 100755 index 0000000..b758044 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1109A.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 16 -96 Left 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1109A +SYMATTR Prefix X +SYMATTR SpiceModel LT1109A.sub +SYMATTR Value2 LT1109A top=1K bot=1T +SYMATTR Description µPower DC/DC Converter Flash Memory VPP Generator, Adjustable Output Voltage +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 16 LEFT 8 +PINATTR PinName _SDN +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1110-12.asy b/spice/copy/sym/PowerProducts/LT1110-12.asy new file mode 100755 index 0000000..44f67b0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1110-12.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1110-12 +SYMATTR Prefix X +SYMATTR Value2 LT1110 top=300K bot=5.6K +SYMATTR SpiceModel LT1110.sub +SYMATTR Description 12 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1110-5.asy b/spice/copy/sym/PowerProducts/LT1110-5.asy new file mode 100755 index 0000000..5005cbd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1110-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1110-5 +SYMATTR Prefix X +SYMATTR Value2 LT1110 top=300K bot=13.8K +SYMATTR SpiceModel LT1110.sub +SYMATTR Description 5 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1110.asy b/spice/copy/sym/PowerProducts/LT1110.asy new file mode 100755 index 0000000..0229dee --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1110.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1110 +SYMATTR Prefix X +SYMATTR Value2 LT1110 top=1K bot=1T +SYMATTR SpiceModel LT1110.sub +SYMATTR Description Adjustable µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1111-12.asy b/spice/copy/sym/PowerProducts/LT1111-12.asy new file mode 100755 index 0000000..c558116 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1111-12.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1111-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1111.sub +SYMATTR Value2 LT1111 top=220K bot=25.5K +SYMATTR Description 12 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName AO +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1111-5.asy b/spice/copy/sym/PowerProducts/LT1111-5.asy new file mode 100755 index 0000000..fd76540 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1111-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1111-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1111.sub +SYMATTR Value2 LT1111 top=220K bot=73.5K +SYMATTR Description 5 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName AO +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1111.asy b/spice/copy/sym/PowerProducts/LT1111.asy new file mode 100755 index 0000000..258ae84 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1111.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1111 +SYMATTR Prefix X +SYMATTR SpiceModel LT1111.sub +SYMATTR Value2 LT1111 top=1K bot=1T +SYMATTR Description Adjustable µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName AO +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1117-2.85.asy b/spice/copy/sym/PowerProducts/LT1117-2.85.asy new file mode 100755 index 0000000..99ed0d5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1117-2.85.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1117-2.85 +SYMATTR Prefix X +SYMATTR SpiceModel LT1117.lib +SYMATTR Value2 LT1117-2.85 +SYMATTR Description 800mA Low Dropout Positive Regulators, Fixed 2.85V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1117-3.3.asy b/spice/copy/sym/PowerProducts/LT1117-3.3.asy new file mode 100755 index 0000000..c93c8e0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1117-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1117-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1117.lib +SYMATTR Value2 LT1117-3.3 +SYMATTR Description 800mA Low Dropout Positive Regulators, Fixed 3.3V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1117-5.asy b/spice/copy/sym/PowerProducts/LT1117-5.asy new file mode 100755 index 0000000..b63585f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1117-5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1117-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1117.lib +SYMATTR Value2 LT1117-5 +SYMATTR Description 800mA Low Dropout Positive Regulators, Fixed 5V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1117.asy b/spice/copy/sym/PowerProducts/LT1117.asy new file mode 100755 index 0000000..88f3a25 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1117.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1117 +SYMATTR Prefix X +SYMATTR SpiceModel LT1117.lib +SYMATTR Value2 LT1117 +SYMATTR Description 800mA Low Dropout Positive Regulators, Adjustable Output Voltage +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1118-2.5.asy b/spice/copy/sym/PowerProducts/LT1118-2.5.asy new file mode 100755 index 0000000..0f3941c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1118-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -96 128 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 16 Top 2 +SYMATTR Value LT1118-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1118.lib +SYMATTR Value2 LT1118-2.5 +SYMATTR Description Low Iq, Low Dropout, 800mA Source and Sink Regulator, Fixed 2.5V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1118-2.85.asy b/spice/copy/sym/PowerProducts/LT1118-2.85.asy new file mode 100755 index 0000000..815896e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1118-2.85.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -96 128 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 16 Top 2 +SYMATTR Value LT1118-2.85 +SYMATTR Prefix X +SYMATTR SpiceModel LT1118.lib +SYMATTR Value2 LT1118-2.85 +SYMATTR Description Low Iq, Low Dropout, 800mA Source and Sink Regulator, Fixed 2.85V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1118-5.asy b/spice/copy/sym/PowerProducts/LT1118-5.asy new file mode 100755 index 0000000..cd46c97 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1118-5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -96 128 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 16 Top 2 +SYMATTR Value LT1118-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1118.lib +SYMATTR Value2 LT1118-5 +SYMATTR Description Low Iq, Low Dropout, 800mA Source and Sink Regulator, Fixed 5V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -128 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1118.asy b/spice/copy/sym/PowerProducts/LT1118.asy new file mode 100755 index 0000000..5d3bd48 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1118.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -96 128 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 16 Top 2 +SYMATTR Value LT1118 +SYMATTR Prefix X +SYMATTR SpiceModel LT1118.lib +SYMATTR Value2 LT1118 +SYMATTR Description Low Iq, Low Dropout, 800mA Source and Sink Regulator, Adjustable Output Voltage +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 48 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN 128 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -128 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1121-3.3.asy b/spice/copy/sym/PowerProducts/LT1121-3.3.asy new file mode 100755 index 0000000..8b5d57c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1121-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1121-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1121.lib +SYMATTR Value2 LT1121-3.3 +SYMATTR Description µPower Low Dropout Regulator with Shutdown, Fixed 3.3V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1121-5.asy b/spice/copy/sym/PowerProducts/LT1121-5.asy new file mode 100755 index 0000000..19f9a50 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1121-5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1121-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1121.lib +SYMATTR Value2 LT1121-5 +SYMATTR Description µPower Low Dropout Regulator with Shutdown, Fixed 5V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1121.asy b/spice/copy/sym/PowerProducts/LT1121.asy new file mode 100755 index 0000000..95ae828 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1121.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1121 +SYMATTR Prefix X +SYMATTR SpiceModel LT1121.lib +SYMATTR Value2 LT1121 +SYMATTR Description µPower Low Dropout Regulator with Shutdown, Adjustable Output Voltage +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1129-3.3.asy b/spice/copy/sym/PowerProducts/LT1129-3.3.asy new file mode 100755 index 0000000..caa21b1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1129-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 15 128 Left 2 +SYMATTR Value LT1129-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1129.lib +SYMATTR Value2 LT1129-3.3 +SYMATTR Description µPower Low Dropout Regulator with Shutdown, Fixed 3.3V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1129-5.asy b/spice/copy/sym/PowerProducts/LT1129-5.asy new file mode 100755 index 0000000..027ac4e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1129-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1129-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1129.lib +SYMATTR Value2 LT1129-5 +SYMATTR Description µPower Low Dropout Regulator with Shutdown, Fixed 3.3V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1129.asy b/spice/copy/sym/PowerProducts/LT1129.asy new file mode 100755 index 0000000..1a9e89c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1129.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 16 128 Left 2 +SYMATTR Value LT1129 +SYMATTR Prefix X +SYMATTR SpiceModel LT1129.lib +SYMATTR Value2 LT1129 +SYMATTR Description µPower Low Dropout Regulator with Shutdown, Adjustable Output Voltage +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1158.asy b/spice/copy/sym/PowerProducts/LT1158.asy new file mode 100755 index 0000000..02d6672 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1158.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -240 176 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 111 Center 2 +SYMATTR Value LT1158 +SYMATTR Prefix X +SYMATTR SpiceModel LT1158.sub +SYMATTR Value2 LT1158 +SYMATTR Description Half-Bridge N-Channel Power MOSFET Driver +PIN -80 -240 TOP 8 +PINATTR PinName BoostDr +PINATTR SpiceOrder 1 +PIN -176 -176 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 2 +PIN -176 144 LEFT 8 +PINATTR PinName ENABLE +PINATTR SpiceOrder 4 +PIN -176 80 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 5 +PIN -176 -112 LEFT 8 +PINATTR PinName INPUT +PINATTR SpiceOrder 6 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 176 208 RIGHT 8 +PINATTR PinName BgateFB +PINATTR SpiceOrder 8 +PIN 176 144 RIGHT 8 +PINATTR PinName Bgate +PINATTR SpiceOrder 9 +PIN 176 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 11 +PIN 176 16 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 12 +PIN 176 -48 RIGHT 8 +PINATTR PinName Tsource +PINATTR SpiceOrder 13 +PIN 176 -112 RIGHT 8 +PINATTR PinName TgateFB +PINATTR SpiceOrder 14 +PIN 176 -176 RIGHT 8 +PINATTR PinName Tgate +PINATTR SpiceOrder 15 +PIN 80 -240 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1160.asy b/spice/copy/sym/PowerProducts/LT1160.asy new file mode 100755 index 0000000..8fee05b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1160.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -208 176 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1160 +SYMATTR Prefix X +SYMATTR SpiceModel LT1160.sub +SYMATTR Value2 LT1160 +SYMATTR Description Half-/Full-Bridge N-Channel Power MOSFET Driver +PIN -80 -208 TOP 8 +PINATTR PinName SV+ +PINATTR SpiceOrder 1 +PIN -176 -80 LEFT 8 +PINATTR PinName INtop +PINATTR SpiceOrder 2 +PIN -176 112 LEFT 8 +PINATTR PinName INbot +PINATTR SpiceOrder 3 +PIN -176 -144 LEFT 8 +PINATTR PinName _UVout +PINATTR SpiceOrder 4 +PIN -80 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 5 +PIN 80 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 176 RIGHT 8 +PINATTR PinName BgateFB +PINATTR SpiceOrder 8 +PIN 176 112 RIGHT 8 +PINATTR PinName Bgate +PINATTR SpiceOrder 9 +PIN 80 -208 TOP 8 +PINATTR PinName PV+ +PINATTR SpiceOrder 10 +PIN 176 48 RIGHT 8 +PINATTR PinName Tsource +PINATTR SpiceOrder 11 +PIN 176 -16 RIGHT 8 +PINATTR PinName TgateFB +PINATTR SpiceOrder 12 +PIN 176 -80 RIGHT 8 +PINATTR PinName Tgate +PINATTR SpiceOrder 13 +PIN 176 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT1161.asy b/spice/copy/sym/PowerProducts/LT1161.asy new file mode 100755 index 0000000..d39002a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1161.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1161 +SYMATTR Prefix X +SYMATTR SpiceModel LT1161.sub +SYMATTR Value2 LT1161 +SYMATTR Description Quad Protected High-Side MOSFET Driver (2 of 4 Channels) +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -160 -144 LEFT 8 +PINATTR PinName Timer1 +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName INPUT1 +PINATTR SpiceOrder 3 +PIN -160 -48 LEFT 8 +PINATTR PinName Timer2 +PINATTR SpiceOrder 4 +PIN -160 144 LEFT 8 +PINATTR PinName INPUT2 +PINATTR SpiceOrder 5 +PIN 0 -192 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 11 +PIN 160 144 RIGHT 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 16 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense2 +PINATTR SpiceOrder 17 +PIN 160 -48 RIGHT 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 18 +PIN 160 -144 RIGHT 8 +PINATTR PinName Sense1 +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LT1162.asy b/spice/copy/sym/PowerProducts/LT1162.asy new file mode 100755 index 0000000..c4357dd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1162.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -208 176 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1162 +SYMATTR Prefix X +SYMATTR SpiceModel LT1160.sub +SYMATTR Value2 LT1160 +SYMATTR Description Full-Bridge N-Channel Power MOSFET Driver(1 of 2 Channels) +PIN -80 -208 TOP 8 +PINATTR PinName SV+ +PINATTR SpiceOrder 1 +PIN -176 -80 LEFT 8 +PINATTR PinName INtop +PINATTR SpiceOrder 2 +PIN -176 112 LEFT 8 +PINATTR PinName INbot +PINATTR SpiceOrder 3 +PIN -176 -144 LEFT 8 +PINATTR PinName _UVout +PINATTR SpiceOrder 4 +PIN -80 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 5 +PIN 80 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN 176 176 RIGHT 8 +PINATTR PinName BgateFB +PINATTR SpiceOrder 8 +PIN 176 112 RIGHT 8 +PINATTR PinName Bgate +PINATTR SpiceOrder 9 +PIN 80 -208 TOP 8 +PINATTR PinName PV+ +PINATTR SpiceOrder 10 +PIN 176 48 RIGHT 8 +PINATTR PinName Tsource +PINATTR SpiceOrder 11 +PIN 176 -16 RIGHT 8 +PINATTR PinName TgateFB +PINATTR SpiceOrder 12 +PIN 176 -80 RIGHT 8 +PINATTR PinName Tgate +PINATTR SpiceOrder 13 +PIN 176 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT1170.asy b/spice/copy/sym/PowerProducts/LT1170.asy new file mode 100755 index 0000000..6f032e6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1170.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1170 +SYMATTR Prefix X +SYMATTR SpiceModel LT1170.sub +SYMATTR Value2 LT1170 +SYMATTR Description 100kHz, 5A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1170HV.asy b/spice/copy/sym/PowerProducts/LT1170HV.asy new file mode 100755 index 0000000..c7622e9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1170HV.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1170HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1170.sub +SYMATTR Value2 LT1170 +SYMATTR Description 100kHz, 5A High Efficiency Switching Regulator(High Voltage version) +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1171.asy b/spice/copy/sym/PowerProducts/LT1171.asy new file mode 100755 index 0000000..0a23b5d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1171.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1171 +SYMATTR Prefix X +SYMATTR SpiceModel LT1171.sub +SYMATTR Value2 LT1171 +SYMATTR Description 100kHz, 2.5A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1171HV.asy b/spice/copy/sym/PowerProducts/LT1171HV.asy new file mode 100755 index 0000000..4a77af8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1171HV.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1171HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1171.sub +SYMATTR Value2 LT1171 +SYMATTR Description 100kHz, 2.5A High Efficiency Switching Regulator(High Voltage version) +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1172.asy b/spice/copy/sym/PowerProducts/LT1172.asy new file mode 100755 index 0000000..273c488 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1172.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1172 +SYMATTR Prefix X +SYMATTR SpiceModel LT1172.sub +SYMATTR Value2 LT1172 +SYMATTR Description 100kHz, 1.25A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1172HV.asy b/spice/copy/sym/PowerProducts/LT1172HV.asy new file mode 100755 index 0000000..90c8688 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1172HV.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1172HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1172.sub +SYMATTR Value2 LT1172 +SYMATTR Description 100kHz, 1.25A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1173-12.asy b/spice/copy/sym/PowerProducts/LT1173-12.asy new file mode 100755 index 0000000..51a7a08 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1173-12.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1173-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT1173.sub +SYMATTR Value2 LT1173 top=753K bot=87.4K +SYMATTR Description 12 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1173-5.asy b/spice/copy/sym/PowerProducts/LT1173-5.asy new file mode 100755 index 0000000..b5cfd81 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1173-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1173-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1173.sub +SYMATTR Value2 LT1173 top=753K bot=250K +SYMATTR Description 5 Volt µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1173.asy b/spice/copy/sym/PowerProducts/LT1173.asy new file mode 100755 index 0000000..77f828b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1173.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1173 +SYMATTR Prefix X +SYMATTR SpiceModel LT1173.sub +SYMATTR Value2 LT1173 top=1K bot=1T +SYMATTR Description Adjustable µPower DC/DC Converter +PIN -64 -144 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1175-5.asy b/spice/copy/sym/PowerProducts/LT1175-5.asy new file mode 100755 index 0000000..0e81775 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1175-5.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1175-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1175.lib +SYMATTR Value2 LT1175-5 +SYMATTR Description 500mA Negative Low Dropout µPower Regulator, Fixed 5V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Ilim2 +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName Output +PINATTR SpiceOrder 3 +PIN 144 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 4 +PIN 80 -160 TOP 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -80 -160 TOP 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName Ilim4 +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1175.asy b/spice/copy/sym/PowerProducts/LT1175.asy new file mode 100755 index 0000000..6d4e1b6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1175.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1175 +SYMATTR Prefix X +SYMATTR SpiceModel LT1175.lib +SYMATTR Value2 LT1175 +SYMATTR Description 500mA Negative Low Dropout µPower Regulator, Adjustable Output Voltage +PIN -144 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Ilim2 +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName Output +PINATTR SpiceOrder 3 +PIN 144 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 4 +PIN 80 -160 TOP 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -80 -160 TOP 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName Ilim4 +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1176-5.asy b/spice/copy/sym/PowerProducts/LT1176-5.asy new file mode 100755 index 0000000..afa1ae5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1176-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 65 Center 2 +SYMATTR Value LT1176-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1176.sub +SYMATTR Value2 LT1176 top=2.8K bot=2.2K +SYMATTR Description Step-Down Switching Regulator, Fixed 5V Output +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 80 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 4 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -160 -80 LEFT 8 +PINATTR PinName Status +PINATTR SpiceOrder 6 +PIN 160 80 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1176.asy b/spice/copy/sym/PowerProducts/LT1176.asy new file mode 100755 index 0000000..aa6984d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1176.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1176 +SYMATTR Prefix X +SYMATTR SpiceModel LT1176.sub +SYMATTR Value2 LT1176 top=10 bot=1G +SYMATTR Description Step-Down Switching Regulator, Adjustable Output Voltage +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 80 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -160 -80 LEFT 8 +PINATTR PinName Status +PINATTR SpiceOrder 6 +PIN 160 80 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1182.asy b/spice/copy/sym/PowerProducts/LT1182.asy new file mode 100755 index 0000000..5293c33 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1182.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -352 224 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1182 +SYMATTR Prefix X +SYMATTR SpiceModel LT1182.sub +SYMATTR Value2 LT1182 +SYMATTR Description CCFL/LCD Contrast Switching Regulator +PIN 224 288 RIGHT 8 +PINATTR PinName CCFL PGND +PINATTR SpiceOrder 1 +PIN 224 96 RIGHT 8 +PINATTR PinName Iccfl +PINATTR SpiceOrder 2 +PIN -224 -288 LEFT 8 +PINATTR PinName DIO +PINATTR SpiceOrder 3 +PIN 224 192 RIGHT 8 +PINATTR PinName CCFL Vc +PINATTR SpiceOrder 4 +PIN 0 352 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN -224 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -224 192 LEFT 8 +PINATTR PinName LCD Vc +PINATTR SpiceOrder 7 +PIN -224 288 LEFT 8 +PINATTR PinName LCD PGND +PINATTR SpiceOrder 8 +PIN -224 -192 LEFT 8 +PINATTR PinName LCD SW +PINATTR SpiceOrder 9 +PIN -224 96 LEFT 8 +PINATTR PinName FBN +PINATTR SpiceOrder 10 +PIN -224 0 LEFT 8 +PINATTR PinName FBP +PINATTR SpiceOrder 11 +PIN 0 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN 224 -96 RIGHT 8 +PINATTR PinName ROYER +PINATTR SpiceOrder 13 +PIN 224 -192 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 14 +PIN 224 0 RIGHT 8 +PINATTR PinName BULB +PINATTR SpiceOrder 15 +PIN 224 -288 RIGHT 8 +PINATTR PinName CCFL SW +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1183.asy b/spice/copy/sym/PowerProducts/LT1183.asy new file mode 100755 index 0000000..7aa7c80 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1183.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -352 224 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT1183 +SYMATTR Prefix X +SYMATTR SpiceModel LT1183.sub +SYMATTR Value2 LT1183 +SYMATTR Description CCFL/LCD Contrast Switching Regulator +PIN 224 288 RIGHT 8 +PINATTR PinName CCFL PGND +PINATTR SpiceOrder 1 +PIN 224 96 RIGHT 8 +PINATTR PinName Iccfl +PINATTR SpiceOrder 2 +PIN -224 -288 LEFT 8 +PINATTR PinName DIO +PINATTR SpiceOrder 3 +PIN 224 192 RIGHT 8 +PINATTR PinName CCFL Vc +PINATTR SpiceOrder 4 +PIN 0 352 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN -224 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -224 192 LEFT 8 +PINATTR PinName LCD Vc +PINATTR SpiceOrder 7 +PIN -224 288 LEFT 8 +PINATTR PinName LCD PGND +PINATTR SpiceOrder 8 +PIN -224 -192 LEFT 8 +PINATTR PinName LCD SW +PINATTR SpiceOrder 9 +PIN -224 96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -224 0 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 11 +PIN 0 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN 224 -96 RIGHT 8 +PINATTR PinName ROYER +PINATTR SpiceOrder 13 +PIN 224 -192 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 14 +PIN 224 0 RIGHT 8 +PINATTR PinName BULB +PINATTR SpiceOrder 15 +PIN 224 -288 RIGHT 8 +PINATTR PinName CCFL SW +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1184.asy b/spice/copy/sym/PowerProducts/LT1184.asy new file mode 100755 index 0000000..a7b9df7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1184.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -224 224 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1184 +SYMATTR Prefix X +SYMATTR SpiceModel LT1184.sub +SYMATTR Value2 LT1184 +SYMATTR Description CCFL Switching Regulator, Grounded-Lamp +PIN 112 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN -224 48 LEFT 8 +PINATTR PinName Iccfl +PINATTR SpiceOrder 2 +PIN -224 -144 LEFT 8 +PINATTR PinName DIO +PINATTR SpiceOrder 3 +PIN 224 144 RIGHT 8 +PINATTR PinName CCFL Vc +PINATTR SpiceOrder 4 +PIN -112 224 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN -224 144 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -224 -48 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 11 +PIN -112 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN 224 0 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 14 +PIN 112 -224 TOP 8 +PINATTR PinName BULB +PINATTR SpiceOrder 15 +PIN 224 -144 RIGHT 8 +PINATTR PinName CCFL SW +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1184F.asy b/spice/copy/sym/PowerProducts/LT1184F.asy new file mode 100755 index 0000000..7ae69c7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1184F.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -224 224 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1184F +SYMATTR Prefix X +SYMATTR SpiceModel LT1184F.sub +SYMATTR Value2 LT1184F +SYMATTR Description CCFL Switching Regulator, Floating-Lamp or Grounded-Lamp +PIN 112 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN -224 48 LEFT 8 +PINATTR PinName Iccfl +PINATTR SpiceOrder 2 +PIN -224 -144 LEFT 8 +PINATTR PinName DIO +PINATTR SpiceOrder 3 +PIN 224 144 RIGHT 8 +PINATTR PinName CCFL Vc +PINATTR SpiceOrder 4 +PIN -112 224 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN -224 144 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -224 -48 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 11 +PIN -112 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN 224 48 RIGHT 8 +PINATTR PinName ROYER +PINATTR SpiceOrder 13 +PIN 224 -48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 14 +PIN 112 -224 TOP 8 +PINATTR PinName BULB +PINATTR SpiceOrder 15 +PIN 224 -144 RIGHT 8 +PINATTR PinName CCFL SW +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1185.asy b/spice/copy/sym/PowerProducts/LT1185.asy new file mode 100755 index 0000000..10bfed9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1185.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT1185 +SYMATTR Prefix X +SYMATTR SpiceModel LT1185.lib +SYMATTR Value2 LT1185 +SYMATTR Description Low Dropout Regulator +PIN 0 -112 TOP 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -128 64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN -128 -48 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1186F.asy b/spice/copy/sym/PowerProducts/LT1186F.asy new file mode 100755 index 0000000..46530d8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1186F.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -320 224 320 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT1186F +SYMATTR Prefix X +SYMATTR SpiceModel LT1186F.sub +SYMATTR Value2 LT1186F +SYMATTR Description DAC Programmable CCFL Switching Regulator(Bits-to-Nits(TM)) +PIN 112 320 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN -224 -48 LEFT 8 +PINATTR PinName Iccfl +PINATTR SpiceOrder 2 +PIN -224 -240 LEFT 8 +PINATTR PinName DIO +PINATTR SpiceOrder 3 +PIN 224 48 RIGHT 8 +PINATTR PinName CCFL Vc +PINATTR SpiceOrder 4 +PIN -112 320 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN -224 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -224 144 LEFT 8 +PINATTR PinName CLK +PINATTR SpiceOrder 7 +PIN -224 240 LEFT 8 +PINATTR PinName _CS +PINATTR SpiceOrder 8 +PIN 224 240 RIGHT 8 +PINATTR PinName Din +PINATTR SpiceOrder 9 +PIN 224 144 RIGHT 8 +PINATTR PinName Dout +PINATTR SpiceOrder 10 +PIN -224 -144 LEFT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 11 +PIN -112 -320 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 +PIN 224 -48 RIGHT 8 +PINATTR PinName ROYER +PINATTR SpiceOrder 13 +PIN 224 -144 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 14 +PIN 112 -320 TOP 8 +PINATTR PinName BULB +PINATTR SpiceOrder 15 +PIN 224 -240 RIGHT 8 +PINATTR PinName CCFL SW +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1241.asy b/spice/copy/sym/PowerProducts/LT1241.asy new file mode 100755 index 0000000..5feaad8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1241.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1241 +SYMATTR Prefix X +SYMATTR SpiceModel LT1241.sub +SYMATTR Value2 LT1241 +SYMATTR Description High Speed Current Mode Pulse Width Modulator +PIN -160 -32 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 1 +PIN -160 -96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN -160 96 LEFT 8 +PINATTR PinName Rt/Ct +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 -64 RIGHT 8 +PINATTR PinName Output +PINATTR SpiceOrder 6 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN -160 32 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1242.asy b/spice/copy/sym/PowerProducts/LT1242.asy new file mode 100755 index 0000000..0be0354 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1242.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1242 +SYMATTR Prefix X +SYMATTR SpiceModel LT1242.sub +SYMATTR Value2 LT1242 +SYMATTR Description High Speed Current Mode Pulse Width Modulator +PIN -160 -32 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 1 +PIN -160 -96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN -160 96 LEFT 8 +PINATTR PinName Rt/Ct +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 -64 RIGHT 8 +PINATTR PinName Output +PINATTR SpiceOrder 6 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN -160 32 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1243.asy b/spice/copy/sym/PowerProducts/LT1243.asy new file mode 100755 index 0000000..a0a389c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1243.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1243 +SYMATTR Prefix X +SYMATTR SpiceModel LT1243.sub +SYMATTR Value2 LT1243 +SYMATTR Description High Speed Current Mode Pulse Width Modulator +PIN -160 -32 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 1 +PIN -160 -96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN -160 96 LEFT 8 +PINATTR PinName Rt/Ct +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 -64 RIGHT 8 +PINATTR PinName Output +PINATTR SpiceOrder 6 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN -160 32 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1244.asy b/spice/copy/sym/PowerProducts/LT1244.asy new file mode 100755 index 0000000..7278cbb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1244.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1244 +SYMATTR Prefix X +SYMATTR SpiceModel LT1244.sub +SYMATTR Value2 LT1244 +SYMATTR Description High Speed Current Mode Pulse Width Modulator +PIN -160 -32 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 1 +PIN -160 -96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN -160 96 LEFT 8 +PINATTR PinName Rt/Ct +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 -64 RIGHT 8 +PINATTR PinName Output +PINATTR SpiceOrder 6 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN -160 32 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1245.asy b/spice/copy/sym/PowerProducts/LT1245.asy new file mode 100755 index 0000000..7406815 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1245.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1245 +SYMATTR Prefix X +SYMATTR SpiceModel LT1245.sub +SYMATTR Value2 LT1245 +SYMATTR Description High Speed Current Mode Pulse Width Modulator +PIN -160 -32 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 1 +PIN -160 -96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN -160 96 LEFT 8 +PINATTR PinName Rt/Ct +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 -64 RIGHT 8 +PINATTR PinName Output +PINATTR SpiceOrder 6 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN -160 32 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1246.asy b/spice/copy/sym/PowerProducts/LT1246.asy new file mode 100755 index 0000000..cddb461 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1246.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1246 +SYMATTR Prefix X +SYMATTR SpiceModel LT1246.sub +SYMATTR Value2 LT1246 +SYMATTR Description 1MHz Off-Line Current Mode PWM and DC/DC Converter +PIN 144 32 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 -32 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName Rt/Ct +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 -96 RIGHT 8 +PINATTR PinName Output +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN -144 -64 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1247.asy b/spice/copy/sym/PowerProducts/LT1247.asy new file mode 100755 index 0000000..96b2abb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1247.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1247 +SYMATTR Prefix X +SYMATTR SpiceModel LT1247.sub +SYMATTR Value2 LT1247 +SYMATTR Description 1MHz Off-Line Current Mode PWM and DC/DC Converter +PIN 144 32 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 -32 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName Rt/Ct +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 -96 RIGHT 8 +PINATTR PinName Output +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN -144 -64 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1248.asy b/spice/copy/sym/PowerProducts/LT1248.asy new file mode 100755 index 0000000..866b2be --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1248.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -320 192 240 +TEXT 0 -80 Center 2 LT +WINDOW 0 0 -199 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1248 +SYMATTR Prefix X +SYMATTR SpiceModel LT1248.sub +SYMATTR Value2 LT1248 +SYMATTR Description Power Factor Controller\n\nNote: External sync capability is not modeled +PIN 96 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -192 -240 LEFT 8 +PINATTR PinName PKlim +PINATTR SpiceOrder 2 +PIN -192 0 LEFT 8 +PINATTR PinName CAout +PINATTR SpiceOrder 3 +PIN -192 -80 LEFT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 4 +PIN -96 -320 TOP 8 +PINATTR PinName Mout +PINATTR SpiceOrder 5 +PIN 96 -320 TOP 8 +PINATTR PinName Iac +PINATTR SpiceOrder 6 +PIN 192 -80 RIGHT 8 +PINATTR PinName VAout +PINATTR SpiceOrder 7 +PIN 192 80 RIGHT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 8 +PIN -192 -160 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 9 +PIN 192 -160 RIGHT 8 +PINATTR PinName Enable +PINATTR SpiceOrder 10 +PIN 192 0 RIGHT 8 +PINATTR PinName Vsense +PINATTR SpiceOrder 11 +PIN -192 80 LEFT 8 +PINATTR PinName Rset +PINATTR SpiceOrder 12 +PIN -96 240 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 13 +PIN -192 160 LEFT 8 +PINATTR PinName Cset +PINATTR SpiceOrder 14 +PIN 192 -240 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN 192 160 RIGHT 8 +PINATTR PinName GTDR +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1249.asy b/spice/copy/sym/PowerProducts/LT1249.asy new file mode 100755 index 0000000..c31292a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1249.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -97 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1249 +SYMATTR Prefix X +SYMATTR SpiceModel LT1249.sub +SYMATTR Value2 LT1249 +SYMATTR Description Power Factor Controller\n\nNote: External sync capability is not modeled. +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -176 64 LEFT 8 +PINATTR PinName CAout +PINATTR SpiceOrder 2 +PIN -96 -160 TOP 8 +PINATTR PinName Mout +PINATTR SpiceOrder 3 +PIN 96 -160 TOP 8 +PINATTR PinName Iac +PINATTR SpiceOrder 4 +PIN 176 -80 RIGHT 8 +PINATTR PinName VAout +PINATTR SpiceOrder 5 +PIN 176 0 RIGHT 8 +PINATTR PinName Vsense +PINATTR SpiceOrder 6 +PIN -176 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN 176 80 RIGHT 8 +PINATTR PinName GTDR +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1268.asy b/spice/copy/sym/PowerProducts/LT1268.asy new file mode 100755 index 0000000..1b7de41 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1268.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1268 +SYMATTR Prefix X +SYMATTR SpiceModel LT1268.sub +SYMATTR Value2 LT1268 +SYMATTR Description 7.5A 150kHz Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1268B.asy b/spice/copy/sym/PowerProducts/LT1268B.asy new file mode 100755 index 0000000..4738eaa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1268B.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1268B +SYMATTR Prefix X +SYMATTR SpiceModel LT1268.sub +SYMATTR Value2 LT1268 +SYMATTR Description 7.5A 150kHz Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1269.asy b/spice/copy/sym/PowerProducts/LT1269.asy new file mode 100755 index 0000000..1bf93ec --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1269.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1269 +SYMATTR Prefix X +SYMATTR SpiceModel LT1269.sub +SYMATTR Value2 LT1269 +SYMATTR Description 4A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1270.asy b/spice/copy/sym/PowerProducts/LT1270.asy new file mode 100755 index 0000000..dc79f1c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1270.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1270 +SYMATTR Prefix X +SYMATTR SpiceModel LT1270.sub +SYMATTR Value2 LT1270 +SYMATTR Description 8A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1270A.asy b/spice/copy/sym/PowerProducts/LT1270A.asy new file mode 100755 index 0000000..357e147 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1270A.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1270A +SYMATTR Prefix X +SYMATTR SpiceModel LT1270A.sub +SYMATTR Value2 LT1270A +SYMATTR Description 10A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1271.asy b/spice/copy/sym/PowerProducts/LT1271.asy new file mode 100755 index 0000000..4c470a3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1271.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1271 +SYMATTR Prefix X +SYMATTR SpiceModel LT1271.sub +SYMATTR Value2 LT1271 +SYMATTR Description 4A High Efficiency Switching Regulator +PIN 128 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1300.asy b/spice/copy/sym/PowerProducts/LT1300.asy new file mode 100755 index 0000000..1e81133 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1300.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1300 +SYMATTR Prefix X +SYMATTR SpiceModel LT1300.sub +SYMATTR Value2 LT1300 +SYMATTR Description µPower High Efficiency 3.3/5V Step-Up DC/DC Converter +PIN -64 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 48 LEFT 8 +PINATTR PinName Sel +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 128 64 RIGHT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 64 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1301.asy b/spice/copy/sym/PowerProducts/LT1301.asy new file mode 100755 index 0000000..a1e5451 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1301.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1301 +SYMATTR Prefix X +SYMATTR SpiceModel LT1301.sub +SYMATTR Value2 LT1301 +SYMATTR Description µPower High Efficiency 5V/12V DC/DC Step-Up Converter for Flash Memory +PIN -64 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 48 LEFT 8 +PINATTR PinName Sel +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 128 64 RIGHT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 64 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1302-5.asy b/spice/copy/sym/PowerProducts/LT1302-5.asy new file mode 100755 index 0000000..a8fa6ce --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1302-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1302-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1302.sub +SYMATTR Value2 LT1302 top=315K bot=105K +SYMATTR Description µPower High Output Current Step-up Fixed 5V DC/DC Converter +PIN -80 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -144 -48 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName It +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 80 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1302.asy b/spice/copy/sym/PowerProducts/LT1302.asy new file mode 100755 index 0000000..3dfb5aa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1302.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1302 +SYMATTR Prefix X +SYMATTR SpiceModel LT1302.sub +SYMATTR Value2 LT1302 top=1K bot=1T +SYMATTR Description µPower High Output Current Step-up Adjustable DC/DC Converter +PIN -80 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -144 -48 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName It +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 80 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1303-5.asy b/spice/copy/sym/PowerProducts/LT1303-5.asy new file mode 100755 index 0000000..c8210b4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1303-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1303-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1303.sub +SYMATTR Value2 LT1303 top=474K bot=156K +SYMATTR Description µPower High Efficiency DC/DC Converter with Low-Battery Detector, Fixed 5V +PIN -64 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 4 +PIN -144 -80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 64 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1303.asy b/spice/copy/sym/PowerProducts/LT1303.asy new file mode 100755 index 0000000..d187756 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1303.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1303 +SYMATTR Prefix X +SYMATTR SpiceModel LT1303.sub +SYMATTR Value2 LT1303 top=1K bot=1T +SYMATTR Description µPower High Efficiency DC/DC Converter with Low-Battery Detector, adjustable output voltage +PIN -64 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -144 -80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 64 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1304-3.3.asy b/spice/copy/sym/PowerProducts/LT1304-3.3.asy new file mode 100755 index 0000000..08813b3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1304-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1304-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1304.sub +SYMATTR Value2 LT1304 top=590K bot=355K +SYMATTR Description µPower DC/DC Converter with Low-Battery Detector Active in Shutdown, Fixed 3.3V +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 0 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 6 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1304-5.asy b/spice/copy/sym/PowerProducts/LT1304-5.asy new file mode 100755 index 0000000..dd499a2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1304-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 -1 65 Center 2 +SYMATTR Value LT1304-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1304.sub +SYMATTR Value2 LT1304 top=590K bot=194.6K +SYMATTR Description µPower DC/DC Converter with Low-Battery Detector Active in Shutdown, Fixed 5V +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 0 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 6 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1304.asy b/spice/copy/sym/PowerProducts/LT1304.asy new file mode 100755 index 0000000..aedce09 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1304.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1304 +SYMATTR Prefix X +SYMATTR SpiceModel LT1304.sub +SYMATTR Value2 LT1304 top=1K bot=1T +SYMATTR Description µPower DC/DC Converter with Low-Battery Detector Active in Shutdown, Adjustable output voltage +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 0 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 6 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1305.asy b/spice/copy/sym/PowerProducts/LT1305.asy new file mode 100755 index 0000000..6f75e5c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1305.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -55 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1305 +SYMATTR SpiceModel LT1305.sub +SYMATTR Value2 LT1305 +SYMATTR Prefix X +SYMATTR Description µPower High Power DC/DC Converter with Low-Battery Detector +PIN -80 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN 144 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 80 112 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1306.asy b/spice/copy/sym/PowerProducts/LT1306.asy new file mode 100755 index 0000000..533e7e4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1306.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 -32 Center 2 LT +WINDOW 0 -1 -104 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1306 +SYMATTR Prefix X +SYMATTR SpiceModel LT1306.sub +SYMATTR Value2 LT1306 +SYMATTR Description Synchronous, Fixed Frequency Step-Up DC/DC Converter +PIN -160 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 160 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 0 -160 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 -160 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 6 +PIN -112 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -160 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1307.asy b/spice/copy/sym/PowerProducts/LT1307.asy new file mode 100755 index 0000000..e50eaae --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1307.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1307 +SYMATTR Prefix X +SYMATTR SpiceModel LT1307.sub +SYMATTR Value2 LT1307 +SYMATTR Description Single Cell µPower 600kHz PWM DC/DC Converter +PIN -144 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1307b.asy b/spice/copy/sym/PowerProducts/LT1307b.asy new file mode 100755 index 0000000..df0777c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1307b.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 1 1 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1307B +SYMATTR Prefix X +SYMATTR SpiceModel LT1307B.sub +SYMATTR Value2 LT1307B +SYMATTR Description Single Cell µPower 600kHz PWM DC/DC Converter +PIN -144 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1308A.asy b/spice/copy/sym/PowerProducts/LT1308A.asy new file mode 100755 index 0000000..9985a91 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1308A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1308A +SYMATTR Prefix X +SYMATTR SpiceModel LT1308A.sub +SYMATTR Value2 LT1308A +SYMATTR Description High Current, Single Cell µPower 600kHz DC/DC Converter +PIN -144 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1308B.asy b/spice/copy/sym/PowerProducts/LT1308B.asy new file mode 100755 index 0000000..44c9b5e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1308B.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1308B +SYMATTR Prefix X +SYMATTR SpiceModel LT1308B.sub +SYMATTR Value2 LT1308B +SYMATTR Description High Current, Single Cell µPower 600kHz DC/DC Converter +PIN -144 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1309.asy b/spice/copy/sym/PowerProducts/LT1309.asy new file mode 100755 index 0000000..559f0c7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1309.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1309 +SYMATTR Prefix X +SYMATTR SpiceModel LT1309.sub +SYMATTR Value2 LT1309 +SYMATTR Description 500kHz µPower DC/DC Converter for Flash Memory +PIN 176 48 RIGHT 8 +PINATTR PinName SoftStart +PINATTR SpiceOrder 1 +PIN -80 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 80 128 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 3 +PIN 80 -128 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -80 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -176 48 LEFT 8 +PINATTR PinName _VPPOK +PINATTR SpiceOrder 6 +PIN 176 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -176 -48 LEFT 8 +PINATTR PinName ON/OFF +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1310.asy b/spice/copy/sym/PowerProducts/LT1310.asy new file mode 100755 index 0000000..f8d83cb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1310.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT1310 +SYMATTR Prefix X +SYMATTR SpiceModel LT1310.sub +SYMATTR Value2 LT1310 +SYMATTR Description 1.5A Boost DC/DC Converter with Phase-Locked Loop +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -160 80 LEFT 8 +PINATTR PinName PLL-LPF +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 4 +PIN 80 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 80 -160 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -80 160 BOTTOM 8 +PINATTR PinName Ct +PINATTR SpiceOrder 9 +PIN 160 80 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT1316.asy b/spice/copy/sym/PowerProducts/LT1316.asy new file mode 100755 index 0000000..31cb067 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1316.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -89 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1316 +SYMATTR Prefix X +SYMATTR SpiceModel LT1316.sub +SYMATTR Value2 LT1316 +SYMATTR Description µPower DC/DC Converter with Programmable Peak Current Limit +PIN 160 48 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 2 +PIN -80 144 BOTTOM 8 +PINATTR PinName Rset +PINATTR SpiceOrder 3 +PIN 80 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 80 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -80 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 160 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1317.asy b/spice/copy/sym/PowerProducts/LT1317.asy new file mode 100755 index 0000000..7406c38 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1317.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1317 +SYMATTR Prefix X +SYMATTR SpiceModel LT1317.sub +SYMATTR Value2 LT1317 +SYMATTR Description µPower, 600kHz PWM DC/DC Converter +PIN -144 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1317b.asy b/spice/copy/sym/PowerProducts/LT1317b.asy new file mode 100755 index 0000000..6d8c6fd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1317b.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1317B +SYMATTR Prefix X +SYMATTR SpiceModel LT1317B.sub +SYMATTR Value2 LT1317B +SYMATTR Description µPower, 600kHz PWM DC/DC Converter +PIN -144 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1336.asy b/spice/copy/sym/PowerProducts/LT1336.asy new file mode 100755 index 0000000..28ec484 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1336.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -224 224 224 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -127 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value LT1336 +SYMATTR Prefix X +SYMATTR SpiceModel LT1336.sub +SYMATTR Value2 LT1336 +SYMATTR Description Half-Bridge N-Channel Power MOSFET Driver with Boost Regulator +PIN -96 -224 TOP 8 +PINATTR PinName Isense +PINATTR SpiceOrder 1 +PIN -224 -160 LEFT 8 +PINATTR PinName SV+ +PINATTR SpiceOrder 2 +PIN -224 96 LEFT 8 +PINATTR PinName InTop +PINATTR SpiceOrder 3 +PIN -224 160 LEFT 8 +PINATTR PinName InBottom +PINATTR SpiceOrder 4 +PIN -224 32 LEFT 8 +PINATTR PinName _UVOUT +PINATTR SpiceOrder 5 +PIN -144 224 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN 144 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 224 160 RIGHT 8 +PINATTR PinName BgateFB +PINATTR SpiceOrder 8 +PIN 224 96 RIGHT 8 +PINATTR PinName BgateDR +PINATTR SpiceOrder 9 +PIN -224 -96 LEFT 8 +PINATTR PinName PV+ +PINATTR SpiceOrder 10 +PIN 224 32 RIGHT 8 +PINATTR PinName Tsource +PINATTR SpiceOrder 11 +PIN 224 -32 RIGHT 8 +PINATTR PinName TgateFB +PINATTR SpiceOrder 12 +PIN 224 -96 RIGHT 8 +PINATTR PinName TgateDR +PINATTR SpiceOrder 13 +PIN 224 -160 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 14 +PIN 0 224 BOTTOM 8 +PINATTR PinName SWGND +PINATTR SpiceOrder 15 +PIN 96 -224 TOP 8 +PINATTR PinName Switch +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1339.asy b/spice/copy/sym/PowerProducts/LT1339.asy new file mode 100755 index 0000000..f47ef6d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1339.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -256 192 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1339 +SYMATTR Prefix X +SYMATTR SpiceModel LT1339.sub +SYMATTR Value2 LT1339 +SYMATTR Description High Power Synchronous DC/DC Controller +PIN -192 -64 LEFT 8 +PINATTR PinName 5Vref +PINATTR SpiceOrder 2 +PIN -192 64 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 3 +PIN -192 0 LEFT 8 +PINATTR PinName SL/ADJ +PINATTR SpiceOrder 4 +PIN -192 -128 LEFT 8 +PINATTR PinName Iave +PINATTR SpiceOrder 5 +PIN -128 256 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 6 +PIN -192 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN 0 256 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 192 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN 192 128 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 11 +PIN 192 192 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 12 +PIN -192 -192 LEFT 8 +PINATTR PinName Run/SHDN +PINATTR SpiceOrder 13 +PIN 192 -128 RIGHT 8 +PINATTR PinName Phase +PINATTR SpiceOrder 14 +PIN 128 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 15 +PIN 192 64 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 16 +PIN 0 -256 TOP 8 +PINATTR PinName 12Vin +PINATTR SpiceOrder 17 +PIN 192 0 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 18 +PIN 192 -64 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 19 +PIN 192 -192 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT1370.asy b/spice/copy/sym/PowerProducts/LT1370.asy new file mode 100755 index 0000000..dd10552 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1370.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1370 +SYMATTR Prefix X +SYMATTR SpiceModel LT1370.sub +SYMATTR Value2 LT1370 +SYMATTR Description 500kHz High Efficiency 6A Switching Regulator +PIN 80 144 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -80 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 144 80 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1370HV.asy b/spice/copy/sym/PowerProducts/LT1370HV.asy new file mode 100755 index 0000000..92b1051 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1370HV.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1370HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1370.sub +SYMATTR Value2 LT1370 +SYMATTR Description 500kHz High Efficiency 6A Switching Regulator, High Voltage Version +PIN 80 144 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -80 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 144 80 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1371.asy b/spice/copy/sym/PowerProducts/LT1371.asy new file mode 100755 index 0000000..4c723e7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1371.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1371 +SYMATTR Prefix X +SYMATTR SpiceModel LT1371.sub +SYMATTR Value2 LT1371 +SYMATTR Description 500kHz High Efficiency 3A Switching Regulator +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1371HV.asy b/spice/copy/sym/PowerProducts/LT1371HV.asy new file mode 100755 index 0000000..86b279c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1371HV.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1371HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1371.sub +SYMATTR Value2 LT1371 +SYMATTR Description 500kHz High Efficiency 3A Switching Regulator(High Voltage version) +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1372.asy b/spice/copy/sym/PowerProducts/LT1372.asy new file mode 100755 index 0000000..b951104 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1372.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1372 +SYMATTR Prefix X +SYMATTR SpiceModel LT1372.sub +SYMATTR Value2 LT1372 +SYMATTR Description 1.5A, 500kHz High Efficiency Step-Down Switching Regulator, Adjustable Output Voltage +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1372HV.asy b/spice/copy/sym/PowerProducts/LT1372HV.asy new file mode 100755 index 0000000..365c292 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1372HV.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1372HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1372.sub +SYMATTR Value2 LT1372 +SYMATTR Description 1.5A, 500kHz High Efficiency Step-Down Switching Regulator, Adjustable Output Voltage(High Voltage version) +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1373.asy b/spice/copy/sym/PowerProducts/LT1373.asy new file mode 100755 index 0000000..79d61b8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1373.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -81 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1373 +SYMATTR Prefix X +SYMATTR SpiceModel LT1373.sub +SYMATTR Value2 LT1373 +SYMATTR Description 250kHz Low Supply Current High Efficiency 1.5A Switching Regulator, Adjustable Output Voltage +PIN 144 96 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 -32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 32 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -80 160 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN 80 160 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1373HV.asy b/spice/copy/sym/PowerProducts/LT1373HV.asy new file mode 100755 index 0000000..593841d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1373HV.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1373HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1373.sub +SYMATTR Value2 LT1373 +SYMATTR Description 250kHz Low Supply Current High Efficiency 1.5A Switching Regulator, Adjustable Output Voltage +PIN 144 96 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 -32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 32 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -80 160 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN 80 160 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1374-5.asy b/spice/copy/sym/PowerProducts/LT1374-5.asy new file mode 100755 index 0000000..9993dca --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1374-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1374-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1374.sub +SYMATTR Value2 LT1374 top=5.36K bot=4.99K +SYMATTR Description 4.5A, 500KHz Step-Down Switching Regulator, Fixed 5Volt Output +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 64 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 32 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 -32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 5 +PIN 160 96 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -160 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1374.asy b/spice/copy/sym/PowerProducts/LT1374.asy new file mode 100755 index 0000000..b27999d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1374.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1374 +SYMATTR Prefix X +SYMATTR SpiceModel LT1374.sub +SYMATTR Value2 LT1374 top=10 bot=1T +SYMATTR Description 4.5A, 500KHz Step-Down Switching Regulator +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 64 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 -32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 5 +PIN 160 96 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -160 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1374HV-5.asy b/spice/copy/sym/PowerProducts/LT1374HV-5.asy new file mode 100755 index 0000000..7d91008 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1374HV-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1374HV-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1374.sub +SYMATTR Value2 LT1374 top=5.36K bot=4.99K +SYMATTR Description 4.5A, 500KHz Step-Down Switching Regulator, Fixed 5Volt Output +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 64 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 32 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 -32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 5 +PIN 160 96 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -160 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1374HV.asy b/spice/copy/sym/PowerProducts/LT1374HV.asy new file mode 100755 index 0000000..763b4f1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1374HV.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1374HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1374.sub +SYMATTR Value2 LT1374 top=10 bot=1T +SYMATTR Description 4.5A, 500KHz Step-Down Switching Regulator, High Voltage Version +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 64 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 -32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 5 +PIN 160 96 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -160 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1375-5.asy b/spice/copy/sym/PowerProducts/LT1375-5.asy new file mode 100755 index 0000000..6bd2523 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1375-5.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 -1 48 Center 2 +SYMATTR Value LT1375-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1375.sub +SYMATTR Value2 LT1375 top=5.36K bot=5K +SYMATTR Description 1.5A, 500kHz Step-Down Switching Regulator, Fixed 5V Output +PIN 64 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1375.asy b/spice/copy/sym/PowerProducts/LT1375.asy new file mode 100755 index 0000000..56e60e2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1375.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -49 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1375 +SYMATTR Prefix X +SYMATTR SpiceModel LT1375.sub +SYMATTR Value2 LT1375 top=1K bot=1T +SYMATTR Description 1.5A, 500kHz Step-Down Switching Regulator, Adjustable Output Voltage +PIN 64 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1375HV.asy b/spice/copy/sym/PowerProducts/LT1375HV.asy new file mode 100755 index 0000000..78e2fb1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1375HV.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1375HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1375.sub +SYMATTR Value2 LT1375 top=1K bot=1T +SYMATTR Description 1.5A, 500kHz Step-Down Switching Regulator, Adjustable Output Voltage +PIN 64 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1376-5.asy b/spice/copy/sym/PowerProducts/LT1376-5.asy new file mode 100755 index 0000000..03207de --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1376-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1376-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1376.sub +SYMATTR Value2 LT1376 top=5.36K bot=4.99K +SYMATTR Description 1.5A, 500kHz Step-Down Switching Regulator, Fixed 5V Output +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 4 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1376.asy b/spice/copy/sym/PowerProducts/LT1376.asy new file mode 100755 index 0000000..def325d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1376.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1376 +SYMATTR Prefix X +SYMATTR SpiceModel LT1376.sub +SYMATTR Value2 LT1376 top=10 bot=1T +SYMATTR Description 1.5A, 500kHz Step-Down Switching Regulator, Adjustable Output Voltage +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 4 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1376HV.asy b/spice/copy/sym/PowerProducts/LT1376HV.asy new file mode 100755 index 0000000..e8bc3ef --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1376HV.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1376HV +SYMATTR Prefix X +SYMATTR SpiceModel LT1376.sub +SYMATTR Value2 LT1376 top=10 bot=1T +SYMATTR Description 1.5A, 500kHz Step-Down Switching Regulator, Adjustable Output Voltage +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 4 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1377.asy b/spice/copy/sym/PowerProducts/LT1377.asy new file mode 100755 index 0000000..e8e854b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1377.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1377 +SYMATTR Prefix X +SYMATTR SpiceModel LT1377.sub +SYMATTR Value2 LT1377 +SYMATTR Description 1.5A, 1MHz High Efficiency Step-Down Switching Regulator, Adjustable Output Voltage +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1424-5.asy b/spice/copy/sym/PowerProducts/LT1424-5.asy new file mode 100755 index 0000000..89735a4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1424-5.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT1424-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1424-5.sub +SYMATTR Value2 LT1424-5 +SYMATTR Description Isolated Flyback Switching Regulator with 5V Output +PIN -160 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -96 144 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 96 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 5 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 160 48 RIGHT 8 +PINATTR PinName Rccomp +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1424-9.asy b/spice/copy/sym/PowerProducts/LT1424-9.asy new file mode 100755 index 0000000..02534f1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1424-9.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1424-9 +SYMATTR Prefix X +SYMATTR SpiceModel LT1424-9.sub +SYMATTR Value2 LT1424-9 +SYMATTR Description Isolated Flyback Switching Regulator with 9V Output +PIN -160 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -96 144 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 96 144 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 5 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 160 48 RIGHT 8 +PINATTR PinName Rccomp +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1425.asy b/spice/copy/sym/PowerProducts/LT1425.asy new file mode 100755 index 0000000..65b51ec --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1425.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -176 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1425 +SYMATTR Prefix X +SYMATTR SpiceModel LT1425.sub +SYMATTR Value2 LT1425 +SYMATTR Description Isolated Flyback Switching Regulator +PIN 176 0 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 3 +PIN -176 -32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 4 +PIN 176 80 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 5 +PIN -80 176 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 7 +PIN 80 176 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 11 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN -176 96 LEFT 8 +PINATTR PinName Rccomp +PINATTR SpiceOrder 13 +PIN -176 32 LEFT 8 +PINATTR PinName Rocomp +PINATTR SpiceOrder 14 +PIN -176 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT1432-3.3.asy b/spice/copy/sym/PowerProducts/LT1432-3.3.asy new file mode 100755 index 0000000..2b8fcdd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1432-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -144 176 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1432-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1432-3.3.sub +SYMATTR Value2 LT1432-3.3 +SYMATTR Description 3.3V High Efficiency Step-Down Switching Regulator Controller +PIN 176 -48 RIGHT 8 +PINATTR PinName Vlim +PINATTR SpiceOrder 1 +PIN 176 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -176 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 112 -144 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Diode +PINATTR SpiceOrder 5 +PIN -112 -144 TOP 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -176 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1432.asy b/spice/copy/sym/PowerProducts/LT1432.asy new file mode 100755 index 0000000..bf8b1c4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1432.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -144 176 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -70 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT1432 +SYMATTR Prefix X +SYMATTR SpiceModel LT1432.sub +SYMATTR Value2 LT1432 +SYMATTR Description 5V High Efficiency Step-Down Switching Regulator Controller +PIN 176 -48 RIGHT 8 +PINATTR PinName Vlim +PINATTR SpiceOrder 1 +PIN 176 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -176 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 112 -144 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Diode +PINATTR SpiceOrder 5 +PIN -112 -144 TOP 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -176 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1461-2.5.asy b/spice/copy/sym/PowerProducts/LT1461-2.5.asy new file mode 100755 index 0000000..a908fc1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1461-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT1461-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1461.lib +SYMATTR Value2 LT1461-2.5 +SYMATTR Description µPower Precision Low Dropout Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LT1461-3.3.asy b/spice/copy/sym/PowerProducts/LT1461-3.3.asy new file mode 100755 index 0000000..bee9d34 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1461-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT1461-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1461.lib +SYMATTR Value2 LT1461-3.3 +SYMATTR Description µPower Precision Low Dropout Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LT1461-3.asy b/spice/copy/sym/PowerProducts/LT1461-3.asy new file mode 100755 index 0000000..2db0ec5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1461-3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT1461-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1461.lib +SYMATTR Value2 LT1461-3 +SYMATTR Description µPower Precision Low Dropout Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LT1461-4.096.asy b/spice/copy/sym/PowerProducts/LT1461-4.096.asy new file mode 100755 index 0000000..60ae706 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1461-4.096.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT1461-4.096 +SYMATTR Prefix X +SYMATTR SpiceModel LT1461.lib +SYMATTR Value2 LT1461-4.096 +SYMATTR Description µPower Precision Low Dropout Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LT1461-5.asy b/spice/copy/sym/PowerProducts/LT1461-5.asy new file mode 100755 index 0000000..c78bef4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1461-5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT1461-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1461.lib +SYMATTR Value2 LT1461-5 +SYMATTR Description µPower Precision Low Dropout Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LT1500-3.asy b/spice/copy/sym/PowerProducts/LT1500-3.asy new file mode 100755 index 0000000..89d23f8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1500-3.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -208 208 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1500-3/5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1500-3.sub +SYMATTR Value2 LT1500-3 +SYMATTR Description Adaptive-Frequency Current-Mode Switching Regulator, Selectable 3.3V or 5V Output +PIN -208 -128 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -208 48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -96 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 96 -208 TOP 8 +PINATTR PinName Isense +PINATTR SpiceOrder 4 +PIN -96 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 96 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 208 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN -208 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 9 +PIN 208 -64 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 10 +PIN -208 -48 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 11 +PIN 208 128 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 208 64 RIGHT 8 +PINATTR PinName SEL3.3/5 +PINATTR SpiceOrder 13 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT1500.asy b/spice/copy/sym/PowerProducts/LT1500.asy new file mode 100755 index 0000000..ac3bc44 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1500.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -208 208 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1500 +SYMATTR Prefix X +SYMATTR SpiceModel LT1500.sub +SYMATTR Value2 LT1500 +SYMATTR Description Adaptive-Frequency Current-Mode Switching Regulator, Adjustable Output Voltage +PIN -208 -128 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -208 48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -96 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 96 -208 TOP 8 +PINATTR PinName Isense +PINATTR SpiceOrder 4 +PIN -96 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 96 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 208 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN -208 128 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 9 +PIN 208 -64 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 10 +PIN -208 -48 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 11 +PIN 208 128 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 208 64 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 13 +PIN 208 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT1501-3.3.asy b/spice/copy/sym/PowerProducts/LT1501-3.3.asy new file mode 100755 index 0000000..0bd5a77 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1501-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT1501-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1501-3.3.sub +SYMATTR Value2 LT1501-3.3 +SYMATTR Description Adaptive-Frequency Current-Mode Switching Regulator, Fixed 3.3V Output +PIN -176 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -80 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 80 -128 TOP 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 176 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 176 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 6 +PIN -176 48 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 176 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1501-5.asy b/spice/copy/sym/PowerProducts/LT1501-5.asy new file mode 100755 index 0000000..17c212e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1501-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 1 72 Center 2 +SYMATTR Value LT1501-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1501-5.sub +SYMATTR Value2 LT1501-5 +SYMATTR Description Adaptive-Frequency Current-Mode Switching Regulator, Fixed 5V Output +PIN -176 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -80 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 80 -128 TOP 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 176 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 176 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 6 +PIN -176 48 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 176 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1501.asy b/spice/copy/sym/PowerProducts/LT1501.asy new file mode 100755 index 0000000..b50faea --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1501.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT1501 +SYMATTR Prefix X +SYMATTR SpiceModel LT1501.sub +SYMATTR Value2 LT1501 +SYMATTR Description Adaptive-Frequency Current-Mode Switching Regulator, Adjustable Output Voltage +PIN -176 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -80 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 80 -128 TOP 8 +PINATTR PinName Isense +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 176 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 176 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 6 +PIN -176 48 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 176 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1505-1.asy b/spice/copy/sym/PowerProducts/LT1505-1.asy new file mode 100755 index 0000000..d1ccbc8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1505-1.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -416 256 416 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -200 Center 2 +WINDOW 3 8 120 Center 2 +SYMATTR Value LT1505-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT1505-1.sub +SYMATTR Value2 LT1505-1 +SYMATTR Description Constant-Current/Voltage High Efficiency Battery Charger +PIN 0 -416 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN 256 -288 RIGHT 8 +PINATTR PinName Tgate +PINATTR SpiceOrder 2 +PIN 256 -224 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -256 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 256 288 RIGHT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 6 +PIN -256 -96 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 7 +PIN -256 -160 LEFT 8 +PINATTR PinName INFET +PINATTR SpiceOrder 8 +PIN -256 224 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN -256 160 LEFT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 12 +PIN -256 96 LEFT 8 +PINATTR PinName _FLAG +PINATTR SpiceOrder 13 +PIN 256 224 RIGHT 8 +PINATTR PinName 4.1V +PINATTR SpiceOrder 14 +PIN 256 160 RIGHT 8 +PINATTR PinName 4.2V +PINATTR SpiceOrder 15 +PIN 256 32 RIGHT 8 +PINATTR PinName 3 Cell +PINATTR SpiceOrder 16 +PIN 256 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 17 +PIN 256 -96 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 18 +PIN 256 -32 RIGHT 8 +PINATTR PinName Prog +PINATTR SpiceOrder 19 +PIN -192 416 BOTTOM 8 +PINATTR PinName BAT2 +PINATTR SpiceOrder 20 +PIN 64 416 BOTTOM 8 +PINATTR PinName Sense +PINATTR SpiceOrder 21 +PIN 192 416 BOTTOM 8 +PINATTR PinName SPIN +PINATTR SpiceOrder 22 +PIN -64 416 BOTTOM 8 +PINATTR PinName BAT +PINATTR SpiceOrder 23 +PIN -160 -416 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 24 +PIN 160 -416 TOP 8 +PINATTR PinName BoostC +PINATTR SpiceOrder 25 +PIN 256 -352 RIGHT 8 +PINATTR PinName Gbias +PINATTR SpiceOrder 26 +PIN 256 -160 RIGHT 8 +PINATTR PinName Bgate +PINATTR SpiceOrder 27 +PIN 256 352 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT1505.asy b/spice/copy/sym/PowerProducts/LT1505.asy new file mode 100755 index 0000000..3d1d4f3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1505.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -416 256 416 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -200 Center 2 +WINDOW 3 8 120 Center 2 +SYMATTR Value LT1505 +SYMATTR Prefix X +SYMATTR SpiceModel LT1505.sub +SYMATTR Value2 LT1505 +SYMATTR Description Constant-Current/Voltage High Efficiency Battery Charger +PIN 0 -416 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN 256 -288 RIGHT 8 +PINATTR PinName Tgate +PINATTR SpiceOrder 2 +PIN 256 -224 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -256 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 256 288 RIGHT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 6 +PIN -256 -96 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 7 +PIN -256 -160 LEFT 8 +PINATTR PinName INFET +PINATTR SpiceOrder 8 +PIN -256 -224 LEFT 8 +PINATTR PinName CLP +PINATTR SpiceOrder 9 +PIN -256 -288 LEFT 8 +PINATTR PinName CLN +PINATTR SpiceOrder 10 +PIN -256 224 LEFT 8 +PINATTR PinName COMP1 +PINATTR SpiceOrder 11 +PIN -256 160 LEFT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 12 +PIN -256 96 LEFT 8 +PINATTR PinName _FLAG +PINATTR SpiceOrder 13 +PIN 256 224 RIGHT 8 +PINATTR PinName 4.1V +PINATTR SpiceOrder 14 +PIN 256 160 RIGHT 8 +PINATTR PinName 4.2V +PINATTR SpiceOrder 15 +PIN 256 32 RIGHT 8 +PINATTR PinName 3 Cell +PINATTR SpiceOrder 16 +PIN 256 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 17 +PIN 256 -96 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 18 +PIN 256 -32 RIGHT 8 +PINATTR PinName Prog +PINATTR SpiceOrder 19 +PIN -192 416 BOTTOM 8 +PINATTR PinName BAT2 +PINATTR SpiceOrder 20 +PIN 64 416 BOTTOM 8 +PINATTR PinName Sense +PINATTR SpiceOrder 21 +PIN 192 416 BOTTOM 8 +PINATTR PinName SPIN +PINATTR SpiceOrder 22 +PIN -64 416 BOTTOM 8 +PINATTR PinName BAT +PINATTR SpiceOrder 23 +PIN -160 -416 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 24 +PIN 160 -416 TOP 8 +PINATTR PinName BoostC +PINATTR SpiceOrder 25 +PIN 256 -352 RIGHT 8 +PINATTR PinName Gbias +PINATTR SpiceOrder 26 +PIN 256 -160 RIGHT 8 +PINATTR PinName Bgate +PINATTR SpiceOrder 27 +PIN 256 352 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT1506-3.3.asy b/spice/copy/sym/PowerProducts/LT1506-3.3.asy new file mode 100755 index 0000000..b3af842 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1506-3.3.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1506-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1506.sub +SYMATTR Value2 LT1506 top=1.82K bot=4.99K +SYMATTR Description 4.5A, 500KHz Step-Down Switching Regulator, Fixed 3.3V Output +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -160 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 5 +PIN -160 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 160 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1506.asy b/spice/copy/sym/PowerProducts/LT1506.asy new file mode 100755 index 0000000..d6e4e3d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1506.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1506 +SYMATTR Prefix X +SYMATTR SpiceModel LT1506.sub +SYMATTR Value2 LT1506 top=10 bot=1T +SYMATTR Description 4.5A, 500KHz Step-Down Switching Regulator, Adjustable Output Voltage +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -160 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 5 +PIN -160 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 160 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1507-3.3.asy b/spice/copy/sym/PowerProducts/LT1507-3.3.asy new file mode 100755 index 0000000..095ebf1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1507-3.3.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 8 32 Center 2 +SYMATTR Value LT1507-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1507.sub +SYMATTR Value2 LT1507 top=1.815K bot=4.99K +SYMATTR Description 500kHz Monolithic Buck Mode Switching Regulator, Fixed 3.3V Output Voltage +PIN 80 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -80 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1507.asy b/spice/copy/sym/PowerProducts/LT1507.asy new file mode 100755 index 0000000..386d655 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1507.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 8 32 Center 2 +SYMATTR Value LT1507 +SYMATTR Prefix X +SYMATTR SpiceModel LT1507.sub +SYMATTR Value2 LT1507 top=1K bot=1T +SYMATTR Description 500kHz Monolithic Buck Mode Switching Regulator, Adjustable Output Voltage +PIN 80 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -80 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1508.asy b/spice/copy/sym/PowerProducts/LT1508.asy new file mode 100755 index 0000000..68f0d84 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1508.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -320 224 320 +TEXT 0 -80 Center 2 LT +WINDOW 0 0 -200 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1508 +SYMATTR Prefix X +SYMATTR SpiceModel LT1508.sub +SYMATTR Value2 LT1508 +SYMATTR Description Power Factor and PWM Controller(Voltage Mode) +PIN 224 80 RIGHT 8 +PINATTR PinName GTDR1 +PINATTR SpiceOrder 1 +PIN 64 320 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 2 +PIN -64 320 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN -224 160 LEFT 8 +PINATTR PinName Cset +PINATTR SpiceOrder 4 +PIN -224 -240 LEFT 8 +PINATTR PinName PKlim +PINATTR SpiceOrder 5 +PIN -224 0 LEFT 8 +PINATTR PinName CAout +PINATTR SpiceOrder 6 +PIN -224 -80 LEFT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 7 +PIN -96 -320 TOP 8 +PINATTR PinName Mout +PINATTR SpiceOrder 8 +PIN 96 -320 TOP 8 +PINATTR PinName Iac +PINATTR SpiceOrder 9 +PIN 224 -160 RIGHT 8 +PINATTR PinName VAout +PINATTR SpiceOrder 10 +PIN 224 0 RIGHT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 11 +PIN -224 -160 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 12 +PIN 176 320 BOTTOM 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 13 +PIN 224 -80 RIGHT 8 +PINATTR PinName Vsense +PINATTR SpiceOrder 14 +PIN -224 80 LEFT 8 +PINATTR PinName Rset +PINATTR SpiceOrder 15 +PIN -176 320 BOTTOM 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 16 +PIN 224 -240 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 17 +PIN -224 240 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 18 +PIN 224 240 RIGHT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 19 +PIN 224 160 RIGHT 8 +PINATTR PinName GTDR2 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT1509.asy b/spice/copy/sym/PowerProducts/LT1509.asy new file mode 100755 index 0000000..31a4600 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1509.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -320 224 320 +TEXT 0 -80 Center 2 LT +WINDOW 0 0 -200 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1509 +SYMATTR Prefix X +SYMATTR SpiceModel LT1509.sub +SYMATTR Value2 LT1509 +SYMATTR Description Power Factor and PWM Controller +PIN 224 80 RIGHT 8 +PINATTR PinName GTDR1 +PINATTR SpiceOrder 1 +PIN 64 320 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 2 +PIN -64 320 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN -224 160 LEFT 8 +PINATTR PinName Cset +PINATTR SpiceOrder 4 +PIN -224 -240 LEFT 8 +PINATTR PinName PKlim +PINATTR SpiceOrder 5 +PIN -224 0 LEFT 8 +PINATTR PinName CAout +PINATTR SpiceOrder 6 +PIN -224 -80 LEFT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 7 +PIN -96 -320 TOP 8 +PINATTR PinName Mout +PINATTR SpiceOrder 8 +PIN 96 -320 TOP 8 +PINATTR PinName Iac +PINATTR SpiceOrder 9 +PIN 224 -160 RIGHT 8 +PINATTR PinName VAout +PINATTR SpiceOrder 10 +PIN 224 0 RIGHT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 11 +PIN -224 -160 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 12 +PIN 176 320 BOTTOM 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 13 +PIN 224 -80 RIGHT 8 +PINATTR PinName Vsense +PINATTR SpiceOrder 14 +PIN -224 80 LEFT 8 +PINATTR PinName Rset +PINATTR SpiceOrder 15 +PIN -176 320 BOTTOM 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 16 +PIN 224 -240 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 17 +PIN -224 240 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 18 +PIN 224 240 RIGHT 8 +PINATTR PinName RAMP +PINATTR SpiceOrder 19 +PIN 224 160 RIGHT 8 +PINATTR PinName GTDR2 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT1510-5.asy b/spice/copy/sym/PowerProducts/LT1510-5.asy new file mode 100755 index 0000000..a2deb74 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1510-5.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -65 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1510-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1510-5.sub +SYMATTR Value2 LT1510-5 +SYMATTR Description 500KHz Constant-Voltage/Constant-Current Battery Charger +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 3 +PIN 144 -32 RIGHT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 5 +PIN -144 -96 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 10 +PIN 144 32 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN 144 96 RIGHT 8 +PINATTR PinName Prog +PINATTR SpiceOrder 13 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT1510.asy b/spice/copy/sym/PowerProducts/LT1510.asy new file mode 100755 index 0000000..26e73fb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1510.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1510 +SYMATTR Prefix X +SYMATTR SpiceModel LT1510.sub +SYMATTR Value2 LT1510 +SYMATTR Description Constant-Voltage/Constant-Current Battery Charger +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 3 +PIN 144 -32 RIGHT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 5 +PIN -144 -96 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 10 +PIN 144 32 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN 144 96 RIGHT 8 +PINATTR PinName Prog +PINATTR SpiceOrder 13 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT1512.asy b/spice/copy/sym/PowerProducts/LT1512.asy new file mode 100755 index 0000000..4db3025 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1512.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1512 +SYMATTR Prefix X +SYMATTR SpiceModel LT1512.sub +SYMATTR Value2 LT1512 +SYMATTR Description SEPIC Constant-Current/Constant Voltage Battery Charger +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName IFB +PINATTR SpiceOrder 3 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -80 160 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN 80 160 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1513-2.asy b/spice/copy/sym/PowerProducts/LT1513-2.asy new file mode 100755 index 0000000..3fbb9ed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1513-2.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1513-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT1513-2.sub +SYMATTR Value2 LT1513-2 +SYMATTR Description SEPIC Constant- or Constant Current/Constant Voltage Battery Charger +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName IFB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1513.asy b/spice/copy/sym/PowerProducts/LT1513.asy new file mode 100755 index 0000000..6154950 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1513.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1513 +SYMATTR Prefix X +SYMATTR SpiceModel LT1513.sub +SYMATTR Value2 LT1513 +SYMATTR Description SEPIC Constant- or Constant Current/Constant Voltage Battery Charger +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName IFB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1521-3.3.asy b/spice/copy/sym/PowerProducts/LT1521-3.3.asy new file mode 100755 index 0000000..143453e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1521-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -73 Center 2 +WINDOW 3 20 125 Left 2 +SYMATTR Value LT1521-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1521.lib +SYMATTR Value2 LT1521-3.3 +SYMATTR Description 300mA Low Dropout Regulator with µPower Quiescent Current and Shutdown, Fixed 3.3V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1521-3.asy b/spice/copy/sym/PowerProducts/LT1521-3.asy new file mode 100755 index 0000000..54f65f0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1521-3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 20 125 Left 2 +SYMATTR Value LT1521-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1521.lib +SYMATTR Value2 LT1521-3 +SYMATTR Description 300mA Low Dropout Regulator with µPower Quiescent Current and Shutdown, Fixed 3V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1521-5.asy b/spice/copy/sym/PowerProducts/LT1521-5.asy new file mode 100755 index 0000000..7e88571 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1521-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 20 125 Left 2 +SYMATTR Value LT1521-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1521.lib +SYMATTR Value2 LT1521-5 +SYMATTR Description 300mA Low Dropout Regulator with µPower Quiescent Current and Shutdown, Fixed 5V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1521.asy b/spice/copy/sym/PowerProducts/LT1521.asy new file mode 100755 index 0000000..a43c3a9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1521.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -73 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1521 +SYMATTR Prefix X +SYMATTR SpiceModel LT1521.lib +SYMATTR Value2 LT1521 +SYMATTR Description 300mA Low Dropout Regulator with µPower Quiescent Current and Shutdown, Adjustable Output Voltage +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 64 112 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN -64 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1528.asy b/spice/copy/sym/PowerProducts/LT1528.asy new file mode 100755 index 0000000..252215a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1528.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 62 Center 2 +SYMATTR Value LT1528 +SYMATTR Prefix X +SYMATTR SpiceModel LT1528.lib +SYMATTR Value2 LT1528 +SYMATTR Description 3A Low Dropout Regulator for µProcessor Applications +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1529-3.3.asy b/spice/copy/sym/PowerProducts/LT1529-3.3.asy new file mode 100755 index 0000000..80fdaf4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1529-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 12 125 Left 2 +SYMATTR Value LT1529-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1529.lib +SYMATTR Value2 LT1529-3.3 +SYMATTR Description 3A Low Dropout Regulator with µPower Quiescent Current and Shutdown, Fixed 3.3V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1529-5.asy b/spice/copy/sym/PowerProducts/LT1529-5.asy new file mode 100755 index 0000000..b66465e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1529-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -72 Center 2 +WINDOW 3 12 125 Left 2 +SYMATTR Value LT1529-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1529.lib +SYMATTR Value2 LT1529-5 +SYMATTR Description 3A Low Dropout Regulator with µPower Quiescent Current and Shutdown, Fixed 5V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1529.asy b/spice/copy/sym/PowerProducts/LT1529.asy new file mode 100755 index 0000000..6d611f6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1529.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1529 +SYMATTR Prefix X +SYMATTR SpiceModel LT1529.lib +SYMATTR Value2 LT1529 +SYMATTR Description 3A Low Dropout Regulator with µPower Quiescent Current and Shutdown, Adjustable Output Voltage +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 64 112 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN -64 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1533.asy b/spice/copy/sym/PowerProducts/LT1533.asy new file mode 100755 index 0000000..676e9b5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1533.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -272 144 272 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT1533 +SYMATTR Prefix X +SYMATTR SpiceModel LT1533.sub +SYMATTR Value2 LT1533 +SYMATTR Description Ultralow Noise 1A Switching Regulator +PIN -144 -160 LEFT 8 +PINATTR PinName COLB +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 5 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -144 160 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -144 224 LEFT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 8 +PIN 144 224 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 144 160 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN 144 32 RIGHT 8 +PINATTR PinName RCSL +PINATTR SpiceOrder 12 +PIN 144 -32 RIGHT 8 +PINATTR PinName RVSL +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 14 +PIN 144 -160 RIGHT 8 +PINATTR PinName COLA +PINATTR SpiceOrder 15 +PIN 144 -224 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1534-1.asy b/spice/copy/sym/PowerProducts/LT1534-1.asy new file mode 100755 index 0000000..6eb6d23 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1534-1.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1534-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT1534-1.sub +SYMATTR Value2 LT1534-1 +SYMATTR Description Ultralow Noise 2A Switching Regulator +PIN 160 -128 RIGHT 8 +PINATTR PinName COL +PINATTR SpiceOrder 2 +PIN -160 -64 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -160 128 LEFT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 8 +PIN -80 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -160 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 +PIN -160 -128 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN 160 64 RIGHT 8 +PINATTR PinName RCSL +PINATTR SpiceOrder 12 +PIN 160 0 RIGHT 8 +PINATTR PinName RVSL +PINATTR SpiceOrder 13 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 14 +PIN 80 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1534.asy b/spice/copy/sym/PowerProducts/LT1534.asy new file mode 100755 index 0000000..611895f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1534.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1534 +SYMATTR Prefix X +SYMATTR SpiceModel LT1534.sub +SYMATTR Value2 LT1534 +SYMATTR Description Ultralow Noise 2A Switching Regulator +PIN 160 -64 RIGHT 8 +PINATTR PinName COL +PINATTR SpiceOrder 2 +PIN -160 -64 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -160 128 LEFT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 8 +PIN -80 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -160 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 +PIN -160 -128 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN 160 64 RIGHT 8 +PINATTR PinName RCSL +PINATTR SpiceOrder 12 +PIN 160 0 RIGHT 8 +PINATTR PinName RVSL +PINATTR SpiceOrder 13 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 14 +PIN 160 -128 RIGHT 8 +PINATTR PinName COL +PINATTR SpiceOrder 15 +PIN 80 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1572.asy b/spice/copy/sym/PowerProducts/LT1572.asy new file mode 100755 index 0000000..7c445c4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1572.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -144 176 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT1572 +SYMATTR Prefix X +SYMATTR SpiceModel LT1572.sub +SYMATTR Value2 LT1572 +SYMATTR Description 100kHz, 1.25A High Efficiency Switching Regulator with Catch Diode +PIN -176 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 176 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 0 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 112 -144 TOP 8 +PINATTR PinName Anode +PINATTR SpiceOrder 6 +PIN 176 -64 RIGHT 8 +PINATTR PinName Cathode +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1573.asy b/spice/copy/sym/PowerProducts/LT1573.asy new file mode 100755 index 0000000..34bde56 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1573.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -79 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT1573 +SYMATTR Prefix X +SYMATTR SpiceModel LT1573.lib +SYMATTR Value2 LT1573 +SYMATTR Description Low Dropout PNP Regulator Driver +PIN -144 -144 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Latch +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1575-1.5.asy b/spice/copy/sym/PowerProducts/LT1575-1.5.asy new file mode 100755 index 0000000..3dbb7a0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1575-1.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 8 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1575-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1575.lib +SYMATTR Value2 LT1575-1.5 +SYMATTR Description Ultrafast Transient Response, Low Dropout Regulator, Fixed Output Voltage +PIN -144 -144 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1575-2.8.asy b/spice/copy/sym/PowerProducts/LT1575-2.8.asy new file mode 100755 index 0000000..bb498bc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1575-2.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 8 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1575-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1575.lib +SYMATTR Value2 LT1575-2.8 +SYMATTR Description Ultrafast Transient Response, Low Dropout Regulator, Fixed Output Voltage +PIN -144 -144 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1575-3.3.asy b/spice/copy/sym/PowerProducts/LT1575-3.3.asy new file mode 100755 index 0000000..b07719a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1575-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 8 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1575-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1575.lib +SYMATTR Value2 LT1575-3.3 +SYMATTR Description Ultrafast Transient Response, Low Dropout Regulator, Fixed Output Voltage +PIN -144 -144 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1575-3.5.asy b/spice/copy/sym/PowerProducts/LT1575-3.5.asy new file mode 100755 index 0000000..4bbf14e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1575-3.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 8 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1575-3.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1575.lib +SYMATTR Value2 LT1575-3.5 +SYMATTR Description Ultrafast Transient Response, Low Dropout Regulator, Fixed Output Voltage +PIN -144 -144 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1575-5.asy b/spice/copy/sym/PowerProducts/LT1575-5.asy new file mode 100755 index 0000000..4a9c272 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1575-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 8 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1575-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1575.lib +SYMATTR Value2 LT1575-5 +SYMATTR Description Ultrafast Transient Response, Low Dropout Regulator, Fixed Output Voltage +PIN -144 -144 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1575.asy b/spice/copy/sym/PowerProducts/LT1575.asy new file mode 100755 index 0000000..93b01c7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1575.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 8 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1575 +SYMATTR Prefix X +SYMATTR SpiceModel LT1575.lib +SYMATTR Value2 LT1575 +SYMATTR Description Ultrafast Transient Response, Low Dropout Regulator, Adjustable Output Voltage +PIN -144 -144 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1576-5.asy b/spice/copy/sym/PowerProducts/LT1576-5.asy new file mode 100755 index 0000000..f9e264b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1576-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1576-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1576.sub +SYMATTR Value2 LT1576 top=15.8K bot=4.98K +SYMATTR Description 1.5A, 200kHz Step-Down Switching Regulator, Fixed 5V Output +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1576.asy b/spice/copy/sym/PowerProducts/LT1576.asy new file mode 100755 index 0000000..3265679 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1576.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1576 +SYMATTR Prefix X +SYMATTR SpiceModel LT1576.sub +SYMATTR Value2 LT1576 top=10 bot=1T +SYMATTR Description 1.5A, 200kHz Step-Down Switching Regulator, Adjustable Output Voltage +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1577-2.8.asy b/spice/copy/sym/PowerProducts/LT1577-2.8.asy new file mode 100755 index 0000000..d598352 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1577-2.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 8 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1577-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1575.lib +SYMATTR Value2 LT1575-2.8 +SYMATTR Description Ultrafast Transient Response, Low Dropout Regulator, Fixed Output Voltage +PIN -144 -144 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1577-3.3.asy b/spice/copy/sym/PowerProducts/LT1577-3.3.asy new file mode 100755 index 0000000..b42af4a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1577-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 8 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1577-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1575.lib +SYMATTR Value2 LT1575-3.3 +SYMATTR Description Ultrafast Transient Response, Low Dropout Regulator, Fixed Output Voltage +PIN -144 -144 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1577-ADJ.asy b/spice/copy/sym/PowerProducts/LT1577-ADJ.asy new file mode 100755 index 0000000..a6b7589 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1577-ADJ.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 8 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1577-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel LT1575.lib +SYMATTR Value2 LT1575 +SYMATTR Description Ultrafast Transient Response, Low Dropout Regulator, Adjustable Output Voltage +PIN -144 -144 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1578-2.5.asy b/spice/copy/sym/PowerProducts/LT1578-2.5.asy new file mode 100755 index 0000000..03e0862 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1578-2.5.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 44 Center 2 +SYMATTR Value LT1578-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1578-2.5.sub +SYMATTR Value2 LT1578-2.5 +SYMATTR Description 1.5A, 200kHz Step-Down Switching Regulator, Fixed 2.5V Output +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 5 +PIN 144 80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1578.asy b/spice/copy/sym/PowerProducts/LT1578.asy new file mode 100755 index 0000000..f00e61b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1578.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1578 +SYMATTR Prefix X +SYMATTR SpiceModel LT1578.sub +SYMATTR Value2 LT1578 +SYMATTR Description 1.5A, 200kHz Step-Down Switching Regulator, Adjustable Output Voltage +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 5 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1580-2.5.asy b/spice/copy/sym/PowerProducts/LT1580-2.5.asy new file mode 100755 index 0000000..e7beb1c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1580-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -144 176 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1580-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1580-2.5 +SYMATTR Description 7A, Very low Dropout Regulator +PIN 64 144 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN -64 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 176 80 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 3 +PIN 176 -80 RIGHT 8 +PINATTR PinName OUTPUT +PINATTR SpiceOrder 4 +PIN -64 -144 TOP 8 +PINATTR PinName POWER +PINATTR SpiceOrder 5 +PIN -176 0 LEFT 8 +PINATTR PinName CONTROL +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1580.asy b/spice/copy/sym/PowerProducts/LT1580.asy new file mode 100755 index 0000000..eee8a28 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1580.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -144 176 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1580 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1580 +SYMATTR Description 7A, Very Low Dropout Regulator +PIN 0 144 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 176 80 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 3 +PIN 176 -80 RIGHT 8 +PINATTR PinName OUTPUT +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName POWER +PINATTR SpiceOrder 5 +PIN -176 0 LEFT 8 +PINATTR PinName CONTROL +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1581-2.5.asy b/spice/copy/sym/PowerProducts/LT1581-2.5.asy new file mode 100755 index 0000000..e7ae249 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1581-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -144 176 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1581-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1581-2.5 +SYMATTR Description 10A, Very low Dropout Regulator +PIN 64 144 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN -64 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 176 80 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 3 +PIN 176 -80 RIGHT 8 +PINATTR PinName OUTPUT +PINATTR SpiceOrder 4 +PIN -64 -144 TOP 8 +PINATTR PinName POWER +PINATTR SpiceOrder 5 +PIN -176 0 LEFT 8 +PINATTR PinName CONTROL +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1581.asy b/spice/copy/sym/PowerProducts/LT1581.asy new file mode 100755 index 0000000..8b93234 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1581.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -144 176 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1581 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1581 +SYMATTR Description 10A, Very Low Dropout Regulator +PIN 0 144 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 176 80 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 3 +PIN 176 -80 RIGHT 8 +PINATTR PinName OUTPUT +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName POWER +PINATTR SpiceOrder 5 +PIN -176 0 LEFT 8 +PINATTR PinName CONTROL +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1584-3.3.asy b/spice/copy/sym/PowerProducts/LT1584-3.3.asy new file mode 100755 index 0000000..5512748 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1584-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1584-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1584-3.3 +SYMATTR Description 7A Low Dropout Fast Response Positive Regulator, Fixed 3.3V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1584-3.38.asy b/spice/copy/sym/PowerProducts/LT1584-3.38.asy new file mode 100755 index 0000000..fac3b00 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1584-3.38.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1584-3.38 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1584-3.38 +SYMATTR Description 7A Low Dropout Fast Response Positive Regulator, Fixed 3.38V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1584-3.45.asy b/spice/copy/sym/PowerProducts/LT1584-3.45.asy new file mode 100755 index 0000000..b565f6a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1584-3.45.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1584-3.45 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1584-3.45 +SYMATTR Description 7A Low Dropout Fast Response Positive Regulator, Fixed 3.45V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1584-3.6.asy b/spice/copy/sym/PowerProducts/LT1584-3.6.asy new file mode 100755 index 0000000..5806b40 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1584-3.6.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1584-3.6 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1584-3.6 +SYMATTR Description 7A Low Dropout Fast Response Positive Regulator, Fixed 3.6V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1584.asy b/spice/copy/sym/PowerProducts/LT1584.asy new file mode 100755 index 0000000..4e698f1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1584.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1584 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1584 +SYMATTR Description 7A Low Dropout Fast Response Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1585-3.3.asy b/spice/copy/sym/PowerProducts/LT1585-3.3.asy new file mode 100755 index 0000000..bb52d0a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1585-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1585-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1585-3.3 +SYMATTR Description 4.6A Low Dropout Fast Response Positive Regulator, Fixed 3.3V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1585-3.38.asy b/spice/copy/sym/PowerProducts/LT1585-3.38.asy new file mode 100755 index 0000000..4ea5eb1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1585-3.38.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1585-3.38 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1585-3.38 +SYMATTR Description 4.6A Low Dropout Fast Response Positive Regulator, Fixed 3.38V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1585-3.45.asy b/spice/copy/sym/PowerProducts/LT1585-3.45.asy new file mode 100755 index 0000000..fc41f54 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1585-3.45.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1585-3.45 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1585-3.45 +SYMATTR Description 4.6A Low Dropout Fast Response Positive Regulator, Fixed 3.45V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1585-3.6.asy b/spice/copy/sym/PowerProducts/LT1585-3.6.asy new file mode 100755 index 0000000..d7c2668 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1585-3.6.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1585-3.6 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1585-3.6 +SYMATTR Description 4.6A Low Dropout Fast Response Positive Regulator, Fixed 3.6V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1585.asy b/spice/copy/sym/PowerProducts/LT1585.asy new file mode 100755 index 0000000..697a184 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1585.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1585 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1585 +SYMATTR Description 4.6A Low Dropout Fast Response Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1587-3.3.asy b/spice/copy/sym/PowerProducts/LT1587-3.3.asy new file mode 100755 index 0000000..de73720 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1587-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1587-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1587-3.3 +SYMATTR Description 4.6A Low Dropout Fast Response Positive Regulator, Fixed 3.3V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1587-3.38.asy b/spice/copy/sym/PowerProducts/LT1587-3.38.asy new file mode 100755 index 0000000..0de2df5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1587-3.38.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1587-3.38 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1587-3.38 +SYMATTR Description 4.6A Low Dropout Fast Response Positive Regulator, Fixed 3.38V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1587-3.45.asy b/spice/copy/sym/PowerProducts/LT1587-3.45.asy new file mode 100755 index 0000000..322adc4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1587-3.45.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1587-3.45 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1587-3.45 +SYMATTR Description 4.6A Low Dropout Fast Response Positive Regulator, Fixed 3.45V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1587-3.6.asy b/spice/copy/sym/PowerProducts/LT1587-3.6.asy new file mode 100755 index 0000000..de50b7c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1587-3.6.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1587-3.6 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1587-3.6 +SYMATTR Description 4.6A Low Dropout Fast Response Positive Regulator, Fixed 3.6V Output +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1587.asy b/spice/copy/sym/PowerProducts/LT1587.asy new file mode 100755 index 0000000..15af54f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1587.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT1587 +SYMATTR Prefix X +SYMATTR SpiceModel LT1584.lib +SYMATTR Value2 LT1587 +SYMATTR Description 3A Low Dropout Fast Response Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1610.asy b/spice/copy/sym/PowerProducts/LT1610.asy new file mode 100755 index 0000000..dd1fa3b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1610.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 -1 56 Center 2 +SYMATTR Value LT1610 +SYMATTR Prefix X +SYMATTR SpiceModel LT1610.sub +SYMATTR Value2 LT1610 +SYMATTR Description 1.7MHz, Single Cell µPower DC/DC Converter +PIN -144 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 -32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 80 112 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 4 +PIN 80 -112 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -80 -112 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -80 112 BOTTOM 8 +PINATTR PinName COMP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1611.asy b/spice/copy/sym/PowerProducts/LT1611.asy new file mode 100755 index 0000000..c9f4e48 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1611.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -96 160 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 32 112 Left 2 +SYMATTR Value LT1611 +SYMATTR Prefix X +SYMATTR SpiceModel LT1611.sub +SYMATTR Value2 LT1611 +SYMATTR Description Inverting 1.4MHz Switching Regulator in SOT-23 +PIN 80 -96 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1612.asy b/spice/copy/sym/PowerProducts/LT1612.asy new file mode 100755 index 0000000..28d8f3b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1612.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1612 +SYMATTR Prefix X +SYMATTR SpiceModel LT1612.sub +SYMATTR Value2 LT1612 +SYMATTR Description Synchronous, Step-Down 800KHz PWM DC/DC Converter +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 160 -80 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN -160 0 LEFT 8 +PINATTR PinName _Mode +PINATTR SpiceOrder 7 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1613.asy b/spice/copy/sym/PowerProducts/LT1613.asy new file mode 100755 index 0000000..24b0b85 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1613.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -96 160 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1613 +SYMATTR Prefix X +SYMATTR SpiceModel LT1613.sub +SYMATTR Value2 LT1613 +SYMATTR Description 1.4MHz, Single Cell DC/DC Converter in 5-Lead SOT-23 +PIN 80 -96 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1614.asy b/spice/copy/sym/PowerProducts/LT1614.asy new file mode 100755 index 0000000..b89ae64 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1614.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1614 +SYMATTR Prefix X +SYMATTR SpiceModel LT1614.sub +SYMATTR Value2 LT1614 +SYMATTR Description Inverting 600kHz Switching Regulator +PIN 144 0 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN 144 80 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1615-1.asy b/spice/copy/sym/PowerProducts/LT1615-1.asy new file mode 100755 index 0000000..f48be51 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1615-1.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1615-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT1615-1.sub +SYMATTR Value2 LT1615-1 +SYMATTR Description µPower Step-Up DC/DC Converter in SOT-23 +PIN 80 -128 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1615.asy b/spice/copy/sym/PowerProducts/LT1615.asy new file mode 100755 index 0000000..6b38509 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1615.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1615 +SYMATTR Prefix X +SYMATTR SpiceModel LT1615.sub +SYMATTR Value2 LT1615 +SYMATTR Description µPower Step-Up DC/DC Converter in SOT-23 +PIN 80 -128 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1616.asy b/spice/copy/sym/PowerProducts/LT1616.asy new file mode 100755 index 0000000..0285b4b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1616.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1616 +SYMATTR Prefix X +SYMATTR SpiceModel LT1616.sub +SYMATTR Value2 LT1616 +SYMATTR Description 600mA, 1.4MHz Step-Down Switching Regulator in SOT-23 +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1617-1.asy b/spice/copy/sym/PowerProducts/LT1617-1.asy new file mode 100755 index 0000000..4ff87ac --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1617-1.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -96 160 96 +TEXT 0 -10 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT1617-1 +SYMATTR Prefix X +SYMATTR Value2 LT1617-1 +SYMATTR SpiceModel LT1617-1.sub +SYMATTR Description µPower Inverting DC/DC Converters in SOT-23 +PIN 80 -96 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1617.asy b/spice/copy/sym/PowerProducts/LT1617.asy new file mode 100755 index 0000000..b104528 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1617.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -96 160 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT1617 +SYMATTR Prefix X +SYMATTR Value2 LT1617 +SYMATTR SpiceModel LT1617.sub +SYMATTR Description µPower Inverting DC/DC Converters in SOT-23 +PIN 80 -96 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1618.asy b/spice/copy/sym/PowerProducts/LT1618.asy new file mode 100755 index 0000000..cddb248 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1618.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -105 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT1618 +SYMATTR Prefix X +SYMATTR SpiceModel LT1618.sub +SYMATTR Value2 LT1618 +SYMATTR Description Constant-Current/Constant-Voltage 1.4MHz Step-Up DC/DC Converter +PIN 144 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -80 -160 TOP 8 +PINATTR PinName ISN +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Iadj +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 80 -160 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT1619.asy b/spice/copy/sym/PowerProducts/LT1619.asy new file mode 100755 index 0000000..f62e0fb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1619.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1619 +SYMATTR SpiceModel LT1619.sub +SYMATTR Value2 LT1619 +SYMATTR Prefix X +SYMATTR Description Low Voltage Current Mode PWM Controller +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -160 80 LEFT 8 +PINATTR PinName VC +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN 160 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 160 -80 RIGHT 8 +PINATTR PinName DRV +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1620.asy b/spice/copy/sym/PowerProducts/LT1620.asy new file mode 100755 index 0000000..7e8fd4c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1620.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 224 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -120 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LT1620 +SYMATTR Prefix X +SYMATTR SpiceModel LT1620.sub +SYMATTR Value2 LT1620 +SYMATTR Description Rail-to-Rail Current Sense Amplifier +PIN -176 -160 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 1 +PIN -176 -80 LEFT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 3 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -176 0 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 +PIN -176 160 LEFT 8 +PINATTR PinName IN- +PINATTR SpiceOrder 8 +PIN 176 160 RIGHT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 9 +PIN 0 -224 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 11 +PIN 176 -160 RIGHT 8 +PINATTR PinName AVE2 +PINATTR SpiceOrder 12 +PIN 176 0 RIGHT 8 +PINATTR PinName PROG2 +PINATTR SpiceOrder 13 +PIN 176 80 RIGHT 8 +PINATTR PinName PROG +PINATTR SpiceOrder 14 +PIN 176 -80 RIGHT 8 +PINATTR PinName AVE +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1620S8.asy b/spice/copy/sym/PowerProducts/LT1620S8.asy new file mode 100755 index 0000000..eded08b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1620S8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1620S8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1620S8.sub +SYMATTR Value2 LT1620S8 +SYMATTR Description Rail-to-Rail Current Sense Amplifier +PIN -144 -80 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName IN- +PINATTR SpiceOrder 4 +PIN 144 80 RIGHT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName PROG +PINATTR SpiceOrder 7 +PIN 144 -80 RIGHT 8 +PINATTR PinName AVE +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1621.asy b/spice/copy/sym/PowerProducts/LT1621.asy new file mode 100755 index 0000000..20065ed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1621.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -368 176 288 +TEXT 0 -120 Center 2 LT +WINDOW 0 0 -280 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LT1621 +SYMATTR Prefix X +SYMATTR SpiceModel LT1621.sub +SYMATTR Value2 LT1621 +SYMATTR Description Dual Rail-to-Rail Current Sense Amplifier +PIN -176 -320 LEFT 8 +PINATTR PinName PROG A +PINATTR SpiceOrder 1 +PIN -176 -240 LEFT 8 +PINATTR PinName AVE A +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName Sense A +PINATTR SpiceOrder 3 +PIN -176 -80 LEFT 8 +PINATTR PinName Iout A +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName GND B +PINATTR SpiceOrder 5 +PIN -176 80 LEFT 8 +PINATTR PinName IN- B +PINATTR SpiceOrder 6 +PIN -176 160 LEFT 8 +PINATTR PinName IN+ B +PINATTR SpiceOrder 7 +PIN -176 240 LEFT 8 +PINATTR PinName Vcc B +PINATTR SpiceOrder 8 +PIN 176 240 RIGHT 8 +PINATTR PinName PROG B +PINATTR SpiceOrder 9 +PIN 176 160 RIGHT 8 +PINATTR PinName AVE B +PINATTR SpiceOrder 10 +PIN 176 80 RIGHT 8 +PINATTR PinName Sense B +PINATTR SpiceOrder 11 +PIN 176 0 RIGHT 8 +PINATTR PinName Iout B +PINATTR SpiceOrder 12 +PIN 176 -80 RIGHT 8 +PINATTR PinName GND A +PINATTR SpiceOrder 13 +PIN 176 -160 RIGHT 8 +PINATTR PinName IN- A +PINATTR SpiceOrder 14 +PIN 176 -240 RIGHT 8 +PINATTR PinName IN+ A +PINATTR SpiceOrder 15 +PIN 176 -320 RIGHT 8 +PINATTR PinName Vcc A +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1641-1.asy b/spice/copy/sym/PowerProducts/LT1641-1.asy new file mode 100755 index 0000000..c49463f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1641-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT1641-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT1641-1.sub +SYMATTR Value2 LT1641-1 +SYMATTR Description Positive High Voltage Hot Swap Controller +PIN -128 -64 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 1 +PIN 128 16 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 128 96 RIGHT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 96 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 6 +PIN 64 -128 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -80 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1641-2.asy b/spice/copy/sym/PowerProducts/LT1641-2.asy new file mode 100755 index 0000000..03b568b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1641-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT1641-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT1641-2.sub +SYMATTR Value2 LT1641-2 +SYMATTR Description Positive High Voltage Hot Swap Controller +PIN -128 -64 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 1 +PIN 128 16 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 128 96 RIGHT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 96 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 6 +PIN 64 -128 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -80 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1676.asy b/spice/copy/sym/PowerProducts/LT1676.asy new file mode 100755 index 0000000..ff5efca --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1676.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1676 +SYMATTR Prefix X +SYMATTR SpiceModel LT1676.sub +SYMATTR Value2 LT1676 +SYMATTR Description Wide Input Range, High Efficiency, Step-Down Switching Regulator +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN 144 -144 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 144 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1680.asy b/spice/copy/sym/PowerProducts/LT1680.asy new file mode 100755 index 0000000..ede3f09 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1680.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -192 192 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1680 +SYMATTR Prefix X +SYMATTR SpiceModel LT1680.sub +SYMATTR Value2 LT1680 +SYMATTR Description High Power DC/DC Step-Up Controller +PIN -192 64 LEFT 8 +PINATTR PinName SL/ADJ +PINATTR SpiceOrder 1 +PIN -192 128 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 2 +PIN -192 -64 LEFT 8 +PINATTR PinName Iave +PINATTR SpiceOrder 3 +PIN -128 192 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 192 128 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 5 +PIN 0 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN 192 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 192 -128 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN 192 -64 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 10 +PIN -192 -128 LEFT 8 +PINATTR PinName Run/SHDN +PINATTR SpiceOrder 11 +PIN 128 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 192 0 RIGHT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 13 +PIN 0 -192 TOP 8 +PINATTR PinName 12Vin +PINATTR SpiceOrder 14 +PIN -192 0 LEFT 8 +PINATTR PinName 5Vref +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1681.asy b/spice/copy/sym/PowerProducts/LT1681.asy new file mode 100755 index 0000000..2d43e46 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1681.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -143 -241 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -183 Center 2 +WINDOW 3 0 145 Center 2 +SYMATTR Value LT1681 +SYMATTR Prefix X +SYMATTR SpiceModel LT1681.sub +SYMATTR Value2 LT1681 +SYMATTR Description Dual Transistor Synchronous Forward Controller +PIN -144 -208 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -160 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 2 +PIN -144 -112 LEFT 8 +PINATTR PinName TERM +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName GSND +PINATTR SpiceOrder 4 +PIN -144 -16 LEFT 8 +PINATTR PinName 5Vref +PINATTR SpiceOrder 5 +PIN -144 32 LEFT 8 +PINATTR PinName FSET +PINATTR SpiceOrder 6 +PIN -144 128 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -144 176 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 224 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 +PIN 144 224 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 11 +PIN 144 176 RIGHT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 12 +PIN 144 128 RIGHT 8 +PINATTR PinName SG +PINATTR SpiceOrder 13 +PIN 144 80 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 14 +PIN 144 32 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 15 +PIN 144 -16 RIGHT 8 +PINATTR PinName GB +PINATTR SpiceOrder 16 +PIN 144 -64 RIGHT 8 +PINATTR PinName BLKSENS +PINATTR SpiceOrder 17 +PIN 144 -112 RIGHT 8 +PINATTR PinName BSTREF +PINATTR SpiceOrder 18 +PIN 144 -160 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 19 +PIN 144 -208 RIGHT 8 +PINATTR PinName Vbst +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT1683.asy b/spice/copy/sym/PowerProducts/LT1683.asy new file mode 100755 index 0000000..a6ec432 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1683.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -400 144 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1683 +SYMATTR Prefix X +SYMATTR SpiceModel LT1683.sub +SYMATTR Value2 LT1683 +SYMATTR Description Slew Rate Controlled Ultralow Noise Push-Pull DC/DC Controller +PIN 144 -240 RIGHT 8 +PINATTR PinName GateA +PINATTR SpiceOrder 1 +PIN 144 -336 RIGHT 8 +PINATTR PinName CapA +PINATTR SpiceOrder 2 +PIN 64 -400 TOP 8 +PINATTR PinName GCL +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName CS +PINATTR SpiceOrder 4 +PIN -144 -240 LEFT 8 +PINATTR PinName V5 +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 7 +PIN -144 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN 144 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN 144 336 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 10 +PIN -64 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 64 400 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN -144 336 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 13 +PIN -144 -336 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 14 +PIN -144 240 LEFT 8 +PINATTR PinName RCSL +PINATTR SpiceOrder 15 +PIN -144 144 LEFT 8 +PINATTR PinName RVSL +PINATTR SpiceOrder 16 +PIN -64 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 17 +PIN 144 -144 RIGHT 8 +PINATTR PinName CapB +PINATTR SpiceOrder 18 +PIN 144 -48 RIGHT 8 +PINATTR PinName GateB +PINATTR SpiceOrder 19 +PIN 144 144 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT1725.asy b/spice/copy/sym/PowerProducts/LT1725.asy new file mode 100755 index 0000000..7cff393 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1725.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -224 192 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT1725 +SYMATTR Prefix X +SYMATTR SpiceModel LT1725.sub +SYMATTR Value2 LT1725 +SYMATTR Description General Purpose Isolated Flyback Controller +PIN 80 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 192 96 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 2 +PIN 192 -96 RIGHT 8 +PINATTR PinName SFST +PINATTR SpiceOrder 3 +PIN -192 -96 LEFT 8 +PINATTR PinName Rocmp +PINATTR SpiceOrder 4 +PIN -192 -32 LEFT 8 +PINATTR PinName Rcmpc +PINATTR SpiceOrder 5 +PIN 192 160 RIGHT 8 +PINATTR PinName OSCAP +PINATTR SpiceOrder 6 +PIN 192 -160 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN -192 -160 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN 192 -32 RIGHT 8 +PINATTR PinName 3Vout +PINATTR SpiceOrder 9 +PIN -80 -224 TOP 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 10 +PIN -80 224 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN -192 32 LEFT 8 +PINATTR PinName MinEnab +PINATTR SpiceOrder 12 +PIN -192 96 LEFT 8 +PINATTR PinName EnDly +PINATTR SpiceOrder 13 +PIN -192 160 LEFT 8 +PINATTR PinName Ton +PINATTR SpiceOrder 14 +PIN 80 -224 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN 192 32 RIGHT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1737.asy b/spice/copy/sym/PowerProducts/LT1737.asy new file mode 100755 index 0000000..394a468 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1737.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -224 192 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT1737 +SYMATTR Prefix X +SYMATTR SpiceModel LT1737.sub +SYMATTR Value2 LT1737 +SYMATTR Description High Power Isolated Flyback Controller +PIN 80 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 192 96 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 2 +PIN 192 -96 RIGHT 8 +PINATTR PinName SFST +PINATTR SpiceOrder 3 +PIN -192 -96 LEFT 8 +PINATTR PinName Rocmp +PINATTR SpiceOrder 4 +PIN -192 -32 LEFT 8 +PINATTR PinName Rcmpc +PINATTR SpiceOrder 5 +PIN 192 160 RIGHT 8 +PINATTR PinName OSCAP +PINATTR SpiceOrder 6 +PIN 192 -160 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN -192 -160 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN 192 -32 RIGHT 8 +PINATTR PinName 3Vout +PINATTR SpiceOrder 9 +PIN -80 -224 TOP 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 10 +PIN -80 224 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN -192 32 LEFT 8 +PINATTR PinName MinEnab +PINATTR SpiceOrder 12 +PIN -192 96 LEFT 8 +PINATTR PinName EnDly +PINATTR SpiceOrder 13 +PIN -192 160 LEFT 8 +PINATTR PinName Ton +PINATTR SpiceOrder 14 +PIN 80 -224 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN 192 32 RIGHT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1738.asy b/spice/copy/sym/PowerProducts/LT1738.asy new file mode 100755 index 0000000..af12dac --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1738.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -352 144 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1738 +SYMATTR Prefix X +SYMATTR SpiceModel LT1738.sub +SYMATTR Value2 LT1738 +SYMATTR Description Slew Rate Controlled Ultralow Noise DC/DC Controller +PIN 144 -192 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 1 +PIN 144 -288 RIGHT 8 +PINATTR PinName Cap +PINATTR SpiceOrder 2 +PIN 64 -352 TOP 8 +PINATTR PinName GCL +PINATTR SpiceOrder 3 +PIN 144 -96 RIGHT 8 +PINATTR PinName CS +PINATTR SpiceOrder 4 +PIN -144 -192 LEFT 8 +PINATTR PinName V5 +PINATTR SpiceOrder 5 +PIN -144 0 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN 144 192 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 10 +PIN 64 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 144 288 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN -64 352 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 13 +PIN -144 -288 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 14 +PIN -144 288 LEFT 8 +PINATTR PinName RCSL +PINATTR SpiceOrder 15 +PIN -144 192 LEFT 8 +PINATTR PinName RVSL +PINATTR SpiceOrder 16 +PIN -64 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 17 +PIN 144 0 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT1761-1.2.asy b/spice/copy/sym/PowerProducts/LT1761-1.2.asy new file mode 100755 index 0000000..2611cca --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-1.2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-1.2 +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, 1.2V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-1.5.asy b/spice/copy/sym/PowerProducts/LT1761-1.5.asy new file mode 100755 index 0000000..fa49112 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-1.5 +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, 1.5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-1.8.asy b/spice/copy/sym/PowerProducts/LT1761-1.8.asy new file mode 100755 index 0000000..a70b866 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-1.8 +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, 1.8V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-2.5.asy b/spice/copy/sym/PowerProducts/LT1761-2.5.asy new file mode 100755 index 0000000..f1f7b4c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-2.5 +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, 2.5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-2.8.asy b/spice/copy/sym/PowerProducts/LT1761-2.8.asy new file mode 100755 index 0000000..b780e22 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-2.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-2.8 +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, 2.8V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-2.asy b/spice/copy/sym/PowerProducts/LT1761-2.asy new file mode 100755 index 0000000..b742731 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-2 +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, 2V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-3.3.asy b/spice/copy/sym/PowerProducts/LT1761-3.3.asy new file mode 100755 index 0000000..fc353dd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-3.3 +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, 3.3V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-3.asy b/spice/copy/sym/PowerProducts/LT1761-3.asy new file mode 100755 index 0000000..43fd584 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-3 +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, 3V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-5.asy b/spice/copy/sym/PowerProducts/LT1761-5.asy new file mode 100755 index 0000000..1bb2caf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-5 +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, 5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-BYP.asy b/spice/copy/sym/PowerProducts/LT1761-BYP.asy new file mode 100755 index 0000000..26cd477 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-BYP.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-BYP +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-BYP +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator in SOT-23, Adjustable Output Voltage +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1761-SD.asy b/spice/copy/sym/PowerProducts/LT1761-SD.asy new file mode 100755 index 0000000..06246b6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1761-SD.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1761-SD +SYMATTR Prefix X +SYMATTR SpiceModel LT1761.lib +SYMATTR Value2 LT1761-SD +SYMATTR Description 100mA Low Noise Low Dropout µPower Regulator with Shutdown in SOT-23, Adjustable Output Voltage +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1762-2.5.asy b/spice/copy/sym/PowerProducts/LT1762-2.5.asy new file mode 100755 index 0000000..6615954 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1762-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1762-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1762.lib +SYMATTR Value2 LT1762-2.5 +SYMATTR Description 150mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 2.5V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1762-3.3.asy b/spice/copy/sym/PowerProducts/LT1762-3.3.asy new file mode 100755 index 0000000..8a65c63 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1762-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1762-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1762.lib +SYMATTR Value2 LT1762-3.3 +SYMATTR Description 150mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 3.3V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1762-3.asy b/spice/copy/sym/PowerProducts/LT1762-3.asy new file mode 100755 index 0000000..f88e1d8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1762-3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1762-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1762.lib +SYMATTR Value2 LT1762-3 +SYMATTR Description 150mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 3V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1762-5.asy b/spice/copy/sym/PowerProducts/LT1762-5.asy new file mode 100755 index 0000000..bddb4ed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1762-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1762-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1762.lib +SYMATTR Value2 LT1762-5 +SYMATTR Description 150mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 5V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1762.asy b/spice/copy/sym/PowerProducts/LT1762.asy new file mode 100755 index 0000000..8cbb6d5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1762.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1762 +SYMATTR Prefix X +SYMATTR SpiceModel LT1762.lib +SYMATTR Value2 LT1762 +SYMATTR Description 150mA Low Noise Low Dropout µPower Regulator with Shutdown, Adjustable Output Voltage +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1763-1.5.asy b/spice/copy/sym/PowerProducts/LT1763-1.5.asy new file mode 100755 index 0000000..75b86ca --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1763-1.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1763-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1763.lib +SYMATTR Value2 LT1763-1.5 +SYMATTR Description 500mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 1.5V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1763-1.8.asy b/spice/copy/sym/PowerProducts/LT1763-1.8.asy new file mode 100755 index 0000000..f21c67d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1763-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1763-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1763.lib +SYMATTR Value2 LT1763-1.8 +SYMATTR Description 500mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 1.8V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1763-2.5.asy b/spice/copy/sym/PowerProducts/LT1763-2.5.asy new file mode 100755 index 0000000..3fdbe8b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1763-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1763-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1763.lib +SYMATTR Value2 LT1763-2.5 +SYMATTR Description 500mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 2.5V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1763-3.3.asy b/spice/copy/sym/PowerProducts/LT1763-3.3.asy new file mode 100755 index 0000000..c420ed8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1763-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1763-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1763.lib +SYMATTR Value2 LT1763-3.3 +SYMATTR Description 500mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 3.3V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1763-3.asy b/spice/copy/sym/PowerProducts/LT1763-3.asy new file mode 100755 index 0000000..9e8bf42 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1763-3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1763-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1763.lib +SYMATTR Value2 LT1763-3 +SYMATTR Description 500mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 3V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1763-5.asy b/spice/copy/sym/PowerProducts/LT1763-5.asy new file mode 100755 index 0000000..7d168a4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1763-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1763-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1763.lib +SYMATTR Value2 LT1763-5 +SYMATTR Description 500mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 5V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1763.asy b/spice/copy/sym/PowerProducts/LT1763.asy new file mode 100755 index 0000000..0364f78 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1763.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1763 +SYMATTR Prefix X +SYMATTR SpiceModel LT1763.lib +SYMATTR Value2 LT1763 +SYMATTR Description 500mA Low Noise Low Dropout µPower Regulator with Shutdown, Adjustable Output Voltage +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1764-1.5.asy b/spice/copy/sym/PowerProducts/LT1764-1.5.asy new file mode 100755 index 0000000..6828f28 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764-1.5 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Fixed 1.5V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1764-1.8.asy b/spice/copy/sym/PowerProducts/LT1764-1.8.asy new file mode 100755 index 0000000..275150a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764-1.8 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Fixed 1.8V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1764-2.5.asy b/spice/copy/sym/PowerProducts/LT1764-2.5.asy new file mode 100755 index 0000000..dcfcba4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764-2.5 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Fixed 2.5V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1764-3.3.asy b/spice/copy/sym/PowerProducts/LT1764-3.3.asy new file mode 100755 index 0000000..8e4b9c3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764-3.3 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Fixed 3.3V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1764.asy b/spice/copy/sym/PowerProducts/LT1764.asy new file mode 100755 index 0000000..947c6cd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764 +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Adjustable Output Voltage +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1764A-1.5.asy b/spice/copy/sym/PowerProducts/LT1764A-1.5.asy new file mode 100755 index 0000000..bab4e27 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764A-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764A-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764-1.5 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Fixed 1.5V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1764A-1.8.asy b/spice/copy/sym/PowerProducts/LT1764A-1.8.asy new file mode 100755 index 0000000..d2117be --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764A-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764A-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764-1.8 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Fixed 1.8V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1764A-2.5.asy b/spice/copy/sym/PowerProducts/LT1764A-2.5.asy new file mode 100755 index 0000000..4e3ef71 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764A-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764A-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764-2.5 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Fixed 2.5V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1764A-3.3.asy b/spice/copy/sym/PowerProducts/LT1764A-3.3.asy new file mode 100755 index 0000000..e338c45 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764A-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764A-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764-3.3 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Fixed 3.3V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1764A.asy b/spice/copy/sym/PowerProducts/LT1764A.asy new file mode 100755 index 0000000..5b5190e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1764A.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1764A +SYMATTR Prefix X +SYMATTR SpiceModel LT1764.lib +SYMATTR Value2 LT1764 +SYMATTR Description 3A, Fast Transient Response, Low Noise, LDO Regulator, Adjustable Output Voltage +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1765.asy b/spice/copy/sym/PowerProducts/LT1765.asy new file mode 100755 index 0000000..4526aed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1765.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1765 +SYMATTR Prefix X +SYMATTR SpiceModel LT1765.sub +SYMATTR Value2 LT1765 +SYMATTR Description Monolithic 3A, 1.25MHz Step-Down Switching Regulator +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1766.asy b/spice/copy/sym/PowerProducts/LT1766.asy new file mode 100755 index 0000000..d409df0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1766.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1766 +SYMATTR Prefix X +SYMATTR SpiceModel LT1766.sub +SYMATTR Value2 LT1766 +SYMATTR Description High Voltage 200KHz Step-Down Switching Regulator +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 0 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 14 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT1767-1.8.asy b/spice/copy/sym/PowerProducts/LT1767-1.8.asy new file mode 100755 index 0000000..758f3cf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1767-1.8.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1767-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1767-x.x.sub +SYMATTR Value2 LT1767-x.x top=5K bot=10K +SYMATTR Description Monolithic 1.5A, 1.25MHz Step-Down Switching Regulator, Fixed 1.8V Output\n\nNote: Sync pin is not modeled. +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1767-2.5.asy b/spice/copy/sym/PowerProducts/LT1767-2.5.asy new file mode 100755 index 0000000..0148c9c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1767-2.5.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 47 Center 2 +SYMATTR Value LT1767-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1767-x.x.sub +SYMATTR Value2 LT1767-x.x top=10.92 bot=10.08 +SYMATTR Description Monolithic 1.5A, 1.25MHz Step-Down Switching Regulator, Fixed 2.5V Output\n\nNote: Sync pin is not modeled. +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1767-3.3.asy b/spice/copy/sym/PowerProducts/LT1767-3.3.asy new file mode 100755 index 0000000..5f49d44 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1767-3.3.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 -1 63 Center 2 +SYMATTR Value LT1767-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1767-x.x.sub +SYMATTR Value2 LT1767-x.x top=17K bot=10K +SYMATTR Description Monolithic 1.5A, 1.25MHz Step-Down Switching Regulator, Fixed 3.3V Output\n\nNote: Sync pin is not modeled. +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1767-5.asy b/spice/copy/sym/PowerProducts/LT1767-5.asy new file mode 100755 index 0000000..781cde9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1767-5.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1767-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1767-x.x.sub +SYMATTR Value2 LT1767-x.x top=31.92K bot=10.08K +SYMATTR Description Monolithic 1.5A, 1.25MHz Step-Down Switching Regulator, Fixed 5V Output\n\nNote: Sync pin is not modeled. +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1767.asy b/spice/copy/sym/PowerProducts/LT1767.asy new file mode 100755 index 0000000..922354b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1767.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1767 +SYMATTR Prefix X +SYMATTR SpiceModel LT1767.sub +SYMATTR Value2 LT1767 +SYMATTR Description Monolithic 1.5A, 1.25MHz Step-Down Switching Regulator\n\nNote: Sync pin is not modeled. +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1776.asy b/spice/copy/sym/PowerProducts/LT1776.asy new file mode 100755 index 0000000..632fc7b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1776.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1776 +SYMATTR Prefix X +SYMATTR SpiceModel LT1776.sub +SYMATTR Value2 LT1776 +SYMATTR Description Wide Input Range, High Efficiency, Step-Down Switching Regulator +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN 144 -144 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 144 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1777.asy b/spice/copy/sym/PowerProducts/LT1777.asy new file mode 100755 index 0000000..39d0916 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1777.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1777 +SYMATTR Prefix X +SYMATTR SpiceModel LT1777.sub +SYMATTR Value2 LT1777 +SYMATTR Description Low Noise Step-Down Switching Regulator +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 80 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 4 +PIN 144 0 RIGHT 8 +PINATTR PinName Vd +PINATTR SpiceOrder 5 +PIN 144 -64 RIGHT 8 +PINATTR PinName Vsw +PINATTR SpiceOrder 6 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -80 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 13 +PIN -144 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT1786F.asy b/spice/copy/sym/PowerProducts/LT1786F.asy new file mode 100755 index 0000000..a990189 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1786F.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -320 224 320 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT1786F +SYMATTR Prefix X +SYMATTR SpiceModel LT1786F.sub +SYMATTR Value2 LT1786F +SYMATTR Description SMBus Programmable CCFL Switching Regulator(Bits-to-Nits(TM)) +PIN 112 320 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN -224 -48 LEFT 8 +PINATTR PinName Iccfl +PINATTR SpiceOrder 2 +PIN -224 -240 LEFT 8 +PINATTR PinName DIO +PINATTR SpiceOrder 3 +PIN 224 48 RIGHT 8 +PINATTR PinName CCFL Vc +PINATTR SpiceOrder 4 +PIN -112 320 BOTTOM 8 +PINATTR PinName AGND +PINATTR SpiceOrder 5 +PIN -224 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -224 144 LEFT 8 +PINATTR PinName _SMBSUS +PINATTR SpiceOrder 7 +PIN -224 240 LEFT 8 +PINATTR PinName ADR +PINATTR SpiceOrder 8 +PIN 224 240 RIGHT 8 +PINATTR PinName SDA +PINATTR SpiceOrder 9 +PIN 224 144 RIGHT 8 +PINATTR PinName SCL +PINATTR SpiceOrder 10 +PIN -224 -144 LEFT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 11 +PIN -112 -320 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 +PIN 224 -48 RIGHT 8 +PINATTR PinName ROYER +PINATTR SpiceOrder 13 +PIN 224 -144 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 14 +PIN 112 -320 TOP 8 +PINATTR PinName BULB +PINATTR SpiceOrder 15 +PIN 224 -240 RIGHT 8 +PINATTR PinName CCFL SW +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1790-1.25.asy b/spice/copy/sym/PowerProducts/LT1790-1.25.asy new file mode 100755 index 0000000..1a0dfca --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1790-1.25.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -48 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1790-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel LT1790.lib +SYMATTR Value2 LT1790-125 +SYMATTR Description µPower SOT-23 Low Dropout 1.25V Reference +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1790-2.048.asy b/spice/copy/sym/PowerProducts/LT1790-2.048.asy new file mode 100755 index 0000000..ca6d428 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1790-2.048.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -48 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1790-2.048 +SYMATTR Prefix X +SYMATTR SpiceModel LT1790.lib +SYMATTR Value2 LT1790-2048 +SYMATTR Description µPower SOT-23 Low Dropout 2.048V Reference +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1790-2.5.asy b/spice/copy/sym/PowerProducts/LT1790-2.5.asy new file mode 100755 index 0000000..e80b3a0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1790-2.5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -48 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1790-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1790.lib +SYMATTR Value2 LT1790-25 +SYMATTR Description µPower SOT-23 Low Dropout 2.5V Reference +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1790-3.3.asy b/spice/copy/sym/PowerProducts/LT1790-3.3.asy new file mode 100755 index 0000000..026c5e3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1790-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -48 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1790-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1790.lib +SYMATTR Value2 LT1790-33 +SYMATTR Description µPower SOT-23 Low Dropout 3.3V Reference +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1790-3.asy b/spice/copy/sym/PowerProducts/LT1790-3.asy new file mode 100755 index 0000000..44d7783 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1790-3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -48 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1790-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1790.lib +SYMATTR Value2 LT1790-3 +SYMATTR Description µPower SOT-23 Low Dropout 3V Reference +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1790-4.096.asy b/spice/copy/sym/PowerProducts/LT1790-4.096.asy new file mode 100755 index 0000000..06dea1a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1790-4.096.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -48 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1790-4.096 +SYMATTR Prefix X +SYMATTR SpiceModel LT1790.lib +SYMATTR Value2 LT1790-4096 +SYMATTR Description µPower SOT-23 Low Dropout 4.096V Reference +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1790-5.asy b/spice/copy/sym/PowerProducts/LT1790-5.asy new file mode 100755 index 0000000..023c7a9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1790-5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -48 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1790-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1790.lib +SYMATTR Value2 LT1790-5 +SYMATTR Description µPower SOT-23 Low Dropout 5V Reference +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT1910.asy b/spice/copy/sym/PowerProducts/LT1910.asy new file mode 100755 index 0000000..fa1dcb8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1910.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LT1910 +SYMATTR Prefix X +SYMATTR SpiceModel LT1910.sub +SYMATTR Value2 LT1910 +SYMATTR Description Protected High Side MOSFET Driver +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 80 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 2 +PIN -128 -80 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 3 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 4 +PIN 128 80 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 128 -80 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1912.asy b/spice/copy/sym/PowerProducts/LT1912.asy new file mode 100755 index 0000000..c5c8a07 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1912.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT1912 +SYMATTR Prefix X +SYMATTR SpiceModel LT1912.sub +SYMATTR Value2 LT1912 +SYMATTR Description 36V, 2A, 500KHz Step-Down Switching Regulator +PIN 160 -128 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT1913.asy b/spice/copy/sym/PowerProducts/LT1913.asy new file mode 100755 index 0000000..b19225a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1913.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT1913 +SYMATTR Prefix X +SYMATTR SpiceModel LT1913.sub +SYMATTR Value2 LT1913 +SYMATTR Description 25V, 3.5A, 2.4MHz Step-Down Switching Regulator +PIN 160 -128 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT1930.asy b/spice/copy/sym/PowerProducts/LT1930.asy new file mode 100755 index 0000000..cbea5a2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1930.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -96 160 96 +TEXT 0 -9 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 1 40 Center 2 +SYMATTR Value LT1930 +SYMATTR Value2 LT1930 +SYMATTR Prefix X +SYMATTR SpiceModel LT1930.sub +SYMATTR Description 1A, 1.2MHz Boost DC/DC Converter in ThinSOT +PIN 80 -96 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1930A.asy b/spice/copy/sym/PowerProducts/LT1930A.asy new file mode 100755 index 0000000..d610cc1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1930A.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -96 160 96 +TEXT 0 -24 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 -1 39 Center 2 +SYMATTR Value LT1930A +SYMATTR Value2 LT1930A +SYMATTR Prefix X +SYMATTR SpiceModel LT1930A.sub +SYMATTR Description 1A, 2.2MHz Boost DC/DC Converter in ThinSOT +PIN 80 -96 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1931.asy b/spice/copy/sym/PowerProducts/LT1931.asy new file mode 100755 index 0000000..43365da --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1931.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -96 160 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 39 Center 2 +SYMATTR Value LT1931 +SYMATTR Value2 LT1931 +SYMATTR Prefix X +SYMATTR SpiceModel LT1931.sub +SYMATTR Description 1.2MHz Inverting DC/DC Converter in ThinSOT +PIN 80 -96 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1931A.asy b/spice/copy/sym/PowerProducts/LT1931A.asy new file mode 100755 index 0000000..804420f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1931A.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -96 160 96 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 39 Center 2 +SYMATTR Value LT1931A +SYMATTR Value2 LT1931A +SYMATTR Prefix X +SYMATTR SpiceModel LT1931A.sub +SYMATTR Description 2.2MHz Inverting DC/DC Converter in ThinSOT +PIN 80 -96 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1932.asy b/spice/copy/sym/PowerProducts/LT1932.asy new file mode 100755 index 0000000..a6bcdfe --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1932.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -95 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1932 +SYMATTR Prefix X +SYMATTR SpiceModel LT1932.sub +SYMATTR Value2 LT1932 +SYMATTR Description Constant-Current DC/DC LED Driver in ThinSOT +PIN 80 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 3 +PIN -160 64 LEFT 8 +PINATTR PinName Rset +PINATTR SpiceOrder 4 +PIN -160 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -80 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1933.asy b/spice/copy/sym/PowerProducts/LT1933.asy new file mode 100755 index 0000000..5d40f2c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1933.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LT1933 +SYMATTR Prefix X +SYMATTR SpiceModel LT1933.sub +SYMATTR Value2 LT1933 +SYMATTR Description 600mA, 500KHz Step-Down Switching Regulator in SOT-23 +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1934-1.asy b/spice/copy/sym/PowerProducts/LT1934-1.asy new file mode 100755 index 0000000..e99afc9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1934-1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LT1934-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT1934-1.sub +SYMATTR Value2 LT1934-1 +SYMATTR Description µPower Step-Down Switching Regulator in ThinSOT +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1934.asy b/spice/copy/sym/PowerProducts/LT1934.asy new file mode 100755 index 0000000..66e874c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1934.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1934 +SYMATTR Prefix X +SYMATTR SpiceModel LT1934.sub +SYMATTR Value2 LT1934 +SYMATTR Description µPower Step-Down Switching Regulator in ThinSOT +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT1935.asy b/spice/copy/sym/PowerProducts/LT1935.asy new file mode 100755 index 0000000..2d46dcf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1935.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -96 160 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1935 +SYMATTR Value2 LT1935 +SYMATTR Prefix X +SYMATTR SpiceModel LT1935.sub +SYMATTR Description 1.2MHz Boost DC/DC Converter in ThinSOT with 2A Switch +PIN 80 -96 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1936.asy b/spice/copy/sym/PowerProducts/LT1936.asy new file mode 100755 index 0000000..770925e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1936.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT1936 +SYMATTR Prefix X +SYMATTR SpiceModel LT1936.sub +SYMATTR Value2 LT1936 +SYMATTR Description 1.4A, 500KHz Step-Down Switching Regulator +PIN 64 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -64 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 64 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -64 144 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN -128 64 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1937.asy b/spice/copy/sym/PowerProducts/LT1937.asy new file mode 100755 index 0000000..6f92383 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1937.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1937 +SYMATTR Prefix X +SYMATTR SpiceModel LT1937.sub +SYMATTR Value2 LT1937 +SYMATTR Description White LED Step-Up Converter in ThinSOT +PIN 80 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1938.asy b/spice/copy/sym/PowerProducts/LT1938.asy new file mode 100755 index 0000000..69634f5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1938.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT1938 +SYMATTR Prefix X +SYMATTR SpiceModel LT3684.sub +SYMATTR Value2 LT3684 +SYMATTR Description 25V, 2.2A, 2.8MHz Step-Down Switching Regulator +PIN 64 -192 TOP 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -64 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 6 +PIN 160 -128 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT1939.asy b/spice/copy/sym/PowerProducts/LT1939.asy new file mode 100755 index 0000000..81c493f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1939.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -304 160 272 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -168 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value LT1939 +SYMATTR Prefix X +SYMATTR SpiceModel LT1939.sub +SYMATTR Value2 LT1939 +SYMATTR Description Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller +PIN -80 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 -224 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -160 224 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 4 +PIN -160 112 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -160 -112 LEFT 8 +PINATTR PinName _Pgood +PINATTR SpiceOrder 7 +PIN 160 -112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN 160 224 RIGHT 8 +PINATTR PinName LFB +PINATTR SpiceOrder 9 +PIN 160 112 RIGHT 8 +PINATTR PinName LDRV +PINATTR SpiceOrder 10 +PIN 80 -304 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 11 +PIN 160 -224 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT1940.asy b/spice/copy/sym/PowerProducts/LT1940.asy new file mode 100755 index 0000000..36918cc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1940.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -208 208 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1940 +SYMATTR Prefix X +SYMATTR SpiceModel LT1940.sub +SYMATTR Value2 LT1940 +SYMATTR Description Dual Monolithic 1.5A, 1.5MHz Step-Down Switching Regulator +PIN 208 -160 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 1 +PIN 208 -96 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 0 -208 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -208 -96 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -208 -160 LEFT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 8 +PIN -208 -32 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN -208 32 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 10 +PIN -208 96 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 11 +PIN -208 160 LEFT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 12 +PIN 208 160 RIGHT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 13 +PIN 208 96 RIGHT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 14 +PIN 208 32 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 15 +PIN 208 -32 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1941.asy b/spice/copy/sym/PowerProducts/LT1941.asy new file mode 100755 index 0000000..484fabe --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1941.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -352 208 368 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 103 Center 2 +SYMATTR Value LT1941 +SYMATTR Prefix X +SYMATTR SpiceModel LT1941.sub +SYMATTR Value2 LT1941 +SYMATTR Description Triple Monolithic Switching Regulator +PIN 0 -352 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 208 16 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 208 -48 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 5 +PIN -208 -304 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 6 +PIN 208 208 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 8 +PIN -208 -240 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 9 +PIN 208 272 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 10 +PIN -208 16 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 11 +PIN 208 144 RIGHT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 12 +PIN -208 80 LEFT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 13 +PIN -208 336 LEFT 8 +PINATTR PinName Run/SS3 +PINATTR SpiceOrder 14 +PIN 208 -176 RIGHT 8 +PINATTR PinName BIAS1 +PINATTR SpiceOrder 15 +PIN 208 -240 RIGHT 8 +PINATTR PinName 12GOOD +PINATTR SpiceOrder 16 +PIN 208 -304 RIGHT 8 +PINATTR PinName 5GOOD +PINATTR SpiceOrder 17 +PIN 208 336 RIGHT 8 +PINATTR PinName Vc3 +PINATTR SpiceOrder 18 +PIN -208 272 LEFT 8 +PINATTR PinName NFB +PINATTR SpiceOrder 19 +PIN -208 208 LEFT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 20 +PIN -208 -176 LEFT 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 21 +PIN -208 -48 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 23 +PIN -208 -112 LEFT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 24 +PIN -208 144 LEFT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 27 +PIN 208 -112 RIGHT 8 +PINATTR PinName BIAS2 +PINATTR SpiceOrder 28 +PIN 0 368 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LT1943.asy b/spice/copy/sym/PowerProducts/LT1943.asy new file mode 100755 index 0000000..505cad1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1943.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 353 -176 -352 +TEXT 0 0 Center 2 LT +WINDOW 123 0 80 Center 2 +WINDOW 0 0 -80 Center 2 +SYMATTR Value2 LT1943 +SYMATTR SpiceModel LT1943.sub +SYMATTR Value LT1943 +SYMATTR Prefix X +SYMATTR Description High Current Quad Output Regulator for TFT LCD Panels +PIN -64 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 2 +PIN -176 288 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 3 +PIN -176 160 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN 176 -224 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 176 160 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 6 +PIN -176 -224 LEFT 8 +PINATTR PinName NFB4 +PINATTR SpiceOrder 7 +PIN -176 -160 LEFT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 8 +PIN 176 224 RIGHT 8 +PINATTR PinName Vc3 +PINATTR SpiceOrder 9 +PIN 176 288 RIGHT 8 +PINATTR PinName Vc4 +PINATTR SpiceOrder 10 +PIN 64 352 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN -176 32 LEFT 8 +PINATTR PinName BOOST +PINATTR SpiceOrder 12 +PIN -176 96 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 13 +PIN -64 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 176 -96 RIGHT 8 +PINATTR PinName SS-234 +PINATTR SpiceOrder 17 +PIN 176 -160 RIGHT 8 +PINATTR PinName RUN-SS +PINATTR SpiceOrder 18 +PIN -176 -288 LEFT 8 +PINATTR PinName SW4 +PINATTR SpiceOrder 19 +PIN 64 -352 TOP 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 21 +PIN -176 -96 LEFT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 22 +PIN -176 -32 LEFT 8 +PINATTR PinName _PGOOD +PINATTR SpiceOrder 23 +PIN 176 96 RIGHT 8 +PINATTR PinName E3 +PINATTR SpiceOrder 24 +PIN 176 -32 RIGHT 8 +PINATTR PinName CT +PINATTR SpiceOrder 25 +PIN 176 32 RIGHT 8 +PINATTR PinName Von +PINATTR SpiceOrder 26 +PIN 176 -288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 27 diff --git a/spice/copy/sym/PowerProducts/LT1944-1.asy b/spice/copy/sym/PowerProducts/LT1944-1.asy new file mode 100755 index 0000000..db789a8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1944-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1944-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT1944-1.sub +SYMATTR Value2 LT1944-1 +SYMATTR Description Dual µPower Step-Up DC/DC Converter +PIN -176 64 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 176 -64 RIGHT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 4 +PIN 176 64 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 176 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN 112 128 BOTTOM 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -112 128 BOTTOM 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 9 +PIN -176 0 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT1944.asy b/spice/copy/sym/PowerProducts/LT1944.asy new file mode 100755 index 0000000..a324347 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1944.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1944 +SYMATTR Prefix X +SYMATTR SpiceModel LT1944.sub +SYMATTR Value2 LT1944 +SYMATTR Description Dual µPower Step-Up DC/DC Converter +PIN -176 64 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 176 -64 RIGHT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 4 +PIN 176 64 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 176 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN 112 128 BOTTOM 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -112 128 BOTTOM 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 9 +PIN -176 0 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT1945.asy b/spice/copy/sym/PowerProducts/LT1945.asy new file mode 100755 index 0000000..1136462 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1945.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1945 +SYMATTR Prefix X +SYMATTR SpiceModel LT1945.sub +SYMATTR Value2 LT1945 +SYMATTR Description Dual µPower Step-Up DC/DC Converter +PIN -176 64 LEFT 8 +PINATTR PinName NFB1 +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 176 -64 RIGHT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 4 +PIN 176 64 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 176 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN 112 128 BOTTOM 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -112 128 BOTTOM 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 9 +PIN -176 0 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT1946.asy b/spice/copy/sym/PowerProducts/LT1946.asy new file mode 100755 index 0000000..8665d8e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1946.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1946 +SYMATTR Prefix X +SYMATTR SpiceModel LT1946.sub +SYMATTR Value2 LT1946 +SYMATTR Description 1.2MHz Boost DC/DC Converter with 1.5A Switch and Soft-Start +PIN -144 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 64 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 64 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN 144 64 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1946A.asy b/spice/copy/sym/PowerProducts/LT1946A.asy new file mode 100755 index 0000000..6dad1f4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1946A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1946A +SYMATTR Prefix X +SYMATTR SpiceModel LT1946A.sub +SYMATTR Value2 LT1946A +SYMATTR Description 2.7MHz Boost DC/DC Converter with 1.5A Switch and Soft-Start +PIN -144 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 64 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 64 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN 144 64 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1947.asy b/spice/copy/sym/PowerProducts/LT1947.asy new file mode 100755 index 0000000..ea0933c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1947.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -192 192 192 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT1947 +SYMATTR Prefix X +SYMATTR SpiceModel LT1947.sub +SYMATTR Value2 LT1947 +SYMATTR Description Adjustable Output TFT-LCD Triple Switching Regulator +PIN 192 -112 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 1 +PIN -192 0 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 2 +PIN -96 192 BOTTOM 8 +PINATTR PinName Ct +PINATTR SpiceOrder 3 +PIN 112 -192 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 4 +PIN 96 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -112 -192 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 7 +PIN -192 112 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 +PIN -192 -112 LEFT 8 +PINATTR PinName Vo2 +PINATTR SpiceOrder 9 +PIN 192 112 RIGHT 8 +PINATTR PinName Von +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT1949-1.asy b/spice/copy/sym/PowerProducts/LT1949-1.asy new file mode 100755 index 0000000..6b38622 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1949-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 89 Center 2 +SYMATTR Value LT1949-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT1949-1.sub +SYMATTR Value2 LT1949-1 +SYMATTR Description 1.1MHz, 1A PWM DC/DC Converter +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 80 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -80 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN -144 -64 LEFT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1949.asy b/spice/copy/sym/PowerProducts/LT1949.asy new file mode 100755 index 0000000..0115fdc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1949.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -95 Center 2 +WINDOW 3 0 90 Center 2 +SYMATTR Value LT1949 +SYMATTR Prefix X +SYMATTR SpiceModel LT1949.sub +SYMATTR Value2 LT1949 +SYMATTR Description 600kHz, 1A Switch PWM DC/DC Converter +PIN 144 64 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 80 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -80 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 7 +PIN -144 -64 LEFT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1950.asy b/spice/copy/sym/PowerProducts/LT1950.asy new file mode 100755 index 0000000..b208b8c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1950.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -208 176 192 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1950 +SYMATTR Value2 LT1950 +SYMATTR Prefix X +SYMATTR SpiceModel LT1950.sub +SYMATTR Description Single Switch PWM Controller with Auxiliary Boost Converter +PIN 176 64 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 176 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -192 64 LEFT 8 +PINATTR PinName Rosc +PINATTR SpiceOrder 3 +PIN -192 0 LEFT 8 +PINATTR PinName Slope +PINATTR SpiceOrder 5 +PIN -192 -64 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 6 +PIN -192 -128 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -80 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -192 128 LEFT 8 +PINATTR PinName Blank +PINATTR SpiceOrder 9 +PIN 176 0 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 10 +PIN 128 -208 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 11 +PIN 176 -64 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 12 +PIN 64 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 13 +PIN 0 -208 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 14 +PIN -128 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 176 -128 RIGHT 8 +PINATTR PinName Vsec +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1952-1.asy b/spice/copy/sym/PowerProducts/LT1952-1.asy new file mode 100755 index 0000000..45166b7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1952-1.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -240 176 272 +TEXT 0 9 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 89 Center 2 +SYMATTR Value LT1952-1 +SYMATTR Value2 LT1952-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT1952-1.sub +SYMATTR Description Single Switch Synchronous Forward Controller +PIN 176 48 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 176 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -192 48 LEFT 8 +PINATTR PinName Rosc +PINATTR SpiceOrder 3 +PIN -192 -32 LEFT 8 +PINATTR PinName SS_MAXDC +PINATTR SpiceOrder 5 +PIN -192 -112 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 6 +PIN -192 -192 LEFT 8 +PINATTR PinName SD_Vsec +PINATTR SpiceOrder 7 +PIN -80 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -192 208 LEFT 8 +PINATTR PinName Blank +PINATTR SpiceOrder 9 +PIN 176 -32 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 10 +PIN 176 -112 RIGHT 8 +PINATTR PinName OC +PINATTR SpiceOrder 11 +PIN -192 128 LEFT 8 +PINATTR PinName Delay +PINATTR SpiceOrder 12 +PIN 80 272 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 13 +PIN 176 -192 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 14 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 176 208 RIGHT 8 +PINATTR PinName SOUT +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1952.asy b/spice/copy/sym/PowerProducts/LT1952.asy new file mode 100755 index 0000000..0a85365 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1952.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -240 176 272 +TEXT 0 9 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 89 Center 2 +SYMATTR Value LT1952 +SYMATTR Value2 LT1952 +SYMATTR Prefix X +SYMATTR SpiceModel LT1952.sub +SYMATTR Description Single Switch Synchronous Forward Controller +PIN 176 48 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 1 +PIN 176 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -192 48 LEFT 8 +PINATTR PinName Rosc +PINATTR SpiceOrder 3 +PIN -192 -32 LEFT 8 +PINATTR PinName SS_MAXDC +PINATTR SpiceOrder 5 +PIN -192 -112 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 6 +PIN -192 -192 LEFT 8 +PINATTR PinName SD_Vsec +PINATTR SpiceOrder 7 +PIN -80 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -192 208 LEFT 8 +PINATTR PinName Blank +PINATTR SpiceOrder 9 +PIN 176 -32 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 10 +PIN 176 -112 RIGHT 8 +PINATTR PinName OC +PINATTR SpiceOrder 11 +PIN -192 128 LEFT 8 +PINATTR PinName Delay +PINATTR SpiceOrder 12 +PIN 80 272 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 13 +PIN 176 -192 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 14 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 176 208 RIGHT 8 +PINATTR PinName SOUT +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1956-5.asy b/spice/copy/sym/PowerProducts/LT1956-5.asy new file mode 100755 index 0000000..f5be914 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1956-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 8 40 Center 2 +SYMATTR Value LT1956-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1956-5.sub +SYMATTR Value2 LT1956-5 +SYMATTR Description High Voltage, 1.5A, 500KHz Step-Down Switching Regulator, Fixed 5V Output +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 12 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT1956.asy b/spice/copy/sym/PowerProducts/LT1956.asy new file mode 100755 index 0000000..b624edc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1956.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value LT1956 +SYMATTR Prefix X +SYMATTR SpiceModel LT1956.sub +SYMATTR Value2 LT1956 +SYMATTR Description High Voltage, 1.5A, 500KHz Step-Down Switching Regulator +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT1959.asy b/spice/copy/sym/PowerProducts/LT1959.asy new file mode 100755 index 0000000..59b7703 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1959.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1959 +SYMATTR Prefix X +SYMATTR SpiceModel LT1959.sub +SYMATTR Value2 LT1959 +SYMATTR Description 4.5A, 500KHz Step-Down Switching Regulator, Adjustable Output Voltage +PIN -80 -160 TOP 8 +PINATTR PinName VIN +PINATTR SpiceOrder 1 +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 80 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -160 64 LEFT 8 +PINATTR PinName VC +PINATTR SpiceOrder 5 +PIN -160 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 160 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN -80 160 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1961.asy b/spice/copy/sym/PowerProducts/LT1961.asy new file mode 100755 index 0000000..2554db1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1961.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT1961 +SYMATTR Prefix X +SYMATTR SpiceModel LT1961.sub +SYMATTR Value2 LT1961 +SYMATTR Description 1.5A, 1.25MHz Step-Up Switching Regulator +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT1962-1.5.asy b/spice/copy/sym/PowerProducts/LT1962-1.5.asy new file mode 100755 index 0000000..1f38b52 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1962-1.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1962-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1962.lib +SYMATTR Value2 LT1962-1.5 +SYMATTR Description 300mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 1.5V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1962-1.8.asy b/spice/copy/sym/PowerProducts/LT1962-1.8.asy new file mode 100755 index 0000000..0d86ccd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1962-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1962-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1962.lib +SYMATTR Value2 LT1962-1.8 +SYMATTR Description 300mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 1.8V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1962-2.5.asy b/spice/copy/sym/PowerProducts/LT1962-2.5.asy new file mode 100755 index 0000000..c966d6d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1962-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1962-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1962.lib +SYMATTR Value2 LT1962-2.5 +SYMATTR Description 300mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 2.5V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1962-3.3.asy b/spice/copy/sym/PowerProducts/LT1962-3.3.asy new file mode 100755 index 0000000..0d6fbb1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1962-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1962-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1962.lib +SYMATTR Value2 LT1962-3.3 +SYMATTR Description 300mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 3.3V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1962-3.asy b/spice/copy/sym/PowerProducts/LT1962-3.asy new file mode 100755 index 0000000..ecdd343 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1962-3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1962-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1962.lib +SYMATTR Value2 LT1962-3 +SYMATTR Description 300mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 3V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1962-5.asy b/spice/copy/sym/PowerProducts/LT1962-5.asy new file mode 100755 index 0000000..d0520c6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1962-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1962-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1962.lib +SYMATTR Value2 LT1962-5 +SYMATTR Description 300mA Low Noise Low Dropout µPower Regulator with Shutdown, Fixed 5V Output +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1962.asy b/spice/copy/sym/PowerProducts/LT1962.asy new file mode 100755 index 0000000..4c6dfac --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1962.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1962 +SYMATTR Prefix X +SYMATTR SpiceModel LT1962.lib +SYMATTR Value2 LT1962 +SYMATTR Description 300mA Low Noise Low Dropout µPower Regulator with Shutdown, Adjustable Output Voltage +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT1963-1.5.asy b/spice/copy/sym/PowerProducts/LT1963-1.5.asy new file mode 100755 index 0000000..add123a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963-1.5 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Fixed 1.5V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1963-1.8.asy b/spice/copy/sym/PowerProducts/LT1963-1.8.asy new file mode 100755 index 0000000..0dae753 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963-1.8 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Fixed 1.8V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1963-2.5.asy b/spice/copy/sym/PowerProducts/LT1963-2.5.asy new file mode 100755 index 0000000..efb904d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963-2.5 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Fixed 2.5V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1963-3.3.asy b/spice/copy/sym/PowerProducts/LT1963-3.3.asy new file mode 100755 index 0000000..1c69836 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963-3.3 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Fixed 3.3V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1963.asy b/spice/copy/sym/PowerProducts/LT1963.asy new file mode 100755 index 0000000..abcfe74 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963 +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Adjustable Output Voltage +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1963A-1.5.asy b/spice/copy/sym/PowerProducts/LT1963A-1.5.asy new file mode 100755 index 0000000..8f438f0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963A-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963A-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963-1.5 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Fixed 1.5V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1963A-1.8.asy b/spice/copy/sym/PowerProducts/LT1963A-1.8.asy new file mode 100755 index 0000000..cc26334 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963A-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963A-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963-1.8 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Fixed 1.8V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1963A-2.5.asy b/spice/copy/sym/PowerProducts/LT1963A-2.5.asy new file mode 100755 index 0000000..d8b22d7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963A-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963A-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963-2.5 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Fixed 2.5V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1963A-3.3.asy b/spice/copy/sym/PowerProducts/LT1963A-3.3.asy new file mode 100755 index 0000000..7a711b0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963A-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963A-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963-3.3 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Fixed 3.3V Output +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1963A.asy b/spice/copy/sym/PowerProducts/LT1963A.asy new file mode 100755 index 0000000..d62ceae --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1963A.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT1963A +SYMATTR Prefix X +SYMATTR SpiceModel LT1963.lib +SYMATTR Value2 LT1963 +SYMATTR Description 1.5A, Low Noise, Fast Transient Response LDO Regulator, Adjustable Output Voltage +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1964-5.asy b/spice/copy/sym/PowerProducts/LT1964-5.asy new file mode 100755 index 0000000..ac99d95 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1964-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 15 125 Left 2 +SYMATTR Value LT1964-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1964.lib +SYMATTR Value2 LT1964-5 +SYMATTR Description 200mA, Low Noise, Low Dropout Negative µPower Regulator in ThinSOT, Fixed -5V Output +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1964-BYP.asy b/spice/copy/sym/PowerProducts/LT1964-BYP.asy new file mode 100755 index 0000000..c7e5772 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1964-BYP.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 10 125 Left 2 +SYMATTR Value LT1964-BYP +SYMATTR Prefix X +SYMATTR SpiceModel LT1964.lib +SYMATTR Value2 LT1964-BYP +SYMATTR Description 200mA, Low Noise, Low Dropout Negative µPower Regulator in ThinSOT, Adjustable Output Voltage +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1964-SD.asy b/spice/copy/sym/PowerProducts/LT1964-SD.asy new file mode 100755 index 0000000..952298a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1964-SD.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 13 127 Left 2 +SYMATTR Value LT1964-SD +SYMATTR Prefix X +SYMATTR SpiceModel LT1964.lib +SYMATTR Value2 LT1964-SD +SYMATTR Description 200mA, Low Noise, Low Dropout Negative µPower Regulator in ThinSOT, Adjustable Output Voltage +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1965-1.5.asy b/spice/copy/sym/PowerProducts/LT1965-1.5.asy new file mode 100755 index 0000000..8b45d71 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1965-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 128 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1965-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1965.lib +SYMATTR Value2 LT1965-x.x R=2.85K +SYMATTR Description 1.1A, Low Noise, Low Dropout Linear Regulator, Fixed 1.5V Output +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1965-1.8.asy b/spice/copy/sym/PowerProducts/LT1965-1.8.asy new file mode 100755 index 0000000..a95148c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1965-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 128 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1965-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT1965.lib +SYMATTR Value2 LT1965-x.x R=5.8K +SYMATTR Description 1.1A, Low Noise, Low Dropout Linear Regulator, Fixed 1.8V Output +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1965-2.5.asy b/spice/copy/sym/PowerProducts/LT1965-2.5.asy new file mode 100755 index 0000000..34ebb06 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1965-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 128 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1965-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1965.lib +SYMATTR Value2 LT1965-x.x R=12.66K +SYMATTR Description 1.1A, Low Noise, Low Dropout Linear Regulator, Fixed 2.5V Output +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1965-3.3.asy b/spice/copy/sym/PowerProducts/LT1965-3.3.asy new file mode 100755 index 0000000..a4bb302 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1965-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 128 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1965-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT1965.lib +SYMATTR Value2 LT1965-x.x R=20.52K +SYMATTR Description 1.1A, Low Noise, Low Dropout Linear Regulator, Fixed 3.3V Output +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1965.asy b/spice/copy/sym/PowerProducts/LT1965.asy new file mode 100755 index 0000000..42a3f5c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1965.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1965 +SYMATTR Prefix X +SYMATTR SpiceModel LT1965.lib +SYMATTR Value2 LT1965 +SYMATTR Description 1.1A, Low Noise, Low Dropout Linear Regulator, Adjustable Output Voltage +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1965B.asy b/spice/copy/sym/PowerProducts/LT1965B.asy new file mode 100755 index 0000000..e2540ee --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1965B.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT1965B +SYMATTR Prefix X +SYMATTR SpiceModel LT1965.lib +SYMATTR Value2 LT1965 +SYMATTR Description 1.1A, Low Noise, Low Dropout Linear Regulator, Adjustable Output Voltage +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT1976.asy b/spice/copy/sym/PowerProducts/LT1976.asy new file mode 100755 index 0000000..bb5d433 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1976.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 224 +TEXT 0 -39 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT1976 +SYMATTR Prefix X +SYMATTR SpiceModel LT1976.sub +SYMATTR Value2 LT1976 +SYMATTR Description High Voltage 1.5A, 200KHz Step-Down Switching Regulator with 100µA Quiescent Current +PIN 160 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -64 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 64 -224 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN -160 160 LEFT 8 +PINATTR PinName CT +PINATTR SpiceOrder 7 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName Css +PINATTR SpiceOrder 9 +PIN 160 -80 RIGHT 8 +PINATTR PinName VBIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 160 160 RIGHT 8 +PINATTR PinName PGFB +PINATTR SpiceOrder 13 +PIN -160 -160 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 +PIN -160 -80 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1976B.asy b/spice/copy/sym/PowerProducts/LT1976B.asy new file mode 100755 index 0000000..b135108 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1976B.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 224 +TEXT 0 -39 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT1976B +SYMATTR Prefix X +SYMATTR SpiceModel LT1976B.sub +SYMATTR Value2 LT1976B +SYMATTR Description High Voltage 1.5A, 200KHz Step-Down Switching Regulator with 100µA Quiescent Current +PIN 160 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -64 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 64 -224 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN -160 160 LEFT 8 +PINATTR PinName CT +PINATTR SpiceOrder 7 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName Css +PINATTR SpiceOrder 9 +PIN 160 -80 RIGHT 8 +PINATTR PinName VBIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 160 160 RIGHT 8 +PINATTR PinName PGFB +PINATTR SpiceOrder 13 +PIN -160 -160 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 +PIN -160 -80 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT1977.asy b/spice/copy/sym/PowerProducts/LT1977.asy new file mode 100755 index 0000000..f3943fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT1977.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 224 +TEXT 0 -39 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT1977 +SYMATTR Prefix X +SYMATTR SpiceModel LT1977.sub +SYMATTR Value2 LT1977 +SYMATTR Description High Voltage 1.5A, 500KHz Step-Down Switching Regulator with 100µA Quiescent Current +PIN 160 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -64 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 64 -224 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN -160 160 LEFT 8 +PINATTR PinName CT +PINATTR SpiceOrder 7 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName Css +PINATTR SpiceOrder 9 +PIN 160 -80 RIGHT 8 +PINATTR PinName VBIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 160 160 RIGHT 8 +PINATTR PinName PGFB +PINATTR SpiceOrder 13 +PIN -160 -160 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 +PIN -160 -80 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT2940.asy b/spice/copy/sym/PowerProducts/LT2940.asy new file mode 100755 index 0000000..adc645b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT2940.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -160 192 240 +TEXT 0 42 Center 2 LT +WINDOW 0 0 -39 Center 2 +WINDOW 3 1 121 Center 2 +SYMATTR Value LT2940 +SYMATTR Prefix X +SYMATTR SpiceModel LT2940.sub +SYMATTR Value2 LT2940 +SYMATTR Description Power and Current Monitor +PIN -192 80 LEFT 8 +PINATTR PinName _CmpOut +PINATTR SpiceOrder 1 +PIN -192 0 LEFT 8 +PINATTR PinName CmpOut +PINATTR SpiceOrder 2 +PIN -192 160 LEFT 8 +PINATTR PinName Cmp+ +PINATTR SpiceOrder 3 +PIN -112 240 BOTTOM 8 +PINATTR PinName Pmon +PINATTR SpiceOrder 4 +PIN 112 240 BOTTOM 8 +PINATTR PinName Imon +PINATTR SpiceOrder 5 +PIN 0 240 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 6 +PIN 192 112 RIGHT 8 +PINATTR PinName V- +PINATTR SpiceOrder 7 +PIN 192 -32 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 8 +PIN -192 -80 LEFT 8 +PINATTR PinName Latch +PINATTR SpiceOrder 9 +PIN 112 -160 TOP 8 +PINATTR PinName I- +PINATTR SpiceOrder 10 +PIN 0 -160 TOP 8 +PINATTR PinName I+ +PINATTR SpiceOrder 11 +PIN -112 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3001.asy b/spice/copy/sym/PowerProducts/LT3001.asy new file mode 100755 index 0000000..2433fff --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3001.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3001 +SYMATTR Prefix X +SYMATTR SpiceModel LT3001.sub +SYMATTR Value2 LT3001 +SYMATTR Description 36V 4W No-Opto Isolated Flyback Converter +PIN -112 64 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 112 64 RIGHT 8 +PINATTR PinName RFB +PINATTR SpiceOrder 3 +PIN 112 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -112 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3002.asy b/spice/copy/sym/PowerProducts/LT3002.asy new file mode 100755 index 0000000..ca7acfc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3002.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -192 112 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3002 +SYMATTR Prefix X +SYMATTR SpiceModel LT3002.sub +SYMATTR Value2 LT3002 +SYMATTR Description 36V 10W No-Opto Isolated Flyback Converter +PIN -112 -48 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN -112 48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN -112 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -112 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 -48 RIGHT 8 +PINATTR PinName RFB +PINATTR SpiceOrder 6 +PIN 112 48 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 7 +PIN 112 144 RIGHT 8 +PINATTR PinName Tc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3007-1.2.asy b/spice/copy/sym/PowerProducts/LT3007-1.2.asy new file mode 100755 index 0000000..eedc9c8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3007-1.2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3007-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-1.2 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Fault Tolerant Linear Regulator, Fixed 1.2V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3007-1.5.asy b/spice/copy/sym/PowerProducts/LT3007-1.5.asy new file mode 100755 index 0000000..52d63e9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3007-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3007-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-1.5 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Fault Tolerant Linear Regulator, Fixed 1.5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3007-1.8.asy b/spice/copy/sym/PowerProducts/LT3007-1.8.asy new file mode 100755 index 0000000..6820c0e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3007-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3007-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-1.8 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Fault Tolerant Linear Regulator, Fixed 1.8V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3007-2.5.asy b/spice/copy/sym/PowerProducts/LT3007-2.5.asy new file mode 100755 index 0000000..9b15395 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3007-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3007-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-2.5 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Fault Tolerant Linear Regulator, Fixed 2.5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3007-3.3.asy b/spice/copy/sym/PowerProducts/LT3007-3.3.asy new file mode 100755 index 0000000..65ff50d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3007-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3007-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-3.3 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Fault Tolerant Linear Regulator, Fixed 3.3V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3007-5.asy b/spice/copy/sym/PowerProducts/LT3007-5.asy new file mode 100755 index 0000000..9aaaf86 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3007-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3007-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-5 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Fault Tolerant Linear Regulator, Fixed 5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3007.asy b/spice/copy/sym/PowerProducts/LT3007.asy new file mode 100755 index 0000000..7e6e5ca --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3007.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3007 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Fault Tolerant Linear Regulator +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3008-1.2.asy b/spice/copy/sym/PowerProducts/LT3008-1.2.asy new file mode 100755 index 0000000..287cd04 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3008-1.2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3008-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-1.2 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Linear Regulator, Fixed 1.2V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3008-1.5.asy b/spice/copy/sym/PowerProducts/LT3008-1.5.asy new file mode 100755 index 0000000..7d9c328 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3008-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3008-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-1.5 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Linear Regulator, Fixed 1.5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3008-1.8.asy b/spice/copy/sym/PowerProducts/LT3008-1.8.asy new file mode 100755 index 0000000..0b79e3e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3008-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3008-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-1.8 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Linear Regulator, Fixed 1.8V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3008-2.5.asy b/spice/copy/sym/PowerProducts/LT3008-2.5.asy new file mode 100755 index 0000000..fa321e6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3008-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3008-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-2.5 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Linear Regulator, Fixed 2.5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3008-3.3.asy b/spice/copy/sym/PowerProducts/LT3008-3.3.asy new file mode 100755 index 0000000..4c89fd5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3008-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3008-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-3.3 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Linear Regulator, Fixed 3.3V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3008-5.asy b/spice/copy/sym/PowerProducts/LT3008-5.asy new file mode 100755 index 0000000..376cde0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3008-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3008-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008-5 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Linear Regulator, Fixed 5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3008.asy b/spice/copy/sym/PowerProducts/LT3008.asy new file mode 100755 index 0000000..bb05a09 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3008.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3008 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3008 +SYMATTR Description 3µA Iq, 20mA, 45V Low Dropout Linear Regulator +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3009-1.2.asy b/spice/copy/sym/PowerProducts/LT3009-1.2.asy new file mode 100755 index 0000000..0ca1c79 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3009-1.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3009-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3009-1.2 +SYMATTR Description 3µA Iq, 20mA Low Dropout Linear Regulator, Fixed 1.2V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3009-1.8.asy b/spice/copy/sym/PowerProducts/LT3009-1.8.asy new file mode 100755 index 0000000..db1c378 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3009-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3009-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3009-1.8 +SYMATTR Description 3µA Iq, 20mA Low Dropout Linear Regulator, Fixed 1.8V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3009-2.5.asy b/spice/copy/sym/PowerProducts/LT3009-2.5.asy new file mode 100755 index 0000000..a71d5b8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3009-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3009-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3009-2.5 +SYMATTR Description 3µA Iq, 20mA Low Dropout Linear Regulator, Fixed 2.5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3009-3.3.asy b/spice/copy/sym/PowerProducts/LT3009-3.3.asy new file mode 100755 index 0000000..71350aa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3009-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3009-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3009-3.3 +SYMATTR Description 3µA Iq, 20mA Low Dropout Linear Regulator, Fixed 3.3V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3009-5.asy b/spice/copy/sym/PowerProducts/LT3009-5.asy new file mode 100755 index 0000000..bfae0a4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3009-5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3009-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3009-5 +SYMATTR Description 3µA Iq, 20mA Low Dropout Linear Regulator, Fixed 5V Output +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3009.asy b/spice/copy/sym/PowerProducts/LT3009.asy new file mode 100755 index 0000000..27bb494 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3009.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LT3009 +SYMATTR Prefix X +SYMATTR SpiceModel LT3009.lib +SYMATTR Value2 LT3009 +SYMATTR Description 3µA Iq, 20mA Low Dropout Linear Regulator, Adjustable Output Voltage +PIN -144 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3010-5.asy b/spice/copy/sym/PowerProducts/LT3010-5.asy new file mode 100755 index 0000000..5c100fb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3010-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 12 125 Left 2 +SYMATTR Value LT3010-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3010.lib +SYMATTR Value2 LT3010-5 +SYMATTR Description 50mA, 3V to 80V Low Dropout µPower Linear Regulator, Fixed 5V Output +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3010.asy b/spice/copy/sym/PowerProducts/LT3010.asy new file mode 100755 index 0000000..ee8c2c1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3010.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 12 125 Left 2 +SYMATTR Value LT3010 +SYMATTR Prefix X +SYMATTR SpiceModel LT3010.lib +SYMATTR Value2 LT3010 +SYMATTR Description 50mA, 3V to 80V Low Dropout µPower Linear Regulator, Adjustable Output Voltage +PIN 144 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3011.asy b/spice/copy/sym/PowerProducts/LT3011.asy new file mode 100755 index 0000000..bb25683 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3011.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3011 +SYMATTR Prefix X +SYMATTR SpiceModel LT3010.lib +SYMATTR Value2 LT3011 +SYMATTR Description 50mA, 3V to 80V Low Dropout µPower Linear Regulator, Adjustable Output Voltage +PIN 144 -96 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 96 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 6 +PIN -144 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3012.asy b/spice/copy/sym/PowerProducts/LT3012.asy new file mode 100755 index 0000000..c2ca171 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3012.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3012 +SYMATTR Prefix X +SYMATTR SpiceModel LT3012.lib +SYMATTR Value2 LT3012 +SYMATTR Description 250mA, 4V to 80V Low Dropout µPower Linear Regulator +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3012B.asy b/spice/copy/sym/PowerProducts/LT3012B.asy new file mode 100755 index 0000000..be54e15 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3012B.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3012B +SYMATTR Prefix X +SYMATTR SpiceModel LT3012.lib +SYMATTR Value2 LT3012B +SYMATTR Description 250mA, 4V to 80V Low Dropout µPower Linear Regulator +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3013.asy b/spice/copy/sym/PowerProducts/LT3013.asy new file mode 100755 index 0000000..15a1bc0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3013.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3013 +SYMATTR Prefix X +SYMATTR SpiceModel LT3013.lib +SYMATTR Value2 LT3013 +SYMATTR Description 250mA, 4V to 80V Low Dropout µPower Linear Regulator with PWRGD +PIN 144 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 6 +PIN 144 80 RIGHT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 +PIN -144 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3013B.asy b/spice/copy/sym/PowerProducts/LT3013B.asy new file mode 100755 index 0000000..b93e85c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3013B.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3013B +SYMATTR Prefix X +SYMATTR SpiceModel LT3013.lib +SYMATTR Value2 LT3013B +SYMATTR Description 250mA, 4V to 80V Low Dropout µPower Linear Regulator with PWRGD +PIN 144 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 6 +PIN 144 80 RIGHT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 7 +PIN -144 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3014.asy b/spice/copy/sym/PowerProducts/LT3014.asy new file mode 100755 index 0000000..eeaa79d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3014.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3014 +SYMATTR Prefix X +SYMATTR SpiceModel LT3014.lib +SYMATTR Value2 LT3014 +SYMATTR Description 20mA, 3V to 80V Low Dropout µPower Linear Regulator +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 64 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3014B.asy b/spice/copy/sym/PowerProducts/LT3014B.asy new file mode 100755 index 0000000..2fdd7e5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3014B.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3014B +SYMATTR Prefix X +SYMATTR SpiceModel LT3014.lib +SYMATTR Value2 LT3014B +SYMATTR Description 20mA, 3V to 80V Low Dropout µPower Linear Regulator +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 64 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3015.asy b/spice/copy/sym/PowerProducts/LT3015.asy new file mode 100755 index 0000000..0f965fe --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3015.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 112 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3015 +SYMATTR Prefix X +SYMATTR SpiceModel LT3015.lib +SYMATTR Value2 LT3015 +SYMATTR Description 1.5A, Low Noise, Negative Linear Regulator with Precision Current Limit +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3020-1.2.asy b/spice/copy/sym/PowerProducts/LT3020-1.2.asy new file mode 100755 index 0000000..01baee9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3020-1.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3020-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3020.lib +SYMATTR Value2 LT3020-1.2 +SYMATTR Description 100mA, Low Voltage, Very Low Dropout Linear Regulator, Fixed 1.2V Output +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT3020-1.5.asy b/spice/copy/sym/PowerProducts/LT3020-1.5.asy new file mode 100755 index 0000000..32ea433 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3020-1.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3020-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3020.lib +SYMATTR Value2 LT3020-1.5 +SYMATTR Description 100mA, Low Voltage, Very Low Dropout Linear Regulator, Fixed 1.5V Output +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT3020-1.8.asy b/spice/copy/sym/PowerProducts/LT3020-1.8.asy new file mode 100755 index 0000000..d5f86d9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3020-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3020-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT3020.lib +SYMATTR Value2 LT3020-1.8 +SYMATTR Description 100mA, Low Voltage, Very Low Dropout Linear Regulator, Fixed 1.8V Output +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT3020.asy b/spice/copy/sym/PowerProducts/LT3020.asy new file mode 100755 index 0000000..a1826a9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3020.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3020 +SYMATTR Prefix X +SYMATTR SpiceModel LT3020.lib +SYMATTR Value2 LT3020 +SYMATTR Description 100mA, Low Voltage, Very Low Dropout Linear Regulator, Adjustable Output Voltage +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 144 64 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT3021-1.2.asy b/spice/copy/sym/PowerProducts/LT3021-1.2.asy new file mode 100755 index 0000000..03cf1fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3021-1.2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3021-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3021.lib +SYMATTR Value2 LT3021-1.2 +SYMATTR Description 500mA, Low Voltage, Very Low Dropout Linear Regulator, Fixed 1.2V Output +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3021-1.5.asy b/spice/copy/sym/PowerProducts/LT3021-1.5.asy new file mode 100755 index 0000000..bb8d370 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3021-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3021-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3021.lib +SYMATTR Value2 LT3021-1.5 +SYMATTR Description 500mA, Low Voltage, Very Low Dropout Linear Regulator, Fixed 1.5V Output +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3021-1.8.asy b/spice/copy/sym/PowerProducts/LT3021-1.8.asy new file mode 100755 index 0000000..5a752e6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3021-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3021-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT3021.lib +SYMATTR Value2 LT3021-1.8 +SYMATTR Description 500mA, Low Voltage, Very Low Dropout Linear Regulator, Fixed 1.8V Output +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3021.asy b/spice/copy/sym/PowerProducts/LT3021.asy new file mode 100755 index 0000000..3e712d6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3021.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3021 +SYMATTR Prefix X +SYMATTR SpiceModel LT3021.lib +SYMATTR Value2 LT3021 +SYMATTR Description 500mA, Low Voltage, Very Low Dropout Linear Regulator, Adjustable Output Voltage +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3022-1.2.asy b/spice/copy/sym/PowerProducts/LT3022-1.2.asy new file mode 100755 index 0000000..2aeef24 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3022-1.2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3022-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3022.sub +SYMATTR Value2 LT3022-1.2 +SYMATTR Description 1A, 0.9V to 10V, Very Low Dropout Linear Regulator, Fixed 1.2V Output Voltage +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3022-1.5.asy b/spice/copy/sym/PowerProducts/LT3022-1.5.asy new file mode 100755 index 0000000..299f5fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3022-1.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3022-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3022.sub +SYMATTR Value2 LT3022-1.5 +SYMATTR Description 1A, 0.9V to 10V, Very Low Dropout Linear Regulator, Fixed 1.5V Output Voltage +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3022-1.8.asy b/spice/copy/sym/PowerProducts/LT3022-1.8.asy new file mode 100755 index 0000000..570d434 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3022-1.8.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3022-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT3022.sub +SYMATTR Value2 LT3022-1.8 +SYMATTR Description 1A, 0.9V to 10V, Very Low Dropout Linear Regulator, Fixed 1.8V Output Voltage +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3022.asy b/spice/copy/sym/PowerProducts/LT3022.asy new file mode 100755 index 0000000..903eab9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3022.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3022 +SYMATTR Prefix X +SYMATTR SpiceModel LT3022.sub +SYMATTR Value2 LT3022 +SYMATTR Description 1A, 0.9V to 10V, Very Low Dropout Linear Regulator, Adjustable Output Voltage +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 7 +PIN -144 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3023.asy b/spice/copy/sym/PowerProducts/LT3023.asy new file mode 100755 index 0000000..deaf7fc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3023.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3023 +SYMATTR Prefix X +SYMATTR SpiceModel LT3023.lib +SYMATTR Value2 LT3023 +SYMATTR Description Dual 100mA, Low Dropout, Low Noise, µPower Regulator +PIN 144 128 RIGHT 8 +PINATTR PinName BYP2 +PINATTR SpiceOrder 1 +PIN 144 176 RIGHT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 2 +PIN -144 176 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 4 +PIN 144 -112 RIGHT 8 +PINATTR PinName BYP1 +PINATTR SpiceOrder 5 +PIN 144 -176 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 6 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 7 +PIN -144 -176 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 9 +PIN 144 64 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3024.asy b/spice/copy/sym/PowerProducts/LT3024.asy new file mode 100755 index 0000000..ee4313b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3024.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3024 +SYMATTR Prefix X +SYMATTR SpiceModel LT3024.lib +SYMATTR Value2 LT3024 +SYMATTR Description Dual 100mA/500mA Low Dropout, Low Noise, µPower Regulator +PIN 144 -112 RIGHT 8 +PINATTR PinName BYP1 +PINATTR SpiceOrder 1 +PIN 144 -176 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 2 +PIN -144 176 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 64 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 5 +PIN 144 128 RIGHT 8 +PINATTR PinName BYP2 +PINATTR SpiceOrder 6 +PIN 144 176 RIGHT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 8 +PIN -144 -176 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 9 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 11 +PIN 144 -64 RIGHT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3027.asy b/spice/copy/sym/PowerProducts/LT3027.asy new file mode 100755 index 0000000..2ebd090 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3027.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3027 +SYMATTR Prefix X +SYMATTR SpiceModel LT3027.lib +SYMATTR Value2 LT3027 +SYMATTR Description Dual 100mA, Low Dropout, Low Noise, µPower Regulator with Independent Inputs +PIN 144 128 RIGHT 8 +PINATTR PinName BYP2 +PINATTR SpiceOrder 1 +PIN 144 176 RIGHT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 4 +PIN 144 -112 RIGHT 8 +PINATTR PinName BYP1 +PINATTR SpiceOrder 5 +PIN 144 -176 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 6 +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 7 +PIN -144 -176 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 8 +PIN -144 0 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 9 +PIN 144 64 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 10 +PIN -144 176 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3028.asy b/spice/copy/sym/PowerProducts/LT3028.asy new file mode 100755 index 0000000..a76aee1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3028.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3028 +SYMATTR Prefix X +SYMATTR SpiceModel LT3028.lib +SYMATTR Value2 LT3028 +SYMATTR Description Dual 100mA/500mA Low Dropout, Low Noise, µPower Regulator with Independent Inputs +PIN 144 -112 RIGHT 8 +PINATTR PinName BYP1 +PINATTR SpiceOrder 1 +PIN 144 -176 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 3 +PIN -144 176 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 64 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 6 +PIN 144 128 RIGHT 8 +PINATTR PinName BYP2 +PINATTR SpiceOrder 8 +PIN 144 176 RIGHT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 9 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 10 +PIN -144 0 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 11 +PIN -144 -176 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 13 +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 15 +PIN 144 -64 RIGHT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3029.asy b/spice/copy/sym/PowerProducts/LT3029.asy new file mode 100755 index 0000000..6d2db87 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3029.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -288 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3029 +SYMATTR Prefix X +SYMATTR SpiceModel LT1763.lib +SYMATTR Value2 LT3029 +SYMATTR Description Dual 500mA/500mA Low Dropout, Low Noise, µPower Regulator +PIN 144 -240 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 2 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -144 RIGHT 8 +PINATTR PinName BYP1 +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 5 +PIN -160 48 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 6 +PIN -160 -144 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 7 +PIN -160 -240 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 9 +PIN 144 240 RIGHT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 10 +PIN 144 144 RIGHT 8 +PINATTR PinName BYP2 +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3030.asy b/spice/copy/sym/PowerProducts/LT3030.asy new file mode 100755 index 0000000..b502301 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3030.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -288 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3030 +SYMATTR Prefix X +SYMATTR SpiceModel LT1763.lib +SYMATTR Value2 LT3030 +SYMATTR Description Dual 750mA/250mA Low Dropout, Low Noise, µPower Linear Regulator +PIN 144 -240 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 2 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 -144 RIGHT 8 +PINATTR PinName BYP1 +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 5 +PIN -160 48 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 6 +PIN -160 -144 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 7 +PIN -160 -240 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 9 +PIN 144 240 RIGHT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 10 +PIN 144 144 RIGHT 8 +PINATTR PinName BYP2 +PINATTR SpiceOrder 11 +PIN -160 144 LEFT 8 +PINATTR PinName PWRGD1 +PINATTR SpiceOrder 12 +PIN -160 240 LEFT 8 +PINATTR PinName PWRGD2 +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3032-5.asy b/spice/copy/sym/PowerProducts/LT3032-5.asy new file mode 100755 index 0000000..f6ffdb1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3032-5.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -224 128 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3032-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3032.lib +SYMATTR Value2 LT3032-5 +SYMATTR Description Dual 150mA Positive/Negative Low Noise Low Dropout Regulator, Fixed +/- 5V Output +PIN 128 -192 RIGHT 8 +PINATTR PinName OUTP +PINATTR SpiceOrder 1 +PIN 128 -96 RIGHT 8 +PINATTR PinName BYPP +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 192 LEFT 8 +PINATTR PinName INN +PINATTR SpiceOrder 6 +PIN 128 192 RIGHT 8 +PINATTR PinName OUTN +PINATTR SpiceOrder 7 +PIN -128 96 LEFT 8 +PINATTR PinName _SHDNN +PINATTR SpiceOrder 10 +PIN 128 96 RIGHT 8 +PINATTR PinName BYPN +PINATTR SpiceOrder 11 +PIN -128 -96 LEFT 8 +PINATTR PinName _SHDNP +PINATTR SpiceOrder 12 +PIN -128 -192 LEFT 8 +PINATTR PinName INP +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT3032.asy b/spice/copy/sym/PowerProducts/LT3032.asy new file mode 100755 index 0000000..11e41ff --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3032.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -320 128 320 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3032 +SYMATTR Prefix X +SYMATTR SpiceModel LT3032.lib +SYMATTR Value2 LT3032 +SYMATTR Description Dual 150mA Positive/Negative Low Noise Low Dropout Regulator, Adjustable Output Voltage +PIN 128 -288 RIGHT 8 +PINATTR PinName OUTP +PINATTR SpiceOrder 1 +PIN 128 -96 RIGHT 8 +PINATTR PinName ADJP +PINATTR SpiceOrder 2 +PIN 128 -192 RIGHT 8 +PINATTR PinName BYPP +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 288 LEFT 8 +PINATTR PinName INN +PINATTR SpiceOrder 6 +PIN 128 288 RIGHT 8 +PINATTR PinName OUTN +PINATTR SpiceOrder 7 +PIN 128 96 RIGHT 8 +PINATTR PinName ADJN +PINATTR SpiceOrder 8 +PIN -128 96 LEFT 8 +PINATTR PinName _SHDNN +PINATTR SpiceOrder 10 +PIN 128 192 RIGHT 8 +PINATTR PinName BYPN +PINATTR SpiceOrder 11 +PIN -128 -96 LEFT 8 +PINATTR PinName _SHDNP +PINATTR SpiceOrder 12 +PIN -128 -288 LEFT 8 +PINATTR PinName INP +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT3033.asy b/spice/copy/sym/PowerProducts/LT3033.asy new file mode 100755 index 0000000..bb209a6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3033.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 224 +TEXT 0 8 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 1 121 Center 2 +SYMATTR Value LT3033 +SYMATTR Prefix X +SYMATTR SpiceModel LT3033.sub +SYMATTR Value2 LT3033 +SYMATTR Description 3A, 0.95V to 10V, Very Low Dropout Linear Regulator with Programmable Current Limit +PIN -128 -160 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 128 -160 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -128 176 LEFT 8 +PINATTR PinName ILIM +PINATTR SpiceOrder 7 +PIN 128 176 RIGHT 8 +PINATTR PinName IMON +PINATTR SpiceOrder 8 +PIN 128 64 RIGHT 8 +PINATTR PinName REF/BYP +PINATTR SpiceOrder 9 +PIN 128 -48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 10 +PIN -128 64 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 11 +PIN -128 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3042.asy b/spice/copy/sym/PowerProducts/LT3042.asy new file mode 100755 index 0000000..d09dee1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3042.asy @@ -0,0 +1,69 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -48 -112 +LINE Normal 64 -40 -48 32 +LINE Normal -48 -112 64 -40 +LINE Normal -198 -144 96 -144 +LINE Normal 96 -64 96 -144 +LINE Normal 80 -47 96 -64 +LINE Normal 96 -17 80 -32 +LINE Normal 96 0 96 -17 +LINE Normal 240 0 96 0 +LINE Normal 80 -16 80 -64 +LINE Normal 80 -40 64 -40 +LINE Normal -80 -16 -48 -16 +LINE Normal -80 80 -80 -16 +LINE Normal 229 80 -80 80 +LINE Normal -128 -64 -48 -64 +LINE Normal -128 123 -128 -77 +LINE Normal -128 -144 -128 -128 +LINE Normal -35 -64 -43 -64 +LINE Normal -35 -16 -43 -16 +LINE Normal -39 -12 -39 -20 +LINE Normal 86 -56 80 -47 +LINE Normal 89 -53 80 -47 +LINE Normal 89 -53 86 -56 +RECTANGLE Normal -240 -192 304 160 +CIRCLE Normal -112 -96 -144 -128 +CIRCLE Normal -112 -77 -144 -109 +CIRCLE Normal -127 -63 -129 -65 +CIRCLE Normal -126 -62 -130 -66 +CIRCLE Normal -125 -61 -131 -67 +CIRCLE Normal -127 -143 -129 -145 +CIRCLE Normal -126 -142 -130 -146 +CIRCLE Normal -125 -141 -131 -147 +TEXT -7 -41 Center 2 LT +WINDOW 0 202 -143 Center 2 +WINDOW 3 202 -79 Center 2 +SYMATTR Value LT3042 +SYMATTR Prefix X +SYMATTR SpiceModel LT3042.sub +SYMATTR Value2 LT3042 +SYMATTR Description 20V, 200mA, Ultralow Noise, Ultrahigh PSRR RF Linear Regulator +PIN -240 -144 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -240 0 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 3 +PIN -240 112 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 96 160 BOTTOM 8 +PINATTR PinName ILIM +PINATTR SpiceOrder 5 +PIN 224 160 BOTTOM 8 +PINATTR PinName PGFB +PINATTR SpiceOrder 6 +PIN -128 160 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 304 80 RIGHT 8 +PINATTR PinName OUTS +PINATTR SpiceOrder 9 +PIN 304 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3045-1.asy b/spice/copy/sym/PowerProducts/LT3045-1.asy new file mode 100755 index 0000000..673a6d7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3045-1.asy @@ -0,0 +1,72 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -48 -112 +LINE Normal 64 -40 -48 32 +LINE Normal -48 -112 64 -40 +LINE Normal -198 -144 96 -144 +LINE Normal 96 -64 96 -144 +LINE Normal 80 -47 96 -64 +LINE Normal 96 -17 80 -32 +LINE Normal 96 0 96 -17 +LINE Normal 240 0 96 0 +LINE Normal 80 -16 80 -64 +LINE Normal 80 -40 64 -40 +LINE Normal -80 -16 -48 -16 +LINE Normal -80 80 -80 -16 +LINE Normal 229 80 -80 80 +LINE Normal -128 -64 -48 -64 +LINE Normal -128 123 -128 -77 +LINE Normal -128 -144 -128 -128 +LINE Normal -35 -64 -43 -64 +LINE Normal -35 -16 -43 -16 +LINE Normal -39 -12 -39 -20 +LINE Normal 86 -56 80 -47 +LINE Normal 89 -53 80 -47 +LINE Normal 89 -53 86 -56 +RECTANGLE Normal -240 -192 304 160 +CIRCLE Normal -112 -96 -144 -128 +CIRCLE Normal -112 -77 -144 -109 +CIRCLE Normal -127 -63 -129 -65 +CIRCLE Normal -126 -62 -130 -66 +CIRCLE Normal -125 -61 -131 -67 +CIRCLE Normal -127 -143 -129 -145 +CIRCLE Normal -126 -142 -130 -146 +CIRCLE Normal -125 -141 -131 -147 +TEXT -7 -41 Center 2 LT +WINDOW 0 202 -143 Center 2 +WINDOW 3 202 -79 Center 2 +SYMATTR Value LT3045-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3045-1.sub +SYMATTR Value2 LT3045-1 +SYMATTR Description 20V, 500mA, Ultralow Noise, Ultrahigh PSRR Linear Regulator with VIOC Control +PIN -240 -144 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -240 16 LEFT 8 +PINATTR PinName VIOC +PINATTR SpiceOrder 11 +PIN -240 -64 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 3 +PIN -240 96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 96 160 BOTTOM 8 +PINATTR PinName ILIM +PINATTR SpiceOrder 5 +PIN 224 160 BOTTOM 8 +PINATTR PinName PGFB +PINATTR SpiceOrder 6 +PIN -128 160 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 304 80 RIGHT 8 +PINATTR PinName OUTS +PINATTR SpiceOrder 9 +PIN 304 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3045.asy b/spice/copy/sym/PowerProducts/LT3045.asy new file mode 100755 index 0000000..1f35754 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3045.asy @@ -0,0 +1,69 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -48 -112 +LINE Normal 64 -40 -48 32 +LINE Normal -48 -112 64 -40 +LINE Normal -198 -144 96 -144 +LINE Normal 96 -64 96 -144 +LINE Normal 80 -47 96 -64 +LINE Normal 96 -17 80 -32 +LINE Normal 96 0 96 -17 +LINE Normal 240 0 96 0 +LINE Normal 80 -16 80 -64 +LINE Normal 80 -40 64 -40 +LINE Normal -80 -16 -48 -16 +LINE Normal -80 80 -80 -16 +LINE Normal 229 80 -80 80 +LINE Normal -128 -64 -48 -64 +LINE Normal -128 123 -128 -77 +LINE Normal -128 -144 -128 -128 +LINE Normal -35 -64 -43 -64 +LINE Normal -35 -16 -43 -16 +LINE Normal -39 -12 -39 -20 +LINE Normal 86 -56 80 -47 +LINE Normal 89 -53 80 -47 +LINE Normal 89 -53 86 -56 +RECTANGLE Normal -240 -192 304 160 +CIRCLE Normal -112 -96 -144 -128 +CIRCLE Normal -112 -77 -144 -109 +CIRCLE Normal -127 -63 -129 -65 +CIRCLE Normal -126 -62 -130 -66 +CIRCLE Normal -125 -61 -131 -67 +CIRCLE Normal -127 -143 -129 -145 +CIRCLE Normal -126 -142 -130 -146 +CIRCLE Normal -125 -141 -131 -147 +TEXT -7 -41 Center 2 LT +WINDOW 0 202 -143 Center 2 +WINDOW 3 202 -79 Center 2 +SYMATTR Value LT3045 +SYMATTR Prefix X +SYMATTR SpiceModel LT3045.sub +SYMATTR Value2 LT3045 +SYMATTR Description 20V, 500mA, Ultralow Noise, Ultrahigh PSRR RF Linear Regulator +PIN -240 -144 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -240 0 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 3 +PIN -240 112 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 96 160 BOTTOM 8 +PINATTR PinName ILIM +PINATTR SpiceOrder 5 +PIN 224 160 BOTTOM 8 +PINATTR PinName PGFB +PINATTR SpiceOrder 6 +PIN -128 160 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 304 80 RIGHT 8 +PINATTR PinName OUTS +PINATTR SpiceOrder 9 +PIN 304 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3048-12.asy b/spice/copy/sym/PowerProducts/LT3048-12.asy new file mode 100755 index 0000000..bf3452e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3048-12.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 64 Center 2 +SYMATTR Value LT3048-12 +SYMATTR Prefix X +SYMATTR SpiceModel LT3048-12.sub +SYMATTR Value2 LT3048-12 +SYMATTR Description Low Noise Bias Generator in 2mm*2mm DFN +PIN -144 -96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 96 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 0 RIGHT 8 +PINATTR PinName LDOOUT +PINATTR SpiceOrder 5 +PIN 144 -96 RIGHT 8 +PINATTR PinName LDOIN +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName BSTOUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3048-15.asy b/spice/copy/sym/PowerProducts/LT3048-15.asy new file mode 100755 index 0000000..14ddc4d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3048-15.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 64 Center 2 +SYMATTR Value LT3048-15 +SYMATTR Prefix X +SYMATTR SpiceModel LT3048-15.sub +SYMATTR Value2 LT3048-15 +SYMATTR Description Low Noise Bias Generator in 2mm*2mm DFN +PIN -144 -96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 96 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 0 RIGHT 8 +PINATTR PinName LDOOUT +PINATTR SpiceOrder 5 +PIN 144 -96 RIGHT 8 +PINATTR PinName LDOIN +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName BSTOUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3048-3.3.asy b/spice/copy/sym/PowerProducts/LT3048-3.3.asy new file mode 100755 index 0000000..e460f64 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3048-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 64 Center 2 +SYMATTR Value LT3048-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3048-3.3.sub +SYMATTR Value2 LT3048-3.3 +SYMATTR Description Low Noise Bias Generator in 2mm*2mm DFN +PIN -144 -96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 96 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 0 RIGHT 8 +PINATTR PinName LDOOUT +PINATTR SpiceOrder 5 +PIN 144 -96 RIGHT 8 +PINATTR PinName LDOIN +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName BSTOUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3048-5.asy b/spice/copy/sym/PowerProducts/LT3048-5.asy new file mode 100755 index 0000000..dda78b9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3048-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 64 Center 2 +SYMATTR Value LT3048-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3048-5.sub +SYMATTR Value2 LT3048-5 +SYMATTR Description Low Noise Bias Generator in 2mm*2mm DFN +PIN -144 -96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 96 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 0 RIGHT 8 +PINATTR PinName LDOOUT +PINATTR SpiceOrder 5 +PIN 144 -96 RIGHT 8 +PINATTR PinName LDOIN +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName BSTOUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3048.asy b/spice/copy/sym/PowerProducts/LT3048.asy new file mode 100755 index 0000000..fc988eb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3048.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 64 Center 2 +SYMATTR Value LT3048 +SYMATTR Prefix X +SYMATTR SpiceModel LT3048.sub +SYMATTR Value2 LT3048 +SYMATTR Description Low Noise Bias Generator in 2mm*2mm DFN +PIN -144 -96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 4 +PIN 144 -96 RIGHT 8 +PINATTR PinName LDOOUT +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName BSTOUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3050-3.3.asy b/spice/copy/sym/PowerProducts/LT3050-3.3.asy new file mode 100755 index 0000000..672c30c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3050-3.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 224 -128 -224 +TEXT 0 0 Center 2 LT +WINDOW 123 0 128 Center 2 +WINDOW 0 0 -128 Center 2 +SYMATTR Value2 LT3050-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3050-3.3.sub +SYMATTR Value LT3050-3.3 +SYMATTR Description 100mA, Linear Regulator with Precision Current Limit and Diagnostic Output +PIN 128 96 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN -128 192 LEFT 8 +PINATTR PinName Imin +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 3 +PIN -128 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -128 -192 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN 128 -192 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 9 +PIN 128 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -128 96 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 11 +PIN 128 0 RIGHT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3050-5.asy b/spice/copy/sym/PowerProducts/LT3050-5.asy new file mode 100755 index 0000000..43ef796 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3050-5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 224 -128 -224 +TEXT 0 0 Center 2 LT +WINDOW 123 0 128 Center 2 +WINDOW 0 0 -128 Center 2 +SYMATTR Value2 LT3050-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3050-5.sub +SYMATTR Value LT3050-5 +SYMATTR Description 100mA, Linear Regulator with Precision Current Limit and Diagnostic Output +PIN 128 96 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN -128 192 LEFT 8 +PINATTR PinName Imin +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 3 +PIN -128 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -128 -192 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN 128 -192 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 9 +PIN 128 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -128 96 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 11 +PIN 128 0 RIGHT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3050.asy b/spice/copy/sym/PowerProducts/LT3050.asy new file mode 100755 index 0000000..4ff4023 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3050.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 224 -128 -224 +TEXT 0 0 Center 2 LT +WINDOW 123 0 128 Center 2 +WINDOW 0 0 -128 Center 2 +SYMATTR Value2 LT3050 +SYMATTR Prefix X +SYMATTR SpiceModel LT3050.sub +SYMATTR Value LT3050 +SYMATTR Description 100mA, Linear Regulator with Precision Current Limit and Diagnostic Output +PIN 128 96 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN -128 192 LEFT 8 +PINATTR PinName Imin +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 3 +PIN -128 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -128 -192 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN 128 -192 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 9 +PIN 128 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -128 96 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 11 +PIN 128 0 RIGHT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3055.asy b/spice/copy/sym/PowerProducts/LT3055.asy new file mode 100755 index 0000000..6af74ec --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3055.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 304 -128 -304 +TEXT 0 0 Center 2 LT +WINDOW 123 0 176 Center 2 +WINDOW 0 0 -176 Center 2 +SYMATTR Value2 LT3055 +SYMATTR Prefix X +SYMATTR SpiceModel LT3055.sub +SYMATTR Value LT3055 +SYMATTR Description 500mA, Linear Regulator with Precision Current Limit and Diagnostics +PIN -128 -240 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -128 -144 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -128 -48 LEFT 8 +PINATTR PinName _Fault1 +PINATTR SpiceOrder 4 +PIN -128 48 LEFT 8 +PINATTR PinName _Fault2 +PINATTR SpiceOrder 5 +PIN -128 144 LEFT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 6 +PIN -128 240 LEFT 8 +PINATTR PinName Temp +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 8 +PIN 128 240 RIGHT 8 +PINATTR PinName Imin +PINATTR SpiceOrder 9 +PIN 128 144 RIGHT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 10 +PIN 128 -48 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 11 +PIN 0 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 +PIN 128 -144 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 14 +PIN 128 -240 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3060-1.2.asy b/spice/copy/sym/PowerProducts/LT3060-1.2.asy new file mode 100755 index 0000000..5907dd8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3060-1.2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3060-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3060-1.2.sub +SYMATTR Value LT3060-1.2 +SYMATTR Description 45Vin, µPower, Low Noise, 100mA Low Dropout, Linear Regulator +PIN 128 112 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3060-1.5.asy b/spice/copy/sym/PowerProducts/LT3060-1.5.asy new file mode 100755 index 0000000..5b6f7c2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3060-1.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3060-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3060-1.5.sub +SYMATTR Value LT3060-1.5 +SYMATTR Description 45Vin, µPower, Low Noise, 100mA Low Dropout, Linear Regulator +PIN 128 112 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3060-1.8.asy b/spice/copy/sym/PowerProducts/LT3060-1.8.asy new file mode 100755 index 0000000..0e40f5a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3060-1.8.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3060-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT3060-1.8.sub +SYMATTR Value LT3060-1.8 +SYMATTR Description 45Vin, µPower, Low Noise, 100mA Low Dropout, Linear Regulator +PIN 128 112 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3060-2.5.asy b/spice/copy/sym/PowerProducts/LT3060-2.5.asy new file mode 100755 index 0000000..91119ec --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3060-2.5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3060-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3060-2.5.sub +SYMATTR Value LT3060-2.5 +SYMATTR Description 45Vin, µPower, Low Noise, 100mA Low Dropout, Linear Regulator +PIN 128 112 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3060-3.3.asy b/spice/copy/sym/PowerProducts/LT3060-3.3.asy new file mode 100755 index 0000000..9a45910 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3060-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3060-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3060-3.3.sub +SYMATTR Value LT3060-3.3 +SYMATTR Description 45Vin, µPower, Low Noise, 100mA Low Dropout, Linear Regulator +PIN 128 112 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3060-3.asy b/spice/copy/sym/PowerProducts/LT3060-3.asy new file mode 100755 index 0000000..2a13231 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3060-3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3060-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3060-3.sub +SYMATTR Value LT3060-3 +SYMATTR Description 45Vin, µPower, Low Noise, 100mA Low Dropout, Linear Regulator +PIN 128 112 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3060-5.asy b/spice/copy/sym/PowerProducts/LT3060-5.asy new file mode 100755 index 0000000..8bd216c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3060-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3060-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3060-5.sub +SYMATTR Value LT3060-5 +SYMATTR Description 45Vin, µPower, Low Noise, 100mA Low Dropout, Linear Regulator +PIN 128 112 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3060.asy b/spice/copy/sym/PowerProducts/LT3060.asy new file mode 100755 index 0000000..e907ad3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3060.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3060 +SYMATTR Prefix X +SYMATTR SpiceModel LT3060.sub +SYMATTR Value LT3060 +SYMATTR Description 45Vin, µPower, Low Noise, 100mA Low Dropout, Linear Regulator +PIN 128 112 RIGHT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3061.asy b/spice/copy/sym/PowerProducts/LT3061.asy new file mode 100755 index 0000000..4c07b23 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3061.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3061 +SYMATTR Prefix X +SYMATTR SpiceModel LT3061.sub +SYMATTR Value LT3061 +SYMATTR Description 45V Vin, µPower, Low Noise, 100mA LDO with Output Discharge +PIN 128 112 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3062.asy b/spice/copy/sym/PowerProducts/LT3062.asy new file mode 100755 index 0000000..37355d9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3062.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3062 +SYMATTR Prefix X +SYMATTR SpiceModel LT3062.sub +SYMATTR Value LT3062 +SYMATTR Description 45V Vin, µPower, Low Noise, 200mA LDO +PIN 128 112 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3063.asy b/spice/copy/sym/PowerProducts/LT3063.asy new file mode 100755 index 0000000..800e6a6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3063.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 160 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 123 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value2 LT3063 +SYMATTR Prefix X +SYMATTR SpiceModel LT3063.lib +SYMATTR Value LT3063 +SYMATTR Description 45V Vin, µPower, Low Noise, 200mA LDO with Output Discharge +PIN 128 112 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 2 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3065.asy b/spice/copy/sym/PowerProducts/LT3065.asy new file mode 100755 index 0000000..b643b72 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3065.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 208 -128 -208 +TEXT 0 0 Center 2 LT +WINDOW 123 0 80 Center 2 +WINDOW 0 0 -80 Center 2 +SYMATTR Value2 LT3065 +SYMATTR Prefix X +SYMATTR SpiceModel LT3065.sub +SYMATTR Value LT3065 +SYMATTR Description 45V Vin, 500mA Low Noise, Linear Regulator with Programmable Current Limit and Power Good +PIN -128 -144 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -128 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -128 48 LEFT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 4 +PIN 128 48 RIGHT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 5 +PIN -128 144 LEFT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 6 +PIN 128 144 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 -48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 8 +PIN 128 -144 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3066.asy b/spice/copy/sym/PowerProducts/LT3066.asy new file mode 100755 index 0000000..98a352f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3066.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 208 -128 -208 +TEXT 0 0 Center 2 LT +WINDOW 123 0 80 Center 2 +WINDOW 0 0 -80 Center 2 +SYMATTR Value2 LT3066 +SYMATTR Prefix X +SYMATTR SpiceModel LT3066.sub +SYMATTR Value LT3066 +SYMATTR Description 45V Vin, 500mA Low Noise, Linear Regulator with Programmable Current Limit and Active Output Discharge +PIN 0 -208 TOP 8 +PINATTR PinName INFILT +PINATTR SpiceOrder 1 +PIN -128 -144 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -128 48 LEFT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 5 +PIN 128 48 RIGHT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 6 +PIN -128 144 LEFT 8 +PINATTR PinName Ref/Byp +PINATTR SpiceOrder 7 +PIN 128 -48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 9 +PIN 128 -144 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 11 +PIN 128 144 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3070-1.asy b/spice/copy/sym/PowerProducts/LT3070-1.asy new file mode 100755 index 0000000..e0a6e19 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3070-1.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 160 336 -160 -320 +TEXT 0 9 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Prefix X +SYMATTR Value LT3070-1 +SYMATTR ModelFile LT3070-1.sub +SYMATTR Description 5A, Low Noise, Programmable Output 85mV Dropout Linear Regulator +SYMATTR Value2 LT3070-1 +PIN 0 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -160 -48 LEFT 8 +PINATTR PinName V00 +PINATTR SpiceOrder 2 +PIN -160 64 LEFT 8 +PINATTR PinName V01 +PINATTR SpiceOrder 3 +PIN -160 176 LEFT 8 +PINATTR PinName V02 +PINATTR SpiceOrder 4 +PIN -160 -272 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 5 +PIN 160 288 RIGHT 8 +PINATTR PinName Ref/BYP +PINATTR SpiceOrder 6 +PIN 160 176 RIGHT 8 +PINATTR PinName MargTol +PINATTR SpiceOrder 7 +PIN 160 64 RIGHT 8 +PINATTR PinName MargSel +PINATTR SpiceOrder 8 +PIN 0 -320 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 9 +PIN 160 -160 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 160 -48 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 11 +PIN -160 -160 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 12 +PIN -160 288 LEFT 8 +PINATTR PinName VIOC +PINATTR SpiceOrder 13 +PIN 160 -272 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT3070.asy b/spice/copy/sym/PowerProducts/LT3070.asy new file mode 100755 index 0000000..8bc247f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3070.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3070 +SYMATTR Prefix X +SYMATTR SpiceModel LT3070.sub +SYMATTR Value2 LT3070 +SYMATTR Description 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName VO0 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName VO1 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName VO2 +PINATTR SpiceOrder 4 +PIN -144 -160 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 5 +PIN 144 160 RIGHT 8 +PINATTR PinName Ref/BYP +PINATTR SpiceOrder 6 +PIN 144 96 RIGHT 8 +PINATTR PinName MargTol +PINATTR SpiceOrder 7 +PIN 144 32 RIGHT 8 +PINATTR PinName MargSel +PINATTR SpiceOrder 8 +PIN 0 -208 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 9 +PIN 144 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 11 +PIN -144 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 12 +PIN -144 160 LEFT 8 +PINATTR PinName VIOC +PINATTR SpiceOrder 13 +PIN 144 -160 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT3071.asy b/spice/copy/sym/PowerProducts/LT3071.asy new file mode 100755 index 0000000..dbafbf6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3071.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3071 +SYMATTR Prefix X +SYMATTR SpiceModel LT3071.sub +SYMATTR Value2 LT3071 +SYMATTR Description 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName VO0 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName VO1 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName VO2 +PINATTR SpiceOrder 4 +PIN -144 -160 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 5 +PIN 144 160 RIGHT 8 +PINATTR PinName REF/BYP +PINATTR SpiceOrder 6 +PIN 144 96 RIGHT 8 +PINATTR PinName MargA +PINATTR SpiceOrder 7 +PIN 144 32 RIGHT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 8 +PIN 0 -208 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 9 +PIN 144 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 11 +PIN -144 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 12 +PIN -144 160 LEFT 8 +PINATTR PinName VIOC +PINATTR SpiceOrder 13 +PIN 144 -160 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT3072.asy b/spice/copy/sym/PowerProducts/LT3072.asy new file mode 100755 index 0000000..d69d5e5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3072.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -416 176 416 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3072 +SYMATTR Prefix X +SYMATTR Description Dual, Low Noise, 2.5A Programmable Output, 80mV Low Dropout Linear Regulator +SYMATTR SpiceLine TA=25 Rth=42 +SYMATTR ModelFile LT3072.sub +PIN 0 416 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -176 -224 LEFT 8 +PINATTR PinName VO1B0 +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName VO1B1 +PINATTR SpiceOrder 3 +PIN -176 -96 LEFT 8 +PINATTR PinName VO1B2 +PINATTR SpiceOrder 4 +PIN 64 -416 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 5 +PIN 176 -32 RIGHT 8 +PINATTR PinName Ref/BYP1 +PINATTR SpiceOrder 6 +PIN 176 -96 RIGHT 8 +PINATTR PinName Imon/lim1 +PINATTR SpiceOrder 7 +PIN 176 -160 RIGHT 8 +PINATTR PinName Marga1 +PINATTR SpiceOrder 8 +PIN -176 -352 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 9 +PIN 176 -288 RIGHT 8 +PINATTR PinName Sense1 +PINATTR SpiceOrder 10 +PIN 176 -224 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 11 +PIN -176 -288 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 12 +PIN -176 -32 LEFT 8 +PINATTR PinName VIOC1 +PINATTR SpiceOrder 13 +PIN 176 -352 RIGHT 8 +PINATTR PinName PWRGD1 +PINATTR SpiceOrder 14 +PIN -64 -416 TOP 8 +PINATTR PinName Temp +PINATTR SpiceOrder 15 +PIN -176 176 LEFT 8 +PINATTR PinName VO2B0 +PINATTR SpiceOrder 16 +PIN -176 240 LEFT 8 +PINATTR PinName VO2B1 +PINATTR SpiceOrder 17 +PIN -176 304 LEFT 8 +PINATTR PinName VO2B2 +PINATTR SpiceOrder 18 +PIN -176 368 LEFT 8 +PINATTR PinName VIOC2 +PINATTR SpiceOrder 19 +PIN 176 368 RIGHT 8 +PINATTR PinName Ref/BYP2 +PINATTR SpiceOrder 20 +PIN 176 240 RIGHT 8 +PINATTR PinName Marga2 +PINATTR SpiceOrder 21 +PIN -176 48 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 22 +PIN 176 112 RIGHT 8 +PINATTR PinName Sense2 +PINATTR SpiceOrder 23 +PIN 176 176 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 24 +PIN -176 112 LEFT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 25 +PIN 176 304 RIGHT 8 +PINATTR PinName Imon/lim2 +PINATTR SpiceOrder 26 +PIN 176 48 RIGHT 8 +PINATTR PinName PWRGD2 +PINATTR SpiceOrder 27 diff --git a/spice/copy/sym/PowerProducts/LT3080-1.asy b/spice/copy/sym/PowerProducts/LT3080-1.asy new file mode 100755 index 0000000..636486c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3080-1.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3080-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3080-1.sub +SYMATTR Value2 LT3080-1 +SYMATTR Description Parallelable 1.1A Adjustable Single Resistor Low Dropout Regulator +PIN 0 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 0 LEFT 8 +PINATTR PinName Vcntrl +PINATTR SpiceOrder 4 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3080.asy b/spice/copy/sym/PowerProducts/LT3080.asy new file mode 100755 index 0000000..84649cd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3080.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3080 +SYMATTR Prefix X +SYMATTR SpiceModel LT3080.sub +SYMATTR Value2 LT3080 +SYMATTR Description Adjustable 1.1A Single Resistor Low Dropout Regulator +PIN 0 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 0 LEFT 8 +PINATTR PinName Vcntrl +PINATTR SpiceOrder 4 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3081.asy b/spice/copy/sym/PowerProducts/LT3081.asy new file mode 100755 index 0000000..af16423 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3081.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3081 +SYMATTR Prefix X +SYMATTR SpiceModel LT3081.sub +SYMATTR Value2 LT3081 +SYMATTR Description 1.5A Single Resistor Rugged Linear Regulator with Monitor\nInternal current limit is modeled based on TO-220 pakage +PIN 128 48 RIGHT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN -128 48 LEFT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN -128 -48 LEFT 8 +PINATTR PinName Temp +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3082.asy b/spice/copy/sym/PowerProducts/LT3082.asy new file mode 100755 index 0000000..2cfb621 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3082.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3082 +SYMATTR Prefix X +SYMATTR SpiceModel LT3082.sub +SYMATTR Value2 LT3082 +SYMATTR Description 200mA Single Resistor Low Dropout Linear Regulator +PIN -64 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN 80 112 BOTTOM 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3083.asy b/spice/copy/sym/PowerProducts/LT3083.asy new file mode 100755 index 0000000..994ea38 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3083.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3083 +SYMATTR Prefix X +SYMATTR SpiceModel LT3083.sub +SYMATTR Value2 LT3083 +SYMATTR Description Adjustable 3A Single Resistor Low Dropout Regulator +PIN 0 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 0 LEFT 8 +PINATTR PinName Vcntrl +PINATTR SpiceOrder 4 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3085.asy b/spice/copy/sym/PowerProducts/LT3085.asy new file mode 100755 index 0000000..8fdc841 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3085.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3085 +SYMATTR Prefix X +SYMATTR SpiceModel LT3085.sub +SYMATTR Value2 LT3085 +SYMATTR Description Adjustable 500mA Single Resistor Low Dropout Regulator +PIN 0 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 0 LEFT 8 +PINATTR PinName Vcntrl +PINATTR SpiceOrder 4 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3086.asy b/spice/copy/sym/PowerProducts/LT3086.asy new file mode 100755 index 0000000..1496754 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3086.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -288 160 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +WINDOW 39 0 160 Center 2 +WINDOW 40 1 192 Center 2 +SYMATTR Value LT3086 +SYMATTR SpiceLine Rpkg=14 Tpkg=10 +SYMATTR SpiceLine2 Rsink=7 Tsink=250 +SYMATTR Prefix X +SYMATTR Description 40V, 2.1A Low Dropout Adjustable Linear Regulator with Monitoring and Cable Drop Compensation\n\nDefault thermal parameters are based on FE package on a moderate size board with thermal vias to internal planes, giving an overall thermal resistance of 21°C/W +SYMATTR ModelFile LT3086.sub +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -160 112 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName CDC +PINATTR SpiceOrder 4 +PIN 160 112 RIGHT 8 +PINATTR PinName Rpwrgd +PINATTR SpiceOrder 5 +PIN 160 -112 RIGHT 8 +PINATTR PinName SET +PINATTR SpiceOrder 6 +PIN 160 -224 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 10 +PIN -160 -224 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 12 +PIN -160 224 LEFT 8 +PINATTR PinName Temp +PINATTR SpiceOrder 13 +PIN -160 -112 LEFT 8 +PINATTR PinName Track +PINATTR SpiceOrder 14 +PIN 160 224 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3088.asy b/spice/copy/sym/PowerProducts/LT3088.asy new file mode 100755 index 0000000..d69c2e0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3088.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3088 +SYMATTR Prefix X +SYMATTR SpiceModel LT3088.sub +SYMATTR Value2 LT3088 +SYMATTR Description 800mA Single Resistor Rugged Linear Regulator +PIN -64 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN 80 112 BOTTOM 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3089.asy b/spice/copy/sym/PowerProducts/LT3089.asy new file mode 100755 index 0000000..2e43764 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3089.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3089 +SYMATTR Prefix X +SYMATTR SpiceModel LT3089.sub +SYMATTR Value2 LT3089 +SYMATTR Description 800mA Single Resistor Rugged Linear Regulator with Monitors +PIN 128 48 RIGHT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN -128 48 LEFT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN -128 -48 LEFT 8 +PINATTR PinName Temp +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3090.asy b/spice/copy/sym/PowerProducts/LT3090.asy new file mode 100755 index 0000000..72026e8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3090.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -39 Center 2 +WINDOW 3 0 41 Center 2 +SYMATTR Value LT3090 +SYMATTR Prefix X +SYMATTR SpiceModel LT3090.sub +SYMATTR Value2 LT3090 +SYMATTR Description -36V, 600mA Negative Linear Regulator with Programmable Current Limit +PIN -64 -128 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -144 64 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName Imonp +PINATTR SpiceOrder 4 +PIN 64 -128 TOP 8 +PINATTR PinName Imonn +PINATTR SpiceOrder 5 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3091.asy b/spice/copy/sym/PowerProducts/LT3091.asy new file mode 100755 index 0000000..f85f00b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3091.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -39 Center 2 +WINDOW 3 0 41 Center 2 +SYMATTR Value LT3091 +SYMATTR Prefix X +SYMATTR SpiceModel LT3091.sub +SYMATTR Value2 LT3091 +SYMATTR Description -36V, 1.5A Negative Linear Regulator with Programmable Current Limit +PIN -64 -128 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -144 64 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName Imonp +PINATTR SpiceOrder 4 +PIN 64 -128 TOP 8 +PINATTR PinName Imonn +PINATTR SpiceOrder 5 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 7 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3092.asy b/spice/copy/sym/PowerProducts/LT3092.asy new file mode 100755 index 0000000..4a080c3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3092.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3092 +SYMATTR Prefix X +SYMATTR SpiceModel LT3092.sub +SYMATTR Value2 LT3092 +SYMATTR Description 200mA Two-Terminal Programmable Current Source +PIN -64 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN 80 112 BOTTOM 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3093.asy b/spice/copy/sym/PowerProducts/LT3093.asy new file mode 100755 index 0000000..0ff55ec --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3093.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +LINE Normal 80 56 80 8 +LINE Normal 96 8 80 24 +LINE Normal 86 50 96 56 +LINE Normal 90 46 86 50 +LINE Normal 96 56 90 46 +LINE Normal 64 32 80 32 +LINE Normal -32 -33 64 32 +LINE Normal -32 97 -32 -33 +LINE Normal 64 32 -32 97 +LINE Normal 64 32 64 32 +LINE Normal -48 -48 110 -48 +LINE Normal -48 0 -48 -48 +LINE Normal -32 0 -48 0 +LINE Normal 96 0 96 8 +LINE Normal 120 0 96 0 +LINE Normal -80 64 -32 64 +LINE Normal 96 176 96 56 +LINE Normal -138 176 96 176 +LINE Normal -80 176 -80 148 +LINE Normal -22 64 -28 64 +LINE Normal -22 0 -28 0 +LINE Normal -25 -3 -25 3 +LINE Normal -80 92 -80 -77 +LINE Normal 88 48 80 40 +RECTANGLE Normal -176 -112 176 224 +CIRCLE Normal -64 124 -96 92 +CIRCLE Normal -64 148 -96 116 +CIRCLE Normal -79 65 -81 63 +CIRCLE Normal -78 66 -82 62 +CIRCLE Normal -77 67 -83 61 +CIRCLE Normal -79 177 -81 175 +CIRCLE Normal -78 178 -82 174 +CIRCLE Normal -77 179 -83 173 +TEXT 3 32 Center 2 LT +TEXT -64 120 Left 2 100µA +WINDOW 0 0 -112 Bottom 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LT3093 +SYMATTR Prefix X +SYMATTR SpiceModel LT3093.sub +SYMATTR Description -20V, 200mA Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator +SYMATTR Value2 LT3093 +PIN -176 176 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 1 +PIN -176 48 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN -176 -16 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN 176 128 RIGHT 8 +PINATTR PinName PGFB +PINATTR SpiceOrder 5 +PIN 96 -112 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 6 +PIN -176 112 LEFT 8 +PINATTR PinName Vioc +PINATTR SpiceOrder 7 +PIN -80 -112 TOP 8 +PINATTR PinName Set +PINATTR SpiceOrder 8 +PIN -176 -80 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 176 -48 RIGHT 8 +PINATTR PinName Outs +PINATTR SpiceOrder 10 +PIN 176 0 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3094.asy b/spice/copy/sym/PowerProducts/LT3094.asy new file mode 100755 index 0000000..b471516 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3094.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +LINE Normal 80 56 80 8 +LINE Normal 96 8 80 24 +LINE Normal 86 50 96 56 +LINE Normal 90 46 86 50 +LINE Normal 96 56 90 46 +LINE Normal 64 32 80 32 +LINE Normal -32 -16 64 32 +LINE Normal -32 80 -32 -16 +LINE Normal 64 32 -32 80 +LINE Normal 64 32 64 32 +LINE Normal -48 -48 110 -48 +LINE Normal -48 0 -48 -48 +LINE Normal -32 0 -48 0 +LINE Normal 96 0 96 8 +LINE Normal 120 0 96 0 +LINE Normal -80 64 -32 64 +LINE Normal 96 176 96 56 +LINE Normal -138 176 96 176 +LINE Normal -80 176 -80 148 +LINE Normal -22 64 -28 64 +LINE Normal -22 0 -28 0 +LINE Normal -25 -3 -25 3 +LINE Normal -80 92 -80 -77 +LINE Normal 88 48 80 40 +RECTANGLE Normal -176 -112 176 224 +CIRCLE Normal -64 124 -96 92 +CIRCLE Normal -64 148 -96 116 +CIRCLE Normal -79 65 -81 63 +CIRCLE Normal -78 66 -82 62 +CIRCLE Normal -77 67 -83 61 +CIRCLE Normal -79 177 -81 175 +CIRCLE Normal -78 178 -82 174 +CIRCLE Normal -77 179 -83 173 +TEXT 4 36 Center 2 LT +TEXT -64 120 Left 2 100µA +WINDOW 0 0 -112 Bottom 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LT3094 +SYMATTR Prefix X +SYMATTR SpiceModel LT3094.sub +SYMATTR Description -20V, 500mA Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator +SYMATTR Value2 LT3094 +PIN -176 176 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 1 +PIN -176 48 LEFT 8 +PINATTR PinName En +PINATTR SpiceOrder 3 +PIN -176 -16 LEFT 8 +PINATTR PinName Pg +PINATTR SpiceOrder 4 +PIN 176 128 RIGHT 8 +PINATTR PinName Pgfb +PINATTR SpiceOrder 5 +PIN 96 -112 TOP 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 6 +PIN -176 112 LEFT 8 +PINATTR PinName Vioc +PINATTR SpiceOrder 7 +PIN -80 -112 TOP 8 +PINATTR PinName Set +PINATTR SpiceOrder 8 +PIN -176 -80 LEFT 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 9 +PIN 176 -48 RIGHT 8 +PINATTR PinName Outs +PINATTR SpiceOrder 10 +PIN 176 0 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3095.asy b/spice/copy/sym/PowerProducts/LT3095.asy new file mode 100755 index 0000000..2e98048 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3095.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -400 224 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT3095 +SYMATTR Prefix X +SYMATTR SpiceModel LT3095.sub +SYMATTR Value2 LT3095 +SYMATTR Description Dual-channel Low Noise Bais Generator +PIN -224 336 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -224 -144 LEFT 8 +PINATTR PinName BSTOUT1 +PINATTR SpiceOrder 2 +PIN -224 240 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 4 +PIN -224 -48 LEFT 8 +PINATTR PinName LDOIN1 +PINATTR SpiceOrder 6 +PIN -224 48 LEFT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 8 +PIN -224 144 LEFT 8 +PINATTR PinName SET1 +PINATTR SpiceOrder 9 +PIN -224 -336 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 10 +PIN 224 -336 RIGHT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 11 +PIN 224 144 RIGHT 8 +PINATTR PinName SET2 +PINATTR SpiceOrder 12 +PIN 224 48 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 13 +PIN 224 -48 RIGHT 8 +PINATTR PinName LDOIN2 +PINATTR SpiceOrder 15 +PIN 224 240 RIGHT 8 +PINATTR PinName RT +PINATTR SpiceOrder 17 +PIN 224 336 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 18 +PIN 224 -144 RIGHT 8 +PINATTR PinName BSTOUT2 +PINATTR SpiceOrder 19 +PIN 224 -240 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 21 +PIN 0 -400 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 22 +PIN -224 -240 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LT3150.asy b/spice/copy/sym/PowerProducts/LT3150.asy new file mode 100755 index 0000000..14d11f8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3150.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 224 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3150 +SYMATTR Prefix X +SYMATTR SpiceModel LT3150.sub +SYMATTR Value2 LT3150 +SYMATTR Description Fast Transient Response, Low Input Voltage, Very Low Dropout Linear Regulator +PIN -160 -192 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -160 -128 LEFT 8 +PINATTR PinName SWGND +PINATTR SpiceOrder 2 +PIN -160 -64 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 4 +PIN -160 64 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 5 +PIN -160 128 LEFT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 6 +PIN -160 192 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 8 +PIN 160 192 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 9 +PIN 160 128 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 11 +PIN 160 64 RIGHT 8 +PINATTR PinName Ineg +PINATTR SpiceOrder 12 +PIN 160 0 RIGHT 8 +PINATTR PinName Ipos +PINATTR SpiceOrder 13 +PIN 160 -64 RIGHT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 14 +PIN 160 -128 RIGHT 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 15 +PIN 160 -192 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3154-1.asy b/spice/copy/sym/PowerProducts/LT3154-1.asy new file mode 100755 index 0000000..0a99d34 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3154-1.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 224 -160 -224 +TEXT 0 1 Center 2 LT +WINDOW 3 1 71 Center 2 +WINDOW 0 2 -64 Center 2 +SYMATTR Value LT3154-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3154-1.sub +SYMATTR Value2 LT3154-1 +SYMATTR Description 5A Low Noise, High Performance Buck-Boost DC/DC Converter, Selectable output 3.3V or 5V +PIN 64 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 64 -224 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 160 -80 RIGHT 8 +PINATTR PinName PVout +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -160 80 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN 160 -160 RIGHT 8 +PINATTR PinName _PGD +PINATTR SpiceOrder 6 +PIN 160 80 RIGHT 8 +PINATTR PinName Vsel +PINATTR SpiceOrder 7 +PIN -64 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 160 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 9 +PIN -160 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -160 160 LEFT 8 +PINATTR PinName Mode/Sync +PINATTR SpiceOrder 11 +PIN 160 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 12 +PIN -64 -224 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 13 +PIN -160 -160 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT3154.asy b/spice/copy/sym/PowerProducts/LT3154.asy new file mode 100755 index 0000000..4392c70 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3154.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 224 -160 -224 +TEXT 0 1 Center 2 LT +WINDOW 3 1 71 Center 2 +WINDOW 0 2 -64 Center 2 +SYMATTR Value LT3154 +SYMATTR Prefix X +SYMATTR SpiceModel LT3154.sub +SYMATTR Value2 LT3154 +SYMATTR Description 5A Low Noise, High Performance Buck-Boost DC/DC Converter, Adjustable Output +PIN 64 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 64 -224 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 160 -160 RIGHT 8 +PINATTR PinName PVout +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -160 80 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN 160 160 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -64 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 80 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 9 +PIN -160 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -160 160 LEFT 8 +PINATTR PinName Mode/Sync +PINATTR SpiceOrder 11 +PIN 160 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 12 +PIN -64 -224 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 13 +PIN -160 -160 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT317A.asy b/spice/copy/sym/PowerProducts/LT317A.asy new file mode 100755 index 0000000..78c35e8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT317A.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value LT317A +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT317A +SYMATTR Description Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LT3420-1.asy b/spice/copy/sym/PowerProducts/LT3420-1.asy new file mode 100755 index 0000000..3f14b56 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3420-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT3420-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3420-1.sub +SYMATTR Value2 LT3420-1 +SYMATTR Description Photoflash Capacitor Charger with Automatic Refresh +PIN 144 80 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 1 +PIN -64 -160 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN 64 -160 TOP 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 3 +PIN -144 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 4 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName SEC +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName Done +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 9 +PIN -64 160 BOTTOM 8 +PINATTR PinName Ct +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3420.asy b/spice/copy/sym/PowerProducts/LT3420.asy new file mode 100755 index 0000000..7dfeaaa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3420.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT3420 +SYMATTR Prefix X +SYMATTR SpiceModel LT3420.sub +SYMATTR Value2 LT3420 +SYMATTR Description Photoflash Capacitor Charger with Automatic Refresh +PIN 144 80 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 1 +PIN -64 -160 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN 64 -160 TOP 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 3 +PIN -144 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 4 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName SEC +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName Done +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 9 +PIN -64 160 BOTTOM 8 +PINATTR PinName Ct +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3430-1.asy b/spice/copy/sym/PowerProducts/LT3430-1.asy new file mode 100755 index 0000000..3ede975 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3430-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT3430-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3430-1.sub +SYMATTR Value2 LT3430-1 +SYMATTR Description High Voltage, 3A, 100KHz Step-Down Switching Regulator +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3430.asy b/spice/copy/sym/PowerProducts/LT3430.asy new file mode 100755 index 0000000..9e6d517 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3430.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT3430 +SYMATTR Prefix X +SYMATTR SpiceModel LT3430.sub +SYMATTR Value2 LT3430 +SYMATTR Description High Voltage, 3A, 200KHz Step-Down Switching Regulator +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3431.asy b/spice/copy/sym/PowerProducts/LT3431.asy new file mode 100755 index 0000000..15b0dff --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3431.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3431 +SYMATTR Prefix X +SYMATTR SpiceModel LT3431.sub +SYMATTR Value2 LT3431 +SYMATTR Description High Voltage, 3A, 500KHz Step-Down Switching Regulator +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 80 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3433.asy b/spice/copy/sym/PowerProducts/LT3433.asy new file mode 100755 index 0000000..718b7d6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3433.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -256 144 240 +TEXT 0 -26 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 54 Center 2 +SYMATTR Value LT3433 +SYMATTR Prefix X +SYMATTR SpiceModel LT3433.sub +SYMATTR Value2 LT3433 +SYMATTR Description High Voltage Step-Up/Step-Down DC/DC Converter +PIN -64 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 1 +PIN 144 -224 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 144 -144 RIGHT 8 +PINATTR PinName SW_H +PINATTR SpiceOrder 3 +PIN -144 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName Burst_EN +PINATTR SpiceOrder 5 +PIN -144 16 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -144 176 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -144 -64 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 10 +PIN -144 -144 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN 144 176 RIGHT 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 12 +PIN 144 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 13 +PIN 64 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 14 +PIN 144 16 RIGHT 8 +PINATTR PinName SW_L +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3434.asy b/spice/copy/sym/PowerProducts/LT3434.asy new file mode 100755 index 0000000..7b7a46c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3434.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 224 +TEXT 0 -39 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT3434 +SYMATTR Prefix X +SYMATTR SpiceModel LT3434.sub +SYMATTR Value2 LT3434 +SYMATTR Description High Voltage 3A, 200KHz Step-Down Switching Regulator with 100µA Quiescent Current +PIN 160 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -64 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 64 -224 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN -160 160 LEFT 8 +PINATTR PinName CT +PINATTR SpiceOrder 7 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName Css +PINATTR SpiceOrder 9 +PIN 160 -80 RIGHT 8 +PINATTR PinName VBIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 160 160 RIGHT 8 +PINATTR PinName PGFB +PINATTR SpiceOrder 13 +PIN -160 -160 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 +PIN -160 -80 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3435.asy b/spice/copy/sym/PowerProducts/LT3435.asy new file mode 100755 index 0000000..095e758 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3435.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 224 +TEXT 0 -39 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT3435 +SYMATTR Prefix X +SYMATTR SpiceModel LT3435.sub +SYMATTR Value2 LT3435 +SYMATTR Description High Voltage 3A, 500KHz Step-Down Switching Regulator with 100µA Quiescent Current +PIN 160 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -64 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 64 -224 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN -160 160 LEFT 8 +PINATTR PinName CT +PINATTR SpiceOrder 7 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName Css +PINATTR SpiceOrder 9 +PIN 160 -80 RIGHT 8 +PINATTR PinName VBIAS +PINATTR SpiceOrder 10 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 160 160 RIGHT 8 +PINATTR PinName PGFB +PINATTR SpiceOrder 13 +PIN -160 -160 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 +PIN -160 -80 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3436.asy b/spice/copy/sym/PowerProducts/LT3436.asy new file mode 100755 index 0000000..6e48dcc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3436.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3436 +SYMATTR Prefix X +SYMATTR SpiceModel LT3436.sub +SYMATTR Value2 LT3436 +SYMATTR Description 3A, 800KHz Switching Regulator +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 64 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT3437.asy b/spice/copy/sym/PowerProducts/LT3437.asy new file mode 100755 index 0000000..651c549 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3437.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 144 +TEXT 0 -39 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LT3437 +SYMATTR Prefix X +SYMATTR SpiceModel LT3437.sub +SYMATTR Value2 LT3437 +SYMATTR Description High Voltage 500mA, 200KHz Step-Down Switching Regulator with 75µA Quiescent Current\n\nNote: Sync pin is not modeled. +PIN 160 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -64 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 64 -224 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName Css +PINATTR SpiceOrder 5 +PIN 160 -80 RIGHT 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -160 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3439.asy b/spice/copy/sym/PowerProducts/LT3439.asy new file mode 100755 index 0000000..ed606d1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3439.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3439 +SYMATTR Prefix X +SYMATTR SpiceModel LT3439.sub +SYMATTR Value2 LT3439 +SYMATTR Description Ultralow Noise 1A Isolated DC/DC Transformer Driver +PIN 64 160 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 144 -80 RIGHT 8 +PINATTR PinName COL A +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName Rsl +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -144 80 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 7 +PIN -64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 144 0 RIGHT 8 +PINATTR PinName COL B +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT3460-1.asy b/spice/copy/sym/PowerProducts/LT3460-1.asy new file mode 100755 index 0000000..e9ab714 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3460-1.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3460-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3460-1.sub +SYMATTR Value2 LT3460-1 +SYMATTR Description 650KHz Step-Up DC/DC Converter in SC70 and DFN +PIN 80 -96 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3460.asy b/spice/copy/sym/PowerProducts/LT3460.asy new file mode 100755 index 0000000..ca52674 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3460.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -96 144 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3460 +SYMATTR Prefix X +SYMATTR SpiceModel LT3460.sub +SYMATTR Value2 LT3460 +SYMATTR Description 1.3MHz Step-Up Converter in SC70 and ThinSOT +PIN 80 -96 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -80 -96 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3461.asy b/spice/copy/sym/PowerProducts/LT3461.asy new file mode 100755 index 0000000..cce3a04 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3461.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3461 +SYMATTR Prefix X +SYMATTR SpiceModel LT3461.sub +SYMATTR Value2 LT3461 +SYMATTR Description 1.3MHz Step-Up Converter in ThinSOT +PIN 0 -128 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3461A.asy b/spice/copy/sym/PowerProducts/LT3461A.asy new file mode 100755 index 0000000..4f4f0f0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3461A.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3461A +SYMATTR Prefix X +SYMATTR SpiceModel LT3461A.sub +SYMATTR Value2 LT3461A +SYMATTR Description 3MHz Step-Up DC/DC Converter in ThinSOT +PIN 0 -128 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3462.asy b/spice/copy/sym/PowerProducts/LT3462.asy new file mode 100755 index 0000000..05e83ed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3462.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -96 112 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 43 Center 2 +SYMATTR Value LT3462 +SYMATTR Prefix X +SYMATTR SpiceModel LT3462.sub +SYMATTR Value2 LT3462 +SYMATTR Description 1.2MHz DC/DC Converter with Integrated Schottky in ThinSOT +PIN -48 -96 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 112 -32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName SDREF +PINATTR SpiceOrder 4 +PIN 48 -96 TOP 8 +PINATTR PinName D +PINATTR SpiceOrder 5 +PIN -112 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3462A.asy b/spice/copy/sym/PowerProducts/LT3462A.asy new file mode 100755 index 0000000..be60315 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3462A.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -96 112 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 43 Center 2 +SYMATTR Value LT3462A +SYMATTR Prefix X +SYMATTR SpiceModel LT3462A.sub +SYMATTR Value2 LT3462A +SYMATTR Description 2.7MHz DC/DC Converter with Integrated Schottky in ThinSOT +PIN -48 -96 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 112 -32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName SDREF +PINATTR SpiceOrder 4 +PIN 48 -96 TOP 8 +PINATTR PinName D +PINATTR SpiceOrder 5 +PIN -112 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3463.asy b/spice/copy/sym/PowerProducts/LT3463.asy new file mode 100755 index 0000000..50a7823 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3463.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -47 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3463 +SYMATTR Prefix X +SYMATTR SpiceModel LT3463.sub +SYMATTR Value2 LT3463 +SYMATTR Description Dual µPower DC/DC Converter with Schottky Diodes +PIN 112 -144 TOP 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 1 +PIN 0 -144 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 112 144 BOTTOM 8 +PINATTR PinName D2 +PINATTR SpiceOrder 5 +PIN 160 80 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 7 +PIN -160 64 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 8 +PIN -160 -64 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 9 +PIN 160 -80 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 10 +PIN -112 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3463A.asy b/spice/copy/sym/PowerProducts/LT3463A.asy new file mode 100755 index 0000000..d8b76c7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3463A.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -47 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3463A +SYMATTR Prefix X +SYMATTR SpiceModel LT3463A.sub +SYMATTR Value2 LT3463A +SYMATTR Description Dual µPower DC/DC Converter with Schottky Diodes +PIN 112 -144 TOP 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 1 +PIN 0 -144 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN 112 144 BOTTOM 8 +PINATTR PinName D2 +PINATTR SpiceOrder 5 +PIN 160 80 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 7 +PIN -160 64 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 8 +PIN -160 -64 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 9 +PIN 160 -80 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 10 +PIN -112 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3464.asy b/spice/copy/sym/PowerProducts/LT3464.asy new file mode 100755 index 0000000..7fc7a68 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3464.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3464 +SYMATTR Prefix X +SYMATTR SpiceModel LT3464.sub +SYMATTR Value2 LT3464 +SYMATTR Description µPower Boost Converter with Integrated Schottky and Output Disconnect in ThinSOT +PIN -144 96 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 1 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 144 -96 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 0 RIGHT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 5 +PIN 64 -160 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3465.asy b/spice/copy/sym/PowerProducts/LT3465.asy new file mode 100755 index 0000000..971c26e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3465.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -24 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3465 +SYMATTR Prefix X +SYMATTR SpiceModel LT3465.sub +SYMATTR Value2 LT3465 +SYMATTR Description White LED Step-Up Converter with Built-In Schottky in ThinSOT +PIN 80 -144 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -80 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3465A.asy b/spice/copy/sym/PowerProducts/LT3465A.asy new file mode 100755 index 0000000..08ffd43 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3465A.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -24 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3465A +SYMATTR Prefix X +SYMATTR SpiceModel LT3465A.sub +SYMATTR Value2 LT3465A +SYMATTR Description 2.4MHz White LED Step-Up Converter with Built-In Schottky in ThinSOT +PIN 80 -144 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -80 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3466-1.asy b/spice/copy/sym/PowerProducts/LT3466-1.asy new file mode 100755 index 0000000..26cb1a2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3466-1.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -24 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3466-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3466-1.sub +SYMATTR Value2 LT3466-1 +SYMATTR Description White LED Driver and Boost Converter in 3mm × 3mm DFN Package\n\nNote: Only channel 2 is modeled. For channel 1, use the LT3466 model. +PIN 80 -144 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -80 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 64 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 9 +PIN 144 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3466.asy b/spice/copy/sym/PowerProducts/LT3466.asy new file mode 100755 index 0000000..7719a9e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3466.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -24 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3466 +SYMATTR Prefix X +SYMATTR SpiceModel LT3466.sub +SYMATTR Value2 LT3466 +SYMATTR Description Dual Full Function White LED Step-Up Converter with Built-In Schottky Diodes(1 of 2 channels modeled) +PIN 80 -144 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -80 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 64 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 64 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 9 +PIN 144 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3467.asy b/spice/copy/sym/PowerProducts/LT3467.asy new file mode 100755 index 0000000..9703721 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3467.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -112 160 112 +TEXT 0 -24 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3467 +SYMATTR Value2 LT3467 +SYMATTR Prefix X +SYMATTR SpiceModel LT3467.sub +SYMATTR Description 1.1A Step-Up DC/DC Converter in ThinSOT with Integrated Soft-Start +PIN 80 -112 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -160 48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN -80 -112 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3467A.asy b/spice/copy/sym/PowerProducts/LT3467A.asy new file mode 100755 index 0000000..66959dc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3467A.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -112 160 112 +TEXT 0 -25 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3467A +SYMATTR Value2 LT3467A +SYMATTR Prefix X +SYMATTR SpiceModel LT3467A.sub +SYMATTR Description 2.1MHz, 1.1A Step-Up DC/DC Converter in ThinSOT with Integrated Soft-Start +PIN 80 -112 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -160 48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN -80 -112 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3468-1.asy b/spice/copy/sym/PowerProducts/LT3468-1.asy new file mode 100755 index 0000000..9375dab --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3468-1.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 -40 Center 2 LT +WINDOW 0 53 -112 Bottom 2 +WINDOW 3 -1 23 Center 2 +SYMATTR Value LT3468-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3468-1.sub +SYMATTR Value2 LT3468-1 +SYMATTR Description Photoflash Capacitor Charger in ThinSOT(TM) +PIN 112 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 -48 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 3 +PIN -112 48 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 4 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3468-2.asy b/spice/copy/sym/PowerProducts/LT3468-2.asy new file mode 100755 index 0000000..8e914d0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3468-2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 -40 Center 2 LT +WINDOW 0 53 -112 Bottom 2 +WINDOW 3 -1 23 Center 2 +SYMATTR Value LT3468-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3468-2.sub +SYMATTR Value2 LT3468-2 +SYMATTR Description Photoflash Capacitor Charger in ThinSOT(TM) +PIN 112 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 -48 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 3 +PIN -112 48 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 4 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3468.asy b/spice/copy/sym/PowerProducts/LT3468.asy new file mode 100755 index 0000000..b3c9a0e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3468.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 -40 Center 2 LT +WINDOW 0 53 -112 Bottom 2 +WINDOW 3 -1 23 Center 2 +SYMATTR Value LT3468 +SYMATTR Prefix X +SYMATTR SpiceModel LT3468.sub +SYMATTR Value2 LT3468 +SYMATTR Description Photoflash Capacitor Charger in ThinSOT(TM) +PIN 112 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 -48 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 3 +PIN -112 48 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 4 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT3469.asy b/spice/copy/sym/PowerProducts/LT3469.asy new file mode 100755 index 0000000..815276f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3469.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 -24 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT3469 +SYMATTR Prefix X +SYMATTR SpiceModel LT3469.sub +SYMATTR Value2 LT3469 +SYMATTR Description Piezo Microactuator Driver with Boost Regulator +PIN 128 80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 128 16 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -80 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 80 -128 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 +PIN -128 48 LEFT 8 +PINATTR PinName +IN +PINATTR SpiceOrder 7 +PIN -128 112 LEFT 8 +PINATTR PinName -IN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3470.asy b/spice/copy/sym/PowerProducts/LT3470.asy new file mode 100755 index 0000000..d79fcfc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3470.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3470 +SYMATTR Prefix X +SYMATTR SpiceModel LT3470.sub +SYMATTR Value2 LT3470 +SYMATTR Description µPower Buck Regulator with Integrated Boost and Catch Diodes +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 64 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 128 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 7 +PIN 128 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3470A.asy b/spice/copy/sym/PowerProducts/LT3470A.asy new file mode 100755 index 0000000..6a981a7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3470A.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3470A +SYMATTR Prefix X +SYMATTR SpiceModel LT3470A.sub +SYMATTR Value2 LT3470A +SYMATTR Description µPower Buck Regulator with Integrated Boost and Catch Diodes +PIN -128 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 64 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 128 0 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 7 +PIN 128 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3471.asy b/spice/copy/sym/PowerProducts/LT3471.asy new file mode 100755 index 0000000..cd41302 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3471.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 160 192 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT3471 +SYMATTR Prefix X +SYMATTR SpiceModel LT3471.sub +SYMATTR Value2 LT3471 +SYMATTR Description Dual 1.3A, 1.2MHz Boost/Inverter in 3mm x 3mm DFN +PIN 160 -128 RIGHT 8 +PINATTR PinName FB1N +PINATTR SpiceOrder 1 +PIN 160 -64 RIGHT 8 +PINATTR PinName FB1P +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN 160 128 RIGHT 8 +PINATTR PinName FB2P +PINATTR SpiceOrder 4 +PIN 160 64 RIGHT 8 +PINATTR PinName FB2N +PINATTR SpiceOrder 5 +PIN 80 192 BOTTOM 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN -176 128 LEFT 8 +PINATTR PinName _SHDN/SS2 +PINATTR SpiceOrder 7 +PIN -176 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -176 -128 LEFT 8 +PINATTR PinName _SHDN/SS1 +PINATTR SpiceOrder 9 +PIN 0 -192 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 10 +PIN -96 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3472.asy b/spice/copy/sym/PowerProducts/LT3472.asy new file mode 100755 index 0000000..0e1007f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3472.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3472 +SYMATTR Prefix X +SYMATTR SpiceModel LT3472.sub +SYMATTR Value2 LT3472 +SYMATTR Description Boost and Inverting DC/DC Converter for CCD Bias +PIN -112 -160 TOP 8 +PINATTR PinName SWP +PINATTR SpiceOrder 1 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -160 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 112 -160 TOP 8 +PINATTR PinName SWN +PINATTR SpiceOrder 4 +PIN 160 -80 RIGHT 8 +PINATTR PinName DN +PINATTR SpiceOrder 5 +PIN 160 80 RIGHT 8 +PINATTR PinName FBN +PINATTR SpiceOrder 6 +PIN 112 160 BOTTOM 8 +PINATTR PinName SSN +PINATTR SpiceOrder 7 +PIN -160 80 LEFT 8 +PINATTR PinName FBP +PINATTR SpiceOrder 8 +PIN -112 160 BOTTOM 8 +PINATTR PinName SSP +PINATTR SpiceOrder 9 +PIN -160 0 LEFT 8 +PINATTR PinName Vpos +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3473.asy b/spice/copy/sym/PowerProducts/LT3473.asy new file mode 100755 index 0000000..fb62514 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3473.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 55 Center 2 +SYMATTR Value LT3473 +SYMATTR Prefix X +SYMATTR SpiceModel LT3473.sub +SYMATTR Value2 LT3473 +SYMATTR Description µPower 1A Boost Converter with Schottky and Output Disconnect +PIN 144 16 RIGHT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 1 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -144 16 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 3 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName _Pgood +PINATTR SpiceOrder 5 +PIN -144 96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3473A.asy b/spice/copy/sym/PowerProducts/LT3473A.asy new file mode 100755 index 0000000..e3e90b5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3473A.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -224 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 86 Center 2 +SYMATTR Value LT3473A +SYMATTR Prefix X +SYMATTR SpiceModel LT3473A.sub +SYMATTR Value2 LT3473A +SYMATTR Description µPower 1A Boost Converter with Schottky and Output Disconnect +PIN 144 -32 RIGHT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 1 +PIN 144 -112 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 128 RIGHT 8 +PINATTR PinName NB1 +PINATTR SpiceOrder 3 +PIN 144 208 RIGHT 8 +PINATTR PinName NE1 +PINATTR SpiceOrder 4 +PIN -144 128 LEFT 8 +PINATTR PinName NB2 +PINATTR SpiceOrder 5 +PIN -144 208 LEFT 8 +PINATTR PinName NE2 +PINATTR SpiceOrder 6 +PIN 144 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -144 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 8 +PIN -144 -112 LEFT 8 +PINATTR PinName _Pgood +PINATTR SpiceOrder 9 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 +PIN -144 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN 144 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3474-1.asy b/spice/copy/sym/PowerProducts/LT3474-1.asy new file mode 100755 index 0000000..3eea071 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3474-1.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3474-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3474-1.sub +SYMATTR Value2 LT3474-1 +SYMATTR Description Step-Down 1A LED Driver +PIN 144 16 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 144 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 3 +PIN -64 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 64 -176 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 9 +PIN -144 -112 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 +PIN -144 -48 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 11 +PIN -144 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN -144 16 LEFT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 13 +PIN 144 80 RIGHT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT3474.asy b/spice/copy/sym/PowerProducts/LT3474.asy new file mode 100755 index 0000000..f8647c5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3474.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3474 +SYMATTR Prefix X +SYMATTR SpiceModel LT3474.sub +SYMATTR Value2 LT3474 +SYMATTR Description Step-Down 1A LED Driver +PIN 144 16 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 144 144 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 3 +PIN -64 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 144 -112 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 64 -176 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 7 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 9 +PIN -144 -112 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 +PIN -144 -48 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 11 +PIN -144 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN -144 16 LEFT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 13 +PIN 144 80 RIGHT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT3475-1.asy b/spice/copy/sym/PowerProducts/LT3475-1.asy new file mode 100755 index 0000000..01a274a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3475-1.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -352 160 432 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 136 Center 2 +SYMATTR Value LT3475-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3475-1.sub +SYMATTR Value2 LT3475-1 +SYMATTR Description Dual Step-Down 1.5A LED Driver +PIN -160 -96 LEFT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 2 +PIN -160 -288 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 3 +PIN -160 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 4 +PIN -64 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 160 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 7 +PIN 160 -288 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName LED2 +PINATTR SpiceOrder 9 +PIN 160 -96 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 10 +PIN 160 96 RIGHT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 11 +PIN 160 384 RIGHT 8 +PINATTR PinName Vadj2 +PINATTR SpiceOrder 12 +PIN 160 192 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 13 +PIN 160 288 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 14 +PIN 0 432 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 15 +PIN 64 -352 TOP 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 16 +PIN -160 288 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 17 +PIN -160 192 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 18 +PIN -160 384 LEFT 8 +PINATTR PinName Vadj1 +PINATTR SpiceOrder 19 +PIN -160 96 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT3475.asy b/spice/copy/sym/PowerProducts/LT3475.asy new file mode 100755 index 0000000..480acb4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3475.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -352 160 432 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 136 Center 2 +SYMATTR Value LT3475 +SYMATTR Prefix X +SYMATTR SpiceModel LT3475.sub +SYMATTR Value2 LT3475 +SYMATTR Description Dual Step-Down 1.5A LED Driver +PIN -160 -96 LEFT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 2 +PIN -160 -288 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 3 +PIN -160 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 4 +PIN -64 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 160 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 7 +PIN 160 -288 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName LED2 +PINATTR SpiceOrder 9 +PIN 160 -96 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 10 +PIN 160 96 RIGHT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 11 +PIN 160 384 RIGHT 8 +PINATTR PinName Vadj2 +PINATTR SpiceOrder 12 +PIN 160 192 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 13 +PIN 160 288 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 14 +PIN 0 432 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 15 +PIN 64 -352 TOP 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 16 +PIN -160 288 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 17 +PIN -160 192 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 18 +PIN -160 384 LEFT 8 +PINATTR PinName Vadj1 +PINATTR SpiceOrder 19 +PIN -160 96 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT3476.asy b/spice/copy/sym/PowerProducts/LT3476.asy new file mode 100755 index 0000000..f916d3a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3476.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3476 +SYMATTR Prefix X +SYMATTR SpiceModel LT3476.sub +SYMATTR Value2 LT3476 +SYMATTR Description High Current Quad Output LED Driver(1 of 4 channels modeled) +PIN 144 48 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 144 128 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN -144 128 LEFT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 3 +PIN 144 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 144 -112 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 5 +PIN 64 -176 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 6 +PIN -64 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -144 48 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 8 +PIN -144 -32 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 9 +PIN -144 -112 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3477.asy b/spice/copy/sym/PowerProducts/LT3477.asy new file mode 100755 index 0000000..df76939 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3477.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -90 Center 2 +WINDOW 3 0 90 Center 2 +SYMATTR Value LT3477 +SYMATTR Prefix X +SYMATTR SpiceModel LT3477.sub +SYMATTR Value2 LT3477 +SYMATTR Description 3A, DC/DC Converter with Dual Rail-to-Rail Current Sense +PIN -176 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 176 192 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -176 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -176 128 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 6 +PIN -176 192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN 176 -128 RIGHT 8 +PINATTR PinName FBN +PINATTR SpiceOrder 8 +PIN 176 -64 RIGHT 8 +PINATTR PinName FBP +PINATTR SpiceOrder 9 +PIN 176 0 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 10 +PIN -176 0 LEFT 8 +PINATTR PinName Iadj2 +PINATTR SpiceOrder 11 +PIN -176 -64 LEFT 8 +PINATTR PinName Iadj1 +PINATTR SpiceOrder 12 +PIN 176 64 RIGHT 8 +PINATTR PinName ISP2 +PINATTR SpiceOrder 13 +PIN 176 128 RIGHT 8 +PINATTR PinName ISN2 +PINATTR SpiceOrder 14 +PIN -112 -192 TOP 8 +PINATTR PinName ISP1 +PINATTR SpiceOrder 15 +PIN 0 -192 TOP 8 +PINATTR PinName ISN1 +PINATTR SpiceOrder 16 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 +PIN 112 -192 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 18 diff --git a/spice/copy/sym/PowerProducts/LT3478-1.asy b/spice/copy/sym/PowerProducts/LT3478-1.asy new file mode 100755 index 0000000..59eb1cd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3478-1.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 71 Center 2 +SYMATTR Value LT3478-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3478-1.sub +SYMATTR Value2 LT3478-1 +SYMATTR Description 4.5A Boost LED Driver with True Color PWM Dimming +PIN 160 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -96 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 -208 TOP 8 +PINATTR PinName Vs +PINATTR SpiceOrder 4 +PIN 96 -208 TOP 8 +PINATTR PinName L +PINATTR SpiceOrder 5 +PIN 160 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 160 -16 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 7 +PIN -160 112 LEFT 8 +PINATTR PinName OVPSET +PINATTR SpiceOrder 8 +PIN 160 112 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 -80 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 10 +PIN -160 -144 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN -160 -16 LEFT 8 +PINATTR PinName Ctrl1 +PINATTR SpiceOrder 12 +PIN -160 48 LEFT 8 +PINATTR PinName Ctrl2 +PINATTR SpiceOrder 13 +PIN -160 176 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 +PIN 160 48 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN 160 176 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 16 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3478.asy b/spice/copy/sym/PowerProducts/LT3478.asy new file mode 100755 index 0000000..c37ef34 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3478.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 71 Center 2 +SYMATTR Value LT3478 +SYMATTR Prefix X +SYMATTR SpiceModel LT3478.sub +SYMATTR Value2 LT3478 +SYMATTR Description 4.5A Boost LED Driver with True Color PWM Dimming +PIN 160 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -96 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 -208 TOP 8 +PINATTR PinName Vs +PINATTR SpiceOrder 4 +PIN 96 -208 TOP 8 +PINATTR PinName L +PINATTR SpiceOrder 5 +PIN 160 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 160 -16 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 7 +PIN -160 112 LEFT 8 +PINATTR PinName OVPSET +PINATTR SpiceOrder 8 +PIN 160 112 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 -80 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 10 +PIN -160 -144 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN -160 -16 LEFT 8 +PINATTR PinName Ctrl1 +PINATTR SpiceOrder 12 +PIN -160 48 LEFT 8 +PINATTR PinName Ctrl2 +PINATTR SpiceOrder 13 +PIN -160 176 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 +PIN 160 48 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN 160 176 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 16 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3479.asy b/spice/copy/sym/PowerProducts/LT3479.asy new file mode 100755 index 0000000..ec5d201 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3479.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -59 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT3479 +SYMATTR Prefix X +SYMATTR SpiceModel LT3479.sub +SYMATTR Value2 LT3479 +SYMATTR Description 3A, Full Featured DC/DC Converter with Soft-Start and Inrush Current Protection +PIN 112 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 -144 TOP 8 +PINATTR PinName L +PINATTR SpiceOrder 3 +PIN -112 -144 TOP 8 +PINATTR PinName Vs +PINATTR SpiceOrder 4 +PIN -160 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -160 -16 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 160 -16 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 +PIN 160 48 RIGHT 8 +PINATTR PinName FBP +PINATTR SpiceOrder 9 +PIN 160 -80 RIGHT 8 +PINATTR PinName FBN +PINATTR SpiceOrder 10 +PIN 160 112 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN -160 48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3480.asy b/spice/copy/sym/PowerProducts/LT3480.asy new file mode 100755 index 0000000..6e507de --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3480.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT3480 +SYMATTR Prefix X +SYMATTR SpiceModel LT3480.sub +SYMATTR Value2 LT3480 +SYMATTR Description 38V, 2A, 2.4MHz Step-Down Switching Regulator with 70µA Quiescent Current +PIN 160 -128 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3481.asy b/spice/copy/sym/PowerProducts/LT3481.asy new file mode 100755 index 0000000..8aa2f9e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3481.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT3481 +SYMATTR Prefix X +SYMATTR SpiceModel LT3481.sub +SYMATTR Value2 LT3481 +SYMATTR Description 36V, 2A, 2.8MHz Step-Down Switching Regulator with 50µA Quiescent Current +PIN 64 -192 TOP 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -64 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 6 +PIN 160 -128 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3482.asy b/spice/copy/sym/PowerProducts/LT3482.asy new file mode 100755 index 0000000..1a0f187 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3482.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -192 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3482 +SYMATTR Prefix X +SYMATTR SpiceModel LT3482.sub +SYMATTR Value2 LT3482 +SYMATTR Description 90V Boost DC/DC Converter with APD Current Monitor +PIN 144 128 RIGHT 8 +PINATTR PinName APD +PINATTR SpiceOrder 2 +PIN 144 -128 RIGHT 8 +PINATTR PinName MONIN +PINATTR SpiceOrder 3 +PIN 144 -64 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 4 +PIN 144 0 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 5 +PIN 80 -192 TOP 8 +PINATTR PinName PUMP +PINATTR SpiceOrder 6 +PIN -80 -192 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -144 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 12 +PIN -144 64 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 13 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 14 +PIN -144 -64 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 15 +PIN -144 128 LEFT 8 +PINATTR PinName MON +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3483.asy b/spice/copy/sym/PowerProducts/LT3483.asy new file mode 100755 index 0000000..d04bc06 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3483.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -96 128 112 +TEXT 0 -24 Center 2 LT +WINDOW 0 16 -112 Left 2 +WINDOW 3 0 23 Center 2 +SYMATTR Value LT3483 +SYMATTR Prefix X +SYMATTR SpiceModel LT3483.sub +SYMATTR Value2 LT3483 +SYMATTR Description Inverting µPower DC/DC Converter with Schottky in ThinSOT Package +PIN 0 -96 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName D +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3483A.asy b/spice/copy/sym/PowerProducts/LT3483A.asy new file mode 100755 index 0000000..2823c16 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3483A.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -96 128 112 +TEXT 0 -24 Center 2 LT +WINDOW 0 16 -112 Left 2 +WINDOW 3 0 23 Center 2 +SYMATTR Value LT3483A +SYMATTR Prefix X +SYMATTR SpiceModel LT3483A.sub +SYMATTR Value2 LT3483A +SYMATTR Description Inverting µPower DC/DC Converter with Schottky in ThinSOT Package +PIN 0 -96 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName D +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3484-0.asy b/spice/copy/sym/PowerProducts/LT3484-0.asy new file mode 100755 index 0000000..8c72289 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3484-0.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 -40 Center 2 LT +WINDOW 0 2 -111 Bottom 2 +WINDOW 3 -1 23 Center 2 +SYMATTR Value LT3484-0 +SYMATTR Prefix X +SYMATTR SpiceModel LT3484-0.sub +SYMATTR Value2 LT3484-0 +SYMATTR Description Photoflash Capacitor Charger +PIN -112 -48 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 1 +PIN -112 48 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 2 +PIN -64 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 112 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 64 -112 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 6 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT3484-1.asy b/spice/copy/sym/PowerProducts/LT3484-1.asy new file mode 100755 index 0000000..ddee877 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3484-1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 -40 Center 2 LT +WINDOW 0 2 -111 Bottom 2 +WINDOW 3 -1 23 Center 2 +SYMATTR Value LT3484-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3484-1.sub +SYMATTR Value2 LT3484-1 +SYMATTR Description Photoflash Capacitor Charger +PIN -112 -48 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 1 +PIN -112 48 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 2 +PIN -64 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 112 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 64 -112 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 6 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT3484-2.asy b/spice/copy/sym/PowerProducts/LT3484-2.asy new file mode 100755 index 0000000..62f681f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3484-2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 -40 Center 2 LT +WINDOW 0 2 -111 Bottom 2 +WINDOW 3 -1 23 Center 2 +SYMATTR Value LT3484-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3484-2.sub +SYMATTR Value2 LT3484-2 +SYMATTR Description Photoflash Capacitor Charger +PIN -112 -48 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 1 +PIN -112 48 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 2 +PIN -64 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 112 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 64 -112 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 6 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT3485-0.asy b/spice/copy/sym/PowerProducts/LT3485-0.asy new file mode 100755 index 0000000..979348c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3485-0.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 44 Center 2 +SYMATTR Value LT3485-0 +SYMATTR Prefix X +SYMATTR SpiceModel LT3485-0.sub +SYMATTR Value2 LT3485-0 +SYMATTR Description Photoflash Capacitor Charger with Output Voltage Monitor and Integrated IGBT Drive -- 1.2A typ Peak Switch Current +PIN -160 0 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 1 +PIN 112 -144 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 160 80 RIGHT 8 +PINATTR PinName IBGTout +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName IBGTin +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName IBGTpwr +PINATTR SpiceOrder 8 +PIN -160 -80 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 9 +PIN 160 0 RIGHT 8 +PINATTR PinName Vmont +PINATTR SpiceOrder 10 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3485-1.asy b/spice/copy/sym/PowerProducts/LT3485-1.asy new file mode 100755 index 0000000..c5d09c5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3485-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 44 Center 2 +SYMATTR Value LT3485-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3485-1.sub +SYMATTR Value2 LT3485-1 +SYMATTR Description Photoflash Capacitor Charger with Output Voltage Monitor and Integrated IGBT Drive -- 550mA typ Peak Switch Current +PIN -160 0 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 1 +PIN 112 -144 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 160 80 RIGHT 8 +PINATTR PinName IBGTout +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName IBGTin +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName IBGTpwr +PINATTR SpiceOrder 8 +PIN -160 -80 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 9 +PIN 160 0 RIGHT 8 +PINATTR PinName Vmont +PINATTR SpiceOrder 10 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3485-2.asy b/spice/copy/sym/PowerProducts/LT3485-2.asy new file mode 100755 index 0000000..d839e50 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3485-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 44 Center 2 +SYMATTR Value LT3485-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3485-2.sub +SYMATTR Value2 LT3485-2 +SYMATTR Description Photoflash Capacitor Charger with Output Voltage Monitor and Integrated IGBT Drive -- 850mA typ Peak Switch Current +PIN -160 0 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 1 +PIN 112 -144 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 160 80 RIGHT 8 +PINATTR PinName IBGTout +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName IBGTin +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName IBGTpwr +PINATTR SpiceOrder 8 +PIN -160 -80 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 9 +PIN 160 0 RIGHT 8 +PINATTR PinName Vmont +PINATTR SpiceOrder 10 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3485-3.asy b/spice/copy/sym/PowerProducts/LT3485-3.asy new file mode 100755 index 0000000..3d8d33c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3485-3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 44 Center 2 +SYMATTR Value LT3485-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3485-3.sub +SYMATTR Value2 LT3485-3 +SYMATTR Description Photoflash Capacitor Charger with Output Voltage Monitor and Integrated IGBT Drive -- 1.7A typ peak Switch Current +PIN -160 0 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 1 +PIN 112 -144 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 160 80 RIGHT 8 +PINATTR PinName IBGTout +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName IBGTin +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName IBGTpwr +PINATTR SpiceOrder 8 +PIN -160 -80 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 9 +PIN 160 0 RIGHT 8 +PINATTR PinName Vmont +PINATTR SpiceOrder 10 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3486.asy b/spice/copy/sym/PowerProducts/LT3486.asy new file mode 100755 index 0000000..59dd830 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3486.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT3486 +SYMATTR Prefix X +SYMATTR SpiceModel LT3486.sub +SYMATTR Value2 LT3486 +SYMATTR Description Dual 1.3A White LED Step-Up Converters with Wide Dimming Range\n\nNote: Only 1 of 2 channels modeled. +PIN 64 -176 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN -64 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -112 RIGHT 8 +PINATTR PinName OVP1 +PINATTR SpiceOrder 3 +PIN 144 48 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 5 +PIN 144 128 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 6 +PIN -144 48 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 7 +PIN -144 128 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 8 +PIN -144 -112 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 13 +PIN -144 -32 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 15 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3487.asy b/spice/copy/sym/PowerProducts/LT3487.asy new file mode 100755 index 0000000..c318075 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3487.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -176 128 176 +TEXT 0 8 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT3487 +SYMATTR Prefix X +SYMATTR SpiceModel LT3487.sub +SYMATTR Value2 LT3487 +SYMATTR Description Boost and Inverting Switching Regulator for CCD Bias +PIN 128 -32 RIGHT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 1 +PIN 128 -112 RIGHT 8 +PINATTR PinName SWP +PINATTR SpiceOrder 2 +PIN -48 -176 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName SWN +PINATTR SpiceOrder 4 +PIN -128 -32 LEFT 8 +PINATTR PinName DN +PINATTR SpiceOrder 5 +PIN 48 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 48 LEFT 8 +PINATTR PinName FBN +PINATTR SpiceOrder 7 +PIN -128 128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 8 +PIN 128 48 RIGHT 8 +PINATTR PinName FBP +PINATTR SpiceOrder 9 +PIN 128 128 RIGHT 8 +PINATTR PinName Vpos +PINATTR SpiceOrder 10 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3489.asy b/spice/copy/sym/PowerProducts/LT3489.asy new file mode 100755 index 0000000..b133161 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3489.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 -1 55 Center 2 +SYMATTR Value LT3489 +SYMATTR Prefix X +SYMATTR SpiceModel LT3489.sub +SYMATTR Value2 LT3489 +SYMATTR Description 2MHz Boost DC/DC Converter with 2.5A Switch and Soft-Start +PIN -128 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -128 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN 128 80 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3491.asy b/spice/copy/sym/PowerProducts/LT3491.asy new file mode 100755 index 0000000..712b880 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3491.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LT3491 +SYMATTR Prefix X +SYMATTR SpiceModel LT3491.sub +SYMATTR Value2 LT3491 +SYMATTR Description White LED Driver with Integrated Schottky in SC70 or 2mm × 2mm DFN +PIN -128 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 0 -112 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName Cap +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 5 +PIN -128 64 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3492.asy b/spice/copy/sym/PowerProducts/LT3492.asy new file mode 100755 index 0000000..47f0bac --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3492.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3492 +SYMATTR Prefix X +SYMATTR SpiceModel LT3492.sub +SYMATTR Value2 LT3492 +SYMATTR Description Triple Output LED Driver(1 of 3 channels modeled) +PIN -176 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -176 0 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -176 128 LEFT 8 +PINATTR PinName Fadj +PINATTR SpiceOrder 4 +PIN 176 128 RIGHT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 7 +PIN -176 64 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 8 +PIN 176 0 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 9 +PIN 176 -64 RIGHT 8 +PINATTR PinName OVP1 +PINATTR SpiceOrder 10 +PIN 0 -192 TOP 8 +PINATTR PinName ISN1 +PINATTR SpiceOrder 12 +PIN -112 -192 TOP 8 +PINATTR PinName ISP1 +PINATTR SpiceOrder 13 +PIN 112 -192 TOP 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 14 +PIN 176 -128 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 15 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3493-3.asy b/spice/copy/sym/PowerProducts/LT3493-3.asy new file mode 100755 index 0000000..6cc6fe8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3493-3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -55 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3493-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3493-3.sub +SYMATTR Value2 LT3493-3 +SYMATTR Description 1.2A, 750KHz Step-Down Switching Regulator in 2mm × 3mm DFN +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -128 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -128 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3493.asy b/spice/copy/sym/PowerProducts/LT3493.asy new file mode 100755 index 0000000..03f94ae --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3493.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -55 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3493 +SYMATTR Prefix X +SYMATTR SpiceModel LT3493.sub +SYMATTR Value2 LT3493 +SYMATTR Description 1.2A, 750KHz Step-Down Switching Regulator in 2mm × 3mm DFN +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -128 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -128 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3494.asy b/spice/copy/sym/PowerProducts/LT3494.asy new file mode 100755 index 0000000..45a7f25 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3494.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3494 +SYMATTR Prefix X +SYMATTR SpiceModel LT3494.sub +SYMATTR Value2 LT3494 +SYMATTR Description µPower Low Noise Boost Converter with Output Disconnect +PIN -128 -96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 -32 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 4 +PIN -128 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3494A.asy b/spice/copy/sym/PowerProducts/LT3494A.asy new file mode 100755 index 0000000..5143601 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3494A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3494A +SYMATTR Prefix X +SYMATTR SpiceModel LT3494A.sub +SYMATTR Value2 LT3494A +SYMATTR Description µPower Low Noise Boost Converter with Output Disconnect +PIN -128 -96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 -32 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 4 +PIN -128 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3495-1.asy b/spice/copy/sym/PowerProducts/LT3495-1.asy new file mode 100755 index 0000000..9a308fb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3495-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3495-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3495-1.sub +SYMATTR Value2 LT3495-1 +SYMATTR Description 350mA µPower Low Noise Boost Converter with Output Disconnect +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 64 -144 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 8 +PIN -64 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3495.asy b/spice/copy/sym/PowerProducts/LT3495.asy new file mode 100755 index 0000000..10d96b5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3495.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3495 +SYMATTR Prefix X +SYMATTR SpiceModel LT3495.sub +SYMATTR Value2 LT3495 +SYMATTR Description 650mA µPower Low Noise Boost Converter with Output Disconnect +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 64 -144 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 8 +PIN -64 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3495B-1.asy b/spice/copy/sym/PowerProducts/LT3495B-1.asy new file mode 100755 index 0000000..7f363d9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3495B-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3495B-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3495B-1.sub +SYMATTR Value2 LT3495B-1 +SYMATTR Description 350mA µPower Low Noise Boost Converter with Output Disconnect +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 64 -144 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 8 +PIN -64 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3495B.asy b/spice/copy/sym/PowerProducts/LT3495B.asy new file mode 100755 index 0000000..c20b26f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3495B.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3495B +SYMATTR Prefix X +SYMATTR SpiceModel LT3495B.sub +SYMATTR Value2 LT3495B +SYMATTR Description 650mA µPower Low Noise Boost Converter with Output Disconnect +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 64 -144 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 8 +PIN -64 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3496.asy b/spice/copy/sym/PowerProducts/LT3496.asy new file mode 100755 index 0000000..4b65fd9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3496.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3496 +SYMATTR Prefix X +SYMATTR SpiceModel LT3496.sub +SYMATTR Value2 LT3496 +SYMATTR Description Triple Output LED Driver(1 of 3 channels modeled) +PIN -176 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -176 0 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -176 128 LEFT 8 +PINATTR PinName Fadj +PINATTR SpiceOrder 4 +PIN 176 128 RIGHT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 7 +PIN -176 64 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 8 +PIN 176 0 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 9 +PIN 176 -64 RIGHT 8 +PINATTR PinName OVP1 +PINATTR SpiceOrder 10 +PIN 0 -192 TOP 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 12 +PIN -112 -192 TOP 8 +PINATTR PinName CAP1 +PINATTR SpiceOrder 13 +PIN 112 -192 TOP 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 14 +PIN 176 -128 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 15 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3497.asy b/spice/copy/sym/PowerProducts/LT3497.asy new file mode 100755 index 0000000..80f10bf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3497.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LT3497 +SYMATTR Prefix X +SYMATTR SpiceModel LT3497.sub +SYMATTR Value2 LT3497 +SYMATTR Description Dual Full Function White LED Driver with Integrated Schottky Diodes(1 of 2 channels modeled) +PIN -128 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 0 -112 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName Cap +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 5 +PIN -128 64 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3498.asy b/spice/copy/sym/PowerProducts/LT3498.asy new file mode 100755 index 0000000..8595c31 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3498.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -240 176 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 103 Center 2 +SYMATTR Value LT3498 +SYMATTR Prefix X +SYMATTR SpiceModel LT3498.sub +SYMATTR Value2 LT3498 +SYMATTR Description 20mA LED Driver and OLED Driver with Integrated Schottky in 3m × 2mm DFN +PIN -192 -64 LEFT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 1 +PIN -192 160 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 2 +PIN -112 240 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN 112 240 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 176 160 RIGHT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 5 +PIN 176 48 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 6 +PIN 176 -64 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 7 +PIN 176 -176 RIGHT 8 +PINATTR PinName CAP2 +PINATTR SpiceOrder 8 +PIN 112 -240 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 9 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -112 -240 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 11 +PIN -192 -176 LEFT 8 +PINATTR PinName CAP1 +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3500.asy b/spice/copy/sym/PowerProducts/LT3500.asy new file mode 100755 index 0000000..febcc2f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3500.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -304 160 272 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -168 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value LT3500 +SYMATTR Prefix X +SYMATTR SpiceModel LT3500.sub +SYMATTR Value2 LT3500 +SYMATTR Description Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller +PIN -80 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 -224 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -160 224 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 4 +PIN -160 112 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -160 -112 LEFT 8 +PINATTR PinName _Pgood +PINATTR SpiceOrder 7 +PIN 160 -112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN 160 224 RIGHT 8 +PINATTR PinName LFB +PINATTR SpiceOrder 9 +PIN 160 112 RIGHT 8 +PINATTR PinName LDRV +PINATTR SpiceOrder 10 +PIN 80 -304 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 11 +PIN 160 -224 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3501.asy b/spice/copy/sym/PowerProducts/LT3501.asy new file mode 100755 index 0000000..f7c3b1d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3501.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -304 208 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 160 Center 2 +SYMATTR Value LT3501 +SYMATTR Prefix X +SYMATTR SpiceModel LT3501.sub +SYMATTR Value2 LT3501 +SYMATTR Description Dual Tracking 3A Step-Down Switching Regulator\n\nNote: Drop-out demand boost cap refresh is not modeled. +PIN 80 -304 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 1 +PIN 208 -128 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 2 +PIN 208 -64 RIGHT 8 +PINATTR PinName IND1 +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 4 +PIN 208 192 RIGHT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 5 +PIN -208 192 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 6 +PIN -208 0 LEFT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 7 +PIN -208 -64 LEFT 8 +PINATTR PinName IND2 +PINATTR SpiceOrder 8 +PIN -208 -128 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 9 +PIN -80 -304 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 10 +PIN -208 -192 LEFT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 11 +PIN -208 256 LEFT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 12 +PIN -208 128 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 13 +PIN -208 64 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 14 +PIN -208 -256 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 +PIN 208 -256 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 16 +PIN 208 64 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 17 +PIN 208 128 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 18 +PIN 208 256 RIGHT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 19 +PIN 208 -192 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 20 +PIN 0 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT3502.asy b/spice/copy/sym/PowerProducts/LT3502.asy new file mode 100755 index 0000000..4fa048e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3502.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -192 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3502 +SYMATTR Prefix X +SYMATTR SpiceModel LT3502.sub +SYMATTR Value2 LT3502 +SYMATTR Description 1.1MHz, 500mA Step-Down Regulator in 2mmx2mm DFN +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName BD +PINATTR SpiceOrder 2 +PIN 144 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 6 +PIN 144 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3502A.asy b/spice/copy/sym/PowerProducts/LT3502A.asy new file mode 100755 index 0000000..48f65d4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3502A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -192 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3502A +SYMATTR Prefix X +SYMATTR SpiceModel LT3502A.sub +SYMATTR Value2 LT3502A +SYMATTR Description 2.2MHz, 500mA Step-Down Regulator in 2mmx2mm DFN +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName BD +PINATTR SpiceOrder 2 +PIN 144 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN -144 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 6 +PIN 144 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3503.asy b/spice/copy/sym/PowerProducts/LT3503.asy new file mode 100755 index 0000000..505d378 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3503.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -55 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3503 +SYMATTR Prefix X +SYMATTR SpiceModel LT3503.sub +SYMATTR Value2 LT3503 +SYMATTR Description 1.2A, 2.2MHz Step-Down Switching Regulator in 2mm × 3mm DFN +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 0 -128 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 3 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -128 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -128 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3504.asy b/spice/copy/sym/PowerProducts/LT3504.asy new file mode 100755 index 0000000..933f8e7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3504.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -592 208 592 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -288 Center 2 +WINDOW 3 0 288 Center 2 +SYMATTR Value LT3504 +SYMATTR Prefix X +SYMATTR SpiceModel LT3504.sub +SYMATTR Value2 LT3504 +SYMATTR Description Quad 40V/1A Step-Down Switching Regulator with 100% Duty Cycle Operation +PIN 208 144 RIGHT 8 +PINATTR PinName DA2 +PINATTR SpiceOrder 1 +PIN 208 48 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 208 -144 RIGHT 8 +PINATTR PinName DA3 +PINATTR SpiceOrder 3 +PIN 208 -240 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 4 +PIN 208 336 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 5 +PIN 208 432 RIGHT 8 +PINATTR PinName DA1 +PINATTR SpiceOrder 6 +PIN 208 -528 RIGHT 8 +PINATTR PinName SW4 +PINATTR SpiceOrder 7 +PIN 208 -432 RIGHT 8 +PINATTR PinName DA4 +PINATTR SpiceOrder 8 +PIN -208 -240 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -208 528 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -208 240 LEFT 8 +PINATTR PinName Run/SS4 +PINATTR SpiceOrder 12 +PIN -208 -48 LEFT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 13 +PIN -208 48 LEFT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 14 +PIN -208 144 LEFT 8 +PINATTR PinName Run/SS3 +PINATTR SpiceOrder 15 +PIN -208 -144 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 16 +PIN -208 432 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 17 +PIN 208 -336 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 19 +PIN 208 528 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 20 +PIN 208 -48 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 21 +PIN 208 240 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 22 +PIN -208 336 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 23 +PIN -208 -432 LEFT 8 +PINATTR PinName SW5 +PINATTR SpiceOrder 24 +PIN -208 -528 LEFT 8 +PINATTR PinName Sky +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT3505.asy b/spice/copy/sym/PowerProducts/LT3505.asy new file mode 100755 index 0000000..02c3174 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3505.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT3505 +SYMATTR Prefix X +SYMATTR SpiceModel LT3505.sub +SYMATTR Value2 LT3505 +SYMATTR Description 1.2A Step-Down Switching Regulator in 3mm × 3mm DFN +PIN 0 -176 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN 160 -128 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN -160 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 4 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -160 128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 160 128 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT3506.asy b/spice/copy/sym/PowerProducts/LT3506.asy new file mode 100755 index 0000000..6ba4909 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3506.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -208 208 208 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 57 Center 2 +SYMATTR Value LT3506 +SYMATTR Prefix X +SYMATTR SpiceModel LT3506.sub +SYMATTR Value2 LT3506 +SYMATTR Description Dual Monolithic 1.6A Step-Down Switching Regulator +PIN 208 -160 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 1 +PIN 208 -96 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 0 -208 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -208 -96 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -208 -160 LEFT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 8 +PIN -208 -32 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN -208 32 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 10 +PIN -208 96 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 11 +PIN -208 160 LEFT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 12 +PIN 208 160 RIGHT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 13 +PIN 208 96 RIGHT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 14 +PIN 208 32 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 15 +PIN 208 -32 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3506A.asy b/spice/copy/sym/PowerProducts/LT3506A.asy new file mode 100755 index 0000000..4799d36 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3506A.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -208 208 208 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 57 Center 2 +SYMATTR Value LT3506A +SYMATTR Prefix X +SYMATTR SpiceModel LT3506A.sub +SYMATTR Value2 LT3506A +SYMATTR Description Dual Monolithic 1.6A Step-Down Switching Regulator +PIN 208 -160 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 1 +PIN 208 -96 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 0 -208 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -208 -96 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -208 -160 LEFT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 8 +PIN -208 -32 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN -208 32 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 10 +PIN -208 96 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 11 +PIN -208 160 LEFT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 12 +PIN 208 160 RIGHT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 13 +PIN 208 96 RIGHT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 14 +PIN 208 32 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 15 +PIN 208 -32 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3507.asy b/spice/copy/sym/PowerProducts/LT3507.asy new file mode 100755 index 0000000..02a9a51 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3507.asy @@ -0,0 +1,110 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -480 208 480 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT3507 +SYMATTR Prefix X +SYMATTR SpiceModel LT3507.sub +SYMATTR Value2 LT3507 +SYMATTR Description Triple Monolithic Step-Down Regulator with LDO +PIN -208 -352 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 1 +PIN -112 -480 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 208 288 RIGHT 8 +PINATTR PinName Vinsw +PINATTR SpiceOrder 4 +PIN 208 352 RIGHT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 5 +PIN 208 416 RIGHT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 6 +PIN -208 -160 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 7 +PIN -208 -32 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 8 +PIN -208 -224 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 9 +PIN -208 -96 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 10 +PIN 208 -96 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 11 +PIN -208 352 LEFT 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 12 +PIN 80 480 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 13 +PIN -208 -416 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 14 +PIN 208 -416 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 15 +PIN -208 32 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 16 +PIN 208 32 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 17 +PIN -208 416 LEFT 8 +PINATTR PinName Track/SS3 +PINATTR SpiceOrder 18 +PIN -208 288 LEFT 8 +PINATTR PinName Vc3 +PINATTR SpiceOrder 19 +PIN -208 224 LEFT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 20 +PIN 208 -32 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 21 +PIN 208 -224 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 22 +PIN 208 -160 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 23 +PIN 208 96 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 24 +PIN 208 160 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 25 +PIN 208 224 RIGHT 8 +PINATTR PinName Track/SS4 +PINATTR SpiceOrder 26 +PIN 208 -352 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 27 +PIN 208 -288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 28 +PIN 0 -480 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 30 +PIN -208 96 LEFT 8 +PINATTR PinName Boost3 +PINATTR SpiceOrder 32 +PIN -208 160 LEFT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 33 +PIN 112 -480 TOP 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 35 +PIN -208 -288 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 37 +PIN -64 480 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LT3507A.asy b/spice/copy/sym/PowerProducts/LT3507A.asy new file mode 100755 index 0000000..acba9c8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3507A.asy @@ -0,0 +1,110 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -480 208 480 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT3507A +SYMATTR Prefix X +SYMATTR SpiceModel LT3507A.sub +SYMATTR Value2 LT3507A +SYMATTR Description Triple Monolithic Step-Down Regulator with LDO +PIN -208 -352 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 1 +PIN -112 -480 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 208 288 RIGHT 8 +PINATTR PinName Vinsw +PINATTR SpiceOrder 4 +PIN 208 352 RIGHT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 5 +PIN 208 416 RIGHT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 6 +PIN -208 -160 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 7 +PIN -208 -32 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 8 +PIN -208 -224 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 9 +PIN -208 -96 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 10 +PIN 208 -96 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 11 +PIN -208 352 LEFT 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 12 +PIN 80 480 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 13 +PIN -208 -416 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 14 +PIN 208 -416 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 15 +PIN -208 32 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 16 +PIN 208 32 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 17 +PIN -208 416 LEFT 8 +PINATTR PinName Track/SS3 +PINATTR SpiceOrder 18 +PIN -208 288 LEFT 8 +PINATTR PinName Vc3 +PINATTR SpiceOrder 19 +PIN -208 224 LEFT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 20 +PIN 208 -32 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 21 +PIN 208 -224 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 22 +PIN 208 -160 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 23 +PIN 208 96 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 24 +PIN 208 160 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 25 +PIN 208 224 RIGHT 8 +PINATTR PinName Track/SS4 +PINATTR SpiceOrder 26 +PIN 208 -352 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 27 +PIN 208 -288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 28 +PIN 0 -480 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 30 +PIN -208 96 LEFT 8 +PINATTR PinName Boost3 +PINATTR SpiceOrder 32 +PIN -208 160 LEFT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 33 +PIN 112 -480 TOP 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 35 +PIN -208 -288 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 37 +PIN -64 480 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LT3508.asy b/spice/copy/sym/PowerProducts/LT3508.asy new file mode 100755 index 0000000..4fa9c02 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3508.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -208 208 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3508 +SYMATTR Prefix X +SYMATTR SpiceModel LT3508.sub +SYMATTR Value2 LT3508 +SYMATTR Description Dual Monolithic 1.4A Step-Down Switching Regulator +PIN 208 -160 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 1 +PIN 0 -208 TOP 6 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN 208 -96 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 96 -208 TOP 6 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN 64 208 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -208 -96 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN -64 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -208 -160 LEFT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 8 +PIN -208 -32 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN -208 32 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 10 +PIN -208 96 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 11 +PIN -208 160 LEFT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 12 +PIN 208 160 RIGHT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 13 +PIN 208 96 RIGHT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 14 +PIN 208 32 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 15 +PIN 208 -32 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 16 +PIN -96 -208 TOP 6 +PINATTR PinName Vin2 +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3509.asy b/spice/copy/sym/PowerProducts/LT3509.asy new file mode 100755 index 0000000..cbd8e11 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3509.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -192 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3509 +SYMATTR Prefix X +SYMATTR SpiceModel LT3509.sub +SYMATTR Value2 LT3509 +SYMATTR Description Dual 36V, 700mA Step-Down Regulator\n\nNote: Only one of two channels modeled. +PIN -144 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName BD +PINATTR SpiceOrder 2 +PIN 144 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 4 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 6 +PIN 144 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN -144 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3510.asy b/spice/copy/sym/PowerProducts/LT3510.asy new file mode 100755 index 0000000..6a7e63b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3510.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -304 208 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 160 Center 2 +SYMATTR Value LT3510 +SYMATTR Prefix X +SYMATTR SpiceModel LT3510.sub +SYMATTR Value2 LT3510 +SYMATTR Description Dual Tracking 2A Step-Down Switching Regulator\n\nNote: Drop-out demand boost cap refresh is not modeled. +PIN 80 -304 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 1 +PIN 208 -128 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 2 +PIN 208 -64 RIGHT 8 +PINATTR PinName IND1 +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 4 +PIN 208 192 RIGHT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 5 +PIN -208 192 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 6 +PIN -208 0 LEFT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 7 +PIN -208 -64 LEFT 8 +PINATTR PinName IND2 +PINATTR SpiceOrder 8 +PIN -208 -128 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 9 +PIN -80 -304 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 10 +PIN -208 -192 LEFT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 11 +PIN -208 256 LEFT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 12 +PIN -208 128 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 13 +PIN -208 64 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 14 +PIN -208 -256 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 +PIN 208 -256 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 16 +PIN 208 64 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 17 +PIN 208 128 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 18 +PIN 208 256 RIGHT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 19 +PIN 208 -192 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 20 +PIN 0 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT3511.asy b/spice/copy/sym/PowerProducts/LT3511.asy new file mode 100755 index 0000000..7de2b41 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3511.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT3511 +SYMATTR Prefix X +SYMATTR SpiceModel LT3511.sub +SYMATTR Value2 LT3511 +SYMATTR Description Monolithic High Voltage Isolated Flyback Converter +PIN -160 -112 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 128 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 +PIN -160 48 LEFT 8 +PINATTR PinName Tc +PINATTR SpiceOrder 11 +PIN 160 48 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 12 +PIN 160 -112 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 14 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3512.asy b/spice/copy/sym/PowerProducts/LT3512.asy new file mode 100755 index 0000000..bcc1013 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3512.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT3512 +SYMATTR Prefix X +SYMATTR SpiceModel LT3512.sub +SYMATTR Value2 LT3512 +SYMATTR Description Monolithic High Voltage Isolated Flyback Converter +PIN -160 -112 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 128 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 +PIN -160 48 LEFT 8 +PINATTR PinName Tc +PINATTR SpiceOrder 11 +PIN 160 48 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 12 +PIN 160 -112 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 14 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3513.asy b/spice/copy/sym/PowerProducts/LT3513.asy new file mode 100755 index 0000000..8de557a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3513.asy @@ -0,0 +1,107 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -512 288 496 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -248 Center 2 +WINDOW 3 0 232 Center 2 +SYMATTR Value LT3513 +SYMATTR Prefix X +SYMATTR SpiceModel LT3513.sub +SYMATTR Value2 LT3513 +SYMATTR Description 2MHz High Current 5-Output Regulator for TFT-LCD Panels +PIN -288 432 LEFT 8 +PINATTR PinName FB5 +PINATTR SpiceOrder 1 +PIN -224 496 BOTTOM 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 2 +PIN 288 -128 RIGHT 8 +PINATTR PinName Run-SS3/4 +PINATTR SpiceOrder 3 +PIN 288 432 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 4 +PIN 288 -208 RIGHT 8 +PINATTR PinName Run-SS2 +PINATTR SpiceOrder 5 +PIN 288 272 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 6 +PIN 288 352 RIGHT 8 +PINATTR PinName E3 +PINATTR SpiceOrder 7 +PIN 288 112 RIGHT 8 +PINATTR PinName Von +PINATTR SpiceOrder 8 +PIN 288 192 RIGHT 8 +PINATTR PinName Vonsink +PINATTR SpiceOrder 9 +PIN 288 32 RIGHT 8 +PINATTR PinName Von_clk +PINATTR SpiceOrder 10 +PIN 288 -368 RIGHT 8 +PINATTR PinName _PGOOD +PINATTR SpiceOrder 11 +PIN 96 496 BOTTOM 8 +PINATTR PinName Vc3 +PINATTR SpiceOrder 12 +PIN 288 -48 RIGHT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 13 +PIN 128 -512 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 15 +PIN -288 -128 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 18 +PIN 288 -448 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 19 +PIN -96 496 BOTTOM 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 20 +PIN 224 496 BOTTOM 8 +PINATTR PinName Vc4 +PINATTR SpiceOrder 21 +PIN 288 -288 RIGHT 8 +PINATTR PinName Run-SS1 +PINATTR SpiceOrder 22 +PIN -288 -208 LEFT 8 +PINATTR PinName NFB4 +PINATTR SpiceOrder 23 +PIN -288 -288 LEFT 8 +PINATTR PinName D4 +PINATTR SpiceOrder 24 +PIN -288 -368 LEFT 8 +PINATTR PinName SW4 +PINATTR SpiceOrder 25 +PIN -288 352 LEFT 8 +PINATTR PinName BD +PINATTR SpiceOrder 26 +PIN -16 -512 TOP 8 +PINATTR PinName LDOPWR +PINATTR SpiceOrder 27 +PIN -288 -48 LEFT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 28 +PIN -288 192 LEFT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 30 +PIN -288 112 LEFT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 31 +PIN -288 272 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 32 +PIN -288 32 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN -160 -512 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 36 +PIN -288 -448 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 38 +PIN 0 496 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LT3514.asy b/spice/copy/sym/PowerProducts/LT3514.asy new file mode 100755 index 0000000..262a59c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3514.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -448 208 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT3514 +SYMATTR Prefix X +SYMATTR SpiceModel LT3514.sub +SYMATTR Value2 LT3514 +SYMATTR Description Triple Step-Down Switching Regulator with 100% Duty Cycle Operation +PIN 208 0 RIGHT 8 +PINATTR PinName DA3 +PINATTR SpiceOrder 3 +PIN 208 -96 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 4 +PIN 208 192 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 5 +PIN 208 288 RIGHT 8 +PINATTR PinName DA1 +PINATTR SpiceOrder 6 +PIN 208 -384 RIGHT 8 +PINATTR PinName SW4 +PINATTR SpiceOrder 7 +PIN 208 -288 RIGHT 8 +PINATTR PinName DA4 +PINATTR SpiceOrder 8 +PIN -208 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -208 192 LEFT 8 +PINATTR PinName Run/SS4 +PINATTR SpiceOrder 12 +PIN -208 0 LEFT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 13 +PIN -208 96 LEFT 8 +PINATTR PinName Run/SS3 +PINATTR SpiceOrder 15 +PIN -208 -96 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 16 +PIN -208 384 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 17 +PIN 208 -192 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 19 +PIN 208 384 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 20 +PIN 208 96 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 21 +PIN -208 288 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 23 +PIN -208 -288 LEFT 8 +PINATTR PinName SW5 +PINATTR SpiceOrder 24 +PIN -208 -384 LEFT 8 +PINATTR PinName Sky +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT3517.asy b/spice/copy/sym/PowerProducts/LT3517.asy new file mode 100755 index 0000000..9e67172 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3517.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3517 +SYMATTR Prefix X +SYMATTR SpiceModel LT3517.sub +SYMATTR Value2 LT3517 +SYMATTR Description Full-Featured LED Controller with 1.5A Switch Current +PIN -176 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -176 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -176 -32 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN 176 -32 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 176 160 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN 176 96 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 6 +PIN -176 96 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 7 +PIN -176 160 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 8 +PIN 176 32 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN 176 -96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -176 32 LEFT 8 +PINATTR PinName TGEN +PINATTR SpiceOrder 11 +PIN 0 -224 TOP 8 +PINATTR PinName ISN +PINATTR SpiceOrder 12 +PIN -112 -224 TOP 8 +PINATTR PinName ISP +PINATTR SpiceOrder 13 +PIN 112 -224 TOP 8 +PINATTR PinName TG +PINATTR SpiceOrder 14 +PIN 176 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 15 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3518.asy b/spice/copy/sym/PowerProducts/LT3518.asy new file mode 100755 index 0000000..8f3b511 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3518.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3518 +SYMATTR Prefix X +SYMATTR SpiceModel LT3518.sub +SYMATTR Value2 LT3518 +SYMATTR Description Full-Featured LED Controller with 2.3A Switch Current +PIN -176 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -176 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -176 -32 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN 176 -32 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 176 160 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN 176 96 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 6 +PIN -176 96 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 7 +PIN -176 160 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 8 +PIN 176 32 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN 176 -96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -176 32 LEFT 8 +PINATTR PinName TGEN +PINATTR SpiceOrder 11 +PIN 0 -224 TOP 8 +PINATTR PinName ISN +PINATTR SpiceOrder 12 +PIN -112 -224 TOP 8 +PINATTR PinName ISP +PINATTR SpiceOrder 13 +PIN 112 -224 TOP 8 +PINATTR PinName TG +PINATTR SpiceOrder 14 +PIN 176 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 15 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3519-1.asy b/spice/copy/sym/PowerProducts/LT3519-1.asy new file mode 100755 index 0000000..e82e456 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3519-1.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 224 +TEXT 0 8 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LT3519-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3519.sub +SYMATTR Value2 LT3519 X=925n +SYMATTR Description LED Driver with Integrated Schottky Diode +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 176 176 RIGHT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 3 +PIN -176 -48 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 4 +PIN -176 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -112 -224 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 0 -224 TOP 8 +PINATTR PinName Anode +PINATTR SpiceOrder 7 +PIN 112 -224 TOP 8 +PINATTR PinName Cathode +PINATTR SpiceOrder 10 +PIN 176 -160 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 11 +PIN 176 -48 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 12 +PIN 176 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 13 +PIN -176 176 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 14 +PIN -176 64 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3519-2.asy b/spice/copy/sym/PowerProducts/LT3519-2.asy new file mode 100755 index 0000000..37ceafd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3519-2.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 224 +TEXT 0 8 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LT3519-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3519.sub +SYMATTR Value2 LT3519 X=380n +SYMATTR Description LED Driver with Integrated Schottky Diode +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 176 176 RIGHT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 3 +PIN -176 -48 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 4 +PIN -176 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -112 -224 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 0 -224 TOP 8 +PINATTR PinName Anode +PINATTR SpiceOrder 7 +PIN 112 -224 TOP 8 +PINATTR PinName Cathode +PINATTR SpiceOrder 10 +PIN 176 -160 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 11 +PIN 176 -48 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 12 +PIN 176 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 13 +PIN -176 176 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 14 +PIN -176 64 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3519.asy b/spice/copy/sym/PowerProducts/LT3519.asy new file mode 100755 index 0000000..0d62d2b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3519.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 224 +TEXT 0 8 Center 2 LT +WINDOW 0 0 -104 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LT3519 +SYMATTR Prefix X +SYMATTR SpiceModel LT3519.sub +SYMATTR Value2 LT3519 X=2.4u +SYMATTR Description LED Driver with Integrated Schottky Diode +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 176 176 RIGHT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 3 +PIN -176 -48 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 4 +PIN -176 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -112 -224 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 0 -224 TOP 8 +PINATTR PinName Anode +PINATTR SpiceOrder 7 +PIN 112 -224 TOP 8 +PINATTR PinName Cathode +PINATTR SpiceOrder 10 +PIN 176 -160 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 11 +PIN 176 -48 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 12 +PIN 176 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 13 +PIN -176 176 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 14 +PIN -176 64 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3570.asy b/spice/copy/sym/PowerProducts/LT3570.asy new file mode 100755 index 0000000..917f83b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3570.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -352 160 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3570 +SYMATTR Prefix X +SYMATTR SpiceModel LT3570.sub +SYMATTR Value2 LT3570 +SYMATTR Description 1.5A Buck Converter, 1.5A Boost Converter and LDO Controller +PIN 0 -352 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 1 +PIN 160 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 4 +PIN 48 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -80 -352 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 7 +PIN -160 192 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 8 +PIN -160 288 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 9 +PIN -160 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 10 +PIN -160 -288 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 11 +PIN -160 -192 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 12 +PIN -160 -96 LEFT 8 +PINATTR PinName _SHDN3 +PINATTR SpiceOrder 13 +PIN -48 352 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN 160 0 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 17 +PIN 160 96 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 18 +PIN 160 -96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 19 +PIN 160 288 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 20 +PIN 160 192 RIGHT 8 +PINATTR PinName NPN_Drv +PINATTR SpiceOrder 21 +PIN 80 -352 TOP 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 22 +PIN 160 -288 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LT3571.asy b/spice/copy/sym/PowerProducts/LT3571.asy new file mode 100755 index 0000000..4eddbe3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3571.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3571 +SYMATTR Prefix X +SYMATTR SpiceModel LT3571.sub +SYMATTR Value2 LT3571 +SYMATTR Description 75V DC/DC Converter for APD Bias +PIN 160 -144 RIGHT 8 +PINATTR PinName APD +PINATTR SpiceOrder 2 +PIN 160 48 RIGHT 8 +PINATTR PinName MonIn +PINATTR SpiceOrder 3 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 64 -208 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -64 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 9 +PIN -64 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -160 -144 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 12 +PIN -160 -48 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 13 +PIN -160 48 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 14 +PIN 160 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 15 +PIN 64 208 BOTTOM 8 +PINATTR PinName MON +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3572.asy b/spice/copy/sym/PowerProducts/LT3572.asy new file mode 100755 index 0000000..920d4df --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3572.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -368 176 320 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3572 +SYMATTR Prefix X +SYMATTR SpiceModel LT3572.sub +SYMATTR Value2 LT3572 +SYMATTR Description Dual Full-Bridge Piezo Driver with 900mA Boost Converter +PIN 0 -368 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -112 -368 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -176 288 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 3 +PIN 176 288 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 16 320 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -176 192 LEFT 8 +PINATTR PinName PWMB +PINATTR SpiceOrder 6 +PIN -176 96 LEFT 8 +PINATTR PinName PWMA +PINATTR SpiceOrder 7 +PIN 112 -368 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN -176 -288 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 +PIN -176 -192 LEFT 8 +PINATTR PinName _SHDNA +PINATTR SpiceOrder 11 +PIN -176 -96 LEFT 8 +PINATTR PinName _SHDNB +PINATTR SpiceOrder 12 +PIN 176 -288 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 13 +PIN 176 192 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN -176 0 LEFT 8 +PINATTR PinName _Pgood +PINATTR SpiceOrder 15 +PIN 176 96 RIGHT 8 +PINATTR PinName _OUTB +PINATTR SpiceOrder 16 +PIN 176 0 RIGHT 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 17 +PIN 176 -192 RIGHT 8 +PINATTR PinName OUTA +PINATTR SpiceOrder 18 +PIN 176 -96 RIGHT 8 +PINATTR PinName _OUTA +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LT3573.asy b/spice/copy/sym/PowerProducts/LT3573.asy new file mode 100755 index 0000000..1fb2215 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3573.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT3573 +SYMATTR Prefix X +SYMATTR SpiceModel LT3573.sub +SYMATTR Value2 LT3573 +SYMATTR Description Isolated Flyback Converter Without an Opto-Coupler +PIN 64 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 160 128 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -112 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 7 +PIN -64 192 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 10 +PIN -160 48 LEFT 8 +PINATTR PinName Rlim +PINATTR SpiceOrder 11 +PIN -160 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN 160 -112 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 13 +PIN 160 48 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 14 +PIN -160 -32 LEFT 8 +PINATTR PinName TC +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3574.asy b/spice/copy/sym/PowerProducts/LT3574.asy new file mode 100755 index 0000000..bdc7477 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3574.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT3574 +SYMATTR Prefix X +SYMATTR SpiceModel LT3574.sub +SYMATTR Value2 LT3574 +SYMATTR Description Isolated Flyback Converter Without an Opto-Coupler +PIN 64 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 160 128 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -112 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 7 +PIN -64 192 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 10 +PIN -160 48 LEFT 8 +PINATTR PinName Rlim +PINATTR SpiceOrder 11 +PIN -160 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN 160 -112 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 13 +PIN 160 48 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 14 +PIN -160 -32 LEFT 8 +PINATTR PinName TC +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3575.asy b/spice/copy/sym/PowerProducts/LT3575.asy new file mode 100755 index 0000000..d4f636e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3575.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT3575 +SYMATTR Prefix X +SYMATTR SpiceModel LT3575.sub +SYMATTR Value2 LT3575 +SYMATTR Description Isolated Flyback Converter Without an Opto-Coupler +PIN 64 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 160 128 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -112 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 7 +PIN -64 192 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 10 +PIN -160 48 LEFT 8 +PINATTR PinName Rlim +PINATTR SpiceOrder 11 +PIN -160 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN 160 -112 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 13 +PIN 160 48 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 14 +PIN -160 -32 LEFT 8 +PINATTR PinName TC +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3579-1.asy b/spice/copy/sym/PowerProducts/LT3579-1.asy new file mode 100755 index 0000000..b1c33f1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3579-1.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3579-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3579.sub +SYMATTR Value2 LT3579 +SYMATTR Description 6A Boost/Inverting DC/DC Converter with Fault Protection\n\nSYNC and CLKOUT pins are not modeled +PIN 144 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 144 -48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 4 +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -48 -208 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 6 +PIN 48 -208 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 9 +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 13 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 14 +PIN 144 144 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 15 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3579.asy b/spice/copy/sym/PowerProducts/LT3579.asy new file mode 100755 index 0000000..65e3094 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3579.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3579 +SYMATTR Prefix X +SYMATTR SpiceModel LT3579.sub +SYMATTR Value2 LT3579 +SYMATTR Description 6A Boost/Inverting DC/DC Converter with Fault Protection\n\nSYNC and CLKOUT pins are not modeled +PIN 144 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 144 -48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 4 +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -48 -208 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 6 +PIN 48 -208 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 9 +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 13 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 14 +PIN 144 144 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 15 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3580.asy b/spice/copy/sym/PowerProducts/LT3580.asy new file mode 100755 index 0000000..0d65139 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3580.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT3580 +SYMATTR Prefix X +SYMATTR SpiceModel LT3580.sub +SYMATTR Value2 LT3580 +SYMATTR Description Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3581.asy b/spice/copy/sym/PowerProducts/LT3581.asy new file mode 100755 index 0000000..ea6cce8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3581.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3581 +SYMATTR Prefix X +SYMATTR SpiceModel LT3581.sub +SYMATTR Value2 LT3581 +SYMATTR Description 3.3A Boost/Inverting DC/DC Converter with Fault Protection\n\nSYNC and CLKOUT pins are not modeled +PIN 144 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 144 -48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 4 +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -48 -208 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 6 +PIN 48 -208 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 9 +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 13 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 14 +PIN 144 144 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 15 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3585-0.asy b/spice/copy/sym/PowerProducts/LT3585-0.asy new file mode 100755 index 0000000..729c498 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3585-0.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 44 Center 2 +SYMATTR Value LT3585-0 +SYMATTR Prefix X +SYMATTR SpiceModel LT3585-0.sub +SYMATTR Value2 LT3585-0 +SYMATTR Description Photoflash Capacitor Charger with Adjustable Input Current and IGBT Driver +PIN -160 0 LEFT 8 +PINATTR PinName CHRG/Iadj +PINATTR SpiceOrder 1 +PIN 112 -144 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName IBGTPU +PINATTR SpiceOrder 5 +PIN 160 80 RIGHT 8 +PINATTR PinName IBGTPD +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName IBGTin +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName IBGTpwr +PINATTR SpiceOrder 8 +PIN -160 -80 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3585-1.asy b/spice/copy/sym/PowerProducts/LT3585-1.asy new file mode 100755 index 0000000..50d1f21 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3585-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 44 Center 2 +SYMATTR Value LT3585-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3585-1.sub +SYMATTR Value2 LT3585-1 +SYMATTR Description Photoflash Capacitor Charger with Adjustable Input Current and IGBT Driver +PIN -160 0 LEFT 8 +PINATTR PinName CHRG/Iadj +PINATTR SpiceOrder 1 +PIN 112 -144 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName IBGTPU +PINATTR SpiceOrder 5 +PIN 160 80 RIGHT 8 +PINATTR PinName IBGTPD +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName IBGTin +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName IBGTpwr +PINATTR SpiceOrder 8 +PIN -160 -80 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3585-2.asy b/spice/copy/sym/PowerProducts/LT3585-2.asy new file mode 100755 index 0000000..220e283 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3585-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 44 Center 2 +SYMATTR Value LT3585-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3585-2.sub +SYMATTR Value2 LT3585-2 +SYMATTR Description Photoflash Capacitor Charger with Adjustable Input Current and IGBT Driver +PIN -160 0 LEFT 8 +PINATTR PinName CHRG/Iadj +PINATTR SpiceOrder 1 +PIN 112 -144 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName IBGTPU +PINATTR SpiceOrder 5 +PIN 160 80 RIGHT 8 +PINATTR PinName IBGTPD +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName IBGTin +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName IBGTpwr +PINATTR SpiceOrder 8 +PIN -160 -80 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3585-3.asy b/spice/copy/sym/PowerProducts/LT3585-3.asy new file mode 100755 index 0000000..de12c6d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3585-3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 44 Center 2 +SYMATTR Value LT3585-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3585-3.sub +SYMATTR Value2 LT3585-3 +SYMATTR Description Photoflash Capacitor Charger with Adjustable Input Current and IGBT Driver +PIN -160 0 LEFT 8 +PINATTR PinName CHRG/Iadj +PINATTR SpiceOrder 1 +PIN 112 -144 TOP 8 +PINATTR PinName Vbat +PINATTR SpiceOrder 2 +PIN -112 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName IBGTPU +PINATTR SpiceOrder 5 +PIN 160 80 RIGHT 8 +PINATTR PinName IBGTPD +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName IBGTin +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName IBGTpwr +PINATTR SpiceOrder 8 +PIN -160 -80 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3587.asy b/spice/copy/sym/PowerProducts/LT3587.asy new file mode 100755 index 0000000..5435788 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3587.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 272 320 -272 -272 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -151 Center 2 +WINDOW 3 0 136 Center 2 +SYMATTR Value LT3587 +SYMATTR Prefix X +SYMATTR Description High Voltage Monolithic Inverter and Dual Boost +SYMATTR SpiceModel LT3587.sub +SYMATTR Value2 LT3587 +PIN 272 96 RIGHT 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 1 +PIN -272 -192 LEFT 8 +PINATTR PinName CAP3 +PINATTR SpiceOrder 2 +PIN -112 -272 TOP 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 3 +PIN 0 320 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -272 96 LEFT 8 +PINATTR PinName _FLT +PINATTR SpiceOrder 5 +PIN 272 256 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 6 +PIN -160 320 BOTTOM 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 9 +PIN 112 -272 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 11 +PIN 272 -192 RIGHT 8 +PINATTR PinName CAP1 +PINATTR SpiceOrder 13 +PIN 272 -112 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 14 +PIN 272 -32 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 15 +PIN -272 176 LEFT 8 +PINATTR PinName EN/SS1 +PINATTR SpiceOrder 16 +PIN 0 -272 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 17 +PIN -272 256 LEFT 8 +PINATTR PinName EN/SS3 +PINATTR SpiceOrder 18 +PIN -272 -112 LEFT 8 +PINATTR PinName Ifb3 +PINATTR SpiceOrder 19 +PIN 272 176 RIGHT 8 +PINATTR PinName Vfb3 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT3590.asy b/spice/copy/sym/PowerProducts/LT3590.asy new file mode 100755 index 0000000..7806d5b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3590.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 41 Center 2 +SYMATTR Value LT3590 +SYMATTR Prefix X +SYMATTR SpiceModel LT3590.sub +SYMATTR Value2 LT3590 +SYMATTR Description 48V Buck Mode LED Driver in SC70 and 2mm × 2mm DFN +PIN -144 -64 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -80 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 80 -144 TOP 8 +PINATTR PinName LED +PINATTR SpiceOrder 5 +PIN -144 64 LEFT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3591.asy b/spice/copy/sym/PowerProducts/LT3591.asy new file mode 100755 index 0000000..62f0470 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3591.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LT3591 +SYMATTR Prefix X +SYMATTR SpiceModel LT3591.sub +SYMATTR Value2 LT3591 +SYMATTR Description White LED Driver with Integrated Schottky in 3mm × 2mm DFN +PIN -128 -48 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 0 -112 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName Cap +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 5 +PIN -128 64 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT3592.asy b/spice/copy/sym/PowerProducts/LT3592.asy new file mode 100755 index 0000000..0d05ee4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3592.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -240 160 208 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -119 Center 2 +WINDOW 3 0 104 Center 2 +SYMATTR Value LT3592 +SYMATTR Prefix X +SYMATTR SpiceModel LT3592.sub +SYMATTR Value2 LT3592 +SYMATTR Description 500mA Wide Input Voltage Range Step-Down LED Driver with 10:1 Dimming +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -176 48 LEFT 8 +PINATTR PinName Bright +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -176 -176 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 160 -176 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 5 +PIN 80 -240 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN -80 -240 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 160 -64 RIGHT 8 +PINATTR PinName Cap +PINATTR SpiceOrder 8 +PIN 160 48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 9 +PIN 160 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3595.asy b/spice/copy/sym/PowerProducts/LT3595.asy new file mode 100755 index 0000000..fa506f0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3595.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 41 Center 2 +SYMATTR Value LT3595 +SYMATTR Prefix X +SYMATTR SpiceModel LT3595.sub +SYMATTR Value2 LT3595 +SYMATTR Description 16 Channel Buck Mode LED Driver\n\nNote: Only 1 of the 16 channels is modeled. +PIN -160 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -64 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 64 -144 TOP 8 +PINATTR PinName L1 +PINATTR SpiceOrder 3 +PIN 160 -80 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 0 RIGHT 8 +PINATTR PinName Rset +PINATTR SpiceOrder 6 +PIN 160 80 RIGHT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 7 +PIN -160 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 +PIN -160 80 LEFT 8 +PINATTR PinName _OpenLED +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3596.asy b/spice/copy/sym/PowerProducts/LT3596.asy new file mode 100755 index 0000000..be22685 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3596.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -432 192 480 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 232 Center 2 +SYMATTR Value LT3596 +SYMATTR Prefix X +SYMATTR SpiceModel LT3596.sub +SYMATTR Value2 LT3596 +SYMATTR Description 60V Step-Down LED Driver\n\nNote: Open LED logic and Fault is not modeled. +PIN -192 272 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN 192 -208 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 2 +PIN -80 -432 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 192 -288 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -192 -368 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 5 +PIN 192 432 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -192 -288 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 7 +PIN 192 192 RIGHT 8 +PINATTR PinName Iset1 +PINATTR SpiceOrder 8 +PIN -192 -128 LEFT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 9 +PIN -192 -48 LEFT 8 +PINATTR PinName PWM3 +PINATTR SpiceOrder 10 +PIN 192 -128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 192 272 RIGHT 8 +PINATTR PinName Iset2 +PINATTR SpiceOrder 12 +PIN 192 352 RIGHT 8 +PINATTR PinName Iset3 +PINATTR SpiceOrder 13 +PIN 0 480 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN 64 -432 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 15 +PIN 192 -368 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 +PIN -192 112 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 17 +PIN -192 -208 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 18 +PIN -192 192 LEFT 8 +PINATTR PinName CTRL3 +PINATTR SpiceOrder 19 +PIN -192 432 LEFT 8 +PINATTR PinName CTRLM +PINATTR SpiceOrder 20 +PIN -192 32 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 21 +PIN 192 -48 RIGHT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 22 +PIN 192 32 RIGHT 8 +PINATTR PinName LED2 +PINATTR SpiceOrder 23 +PIN 192 112 RIGHT 8 +PINATTR PinName LED3 +PINATTR SpiceOrder 24 +PIN -192 352 LEFT 8 +PINATTR PinName Tset +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT3597.asy b/spice/copy/sym/PowerProducts/LT3597.asy new file mode 100755 index 0000000..bad520f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3597.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -304 192 272 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -135 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LT3597 +SYMATTR Prefix X +SYMATTR SpiceModel LT3597.sub +SYMATTR Value2 LT3597 +SYMATTR Description 60V Step-Down LED Driver\n\nNotes:\n 1. Only one channel modeled.\n 2. Open LED logic and Fault is not modeled. +PIN -192 80 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN 192 -80 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 2 +PIN -80 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 192 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -192 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 5 +PIN 192 160 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -192 -160 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 7 +PIN 192 240 RIGHT 8 +PINATTR PinName Iset1 +PINATTR SpiceOrder 8 +PIN 192 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 0 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN 64 -304 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 15 +PIN 192 -240 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 +PIN -192 -80 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 18 +PIN -192 240 LEFT 8 +PINATTR PinName CTRLM +PINATTR SpiceOrder 20 +PIN -192 0 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 21 +PIN 192 0 RIGHT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 22 +PIN -192 160 LEFT 8 +PINATTR PinName Tset +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT3598.asy b/spice/copy/sym/PowerProducts/LT3598.asy new file mode 100755 index 0000000..230fc1d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3598.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -368 192 320 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 152 Center 2 +SYMATTR Value LT3598 +SYMATTR Prefix X +SYMATTR SpiceModel LT3598.sub +SYMATTR Value2 LT3598 +SYMATTR Description 6-String 30mA LED Driver with 1.5% Current Matching\n\nNote: Open LED logic and LED disable is not modeled. +PIN 192 -128 RIGHT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 1 +PIN 192 -48 RIGHT 8 +PINATTR PinName LED2 +PINATTR SpiceOrder 2 +PIN 192 32 RIGHT 8 +PINATTR PinName LED3 +PINATTR SpiceOrder 3 +PIN 192 112 RIGHT 8 +PINATTR PinName LED4 +PINATTR SpiceOrder 4 +PIN 192 192 RIGHT 8 +PINATTR PinName LED5 +PINATTR SpiceOrder 5 +PIN 192 272 RIGHT 8 +PINATTR PinName LED6 +PINATTR SpiceOrder 6 +PIN -192 192 LEFT 8 +PINATTR PinName Iset +PINATTR SpiceOrder 8 +PIN -192 32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 9 +PIN -192 272 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 +PIN 192 -208 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN -192 112 LEFT 8 +PINATTR PinName Tset +PINATTR SpiceOrder 12 +PIN -192 -208 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 15 +PIN -192 -128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 16 +PIN -64 320 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 17 +PIN -192 -48 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 18 +PIN -192 -288 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 20 +PIN -144 -368 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 +PIN 0 -368 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 22 +PIN 144 -368 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 23 +PIN 192 -288 RIGHT 8 +PINATTR PinName Vo_sw +PINATTR SpiceOrder 24 +PIN 64 320 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT3599.asy b/spice/copy/sym/PowerProducts/LT3599.asy new file mode 100755 index 0000000..4a3266a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3599.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -368 192 320 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 152 Center 2 +SYMATTR Value LT3599 +SYMATTR Prefix X +SYMATTR SpiceModel LT3599.sub +SYMATTR Value2 LT3599 +SYMATTR Description 4-Channel 120mA LED Driver with 1.5% Current Matching\n\nNote: Open/Shorted LED logic not modeled. +PIN 192 -128 RIGHT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 1 +PIN 192 -48 RIGHT 8 +PINATTR PinName LED2 +PINATTR SpiceOrder 2 +PIN 192 32 RIGHT 8 +PINATTR PinName LED3 +PINATTR SpiceOrder 3 +PIN 192 112 RIGHT 8 +PINATTR PinName LED4 +PINATTR SpiceOrder 4 +PIN 192 192 RIGHT 8 +PINATTR PinName Disable4 +PINATTR SpiceOrder 5 +PIN -192 192 LEFT 8 +PINATTR PinName Iset +PINATTR SpiceOrder 8 +PIN -192 32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 9 +PIN 192 272 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 +PIN 192 -208 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN -192 112 LEFT 8 +PINATTR PinName Tset +PINATTR SpiceOrder 12 +PIN -192 -208 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 15 +PIN -192 -128 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 16 +PIN -192 272 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 17 +PIN -192 -48 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 18 +PIN -192 -288 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 20 +PIN -144 -368 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 +PIN 0 -368 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 22 +PIN 144 -368 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 23 +PIN 192 -288 RIGHT 8 +PINATTR PinName Vo_sw +PINATTR SpiceOrder 24 +PIN 0 320 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT3640.asy b/spice/copy/sym/PowerProducts/LT3640.asy new file mode 100755 index 0000000..6cdb2f3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3640.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 192 448 -192 -448 +TEXT 0 0 Center 2 LT +WINDOW 3 0 144 Center 2 +WINDOW 0 0 -144 Center 2 +SYMATTR Value LT3640 +SYMATTR Prefix X +SYMATTR SpiceModel LT3640.sub +SYMATTR Value2 LT3640 +SYMATTR Description Dual Monalithic Buck Regulator with Power-On Reset and Watchdog Timer +PIN -96 448 BOTTOM 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 2 +PIN 192 0 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 384 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -192 -96 LEFT 8 +PINATTR PinName _RST2 +PINATTR SpiceOrder 5 +PIN -192 -192 LEFT 8 +PINATTR PinName _RST1 +PINATTR SpiceOrder 6 +PIN -192 0 LEFT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 7 +PIN -192 192 LEFT 8 +PINATTR PinName CWDT +PINATTR SpiceOrder 8 +PIN -192 288 LEFT 8 +PINATTR PinName CPOR +PINATTR SpiceOrder 9 +PIN -192 -288 LEFT 8 +PINATTR PinName _WDE +PINATTR SpiceOrder 10 +PIN -192 96 LEFT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 11 +PIN 0 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 +PIN 192 -96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 15 +PIN 192 -192 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 16 +PIN 192 -288 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 17 +PIN 192 -384 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 18 +PIN 64 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 19 +PIN 192 96 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 21 +PIN 192 288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 22 +PIN 192 192 RIGHT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 24 +PIN 96 448 BOTTOM 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 25 +PIN 192 384 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 26 +PIN -192 -384 LEFT 8 +PINATTR PinName _PGOOD +PINATTR SpiceOrder 27 +PIN -64 -448 TOP 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3641.asy b/spice/copy/sym/PowerProducts/LT3641.asy new file mode 100755 index 0000000..0dda3b8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3641.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 192 448 -192 -448 +TEXT 0 0 Center 2 LT +WINDOW 3 0 144 Center 2 +WINDOW 0 0 -144 Center 2 +SYMATTR Value LT3641 +SYMATTR Prefix X +SYMATTR SpiceModel LT3641.sub +SYMATTR Value2 LT3641 +SYMATTR Description Dual Monalithic Buck Regulator with Power-On Reset and Watchdog Timer +PIN -96 448 BOTTOM 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 2 +PIN 192 0 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 384 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -192 -96 LEFT 8 +PINATTR PinName _RST2 +PINATTR SpiceOrder 5 +PIN -192 -192 LEFT 8 +PINATTR PinName _RST1 +PINATTR SpiceOrder 6 +PIN -192 0 LEFT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 7 +PIN -192 192 LEFT 8 +PINATTR PinName CWDT +PINATTR SpiceOrder 8 +PIN -192 288 LEFT 8 +PINATTR PinName CPOR +PINATTR SpiceOrder 9 +PIN -192 -288 LEFT 8 +PINATTR PinName _WDE +PINATTR SpiceOrder 10 +PIN -192 96 LEFT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 11 +PIN 0 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 +PIN 192 -96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 15 +PIN 192 -192 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 16 +PIN 192 -288 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 17 +PIN 192 -384 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 18 +PIN 64 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 19 +PIN 192 96 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 21 +PIN 192 288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 22 +PIN 192 192 RIGHT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 24 +PIN 96 448 BOTTOM 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 25 +PIN 192 384 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 26 +PIN -192 -384 LEFT 8 +PINATTR PinName _PGOOD2 +PINATTR SpiceOrder 27 +PIN -64 -448 TOP 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3645.asy b/spice/copy/sym/PowerProducts/LT3645.asy new file mode 100755 index 0000000..6eac02f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3645.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -272 160 272 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -167 Center 2 +WINDOW 3 0 168 Center 2 +SYMATTR Value LT3645 +SYMATTR Prefix X +SYMATTR SpiceModel LT3645.sub +SYMATTR Value2 LT3645 +SYMATTR Description 36V 500mA Step-Down Regulator and 200mA LDO +PIN -160 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 160 112 RIGHT 8 +PINATTR PinName Vcc2 +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 -112 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 4 +PIN 0 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 -112 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 6 +PIN 0 -272 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 160 -224 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN -160 224 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN 160 224 RIGHT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 10 +PIN -160 112 LEFT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 11 +PIN -160 0 LEFT 8 +PINATTR PinName NPG +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3650-4.1.asy b/spice/copy/sym/PowerProducts/LT3650-4.1.asy new file mode 100755 index 0000000..fc42361 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3650-4.1.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT3650-4.1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3650-4.1.sub +SYMATTR Value2 LT3650-4.1 +SYMATTR Description High Voltage 2A Monolithic Li-Ion Battery Charger +PIN -144 -240 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName CLP +PINATTR SpiceOrder 2 +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN -144 144 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 240 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 11 +PIN 144 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3650-4.2.asy b/spice/copy/sym/PowerProducts/LT3650-4.2.asy new file mode 100755 index 0000000..49f8725 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3650-4.2.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT3650-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3650-4.2.sub +SYMATTR Value2 LT3650-4.2 +SYMATTR Description High Voltage 2A Monolithic Li-Ion Battery Charger +PIN -144 -240 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName CLP +PINATTR SpiceOrder 2 +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN -144 144 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 240 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 11 +PIN 144 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3650-8.2.asy b/spice/copy/sym/PowerProducts/LT3650-8.2.asy new file mode 100755 index 0000000..7781c88 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3650-8.2.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT3650-8.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3650-8.2.sub +SYMATTR Value2 LT3650-8.2 +SYMATTR Description High Voltage 2Amp Monolithic 2-Cell Li-Ion Battery Charger +PIN -144 -240 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName CLP +PINATTR SpiceOrder 2 +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN -144 144 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 240 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 11 +PIN 144 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3650-8.4.asy b/spice/copy/sym/PowerProducts/LT3650-8.4.asy new file mode 100755 index 0000000..9db1015 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3650-8.4.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT3650-8.4 +SYMATTR Prefix X +SYMATTR SpiceModel LT3650-8.4.sub +SYMATTR Value2 LT3650-8.4 +SYMATTR Description High Voltage 2Amp Monolithic 2-Cell Li-Ion Battery Charger +PIN -144 -240 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName CLP +PINATTR SpiceOrder 2 +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN -144 144 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 240 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 11 +PIN 144 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3651-4.1.asy b/spice/copy/sym/PowerProducts/LT3651-4.1.asy new file mode 100755 index 0000000..e235d3b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3651-4.1.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -351 160 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3651-4.1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3651-4.1.sub +SYMATTR Value2 LT3651-4.1 +SYMATTR Description Monolithic 4A High Voltage 1-Cell Li-Ion Battery Charger +PIN 160 192 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 1 +PIN -160 -192 LEFT 8 +PINATTR PinName _ACPR +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 4 +PIN 160 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 5 +PIN 0 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN -160 288 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 8 +PIN -160 0 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 9 +PIN -160 -96 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 10 +PIN -160 -288 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN -160 96 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 12 +PIN -48 -352 TOP 8 +PINATTR PinName CLP +PINATTR SpiceOrder 13 +PIN 48 -352 TOP 8 +PINATTR PinName CLN +PINATTR SpiceOrder 14 +PIN 160 -288 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 160 288 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 16 +PIN -160 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3651-4.2.asy b/spice/copy/sym/PowerProducts/LT3651-4.2.asy new file mode 100755 index 0000000..a8b92e5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3651-4.2.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -351 160 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3651-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3651-4.2.sub +SYMATTR Value2 LT3651-4.2 +SYMATTR Description Monolithic 4A High Voltage 1-Cell Li-Ion Battery Charger +PIN 160 192 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 1 +PIN -160 -192 LEFT 8 +PINATTR PinName _ACPR +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 4 +PIN 160 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 5 +PIN 0 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN -160 288 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 8 +PIN -160 0 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 9 +PIN -160 -96 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 10 +PIN -160 -288 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN -160 96 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 12 +PIN -48 -352 TOP 8 +PINATTR PinName CLP +PINATTR SpiceOrder 13 +PIN 48 -352 TOP 8 +PINATTR PinName CLN +PINATTR SpiceOrder 14 +PIN 160 -288 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 160 288 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 16 +PIN -160 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3651-8.2.asy b/spice/copy/sym/PowerProducts/LT3651-8.2.asy new file mode 100755 index 0000000..7cabdd4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3651-8.2.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -351 160 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3651-8.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3651-8.2.sub +SYMATTR Value2 LT3651-8.2 +SYMATTR Description Monolithic 4A High Voltage 2-Cell Li-Ion Battery Charger +PIN 160 192 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 1 +PIN -160 -192 LEFT 8 +PINATTR PinName _ACPR +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 4 +PIN 160 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 5 +PIN 0 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN -160 288 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 8 +PIN -160 0 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 9 +PIN -160 -96 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 10 +PIN -160 -288 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN -160 96 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 12 +PIN -48 -352 TOP 8 +PINATTR PinName CLP +PINATTR SpiceOrder 13 +PIN 48 -352 TOP 8 +PINATTR PinName CLN +PINATTR SpiceOrder 14 +PIN 160 -288 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 160 288 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 16 +PIN -160 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3651-8.4.asy b/spice/copy/sym/PowerProducts/LT3651-8.4.asy new file mode 100755 index 0000000..ee0c79a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3651-8.4.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -351 160 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3651-8.4 +SYMATTR Prefix X +SYMATTR SpiceModel LT3651-8.4.sub +SYMATTR Value2 LT3651-8.4 +SYMATTR Description Monolithic 4A High Voltage 2-Cell Li-Ion Battery Charger +PIN 160 192 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 1 +PIN -160 -192 LEFT 8 +PINATTR PinName _ACPR +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 3 +PIN 160 0 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 4 +PIN 160 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 5 +PIN 0 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN -160 288 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 8 +PIN -160 0 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 9 +PIN -160 -96 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 10 +PIN -160 -288 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 11 +PIN -160 96 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 12 +PIN -48 -352 TOP 8 +PINATTR PinName CLP +PINATTR SpiceOrder 13 +PIN 48 -352 TOP 8 +PINATTR PinName CLN +PINATTR SpiceOrder 14 +PIN 160 -288 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 160 288 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 16 +PIN -160 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3652.asy b/spice/copy/sym/PowerProducts/LT3652.asy new file mode 100755 index 0000000..01a2eab --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3652.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT3652 +SYMATTR Prefix X +SYMATTR SpiceModel LT3652.sub +SYMATTR Value2 LT3652 +SYMATTR Description Power Tracking 2A Battery Charger for Solar Power +PIN -144 -240 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName Vin_reg +PINATTR SpiceOrder 2 +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN -144 144 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 240 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 11 +PIN 144 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3652HV.asy b/spice/copy/sym/PowerProducts/LT3652HV.asy new file mode 100755 index 0000000..d4c84f2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3652HV.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT3652HV +SYMATTR Prefix X +SYMATTR SpiceModel LT3652.sub +SYMATTR Value2 LT3652 +SYMATTR Description Power Tracking 2A Battery Charger +PIN -144 -240 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName Vin_reg +PINATTR SpiceOrder 2 +PIN -144 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN -144 144 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 240 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 11 +PIN 144 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3663-3.3.asy b/spice/copy/sym/PowerProducts/LT3663-3.3.asy new file mode 100755 index 0000000..86fed0a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3663-3.3.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -208 128 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -103 Center 2 +WINDOW 3 0 104 Center 2 +SYMATTR Value LT3663-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3663-x.sub +SYMATTR Value2 LT3663-x x=27.8K +SYMATTR Description 1.2A Step-Down Switching Regulator with Output Current Limit +PIN -128 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 -48 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 2 +PIN 128 160 RIGHT 8 +PINATTR PinName Vouts +PINATTR SpiceOrder 3 +PIN -128 160 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 4 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 6 +PIN 0 -208 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 128 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3663-5.asy b/spice/copy/sym/PowerProducts/LT3663-5.asy new file mode 100755 index 0000000..8a32f05 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3663-5.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -208 128 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -103 Center 2 +WINDOW 3 0 104 Center 2 +SYMATTR Value LT3663-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3663-x.sub +SYMATTR Value2 LT3663-x x=46.7K +SYMATTR Description 1.2A Step-Down Switching Regulator with Output Current Limit +PIN -128 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 -48 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 2 +PIN 128 160 RIGHT 8 +PINATTR PinName Vouts +PINATTR SpiceOrder 3 +PIN -128 160 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 4 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 6 +PIN 0 -208 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 128 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3663.asy b/spice/copy/sym/PowerProducts/LT3663.asy new file mode 100755 index 0000000..2eda092 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3663.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -208 128 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -103 Center 2 +WINDOW 3 0 104 Center 2 +SYMATTR Value LT3663 +SYMATTR Prefix X +SYMATTR SpiceModel LT3663.sub +SYMATTR Value2 LT3663 +SYMATTR Description 1.2A Step-Down Switching Regulator with Output Current Limit +PIN -128 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 -48 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 2 +PIN 128 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -128 160 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 4 +PIN 128 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 6 +PIN 0 -208 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 128 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT3667.asy b/spice/copy/sym/PowerProducts/LT3667.asy new file mode 100755 index 0000000..6dac36a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3667.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -400 240 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LT3667 +SYMATTR Prefix X +SYMATTR SpiceModel LT3667.sub +SYMATTR Value2 LT3667 +SYMATTR Description 40V, 400mA Step-Down Switching Regulator with Dual Fault Protection LDOs +PIN 240 -336 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -96 -400 TOP 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -224 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 96 -400 TOP 8 +PINATTR PinName BD +PINATTR SpiceOrder 5 +PIN 240 144 RIGHT 8 +PINATTR PinName IN3 +PINATTR SpiceOrder 6 +PIN 240 240 RIGHT 8 +PINATTR PinName OUT3 +PINATTR SpiceOrder 7 +PIN 240 336 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 8 +PIN -224 -144 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 9 +PIN 240 -48 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 10 +PIN -224 -48 LEFT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 11 +PIN -224 48 LEFT 8 +PINATTR PinName PG3 +PINATTR SpiceOrder 12 +PIN -224 336 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 13 +PIN -224 240 LEFT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 14 +PIN 240 48 RIGHT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 15 +PIN -96 400 BOTTOM 8 +PINATTR PinName EN2/ILim2 +PINATTR SpiceOrder 16 +PIN 96 400 BOTTOM 8 +PINATTR PinName EN3/ILim3 +PINATTR SpiceOrder 17 +PIN -224 -240 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 18 +PIN -224 -336 LEFT 8 +PINATTR PinName UVLO1 +PINATTR SpiceOrder 19 +PIN 0 -400 TOP 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 20 +PIN 240 -144 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 23 +PIN 240 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 24 +PIN 0 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT3668.asy b/spice/copy/sym/PowerProducts/LT3668.asy new file mode 100755 index 0000000..570fe51 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3668.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -400 240 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LT3668 +SYMATTR Prefix X +SYMATTR SpiceModel LT3668.sub +SYMATTR Value2 LT3668 +SYMATTR Description 40V, 400mA Step-Down Switching Regulator with Dual Fault Protected Tracking LDOs +PIN 240 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 240 -336 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN -224 -240 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -224 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 240 144 RIGHT 8 +PINATTR PinName IN3/BD +PINATTR SpiceOrder 5 +PIN 240 240 RIGHT 8 +PINATTR PinName OUT3 +PINATTR SpiceOrder 6 +PIN 240 336 RIGHT 8 +PINATTR PinName ADJ3 +PINATTR SpiceOrder 7 +PIN 240 -48 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 8 +PIN -224 336 LEFT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 9 +PIN -224 240 LEFT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 10 +PIN 240 48 RIGHT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 11 +PIN -96 400 BOTTOM 8 +PINATTR PinName EN2/ILim2 +PINATTR SpiceOrder 12 +PIN 96 400 BOTTOM 8 +PINATTR PinName EN3/ILim3 +PINATTR SpiceOrder 13 +PIN -224 -144 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 14 +PIN -224 -336 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 15 +PIN 240 -144 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 16 +PIN -224 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3680.asy b/spice/copy/sym/PowerProducts/LT3680.asy new file mode 100755 index 0000000..f59b9f5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3680.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT3680 +SYMATTR Prefix X +SYMATTR SpiceModel LT3680.sub +SYMATTR Value2 LT3680 +SYMATTR Description 38V, 3.5A, 2.4MHz Step-Down Switching Regulator with 75µA Quiescent Current +PIN 160 -128 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3681.asy b/spice/copy/sym/PowerProducts/LT3681.asy new file mode 100755 index 0000000..5e53f4b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3681.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 176 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT3681 +SYMATTR Prefix X +SYMATTR SpiceModel LT3681.sub +SYMATTR Value2 LT3681 +SYMATTR Description 36V, 2A, 2.8MHz Step-Down Switching Regulator with Integrated Power Schottky Diode +PIN 0 -192 TOP 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 -128 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -96 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 6 +PIN 96 -192 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN -48 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 160 32 RIGHT 8 +PINATTR PinName DC +PINATTR SpiceOrder 12 +PIN 48 176 BOTTOM 8 +PINATTR PinName DA +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3682.asy b/spice/copy/sym/PowerProducts/LT3682.asy new file mode 100755 index 0000000..32dc127 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3682.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -208 128 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3682 +SYMATTR Prefix X +SYMATTR SpiceModel LT3682.sub +SYMATTR Value2 LT3682 +SYMATTR Description 1A µPower Step-Down Switching Regulator\n\nNote: SYNC is not modeled, and Burst Mode is always chosen +PIN -128 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 128 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 48 -208 TOP 8 +PINATTR PinName BD +PINATTR SpiceOrder 5 +PIN 128 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 7 +PIN 128 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN -128 -144 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 9 +PIN -128 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN -48 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3684.asy b/spice/copy/sym/PowerProducts/LT3684.asy new file mode 100755 index 0000000..6e8c2b3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3684.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT3684 +SYMATTR Prefix X +SYMATTR SpiceModel LT3684.sub +SYMATTR Value2 LT3684 +SYMATTR Description 36V, 2A, 2.8MHz Step-Down Switching Regulator +PIN 64 -192 TOP 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -64 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 6 +PIN 160 -128 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3685.asy b/spice/copy/sym/PowerProducts/LT3685.asy new file mode 100755 index 0000000..3de8c65 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3685.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT3685 +SYMATTR Prefix X +SYMATTR SpiceModel LT3685.sub +SYMATTR Value2 LT3685 +SYMATTR Description 38V, 2A, 2.4MHz Step-Down Switching Regulator +PIN 160 -128 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3686.asy b/spice/copy/sym/PowerProducts/LT3686.asy new file mode 100755 index 0000000..e2ad759 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3686.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -224 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3686 +SYMATTR Prefix X +SYMATTR SpiceModel LT3686.sub +SYMATTR Value2 LT3686 +SYMATTR Description 37V, 1.2A Step-Down Regulator in a 3mm × 3mm DFN +PIN -144 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 144 -192 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 2 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 192 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -144 -96 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 8 +PIN 144 96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3686A.asy b/spice/copy/sym/PowerProducts/LT3686A.asy new file mode 100755 index 0000000..5f09251 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3686A.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -224 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3686A +SYMATTR Prefix X +SYMATTR SpiceModel LT3686A.sub +SYMATTR Value2 LT3686A +SYMATTR Description 37V, 1.2A Step-Down Regulator in a 3mm × 3mm DFN +PIN -144 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 144 -192 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 2 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 192 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -144 -96 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName Mode/Sync +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 8 +PIN 144 96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3688.asy b/spice/copy/sym/PowerProducts/LT3688.asy new file mode 100755 index 0000000..edf05f1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3688.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -368 160 416 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3688 +SYMATTR Prefix X +SYMATTR SpiceModel LT3688.sub +SYMATTR Value2 LT3688 +SYMATTR Description Dual 800mA Step-Down Regulator with Power-On Reset and Watchdog Timer\n\nNote: Only one of two channels modeled. +PIN -160 160 LEFT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 1 +PIN 160 272 RIGHT 8 +PINATTR PinName Cwdt +PINATTR SpiceOrder 2 +PIN 160 160 RIGHT 8 +PINATTR PinName Cpor +PINATTR SpiceOrder 3 +PIN 160 384 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -160 384 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN 160 -336 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN 160 -240 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN -160 -336 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 160 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 160 -48 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 10 +PIN -160 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 11 +PIN 160 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 -48 LEFT 8 +PINATTR PinName _WDE +PINATTR SpiceOrder 13 +PIN -160 -144 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN -160 48 LEFT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 15 +PIN -160 272 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 16 +PIN 0 416 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3689-5.asy b/spice/copy/sym/PowerProducts/LT3689-5.asy new file mode 100755 index 0000000..5ff28ce --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3689-5.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -368 160 416 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3689-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3689-5.sub +SYMATTR Value2 LT3689-5 +SYMATTR Description 700mA Step-Down Regulator with Power-On Reset and Watchdog Timer +PIN -160 160 LEFT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 1 +PIN 160 272 RIGHT 8 +PINATTR PinName Cwdt +PINATTR SpiceOrder 2 +PIN 160 160 RIGHT 8 +PINATTR PinName Cpor +PINATTR SpiceOrder 3 +PIN 160 384 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -160 384 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN 160 -336 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 160 -240 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN -160 -336 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 160 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 160 -48 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 10 +PIN -160 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 11 +PIN 160 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 -48 LEFT 8 +PINATTR PinName _WDE +PINATTR SpiceOrder 13 +PIN -160 -144 LEFT 8 +PINATTR PinName _W/T +PINATTR SpiceOrder 14 +PIN -160 48 LEFT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 15 +PIN -160 272 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 16 +PIN 0 416 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3689.asy b/spice/copy/sym/PowerProducts/LT3689.asy new file mode 100755 index 0000000..3b8b4be --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3689.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -368 160 416 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3689 +SYMATTR Prefix X +SYMATTR SpiceModel LT3689.sub +SYMATTR Value2 LT3689 +SYMATTR Description 700mA Step-Down Regulator with Power-On Reset and Watchdog Timer +PIN -160 160 LEFT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 1 +PIN 160 272 RIGHT 8 +PINATTR PinName Cwdt +PINATTR SpiceOrder 2 +PIN 160 160 RIGHT 8 +PINATTR PinName Cpor +PINATTR SpiceOrder 3 +PIN 160 384 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -160 384 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN 160 -336 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 6 +PIN 160 -240 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN -160 -336 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 160 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 160 -48 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 10 +PIN -160 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 11 +PIN 160 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 -48 LEFT 8 +PINATTR PinName _WDE +PINATTR SpiceOrder 13 +PIN -160 -144 LEFT 8 +PINATTR PinName _W/T +PINATTR SpiceOrder 14 +PIN -160 48 LEFT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 15 +PIN -160 272 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 16 +PIN 0 416 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3690.asy b/spice/copy/sym/PowerProducts/LT3690.asy new file mode 100755 index 0000000..077fa68 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3690.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -240 160 336 +TEXT 0 56 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 0 136 Center 2 +SYMATTR Value LT3690 +SYMATTR Prefix X +SYMATTR SpiceModel LT3690.sub +SYMATTR Value2 LT3690 +SYMATTR Description 36V, 4A, 1.5MHz Step-Down Switching Regulator with 70µA Quiescent Current +PIN 160 -96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN 160 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -160 -96 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 6 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 160 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 288 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 160 288 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN -160 0 LEFT 8 +PINATTR PinName VccINT +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3692.asy b/spice/copy/sym/PowerProducts/LT3692.asy new file mode 100755 index 0000000..4ca2f33 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3692.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -544 208 544 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT3692 +SYMATTR Prefix X +SYMATTR SpiceModel LT3692.sub +SYMATTR Value2 LT3692 +SYMATTR Description Monolithic Dual Tracking 3.5A Step-Down Switching Regulator +PIN 208 -384 RIGHT 8 +PINATTR PinName Bst1 +PINATTR SpiceOrder 1 +PIN 208 192 RIGHT 8 +PINATTR PinName CMPO1 +PINATTR SpiceOrder 2 +PIN 208 96 RIGHT 8 +PINATTR PinName CMPI1 +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN -208 0 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN -208 96 LEFT 8 +PINATTR PinName CMPI2 +PINATTR SpiceOrder 6 +PIN -208 192 LEFT 8 +PINATTR PinName CMPO2 +PINATTR SpiceOrder 7 +PIN -208 -384 LEFT 8 +PINATTR PinName Bst2 +PINATTR SpiceOrder 8 +PIN -208 -96 LEFT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 9 +PIN -208 -192 LEFT 8 +PINATTR PinName IND2 +PINATTR SpiceOrder 11 +PIN -208 -288 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 13 +PIN -96 -544 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 14 +PIN -208 -480 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 15 +PIN -208 384 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 16 +PIN -208 480 LEFT 8 +PINATTR PinName Ilim2 +PINATTR SpiceOrder 17 +PIN -208 288 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 18 +PIN 96 544 BOTTOM 8 +PINATTR PinName DIV +PINATTR SpiceOrder 19 +PIN 0 -544 TOP 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 21 +PIN -96 544 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 22 +PIN 208 288 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 23 +PIN 208 480 RIGHT 8 +PINATTR PinName Ilim1 +PINATTR SpiceOrder 24 +PIN 208 384 RIGHT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 25 +PIN 208 -480 RIGHT 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 26 +PIN 96 -544 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 27 +PIN 208 -288 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 28 +PIN 208 -192 RIGHT 8 +PINATTR PinName IND1 +PINATTR SpiceOrder 30 +PIN 208 -96 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 32 +PIN 0 544 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 33 diff --git a/spice/copy/sym/PowerProducts/LT3692A.asy b/spice/copy/sym/PowerProducts/LT3692A.asy new file mode 100755 index 0000000..2bdcbcc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3692A.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -544 208 544 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT3692A +SYMATTR Prefix X +SYMATTR SpiceModel LT3692A.sub +SYMATTR Value2 LT3692A +SYMATTR Description Monolithic Dual Tracking 3.5A Step-Down Switching Regulator +PIN 208 -384 RIGHT 8 +PINATTR PinName Bst1 +PINATTR SpiceOrder 1 +PIN 208 192 RIGHT 8 +PINATTR PinName CMPO1 +PINATTR SpiceOrder 2 +PIN 208 96 RIGHT 8 +PINATTR PinName CMPI1 +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN -208 0 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN -208 96 LEFT 8 +PINATTR PinName CMPI2 +PINATTR SpiceOrder 6 +PIN -208 192 LEFT 8 +PINATTR PinName CMPO2 +PINATTR SpiceOrder 7 +PIN -208 -384 LEFT 8 +PINATTR PinName Bst2 +PINATTR SpiceOrder 8 +PIN -208 -96 LEFT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 9 +PIN -208 -192 LEFT 8 +PINATTR PinName IND2 +PINATTR SpiceOrder 11 +PIN -208 -288 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 13 +PIN -96 -544 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 14 +PIN -208 -480 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 15 +PIN -208 288 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 16 +PIN -208 480 LEFT 8 +PINATTR PinName Ilim2 +PINATTR SpiceOrder 17 +PIN -208 384 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 18 +PIN 96 544 BOTTOM 8 +PINATTR PinName DIV +PINATTR SpiceOrder 19 +PIN 0 -544 TOP 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 21 +PIN -96 544 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 22 +PIN 208 384 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 23 +PIN 208 480 RIGHT 8 +PINATTR PinName Ilim1 +PINATTR SpiceOrder 24 +PIN 208 288 RIGHT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 25 +PIN 208 -480 RIGHT 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 26 +PIN 96 -544 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 27 +PIN 208 -288 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 28 +PIN 208 -192 RIGHT 8 +PINATTR PinName IND1 +PINATTR SpiceOrder 30 +PIN 208 -96 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 32 +PIN 0 544 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 33 diff --git a/spice/copy/sym/PowerProducts/LT3693.asy b/spice/copy/sym/PowerProducts/LT3693.asy new file mode 100755 index 0000000..e5bb276 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3693.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT3693 +SYMATTR Prefix X +SYMATTR SpiceModel LT3693.sub +SYMATTR Value2 LT3693 +SYMATTR Description 38V, 3.5A, 2.4MHz Step-Down Switching Regulator +PIN 160 -128 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3694-1.asy b/spice/copy/sym/PowerProducts/LT3694-1.asy new file mode 100755 index 0000000..6bf889b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3694-1.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -416 240 368 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3694-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3694-1.sub +SYMATTR Value2 LT3694-1 +SYMATTR Description 36V, 2.6A Fault Monolithic Buck Regulator with Dual LDO +PIN 0 -416 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -224 -384 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 2 +PIN -224 -192 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 3 +PIN -224 -288 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 4 +PIN -224 -96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -160 368 BOTTOM 8 +PINATTR PinName TRK/SS1 +PINATTR SpiceOrder 6 +PIN -48 368 BOTTOM 8 +PINATTR PinName TRK/SS2 +PINATTR SpiceOrder 7 +PIN -224 288 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 8 +PIN -224 192 LEFT 8 +PINATTR PinName Drv2 +PINATTR SpiceOrder 9 +PIN -224 96 LEFT 8 +PINATTR PinName Lim2 +PINATTR SpiceOrder 10 +PIN 240 96 RIGHT 8 +PINATTR PinName Lim3 +PINATTR SpiceOrder 11 +PIN 240 192 RIGHT 8 +PINATTR PinName Drv3 +PINATTR SpiceOrder 12 +PIN 240 288 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 13 +PIN 64 368 BOTTOM 8 +PINATTR PinName TRK/SS3 +PINATTR SpiceOrder 14 +PIN 240 0 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 15 +PIN -224 0 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 16 +PIN 240 -384 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 17 +PIN 240 -288 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 18 +PIN 240 -96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 19 +PIN 240 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 20 +PIN 176 368 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT3694.asy b/spice/copy/sym/PowerProducts/LT3694.asy new file mode 100755 index 0000000..416a2cc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3694.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -416 240 368 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3694 +SYMATTR Prefix X +SYMATTR SpiceModel LT3694.sub +SYMATTR Value2 LT3694 +SYMATTR Description 36V, 2.6A Fault Monolithic Buck Regulator with Dual LDO +PIN 0 -416 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -224 -384 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 2 +PIN -224 -192 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 3 +PIN -224 -288 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 4 +PIN -224 -96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -160 368 BOTTOM 8 +PINATTR PinName TRK/SS1 +PINATTR SpiceOrder 6 +PIN -48 368 BOTTOM 8 +PINATTR PinName TRK/SS2 +PINATTR SpiceOrder 7 +PIN -224 288 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 8 +PIN -224 192 LEFT 8 +PINATTR PinName Drv2 +PINATTR SpiceOrder 9 +PIN -224 96 LEFT 8 +PINATTR PinName Lim2 +PINATTR SpiceOrder 10 +PIN 240 96 RIGHT 8 +PINATTR PinName Lim3 +PINATTR SpiceOrder 11 +PIN 240 192 RIGHT 8 +PINATTR PinName Drv3 +PINATTR SpiceOrder 12 +PIN 240 288 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 13 +PIN 64 368 BOTTOM 8 +PINATTR PinName TRK/SS3 +PINATTR SpiceOrder 14 +PIN 240 0 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 15 +PIN -224 0 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 16 +PIN 240 -384 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 17 +PIN 240 -288 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 18 +PIN 240 -96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 19 +PIN 240 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 20 +PIN 176 368 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT3695-3.3.asy b/spice/copy/sym/PowerProducts/LT3695-3.3.asy new file mode 100755 index 0000000..1e91df8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3695-3.3.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -224 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3695-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3695-x.sub +SYMATTR Value2 LT3695-x R=313.3K +SYMATTR Description 1A Fault Tolerant µPower Step-Down Regulator, Fixed 3.3V Output +PIN 48 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 144 96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 7 +PIN 0 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -144 192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 13 +PIN -48 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN 144 -192 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 15 +PIN 144 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3695-5.asy b/spice/copy/sym/PowerProducts/LT3695-5.asy new file mode 100755 index 0000000..95fc269 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3695-5.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -224 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3695-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3695-x.sub +SYMATTR Value2 LT3695-x R=526K +SYMATTR Description 1A Fault Tolerant µPower Step-Down Regulator, Fixed 5V Output +PIN 48 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 144 96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 7 +PIN 0 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -144 192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 13 +PIN -48 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN 144 -192 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 15 +PIN 144 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3695.asy b/spice/copy/sym/PowerProducts/LT3695.asy new file mode 100755 index 0000000..5606878 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3695.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -224 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3695 +SYMATTR Prefix X +SYMATTR SpiceModel LT3695.sub +SYMATTR Value2 LT3695 +SYMATTR Description 1A Fault Tolerant µPower Step-Down Regulator +PIN 48 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 144 96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 7 +PIN 0 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN -144 192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN -144 -192 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 13 +PIN -48 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN 144 -192 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 15 +PIN 144 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3697.asy b/spice/copy/sym/PowerProducts/LT3697.asy new file mode 100755 index 0000000..aab4fdd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3697.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -256 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT3697 +SYMATTR Prefix X +SYMATTR SpiceModel LT3697.sub +SYMATTR Value2 LT3697 +SYMATTR Description USB 5V 2.5A Output, 35V Input Buck with Cable Drop Compensation\n\nNote: Sync function is not modeled. +PIN 48 256 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN -48 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 13 +PIN 48 -256 TOP 8 +PINATTR PinName BST +PINATTR SpiceOrder 16 +PIN 144 -96 RIGHT 8 +PINATTR PinName SYS +PINATTR SpiceOrder 18 +PIN -144 -96 LEFT 8 +PINATTR PinName _FLT +PINATTR SpiceOrder 19 +PIN 144 192 RIGHT 8 +PINATTR PinName USB5V +PINATTR SpiceOrder 20 +PIN 144 0 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 21 +PIN 144 96 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 22 +PIN -144 192 LEFT 8 +PINATTR PinName RCBL +PINATTR SpiceOrder 23 +PIN -144 96 LEFT 8 +PINATTR PinName Rlim +PINATTR SpiceOrder 24 +PIN -48 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT3724.asy b/spice/copy/sym/PowerProducts/LT3724.asy new file mode 100755 index 0000000..c29e2e1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3724.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -240 160 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -73 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT3724 +SYMATTR Prefix X +SYMATTR SpiceModel LT3724.sub +SYMATTR Value2 LT3724 +SYMATTR Description High-Voltage Current Mode Switching Regulator Controller +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 -192 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -160 -112 LEFT 8 +PINATTR PinName Css +PINATTR SpiceOrder 4 +PIN -160 -32 LEFT 8 +PINATTR PinName Burst_EN +PINATTR SpiceOrder 5 +PIN -160 48 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -160 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN -160 208 LEFT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 160 208 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN 160 128 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 +PIN 160 48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 160 -32 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 15 +PIN 160 -112 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 +PIN 0 256 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3740.asy b/spice/copy/sym/PowerProducts/LT3740.asy new file mode 100755 index 0000000..bb9d142 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3740.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -224 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3740 +SYMATTR Prefix X +SYMATTR SpiceModel LT3740.sub +SYMATTR Value2 LT3740 +SYMATTR Description Wide Operating Range, Valley Mode, No Rsense Synchronous Step-Down Controller +PIN 144 192 RIGHT 8 +PINATTR PinName SN- +PINATTR SpiceOrder 1 +PIN 64 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 144 128 RIGHT 8 +PINATTR PinName Bgate +PINATTR SpiceOrder 3 +PIN 144 -192 RIGHT 8 +PINATTR PinName BGDP +PINATTR SpiceOrder 4 +PIN 144 64 RIGHT 8 +PINATTR PinName SN+ +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 144 -64 RIGHT 8 +PINATTR PinName Tgate +PINATTR SpiceOrder 7 +PIN 144 -128 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 8 +PIN -144 -192 LEFT 8 +PINATTR PinName SWB +PINATTR SpiceOrder 9 +PIN 0 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -144 0 LEFT 8 +PINATTR PinName Range +PINATTR SpiceOrder 11 +PIN -144 -64 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 12 +PIN -144 -128 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 13 +PIN -144 64 LEFT 8 +PINATTR PinName Xref +PINATTR SpiceOrder 14 +PIN -144 192 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 15 +PIN -144 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 16 +PIN -64 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3741.asy b/spice/copy/sym/PowerProducts/LT3741.asy new file mode 100755 index 0000000..4878cea --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3741.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -352 176 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3741 +SYMATTR Prefix X +SYMATTR SpiceModel LT3741.sub +SYMATTR Value2 LT3741 +SYMATTR Description High Power, Constant Current, Constant Voltage, Step-Down Controller +PIN 0 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -176 -288 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 2 +PIN -176 -192 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 6 +PIN -176 192 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 176 288 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN 176 96 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 11 +PIN 176 192 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 12 +PIN -176 288 LEFT 8 +PINATTR PinName VC +PINATTR SpiceOrder 14 +PIN -176 -96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN 176 -192 RIGHT 8 +PINATTR PinName HG +PINATTR SpiceOrder 23 +PIN 176 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 24 +PIN 176 -288 RIGHT 8 +PINATTR PinName CBOOT +PINATTR SpiceOrder 25 +PIN 176 0 RIGHT 8 +PINATTR PinName LG +PINATTR SpiceOrder 26 +PIN 64 -352 TOP 8 +PINATTR PinName Vcc_int +PINATTR SpiceOrder 27 +PIN -64 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3742.asy b/spice/copy/sym/PowerProducts/LT3742.asy new file mode 100755 index 0000000..024fa15 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3742.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -352 176 400 +TEXT 1 0 Center 2 LT +WINDOW 0 -4 -163 Center 2 +WINDOW 3 1 229 Center 2 +SYMATTR Value LT3742 +SYMATTR Prefix X +SYMATTR SpiceModel LT3742.sub +SYMATTR Value2 LT3742 +SYMATTR Description Dual, 2-Phase Step-Down Switching Controller +PIN -192 -208 LEFT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 1 +PIN -80 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -192 -288 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 3 +PIN 64 -352 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 4 +PIN 176 -288 RIGHT 8 +PINATTR PinName SWB +PINATTR SpiceOrder 5 +PIN 176 -208 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 6 +PIN 176 -128 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 7 +PIN 176 -48 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 10 +PIN 176 32 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 11 +PIN 176 112 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 12 +PIN 176 352 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 13 +PIN 176 192 RIGHT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 14 +PIN 176 272 RIGHT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 15 +PIN -192 272 LEFT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 16 +PIN -192 192 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 17 +PIN -192 352 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 18 +PIN -192 112 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 19 +PIN -192 32 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 20 +PIN -192 -48 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 21 +PIN -192 -128 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 24 +PIN 0 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT3743.asy b/spice/copy/sym/PowerProducts/LT3743.asy new file mode 100755 index 0000000..074699b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3743.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -448 224 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT3743 +SYMATTR Prefix X +SYMATTR SpiceModel LT3743.sub +SYMATTR Value2 LT3743 +SYMATTR Description High Current Synchronous Step-Down LED Driver with Three-State Control +PIN -224 384 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -224 -384 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 2 +PIN -128 -448 TOP 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -224 96 LEFT 8 +PINATTR PinName CTRL_T +PINATTR SpiceOrder 4 +PIN -224 -192 LEFT 8 +PINATTR PinName CTRL_H +PINATTR SpiceOrder 6 +PIN -224 -96 LEFT 8 +PINATTR PinName CTRL_L +PINATTR SpiceOrder 7 +PIN -224 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 224 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN 224 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 11 +PIN 224 96 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 12 +PIN -96 448 BOTTOM 8 +PINATTR PinName VCL +PINATTR SpiceOrder 13 +PIN 96 448 BOTTOM 8 +PINATTR PinName VCH +PINATTR SpiceOrder 14 +PIN -224 -288 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -224 192 LEFT 8 +PINATTR PinName CTRL_SEL +PINATTR SpiceOrder 17 +PIN -224 288 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 18 +PIN 224 384 RIGHT 8 +PINATTR PinName PWMGH +PINATTR SpiceOrder 19 +PIN 224 288 RIGHT 8 +PINATTR PinName PWMGL +PINATTR SpiceOrder 22 +PIN 224 -288 RIGHT 8 +PINATTR PinName HG +PINATTR SpiceOrder 23 +PIN 224 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 24 +PIN 224 -384 RIGHT 8 +PINATTR PinName CBOOT +PINATTR SpiceOrder 25 +PIN 224 -96 RIGHT 8 +PINATTR PinName LG +PINATTR SpiceOrder 26 +PIN 0 -448 TOP 8 +PINATTR PinName Vcc_int +PINATTR SpiceOrder 27 +PIN 128 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3744.asy b/spice/copy/sym/PowerProducts/LT3744.asy new file mode 100755 index 0000000..db22a11 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3744.asy @@ -0,0 +1,110 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -640 224 640 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT3744 +SYMATTR Prefix X +SYMATTR SpiceModel LT3744.sub +SYMATTR Value2 LT3744 +SYMATTR Description High Current Synchronous Step-Down LED Driver +PIN 48 -640 TOP 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN -224 -288 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 2 +PIN -144 -640 TOP 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -224 -384 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 4 +PIN -224 -480 LEFT 8 +PINATTR PinName CTRL3 +PINATTR SpiceOrder 5 +PIN -224 -576 LEFT 8 +PINATTR PinName CTRLT +PINATTR SpiceOrder 6 +PIN -224 0 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 7 +PIN -224 -96 LEFT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 8 +PIN -224 -192 LEFT 8 +PINATTR PinName PWM3 +PINATTR SpiceOrder 9 +PIN -224 96 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 10 +PIN -224 192 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 11 +PIN -224 288 LEFT 8 +PINATTR PinName SGND +PINATTR SpiceOrder 12 +PIN -224 384 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 13 +PIN -224 480 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN 224 96 RIGHT 8 +PINATTR PinName LED_ISN +PINATTR SpiceOrder 15 +PIN 224 0 RIGHT 8 +PINATTR PinName LED_ISP +PINATTR SpiceOrder 16 +PIN 224 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 17 +PIN 144 640 BOTTOM 8 +PINATTR PinName Vc3 +PINATTR SpiceOrder 18 +PIN 0 640 BOTTOM 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 19 +PIN -144 640 BOTTOM 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 20 +PIN 224 -96 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 21 +PIN 224 -192 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 22 +PIN 224 480 RIGHT 8 +PINATTR PinName PWM_OUT3 +PINATTR SpiceOrder 23 +PIN 224 576 RIGHT 8 +PINATTR PinName VFNEG +PINATTR SpiceOrder 24 +PIN 224 384 RIGHT 8 +PINATTR PinName PWM_OUT2 +PINATTR SpiceOrder 25 +PIN -224 576 LEFT 8 +PINATTR PinName VEE +PINATTR SpiceOrder 26 +PIN 224 288 RIGHT 8 +PINATTR PinName PWM_OUT1 +PINATTR SpiceOrder 27 +PIN 224 -480 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 29 +PIN 224 -384 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 30 +PIN 224 -576 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 31 +PIN 224 -288 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 32 +PIN 144 -640 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 34 +PIN -48 -640 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 36 diff --git a/spice/copy/sym/PowerProducts/LT3745.asy b/spice/copy/sym/PowerProducts/LT3745.asy new file mode 100755 index 0000000..c424bfb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3745.asy @@ -0,0 +1,200 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -640 -512 641 576 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 232 Center 2 +SYMATTR Value LT3745 +SYMATTR Prefix X +SYMATTR SpiceModel LT3745.sub +SYMATTR Value2 LT3745 +SYMATTR Description 16-Channel 50mA LED Driver with Buck Controller (Overtemperature not modeled) +PIN -208 -512 TOP 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 640 0 RIGHT 8 +PINATTR PinName LED7 +PINATTR SpiceOrder 2 +PIN 640 -64 RIGHT 8 +PINATTR PinName LED6 +PINATTR SpiceOrder 3 +PIN 640 -128 RIGHT 8 +PINATTR PinName LED5 +PINATTR SpiceOrder 4 +PIN 640 -192 RIGHT 8 +PINATTR PinName LED4 +PINATTR SpiceOrder 5 +PIN 640 -256 RIGHT 8 +PINATTR PinName LED3 +PINATTR SpiceOrder 6 +PIN 640 -320 RIGHT 8 +PINATTR PinName LED2 +PINATTR SpiceOrder 7 +PIN 640 -384 RIGHT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 8 +PIN 640 -448 RIGHT 8 +PINATTR PinName LED0 +PINATTR SpiceOrder 9 +PIN 560 576 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -80 -512 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN -512 -512 TOP 8 +PINATTR PinName PWMCK +PINATTR SpiceOrder 16 +PIN 640 512 RIGHT 8 +PINATTR PinName LED15 +PINATTR SpiceOrder 22 +PIN 640 448 RIGHT 8 +PINATTR PinName LED14 +PINATTR SpiceOrder 23 +PIN 640 384 RIGHT 8 +PINATTR PinName LED13 +PINATTR SpiceOrder 24 +PIN 640 320 RIGHT 8 +PINATTR PinName LED12 +PINATTR SpiceOrder 25 +PIN 640 256 RIGHT 8 +PINATTR PinName LED11 +PINATTR SpiceOrder 26 +PIN 640 192 RIGHT 8 +PINATTR PinName LED10 +PINATTR SpiceOrder 27 +PIN 640 128 RIGHT 8 +PINATTR PinName LED9 +PINATTR SpiceOrder 28 +PIN 640 64 RIGHT 8 +PINATTR PinName LED8 +PINATTR SpiceOrder 29 +PIN -320 -512 TOP 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 30 +PIN 240 -512 TOP 8 +PINATTR PinName RT +PINATTR SpiceOrder 31 +PIN 320 -512 TOP 8 +PINATTR PinName SS +PINATTR SpiceOrder 32 +PIN 400 -512 TOP 8 +PINATTR PinName FB +PINATTR SpiceOrder 33 +PIN 576 -512 TOP 8 +PINATTR PinName ISN +PINATTR SpiceOrder 34 +PIN 496 -512 TOP 8 +PINATTR PinName ISP +PINATTR SpiceOrder 35 +PIN 0 -512 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 36 +PIN 160 -512 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 37 +PIN 80 -512 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 38 +PIN -592 -512 TOP 8 +PINATTR PinName C1 +PINATTR SpiceOrder 39 +PIN -416 -512 TOP 8 +PINATTR PinName Iset +PINATTR SpiceOrder 40 +PIN -640 -448 LEFT 8 +PINATTR PinName GS0 +PINATTR SpiceOrder 41 +PIN -560 576 BOTTOM 8 +PINATTR PinName DC0 +PINATTR SpiceOrder 42 +PIN -640 -384 LEFT 8 +PINATTR PinName GS1 +PINATTR SpiceOrder 43 +PIN -496 576 BOTTOM 8 +PINATTR PinName DC1 +PINATTR SpiceOrder 44 +PIN -640 -320 LEFT 8 +PINATTR PinName GS2 +PINATTR SpiceOrder 45 +PIN -432 576 BOTTOM 8 +PINATTR PinName DC2 +PINATTR SpiceOrder 46 +PIN -640 -256 LEFT 8 +PINATTR PinName GS3 +PINATTR SpiceOrder 47 +PIN -368 576 BOTTOM 8 +PINATTR PinName DC3 +PINATTR SpiceOrder 48 +PIN -640 -192 LEFT 8 +PINATTR PinName GS4 +PINATTR SpiceOrder 49 +PIN -304 576 BOTTOM 8 +PINATTR PinName DC4 +PINATTR SpiceOrder 50 +PIN -640 -128 LEFT 8 +PINATTR PinName GS5 +PINATTR SpiceOrder 51 +PIN -240 576 BOTTOM 8 +PINATTR PinName DC5 +PINATTR SpiceOrder 52 +PIN -640 -64 LEFT 8 +PINATTR PinName GS6 +PINATTR SpiceOrder 53 +PIN -176 576 BOTTOM 8 +PINATTR PinName DC6 +PINATTR SpiceOrder 54 +PIN -640 0 LEFT 8 +PINATTR PinName GS7 +PINATTR SpiceOrder 55 +PIN -112 576 BOTTOM 8 +PINATTR PinName DC7 +PINATTR SpiceOrder 56 +PIN -640 64 LEFT 8 +PINATTR PinName GS8 +PINATTR SpiceOrder 57 +PIN -48 576 BOTTOM 8 +PINATTR PinName DC8 +PINATTR SpiceOrder 58 +PIN -640 128 LEFT 8 +PINATTR PinName GS9 +PINATTR SpiceOrder 59 +PIN 16 576 BOTTOM 8 +PINATTR PinName DC9 +PINATTR SpiceOrder 60 +PIN -640 192 LEFT 8 +PINATTR PinName GS10 +PINATTR SpiceOrder 61 +PIN 80 576 BOTTOM 8 +PINATTR PinName DC10 +PINATTR SpiceOrder 62 +PIN -640 256 LEFT 8 +PINATTR PinName GS11 +PINATTR SpiceOrder 63 +PIN 160 576 BOTTOM 8 +PINATTR PinName DC11 +PINATTR SpiceOrder 64 +PIN -640 320 LEFT 8 +PINATTR PinName GS12 +PINATTR SpiceOrder 65 +PIN 240 576 BOTTOM 8 +PINATTR PinName DC12 +PINATTR SpiceOrder 66 +PIN -640 384 LEFT 8 +PINATTR PinName GS13 +PINATTR SpiceOrder 67 +PIN 320 576 BOTTOM 8 +PINATTR PinName DC13 +PINATTR SpiceOrder 68 +PIN -640 448 LEFT 8 +PINATTR PinName GS14 +PINATTR SpiceOrder 69 +PIN 400 576 BOTTOM 8 +PINATTR PinName DC14 +PINATTR SpiceOrder 70 +PIN -640 512 LEFT 8 +PINATTR PinName GS15 +PINATTR SpiceOrder 71 +PIN 480 576 BOTTOM 8 +PINATTR PinName DC15 +PINATTR SpiceOrder 72 diff --git a/spice/copy/sym/PowerProducts/LT3748.asy b/spice/copy/sym/PowerProducts/LT3748.asy new file mode 100755 index 0000000..6ad93e0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3748.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT3748 +SYMATTR Prefix X +SYMATTR SpiceModel LT3748.sub +SYMATTR Value2 LT3748 +SYMATTR Description 100V Isolated Flyback Controller +PIN -64 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 4 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 64 192 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 6 +PIN -160 -112 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 7 +PIN -160 128 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 10 +PIN 160 128 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 11 +PIN -160 48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 12 +PIN 160 -112 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 13 +PIN 160 -32 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 14 +PIN -160 -32 LEFT 8 +PINATTR PinName TC +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LT3750.asy b/spice/copy/sym/PowerProducts/LT3750.asy new file mode 100755 index 0000000..d2c5bd9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3750.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT3750 +SYMATTR Prefix X +SYMATTR SpiceModel LT3750.sub +SYMATTR Value2 LT3750 +SYMATTR Description Capacitor Charger Controller +PIN 0 -160 TOP 8 +PINATTR PinName Vtrans +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName _DONE +PINATTR SpiceOrder 2 +PIN -128 48 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 3 +PIN -128 -112 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 4 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 128 RIGHT 8 +PINATTR PinName Source +PINATTR SpiceOrder 6 +PIN 128 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 7 +PIN 128 -32 RIGHT 8 +PINATTR PinName RDCM +PINATTR SpiceOrder 8 +PIN 128 -112 RIGHT 8 +PINATTR PinName RVout +PINATTR SpiceOrder 9 +PIN -128 128 LEFT 8 +PINATTR PinName RBG +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3751.asy b/spice/copy/sym/PowerProducts/LT3751.asy new file mode 100755 index 0000000..3b5fe02 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3751.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -400 160 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT3751 +SYMATTR Prefix X +SYMATTR SpiceModel LT3751.sub +SYMATTR Value2 LT3751 +SYMATTR Description High Voltage Capacitor Charger Controller with Regulation +PIN -64 -400 TOP 8 +PINATTR PinName RVtrans +PINATTR SpiceOrder 1 +PIN -160 -144 LEFT 8 +PINATTR PinName UVLO1 +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName OVLO1 +PINATTR SpiceOrder 3 +PIN -160 -336 LEFT 8 +PINATTR PinName UVLO2 +PINATTR SpiceOrder 4 +PIN -160 -240 LEFT 8 +PINATTR PinName OVLO2 +PINATTR SpiceOrder 5 +PIN -160 240 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 6 +PIN -160 336 LEFT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName Charge +PINATTR SpiceOrder 8 +PIN -160 144 LEFT 8 +PINATTR PinName Clamp +PINATTR SpiceOrder 9 +PIN 160 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN 160 144 RIGHT 8 +PINATTR PinName CSN +PINATTR SpiceOrder 11 +PIN 160 48 RIGHT 8 +PINATTR PinName CSP +PINATTR SpiceOrder 12 +PIN 64 -400 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 13 +PIN 160 -48 RIGHT 8 +PINATTR PinName LVGate +PINATTR SpiceOrder 14 +PIN 160 -144 RIGHT 8 +PINATTR PinName HVGate +PINATTR SpiceOrder 15 +PIN 160 336 RIGHT 8 +PINATTR PinName RBG +PINATTR SpiceOrder 16 +PIN 160 -240 RIGHT 8 +PINATTR PinName RVout +PINATTR SpiceOrder 18 +PIN 160 -336 RIGHT 8 +PINATTR PinName RDCM +PINATTR SpiceOrder 20 +PIN 0 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT3752-1.asy b/spice/copy/sym/PowerProducts/LT3752-1.asy new file mode 100755 index 0000000..c041203 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3752-1.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -352 -352 352 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3752-1 +SYMATTR Value2 LT3752-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3752-1.sub +SYMATTR Description Active Clamp Synchronous Forward Controller with Internal Housekeeping Controller +PIN -144 -352 TOP 8 +PINATTR PinName HFB +PINATTR SpiceOrder 1 +PIN -240 -352 TOP 8 +PINATTR PinName HCOMP +PINATTR SpiceOrder 2 +PIN -288 352 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN 352 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 352 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN -352 288 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 6 +PIN -352 96 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 7 +PIN -192 352 BOTTOM 8 +PINATTR PinName Ivsec +PINATTR SpiceOrder 8 +PIN -352 -96 LEFT 8 +PINATTR PinName UVLO_Vsec +PINATTR SpiceOrder 9 +PIN -352 0 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 10 +PIN 0 352 BOTTOM 8 +PINATTR PinName Tao +PINATTR SpiceOrder 11 +PIN 96 352 BOTTOM 8 +PINATTR PinName Tas +PINATTR SpiceOrder 12 +PIN 192 352 BOTTOM 8 +PINATTR PinName Tos +PINATTR SpiceOrder 13 +PIN -96 352 BOTTOM 8 +PINATTR PinName Tblnk +PINATTR SpiceOrder 14 +PIN -352 192 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 17 +PIN 288 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 144 -352 TOP 8 +PINATTR PinName PGND +PINATTR SpiceOrder 19 +PIN 352 0 RIGHT 8 +PINATTR PinName Isensen +PINATTR SpiceOrder 20 +PIN 352 -96 RIGHT 8 +PINATTR PinName Isensep +PINATTR SpiceOrder 21 +PIN 352 -192 RIGHT 8 +PINATTR PinName OC +PINATTR SpiceOrder 22 +PIN 352 -288 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 24 +PIN -352 -288 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 26 +PIN -352 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 +PIN 352 288 RIGHT 8 +PINATTR PinName SOUT +PINATTR SpiceOrder 30 +PIN 240 -352 TOP 8 +PINATTR PinName AOUT +PINATTR SpiceOrder 32 +PIN 48 -352 TOP 8 +PINATTR PinName HOUT +PINATTR SpiceOrder 34 +PIN -48 -352 TOP 8 +PINATTR PinName HIsense +PINATTR SpiceOrder 36 diff --git a/spice/copy/sym/PowerProducts/LT3752-2.asy b/spice/copy/sym/PowerProducts/LT3752-2.asy new file mode 100755 index 0000000..b7decd1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3752-2.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -352 -352 352 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3752-2 +SYMATTR Value2 LT3752-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3752-2.sub +SYMATTR Description Active Clamp Synchronous Forward Controller with Internal Housekeeping Controller +PIN -288 352 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN 352 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 352 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN -352 288 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 6 +PIN -352 96 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 7 +PIN -192 352 BOTTOM 8 +PINATTR PinName Ivsec +PINATTR SpiceOrder 8 +PIN -352 -96 LEFT 8 +PINATTR PinName UVLO_Vsec +PINATTR SpiceOrder 9 +PIN -352 0 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 10 +PIN 0 352 BOTTOM 8 +PINATTR PinName Tao +PINATTR SpiceOrder 11 +PIN 96 352 BOTTOM 8 +PINATTR PinName Tas +PINATTR SpiceOrder 12 +PIN 192 352 BOTTOM 8 +PINATTR PinName Tos +PINATTR SpiceOrder 13 +PIN -96 352 BOTTOM 8 +PINATTR PinName Tblnk +PINATTR SpiceOrder 14 +PIN -352 192 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 17 +PIN 288 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 144 -352 TOP 8 +PINATTR PinName PGND +PINATTR SpiceOrder 19 +PIN 352 0 RIGHT 8 +PINATTR PinName Isensen +PINATTR SpiceOrder 20 +PIN 352 -96 RIGHT 8 +PINATTR PinName Isensep +PINATTR SpiceOrder 21 +PIN 352 -288 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 24 +PIN -352 -288 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 26 +PIN -352 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 +PIN 352 288 RIGHT 8 +PINATTR PinName SOUT +PINATTR SpiceOrder 30 +PIN 240 -352 TOP 8 +PINATTR PinName AOUT +PINATTR SpiceOrder 32 diff --git a/spice/copy/sym/PowerProducts/LT3752.asy b/spice/copy/sym/PowerProducts/LT3752.asy new file mode 100755 index 0000000..7c0fc14 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3752.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -352 -352 352 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3752 +SYMATTR Value2 LT3752 +SYMATTR Prefix X +SYMATTR SpiceModel LT3752.sub +SYMATTR Description Active Clamp Synchronous Forward Controller with Internal Housekeeping Controller +PIN -144 -352 TOP 8 +PINATTR PinName HFB +PINATTR SpiceOrder 1 +PIN -240 -352 TOP 8 +PINATTR PinName HCOMP +PINATTR SpiceOrder 2 +PIN -288 352 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN 352 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 352 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN -352 288 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 6 +PIN -352 96 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 7 +PIN -192 352 BOTTOM 8 +PINATTR PinName Ivsec +PINATTR SpiceOrder 8 +PIN -352 -96 LEFT 8 +PINATTR PinName UVLO_Vsec +PINATTR SpiceOrder 9 +PIN -352 0 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 10 +PIN 0 352 BOTTOM 8 +PINATTR PinName Tao +PINATTR SpiceOrder 11 +PIN 96 352 BOTTOM 8 +PINATTR PinName Tas +PINATTR SpiceOrder 12 +PIN 192 352 BOTTOM 8 +PINATTR PinName Tos +PINATTR SpiceOrder 13 +PIN -96 352 BOTTOM 8 +PINATTR PinName Tblnk +PINATTR SpiceOrder 14 +PIN -352 192 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 17 +PIN 288 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 144 -352 TOP 8 +PINATTR PinName PGND +PINATTR SpiceOrder 19 +PIN 352 0 RIGHT 8 +PINATTR PinName Isensen +PINATTR SpiceOrder 20 +PIN 352 -96 RIGHT 8 +PINATTR PinName Isensep +PINATTR SpiceOrder 21 +PIN 352 -192 RIGHT 8 +PINATTR PinName OC +PINATTR SpiceOrder 22 +PIN 352 -288 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 24 +PIN -352 -288 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 26 +PIN -352 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 +PIN 352 288 RIGHT 8 +PINATTR PinName SOUT +PINATTR SpiceOrder 30 +PIN 240 -352 TOP 8 +PINATTR PinName AOUT +PINATTR SpiceOrder 32 +PIN 48 -352 TOP 8 +PINATTR PinName HOUT +PINATTR SpiceOrder 34 +PIN -48 -352 TOP 8 +PINATTR PinName HIsense +PINATTR SpiceOrder 36 diff --git a/spice/copy/sym/PowerProducts/LT3753.asy b/spice/copy/sym/PowerProducts/LT3753.asy new file mode 100755 index 0000000..2eeb843 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3753.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -352 256 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3753 +SYMATTR Value2 LT3753 +SYMATTR Prefix X +SYMATTR SpiceModel LT3753.sub +SYMATTR Description Active Clamp Synchronous Forward Controller +PIN -48 -352 TOP 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN 256 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 256 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN -256 96 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 6 +PIN -256 -96 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 7 +PIN -192 352 BOTTOM 8 +PINATTR PinName Ivsec +PINATTR SpiceOrder 8 +PIN -256 -288 LEFT 8 +PINATTR PinName UVLO_Vsec +PINATTR SpiceOrder 9 +PIN -256 -192 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 10 +PIN 0 352 BOTTOM 8 +PINATTR PinName Tao +PINATTR SpiceOrder 11 +PIN 96 352 BOTTOM 8 +PINATTR PinName Tas +PINATTR SpiceOrder 12 +PIN 192 352 BOTTOM 8 +PINATTR PinName Tos +PINATTR SpiceOrder 13 +PIN -96 352 BOTTOM 8 +PINATTR PinName Tblnk +PINATTR SpiceOrder 14 +PIN -256 0 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 17 +PIN -256 288 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -256 192 LEFT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 19 +PIN 256 0 RIGHT 8 +PINATTR PinName Isensen +PINATTR SpiceOrder 20 +PIN 256 -96 RIGHT 8 +PINATTR PinName Isensep +PINATTR SpiceOrder 21 +PIN 256 -192 RIGHT 8 +PINATTR PinName OC +PINATTR SpiceOrder 22 +PIN 256 -288 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 24 +PIN 48 -352 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 26 +PIN -144 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 +PIN 256 288 RIGHT 8 +PINATTR PinName SOUT +PINATTR SpiceOrder 30 +PIN 144 -352 TOP 8 +PINATTR PinName AOUT +PINATTR SpiceOrder 32 diff --git a/spice/copy/sym/PowerProducts/LT3754.asy b/spice/copy/sym/PowerProducts/LT3754.asy new file mode 100755 index 0000000..0fe7cab --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3754.asy @@ -0,0 +1,107 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -496 192 864 +TEXT 0 128 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 448 Center 2 +SYMATTR Value LT3754 +SYMATTR Prefix X +SYMATTR SpiceModel LT3754.sub +SYMATTR Value2 LT3754 +SYMATTR Description 16-Channel × 50mA LED Driver\n\nNote: Open LED logic not modeled. +PIN 192 -128 RIGHT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 1 +PIN 192 -64 RIGHT 8 +PINATTR PinName LED2 +PINATTR SpiceOrder 2 +PIN 192 0 RIGHT 8 +PINATTR PinName LED3 +PINATTR SpiceOrder 3 +PIN 192 64 RIGHT 8 +PINATTR PinName LED4 +PINATTR SpiceOrder 4 +PIN 192 128 RIGHT 8 +PINATTR PinName LED5 +PINATTR SpiceOrder 5 +PIN 192 192 RIGHT 8 +PINATTR PinName LED6 +PINATTR SpiceOrder 6 +PIN 192 256 RIGHT 8 +PINATTR PinName LED7 +PINATTR SpiceOrder 7 +PIN 192 320 RIGHT 8 +PINATTR PinName LED8 +PINATTR SpiceOrder 8 +PIN 192 -320 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 192 -448 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN -192 -320 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 11 +PIN 0 -496 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN -192 -448 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 13 +PIN -192 -64 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 15 +PIN 192 -192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 16 +PIN 192 384 RIGHT 8 +PINATTR PinName LED9 +PINATTR SpiceOrder 17 +PIN 192 448 RIGHT 8 +PINATTR PinName LED10 +PINATTR SpiceOrder 18 +PIN 192 512 RIGHT 8 +PINATTR PinName LED11 +PINATTR SpiceOrder 19 +PIN 192 576 RIGHT 8 +PINATTR PinName LED12 +PINATTR SpiceOrder 20 +PIN 192 640 RIGHT 8 +PINATTR PinName LED13 +PINATTR SpiceOrder 21 +PIN 192 704 RIGHT 8 +PINATTR PinName LED14 +PINATTR SpiceOrder 22 +PIN 192 768 RIGHT 8 +PINATTR PinName LED15 +PINATTR SpiceOrder 23 +PIN 192 832 RIGHT 8 +PINATTR PinName LED16 +PINATTR SpiceOrder 24 +PIN -192 704 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 25 +PIN -192 -192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 26 +PIN -192 64 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 27 +PIN -192 576 LEFT 8 +PINATTR PinName OVPset +PINATTR SpiceOrder 28 +PIN -192 192 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 29 +PIN -192 448 LEFT 8 +PINATTR PinName Tset +PINATTR SpiceOrder 30 +PIN -192 320 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 31 +PIN -192 832 LEFT 8 +PINATTR PinName Iset +PINATTR SpiceOrder 32 +PIN 0 864 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 33 diff --git a/spice/copy/sym/PowerProducts/LT3755-1.asy b/spice/copy/sym/PowerProducts/LT3755-1.asy new file mode 100755 index 0000000..b0e1387 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3755-1.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3755-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3755-1.sub +SYMATTR Value2 LT3755-1 +SYMATTR Description Full-Featured LED Controller +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWMin +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 176 -160 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 96 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN -176 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3755-2.asy b/spice/copy/sym/PowerProducts/LT3755-2.asy new file mode 100755 index 0000000..c1d0a76 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3755-2.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3755-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3755-2.sub +SYMATTR Value2 LT3755-2 +SYMATTR Description 40Vin, 75Vout LED Controller +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWMin +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName _OPENLED +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 176 -160 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 96 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN -176 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3755.asy b/spice/copy/sym/PowerProducts/LT3755.asy new file mode 100755 index 0000000..e645d0a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3755.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3755 +SYMATTR Prefix X +SYMATTR SpiceModel LT3755.sub +SYMATTR Value2 LT3755 +SYMATTR Description Full-Featured LED Controller +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWMin +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName _OPENLED +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 176 -160 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 96 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN -176 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3756-1.asy b/spice/copy/sym/PowerProducts/LT3756-1.asy new file mode 100755 index 0000000..83bf3cb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3756-1.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3756-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3756-1.sub +SYMATTR Value2 LT3756-1 +SYMATTR Description Full-Featured LED Controller +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWMin +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 176 -160 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 96 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN -176 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3756-2.asy b/spice/copy/sym/PowerProducts/LT3756-2.asy new file mode 100755 index 0000000..b4b16d5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3756-2.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3756-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT3756.sub +SYMATTR Value2 LT3756 +SYMATTR Description Full-Featured LED Controller +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWMin +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName _OPENLED +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 176 -160 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 96 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN -176 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3756.asy b/spice/copy/sym/PowerProducts/LT3756.asy new file mode 100755 index 0000000..69e28e9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3756.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3756 +SYMATTR Prefix X +SYMATTR SpiceModel LT3756.sub +SYMATTR Value2 LT3756 +SYMATTR Description Full-Featured LED Controller +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWMin +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName _OPENLED +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 176 -160 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 96 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN -176 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3757.asy b/spice/copy/sym/PowerProducts/LT3757.asy new file mode 100755 index 0000000..2a567c4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3757.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3757 +SYMATTR Prefix X +SYMATTR SpiceModel LT3757.sub +SYMATTR Value2 LT3757 +SYMATTR Description Boost, Flyback, SEPIC and Inverting Controller +PIN -160 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 144 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 160 -48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 7 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 9 +PIN 0 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3757A.asy b/spice/copy/sym/PowerProducts/LT3757A.asy new file mode 100755 index 0000000..c355362 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3757A.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3757A +SYMATTR Prefix X +SYMATTR SpiceModel LT3757A.sub +SYMATTR Value2 LT3757A +SYMATTR Description Boost, Flyback, SEPIC and Inverting Controller +PIN -160 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 144 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 160 -48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 7 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 9 +PIN 0 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3758.asy b/spice/copy/sym/PowerProducts/LT3758.asy new file mode 100755 index 0000000..852b63f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3758.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3758 +SYMATTR Prefix X +SYMATTR SpiceModel LT3758.sub +SYMATTR Value2 LT3758 +SYMATTR Description High Input Voltage, Boost, Flyback, SEPIC and Inverting Controller +PIN -160 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 144 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 160 -48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 7 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 9 +PIN 0 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3758A.asy b/spice/copy/sym/PowerProducts/LT3758A.asy new file mode 100755 index 0000000..d342dc8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3758A.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3758A +SYMATTR Prefix X +SYMATTR SpiceModel LT3758A.sub +SYMATTR Value2 LT3758A +SYMATTR Description High Input Voltage, Boost, Flyback, SEPIC and Inverting Controller +PIN -160 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 144 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 160 -48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 7 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 9 +PIN 0 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3759.asy b/spice/copy/sym/PowerProducts/LT3759.asy new file mode 100755 index 0000000..6d38fa1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3759.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3759 +SYMATTR Prefix X +SYMATTR SpiceModel LT3759.sub +SYMATTR Value2 LT3759 +SYMATTR Description Wide Input Voltage Range Boost/SEPIC/Inverting Controller +PIN -160 192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 192 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName _Pgood +PINATTR SpiceOrder 6 +PIN 160 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN 160 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 8 +PIN 160 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 9 +PIN 160 -96 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 10 +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -160 -192 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 12 +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3760.asy b/spice/copy/sym/PowerProducts/LT3760.asy new file mode 100755 index 0000000..0f78cab --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3760.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -496 192 864 +TEXT 0 128 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 448 Center 2 +SYMATTR Value LT3760 +SYMATTR Prefix X +SYMATTR SpiceModel LT3760.sub +SYMATTR Value2 LT3760 +SYMATTR Description 8-Channel × 100mA LED Driver\n\nNote: Open LED logic not modeled. +PIN 192 -64 RIGHT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 1 +PIN 192 64 RIGHT 8 +PINATTR PinName LED2 +PINATTR SpiceOrder 2 +PIN 192 192 RIGHT 8 +PINATTR PinName LED3 +PINATTR SpiceOrder 3 +PIN 192 320 RIGHT 8 +PINATTR PinName LED4 +PINATTR SpiceOrder 4 +PIN 192 448 RIGHT 8 +PINATTR PinName LED5 +PINATTR SpiceOrder 5 +PIN 192 576 RIGHT 8 +PINATTR PinName LED6 +PINATTR SpiceOrder 6 +PIN 192 704 RIGHT 8 +PINATTR PinName LED7 +PINATTR SpiceOrder 7 +PIN 192 832 RIGHT 8 +PINATTR PinName LED8 +PINATTR SpiceOrder 8 +PIN 192 -320 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 192 -448 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN -192 -320 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 11 +PIN 0 -496 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN -192 -448 LEFT 8 +PINATTR PinName _SHDN/UVLO +PINATTR SpiceOrder 13 +PIN -192 -64 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 15 +PIN 192 -192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 16 +PIN -192 704 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 25 +PIN -192 -192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 26 +PIN -192 64 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 27 +PIN -192 576 LEFT 8 +PINATTR PinName OVPset +PINATTR SpiceOrder 28 +PIN -192 192 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 29 +PIN -192 448 LEFT 8 +PINATTR PinName Tset +PINATTR SpiceOrder 30 +PIN -192 320 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 31 +PIN -192 832 LEFT 8 +PINATTR PinName Iset +PINATTR SpiceOrder 32 +PIN 0 864 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 33 diff --git a/spice/copy/sym/PowerProducts/LT3761.asy b/spice/copy/sym/PowerProducts/LT3761.asy new file mode 100755 index 0000000..cd1a891 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3761.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3761 +SYMATTR Prefix X +SYMATTR SpiceModel LT3761.sub +SYMATTR Value2 LT3761 +SYMATTR Description 60Vin LED Controller with Internal PWM Generator +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName _OPENLED +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName DIM/SS +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 176 -160 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 96 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN -176 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3761A.asy b/spice/copy/sym/PowerProducts/LT3761A.asy new file mode 100755 index 0000000..6e66cb4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3761A.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3761A +SYMATTR Prefix X +SYMATTR SpiceModel LT3761A.sub +SYMATTR Value2 LT3761A +SYMATTR Description 60 Vin LED Controller with Internal PWM Generator +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName _OPENLED +PINATTR SpiceOrder 3 +PIN -176 96 LEFT 8 +PINATTR PinName DIM/SS +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 9 +PIN 176 -160 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 96 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN -176 32 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3762.asy b/spice/copy/sym/PowerProducts/LT3762.asy new file mode 100755 index 0000000..0e38322 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3762.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -352 256 368 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3762 +SYMATTR Prefix X +SYMATTR SpiceModel LT3762.sub +SYMATTR Value2 LT3762 +SYMATTR Description 60V Synchronous Boost LED Controller +PIN -256 64 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 1 +PIN -256 0 LEFT 8 +PINATTR PinName DIM +PINATTR SpiceOrder 2 +PIN -96 368 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 3 +PIN -192 368 BOTTOM 8 +PINATTR PinName SSFM +PINATTR SpiceOrder 4 +PIN 96 368 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN -256 -128 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 6 +PIN -256 -192 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 7 +PIN -256 -64 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 8 +PIN 192 368 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN 256 -96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN 0 368 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 256 96 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 12 +PIN 256 32 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 256 -32 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN 256 -160 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 15 +PIN 256 -288 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 16 +PIN 256 -224 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 17 +PIN 176 -352 TOP 8 +PINATTR PinName BG +PINATTR SpiceOrder 18 +PIN 64 -352 TOP 8 +PINATTR PinName SNSN +PINATTR SpiceOrder 19 +PIN -64 -352 TOP 8 +PINATTR PinName SNSP +PINATTR SpiceOrder 20 +PIN -176 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 +PIN 256 224 RIGHT 8 +PINATTR PinName AuxSW1 +PINATTR SpiceOrder 22 +PIN 256 288 RIGHT 8 +PINATTR PinName AuxBST +PINATTR SpiceOrder 23 +PIN 256 160 RIGHT 8 +PINATTR PinName AuxSW2 +PINATTR SpiceOrder 24 +PIN -256 288 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -256 -256 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 26 +PIN -256 224 LEFT 8 +PINATTR PinName _OpenLED +PINATTR SpiceOrder 27 +PIN -256 144 LEFT 8 +PINATTR PinName _ShortLED +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3763.asy b/spice/copy/sym/PowerProducts/LT3763.asy new file mode 100755 index 0000000..7386f50 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3763.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -496 192 496 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT3763 +SYMATTR Prefix X +SYMATTR SpiceModel LT3763.sub +SYMATTR Value2 LT3763 +SYMATTR Description 60V High Current Step-Down LED Driver Controller +PIN 192 -48 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 1 +PIN 192 -432 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 96 -496 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -192 -432 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 4 +PIN -192 -336 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 5 +PIN 0 -496 TOP 8 +PINATTR PinName Vinn +PINATTR SpiceOrder 6 +PIN -96 -496 TOP 8 +PINATTR PinName Vinp +PINATTR SpiceOrder 7 +PIN -192 48 LEFT 8 +PINATTR PinName IVinmon +PINATTR SpiceOrder 8 +PIN 192 432 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 9 +PIN -192 -48 LEFT 8 +PINATTR PinName FBin +PINATTR SpiceOrder 10 +PIN 192 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 64 496 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 +PIN -192 -240 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 13 +PIN -192 -144 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 14 +PIN -192 336 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 15 +PIN 192 144 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 16 +PIN 192 48 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 17 +PIN -192 240 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 18 +PIN -192 144 LEFT 8 +PINATTR PinName Ismon +PINATTR SpiceOrder 19 +PIN -64 496 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 20 +PIN -192 432 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 22 +PIN 192 336 RIGHT 8 +PINATTR PinName PWM_out +PINATTR SpiceOrder 24 +PIN 192 -240 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 25 +PIN 192 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 26 +PIN 192 -336 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 27 diff --git a/spice/copy/sym/PowerProducts/LT3781.asy b/spice/copy/sym/PowerProducts/LT3781.asy new file mode 100755 index 0000000..96b2dfb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3781.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -143 -241 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -183 Center 2 +WINDOW 3 0 145 Center 2 +SYMATTR Value LT3781 +SYMATTR Prefix X +SYMATTR SpiceModel LT3781.sub +SYMATTR Value2 LT3781 +SYMATTR Description "Bootstrap" Start Dual Transistor Synchronous Forward Controller +PIN -144 -208 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -160 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 2 +PIN -144 -112 LEFT 8 +PINATTR PinName THERM +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName GSND +PINATTR SpiceOrder 4 +PIN -144 -16 LEFT 8 +PINATTR PinName 5Vref +PINATTR SpiceOrder 5 +PIN -144 32 LEFT 8 +PINATTR PinName FSET +PINATTR SpiceOrder 6 +PIN -144 128 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -144 176 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 224 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 10 +PIN 144 224 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 11 +PIN 144 176 RIGHT 8 +PINATTR PinName SG +PINATTR SpiceOrder 12 +PIN 144 128 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 13 +PIN 144 80 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 14 +PIN 144 32 RIGHT 8 +PINATTR PinName GB +PINATTR SpiceOrder 15 +PIN 144 -112 RIGHT 8 +PINATTR PinName BSTREF +PINATTR SpiceOrder 18 +PIN 144 -160 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 19 +PIN 144 -208 RIGHT 8 +PINATTR PinName Vbst +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT3782.asy b/spice/copy/sym/PowerProducts/LT3782.asy new file mode 100755 index 0000000..abf8b5f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3782.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -256 208 464 +TEXT 0 112 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 256 Center 2 +SYMATTR Value LT3782 +SYMATTR Prefix X +SYMATTR SpiceModel LT3782.sub +SYMATTR Value2 LT3782 +SYMATTR Description 2-Phase Step-Up DC/DC Controller\n\nNote: Synchronous rectification pins are not modeled. +PIN 0 464 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 208 400 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN -208 304 LEFT 8 +PINATTR PinName DCL +PINATTR SpiceOrder 7 +PIN -208 -128 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 8 +PIN -208 -16 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 9 +PIN -208 400 LEFT 8 +PINATTR PinName Slope +PINATTR SpiceOrder 10 +PIN -208 208 LEFT 8 +PINATTR PinName Rset +PINATTR SpiceOrder 11 +PIN 208 -16 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 12 +PIN 208 -128 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 13 +PIN 208 304 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN 208 208 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN 208 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -208 112 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN 208 48 RIGHT 8 +PINATTR PinName Vee2 +PINATTR SpiceOrder 19 +PIN 208 -192 RIGHT 8 +PINATTR PinName Bgate2 +PINATTR SpiceOrder 20 +PIN 144 -256 TOP 8 +PINATTR PinName Gbias2 +PINATTR SpiceOrder 21 +PIN -48 -256 TOP 8 +PINATTR PinName Gbias1 +PINATTR SpiceOrder 22 +PIN -208 -192 LEFT 8 +PINATTR PinName Bgate1 +PINATTR SpiceOrder 23 +PIN -208 48 LEFT 8 +PINATTR PinName Vee1 +PINATTR SpiceOrder 24 +PIN -144 -256 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 27 +PIN 48 -256 TOP 8 +PINATTR PinName Gbias +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3782A.asy b/spice/copy/sym/PowerProducts/LT3782A.asy new file mode 100755 index 0000000..bf49348 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3782A.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -256 208 464 +TEXT 0 112 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 256 Center 2 +SYMATTR Value LT3782A +SYMATTR Prefix X +SYMATTR SpiceModel LT3782.sub +SYMATTR Value2 LT3782 +SYMATTR Description 2-Phase Step-Up DC/DC Controller\n\nNote: Synchronous rectification pins are not modeled. +PIN 0 464 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 208 400 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN -208 304 LEFT 8 +PINATTR PinName DCL +PINATTR SpiceOrder 7 +PIN -208 -128 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 8 +PIN -208 -16 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 9 +PIN -208 400 LEFT 8 +PINATTR PinName Slope +PINATTR SpiceOrder 10 +PIN -208 208 LEFT 8 +PINATTR PinName Rset +PINATTR SpiceOrder 11 +PIN 208 -16 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 12 +PIN 208 -128 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 13 +PIN 208 304 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN 208 208 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN 208 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -208 112 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN 208 48 RIGHT 8 +PINATTR PinName Vee2 +PINATTR SpiceOrder 19 +PIN 208 -192 RIGHT 8 +PINATTR PinName Bgate2 +PINATTR SpiceOrder 20 +PIN 144 -256 TOP 8 +PINATTR PinName Gbias2 +PINATTR SpiceOrder 21 +PIN -48 -256 TOP 8 +PINATTR PinName Gbias1 +PINATTR SpiceOrder 22 +PIN -208 -192 LEFT 8 +PINATTR PinName Bgate1 +PINATTR SpiceOrder 23 +PIN -208 48 LEFT 8 +PINATTR PinName Vee1 +PINATTR SpiceOrder 24 +PIN -144 -256 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 27 +PIN 48 -256 TOP 8 +PINATTR PinName Gbias +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3790.asy b/spice/copy/sym/PowerProducts/LT3790.asy new file mode 100755 index 0000000..3ba597c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3790.asy @@ -0,0 +1,116 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 304 544 -304 -544 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value LT3790 +SYMATTR Prefix X +SYMATTR SpiceModel LT3790.sub +SYMATTR Value2 LT3790 +SYMATTR Description 60V Synchronous 4-Switch Buck-Boost Controller +PIN -304 384 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 1 +PIN -160 544 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN -304 480 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 3 +PIN -304 96 LEFT 8 +PINATTR PinName _C/10 +PINATTR SpiceOrder 4 +PIN -304 0 LEFT 8 +PINATTR PinName _SHORT +PINATTR SpiceOrder 5 +PIN -304 288 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 6 +PIN -304 -96 LEFT 8 +PINATTR PinName ISmon +PINATTR SpiceOrder 7 +PIN -304 -192 LEFT 8 +PINATTR PinName IVinmon +PINATTR SpiceOrder 8 +PIN -304 -480 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN -240 -544 TOP 8 +PINATTR PinName IVinP +PINATTR SpiceOrder 10 +PIN -144 -544 TOP 8 +PINATTR PinName IVinN +PINATTR SpiceOrder 11 +PIN -48 -544 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN 240 -544 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 304 -288 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 14 +PIN 304 -384 RIGHT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 15 +PIN 304 -192 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 16 +PIN 304 192 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 17 +PIN 304 -96 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 18 +PIN 304 288 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 304 384 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 21 +PIN 304 -480 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 22 +PIN 304 480 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 24 +PIN 144 -544 TOP 8 +PINATTR PinName ISP +PINATTR SpiceOrder 25 +PIN 48 -544 TOP 8 +PINATTR PinName ISN +PINATTR SpiceOrder 26 +PIN 304 0 RIGHT 8 +PINATTR PinName SNSP +PINATTR SpiceOrder 27 +PIN 304 96 RIGHT 8 +PINATTR PinName SNSN +PINATTR SpiceOrder 28 +PIN -240 544 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 30 +PIN 160 544 BOTTOM 8 +PINATTR PinName PWMOUT +PINATTR SpiceOrder 31 +PIN -304 192 LEFT 8 +PINATTR PinName CCM +PINATTR SpiceOrder 32 +PIN -304 -288 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 33 +PIN -80 544 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 34 +PIN 0 544 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 35 +PIN 80 544 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 36 +PIN 240 544 BOTTOM 8 +PINATTR PinName FB +PINATTR SpiceOrder 37 +PIN -304 -384 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LT3791-1.asy b/spice/copy/sym/PowerProducts/LT3791-1.asy new file mode 100755 index 0000000..2721e8f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3791-1.asy @@ -0,0 +1,116 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 304 544 -304 -544 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value LT3791-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3791-1.sub +SYMATTR Value2 LT3791-1 +SYMATTR Description 60V 4-Switch Synchronous Buck-Boost Controller +PIN -304 384 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 1 +PIN -160 544 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN -304 480 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 3 +PIN -304 96 LEFT 8 +PINATTR PinName _C/10 +PINATTR SpiceOrder 4 +PIN -304 0 LEFT 8 +PINATTR PinName _SHORT +PINATTR SpiceOrder 5 +PIN -304 288 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 6 +PIN -304 -96 LEFT 8 +PINATTR PinName ISmon +PINATTR SpiceOrder 7 +PIN -304 -192 LEFT 8 +PINATTR PinName IVinmon +PINATTR SpiceOrder 8 +PIN -304 -480 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN -240 -544 TOP 8 +PINATTR PinName IVinP +PINATTR SpiceOrder 10 +PIN -144 -544 TOP 8 +PINATTR PinName IVinN +PINATTR SpiceOrder 11 +PIN -48 -544 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN 240 -544 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 304 -288 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 14 +PIN 304 -384 RIGHT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 15 +PIN 304 -192 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 16 +PIN 304 192 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 17 +PIN 304 -96 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 18 +PIN 304 288 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 304 384 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 21 +PIN 304 -480 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 22 +PIN 304 480 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 24 +PIN 144 -544 TOP 8 +PINATTR PinName ISP +PINATTR SpiceOrder 25 +PIN 48 -544 TOP 8 +PINATTR PinName ISN +PINATTR SpiceOrder 26 +PIN 304 0 RIGHT 8 +PINATTR PinName SNSP +PINATTR SpiceOrder 27 +PIN 304 96 RIGHT 8 +PINATTR PinName SNSN +PINATTR SpiceOrder 28 +PIN -240 544 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 30 +PIN 160 544 BOTTOM 8 +PINATTR PinName PWMOUT +PINATTR SpiceOrder 31 +PIN -304 192 LEFT 8 +PINATTR PinName CCM +PINATTR SpiceOrder 32 +PIN -304 -288 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 33 +PIN -80 544 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 34 +PIN 0 544 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 35 +PIN 80 544 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 36 +PIN 240 544 BOTTOM 8 +PINATTR PinName FB +PINATTR SpiceOrder 37 +PIN -304 -384 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LT3791.asy b/spice/copy/sym/PowerProducts/LT3791.asy new file mode 100755 index 0000000..e7a409c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3791.asy @@ -0,0 +1,113 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 304 544 -304 -544 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value LT3791 +SYMATTR Prefix X +SYMATTR SpiceModel LT3791.sub +SYMATTR Value2 LT3791 +SYMATTR Description 60V 4-Switch Synchronous Buck-Boost LED Driver Controller +PIN -304 384 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 1 +PIN -144 544 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN -304 480 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 3 +PIN -304 96 LEFT 8 +PINATTR PinName _OPENLED +PINATTR SpiceOrder 4 +PIN -304 0 LEFT 8 +PINATTR PinName _SHORTLED +PINATTR SpiceOrder 5 +PIN -304 288 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 6 +PIN -304 -96 LEFT 8 +PINATTR PinName ISmon +PINATTR SpiceOrder 7 +PIN -304 -192 LEFT 8 +PINATTR PinName IVinmon +PINATTR SpiceOrder 8 +PIN -304 -480 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN -240 -544 TOP 8 +PINATTR PinName IVinP +PINATTR SpiceOrder 10 +PIN -144 -544 TOP 8 +PINATTR PinName IVinN +PINATTR SpiceOrder 11 +PIN -48 -544 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN 240 -544 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 304 -288 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 14 +PIN 304 -384 RIGHT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 15 +PIN 304 -192 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 16 +PIN 304 192 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 17 +PIN 304 -96 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 18 +PIN 304 288 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 304 384 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 21 +PIN 304 -480 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 22 +PIN 304 480 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 24 +PIN 144 -544 TOP 8 +PINATTR PinName ISP +PINATTR SpiceOrder 25 +PIN 48 -544 TOP 8 +PINATTR PinName ISN +PINATTR SpiceOrder 26 +PIN 304 0 RIGHT 8 +PINATTR PinName SNSP +PINATTR SpiceOrder 27 +PIN 304 96 RIGHT 8 +PINATTR PinName SNSN +PINATTR SpiceOrder 28 +PIN -240 544 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 30 +PIN 144 544 BOTTOM 8 +PINATTR PinName PWMOUT +PINATTR SpiceOrder 31 +PIN -304 -288 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 33 +PIN -48 544 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 34 +PIN -304 192 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 35 +PIN 48 544 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 36 +PIN 240 544 BOTTOM 8 +PINATTR PinName FB +PINATTR SpiceOrder 37 +PIN -304 -384 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LT3795.asy b/spice/copy/sym/PowerProducts/LT3795.asy new file mode 100755 index 0000000..f83a9ad --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3795.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -400 208 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LT3795 +SYMATTR Prefix X +SYMATTR SpiceModel LT3795.sub +SYMATTR Value2 LT3795 +SYMATTR Description 110V LED Controller with Spread Spectrum Frequency Modulation +PIN 208 48 RIGHT 8 +PINATTR PinName Isp +PINATTR SpiceOrder 1 +PIN 208 144 RIGHT 8 +PINATTR PinName Isn +PINATTR SpiceOrder 2 +PIN 208 240 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 3 +PIN 208 -144 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -160 400 BOTTOM 8 +PINATTR PinName Ismon +PINATTR SpiceOrder 5 +PIN -208 -48 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 6 +PIN 208 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 0 400 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 +PIN -208 -144 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 9 +PIN -208 -240 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 10 +PIN 160 400 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN 80 400 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -80 400 BOTTOM 8 +PINATTR PinName RAMP +PINATTR SpiceOrder 13 +PIN -208 48 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 +PIN -208 240 LEFT 8 +PINATTR PinName _ShortLED +PINATTR SpiceOrder 15 +PIN -208 336 LEFT 8 +PINATTR PinName _OpenLED +PINATTR SpiceOrder 16 +PIN 208 -240 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 18 +PIN 208 -336 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 19 +PIN 208 336 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 +PIN -48 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 23 +PIN -144 -400 TOP 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 24 +PIN -208 -336 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 25 +PIN 144 -400 TOP 8 +PINATTR PinName IVIN +PINATTR SpiceOrder 26 +PIN 48 -400 TOP 8 +PINATTR PinName IVINP +PINATTR SpiceOrder 27 +PIN -208 144 LEFT 8 +PINATTR PinName IVINCOMP +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3796-1.asy b/spice/copy/sym/PowerProducts/LT3796-1.asy new file mode 100755 index 0000000..e5ef7f3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3796-1.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -400 208 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LT3796-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3796-1.sub +SYMATTR Value2 LT3796-1 +SYMATTR Description 100V Constant-Current and Constant-Voltage Controller with Dual Current Sense +PIN 208 48 RIGHT 8 +PINATTR PinName Isp +PINATTR SpiceOrder 1 +PIN 208 144 RIGHT 8 +PINATTR PinName Isn +PINATTR SpiceOrder 2 +PIN 208 240 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 3 +PIN 208 -144 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -208 144 LEFT 8 +PINATTR PinName Ismon +PINATTR SpiceOrder 5 +PIN -80 400 BOTTOM 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 6 +PIN 208 -48 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 7 +PIN 0 400 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 +PIN -208 -144 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 9 +PIN -208 -240 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 10 +PIN 160 400 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN 80 400 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -160 400 BOTTOM 8 +PINATTR PinName TGEN +PINATTR SpiceOrder 13 +PIN -208 -48 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 +PIN -208 240 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 15 +PIN -208 336 LEFT 8 +PINATTR PinName _Vmode +PINATTR SpiceOrder 16 +PIN 208 -240 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 18 +PIN 208 -336 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 19 +PIN 208 336 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 +PIN -144 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 23 +PIN -208 -336 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 24 +PIN -48 -400 TOP 8 +PINATTR PinName Vs +PINATTR SpiceOrder 25 +PIN 144 -400 TOP 8 +PINATTR PinName Csn +PINATTR SpiceOrder 26 +PIN 48 -400 TOP 8 +PINATTR PinName Csp +PINATTR SpiceOrder 27 +PIN -208 48 LEFT 8 +PINATTR PinName Csout +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3796.asy b/spice/copy/sym/PowerProducts/LT3796.asy new file mode 100755 index 0000000..1c46318 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3796.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -400 208 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LT3796 +SYMATTR Prefix X +SYMATTR SpiceModel LT3796.sub +SYMATTR Value2 LT3796 +SYMATTR Description 100V Constant-Current and Constant-Voltage Controller with Dual Current Sense +PIN 208 48 RIGHT 8 +PINATTR PinName Isp +PINATTR SpiceOrder 1 +PIN 208 144 RIGHT 8 +PINATTR PinName Isn +PINATTR SpiceOrder 2 +PIN 208 240 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 3 +PIN 208 -144 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -208 144 LEFT 8 +PINATTR PinName Ismon +PINATTR SpiceOrder 5 +PIN 48 400 BOTTOM 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 6 +PIN 208 -48 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 7 +PIN -144 400 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 +PIN -208 -144 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 9 +PIN -208 -240 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 10 +PIN 160 400 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN -48 400 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -208 -48 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 +PIN -208 240 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 15 +PIN -208 336 LEFT 8 +PINATTR PinName _Vmode +PINATTR SpiceOrder 16 +PIN 208 -240 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 18 +PIN 208 -336 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 19 +PIN 208 336 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 +PIN -144 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 23 +PIN -208 -336 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 24 +PIN -48 -400 TOP 8 +PINATTR PinName Vs +PINATTR SpiceOrder 25 +PIN 144 -400 TOP 8 +PINATTR PinName Csn +PINATTR SpiceOrder 26 +PIN 48 -400 TOP 8 +PINATTR PinName Csp +PINATTR SpiceOrder 27 +PIN -208 48 LEFT 8 +PINATTR PinName Csout +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3797.asy b/spice/copy/sym/PowerProducts/LT3797.asy new file mode 100755 index 0000000..ee05515 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3797.asy @@ -0,0 +1,152 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -496 -688 496 688 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT3797 +SYMATTR Prefix X +SYMATTR SpiceModel LT3797.sub +SYMATTR Value2 LT3797 +SYMATTR Description Triple Output LED Driver Controller +PIN -496 -144 LEFT 8 +PINATTR PinName _FLT1 +PINATTR SpiceOrder 1 +PIN -496 -48 LEFT 8 +PINATTR PinName _FLT2 +PINATTR SpiceOrder 2 +PIN -496 48 LEFT 8 +PINATTR PinName _FLT3 +PINATTR SpiceOrder 3 +PIN -496 144 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 4 +PIN -496 240 LEFT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 5 +PIN -496 336 LEFT 8 +PINATTR PinName PWM3 +PINATTR SpiceOrder 6 +PIN -496 -240 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 7 +PIN -496 432 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 8 +PIN -496 528 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 9 +PIN -496 624 LEFT 8 +PINATTR PinName CTRL3 +PINATTR SpiceOrder 10 +PIN -496 -336 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 11 +PIN -496 -432 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 12 +PIN 496 -144 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 14 +PIN 496 -240 RIGHT 8 +PINATTR PinName Isn1 +PINATTR SpiceOrder 15 +PIN 496 -336 RIGHT 8 +PINATTR PinName Isp1 +PINATTR SpiceOrder 16 +PIN 496 -48 RIGHT 8 +PINATTR PinName FBH1 +PINATTR SpiceOrder 17 +PIN -432 688 BOTTOM 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 19 +PIN 192 -688 TOP 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 20 +PIN 496 -432 RIGHT 8 +PINATTR PinName Sensen1 +PINATTR SpiceOrder 21 +PIN 496 -528 RIGHT 8 +PINATTR PinName Sensep1 +PINATTR SpiceOrder 22 +PIN 496 -624 RIGHT 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 23 +PIN 496 48 RIGHT 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 24 +PIN 496 144 RIGHT 8 +PINATTR PinName Sensep2 +PINATTR SpiceOrder 25 +PIN 496 240 RIGHT 8 +PINATTR PinName Sensen2 +PINATTR SpiceOrder 26 +PIN 288 -688 TOP 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 27 +PIN -336 688 BOTTOM 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 28 +PIN 496 624 RIGHT 8 +PINATTR PinName FBH2 +PINATTR SpiceOrder 30 +PIN 496 336 RIGHT 8 +PINATTR PinName Isp2 +PINATTR SpiceOrder 31 +PIN 496 432 RIGHT 8 +PINATTR PinName Isn2 +PINATTR SpiceOrder 32 +PIN 496 528 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 33 +PIN -48 688 BOTTOM 8 +PINATTR PinName TG3 +PINATTR SpiceOrder 35 +PIN 48 688 BOTTOM 8 +PINATTR PinName Isn3 +PINATTR SpiceOrder 36 +PIN 144 688 BOTTOM 8 +PINATTR PinName Isp3 +PINATTR SpiceOrder 37 +PIN -144 688 BOTTOM 8 +PINATTR PinName FBH3 +PINATTR SpiceOrder 38 +PIN -240 688 BOTTOM 8 +PINATTR PinName Vc3 +PINATTR SpiceOrder 40 +PIN 384 -688 TOP 8 +PINATTR PinName SS3 +PINATTR SpiceOrder 41 +PIN 240 688 BOTTOM 8 +PINATTR PinName Sensen3 +PINATTR SpiceOrder 42 +PIN 336 688 BOTTOM 8 +PINATTR PinName Sensep3 +PINATTR SpiceOrder 43 +PIN 432 688 BOTTOM 8 +PINATTR PinName Gate3 +PINATTR SpiceOrder 44 +PIN 0 -688 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 45 +PIN -288 -688 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 47 +PIN -96 -688 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 48 +PIN -192 -688 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 49 +PIN -384 -688 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 50 +PIN -496 -624 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 51 +PIN -496 -528 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 52 +PIN 96 -688 TOP 8 +PINATTR PinName GND +PINATTR SpiceOrder 53 diff --git a/spice/copy/sym/PowerProducts/LT3798.asy b/spice/copy/sym/PowerProducts/LT3798.asy new file mode 100755 index 0000000..41c588f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3798.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -336 160 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3798 +SYMATTR Prefix X +SYMATTR SpiceModel LT3798.sub +SYMATTR Value2 LT3798 +SYMATTR Description Isolated No Opto-Coupler Flyback Controller with Active PFC +PIN -160 0 LEFT 8 +PINATTR PinName Ctrl1 +PINATTR SpiceOrder 1 +PIN -160 96 LEFT 8 +PINATTR PinName Ctrl2 +PINATTR SpiceOrder 2 +PIN -160 192 LEFT 8 +PINATTR PinName Ctrl3 +PINATTR SpiceOrder 3 +PIN -160 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 4 +PIN -160 288 LEFT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 5 +PIN -64 352 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN 160 192 RIGHT 8 +PINATTR PinName Comp+ +PINATTR SpiceOrder 7 +PIN 160 288 RIGHT 8 +PINATTR PinName Comp- +PINATTR SpiceOrder 8 +PIN 160 -192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN 160 -288 RIGHT 8 +PINATTR PinName DCM +PINATTR SpiceOrder 10 +PIN 0 -336 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -160 -288 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 12 +PIN 160 -96 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 160 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 14 +PIN 160 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 15 +PIN -160 -192 LEFT 8 +PINATTR PinName Vin_sense +PINATTR SpiceOrder 16 +PIN 64 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3799-1.asy b/spice/copy/sym/PowerProducts/LT3799-1.asy new file mode 100755 index 0000000..e9ea677 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3799-1.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -336 160 336 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3799-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3799-1.sub +SYMATTR Value2 LT3799-1 +SYMATTR Description Offline Isolated Flyback LED Converter With Active PFC +PIN -160 96 LEFT 8 +PINATTR PinName Ctrl1 +PINATTR SpiceOrder 1 +PIN -160 192 LEFT 8 +PINATTR PinName Ctrl2 +PINATTR SpiceOrder 2 +PIN -160 288 LEFT 8 +PINATTR PinName Ctrl3 +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -160 -192 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN 160 192 RIGHT 8 +PINATTR PinName Comp+ +PINATTR SpiceOrder 7 +PIN 160 288 RIGHT 8 +PINATTR PinName Comp- +PINATTR SpiceOrder 8 +PIN 160 -192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN 160 -288 RIGHT 8 +PINATTR PinName DCM +PINATTR SpiceOrder 10 +PIN 0 -336 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN 160 -96 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 160 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 14 +PIN 160 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 15 +PIN -160 -288 LEFT 8 +PINATTR PinName Vin_sense +PINATTR SpiceOrder 16 +PIN 0 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3799.asy b/spice/copy/sym/PowerProducts/LT3799.asy new file mode 100755 index 0000000..a389908 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3799.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -336 160 336 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3799 +SYMATTR Prefix X +SYMATTR SpiceModel LT3799.sub +SYMATTR Value2 LT3799 +SYMATTR Description Offline Isolated Flyback LED Converter With Active PFC +PIN -160 96 LEFT 8 +PINATTR PinName Ctrl1 +PINATTR SpiceOrder 1 +PIN -160 192 LEFT 8 +PINATTR PinName Ctrl2 +PINATTR SpiceOrder 2 +PIN -160 288 LEFT 8 +PINATTR PinName Ctrl3 +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -160 -192 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN 160 192 RIGHT 8 +PINATTR PinName Comp+ +PINATTR SpiceOrder 7 +PIN 160 288 RIGHT 8 +PINATTR PinName Comp- +PINATTR SpiceOrder 8 +PIN 160 -192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN 160 -288 RIGHT 8 +PINATTR PinName DCM +PINATTR SpiceOrder 10 +PIN 0 -336 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN 160 -96 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 160 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 14 +PIN 160 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 15 +PIN -160 -288 LEFT 8 +PINATTR PinName Vin_sense +PINATTR SpiceOrder 16 +PIN 0 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3800.asy b/spice/copy/sym/PowerProducts/LT3800.asy new file mode 100755 index 0000000..65de3be --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3800.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -240 192 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -73 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT3800 +SYMATTR Prefix X +SYMATTR SpiceModel LT3800.sub +SYMATTR Value2 LT3800 +SYMATTR Description High-Voltage Synchronous Current mode Step-Down Controller +PIN -64 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -192 -192 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -192 -112 LEFT 8 +PINATTR PinName Css +PINATTR SpiceOrder 4 +PIN -192 -32 LEFT 8 +PINATTR PinName Burst_EN +PINATTR SpiceOrder 5 +PIN -192 48 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -192 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN -192 208 LEFT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 192 208 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN 192 128 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 192 48 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 11 +PIN 64 -240 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 +PIN 192 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 192 -112 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 15 +PIN 192 -192 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 +PIN 0 256 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3825.asy b/spice/copy/sym/PowerProducts/LT3825.asy new file mode 100755 index 0000000..d5148ae --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3825.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value LT3825 +SYMATTR Prefix X +SYMATTR SpiceModel LT3825.sub +SYMATTR Value2 LT3825 +SYMATTR Description Isolated No-Opto Synchronous Flyback Controller with Wide Input Supply Range +PIN 176 0 RIGHT 8 +PINATTR PinName SG +PINATTR SpiceOrder 1 +PIN 64 -288 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -176 160 LEFT 8 +PINATTR PinName Ton +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName ENDLY +PINATTR SpiceOrder 4 +PIN -176 -160 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN -176 -240 LEFT 8 +PINATTR PinName SFST +PINATTR SpiceOrder 6 +PIN -176 -80 LEFT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN 176 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN 176 80 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -64 -288 TOP 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 10 +PIN 176 -80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 11 +PIN 176 -160 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 12 +PIN 176 240 RIGHT 8 +PINATTR PinName Ccmp +PINATTR SpiceOrder 13 +PIN -176 240 LEFT 8 +PINATTR PinName Rcmp +PINATTR SpiceOrder 14 +PIN -176 0 LEFT 8 +PINATTR PinName PGDLY +PINATTR SpiceOrder 15 +PIN 176 -240 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3837.asy b/spice/copy/sym/PowerProducts/LT3837.asy new file mode 100755 index 0000000..ca4dd62 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3837.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LT3837 +SYMATTR Prefix X +SYMATTR SpiceModel LT3837.sub +SYMATTR Value2 LT3837 +SYMATTR Description Isolated No-Opto Synchronous Flyback Controller +PIN 176 0 RIGHT 8 +PINATTR PinName SG +PINATTR SpiceOrder 1 +PIN 80 -288 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -176 240 LEFT 8 +PINATTR PinName Ton +PINATTR SpiceOrder 3 +PIN -176 160 LEFT 8 +PINATTR PinName ENDLY +PINATTR SpiceOrder 4 +PIN -176 -160 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN -176 -80 LEFT 8 +PINATTR PinName SFST +PINATTR SpiceOrder 6 +PIN -176 0 LEFT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN -176 -240 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN 176 240 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -80 -288 TOP 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 10 +PIN 176 -80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 11 +PIN 176 -160 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName Ccmp +PINATTR SpiceOrder 13 +PIN 176 80 RIGHT 8 +PINATTR PinName Rcmp +PINATTR SpiceOrder 14 +PIN -176 80 LEFT 8 +PINATTR PinName PGDLY +PINATTR SpiceOrder 15 +PIN 176 -240 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3840.asy b/spice/copy/sym/PowerProducts/LT3840.asy new file mode 100755 index 0000000..4d9eaf3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3840.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -544 176 544 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT3840 +SYMATTR Prefix X +SYMATTR SpiceModel LT3840.sub +SYMATTR Value2 LT3840 +SYMATTR Description Wide Input Range Synchronous Regulator Controller with Accurate Current Limit \n\nNote: SYNC function is not modeled +PIN 0 -544 TOP 8 +PINATTR PinName AUXSW1 +PINATTR SpiceOrder 1 +PIN 176 384 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN -176 -288 LEFT 8 +PINATTR PinName AUXVin +PINATTR SpiceOrder 3 +PIN -176 288 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 480 LEFT 8 +PINATTR PinName TK/SS +PINATTR SpiceOrder 6 +PIN 176 288 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -176 384 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 +PIN -176 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -176 192 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 10 +PIN -176 -96 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 11 +PIN -176 -192 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 12 +PIN -176 -480 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 13 +PIN -176 -384 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 14 +PIN 176 480 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 15 +PIN -112 544 BOTTOM 8 +PINATTR PinName IMON +PINATTR SpiceOrder 16 +PIN 112 544 BOTTOM 8 +PINATTR PinName ICTRL +PINATTR SpiceOrder 17 +PIN 0 544 BOTTOM 8 +PINATTR PinName IComp +PINATTR SpiceOrder 18 +PIN 176 96 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 19 +PIN 176 192 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 20 +PIN 176 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 21 +PIN 176 -288 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 22 +PIN 176 -384 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 23 +PIN 176 0 RIGHT 8 +PINATTR PinName BGRTN +PINATTR SpiceOrder 24 +PIN 176 -96 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 25 +PIN 176 -480 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 26 +PIN 112 -544 TOP 8 +PINATTR PinName AUXSW2 +PINATTR SpiceOrder 27 +PIN -112 -544 TOP 8 +PINATTR PinName AUXBST +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3844.asy b/spice/copy/sym/PowerProducts/LT3844.asy new file mode 100755 index 0000000..a9e28d0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3844.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -288 192 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT3844 +SYMATTR Prefix X +SYMATTR SpiceModel LT3844.sub +SYMATTR Value2 LT3844 +SYMATTR Description High-Voltage Current Mode Switching Regulator Controller with Programmable Operating Frequency +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -192 -240 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -192 -144 LEFT 8 +PINATTR PinName Css +PINATTR SpiceOrder 3 +PIN -192 -48 LEFT 8 +PINATTR PinName Burst_EN +PINATTR SpiceOrder 4 +PIN -192 240 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -192 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -192 48 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 8 +PIN -64 288 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN 192 240 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 10 +PIN 192 144 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 11 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 192 -240 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 13 +PIN 192 48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 192 -48 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 15 +PIN 192 -144 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3845.asy b/spice/copy/sym/PowerProducts/LT3845.asy new file mode 100755 index 0000000..ac90d1b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3845.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -240 192 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -73 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT3845 +SYMATTR Prefix X +SYMATTR SpiceModel LT3845.sub +SYMATTR Value2 LT3845 +SYMATTR Description High-Voltage Synchronous Current mode Step-Down Controller with Adjustable Operating Frequency +PIN -64 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -192 -192 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -192 -112 LEFT 8 +PINATTR PinName Css +PINATTR SpiceOrder 3 +PIN -192 -32 LEFT 8 +PINATTR PinName Burst_EN +PINATTR SpiceOrder 4 +PIN -192 208 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -192 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -192 48 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 8 +PIN 192 208 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 9 +PIN 192 128 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 10 +PIN 64 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 11 +PIN 192 48 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 12 +PIN 64 -240 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 13 +PIN 192 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 192 -112 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 15 +PIN 192 -192 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 +PIN -64 256 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3845A.asy b/spice/copy/sym/PowerProducts/LT3845A.asy new file mode 100755 index 0000000..7b76639 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3845A.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -240 192 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -73 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT3845A +SYMATTR Prefix X +SYMATTR SpiceModel LT3845A.sub +SYMATTR Value2 LT3845A +SYMATTR Description High-Voltage Synchronous Current mode Step-Down Controller with Adjustable Operating Frequency +PIN -64 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -192 -192 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -192 -112 LEFT 8 +PINATTR PinName Css +PINATTR SpiceOrder 3 +PIN -192 -32 LEFT 8 +PINATTR PinName Burst_EN +PINATTR SpiceOrder 4 +PIN -192 208 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -192 128 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN -192 48 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 8 +PIN 192 208 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 9 +PIN 192 128 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 10 +PIN 64 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 11 +PIN 192 48 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 12 +PIN 64 -240 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 13 +PIN 192 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 192 -112 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 15 +PIN 192 -192 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 +PIN -64 256 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3905.asy b/spice/copy/sym/PowerProducts/LT3905.asy new file mode 100755 index 0000000..4bf0c59 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3905.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -304 160 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3905 +SYMATTR Prefix X +SYMATTR SpiceModel LT3905.sub +SYMATTR Value2 LT3905 +SYMATTR Description Boost DC/DC Converter with APD Current Monitor +PIN -160 144 LEFT 8 +PINATTR PinName _ILIM +PINATTR SpiceOrder 1 +PIN 160 240 RIGHT 8 +PINATTR PinName LOS_MON +PINATTR SpiceOrder 2 +PIN 160 144 RIGHT 8 +PINATTR PinName LIM_MON +PINATTR SpiceOrder 3 +PIN -160 240 LEFT 8 +PINATTR PinName MON +PINATTR SpiceOrder 4 +PIN 160 48 RIGHT 8 +PINATTR PinName APD +PINATTR SpiceOrder 5 +PIN 160 -48 RIGHT 8 +PINATTR PinName MonIn +PINATTR SpiceOrder 6 +PIN 64 -304 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 160 -240 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 64 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -64 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -160 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 11 +PIN -160 -48 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 12 +PIN -160 48 LEFT 8 +PINATTR PinName LOS +PINATTR SpiceOrder 13 +PIN -160 -144 LEFT 8 +PINATTR PinName LOS_ADJ +PINATTR SpiceOrder 14 +PIN 160 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 15 +PIN -64 304 BOTTOM 8 +PINATTR PinName Fsel +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3909.asy b/spice/copy/sym/PowerProducts/LT3909.asy new file mode 100755 index 0000000..f99ab1e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3909.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3909 +SYMATTR Prefix X +SYMATTR SpiceModel LT3909.sub +SYMATTR Value2 LT3909 +SYMATTR Description 2-String x 60mA, 2MHz Step-Up LED Driver with +/-2% Current Matching +PIN -96 208 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 1 +PIN -160 -112 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -160 -32 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 3 +PIN 96 208 BOTTOM 8 +PINATTR PinName Iset +PINATTR SpiceOrder 4 +PIN -160 128 LEFT 8 +PINATTR PinName Ctrl +PINATTR SpiceOrder 5 +PIN 160 -112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -160 48 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 7 +PIN 160 128 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 8 +PIN 160 48 RIGHT 8 +PINATTR PinName LED2 +PINATTR SpiceOrder 9 +PIN 160 -32 RIGHT 8 +PINATTR PinName LED1 +PINATTR SpiceOrder 10 +PIN 64 -192 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 11 +PIN -64 -192 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 12 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT3922-1.asy b/spice/copy/sym/PowerProducts/LT3922-1.asy new file mode 100755 index 0000000..519a9ff --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3922-1.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -352 208 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -119 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value LT3922-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3922-1.sub +SYMATTR Value2 LT3922-1 +SYMATTR Description 36V, 2A Synchronous Step-Up LED Driver +PIN -64 -352 TOP 6 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 64 -352 TOP 6 +PINATTR PinName BST +PINATTR SpiceOrder 2 +PIN -208 160 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -208 -320 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -208 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 5 +PIN -208 -160 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 6 +PIN -208 0 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 7 +PIN -208 80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 8 +PIN 208 -160 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 9 +PIN 208 -80 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 10 +PIN 64 352 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 208 -240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 208 160 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 13 +PIN 208 80 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 14 +PIN -208 240 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 15 +PIN -64 352 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 16 +PIN -208 -80 LEFT 8 +PINATTR PinName SYNC/SPRD +PINATTR SpiceOrder 17 +PIN 208 240 RIGHT 8 +PINATTR PinName RP +PINATTR SpiceOrder 18 +PIN -208 320 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 19 +PIN 208 0 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 20 +PIN 208 -320 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 21 +PIN 208 320 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 22 diff --git a/spice/copy/sym/PowerProducts/LT3922.asy b/spice/copy/sym/PowerProducts/LT3922.asy new file mode 100755 index 0000000..d1522e6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3922.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -352 208 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -119 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value LT3922 +SYMATTR Prefix X +SYMATTR SpiceModel LT3922.sub +SYMATTR Value2 LT3922 +SYMATTR Description 36V, 2A Synchronous Step-Up LED Driver +PIN -64 -352 TOP 6 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 64 -352 TOP 6 +PINATTR PinName BST +PINATTR SpiceOrder 2 +PIN -208 160 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -208 -320 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -208 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 5 +PIN -208 -160 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 6 +PIN -208 0 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 7 +PIN -208 80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 8 +PIN 208 -160 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 9 +PIN 208 -80 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 10 +PIN 64 352 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 208 -240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 208 160 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 13 +PIN 208 80 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 14 +PIN -208 240 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 15 +PIN -64 352 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 16 +PIN -208 -80 LEFT 8 +PINATTR PinName SYNC/SPRD +PINATTR SpiceOrder 17 +PIN 208 240 RIGHT 8 +PINATTR PinName RP +PINATTR SpiceOrder 18 +PIN -208 320 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 19 +PIN 208 0 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 20 +PIN 208 -320 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 21 +PIN 208 320 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 22 diff --git a/spice/copy/sym/PowerProducts/LT3932-1.asy b/spice/copy/sym/PowerProducts/LT3932-1.asy new file mode 100755 index 0000000..652687d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3932-1.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -352 208 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -119 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value LT3932-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT3932-1.sub +SYMATTR Value2 LT3932-1 +SYMATTR Description 36V, 2A Synchronous Step-Down LED Driver +PIN 0 -352 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 1 +PIN 208 -320 RIGHT 6 +PINATTR PinName BST +PINATTR SpiceOrder 2 +PIN 208 -240 RIGHT 6 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 208 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 208 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 208 0 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 6 +PIN 208 80 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 7 +PIN 208 160 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 8 +PIN 208 240 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 9 +PIN 208 320 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 80 352 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN -64 352 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -208 320 LEFT 8 +PINATTR PinName RP +PINATTR SpiceOrder 13 +PIN -208 240 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN -208 160 LEFT 8 +PINATTR PinName SYNC/SPRD +PINATTR SpiceOrder 15 +PIN -208 80 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 16 +PIN -208 0 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 17 +PIN -208 -80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 18 +PIN -208 -160 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 19 +PIN -208 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 20 +PIN -208 -320 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT3932.asy b/spice/copy/sym/PowerProducts/LT3932.asy new file mode 100755 index 0000000..959b116 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3932.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -352 208 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -119 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value LT3932 +SYMATTR Prefix X +SYMATTR SpiceModel LT3932.sub +SYMATTR Value2 LT3932 +SYMATTR Description 36V, 2A Synchronous Step-Down LED Driver +PIN -208 -160 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 19 +PIN -208 240 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN 80 352 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN 208 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 208 0 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 6 +PIN 208 80 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 7 +PIN 208 240 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 9 +PIN -208 80 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 16 +PIN -208 320 LEFT 8 +PINATTR PinName RP +PINATTR SpiceOrder 13 +PIN -64 352 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -208 160 LEFT 8 +PINATTR PinName SYNC/SPRD +PINATTR SpiceOrder 15 +PIN -208 0 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 17 +PIN 208 160 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 8 +PIN 208 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 208 320 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -208 -320 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 +PIN 208 -240 RIGHT 6 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 208 -320 RIGHT 6 +PINATTR PinName BST +PINATTR SpiceOrder 2 +PIN 0 -352 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 1 +PIN -208 -80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 18 +PIN -208 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT3934S.asy b/spice/copy/sym/PowerProducts/LT3934S.asy new file mode 100755 index 0000000..f8b5ba1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3934S.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -352 208 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -119 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value LT3934S +SYMATTR Prefix X +SYMATTR SpiceModel LT3934S.sub +SYMATTR Value2 LT3934S +SYMATTR Description 36V, 4A Synchronous Step-Down LED Driver +PIN 0 -352 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 1 +PIN 208 -320 RIGHT 6 +PINATTR PinName BST +PINATTR SpiceOrder 2 +PIN 208 -240 RIGHT 6 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 208 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 208 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 208 0 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 6 +PIN 208 80 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 7 +PIN 208 160 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 8 +PIN 208 240 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 9 +PIN 208 320 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 80 352 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN -64 352 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -208 320 LEFT 8 +PINATTR PinName RP +PINATTR SpiceOrder 13 +PIN -208 240 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN -208 160 LEFT 8 +PINATTR PinName SYNC/SPRD +PINATTR SpiceOrder 15 +PIN -208 80 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 16 +PIN -208 0 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 17 +PIN -208 -80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 18 +PIN -208 -160 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 19 +PIN -208 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 20 +PIN -208 -320 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT3935.asy b/spice/copy/sym/PowerProducts/LT3935.asy new file mode 100755 index 0000000..1ef2d7b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3935.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -352 208 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -119 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value LT3935 +SYMATTR Prefix X +SYMATTR SpiceModel LT3935.sub +SYMATTR Value2 LT3935 +SYMATTR Description 36V, 4A Synchronous Step-Down LED Driver +PIN 0 -352 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 1 +PIN 208 -320 RIGHT 6 +PINATTR PinName BST +PINATTR SpiceOrder 2 +PIN 208 -240 RIGHT 6 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 208 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 208 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 208 0 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 6 +PIN 208 80 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 7 +PIN 208 240 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 9 +PIN 208 320 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 80 352 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 +PIN -64 352 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -208 320 LEFT 8 +PINATTR PinName RP +PINATTR SpiceOrder 13 +PIN -208 240 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN -208 160 LEFT 8 +PINATTR PinName SYNC/SPRD +PINATTR SpiceOrder 15 +PIN -208 80 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 16 +PIN -208 0 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 17 +PIN -208 -80 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 18 +PIN -208 -160 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 19 +PIN -208 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 20 +PIN -208 -320 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT3942.asy b/spice/copy/sym/PowerProducts/LT3942.asy new file mode 100755 index 0000000..7112361 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3942.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 289 529 -304 -496 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -304 Center 2 +SYMATTR Value LT3942 +SYMATTR Prefix X +SYMATTR SpiceModel LT3942.sub +SYMATTR Value2 LT3942 +SYMATTR Description 36V 2A Synchronous Buck-Boost Controller and LED Driver +PIN -304 -416 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 1 +PIN -304 -336 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -304 -32 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 4 +PIN -304 -256 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 5 +PIN -304 -144 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 6 +PIN -304 368 LEFT 8 +PINATTR PinName RP +PINATTR SpiceOrder 7 +PIN -304 288 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 8 +PIN -304 128 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 9 +PIN -304 208 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 10 +PIN 288 -144 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 11 +PIN 288 -64 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 12 +PIN 288 128 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 13 +PIN -304 48 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 14 +PIN 288 288 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 15 +PIN 288 -304 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN 288 208 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 17 +PIN 288 368 RIGHT 8 +PINATTR PinName RT +PINATTR SpiceOrder 18 +PIN 288 448 RIGHT 8 +PINATTR PinName SYNC/SPRD +PINATTR SpiceOrder 19 +PIN 288 48 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 20 +PIN 288 -416 RIGHT 8 +PINATTR PinName PVout +PINATTR SpiceOrder 21 +PIN 64 -496 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 23 +PIN 192 -496 TOP 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 25 +PIN -208 -496 TOP 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 26 +PIN -80 -496 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 27 +PIN -304 448 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LT3950.asy b/spice/copy/sym/PowerProducts/LT3950.asy new file mode 100755 index 0000000..69b57fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3950.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -320 192 352 +TEXT 0 1 Center 2 LT +WINDOW 0 0 -63 Center 2 +WINDOW 3 3 83 Center 2 +SYMATTR Value LT3950 +SYMATTR Prefix X +SYMATTR SpiceModel LT3950.sub +SYMATTR Value2 LT3950 +SYMATTR Description 60V,1.5A LED Driver with Internal Exponential Scale Dimming +PIN 192 -160 RIGHT 8 +PINATTR PinName Isp +PINATTR SpiceOrder 1 +PIN 192 -48 RIGHT 8 +PINATTR PinName Isn +PINATTR SpiceOrder 2 +PIN 192 64 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 3 +PIN 128 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -192 -48 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN 0 -320 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 192 -272 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 192 176 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 +PIN -192 176 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 9 +PIN -192 -160 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 10 +PIN -128 352 BOTTOM 8 +PINATTR PinName RP +PINATTR SpiceOrder 11 +PIN 0 352 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -192 -272 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN -192 288 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 +PIN -192 64 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 15 +PIN 192 288 RIGHT 8 +PINATTR PinName SYNC/SPRD +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT3952.asy b/spice/copy/sym/PowerProducts/LT3952.asy new file mode 100755 index 0000000..f2f2425 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3952.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -400 208 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LT3952 +SYMATTR Prefix X +SYMATTR SpiceModel LT3952.sub +SYMATTR Value2 LT3952 +SYMATTR Description 60V LED Driver with 4A Switch Current +PIN 208 -48 RIGHT 8 +PINATTR PinName Isp +PINATTR SpiceOrder 1 +PIN 208 48 RIGHT 8 +PINATTR PinName Isn +PINATTR SpiceOrder 2 +PIN 208 144 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 3 +PIN 208 -240 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 400 BOTTOM 8 +PINATTR PinName Ismon +PINATTR SpiceOrder 5 +PIN 208 -336 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 208 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -48 400 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 +PIN -208 -144 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 9 +PIN -208 -240 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 10 +PIN 144 400 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN 48 400 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -208 -48 LEFT 8 +PINATTR PinName DIM +PINATTR SpiceOrder 13 +PIN -208 48 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 +PIN -208 240 LEFT 8 +PINATTR PinName _ShortLED +PINATTR SpiceOrder 15 +PIN -208 336 LEFT 8 +PINATTR PinName _OpenLED +PINATTR SpiceOrder 16 +PIN 208 240 RIGHT 8 +PINATTR PinName SYNC/SPRD +PINATTR SpiceOrder 17 +PIN 208 336 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 +PIN -48 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 23 +PIN -144 -400 TOP 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 24 +PIN -208 -336 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 25 +PIN 144 -400 TOP 8 +PINATTR PinName IVINN +PINATTR SpiceOrder 26 +PIN 48 -400 TOP 8 +PINATTR PinName IVINP +PINATTR SpiceOrder 27 +PIN -208 144 LEFT 8 +PINATTR PinName IVINCOMP +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3952A.asy b/spice/copy/sym/PowerProducts/LT3952A.asy new file mode 100755 index 0000000..38c0926 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3952A.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -416 208 416 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT3952A +SYMATTR Prefix X +SYMATTR SpiceModel LT3952A.sub +SYMATTR Value2 LT3952A +SYMATTR Description 60V LED Driver with 4A Switch Current +PIN 208 -48 RIGHT 8 +PINATTR PinName Isp +PINATTR SpiceOrder 1 +PIN 208 48 RIGHT 8 +PINATTR PinName Isn +PINATTR SpiceOrder 2 +PIN 208 144 RIGHT 8 +PINATTR PinName Tg +PINATTR SpiceOrder 3 +PIN 208 -240 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 416 BOTTOM 8 +PINATTR PinName Ismon +PINATTR SpiceOrder 5 +PIN 208 -336 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 208 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -48 416 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 +PIN -208 -144 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 9 +PIN -208 -240 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 10 +PIN 144 416 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN 48 416 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 12 +PIN -208 -48 LEFT 8 +PINATTR PinName DIM +PINATTR SpiceOrder 13 +PIN -208 48 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 +PIN -208 240 LEFT 8 +PINATTR PinName _ShortLED +PINATTR SpiceOrder 15 +PIN -208 336 LEFT 8 +PINATTR PinName _OpenLED +PINATTR SpiceOrder 16 +PIN 208 240 RIGHT 8 +PINATTR PinName Sync/Sprd +PINATTR SpiceOrder 17 +PIN 208 336 RIGHT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 20 +PIN -48 -416 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 23 +PIN -144 -416 TOP 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 24 +PIN -208 -336 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 25 +PIN 144 -416 TOP 8 +PINATTR PinName IVinN +PINATTR SpiceOrder 26 +PIN 48 -416 TOP 8 +PINATTR PinName IVinP +PINATTR SpiceOrder 27 +PIN -208 144 LEFT 8 +PINATTR PinName IVinComp +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LT3954.asy b/spice/copy/sym/PowerProducts/LT3954.asy new file mode 100755 index 0000000..8b5ed9d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3954.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3954 +SYMATTR Prefix X +SYMATTR SpiceModel LT3954.sub +SYMATTR Value2 LT3954 +SYMATTR Description 40Vin LED Converter with Internal PWM Generator +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName _Vmode +PINATTR SpiceOrder 3 +PIN -176 160 LEFT 8 +PINATTR PinName DIM/SS +PINATTR SpiceOrder 4 +PIN -176 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN -176 96 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 -96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 32 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 -32 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN 176 160 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN -48 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 +PIN 176 96 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 18 +PIN 48 288 BOTTOM 8 +PINATTR PinName GNDK +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LT3955.asy b/spice/copy/sym/PowerProducts/LT3955.asy new file mode 100755 index 0000000..e4dfff8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3955.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3955 +SYMATTR Prefix X +SYMATTR SpiceModel LT3955.sub +SYMATTR Value2 LT3955 +SYMATTR Description 60Vin LED Converter with Internal PWM Generator +PIN -176 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 224 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName _Vmode +PINATTR SpiceOrder 3 +PIN -176 160 LEFT 8 +PINATTR PinName DIM/SS +PINATTR SpiceOrder 4 +PIN -176 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -224 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -224 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN -176 96 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 10 +PIN 176 224 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 -96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 32 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 -32 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN 176 160 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 -32 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN -48 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 +PIN 176 96 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 18 +PIN 48 288 BOTTOM 8 +PINATTR PinName GNDK +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LT3956.asy b/spice/copy/sym/PowerProducts/LT3956.asy new file mode 100755 index 0000000..a53bc70 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3956.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3956 +SYMATTR Prefix X +SYMATTR SpiceModel LT3956.sub +SYMATTR Value2 LT3956 +SYMATTR Description 80 Vin, 80 Vout Constant-Current, Constant-Voltage Converter +PIN -176 -80 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 1 +PIN -176 240 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 2 +PIN -176 -160 LEFT 8 +PINATTR PinName _VMODE +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN -176 -240 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 6 +PIN 176 -240 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 176 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 +PIN 176 240 RIGHT 8 +PINATTR PinName PWMout +PINATTR SpiceOrder 11 +PIN 176 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 13 +PIN 176 0 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN 176 160 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -176 0 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 16 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3957.asy b/spice/copy/sym/PowerProducts/LT3957.asy new file mode 100755 index 0000000..9a7a935 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3957.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3957 +SYMATTR Prefix X +SYMATTR SpiceModel LT3957.sub +SYMATTR Value2 LT3957 +SYMATTR Description Boost, Flyback, SEPIC and Inverting Controller with 5A, 40V Switch +PIN -160 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 144 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 64 -208 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense2 +PINATTR SpiceOrder 6 +PIN 160 -48 RIGHT 8 +PINATTR PinName Sense1 +PINATTR SpiceOrder 7 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN -64 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -64 208 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 64 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3957A.asy b/spice/copy/sym/PowerProducts/LT3957A.asy new file mode 100755 index 0000000..bdcee1f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3957A.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3957A +SYMATTR Prefix X +SYMATTR SpiceModel LT3957A.sub +SYMATTR Value2 LT3957A +SYMATTR Description Boost, Flyback, SEPIC and Inverting Controller with 5A, 40V Switch +PIN -160 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 144 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 64 -208 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense2 +PINATTR SpiceOrder 6 +PIN 160 -48 RIGHT 8 +PINATTR PinName Sense1 +PINATTR SpiceOrder 7 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN -64 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -64 208 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 64 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3958.asy b/spice/copy/sym/PowerProducts/LT3958.asy new file mode 100755 index 0000000..45ff167 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3958.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3958 +SYMATTR Prefix X +SYMATTR SpiceModel LT3958.sub +SYMATTR Value2 LT3958 +SYMATTR Description High Input Voltage Boost, Flyback, SEPIC and Inverting Controller +PIN -160 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 144 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 64 -208 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense2 +PINATTR SpiceOrder 6 +PIN 160 -48 RIGHT 8 +PINATTR PinName Sense1 +PINATTR SpiceOrder 7 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -160 -144 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN -64 -208 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -64 208 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 64 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT3959.asy b/spice/copy/sym/PowerProducts/LT3959.asy new file mode 100755 index 0000000..990a417 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3959.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3959 +SYMATTR Prefix X +SYMATTR SpiceModel LT3959.sub +SYMATTR Value2 LT3959 +SYMATTR Description Wide Input Voltage Range Boost/SEPIC/Inverting Converter with 6A, 40V Switch +PIN -160 192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 96 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName _Pgood +PINATTR SpiceOrder 6 +PIN 160 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 9 +PIN 160 0 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 10 +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -160 -192 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 12 +PIN 0 256 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 13 +PIN 160 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 160 192 RIGHT 8 +PINATTR PinName GNDK +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT3964.asy b/spice/copy/sym/PowerProducts/LT3964.asy new file mode 100755 index 0000000..36482a5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3964.asy @@ -0,0 +1,57 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 288 -144 -304 +TEXT 0 0 Center 2 LT +TEXT 1 65 Center 2 LT3964 +WINDOW 0 0 -64 Center 2 +WINDOW 3 -1 -217 Center 2 +SYMATTR Value ADIM=255 +SYMATTR SpiceModel LT3964 +SYMATTR Prefix X +SYMATTR Description Dual (single model) 36V, Synchronous 1.6A Buck LED Driver with I2C +SYMATTR ModelFile LT3964.sub +PIN 144 -96 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 144 -176 RIGHT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 3 +PIN 0 -304 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -144 -256 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 5 +PIN -144 128 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 8 +PIN 144 -16 RIGHT 8 +PINATTR PinName ISP1 +PINATTR SpiceOrder 9 +PIN 144 144 RIGHT 8 +PINATTR PinName ISN1 +PINATTR SpiceOrder 10 +PIN 144 64 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 12 +PIN -144 -64 LEFT 8 +PINATTR PinName _Alert +PINATTR SpiceOrder 15 +PIN 144 -256 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 16 +PIN -144 224 LEFT 8 +PINATTR PinName Sync/CLK +PINATTR SpiceOrder 17 +PIN -144 -160 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 19 +PIN 144 224 RIGHT 8 +PINATTR PinName PWMTG1 +PINATTR SpiceOrder 20 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 22 diff --git a/spice/copy/sym/PowerProducts/LT3970-3.3.asy b/spice/copy/sym/PowerProducts/LT3970-3.3.asy new file mode 100755 index 0000000..7bfecdd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3970-3.3.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 48 Center 2 +SYMATTR Value LT3970-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3970-3.3.sub +SYMATTR Value2 LT3970-3.3 +SYMATTR Description 40V, 350mA Step-Down Regulator with 2.5µA Quiescent Current and Integrated Diodes, Fixed 3.3V output. +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -128 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 64 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 8 +PIN -128 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -128 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3970-5.asy b/spice/copy/sym/PowerProducts/LT3970-5.asy new file mode 100755 index 0000000..ad3a0b7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3970-5.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 48 Center 2 +SYMATTR Value LT3970-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3970-5.sub +SYMATTR Value2 LT3970-5 +SYMATTR Description 40V, 350mA Step-Down Regulator with 2.5µA Quiescent Current and Integrated Diodes, Fixed 5V output. +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -128 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 64 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 8 +PIN -128 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -128 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3970.asy b/spice/copy/sym/PowerProducts/LT3970.asy new file mode 100755 index 0000000..96568b2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3970.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3970 +SYMATTR Prefix X +SYMATTR SpiceModel LT3970.sub +SYMATTR Value2 LT3970 +SYMATTR Description 40V, 350mA Step-Down Regulator with 2.5µA Quiescent Current and Integrated Diodes +PIN 128 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -128 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 64 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 8 +PIN -128 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -128 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3971-3.3.asy b/spice/copy/sym/PowerProducts/LT3971-3.3.asy new file mode 100755 index 0000000..4686f37 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3971-3.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3971-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT3971-3.3.sub +SYMATTR Value2 LT3971-3.3 +SYMATTR Description 38V, 1.2A, 2MHz Step-Down Regulator with 2.8µA Quiescent Current\n\nNote: Sync pin is not modeled; Burst Mode is selected. +PIN 144 -96 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 144 192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -144 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3971-5.asy b/spice/copy/sym/PowerProducts/LT3971-5.asy new file mode 100755 index 0000000..18e3939 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3971-5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3971-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3971-5.sub +SYMATTR Value2 LT3971-5 +SYMATTR Description 38V, 1.2A, 2MHz Step-Down Regulator with 2.8µA Quiescent Current\n\nNote: Sync pin is not modeled; Burst Mode is selected. +PIN 144 -96 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 144 192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -144 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3971.asy b/spice/copy/sym/PowerProducts/LT3971.asy new file mode 100755 index 0000000..a44435b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3971.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3971 +SYMATTR Prefix X +SYMATTR SpiceModel LT3971.sub +SYMATTR Value2 LT3971 +SYMATTR Description 38V, 1.2A, 2MHz Step-Down Regulator with 2.8µA Quiescent Current\n\nNote: Sync pin is not modeled; Burst Mode is selected. +PIN 144 -96 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -144 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3971A-5.asy b/spice/copy/sym/PowerProducts/LT3971A-5.asy new file mode 100755 index 0000000..4627df1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3971A-5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3971A-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT3971-5.sub +SYMATTR Value2 LT3971-5 +SYMATTR Description 38V, 1.2A, 2MHz Step-Down Regulator with 2.2µA Quiescent Current\n\nNote: Sync pin is not modeled; Burst Mode is selected. +PIN 144 -96 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 144 192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -144 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3971A.asy b/spice/copy/sym/PowerProducts/LT3971A.asy new file mode 100755 index 0000000..80277e8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3971A.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3971A +SYMATTR Prefix X +SYMATTR SpiceModel LT3971.sub +SYMATTR Value2 LT3971 +SYMATTR Description 38V, 1.2A, 2MHz Step-Down Regulator with 2.2µA Quiescent Current\n\nNote: Sync pin is not modeled; Burst Mode is selected. +PIN 144 -96 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -144 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3972.asy b/spice/copy/sym/PowerProducts/LT3972.asy new file mode 100755 index 0000000..fae5674 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3972.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT3972 +SYMATTR Prefix X +SYMATTR SpiceModel LT3972.sub +SYMATTR Value2 LT3972 +SYMATTR Description 33V, 3.5A, 2.4MHz Step-Down Switching Regulator with 75µA Quiescent Current +PIN 160 -128 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 160 32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -160 112 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -160 -48 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -160 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3973.asy b/spice/copy/sym/PowerProducts/LT3973.asy new file mode 100755 index 0000000..c1c119a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3973.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -208 128 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3973 +SYMATTR Prefix X +SYMATTR SpiceModel LT3973.sub +SYMATTR Value2 LT3973 +SYMATTR Description 42V, 750mA Step-Down Regulator with 2.5µA Quiescent Current and Integrated Diodes +PIN 128 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -128 -48 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 3 +PIN -128 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 0 -208 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 128 -48 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 8 +PIN -128 48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -128 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 128 48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/PowerProducts/LT3975.asy b/spice/copy/sym/PowerProducts/LT3975.asy new file mode 100755 index 0000000..5d46b44 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3975.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3975 +SYMATTR Prefix X +SYMATTR SpiceModel LT3975.sub +SYMATTR Value2 LT3975 +SYMATTR Description 42V, 2.5A, 2MHz Step-Down Switching Regulator with 2.7µA Quiescent Current\n\nNote: Sync pin is not modeled; Burst Mode is selected. +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN 144 -96 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 13 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 14 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN -144 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3976.asy b/spice/copy/sym/PowerProducts/LT3976.asy new file mode 100755 index 0000000..7741027 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3976.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3976 +SYMATTR Prefix X +SYMATTR SpiceModel LT3976.sub +SYMATTR Value2 LT3976 +SYMATTR Description 42V, 5A, 2MHz Step-Down Switching Regulator with 3.3µA Quiescent Current\n\nNote: Sync pin is not modeled; Burst Mode is selected. +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN 144 -96 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 13 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 14 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN -144 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3980.asy b/spice/copy/sym/PowerProducts/LT3980.asy new file mode 100755 index 0000000..40ab2fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3980.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3980 +SYMATTR Prefix X +SYMATTR SpiceModel LT3980.sub +SYMATTR Value2 LT3980 +SYMATTR Description 58V, 2A, 2.4MHz Step-Down Switching Regulator with 85µA Quiescent Current +PIN 144 -192 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 144 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN -144 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -144 192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3988.asy b/spice/copy/sym/PowerProducts/LT3988.asy new file mode 100755 index 0000000..9b9d5db --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3988.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -272 208 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LT3988 +SYMATTR Prefix X +SYMATTR SpiceModel LT3988.sub +SYMATTR Value2 LT3988 +SYMATTR Description Dual 60v Monolithic 1A Step-Down Switching Regulator +PIN -208 32 LEFT 8 +PINATTR PinName DA1 +PINATTR SpiceOrder 1 +PIN -208 -48 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 2 +PIN -208 -128 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 3 +PIN 208 -208 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 4 +PIN -208 -208 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 5 +PIN 208 -128 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 6 +PIN 208 -48 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 7 +PIN 208 32 RIGHT 8 +PINATTR PinName DA2 +PINATTR SpiceOrder 8 +PIN 64 -272 TOP 6 +PINATTR PinName Vin2 +PINATTR SpiceOrder 9 +PIN 208 192 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 10 +PIN 208 112 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 11 +PIN 64 256 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 13 +PIN -208 112 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 14 +PIN -208 192 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 15 +PIN -64 -272 TOP 6 +PINATTR PinName Vin1 +PINATTR SpiceOrder 16 +PIN -64 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3990.asy b/spice/copy/sym/PowerProducts/LT3990.asy new file mode 100755 index 0000000..d5f863a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3990.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT3990 +SYMATTR Prefix X +SYMATTR SpiceModel LT3990.sub +SYMATTR Value2 LT3990 +SYMATTR Description 62V, 350mA Step-Down Regulator with 2.5µA Quiescent Current and Integrated Diodes +PIN 128 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -128 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 64 -160 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 8 +PIN -128 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -128 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT3991.asy b/spice/copy/sym/PowerProducts/LT3991.asy new file mode 100755 index 0000000..c09b763 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3991.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3991 +SYMATTR Prefix X +SYMATTR SpiceModel LT3991.sub +SYMATTR Value2 LT3991 +SYMATTR Description 55V, 1.2A, Step-Down Regulator with 2.8µA Quiescent Current\n\nNote: Sync pin is not modeled; Burst Mode is selected. +PIN 144 -96 RIGHT 8 +PINATTR PinName BD +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 9 +PIN -144 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT3992.asy b/spice/copy/sym/PowerProducts/LT3992.asy new file mode 100755 index 0000000..638b70e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3992.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -544 208 544 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT3992 +SYMATTR Prefix X +SYMATTR SpiceModel LT3992.sub +SYMATTR Value2 LT3992 +SYMATTR Description Monolithic Dual Tracking 3A Step-Down Switching Regulator +PIN 208 -384 RIGHT 8 +PINATTR PinName Bst1 +PINATTR SpiceOrder 1 +PIN 208 192 RIGHT 8 +PINATTR PinName CMPO1 +PINATTR SpiceOrder 2 +PIN 208 96 RIGHT 8 +PINATTR PinName CMPI1 +PINATTR SpiceOrder 3 +PIN 208 0 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN -208 0 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN -208 96 LEFT 8 +PINATTR PinName CMPI2 +PINATTR SpiceOrder 6 +PIN -208 192 LEFT 8 +PINATTR PinName CMPO2 +PINATTR SpiceOrder 7 +PIN -208 -384 LEFT 8 +PINATTR PinName Bst2 +PINATTR SpiceOrder 8 +PIN -208 -96 LEFT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 9 +PIN -208 -192 LEFT 8 +PINATTR PinName IND2 +PINATTR SpiceOrder 11 +PIN -208 -288 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 13 +PIN -96 -544 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 14 +PIN -208 -480 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 15 +PIN -208 288 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 16 +PIN -208 480 LEFT 8 +PINATTR PinName Ilim2 +PINATTR SpiceOrder 17 +PIN -208 384 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 18 +PIN 96 544 BOTTOM 8 +PINATTR PinName DIV +PINATTR SpiceOrder 19 +PIN 0 -544 TOP 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 21 +PIN -96 544 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 22 +PIN 208 384 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 23 +PIN 208 480 RIGHT 8 +PINATTR PinName Ilim1 +PINATTR SpiceOrder 24 +PIN 208 288 RIGHT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 25 +PIN 208 -480 RIGHT 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 26 +PIN 96 -544 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 27 +PIN 208 -288 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 28 +PIN 208 -192 RIGHT 8 +PINATTR PinName IND1 +PINATTR SpiceOrder 30 +PIN 208 -96 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 32 +PIN 0 544 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 33 diff --git a/spice/copy/sym/PowerProducts/LT3995.asy b/spice/copy/sym/PowerProducts/LT3995.asy new file mode 100755 index 0000000..83c4f08 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3995.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT3995 +SYMATTR Prefix X +SYMATTR SpiceModel LT3995.sub +SYMATTR Value2 LT3995 +SYMATTR Description 60V, 3A, 2MHz Step-Down Switching Regulator with 2.7µA Quiescent Current\n\nNote: Sync pin is not modeled; Burst Mode is selected. +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN 144 -96 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 144 0 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -144 -192 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 13 +PIN -144 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 14 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN -144 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT3999.asy b/spice/copy/sym/PowerProducts/LT3999.asy new file mode 100755 index 0000000..7df8a91 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT3999.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -256 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT3999 +SYMATTR Prefix X +SYMATTR SpiceModel LT3999.sub +SYMATTR Value2 LT3999 +SYMATTR Description Low Noise, 1A, 1MHz Push-Pull DC/DC Driver with Duty Cycle Control +PIN 144 -192 RIGHT 8 +PINATTR PinName SWA +PINATTR SpiceOrder 1 +PIN 144 192 RIGHT 8 +PINATTR PinName Rbias +PINATTR SpiceOrder 2 +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -144 -192 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName OVLO/DC +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName Rdc +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 8 +PIN -144 192 LEFT 8 +PINATTR PinName Ilim/SS +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName SWB +PINATTR SpiceOrder 10 +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT4180.asy b/spice/copy/sym/PowerProducts/LT4180.asy new file mode 100755 index 0000000..073beaa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4180.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -320 160 320 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT4180 +SYMATTR Prefix X +SYMATTR SpiceModel LT4180.sub +SYMATTR Value2 LT4180 +SYMATTR Description Virtual Remote Sense Controller\n\nNote: Sample/Track/Hold capacitors are internally modeled for compute speed. The model uses Chold4 only to program the Soft Correct rate. +PIN 160 288 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 1 +PIN -160 192 LEFT 8 +PINATTR PinName Drain +PINATTR SpiceOrder 2 +PIN -160 288 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 3 +PIN -160 96 LEFT 8 +PINATTR PinName Chold4 +PINATTR SpiceOrder 10 +PIN -160 -192 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 0 320 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 +PIN 160 -96 RIGHT 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 13 +PIN 160 -192 RIGHT 8 +PINATTR PinName Rosc +PINATTR SpiceOrder 14 +PIN -160 0 LEFT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 15 +PIN 160 192 RIGHT 8 +PINATTR PinName DIV2 +PINATTR SpiceOrder 16 +PIN 160 96 RIGHT 8 +PINATTR PinName DIV1 +PINATTR SpiceOrder 17 +PIN 160 0 RIGHT 8 +PINATTR PinName DIV0 +PINATTR SpiceOrder 18 +PIN -160 -96 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 20 +PIN -160 -288 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 21 +PIN 160 -288 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 22 +PIN 0 -320 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LT4220.asy b/spice/copy/sym/PowerProducts/LT4220.asy new file mode 100755 index 0000000..d294c12 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4220.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 334 240 -336 -192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4220 +SYMATTR Prefix X +SYMATTR SpiceModel LT4220.sub +SYMATTR Value2 LT4220 +SYMATTR Description Dual Supply Hot Swap Controller +PIN -208 240 BOTTOM 8 +PINATTR PinName VEE +PINATTR SpiceOrder 1 +PIN -64 240 BOTTOM 8 +PINATTR PinName SENSEK +PINATTR SpiceOrder 2 +PIN 80 240 BOTTOM 8 +PINATTR PinName SENSE- +PINATTR SpiceOrder 3 +PIN 224 240 BOTTOM 8 +PINATTR PinName GATE- +PINATTR SpiceOrder 4 +PIN 336 144 RIGHT 8 +PINATTR PinName FB- +PINATTR SpiceOrder 5 +PIN -336 144 LEFT 8 +PINATTR PinName ON- +PINATTR SpiceOrder 6 +PIN -208 -192 TOP 8 +PINATTR PinName TRACK +PINATTR SpiceOrder 7 +PIN -336 64 LEFT 8 +PINATTR PinName TIMER +PINATTR SpiceOrder 8 +PIN 336 64 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 336 -96 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 10 +PIN -336 -96 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 11 +PIN -336 -16 LEFT 8 +PINATTR PinName ON+ +PINATTR SpiceOrder 12 +PIN 336 -16 RIGHT 8 +PINATTR PinName FB+ +PINATTR SpiceOrder 13 +PIN 224 -192 TOP 8 +PINATTR PinName GATE+ +PINATTR SpiceOrder 14 +PIN 80 -192 TOP 8 +PINATTR PinName SENSE+ +PINATTR SpiceOrder 15 +PIN -64 -192 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT4250H.asy b/spice/copy/sym/PowerProducts/LT4250H.asy new file mode 100755 index 0000000..e900e6c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4250H.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 288 160 -256 -143 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4250H +SYMATTR Prefix X +SYMATTR SpiceModel LT4250H.sub +SYMATTR Value2 LT4250H +SYMATTR Description Negative 48V Hot Swap Controller +PIN 288 0 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 1 +PIN -256 80 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -256 -80 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 3 +PIN -208 160 BOTTOM 8 +PINATTR PinName Vee +PINATTR SpiceOrder 4 +PIN -64 160 BOTTOM 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN 80 160 BOTTOM 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 224 160 BOTTOM 8 +PINATTR PinName Drain +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT4250L.asy b/spice/copy/sym/PowerProducts/LT4250L.asy new file mode 100755 index 0000000..c7b90e2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4250L.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 288 160 -256 -143 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4250L +SYMATTR Prefix X +SYMATTR SpiceModel LT4250L.sub +SYMATTR Value2 LT4250L +SYMATTR Description Negative 48V Hot Swap Controller +PIN 288 0 RIGHT 8 +PINATTR PinName _PWRGD +PINATTR SpiceOrder 1 +PIN -256 80 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -256 -80 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 3 +PIN -208 160 BOTTOM 8 +PINATTR PinName Vee +PINATTR SpiceOrder 4 +PIN -64 160 BOTTOM 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN 80 160 BOTTOM 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 224 160 BOTTOM 8 +PINATTR PinName Drain +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT4256-1.asy b/spice/copy/sym/PowerProducts/LT4256-1.asy new file mode 100755 index 0000000..c5506e2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4256-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4256-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT4256-1.sub +SYMATTR Value2 LT4256-1 +SYMATTR Description Positive High Voltage Hot Swap Controller +PIN -128 -64 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 1 +PIN 128 16 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 128 96 RIGHT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 96 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 64 -128 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -64 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT4256-2.asy b/spice/copy/sym/PowerProducts/LT4256-2.asy new file mode 100755 index 0000000..b70d7c6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4256-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4256-2 +SYMATTR Prefix X +SYMATTR SpiceModel LT4256-2.sub +SYMATTR Value2 LT4256-2 +SYMATTR Description Positive High Voltage Hot Swap Controller +PIN -128 -64 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 1 +PIN 128 16 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 128 96 RIGHT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 96 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 64 -128 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -64 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT4256-3.asy b/spice/copy/sym/PowerProducts/LT4256-3.asy new file mode 100755 index 0000000..7de2630 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4256-3.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 240 -144 -192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4256-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT4256-3.sub +SYMATTR Value2 LT4256-3 +SYMATTR Description Positive High Voltage Hot Swap Controller with Open-Circuit Detect +PIN -144 -96 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 1 +PIN -144 -16 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -144 64 LEFT 8 +PINATTR PinName Open +PINATTR SpiceOrder 4 +PIN 160 112 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 5 +PIN 160 192 RIGHT 8 +PINATTR PinName Retry +PINATTR SpiceOrder 7 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -144 160 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 9 +PIN 160 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 12 +PIN 160 -128 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 13 +PIN 64 -192 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 15 +PIN -64 -192 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT4275A.asy b/spice/copy/sym/PowerProducts/LT4275A.asy new file mode 100755 index 0000000..6304e8e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4275A.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 160 -192 -160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4275A +SYMATTR Prefix X +SYMATTR SpiceModel LT4275A.sub +SYMATTR Value2 LT4275A +SYMATTR Description LTPoE++/PoE+/PoE PD Controller +PIN -192 -128 LEFT 8 +PINATTR PinName _IEEEUVLO +PINATTR SpiceOrder 1 +PIN -192 -64 LEFT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 2 +PIN -192 0 LEFT 8 +PINATTR PinName Rclass +PINATTR SpiceOrder 3 +PIN -192 64 LEFT 8 +PINATTR PinName Rclass++ +PINATTR SpiceOrder 4 +PIN -192 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 192 128 RIGHT 8 +PINATTR PinName _T2P +PINATTR SpiceOrder 6 +PIN 192 64 RIGHT 8 +PINATTR PinName pwrGD +PINATTR SpiceOrder 7 +PIN 192 0 RIGHT 8 +PINATTR PinName HSsrc +PINATTR SpiceOrder 8 +PIN 192 -64 RIGHT 8 +PINATTR PinName HSgate +PINATTR SpiceOrder 9 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vport +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT4276A.asy b/spice/copy/sym/PowerProducts/LT4276A.asy new file mode 100755 index 0000000..bcb039d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4276A.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 464 256 -464 -256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4276A +SYMATTR Prefix X +SYMATTR SpiceModel LT4276A.sub +SYMATTR Value2 LT4276A +SYMATTR Description LTPoE++/PoE+/PoE PD Forward/Flyback Controller (fault logic not implemented due to 86ms delay) +PIN 464 192 RIGHT 8 +PINATTR PinName FB31 +PINATTR SpiceOrder 14 +PIN 464 112 RIGHT 8 +PINATTR PinName ITHB +PINATTR SpiceOrder 13 +PIN 464 32 RIGHT 8 +PINATTR PinName SG +PINATTR SpiceOrder 18 +PIN 464 -48 RIGHT 8 +PINATTR PinName ISEN- +PINATTR SpiceOrder 16 +PIN 464 -128 RIGHT 8 +PINATTR PinName ISEN+ +PINATTR SpiceOrder 17 +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 464 -208 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 20 +PIN -256 -256 TOP 8 +PINATTR PinName Vport +PINATTR SpiceOrder 28 +PIN -464 -208 LEFT 8 +PINATTR PinName Rclass +PINATTR SpiceOrder 4 +PIN -464 -128 LEFT 8 +PINATTR PinName Rclass++ +PINATTR SpiceOrder 3 +PIN -464 -48 LEFT 8 +PINATTR PinName SFST +PINATTR SpiceOrder 11 +PIN -464 32 LEFT 8 +PINATTR PinName Rosc +PINATTR SpiceOrder 10 +PIN -464 112 LEFT 8 +PINATTR PinName RLDCMP +PINATTR SpiceOrder 15 +PIN -464 192 LEFT 8 +PINATTR PinName T2P +PINATTR SpiceOrder 5 +PIN -336 -256 TOP 8 +PINATTR PinName AUX +PINATTR SpiceOrder 2 +PIN -160 -256 TOP 8 +PINATTR PinName HSgate +PINATTR SpiceOrder 26 +PIN -48 -256 TOP 8 +PINATTR PinName HSsrc +PINATTR SpiceOrder 25 +PIN 144 -256 TOP 8 +PINATTR PinName SWVcc +PINATTR SpiceOrder 23 +PIN 48 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN 240 -256 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 +PIN 352 -256 TOP 8 +PINATTR PinName FFSDLY +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT4295.asy b/spice/copy/sym/PowerProducts/LT4295.asy new file mode 100755 index 0000000..a7d58db --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4295.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 464 256 -464 -256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4295 +SYMATTR Prefix X +SYMATTR SpiceModel LT4295.sub +SYMATTR Value2 LT4295 +SYMATTR Description IEEE 802.3bt PD Interface with Forward/Flyback Controller (fault logic not implemented due to 86ms delay) +PIN 464 192 RIGHT 8 +PINATTR PinName FB31 +PINATTR SpiceOrder 14 +PIN 464 112 RIGHT 8 +PINATTR PinName ITHB +PINATTR SpiceOrder 13 +PIN 464 32 RIGHT 8 +PINATTR PinName SG +PINATTR SpiceOrder 18 +PIN 464 -48 RIGHT 8 +PINATTR PinName ISEN- +PINATTR SpiceOrder 16 +PIN 464 -128 RIGHT 8 +PINATTR PinName ISEN+ +PINATTR SpiceOrder 17 +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 464 -208 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 20 +PIN -256 -256 TOP 8 +PINATTR PinName Vport +PINATTR SpiceOrder 28 +PIN -464 -208 LEFT 8 +PINATTR PinName Rclass +PINATTR SpiceOrder 4 +PIN -464 -128 LEFT 8 +PINATTR PinName Rclass++ +PINATTR SpiceOrder 3 +PIN -464 -48 LEFT 8 +PINATTR PinName SFST +PINATTR SpiceOrder 11 +PIN -464 32 LEFT 8 +PINATTR PinName Rosc +PINATTR SpiceOrder 10 +PIN -464 112 LEFT 8 +PINATTR PinName RLDCMP +PINATTR SpiceOrder 15 +PIN -464 192 LEFT 8 +PINATTR PinName T2P +PINATTR SpiceOrder 5 +PIN -336 -256 TOP 8 +PINATTR PinName AUX +PINATTR SpiceOrder 2 +PIN -160 -256 TOP 8 +PINATTR PinName HSgate +PINATTR SpiceOrder 26 +PIN -48 -256 TOP 8 +PINATTR PinName HSsrc +PINATTR SpiceOrder 25 +PIN 144 -256 TOP 8 +PINATTR PinName SWVcc +PINATTR SpiceOrder 23 +PIN 48 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN 240 -256 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 +PIN 352 -256 TOP 8 +PINATTR PinName FFSDLY +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT4430.asy b/spice/copy/sym/PowerProducts/LT4430.asy new file mode 100755 index 0000000..ea7fb3a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT4430.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 128 +TEXT 0 8 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT4430 +SYMATTR Prefix X +SYMATTR SpiceModel LT4430.sub +SYMATTR Value2 LT4430 +SYMATTR Description Secondary-Side Optocoupler Driver +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 64 LEFT 8 +PINATTR PinName OC +PINATTR SpiceOrder 3 +PIN 128 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 128 64 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName OPTO +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT6105.asy b/spice/copy/sym/PowerProducts/LT6105.asy new file mode 100755 index 0000000..1e65eb4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT6105.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT6105 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LT6105 +SYMATTR Description Precision, Extended Input Range Current Sense Amplifier +PIN 80 -128 TOP 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -80 -128 TOP 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT6110.asy b/spice/copy/sym/PowerProducts/LT6110.asy new file mode 100755 index 0000000..e6ce532 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT6110.asy @@ -0,0 +1,87 @@ +Version 4 +SymbolType BLOCK +LINE Normal 144 -64 48 -64 +LINE Normal 96 14 144 -64 +LINE Normal 48 -64 96 14 +LINE Normal 87 -51 73 -51 +LINE Normal 119 -51 105 -51 +LINE Normal 96 64 96 14 +LINE Normal 80 -87 80 -64 +LINE Normal 112 -160 112 -64 +LINE Normal 80 -44 80 -58 +LINE Normal -30 56 -46 40 +LINE Normal -46 88 -30 72 +LINE Normal -30 80 -30 48 +LINE Normal -42 79 -46 88 +LINE Normal -37 84 -46 88 +LINE Normal -46 32 -46 40 +LINE Normal -46 88 -46 96 +LINE Normal -80 56 -96 40 +LINE Normal -96 88 -80 72 +LINE Normal -80 80 -80 48 +LINE Normal -96 88 -96 96 +LINE Normal -128 56 -144 40 +LINE Normal -144 88 -128 72 +LINE Normal -128 80 -128 48 +LINE Normal -144 0 -144 40 +LINE Normal 40 -111 48 -119 +LINE Normal 24 -127 40 -111 +LINE Normal 24 -127 8 -111 +LINE Normal -8 -127 8 -111 +LINE Normal -8 -127 -24 -111 +LINE Normal -40 -127 -24 -111 +LINE Normal 48 -119 48 -160 +LINE Normal -48 -119 -48 -160 +LINE Normal 0 64 0 32 +LINE Normal 0 32 -46 32 +LINE Normal -96 -160 -96 40 +LINE Normal -128 64 96 64 +LINE Normal -144 96 -46 96 +LINE Normal -144 0 -176 0 +LINE Normal -96 -87 80 -87 +LINE Normal -144 128 -144 88 +LINE Normal -48 -119 -40 -127 +LINE Normal -92 79 -96 88 +LINE Normal -87 84 -96 88 +LINE Normal -140 79 -144 88 +LINE Normal -135 84 -144 88 +LINE Normal -37 84 -42 79 +LINE Normal -87 84 -92 79 +LINE Normal -135 84 -140 79 +RECTANGLE Normal 176 128 -176 -160 +TEXT 0 0 Center 2 LT +TEXT 1 110 Center 2 V- +TEXT -44 -144 Left 2 V+ +TEXT -144 -4 Bottom 2 IOUT +TEXT 52 -144 Left 2 RS +TEXT 117 -144 Left 2 -IN +TEXT -107 99 Top 2 IMON +TEXT -96 -141 Left 2 +IN +WINDOW 3 0 -40 Center 2 +WINDOW 0 0 -160 Bottom 2 +SYMATTR Value LT6110 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5.lib +SYMATTR Value2 LT6110 +SYMATTR Description Cable/Wire Drop Compensator +PIN -96 -160 NONE 8 +PINATTR PinName +IN +PINATTR SpiceOrder 1 +PIN -48 -160 NONE 8 +PINATTR PinName V+ +PINATTR SpiceOrder 2 +PIN 48 -160 NONE 8 +PINATTR PinName RS +PINATTR SpiceOrder 3 +PIN 112 -160 NONE 8 +PINATTR PinName -IN +PINATTR SpiceOrder 4 +PIN 0 128 NONE 8 +PINATTR PinName V- +PINATTR SpiceOrder 5 +PIN -144 128 NONE 8 +PINATTR PinName IMON +PINATTR SpiceOrder 6 +PIN -176 0 NONE 8 +PINATTR PinName IOUT +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LT7101.asy b/spice/copy/sym/PowerProducts/LT7101.asy new file mode 100755 index 0000000..70a9bf9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT7101.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -384 192 336 +TEXT 0 -22 Center 2 LT +WINDOW 0 0 -184 Center 2 +WINDOW 3 0 135 Center 2 +SYMATTR Value LT7101 +SYMATTR Prefix X +SYMATTR Description 105V, 1A Low EMI Synchronous Step-Down Regulator with Fast Current Programming +SYMATTR SpiceModel LT7101.sub +SYMATTR Value2 LT7101 +PIN -192 -224 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 3 +PIN -64 336 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN -192 -144 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 7 +PIN -192 16 LEFT 8 +PINATTR PinName Rind +PINATTR SpiceOrder 8 +PIN 192 16 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 9 +PIN 192 -64 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 10 +PIN -192 -64 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -192 256 LEFT 8 +PINATTR PinName PLLin/Mode +PINATTR SpiceOrder 12 +PIN -192 176 LEFT 8 +PINATTR PinName CLKOut +PINATTR SpiceOrder 13 +PIN 128 -384 TOP 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 14 +PIN -192 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 15 +PIN -128 -384 TOP 8 +PINATTR PinName Ictrl +PINATTR SpiceOrder 16 +PIN 0 -384 TOP 8 +PINATTR PinName Imon +PINATTR SpiceOrder 17 +PIN 192 176 RIGHT 8 +PINATTR PinName VPRG1 +PINATTR SpiceOrder 18 +PIN 192 256 RIGHT 8 +PINATTR PinName VPRG2 +PINATTR SpiceOrder 19 +PIN 192 -144 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 20 +PIN 192 96 RIGHT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 21 +PIN 192 -224 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 24 +PIN 192 -304 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 27 +PIN -192 -304 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 30 +PIN 64 336 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 35 diff --git a/spice/copy/sym/PowerProducts/LT8210.asy b/spice/copy/sym/PowerProducts/LT8210.asy new file mode 100755 index 0000000..eadbf93 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8210.asy @@ -0,0 +1,110 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 1008 -160 -1008 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -512 Center 2 +WINDOW 3 0 512 Center 2 +SYMATTR Value LT8210 +SYMATTR Value2 LT8210 +SYMATTR Prefix X +SYMATTR SpiceModel LT8210.sub +SYMATTR Description 100V Vin and Vout Synchronous 4-switch Buck-Boost DC/DC Controller with Pass Through. +PIN -160 -960 LEFT 8 +PINATTR PinName En UVLO +PINATTR SpiceOrder 1 +PIN -160 -576 LEFT 8 +PINATTR PinName Mode2 +PINATTR SpiceOrder 2 +PIN -160 -704 LEFT 8 +PINATTR PinName Mode1 +PINATTR SpiceOrder 3 +PIN -160 -832 LEFT 8 +PINATTR PinName Sync SPRD +PINATTR SpiceOrder 4 +PIN -160 -320 LEFT 8 +PINATTR PinName PWGD +PINATTR SpiceOrder 5 +PIN -160 -192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN 0 1008 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 7 +PIN -160 -448 LEFT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 +PIN -160 -64 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN -160 64 LEFT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 10 +PIN -160 192 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 11 +PIN -160 320 LEFT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 12 +PIN -160 448 LEFT 8 +PINATTR PinName Fb2 +PINATTR SpiceOrder 13 +PIN -160 576 LEFT 8 +PINATTR PinName Fb1 +PINATTR SpiceOrder 14 +PIN -160 704 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 16 +PIN 160 960 RIGHT 8 +PINATTR PinName SNSN2 +PINATTR SpiceOrder 18 +PIN 160 832 RIGHT 8 +PINATTR PinName SNSP2 +PINATTR SpiceOrder 19 +PIN 160 704 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 20 +PIN 160 576 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 21 +PIN 160 448 RIGHT 8 +PINATTR PinName Bst2 +PINATTR SpiceOrder 22 +PIN 160 320 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 24 +PIN 160 192 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 25 +PIN 160 -192 RIGHT 8 +PINATTR PinName Bg1 +PINATTR SpiceOrder 26 +PIN -160 960 LEFT 8 +PINATTR PinName GateVcc +PINATTR SpiceOrder 27 +PIN -160 832 LEFT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 28 +PIN 160 -448 RIGHT 8 +PINATTR PinName Bst1 +PINATTR SpiceOrder 30 +PIN 160 -320 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 160 -576 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 32 +PIN 160 64 RIGHT 8 +PINATTR PinName SNSN1 +PINATTR SpiceOrder 33 +PIN 160 -64 RIGHT 8 +PINATTR PinName SNSP1 +PINATTR SpiceOrder 34 +PIN 160 -704 RIGHT 8 +PINATTR PinName VinP +PINATTR SpiceOrder 36 +PIN 160 -832 RIGHT 8 +PINATTR PinName DG +PINATTR SpiceOrder 37 +PIN 160 -960 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LT8228.asy b/spice/copy/sym/PowerProducts/LT8228.asy new file mode 100755 index 0000000..079fea6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8228.asy @@ -0,0 +1,125 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 735 -336 -737 368 +TEXT 0 2 Center 2 LT +WINDOW 0 2 -47 Center 2 +WINDOW 3 0 45 Center 2 +SYMATTR Value LT8228 +SYMATTR Prefix X +SYMATTR SpiceModel LT8228.sub +SYMATTR Value2 LT8228 +SYMATTR Description Bidirectional Synchronous 100V Buck/Boost Controller with Reverse Supply, Reverse Current and Fault Protection\n\nNote: REPORT pin is not modeled. +PIN -384 -336 TOP 8 +PINATTR PinName SNS1P +PINATTR SpiceOrder 1 +PIN -288 -336 TOP 8 +PINATTR PinName SNS1N +PINATTR SpiceOrder 2 +PIN -736 0 LEFT 8 +PINATTR PinName UV1 +PINATTR SpiceOrder 3 +PIN -736 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN -240 368 BOTTOM 8 +PINATTR PinName IMON1 +PINATTR SpiceOrder 5 +PIN -576 368 BOTTOM 8 +PINATTR PinName ISET1N +PINATTR SpiceOrder 6 +PIN -432 368 BOTTOM 8 +PINATTR PinName ISET2N +PINATTR SpiceOrder 7 +PIN -336 368 BOTTOM 8 +PINATTR PinName VC1 +PINATTR SpiceOrder 8 +PIN 48 368 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN -48 368 BOTTOM 8 +PINATTR PinName VC2 +PINATTR SpiceOrder 10 +PIN 400 368 BOTTOM 8 +PINATTR PinName ISET1P +PINATTR SpiceOrder 11 +PIN 576 368 BOTTOM 8 +PINATTR PinName ISET2P +PINATTR SpiceOrder 12 +PIN -144 368 BOTTOM 8 +PINATTR PinName IMON2 +PINATTR SpiceOrder 13 +PIN 576 -336 TOP 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 14 +PIN 736 -96 RIGHT 8 +PINATTR PinName UV2 +PINATTR SpiceOrder 15 +PIN 240 368 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 16 +PIN -736 208 LEFT 8 +PINATTR PinName ISHARE +PINATTR SpiceOrder 17 +PIN 384 -336 TOP 8 +PINATTR PinName SNS2P +PINATTR SpiceOrder 18 +PIN 480 -336 TOP 8 +PINATTR PinName SNS2N +PINATTR SpiceOrder 19 +PIN 736 208 RIGHT 8 +PINATTR PinName IGND +PINATTR SpiceOrder 20 +PIN 672 368 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 736 0 RIGHT 8 +PINATTR PinName DRXN +PINATTR SpiceOrder 22 +PIN -672 368 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 23 +PIN 736 96 RIGHT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 24 +PIN 192 -336 TOP 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 +PIN 144 368 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 26 +PIN 288 -336 TOP 8 +PINATTR PinName BG +PINATTR SpiceOrder 27 +PIN 96 -336 TOP 8 +PINATTR PinName Drvcc +PINATTR SpiceOrder 28 +PIN -736 -192 LEFT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 29 +PIN -96 -336 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 30 +PIN -192 -336 TOP 8 +PINATTR PinName TG +PINATTR SpiceOrder 31 +PIN 0 -336 TOP 8 +PINATTR PinName BST +PINATTR SpiceOrder 32 +PIN -736 -96 LEFT 8 +PINATTR PinName ENABLE +PINATTR SpiceOrder 33 +PIN 736 -192 RIGHT 8 +PINATTR PinName DS2 +PINATTR SpiceOrder 34 +PIN 672 -336 TOP 8 +PINATTR PinName DG2 +PINATTR SpiceOrder 35 +PIN -480 -336 TOP 8 +PINATTR PinName V1D +PINATTR SpiceOrder 36 +PIN -672 -336 TOP 8 +PINATTR PinName DS1 +PINATTR SpiceOrder 37 +PIN -576 -336 TOP 8 +PINATTR PinName DG1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LT8300.asy b/spice/copy/sym/PowerProducts/LT8300.asy new file mode 100755 index 0000000..6d957d4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8300.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT8300 +SYMATTR Prefix X +SYMATTR SpiceModel LT8300.sub +SYMATTR Value2 LT8300 +SYMATTR Description 100V µPower Flyback Converter with 150V/260mA Switch +PIN -112 64 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 112 64 RIGHT 8 +PINATTR PinName RFB +PINATTR SpiceOrder 3 +PIN 112 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -112 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT8301.asy b/spice/copy/sym/PowerProducts/LT8301.asy new file mode 100755 index 0000000..e68947a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8301.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT8301 +SYMATTR Prefix X +SYMATTR SpiceModel LT8301.sub +SYMATTR Value2 LT8301 +SYMATTR Description 42Vin µPower No-Opto Isolated Flyback Converter with 65V/1.2A Switch +PIN -112 64 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 112 64 RIGHT 8 +PINATTR PinName RFB +PINATTR SpiceOrder 3 +PIN 112 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -112 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT8302.asy b/spice/copy/sym/PowerProducts/LT8302.asy new file mode 100755 index 0000000..0c23ddb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8302.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -192 112 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT8302 +SYMATTR Prefix X +SYMATTR SpiceModel LT8302.sub +SYMATTR Value2 LT8302 +SYMATTR Description 42Vin µPower No-Opto Isolated Flyback Converter with 65V/3.6A Switch +PIN -112 -48 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN -112 48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN -112 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -112 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 -48 RIGHT 8 +PINATTR PinName RFB +PINATTR SpiceOrder 6 +PIN 112 48 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 7 +PIN 112 144 RIGHT 8 +PINATTR PinName Tc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT8303.asy b/spice/copy/sym/PowerProducts/LT8303.asy new file mode 100755 index 0000000..5e601b0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8303.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LT8303 +SYMATTR Prefix X +SYMATTR SpiceModel LT8303.sub +SYMATTR Value2 LT8303 +SYMATTR Description 100V µPower Isoloated Flyback Converter with 150V/450mA Switch +PIN -112 64 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 112 64 RIGHT 8 +PINATTR PinName RFB +PINATTR SpiceOrder 3 +PIN 112 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -112 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT8304-1.asy b/spice/copy/sym/PowerProducts/LT8304-1.asy new file mode 100755 index 0000000..1e8e36a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8304-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -192 112 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT8304-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT8304-1.sub +SYMATTR Value2 LT8304-1 +SYMATTR Description 100Vin µPower No-Opto Isolated Flyback Converter with 150V/2A Switch (optimized for high step-up output applications) +PIN -112 -48 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN -112 48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN -112 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -112 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 -48 RIGHT 8 +PINATTR PinName RFB +PINATTR SpiceOrder 6 +PIN 112 48 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 7 +PIN 112 144 RIGHT 8 +PINATTR PinName Tc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT8304.asy b/spice/copy/sym/PowerProducts/LT8304.asy new file mode 100755 index 0000000..c44576d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8304.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -192 112 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT8304 +SYMATTR Prefix X +SYMATTR SpiceModel LT8304.sub +SYMATTR Value2 LT8304 +SYMATTR Description 100Vin µPower No-Opto Isolated Flyback Converter with 150V/2A Switch +PIN -112 -48 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN -112 48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN -112 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -112 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 112 -48 RIGHT 8 +PINATTR PinName RFB +PINATTR SpiceOrder 6 +PIN 112 48 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 7 +PIN 112 144 RIGHT 8 +PINATTR PinName Tc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT8306.asy b/spice/copy/sym/PowerProducts/LT8306.asy new file mode 100755 index 0000000..9bd6788 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8306.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -192 112 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LT8306 +SYMATTR Prefix X +SYMATTR SpiceModel LT8306.sub +SYMATTR Value2 LT8306 +SYMATTR Description 60V Low-Iq No-Opto Isolated Flyback Controller +PIN -112 -48 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 6 +PIN -112 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 112 -144 RIGHT 8 +PINATTR PinName RFB +PINATTR SpiceOrder 4 +PIN 112 -48 RIGHT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 3 +PIN 112 48 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 1 diff --git a/spice/copy/sym/PowerProducts/LT8309.asy b/spice/copy/sym/PowerProducts/LT8309.asy new file mode 100755 index 0000000..01bf5bd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8309.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 1 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8309 +SYMATTR Prefix X +SYMATTR SpiceModel LT8309.sub +SYMATTR Value2 LT8309 +SYMATTR Description Secondary-Side Synchronous Rectifier Driver +PIN -128 96 LEFT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 -96 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -128 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 4 +PIN -128 0 LEFT 8 +PINATTR PinName Drain +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT8310.asy b/spice/copy/sym/PowerProducts/LT8310.asy new file mode 100755 index 0000000..d1dee72 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8310.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -304 160 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT8310 +SYMATTR Prefix X +SYMATTR SpiceModel LT8310.sub +SYMATTR Value2 LT8310 +SYMATTR Description 100Vin Forward Converter Controller +PIN -160 -240 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 1 +PIN -160 -144 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 3 +PIN -160 -48 LEFT 8 +PINATTR PinName DFILT +PINATTR SpiceOrder 5 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -160 144 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -160 240 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN 160 144 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 10 +PIN 160 240 RIGHT 8 +PINATTR PinName Sout +PINATTR SpiceOrder 11 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 13 +PIN 160 -48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 14 +PIN 160 -240 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 15 +PIN 160 -144 RIGHT 8 +PINATTR PinName RDVin +PINATTR SpiceOrder 16 +PIN 0 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 18 +PIN 0 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT8311.asy b/spice/copy/sym/PowerProducts/LT8311.asy new file mode 100755 index 0000000..e438103 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8311.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -304 -176 304 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT8311 +SYMATTR Prefix X +SYMATTR SpiceModel LT8311.sub +SYMATTR Value2 LT8311 +SYMATTR Description Preactive Secondary Synchronous and Opto Control for Forward Converters +PIN -144 -176 TOP 8 +PINATTR PinName CSW +PINATTR SpiceOrder 1 +PIN -240 -176 TOP 8 +PINATTR PinName FG +PINATTR SpiceOrder 5 +PIN -304 96 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 15 +PIN 304 96 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 +PIN 144 -176 TOP 8 +PINATTR PinName CG +PINATTR SpiceOrder 16 +PIN -304 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 304 -96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 240 160 BOTTOM 8 +PINATTR PinName _Pgood +PINATTR SpiceOrder 13 +PIN -48 -176 TOP 8 +PINATTR PinName FSW +PINATTR SpiceOrder 3 +PIN 48 -176 TOP 8 +PINATTR PinName CSP +PINATTR SpiceOrder 20 +PIN 240 -176 TOP 8 +PINATTR PinName CSN +PINATTR SpiceOrder 18 +PIN -304 0 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 6 +PIN -240 160 BOTTOM 8 +PINATTR PinName OPTO +PINATTR SpiceOrder 9 +PIN -144 160 BOTTOM 8 +PINATTR PinName _PMode +PINATTR SpiceOrder 8 +PIN -48 160 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN 48 160 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 12 +PIN 144 160 BOTTOM 8 +PINATTR PinName COMP +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT8312.asy b/spice/copy/sym/PowerProducts/LT8312.asy new file mode 100755 index 0000000..7a0f42b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8312.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -256 160 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8312 +SYMATTR Prefix X +SYMATTR SpiceModel LT8312.sub +SYMATTR Value2 LT8312 +SYMATTR Description Boost Controller with Power Factor Correction +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 4 +PIN -160 96 LEFT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 5 +PIN 160 192 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 6 +PIN 160 -96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN 160 -192 RIGHT 8 +PINATTR PinName DCM +PINATTR SpiceOrder 10 +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -160 -192 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 12 +PIN -160 192 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 160 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 14 +PIN 160 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 15 +PIN -160 -96 LEFT 8 +PINATTR PinName Vin_sense +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT8315.asy b/spice/copy/sym/PowerProducts/LT8315.asy new file mode 100755 index 0000000..7d102d6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8315.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 159 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT8315 +SYMATTR Prefix X +SYMATTR SpiceModel LT8315.sub +SYMATTR Value2 LT8315 +SYMATTR Description 560Vin µPower No-Opto Isolated Flyback Converter with 630V/300mA Switch +PIN 160 48 RIGHT 8 +PINATTR PinName Drain +PINATTR SpiceOrder 1 +PIN -160 -48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -64 -224 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 9 +PIN 64 -224 TOP 8 +PINATTR PinName DCM +PINATTR SpiceOrder 10 +PIN 160 -48 RIGHT 8 +PINATTR PinName TC +PINATTR SpiceOrder 11 +PIN 160 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 144 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 13 +PIN -64 224 BOTTOM 8 +PINATTR PinName Ireg/SS +PINATTR SpiceOrder 14 +PIN 64 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 15 +PIN -160 48 LEFT 8 +PINATTR PinName Smode +PINATTR SpiceOrder 16 +PIN -160 -144 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 17 +PIN 160 144 RIGHT 8 +PINATTR PinName Source +PINATTR SpiceOrder 18 diff --git a/spice/copy/sym/PowerProducts/LT8316.asy b/spice/copy/sym/PowerProducts/LT8316.asy new file mode 100755 index 0000000..8d3199c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8316.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -272 159 272 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT8316 +SYMATTR Prefix X +SYMATTR SpiceModel LT8316.sub +SYMATTR Value2 LT8316 +SYMATTR Description 600Vin µPower No-Opto Isolated Flyback Controller +PIN -64 -272 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 -96 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 8 +PIN 64 -272 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 9 +PIN 160 -192 RIGHT 8 +PINATTR PinName DCM +PINATTR SpiceOrder 10 +PIN 160 0 RIGHT 8 +PINATTR PinName TC +PINATTR SpiceOrder 11 +PIN 160 -96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -160 192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 13 +PIN -64 272 BOTTOM 8 +PINATTR PinName Ireg/SS +PINATTR SpiceOrder 14 +PIN 64 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 15 +PIN -160 0 LEFT 8 +PINATTR PinName Smode +PINATTR SpiceOrder 16 +PIN -160 -192 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 17 +PIN 160 192 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 18 +PIN 160 96 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LT8330.asy b/spice/copy/sym/PowerProducts/LT8330.asy new file mode 100755 index 0000000..cc1f66a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8330.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -112 160 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8330 +SYMATTR Value2 LT8330 +SYMATTR Prefix X +SYMATTR SpiceModel LT8330.sub +SYMATTR Description Low Iq Boost/SEPIC/Inverting Converter with 1A, 60V Switch +PIN 80 -112 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 80 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 0 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 8 +PIN -80 112 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN -80 -112 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT8331.asy b/spice/copy/sym/PowerProducts/LT8331.asy new file mode 100755 index 0000000..21d09bd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8331.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8331 +SYMATTR Value2 LT8331 +SYMATTR Prefix X +SYMATTR SpiceModel LT8331.sub +SYMATTR Description Low Iq Boost/SEPIC/Inverting Converter with 0.5A, 140V Switch +PIN -160 -96 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN -80 -160 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -96 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 5 +PIN 160 96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 160 0 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 9 +PIN -160 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN -80 160 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN -160 0 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 12 +PIN 80 -160 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 80 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8335.asy b/spice/copy/sym/PowerProducts/LT8335.asy new file mode 100755 index 0000000..4a7d96f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8335.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -112 160 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8335 +SYMATTR Value2 LT8335 +SYMATTR Prefix X +SYMATTR SpiceModel LT8335.sub +SYMATTR Description Low Iq Boost/SEPIC/Inverting Converter with 2A, 28V Switch +PIN 80 -112 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 80 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 0 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 8 +PIN -80 112 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN -80 -112 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT8336.asy b/spice/copy/sym/PowerProducts/LT8336.asy new file mode 100755 index 0000000..5d789ab --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8336.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -144 208 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8336 +SYMATTR Value2 LT8336 +SYMATTR Prefix X +SYMATTR SpiceModel LT8336.sub +SYMATTR Description 40V, 2.5A, Low Iq Synchronous Step-Up Silent Switcher +PIN -208 64 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 128 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 208 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 144 -144 TOP 4 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -128 144 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -144 -144 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -208 -64 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 10 +PIN -208 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8337-1.asy b/spice/copy/sym/PowerProducts/LT8337-1.asy new file mode 100755 index 0000000..51acdd4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8337-1.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -144 208 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8337-1 +SYMATTR Value2 LT8337-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT8337-1.sub +SYMATTR Description 28V, 5A Low Iq Synchronous Step-Up Silent Switcher with PassThru +PIN -208 64 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 128 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 208 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 144 -144 TOP 4 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -128 144 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -144 -144 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -208 -64 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 10 +PIN -208 0 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8337.asy b/spice/copy/sym/PowerProducts/LT8337.asy new file mode 100755 index 0000000..0ed3d5f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8337.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -144 208 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8337 +SYMATTR Value2 LT8337 +SYMATTR Prefix X +SYMATTR SpiceModel LT8337.sub +SYMATTR Description 28V, 5A Low Iq Synchronous Step-Up Silent Switcher +PIN -208 64 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 2 +PIN 128 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 208 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN 144 -144 TOP 4 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN -128 144 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -144 -144 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -208 -64 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 10 +PIN -208 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8350S.asy b/spice/copy/sym/PowerProducts/LT8350S.asy new file mode 100755 index 0000000..944fae5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8350S.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 289 529 -304 -496 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -304 Center 2 +SYMATTR Value LT8350S +SYMATTR Prefix X +SYMATTR SpiceModel LT8350S.sub +SYMATTR Value2 LT8350S +SYMATTR Description 40VIN 18VOUT 6A Synchronous Buck-Boost Silent Switcher +PIN -304 -416 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -304 -256 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 5 +PIN -304 -32 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 6 +PIN -304 368 LEFT 8 +PINATTR PinName RP +PINATTR SpiceOrder 7 +PIN -304 288 LEFT 8 +PINATTR PinName LOADEN +PINATTR SpiceOrder 8 +PIN -304 128 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 9 +PIN -304 448 LEFT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 10 +PIN 288 -288 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 11 +PIN 288 -208 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 12 +PIN -304 208 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 13 +PIN 288 -128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 14 +PIN 288 128 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 15 +PIN -304 48 LEFT 8 +PINATTR PinName _PGOOD +PINATTR SpiceOrder 16 +PIN 288 208 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 17 +PIN 288 288 RIGHT 8 +PINATTR PinName RT +PINATTR SpiceOrder 18 +PIN 288 368 RIGHT 8 +PINATTR PinName SYNC/MODE +PINATTR SpiceOrder 19 +PIN 288 448 RIGHT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 20 +PIN 288 -48 RIGHT 8 +PINATTR PinName LOADTG +PINATTR SpiceOrder 22 +PIN 288 -416 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 24 +PIN 64 -496 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 27 +PIN 192 -496 TOP 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 29 +PIN -208 -496 TOP 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 30 +PIN -80 -496 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 0 528 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 33 +PIN 288 48 RIGHT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT8357.asy b/spice/copy/sym/PowerProducts/LT8357.asy new file mode 100755 index 0000000..2dcad1f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8357.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 208 304 -208 -288 +TEXT 0 0 Center 2 LT +WINDOW 3 1 129 Center 2 +WINDOW 0 -1 -127 Center 2 +SYMATTR Value LT8357 +SYMATTR Prefix X +SYMATTR SpiceModel LT8357.sub +SYMATTR Value2 LT8357 +SYMATTR Description 60V 2MHz Low-Iq Boost, SEPIC and Flyback Controller +PIN -208 192 LEFT 8 +PINATTR PinName VC +PINATTR SpiceOrder 1 +PIN 208 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN -208 80 LEFT 8 +PINATTR PinName PGOOD +PINATTR SpiceOrder 3 +PIN -128 304 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 0 304 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 5 +PIN -208 -32 LEFT 8 +PINATTR PinName SYNC/MODE +PINATTR SpiceOrder 6 +PIN 208 -32 RIGHT 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 7 +PIN 208 -112 RIGHT 8 +PINATTR PinName GATEN +PINATTR SpiceOrder 8 +PIN 208 -176 RIGHT 8 +PINATTR PinName GATEP +PINATTR SpiceOrder 9 +PIN 128 304 BOTTOM 8 +PINATTR PinName INTVCC +PINATTR SpiceOrder 10 +PIN -208 -176 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 11 +PIN 0 -288 TOP 8 +PINATTR PinName VIN +PINATTR SpiceOrder 12 +PIN 208 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LT8361.asy b/spice/copy/sym/PowerProducts/LT8361.asy new file mode 100755 index 0000000..c04fe10 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8361.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 3 88 Center 2 +SYMATTR Value LT8361 +SYMATTR Value2 LT8361 +SYMATTR Prefix X +SYMATTR SpiceModel LT8361.sub +SYMATTR Description Low Iq Boost/SEPIC/Inverting Converter with 2A, 100V Switch +PIN -160 -144 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 160 48 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -80 -208 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 160 -48 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 9 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN -160 144 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN -160 -48 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 12 +PIN 80 -208 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8362.asy b/spice/copy/sym/PowerProducts/LT8362.asy new file mode 100755 index 0000000..2724a40 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8362.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 3 88 Center 2 +SYMATTR Value LT8362 +SYMATTR Value2 LT8362 +SYMATTR Prefix X +SYMATTR SpiceModel LT8362.sub +SYMATTR Description Low Iq Boost/SEPIC/Inverting Converter with 2A, 60V Switch +PIN -160 -144 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN -80 -208 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 160 -48 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 9 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN -160 144 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN -160 -48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 12 +PIN 80 -208 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 +PIN 160 48 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/PowerProducts/LT8364.asy b/spice/copy/sym/PowerProducts/LT8364.asy new file mode 100755 index 0000000..8d31ab3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8364.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 3 88 Center 2 +SYMATTR Value LT8364 +SYMATTR Value2 LT8364 +SYMATTR Prefix X +SYMATTR SpiceModel LT8364.sub +SYMATTR Description Low Iq Boost/SEPIC/Inverting Converter with 4A, 60V Switch +PIN -160 -144 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 160 48 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN -80 -208 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 5 +PIN 160 144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 160 -48 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 9 +PIN -160 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN -160 144 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN -160 -48 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 12 +PIN 80 -208 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8365.asy b/spice/copy/sym/PowerProducts/LT8365.asy new file mode 100755 index 0000000..5572283 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8365.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8365 +SYMATTR Value2 LT8365 +SYMATTR Prefix X +SYMATTR SpiceModel LT8365.sub +SYMATTR Description Low Iq Boost/SEPIC/Inverting Converter with 1.5A, 150V Switch +PIN -160 -96 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN -80 -160 TOP 4 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 160 -96 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 5 +PIN 160 96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 96 160 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 9 +PIN -160 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN -96 160 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN -160 0 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 12 +PIN 80 -160 TOP 4 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8390.asy b/spice/copy/sym/PowerProducts/LT8390.asy new file mode 100755 index 0000000..c136745 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8390.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 304 544 -304 -544 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value LT8390 +SYMATTR Prefix X +SYMATTR SpiceModel LT8390.sub +SYMATTR Value2 LT8390 +SYMATTR Description 60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum +PIN -304 -368 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 1 +PIN -304 -464 LEFT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 2 +PIN -192 -544 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN -304 -288 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 4 +PIN -64 -544 TOP 8 +PINATTR PinName LSP +PINATTR SpiceOrder 5 +PIN 64 -544 TOP 8 +PINATTR PinName LSN +PINATTR SpiceOrder 6 +PIN -304 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -304 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -304 -112 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN -304 272 LEFT 8 +PINATTR PinName LoadEN +PINATTR SpiceOrder 11 +PIN -304 176 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 12 +PIN -304 368 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 13 +PIN 304 -112 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN 304 -16 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 15 +PIN 304 272 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 16 +PIN -304 80 LEFT 8 +PINATTR PinName _PGood +PINATTR SpiceOrder 17 +PIN -192 544 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 18 +PIN 304 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 19 +PIN 0 544 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 20 +PIN 192 544 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 21 +PIN -304 448 LEFT 8 +PINATTR PinName Sync/SPRD +PINATTR SpiceOrder 22 +PIN 304 176 RIGHT 8 +PINATTR PinName LoadTG +PINATTR SpiceOrder 23 +PIN 304 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 24 +PIN 304 -288 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 25 +PIN 192 -544 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 26 +PIN 304 -464 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 27 +PIN 304 -368 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 28 +PIN 304 448 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LT8390A.asy b/spice/copy/sym/PowerProducts/LT8390A.asy new file mode 100755 index 0000000..c945536 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8390A.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 304 544 -304 -544 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value LT8390A +SYMATTR Prefix X +SYMATTR SpiceModel LT8390A.sub +SYMATTR Value2 LT8390A +SYMATTR Description 60V 2MHz Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum +PIN -304 -368 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 1 +PIN -304 -464 LEFT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 2 +PIN -192 -544 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN -304 -288 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 4 +PIN -64 -544 TOP 8 +PINATTR PinName LSP +PINATTR SpiceOrder 5 +PIN 64 -544 TOP 8 +PINATTR PinName LSN +PINATTR SpiceOrder 6 +PIN -304 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -304 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -304 -112 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN -304 272 LEFT 8 +PINATTR PinName LoadEN +PINATTR SpiceOrder 11 +PIN -304 176 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 12 +PIN -304 368 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 13 +PIN 304 -112 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN 304 -16 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 15 +PIN 304 272 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 16 +PIN -304 80 LEFT 8 +PINATTR PinName _PGood +PINATTR SpiceOrder 17 +PIN -192 544 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 18 +PIN 304 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 19 +PIN 0 544 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 20 +PIN 192 544 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 21 +PIN -304 448 LEFT 8 +PINATTR PinName Sync/SPRD +PINATTR SpiceOrder 22 +PIN 304 176 RIGHT 8 +PINATTR PinName LoadTG +PINATTR SpiceOrder 23 +PIN 304 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 24 +PIN 304 -288 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 25 +PIN 192 -544 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 26 +PIN 304 -464 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 27 +PIN 304 -368 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 28 +PIN 304 448 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LT8391.asy b/spice/copy/sym/PowerProducts/LT8391.asy new file mode 100755 index 0000000..fe75261 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8391.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 304 512 -304 -528 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value LT8391 +SYMATTR Prefix X +SYMATTR SpiceModel LT8391.sub +SYMATTR Value2 LT8391 +SYMATTR Description 60V Synchronous 4-Switch Buck-Boost LED Controller with Spread Spectrum +PIN -304 -368 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 1 +PIN -304 -464 LEFT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 2 +PIN -192 -528 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN -304 -288 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 4 +PIN -64 -528 TOP 8 +PINATTR PinName LSP +PINATTR SpiceOrder 5 +PIN 64 -528 TOP 8 +PINATTR PinName LSN +PINATTR SpiceOrder 6 +PIN -304 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -304 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -304 -112 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN 304 176 RIGHT 8 +PINATTR PinName Rp +PINATTR SpiceOrder 10 +PIN -304 448 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 11 +PIN -304 176 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 12 +PIN -304 368 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 13 +PIN 304 -112 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN 304 -16 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 15 +PIN -304 272 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 16 +PIN -304 80 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 17 +PIN -192 512 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 18 +PIN 304 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 19 +PIN 0 512 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 20 +PIN 192 512 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 21 +PIN 304 272 RIGHT 8 +PINATTR PinName Sync/SPRD +PINATTR SpiceOrder 22 +PIN 304 368 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 23 +PIN 304 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 24 +PIN 304 -288 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 25 +PIN 192 -528 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 26 +PIN 304 -464 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 27 +PIN 304 -368 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 28 +PIN 304 448 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LT8391A.asy b/spice/copy/sym/PowerProducts/LT8391A.asy new file mode 100755 index 0000000..eff2a1b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8391A.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 304 512 -304 -528 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value LT8391A +SYMATTR Prefix X +SYMATTR SpiceModel LT8391A.sub +SYMATTR Value2 LT8391A +SYMATTR Description 60V 2MHz Synchronous 4-Switch Buck-Boost LED Driver Controller with Spread Spectrum +PIN -304 -368 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 1 +PIN -304 -464 LEFT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 2 +PIN -192 -528 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN -304 -288 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 4 +PIN -64 -528 TOP 8 +PINATTR PinName LSP +PINATTR SpiceOrder 5 +PIN 64 -528 TOP 8 +PINATTR PinName LSN +PINATTR SpiceOrder 6 +PIN -304 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -304 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -304 -112 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN 304 176 RIGHT 8 +PINATTR PinName Rp +PINATTR SpiceOrder 10 +PIN -304 448 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 11 +PIN -304 176 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 12 +PIN -304 368 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 13 +PIN 304 -112 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN 304 -16 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 15 +PIN -304 272 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 16 +PIN -304 80 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 17 +PIN -192 512 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 18 +PIN 304 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 19 +PIN 0 512 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 20 +PIN 192 512 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 21 +PIN 304 272 RIGHT 8 +PINATTR PinName Sync/SPRD +PINATTR SpiceOrder 22 +PIN 304 368 RIGHT 8 +PINATTR PinName PWMTG +PINATTR SpiceOrder 23 +PIN 304 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 24 +PIN 304 -288 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 25 +PIN 192 -528 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 26 +PIN 304 -464 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 27 +PIN 304 -368 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 28 +PIN 304 448 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LT8392.asy b/spice/copy/sym/PowerProducts/LT8392.asy new file mode 100755 index 0000000..2641e37 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8392.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 304 544 -304 -544 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value LT8392 +SYMATTR Prefix X +SYMATTR SpiceModel LT8392.sub +SYMATTR Value2 LT8392 +SYMATTR Description 60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum +PIN -304 -368 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 1 +PIN -304 -464 LEFT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 2 +PIN -192 -544 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN -304 -288 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 4 +PIN -64 -544 TOP 8 +PINATTR PinName LSP +PINATTR SpiceOrder 5 +PIN 64 -544 TOP 8 +PINATTR PinName LSN +PINATTR SpiceOrder 6 +PIN -304 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -304 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -304 -112 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 9 +PIN 304 368 RIGHT 8 +PINATTR PinName TEST +PINATTR SpiceOrder 10 +PIN -304 272 LEFT 8 +PINATTR PinName TRIM +PINATTR SpiceOrder 11 +PIN -304 176 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 12 +PIN -304 368 LEFT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 13 +PIN 304 -16 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 14 +PIN 304 80 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 15 +PIN 304 272 RIGHT 8 +PINATTR PinName ISMON +PINATTR SpiceOrder 16 +PIN -304 80 LEFT 8 +PINATTR PinName _PGood +PINATTR SpiceOrder 17 +PIN -192 544 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 18 +PIN 304 176 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 19 +PIN 0 544 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 20 +PIN 192 544 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 21 +PIN -304 448 LEFT 8 +PINATTR PinName Sync/SPRD +PINATTR SpiceOrder 22 +PIN 304 -112 RIGHT 8 +PINATTR PinName EXTVCC +PINATTR SpiceOrder 23 +PIN 304 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 24 +PIN 304 -288 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 25 +PIN 192 -544 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 26 +PIN 304 -464 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 27 +PIN 304 -368 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 28 +PIN 304 448 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LT8410-1.asy b/spice/copy/sym/PowerProducts/LT8410-1.asy new file mode 100755 index 0000000..50e8a9a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8410-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT8410-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT8410-1.sub +SYMATTR Value2 LT8410-1 +SYMATTR Description Ultralow Power Boost Converter with Output Disconnect +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -64 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 64 -144 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 7 +PIN 144 80 RIGHT 8 +PINATTR PinName FBP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT8410.asy b/spice/copy/sym/PowerProducts/LT8410.asy new file mode 100755 index 0000000..dab0dad --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8410.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT8410 +SYMATTR Prefix X +SYMATTR SpiceModel LT8410.sub +SYMATTR Value2 LT8410 +SYMATTR Description Ultralow Power Boost Converter with Output Disconnect +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -64 -144 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 64 -144 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 7 +PIN 144 80 RIGHT 8 +PINATTR PinName FBP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LT8415.asy b/spice/copy/sym/PowerProducts/LT8415.asy new file mode 100755 index 0000000..eed3464 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8415.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -224 144 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -119 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LT8415 +SYMATTR Prefix X +SYMATTR SpiceModel LT8415.sub +SYMATTR Value2 LT8415 +SYMATTR Description Ultralow Power Boost Converter with Dual Half-Bridge Switches +PIN -144 160 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -160 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -64 -224 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -144 -80 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 5 +PIN -144 0 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 7 +PIN 144 -80 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 8 +PIN 144 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 9 +PIN 64 -224 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 10 +PIN 144 80 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 11 +PIN 144 160 RIGHT 8 +PINATTR PinName FBP +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LT8471.asy b/spice/copy/sym/PowerProducts/LT8471.asy new file mode 100755 index 0000000..47e8464 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8471.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -304 208 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LT8471 +SYMATTR Prefix X +SYMATTR SpiceModel LT8471.sub +SYMATTR Value2 LT8471 +SYMATTR Description Monolithic Boost/Inverting DC/DC Converter with Soft-Start +PIN 208 -272 RIGHT 8 +PINATTR PinName C1 +PINATTR SpiceOrder 1 +PIN 208 -192 RIGHT 8 +PINATTR PinName E1 +PINATTR SpiceOrder 2 +PIN -208 -272 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 3 +PIN -16 256 BOTTOM 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 4 +PIN 208 -112 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 5 +PIN -208 48 LEFT 8 +PINATTR PinName OV/UV +PINATTR SpiceOrder 6 +PIN -144 256 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 7 +PIN -208 128 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 8 +PIN 208 -32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -208 -32 LEFT 8 +PINATTR PinName C3 +PINATTR SpiceOrder 13 +PIN -208 -112 LEFT 8 +PINATTR PinName SHOUT +PINATTR SpiceOrder 14 +PIN -208 208 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 15 +PIN 208 208 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 16 +PIN 96 256 BOTTOM 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 17 +PIN -208 -192 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 18 +PIN 208 128 RIGHT 8 +PINATTR PinName E2 +PINATTR SpiceOrder 19 +PIN 208 48 RIGHT 8 +PINATTR PinName C2 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8494.asy b/spice/copy/sym/PowerProducts/LT8494.asy new file mode 100755 index 0000000..00033fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8494.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -176 208 144 +TEXT 0 -15 Center 2 LT +WINDOW 0 3 -65 Center 2 +WINDOW 3 -2 33 Center 2 +SYMATTR Value LT8494 +SYMATTR Prefix X +SYMATTR SpiceModel LT8494.sub +SYMATTR Value2 LT8494 +SYMATTR Description Monolithic Boost/Sepic DC/DC Low Iq Converter +PIN 208 -144 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 1 +PIN 208 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 208 16 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 7 +PIN -208 16 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -208 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN -208 -64 LEFT 8 +PINATTR PinName SWEN +PINATTR SpiceOrder 12 +PIN 208 96 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN -208 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 18 +PIN 0 -176 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8495.asy b/spice/copy/sym/PowerProducts/LT8495.asy new file mode 100755 index 0000000..494163d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8495.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -304 208 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 -3 67 Center 2 +SYMATTR Value LT8495 +SYMATTR Prefix X +SYMATTR SpiceModel LT8495.sub +SYMATTR Value2 LT8495 +SYMATTR Description Monolithic Boost/Sepic DC/DC Low Iq Converter with Watchdog and POR +PIN 208 -272 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 1 +PIN 208 -112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -208 -112 LEFT 8 +PINATTR PinName CPOR +PINATTR SpiceOrder 5 +PIN -208 -32 LEFT 8 +PINATTR PinName CWDT +PINATTR SpiceOrder 6 +PIN 208 128 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 7 +PIN -208 48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN -208 128 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 10 +PIN 208 -192 RIGHT 8 +PINATTR PinName _RSTin +PINATTR SpiceOrder 11 +PIN -208 -192 LEFT 8 +PINATTR PinName SWEN +PINATTR SpiceOrder 12 +PIN 208 208 RIGHT 8 +PINATTR PinName WDE +PINATTR SpiceOrder 13 +PIN 208 -32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN 208 48 RIGHT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 15 +PIN -208 208 LEFT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 16 +PIN -208 -272 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 18 +PIN 0 -304 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8570-1.asy b/spice/copy/sym/PowerProducts/LT8570-1.asy new file mode 100755 index 0000000..3574096 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8570-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8570-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT8570-1.sub +SYMATTR Value2 LT8570-1 +SYMATTR Description Boost/SEPIC/Inverting DC/DC Converter with 65V Switch, Soft-Start and Synchronization \n\n Synchronization function is not modeled +PIN 144 0 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT8570.asy b/spice/copy/sym/PowerProducts/LT8570.asy new file mode 100755 index 0000000..ba1f230 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8570.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8570 +SYMATTR Prefix X +SYMATTR SpiceModel LT8570.sub +SYMATTR Value2 LT8570 +SYMATTR Description Boost/SEPIC/Inverting DC/DC Converter with 65V Switch, Soft-Start and Synchronization \n\n Synchronization function is not modeled +PIN 144 0 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT8580.asy b/spice/copy/sym/PowerProducts/LT8580.asy new file mode 100755 index 0000000..76885bf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8580.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8580 +SYMATTR Prefix X +SYMATTR SpiceModel LT8580.sub +SYMATTR Value2 LT8580 +SYMATTR Description Boost/Inverting DC/DC Converter with 1A 65V Switch, Soft-Start, and Synchronization \n\n Synchronization function is not modeled +PIN 144 0 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN -144 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LT8582.asy b/spice/copy/sym/PowerProducts/LT8582.asy new file mode 100755 index 0000000..8c54393 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8582.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -496 144 496 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT8582 +SYMATTR Prefix X +SYMATTR SpiceModel LT8582.sub +SYMATTR Value2 LT8582 +SYMATTR Description Dual 3A Boost/Inverting/SEPIC DC/DC Converter with Fault Protection +PIN -80 -496 TOP 8 +PINATTR PinName SWA1 +PINATTR SpiceOrder 1 +PIN -144 -432 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN -144 -240 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 3 +PIN 144 -336 RIGHT 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 4 +PIN 144 -240 RIGHT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 5 +PIN 144 -432 RIGHT 8 +PINATTR PinName FBx1 +PINATTR SpiceOrder 6 +PIN 144 432 RIGHT 8 +PINATTR PinName FBx2 +PINATTR SpiceOrder 7 +PIN 144 240 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 8 +PIN 144 336 RIGHT 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 9 +PIN -144 240 LEFT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 10 +PIN -144 432 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 11 +PIN -80 496 BOTTOM 8 +PINATTR PinName SWA2 +PINATTR SpiceOrder 12 +PIN 80 496 BOTTOM 8 +PINATTR PinName SWB2 +PINATTR SpiceOrder 13 +PIN -144 48 LEFT 8 +PINATTR PinName Clkout2 +PINATTR SpiceOrder 14 +PIN -144 336 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 15 +PIN 144 48 RIGHT 8 +PINATTR PinName Rt2 +PINATTR SpiceOrder 16 +PIN 144 144 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 17 +PIN -144 144 LEFT 8 +PINATTR PinName SYNC2 +PINATTR SpiceOrder 18 +PIN -144 -144 LEFT 8 +PINATTR PinName SYNC1 +PINATTR SpiceOrder 19 +PIN 144 -144 RIGHT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 20 +PIN 144 -48 RIGHT 8 +PINATTR PinName Rt1 +PINATTR SpiceOrder 21 +PIN -144 -336 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 22 +PIN -144 -48 LEFT 8 +PINATTR PinName Clkout1 +PINATTR SpiceOrder 23 +PIN 80 -496 TOP 8 +PINATTR PinName SWB1 +PINATTR SpiceOrder 24 +PIN 0 496 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT8584.asy b/spice/copy/sym/PowerProducts/LT8584.asy new file mode 100755 index 0000000..7da10a3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8584.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT8584 +SYMATTR Prefix X +SYMATTR SpiceModel LT8584.sub +SYMATTR Value2 LT8584 +SYMATTR Description 2.5A Monolithic Active Cell Balancer with Telemetry Interface +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 0 -208 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 13 +PIN -144 128 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 5 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vsns +PINATTR SpiceOrder 11 +PIN -144 48 LEFT 8 +PINATTR PinName Vcell +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 8 +PIN 144 -48 RIGHT 8 +PINATTR PinName Din +PINATTR SpiceOrder 7 +PIN 144 48 RIGHT 8 +PINATTR PinName Dchrg +PINATTR SpiceOrder 12 +PIN 144 128 RIGHT 8 +PINATTR PinName Rtmr +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LT8601.asy b/spice/copy/sym/PowerProducts/LT8601.asy new file mode 100755 index 0000000..b975bb3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8601.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 224 528 -240 -528 +TEXT 0 0 Center 2 LT +WINDOW 3 0 192 Center 2 +WINDOW 0 0 -192 Center 2 +SYMATTR Value LT8601 +SYMATTR Prefix X +SYMATTR SpiceModel LT8601.sub +SYMATTR Value2 LT8601 +SYMATTR Description 42V Triple Monolithic Synchronous Step-Down Regulator +PIN -240 -144 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 1 +PIN 128 528 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 224 -336 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 224 -432 RIGHT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 4 +PIN 224 -144 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 5 +PIN 224 -48 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN 144 -528 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 10 +PIN -240 -48 LEFT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 11 +PIN -240 48 LEFT 8 +PINATTR PinName PG3 +PINATTR SpiceOrder 12 +PIN 48 -528 TOP 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 14 +PIN 224 240 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 15 +PIN 224 144 RIGHT 8 +PINATTR PinName PVin3 +PINATTR SpiceOrder 17 +PIN -240 144 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 18 +PIN 0 528 BOTTOM 8 +PINATTR PinName TRKSS2 +PINATTR SpiceOrder 20 +PIN -128 528 BOTTOM 8 +PINATTR PinName TRKSS1 +PINATTR SpiceOrder 21 +PIN -240 -432 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 22 +PIN -144 -528 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 23 +PIN 224 336 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 24 +PIN 224 48 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 25 +PIN 224 -240 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 26 +PIN -240 240 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 28 +PIN 224 432 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 29 +PIN -240 336 LEFT 8 +PINATTR PinName CPOR +PINATTR SpiceOrder 31 +PIN -240 -240 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 32 +PIN -240 432 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 33 +PIN -48 -528 TOP 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 37 +PIN -240 -336 LEFT 8 +PINATTR PinName POREN +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LT8602.asy b/spice/copy/sym/PowerProducts/LT8602.asy new file mode 100755 index 0000000..4ffdede --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8602.asy @@ -0,0 +1,107 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 224 592 -240 -592 +TEXT 0 0 Center 2 LT +WINDOW 3 0 192 Center 2 +WINDOW 0 0 -192 Center 2 +SYMATTR Value LT8602 +SYMATTR Prefix X +SYMATTR SpiceModel LT8602.sub +SYMATTR Value2 LT8602 +SYMATTR Description 42V Quadl Monolithic Synchronous Step-Down Regulator +PIN -240 -240 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 1 +PIN 128 592 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 224 -432 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 224 -528 RIGHT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 4 +PIN 224 -240 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 5 +PIN 224 -144 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN 144 -592 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 10 +PIN -240 -144 LEFT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 11 +PIN -240 48 LEFT 8 +PINATTR PinName PG4 +PINATTR SpiceOrder 12 +PIN 48 -592 TOP 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 14 +PIN 224 432 RIGHT 8 +PINATTR PinName SW4 +PINATTR SpiceOrder 15 +PIN 224 144 RIGHT 8 +PINATTR PinName PVin4 +PINATTR SpiceOrder 17 +PIN -240 240 LEFT 8 +PINATTR PinName Run4 +PINATTR SpiceOrder 18 +PIN 48 592 BOTTOM 8 +PINATTR PinName TRKSS2 +PINATTR SpiceOrder 20 +PIN -48 592 BOTTOM 8 +PINATTR PinName TRKSS1 +PINATTR SpiceOrder 21 +PIN -240 -528 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 22 +PIN -144 -592 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 23 +PIN 224 528 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 24 +PIN 224 -48 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 25 +PIN 224 -336 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 26 +PIN 224 336 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 27 +PIN -240 336 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 28 +PIN -144 592 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 29 +PIN -240 144 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 30 +PIN -240 432 LEFT 8 +PINATTR PinName CPOR +PINATTR SpiceOrder 31 +PIN -240 -336 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 32 +PIN -240 528 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 33 +PIN 224 48 RIGHT 8 +PINATTR PinName PVin3 +PINATTR SpiceOrder 34 +PIN 224 240 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 36 +PIN -48 -592 TOP 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 37 +PIN -240 -432 LEFT 8 +PINATTR PinName POREN +PINATTR SpiceOrder 39 +PIN -240 -48 LEFT 8 +PINATTR PinName PG3 +PINATTR SpiceOrder 40 diff --git a/spice/copy/sym/PowerProducts/LT8603.asy b/spice/copy/sym/PowerProducts/LT8603.asy new file mode 100755 index 0000000..1941115 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8603.asy @@ -0,0 +1,116 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 224 640 -240 -640 +TEXT 0 0 Center 2 LT +WINDOW 3 0 240 Center 2 +WINDOW 0 0 -240 Center 2 +SYMATTR Value LT8603 +SYMATTR Prefix X +SYMATTR SpiceModel LT8603.sub +SYMATTR Value2 LT8603 +SYMATTR Description 42V, Low Iq, Quad Output Triple Monolithic Buck Converter and Boost Converter +PIN -240 -288 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 1 +PIN 160 640 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 224 -480 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN 224 -576 RIGHT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 4 +PIN 224 -288 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 5 +PIN 224 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 6 +PIN 144 -640 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 9 +PIN -240 -192 LEFT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 10 +PIN -240 0 LEFT 8 +PINATTR PinName PG4 +PINATTR SpiceOrder 11 +PIN -240 288 LEFT 8 +PINATTR PinName FSEL4A +PINATTR SpiceOrder 12 +PIN 48 -640 TOP 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 14 +PIN 224 480 RIGHT 8 +PINATTR PinName Gate4 +PINATTR SpiceOrder 15 +PIN -240 192 LEFT 8 +PINATTR PinName INTVcc4 +PINATTR SpiceOrder 16 +PIN -240 384 LEFT 8 +PINATTR PinName FSEL4B +PINATTR SpiceOrder 17 +PIN 224 384 RIGHT 8 +PINATTR PinName ISN4 +PINATTR SpiceOrder 18 +PIN 224 288 RIGHT 8 +PINATTR PinName ISP4 +PINATTR SpiceOrder 19 +PIN -240 576 LEFT 8 +PINATTR PinName TRKSS2 +PINATTR SpiceOrder 20 +PIN -240 480 LEFT 8 +PINATTR PinName TRKSS1 +PINATTR SpiceOrder 21 +PIN -240 -576 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 22 +PIN -144 -640 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 23 +PIN 224 576 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 24 +PIN 224 -96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 25 +PIN 224 -384 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 26 +PIN 224 192 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 27 +PIN -240 96 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 28 +PIN -80 640 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 29 +PIN -160 640 BOTTOM 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 30 +PIN 80 640 BOTTOM 8 +PINATTR PinName CPOR +PINATTR SpiceOrder 31 +PIN -240 -384 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 32 +PIN 0 640 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 33 +PIN 224 0 RIGHT 8 +PINATTR PinName PVin3 +PINATTR SpiceOrder 34 +PIN 224 96 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 36 +PIN -48 -640 TOP 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 37 +PIN -240 -480 LEFT 8 +PINATTR PinName POREN +PINATTR SpiceOrder 39 +PIN -240 -96 LEFT 8 +PINATTR PinName PG3 +PINATTR SpiceOrder 40 diff --git a/spice/copy/sym/PowerProducts/LT8606.asy b/spice/copy/sym/PowerProducts/LT8606.asy new file mode 100755 index 0000000..7ea1e4e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8606.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8606 +SYMATTR Prefix X +SYMATTR SpiceModel LT8606.sub +SYMATTR Value2 LT8606 +SYMATTR Description 42V, 350mA Step-Down Regulator with 2.5µA Quiescent Current +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8607.asy b/spice/copy/sym/PowerProducts/LT8607.asy new file mode 100755 index 0000000..cb13532 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8607.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8607 +SYMATTR Prefix X +SYMATTR SpiceModel LT8607.sub +SYMATTR Value2 LT8607 +SYMATTR Description 42V, 750mA Peak Synchronous Step-Down Regulator with 2.5µA Quiescent Current +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8608.asy b/spice/copy/sym/PowerProducts/LT8608.asy new file mode 100755 index 0000000..21f2ab8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8608.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8608 +SYMATTR Prefix X +SYMATTR SpiceModel LT8608.sub +SYMATTR Value2 LT8608 +SYMATTR Description 42V, 1.5A Peak Synchronous Step-Down Regulator with 2.5µA Quiescent Current +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8609.asy b/spice/copy/sym/PowerProducts/LT8609.asy new file mode 100755 index 0000000..74ab9f2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8609.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8609 +SYMATTR Prefix X +SYMATTR SpiceModel LT8609.sub +SYMATTR Value2 LT8609 +SYMATTR Description 42V, 2A/3A Peak Synchronous Step-Down Regulator with 2.5µA Quiescent Current +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8609A.asy b/spice/copy/sym/PowerProducts/LT8609A.asy new file mode 100755 index 0000000..a7b49b4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8609A.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8609A +SYMATTR Prefix X +SYMATTR SpiceModel LT8609A.sub +SYMATTR Value2 LT8609A +SYMATTR Description 42V, 2A/3A Peak Synchronous Step-Down Regulator with 2.5µA Quiescent Current +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8609B.asy b/spice/copy/sym/PowerProducts/LT8609B.asy new file mode 100755 index 0000000..a4f5443 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8609B.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8609B +SYMATTR Prefix X +SYMATTR SpiceModel LT8609.sub +SYMATTR Value2 LT8609 +SYMATTR Description 42V, 2A/3A Peak Synchronous Step-Down Regulator with 2.5µA Quiescent Current +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8609S.asy b/spice/copy/sym/PowerProducts/LT8609S.asy new file mode 100755 index 0000000..c7bc4c0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8609S.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8609S +SYMATTR Prefix X +SYMATTR SpiceModel LT8609S.sub +SYMATTR Value2 LT8609S +SYMATTR Description 42V, 2A/3A Peak Synchronous Step-Down Regulator with 2.5µA Quiescent Current +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8610.asy b/spice/copy/sym/PowerProducts/LT8610.asy new file mode 100755 index 0000000..d390a2d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8610.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8610 +SYMATTR Prefix X +SYMATTR SpiceModel LT8610.sub +SYMATTR Value2 LT8610 +SYMATTR Description 42V, 2.5A Synchronous Step-Down Regulator with 2.5µA Quiescent Current\n\nNote: Sync function is not modeled. +PIN -144 -96 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 1 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 2 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 64 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -64 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8610A.asy b/spice/copy/sym/PowerProducts/LT8610A.asy new file mode 100755 index 0000000..d746b02 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8610A.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8610A +SYMATTR Prefix X +SYMATTR SpiceModel LT8610A.sub +SYMATTR Value2 LT8610A +SYMATTR Description 42V, 3.5A Synchronous Step-Down Regulator with 2.5µA Quiescent Current\n\nNote: Sync function is not modeled. +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 2 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 64 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -64 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8610AB.asy b/spice/copy/sym/PowerProducts/LT8610AB.asy new file mode 100755 index 0000000..c1e94a9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8610AB.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8610AB +SYMATTR Prefix X +SYMATTR SpiceModel LT8610AB.sub +SYMATTR Value2 LT8610AB +SYMATTR Description 42V, 3.5A Synchronous Step-Down Regulator with 2.5µA Quiescent Current\n\nNote: Sync function is not modeled. +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 2 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 64 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -64 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8610AC.asy b/spice/copy/sym/PowerProducts/LT8610AC.asy new file mode 100755 index 0000000..8670af4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8610AC.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8610AC +SYMATTR Prefix X +SYMATTR SpiceModel LT8610AC.sub +SYMATTR Value2 LT8610AC +SYMATTR Description 42V, 3.5A Synchronous Step-Down Regulator with 2.5µA Quiescent Current\n\nNote: Sync function is not modeled. +PIN -144 -96 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 1 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 2 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 64 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -64 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8611.asy b/spice/copy/sym/PowerProducts/LT8611.asy new file mode 100755 index 0000000..4272c25 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8611.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -336 144 336 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT8611 +SYMATTR Prefix X +SYMATTR SpiceModel LT8611.sub +SYMATTR Value2 LT8611 +SYMATTR Description 42V, 2.5A Synchronous Step-Down Regulator with Current Sense and 1.6µA Quiescent Current\n\nNote: Sync function is not modeled. +PIN -144 -96 LEFT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 1 +PIN -144 192 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 2 +PIN -144 288 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -288 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -336 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -144 96 LEFT 8 +PINATTR PinName Ictrl +PINATTR SpiceOrder 6 +PIN 64 336 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 96 RIGHT 8 +PINATTR PinName Isp +PINATTR SpiceOrder 8 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 192 RIGHT 8 +PINATTR PinName Isn +PINATTR SpiceOrder 10 +PIN -144 -192 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 11 +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -288 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -192 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 144 288 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -64 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8612.asy b/spice/copy/sym/PowerProducts/LT8612.asy new file mode 100755 index 0000000..9e4a064 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8612.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8612 +SYMATTR Prefix X +SYMATTR SpiceModel LT8612.sub +SYMATTR Value2 LT8612 +SYMATTR Description 42V, 6A Synchronous Step-Down Regulator with 3µA Quiescent Current\n\nNote: Sync function is not modeled. +PIN -144 -96 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 1 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 2 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 64 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -64 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8613.asy b/spice/copy/sym/PowerProducts/LT8613.asy new file mode 100755 index 0000000..644f8b4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8613.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -336 144 336 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LT8613 +SYMATTR Prefix X +SYMATTR SpiceModel LT8613.sub +SYMATTR Value2 LT8613 +SYMATTR Description 42V, 6A Synchronous Step-Down Regulator with Current Sense and 3µA Quiescent Current +PIN -144 -96 LEFT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 1 +PIN -144 192 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 2 +PIN -144 288 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -288 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -336 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -144 96 LEFT 8 +PINATTR PinName Ictrl +PINATTR SpiceOrder 6 +PIN 64 336 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 96 RIGHT 8 +PINATTR PinName Isp +PINATTR SpiceOrder 8 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 192 RIGHT 8 +PINATTR PinName Isn +PINATTR SpiceOrder 10 +PIN -144 -192 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 11 +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -288 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -192 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 144 288 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -64 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8614.asy b/spice/copy/sym/PowerProducts/LT8614.asy new file mode 100755 index 0000000..38c0c8e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8614.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8614 +SYMATTR Prefix X +SYMATTR SpiceModel LT8614.sub +SYMATTR Value2 LT8614 +SYMATTR Description 42V, 4A Synchronous Step-Down Silent Switcher with 2.5µA Quiescent Current\n\nNote: Sync function is not modeled. +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -144 -144 LEFT 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 6 +PIN 144 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 144 -144 RIGHT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 10 +PIN 144 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 13 +PIN 0 -304 TOP 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 14 +PIN -48 304 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 240 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 17 +PIN 48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -144 144 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8616.asy b/spice/copy/sym/PowerProducts/LT8616.asy new file mode 100755 index 0000000..3ec91a2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8616.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -432 144 432 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8616 +SYMATTR Prefix X +SYMATTR SpiceModel LT8616.sub +SYMATTR Value2 LT8616 +SYMATTR Description Dual 42V Synchronous Monolithic Step-Down Regulator with 6.5µA Quiescent Current +PIN -144 -96 LEFT 8 +PINATTR PinName EN/UV2 +PINATTR SpiceOrder 1 +PIN 144 96 RIGHT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 2 +PIN 144 288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 3 +PIN 144 192 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 6 +PIN 144 -384 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 8 +PIN 144 -288 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 9 +PIN 144 -96 RIGHT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 11 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS1 +PINATTR SpiceOrder 12 +PIN 144 -192 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 13 +PIN -144 384 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 -288 LEFT 8 +PINATTR PinName EN/UV1 +PINATTR SpiceOrder 16 +PIN -144 288 LEFT 8 +PINATTR PinName SYNC/Mode +PINATTR SpiceOrder 17 +PIN -144 -384 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 19 +PIN -144 0 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 144 0 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 22 +PIN -144 -192 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 24 +PIN 144 384 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 26 +PIN -144 192 LEFT 8 +PINATTR PinName TR/SS2 +PINATTR SpiceOrder 28 +PIN 0 432 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LT8618-3.3.asy b/spice/copy/sym/PowerProducts/LT8618-3.3.asy new file mode 100755 index 0000000..42a4145 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8618-3.3.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8618-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT8618-3.3.sub +SYMATTR Value2 LT8618-3.3 +SYMATTR Description High Efficiency 65V/100mA Synchronous Buck, 3.3V Fixed Output +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 4 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN 144 192 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN 144 -192 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN -144 -96 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8618.asy b/spice/copy/sym/PowerProducts/LT8618.asy new file mode 100755 index 0000000..5d00e72 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8618.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8618 +SYMATTR Prefix X +SYMATTR SpiceModel LT8618.sub +SYMATTR Value2 LT8618 +SYMATTR Description High Efficiency 65V/100mA Synchronous Buck +PIN 144 -96 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 4 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 5 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN 144 -192 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN -144 -96 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 9 +PIN -144 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LT8619-5.asy b/spice/copy/sym/PowerProducts/LT8619-5.asy new file mode 100755 index 0000000..b906268 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8619-5.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -192 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT8619-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT8619-5.sub +SYMATTR Value2 LT8619-5 +SYMATTR Description 60V, 1.2A Synchronous 5V Step-Down Regulator with 6µA Quiescent Current +PIN -144 -48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -144 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 48 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 64 192 BOTTOM 8 +PINATTR PinName OUT +PINATTR SpiceOrder 18 +PIN -64 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8619.asy b/spice/copy/sym/PowerProducts/LT8619.asy new file mode 100755 index 0000000..10924df --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8619.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -192 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT8619 +SYMATTR Prefix X +SYMATTR SpiceModel LT8619.sub +SYMATTR Value2 LT8619 +SYMATTR Description 60V, 1.2A Synchronous Step-Down Regulator with 6µA Quiescent Current +PIN -144 -48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 1 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -144 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 48 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 64 192 BOTTOM 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN -64 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8620.asy b/spice/copy/sym/PowerProducts/LT8620.asy new file mode 100755 index 0000000..4b1974e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8620.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LT8620 +SYMATTR Prefix X +SYMATTR SpiceModel LT8620.sub +SYMATTR Value2 LT8620 +SYMATTR Description 65V, 2A Synchronous Step-Down Regulator with 2.5µA Quiescent Current\n\nNote: Sync function is not modeled. +PIN -144 -96 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 1 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 2 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 12 +PIN 144 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 15 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 16 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8630.asy b/spice/copy/sym/PowerProducts/LT8630.asy new file mode 100755 index 0000000..7578e17 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8630.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -256 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT8630 +SYMATTR Prefix X +SYMATTR SpiceModel LT8630.sub +SYMATTR Value2 LT8630 +SYMATTR Description 100V, 0.6A Synchronous µPower Step-Down High Efficiency Switching Regulator +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 3 +PIN -144 -96 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 5 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 144 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 12 +PIN 144 0 RIGHT 8 +PINATTR PinName IND +PINATTR SpiceOrder 14 +PIN -144 0 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 16 +PIN 144 -192 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 18 +PIN 144 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 20 +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT8631.asy b/spice/copy/sym/PowerProducts/LT8631.asy new file mode 100755 index 0000000..69aebe7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8631.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -256 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT8631 +SYMATTR Prefix X +SYMATTR SpiceModel LT8631.sub +SYMATTR Value2 LT8631 +SYMATTR Description 100V, 1A Synchronous µPower Step-Down Regulator\n\nNote: Sync function is not modeled. +PIN -64 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -192 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 5 +PIN -144 -96 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 7 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 144 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 12 +PIN 144 0 RIGHT 8 +PINATTR PinName IND +PINATTR SpiceOrder 14 +PIN 64 -256 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 16 +PIN 144 -192 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 18 +PIN 144 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 20 +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LT8640-1.asy b/spice/copy/sym/PowerProducts/LT8640-1.asy new file mode 100755 index 0000000..2d853f9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8640-1.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8640-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT8640-1.sub +SYMATTR Value2 LT8640-1 +SYMATTR Description 42V, 5A Synchronous Step-Down Silent Switcher with 2.5µA Quiescent Current\n\nNote: Sync function is not modeled. +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -144 -144 LEFT 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 6 +PIN 144 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 144 -144 RIGHT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 10 +PIN 144 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 13 +PIN 0 -304 TOP 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 14 +PIN -48 304 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 240 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 17 +PIN 48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -144 144 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8640.asy b/spice/copy/sym/PowerProducts/LT8640.asy new file mode 100755 index 0000000..b08f5ea --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8640.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8640 +SYMATTR Prefix X +SYMATTR SpiceModel LT8640.sub +SYMATTR Value2 LT8640 +SYMATTR Description 42V, 5A Synchronous Step-Down Silent Switcher with 2.5µA Quiescent Current +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -144 -144 LEFT 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 6 +PIN 144 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 144 -144 RIGHT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 10 +PIN 144 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 13 +PIN 0 -304 TOP 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 14 +PIN -48 304 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 240 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 17 +PIN 48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -144 144 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8640S.asy b/spice/copy/sym/PowerProducts/LT8640S.asy new file mode 100755 index 0000000..2f96dd9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8640S.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8640S +SYMATTR Prefix X +SYMATTR SpiceModel LT8640S.sub +SYMATTR Value2 LT8640S +SYMATTR Description 42V, 5A Synchronous Step-Down Silent Switcher with 2.5µA Quiescent Current (Internal capacitors for Vin, Vcc, BootStrap) +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -144 -144 LEFT 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 6 +PIN 144 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 144 -144 RIGHT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 10 +PIN 144 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 13 +PIN -48 -304 TOP 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 14 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 240 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 17 +PIN 48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 48 -304 TOP 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 +PIN -48 304 BOTTOM 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LT8641.asy b/spice/copy/sym/PowerProducts/LT8641.asy new file mode 100755 index 0000000..ff0211e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8641.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8641 +SYMATTR Prefix X +SYMATTR SpiceModel LT8641.sub +SYMATTR Value2 LT8641 +SYMATTR Description 65V, 3.5A Synchronous Step-Down Silent Switcher with 2.5µA Quiescent Current +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -144 -144 LEFT 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 6 +PIN 144 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 144 -144 RIGHT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 10 +PIN 144 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 13 +PIN 0 -304 TOP 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 14 +PIN -48 304 BOTTOM 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 240 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 48 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 17 +PIN 48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -144 144 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8642S.asy b/spice/copy/sym/PowerProducts/LT8642S.asy new file mode 100755 index 0000000..65ff737 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8642S.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8642S +SYMATTR Prefix X +SYMATTR SpiceModel LT8642S.sub +SYMATTR Value2 LT8642S +SYMATTR Description 18V, 10A Synchronous Step-Down Silent Switcher 2 +PIN -144 -48 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN 0 -304 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 0 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 144 -240 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN -144 -144 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 17 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 18 +PIN 144 144 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 19 +PIN -144 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 20 +PIN -144 240 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 21 +PIN 144 48 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 22 +PIN 144 240 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 23 +PIN 144 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LT8643S.asy b/spice/copy/sym/PowerProducts/LT8643S.asy new file mode 100755 index 0000000..2101de2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8643S.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8643S +SYMATTR Prefix X +SYMATTR SpiceModel LT8643S.sub +SYMATTR Value2 LT8643S +SYMATTR Description 42V, 6A Synchronous Step-Down Silent Switcher with 2.5µA Quiescent Current with External Compensation (Internal capacitors for Vin, Vcc, BootStrap) +PIN 144 0 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -48 304 BOTTOM 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 5 +PIN -144 -160 LEFT 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 6 +PIN -144 -80 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 7 +PIN 144 160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 144 -160 RIGHT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 10 +PIN 144 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 13 +PIN 0 -304 TOP 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 14 +PIN -144 160 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 240 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 17 +PIN 48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 144 -80 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8644S.asy b/spice/copy/sym/PowerProducts/LT8644S.asy new file mode 100755 index 0000000..4373243 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8644S.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8644S +SYMATTR Prefix X +SYMATTR Value2 LT8644S +SYMATTR Description 18V, 10A Synchronous Step-Down Silent Switcher 2 +SYMATTR ModelFile LT8644S.sub +PIN -144 -48 LEFT 8 +PINATTR PinName PHMODE +PINATTR SpiceOrder 1 +PIN 0 -304 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 0 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 4 +PIN -144 -208 LEFT 8 +PINATTR PinName PVin +PINATTR SpiceOrder 5 +PIN 144 -224 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN -144 -144 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 17 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 18 +PIN 144 144 RIGHT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 19 +PIN -144 48 LEFT 8 +PINATTR PinName SYNC/Mode +PINATTR SpiceOrder 20 +PIN -144 240 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 21 +PIN 144 48 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 22 +PIN 144 240 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 23 +PIN 144 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LT8645S.asy b/spice/copy/sym/PowerProducts/LT8645S.asy new file mode 100755 index 0000000..ce823b3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8645S.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8645S +SYMATTR Prefix X +SYMATTR SpiceModel LT8645S.sub +SYMATTR Value2 LT8645S +SYMATTR Description 65V, 8A Synchronous Step-Down Silent Switcher with 2.5µA Quiescent Current (Internal capacitors for Vin, Vcc, BootStrap) +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -48 304 BOTTOM 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 5 +PIN -144 -144 LEFT 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 6 +PIN 144 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 144 -144 RIGHT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 10 +PIN 144 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 13 +PIN -48 -304 TOP 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 14 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 240 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 17 +PIN 48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 48 -304 TOP 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8646S.asy b/spice/copy/sym/PowerProducts/LT8646S.asy new file mode 100755 index 0000000..b324ced --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8646S.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LT8646S +SYMATTR Prefix X +SYMATTR SpiceModel LT8646S.sub +SYMATTR Value2 LT8646S +SYMATTR Description 65V, 8A Synchronous Step-Down Silent Switcher with 2.5µA Quiescent Current (Internal capacitors for Vin, Vcc, BootStrap) +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 144 48 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -80 304 BOTTOM 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 5 +PIN -144 -144 LEFT 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 6 +PIN 144 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 144 -144 RIGHT 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 10 +PIN 144 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 13 +PIN -48 -304 TOP 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 14 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 240 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 17 +PIN 0 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 48 -304 TOP 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 +PIN 80 304 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 30 diff --git a/spice/copy/sym/PowerProducts/LT8648S.asy b/spice/copy/sym/PowerProducts/LT8648S.asy new file mode 100755 index 0000000..4319ca3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8648S.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT8648S +SYMATTR Prefix X +SYMATTR SpiceModel LT8648S.sub +SYMATTR Value2 LT8648S +SYMATTR Description 40V, 15A Synchronous Step-Down Silent Switcher 2 with 2.5µA Quiesent Current +PIN 144 -64 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 1 +PIN 144 32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 2 +PIN 144 -240 RIGHT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -144 128 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 5 +PIN 144 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 -64 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -144 -160 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN 144 224 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 9 +PIN 0 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 0 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN -144 -240 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 12 +PIN -144 224 LEFT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 13 +PIN 144 -160 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LT8650S.asy b/spice/copy/sym/PowerProducts/LT8650S.asy new file mode 100755 index 0000000..18051ac --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8650S.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -432 144 448 +TEXT 0 16 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 160 Center 2 +SYMATTR Value LT8650S +SYMATTR Prefix X +SYMATTR SpiceModel LT8650S.sub +SYMATTR Value2 LT8650S +SYMATTR Description Dual Channel 4A, 42V, Synchronous Step-Down Silent Switcher with 6.2µA Quiescent Current +PIN 144 -368 RIGHT 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 12 +PIN 144 304 RIGHT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 15 +PIN 144 -176 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 20 +PIN 144 -272 RIGHT 8 +PINATTR PinName BST2 +PINATTR SpiceOrder 18 +PIN -144 -272 LEFT 8 +PINATTR PinName BST1 +PINATTR SpiceOrder 24 +PIN -144 -176 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 22 +PIN -144 304 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 14 +PIN -144 112 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 29 +PIN -144 -80 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 28 +PIN -144 400 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -144 -368 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 11 +PIN -144 208 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 16 +PIN -64 -432 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN 144 208 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 25 +PIN 144 400 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 26 +PIN 64 -432 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 7 +PIN 144 -80 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 31 +PIN 144 112 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 30 +PIN 64 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 16 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 27 +PIN 144 16 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 32 +PIN -64 448 BOTTOM 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LT8652S.asy b/spice/copy/sym/PowerProducts/LT8652S.asy new file mode 100755 index 0000000..79e5e99 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8652S.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -432 144 656 +TEXT 0 112 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 1 400 Center 2 +SYMATTR Value LT8652S +SYMATTR Prefix X +SYMATTR SpiceModel LT8652S.sub +SYMATTR Value2 LT8652S +SYMATTR Description Dual Channel 8.5A, 18V, Synchronous Step-Down Silent Switcher with 16µA Quiescent Current +PIN 144 592 RIGHT 8 +PINATTR PinName Imon2 +PINATTR SpiceOrder 1 +PIN 144 208 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 2 +PIN -144 496 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN 64 656 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 -368 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 5 +PIN 144 -368 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 9 +PIN 0 -432 TOP 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 13 +PIN 144 400 RIGHT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 15 +PIN -144 400 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 16 +PIN -144 304 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 17 +PIN -64 656 BOTTOM 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 18 +PIN 144 -272 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 19 +PIN 144 -176 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 20 +PIN -144 -176 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 23 +PIN -144 -272 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 26 +PIN 144 496 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 27 +PIN 144 304 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 28 +PIN -144 208 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 29 +PIN -144 592 LEFT 8 +PINATTR PinName Imon1 +PINATTR SpiceOrder 30 +PIN -144 112 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 31 +PIN -144 -80 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 32 +PIN -144 16 LEFT 8 +PINATTR PinName SnsGnd1 +PINATTR SpiceOrder 33 +PIN 144 16 RIGHT 8 +PINATTR PinName SnsGnd2 +PINATTR SpiceOrder 34 +PIN 144 -80 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 35 +PIN 144 112 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 36 diff --git a/spice/copy/sym/PowerProducts/LT8653S.asy b/spice/copy/sym/PowerProducts/LT8653S.asy new file mode 100755 index 0000000..850fa10 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8653S.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -384 144 384 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LT8653S +SYMATTR Prefix X +SYMATTR SpiceModel LT8653S.sub +SYMATTR Value2 LT8653S +SYMATTR Description Dual Channel 2A, 42V, Synchronous Step-Down Silent Switcher with 6.2µA Quiescent Current +PIN -64 384 BOTTOM 8 +PINATTR PinName D0 +PINATTR SpiceOrder 19 +PIN 64 384 BOTTOM 8 +PINATTR PinName D1 +PINATTR SpiceOrder 20 +PIN 144 144 RIGHT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 4 +PIN -144 48 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN -144 336 LEFT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 6 +PIN -144 -336 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 7 +PIN 144 -336 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 9 +PIN 144 240 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 10 +PIN -144 -144 LEFT 8 +PINATTR PinName Vc1 +PINATTR SpiceOrder 11 +PIN -144 -240 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 12 +PIN -144 -48 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 13 +PIN 144 -48 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 14 +PIN 144 -240 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 15 +PIN 144 -144 RIGHT 8 +PINATTR PinName Vc2 +PINATTR SpiceOrder 16 +PIN -144 240 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 17 +PIN 64 -384 TOP 8 +PINATTR PinName EN +PINATTR SpiceOrder 18 +PIN -64 -384 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 144 336 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/PowerProducts/LT8672.asy b/spice/copy/sym/PowerProducts/LT8672.asy new file mode 100755 index 0000000..f56efbf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8672.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -320 -128 304 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8672 +SYMATTR SpiceModel LT8672.sub +SYMATTR Description Active Rectifier Controller with Reverse Protection +SYMATTR Value2 LT8672 +SYMATTR Prefix X +PIN -320 0 LEFT 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 304 0 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 3 +PIN 256 -128 TOP 8 +PINATTR PinName AUXSW +PINATTR SpiceOrder 6 +PIN 128 -128 TOP 8 +PINATTR PinName AUX +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName DRAIN +PINATTR SpiceOrder 8 +PIN -256 -128 TOP 8 +PINATTR PinName SOURCE +PINATTR SpiceOrder 9 +PIN -128 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LT8697.asy b/spice/copy/sym/PowerProducts/LT8697.asy new file mode 100755 index 0000000..996708b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8697.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LT8697 +SYMATTR Prefix X +SYMATTR SpiceModel LT8697.sub +SYMATTR Value2 LT8697 +SYMATTR Description USB 5V 2.5A Output 42V Input Synchronous Buck with Cable Drop Compensation\n\nNote: Sync function is not modeled. +PIN -144 -48 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 4 +PIN -48 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 48 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 13 +PIN 144 -144 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 16 +PIN 48 -304 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 17 +PIN 144 -240 RIGHT 8 +PINATTR PinName SYS +PINATTR SpiceOrder 18 +PIN -144 -144 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 240 RIGHT 8 +PINATTR PinName USB5V +PINATTR SpiceOrder 20 +PIN 144 48 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 21 +PIN 144 144 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 22 +PIN -144 240 LEFT 8 +PINATTR PinName RCBL +PINATTR SpiceOrder 23 +PIN -144 144 LEFT 8 +PINATTR PinName ICTRL +PINATTR SpiceOrder 24 +PIN -48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LT8705.asy b/spice/copy/sym/PowerProducts/LT8705.asy new file mode 100755 index 0000000..f9b9736 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8705.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -576 -400 672 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8705 +SYMATTR Prefix X +SYMATTR SpiceModel LT8705.sub +SYMATTR Value2 LT8705 +SYMATTR Description Synchronous Buck/Boost DC/DC Converter with Soft-Start +PIN -576 -144 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN 112 -400 TOP 8 +PINATTR PinName CSN +PINATTR SpiceOrder 2 +PIN -16 -400 TOP 8 +PINATTR PinName CSP +PINATTR SpiceOrder 3 +PIN -576 -16 LEFT 8 +PINATTR PinName LDO +PINATTR SpiceOrder 4 +PIN -576 112 LEFT 8 +PINATTR PinName FBIN +PINATTR SpiceOrder 5 +PIN 672 -144 RIGHT 8 +PINATTR PinName FBOUT +PINATTR SpiceOrder 6 +PIN 672 368 RIGHT 8 +PINATTR PinName IMON_OUT +PINATTR SpiceOrder 7 +PIN -576 304 LEFT 8 +PINATTR PinName VC +PINATTR SpiceOrder 8 +PIN -576 240 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN 0 400 BOTTOM 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 10 +PIN -576 176 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -320 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 +PIN -144 -400 TOP 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 14 +PIN 672 -16 RIGHT 8 +PINATTR PinName GATEVCC +PINATTR SpiceOrder 15 +PIN 240 -400 TOP 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 16 +PIN 496 -400 TOP 8 +PINATTR PinName BOOST2 +PINATTR SpiceOrder 17 +PIN 624 -400 TOP 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 18 +PIN 368 -400 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN -272 -400 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 21 +PIN -528 -400 TOP 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 22 +PIN -400 -400 TOP 8 +PINATTR PinName BOOST1 +PINATTR SpiceOrder 23 +PIN 672 48 RIGHT 8 +PINATTR PinName SRVO_FBIN +PINATTR SpiceOrder 25 +PIN 672 176 RIGHT 8 +PINATTR PinName SRVO_IIN +PINATTR SpiceOrder 26 +PIN 672 240 RIGHT 8 +PINATTR PinName SRVO_IOUT +PINATTR SpiceOrder 27 +PIN 672 112 RIGHT 8 +PINATTR PinName SRVO_FBOUT +PINATTR SpiceOrder 28 +PIN 672 -208 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 29 +PIN 672 -272 RIGHT 8 +PINATTR PinName CSNOUT +PINATTR SpiceOrder 30 +PIN 672 -336 RIGHT 8 +PINATTR PinName CSPOUT +PINATTR SpiceOrder 31 +PIN -576 -336 LEFT 8 +PINATTR PinName CSNIN +PINATTR SpiceOrder 32 +PIN -576 -272 LEFT 8 +PINATTR PinName CSPIN +PINATTR SpiceOrder 33 +PIN -576 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 34 +PIN 672 -80 RIGHT 8 +PINATTR PinName INTVCC +PINATTR SpiceOrder 35 +PIN -576 -80 LEFT 8 +PINATTR PinName SWEN +PINATTR SpiceOrder 36 +PIN -576 48 LEFT 8 +PINATTR PinName MODE +PINATTR SpiceOrder 37 +PIN 672 304 RIGHT 8 +PINATTR PinName IMON_IN +PINATTR SpiceOrder 38 +PIN 368 400 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LT8705A.asy b/spice/copy/sym/PowerProducts/LT8705A.asy new file mode 100755 index 0000000..1a59c31 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8705A.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -576 -400 672 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8705A +SYMATTR Prefix X +SYMATTR SpiceModel LT8705A.sub +SYMATTR Value2 LT8705A +SYMATTR Description Synchronous Buck/Boost DC/DC Converter with Soft-Start +PIN -576 -144 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN 112 -400 TOP 8 +PINATTR PinName CSN +PINATTR SpiceOrder 2 +PIN -16 -400 TOP 8 +PINATTR PinName CSP +PINATTR SpiceOrder 3 +PIN -576 -16 LEFT 8 +PINATTR PinName LDO +PINATTR SpiceOrder 4 +PIN -576 112 LEFT 8 +PINATTR PinName FBIN +PINATTR SpiceOrder 5 +PIN 672 -144 RIGHT 8 +PINATTR PinName FBOUT +PINATTR SpiceOrder 6 +PIN 672 368 RIGHT 8 +PINATTR PinName IMON_OUT +PINATTR SpiceOrder 7 +PIN -576 304 LEFT 8 +PINATTR PinName VC +PINATTR SpiceOrder 8 +PIN -576 240 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN 0 400 BOTTOM 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 10 +PIN -576 176 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -320 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 +PIN -144 -400 TOP 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 14 +PIN 672 -16 RIGHT 8 +PINATTR PinName GATEVCC +PINATTR SpiceOrder 15 +PIN 240 -400 TOP 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 16 +PIN 496 -400 TOP 8 +PINATTR PinName BOOST2 +PINATTR SpiceOrder 17 +PIN 624 -400 TOP 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 18 +PIN 368 -400 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN -272 -400 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 21 +PIN -528 -400 TOP 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 22 +PIN -400 -400 TOP 8 +PINATTR PinName BOOST1 +PINATTR SpiceOrder 23 +PIN 672 48 RIGHT 8 +PINATTR PinName SRVO_FBIN +PINATTR SpiceOrder 25 +PIN 672 176 RIGHT 8 +PINATTR PinName SRVO_IIN +PINATTR SpiceOrder 26 +PIN 672 240 RIGHT 8 +PINATTR PinName SRVO_IOUT +PINATTR SpiceOrder 27 +PIN 672 112 RIGHT 8 +PINATTR PinName SRVO_FBOUT +PINATTR SpiceOrder 28 +PIN 672 -208 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 29 +PIN 672 -272 RIGHT 8 +PINATTR PinName CSNOUT +PINATTR SpiceOrder 30 +PIN 672 -336 RIGHT 8 +PINATTR PinName CSPOUT +PINATTR SpiceOrder 31 +PIN -576 -336 LEFT 8 +PINATTR PinName CSNIN +PINATTR SpiceOrder 32 +PIN -576 -272 LEFT 8 +PINATTR PinName CSPIN +PINATTR SpiceOrder 33 +PIN -576 -208 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 34 +PIN 672 -80 RIGHT 8 +PINATTR PinName INTVCC +PINATTR SpiceOrder 35 +PIN -576 -80 LEFT 8 +PINATTR PinName SWEN +PINATTR SpiceOrder 36 +PIN -576 48 LEFT 8 +PINATTR PinName MODE +PINATTR SpiceOrder 37 +PIN 672 304 RIGHT 8 +PINATTR PinName IMON_IN +PINATTR SpiceOrder 38 +PIN 368 400 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LT8708-1.asy b/spice/copy/sym/PowerProducts/LT8708-1.asy new file mode 100755 index 0000000..9be489b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8708-1.asy @@ -0,0 +1,131 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -624 -384 624 384 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8708-1 +SYMATTR Prefix X +SYMATTR SpiceModel LT8708-1.sub +SYMATTR Value2 LT8708-1 +SYMATTR Description 80V Synchronous 4-Switch Buck-Boost Slave Controller for LT8708 Multiphase System +PIN -624 -128 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN 64 -384 TOP 8 +PINATTR PinName CSN +PINATTR SpiceOrder 2 +PIN -64 -384 TOP 8 +PINATTR PinName CSP +PINATTR SpiceOrder 3 +PIN -624 0 LEFT 8 +PINATTR PinName LDO33 +PINATTR SpiceOrder 4 +PIN -624 128 LEFT 8 +PINATTR PinName FBIN +PINATTR SpiceOrder 5 +PIN 624 -128 RIGHT 8 +PINATTR PinName FBOUT +PINATTR SpiceOrder 6 +PIN 624 320 RIGHT 8 +PINATTR PinName IMON_OP +PINATTR SpiceOrder 7 +PIN 624 192 RIGHT 8 +PINATTR PinName VC +PINATTR SpiceOrder 8 +PIN -624 256 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN 64 384 BOTTOM 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 10 +PIN -80 384 BOTTOM 8 +PINATTR PinName _RVSOFF +PINATTR SpiceOrder 11 +PIN -624 192 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -224 384 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 +PIN -192 -384 TOP 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 14 +PIN 624 0 RIGHT 8 +PINATTR PinName GATEVCC +PINATTR SpiceOrder 15 +PIN 192 -384 TOP 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 16 +PIN 448 -384 TOP 8 +PINATTR PinName BOOST2 +PINATTR SpiceOrder 17 +PIN 576 -384 TOP 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 18 +PIN 320 -384 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN -320 -384 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 21 +PIN -576 -384 TOP 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 22 +PIN -448 -384 TOP 8 +PINATTR PinName BOOST1 +PINATTR SpiceOrder 23 +PIN 624 -192 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 29 +PIN 624 -256 RIGHT 8 +PINATTR PinName CSNOUT +PINATTR SpiceOrder 30 +PIN 624 -320 RIGHT 8 +PINATTR PinName CSPOUT +PINATTR SpiceOrder 31 +PIN -624 -320 LEFT 8 +PINATTR PinName CSNIN +PINATTR SpiceOrder 32 +PIN -624 -256 LEFT 8 +PINATTR PinName CSPIN +PINATTR SpiceOrder 33 +PIN -624 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 34 +PIN 624 -64 RIGHT 8 +PINATTR PinName INTVCC +PINATTR SpiceOrder 35 +PIN -624 -64 LEFT 8 +PINATTR PinName SWEN +PINATTR SpiceOrder 36 +PIN -624 64 LEFT 8 +PINATTR PinName MODE +PINATTR SpiceOrder 37 +PIN 624 256 RIGHT 8 +PINATTR PinName IMON_INP +PINATTR SpiceOrder 38 +PIN 208 384 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 39 +PIN -368 384 BOTTOM 8 +PINATTR PinName DIR +PINATTR SpiceOrder 42 +PIN 496 384 BOTTOM 8 +PINATTR PinName IMON_ON +PINATTR SpiceOrder 43 +PIN 352 384 BOTTOM 8 +PINATTR PinName IMON_INN +PINATTR SpiceOrder 44 +PIN -624 320 LEFT 8 +PINATTR PinName VINHIMON +PINATTR SpiceOrder 45 +PIN -512 384 BOTTOM 8 +PINATTR PinName VOUTLOMON +PINATTR SpiceOrder 46 +PIN 624 64 RIGHT 8 +PINATTR PinName ICP +PINATTR SpiceOrder 47 +PIN 624 128 RIGHT 8 +PINATTR PinName ICN +PINATTR SpiceOrder 48 diff --git a/spice/copy/sym/PowerProducts/LT8708.asy b/spice/copy/sym/PowerProducts/LT8708.asy new file mode 100755 index 0000000..8eb7283 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8708.asy @@ -0,0 +1,131 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -624 -384 624 384 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8708 +SYMATTR Prefix X +SYMATTR SpiceModel LT8708.sub +SYMATTR Value2 LT8708 +SYMATTR Description 80V Synchronous 4-Switch Buck-Boost DC/DC Controller with Flexible Bidirectional Capability +PIN -624 -128 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN 64 -384 TOP 8 +PINATTR PinName CSN +PINATTR SpiceOrder 2 +PIN -64 -384 TOP 8 +PINATTR PinName CSP +PINATTR SpiceOrder 3 +PIN -624 0 LEFT 8 +PINATTR PinName LDO33 +PINATTR SpiceOrder 4 +PIN -624 128 LEFT 8 +PINATTR PinName FBIN +PINATTR SpiceOrder 5 +PIN 624 -128 RIGHT 8 +PINATTR PinName FBOUT +PINATTR SpiceOrder 6 +PIN 624 320 RIGHT 8 +PINATTR PinName IMON_OP +PINATTR SpiceOrder 7 +PIN 624 192 RIGHT 8 +PINATTR PinName VC +PINATTR SpiceOrder 8 +PIN -624 256 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN 64 384 BOTTOM 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 10 +PIN -80 384 BOTTOM 8 +PINATTR PinName _RVSOFF +PINATTR SpiceOrder 11 +PIN -624 192 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -224 384 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 +PIN -192 -384 TOP 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 14 +PIN 624 0 RIGHT 8 +PINATTR PinName GATEVCC +PINATTR SpiceOrder 15 +PIN 192 -384 TOP 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 16 +PIN 448 -384 TOP 8 +PINATTR PinName BOOST2 +PINATTR SpiceOrder 17 +PIN 576 -384 TOP 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 18 +PIN 320 -384 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN -320 -384 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 21 +PIN -576 -384 TOP 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 22 +PIN -448 -384 TOP 8 +PINATTR PinName BOOST1 +PINATTR SpiceOrder 23 +PIN 624 -192 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 29 +PIN 624 -256 RIGHT 8 +PINATTR PinName CSNOUT +PINATTR SpiceOrder 30 +PIN 624 -320 RIGHT 8 +PINATTR PinName CSPOUT +PINATTR SpiceOrder 31 +PIN -624 -320 LEFT 8 +PINATTR PinName CSNIN +PINATTR SpiceOrder 32 +PIN -624 -256 LEFT 8 +PINATTR PinName CSPIN +PINATTR SpiceOrder 33 +PIN -624 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 34 +PIN 624 -64 RIGHT 8 +PINATTR PinName INTVCC +PINATTR SpiceOrder 35 +PIN -624 -64 LEFT 8 +PINATTR PinName SWEN +PINATTR SpiceOrder 36 +PIN -624 64 LEFT 8 +PINATTR PinName MODE +PINATTR SpiceOrder 37 +PIN 624 256 RIGHT 8 +PINATTR PinName IMON_INP +PINATTR SpiceOrder 38 +PIN 208 384 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 39 +PIN -368 384 BOTTOM 8 +PINATTR PinName DIR +PINATTR SpiceOrder 42 +PIN 496 384 BOTTOM 8 +PINATTR PinName IMON_ON +PINATTR SpiceOrder 43 +PIN 352 384 BOTTOM 8 +PINATTR PinName IMON_INN +PINATTR SpiceOrder 44 +PIN -624 320 LEFT 8 +PINATTR PinName VINHIMON +PINATTR SpiceOrder 45 +PIN -512 384 BOTTOM 8 +PINATTR PinName VOUTLOMON +PINATTR SpiceOrder 46 +PIN 624 64 RIGHT 8 +PINATTR PinName ICP +PINATTR SpiceOrder 47 +PIN 624 128 RIGHT 8 +PINATTR PinName ICN +PINATTR SpiceOrder 48 diff --git a/spice/copy/sym/PowerProducts/LT8709.asy b/spice/copy/sym/PowerProducts/LT8709.asy new file mode 100755 index 0000000..464837c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8709.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -208 208 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8709 +SYMATTR Prefix X +SYMATTR SpiceModel LT8709.sub +SYMATTR Value2 LT8709 +SYMATTR Description Synchronous Boost/Inverting DC/DC Converter with Soft-Start +PIN 208 112 RIGHT 8 +PINATTR PinName FBY +PINATTR SpiceOrder 1 +PIN 208 160 RIGHT 8 +PINATTR PinName VC +PINATTR SpiceOrder 2 +PIN 96 224 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN 208 64 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN -16 224 BOTTOM 8 +PINATTR PinName IMON +PINATTR SpiceOrder 5 +PIN 208 -128 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 6 +PIN 208 -80 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 7 +PIN 208 -32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 8 +PIN 208 16 RIGHT 8 +PINATTR PinName INTVEE +PINATTR SpiceOrder 9 +PIN 144 -208 TOP 8 +PINATTR PinName TG +PINATTR SpiceOrder 10 +PIN -144 -208 TOP 8 +PINATTR PinName BG +PINATTR SpiceOrder 11 +PIN -208 16 LEFT 8 +PINATTR PinName INTVCC +PINATTR SpiceOrder 12 +PIN -208 -128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 +PIN 32 -208 TOP 8 +PINATTR PinName CSN +PINATTR SpiceOrder 14 +PIN -32 -208 TOP 8 +PINATTR PinName CSP +PINATTR SpiceOrder 15 +PIN -208 -80 LEFT 8 +PINATTR PinName EN/FBIN +PINATTR SpiceOrder 16 +PIN -208 -32 LEFT 8 +PINATTR PinName MODE +PINATTR SpiceOrder 17 +PIN -208 64 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 18 +PIN -144 224 BOTTOM 8 +PINATTR PinName -VIN +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8710.asy b/spice/copy/sym/PowerProducts/LT8710.asy new file mode 100755 index 0000000..553cbbd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8710.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -208 208 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT8710 +SYMATTR Prefix X +SYMATTR SpiceModel LT8710.sub +SYMATTR Value2 LT8710 +SYMATTR Description Synchronous Boost/Inverting DC/DC Converter with Soft-Start +PIN 208 96 RIGHT 8 +PINATTR PinName FBX +PINATTR SpiceOrder 1 +PIN 208 160 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 112 208 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -208 160 LEFT 8 +PINATTR PinName Flag +PINATTR SpiceOrder 4 +PIN -128 208 BOTTOM 8 +PINATTR PinName Imon +PINATTR SpiceOrder 5 +PIN 208 -96 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 6 +PIN 208 -160 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 7 +PIN -208 96 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 8 +PIN 208 -32 RIGHT 8 +PINATTR PinName IntVee +PINATTR SpiceOrder 9 +PIN 144 -208 TOP 8 +PINATTR PinName TG +PINATTR SpiceOrder 10 +PIN -144 -208 TOP 8 +PINATTR PinName BG +PINATTR SpiceOrder 11 +PIN -208 32 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 12 +PIN -208 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 32 -208 TOP 8 +PINATTR PinName CSN +PINATTR SpiceOrder 14 +PIN -32 -208 TOP 8 +PINATTR PinName CSP +PINATTR SpiceOrder 15 +PIN -208 -96 LEFT 8 +PINATTR PinName EN/FBin +PINATTR SpiceOrder 16 +PIN -208 -32 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 17 +PIN 208 32 RIGHT 8 +PINATTR PinName RT +PINATTR SpiceOrder 18 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LT8711.asy b/spice/copy/sym/PowerProducts/LT8711.asy new file mode 100755 index 0000000..bf5fe5b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8711.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -288 208 272 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LT8711 +SYMATTR Prefix X +SYMATTR SpiceModel LT8711.sub +SYMATTR Value2 LT8711 +SYMATTR Description µPower Synchronous Multitopology Controller with 42V Input Capability +PIN 208 224 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 +PIN -208 160 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN -208 224 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN -208 -160 LEFT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 14 +PIN 208 160 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 5 +PIN 208 96 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 4 +PIN -208 32 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 17 +PIN 208 -224 RIGHT 8 +PINATTR PinName IntVee +PINATTR SpiceOrder 6 +PIN 208 -160 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 8 +PIN 208 -96 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 10 +PIN -208 -32 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 12 +PIN -96 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN -208 -224 LEFT 8 +PINATTR PinName EN/FBin +PINATTR SpiceOrder 19 +PIN -208 -96 LEFT 8 +PINATTR PinName OpMode +PINATTR SpiceOrder 3 +PIN -208 96 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 18 +PIN 0 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 21 +PIN 96 -288 TOP 8 +PINATTR PinName Bias +PINATTR SpiceOrder 7 +PIN 208 32 RIGHT 8 +PINATTR PinName CSN +PINATTR SpiceOrder 15 +PIN 208 -32 RIGHT 8 +PINATTR PinName CSP +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LT8714.asy b/spice/copy/sym/PowerProducts/LT8714.asy new file mode 100755 index 0000000..a9f5488 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LT8714.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -208 208 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LT8714 +SYMATTR Prefix X +SYMATTR SpiceModel LT8714.sub +SYMATTR Value2 LT8714 +SYMATTR Description Bipolar Output Synchronous Controller with Seamless Four Quadrant Operation +PIN 208 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 208 176 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 2 +PIN 96 224 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -208 -32 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 4 +PIN -16 224 BOTTOM 8 +PINATTR PinName Imon +PINATTR SpiceOrder 5 +PIN 208 -80 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 6 +PIN 208 -128 RIGHT 8 +PINATTR PinName ISP +PINATTR SpiceOrder 7 +PIN 208 -32 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 8 +PIN 208 16 RIGHT 8 +PINATTR PinName INTVee +PINATTR SpiceOrder 9 +PIN 144 -208 TOP 8 +PINATTR PinName Tg +PINATTR SpiceOrder 10 +PIN -144 -208 TOP 8 +PINATTR PinName BG +PINATTR SpiceOrder 11 +PIN -208 16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 12 +PIN -208 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 32 -208 TOP 8 +PINATTR PinName CSN +PINATTR SpiceOrder 14 +PIN -32 -208 TOP 8 +PINATTR PinName CSP +PINATTR SpiceOrder 15 +PIN -208 -80 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 16 +PIN 208 112 RIGHT 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 17 +PIN -208 64 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 18 +PIN -144 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC1044.asy b/spice/copy/sym/PowerProducts/LTC1044.asy new file mode 100755 index 0000000..cf2363f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1044.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 63 Center 2 +SYMATTR Value LTC1044/7660 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1044.sub +SYMATTR Value2 LTC1044 +SYMATTR Description Switched Capacitor Voltage Converter +PIN -128 -96 LEFT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Cap+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName Cap- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName LV +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1044A.asy b/spice/copy/sym/PowerProducts/LTC1044A.asy new file mode 100755 index 0000000..c9d39f8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1044A.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1044A +SYMATTR Prefix X +SYMATTR SpiceModel LTC1044A.sub +SYMATTR Value2 LTC1044A +SYMATTR Description 12V CMOS Switched Capacitor Voltage Converter +PIN -128 -96 LEFT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Cap+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName Cap- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName LV +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1046.asy b/spice/copy/sym/PowerProducts/LTC1046.asy new file mode 100755 index 0000000..47a7656 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1046.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1046 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1046.sub +SYMATTR Value2 LTC1046 +SYMATTR Description "Inductorless" 5V to -5V Converter +PIN -128 -96 LEFT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Cap+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName Cap- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName LV +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1142.asy b/spice/copy/sym/PowerProducts/LTC1142.asy new file mode 100755 index 0000000..7b82a58 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1142.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -240 400 240 +TEXT 0 -40 Center 2 LT +WINDOW 0 -1 -168 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1142 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1142.sub +SYMATTR Value2 LTC1142 +SYMATTR Description Dual High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 3.3V and 5V Outputs +PIN -400 -80 LEFT 8 +PINATTR PinName Sense+3 +PINATTR SpiceOrder 1 +PIN -160 -240 TOP 8 +PINATTR PinName SHDN3 +PINATTR SpiceOrder 2 +PIN -176 240 BOTTOM 8 +PINATTR PinName SGND3 +PINATTR SpiceOrder 3 +PIN -320 240 BOTTOM 8 +PINATTR PinName PGND3 +PINATTR SpiceOrder 4 +PIN -400 80 LEFT 8 +PINATTR PinName N-drive3 +PINATTR SpiceOrder 6 +PIN 400 -160 RIGHT 8 +PINATTR PinName P-drive5 +PINATTR SpiceOrder 9 +PIN 320 -240 TOP 8 +PINATTR PinName Vin5 +PINATTR SpiceOrder 10 +PIN 48 240 BOTTOM 8 +PINATTR PinName Ct5 +PINATTR SpiceOrder 11 +PIN 400 160 RIGHT 8 +PINATTR PinName Ith5 +PINATTR SpiceOrder 13 +PIN 400 0 RIGHT 8 +PINATTR PinName Sense-5 +PINATTR SpiceOrder 14 +PIN 400 -80 RIGHT 8 +PINATTR PinName Sense+5 +PINATTR SpiceOrder 15 +PIN 160 -240 TOP 8 +PINATTR PinName SHDN5 +PINATTR SpiceOrder 16 +PIN 176 240 BOTTOM 8 +PINATTR PinName SGND5 +PINATTR SpiceOrder 17 +PIN 320 240 BOTTOM 8 +PINATTR PinName PGND5 +PINATTR SpiceOrder 18 +PIN 400 80 RIGHT 8 +PINATTR PinName N-drive5 +PINATTR SpiceOrder 20 +PIN -400 -160 LEFT 8 +PINATTR PinName P-drive3 +PINATTR SpiceOrder 23 +PIN -320 -240 TOP 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 24 +PIN -48 240 BOTTOM 8 +PINATTR PinName Ct3 +PINATTR SpiceOrder 25 +PIN -400 160 LEFT 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 27 +PIN -400 0 LEFT 8 +PINATTR PinName Sense-3 +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1142HV-ADJ.asy b/spice/copy/sym/PowerProducts/LTC1142HV-ADJ.asy new file mode 100755 index 0000000..56b308a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1142HV-ADJ.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -240 400 320 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1142HV-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel LTC1142-ADJ.sub +SYMATTR Value2 LTC1142-ADJ +SYMATTR Description Dual High Efficiency Synchronous Step-Down Switching Regulator Controller, Adjustable Output Voltages +PIN -400 -80 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 1 +PIN -400 240 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 2 +PIN -160 -240 TOP 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 3 +PIN -176 320 BOTTOM 8 +PINATTR PinName SGND1 +PINATTR SpiceOrder 4 +PIN -320 320 BOTTOM 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 5 +PIN -400 80 LEFT 8 +PINATTR PinName N-drive1 +PINATTR SpiceOrder 6 +PIN 400 -160 RIGHT 8 +PINATTR PinName P-drive2 +PINATTR SpiceOrder 9 +PIN 320 -240 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 10 +PIN 48 320 BOTTOM 8 +PINATTR PinName Ct2 +PINATTR SpiceOrder 11 +PIN 400 160 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 13 +PIN 400 0 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 14 +PIN 400 -80 RIGHT 8 +PINATTR PinName Sense+2 +PINATTR SpiceOrder 15 +PIN 400 240 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 16 +PIN 160 -240 TOP 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 17 +PIN 176 320 BOTTOM 8 +PINATTR PinName SGND2 +PINATTR SpiceOrder 18 +PIN 320 320 BOTTOM 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 19 +PIN 400 80 RIGHT 8 +PINATTR PinName N-drive2 +PINATTR SpiceOrder 20 +PIN -400 -160 LEFT 8 +PINATTR PinName P-drive1 +PINATTR SpiceOrder 23 +PIN -320 -240 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 24 +PIN -48 320 BOTTOM 8 +PINATTR PinName Ct1 +PINATTR SpiceOrder 25 +PIN -400 160 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 27 +PIN -400 0 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1142HV.asy b/spice/copy/sym/PowerProducts/LTC1142HV.asy new file mode 100755 index 0000000..ed10da3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1142HV.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -240 400 240 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1142HV +SYMATTR Prefix X +SYMATTR SpiceModel LTC1142.sub +SYMATTR Value2 LTC1142 +SYMATTR Description Dual High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 3.3V and 5V Outputs +PIN -400 -80 LEFT 8 +PINATTR PinName Sense+3 +PINATTR SpiceOrder 1 +PIN -160 -240 TOP 8 +PINATTR PinName SHDN3 +PINATTR SpiceOrder 2 +PIN -176 240 BOTTOM 8 +PINATTR PinName SGND3 +PINATTR SpiceOrder 3 +PIN -320 240 BOTTOM 8 +PINATTR PinName PGND3 +PINATTR SpiceOrder 4 +PIN -400 80 LEFT 8 +PINATTR PinName N-drive3 +PINATTR SpiceOrder 6 +PIN 400 -160 RIGHT 8 +PINATTR PinName P-drive5 +PINATTR SpiceOrder 9 +PIN 320 -240 TOP 8 +PINATTR PinName Vin5 +PINATTR SpiceOrder 10 +PIN 48 240 BOTTOM 8 +PINATTR PinName Ct5 +PINATTR SpiceOrder 11 +PIN 400 160 RIGHT 8 +PINATTR PinName Ith5 +PINATTR SpiceOrder 13 +PIN 400 0 RIGHT 8 +PINATTR PinName Sense-5 +PINATTR SpiceOrder 14 +PIN 400 -80 RIGHT 8 +PINATTR PinName Sense+5 +PINATTR SpiceOrder 15 +PIN 160 -240 TOP 8 +PINATTR PinName SHDN5 +PINATTR SpiceOrder 16 +PIN 176 240 BOTTOM 8 +PINATTR PinName SGND5 +PINATTR SpiceOrder 17 +PIN 320 240 BOTTOM 8 +PINATTR PinName PGND5 +PINATTR SpiceOrder 18 +PIN 400 80 RIGHT 8 +PINATTR PinName N-drive5 +PINATTR SpiceOrder 20 +PIN -400 -160 LEFT 8 +PINATTR PinName P-drive3 +PINATTR SpiceOrder 23 +PIN -320 -240 TOP 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 24 +PIN -48 240 BOTTOM 8 +PINATTR PinName Ct3 +PINATTR SpiceOrder 25 +PIN -400 160 LEFT 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 27 +PIN -400 0 LEFT 8 +PINATTR PinName Sense-3 +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1142L-ADJ.asy b/spice/copy/sym/PowerProducts/LTC1142L-ADJ.asy new file mode 100755 index 0000000..616858a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1142L-ADJ.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -240 400 320 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1142L-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel LTC1142-ADJ.sub +SYMATTR Value2 LTC1142-ADJ +SYMATTR Description Dual High Efficiency Synchronous Step-Down Switching Regulator Controller, Adjustable Output Voltages +PIN -400 -80 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 1 +PIN -400 240 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 2 +PIN -160 -240 TOP 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 3 +PIN -176 320 BOTTOM 8 +PINATTR PinName SGND1 +PINATTR SpiceOrder 4 +PIN -320 320 BOTTOM 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 5 +PIN -400 80 LEFT 8 +PINATTR PinName N-drive1 +PINATTR SpiceOrder 6 +PIN 400 -160 RIGHT 8 +PINATTR PinName P-drive2 +PINATTR SpiceOrder 9 +PIN 320 -240 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 10 +PIN 48 320 BOTTOM 8 +PINATTR PinName Ct2 +PINATTR SpiceOrder 11 +PIN 400 160 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 13 +PIN 400 0 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 14 +PIN 400 -80 RIGHT 8 +PINATTR PinName Sense+2 +PINATTR SpiceOrder 15 +PIN 400 240 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 16 +PIN 160 -240 TOP 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 17 +PIN 176 320 BOTTOM 8 +PINATTR PinName SGND2 +PINATTR SpiceOrder 18 +PIN 320 320 BOTTOM 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 19 +PIN 400 80 RIGHT 8 +PINATTR PinName N-drive2 +PINATTR SpiceOrder 20 +PIN -400 -160 LEFT 8 +PINATTR PinName P-drive1 +PINATTR SpiceOrder 23 +PIN -320 -240 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 24 +PIN -48 320 BOTTOM 8 +PINATTR PinName Ct1 +PINATTR SpiceOrder 25 +PIN -400 160 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 27 +PIN -400 0 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1143.asy b/spice/copy/sym/PowerProducts/LTC1143.asy new file mode 100755 index 0000000..5c52692 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1143.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -240 256 240 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1143 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1143.sub +SYMATTR Value2 LTC1143 +SYMATTR Description Dual High Efficiency SO-16 Step-Down Switching Regulator Controller, Fixed 3.3V and 5V Outputs +PIN -256 -80 LEFT 8 +PINATTR PinName Sense+3 +PINATTR SpiceOrder 1 +PIN -256 80 LEFT 8 +PINATTR PinName SHDN3 +PINATTR SpiceOrder 2 +PIN -192 240 BOTTOM 8 +PINATTR PinName GND3 +PINATTR SpiceOrder 3 +PIN -256 -160 LEFT 8 +PINATTR PinName P-drive3 +PINATTR SpiceOrder 4 +PIN 128 -240 TOP 8 +PINATTR PinName Vin5 +PINATTR SpiceOrder 5 +PIN 64 240 BOTTOM 8 +PINATTR PinName Ct5 +PINATTR SpiceOrder 6 +PIN 256 160 RIGHT 8 +PINATTR PinName Ith5 +PINATTR SpiceOrder 7 +PIN 256 0 RIGHT 8 +PINATTR PinName Sense-5 +PINATTR SpiceOrder 8 +PIN 256 -80 RIGHT 8 +PINATTR PinName Sense+5 +PINATTR SpiceOrder 9 +PIN 256 80 RIGHT 8 +PINATTR PinName SHND5 +PINATTR SpiceOrder 10 +PIN 192 240 BOTTOM 8 +PINATTR PinName GND5 +PINATTR SpiceOrder 11 +PIN 256 -160 RIGHT 8 +PINATTR PinName P-drive5 +PINATTR SpiceOrder 12 +PIN -128 -240 TOP 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 13 +PIN -64 240 BOTTOM 8 +PINATTR PinName Ct3 +PINATTR SpiceOrder 14 +PIN -256 160 LEFT 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 15 +PIN -256 0 LEFT 8 +PINATTR PinName Sense-3 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1143L-ADJ.asy b/spice/copy/sym/PowerProducts/LTC1143L-ADJ.asy new file mode 100755 index 0000000..331c36d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1143L-ADJ.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -240 256 240 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1143L-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel LTC1143L-ADJ.sub +SYMATTR Value2 LTC1143L-ADJ +SYMATTR Description Dual High Efficiency SO-16 Step-Down Switching Regulator Controller, Adjustable Output Voltages +PIN -256 -80 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 1 +PIN -256 80 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 2 +PIN -192 240 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN -256 -160 LEFT 8 +PINATTR PinName P-drive1 +PINATTR SpiceOrder 4 +PIN 128 -240 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 5 +PIN 64 240 BOTTOM 8 +PINATTR PinName Ct2 +PINATTR SpiceOrder 6 +PIN 256 160 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 7 +PIN 256 0 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 8 +PIN 256 -80 RIGHT 8 +PINATTR PinName Sense+2 +PINATTR SpiceOrder 9 +PIN 256 80 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 10 +PIN 192 240 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 11 +PIN 256 -160 RIGHT 8 +PINATTR PinName P-drive2 +PINATTR SpiceOrder 12 +PIN -128 -240 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 13 +PIN -64 240 BOTTOM 8 +PINATTR PinName Ct1 +PINATTR SpiceOrder 14 +PIN -256 160 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 15 +PIN -256 0 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1143L.asy b/spice/copy/sym/PowerProducts/LTC1143L.asy new file mode 100755 index 0000000..1099d59 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1143L.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -240 256 240 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1143L +SYMATTR Prefix X +SYMATTR SpiceModel LTC1143.sub +SYMATTR Value2 LTC1143 +SYMATTR Description Dual High Efficiency SO-16 Step-Down Switching Regulator Controller, Fixed 3.3V and 5V Outputs +PIN -256 -80 LEFT 8 +PINATTR PinName Sense+3 +PINATTR SpiceOrder 1 +PIN -256 80 LEFT 8 +PINATTR PinName SHDN3 +PINATTR SpiceOrder 2 +PIN -192 240 BOTTOM 8 +PINATTR PinName GND3 +PINATTR SpiceOrder 3 +PIN -256 -160 LEFT 8 +PINATTR PinName P-drive3 +PINATTR SpiceOrder 4 +PIN 128 -240 TOP 8 +PINATTR PinName Vin5 +PINATTR SpiceOrder 5 +PIN 64 240 BOTTOM 8 +PINATTR PinName Ct5 +PINATTR SpiceOrder 6 +PIN 256 160 RIGHT 8 +PINATTR PinName Ith5 +PINATTR SpiceOrder 7 +PIN 256 0 RIGHT 8 +PINATTR PinName Sense-5 +PINATTR SpiceOrder 8 +PIN 256 -80 RIGHT 8 +PINATTR PinName Sense+5 +PINATTR SpiceOrder 9 +PIN 256 80 RIGHT 8 +PINATTR PinName SHND5 +PINATTR SpiceOrder 10 +PIN 192 240 BOTTOM 8 +PINATTR PinName GND5 +PINATTR SpiceOrder 11 +PIN 256 -160 RIGHT 8 +PINATTR PinName P-drive5 +PINATTR SpiceOrder 12 +PIN -128 -240 TOP 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 13 +PIN -64 240 BOTTOM 8 +PINATTR PinName Ct3 +PINATTR SpiceOrder 14 +PIN -256 160 LEFT 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 15 +PIN -256 0 LEFT 8 +PINATTR PinName Sense-3 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1144.asy b/spice/copy/sym/PowerProducts/LTC1144.asy new file mode 100755 index 0000000..dd2058f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1144.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1144 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1144.sub +SYMATTR Value2 LTC1144 +SYMATTR Description Switched-Capacitor Wide Input Range Voltage Converter with Shutdown +PIN -128 -96 LEFT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Cap+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName Cap- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1147-3.3.asy b/spice/copy/sym/PowerProducts/LTC1147-3.3.asy new file mode 100755 index 0000000..8707a74 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1147-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -55 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value LTC1147-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1147-3.3.sub +SYMATTR Value2 LTC1147-3.3 +SYMATTR Description High Efficiency Step-Down Switching Regulator Controller, Fixed 3.3V Output +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN 160 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 5 +PIN -160 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 160 -80 RIGHT 8 +PINATTR PinName Pdrive +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1147-5.asy b/spice/copy/sym/PowerProducts/LTC1147-5.asy new file mode 100755 index 0000000..83df65c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1147-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 0 57 Center 2 +SYMATTR Value LTC1147-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1147-5.sub +SYMATTR Value2 LTC1147-5 +SYMATTR Description High Efficiency Step-Down Switching Regulator Controller, Fixed 5V Output +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN 160 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 5 +PIN -160 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 160 -80 RIGHT 8 +PINATTR PinName Pdrive +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1147L-3.3.asy b/spice/copy/sym/PowerProducts/LTC1147L-3.3.asy new file mode 100755 index 0000000..089f47a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1147L-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value LTC1147L-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1147-3.3.sub +SYMATTR Value2 LTC1147-3.3 +SYMATTR Description High Efficiency Step-Down Switching Regulator Controller, Fixed 3.3V Output +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN 160 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 5 +PIN -160 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 6 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 160 -80 RIGHT 8 +PINATTR PinName Pdrive +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1147L.asy b/spice/copy/sym/PowerProducts/LTC1147L.asy new file mode 100755 index 0000000..1adc75b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1147L.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1147L +SYMATTR Prefix X +SYMATTR SpiceModel LTC1147.sub +SYMATTR Value2 LTC1147 +SYMATTR Description High Efficiency Step-Down Switching Regulator Controller, Adjustable Output Voltage +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN 160 32 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN 160 -32 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 5 +PIN 160 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName Pdrive +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1148-3.3.asy b/spice/copy/sym/PowerProducts/LTC1148-3.3.asy new file mode 100755 index 0000000..2c26ac8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1148-3.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1148-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1148-3.3.sub +SYMATTR Value2 LTC1148-3.3 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 3.3V Output +PIN 176 -144 RIGHT 8 +PINATTR PinName P-drive +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 -64 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN -176 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN -96 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 96 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName N-drive +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1148-5.asy b/spice/copy/sym/PowerProducts/LTC1148-5.asy new file mode 100755 index 0000000..adee4e1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1148-5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1148-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1148-5.sub +SYMATTR Value2 LTC1148-5 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 5V Output +PIN 176 -144 RIGHT 8 +PINATTR PinName P-drive +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 -64 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN -176 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN -96 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 96 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName N-drive +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1148.asy b/spice/copy/sym/PowerProducts/LTC1148.asy new file mode 100755 index 0000000..c3daf6e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1148.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1148 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1148.sub +SYMATTR Value2 LTC1148 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Adjustable Output Voltage +PIN 176 -144 RIGHT 8 +PINATTR PinName P-drive +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 -64 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN 112 192 BOTTOM 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN -112 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 0 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName N-drive +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1148HV-3.3.asy b/spice/copy/sym/PowerProducts/LTC1148HV-3.3.asy new file mode 100755 index 0000000..a48831e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1148HV-3.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -105 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1148HV-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1148-3.3.sub +SYMATTR Value2 LTC1148-3.3 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 3.3V Output +PIN 176 -144 RIGHT 8 +PINATTR PinName P-drive +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 -64 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN -176 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN -96 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 96 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName N-drive +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1148HV-5.asy b/spice/copy/sym/PowerProducts/LTC1148HV-5.asy new file mode 100755 index 0000000..82db053 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1148HV-5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 192 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -104 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1148HV-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1148-5.sub +SYMATTR Value2 LTC1148-5 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 5V Output +PIN 176 -144 RIGHT 8 +PINATTR PinName P-drive +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 -64 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN -176 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN -96 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 96 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName N-drive +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1148HV.asy b/spice/copy/sym/PowerProducts/LTC1148HV.asy new file mode 100755 index 0000000..17b8618 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1148HV.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1148HV +SYMATTR Prefix X +SYMATTR SpiceModel LTC1148.sub +SYMATTR Value2 LTC1148 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Adjustable Output Voltage +PIN 176 -144 RIGHT 8 +PINATTR PinName P-drive +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 -64 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN 112 192 BOTTOM 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN -112 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 0 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName N-drive +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1148L-3.3.asy b/spice/copy/sym/PowerProducts/LTC1148L-3.3.asy new file mode 100755 index 0000000..9de3acb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1148L-3.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1148L-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1148-3.3.sub +SYMATTR Value2 LTC1148-3.3 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 3.3V Output +PIN 176 -144 RIGHT 8 +PINATTR PinName P-drive +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 -64 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN -176 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN -96 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 96 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName N-drive +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1148L.asy b/spice/copy/sym/PowerProducts/LTC1148L.asy new file mode 100755 index 0000000..86cad0e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1148L.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 176 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1148L +SYMATTR Prefix X +SYMATTR SpiceModel LTC1148.sub +SYMATTR Value2 LTC1148 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Adjustable Output Voltage +PIN 176 -144 RIGHT 8 +PINATTR PinName P-drive +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 -64 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN 112 192 BOTTOM 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -176 -80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN -112 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 0 192 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName N-drive +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1149-3.3.asy b/spice/copy/sym/PowerProducts/LTC1149-3.3.asy new file mode 100755 index 0000000..911390f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1149-3.3.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -224 208 224 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1149-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1149-3.3.sub +SYMATTR Value2 LTC1149-3.3 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 3.3V Output +PIN 208 -160 RIGHT 8 +PINATTR PinName P-Gate +PINATTR SpiceOrder 1 +PIN 96 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -208 -160 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 208 -80 RIGHT 8 +PINATTR PinName P-Drive +PINATTR SpiceOrder 4 +PIN -208 160 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -208 80 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN -208 -80 LEFT 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 10 +PIN -128 224 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 128 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 208 160 RIGHT 8 +PINATTR PinName N-Gate +PINATTR SpiceOrder 13 +PIN 0 224 BOTTOM 8 +PINATTR PinName RGND +PINATTR SpiceOrder 14 +PIN -208 0 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 15 +PIN -96 -224 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1149-5.asy b/spice/copy/sym/PowerProducts/LTC1149-5.asy new file mode 100755 index 0000000..4385c81 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1149-5.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -224 208 224 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1149-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1149-5.sub +SYMATTR Value2 LTC1149-5 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 5V Output +PIN 208 -160 RIGHT 8 +PINATTR PinName P-Gate +PINATTR SpiceOrder 1 +PIN 96 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -208 -160 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 208 -80 RIGHT 8 +PINATTR PinName P-Drive +PINATTR SpiceOrder 4 +PIN -208 160 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -208 80 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN -208 -80 LEFT 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 10 +PIN -128 224 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 128 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 208 160 RIGHT 8 +PINATTR PinName N-Gate +PINATTR SpiceOrder 13 +PIN 0 224 BOTTOM 8 +PINATTR PinName RGND +PINATTR SpiceOrder 14 +PIN -208 0 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 15 +PIN -96 -224 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1149.asy b/spice/copy/sym/PowerProducts/LTC1149.asy new file mode 100755 index 0000000..4eeb569 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1149.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -224 208 224 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1149 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1149.sub +SYMATTR Value2 LTC1149 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Adjustable Output Voltage +PIN 208 -160 RIGHT 8 +PINATTR PinName P-Gate +PINATTR SpiceOrder 1 +PIN 96 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -208 -160 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 208 -80 RIGHT 8 +PINATTR PinName P-Drive +PINATTR SpiceOrder 4 +PIN -208 -80 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -208 80 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN -208 160 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -128 224 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 128 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 208 160 RIGHT 8 +PINATTR PinName N-Gate +PINATTR SpiceOrder 13 +PIN 0 224 BOTTOM 8 +PINATTR PinName RGND +PINATTR SpiceOrder 14 +PIN -208 0 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 15 +PIN -96 -224 TOP 8 +PINATTR PinName CAP +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1154.asy b/spice/copy/sym/PowerProducts/LTC1154.asy new file mode 100755 index 0000000..813db57 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1154.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -192 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1154 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1154.sub +SYMATTR Value2 LTC1154 +SYMATTR Description High-Side µPower MOSFET Driver +PIN -144 -144 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName STATUS +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName SD +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName G +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName DS +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Vs +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1155.asy b/spice/copy/sym/PowerProducts/LTC1155.asy new file mode 100755 index 0000000..adcc736 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1155.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC1155 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1155.sub +SYMATTR Value2 LTC1155 +SYMATTR Description Dual High-Side µPower MOSFET Driver +PIN 128 -144 RIGHT 8 +PINATTR PinName DS1 +PINATTR SpiceOrder 1 +PIN 128 48 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 2 +PIN -128 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 -48 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 4 +PIN -128 48 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 5 +PIN -128 -144 LEFT 8 +PINATTR PinName Vs +PINATTR SpiceOrder 6 +PIN 128 144 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 128 -48 RIGHT 8 +PINATTR PinName DS2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1156.asy b/spice/copy/sym/PowerProducts/LTC1156.asy new file mode 100755 index 0000000..ae01626 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1156.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC1156 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1156.sub +SYMATTR Value2 LTC1156 +SYMATTR Description Quad High-Side µPower MOSFET Driver with Internal Charge Pump (2 of 4 Channels) +PIN -128 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -48 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName Vs +PINATTR SpiceOrder 3 +PIN -128 48 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName DS2 +PINATTR SpiceOrder 13 +PIN 128 144 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 14 +PIN 128 -144 RIGHT 8 +PINATTR PinName DS1 +PINATTR SpiceOrder 15 +PIN 128 48 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1157.asy b/spice/copy/sym/PowerProducts/LTC1157.asy new file mode 100755 index 0000000..d190590 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1157.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -96 112 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LTC1157 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1157.sub +SYMATTR Value2 LTC1157 +SYMATTR Description 3.3V Dual µPower High-Side/Low-Side MOSFET Driver +PIN 112 -48 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 2 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -112 -48 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 4 +PIN -112 48 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 5 +PIN 0 -96 TOP 8 +PINATTR PinName Vs +PINATTR SpiceOrder 6 +PIN 112 48 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LTC1159-3.3.asy b/spice/copy/sym/PowerProducts/LTC1159-3.3.asy new file mode 100755 index 0000000..3b732db --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1159-3.3.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -240 208 320 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1159-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1159-3.3.sub +SYMATTR Value2 LTC1159-3.3 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 3.3V Output +PIN 208 -160 RIGHT 8 +PINATTR PinName P-Gate +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -208 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 208 -80 RIGHT 8 +PINATTR PinName P-Drive +PINATTR SpiceOrder 4 +PIN -208 240 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -208 160 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN -208 0 LEFT 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 10 +PIN -128 320 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 128 320 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 208 240 RIGHT 8 +PINATTR PinName N-Gate +PINATTR SpiceOrder 13 +PIN 208 160 RIGHT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 14 +PIN -208 80 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 15 +PIN -208 -160 LEFT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1159-5.asy b/spice/copy/sym/PowerProducts/LTC1159-5.asy new file mode 100755 index 0000000..d311726 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1159-5.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -240 208 320 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1159-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1159-5.sub +SYMATTR Value2 LTC1159-5 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 5V Output +PIN 208 -160 RIGHT 8 +PINATTR PinName P-Gate +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -208 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 208 -80 RIGHT 8 +PINATTR PinName P-Drive +PINATTR SpiceOrder 4 +PIN -208 240 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -208 160 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN -208 0 LEFT 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 10 +PIN -128 320 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 128 320 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 208 240 RIGHT 8 +PINATTR PinName N-Gate +PINATTR SpiceOrder 13 +PIN 208 160 RIGHT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 14 +PIN -208 80 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 15 +PIN -208 -160 LEFT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1159.asy b/spice/copy/sym/PowerProducts/LTC1159.asy new file mode 100755 index 0000000..1e978e1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1159.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -240 208 320 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1159 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1159.sub +SYMATTR Value2 LTC1159 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator Controller, Adjustable Output Voltage +PIN 208 -160 RIGHT 8 +PINATTR PinName P-Gate +PINATTR SpiceOrder 1 +PIN 0 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -208 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 208 -80 RIGHT 8 +PINATTR PinName P-Drive +PINATTR SpiceOrder 4 +PIN -208 160 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -208 80 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN -208 240 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -128 320 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 128 320 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 208 240 RIGHT 8 +PINATTR PinName N-Gate +PINATTR SpiceOrder 13 +PIN 208 160 RIGHT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 14 +PIN -208 0 LEFT 8 +PINATTR PinName SHDN2 +PINATTR SpiceOrder 15 +PIN -208 -160 LEFT 8 +PINATTR PinName CAP +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1163.asy b/spice/copy/sym/PowerProducts/LTC1163.asy new file mode 100755 index 0000000..fbd016d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1163.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1163 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1163.sub +SYMATTR Value2 LTC1163 +SYMATTR Description Triple 1.8V to 6V High-Side MOSFET Driver +PIN -128 -112 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName IN3 +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 112 RIGHT 8 +PINATTR PinName OUT3 +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 6 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName Vs +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1165.asy b/spice/copy/sym/PowerProducts/LTC1165.asy new file mode 100755 index 0000000..d36b303 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1165.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1165 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1165.sub +SYMATTR Value2 LTC1165 +SYMATTR Description Triple 1.8V to 6V High-Side MOSFET Driver +PIN -128 -112 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 2 +PIN -128 112 LEFT 8 +PINATTR PinName IN3 +PINATTR SpiceOrder 3 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 112 RIGHT 8 +PINATTR PinName OUT3 +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 6 +PIN 128 -112 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName Vs +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1174-3.3.asy b/spice/copy/sym/PowerProducts/LTC1174-3.3.asy new file mode 100755 index 0000000..bb811ff --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1174-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 -35 Center 2 LT +WINDOW 0 8 -128 Left 2 +WINDOW 3 -1 36 Center 2 +SYMATTR Value LTC1174-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1174.sub +SYMATTR Value2 LTC1174 top=51K bot=31.5K +SYMATTR Description High Efficiency Step-Down and Inverting DC/DC Converter, Fixed 3.3V +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 64 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1174-5.asy b/spice/copy/sym/PowerProducts/LTC1174-5.asy new file mode 100755 index 0000000..5fc288b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1174-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 -35 Center 2 LT +WINDOW 0 8 -128 Left 2 +WINDOW 3 -1 36 Center 2 +SYMATTR Value LTC1174-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1174.sub +SYMATTR Value2 LTC1174 top=93.5K bot=31.5K +SYMATTR Description High Efficiency Step-Down and Inverting DC/DC Converter, Fixed 5V +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 64 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1174.asy b/spice/copy/sym/PowerProducts/LTC1174.asy new file mode 100755 index 0000000..efe28d8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1174.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 -35 Center 2 LT +WINDOW 0 8 -128 Left 2 +WINDOW 3 -1 36 Center 2 +SYMATTR Value LTC1174 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1174.sub +SYMATTR Value2 LTC1174 top=1K bot=1T +SYMATTR Description High Efficiency Step-Down and Inverting DC/DC Converter, Adjustable Output Voltage +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 64 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1174HV-3.3.asy b/spice/copy/sym/PowerProducts/LTC1174HV-3.3.asy new file mode 100755 index 0000000..236ae65 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1174HV-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 -35 Center 2 LT +WINDOW 0 8 -128 Left 2 +WINDOW 3 -1 36 Center 2 +SYMATTR Value LTC1174HV-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1174.sub +SYMATTR Value2 LTC1174 top=51K bot=31.5K +SYMATTR Description High Efficiency Step-Down and Inverting DC/DC Converter, Fixed 3.3V +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 64 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1174HV-5.asy b/spice/copy/sym/PowerProducts/LTC1174HV-5.asy new file mode 100755 index 0000000..541613b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1174HV-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 -35 Center 2 LT +WINDOW 0 8 -128 Left 2 +WINDOW 3 -1 36 Center 2 +SYMATTR Value LTC1174HV-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1174.sub +SYMATTR Value2 LTC1174 top=93.5K bot=31.5K +SYMATTR Description High Efficiency Step-Down and Inverting DC/DC Converter, Fixed 5V +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 64 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1174HV.asy b/spice/copy/sym/PowerProducts/LTC1174HV.asy new file mode 100755 index 0000000..ed50c4c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1174HV.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 -35 Center 2 LT +WINDOW 0 8 -128 Left 2 +WINDOW 3 -1 36 Center 2 +SYMATTR Value LTC1174HV +SYMATTR Prefix X +SYMATTR SpiceModel LTC1174.sub +SYMATTR Value2 LTC1174 top=1K bot=1T +SYMATTR Description High Efficiency Step-Down and Inverting DC/DC Converter, Adjustable Output Voltage +PIN 128 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 64 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1255.asy b/spice/copy/sym/PowerProducts/LTC1255.asy new file mode 100755 index 0000000..8844842 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1255.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC1255 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1255.sub +SYMATTR Value2 LTC1255 +SYMATTR Description Dual 24V High-Side MOSFET Driver +PIN -128 -80 LEFT 8 +PINATTR PinName DS1 +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 80 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 4 +PIN 128 80 RIGHT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vs +PINATTR SpiceOrder 6 +PIN 128 0 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 128 -80 RIGHT 8 +PINATTR PinName DS2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1261.asy b/spice/copy/sym/PowerProducts/LTC1261.asy new file mode 100755 index 0000000..76978cb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1261.asy @@ -0,0 +1,58 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 320 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 96 Center 2 LT +WINDOW 0 0 0 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTC1261 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1261.sub +SYMATTR Value2 LTC1261 +SYMATTR Description Switched Capacitor Regulated Voltage Inverter +PIN -144 -96 LEFT 8 +PINATTR PinName NC +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 5 +PIN -144 224 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -144 288 LEFT 8 +PINATTR PinName R0 +PINATTR SpiceOrder 7 +PIN 144 288 RIGHT 8 +PINATTR PinName R1 +PINATTR SpiceOrder 8 +PIN 144 224 RIGHT 8 +PINATTR PinName Radj +PINATTR SpiceOrder 9 +PIN 144 160 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 11 +PIN 144 32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 12 +PIN 144 -32 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1261CS8-4.5.asy b/spice/copy/sym/PowerProducts/LTC1261CS8-4.5.asy new file mode 100755 index 0000000..db36b3e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1261CS8-4.5.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1261CS8-4.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1261CS8-4.5.sub +SYMATTR Value2 LTC1261CS8-4.5 +SYMATTR Description Switched Capacitor Regulated Voltage Inverter, Fixed 4.5V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1261CS8-4.asy b/spice/copy/sym/PowerProducts/LTC1261CS8-4.asy new file mode 100755 index 0000000..fac5617 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1261CS8-4.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1261CS8-4 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1261CS8-4.sub +SYMATTR Value2 LTC1261CS8-4 +SYMATTR Description Switched Capacitor Regulated Voltage Inverter, Fixed 4V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1261CS8.asy b/spice/copy/sym/PowerProducts/LTC1261CS8.asy new file mode 100755 index 0000000..b264f8b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1261CS8.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1261CS8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1261CS8.sub +SYMATTR Value2 LTC1261CS8 +SYMATTR Description Switched Capacitor Regulated Voltage Inverter +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1261LCS8-4.5.asy b/spice/copy/sym/PowerProducts/LTC1261LCS8-4.5.asy new file mode 100755 index 0000000..df13254 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1261LCS8-4.5.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1261LCS8-4.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1261LCS8-4.5.sub +SYMATTR Value2 LTC1261LCS8-4.5 +SYMATTR Description Switched Capacitor Regulated Voltage Inverter, Fixed 4.5V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1261LCS8-4.asy b/spice/copy/sym/PowerProducts/LTC1261LCS8-4.asy new file mode 100755 index 0000000..f84fd73 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1261LCS8-4.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1261LCS8-4 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1261LCS8-4.sub +SYMATTR Value2 LTC1261LCS8-4 +SYMATTR Description Switched Capacitor Regulated Voltage Inverter, Fixed 4V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1261LCS8.asy b/spice/copy/sym/PowerProducts/LTC1261LCS8.asy new file mode 100755 index 0000000..5d2a60a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1261LCS8.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 64 Center 2 +SYMATTR Value LTC1261LCS8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1261LCS8.sub +SYMATTR Value2 LTC1261LCS8 +SYMATTR Description Switched Capacitor Regulated Voltage Inverter +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1262.asy b/spice/copy/sym/PowerProducts/LTC1262.asy new file mode 100755 index 0000000..1612b62 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1262.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1262 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1262.sub +SYMATTR Value2 LTC1262 +SYMATTR Description 12V, 30mA Flash Memory Programming Supply +PIN -144 -96 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1263.asy b/spice/copy/sym/PowerProducts/LTC1263.asy new file mode 100755 index 0000000..60eab3b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1263.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1263 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1263.sub +SYMATTR Value2 LTC1263 +SYMATTR Description 12V, 60mA Flash Memory Programming Supply +PIN -144 -96 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1265-3.3.asy b/spice/copy/sym/PowerProducts/LTC1265-3.3.asy new file mode 100755 index 0000000..37c5ad5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1265-3.3.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 224 +TEXT 0 40 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1265-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1265-3.3.sub +SYMATTR Value2 LTC1265-3.3 +SYMATTR Description 1.2A, High Efficiency Step-Down DC/DC Controller, Fixed 3.3V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -176 -80 LEFT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 5 +PIN -176 80 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN -96 224 BOTTOM 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN 96 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1265-5.asy b/spice/copy/sym/PowerProducts/LTC1265-5.asy new file mode 100755 index 0000000..0ba53e0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1265-5.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 224 +TEXT 0 44 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1265-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1265-5.sub +SYMATTR Value2 LTC1265-5 +SYMATTR Description 1.2A, High Efficiency Step-Down DC/DC Controller, Fixed 5V Output +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -176 -80 LEFT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 5 +PIN -176 80 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN -96 224 BOTTOM 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN 96 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1265.asy b/spice/copy/sym/PowerProducts/LTC1265.asy new file mode 100755 index 0000000..97087c1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1265.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 224 +TEXT 0 38 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1265 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1265.sub +SYMATTR Value2 LTC1265 +SYMATTR Description 1.2A, High Efficiency Step-Down DC/DC Controller, Adjustable Output Voltage +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -176 -80 LEFT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 5 +PIN -176 80 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN 176 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -96 224 BOTTOM 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN 96 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1266-3.3.asy b/spice/copy/sym/PowerProducts/LTC1266-3.3.asy new file mode 100755 index 0000000..8acbe7e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1266-3.3.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -240 208 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1266-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1266-3.3.sub +SYMATTR Value2 LTC1266-3.3 +SYMATTR Description Synchronous Regulator Controller for N- or P-Channel MOSFETs, Fixed 3.3V Output +PIN 208 -80 RIGHT 8 +PINATTR PinName T-drive +PINATTR SpiceOrder 1 +PIN 96 -240 TOP 8 +PINATTR PinName PWR Vin +PINATTR SpiceOrder 2 +PIN -208 -80 LEFT 8 +PINATTR PinName PINV +PINATTR SpiceOrder 3 +PIN -208 0 LEFT 8 +PINATTR PinName BINH +PINATTR SpiceOrder 4 +PIN -96 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -128 240 BOTTOM 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -208 160 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN -208 80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 11 +PIN 0 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 12 +PIN -208 -160 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 13 +PIN 208 -160 RIGHT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 14 +PIN 128 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 15 +PIN 208 160 RIGHT 8 +PINATTR PinName B-drive +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1266-5.asy b/spice/copy/sym/PowerProducts/LTC1266-5.asy new file mode 100755 index 0000000..bfc9eb2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1266-5.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -240 208 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1266-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1266-5.sub +SYMATTR Value2 LTC1266-5 +SYMATTR Description Synchronous Regulator Controller for N- or P-Channel MOSFETs, Fixed 5V Output +PIN 208 -80 RIGHT 8 +PINATTR PinName T-drive +PINATTR SpiceOrder 1 +PIN 96 -240 TOP 8 +PINATTR PinName PWR Vin +PINATTR SpiceOrder 2 +PIN -208 -80 LEFT 8 +PINATTR PinName PINV +PINATTR SpiceOrder 3 +PIN -208 0 LEFT 8 +PINATTR PinName BINH +PINATTR SpiceOrder 4 +PIN -96 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -128 240 BOTTOM 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -208 160 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN -208 80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 11 +PIN 0 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 12 +PIN -208 -160 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 13 +PIN 208 -160 RIGHT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 14 +PIN 128 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 15 +PIN 208 160 RIGHT 8 +PINATTR PinName B-drive +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1266.asy b/spice/copy/sym/PowerProducts/LTC1266.asy new file mode 100755 index 0000000..403f47c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1266.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -240 208 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1266 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1266.sub +SYMATTR Value2 LTC1266 +SYMATTR Description Synchronous Regulator Controller for N- or P-Channel MOSFETs, Adjustable Output Voltage +PIN 208 -80 RIGHT 8 +PINATTR PinName T-drive +PINATTR SpiceOrder 1 +PIN 96 -240 TOP 8 +PINATTR PinName PWR Vin +PINATTR SpiceOrder 2 +PIN -208 -80 LEFT 8 +PINATTR PinName PINV +PINATTR SpiceOrder 3 +PIN -208 0 LEFT 8 +PINATTR PinName BINH +PINATTR SpiceOrder 4 +PIN -96 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -208 240 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 6 +PIN -208 160 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 8 +PIN 208 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 9 +PIN 208 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -208 80 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 11 +PIN -96 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 12 +PIN -208 -160 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 13 +PIN 208 -160 RIGHT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 14 +PIN 96 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 15 +PIN 208 160 RIGHT 8 +PINATTR PinName B-drive +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1267-ADJ.asy b/spice/copy/sym/PowerProducts/LTC1267-ADJ.asy new file mode 100755 index 0000000..52d462b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1267-ADJ.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -320 400 400 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -224 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1267-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel LTC1267-ADJ.sub +SYMATTR Value2 LTC1267-ADJ +SYMATTR Description Dual High Efficiency Synchronous Step-Down Switching Regulator Controller, Adjustable Output Voltages +PIN 0 -320 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -400 -240 LEFT 8 +PINATTR PinName CAP1 +PINATTR SpiceOrder 3 +PIN -400 -160 LEFT 8 +PINATTR PinName P-gate1 +PINATTR SpiceOrder 4 +PIN -400 -80 LEFT 8 +PINATTR PinName P-drive1 +PINATTR SpiceOrder 5 +PIN -400 240 LEFT 8 +PINATTR PinName N-gate1 +PINATTR SpiceOrder 6 +PIN -336 400 BOTTOM 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -320 -320 TOP 8 +PINATTR PinName Vcc1 +PINATTR SpiceOrder 8 +PIN -256 400 BOTTOM 8 +PINATTR PinName Ct1 +PINATTR SpiceOrder 9 +PIN -400 320 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 10 +PIN -128 400 BOTTOM 8 +PINATTR PinName SGND1 +PINATTR SpiceOrder 11 +PIN -400 160 LEFT 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 12 +PIN -400 80 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 13 +PIN -400 0 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 14 +PIN 400 320 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 15 +PIN 256 400 BOTTOM 8 +PINATTR PinName Ct2 +PINATTR SpiceOrder 16 +PIN 400 80 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 17 +PIN 400 0 RIGHT 8 +PINATTR PinName Sense+2 +PINATTR SpiceOrder 18 +PIN 336 400 BOTTOM 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 19 +PIN 128 400 BOTTOM 8 +PINATTR PinName SGND2 +PINATTR SpiceOrder 20 +PIN 320 -320 TOP 8 +PINATTR PinName Vcc2 +PINATTR SpiceOrder 21 +PIN 0 400 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 22 +PIN 400 240 RIGHT 8 +PINATTR PinName N-gate2 +PINATTR SpiceOrder 23 +PIN 400 -80 RIGHT 8 +PINATTR PinName P-drive2 +PINATTR SpiceOrder 24 +PIN 400 -160 RIGHT 8 +PINATTR PinName P-gate2 +PINATTR SpiceOrder 25 +PIN 400 -240 RIGHT 8 +PINATTR PinName CAP2 +PINATTR SpiceOrder 26 +PIN -160 -320 TOP 8 +PINATTR PinName MSHDN +PINATTR SpiceOrder 27 +PIN 160 -320 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1267-ADJ5.asy b/spice/copy/sym/PowerProducts/LTC1267-ADJ5.asy new file mode 100755 index 0000000..362fce2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1267-ADJ5.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -320 400 400 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -224 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1267-ADJ5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1267-ADJ5.sub +SYMATTR Value2 LTC1267-ADJ5 +SYMATTR Description Dual High Efficiency Synchronous Step-Down Switching Regulator Controller, One Adjustable Output Voltage and One Fixed 5V Output +PIN 0 -320 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -400 -240 LEFT 8 +PINATTR PinName CAP1 +PINATTR SpiceOrder 3 +PIN -400 -160 LEFT 8 +PINATTR PinName P-gate1 +PINATTR SpiceOrder 4 +PIN -400 -80 LEFT 8 +PINATTR PinName P-drive1 +PINATTR SpiceOrder 5 +PIN -400 240 LEFT 8 +PINATTR PinName N-gate1 +PINATTR SpiceOrder 6 +PIN -336 400 BOTTOM 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -320 -320 TOP 8 +PINATTR PinName Vcc1 +PINATTR SpiceOrder 8 +PIN -256 400 BOTTOM 8 +PINATTR PinName Ct1 +PINATTR SpiceOrder 9 +PIN -400 320 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 10 +PIN -128 400 BOTTOM 8 +PINATTR PinName SGND1 +PINATTR SpiceOrder 11 +PIN -400 160 LEFT 8 +PINATTR PinName SHDN1 +PINATTR SpiceOrder 12 +PIN -400 80 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 13 +PIN -400 0 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 14 +PIN 400 320 RIGHT 8 +PINATTR PinName Ith5 +PINATTR SpiceOrder 15 +PIN 256 400 BOTTOM 8 +PINATTR PinName Ct5 +PINATTR SpiceOrder 16 +PIN 400 80 RIGHT 8 +PINATTR PinName Sense-5 +PINATTR SpiceOrder 17 +PIN 400 0 RIGHT 8 +PINATTR PinName Sense+5 +PINATTR SpiceOrder 18 +PIN 400 160 RIGHT 8 +PINATTR PinName SHDN5 +PINATTR SpiceOrder 19 +PIN 128 400 BOTTOM 8 +PINATTR PinName SGND5 +PINATTR SpiceOrder 20 +PIN 320 -320 TOP 8 +PINATTR PinName Vcc5 +PINATTR SpiceOrder 21 +PIN 0 400 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 22 +PIN 400 240 RIGHT 8 +PINATTR PinName N-gate5 +PINATTR SpiceOrder 23 +PIN 400 -80 RIGHT 8 +PINATTR PinName P-drive5 +PINATTR SpiceOrder 24 +PIN 400 -160 RIGHT 8 +PINATTR PinName P-gate5 +PINATTR SpiceOrder 25 +PIN 400 -240 RIGHT 8 +PINATTR PinName CAP5 +PINATTR SpiceOrder 26 +PIN -160 -320 TOP 8 +PINATTR PinName MSHDN +PINATTR SpiceOrder 27 +PIN 160 -320 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1267.asy b/spice/copy/sym/PowerProducts/LTC1267.asy new file mode 100755 index 0000000..adb4263 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1267.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -320 400 400 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1267 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1267.sub +SYMATTR Value2 LTC1267 +SYMATTR Description Dual High Efficiency Synchronous Step-Down Switching Regulator Controller, Fixed 3.3V and 5V Outputs +PIN 0 -320 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -400 -240 LEFT 8 +PINATTR PinName CAP3 +PINATTR SpiceOrder 3 +PIN -400 -160 LEFT 8 +PINATTR PinName P-gate3 +PINATTR SpiceOrder 4 +PIN -400 -80 LEFT 8 +PINATTR PinName P-drive3 +PINATTR SpiceOrder 5 +PIN -400 240 LEFT 8 +PINATTR PinName N-gate3 +PINATTR SpiceOrder 6 +PIN -320 400 BOTTOM 8 +PINATTR PinName PGND3 +PINATTR SpiceOrder 7 +PIN -320 -320 TOP 8 +PINATTR PinName Vcc3 +PINATTR SpiceOrder 8 +PIN -48 400 BOTTOM 8 +PINATTR PinName Ct3 +PINATTR SpiceOrder 9 +PIN -400 320 LEFT 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 10 +PIN -176 400 BOTTOM 8 +PINATTR PinName SGND3 +PINATTR SpiceOrder 11 +PIN -400 160 LEFT 8 +PINATTR PinName SHDN3 +PINATTR SpiceOrder 12 +PIN -400 80 LEFT 8 +PINATTR PinName Sense-3 +PINATTR SpiceOrder 13 +PIN -400 0 LEFT 8 +PINATTR PinName Sense+3 +PINATTR SpiceOrder 14 +PIN 400 320 RIGHT 8 +PINATTR PinName Ith5 +PINATTR SpiceOrder 15 +PIN 48 400 BOTTOM 8 +PINATTR PinName Ct5 +PINATTR SpiceOrder 16 +PIN 400 80 RIGHT 8 +PINATTR PinName Sense-5 +PINATTR SpiceOrder 17 +PIN 400 0 RIGHT 8 +PINATTR PinName Sense+5 +PINATTR SpiceOrder 18 +PIN 400 160 RIGHT 8 +PINATTR PinName SHDN5 +PINATTR SpiceOrder 19 +PIN 176 400 BOTTOM 8 +PINATTR PinName SGND5 +PINATTR SpiceOrder 20 +PIN 320 -320 TOP 8 +PINATTR PinName Vcc5 +PINATTR SpiceOrder 21 +PIN 320 400 BOTTOM 8 +PINATTR PinName PGND5 +PINATTR SpiceOrder 22 +PIN 400 240 RIGHT 8 +PINATTR PinName N-gate5 +PINATTR SpiceOrder 23 +PIN 400 -80 RIGHT 8 +PINATTR PinName P-drive5 +PINATTR SpiceOrder 24 +PIN 400 -160 RIGHT 8 +PINATTR PinName P-gate5 +PINATTR SpiceOrder 25 +PIN 400 -240 RIGHT 8 +PINATTR PinName CAP5 +PINATTR SpiceOrder 26 +PIN -160 -320 TOP 8 +PINATTR PinName MSHDN +PINATTR SpiceOrder 27 +PIN 160 -320 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1429.asy b/spice/copy/sym/PowerProducts/LTC1429.asy new file mode 100755 index 0000000..0817cdc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1429.asy @@ -0,0 +1,58 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 320 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 96 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 256 Center 2 +SYMATTR Value LTC1429 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1429.sub +SYMATTR Value2 LTC1429 +SYMATTR Description Clock-Synchronized Switched Capacitor Regulated Voltage Inverter +PIN -144 -96 LEFT 8 +PINATTR PinName NC +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 5 +PIN -144 224 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -144 288 LEFT 8 +PINATTR PinName R0 +PINATTR SpiceOrder 7 +PIN 144 288 RIGHT 8 +PINATTR PinName R1 +PINATTR SpiceOrder 8 +PIN 144 224 RIGHT 8 +PINATTR PinName Radj +PINATTR SpiceOrder 9 +PIN 144 160 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 11 +PIN 144 32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 12 +PIN 144 -32 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1429CS8-4.asy b/spice/copy/sym/PowerProducts/LTC1429CS8-4.asy new file mode 100755 index 0000000..e04b668 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1429CS8-4.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1429CS8-4 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1429CS8-4.sub +SYMATTR Value2 LTC1429CS8-4 +SYMATTR Description Clock-Synchronized Switched Capacitor Regulated Voltage Inverter, Fixed 4V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1430.asy b/spice/copy/sym/PowerProducts/LTC1430.asy new file mode 100755 index 0000000..e4b01dc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1430.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -224 192 224 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1430 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1430.sub +SYMATTR Value2 LTC1430 +SYMATTR Description High Power Step-Down Synchronous Switching Regulator Controller +PIN 192 -160 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 1 +PIN 64 -224 TOP 8 +PINATTR PinName PVcc1 +PINATTR SpiceOrder 2 +PIN 64 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 3 +PIN -64 224 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 192 160 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 5 +PIN 192 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 192 32 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 7 +PIN -192 96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 +PIN -192 -32 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN -192 160 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN -192 32 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -192 -160 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 12 +PIN 192 -96 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 13 +PIN -192 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 14 +PIN -64 -224 TOP 8 +PINATTR PinName PVcc2 +PINATTR SpiceOrder 15 +PIN 192 -32 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1430A.asy b/spice/copy/sym/PowerProducts/LTC1430A.asy new file mode 100755 index 0000000..bd273b8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1430A.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -224 192 224 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1430A +SYMATTR Prefix X +SYMATTR SpiceModel LTC1430A.sub +SYMATTR Value2 LTC1430A +SYMATTR Description High Power Step-Down Synchronous Switching Regulator Controller +PIN 192 -160 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 1 +PIN 64 -224 TOP 8 +PINATTR PinName PVcc1 +PINATTR SpiceOrder 2 +PIN 64 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 3 +PIN -64 224 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 192 160 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 5 +PIN 192 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 192 32 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 7 +PIN -192 96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 +PIN -192 -32 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN -192 160 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN -192 32 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -192 -160 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 12 +PIN 192 -96 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 13 +PIN -192 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 14 +PIN -64 -224 TOP 8 +PINATTR PinName PVcc2 +PINATTR SpiceOrder 15 +PIN 192 -32 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1433.asy b/spice/copy/sym/PowerProducts/LTC1433.asy new file mode 100755 index 0000000..eba7dbe --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1433.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -176 176 176 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1433 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1433.sub +SYMATTR Value2 LTC1433 +SYMATTR Description 450mA, Low Noise Current Mode Step-Down DC/DC Converter +PIN 176 -32 RIGHT 8 +PINATTR PinName SSW +PINATTR SpiceOrder 1 +PIN 176 -96 RIGHT 8 +PINATTR PinName BSW +PINATTR SpiceOrder 3 +PIN 80 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -176 96 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 6 +PIN -176 -96 LEFT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 7 +PIN -176 -32 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 8 +PIN 176 96 RIGHT 8 +PINATTR PinName Vprog +PINATTR SpiceOrder 9 +PIN 176 32 RIGHT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 10 +PIN -176 32 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 11 +PIN -80 176 BOTTOM 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 13 +PIN -80 -176 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 14 +PIN 80 -176 TOP 8 +PINATTR PinName PWRVin +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1434.asy b/spice/copy/sym/PowerProducts/LTC1434.asy new file mode 100755 index 0000000..6d1defd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1434.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -192 192 192 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -136 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LTC1434 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1434.sub +SYMATTR Value2 LTC1434 +SYMATTR Description 450mA, Low Noise Current Mode Step-Down DC/DC Converter +PIN 192 -64 RIGHT 8 +PINATTR PinName SSW +PINATTR SpiceOrder 2 +PIN 192 -128 RIGHT 8 +PINATTR PinName BSW +PINATTR SpiceOrder 4 +PIN 80 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -192 128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 7 +PIN 192 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 9 +PIN -192 -128 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 10 +PIN 192 128 RIGHT 8 +PINATTR PinName Vprog +PINATTR SpiceOrder 11 +PIN 192 64 RIGHT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 12 +PIN -192 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 13 +PIN -80 192 BOTTOM 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 15 +PIN -192 0 LEFT 8 +PINATTR PinName PLL LPF +PINATTR SpiceOrder 16 +PIN -192 -64 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 17 +PIN -80 -192 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 18 +PIN 80 -192 TOP 8 +PINATTR PinName PWRVin +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC1435A.asy b/spice/copy/sym/PowerProducts/LTC1435A.asy new file mode 100755 index 0000000..b20fd3d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1435A.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 240 +TEXT 0 -32 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1435A +SYMATTR Value2 LTC1435A +SYMATTR Prefix X +SYMATTR SpiceModel LTC1435A.sub +SYMATTR Description High Efficiency Low Noise Synchronous Step-Down Switching Regulator +PIN -176 -160 LEFT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 1 +PIN -176 -96 LEFT 8 +PINATTR PinName SOFT +PINATTR SpiceOrder 2 +PIN -176 -32 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN -176 -224 LEFT 8 +PINATTR PinName SFB +PINATTR SpiceOrder 4 +PIN -176 96 LEFT 8 +PINATTR PinName SGND +PINATTR SpiceOrder 5 +PIN -176 160 LEFT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 6 +PIN -96 240 BOTTOM 8 +PINATTR PinName SEN- +PINATTR SpiceOrder 7 +PIN 96 240 BOTTOM 8 +PINATTR PinName SEN+ +PINATTR SpiceOrder 8 +PIN 176 -224 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 9 +PIN 176 160 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 176 96 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 11 +PIN 176 32 RIGHT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 12 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 176 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 176 -32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 15 +PIN 176 -160 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1436A-PLL.asy b/spice/copy/sym/PowerProducts/LTC1436A-PLL.asy new file mode 100755 index 0000000..a57c6b5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1436A-PLL.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -384 208 384 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -200 Center 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LTC1436A-PLL +SYMATTR Value2 LTC1436A-PLL +SYMATTR Prefix X +SYMATTR SpiceModel LTC1436A-PLL.sub +SYMATTR Description High Efficiency Low Noise Synchronous Step-Down Switching Regulator +PIN -208 80 LEFT 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 1 +PIN 208 320 RIGHT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN -208 0 LEFT 8 +PINATTR PinName PLL LPF +PINATTR SpiceOrder 3 +PIN -208 -80 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 4 +PIN -208 -240 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 5 +PIN -208 -320 LEFT 8 +PINATTR PinName SFB +PINATTR SpiceOrder 6 +PIN -80 384 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 7 +PIN -208 -160 LEFT 8 +PINATTR PinName Vprog +PINATTR SpiceOrder 8 +PIN 208 240 RIGHT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 9 +PIN 208 160 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 10 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 11 +PIN -208 320 LEFT 8 +PINATTR PinName AUXON +PINATTR SpiceOrder 12 +PIN -208 240 LEFT 8 +PINATTR PinName AUXFB +PINATTR SpiceOrder 13 +PIN -208 160 LEFT 8 +PINATTR PinName AUXDR +PINATTR SpiceOrder 14 +PIN 0 -384 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 15 +PIN 80 384 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 +PIN 208 0 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 17 +PIN 128 -384 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 18 +PIN -128 -384 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 19 +PIN 208 -240 RIGHT 8 +PINATTR PinName TGS +PINATTR SpiceOrder 20 +PIN 208 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 21 +PIN 208 -160 RIGHT 8 +PINATTR PinName TGL +PINATTR SpiceOrder 22 +PIN 208 -320 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 23 diff --git a/spice/copy/sym/PowerProducts/LTC1436A.asy b/spice/copy/sym/PowerProducts/LTC1436A.asy new file mode 100755 index 0000000..0e76807 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1436A.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -384 208 384 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -200 Center 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LTC1436A +SYMATTR Value2 LTC1436A +SYMATTR Prefix X +SYMATTR SpiceModel LTC1436A.sub +SYMATTR Description High Efficiency Low Noise Synchronous Step-Down Switching Regulator +PIN -208 80 LEFT 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 1 +PIN 208 320 RIGHT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN -208 0 LEFT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 3 +PIN -208 -80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 4 +PIN -208 -240 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 5 +PIN -208 -320 LEFT 8 +PINATTR PinName SFB +PINATTR SpiceOrder 6 +PIN -80 384 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 7 +PIN -208 -160 LEFT 8 +PINATTR PinName Vprog +PINATTR SpiceOrder 8 +PIN 208 240 RIGHT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 9 +PIN 208 160 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 10 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 11 +PIN -208 320 LEFT 8 +PINATTR PinName AUXON +PINATTR SpiceOrder 12 +PIN -208 240 LEFT 8 +PINATTR PinName AUXFB +PINATTR SpiceOrder 13 +PIN -208 160 LEFT 8 +PINATTR PinName AUXDR +PINATTR SpiceOrder 14 +PIN 0 -384 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 15 +PIN 80 384 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 +PIN 208 0 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 17 +PIN 128 -384 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 18 +PIN -128 -384 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 19 +PIN 208 -240 RIGHT 8 +PINATTR PinName TGS +PINATTR SpiceOrder 20 +PIN 208 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 21 +PIN 208 -160 RIGHT 8 +PINATTR PinName TGL +PINATTR SpiceOrder 22 +PIN 208 -320 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 23 diff --git a/spice/copy/sym/PowerProducts/LTC1437A.asy b/spice/copy/sym/PowerProducts/LTC1437A.asy new file mode 100755 index 0000000..0fcee91 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1437A.asy @@ -0,0 +1,89 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -464 256 384 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -200 Center 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LTC1437A +SYMATTR Value2 LTC1437A +SYMATTR Prefix X +SYMATTR SpiceModel LTC1437A.sub +SYMATTR Description High Efficiency Low Noise Synchronous Step-Down Switching Regulator +PIN -256 -400 LEFT 8 +PINATTR PinName PLL LPF +PINATTR SpiceOrder 1 +PIN -256 80 LEFT 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 2 +PIN 256 320 RIGHT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 3 +PIN -256 0 LEFT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 4 +PIN -256 -80 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 5 +PIN -256 -240 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN -256 -320 LEFT 8 +PINATTR PinName SFB +PINATTR SpiceOrder 7 +PIN -112 384 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -256 -160 LEFT 8 +PINATTR PinName Vprog +PINATTR SpiceOrder 9 +PIN 256 240 RIGHT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 10 +PIN 256 160 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 12 +PIN 256 80 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 13 +PIN -256 320 LEFT 8 +PINATTR PinName AUXON +PINATTR SpiceOrder 14 +PIN -256 240 LEFT 8 +PINATTR PinName AUXFB +PINATTR SpiceOrder 15 +PIN -256 160 LEFT 8 +PINATTR PinName AUXDR +PINATTR SpiceOrder 16 +PIN -64 -464 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 17 +PIN 112 384 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 18 +PIN 256 0 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 19 +PIN 64 -464 TOP 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 20 +PIN 192 -464 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 21 +PIN -192 -464 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 22 +PIN 256 -240 RIGHT 8 +PINATTR PinName TGS +PINATTR SpiceOrder 23 +PIN 256 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 24 +PIN 256 -160 RIGHT 8 +PINATTR PinName TGL +PINATTR SpiceOrder 25 +PIN 256 -320 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 26 +PIN 256 -400 RIGHT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1438-ADJ.asy b/spice/copy/sym/PowerProducts/LTC1438-ADJ.asy new file mode 100755 index 0000000..814d37b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1438-ADJ.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -416 -400 416 480 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LTC1438-ADJ +SYMATTR Prefix X +SYMATTR SpiceModel LTC1438-ADJ.sub +SYMATTR Value2 LTC1438-ADJ +SYMATTR Description Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulator +PIN -320 480 BOTTOM 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 1 +PIN -416 80 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 2 +PIN -416 160 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 3 +PIN -416 240 LEFT 8 +PINATTR PinName Vsense1 +PINATTR SpiceOrder 4 +PIN -416 400 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 5 +PIN -160 480 BOTTOM 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 7 +PIN 0 480 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -416 320 LEFT 8 +PINATTR PinName SFB1 +PINATTR SpiceOrder 11 +PIN 416 400 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 12 +PIN 416 320 RIGHT 8 +PINATTR PinName Vosense2 +PINATTR SpiceOrder 14 +PIN 416 240 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 15 +PIN 416 160 RIGHT 8 +PINATTR PinName Sense+2 +PINATTR SpiceOrder 16 +PIN 320 480 BOTTOM 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 17 +PIN 416 -320 RIGHT 8 +PINATTR PinName AUXDR +PINATTR SpiceOrder 18 +PIN 416 -240 RIGHT 8 +PINATTR PinName AUXFB +PINATTR SpiceOrder 19 +PIN -416 -320 LEFT 8 +PINATTR PinName AUXON +PINATTR SpiceOrder 20 +PIN 416 -160 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 21 +PIN 416 -80 RIGHT 8 +PINATTR PinName TGL2 +PINATTR SpiceOrder 22 +PIN 416 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 23 +PIN 240 -400 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 25 +PIN 416 80 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 26 +PIN 160 480 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 27 +PIN 0 -400 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 28 +PIN -416 0 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 29 +PIN -240 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 30 +PIN -416 -80 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 32 +PIN -416 -160 LEFT 8 +PINATTR PinName TGL1 +PINATTR SpiceOrder 33 +PIN -416 -240 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 34 diff --git a/spice/copy/sym/PowerProducts/LTC1438.asy b/spice/copy/sym/PowerProducts/LTC1438.asy new file mode 100755 index 0000000..c2f4399 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1438.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -416 -400 416 480 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LTC1438 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1438.sub +SYMATTR Value2 LTC1438 +SYMATTR Description Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulator +PIN -320 480 BOTTOM 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 1 +PIN -416 80 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 2 +PIN -416 160 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 3 +PIN -416 320 LEFT 8 +PINATTR PinName Vprog1 +PINATTR SpiceOrder 4 +PIN -416 400 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 5 +PIN -160 480 BOTTOM 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 7 +PIN 0 480 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -416 240 LEFT 8 +PINATTR PinName SFB1 +PINATTR SpiceOrder 11 +PIN 416 400 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 12 +PIN 416 320 RIGHT 8 +PINATTR PinName Vosense2 +PINATTR SpiceOrder 14 +PIN 416 240 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 15 +PIN 416 160 RIGHT 8 +PINATTR PinName Sense+2 +PINATTR SpiceOrder 16 +PIN 320 480 BOTTOM 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 17 +PIN 416 -320 RIGHT 8 +PINATTR PinName AUXDR +PINATTR SpiceOrder 18 +PIN 416 -240 RIGHT 8 +PINATTR PinName AUXFB +PINATTR SpiceOrder 19 +PIN -416 -320 LEFT 8 +PINATTR PinName AUXON +PINATTR SpiceOrder 20 +PIN 416 -160 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 21 +PIN 416 -80 RIGHT 8 +PINATTR PinName TGL2 +PINATTR SpiceOrder 22 +PIN 416 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 23 +PIN 240 -400 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 25 +PIN 416 80 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 26 +PIN 160 480 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 27 +PIN 0 -400 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 28 +PIN -416 0 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 29 +PIN -240 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 30 +PIN -416 -80 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 32 +PIN -416 -160 LEFT 8 +PINATTR PinName TGL1 +PINATTR SpiceOrder 33 +PIN -416 -240 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 34 diff --git a/spice/copy/sym/PowerProducts/LTC1439.asy b/spice/copy/sym/PowerProducts/LTC1439.asy new file mode 100755 index 0000000..dba51be --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1439.asy @@ -0,0 +1,116 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -416 -560 416 560 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LTC1439 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1439.sub +SYMATTR Value2 LTC1439 +SYMATTR Description Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulator +PIN -320 560 BOTTOM 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 1 +PIN -416 160 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 2 +PIN -416 240 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 3 +PIN -416 400 LEFT 8 +PINATTR PinName Vprog1 +PINATTR SpiceOrder 4 +PIN -416 480 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 5 +PIN -160 560 BOTTOM 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 7 +PIN 0 560 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -416 -320 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 9 +PIN 416 -320 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 10 +PIN -416 320 LEFT 8 +PINATTR PinName SFB1 +PINATTR SpiceOrder 11 +PIN 416 480 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 12 +PIN 416 400 RIGHT 8 +PINATTR PinName Vprog2 +PINATTR SpiceOrder 13 +PIN 416 320 RIGHT 8 +PINATTR PinName Vosense2 +PINATTR SpiceOrder 14 +PIN 416 240 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 15 +PIN 416 160 RIGHT 8 +PINATTR PinName Sense+2 +PINATTR SpiceOrder 16 +PIN 320 560 BOTTOM 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 17 +PIN 416 -480 RIGHT 8 +PINATTR PinName AUXDR +PINATTR SpiceOrder 18 +PIN 416 -400 RIGHT 8 +PINATTR PinName AUXFB +PINATTR SpiceOrder 19 +PIN 336 -560 TOP 8 +PINATTR PinName AUXON +PINATTR SpiceOrder 20 +PIN 416 -240 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 21 +PIN 416 -80 RIGHT 8 +PINATTR PinName TGL2 +PINATTR SpiceOrder 22 +PIN 416 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 23 +PIN 416 -160 RIGHT 8 +PINATTR PinName TGS2 +PINATTR SpiceOrder 24 +PIN 112 -560 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 25 +PIN 416 80 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 26 +PIN 160 560 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 27 +PIN -112 -560 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 28 +PIN -416 80 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 29 +PIN -336 -560 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 30 +PIN -416 -160 LEFT 8 +PINATTR PinName TGS1 +PINATTR SpiceOrder 31 +PIN -416 0 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 32 +PIN -416 -80 LEFT 8 +PINATTR PinName TGL1 +PINATTR SpiceOrder 33 +PIN -416 -240 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 34 +PIN -416 -480 LEFT 8 +PINATTR PinName PLL IN +PINATTR SpiceOrder 35 +PIN -416 -400 LEFT 8 +PINATTR PinName PLL LPF +PINATTR SpiceOrder 36 diff --git a/spice/copy/sym/PowerProducts/LTC1473L.asy b/spice/copy/sym/PowerProducts/LTC1473L.asy new file mode 100755 index 0000000..14892b1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1473L.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -368 160 368 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTC1473L +SYMATTR Prefix X +SYMATTR SpiceModel LTC1473L.sub +SYMATTR Value2 LTC1473L +SYMATTR Description Dual Low Voltage PowerPath Switch Driver +PIN -160 -336 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN -160 -240 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 2 +PIN -160 -144 LEFT 8 +PINATTR PinName _DIODE +PINATTR SpiceOrder 3 +PIN -160 -48 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 4 +PIN -160 48 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN -160 144 LEFT 8 +PINATTR PinName VGG +PINATTR SpiceOrder 6 +PIN -160 240 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN -160 336 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 336 RIGHT 8 +PINATTR PinName GB2 +PINATTR SpiceOrder 9 +PIN 160 240 RIGHT 8 +PINATTR PinName SAB2 +PINATTR SpiceOrder 10 +PIN 160 144 RIGHT 8 +PINATTR PinName GA2 +PINATTR SpiceOrder 11 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 12 +PIN 160 -48 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 13 +PIN 160 -144 RIGHT 8 +PINATTR PinName GB1 +PINATTR SpiceOrder 14 +PIN 160 -240 RIGHT 8 +PINATTR PinName SAB1 +PINATTR SpiceOrder 15 +PIN 160 -336 RIGHT 8 +PINATTR PinName GA1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1474-3.3.asy b/spice/copy/sym/PowerProducts/LTC1474-3.3.asy new file mode 100755 index 0000000..3d373fc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1474-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1474-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1474.sub +SYMATTR Value2 LTC1474 top=1.68Meg bot=1Meg +SYMATTR Description Low Quiescent Current, High Efficiency Step-Down Converter, 3.3V Output +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1474-5.asy b/spice/copy/sym/PowerProducts/LTC1474-5.asy new file mode 100755 index 0000000..a8fbfee --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1474-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1474-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1474.sub +SYMATTR Value2 LTC1474 top=3.05Meg bot=1Meg +SYMATTR Description Low Quiescent Current, High Efficiency Step-Down Converter, 5V Output +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1474.asy b/spice/copy/sym/PowerProducts/LTC1474.asy new file mode 100755 index 0000000..bd6ae45 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1474.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1474 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1474.sub +SYMATTR Value2 LTC1474 top=10 bot=1T +SYMATTR Description Low Quiescent Current, High Efficiency Step-Down Converter, Adjustable Output Voltage +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1475-3.3.asy b/spice/copy/sym/PowerProducts/LTC1475-3.3.asy new file mode 100755 index 0000000..a535594 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1475-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1475-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1475.sub +SYMATTR Value2 LTC1475 top=1.68Meg bot=1Meg +SYMATTR Description Low Quiescent Current, High Efficiency Step-Down Converter, 3.3V Output +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName _OFF +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName _ON +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1475-5.asy b/spice/copy/sym/PowerProducts/LTC1475-5.asy new file mode 100755 index 0000000..4104354 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1475-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1475-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1475.sub +SYMATTR Value2 LTC1475 top=3.05Meg bot=1Meg +SYMATTR Description Low Quiescent Current, High Efficiency Step-Down Converter, 5V Output +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName _OFF +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName _ON +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1475.asy b/spice/copy/sym/PowerProducts/LTC1475.asy new file mode 100755 index 0000000..4838dee --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1475.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1475 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1475.sub +SYMATTR Value2 LTC1475 top=10 bot=1T +SYMATTR Description Low Quiescent Current, High Efficiency Step-Down Converter, Adjustable Output Voltage +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName _OFF +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName _ON +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1502-3.3.asy b/spice/copy/sym/PowerProducts/LTC1502-3.3.asy new file mode 100755 index 0000000..69cb0a5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1502-3.3.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1502-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1502-3.3.sub +SYMATTR Value2 LTC1502-3.3 +SYMATTR Description Single Cell to 3.3V Regulated Charge Pump DC/DC Converter +PIN -144 -96 LEFT 8 +PINATTR PinName C2 +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName C3- +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName C3+ +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1503-1.8.asy b/spice/copy/sym/PowerProducts/LTC1503-1.8.asy new file mode 100755 index 0000000..aea4aab --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1503-1.8.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 65 Center 2 +SYMATTR Value LTC1503-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1503-1.8.sub +SYMATTR Value2 LTC1503-1.8 +SYMATTR Description High Efficiency Inductorless Step-Down DC/DC Converter, Fixed 1.8V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1503-2.asy b/spice/copy/sym/PowerProducts/LTC1503-2.asy new file mode 100755 index 0000000..e681360 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1503-2.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1503-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1503-2.sub +SYMATTR Value2 LTC1503-2 +SYMATTR Description High Efficiency Inductorless Step-Down DC/DC Converter, Fixed 2V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1504-3.3.asy b/spice/copy/sym/PowerProducts/LTC1504-3.3.asy new file mode 100755 index 0000000..5f9ac25 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1504-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC1504-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1504.sub +SYMATTR Value2 LTC1504 top=20.4K bot=12.6K +SYMATTR Description 500mA Low Voltage Step-Down Synchronous Regulator, Fixed 3.3V Output +PIN 96 -144 TOP 8 +PINATTR PinName Imax +PINATTR SpiceOrder 1 +PIN -96 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 112 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHND +PINATTR SpiceOrder 6 +PIN -112 144 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1504.asy b/spice/copy/sym/PowerProducts/LTC1504.asy new file mode 100755 index 0000000..6e86f8c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1504.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 89 Center 2 +SYMATTR Value LTC1504 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1504.sub +SYMATTR Value2 LTC1504 top=10 bot=1T +SYMATTR Description 500mA Low Voltage Step-Down Synchronous Regulator, Adjustable Output Voltage +PIN 96 -144 TOP 8 +PINATTR PinName Imax +PINATTR SpiceOrder 1 +PIN -96 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 112 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHND +PINATTR SpiceOrder 6 +PIN -112 144 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1504A-3.3.asy b/spice/copy/sym/PowerProducts/LTC1504A-3.3.asy new file mode 100755 index 0000000..7acb6ed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1504A-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 86 Center 2 +SYMATTR Value LTC1504-3.3A +SYMATTR Prefix X +SYMATTR SpiceModel LTC1504A.sub +SYMATTR Value2 LTC1504A top=20.4K bot=12.6K +SYMATTR Description 500mA Low Voltage Step-Down Synchronous Regulator, Fixed 3.3V Output +PIN 96 -144 TOP 8 +PINATTR PinName Imax +PINATTR SpiceOrder 1 +PIN -96 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 112 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHND +PINATTR SpiceOrder 6 +PIN -112 144 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1504A.asy b/spice/copy/sym/PowerProducts/LTC1504A.asy new file mode 100755 index 0000000..1eff31d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1504A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC1504A +SYMATTR Prefix X +SYMATTR SpiceModel LTC1504A.sub +SYMATTR Value2 LTC1504A top=10 bot=1T +SYMATTR Description 500mA Low Voltage Step-Down Synchronous Regulator, Adjustable Output Voltage +PIN 96 -144 TOP 8 +PINATTR PinName Imax +PINATTR SpiceOrder 1 +PIN -96 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 112 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHND +PINATTR SpiceOrder 6 +PIN -112 144 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1514-3.3.asy b/spice/copy/sym/PowerProducts/LTC1514-3.3.asy new file mode 100755 index 0000000..15fc2da --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1514-3.3.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1514-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1514-3.3.sub +SYMATTR Value2 LTC1514-3.3 +SYMATTR Description Step-Up/Step-Down Switched Capacitor DC/DC Converter with Low-Battery Comparator, Fixed 3.3V Output +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1514-5.asy b/spice/copy/sym/PowerProducts/LTC1514-5.asy new file mode 100755 index 0000000..dedb35d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1514-5.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1514-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1514-5.sub +SYMATTR Value2 LTC1514-5 +SYMATTR Description Step-Up/Step-Down Switched Capacitor DC/DC Converter with Low-Battery Comparator, Fixed 5V Output +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1515-3.3.asy b/spice/copy/sym/PowerProducts/LTC1515-3.3.asy new file mode 100755 index 0000000..9dcefe1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1515-3.3.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1515-3.3/5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1515-3.3.sub +SYMATTR Value2 LTC1515-3.3 +SYMATTR Description Step-Up/Step-Down Switched Capacitor DC/DC Converter with Reset, Programmable 3.3V or 5V Output Voltage +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName POR +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName 5/3.3 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1515-3.asy b/spice/copy/sym/PowerProducts/LTC1515-3.asy new file mode 100755 index 0000000..1df27a5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1515-3.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 65 Center 2 +SYMATTR Value LTC1515-3/5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1515-3.sub +SYMATTR Value2 LTC1515-3 +SYMATTR Description Step-Up/Step-Down Switched Capacitor DC/DC Converter with Reset, Programmable 3V or 5V Output Voltage +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName POR +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName 5/3 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1515.asy b/spice/copy/sym/PowerProducts/LTC1515.asy new file mode 100755 index 0000000..288fc95 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1515.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1515 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1515.sub +SYMATTR Value2 LTC1515 +SYMATTR Description Step-Up/Step-Down Switched Capacitor DC/DC Converter with Reset, Adjustable Output Voltage +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName POR +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1516.asy b/spice/copy/sym/PowerProducts/LTC1516.asy new file mode 100755 index 0000000..e396910 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1516.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1516 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1516.sub +SYMATTR Value2 LTC1516 +SYMATTR Description µPower, Regulated 5V Charge Pump DC/DC Converter +PIN -144 -96 LEFT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1517-3.3.asy b/spice/copy/sym/PowerProducts/LTC1517-3.3.asy new file mode 100755 index 0000000..76b74bf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1517-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value LTC1517-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1517-3.3.sub +SYMATTR Value2 LTC1517-3.3 +SYMATTR Description µPower, Regulated 3.3V Charge Pump in a 5-Pin SOT-23 Package +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 80 -112 TOP 8 +PINATTR PinName Cap+ +PINATTR SpiceOrder 4 +PIN -80 -112 TOP 8 +PINATTR PinName Cap- +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LTC1517-5.asy b/spice/copy/sym/PowerProducts/LTC1517-5.asy new file mode 100755 index 0000000..3b8f323 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1517-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value LTC1517-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1517-5.sub +SYMATTR Value2 LTC1517-5 +SYMATTR Description µPower, Regulated 5V Charge Pump in a 5-Pin SOT-23 Package +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 80 -112 TOP 8 +PINATTR PinName Cap+ +PINATTR SpiceOrder 4 +PIN -80 -112 TOP 8 +PINATTR PinName Cap- +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LTC1522.asy b/spice/copy/sym/PowerProducts/LTC1522.asy new file mode 100755 index 0000000..7f3b21b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1522.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC1522 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1522.sub +SYMATTR Value2 LTC1522 +SYMATTR Description µPower, Regulated 5V Charge Pump DC/DC Converter +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 144 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN -144 -64 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 4 +PIN -144 64 LEFT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 64 RIGHT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LTC1530-1.9.asy b/spice/copy/sym/PowerProducts/LTC1530-1.9.asy new file mode 100755 index 0000000..816a57e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1530-1.9.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 65 Center 2 +SYMATTR Value LTC1530-1.9 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1530.sub +SYMATTR Value2 LTC1530 Top=22077 Bot=41K +SYMATTR Description High Power Synchronous Switching Regulator Controller, Fixed 1.9 Volt Output +PIN 0 -160 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 1 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN -160 -32 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 5 +PIN 160 -32 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 6 +PIN 160 32 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1530-2.5.asy b/spice/copy/sym/PowerProducts/LTC1530-2.5.asy new file mode 100755 index 0000000..b7fd271 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1530-2.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1530-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1530.sub +SYMATTR Value2 LTC1530 Top=41996 Bot=41K +SYMATTR Description High Power Synchronous Switching Regulator Controller, Fixed 2.5 Volt Output +PIN 0 -160 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 1 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN -160 -32 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 5 +PIN 160 -32 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 6 +PIN 160 32 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1530-2.8.asy b/spice/copy/sym/PowerProducts/LTC1530-2.8.asy new file mode 100755 index 0000000..068f736 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1530-2.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1530-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1530.sub +SYMATTR Value2 LTC1530 Top=51955 Bot=41K +SYMATTR Description High Power Synchronous Switching Regulator Controller, Fixed 2.8 Volt Output +PIN 0 -160 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 1 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN -160 -32 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 5 +PIN 160 -32 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 6 +PIN 160 32 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1530-3.3.asy b/spice/copy/sym/PowerProducts/LTC1530-3.3.asy new file mode 100755 index 0000000..09bc2c0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1530-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1530-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1530.sub +SYMATTR Value2 LTC1530 Top=68555 Bot=41K +SYMATTR Description High Power Synchronous Switching Regulator Controller, Fixed 3.3 Volt Output +PIN 0 -160 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 1 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN -160 -32 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 5 +PIN 160 -32 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 6 +PIN 160 32 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1530.asy b/spice/copy/sym/PowerProducts/LTC1530.asy new file mode 100755 index 0000000..1336a30 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1530.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1530 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1530.sub +SYMATTR Value2 LTC1530 Top=10 Bot=1T +SYMATTR Description High Power Synchronous Switching Regulator Controller, Adjustable Output Voltage +PIN 0 -160 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 1 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 160 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 -32 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 5 +PIN 160 -32 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 6 +PIN 160 32 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 7 +PIN 160 -96 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1538-AUX.asy b/spice/copy/sym/PowerProducts/LTC1538-AUX.asy new file mode 100755 index 0000000..ea67ee3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1538-AUX.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -416 -400 416 480 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LTC1538-AUX +SYMATTR Prefix X +SYMATTR SpiceModel LTC1538-AUX.sub +SYMATTR Value2 LTC1538-AUX +SYMATTR Description Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulator +PIN -320 480 BOTTOM 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 1 +PIN -416 80 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 2 +PIN -416 160 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 3 +PIN -416 320 LEFT 8 +PINATTR PinName Vprog1 +PINATTR SpiceOrder 4 +PIN -416 400 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 5 +PIN -160 480 BOTTOM 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 7 +PIN 0 480 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -416 240 LEFT 8 +PINATTR PinName SFB1 +PINATTR SpiceOrder 11 +PIN 416 400 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 12 +PIN 416 320 RIGHT 8 +PINATTR PinName Vosense2 +PINATTR SpiceOrder 14 +PIN 416 240 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 15 +PIN 416 160 RIGHT 8 +PINATTR PinName Sense+2 +PINATTR SpiceOrder 16 +PIN 320 480 BOTTOM 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 17 +PIN 416 -320 RIGHT 8 +PINATTR PinName AUXDR +PINATTR SpiceOrder 18 +PIN 416 -240 RIGHT 8 +PINATTR PinName AUXFB +PINATTR SpiceOrder 19 +PIN -416 -320 LEFT 8 +PINATTR PinName AUXON +PINATTR SpiceOrder 20 +PIN 416 -160 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 21 +PIN 416 -80 RIGHT 8 +PINATTR PinName TGL2 +PINATTR SpiceOrder 22 +PIN 416 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 23 +PIN 240 -400 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 25 +PIN 416 80 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 26 +PIN 160 480 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 27 +PIN 0 -400 TOP 8 +PINATTR PinName INTVcc/5V +PINATTR SpiceOrder 28 +PIN -416 0 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 29 +PIN -240 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 30 +PIN -416 -80 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 32 +PIN -416 -160 LEFT 8 +PINATTR PinName TGL1 +PINATTR SpiceOrder 33 +PIN -416 -240 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 34 diff --git a/spice/copy/sym/PowerProducts/LTC1539.asy b/spice/copy/sym/PowerProducts/LTC1539.asy new file mode 100755 index 0000000..6ed5908 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1539.asy @@ -0,0 +1,116 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -416 -560 416 560 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LTC1539 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1539.sub +SYMATTR Value2 LTC1539 +SYMATTR Description Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulator +PIN -320 560 BOTTOM 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 1 +PIN -416 160 LEFT 8 +PINATTR PinName Sense+1 +PINATTR SpiceOrder 2 +PIN -416 240 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 3 +PIN -416 400 LEFT 8 +PINATTR PinName Vprog1 +PINATTR SpiceOrder 4 +PIN -416 480 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 5 +PIN -160 560 BOTTOM 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 7 +PIN 0 560 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -416 -320 LEFT 8 +PINATTR PinName LBI +PINATTR SpiceOrder 9 +PIN 416 -320 RIGHT 8 +PINATTR PinName LBO +PINATTR SpiceOrder 10 +PIN -416 320 LEFT 8 +PINATTR PinName SFB1 +PINATTR SpiceOrder 11 +PIN 416 480 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 12 +PIN 416 400 RIGHT 8 +PINATTR PinName Vprog2 +PINATTR SpiceOrder 13 +PIN 416 320 RIGHT 8 +PINATTR PinName Vosense2 +PINATTR SpiceOrder 14 +PIN 416 240 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 15 +PIN 416 160 RIGHT 8 +PINATTR PinName Sense+2 +PINATTR SpiceOrder 16 +PIN 320 560 BOTTOM 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 17 +PIN 416 -480 RIGHT 8 +PINATTR PinName AUXDR +PINATTR SpiceOrder 18 +PIN 416 -400 RIGHT 8 +PINATTR PinName AUXFB +PINATTR SpiceOrder 19 +PIN 336 -560 TOP 8 +PINATTR PinName AUXON +PINATTR SpiceOrder 20 +PIN 416 -240 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 21 +PIN 416 -80 RIGHT 8 +PINATTR PinName TGL2 +PINATTR SpiceOrder 22 +PIN 416 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 23 +PIN 416 -160 RIGHT 8 +PINATTR PinName TGS2 +PINATTR SpiceOrder 24 +PIN 112 -560 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 25 +PIN 416 80 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 26 +PIN 160 560 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 27 +PIN -112 -560 TOP 8 +PINATTR PinName INTVcc/5V +PINATTR SpiceOrder 28 +PIN -416 80 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 29 +PIN -336 -560 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 30 +PIN -416 -160 LEFT 8 +PINATTR PinName TGS1 +PINATTR SpiceOrder 31 +PIN -416 0 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 32 +PIN -416 -80 LEFT 8 +PINATTR PinName TGL1 +PINATTR SpiceOrder 33 +PIN -416 -240 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 34 +PIN -416 -480 LEFT 8 +PINATTR PinName PLL IN +PINATTR SpiceOrder 35 +PIN -416 -400 LEFT 8 +PINATTR PinName PLL LPF +PINATTR SpiceOrder 36 diff --git a/spice/copy/sym/PowerProducts/LTC1550.asy b/spice/copy/sym/PowerProducts/LTC1550.asy new file mode 100755 index 0000000..69c81d9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1550.asy @@ -0,0 +1,64 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 384 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 96 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 320 Center 2 +SYMATTR Value LTC1550 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1550.sub +SYMATTR Value2 LTC1550 +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Adjustable Output +PIN -144 -96 LEFT 8 +PINATTR PinName NC +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName NC +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN -144 224 LEFT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN -144 288 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 7 +PIN -144 352 LEFT 8 +PINATTR PinName NC +PINATTR SpiceOrder 8 +PIN 144 352 RIGHT 8 +PINATTR PinName NC +PINATTR SpiceOrder 9 +PIN 144 288 RIGHT 8 +PINATTR PinName NC +PINATTR SpiceOrder 10 +PIN 144 224 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 11 +PIN 144 160 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 12 +PIN 144 96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 13 +PIN 144 32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 14 +PIN 144 -32 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1550CS8-4.1.asy b/spice/copy/sym/PowerProducts/LTC1550CS8-4.1.asy new file mode 100755 index 0000000..f71c652 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1550CS8-4.1.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1550CS8-4.1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1550CS8-4.1.sub +SYMATTR Value2 LTC1550CS8-4.1 +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Fixed -4.1V Output +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1550L.asy b/spice/copy/sym/PowerProducts/LTC1550L.asy new file mode 100755 index 0000000..796285c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1550L.asy @@ -0,0 +1,64 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 384 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 96 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 320 Center 2 +SYMATTR Value LTC1550L +SYMATTR Prefix X +SYMATTR SpiceModel LTC1550L.sub +SYMATTR Value2 LTC1550L +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Adjustable Output +PIN -144 -96 LEFT 8 +PINATTR PinName NC +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName NC +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN -144 224 LEFT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 6 +PIN -144 288 LEFT 8 +PINATTR PinName AGND +PINATTR SpiceOrder 7 +PIN -144 352 LEFT 8 +PINATTR PinName NC +PINATTR SpiceOrder 8 +PIN 144 352 RIGHT 8 +PINATTR PinName NC +PINATTR SpiceOrder 9 +PIN 144 288 RIGHT 8 +PINATTR PinName NC +PINATTR SpiceOrder 10 +PIN 144 224 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 11 +PIN 144 160 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 12 +PIN 144 96 RIGHT 8 +PINATTR PinName NC +PINATTR SpiceOrder 13 +PIN 144 32 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 14 +PIN 144 -32 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 15 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1550LCS8-2.5.asy b/spice/copy/sym/PowerProducts/LTC1550LCS8-2.5.asy new file mode 100755 index 0000000..1c94109 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1550LCS8-2.5.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1550LCS8-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1550LCS8-2.5.sub +SYMATTR Value2 LTC1550LCS8-2.5 +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Fixed 2.5V Output +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1550LCS8-2.asy b/spice/copy/sym/PowerProducts/LTC1550LCS8-2.asy new file mode 100755 index 0000000..079d76e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1550LCS8-2.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1550LCS8-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1550LCS8-2.sub +SYMATTR Value2 LTC1550LCS8-2 +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Fixed 2V Output +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1550LCS8-4.1.asy b/spice/copy/sym/PowerProducts/LTC1550LCS8-4.1.asy new file mode 100755 index 0000000..2465866 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1550LCS8-4.1.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1550LCS8-4.1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1550LCS8-4.1.sub +SYMATTR Value2 LTC1550LCS8-4.1 +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Fixed 4.1V Output +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1550LCS8.asy b/spice/copy/sym/PowerProducts/LTC1550LCS8.asy new file mode 100755 index 0000000..b5e4fad --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1550LCS8.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1550LCS8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1550LCS8.sub +SYMATTR Value2 LTC1550LCS8 +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Adjustable Output Voltage +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1551CS8-4.1.asy b/spice/copy/sym/PowerProducts/LTC1551CS8-4.1.asy new file mode 100755 index 0000000..f822723 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1551CS8-4.1.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1551CS8-4.1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1551CS8-4.1.sub +SYMATTR Value2 LTC1551CS8-4.1 +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Fixed -4.1V Output +PIN -144 -96 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1551LCS8-4.1.asy b/spice/copy/sym/PowerProducts/LTC1551LCS8-4.1.asy new file mode 100755 index 0000000..7655d77 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1551LCS8-4.1.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1551LCS8-4.1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1551LCS8-4.1.sub +SYMATTR Value2 LTC1551LCS8-4.1 +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Fixed -4.1V Output +PIN -144 -96 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName REG +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1551LCS8.asy b/spice/copy/sym/PowerProducts/LTC1551LCS8.asy new file mode 100755 index 0000000..cfaf468 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1551LCS8.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1551LCS8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1551LCS8.sub +SYMATTR Value2 LTC1551LCS8 +SYMATTR Description Low Noise, Switched Capacitor Regulated Voltage Inverter, Adjustable Output Voltage +PIN -144 -96 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName CPout +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1553.asy b/spice/copy/sym/PowerProducts/LTC1553.asy new file mode 100755 index 0000000..4ca2945 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1553.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -320 192 320 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -232 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1553 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1553.sub +SYMATTR Value2 LTC1553 +SYMATTR Description 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor +PIN 192 0 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 1 +PIN 80 -320 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 2 +PIN 80 320 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 3 +PIN -80 320 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN -80 -320 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN 192 80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 192 -240 RIGHT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 7 +PIN 192 -80 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 8 +PIN 192 240 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN 192 160 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN -192 -128 LEFT 8 +PINATTR PinName _OT +PINATTR SpiceOrder 11 +PIN -192 -192 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 12 +PIN -192 -256 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 13 +PIN -192 -64 LEFT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 14 +PIN -192 0 LEFT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 15 +PIN -192 64 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 16 +PIN -192 128 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 17 +PIN -192 192 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 18 +PIN -192 256 LEFT 8 +PINATTR PinName OUTEN +PINATTR SpiceOrder 19 +PIN 192 -160 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC1553L.asy b/spice/copy/sym/PowerProducts/LTC1553L.asy new file mode 100755 index 0000000..19f8025 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1553L.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -320 192 320 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -231 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LTC1553L +SYMATTR Prefix X +SYMATTR SpiceModel LTC1553.sub +SYMATTR Value2 LTC1553 +SYMATTR Description 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor +PIN 192 0 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 1 +PIN 80 -320 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 2 +PIN 80 320 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 3 +PIN -80 320 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN -80 -320 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN 192 80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 192 -240 RIGHT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 7 +PIN 192 -80 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 8 +PIN 192 240 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN 192 160 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN -192 -128 LEFT 8 +PINATTR PinName _OT +PINATTR SpiceOrder 11 +PIN -192 -192 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 12 +PIN -192 -256 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 13 +PIN -192 -64 LEFT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 14 +PIN -192 0 LEFT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 15 +PIN -192 64 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 16 +PIN -192 128 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 17 +PIN -192 192 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 18 +PIN -192 256 LEFT 8 +PINATTR PinName OUTEN +PINATTR SpiceOrder 19 +PIN 192 -160 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC1574-3.3.asy b/spice/copy/sym/PowerProducts/LTC1574-3.3.asy new file mode 100755 index 0000000..e088940 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1574-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 8 -96 Left 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LTC1574-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1574.sub +SYMATTR Value2 LTC1574 top=51K bot=31.5K +SYMATTR Description High Efficiency Step-Down DC/DC Converter with Internal Schottky Diode, Fixed 3.3V Output +PIN 128 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 48 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -16 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1574-5.asy b/spice/copy/sym/PowerProducts/LTC1574-5.asy new file mode 100755 index 0000000..6554ba4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1574-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 8 -96 Left 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LTC1574-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1574.sub +SYMATTR Value2 LTC1574 top=93.5K bot=31.5K +SYMATTR Description High Efficiency Step-Down DC/DC Converter with Internal Schottky Diode, Fixed 5V Output +PIN 128 48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 48 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -16 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1574.asy b/spice/copy/sym/PowerProducts/LTC1574.asy new file mode 100755 index 0000000..3263372 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1574.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 8 -96 Left 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LTC1574 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1574.sub +SYMATTR Value2 LTC1574 top=1K bot=1T +SYMATTR Description High Efficiency Step-Down DC/DC Converter with Internal Schottky Diode, Adjustable Output Voltage +PIN 128 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 48 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -16 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1574HV.asy b/spice/copy/sym/PowerProducts/LTC1574HV.asy new file mode 100755 index 0000000..b3c52de --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1574HV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -80 128 112 +TEXT 0 8 Center 2 LT +WINDOW 0 8 -96 Left 2 +WINDOW 3 8 128 Left 2 +SYMATTR Value LTC1574HV +SYMATTR Prefix X +SYMATTR SpiceModel LTC1574.sub +SYMATTR Value2 LTC1574 top=1K bot=1T +SYMATTR Description High Efficiency Step-Down DC/DC Converter with Internal Schottky Diode, Adjustable Output Voltage +PIN 128 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -16 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -80 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -128 48 LEFT 8 +PINATTR PinName Ipgm +PINATTR SpiceOrder 7 +PIN -128 -16 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1622.asy b/spice/copy/sym/PowerProducts/LTC1622.asy new file mode 100755 index 0000000..4762796 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1622.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1622 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1622.sub +SYMATTR Value2 LTC1622 +SYMATTR Description Low Input Voltage Current Mode Step-Down DC/DC Controller +PIN 160 -80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 2 +PIN 160 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 80 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 4 +PIN -160 -80 LEFT 8 +PINATTR PinName MODE +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName PDRV +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1624.asy b/spice/copy/sym/PowerProducts/LTC1624.asy new file mode 100755 index 0000000..f0b63ba --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1624.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1624 +SYMATTR SpiceModel LTC1624.sub +SYMATTR Value2 LTC1624 +SYMATTR Prefix X +SYMATTR Description High Efficiency SO-8 N-Channel Switching Regulator Controller +PIN -160 -80 LEFT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 2 +PIN -160 80 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 160 0 RIGHT 8 +PINATTR PinName Tg +PINATTR SpiceOrder 6 +PIN 160 -80 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1625.asy b/spice/copy/sym/PowerProducts/LTC1625.asy new file mode 100755 index 0000000..201f427 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1625.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -384 240 384 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -256 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1625 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1625.sub +SYMATTR Value2 LTC1625 +SYMATTR Description No Rsense(TM) Current Mode Synchronous Step-Down Switching Regulator +PIN -240 -320 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 1 +PIN -240 -192 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 3 +PIN -240 -64 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -240 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 5 +PIN -112 384 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN -240 320 LEFT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 7 +PIN -240 192 LEFT 8 +PINATTR PinName Vprog +PINATTR SpiceOrder 8 +PIN 112 384 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 9 +PIN 240 320 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 10 +PIN 240 192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 11 +PIN 240 64 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 12 +PIN 240 -192 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 13 +PIN 240 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 240 -320 RIGHT 8 +PINATTR PinName TK +PINATTR SpiceOrder 15 +PIN 0 -384 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1626.asy b/spice/copy/sym/PowerProducts/LTC1626.asy new file mode 100755 index 0000000..afe0a78 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1626.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -128 176 224 +TEXT 0 40 Center 2 LT +WINDOW 0 0 -39 Center 2 +WINDOW 3 0 121 Center 2 +SYMATTR Value LTC1626 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1626.sub +SYMATTR Value2 LTC1626 +SYMATTR Description Low Voltage, High Efficiency Step-Down DC/DC Controller, Adjustable Output Voltage +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -176 -80 LEFT 8 +PINATTR PinName LBout +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName LBin +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 5 +PIN -176 80 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 176 80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN 176 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -96 224 BOTTOM 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 10 +PIN 96 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC1627.asy b/spice/copy/sym/PowerProducts/LTC1627.asy new file mode 100755 index 0000000..822908c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1627.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC1627 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1627.sub +SYMATTR Value2 LTC1627 +SYMATTR Description Monolithic Synchronous Step-Down Switching Regulator +PIN -144 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN 144 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vdr +PINATTR SpiceOrder 7 +PIN 144 96 RIGHT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1628-PG.asy b/spice/copy/sym/PowerProducts/LTC1628-PG.asy new file mode 100755 index 0000000..99467ad --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1628-PG.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -464 224 672 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -336 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LTC1628-PG +SYMATTR Prefix X +SYMATTR SpiceModel LTC1628-PG.sub +SYMATTR Value2 LTC1628-PG +SYMATTR Description High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator +PIN -224 384 LEFT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 1 +PIN -224 0 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN -224 96 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -224 192 LEFT 8 +PINATTR PinName Vosense1 +PINATTR SpiceOrder 4 +PIN 224 592 RIGHT 8 +PINATTR PinName FreqSet +PINATTR SpiceOrder 5 +PIN 0 672 BOTTOM 8 +PINATTR PinName STBYMD +PINATTR SpiceOrder 6 +PIN -224 480 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 7 +PIN -224 288 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 8 +PIN -144 672 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN 224 480 RIGHT 8 +PINATTR PinName 3.3Vout +PINATTR SpiceOrder 10 +PIN 224 288 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 11 +PIN 224 192 RIGHT 8 +PINATTR PinName Vosense2 +PINATTR SpiceOrder 12 +PIN 224 96 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 224 0 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN 224 384 RIGHT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 15 +PIN 224 -384 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 16 +PIN 224 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 224 -288 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 18 +PIN 224 -96 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 144 672 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 +PIN 0 -464 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 144 -464 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 22 +PIN -224 -96 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -144 -464 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN -224 -288 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 25 +PIN -224 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 26 +PIN -224 -384 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 27 +PIN -224 592 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1628-SYNC.asy b/spice/copy/sym/PowerProducts/LTC1628-SYNC.asy new file mode 100755 index 0000000..540a196 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1628-SYNC.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -464 224 672 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -336 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LTC1628-SYNC +SYMATTR Prefix X +SYMATTR SpiceModel LTC1628-SYNC.sub +SYMATTR Value2 LTC1628-SYNC +SYMATTR Description High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator +PIN -224 384 LEFT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 1 +PIN -224 0 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN -224 96 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -224 192 LEFT 8 +PINATTR PinName Vosense1 +PINATTR SpiceOrder 4 +PIN 224 592 RIGHT 8 +PINATTR PinName PLLFLTR +PINATTR SpiceOrder 5 +PIN 0 672 BOTTOM 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -224 480 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 7 +PIN -224 288 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 8 +PIN -144 672 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN 224 480 RIGHT 8 +PINATTR PinName 3.3Vout +PINATTR SpiceOrder 10 +PIN 224 288 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 11 +PIN 224 192 RIGHT 8 +PINATTR PinName Vosense2 +PINATTR SpiceOrder 12 +PIN 224 96 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 224 0 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN 224 384 RIGHT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 15 +PIN 224 -384 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 16 +PIN 224 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 224 -288 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 18 +PIN 224 -96 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 144 672 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 +PIN 0 -464 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 144 -464 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 22 +PIN -224 -96 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -144 -464 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN -224 -288 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 25 +PIN -224 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 26 +PIN -224 -384 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 27 +PIN -224 592 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1628.asy b/spice/copy/sym/PowerProducts/LTC1628.asy new file mode 100755 index 0000000..a038c47 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1628.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -464 224 672 +TEXT 0 -48 Center 2 LT +WINDOW 0 0 -336 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LTC1628 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1628.sub +SYMATTR Value2 LTC1628 +SYMATTR Description High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator +PIN -224 384 LEFT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 1 +PIN -224 0 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN -224 96 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -224 192 LEFT 8 +PINATTR PinName Vosense1 +PINATTR SpiceOrder 4 +PIN 224 592 RIGHT 8 +PINATTR PinName FreqSet +PINATTR SpiceOrder 5 +PIN 0 672 BOTTOM 8 +PINATTR PinName STBYMD +PINATTR SpiceOrder 6 +PIN -224 480 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 7 +PIN -224 288 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 8 +PIN -144 672 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN 224 480 RIGHT 8 +PINATTR PinName 3.3Vout +PINATTR SpiceOrder 10 +PIN 224 288 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 11 +PIN 224 192 RIGHT 8 +PINATTR PinName Vosense2 +PINATTR SpiceOrder 12 +PIN 224 96 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 224 0 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN 224 384 RIGHT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 15 +PIN 224 -384 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 16 +PIN 224 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 224 -288 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 18 +PIN 224 -96 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 144 672 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 +PIN 0 -464 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 144 -464 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 22 +PIN -224 -96 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -144 -464 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN -224 -288 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 25 +PIN -224 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 26 +PIN -224 -384 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 27 +PIN -224 592 LEFT 8 +PINATTR PinName FLTCPL +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1629-6.asy b/spice/copy/sym/PowerProducts/LTC1629-6.asy new file mode 100755 index 0000000..dcffb05 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1629-6.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -448 256 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -288 Center 2 +WINDOW 3 8 224 Center 2 +SYMATTR Value LTC1629-6 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1629-6.sub +SYMATTR Value2 LTC1629-6 +SYMATTR Description PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator +PIN -256 -64 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -64 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 256 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -192 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -256 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 -384 LEFT 8 +PINATTR PinName PHASEMD +PINATTR SpiceOrder 7 +PIN -256 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 192 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN -256 320 LEFT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN -256 384 LEFT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 384 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 128 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 15 +PIN 256 64 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 16 +PIN 256 192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 256 128 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 18 +PIN 256 256 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 112 448 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 +PIN 160 -448 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 0 -448 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 22 +PIN 256 -192 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -160 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN 256 -320 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 25 +PIN 256 -256 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 26 +PIN 256 -384 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 27 +PIN -256 -320 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1629-PG.asy b/spice/copy/sym/PowerProducts/LTC1629-PG.asy new file mode 100755 index 0000000..680a23a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1629-PG.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -448 256 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -288 Center 2 +WINDOW 3 8 224 Center 2 +SYMATTR Value LTC1629-PG +SYMATTR Prefix X +SYMATTR SpiceModel LTC1629-PG.sub +SYMATTR Value2 LTC1629-PG +SYMATTR Description PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator +PIN -256 -64 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -64 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 256 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -192 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -256 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 -384 LEFT 8 +PINATTR PinName PHASEMD +PINATTR SpiceOrder 7 +PIN -256 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 192 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN -256 320 LEFT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN -256 384 LEFT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 384 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 128 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 15 +PIN 256 64 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 16 +PIN 256 192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 256 128 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 18 +PIN 256 256 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 112 448 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 +PIN 160 -448 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 0 -448 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 22 +PIN 256 -192 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -160 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN 256 -320 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 25 +PIN 256 -256 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 26 +PIN 256 -384 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 27 +PIN -256 -320 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1629.asy b/spice/copy/sym/PowerProducts/LTC1629.asy new file mode 100755 index 0000000..fd621de --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1629.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -448 256 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -288 Center 2 +WINDOW 3 8 224 Center 2 +SYMATTR Value LTC1629 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1629.sub +SYMATTR Value2 LTC1629 +SYMATTR Description PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator +PIN -256 -64 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -64 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 256 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -192 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -256 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 -384 LEFT 8 +PINATTR PinName PHASEMD +PINATTR SpiceOrder 7 +PIN -256 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 192 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN -256 320 LEFT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN -256 384 LEFT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 384 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 128 LEFT 8 +PINATTR PinName AmpMode +PINATTR SpiceOrder 15 +PIN 256 64 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 16 +PIN 256 192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 256 128 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 18 +PIN 256 256 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 112 448 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 +PIN 160 -448 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 0 -448 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 22 +PIN 256 -192 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -160 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN 256 -320 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 25 +PIN 256 -256 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 26 +PIN 256 -384 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 27 +PIN -256 -320 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1647-1.asy b/spice/copy/sym/PowerProducts/LTC1647-1.asy new file mode 100755 index 0000000..577ae13 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1647-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1647-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1647-1.sub +SYMATTR Value2 LTC1647-1 +SYMATTR Description Dual Hot Swap Controllers +PIN -128 -64 LEFT 8 +PINATTR PinName ON1 +PINATTR SpiceOrder 2 +PIN 128 80 RIGHT 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 5 +PIN -80 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -64 RIGHT 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 6 +PIN 64 -128 TOP 8 +PINATTR PinName Sense1 +PINATTR SpiceOrder 8 +PIN -80 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN 64 144 BOTTOM 8 +PINATTR PinName Sense2 +PINATTR SpiceOrder 7 +PIN -128 80 LEFT 8 +PINATTR PinName ON2 +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LTC1647-2.asy b/spice/copy/sym/PowerProducts/LTC1647-2.asy new file mode 100755 index 0000000..a242f48 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1647-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1647-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1647-2.sub +SYMATTR Value2 LTC1647-2 +SYMATTR Description Dual Hot Swap Controllers +PIN -128 -64 LEFT 8 +PINATTR PinName ON1 +PINATTR SpiceOrder 2 +PIN 128 80 RIGHT 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 5 +PIN -80 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -64 RIGHT 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 6 +PIN 64 -128 TOP 8 +PINATTR PinName Sense1 +PINATTR SpiceOrder 8 +PIN -80 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN 64 144 BOTTOM 8 +PINATTR PinName Sense2 +PINATTR SpiceOrder 7 +PIN -128 80 LEFT 8 +PINATTR PinName ON2 +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/LTC1647-3.asy b/spice/copy/sym/PowerProducts/LTC1647-3.asy new file mode 100755 index 0000000..9c27777 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1647-3.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1647-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1647-3.sub +SYMATTR Value2 LTC1647-3 +SYMATTR Description Dual Hot Swap Controllers +PIN -16 -160 TOP 8 +PINATTR PinName Vcc1 +PINATTR SpiceOrder 1 +PIN -160 -128 LEFT 8 +PINATTR PinName ON1 +PINATTR SpiceOrder 2 +PIN -160 -64 LEFT 8 +PINATTR PinName _Fault1 +PINATTR SpiceOrder 3 +PIN -160 128 LEFT 8 +PINATTR PinName ON2 +PINATTR SpiceOrder 4 +PIN -160 64 LEFT 8 +PINATTR PinName _Fault2 +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 48 RIGHT 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 12 +PIN 160 -48 RIGHT 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 13 +PIN 96 160 BOTTOM 8 +PINATTR PinName Sense2 +PINATTR SpiceOrder 14 +PIN 96 -160 TOP 8 +PINATTR PinName Sense1 +PINATTR SpiceOrder 15 +PIN -16 160 BOTTOM 8 +PINATTR PinName Vcc2 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1649.asy b/spice/copy/sym/PowerProducts/LTC1649.asy new file mode 100755 index 0000000..0ccd351 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1649.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -224 208 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1649 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1649.sub +SYMATTR Value2 LTC1649 +SYMATTR Description 3.3V Input High Power Step-Down Synchronous Switching Regulator Controller, Adjustable Output Voltage +PIN 208 -160 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 1 +PIN 128 -224 TOP 8 +PINATTR PinName PVcc1 +PINATTR SpiceOrder 2 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 208 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -208 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -208 160 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 6 +PIN -208 32 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 208 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 8 +PIN 208 32 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 9 +PIN -128 -224 TOP 8 +PINATTR PinName CPout +PINATTR SpiceOrder 10 +PIN -208 96 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 11 +PIN -208 -32 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 12 +PIN 208 -96 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 13 +PIN -208 -160 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 14 +PIN 0 -224 TOP 8 +PINATTR PinName PVcc2 +PINATTR SpiceOrder 15 +PIN 208 -32 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1682-3.3.asy b/spice/copy/sym/PowerProducts/LTC1682-3.3.asy new file mode 100755 index 0000000..dfb3ae6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1682-3.3.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 64 Center 2 +SYMATTR Value LTC1682-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1682-3.3.sub +SYMATTR Value2 LTC1682-3.3 +SYMATTR Description Doubler Charge Pump with Low Noise Linear Regulator, Fixed 3.3V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName FILT +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName CPO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1682-5.asy b/spice/copy/sym/PowerProducts/LTC1682-5.asy new file mode 100755 index 0000000..3c33bb7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1682-5.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1682-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1682-5.sub +SYMATTR Value2 LTC1682-5 +SYMATTR Description Doubler Charge Pump with Low Noise Linear Regulator, Fixed 5V Output +PIN -144 -96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName FILT +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName CPO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1682.asy b/spice/copy/sym/PowerProducts/LTC1682.asy new file mode 100755 index 0000000..bc2857d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1682.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -144 -128 144 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1682 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1682.sub +SYMATTR Value2 LTC1682 +SYMATTR Description Doubler Charge Pump with Low Noise Linear Regulator, Adjustable Output Voltage +PIN -144 -96 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName CPO +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1693-1.asy b/spice/copy/sym/PowerProducts/LTC1693-1.asy new file mode 100755 index 0000000..ae94e61 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1693-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -76 Center 2 +WINDOW 3 0 73 Center 2 +SYMATTR Value LTC1693-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1693-1.sub +SYMATTR Value2 LTC1693-1 +SYMATTR Description Dual High Speed MOSFET Driver +PIN -128 -48 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN -64 128 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 2 +PIN -128 48 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 3 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 48 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 5 +PIN 64 -128 TOP 8 +PINATTR PinName Vcc2 +PINATTR SpiceOrder 6 +PIN 128 -48 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 7 +PIN -64 -128 TOP 8 +PINATTR PinName Vcc1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1693-2.asy b/spice/copy/sym/PowerProducts/LTC1693-2.asy new file mode 100755 index 0000000..e9ff6b2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1693-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 73 Center 2 +SYMATTR Value LTC1693-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1693-2.sub +SYMATTR Value2 LTC1693-2 +SYMATTR Description Dual High Speed MOSFET Driver +PIN -128 -48 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN -64 128 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 2 +PIN -128 48 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 3 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 4 +PIN 128 48 RIGHT 8 +PINATTR PinName _OUT2 +PINATTR SpiceOrder 5 +PIN 64 -128 TOP 8 +PINATTR PinName Vcc2 +PINATTR SpiceOrder 6 +PIN 128 -48 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 7 +PIN -64 -128 TOP 8 +PINATTR PinName Vcc1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1693-3.asy b/spice/copy/sym/PowerProducts/LTC1693-3.asy new file mode 100755 index 0000000..3498007 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1693-3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -96 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LTC1693-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1693-3.sub +SYMATTR Value2 LTC1693-3 +SYMATTR Description High Speed MOSFET Driver +PIN -128 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -128 48 LEFT 8 +PINATTR PinName PHI +PINATTR SpiceOrder 3 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -96 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1693-5.asy b/spice/copy/sym/PowerProducts/LTC1693-5.asy new file mode 100755 index 0000000..4ba3294 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1693-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -96 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LTC1693-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1693-5.sub +SYMATTR Value2 LTC1693-5 +SYMATTR Description High Speed Single P-Channel MOSFET Driver +PIN -128 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -128 48 LEFT 8 +PINATTR PinName PHI +PINATTR SpiceOrder 3 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 0 -96 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1697.asy b/spice/copy/sym/PowerProducts/LTC1697.asy new file mode 100755 index 0000000..32f0b7e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1697.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 160 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC1697 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1697.sub +SYMATTR Value2 LTC1697 +SYMATTR Description High Efficiency Low Power 1W CCFL Switching Regulator +PIN -160 96 LEFT 8 +PINATTR PinName Cdim +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName Vdim +PINATTR SpiceOrder 2 +PIN 96 -176 TOP 8 +PINATTR PinName OVsen +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 -96 RIGHT 8 +PINATTR PinName Lamp +PINATTR SpiceOrder 6 +PIN -96 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 7 +PIN 160 0 RIGHT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 +PIN 160 96 RIGHT 8 +PINATTR PinName Rprog +PINATTR SpiceOrder 9 +PIN -160 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC1698.asy b/spice/copy/sym/PowerProducts/LTC1698.asy new file mode 100755 index 0000000..e4b2d63 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1698.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 224 -144 -209 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 64 Center 2 +WINDOW 0 0 -128 Center 2 +SYMATTR Value LTC1698 +SYMATTR SpiceModel LTC1698.sub +SYMATTR Value2 LTC1698 +SYMATTR Prefix X +SYMATTR Description Isolated Secondary Synchronous Rectifier Controller +PIN -64 -208 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -144 -160 LEFT 8 +PINATTR PinName CG +PINATTR SpiceOrder 2 +PIN -64 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 3 +PIN 64 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName OPTODRV +PINATTR SpiceOrder 5 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vcomp +PINATTR SpiceOrder 6 +PIN 144 96 RIGHT 8 +PINATTR PinName MARGIN +PINATTR SpiceOrder 7 +PIN 144 -160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN 144 32 RIGHT 8 +PINATTR PinName OVPIN +PINATTR SpiceOrder 9 +PIN 64 -208 TOP 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 10 +PIN -144 32 LEFT 8 +PINATTR PinName Isnsgnd +PINATTR SpiceOrder 11 +PIN -144 -32 LEFT 8 +PINATTR PinName Isns +PINATTR SpiceOrder 12 +PIN 144 -32 RIGHT 8 +PINATTR PinName Icomp +PINATTR SpiceOrder 13 +PIN 144 160 RIGHT 8 +PINATTR PinName Vaux +PINATTR SpiceOrder 14 +PIN -144 96 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 15 +PIN -144 -96 LEFT 8 +PINATTR PinName FG +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1700.asy b/spice/copy/sym/PowerProducts/LTC1700.asy new file mode 100755 index 0000000..94f0ab8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1700.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1700 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1700.sub +SYMATTR Value2 LTC1700 +SYMATTR Description No Rsense Synchronous Step-Up DC/DC Controller +PIN -80 208 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 1 +PIN -160 -144 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 2 +PIN -160 48 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 -48 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 4 +PIN -160 144 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 5 +PIN 160 48 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 6 +PIN 160 144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 160 -48 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 8 +PIN 80 208 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 9 +PIN 160 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC1701.asy b/spice/copy/sym/PowerProducts/LTC1701.asy new file mode 100755 index 0000000..b4cb3d3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1701.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 89 Center 2 +SYMATTR Value LTC1701 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1701.sub +SYMATTR Value2 LTC1701 +SYMATTR Description 1MHz Step-Down DC/DC Converter in SOT-23 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName Ith/Run +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LTC1701B.asy b/spice/copy/sym/PowerProducts/LTC1701B.asy new file mode 100755 index 0000000..e3d1aee --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1701B.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -112 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 89 Center 2 +SYMATTR Value LTC1701B +SYMATTR Prefix X +SYMATTR SpiceModel LTC1701B.sub +SYMATTR Value2 LTC1701B +SYMATTR Description 1MHz Step-Down DC/DC Converter in SOT-23 +PIN 144 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName Ith/Run +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LTC1702.asy b/spice/copy/sym/PowerProducts/LTC1702.asy new file mode 100755 index 0000000..2a8f6bc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1702.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -208 192 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1702 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1702.sub +SYMATTR Value2 LTC1702 +SYMATTR Description Dual 550kHz Synchronous 2-Phase Switching Regulator Controller\n\nNote: Only one phase of two phases is modeled. +PIN 0 -208 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 1 +PIN 112 -208 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 192 0 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 3 +PIN 192 -128 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 4 +PIN 192 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -192 64 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 6 +PIN -192 -64 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN -192 -128 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 8 +PIN -192 128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 9 +PIN 192 64 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN -80 208 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 192 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -112 -208 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 13 +PIN -192 0 LEFT 8 +PINATTR PinName Fault +PINATTR SpiceOrder 17 +PIN 80 208 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LTC1702A.asy b/spice/copy/sym/PowerProducts/LTC1702A.asy new file mode 100755 index 0000000..1b51c8b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1702A.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -208 192 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1702A +SYMATTR Prefix X +SYMATTR SpiceModel LTC1702A.sub +SYMATTR Value2 LTC1702A +SYMATTR Description Dual 550kHz Synchronous 2-Phase Switching Regulator Controller\n\nNote: Only one phase of two phases is modeled. +PIN 0 -208 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 1 +PIN 112 -208 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 2 +PIN 192 0 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 3 +PIN 192 -128 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 4 +PIN 192 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN -192 64 LEFT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 6 +PIN -192 -64 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN -192 -128 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 8 +PIN -192 128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 9 +PIN 192 64 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN -80 208 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 192 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -112 -208 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 13 +PIN -192 0 LEFT 8 +PINATTR PinName Fault +PINATTR SpiceOrder 17 +PIN 80 208 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LTC1703.asy b/spice/copy/sym/PowerProducts/LTC1703.asy new file mode 100755 index 0000000..2b72217 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1703.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -416 -400 416 480 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 200 Center 2 +SYMATTR Value LTC1703 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1703.sub +SYMATTR Value2 LTC1703 +SYMATTR Description Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with VID +PIN 96 -400 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 1 +PIN -288 -400 TOP 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 2 +PIN -416 -80 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 3 +PIN -416 -240 LEFT 8 +PINATTR PinName TB1 +PINATTR SpiceOrder 4 +PIN -416 -160 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 5 +PIN -416 240 LEFT 8 +PINATTR PinName Imax1 +PINATTR SpiceOrder 6 +PIN -416 -320 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 7 +PIN -288 480 BOTTOM 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 8 +PIN -416 80 LEFT 8 +PINATTR PinName COMP1 +PINATTR SpiceOrder 9 +PIN -96 480 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 10 +PIN -416 160 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 11 +PIN -416 0 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 12 +PIN -416 320 LEFT 8 +PINATTR PinName VD0 +PINATTR SpiceOrder 13 +PIN -416 400 LEFT 8 +PINATTR PinName VD1 +PINATTR SpiceOrder 14 +PIN 416 400 RIGHT 8 +PINATTR PinName VD2 +PINATTR SpiceOrder 15 +PIN 416 320 RIGHT 8 +PINATTR PinName VD3 +PINATTR SpiceOrder 16 +PIN 416 240 RIGHT 8 +PINATTR PinName VD4 +PINATTR SpiceOrder 17 +PIN -96 -400 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 18 +PIN 416 80 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 19 +PIN 416 0 RIGHT 8 +PINATTR PinName COMP2 +PINATTR SpiceOrder 20 +PIN 288 480 BOTTOM 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 21 +PIN 416 -320 RIGHT 8 +PINATTR PinName FAULT +PINATTR SpiceOrder 22 +PIN 96 480 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 23 +PIN 416 -160 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 24 +PIN 416 -240 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 25 +PIN 416 -80 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 26 +PIN 288 -400 TOP 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 27 +PIN 416 160 RIGHT 8 +PINATTR PinName Imax2 +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1706-19.asy b/spice/copy/sym/PowerProducts/LTC1706-19.asy new file mode 100755 index 0000000..1e6b1d4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1706-19.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 1 64 Center 2 +SYMATTR Value LTC1706-19 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1706-19.sub +SYMATTR Value2 LTC1706-19 +SYMATTR Description VID Voltage Programmer +PIN 144 32 RIGHT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 1 +PIN 144 96 RIGHT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 80 -160 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 144 -96 RIGHT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 7 +PIN 144 -32 RIGHT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1706-61.asy b/spice/copy/sym/PowerProducts/LTC1706-61.asy new file mode 100755 index 0000000..20e575c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1706-61.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1706-61 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1706-61.sub +SYMATTR Value2 LTC1706-61 +SYMATTR Description 5-Bit VID Voltage Programmer for AMD Opteron CPUs +PIN 144 0 RIGHT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 80 -160 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 144 -96 RIGHT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 8 +PIN 144 96 RIGHT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC1706-63.asy b/spice/copy/sym/PowerProducts/LTC1706-63.asy new file mode 100755 index 0000000..426193c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1706-63.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1706-63 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1706-63.sub +SYMATTR Value2 LTC1706-63 +SYMATTR Description 5-Bit VID Voltage Programmer for Sun CPUs +PIN 144 0 RIGHT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 80 -160 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 144 -96 RIGHT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 8 +PIN 144 96 RIGHT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC1706-81.asy b/spice/copy/sym/PowerProducts/LTC1706-81.asy new file mode 100755 index 0000000..62fbfed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1706-81.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1706-81 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1706-81.sub +SYMATTR Value2 LTC1706-81 +SYMATTR Description 5-Bit Desktop VID Voltage Programmer +PIN 144 0 RIGHT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 80 -160 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 144 -96 RIGHT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 8 +PIN 144 96 RIGHT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC1706-82.asy b/spice/copy/sym/PowerProducts/LTC1706-82.asy new file mode 100755 index 0000000..19421b1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1706-82.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1706-82 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1706-82.sub +SYMATTR Value2 LTC1706-82 +SYMATTR Description VID Voltage Programmer for Intel VRM9.0/9.1 +PIN 144 0 RIGHT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 80 -160 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 144 -96 RIGHT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 8 +PIN 144 96 RIGHT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC1706-85.asy b/spice/copy/sym/PowerProducts/LTC1706-85.asy new file mode 100755 index 0000000..7f708ee --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1706-85.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1706-85 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1706-85.sub +SYMATTR Value2 LTC1706-85 +SYMATTR Description VID Voltage Programmer for Intel VRM 8.5 +PIN 144 0 RIGHT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 2 +PIN -80 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 80 -160 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 144 -96 RIGHT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 7 +PIN 144 -48 RIGHT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 8 +PIN 144 96 RIGHT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC1707.asy b/spice/copy/sym/PowerProducts/LTC1707.asy new file mode 100755 index 0000000..5907c2d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1707.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 0 57 Center 2 +SYMATTR Value LTC1707 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1707.sub +SYMATTR Value2 LTC1707 +SYMATTR Description High Efficiency Monolithic Synchronous Step-Down Regulator\n\nNote: External sync. capability is not modeled. +PIN 144 80 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 -80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 7 +PIN -144 0 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1709-7.asy b/spice/copy/sym/PowerProducts/LTC1709-7.asy new file mode 100755 index 0000000..df5e718 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1709-7.asy @@ -0,0 +1,113 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -512 256 512 +TEXT 0 -96 Center 2 LT +WINDOW 0 0 -352 Center 2 +WINDOW 3 8 192 Center 2 +SYMATTR Value LTC1709-7 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1709-7.sub +SYMATTR Value2 LTC1709-7 +SYMATTR Description 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulator\n\nNote: The FCB pin is not modeled. The model only operates in Forced Continuous Mode. +PIN -256 -256 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -192 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 -64 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -320 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -384 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 -192 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 512 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 128 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN 256 448 RIGHT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN 256 384 RIGHT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 256 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 0 LEFT 8 +PINATTR PinName AttenOut +PINATTR SpiceOrder 15 +PIN -256 64 LEFT 8 +PINATTR PinName AttenIn +PINATTR SpiceOrder 16 +PIN -256 192 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 17 +PIN -256 256 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 18 +PIN -256 320 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 19 +PIN -256 384 LEFT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 20 +PIN -256 448 LEFT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 21 +PIN 0 -512 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 22 +PIN -256 -128 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 23 +PIN 256 0 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 24 +PIN 256 128 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 25 +PIN 256 64 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 26 +PIN 256 192 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 27 +PIN 112 512 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 28 +PIN 160 -512 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 29 +PIN -256 -448 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 30 +PIN 256 -256 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 31 +PIN -160 -512 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 32 +PIN 256 -384 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 33 +PIN 256 -320 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN 256 -448 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 35 diff --git a/spice/copy/sym/PowerProducts/LTC1709-8.asy b/spice/copy/sym/PowerProducts/LTC1709-8.asy new file mode 100755 index 0000000..308b3fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1709-8.asy @@ -0,0 +1,113 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -512 256 512 +TEXT 0 -96 Center 2 LT +WINDOW 0 0 -352 Center 2 +WINDOW 3 8 192 Center 2 +SYMATTR Value LTC1709-8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1709-8.sub +SYMATTR Value2 LTC1709-8 +SYMATTR Description 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulator +PIN -256 -256 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -192 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 -64 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -320 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -384 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 -192 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 512 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 128 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN 256 448 RIGHT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN 256 384 RIGHT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 256 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 0 LEFT 8 +PINATTR PinName AttenOut +PINATTR SpiceOrder 15 +PIN -256 64 LEFT 8 +PINATTR PinName AttenIn +PINATTR SpiceOrder 16 +PIN -256 192 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 17 +PIN -256 256 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 18 +PIN -256 320 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 19 +PIN -256 384 LEFT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 20 +PIN -256 448 LEFT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 21 +PIN 0 -512 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 22 +PIN -256 -128 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 23 +PIN 256 0 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 24 +PIN 256 128 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 25 +PIN 256 64 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 26 +PIN 256 192 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 27 +PIN 112 512 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 28 +PIN 160 -512 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 29 +PIN -256 -448 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 30 +PIN 256 -256 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 31 +PIN -160 -512 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 32 +PIN 256 -384 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 33 +PIN 256 -320 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN 256 -448 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 35 diff --git a/spice/copy/sym/PowerProducts/LTC1709-85.asy b/spice/copy/sym/PowerProducts/LTC1709-85.asy new file mode 100755 index 0000000..13792bc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1709-85.asy @@ -0,0 +1,113 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -512 256 512 +TEXT 0 -96 Center 2 LT +WINDOW 0 0 -352 Center 2 +WINDOW 3 8 192 Center 2 +SYMATTR Value LTC1709-85 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1709-85.sub +SYMATTR Value2 LTC1709-85 +SYMATTR Description 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulator\n\nNote: The FCB pin is not modeled. The model only operates in Forced Continuous Mode. +PIN -256 -256 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -192 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 -64 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -320 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -384 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 -192 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 512 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 128 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN 256 448 RIGHT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN 256 384 RIGHT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 256 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 0 LEFT 8 +PINATTR PinName AttenOut +PINATTR SpiceOrder 15 +PIN -256 64 LEFT 8 +PINATTR PinName AttenIn +PINATTR SpiceOrder 16 +PIN -256 192 LEFT 8 +PINATTR PinName VID25mV +PINATTR SpiceOrder 17 +PIN -256 256 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 18 +PIN -256 320 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 19 +PIN -256 384 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 20 +PIN -256 448 LEFT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 21 +PIN 0 -512 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 22 +PIN -256 -128 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 23 +PIN 256 0 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 24 +PIN 256 128 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 25 +PIN 256 64 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 26 +PIN 256 192 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 27 +PIN 112 512 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 28 +PIN 160 -512 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 29 +PIN -256 -448 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 30 +PIN 256 -256 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 31 +PIN -160 -512 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 32 +PIN 256 -384 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 33 +PIN 256 -320 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN 256 -448 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 35 diff --git a/spice/copy/sym/PowerProducts/LTC1709-9.asy b/spice/copy/sym/PowerProducts/LTC1709-9.asy new file mode 100755 index 0000000..1a624a7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1709-9.asy @@ -0,0 +1,113 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -512 256 512 +TEXT 0 -96 Center 2 LT +WINDOW 0 0 -352 Center 2 +WINDOW 3 8 192 Center 2 +SYMATTR Value LTC1709-9 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1709-9.sub +SYMATTR Value2 LTC1709-9 +SYMATTR Description 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulator +PIN -256 -256 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -192 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 -64 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -320 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -384 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 -192 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 512 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 128 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN 256 448 RIGHT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN 256 384 RIGHT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 256 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 0 LEFT 8 +PINATTR PinName AttenOut +PINATTR SpiceOrder 15 +PIN -256 64 LEFT 8 +PINATTR PinName AttenIn +PINATTR SpiceOrder 16 +PIN -256 192 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 17 +PIN -256 256 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 18 +PIN -256 320 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 19 +PIN -256 384 LEFT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 20 +PIN -256 448 LEFT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 21 +PIN 0 -512 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 22 +PIN -256 -128 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 23 +PIN 256 0 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 24 +PIN 256 128 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 25 +PIN 256 64 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 26 +PIN 256 192 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 27 +PIN 112 512 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 28 +PIN 160 -512 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 29 +PIN -256 -448 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 30 +PIN 256 -256 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 31 +PIN -160 -512 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 32 +PIN 256 -384 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 33 +PIN 256 -320 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN 256 -448 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 35 diff --git a/spice/copy/sym/PowerProducts/LTC1709.asy b/spice/copy/sym/PowerProducts/LTC1709.asy new file mode 100755 index 0000000..ac4fc1e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1709.asy @@ -0,0 +1,113 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -512 256 512 +TEXT 0 -96 Center 2 LT +WINDOW 0 0 -352 Center 2 +WINDOW 3 8 192 Center 2 +SYMATTR Value LTC1709 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1709.sub +SYMATTR Value2 LTC1709 +SYMATTR Description 2-Phase, 5-Bit Adjustable, High Efficiency, Synchronous Step-Down Switching Regulator +PIN -256 -256 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -192 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 -64 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -320 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -384 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 -192 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 512 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 128 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN 256 448 RIGHT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN 256 384 RIGHT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 256 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 0 LEFT 8 +PINATTR PinName AttenOut +PINATTR SpiceOrder 15 +PIN -256 64 LEFT 8 +PINATTR PinName AttenIn +PINATTR SpiceOrder 16 +PIN -256 192 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 17 +PIN -256 256 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 18 +PIN -256 320 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 19 +PIN -256 384 LEFT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 20 +PIN -256 448 LEFT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 21 +PIN 0 -512 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 22 +PIN -256 -128 LEFT 8 +PINATTR PinName AmpMode +PINATTR SpiceOrder 23 +PIN 256 0 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 24 +PIN 256 128 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 25 +PIN 256 64 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 26 +PIN 256 192 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 27 +PIN 112 512 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 28 +PIN 160 -512 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 29 +PIN -256 -448 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 30 +PIN 256 -256 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 31 +PIN -160 -512 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 32 +PIN 256 -384 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 33 +PIN 256 -320 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN 256 -448 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 35 diff --git a/spice/copy/sym/PowerProducts/LTC1733.asy b/spice/copy/sym/PowerProducts/LTC1733.asy new file mode 100755 index 0000000..d9fa1bb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1733.asy @@ -0,0 +1,39 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 96 Center 2 +WINDOW 38 0 48 Center 2 +SYMATTR Value TimeOut=10 +SYMATTR SpiceModel LTC1733 +SYMATTR Prefix X +SYMATTR Description Monolithic Linear Lithion-Ion Battery Charger with Thermal Regulation Themal Current Limit is NOT MODELED +SYMATTR ModelFile LTC1733.sub +PIN -144 -48 LEFT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 1 +PIN 0 -208 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN 144 -48 RIGHT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 48 LEFT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 6 +PIN 144 144 RIGHT 8 +PINATTR PinName PROG +PINATTR SpiceOrder 7 +PIN -144 -144 LEFT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN 144 -144 RIGHT 8 +PINATTR PinName _ACPR +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC1734-4.1.asy b/spice/copy/sym/PowerProducts/LTC1734-4.1.asy new file mode 100755 index 0000000..88bf795 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1734-4.1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1734-4.1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1734-x.x.sub +SYMATTR Value2 LTC1734-x.x Ref=4.1 +SYMATTR Description Lithium-Ion Linear Battery Charger in ThinSOT +PIN 144 -96 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Prog +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1734-4.2.asy b/spice/copy/sym/PowerProducts/LTC1734-4.2.asy new file mode 100755 index 0000000..bc145e2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1734-4.2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1734-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1734-x.x.sub +SYMATTR Value2 LTC1734-x.x Ref=4.2 +SYMATTR Description Lithium-Ion Linear Battery Charger in ThinSOT +PIN 144 -96 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Prog +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1734L-4.1.asy b/spice/copy/sym/PowerProducts/LTC1734L-4.1.asy new file mode 100755 index 0000000..67dc063 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1734L-4.1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 73 Center 2 +SYMATTR Value LTC1734L-4.1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1734L-x.x.sub +SYMATTR Value2 LTC1734L-x.x Ref=4.1 +SYMATTR Description Lithium-Ion Linear Battery Charger in ThinSOT +PIN 144 -96 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Prog +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1734L-4.2.asy b/spice/copy/sym/PowerProducts/LTC1734L-4.2.asy new file mode 100755 index 0000000..c34d4e4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1734L-4.2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -71 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1734L-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1734L-x.x.sub +SYMATTR Value2 LTC1734L-x.x Ref=4.2 +SYMATTR Description Lithium-Ion Linear Battery Charger in ThinSOT +PIN 144 -96 RIGHT 8 +PINATTR PinName Isense +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName Prog +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1735-1.asy b/spice/copy/sym/PowerProducts/LTC1735-1.asy new file mode 100755 index 0000000..0795f70 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1735-1.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -272 224 336 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1735-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1735-1.sub +SYMATTR Value2 LTC1735-1 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator +PIN -224 192 LEFT 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 1 +PIN -224 -64 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN -224 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN -224 -192 LEFT 8 +PINATTR PinName PGOOD +PINATTR SpiceOrder 4 +PIN 224 208 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 5 +PIN 224 144 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 6 +PIN 224 272 RIGHT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 7 +PIN -112 336 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN 0 -272 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 9 +PIN 112 336 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 224 64 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 11 +PIN 144 -272 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 12 +PIN -144 -272 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 224 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 224 -192 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 15 +PIN 224 -128 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1735.asy b/spice/copy/sym/PowerProducts/LTC1735.asy new file mode 100755 index 0000000..1df0f3d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1735.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -272 224 336 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1735 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1735.sub +SYMATTR Value2 LTC1735 +SYMATTR Description High Efficiency Synchronous Step-Down Switching Regulator +PIN -224 192 LEFT 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 1 +PIN -224 -64 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN -224 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN -224 -192 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -112 336 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 5 +PIN 224 272 RIGHT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 6 +PIN 224 208 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 224 144 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN 0 -272 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 9 +PIN 112 336 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 224 64 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 11 +PIN 144 -272 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 12 +PIN -144 -272 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 224 -32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 224 -192 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 15 +PIN 224 -128 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1736.asy b/spice/copy/sym/PowerProducts/LTC1736.asy new file mode 100755 index 0000000..43f4058 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1736.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -256 256 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -160 Center 2 +WINDOW 3 0 160 Center 2 +SYMATTR Value LTC1736 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1736.sub +SYMATTR Value2 LTC1736 +SYMATTR Description 5-Bit Adjustable High Efficiency Synchronous Step-Down Switching Regulator +PIN -256 -192 LEFT 8 +PINATTR PinName Cosc +PINATTR SpiceOrder 1 +PIN -256 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN -256 -64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN -256 288 LEFT 8 +PINATTR PinName SGND +PINATTR SpiceOrder 5 +PIN -256 0 LEFT 8 +PINATTR PinName PGOOD +PINATTR SpiceOrder 6 +PIN 0 352 BOTTOM 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 7 +PIN 160 352 BOTTOM 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN -256 224 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -160 352 BOTTOM 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 10 +PIN -256 160 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 11 +PIN -256 128 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 12 +PIN -256 96 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 13 +PIN -256 64 LEFT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 14 +PIN -256 32 LEFT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 15 +PIN 256 32 RIGHT 8 +PINATTR PinName VIDVcc +PINATTR SpiceOrder 16 +PIN 256 288 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 18 +PIN 256 224 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 19 +PIN 256 96 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 +PIN 256 -224 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 +PIN 256 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 22 +PIN 256 -32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 23 +PIN 256 -160 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LTC1751-3.3.asy b/spice/copy/sym/PowerProducts/LTC1751-3.3.asy new file mode 100755 index 0000000..d6ee1c9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1751-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 144 +TEXT 0 -9 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1751-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1751-3.3.sub +SYMATTR Value2 LTC1751-3.3 +SYMATTR Description µPower, Regulated Charge Pump DC/DC Converter, Fixed 3.3V Output +PIN 128 -48 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 1 +PIN 128 -128 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -128 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 112 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 32 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1751-5.asy b/spice/copy/sym/PowerProducts/LTC1751-5.asy new file mode 100755 index 0000000..ebc6ba3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1751-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 144 +TEXT 0 -9 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1751-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1751-5.sub +SYMATTR Value2 LTC1751-5 +SYMATTR Description µPower, Regulated Charge Pump DC/DC Converter, Fixed 5V Output +PIN 128 -48 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 1 +PIN 128 -128 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -128 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 112 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 32 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1751.asy b/spice/copy/sym/PowerProducts/LTC1751.asy new file mode 100755 index 0000000..46553db --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1751.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 144 +TEXT 0 -9 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC1751 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1751.sub +SYMATTR Value2 LTC1751 +SYMATTR Description µPower, Regulated Charge Pump DC/DC Converter +PIN 128 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 128 -128 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -128 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -128 112 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 112 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -128 32 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1753.asy b/spice/copy/sym/PowerProducts/LTC1753.asy new file mode 100755 index 0000000..ea25791 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1753.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -320 192 320 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTC1753 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1753.sub +SYMATTR Value2 LTC1753 +SYMATTR Description 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor +PIN 192 0 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 1 +PIN 80 -320 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 2 +PIN 80 320 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 3 +PIN -80 320 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN -80 -320 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN 192 160 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 +PIN 192 -240 RIGHT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 7 +PIN 192 -80 RIGHT 8 +PINATTR PinName Ifb +PINATTR SpiceOrder 8 +PIN -192 256 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 9 +PIN 192 240 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 10 +PIN 192 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN -192 -192 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 12 +PIN -192 -256 LEFT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 13 +PIN -192 -128 LEFT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 14 +PIN -192 -64 LEFT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 15 +PIN -192 0 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 16 +PIN -192 64 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 17 +PIN -192 128 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 18 +PIN -192 192 LEFT 8 +PINATTR PinName OUTEN +PINATTR SpiceOrder 19 +PIN 192 -160 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC1754-3.3.asy b/spice/copy/sym/PowerProducts/LTC1754-3.3.asy new file mode 100755 index 0000000..0d9fe91 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1754-3.3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1754-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1754-3.3.sub +SYMATTR Value2 LTC1754-3.3 +SYMATTR Description µPower, Regulated 3.3V Charge Pump with Shutdown in SOT-23 +PIN -128 -64 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1754-5.asy b/spice/copy/sym/PowerProducts/LTC1754-5.asy new file mode 100755 index 0000000..1c3fea4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1754-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1754-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1754-5.sub +SYMATTR Value2 LTC1754-5 +SYMATTR Description µPower, Regulated 5V Charge Pump with Shutdown in SOT-23 +PIN -128 -64 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1771.asy b/spice/copy/sym/PowerProducts/LTC1771.asy new file mode 100755 index 0000000..7d8ba1d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1771.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 0 57 Center 2 +SYMATTR Value LTC1771 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1771.sub +SYMATTR Value2 LTC1771 +SYMATTR Description 10µA Quiescent Current High Efficiency Step-Down DC/DC Controller +PIN -144 80 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 2 +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 0 RIGHT 8 +PINATTR PinName Pgate +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 144 -80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 7 +PIN -144 -80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1772.asy b/spice/copy/sym/PowerProducts/LTC1772.asy new file mode 100755 index 0000000..1ceb9d1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1772.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1772 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1772.sub +SYMATTR Value2 LTC1772 +SYMATTR Description Constant Frequency Current Mode Step-Down DC/DC Controller in SOT-23 +PIN -176 0 LEFT 8 +PINATTR PinName Ith/Run +PINATTR SpiceOrder 1 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 176 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 176 -80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 176 0 RIGHT 8 +PINATTR PinName Pgate +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1772B.asy b/spice/copy/sym/PowerProducts/LTC1772B.asy new file mode 100755 index 0000000..69fa022 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1772B.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -160 176 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1772B +SYMATTR Prefix X +SYMATTR SpiceModel LTC1772B.sub +SYMATTR Value2 LTC1772B +SYMATTR Description Constant Frequency Current Mode Step-Down DC/DC Controller in SOT-23 +PIN -176 0 LEFT 8 +PINATTR PinName Ith/Run +PINATTR SpiceOrder 1 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 176 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 176 -80 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 176 0 RIGHT 8 +PINATTR PinName Pgate +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1773.asy b/spice/copy/sym/PowerProducts/LTC1773.asy new file mode 100755 index 0000000..df84ac3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1773.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1773 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1773.sub +SYMATTR Value2 LTC1773 +SYMATTR Description Synchronous Step-Down Regulator Controller +PIN -160 32 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 1 +PIN -160 -32 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN -160 -96 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 3 +PIN -160 96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 160 96 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 160 -96 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 9 +PIN 160 32 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC1775.asy b/spice/copy/sym/PowerProducts/LTC1775.asy new file mode 100755 index 0000000..42a6d04 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1775.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -384 240 384 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -256 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC1775 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1775.sub +SYMATTR Value2 LTC1775 +SYMATTR Description High Power No Rsense(TM) Current Mode Synchronous Step-Down Switching Regulator +PIN -240 -320 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 1 +PIN -240 -192 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 3 +PIN -240 -64 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -240 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 5 +PIN -112 384 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN -240 320 LEFT 8 +PINATTR PinName Vosense +PINATTR SpiceOrder 7 +PIN -240 192 LEFT 8 +PINATTR PinName Vprog +PINATTR SpiceOrder 8 +PIN 112 384 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 9 +PIN 240 320 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 10 +PIN 240 192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 11 +PIN 240 64 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 12 +PIN 240 -192 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 13 +PIN 240 -64 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 240 -320 RIGHT 8 +PINATTR PinName TK +PINATTR SpiceOrder 15 +PIN 0 -384 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1778-1.asy b/spice/copy/sym/PowerProducts/LTC1778-1.asy new file mode 100755 index 0000000..f956b28 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1778-1.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -136 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LTC1778-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1778-1.sub +SYMATTR Value2 LTC1778-1 +SYMATTR Description Wide Operating Range, No Rsense(TM) Step-Down Controller +PIN -176 -32 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN -176 160 LEFT 8 +PINATTR PinName Von +PINATTR SpiceOrder 2 +PIN -176 32 LEFT 8 +PINATTR PinName Vrng +PINATTR SpiceOrder 3 +PIN -176 -96 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -176 96 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 5 +PIN -80 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -80 -224 TOP 8 +PINATTR PinName Ion +PINATTR SpiceOrder 7 +PIN 176 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -176 -160 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 9 +PIN 80 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 176 32 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 11 +PIN 176 96 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 12 +PIN 80 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 13 +PIN 176 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 176 -160 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 15 +PIN 176 -32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1778.asy b/spice/copy/sym/PowerProducts/LTC1778.asy new file mode 100755 index 0000000..8d48ce5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1778.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 224 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -128 Center 2 +WINDOW 3 0 88 Center 2 +SYMATTR Value LTC1778 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1778.sub +SYMATTR Value2 LTC1778 +SYMATTR Description Wide Operating Range, No Rsense(TM) Step-Down Controller +PIN -176 -32 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN -176 160 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 2 +PIN -176 32 LEFT 8 +PINATTR PinName Vrng +PINATTR SpiceOrder 3 +PIN -176 -96 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -176 96 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 5 +PIN -80 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -80 -224 TOP 8 +PINATTR PinName Ion +PINATTR SpiceOrder 7 +PIN 176 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -176 -160 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 9 +PIN 80 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 176 32 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 11 +PIN 176 96 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 12 +PIN 80 224 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 13 +PIN 176 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 14 +PIN 176 -160 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 15 +PIN 176 -32 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1779.asy b/spice/copy/sym/PowerProducts/LTC1779.asy new file mode 100755 index 0000000..d4e8184 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1779.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 65 Center 2 +SYMATTR Value LTC1779 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1779.sub +SYMATTR Value2 LTC1779 +SYMATTR Description 250mA Current Mode Step-Down DC/DC Controller in SOT-23 +PIN -144 -48 LEFT 8 +PINATTR PinName Ith/Run +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1798.asy b/spice/copy/sym/PowerProducts/LTC1798.asy new file mode 100755 index 0000000..7d4baea --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1798.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -96 112 96 +TEXT 0 -32 Center 2 LT +WINDOW 0 26 -107 Left 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LTC1798 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1798.lib +SYMATTR Value2 LTC1798 +SYMATTR Description µPower Low Dropout Reference +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 0 -96 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 112 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 112 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LTC1844-1.5.asy b/spice/copy/sym/PowerProducts/LTC1844-1.5.asy new file mode 100755 index 0000000..6a1e863 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1844-1.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1844-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1844.lib +SYMATTR Value2 LTC1844-1.5 +SYMATTR Description 150mA, µPower, Low Noise, VLDO Linear Regulator +PIN -144 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LTC1844-1.8.asy b/spice/copy/sym/PowerProducts/LTC1844-1.8.asy new file mode 100755 index 0000000..37efb2d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1844-1.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1844-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1844.lib +SYMATTR Value2 LTC1844-1.8 +SYMATTR Description 150mA, µPower, Low Noise, VLDO Linear Regulator +PIN -144 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LTC1844-2.5.asy b/spice/copy/sym/PowerProducts/LTC1844-2.5.asy new file mode 100755 index 0000000..25d7629 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1844-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1844-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1844.lib +SYMATTR Value2 LTC1844-2.5 +SYMATTR Description 150mA, µPower, Low Noise, VLDO Linear Regulator +PIN -144 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LTC1844-2.8.asy b/spice/copy/sym/PowerProducts/LTC1844-2.8.asy new file mode 100755 index 0000000..4bdbef0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1844-2.8.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1844-2.8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1844.lib +SYMATTR Value2 LTC1844-2.8 +SYMATTR Description 150mA, µPower, Low Noise, VLDO Linear Regulator +PIN -144 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LTC1844-3.3.asy b/spice/copy/sym/PowerProducts/LTC1844-3.3.asy new file mode 100755 index 0000000..4cc6d3e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1844-3.3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1844-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1844.lib +SYMATTR Value2 LTC1844-3.3 +SYMATTR Description 150mA, µPower, Low Noise, VLDO Linear Regulator +PIN -144 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/PowerProducts/LTC1844-SD.asy b/spice/copy/sym/PowerProducts/LTC1844-SD.asy new file mode 100755 index 0000000..46b6782 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1844-SD.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -41 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1844-SD +SYMATTR Prefix X +SYMATTR SpiceModel LTC1844.lib +SYMATTR Value2 LTC1844-SD +SYMATTR Description 150mA, µPower, Low Noise, VLDO Linear Regulator +PIN -144 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LTC1871-1.asy b/spice/copy/sym/PowerProducts/LTC1871-1.asy new file mode 100755 index 0000000..9a39c18 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1871-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1871-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1871-1.sub +SYMATTR Value2 LTC1871-1 +SYMATTR Description Wide Input Range, No Rsense(TM) Current Mode Boost, Flyback and SEPIC Controller +PIN 160 -144 RIGHT 8 +PINATTR PinName Run +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 2 +PIN 160 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 144 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 5 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 160 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC1871-7.asy b/spice/copy/sym/PowerProducts/LTC1871-7.asy new file mode 100755 index 0000000..e44f67e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1871-7.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1871-7 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1871-7.sub +SYMATTR Value2 LTC1871-7 +SYMATTR Description High Input Voltage, Current Mode Boost, Flyback and SEPIC Controller +PIN 160 -144 RIGHT 8 +PINATTR PinName Run +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 2 +PIN 160 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 144 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 5 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 160 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC1871.asy b/spice/copy/sym/PowerProducts/LTC1871.asy new file mode 100755 index 0000000..d0aad06 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1871.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1871 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1871.sub +SYMATTR Value2 LTC1871 +SYMATTR Description Wide Input Range, No Rsense(TM) Current Mode Boost, Flyback and SEPIC Controller +PIN 160 -144 RIGHT 8 +PINATTR PinName Run +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 2 +PIN 160 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN -160 144 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 5 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 7 +PIN -160 -144 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN 160 -48 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC1872.asy b/spice/copy/sym/PowerProducts/LTC1872.asy new file mode 100755 index 0000000..3f590df --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1872.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1872 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1872.sub +SYMATTR Value2 LTC1872 +SYMATTR Description Constant Frequency Current Mode Step-Up DC/DC Controller in SOT-23 +PIN -144 -48 LEFT 8 +PINATTR PinName Ith/Run +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Ngate +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1872B.asy b/spice/copy/sym/PowerProducts/LTC1872B.asy new file mode 100755 index 0000000..19d7ca2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1872B.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1872B +SYMATTR Prefix X +SYMATTR SpiceModel LTC1872B.sub +SYMATTR Value2 LTC1872B +SYMATTR Description Constant Frequency Current Mode Step-Up DC/DC Controller in SOT-23 +PIN -144 -48 LEFT 8 +PINATTR PinName Ith/Run +PINATTR SpiceOrder 1 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Ngate +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1873.asy b/spice/copy/sym/PowerProducts/LTC1873.asy new file mode 100755 index 0000000..3d79aed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1873.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -368 288 368 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -256 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1873 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1873.sub +SYMATTR Value2 LTC1873 +SYMATTR Description Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID +PIN 64 -368 TOP 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 1 +PIN -208 -368 TOP 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 2 +PIN -288 -160 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 3 +PIN -288 -288 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 4 +PIN -288 -224 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 5 +PIN -288 -96 LEFT 8 +PINATTR PinName Imax1 +PINATTR SpiceOrder 6 +PIN 288 96 RIGHT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 7 +PIN -208 368 BOTTOM 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 8 +PIN -288 -32 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 9 +PIN -64 368 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 10 +PIN -288 32 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 11 +PIN -288 96 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 12 +PIN -288 160 LEFT 8 +PINATTR PinName VID0 +PINATTR SpiceOrder 13 +PIN -288 224 LEFT 8 +PINATTR PinName VID1 +PINATTR SpiceOrder 14 +PIN -288 288 LEFT 8 +PINATTR PinName VID2 +PINATTR SpiceOrder 15 +PIN 288 288 RIGHT 8 +PINATTR PinName VID3 +PINATTR SpiceOrder 16 +PIN 288 224 RIGHT 8 +PINATTR PinName VID4 +PINATTR SpiceOrder 17 +PIN -64 -368 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 18 +PIN 288 32 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 19 +PIN 288 -32 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 20 +PIN 208 368 BOTTOM 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 21 +PIN 288 160 RIGHT 8 +PINATTR PinName Fault +PINATTR SpiceOrder 22 +PIN 64 368 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 23 +PIN 288 -224 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 24 +PIN 288 -288 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 25 +PIN 288 -160 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 26 +PIN 208 -368 TOP 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 27 +PIN 288 -96 RIGHT 8 +PINATTR PinName Imax2 +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC1874.asy b/spice/copy/sym/PowerProducts/LTC1874.asy new file mode 100755 index 0000000..84c676d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1874.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -272 -224 272 224 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -168 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1874 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1874.sub +SYMATTR Value2 LTC1874 +SYMATTR Description Dual Constant Frequency Current Mode Step-Down DC/DC Controller +PIN -64 -224 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 1 +PIN -272 -144 LEFT 8 +PINATTR PinName Sense-1 +PINATTR SpiceOrder 2 +PIN -64 224 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 3 +PIN -272 48 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN 272 144 RIGHT 8 +PINATTR PinName Ith/Run2 +PINATTR SpiceOrder 5 +PIN 192 224 BOTTOM 8 +PINATTR PinName PGND2 +PINATTR SpiceOrder 6 +PIN 272 -48 RIGHT 8 +PINATTR PinName Pgate2 +PINATTR SpiceOrder 7 +PIN 192 -224 TOP 8 +PINATTR PinName PVin2 +PINATTR SpiceOrder 8 +PIN 64 -224 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 9 +PIN 272 -144 RIGHT 8 +PINATTR PinName Sense-2 +PINATTR SpiceOrder 10 +PIN 64 224 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 11 +PIN 272 48 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 12 +PIN -272 144 LEFT 8 +PINATTR PinName Ith/Run1 +PINATTR SpiceOrder 13 +PIN -192 224 BOTTOM 8 +PINATTR PinName PGND1 +PINATTR SpiceOrder 14 +PIN -272 -48 LEFT 8 +PINATTR PinName Pgate1 +PINATTR SpiceOrder 15 +PIN -192 -224 TOP 8 +PINATTR PinName PVin1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1875.asy b/spice/copy/sym/PowerProducts/LTC1875.asy new file mode 100755 index 0000000..2b9b2a0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1875.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1875 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1875.sub +SYMATTR Value2 LTC1875 +SYMATTR Description 1.5A Synchronous Step-Down Regulator with 15µA Quiescent Current +PIN -64 160 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 1 +PIN -160 -32 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN 160 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 160 96 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 4 +PIN 160 -96 RIGHT 8 +PINATTR PinName SWP +PINATTR SpiceOrder 5 +PIN 160 -32 RIGHT 8 +PINATTR PinName SWN +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 64 -160 TOP 8 +PINATTR PinName PVin +PINATTR SpiceOrder 8 +PIN -64 -160 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 13 +PIN -160 -96 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 14 +PIN -160 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 15 +PIN -160 96 LEFT 8 +PINATTR PinName PLL_LPF +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1877.asy b/spice/copy/sym/PowerProducts/LTC1877.asy new file mode 100755 index 0000000..da7e9d5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1877.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1877 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1877.sub +SYMATTR Value2 LTC1877 +SYMATTR Description High Efficiency Monolithic Synchronous Step-Down Regulator\n\nNote: External sync. capability is not modeled. +PIN -144 80 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 -80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LTC1878.asy b/spice/copy/sym/PowerProducts/LTC1878.asy new file mode 100755 index 0000000..f857a1d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1878.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1878 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1878.sub +SYMATTR Value2 LTC1878 +SYMATTR Description High Efficiency Monolithic Synchronous Step-Down Regulator\n\nNote: External sync. capability is not modeled. +PIN -144 80 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 -80 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LTC1879.asy b/spice/copy/sym/PowerProducts/LTC1879.asy new file mode 100755 index 0000000..5f37968 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1879.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -160 160 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -72 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1879 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1879.sub +SYMATTR Value2 LTC1879 +SYMATTR Description 1.2A Synchronous Step-Down Regulator with 15µA Quiescent Current +PIN -64 160 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 1 +PIN -160 -32 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN 160 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 160 96 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 4 +PIN 160 -96 RIGHT 8 +PINATTR PinName SWP +PINATTR SpiceOrder 5 +PIN 160 -32 RIGHT 8 +PINATTR PinName SWN +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 7 +PIN 64 -160 TOP 8 +PINATTR PinName PVin +PINATTR SpiceOrder 8 +PIN -64 -160 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 13 +PIN -160 -96 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 14 +PIN -160 32 LEFT 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 15 +PIN -160 96 LEFT 8 +PINATTR PinName PLL_LPF +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC1911-1.5.asy b/spice/copy/sym/PowerProducts/LTC1911-1.5.asy new file mode 100755 index 0000000..066a015 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1911-1.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1911-1.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1911-1.5.sub +SYMATTR Value2 LTC1911-1.5 +SYMATTR Description Low Noise, High Efficiency Inductorless Step-Down DC/DC Converter, Fixed 1.5V Output +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 5 +PIN 144 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 144 48 RIGHT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1911-1.8.asy b/spice/copy/sym/PowerProducts/LTC1911-1.8.asy new file mode 100755 index 0000000..c343720 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1911-1.8.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -176 144 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1911-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1911-1.8.sub +SYMATTR Value2 LTC1911-1.8 +SYMATTR Description Low Noise, High Efficiency Inductorless Step-Down DC/DC Converter, Fixed 1.8V Output +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName C2+ +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName C2- +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName C1- +PINATTR SpiceOrder 5 +PIN 144 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 144 48 RIGHT 8 +PINATTR PinName C1+ +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC1922-1.asy b/spice/copy/sym/PowerProducts/LTC1922-1.asy new file mode 100755 index 0000000..43f38fa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1922-1.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -288 192 288 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1922-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1922-1.sub +SYMATTR Value2 LTC1922-1 +SYMATTR Description Synchronous Phase Modulated Full-Bridge Controller +PIN 192 -32 RIGHT 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 2 +PIN 192 -96 RIGHT 8 +PINATTR PinName CS +PINATTR SpiceOrder 3 +PIN -192 160 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 4 +PIN -192 32 LEFT 8 +PINATTR PinName RLEB +PINATTR SpiceOrder 5 +PIN -192 224 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -112 288 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -192 -224 LEFT 8 +PINATTR PinName PDLY +PINATTR SpiceOrder 8 +PIN -192 -96 LEFT 8 +PINATTR PinName SBUS +PINATTR SpiceOrder 9 +PIN -192 -160 LEFT 8 +PINATTR PinName ADLY +PINATTR SpiceOrder 10 +PIN -192 -32 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 11 +PIN 192 224 RIGHT 8 +PINATTR PinName _OutF +PINATTR SpiceOrder 12 +PIN 192 160 RIGHT 8 +PINATTR PinName _OutE +PINATTR SpiceOrder 13 +PIN 192 32 RIGHT 8 +PINATTR PinName OutD +PINATTR SpiceOrder 14 +PIN 0 -288 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN 192 96 RIGHT 8 +PINATTR PinName OutC +PINATTR SpiceOrder 16 +PIN 192 -160 RIGHT 8 +PINATTR PinName OutB +PINATTR SpiceOrder 17 +PIN 192 -224 RIGHT 8 +PINATTR PinName OutA +PINATTR SpiceOrder 18 +PIN 112 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 19 +PIN 0 288 BOTTOM 8 +PINATTR PinName Ct +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC1928-5.asy b/spice/copy/sym/PowerProducts/LTC1928-5.asy new file mode 100755 index 0000000..9632f24 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1928-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -127 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC1928-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1928-5.sub +SYMATTR Value2 LTC1928-5 +SYMATTR Description Doubler Charge Pump with Low Noise Linear Regulator in ThinSOT +PIN -128 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 128 80 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 128 -80 RIGHT 8 +PINATTR PinName CPO +PINATTR SpiceOrder 4 +PIN -128 0 LEFT 8 +PINATTR PinName CP +PINATTR SpiceOrder 5 +PIN -128 80 LEFT 8 +PINATTR PinName _CN/SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1929-PG.asy b/spice/copy/sym/PowerProducts/LTC1929-PG.asy new file mode 100755 index 0000000..7c97a85 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1929-PG.asy @@ -0,0 +1,89 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -448 256 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -216 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LTC1929-PG +SYMATTR Prefix X +SYMATTR SpiceModel LTC1929-PG.sub +SYMATTR Value2 LTC1929-PG +SYMATTR Description 2-Phase, High Efficiency, Synchronous Step-Down Switching Regulator +PIN -256 -64 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -64 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 256 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -192 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -256 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 192 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN -256 320 LEFT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN -256 384 LEFT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 384 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 -384 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 15 +PIN 256 64 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 16 +PIN 256 192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 256 128 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 18 +PIN 256 256 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 112 448 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 +PIN 160 -448 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 0 -448 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 22 +PIN 256 -192 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -160 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN 256 -320 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 25 +PIN 256 -256 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 26 +PIN 256 -384 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 27 diff --git a/spice/copy/sym/PowerProducts/LTC1929.asy b/spice/copy/sym/PowerProducts/LTC1929.asy new file mode 100755 index 0000000..bd5b985 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1929.asy @@ -0,0 +1,89 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -448 256 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -216 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTC1929 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1929.sub +SYMATTR Value2 LTC1929 +SYMATTR Description 2-Phase, High Efficiency, Synchronous Step-Down Switching Regulator +PIN -256 -64 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 1 +PIN 256 -128 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 2 +PIN 256 -64 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 3 +PIN -256 256 LEFT 8 +PINATTR PinName EAIN +PINATTR SpiceOrder 4 +PIN -256 -192 LEFT 8 +PINATTR PinName PLLFLT +PINATTR SpiceOrder 5 +PIN -256 -256 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 6 +PIN -256 64 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 8 +PIN -112 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -256 192 LEFT 8 +PINATTR PinName DiffOut +PINATTR SpiceOrder 10 +PIN -256 320 LEFT 8 +PINATTR PinName OS- +PINATTR SpiceOrder 11 +PIN -256 384 LEFT 8 +PINATTR PinName OS+ +PINATTR SpiceOrder 12 +PIN 256 384 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 256 320 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 14 +PIN -256 128 LEFT 8 +PINATTR PinName AmpMode +PINATTR SpiceOrder 15 +PIN 256 64 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 16 +PIN 256 192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 256 128 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 18 +PIN 256 256 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 19 +PIN 112 448 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 +PIN 160 -448 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 0 -448 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 22 +PIN 256 -192 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -160 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN 256 -320 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 25 +PIN 256 -256 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 26 +PIN 256 -384 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 27 diff --git a/spice/copy/sym/PowerProducts/LTC1981.asy b/spice/copy/sym/PowerProducts/LTC1981.asy new file mode 100755 index 0000000..8200c97 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1981.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC1981 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1981.sub +SYMATTR Value2 LTC1981 +SYMATTR Description Singlel µPower High Side Swtich Controllers in SOT-23 +PIN -112 -80 LEFT 8 +PINATTR PinName GDR +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 4 +PIN 112 -80 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LTC1982.asy b/spice/copy/sym/PowerProducts/LTC1982.asy new file mode 100755 index 0000000..4d6e5c8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1982.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -128 112 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC1982 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1982.sub +SYMATTR Value2 LTC1982 +SYMATTR Description Dual µPower High Side Swtich Controllers in SOT-23 +PIN -112 -96 LEFT 8 +PINATTR PinName _SHDN1 +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 96 LEFT 8 +PINATTR PinName _SHDN2 +PINATTR SpiceOrder 3 +PIN 112 96 RIGHT 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 5 +PIN 112 -96 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1983-3.asy b/spice/copy/sym/PowerProducts/LTC1983-3.asy new file mode 100755 index 0000000..37d810d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1983-3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1983-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1983-3.sub +SYMATTR Value2 LTC1983-3 +SYMATTR Description 100mA Regulated Charge-Pump Inverters in ThinSOT +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName C- +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 -80 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1983-5.asy b/spice/copy/sym/PowerProducts/LTC1983-5.asy new file mode 100755 index 0000000..d46fe8a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1983-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC1983-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1983-5.sub +SYMATTR Value2 LTC1983-5 +SYMATTR Description 100mA Regulated Charge-Pump Inverters in ThinSOT +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName C- +PINATTR SpiceOrder 4 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 -80 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC1986.asy b/spice/copy/sym/PowerProducts/LTC1986.asy new file mode 100755 index 0000000..d178425 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC1986.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1986 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1986.sub +SYMATTR Value2 LTC1986 +SYMATTR Description 3V/5V SIM Power Supply in SOT-23 +PIN -128 -64 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 64 LEFT 8 +PINATTR PinName MODE +PINATTR SpiceOrder 3 +PIN 128 64 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 5 +PIN 128 -64 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC2900-1.asy b/spice/copy/sym/PowerProducts/LTC2900-1.asy new file mode 100755 index 0000000..ffb8448 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2900-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 208 -128 -208 +TEXT 0 0 Center 2 LT +WINDOW 3 0 121 Center 2 +WINDOW 0 0 -120 Center 2 +SYMATTR Value LTC2900-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2900-1.sub +SYMATTR Description Programmable Quad Supply Monitor with Adjustable Reset Timer +SYMATTR Value2 LTC2900-1 +PIN -128 0 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 1 +PIN -128 -160 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 2 +PIN 128 80 RIGHT 8 +PINATTR PinName CRT +PINATTR SpiceOrder 3 +PIN 128 -160 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 4 +PIN -128 160 LEFT 8 +PINATTR PinName _PBR +PINATTR SpiceOrder 5 +PIN 128 160 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 0 RIGHT 8 +PINATTR PinName VPG +PINATTR SpiceOrder 7 +PIN 128 -80 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 +PIN -128 80 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 9 +PIN -128 -80 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC2900-2.asy b/spice/copy/sym/PowerProducts/LTC2900-2.asy new file mode 100755 index 0000000..f051151 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2900-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 208 -128 -208 +TEXT 0 0 Center 2 LT +WINDOW 3 0 119 Center 2 +WINDOW 0 0 -119 Center 2 +SYMATTR Value LTC2900-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2900-2.sub +SYMATTR Description Programmable Quad Supply Monitor with Adjustable Reset Timer +SYMATTR Value2 LTC2900-2 +PIN -128 0 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 1 +PIN -128 -160 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 2 +PIN 128 80 RIGHT 8 +PINATTR PinName CRT +PINATTR SpiceOrder 3 +PIN 128 -160 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 4 +PIN -128 160 LEFT 8 +PINATTR PinName _PBR +PINATTR SpiceOrder 5 +PIN 128 160 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 0 RIGHT 8 +PINATTR PinName VPG +PINATTR SpiceOrder 7 +PIN 128 -80 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 +PIN -128 80 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 9 +PIN -128 -80 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC2902-1.asy b/spice/copy/sym/PowerProducts/LTC2902-1.asy new file mode 100755 index 0000000..ebcff85 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2902-1.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 192 -160 -176 +TEXT -3 -88 Center 2 LT +WINDOW 3 -3 -24 Center 2 +WINDOW 0 -3 -152 Center 2 +SYMATTR Value LTC2902-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2902-1.sub +SYMATTR Description Programmable Quad Supply Monitor with Adjustable Reset Timer and Supply Tolerance +SYMATTR Value2 LTC2902-1 +PIN 176 -48 RIGHT 8 +PINATTR PinName COMP3 +PINATTR SpiceOrder 1 +PIN 176 -144 RIGHT 8 +PINATTR PinName COMP1 +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 3 +PIN -160 -144 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 4 +PIN 64 192 BOTTOM 8 +PINATTR PinName CRT +PINATTR SpiceOrder 5 +PIN 176 48 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN -160 96 LEFT 8 +PINATTR PinName T0 +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName _RDIS +PINATTR SpiceOrder 8 +PIN -160 144 LEFT 8 +PINATTR PinName T1 +PINATTR SpiceOrder 9 +PIN -48 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 176 144 RIGHT 8 +PINATTR PinName VPG +PINATTR SpiceOrder 11 +PIN 176 96 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 12 +PIN -160 0 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 13 +PIN -160 -96 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 14 +PIN 176 0 RIGHT 8 +PINATTR PinName COMP4 +PINATTR SpiceOrder 15 +PIN 176 -96 RIGHT 8 +PINATTR PinName COMP2 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC2902-2.asy b/spice/copy/sym/PowerProducts/LTC2902-2.asy new file mode 100755 index 0000000..a259165 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2902-2.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 192 -160 -176 +TEXT -3 -88 Center 2 LT +WINDOW 3 -3 -24 Center 2 +WINDOW 0 -3 -152 Center 2 +SYMATTR Value LTC2902-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2902-2.sub +SYMATTR Description Programmable Quad Supply Monitor with Adjustable Reset Timer and Supply Tolerance +SYMATTR Value2 LTC2902-2 +PIN 176 -48 RIGHT 8 +PINATTR PinName COMP3 +PINATTR SpiceOrder 1 +PIN 176 -144 RIGHT 8 +PINATTR PinName COMP1 +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 3 +PIN -160 -144 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 4 +PIN 64 192 BOTTOM 8 +PINATTR PinName CRT +PINATTR SpiceOrder 5 +PIN 176 48 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN -160 96 LEFT 8 +PINATTR PinName T0 +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName _RDIS +PINATTR SpiceOrder 8 +PIN -160 144 LEFT 8 +PINATTR PinName T1 +PINATTR SpiceOrder 9 +PIN -48 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 176 144 RIGHT 8 +PINATTR PinName VPG +PINATTR SpiceOrder 11 +PIN 176 96 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 12 +PIN -160 0 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 13 +PIN -160 -96 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 14 +PIN 176 0 RIGHT 8 +PINATTR PinName COMP4 +PINATTR SpiceOrder 15 +PIN 176 -96 RIGHT 8 +PINATTR PinName COMP2 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC2903-A1.asy b/spice/copy/sym/PowerProducts/LTC2903-A1.asy new file mode 100755 index 0000000..a568e7a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2903-A1.asy @@ -0,0 +1,30 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 112 -96 -96 +ARC Normal -9 -106 8 -89 -3 -97 27 -93 +TEXT 0 -40 Center 2 LT +WINDOW 3 0 40 Center 2 +WINDOW 0 0 -96 Bottom 2 +SYMATTR Value LTC2903-A1 +SYMATTR Prefix X +SYMATTR Description Precision Quad Supply Monitor in 6-Lead SOT-23 +SYMATTR Value2 LTC2903-A1 +SYMATTR SpiceModel LTC2903-A1.sub +PIN -96 -64 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -96 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 80 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 3 +PIN 96 80 RIGHT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 5 +PIN 96 -64 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC2903-B1.asy b/spice/copy/sym/PowerProducts/LTC2903-B1.asy new file mode 100755 index 0000000..30cbc35 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2903-B1.asy @@ -0,0 +1,30 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 112 -96 -96 +ARC Normal -9 -106 8 -89 -3 -97 9 -96 +TEXT 0 -40 Center 2 LT +WINDOW 3 0 40 Center 2 +WINDOW 0 0 -96 Bottom 2 +SYMATTR Value LTC2903-B1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2903-B1.sub +SYMATTR Description Precision Quad Supply Monitor in 6-Lead SOT-23 +SYMATTR Value2 LTC2903-B1 +PIN -96 -64 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -96 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 80 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 3 +PIN 96 80 RIGHT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 5 +PIN 96 -64 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC2903-C1.asy b/spice/copy/sym/PowerProducts/LTC2903-C1.asy new file mode 100755 index 0000000..c12fd4f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2903-C1.asy @@ -0,0 +1,30 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 112 -96 -96 +ARC Normal -9 -106 8 -89 -3 -97 27 -93 +TEXT 0 -40 Center 2 LT +WINDOW 3 0 40 Center 2 +WINDOW 0 0 -96 Bottom 2 +SYMATTR Value LTC2903-C1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2903-C1.sub +SYMATTR Description Precision Quad Supply Monitor in 6-Lead SOT-23 +SYMATTR Value2 LTC2903-C1 +PIN -96 -64 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -96 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 80 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 3 +PIN 96 80 RIGHT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 5 +PIN 96 -64 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC2903-D1.asy b/spice/copy/sym/PowerProducts/LTC2903-D1.asy new file mode 100755 index 0000000..1c6d727 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2903-D1.asy @@ -0,0 +1,30 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 112 -96 -96 +ARC Normal -9 -106 8 -89 -3 -97 27 -93 +TEXT 0 -40 Center 2 LT +WINDOW 3 0 40 Center 2 +WINDOW 0 0 -96 Bottom 2 +SYMATTR Value LTC2903-D1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2903-D1.sub +SYMATTR Description Precision Quad Supply Monitor in 6-Lead SOT-23 +SYMATTR Value2 LTC2903-D1 +PIN -96 -64 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -96 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 80 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 3 +PIN 96 80 RIGHT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 5 +PIN 96 -64 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC2903-E1.asy b/spice/copy/sym/PowerProducts/LTC2903-E1.asy new file mode 100755 index 0000000..391d372 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2903-E1.asy @@ -0,0 +1,30 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 112 -96 -96 +ARC Normal -9 -106 8 -89 -3 -97 27 -93 +TEXT 0 -40 Center 2 LT +WINDOW 3 0 40 Center 2 +WINDOW 0 -1 -97 Bottom 2 +SYMATTR Value LTC2903-E1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2903-E1.sub +SYMATTR Description Precision Quad Supply Monitor in 6-Lead SOT-23 +SYMATTR Value2 LTC2903-E1 +PIN -96 -64 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -96 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -96 80 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 3 +PIN 96 80 RIGHT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 5 +PIN 96 -64 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC2904.asy b/spice/copy/sym/PowerProducts/LTC2904.asy new file mode 100755 index 0000000..2a78a7e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2904.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 128 -128 -127 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2904 +SYMATTR Prefix X +SYMATTR Description Precision Dual Supply Monitor with Pin-Selectable Thresholds +SYMATTR SpiceModel LTC2904.sub +SYMATTR Value2 LTC2904 +PIN 128 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 2 +PIN 128 -32 RIGHT 8 +PINATTR PinName RST +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 4 +PIN -128 -96 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 5 +PIN -128 32 LEFT 8 +PINATTR PinName Vs2 +PINATTR SpiceOrder 6 +PIN -128 -32 LEFT 8 +PINATTR PinName Vs1 +PINATTR SpiceOrder 7 +PIN -128 96 LEFT 8 +PINATTR PinName TOL +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2905.asy b/spice/copy/sym/PowerProducts/LTC2905.asy new file mode 100755 index 0000000..0a02deb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2905.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 128 -128 -127 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2905 +SYMATTR Prefix X +SYMATTR Description Precision Dual Supply Monitor with Pin-Selectable Thresholds +SYMATTR SpiceModel LTC2905.sub +SYMATTR Value2 LTC2905 +PIN 128 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 2 +PIN 128 -32 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 3 +PIN 128 -96 RIGHT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 4 +PIN -128 -96 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 5 +PIN -128 32 LEFT 8 +PINATTR PinName Vs2 +PINATTR SpiceOrder 6 +PIN -128 -32 LEFT 8 +PINATTR PinName Vs1 +PINATTR SpiceOrder 7 +PIN -128 96 LEFT 8 +PINATTR PinName TOL +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2906.asy b/spice/copy/sym/PowerProducts/LTC2906.asy new file mode 100755 index 0000000..51ce7d2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2906.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 128 -128 -127 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2906 +SYMATTR Prefix X +SYMATTR Description Precision Dual Supply Monitor with One Pin-Selectable Threshold and One Adjustable Input +SYMATTR SpiceModel LTC2906.sub +SYMATTR Value2 LTC2906 +PIN 128 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 2 +PIN 128 -32 RIGHT 8 +PINATTR PinName RST +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 4 +PIN -128 -96 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 5 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 6 +PIN -128 32 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 7 +PIN -128 96 LEFT 8 +PINATTR PinName TOL +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2907.asy b/spice/copy/sym/PowerProducts/LTC2907.asy new file mode 100755 index 0000000..2f96b0c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2907.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 128 -128 -127 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2907 +SYMATTR Prefix X +SYMATTR Description Precision Dual Supply Monitor with One Pin-Selectable Threshold and One Adjustable Input +SYMATTR SpiceModel LTC2907.sub +SYMATTR Value2 LTC2907 +PIN 128 32 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 128 96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 2 +PIN 128 -32 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 4 +PIN -128 -96 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 5 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vadj +PINATTR SpiceOrder 6 +PIN -128 32 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 7 +PIN -128 96 LEFT 8 +PINATTR PinName TOL +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2908-A1.asy b/spice/copy/sym/PowerProducts/LTC2908-A1.asy new file mode 100755 index 0000000..4346bcb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2908-A1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 112 -144 -95 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -39 Center 2 +WINDOW 3 1 53 Center 2 +SYMATTR Value LTC2908-A1 +SYMATTR Prefix X +SYMATTR Description Precision Six Supply Monitor (5, 3.3, 2.5, 1.8, 2 adjust-0.5) +SYMATTR SpiceModel LTC2908-A1.sub +SYMATTR Value2 LTC2908-A1 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 3 +PIN -144 -16 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 5 +PIN 144 -64 RIGHT 8 +PINATTR PinName Vadj1 +PINATTR SpiceOrder 6 +PIN -144 32 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 7 +PIN 144 -16 RIGHT 8 +PINATTR PinName Vadj2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2908-B1.asy b/spice/copy/sym/PowerProducts/LTC2908-B1.asy new file mode 100755 index 0000000..242dd95 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2908-B1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 112 -144 -95 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 1 53 Center 2 +SYMATTR Value LTC2908-B1 +SYMATTR Prefix X +SYMATTR Description Precision Six Supply Monitor (3.3, 2.5, 1.8, 1.5, 2 adjust-0.5) +SYMATTR SpiceModel LTC2908-B1 +SYMATTR ModelFile LTC2908-B1.sub +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 144 80 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 2 +PIN -144 80 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 3 +PIN -144 -16 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 4 +PIN -144 -64 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 5 +PIN 144 -64 RIGHT 8 +PINATTR PinName Vadj1 +PINATTR SpiceOrder 6 +PIN -144 32 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 7 +PIN 144 -16 RIGHT 8 +PINATTR PinName Vadj2 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2908-C1.asy b/spice/copy/sym/PowerProducts/LTC2908-C1.asy new file mode 100755 index 0000000..98f2110 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2908-C1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 128 -160 -128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 1 40 Center 2 +SYMATTR Value LTC2908-C1 +SYMATTR Prefix X +SYMATTR Description Hex Supply Monitor (2.5, 5 adjust-0.5) +SYMATTR SpiceModel LTC2908-C1 +SYMATTR ModelFile LTC2908-C1.sub +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 80 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 2 +PIN 160 0 RIGHT 8 +PINATTR PinName Vadj5 +PINATTR SpiceOrder 3 +PIN 0 -128 TOP 8 +PINATTR PinName V1 +PINATTR SpiceOrder 4 +PIN -160 -80 LEFT 8 +PINATTR PinName Vadj1 +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName Vadj2 +PINATTR SpiceOrder 6 +PIN -160 80 LEFT 8 +PINATTR PinName Vadj3 +PINATTR SpiceOrder 7 +PIN 160 -80 RIGHT 8 +PINATTR PinName Vadj4 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2910.asy b/spice/copy/sym/PowerProducts/LTC2910.asy new file mode 100755 index 0000000..5798b58 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2910.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 -208 -128 208 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2910 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2910.sub +SYMATTR Value2 LTC2910 +SYMATTR Description Octal Positive/Negative Voltage Monitor +PIN -128 -192 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -128 -144 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 2 +PIN -128 -96 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 3 +PIN -128 -48 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 4 +PIN -128 0 LEFT 8 +PINATTR PinName V5 +PINATTR SpiceOrder 5 +PIN -128 48 LEFT 8 +PINATTR PinName V6 +PINATTR SpiceOrder 6 +PIN -128 144 LEFT 8 +PINATTR PinName V7 +PINATTR SpiceOrder 7 +PIN -128 192 LEFT 8 +PINATTR PinName V8 +PINATTR SpiceOrder 8 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -128 96 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 10 +PIN 128 0 RIGHT 8 +PINATTR PinName RST +PINATTR SpiceOrder 11 +PIN 128 -96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 12 +PIN 128 96 RIGHT 8 +PINATTR PinName DIS +PINATTR SpiceOrder 13 +PIN 128 -192 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 14 +PIN 128 192 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 15 +PIN 0 -208 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC2912-1.asy b/spice/copy/sym/PowerProducts/LTC2912-1.asy new file mode 100755 index 0000000..5b19753 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2912-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 160 -112 -160 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2912-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2912-1.sub +SYMATTR Value2 LTC2912-1 +SYMATTR Description Single UV/OV Voltage Monitor +PIN 112 96 RIGHT 8 +PINATTR PinName _Latch +PINATTR SpiceOrder 1 +PIN 112 -112 RIGHT 8 +PINATTR PinName _UV +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName _OV +PINATTR SpiceOrder 3 +PIN -48 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 48 160 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 5 +PIN -112 0 LEFT 8 +PINATTR PinName VL +PINATTR SpiceOrder 6 +PIN -112 -112 LEFT 8 +PINATTR PinName VH +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2912-2.asy b/spice/copy/sym/PowerProducts/LTC2912-2.asy new file mode 100755 index 0000000..e60984a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2912-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 160 -112 -160 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2912-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2912-2.sub +SYMATTR Value2 LTC2912-2 +SYMATTR Description Single UV/OV Voltage Monitor +PIN 112 96 RIGHT 8 +PINATTR PinName DIS +PINATTR SpiceOrder 1 +PIN 112 -112 RIGHT 8 +PINATTR PinName _UV +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName _OV +PINATTR SpiceOrder 3 +PIN -48 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 48 160 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 5 +PIN -112 0 LEFT 8 +PINATTR PinName VL +PINATTR SpiceOrder 6 +PIN -112 -112 LEFT 8 +PINATTR PinName VH +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2912-3.asy b/spice/copy/sym/PowerProducts/LTC2912-3.asy new file mode 100755 index 0000000..1c8c342 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2912-3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 160 -112 -160 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2912-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2912-3.sub +SYMATTR Value2 LTC2912-3 +SYMATTR Description Single UV/OV Voltage Monitor +PIN 112 96 RIGHT 8 +PINATTR PinName _Latch +PINATTR SpiceOrder 1 +PIN 112 -112 RIGHT 8 +PINATTR PinName _UV +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OV +PINATTR SpiceOrder 3 +PIN -48 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 48 160 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 5 +PIN -112 0 LEFT 8 +PINATTR PinName VL +PINATTR SpiceOrder 6 +PIN -112 -112 LEFT 8 +PINATTR PinName VH +PINATTR SpiceOrder 7 +PIN 0 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2913-1.asy b/spice/copy/sym/PowerProducts/LTC2913-1.asy new file mode 100755 index 0000000..eecabdc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2913-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 208 -112 -208 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2913-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2913-1.sub +SYMATTR Value2 LTC2913-1 +SYMATTR Description Dual UV/OV Voltage Monitor +PIN -112 -176 LEFT 8 +PINATTR PinName VH1 +PINATTR SpiceOrder 1 +PIN -112 -64 LEFT 8 +PINATTR PinName VL1 +PINATTR SpiceOrder 2 +PIN -112 -16 LEFT 8 +PINATTR PinName VH2 +PINATTR SpiceOrder 3 +PIN -112 96 LEFT 8 +PINATTR PinName VL2 +PINATTR SpiceOrder 4 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 112 -32 RIGHT 8 +PINATTR PinName _OV +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName _UV +PINATTR SpiceOrder 7 +PIN 112 96 RIGHT 8 +PINATTR PinName _Latch +PINATTR SpiceOrder 8 +PIN 112 144 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 9 +PIN 0 -208 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC2913-2.asy b/spice/copy/sym/PowerProducts/LTC2913-2.asy new file mode 100755 index 0000000..1a0a9a6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2913-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 208 -112 -208 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2913-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2913-2.sub +SYMATTR Value2 LTC2913-2 +SYMATTR Description Dual UV/OV Voltage Monitor +PIN -112 -176 LEFT 8 +PINATTR PinName VH1 +PINATTR SpiceOrder 1 +PIN -112 -64 LEFT 8 +PINATTR PinName VL1 +PINATTR SpiceOrder 2 +PIN -112 -16 LEFT 8 +PINATTR PinName VH2 +PINATTR SpiceOrder 3 +PIN -112 96 LEFT 8 +PINATTR PinName VL2 +PINATTR SpiceOrder 4 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 112 -32 RIGHT 8 +PINATTR PinName _OV +PINATTR SpiceOrder 6 +PIN 112 -112 RIGHT 8 +PINATTR PinName _UV +PINATTR SpiceOrder 7 +PIN 112 96 RIGHT 8 +PINATTR PinName DIS +PINATTR SpiceOrder 8 +PIN 112 144 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 9 +PIN 0 -208 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC2914-1.asy b/spice/copy/sym/PowerProducts/LTC2914-1.asy new file mode 100755 index 0000000..e3371cd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2914-1.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 336 -128 -336 +TEXT 0 0 Center 2 LT +WINDOW 3 0 88 Center 2 +WINDOW 0 0 -88 Center 2 +SYMATTR Value LTC2914-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2914-1.sub +SYMATTR Value2 LTC2914-1 +SYMATTR Description Quad UV/OV Postive/Negative Voltage Monitor +PIN -128 -288 LEFT 8 +PINATTR PinName VH1 +PINATTR SpiceOrder 1 +PIN -128 -176 LEFT 8 +PINATTR PinName VL1 +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName VH2 +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName VL2 +PINATTR SpiceOrder 4 +PIN -128 32 LEFT 8 +PINATTR PinName VH3 +PINATTR SpiceOrder 5 +PIN -128 144 LEFT 8 +PINATTR PinName VL3 +PINATTR SpiceOrder 6 +PIN -128 176 LEFT 8 +PINATTR PinName VH4 +PINATTR SpiceOrder 7 +PIN -128 288 LEFT 8 +PINATTR PinName VL4 +PINATTR SpiceOrder 8 +PIN -48 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -128 0 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 10 +PIN 128 -160 RIGHT 8 +PINATTR PinName _OV +PINATTR SpiceOrder 11 +PIN 128 0 RIGHT 8 +PINATTR PinName _UV +PINATTR SpiceOrder 12 +PIN 128 160 RIGHT 8 +PINATTR PinName _Latch +PINATTR SpiceOrder 13 +PIN 128 -272 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 14 +PIN 48 336 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 15 +PIN 0 -336 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC2914-2.asy b/spice/copy/sym/PowerProducts/LTC2914-2.asy new file mode 100755 index 0000000..164b1f0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2914-2.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 336 -128 -336 +TEXT 0 0 Center 2 LT +WINDOW 3 0 88 Center 2 +WINDOW 0 0 -87 Center 2 +SYMATTR Value LTC2914-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2914-2.sub +SYMATTR Value2 LTC2914-2 +SYMATTR Description Quad UV/OV Postive/Negative Voltage Monitor +PIN -128 -288 LEFT 8 +PINATTR PinName VH1 +PINATTR SpiceOrder 1 +PIN -128 -176 LEFT 8 +PINATTR PinName VL1 +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName VH2 +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName VL2 +PINATTR SpiceOrder 4 +PIN -128 32 LEFT 8 +PINATTR PinName VH3 +PINATTR SpiceOrder 5 +PIN -128 144 LEFT 8 +PINATTR PinName VL3 +PINATTR SpiceOrder 6 +PIN -128 176 LEFT 8 +PINATTR PinName VH4 +PINATTR SpiceOrder 7 +PIN -128 288 LEFT 8 +PINATTR PinName VL4 +PINATTR SpiceOrder 8 +PIN -48 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -128 0 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 10 +PIN 128 -160 RIGHT 8 +PINATTR PinName _OV +PINATTR SpiceOrder 11 +PIN 128 0 RIGHT 8 +PINATTR PinName _UV +PINATTR SpiceOrder 12 +PIN 128 160 RIGHT 8 +PINATTR PinName DIS +PINATTR SpiceOrder 13 +PIN 128 -272 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 14 +PIN 48 336 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 15 +PIN 0 -336 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC2919-25.asy b/spice/copy/sym/PowerProducts/LTC2919-25.asy new file mode 100755 index 0000000..4ff32af --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2919-25.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 160 -160 -176 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 0 Center 2 +SYMATTR Value LTC2919-2.5 +SYMATTR Prefix X +SYMATTR Description Precision Triple/Dual Input UV/OV and Negative Voltage Monitor, 2.5V UVLO +SYMATTR SpiceModel LTC2919-25.sub +SYMATTR Value2 LTC2919-25 +PIN -160 -128 LEFT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 1 +PIN -160 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 3 +PIN -160 64 LEFT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 4 +PIN -160 128 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 5 +PIN 160 128 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 64 RIGHT 8 +PINATTR PinName REF +PINATTR SpiceOrder 7 +PIN 160 0 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 8 +PIN 160 -64 RIGHT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 9 +PIN 160 -128 RIGHT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC2919-33.asy b/spice/copy/sym/PowerProducts/LTC2919-33.asy new file mode 100755 index 0000000..13c0c26 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2919-33.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 160 -160 -176 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 0 Center 2 +SYMATTR Value LTC2919-3.3 +SYMATTR Prefix X +SYMATTR Description Precision Triple/Dual Input UV/OV and Negative Voltage Monitor, 3.3V UVLO +SYMATTR SpiceModel LTC2919-33.sub +SYMATTR Value2 LTC2919-33 +PIN -160 -128 LEFT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 1 +PIN -160 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 3 +PIN -160 64 LEFT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 4 +PIN -160 128 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 5 +PIN 160 128 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 64 RIGHT 8 +PINATTR PinName REF +PINATTR SpiceOrder 7 +PIN 160 0 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 8 +PIN 160 -64 RIGHT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 9 +PIN 160 -128 RIGHT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC2919-50.asy b/spice/copy/sym/PowerProducts/LTC2919-50.asy new file mode 100755 index 0000000..ca96257 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2919-50.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 160 -160 -176 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 0 Center 2 +SYMATTR Value LTC2919-5.0 +SYMATTR Prefix X +SYMATTR Description Precision Triple/Dual Input UV/OV and Negative Voltage Monitor, 5.0V UVLO +SYMATTR SpiceModel LTC2919-50.sub +SYMATTR Value2 LTC2919-50 +PIN -160 -128 LEFT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 1 +PIN -160 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 3 +PIN -160 64 LEFT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 4 +PIN -160 128 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 5 +PIN 160 128 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 64 RIGHT 8 +PINATTR PinName REF +PINATTR SpiceOrder 7 +PIN 160 0 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 8 +PIN 160 -64 RIGHT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 9 +PIN 160 -128 RIGHT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC2920-1.asy b/spice/copy/sym/PowerProducts/LTC2920-1.asy new file mode 100755 index 0000000..9f44dc1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2920-1.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2920-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2920-1.sub +SYMATTR Value2 LTC2920-1 +SYMATTR Description Single/Dual Power Supply Margining Controller +PIN 0 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName IM1 +PINATTR SpiceOrder 3 +PIN -128 80 LEFT 8 +PINATTR PinName RS1 +PINATTR SpiceOrder 4 +PIN -128 -64 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/LTC2920-2.asy b/spice/copy/sym/PowerProducts/LTC2920-2.asy new file mode 100755 index 0000000..050e3e8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2920-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC2920-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2920-2.sub +SYMATTR Value2 LTC2920-2 +SYMATTR Description Single/Dual Power Supply Margining Controller +PIN -128 112 LEFT 8 +PINATTR PinName RS2 +PINATTR SpiceOrder 1 +PIN -128 48 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 2 +PIN -128 -96 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 3 +PIN -128 -32 LEFT 8 +PINATTR PinName RS1 +PINATTR SpiceOrder 4 +PIN 128 -48 RIGHT 8 +PINATTR PinName IM1 +PINATTR SpiceOrder 5 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 80 RIGHT 8 +PINATTR PinName IM2 +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2921-2.5.asy b/spice/copy/sym/PowerProducts/LTC2921-2.5.asy new file mode 100755 index 0000000..2bf1b62 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2921-2.5.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 336 -144 -336 +TEXT 0 -128 Center 2 LT +WINDOW 3 0 -39 Center 2 +WINDOW 0 1 -199 Center 2 +SYMATTR Value LTC2921-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2921-2.5.sub +SYMATTR Description Power Supply Tracker with Input Monitors +SYMATTR Value2 LTC2921-2.5 +PIN -144 -240 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -144 -160 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 4 +PIN -144 240 LEFT 8 +PINATTR PinName S3 +PINATTR SpiceOrder 5 +PIN 144 240 RIGHT 8 +PINATTR PinName D3 +PINATTR SpiceOrder 6 +PIN -144 160 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 7 +PIN 144 160 RIGHT 8 +PINATTR PinName D2 +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 9 +PIN 144 80 RIGHT 8 +PINATTR PinName D1 +PINATTR SpiceOrder 10 +PIN -64 336 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 11 +PIN 144 0 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 12 +PIN 144 -240 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 13 +PIN 64 -336 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 14 +PIN -64 -336 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN 64 336 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC2921-3.3.asy b/spice/copy/sym/PowerProducts/LTC2921-3.3.asy new file mode 100755 index 0000000..e9b628f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2921-3.3.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 336 -144 -336 +TEXT 0 -128 Center 2 LT +WINDOW 3 0 -39 Center 2 +WINDOW 0 1 -199 Center 2 +SYMATTR Value LTC2921-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2921-3.3.sub +SYMATTR Description Power Supply Tracker with Input Monitors +SYMATTR Value2 LTC2921-3.3 +PIN -144 -240 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -144 -160 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 4 +PIN -144 240 LEFT 8 +PINATTR PinName S3 +PINATTR SpiceOrder 5 +PIN 144 240 RIGHT 8 +PINATTR PinName D3 +PINATTR SpiceOrder 6 +PIN -144 160 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 7 +PIN 144 160 RIGHT 8 +PINATTR PinName D2 +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 9 +PIN 144 80 RIGHT 8 +PINATTR PinName D1 +PINATTR SpiceOrder 10 +PIN -64 336 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 11 +PIN 144 0 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 12 +PIN 144 -240 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 13 +PIN 64 -336 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 14 +PIN -64 -336 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN 64 336 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC2921.asy b/spice/copy/sym/PowerProducts/LTC2921.asy new file mode 100755 index 0000000..e5d0615 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2921.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 336 -144 -336 +TEXT 0 -128 Center 2 LT +WINDOW 3 0 -39 Center 2 +WINDOW 0 1 -199 Center 2 +SYMATTR Value LTC2921 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2921.sub +SYMATTR Description Power Supply Tracker with Input Monitors +SYMATTR Value2 LTC2921 +PIN 144 0 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 12 +PIN 144 80 RIGHT 8 +PINATTR PinName D1 +PINATTR SpiceOrder 10 +PIN -144 -160 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 3 +PIN -144 0 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 4 +PIN -144 80 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 9 +PIN 144 160 RIGHT 8 +PINATTR PinName D2 +PINATTR SpiceOrder 8 +PIN 144 240 RIGHT 8 +PINATTR PinName D3 +PINATTR SpiceOrder 6 +PIN -64 -336 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN -64 336 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 11 +PIN 64 336 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 16 +PIN -144 240 LEFT 8 +PINATTR PinName S3 +PINATTR SpiceOrder 5 +PIN -144 160 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 7 +PIN 144 -240 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 13 +PIN -144 -240 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN 64 -336 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTC2922-2.5.asy b/spice/copy/sym/PowerProducts/LTC2922-2.5.asy new file mode 100755 index 0000000..961291c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2922-2.5.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 416 -144 -416 +TEXT 0 -128 Center 2 LT +WINDOW 3 0 -39 Center 2 +WINDOW 0 1 -199 Center 2 +SYMATTR Value LTC2922-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2922-2.5.sub +SYMATTR Description Power Supply Tracker with Input Monitors +SYMATTR Value2 LTC2922-2.5 +PIN -144 -320 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -144 -240 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 2 +PIN -144 -160 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 3 +PIN -144 -80 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 4 +PIN -144 240 LEFT 8 +PINATTR PinName S3 +PINATTR SpiceOrder 5 +PIN 144 240 RIGHT 8 +PINATTR PinName D3 +PINATTR SpiceOrder 6 +PIN -144 160 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 7 +PIN 144 160 RIGHT 8 +PINATTR PinName D2 +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 9 +PIN 144 80 RIGHT 8 +PINATTR PinName D1 +PINATTR SpiceOrder 10 +PIN -64 416 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 11 +PIN 144 -80 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 12 +PIN 144 -320 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 13 +PIN 64 -416 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 14 +PIN -64 -416 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN 64 416 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 16 +PIN -144 0 LEFT 8 +PINATTR PinName S0 +PINATTR SpiceOrder 17 +PIN 144 0 RIGHT 8 +PINATTR PinName D0 +PINATTR SpiceOrder 18 +PIN -144 320 LEFT 8 +PINATTR PinName S4 +PINATTR SpiceOrder 19 +PIN 144 320 RIGHT 8 +PINATTR PinName D4 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC2922-3.3.asy b/spice/copy/sym/PowerProducts/LTC2922-3.3.asy new file mode 100755 index 0000000..6343c66 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2922-3.3.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 416 -144 -416 +TEXT 0 -128 Center 2 LT +WINDOW 3 0 -39 Center 2 +WINDOW 0 1 -199 Center 2 +SYMATTR Value LTC2922-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2922-3.3.sub +SYMATTR Description Power Supply Tracker with Input Monitors +SYMATTR Value2 LTC2922-3.3 +PIN -144 -320 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -144 -240 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 2 +PIN -144 -160 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 3 +PIN -144 -80 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 4 +PIN -144 240 LEFT 8 +PINATTR PinName S3 +PINATTR SpiceOrder 5 +PIN 144 240 RIGHT 8 +PINATTR PinName D3 +PINATTR SpiceOrder 6 +PIN -144 160 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 7 +PIN 144 160 RIGHT 8 +PINATTR PinName D2 +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 9 +PIN 144 80 RIGHT 8 +PINATTR PinName D1 +PINATTR SpiceOrder 10 +PIN -64 416 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 11 +PIN 144 -80 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 12 +PIN 144 -320 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 13 +PIN 64 -416 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 14 +PIN -64 -416 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN 64 416 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 16 +PIN -144 0 LEFT 8 +PINATTR PinName S0 +PINATTR SpiceOrder 17 +PIN 144 0 RIGHT 8 +PINATTR PinName D0 +PINATTR SpiceOrder 18 +PIN -144 320 LEFT 8 +PINATTR PinName S4 +PINATTR SpiceOrder 19 +PIN 144 320 RIGHT 8 +PINATTR PinName D4 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC2922.asy b/spice/copy/sym/PowerProducts/LTC2922.asy new file mode 100755 index 0000000..0c589c9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2922.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 416 -144 -416 +TEXT 0 -128 Center 2 LT +WINDOW 3 0 -39 Center 2 +WINDOW 0 1 -199 Center 2 +SYMATTR Value LTC2922 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2922.sub +SYMATTR Description Power Supply Tracker with Input Monitors +SYMATTR Value2 LTC2922 +PIN -144 -320 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -144 -240 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 2 +PIN -144 -160 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 3 +PIN -144 -80 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 4 +PIN -144 240 LEFT 8 +PINATTR PinName S3 +PINATTR SpiceOrder 5 +PIN 144 240 RIGHT 8 +PINATTR PinName D3 +PINATTR SpiceOrder 6 +PIN -144 160 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 7 +PIN 144 160 RIGHT 8 +PINATTR PinName D2 +PINATTR SpiceOrder 8 +PIN -144 80 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 9 +PIN 144 80 RIGHT 8 +PINATTR PinName D1 +PINATTR SpiceOrder 10 +PIN -64 416 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 11 +PIN 144 -80 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 12 +PIN 144 -320 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 13 +PIN 64 -416 TOP 8 +PINATTR PinName Sense +PINATTR SpiceOrder 14 +PIN -64 -416 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 15 +PIN 64 416 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 16 +PIN -144 0 LEFT 8 +PINATTR PinName S0 +PINATTR SpiceOrder 17 +PIN 144 0 RIGHT 8 +PINATTR PinName D0 +PINATTR SpiceOrder 18 +PIN -144 320 LEFT 8 +PINATTR PinName S4 +PINATTR SpiceOrder 19 +PIN 144 320 RIGHT 8 +PINATTR PinName D4 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC2923.asy b/spice/copy/sym/PowerProducts/LTC2923.asy new file mode 100755 index 0000000..670a41f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2923.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 160 224 -160 -224 +TEXT 0 9 Center 2 LT +WINDOW 3 0 119 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTC2923 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2923.sub +SYMATTR Value2 LTC2923 +SYMATTR Description Power Supply Tracking Controller +PIN -112 -224 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -160 -160 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 2 +PIN -160 64 LEFT 8 +PINATTR PinName Track1 +PINATTR SpiceOrder 3 +PIN -160 176 LEFT 8 +PINATTR PinName Track2 +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName RampBuf +PINATTR SpiceOrder 5 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 176 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 7 +PIN 160 -160 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 8 +PIN 160 64 RIGHT 8 +PINATTR PinName _SDO +PINATTR SpiceOrder 9 +PIN 160 -48 RIGHT 8 +PINATTR PinName Status +PINATTR SpiceOrder 10 +PIN 0 -224 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 11 +PIN 112 -224 TOP 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LTC2924.asy b/spice/copy/sym/PowerProducts/LTC2924.asy new file mode 100755 index 0000000..fe3dfb9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2924.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 304 -144 -287 +TEXT 0 -128 Center 2 LT +WINDOW 3 0 -39 Center 2 +WINDOW 0 1 -199 Center 2 +SYMATTR Value LTC2924 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2924.sub +SYMATTR Description Programmable Quad Supply Monitor with Adjustable Reset Timer +SYMATTR Value2 LTC2924 +PIN 144 -160 RIGHT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN 144 -80 RIGHT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 2 +PIN 144 0 RIGHT 8 +PINATTR PinName IN3 +PINATTR SpiceOrder 3 +PIN 144 80 RIGHT 8 +PINATTR PinName IN4 +PINATTR SpiceOrder 4 +PIN -144 -160 LEFT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 5 +PIN -144 -80 LEFT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName OUT3 +PINATTR SpiceOrder 7 +PIN -144 80 LEFT 8 +PINATTR PinName OUT4 +PINATTR SpiceOrder 8 +PIN 144 160 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 9 +PIN 144 240 RIGHT 8 +PINATTR PinName _Done +PINATTR SpiceOrder 10 +PIN 0 -288 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 11 +PIN -48 304 BOTTOM 8 +PINATTR PinName PGT +PINATTR SpiceOrder 12 +PIN 48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 +PIN -144 240 LEFT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 14 +PIN -144 160 LEFT 8 +PINATTR PinName HYS/CFG +PINATTR SpiceOrder 15 +PIN 144 -240 RIGHT 8 +PINATTR PinName ON +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTC2926.asy b/spice/copy/sym/PowerProducts/LTC2926.asy new file mode 100755 index 0000000..f02f367 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2926.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -256 256 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2926 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2926.sub +SYMATTR Value2 LTC2926 +SYMATTR Description MOSFET-Controlled Power Supply Tracker +PIN -192 -256 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -256 0 LEFT 8 +PINATTR PinName Track1 +PINATTR SpiceOrder 2 +PIN 256 -112 RIGHT 8 +PINATTR PinName Fb1 +PINATTR SpiceOrder 3 +PIN 256 -192 RIGHT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 4 +PIN 192 -256 TOP 8 +PINATTR PinName Sgate1 +PINATTR SpiceOrder 5 +PIN -256 -192 LEFT 8 +PINATTR PinName D1 +PINATTR SpiceOrder 6 +PIN -256 192 LEFT 8 +PINATTR PinName On +PINATTR SpiceOrder 7 +PIN 0 256 BOTTOM 8 +PINATTR PinName Pgtmr +PINATTR SpiceOrder 8 +PIN -256 128 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 9 +PIN -192 256 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 10 +PIN 256 208 RIGHT 8 +PINATTR PinName Rsgate +PINATTR SpiceOrder 13 +PIN -96 -256 TOP 8 +PINATTR PinName Mgate +PINATTR SpiceOrder 12 +PIN 256 128 RIGHT 8 +PINATTR PinName Status/PGI +PINATTR SpiceOrder 14 +PIN -256 -128 LEFT 8 +PINATTR PinName D2 +PINATTR SpiceOrder 15 +PIN 96 -256 TOP 8 +PINATTR PinName Sgate2 +PINATTR SpiceOrder 16 +PIN 256 -32 RIGHT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 17 +PIN 256 48 RIGHT 8 +PINATTR PinName Fb2 +PINATTR SpiceOrder 18 +PIN -256 64 LEFT 8 +PINATTR PinName Track2 +PINATTR SpiceOrder 19 +PIN -256 -64 LEFT 8 +PINATTR PinName Rampbuf +PINATTR SpiceOrder 20 +PIN 0 -256 TOP 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTC2927.asy b/spice/copy/sym/PowerProducts/LTC2927.asy new file mode 100755 index 0000000..55a9a0f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2927.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 160 192 -160 -176 +TEXT 0 0 Center 2 LT +WINDOW 3 0 74 Center 2 +WINDOW 0 -1 -72 Center 2 +SYMATTR Value LTC2927 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2927.sub +SYMATTR Value2 LTC2927 +SYMATTR Description Single Power Supply Tracking Controller +PIN 0 -176 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -160 -112 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 2 +PIN -160 16 LEFT 8 +PINATTR PinName RampBuf +PINATTR SpiceOrder 3 +PIN -160 128 LEFT 8 +PINATTR PinName Track +PINATTR SpiceOrder 4 +PIN 160 -112 RIGHT 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 5 +PIN 160 16 RIGHT 8 +PINATTR PinName _SDO +PINATTR SpiceOrder 6 +PIN 160 128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2930.asy b/spice/copy/sym/PowerProducts/LTC2930.asy new file mode 100755 index 0000000..a4a65c2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2930.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 208 -128 -192 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2930 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2930.sub +SYMATTR Value2 LTC2930 +SYMATTR Description Configurable Six Supply Monitor with Adjustable Reset Timer, Manual Reset +PIN -128 48 LEFT 8 +PINATTR PinName V5 +PINATTR SpiceOrder 1 +PIN -128 -48 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 2 +PIN -128 -144 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 3 +PIN 80 208 BOTTOM 8 +PINATTR PinName CRT +PINATTR SpiceOrder 4 +PIN 128 -96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 5 +PIN 128 96 RIGHT 8 +PINATTR PinName _MR +PINATTR SpiceOrder 6 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -80 208 BOTTOM 8 +PINATTR PinName VPG +PINATTR SpiceOrder 8 +PIN -128 144 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 9 +PIN -128 0 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 10 +PIN -128 -96 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 11 +PIN -128 96 LEFT 8 +PINATTR PinName V6 +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LTC2932.asy b/spice/copy/sym/PowerProducts/LTC2932.asy new file mode 100755 index 0000000..3d3e984 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2932.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 304 -160 -176 +TEXT -3 -88 Center 2 LT +WINDOW 3 -3 -24 Center 2 +WINDOW 0 -3 -152 Center 2 +SYMATTR Value LTC2932 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2932.sub +SYMATTR Description Configurable Six Supply Monitor with Adjustable Reset Timer and Supply Tolerance +SYMATTR Value2 LTC2932 +PIN 176 48 RIGHT 8 +PINATTR PinName COMP5 +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName V5 +PINATTR SpiceOrder 2 +PIN 176 -48 RIGHT 8 +PINATTR PinName COMP3 +PINATTR SpiceOrder 3 +PIN 176 -144 RIGHT 8 +PINATTR PinName COMP1 +PINATTR SpiceOrder 4 +PIN -160 -48 LEFT 8 +PINATTR PinName V3 +PINATTR SpiceOrder 5 +PIN -160 -144 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 6 +PIN 64 304 BOTTOM 8 +PINATTR PinName CRT +PINATTR SpiceOrder 7 +PIN 176 160 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 8 +PIN -160 208 LEFT 8 +PINATTR PinName T0 +PINATTR SpiceOrder 9 +PIN -160 160 LEFT 8 +PINATTR PinName _RDIS +PINATTR SpiceOrder 10 +PIN -160 256 LEFT 8 +PINATTR PinName T1 +PINATTR SpiceOrder 11 +PIN -48 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 +PIN 176 256 RIGHT 8 +PINATTR PinName VPG +PINATTR SpiceOrder 13 +PIN 176 208 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 14 +PIN -160 0 LEFT 8 +PINATTR PinName V4 +PINATTR SpiceOrder 15 +PIN -160 -96 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 16 +PIN 176 0 RIGHT 8 +PINATTR PinName COMP4 +PINATTR SpiceOrder 17 +PIN 176 -96 RIGHT 8 +PINATTR PinName COMP2 +PINATTR SpiceOrder 18 +PIN -160 96 LEFT 8 +PINATTR PinName V6 +PINATTR SpiceOrder 19 +PIN 176 96 RIGHT 8 +PINATTR PinName COMP6 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTC2934-1.asy b/spice/copy/sym/PowerProducts/LTC2934-1.asy new file mode 100755 index 0000000..2ae9865 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2934-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -128 +TEXT 0 0 Center 2 LT +WINDOW 3 0 43 Center 2 +WINDOW 0 0 -43 Center 2 +SYMATTR Value LTC2934-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2934-1.sub +SYMATTR Value2 LTC2934-1 +SYMATTR Description Ultra-Low Power Adjustable Supervisor with Power-Fail Output +PIN -112 -96 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN -112 16 LEFT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 2 +PIN 112 -80 RIGHT 8 +PINATTR PinName RT +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 112 80 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN -112 96 LEFT 8 +PINATTR PinName _MR +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2934-2.asy b/spice/copy/sym/PowerProducts/LTC2934-2.asy new file mode 100755 index 0000000..43a923b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2934-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -128 +TEXT 0 0 Center 2 LT +WINDOW 3 0 43 Center 2 +WINDOW 0 0 -43 Center 2 +SYMATTR Value LTC2934-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2934-2.sub +SYMATTR Value2 LTC2934-2 +SYMATTR Description Ultra-Low Power Adjustable Supervisor with Power_Fail Output +PIN -112 -96 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN -112 16 LEFT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 2 +PIN 112 -80 RIGHT 8 +PINATTR PinName RT +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 112 80 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN -112 96 LEFT 8 +PINATTR PinName _MR +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2935-1.asy b/spice/copy/sym/PowerProducts/LTC2935-1.asy new file mode 100755 index 0000000..2cecb9d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2935-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 128 -96 -128 +TEXT 0 0 Center 2 LT +WINDOW 3 0 43 Center 2 +WINDOW 0 0 -43 Center 2 +SYMATTR Value LTC2935-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2935-1.sub +SYMATTR Value2 LTC2935-1 +SYMATTR Description Ultra-Low Power Supervisor with Power-Fail Output, Selectable Thresholds +PIN -96 -80 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 1 +PIN -96 0 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 2 +PIN -96 80 LEFT 8 +PINATTR PinName S0 +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 96 -80 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN 96 80 RIGHT 8 +PINATTR PinName MR +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2935-2.asy b/spice/copy/sym/PowerProducts/LTC2935-2.asy new file mode 100755 index 0000000..77f34ce --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2935-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 128 -96 -128 +TEXT 0 0 Center 2 LT +WINDOW 3 0 43 Center 2 +WINDOW 0 0 -43 Center 2 +SYMATTR Value LTC2935-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2935-2.sub +SYMATTR Value2 LTC2935-2 +SYMATTR Description Ultra-Low Power Supervisor with Power-Fail Output, Selectable Thresholds +PIN -96 -80 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 1 +PIN -96 0 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 2 +PIN -96 80 LEFT 8 +PINATTR PinName S0 +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 96 -80 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN 96 80 RIGHT 8 +PINATTR PinName MR +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2935-3.asy b/spice/copy/sym/PowerProducts/LTC2935-3.asy new file mode 100755 index 0000000..a93f54b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2935-3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 128 -96 -128 +TEXT 0 0 Center 2 LT +WINDOW 3 0 43 Center 2 +WINDOW 0 0 -43 Center 2 +SYMATTR Value LTC2935-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2935-3.sub +SYMATTR Value2 LTC2935-3 +SYMATTR Description Ultra-Low Power Supervisor with Power-Fail Output, Selectable Thresholds +PIN -96 -80 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 1 +PIN -96 0 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 2 +PIN -96 80 LEFT 8 +PINATTR PinName S0 +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 96 -80 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN 96 80 RIGHT 8 +PINATTR PinName MR +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2935-4.asy b/spice/copy/sym/PowerProducts/LTC2935-4.asy new file mode 100755 index 0000000..2fc924e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2935-4.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 96 128 -96 -128 +TEXT 0 0 Center 2 LT +WINDOW 3 0 43 Center 2 +WINDOW 0 0 -43 Center 2 +SYMATTR Value LTC2935-4 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2935-4.sub +SYMATTR Value2 LTC2935-4 +SYMATTR Description Ultra-Low Power Supervisor with Power-Fail Output, Selectable Thresholds +PIN -96 -80 LEFT 8 +PINATTR PinName S2 +PINATTR SpiceOrder 1 +PIN -96 0 LEFT 8 +PINATTR PinName S1 +PINATTR SpiceOrder 2 +PIN -96 80 LEFT 8 +PINATTR PinName S0 +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 96 0 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 96 -80 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN 96 80 RIGHT 8 +PINATTR PinName MR +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName VCC +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC2992.asy b/spice/copy/sym/PowerProducts/LTC2992.asy new file mode 100755 index 0000000..dc74525 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC2992.asy @@ -0,0 +1,142 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -352 -592 352 592 +TEXT 0 -96 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 0 Center 2 +WINDOW 123 0 160 Center 2 +WINDOW 39 0 128 Center 2 +WINDOW 40 0 96 Center 2 +SYMATTR Value LTC2992 +SYMATTR Value2 CA2=0 CA1=0 CA0=0 +SYMATTR SpiceLine CA6=0 CA5=0 CA4=0 CA3=0 +SYMATTR SpiceLine2 NADC7=0 CA7=0 +SYMATTR Prefix X +SYMATTR Description Dual Wide Range Power Monitor +SYMATTR ModelFile LTC2992.sub +PIN -352 -448 LEFT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -352 448 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -352 -352 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 3 +PIN -352 -176 LEFT 8 +PINATTR PinName GPIO1 +PINATTR SpiceOrder 4 +PIN -352 -80 LEFT 8 +PINATTR PinName GPIO2 +PINATTR SpiceOrder 5 +PIN -352 16 LEFT 8 +PINATTR PinName GPIO3 +PINATTR SpiceOrder 6 +PIN -352 112 LEFT 8 +PINATTR PinName GPIO4 +PINATTR SpiceOrder 7 +PIN -352 288 LEFT 8 +PINATTR PinName >SD +PINATTR SpiceOrder 8 +PIN -208 -592 TOP 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 9 +PIN -80 -592 TOP 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 10 +PIN 80 -592 TOP 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 11 +PIN 208 -592 TOP 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 12 +PIN 352 -512 RIGHT 8 +PINATTR PinName >Power1 +PINATTR SpiceOrder 13 +PIN 352 -464 RIGHT 8 +PINATTR PinName >MaxPower1 +PINATTR SpiceOrder 14 +PIN 352 -416 RIGHT 8 +PINATTR PinName >MinPower1 +PINATTR SpiceOrder 15 +PIN 352 -352 RIGHT 8 +PINATTR PinName >Power2 +PINATTR SpiceOrder 16 +PIN 352 -304 RIGHT 8 +PINATTR PinName >MaxPower2 +PINATTR SpiceOrder 17 +PIN 352 -256 RIGHT 8 +PINATTR PinName >MinPower2 +PINATTR SpiceOrder 18 +PIN 352 -192 RIGHT 8 +PINATTR PinName >DSense1 +PINATTR SpiceOrder 19 +PIN 352 -144 RIGHT 8 +PINATTR PinName >MaxDSense1 +PINATTR SpiceOrder 20 +PIN 352 -96 RIGHT 8 +PINATTR PinName >MinDSense1 +PINATTR SpiceOrder 21 +PIN 352 -32 RIGHT 8 +PINATTR PinName >DSense2 +PINATTR SpiceOrder 22 +PIN 352 16 RIGHT 8 +PINATTR PinName >MaxDSense2 +PINATTR SpiceOrder 23 +PIN 352 64 RIGHT 8 +PINATTR PinName >MinDSense2 +PINATTR SpiceOrder 24 +PIN 352 128 RIGHT 8 +PINATTR PinName >Sense1+ +PINATTR SpiceOrder 25 +PIN 352 176 RIGHT 8 +PINATTR PinName >MaxSense1+ +PINATTR SpiceOrder 26 +PIN 352 224 RIGHT 8 +PINATTR PinName >MinSense1+ +PINATTR SpiceOrder 27 +PIN 352 288 RIGHT 8 +PINATTR PinName >Sense2+ +PINATTR SpiceOrder 28 +PIN 352 336 RIGHT 8 +PINATTR PinName >MaxSense2+ +PINATTR SpiceOrder 29 +PIN 352 384 RIGHT 8 +PINATTR PinName >MinSense2+ +PINATTR SpiceOrder 30 +PIN -224 592 VLEFT 8 +PINATTR PinName Status +PINATTR SpiceOrder 8 +PIN 400 64 RIGHT 8 +PINATTR PinName >Class +PINATTR SpiceOrder 9 +PIN -400 -96 LEFT 8 +PINATTR PinName Auto +PINATTR SpiceOrder 10 +PIN -400 -16 LEFT 8 +PINATTR PinName Mid +PINATTR SpiceOrder 11 +PIN -400 64 LEFT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 12 +PIN -400 144 LEFT 8 +PINATTR PinName _Shdn +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTC4278.asy b/spice/copy/sym/PowerProducts/LTC4278.asy new file mode 100755 index 0000000..329dbcf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4278.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 400 -144 -384 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTC4278 +SYMATTR Value2 LTC4278 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4278.sub +SYMATTR Description IEEE802.3at PD with Synchronous No-Opto Flyback Controller with 12V AUX Support +PIN -144 -352 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -144 -288 LEFT 8 +PINATTR PinName _T2PSE +PINATTR SpiceOrder 2 +PIN -144 -224 LEFT 8 +PINATTR PinName RCLASS +PINATTR SpiceOrder 3 +PIN -144 -160 LEFT 8 +PINATTR PinName VPORTN +PINATTR SpiceOrder 4 +PIN 144 352 RIGHT 8 +PINATTR PinName SG +PINATTR SpiceOrder 5 +PIN -144 -32 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 6 +PIN -144 32 LEFT 8 +PINATTR PinName TON +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName ENDLY +PINATTR SpiceOrder 8 +PIN -144 160 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 9 +PIN -144 224 LEFT 8 +PINATTR PinName SFST +PINATTR SpiceOrder 10 +PIN -144 288 LEFT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 11 +PIN -144 352 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN -144 -96 LEFT 8 +PINATTR PinName VCMP +PINATTR SpiceOrder 13 +PIN 144 288 RIGHT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 14 +PIN 144 224 RIGHT 8 +PINATTR PinName SENSE- +PINATTR SpiceOrder 15 +PIN 144 160 RIGHT 8 +PINATTR PinName SENSE+ +PINATTR SpiceOrder 16 +PIN 144 96 RIGHT 8 +PINATTR PinName CCMP +PINATTR SpiceOrder 17 +PIN 144 32 RIGHT 8 +PINATTR PinName RCMP +PINATTR SpiceOrder 18 +PIN 144 -32 RIGHT 8 +PINATTR PinName PGDLY +PINATTR SpiceOrder 19 +PIN 144 -96 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 20 +PIN 144 -160 RIGHT 8 +PINATTR PinName VNEG +PINATTR SpiceOrder 21 +PIN 144 -224 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 22 +PIN 144 -288 RIGHT 8 +PINATTR PinName _PWRGD +PINATTR SpiceOrder 23 +PIN 144 -352 RIGHT 8 +PINATTR PinName VPORTP +PINATTR SpiceOrder 24 +PIN 0 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LTC4280.asy b/spice/copy/sym/PowerProducts/LTC4280.asy new file mode 100755 index 0000000..5e00191 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4280.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 336 144 -320 -128 +TEXT 0 -16 Center 2 LT +WINDOW 3 0 32 Center 2 +WINDOW 0 0 -64 Center 2 +WINDOW 39 0 80 Center 2 +SYMATTR Value LTC4280 +SYMATTR SpiceLine uvautoretry=1 ovautoretry=1 ocautoretry=0 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4280 +SYMATTR Description Hot Swap Controller with I2C Compatible Monitoring +SYMATTR ModelFile LTC4280.sub +SYMATTR Value2 LTC4280 +PIN -320 -64 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 1 +PIN -320 0 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -240 144 BOTTOM 8 +PINATTR PinName FILTER +PINATTR SpiceOrder 3 +PIN -80 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -320 64 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 5 +PIN 336 64 RIGHT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 6 +PIN 240 144 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 7 +PIN 80 144 BOTTOM 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 +PIN 336 0 RIGHT 8 +PINATTR PinName GPIO +PINATTR SpiceOrder 9 +PIN 336 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN 224 -128 TOP 8 +PINATTR PinName Source +PINATTR SpiceOrder 11 +PIN 112 -128 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 12 +PIN 0 -128 TOP 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 13 +PIN -112 -128 TOP 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 14 +PIN -224 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LTC4281.asy b/spice/copy/sym/PowerProducts/LTC4281.asy new file mode 100755 index 0000000..5a76926 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4281.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -432 -160 432 192 +TEXT 0 0 Center 2 LT +WINDOW 3 0 -41 Center 2 +WINDOW 0 0 41 Center 2 +WINDOW 123 0 80 Center 2 +WINDOW 39 0 128 Center 2 +SYMATTR Value LTC4281 +SYMATTR Value2 OVRTRY=1 UVRTRY=1 OCRTRY=0 +SYMATTR SpiceLine FETBADRTRY=1 FETBADTIMOUT=10m +SYMATTR Prefix X +SYMATTR Description Hot Swap Controller with I2C Compatible Monitoring +SYMATTR ModelFile LTC4281.sub +PIN -432 96 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 1 +PIN -432 -32 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -336 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -432 32 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 5 +PIN 336 192 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 432 96 RIGHT 8 +PINATTR PinName GPIO2/Stress +PINATTR SpiceOrder 18 +PIN 432 32 RIGHT 8 +PINATTR PinName GPIO1/PG +PINATTR SpiceOrder 19 +PIN 432 -32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 21 +PIN 432 -96 RIGHT 8 +PINATTR PinName Source +PINATTR SpiceOrder 22 +PIN 272 -160 TOP 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 23 +PIN 112 -160 TOP 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 27 +PIN -112 -160 TOP 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 29 +PIN -272 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 31 +PIN -432 -96 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 32 diff --git a/spice/copy/sym/PowerProducts/LTC4282.asy b/spice/copy/sym/PowerProducts/LTC4282.asy new file mode 100755 index 0000000..d140275 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4282.asy @@ -0,0 +1,67 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -432 -160 432 192 +TEXT 0 0 Center 2 LT +WINDOW 3 0 -41 Center 2 +WINDOW 0 0 41 Center 2 +WINDOW 123 0 80 Center 2 +WINDOW 39 0 119 Center 2 +WINDOW 40 0 160 Center 2 +SYMATTR Value LTC4282 +SYMATTR Value2 OVRTRY=1 UVRTRY=1 OCRTRY=0 +SYMATTR SpiceLine FETBADRTRY=1 FETBADTIMOUT=10m +SYMATTR Prefix X +SYMATTR Description High Current Hot Swap Controller with I2C Compatible Monitoring +SYMATTR ModelFile LTC4282.sub +SYMATTR SpiceLine2 ILIM_ADJUST=4 +PIN -432 96 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 1 +PIN -432 -32 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -336 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -432 32 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 5 +PIN 336 192 BOTTOM 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 432 96 RIGHT 8 +PINATTR PinName GPIO2/Stress +PINATTR SpiceOrder 18 +PIN 432 32 RIGHT 8 +PINATTR PinName GPIO1/PG +PINATTR SpiceOrder 19 +PIN 432 -32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 21 +PIN 432 -96 RIGHT 8 +PINATTR PinName Source +PINATTR SpiceOrder 22 +PIN 224 -160 TOP 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 23 +PIN 336 -160 TOP 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 24 +PIN 112 -160 TOP 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 25 +PIN 0 -160 TOP 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 27 +PIN -224 -160 TOP 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 28 +PIN -112 -160 TOP 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 29 +PIN -336 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 31 +PIN -432 -96 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 32 diff --git a/spice/copy/sym/PowerProducts/LTC4283.asy b/spice/copy/sym/PowerProducts/LTC4283.asy new file mode 100755 index 0000000..1c5d375 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4283.asy @@ -0,0 +1,82 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -592 -224 592 224 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +WINDOW 123 0 80 Center 2 +WINDOW 39 0 112 Center 2 +WINDOW 40 0 144 Center 2 +SYMATTR Value LTC4283 +SYMATTR Value2 A6=1 A5=0 A4=1 A3=1 A2=0 B7=0 B6=0 B5=0 B4=0 B3=0 B2=0 B1=1 B0=1 +SYMATTR SpiceLine D7=0 D6=0 D5=0 D4=0 D3=0 D2=0 D1=0 D0=0 +SYMATTR SpiceLine2 E7=1 E6=1 E5=0 E4=0 E3=0 E2=0 E1=0 F7=0 +SYMATTR Prefix X +SYMATTR Description Negative Voltage Hot Swap Controller with Energy Monitor +SYMATTR ModelFile LTC4283.sub +PIN -592 160 LEFT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 1 +PIN -592 -96 LEFT 8 +PINATTR PinName UVL +PINATTR SpiceOrder 2 +PIN -592 -160 LEFT 8 +PINATTR PinName UVH +PINATTR SpiceOrder 3 +PIN -592 -32 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 4 +PIN 592 -192 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 5 +PIN 592 -128 RIGHT 8 +PINATTR PinName Voutth +PINATTR SpiceOrder 6 +PIN -480 224 BOTTOM 8 +PINATTR PinName Vee +PINATTR SpiceOrder 11 +PIN -288 224 BOTTOM 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 14 +PIN -176 224 BOTTOM 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 15 +PIN 176 224 BOTTOM 8 +PINATTR PinName Gate +PINATTR SpiceOrder 18 +PIN 448 224 BOTTOM 8 +PINATTR PinName Drain +PINATTR SpiceOrder 20 +PIN 592 192 RIGHT 8 +PINATTR PinName Drns +PINATTR SpiceOrder 21 +PIN 448 -224 TOP 8 +PINATTR PinName Rtns +PINATTR SpiceOrder 22 +PIN -592 96 LEFT 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 23 +PIN -592 32 LEFT 8 +PINATTR PinName Tmr +PINATTR SpiceOrder 24 +PIN 592 -64 RIGHT 8 +PINATTR PinName PGIO1 +PINATTR SpiceOrder 29 +PIN 592 0 RIGHT 8 +PINATTR PinName PGIO2 +PINATTR SpiceOrder 30 +PIN 592 64 RIGHT 8 +PINATTR PinName PGIO3 +PINATTR SpiceOrder 31 +PIN 592 128 RIGHT 8 +PINATTR PinName PGIO4 +PINATTR SpiceOrder 32 +PIN -480 -224 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 42 +PIN -144 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 43 +PIN -240 -224 TOP 8 +PINATTR PinName Vz +PINATTR SpiceOrder 44 diff --git a/spice/copy/sym/PowerProducts/LTC4284.asy b/spice/copy/sym/PowerProducts/LTC4284.asy new file mode 100755 index 0000000..0eeb5e2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4284.asy @@ -0,0 +1,94 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -640 -224 640 224 +TEXT 0 0 Center 2 LT +WINDOW 3 0 -41 Center 2 +WINDOW 0 0 41 Center 2 +WINDOW 123 0 80 Center 2 +WINDOW 39 0 112 Center 2 +WINDOW 40 0 144 Center 2 +SYMATTR Value LTC4284 +SYMATTR Value2 A6=1 A5=0 A4=1 A3=1 A2=0 B7=0 B6=0 B5=0 B4=0 B3=0 B2=0 B1=1 B0=1 +SYMATTR SpiceLine D7=0 D6=0 D5=0 D4=0 D3=0 D2=0 D1=0 D0=0 +SYMATTR SpiceLine2 E7=1 E6=1 E5=0 E4=0 E3=0 E2=0 E1=0 F7=0 +SYMATTR Prefix X +SYMATTR Description High Power Negative Voltage Hot Swap Controller with Power Monitor and EEPROM +SYMATTR ModelFile LTC4284.sub +PIN -640 160 LEFT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 1 +PIN -640 -96 LEFT 8 +PINATTR PinName UVL +PINATTR SpiceOrder 2 +PIN -640 -160 LEFT 8 +PINATTR PinName UVH +PINATTR SpiceOrder 3 +PIN -640 -32 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 4 +PIN 640 -192 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 5 +PIN 640 -128 RIGHT 8 +PINATTR PinName Voutth +PINATTR SpiceOrder 6 +PIN -528 224 BOTTOM 8 +PINATTR PinName Vee +PINATTR SpiceOrder 11 +PIN -400 224 BOTTOM 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 12 +PIN -288 224 BOTTOM 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 14 +PIN -176 224 BOTTOM 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 15 +PIN -64 224 BOTTOM 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 17 +PIN 176 224 BOTTOM 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 18 +PIN 304 224 BOTTOM 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 19 +PIN 480 224 BOTTOM 8 +PINATTR PinName Drain +PINATTR SpiceOrder 20 +PIN 640 192 RIGHT 8 +PINATTR PinName Drns +PINATTR SpiceOrder 21 +PIN 512 -224 TOP 8 +PINATTR PinName Rtns +PINATTR SpiceOrder 22 +PIN -640 96 LEFT 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 23 +PIN -640 32 LEFT 8 +PINATTR PinName Tmr +PINATTR SpiceOrder 24 +PIN 640 -64 RIGHT 8 +PINATTR PinName PGIO1 +PINATTR SpiceOrder 29 +PIN 640 0 RIGHT 8 +PINATTR PinName PGIO2 +PINATTR SpiceOrder 30 +PIN 640 64 RIGHT 8 +PINATTR PinName PGIO3 +PINATTR SpiceOrder 31 +PIN 640 128 RIGHT 8 +PINATTR PinName PGIO4 +PINATTR SpiceOrder 32 +PIN -432 -224 TOP 8 +PINATTR PinName Mode +PINATTR SpiceOrder 40 +PIN -528 -224 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 42 +PIN -144 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 43 +PIN -240 -224 TOP 8 +PINATTR PinName Vz +PINATTR SpiceOrder 44 diff --git a/spice/copy/sym/PowerProducts/LTC4354.asy b/spice/copy/sym/PowerProducts/LTC4354.asy new file mode 100755 index 0000000..7b26e11 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4354.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 96 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LTC4354 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4354.sub +SYMATTR Value2 LTC4354 +SYMATTR Description Negative Voltage Diode-OR Controller and Monitor +PIN -128 -80 LEFT 8 +PINATTR PinName DA +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 2 +PIN -128 -16 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -128 48 LEFT 8 +PINATTR PinName GA +PINATTR SpiceOrder 4 +PIN 128 48 RIGHT 8 +PINATTR PinName GB +PINATTR SpiceOrder 6 +PIN 128 -16 RIGHT 8 +PINATTR PinName FAULT +PINATTR SpiceOrder 7 +PIN 128 -80 RIGHT 8 +PINATTR PinName DB +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC4372.asy b/spice/copy/sym/PowerProducts/LTC4372.asy new file mode 100755 index 0000000..0e44a4e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4372.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -128 240 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 47 Center 2 +SYMATTR Value LTC4372 +SYMATTR SpiceModel LTC4372.sub +SYMATTR Description Low Quiescent Current Ideal Diode Controller +SYMATTR Value2 LTC4372 +SYMATTR Prefix X +PIN 192 -128 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 64 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 2 +PIN -64 -128 TOP 8 +PINATTR PinName SOURCE +PINATTR SpiceOrder 3 +PIN -192 -128 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 4 +PIN 0 128 BOTTOM 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 8 +PIN -160 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 160 128 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 5 +PIN -240 0 LEFT 8 +PINATTR PinName 2UPU +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LTC4373.asy b/spice/copy/sym/PowerProducts/LTC4373.asy new file mode 100755 index 0000000..54e3c62 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4373.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -128 240 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 47 Center 2 +SYMATTR Value LTC4373 +SYMATTR SpiceModel LTC4373.sub +SYMATTR Description Ideal Diode Controller with Reverse Input Protection +SYMATTR Value2 LTC4373 +SYMATTR Prefix X +PIN 192 -128 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 64 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 2 +PIN -32 -128 TOP 8 +PINATTR PinName SOURCE +PINATTR SpiceOrder 3 +PIN -192 -128 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 4 +PIN 160 128 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 5 +PIN -80 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -240 64 LEFT 8 +PINATTR PinName _UVOUT +PINATTR SpiceOrder 7 +PIN -240 -64 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC4376.asy b/spice/copy/sym/PowerProducts/LTC4376.asy new file mode 100755 index 0000000..8d598a0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4376.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -128 240 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 47 Center 2 +SYMATTR Value LTC4376 +SYMATTR SpiceModel LTC4376.sub +SYMATTR Description 7A Ideal Diode with Reverse Input Protection +SYMATTR Value2 LTC4376 +SYMATTR Prefix X +PIN 240 -96 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 17 +PIN -240 -96 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 4 +PIN -240 96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 12 +PIN 0 128 BOTTOM 8 +PINATTR PinName VSS +PINATTR SpiceOrder 6 +PIN -240 -48 LEFT 8 +PINATTR PinName CS +PINATTR SpiceOrder 9 +PIN -240 48 LEFT 8 +PINATTR PinName INK +PINATTR SpiceOrder 10 +PIN 240 0 RIGHT 8 +PINATTR PinName OUTK +PINATTR SpiceOrder 7 +PIN -240 0 LEFT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC4412.asy b/spice/copy/sym/PowerProducts/LTC4412.asy new file mode 100755 index 0000000..77c23da --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4412.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTC4412 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4412.sub +SYMATTR Value2 LTC4412 +SYMATTR Description Low Loss PowerPath Controller in ThinSOT +PIN -128 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 80 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName STAT +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 5 +PIN 128 -80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC4412HV.asy b/spice/copy/sym/PowerProducts/LTC4412HV.asy new file mode 100755 index 0000000..a0ecdfe --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4412HV.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTC4412HV +SYMATTR Prefix X +SYMATTR SpiceModel LTC4412.sub +SYMATTR Value2 LTC4412 +SYMATTR Description Low Loss PowerPath Controller in ThinSOT +PIN -128 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 80 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName STAT +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 5 +PIN 128 -80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC4418.asy b/spice/copy/sym/PowerProducts/LTC4418.asy new file mode 100755 index 0000000..d7578c8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4418.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -416 256 416 +TEXT 0 0 Center 2 LT +TEXT -176 389 Center 2 GND +TEXT 0 389 Center 2 HYS +TEXT 176 389 Center 2 TMR +WINDOW 0 0 -96 Center 2 +WINDOW 123 0 96 Center 2 +SYMATTR Value LTC4418 +SYMATTR SpiceModel LTC4418.sub +SYMATTR Description Dual Channel Prioritized PowerPath Controller +SYMATTR Value2 LTC4418 +SYMATTR Prefix X +PIN 256 224 RIGHT 10 +PINATTR PinName EN +PINATTR SpiceOrder 18 +PIN 256 336 RIGHT 10 +PINATTR PinName _SHDN +PINATTR SpiceOrder 19 +PIN 256 112 RIGHT 10 +PINATTR PinName IntVcc +PINATTR SpiceOrder 10 +PIN -256 -192 LEFT 10 +PINATTR PinName UV1 +PINATTR SpiceOrder 2 +PIN -256 -64 LEFT 10 +PINATTR PinName OV1 +PINATTR SpiceOrder 3 +PIN -256 192 LEFT 10 +PINATTR PinName UV2 +PINATTR SpiceOrder 4 +PIN -256 320 LEFT 10 +PINATTR PinName OV2 +PINATTR SpiceOrder 5 +PIN 0 416 NONE 0 +PINATTR PinName HYS +PINATTR SpiceOrder 20 +PIN 176 416 NONE 0 +PINATTR PinName TMR +PINATTR SpiceOrder 1 +PIN 256 -224 RIGHT 10 +PINATTR PinName _VALID1 +PINATTR SpiceOrder 6 +PIN 256 -112 RIGHT 10 +PINATTR PinName _VALID2 +PINATTR SpiceOrder 7 +PIN -176 416 NONE 0 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 256 0 RIGHT 10 +PINATTR PinName CAS +PINATTR SpiceOrder 9 +PIN 256 -336 RIGHT 10 +PINATTR PinName Vout +PINATTR SpiceOrder 15 +PIN 176 -416 TOP 10 +PINATTR PinName G2 +PINATTR SpiceOrder 11 +PIN 96 -416 TOP 10 +PINATTR PinName VS2 +PINATTR SpiceOrder 12 +PIN -96 -416 TOP 10 +PINATTR PinName G1 +PINATTR SpiceOrder 13 +PIN -176 -416 TOP 10 +PINATTR PinName VS1 +PINATTR SpiceOrder 14 +PIN -256 64 LEFT 10 +PINATTR PinName V2 +PINATTR SpiceOrder 16 +PIN -256 -320 LEFT 10 +PINATTR PinName V1 +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTC4419.asy b/spice/copy/sym/PowerProducts/LTC4419.asy new file mode 100755 index 0000000..76e390b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4419.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC4419 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4419.sub +SYMATTR Value2 LTC4419 +SYMATTR Description 18V Dual Input µPower PowerPath Prioritizer +PIN -160 -128 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -160 32 LEFT 8 +PINATTR PinName Cmp1 +PINATTR SpiceOrder 2 +PIN -160 -48 LEFT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 3 +PIN 0 240 BOTTOM 4 +PINATTR PinName Gnd +PINATTR SpiceOrder 4 +PIN 160 -48 RIGHT 8 +PINATTR PinName Cmpout1 +PINATTR SpiceOrder 5 +PIN 160 32 RIGHT 8 +PINATTR PinName Cmpout2 +PINATTR SpiceOrder 6 +PIN 160 192 RIGHT 8 +PINATTR PinName V2on +PINATTR SpiceOrder 7 +PIN 160 -128 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 8 +PIN -160 192 LEFT 8 +PINATTR PinName Cmp2 +PINATTR SpiceOrder 9 +PIN -160 112 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC4420.asy b/spice/copy/sym/PowerProducts/LTC4420.asy new file mode 100755 index 0000000..b7cd320 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4420.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -208 160 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC4420 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4420.sub +SYMATTR Value2 LTC4420 +SYMATTR Description 18V Dual Input µPower PowerPath Prioritizer with Backup Supply Monitoring +PIN -160 -160 LEFT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName Cmp1 +PINATTR SpiceOrder 2 +PIN -160 -80 LEFT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 3 +PIN 0 288 BOTTOM 4 +PINATTR PinName Gnd +PINATTR SpiceOrder 4 +PIN 160 -64 RIGHT 8 +PINATTR PinName Cmpout1 +PINATTR SpiceOrder 5 +PIN 160 -160 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 8 +PIN -160 160 LEFT 8 +PINATTR PinName v2uv +PINATTR SpiceOrder 11 +PIN -160 80 LEFT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 10 +PIN -160 240 LEFT 8 +PINATTR PinName Gndsw +PINATTR SpiceOrder 12 +PIN 160 32 RIGHT 8 +PINATTR PinName V2ok +PINATTR SpiceOrder 7 +PIN 160 128 RIGHT 8 +PINATTR PinName _v2dis +PINATTR SpiceOrder 9 +PIN 160 224 RIGHT 8 +PINATTR PinName v2test +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC4421.asy b/spice/copy/sym/PowerProducts/LTC4421.asy new file mode 100755 index 0000000..cd973ba --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4421.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -704 -400 705 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 123 0 96 Center 2 +SYMATTR Value2 LTC4421 +SYMATTR Value LTC4421 +SYMATTR SpiceModel LTC4421.sub +SYMATTR Description High Power Prioritized PowerPath Controller +SYMATTR Prefix X +PIN -48 -400 VRIGHT 10 +PINATTR PinName CPO +PINATTR SpiceOrder 1 +PIN 48 -400 VRIGHT 10 +PINATTR PinName CPORef +PINATTR SpiceOrder 2 +PIN -160 -400 VRIGHT 10 +PINATTR PinName Out1 +PINATTR SpiceOrder 3 +PIN -256 -400 VRIGHT 10 +PINATTR PinName Sense1 +PINATTR SpiceOrder 4 +PIN -384 -400 VRIGHT 10 +PINATTR PinName Source1 +PINATTR SpiceOrder 5 +PIN -480 -400 VRIGHT 10 +PINATTR PinName Gate1 +PINATTR SpiceOrder 6 +PIN -576 -400 VRIGHT 10 +PINATTR PinName V1 +PINATTR SpiceOrder 7 +PIN -704 -336 LEFT 10 +PINATTR PinName UVF1 +PINATTR SpiceOrder 8 +PIN -704 -208 LEFT 10 +PINATTR PinName UVR1 +PINATTR SpiceOrder 9 +PIN -704 -80 LEFT 10 +PINATTR PinName OV1 +PINATTR SpiceOrder 10 +PIN 0 400 BOTTOM 8 +PINATTR PinName Tmr1 +PINATTR SpiceOrder 11 +PIN 704 208 RIGHT 10 +PINATTR PinName _DISABLE1 +PINATTR SpiceOrder 12 +PIN 704 -128 RIGHT 10 +PINATTR PinName _CH1 +PINATTR SpiceOrder 13 +PIN 704 -224 RIGHT 10 +PINATTR PinName _VALID1 +PINATTR SpiceOrder 14 +PIN 704 -32 RIGHT 10 +PINATTR PinName _FAULT1 +PINATTR SpiceOrder 15 +PIN 704 352 RIGHT 10 +PINATTR PinName CASIN +PINATTR SpiceOrder 16 +PIN 352 400 BOTTOM 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 17 +PIN 704 64 RIGHT 10 +PINATTR PinName CASOUT +PINATTR SpiceOrder 18 +PIN -176 400 BOTTOM 8 +PINATTR PinName Qual +PINATTR SpiceOrder 19 +PIN 704 160 RIGHT 10 +PINATTR PinName RETRY +PINATTR SpiceOrder 20 +PIN 704 304 RIGHT 10 +PINATTR PinName _SHDN +PINATTR SpiceOrder 21 +PIN 704 16 RIGHT 10 +PINATTR PinName _FAULT2 +PINATTR SpiceOrder 22 +PIN 704 -176 RIGHT 10 +PINATTR PinName _VALID2 +PINATTR SpiceOrder 23 +PIN 704 -80 RIGHT 10 +PINATTR PinName _CH2 +PINATTR SpiceOrder 24 +PIN 704 256 RIGHT 10 +PINATTR PinName _DISABLE2 +PINATTR SpiceOrder 25 +PIN 176 400 BOTTOM 8 +PINATTR PinName Tmr2 +PINATTR SpiceOrder 26 +PIN -704 304 LEFT 10 +PINATTR PinName OV2 +PINATTR SpiceOrder 27 +PIN -704 176 LEFT 10 +PINATTR PinName UVR2 +PINATTR SpiceOrder 28 +PIN -704 48 LEFT 10 +PINATTR PinName UVF2 +PINATTR SpiceOrder 29 +PIN 160 -400 VRIGHT 10 +PINATTR PinName V2 +PINATTR SpiceOrder 30 +PIN 256 -400 VRIGHT 10 +PINATTR PinName Gate2 +PINATTR SpiceOrder 31 +PIN 352 -400 VRIGHT 10 +PINATTR PinName Source2 +PINATTR SpiceOrder 32 +PIN 480 -400 VRIGHT 10 +PINATTR PinName Sense2 +PINATTR SpiceOrder 33 +PIN 576 -400 VRIGHT 10 +PINATTR PinName Out2 +PINATTR SpiceOrder 34 +PIN -352 400 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 35 +PIN 704 -304 RIGHT 10 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 36 diff --git a/spice/copy/sym/PowerProducts/LTC4440-5.asy b/spice/copy/sym/PowerProducts/LTC4440-5.asy new file mode 100755 index 0000000..e713912 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4440-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC4440-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4440-5.sub +SYMATTR Value2 LTC4440-5 +SYMATTR Description High Speed, High Voltage High side Gate Driver +PIN -128 -80 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN -128 80 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName INP +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 5 +PIN 128 -80 RIGHT 8 +PINATTR PinName BOOST +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC4440.asy b/spice/copy/sym/PowerProducts/LTC4440.asy new file mode 100755 index 0000000..84c70d3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4440.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC4440 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4440.sub +SYMATTR Value2 LTC4440 +SYMATTR Description High Speed, High Voltage High side Gate Driver +PIN -128 -80 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN -128 80 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName INP +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 5 +PIN 128 -80 RIGHT 8 +PINATTR PinName BOOST +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC4440A-5.asy b/spice/copy/sym/PowerProducts/LTC4440A-5.asy new file mode 100755 index 0000000..2f6e258 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4440A-5.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC4440A-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4440-5.sub +SYMATTR Value2 LTC4440-5 +SYMATTR Description High Speed, High Voltage, High Side Gate Driver +PIN -128 -80 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN -128 80 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName INP +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 4 +PIN 128 0 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 5 +PIN 128 -80 RIGHT 8 +PINATTR PinName BOOST +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTC4441-1.asy b/spice/copy/sym/PowerProducts/LTC4441-1.asy new file mode 100755 index 0000000..75f957e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4441-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 0 55 Center 2 +SYMATTR Value LTC4441-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4441-1.sub +SYMATTR Value2 LTC4441-1 +SYMATTR Description N-Channel MOSFET Gate Driver +PIN 160 96 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 2 +PIN -160 96 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName EN/SHDN +PINATTR SpiceOrder 4 +PIN -160 -96 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 160 -96 RIGHT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 7 +PIN 160 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC4441.asy b/spice/copy/sym/PowerProducts/LTC4441.asy new file mode 100755 index 0000000..063b099 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4441.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -105 Center 2 +WINDOW 3 0 87 Center 2 +SYMATTR Value LTC4441 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4441.sub +SYMATTR Value2 LTC4441 +SYMATTR Description N-Channel MOSFET Gate Driver +PIN 160 48 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 160 144 RIGHT 8 +PINATTR PinName Blank +PINATTR SpiceOrder 2 +PIN -160 144 LEFT 8 +PINATTR PinName Rblank +PINATTR SpiceOrder 3 +PIN 0 192 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN -160 48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName EN/SHDN +PINATTR SpiceOrder 6 +PIN -160 -144 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 +PIN 160 -144 RIGHT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 9 +PIN 160 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC4442-1.asy b/spice/copy/sym/PowerProducts/LTC4442-1.asy new file mode 100755 index 0000000..6f11eed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4442-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC4442-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4442-1.sub +SYMATTR Value2 LTC4442-1 +SYMATTR Description High Speed Synchronous N-Channel MOSFET Driver +PIN 128 -80 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 2 +PIN 128 80 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName Vlogic +PINATTR SpiceOrder 6 +PIN -128 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC4442.asy b/spice/copy/sym/PowerProducts/LTC4442.asy new file mode 100755 index 0000000..6546bda --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4442.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC4442 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4442.sub +SYMATTR Value2 LTC4442 +SYMATTR Description High Speed Synchronous N-Channel MOSFET Driver +PIN 128 -80 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 2 +PIN 128 80 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 3 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -128 80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName Vlogic +PINATTR SpiceOrder 6 +PIN -128 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC4444-5.asy b/spice/copy/sym/PowerProducts/LTC4444-5.asy new file mode 100755 index 0000000..372f577 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4444-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC4444-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4444-5.sub +SYMATTR Value2 LTC4444-5 +SYMATTR Description High Voltage Synchronous N-Channel MOSFET Driver +PIN -128 0 LEFT 8 +PINATTR PinName Tinp +PINATTR SpiceOrder 1 +PIN -128 80 LEFT 8 +PINATTR PinName Binp +PINATTR SpiceOrder 2 +PIN -128 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 128 -80 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC4444.asy b/spice/copy/sym/PowerProducts/LTC4444.asy new file mode 100755 index 0000000..875155b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4444.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC4444 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4444.sub +SYMATTR Value2 LTC4444 +SYMATTR Description High Voltage Synchronous N-Channel MOSFET Driver +PIN -128 0 LEFT 8 +PINATTR PinName Tinp +PINATTR SpiceOrder 1 +PIN -128 80 LEFT 8 +PINATTR PinName Binp +PINATTR SpiceOrder 2 +PIN -128 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 128 -80 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC4446.asy b/spice/copy/sym/PowerProducts/LTC4446.asy new file mode 100755 index 0000000..63dfbe7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4446.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC4446 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4446.sub +SYMATTR Value2 LTC4446 +SYMATTR Description High Voltage High Side/ Low Side N-Channel MOSFET Driver +PIN -128 0 LEFT 8 +PINATTR PinName Tinp +PINATTR SpiceOrder 1 +PIN -128 80 LEFT 8 +PINATTR PinName Binp +PINATTR SpiceOrder 2 +PIN -128 -80 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 6 +PIN 128 -80 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 8 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC4449.asy b/spice/copy/sym/PowerProducts/LTC4449.asy new file mode 100755 index 0000000..c180e0d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC4449.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC4449 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4449.sub +SYMATTR Value2 LTC4449 +SYMATTR Description High Speed Synchronous N-Channel MOSFET Driver +PIN 128 -80 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 4 +PIN 128 80 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 5 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -128 80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 7 +PIN -128 -80 LEFT 8 +PINATTR PinName Vlogic +PINATTR SpiceOrder 8 +PIN -128 0 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 9 +PIN 0 -144 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTC660.asy b/spice/copy/sym/PowerProducts/LTC660.asy new file mode 100755 index 0000000..36397d1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC660.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC660 +SYMATTR Prefix X +SYMATTR SpiceModel LTC660.sub +SYMATTR Value2 LTC660 +SYMATTR Description 100mA CMOS Voltage Converter +PIN -128 -96 LEFT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Cap+ +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName Cap- +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName LV +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName OSC +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTC7000-1.asy b/spice/copy/sym/PowerProducts/LTC7000-1.asy new file mode 100755 index 0000000..52e704c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7000-1.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -224 256 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC7000-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7000-1.sub +SYMATTR Value2 LTC7000-1 +SYMATTR Description Fast 150V Protected High Side NMOS Static Switch Driver +PIN -256 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 256 -32 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -256 80 LEFT 8 +PINATTR PinName Vccuv +PINATTR SpiceOrder 4 +PIN 256 80 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -256 160 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN -144 224 BOTTOM 8 +PINATTR PinName INP +PINATTR SpiceOrder 7 +PIN 112 -224 TOP 8 +PINATTR PinName TGdn +PINATTR SpiceOrder 11 +PIN 16 -224 TOP 8 +PINATTR PinName TGup +PINATTR SpiceOrder 12 +PIN 224 -224 TOP 8 +PINATTR PinName TS +PINATTR SpiceOrder 13 +PIN 256 -128 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 14 +PIN -96 -224 TOP 8 +PINATTR PinName SNS- +PINATTR SpiceOrder 15 +PIN -192 -224 TOP 8 +PINATTR PinName SNS+ +PINATTR SpiceOrder 16 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTC7000.asy b/spice/copy/sym/PowerProducts/LTC7000.asy new file mode 100755 index 0000000..a87eb4d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7000.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -224 256 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC7000 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7000.sub +SYMATTR Value2 LTC7000 +SYMATTR Description Fast 150V Protected High Side NMOS Static Switch Driver +PIN -256 -80 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 1 +PIN -256 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 256 -32 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -256 80 LEFT 8 +PINATTR PinName Vccuv +PINATTR SpiceOrder 4 +PIN 256 80 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -256 160 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN -144 224 BOTTOM 8 +PINATTR PinName INP +PINATTR SpiceOrder 7 +PIN -256 0 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 8 +PIN 128 224 BOTTOM 8 +PINATTR PinName Iset +PINATTR SpiceOrder 9 +PIN 256 160 RIGHT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 10 +PIN 112 -224 TOP 8 +PINATTR PinName TGdn +PINATTR SpiceOrder 11 +PIN 16 -224 TOP 8 +PINATTR PinName TGup +PINATTR SpiceOrder 12 +PIN 224 -224 TOP 8 +PINATTR PinName TS +PINATTR SpiceOrder 13 +PIN 256 -128 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 14 +PIN -96 -224 TOP 8 +PINATTR PinName SNS- +PINATTR SpiceOrder 15 +PIN -192 -224 TOP 8 +PINATTR PinName SNS+ +PINATTR SpiceOrder 16 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTC7001.asy b/spice/copy/sym/PowerProducts/LTC7001.asy new file mode 100755 index 0000000..63fbff1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7001.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -146 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC7001 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7001.sub +SYMATTR Value2 LTC7001 +SYMATTR Description Fast 150V High Side NMOS Static Switch Driver +PIN -144 -128 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 32 LEFT 8 +PINATTR PinName Vccuv +PINATTR SpiceOrder 2 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 -48 LEFT 8 +PINATTR PinName INP +PINATTR SpiceOrder 4 +PIN -144 112 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName TGdn +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName TGup +PINATTR SpiceOrder 7 +PIN 144 112 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 8 +PIN 144 -128 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC7003.asy b/spice/copy/sym/PowerProducts/LTC7003.asy new file mode 100755 index 0000000..783daad --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7003.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -224 256 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC7003 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7003.sub +SYMATTR Value2 LTC7003 +SYMATTR Description Fast 60V Protected High Side NMOS Static Switch Driver +PIN -256 -80 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 1 +PIN -256 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 256 -32 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -256 80 LEFT 8 +PINATTR PinName Vccuv +PINATTR SpiceOrder 4 +PIN 256 80 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -256 160 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN -144 224 BOTTOM 8 +PINATTR PinName INP +PINATTR SpiceOrder 7 +PIN -256 0 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 8 +PIN 128 224 BOTTOM 8 +PINATTR PinName Iset +PINATTR SpiceOrder 9 +PIN 256 160 RIGHT 8 +PINATTR PinName Imon +PINATTR SpiceOrder 10 +PIN 112 -224 TOP 8 +PINATTR PinName TGdn +PINATTR SpiceOrder 11 +PIN 16 -224 TOP 8 +PINATTR PinName TGup +PINATTR SpiceOrder 12 +PIN 224 -224 TOP 8 +PINATTR PinName TS +PINATTR SpiceOrder 13 +PIN 256 -128 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 14 +PIN -96 -224 TOP 8 +PINATTR PinName SNS- +PINATTR SpiceOrder 15 +PIN -192 -224 TOP 8 +PINATTR PinName SNS+ +PINATTR SpiceOrder 16 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTC7004.asy b/spice/copy/sym/PowerProducts/LTC7004.asy new file mode 100755 index 0000000..3133539 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7004.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC7004 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7004.sub +SYMATTR Value2 LTC7004 +SYMATTR Description Fast 60V High Side NMOS Static Switch Driver +PIN -144 -128 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 32 LEFT 8 +PINATTR PinName Vccuv +PINATTR SpiceOrder 2 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 -48 LEFT 8 +PINATTR PinName INP +PINATTR SpiceOrder 4 +PIN -144 112 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName TGdn +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName TGup +PINATTR SpiceOrder 7 +PIN 144 112 RIGHT 8 +PINATTR PinName TS +PINATTR SpiceOrder 8 +PIN 144 -128 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTC7050-1.asy b/spice/copy/sym/PowerProducts/LTC7050-1.asy new file mode 100755 index 0000000..b690496 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7050-1.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -336 144 336 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC7050-1 +SYMATTR Prefix X +SYMATTR Value2 LTC7050-1 RTon=8m RBon=1.5m OV=18 +SYMATTR Description Dual 30A Monolithic Driver and Half Bridge with Current Sense and Temperature Monitor +SYMATTR SpiceModel LTC7050-1.sub +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 2 +PIN -144 96 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 3 +PIN 144 288 RIGHT 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN -144 192 LEFT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 7 +PIN -144 288 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 8 +PIN -144 -192 LEFT 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 9 +PIN -144 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 144 -288 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 11 +PIN 0 336 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 144 -192 RIGHT 8 +PINATTR PinName Isns1 +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Fltb1 +PINATTR SpiceOrder 14 +PIN 144 192 RIGHT 8 +PINATTR PinName Fltb2 +PINATTR SpiceOrder 15 +PIN 144 96 RIGHT 8 +PINATTR PinName Isns2 +PINATTR SpiceOrder 16 +PIN 144 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTC7050.asy b/spice/copy/sym/PowerProducts/LTC7050.asy new file mode 100755 index 0000000..ac4b088 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7050.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -336 144 336 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC7050 +SYMATTR Prefix X +SYMATTR Value2 LTC7050 RTon=5m RBon=1.2m OV=14.8 +SYMATTR Description Dual 30A Monolithic Driver and Half Bridge with Current Sense and Temperature Monitor +SYMATTR SpiceModel LTC7050.sub +PIN -144 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 2 +PIN -144 96 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 3 +PIN 144 288 RIGHT 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN -144 192 LEFT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 7 +PIN -144 288 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 8 +PIN -144 -192 LEFT 8 +PINATTR PinName PVcc +PINATTR SpiceOrder 9 +PIN -144 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN 144 -288 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 11 +PIN 0 336 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 12 +PIN 144 -192 RIGHT 8 +PINATTR PinName Isns1 +PINATTR SpiceOrder 13 +PIN 144 -96 RIGHT 8 +PINATTR PinName Fltb1 +PINATTR SpiceOrder 14 +PIN 144 192 RIGHT 8 +PINATTR PinName Fltb2 +PINATTR SpiceOrder 15 +PIN 144 96 RIGHT 8 +PINATTR PinName Isns2 +PINATTR SpiceOrder 16 +PIN 144 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTC7060.asy b/spice/copy/sym/PowerProducts/LTC7060.asy new file mode 100755 index 0000000..a921e44 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7060.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -257 160 255 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC7060 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7060.sub +SYMATTR Value2 LTC7060 +SYMATTR Description 100V Half Bridge Driver with Floating Grounds and Programmable Dead-Time +PIN -160 96 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 1 +PIN -160 -96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN -160 0 LEFT 8 +PINATTR PinName _FLT +PINATTR SpiceOrder 3 +PIN -160 192 LEFT 8 +PINATTR PinName DT +PINATTR SpiceOrder 4 +PIN 0 -256 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN -160 -192 LEFT 8 +PINATTR PinName BGVcc +PINATTR SpiceOrder 6 +PIN 160 192 RIGHT 8 +PINATTR PinName BGRTN +PINATTR SpiceOrder 7 +PIN 160 96 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 9 +PIN 160 -96 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 10 +PIN 160 -192 RIGHT 8 +PINATTR PinName BST +PINATTR SpiceOrder 11 +PIN 0 256 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LTC7103.asy b/spice/copy/sym/PowerProducts/LTC7103.asy new file mode 100755 index 0000000..4a45e5b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7103.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -320 192 336 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC7103 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7103.sub +SYMATTR Value2 LTC7103 +SYMATTR Description 105V, 2.3A Low EMI Synchronous Step-Down Regulator +PIN 192 -160 RIGHT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 +PIN -192 0 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -128 -320 TOP 8 +PINATTR PinName ICTRL +PINATTR SpiceOrder 16 +PIN 192 80 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 0 336 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 35 +PIN -192 240 LEFT 8 +PINATTR PinName PLLin/Mode +PINATTR SpiceOrder 12 +PIN -192 80 LEFT 8 +PINATTR PinName Rind +PINATTR SpiceOrder 8 +PIN -128 336 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN -192 160 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 15 +PIN 192 -80 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 10 +PIN 0 -320 TOP 8 +PINATTR PinName Imon +PINATTR SpiceOrder 17 +PIN 192 0 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 9 +PIN 128 -320 TOP 8 +PINATTR PinName PGood +PINATTR SpiceOrder 14 +PIN 192 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 24 +PIN -192 -160 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 3 +PIN -192 -80 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 7 +PIN 192 160 RIGHT 8 +PINATTR PinName VPRG1 +PINATTR SpiceOrder 18 +PIN 192 240 RIGHT 8 +PINATTR PinName VPRG2 +PINATTR SpiceOrder 19 +PIN 128 336 BOTTOM 8 +PINATTR PinName CLKOut +PINATTR SpiceOrder 13 +PIN -192 -240 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 30 diff --git a/spice/copy/sym/PowerProducts/LTC7124.asy b/spice/copy/sym/PowerProducts/LTC7124.asy new file mode 100755 index 0000000..f35f4a7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7124.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 288 -176 -288 +TEXT 0 0 Center 2 LT +WINDOW 3 0 112 Center 2 +WINDOW 0 0 -112 Center 2 +SYMATTR Value LTC7124 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7124.sub +SYMATTR Value2 LTC7124 +SYMATTR Description 17V, Dual 3.5A Synchronous Step-Down Regulator with Ultralow Quiescent Current +PIN 96 288 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -64 -288 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 3 +PIN 0 288 BOTTOM 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 4 +PIN -96 288 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 5 +PIN 64 -288 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 6 +PIN 176 240 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN 176 -80 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 10 +PIN 176 0 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 11 +PIN 176 -240 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 13 +PIN 176 80 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 15 +PIN -176 -160 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 16 +PIN 176 -160 RIGHT 8 +PINATTR PinName Mode/Sync +PINATTR SpiceOrder 17 +PIN -176 80 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 18 +PIN -176 160 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 19 +PIN -176 -240 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 21 +PIN -176 0 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 22 +PIN -176 -80 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 23 +PIN -176 240 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LTC7130.asy b/spice/copy/sym/PowerProducts/LTC7130.asy new file mode 100755 index 0000000..9409c9c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7130.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -496 176 496 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTC7130 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7130.sub +SYMATTR Value2 LTC7130 +SYMATTR Description 20V 20A Monolithic Buck Converter with Ultralow DCR Sensing +PIN -176 -48 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 1 +PIN -176 -432 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 2 +PIN -176 48 LEFT 8 +PINATTR PinName TK/SS +PINATTR SpiceOrder 3 +PIN -176 144 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 4 +PIN 176 432 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 5 +PIN 176 336 RIGHT 8 +PINATTR PinName DIFFOut +PINATTR SpiceOrder 6 +PIN 176 240 RIGHT 8 +PINATTR PinName DIFFN +PINATTR SpiceOrder 7 +PIN 176 144 RIGHT 8 +PINATTR PinName DIFFP +PINATTR SpiceOrder 8 +PIN 176 -144 RIGHT 8 +PINATTR PinName SNSD+ +PINATTR SpiceOrder 9 +PIN 176 -48 RIGHT 8 +PINATTR PinName SNS- +PINATTR SpiceOrder 10 +PIN 176 48 RIGHT 8 +PINATTR PinName SNSA+ +PINATTR SpiceOrder 11 +PIN -176 -144 LEFT 8 +PINATTR PinName ILim +PINATTR SpiceOrder 12 +PIN -176 336 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 13 +PIN 0 496 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 14 +PIN 176 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 16 +PIN 176 -336 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 18 +PIN 0 -496 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 19 +PIN -96 -496 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 20 +PIN 96 -496 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 21 +PIN -176 240 LEFT 8 +PINATTR PinName ITemp +PINATTR SpiceOrder 22 +PIN -176 -336 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 23 +PIN -176 -240 LEFT 8 +PINATTR PinName Mode/PLLIn +PINATTR SpiceOrder 24 +PIN -176 432 LEFT 8 +PINATTR PinName SGND +PINATTR SpiceOrder 25 +PIN 176 -432 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTC7132.asy b/spice/copy/sym/PowerProducts/LTC7132.asy new file mode 100755 index 0000000..d38d116 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7132.asy @@ -0,0 +1,108 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -464 256 640 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 242 Center 2 +SYMATTR Value LTC7132 +SYMATTR Prefix X +SYMATTR Description 25A, Dual PolyPhase Step-Down DC/DC Regulator with Sub-Milliohm DCR Sensing and Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTC7132.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=2 Fault_response=0 Retry_delay=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K LowDcr=1 +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 Sync=0 +PIN 256 0 RIGHT 8 +PINATTR PinName Vsense0+ +PINATTR SpiceOrder 1 +PIN 256 96 RIGHT 8 +PINATTR PinName Vsense0- +PINATTR SpiceOrder 2 +PIN -256 -192 LEFT 8 +PINATTR PinName Isense1+ +PINATTR SpiceOrder 3 +PIN -256 -96 LEFT 8 +PINATTR PinName Isense1- +PINATTR SpiceOrder 4 +PIN 256 288 RIGHT 8 +PINATTR PinName IthR0 +PINATTR SpiceOrder 5 +PIN 256 192 RIGHT 8 +PINATTR PinName Ith0 +PINATTR SpiceOrder 6 +PIN 256 -192 RIGHT 8 +PINATTR PinName Isense0+ +PINATTR SpiceOrder 7 +PIN 256 -96 RIGHT 8 +PINATTR PinName Isense0- +PINATTR SpiceOrder 8 +PIN 96 640 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 11 +PIN 192 640 BOTTOM 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 17 +PIN -192 640 BOTTOM 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 18 +PIN 256 384 RIGHT 8 +PINATTR PinName Vout_cfg0 +PINATTR SpiceOrder 21 +PIN -256 384 LEFT 8 +PINATTR PinName Vout_cfg1 +PINATTR SpiceOrder 22 +PIN 256 480 RIGHT 8 +PINATTR PinName Freq_cfg +PINATTR SpiceOrder 23 +PIN -256 480 LEFT 8 +PINATTR PinName Phase_cfg +PINATTR SpiceOrder 24 +PIN -96 640 BOTTOM 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 25 +PIN 0 640 BOTTOM 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 28 +PIN -256 192 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 29 +PIN -256 288 LEFT 8 +PINATTR PinName IthR1 +PINATTR SpiceOrder 30 +PIN -256 96 LEFT 8 +PINATTR PinName Vsense1- +PINATTR SpiceOrder 31 +PIN -256 0 LEFT 8 +PINATTR PinName Vsense1+ +PINATTR SpiceOrder 32 +PIN -256 576 LEFT 8 +PINATTR PinName PGood1 +PINATTR SpiceOrder 33 +PIN -256 -288 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN -256 -384 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 36 +PIN -96 -464 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 38 +PIN -192 -464 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 39 +PIN 192 -464 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 40 +PIN 0 -464 TOP 8 +PINATTR PinName PGND +PINATTR SpiceOrder 41 +PIN 256 -384 RIGHT 8 +PINATTR PinName Boost0 +PINATTR SpiceOrder 43 +PIN 256 -288 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 45 +PIN 256 576 RIGHT 8 +PINATTR PinName PGood0 +PINATTR SpiceOrder 48 +PIN 96 -464 TOP 8 +PINATTR PinName SGND +PINATTR SpiceOrder 49 diff --git a/spice/copy/sym/PowerProducts/LTC7138.asy b/spice/copy/sym/PowerProducts/LTC7138.asy new file mode 100755 index 0000000..829df5b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7138.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -256 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC7138 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7138.sub +SYMATTR Value2 LTC7138 +SYMATTR Description High Efficiency, 140V 400mA Step-Down Regulator +PIN 144 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 2 +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 -96 RIGHT 8 +PINATTR PinName Anode +PINATTR SpiceOrder 4 +PIN -144 -192 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -144 192 LEFT 8 +PINATTR PinName Vprg2 +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName Vprg1 +PINATTR SpiceOrder 7 +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 144 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName Iset +PINATTR SpiceOrder 11 +PIN 144 192 RIGHT 8 +PINATTR PinName FBO +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LTC7149.asy b/spice/copy/sym/PowerProducts/LTC7149.asy new file mode 100755 index 0000000..6dfe529 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7149.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 208 256 -208 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 128 Center 2 +WINDOW 0 0 -128 Center 2 +SYMATTR Value LTC7149 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7149.sub +SYMATTR Value2 LTC7149 +SYMATTR Description 60V, 4A Synchronous Step-Down Regulator with Rail-to-Rail Programmable Inverting Output +PIN 128 256 BOTTOM 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 1 +PIN -112 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -208 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -128 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -208 192 LEFT 8 +PINATTR PinName Mode/SYNC +PINATTR SpiceOrder 7 +PIN -208 0 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN 208 96 RIGHT 8 +PINATTR PinName PGDFB +PINATTR SpiceOrder 9 +PIN 208 192 RIGHT 8 +PINATTR PinName SVout- +PINATTR SpiceOrder 10 +PIN -208 -192 LEFT 8 +PINATTR PinName VinREG +PINATTR SpiceOrder 11 +PIN -208 96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 12 +PIN 208 -192 RIGHT 8 +PINATTR PinName Voutsns +PINATTR SpiceOrder 13 +PIN 48 256 BOTTOM 8 +PINATTR PinName Iset +PINATTR SpiceOrder 14 +PIN -48 256 BOTTOM 8 +PINATTR PinName Ith +PINATTR SpiceOrder 15 +PIN 112 -256 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 16 +PIN 0 -256 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 17 +PIN 208 -96 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 18 +PIN 208 0 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LTC7150S.asy b/spice/copy/sym/PowerProducts/LTC7150S.asy new file mode 100755 index 0000000..79cb1dc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7150S.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 240 -176 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 72 Center 2 +WINDOW 0 0 -88 Center 2 +SYMATTR Value LTC7150S +SYMATTR Prefix X +SYMATTR SpiceModel LTC7150S.sub +SYMATTR Value2 LTC7150S +SYMATTR Description 20V, 20A Synchronous Step-Down Regulator +PIN -176 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -176 112 LEFT 8 +PINATTR PinName PhMode +PINATTR SpiceOrder 2 +PIN 176 112 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -176 -128 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 5 +PIN 176 192 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN -176 -208 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN 176 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN 64 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 176 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 11 +PIN 64 -256 TOP 8 +PINATTR PinName PVin +PINATTR SpiceOrder 17 +PIN -64 -256 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 19 +PIN 176 -128 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN -64 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 22 +PIN -176 32 LEFT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 23 +PIN -176 -48 LEFT 8 +PINATTR PinName SYNC/Mode +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LTC7151S.asy b/spice/copy/sym/PowerProducts/LTC7151S.asy new file mode 100755 index 0000000..acb6694 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7151S.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 240 -176 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 72 Center 2 +WINDOW 0 0 -88 Center 2 +SYMATTR Value LTC7151S +SYMATTR Prefix X +SYMATTR SpiceModel LTC7151S.sub +SYMATTR Value2 LTC7151S +SYMATTR Description 20V, 15A Synchronous Step-Down Silent Switcher 2 Regulator +PIN -176 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN -176 112 LEFT 8 +PINATTR PinName PhMode +PINATTR SpiceOrder 2 +PIN 176 112 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -176 -128 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 5 +PIN 176 192 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN -176 -208 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN 176 -208 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN 0 240 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 10 +PIN 176 -48 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 11 +PIN 64 -256 TOP 8 +PINATTR PinName PVin +PINATTR SpiceOrder 17 +PIN -64 -256 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 19 +PIN 176 -128 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN -176 32 LEFT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 23 +PIN -176 -48 LEFT 8 +PINATTR PinName Mode/Sync +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LTC7800.asy b/spice/copy/sym/PowerProducts/LTC7800.asy new file mode 100755 index 0000000..b65fbaf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7800.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -352 192 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -143 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC7800 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7800.sub +SYMATTR Value2 LTC7800 +SYMATTR Description Low Iq, 60V High Frequency Synchronous Step-Down Controller +PIN 192 192 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 1 +PIN -192 0 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 2 +PIN -192 96 LEFT 8 +PINATTR PinName PLLIN/Mode +PINATTR SpiceOrder 5 +PIN -80 352 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN -192 -288 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN 0 -352 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 19 +PIN 96 -352 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 +PIN 80 352 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 21 +PIN -96 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 22 +PIN 192 0 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 23 +PIN 192 -192 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 24 +PIN 192 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 25 +PIN 192 -288 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 26 +PIN -192 -192 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 27 +PIN -192 -96 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 28 +PIN -192 192 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 29 +PIN -192 288 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 30 +PIN 192 288 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 31 +PIN 192 96 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 32 diff --git a/spice/copy/sym/PowerProducts/LTC7801.asy b/spice/copy/sym/PowerProducts/LTC7801.asy new file mode 100755 index 0000000..09d9d68 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7801.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -496 192 464 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -175 Center 2 +WINDOW 3 0 160 Center 2 +SYMATTR Value LTC7801 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7801.sub +SYMATTR Value2 LTC7801 +SYMATTR Description 150V Low Iq, Synchronous Step-Down DC/DC Controller +PIN -192 -176 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 1 +PIN 192 -96 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 3 +PIN 192 -16 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 4 +PIN -192 304 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN 192 64 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 6 +PIN -192 384 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 7 +PIN -192 -16 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 8 +PIN -192 -416 LEFT 8 +PINATTR PinName CPump_EN +PINATTR SpiceOrder 10 +PIN -192 64 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 13 +PIN -192 -256 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 14 +PIN -192 -96 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 17 +PIN 192 224 RIGHT 8 +PINATTR PinName DRVset +PINATTR SpiceOrder 18 +PIN 192 304 RIGHT 8 +PINATTR PinName DRVUV +PINATTR SpiceOrder 19 +PIN 192 -416 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 20 +PIN 192 -256 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 21 +PIN 192 -336 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 22 +PIN 192 -176 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 24 +PIN 0 464 BOTTOM 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 26 +PIN -112 464 BOTTOM 8 +PINATTR PinName NDRV +PINATTR SpiceOrder 28 +PIN -112 -496 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 30 +PIN 112 -496 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 32 +PIN -192 -336 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 34 +PIN 0 -496 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 38 +PIN 112 464 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LTC7802.asy b/spice/copy/sym/PowerProducts/LTC7802.asy new file mode 100755 index 0000000..1b9ca6f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7802.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -560 208 624 +TEXT -1 1 Center 2 LT +WINDOW 0 -1 -142 Center 2 +WINDOW 3 -1 145 Center 2 +SYMATTR Value LTC7802 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7802.sub +SYMATTR Value2 LTC7802 +SYMATTR Description 40V Low IQ, 3MHz Dual, 2-Phase Synchronous Step-Down Controller with Spread Spectrum +PIN -240 176 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 1 +PIN -240 560 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 2 +PIN -240 -400 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 3 +PIN 80 624 BOTTOM 8 +PINATTR PinName Mode +PINATTR SpiceOrder 4 +PIN 208 560 RIGHT 8 +PINATTR PinName PLLin/Spread +PINATTR SpiceOrder 5 +PIN -112 624 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -240 -496 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 7 +PIN 208 -400 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 8 +PIN 208 -208 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 9 +PIN 208 -304 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 10 +PIN 208 -16 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 11 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 12 +PIN 208 176 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 208 272 RIGHT 8 +PINATTR PinName Vfb2 +PINATTR SpiceOrder 14 +PIN 208 368 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 15 +PIN 208 -112 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 16 +PIN 208 464 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 17 +PIN 208 -496 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 18 +PIN -16 -560 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 19 +PIN 128 -560 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 +PIN -240 368 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 21 +PIN -160 -560 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 22 +PIN -240 -16 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -240 -208 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 24 +PIN -240 -112 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 25 +PIN -240 -304 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 26 +PIN -240 272 LEFT 8 +PINATTR PinName Vfb1 +PINATTR SpiceOrder 27 +PIN -240 80 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 28 +PIN -240 464 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LTC7803.asy b/spice/copy/sym/PowerProducts/LTC7803.asy new file mode 100755 index 0000000..d33f707 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7803.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -352 192 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -143 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC7803 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7803.sub +SYMATTR Value2 LTC7803 +SYMATTR Description 40V Low Iq, 100% Duty Cycle, Synchronous Step-Down Controller with Spread Spectrum +PIN 192 192 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 1 +PIN -192 0 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 2 +PIN -192 96 LEFT 8 +PINATTR PinName PLLin/Spread +PINATTR SpiceOrder 5 +PIN -192 -288 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN -192 -192 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 19 +PIN 80 -352 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 +PIN 0 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -80 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 22 +PIN 192 0 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 23 +PIN 192 -192 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 24 +PIN 192 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 25 +PIN 192 -288 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 26 +PIN -192 -96 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 4 +PIN -192 192 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 29 +PIN -192 288 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 30 +PIN 192 288 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 31 +PIN 192 96 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 32 diff --git a/spice/copy/sym/PowerProducts/LTC7804.asy b/spice/copy/sym/PowerProducts/LTC7804.asy new file mode 100755 index 0000000..313329d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7804.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -400 240 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 1 192 Center 2 +SYMATTR Value LTC7804 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7804.sub +SYMATTR Value2 LTC7804 +SYMATTR Description Low Iq Synchronous Boost Controller +PIN 240 144 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 1 +PIN -240 48 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 2 +PIN -240 -336 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 22 +PIN -240 240 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 4 +PIN -240 144 LEFT 8 +PINATTR PinName PLLin/Spread +PINATTR SpiceOrder 5 +PIN 0 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -240 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN -240 -144 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 19 +PIN -240 -48 LEFT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 20 +PIN 240 -336 RIGHT 8 +PINATTR PinName Boost +PINATTR SpiceOrder 24 +PIN 240 -240 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 26 +PIN 240 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 25 +PIN 240 -48 RIGHT 8 +PINATTR PinName BG +PINATTR SpiceOrder 23 +PIN 240 48 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 32 +PIN 240 336 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 30 +PIN 240 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 31 +PIN -240 336 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LTC7805.asy b/spice/copy/sym/PowerProducts/LTC7805.asy new file mode 100755 index 0000000..9423bf0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7805.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -560 208 624 +TEXT -1 1 Center 2 LT +WINDOW 0 -1 -142 Center 2 +WINDOW 3 -1 145 Center 2 +SYMATTR Value LTC7805 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7805.sub +SYMATTR Value2 LTC7805 +SYMATTR Description 40V Low IQ, Dual, 2-Phase 100% Duty Cycle Synchronous Step-Down Controller with Spread Spectrum +PIN -240 176 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 1 +PIN -240 560 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 2 +PIN -240 -400 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 3 +PIN 80 624 BOTTOM 8 +PINATTR PinName Mode +PINATTR SpiceOrder 4 +PIN 208 560 RIGHT 8 +PINATTR PinName PLLin/Spread +PINATTR SpiceOrder 5 +PIN -112 624 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -240 -496 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 7 +PIN 208 -400 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 8 +PIN 208 -208 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 9 +PIN 208 -304 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 10 +PIN 208 -16 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 11 +PIN 208 80 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 12 +PIN 208 176 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 208 272 RIGHT 8 +PINATTR PinName Vfb2 +PINATTR SpiceOrder 14 +PIN 208 368 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 15 +PIN 208 -112 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 16 +PIN 208 464 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 17 +PIN 208 -496 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 18 +PIN -16 -560 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 19 +PIN 128 -560 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 +PIN -240 368 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 21 +PIN -160 -560 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 22 +PIN -240 -16 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN -240 -208 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 24 +PIN -240 -112 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 25 +PIN -240 -304 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 26 +PIN -240 272 LEFT 8 +PINATTR PinName Vfb1 +PINATTR SpiceOrder 27 +PIN -240 80 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 28 +PIN -240 464 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LTC7810.asy b/spice/copy/sym/PowerProducts/LTC7810.asy new file mode 100755 index 0000000..ee1a618 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7810.asy @@ -0,0 +1,107 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -592 224 592 +TEXT 0 0 Center 2 LT +WINDOW 0 -11 -290 Center 2 +WINDOW 3 -5 290 Center 2 +SYMATTR Value LTC7810 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7810.sub +SYMATTR Value2 LTC7810 +SYMATTR Description 150V Low Iq, Dual, 2-Phase Synchronous Step-Down DC/DC Controller\n\nNote: REGSD pin is not modeled. +PIN -240 48 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 1 +PIN 48 592 BOTTOM 8 +PINATTR PinName DRVset +PINATTR SpiceOrder 2 +PIN -240 432 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 3 +PIN 224 432 RIGHT 8 +PINATTR PinName PLLin +PINATTR SpiceOrder 4 +PIN 160 592 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 5 +PIN 224 528 RIGHT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 8 +PIN -64 592 BOTTOM 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 9 +PIN -64 -592 TOP 8 +PINATTR PinName NDRV +PINATTR SpiceOrder 10 +PIN 160 -592 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 11 +PIN 224 48 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 12 +PIN 224 -48 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 13 +PIN 224 144 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 14 +PIN 224 240 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 15 +PIN 224 336 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 16 +PIN -240 528 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 17 +PIN 224 -336 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 19 +PIN 224 -240 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 20 +PIN 224 -432 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 21 +PIN 224 -144 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 24 +PIN -176 592 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 25 +PIN 48 -592 TOP 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 26 +PIN 224 -528 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 29 +PIN -240 -528 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 32 +PIN -176 -592 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 35 +PIN -240 -144 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 37 +PIN -240 -432 LEFT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 40 +PIN -240 -240 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 41 +PIN -240 -336 LEFT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 42 +PIN -240 336 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 45 +PIN -240 240 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 46 +PIN -240 144 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 47 +PIN -240 -48 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 48 diff --git a/spice/copy/sym/PowerProducts/LTC7812.asy b/spice/copy/sym/PowerProducts/LTC7812.asy new file mode 100755 index 0000000..90eb11a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7812.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -272 -544 256 544 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC7812 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7812.sub +SYMATTR Value2 LTC7812 +SYMATTR Description Low Iq, 38V Synchronous Boost + Buck Controller +PIN 160 544 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 1 +PIN 256 -480 RIGHT 8 +PINATTR PinName PLLIN/Mode +PINATTR SpiceOrder 2 +PIN -272 -384 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 3 +PIN -272 384 LEFT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 4 +PIN -272 288 LEFT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 5 +PIN -272 -192 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 6 +PIN -272 480 LEFT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 7 +PIN 0 544 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN 256 -384 RIGHT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 10 +PIN 256 -288 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 11 +PIN 256 288 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 12 +PIN 256 192 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 13 +PIN 256 384 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 14 +PIN 256 480 RIGHT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 15 +PIN -272 -480 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 16 +PIN -272 -288 LEFT 8 +PINATTR PinName OV2 +PINATTR SpiceOrder 17 +PIN 256 -192 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 18 +PIN 256 0 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 19 +PIN 256 -96 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 20 +PIN 256 96 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 21 +PIN 0 -544 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 22 +PIN 128 -544 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 23 +PIN -128 -544 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 24 +PIN -272 192 LEFT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 25 +PIN -272 -96 LEFT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 26 +PIN -272 0 LEFT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 27 +PIN -272 96 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 28 +PIN -160 544 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LTC7813.asy b/spice/copy/sym/PowerProducts/LTC7813.asy new file mode 100755 index 0000000..ba9ae3b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7813.asy @@ -0,0 +1,107 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -656 256 656 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC7813 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7813.sub +SYMATTR Value2 LTC7813 +SYMATTR Description Low Iq, 60V Synchronous Boost+Buck Controller +PIN 144 656 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 1 +PIN -144 656 BOTTOM 8 +PINATTR PinName PLLIN/Mode +PINATTR SpiceOrder 2 +PIN -256 -192 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 3 +PIN -256 480 LEFT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 4 +PIN -256 384 LEFT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 5 +PIN -256 -96 LEFT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 6 +PIN -256 576 LEFT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 7 +PIN 0 656 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 256 -384 RIGHT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 9 +PIN -256 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 10 +PIN -256 -288 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 11 +PIN 256 480 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 12 +PIN 256 384 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 13 +PIN 256 576 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 14 +PIN 256 -96 RIGHT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 15 +PIN 256 -192 RIGHT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 16 +PIN -256 -576 LEFT 8 +PINATTR PinName DRVSET +PINATTR SpiceOrder 17 +PIN 256 96 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 18 +PIN 256 192 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 19 +PIN 256 0 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 20 +PIN 256 288 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 21 +PIN -144 -656 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 22 +PIN 144 -656 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 23 +PIN 256 -288 RIGHT 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 24 +PIN -256 288 LEFT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 25 +PIN -256 0 LEFT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 26 +PIN -256 96 LEFT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 27 +PIN -256 192 LEFT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 28 +PIN 256 -480 RIGHT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 29 +PIN -256 -480 LEFT 8 +PINATTR PinName DRVUV +PINATTR SpiceOrder 30 +PIN 256 -576 RIGHT 8 +PINATTR PinName VPRG2 +PINATTR SpiceOrder 33 +PIN 0 -656 TOP 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LTC7815.asy b/spice/copy/sym/PowerProducts/LTC7815.asy new file mode 100755 index 0000000..b4c3d74 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7815.asy @@ -0,0 +1,128 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -784 256 784 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -336 Center 2 +WINDOW 3 0 336 Center 2 +SYMATTR Value LTC7815 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7815.sub +SYMATTR Value2 LTC7815 +SYMATTR Description Low Iq, 2.25MHz, Triple Output, Buck/Buck/Boost Synchronous Controller +PIN 144 784 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 1 +PIN -144 784 BOTTOM 8 +PINATTR PinName PLLIN/Mode +PINATTR SpiceOrder 2 +PIN -256 -144 LEFT 8 +PINATTR PinName SS3 +PINATTR SpiceOrder 3 +PIN -256 624 LEFT 8 +PINATTR PinName Sense3+ +PINATTR SpiceOrder 4 +PIN -256 528 LEFT 8 +PINATTR PinName Sense3- +PINATTR SpiceOrder 5 +PIN -256 48 LEFT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 6 +PIN -256 720 LEFT 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 7 +PIN 48 784 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -256 -624 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 9 +PIN -256 -528 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 10 +PIN -256 -432 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 11 +PIN 256 528 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 12 +PIN 256 432 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 13 +PIN 256 624 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 14 +PIN 256 720 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 15 +PIN -256 -240 LEFT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 16 +PIN -256 -48 LEFT 8 +PINATTR PinName OV3 +PINATTR SpiceOrder 17 +PIN 256 48 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 18 +PIN 256 240 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 256 144 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 20 +PIN 256 336 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 21 +PIN 0 -784 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 22 +PIN 96 -784 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 23 +PIN -96 -784 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 24 +PIN -256 432 LEFT 8 +PINATTR PinName BG3 +PINATTR SpiceOrder 25 +PIN -256 144 LEFT 8 +PINATTR PinName Boost3 +PINATTR SpiceOrder 26 +PIN -256 240 LEFT 8 +PINATTR PinName TG3 +PINATTR SpiceOrder 27 +PIN -256 336 LEFT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 28 +PIN 256 -432 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 29 +PIN 256 -624 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 30 +PIN 256 -528 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 256 -720 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 32 +PIN -256 -720 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 33 +PIN -256 -336 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 34 +PIN 256 -48 RIGHT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 35 +PIN 256 -144 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 36 +PIN 256 -336 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 37 +PIN 256 -240 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 38 +PIN -48 784 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LTC7817.asy b/spice/copy/sym/PowerProducts/LTC7817.asy new file mode 100755 index 0000000..0ed4e6e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7817.asy @@ -0,0 +1,125 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -560 272 1008 +TEXT 14 1 Center 2 LT +WINDOW 0 14 -142 Center 2 +WINDOW 3 14 145 Center 2 +SYMATTR Value LTC7817 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7817.sub +SYMATTR Value2 LTC7817 +SYMATTR Description 40V Low IQ, 3MHz Dual, Triple Output Buck/Buck/Boost Synchronous Controller +PIN 272 -16 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 1 +PIN 112 1008 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 2 +PIN -240 -496 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 3 +PIN 16 1008 BOTTOM 8 +PINATTR PinName Mode +PINATTR SpiceOrder 4 +PIN -80 1008 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -240 -400 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 7 +PIN -240 176 LEFT 8 +PINATTR PinName VPRG3 +PINATTR SpiceOrder 8 +PIN 272 368 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 9 +PIN 272 272 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 10 +PIN 272 560 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 11 +PIN 272 656 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 12 +PIN 272 752 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 272 848 RIGHT 8 +PINATTR PinName Vfb2 +PINATTR SpiceOrder 14 +PIN 272 944 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 15 +PIN 272 464 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 16 +PIN -240 -16 LEFT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 17 +PIN -240 -304 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 18 +PIN 16 -560 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 19 +PIN 112 -560 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 +PIN 272 176 RIGHT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 21 +PIN -80 -560 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 22 +PIN 272 -208 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN 272 -400 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 24 +PIN 272 -304 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 25 +PIN 272 -496 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 26 +PIN 272 80 RIGHT 8 +PINATTR PinName Vfb1 +PINATTR SpiceOrder 27 +PIN 272 -112 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 28 +PIN -240 -112 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 29 +PIN -240 368 LEFT 8 +PINATTR PinName Boost3 +PINATTR SpiceOrder 30 +PIN -240 464 LEFT 8 +PINATTR PinName TG3 +PINATTR SpiceOrder 31 +PIN -240 560 LEFT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 32 +PIN -240 656 LEFT 8 +PINATTR PinName BG3 +PINATTR SpiceOrder 33 +PIN -240 848 LEFT 8 +PINATTR PinName Sense3+ +PINATTR SpiceOrder 34 +PIN -240 752 LEFT 8 +PINATTR PinName Sense3- +PINATTR SpiceOrder 35 +PIN -240 272 LEFT 8 +PINATTR PinName Vfb3 +PINATTR SpiceOrder 36 +PIN -240 944 LEFT 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 37 +PIN -240 80 LEFT 8 +PINATTR PinName SS3 +PINATTR SpiceOrder 38 +PIN -240 -208 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LTC7818.asy b/spice/copy/sym/PowerProducts/LTC7818.asy new file mode 100755 index 0000000..9d4c18e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7818.asy @@ -0,0 +1,134 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -560 272 1088 +TEXT 14 1 Center 2 LT +WINDOW 0 14 -142 Center 2 +WINDOW 3 14 145 Center 2 +SYMATTR Value LTC7818 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7818.sub +SYMATTR Value2 LTC7818 +SYMATTR Description 40V Low IQ, 3MHz Dual, 2-Phase Synchronous Step-Down Controller with Spread Spectrum +PIN 272 -16 RIGHT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 1 +PIN 160 1088 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 2 +PIN -240 -496 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 3 +PIN 64 1088 BOTTOM 8 +PINATTR PinName Mode +PINATTR SpiceOrder 4 +PIN 272 1024 RIGHT 8 +PINATTR PinName PLLin/Spread +PINATTR SpiceOrder 5 +PIN -32 1088 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -240 -400 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 7 +PIN -240 176 LEFT 8 +PINATTR PinName VPRG3 +PINATTR SpiceOrder 8 +PIN 272 368 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 9 +PIN 272 272 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 10 +PIN 272 560 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 11 +PIN 272 656 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 12 +PIN 272 752 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 13 +PIN 272 848 RIGHT 8 +PINATTR PinName Vfb2 +PINATTR SpiceOrder 14 +PIN 272 944 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 15 +PIN 272 464 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 16 +PIN -240 -16 LEFT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 17 +PIN -240 -304 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 18 +PIN 16 -560 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 19 +PIN 112 -560 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 +PIN 272 176 RIGHT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 21 +PIN -80 -560 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 22 +PIN 272 -208 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 23 +PIN 272 -400 RIGHT 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 24 +PIN 272 -304 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 25 +PIN 272 -496 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 26 +PIN 272 80 RIGHT 8 +PINATTR PinName Vfb1 +PINATTR SpiceOrder 27 +PIN 272 -112 RIGHT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 28 +PIN -240 -112 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 29 +PIN -240 368 LEFT 8 +PINATTR PinName Boost3 +PINATTR SpiceOrder 30 +PIN -240 464 LEFT 8 +PINATTR PinName TG3 +PINATTR SpiceOrder 31 +PIN -240 560 LEFT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 32 +PIN -240 656 LEFT 8 +PINATTR PinName BG3 +PINATTR SpiceOrder 33 +PIN -240 848 LEFT 8 +PINATTR PinName Sense3+ +PINATTR SpiceOrder 34 +PIN -240 752 LEFT 8 +PINATTR PinName Sense3- +PINATTR SpiceOrder 35 +PIN -240 272 LEFT 8 +PINATTR PinName Vfb3 +PINATTR SpiceOrder 36 +PIN -240 944 LEFT 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 37 +PIN -240 80 LEFT 8 +PINATTR PinName SS3 +PINATTR SpiceOrder 38 +PIN -240 -208 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 39 +PIN -128 1088 BOTTOM 8 +PINATTR PinName OV3 +PINATTR SpiceOrder 40 +PIN -240 1024 LEFT 8 +PINATTR PinName IMON3 +PINATTR SpiceOrder 41 diff --git a/spice/copy/sym/PowerProducts/LTC7820.asy b/spice/copy/sym/PowerProducts/LTC7820.asy new file mode 100755 index 0000000..b63fca0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7820.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -544 256 512 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LTC7820 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7820.sub +SYMATTR Value2 LTC7820 +SYMATTR Description Fixed Ratio High Power Inductorless (Charge Pump) DC/DC Controller +PIN -256 -288 LEFT 8 +PINATTR PinName TIMER +PINATTR SpiceOrder 1 +PIN -256 96 LEFT 8 +PINATTR PinName HYS_PRGM +PINATTR SpiceOrder 2 +PIN -256 -96 LEFT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 3 +PIN -256 288 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 4 +PIN 128 -544 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN -256 384 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 6 +PIN -256 192 LEFT 8 +PINATTR PinName PGOOD +PINATTR SpiceOrder 7 +PIN -256 0 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 8 +PIN -256 480 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 9 +PIN 256 480 RIGHT 8 +PINATTR PinName G4 +PINATTR SpiceOrder 10 +PIN 256 384 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 11 +PIN 256 288 RIGHT 8 +PINATTR PinName G3 +PINATTR SpiceOrder 12 +PIN 256 192 RIGHT 8 +PINATTR PinName BOOST3 +PINATTR SpiceOrder 13 +PIN 256 96 RIGHT 8 +PINATTR PinName VLOW_SENSE +PINATTR SpiceOrder 14 +PIN 256 0 RIGHT 8 +PINATTR PinName Vlow +PINATTR SpiceOrder 15 +PIN 256 -96 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 16 +PIN 256 -192 RIGHT 8 +PINATTR PinName BOOST2 +PINATTR SpiceOrder 17 +PIN 256 -288 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 18 +PIN 256 -384 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 19 +PIN 256 -480 RIGHT 8 +PINATTR PinName BOOST1 +PINATTR SpiceOrder 20 +PIN -96 -544 TOP 8 +PINATTR PinName VHIGH_SENSE +PINATTR SpiceOrder 21 +PIN -256 -480 LEFT 8 +PINATTR PinName Isense- +PINATTR SpiceOrder 22 +PIN -256 -384 LEFT 8 +PINATTR PinName Isense+ +PINATTR SpiceOrder 23 +PIN 0 512 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 24 +PIN -256 -192 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LTC7821.asy b/spice/copy/sym/PowerProducts/LTC7821.asy new file mode 100755 index 0000000..8b68d04 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7821.asy @@ -0,0 +1,104 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -640 256 640 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -338 Center 2 +WINDOW 3 -1 334 Center 2 +SYMATTR Value LTC7821 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7821.sub +SYMATTR Value2 LTC7821 +SYMATTR Description Hybrid Step-Down Synchronous Controller +PIN -256 -288 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN -256 -96 LEFT 8 +PINATTR PinName Hys_prgm +PINATTR SpiceOrder 9 +PIN -128 -640 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 16 +PIN -256 0 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -256 -576 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 +PIN -256 192 LEFT 8 +PINATTR PinName Fault +PINATTR SpiceOrder 4 +PIN -256 96 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 5 +PIN -256 -192 LEFT 8 +PINATTR PinName Mode/PLL +PINATTR SpiceOrder 1 +PIN -256 288 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 19 +PIN 256 288 RIGHT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 18 +PIN 256 192 RIGHT 8 +PINATTR PinName Sw3 +PINATTR SpiceOrder 20 +PIN 256 96 RIGHT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 21 +PIN 256 0 RIGHT 8 +PINATTR PinName Boost3 +PINATTR SpiceOrder 22 +PIN 256 -96 RIGHT 8 +PINATTR PinName Mid_sense +PINATTR SpiceOrder 26 +PIN 256 -192 RIGHT 8 +PINATTR PinName Mid +PINATTR SpiceOrder 25 +PIN 256 -288 RIGHT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 24 +PIN 256 -384 RIGHT 8 +PINATTR PinName Boost2 +PINATTR SpiceOrder 23 +PIN 256 -480 RIGHT 8 +PINATTR PinName Sw1 +PINATTR SpiceOrder 29 +PIN 256 -576 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 30 +PIN 128 -640 TOP 8 +PINATTR PinName Boost1 +PINATTR SpiceOrder 31 +PIN -256 -480 LEFT 8 +PINATTR PinName Vin_sense +PINATTR SpiceOrder 27 +PIN 256 384 RIGHT 8 +PINATTR PinName Isns+ +PINATTR SpiceOrder 15 +PIN 256 480 RIGHT 8 +PINATTR PinName Isns- +PINATTR SpiceOrder 14 +PIN 128 640 BOTTOM 8 +PINATTR PinName Pgnd +PINATTR SpiceOrder 17 +PIN -256 -384 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 3 +PIN -256 576 LEFT 8 +PINATTR PinName Sgnd +PINATTR SpiceOrder 33 +PIN 256 576 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 13 +PIN -256 384 LEFT 8 +PINATTR PinName ExtRef +PINATTR SpiceOrder 8 +PIN -128 640 BOTTOM 8 +PINATTR PinName Ith +PINATTR SpiceOrder 10 +PIN -256 480 LEFT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 2 +PIN 0 640 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LTC7840.asy b/spice/copy/sym/PowerProducts/LTC7840.asy new file mode 100755 index 0000000..8ca6ac5 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7840.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -368 -448 368 448 +TEXT 0 0 Center 2 LT +WINDOW 0 2 -243 Center 2 +WINDOW 3 2 242 Center 2 +SYMATTR Value LTC7840 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7840.sub +SYMATTR Value2 LTC7840 +SYMATTR Description Dual Phase Dual Output Non-Synchronous Boost Controller +PIN -288 448 BOTTOM 8 +PINATTR PinName Dmax +PINATTR SpiceOrder 1 +PIN 0 448 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 2 +PIN -368 96 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 3 +PIN -368 -96 LEFT 8 +PINATTR PinName VFB1 +PINATTR SpiceOrder 4 +PIN -368 0 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 5 +PIN -288 -448 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 6 +PIN 288 -448 TOP 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 7 +PIN 368 96 RIGHT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 8 +PIN 368 -96 RIGHT 8 +PINATTR PinName VFB2 +PINATTR SpiceOrder 9 +PIN 368 0 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 10 +PIN 368 -288 RIGHT 8 +PINATTR PinName Sense2+ +PINATTR SpiceOrder 11 +PIN 368 -192 RIGHT 8 +PINATTR PinName Sense2- +PINATTR SpiceOrder 12 +PIN 368 192 RIGHT 8 +PINATTR PinName Ilim2 +PINATTR SpiceOrder 13 +PIN 368 288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 14 +PIN -368 288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 15 +PIN 368 -384 RIGHT 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 16 +PIN 144 448 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 17 +PIN -368 -384 LEFT 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 18 +PIN 0 -448 TOP 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 19 +PIN -144 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 20 +PIN -144 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 21 +PIN 144 -448 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 22 +PIN -368 192 LEFT 8 +PINATTR PinName Ilim1 +PINATTR SpiceOrder 23 +PIN -368 -192 LEFT 8 +PINATTR PinName Sense1- +PINATTR SpiceOrder 24 +PIN -368 -288 LEFT 8 +PINATTR PinName Sense1+ +PINATTR SpiceOrder 25 +PIN 288 448 BOTTOM 8 +PINATTR PinName Blank +PINATTR SpiceOrder 26 +PIN 368 384 RIGHT 8 +PINATTR PinName CLKOut +PINATTR SpiceOrder 27 +PIN -368 384 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTC7851-1.asy b/spice/copy/sym/PowerProducts/LTC7851-1.asy new file mode 100755 index 0000000..321b5b0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7851-1.asy @@ -0,0 +1,185 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -480 -992 480 976 +TEXT 0 0 Center 2 LT +WINDOW 0 -4 -471 Center 2 +WINDOW 3 3 482 Center 2 +SYMATTR Value LTC7851-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7851-1.sub +SYMATTR Value2 LTC7851-1 +SYMATTR Description Quad Output, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing\n\nNote: Internal soft-start timer is reduced to 0.5ms from 2ms +PIN 480 -528 RIGHT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 1 +PIN 480 -240 RIGHT 8 +PINATTR PinName Vsnsp1 +PINATTR SpiceOrder 2 +PIN 480 -144 RIGHT 8 +PINATTR PinName Vsnsn1 +PINATTR SpiceOrder 3 +PIN 480 -336 RIGHT 8 +PINATTR PinName Vsnsout1 +PINATTR SpiceOrder 4 +PIN 480 624 RIGHT 8 +PINATTR PinName Vsnsout2 +PINATTR SpiceOrder 6 +PIN 480 816 RIGHT 8 +PINATTR PinName Vsnsn2 +PINATTR SpiceOrder 7 +PIN 480 720 RIGHT 8 +PINATTR PinName Vsnsp2 +PINATTR SpiceOrder 8 +PIN 480 432 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 9 +PIN 480 528 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 10 +PIN 0 -992 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 11 +PIN -480 -432 LEFT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 12 +PIN -480 -528 LEFT 8 +PINATTR PinName Comp3 +PINATTR SpiceOrder 13 +PIN -480 -240 LEFT 8 +PINATTR PinName Vsnsp3 +PINATTR SpiceOrder 14 +PIN -480 -144 LEFT 8 +PINATTR PinName Vsnsn3 +PINATTR SpiceOrder 15 +PIN -480 -336 LEFT 8 +PINATTR PinName Vsnsout3 +PINATTR SpiceOrder 16 +PIN -480 624 LEFT 8 +PINATTR PinName Vsnsout4 +PINATTR SpiceOrder 17 +PIN -480 816 LEFT 8 +PINATTR PinName Vsnsn4 +PINATTR SpiceOrder 18 +PIN -480 720 LEFT 8 +PINATTR PinName Vsnsp4 +PINATTR SpiceOrder 19 +PIN -480 432 LEFT 8 +PINATTR PinName Comp4 +PINATTR SpiceOrder 20 +PIN -480 528 LEFT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 21 +PIN -384 976 BOTTOM 8 +PINATTR PinName SS4 +PINATTR SpiceOrder 22 +PIN -288 -992 TOP 8 +PINATTR PinName Run4 +PINATTR SpiceOrder 23 +PIN -480 144 LEFT 8 +PINATTR PinName PWM4 +PINATTR SpiceOrder 24 +PIN -192 -992 TOP 8 +PINATTR PinName Pgood4 +PINATTR SpiceOrder 25 +PIN -480 -816 LEFT 8 +PINATTR PinName PWM3 +PINATTR SpiceOrder 26 +PIN -384 -992 TOP 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 27 +PIN -96 -992 TOP 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 28 +PIN -192 976 BOTTOM 8 +PINATTR PinName Ilim4 +PINATTR SpiceOrder 29 +PIN -480 48 LEFT 8 +PINATTR PinName Iavg4 +PINATTR SpiceOrder 30 +PIN -480 240 LEFT 8 +PINATTR PinName Isns4p +PINATTR SpiceOrder 31 +PIN -480 336 LEFT 8 +PINATTR PinName Isns4n +PINATTR SpiceOrder 32 +PIN -480 -624 LEFT 8 +PINATTR PinName Isns3n +PINATTR SpiceOrder 33 +PIN -480 -720 LEFT 8 +PINATTR PinName Isns3p +PINATTR SpiceOrder 34 +PIN -480 -48 LEFT 8 +PINATTR PinName Iavg3 +PINATTR SpiceOrder 35 +PIN -96 976 BOTTOM 8 +PINATTR PinName Ilim3 +PINATTR SpiceOrder 36 +PIN -288 976 BOTTOM 8 +PINATTR PinName SS3 +PINATTR SpiceOrder 37 +PIN 96 -992 TOP 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 38 +PIN -480 -912 LEFT 8 +PINATTR PinName Vinsns +PINATTR SpiceOrder 39 +PIN 288 976 BOTTOM 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 40 +PIN 96 976 BOTTOM 8 +PINATTR PinName Ilim2 +PINATTR SpiceOrder 41 +PIN 480 48 RIGHT 8 +PINATTR PinName Iavg2 +PINATTR SpiceOrder 42 +PIN 480 240 RIGHT 8 +PINATTR PinName Isns2p +PINATTR SpiceOrder 43 +PIN 480 336 RIGHT 8 +PINATTR PinName Isns2n +PINATTR SpiceOrder 44 +PIN 480 -624 RIGHT 8 +PINATTR PinName Isns1n +PINATTR SpiceOrder 45 +PIN 480 -720 RIGHT 8 +PINATTR PinName Isns1p +PINATTR SpiceOrder 46 +PIN 480 -48 RIGHT 8 +PINATTR PinName Iavg1 +PINATTR SpiceOrder 47 +PIN 192 976 BOTTOM 8 +PINATTR PinName Ilim1 +PINATTR SpiceOrder 48 +PIN 192 -992 TOP 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 49 +PIN 480 144 RIGHT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 50 +PIN 288 -992 TOP 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 51 +PIN 480 -816 RIGHT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 52 +PIN 384 -992 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 53 +PIN 480 912 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 54 +PIN -480 912 LEFT 8 +PINATTR PinName CLKIN +PINATTR SpiceOrder 55 +PIN 480 -912 RIGHT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 56 +PIN 384 976 BOTTOM 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 57 +PIN 480 -432 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 58 +PIN 0 976 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 59 diff --git a/spice/copy/sym/PowerProducts/LTC7851.asy b/spice/copy/sym/PowerProducts/LTC7851.asy new file mode 100755 index 0000000..4e982be --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7851.asy @@ -0,0 +1,185 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -480 -992 480 976 +TEXT 0 0 Center 2 LT +WINDOW 0 -4 -471 Center 2 +WINDOW 3 3 482 Center 2 +SYMATTR Value LTC7851 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7851.sub +SYMATTR Value2 LTC7851 +SYMATTR Description Quad Output, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing\n\nNote: Internal soft-start timer is reduced to 0.5ms from 2ms +PIN 480 -528 RIGHT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 1 +PIN 480 -240 RIGHT 8 +PINATTR PinName Vsnsp1 +PINATTR SpiceOrder 2 +PIN 480 -144 RIGHT 8 +PINATTR PinName Vsnsn1 +PINATTR SpiceOrder 3 +PIN 480 -336 RIGHT 8 +PINATTR PinName Vsnsout1 +PINATTR SpiceOrder 4 +PIN 480 624 RIGHT 8 +PINATTR PinName Vsnsout2 +PINATTR SpiceOrder 6 +PIN 480 816 RIGHT 8 +PINATTR PinName Vsnsn2 +PINATTR SpiceOrder 7 +PIN 480 720 RIGHT 8 +PINATTR PinName Vsnsp2 +PINATTR SpiceOrder 8 +PIN 480 432 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 9 +PIN 480 528 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 10 +PIN 0 -992 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 11 +PIN -480 -432 LEFT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 12 +PIN -480 -528 LEFT 8 +PINATTR PinName Comp3 +PINATTR SpiceOrder 13 +PIN -480 -240 LEFT 8 +PINATTR PinName Vsnsp3 +PINATTR SpiceOrder 14 +PIN -480 -144 LEFT 8 +PINATTR PinName Vsnsn3 +PINATTR SpiceOrder 15 +PIN -480 -336 LEFT 8 +PINATTR PinName Vsnsout3 +PINATTR SpiceOrder 16 +PIN -480 624 LEFT 8 +PINATTR PinName Vsnsout4 +PINATTR SpiceOrder 17 +PIN -480 816 LEFT 8 +PINATTR PinName Vsnsn4 +PINATTR SpiceOrder 18 +PIN -480 720 LEFT 8 +PINATTR PinName Vsnsp4 +PINATTR SpiceOrder 19 +PIN -480 432 LEFT 8 +PINATTR PinName Comp4 +PINATTR SpiceOrder 20 +PIN -480 528 LEFT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 21 +PIN -384 976 BOTTOM 8 +PINATTR PinName SS4 +PINATTR SpiceOrder 22 +PIN -288 -992 TOP 8 +PINATTR PinName Run4 +PINATTR SpiceOrder 23 +PIN -480 144 LEFT 8 +PINATTR PinName PWM4 +PINATTR SpiceOrder 24 +PIN -192 -992 TOP 8 +PINATTR PinName Pgood4 +PINATTR SpiceOrder 25 +PIN -480 -816 LEFT 8 +PINATTR PinName PWM3 +PINATTR SpiceOrder 26 +PIN -384 -992 TOP 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 27 +PIN -96 -992 TOP 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 28 +PIN -192 976 BOTTOM 8 +PINATTR PinName Ilim4 +PINATTR SpiceOrder 29 +PIN -480 48 LEFT 8 +PINATTR PinName Iavg4 +PINATTR SpiceOrder 30 +PIN -480 240 LEFT 8 +PINATTR PinName Isns4p +PINATTR SpiceOrder 31 +PIN -480 336 LEFT 8 +PINATTR PinName Isns4n +PINATTR SpiceOrder 32 +PIN -480 -624 LEFT 8 +PINATTR PinName Isns3n +PINATTR SpiceOrder 33 +PIN -480 -720 LEFT 8 +PINATTR PinName Isns3p +PINATTR SpiceOrder 34 +PIN -480 -48 LEFT 8 +PINATTR PinName Iavg3 +PINATTR SpiceOrder 35 +PIN -96 976 BOTTOM 8 +PINATTR PinName Ilim3 +PINATTR SpiceOrder 36 +PIN -288 976 BOTTOM 8 +PINATTR PinName SS3 +PINATTR SpiceOrder 37 +PIN 96 -992 TOP 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 38 +PIN -480 -912 LEFT 8 +PINATTR PinName Vinsns +PINATTR SpiceOrder 39 +PIN 288 976 BOTTOM 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 40 +PIN 96 976 BOTTOM 8 +PINATTR PinName Ilim2 +PINATTR SpiceOrder 41 +PIN 480 48 RIGHT 8 +PINATTR PinName Iavg2 +PINATTR SpiceOrder 42 +PIN 480 240 RIGHT 8 +PINATTR PinName Isns2p +PINATTR SpiceOrder 43 +PIN 480 336 RIGHT 8 +PINATTR PinName Isns2n +PINATTR SpiceOrder 44 +PIN 480 -624 RIGHT 8 +PINATTR PinName Isns1n +PINATTR SpiceOrder 45 +PIN 480 -720 RIGHT 8 +PINATTR PinName Isns1p +PINATTR SpiceOrder 46 +PIN 480 -48 RIGHT 8 +PINATTR PinName Iavg1 +PINATTR SpiceOrder 47 +PIN 192 976 BOTTOM 8 +PINATTR PinName Ilim1 +PINATTR SpiceOrder 48 +PIN 192 -992 TOP 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 49 +PIN 480 144 RIGHT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 50 +PIN 288 -992 TOP 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 51 +PIN 480 -816 RIGHT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 52 +PIN 384 -992 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 53 +PIN 480 912 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 54 +PIN -480 912 LEFT 8 +PINATTR PinName CLKIN +PINATTR SpiceOrder 55 +PIN 480 -912 RIGHT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 56 +PIN 384 976 BOTTOM 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 57 +PIN 480 -432 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 58 +PIN 0 976 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 59 diff --git a/spice/copy/sym/PowerProducts/LTC7852.asy b/spice/copy/sym/PowerProducts/LTC7852.asy new file mode 100755 index 0000000..2937dec --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7852.asy @@ -0,0 +1,155 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -336 -864 320 896 +TEXT 0 0 Center 2 LT +WINDOW 0 -5 -417 Center 2 +WINDOW 3 -9 448 Center 2 +SYMATTR Value LTC7852 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7852.sub +SYMATTR Value2 LTC7852 +SYMATTR Description Dual Output, 6-Phase, Multiphase Current Mode Synchronous Controller with Current Monitoring +PIN -336 -512 LEFT 8 +PINATTR PinName SNSavg4 +PINATTR SpiceOrder 1 +PIN -336 -608 LEFT 8 +PINATTR PinName SNSp4 +PINATTR SpiceOrder 2 +PIN -336 -416 LEFT 8 +PINATTR PinName SNSn4 +PINATTR SpiceOrder 3 +PIN -336 -128 LEFT 8 +PINATTR PinName SNSavg5 +PINATTR SpiceOrder 4 +PIN -336 -224 LEFT 8 +PINATTR PinName SNSp5 +PINATTR SpiceOrder 5 +PIN -336 -32 LEFT 8 +PINATTR PinName SNSn5 +PINATTR SpiceOrder 6 +PIN -336 256 LEFT 8 +PINATTR PinName SNSavg6 +PINATTR SpiceOrder 7 +PIN -336 160 LEFT 8 +PINATTR PinName SNSp6 +PINATTR SpiceOrder 8 +PIN -336 352 LEFT 8 +PINATTR PinName SNSn6 +PINATTR SpiceOrder 9 +PIN -336 -800 LEFT 8 +PINATTR PinName PGood2 +PINATTR SpiceOrder 10 +PIN -336 736 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 11 +PIN -336 640 LEFT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 12 +PIN -336 544 LEFT 8 +PINATTR PinName Vosns2- +PINATTR SpiceOrder 13 +PIN -336 448 LEFT 8 +PINATTR PinName Vosns2+ +PINATTR SpiceOrder 14 +PIN 240 -864 TOP 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 15 +PIN -240 896 BOTTOM 8 +PINATTR PinName Ilim2 +PINATTR SpiceOrder 16 +PIN -336 832 LEFT 8 +PINATTR PinName Imon2 +PINATTR SpiceOrder 17 +PIN 48 896 BOTTOM 8 +PINATTR PinName V1p5 +PINATTR SpiceOrder 18 +PIN 320 832 RIGHT 8 +PINATTR PinName Imon1 +PINATTR SpiceOrder 19 +PIN 48 -864 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 20 +PIN 144 896 BOTTOM 8 +PINATTR PinName Phcfg +PINATTR SpiceOrder 21 +PIN -144 896 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 22 +PIN 240 896 BOTTOM 8 +PINATTR PinName Ilim1 +PINATTR SpiceOrder 23 +PIN -240 -864 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 24 +PIN 320 448 RIGHT 8 +PINATTR PinName Vosns1+ +PINATTR SpiceOrder 25 +PIN 320 544 RIGHT 8 +PINATTR PinName Vosns1- +PINATTR SpiceOrder 26 +PIN 320 640 RIGHT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 27 +PIN 320 736 RIGHT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 28 +PIN 320 -800 RIGHT 8 +PINATTR PinName PGood1 +PINATTR SpiceOrder 29 +PIN 320 -416 RIGHT 8 +PINATTR PinName SNSn1 +PINATTR SpiceOrder 30 +PIN 320 -608 RIGHT 8 +PINATTR PinName SNSp1 +PINATTR SpiceOrder 31 +PIN 320 -512 RIGHT 8 +PINATTR PinName SNSavg1 +PINATTR SpiceOrder 32 +PIN 320 -32 RIGHT 8 +PINATTR PinName SNSn2 +PINATTR SpiceOrder 33 +PIN 320 -224 RIGHT 8 +PINATTR PinName SNSp2 +PINATTR SpiceOrder 34 +PIN 320 -128 RIGHT 8 +PINATTR PinName SNSavg2 +PINATTR SpiceOrder 35 +PIN 320 352 RIGHT 8 +PINATTR PinName SNSn3 +PINATTR SpiceOrder 36 +PIN 320 160 RIGHT 8 +PINATTR PinName SNSp3 +PINATTR SpiceOrder 37 +PIN 320 256 RIGHT 8 +PINATTR PinName SNSavg3 +PINATTR SpiceOrder 38 +PIN -48 -864 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 39 +PIN 144 -864 TOP 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 40 +PIN 320 -704 RIGHT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 41 +PIN 320 -320 RIGHT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 42 +PIN 320 64 RIGHT 8 +PINATTR PinName PWM3 +PINATTR SpiceOrder 43 +PIN -336 -704 LEFT 8 +PINATTR PinName PWM4 +PINATTR SpiceOrder 44 +PIN -336 -320 LEFT 8 +PINATTR PinName PWM5 +PINATTR SpiceOrder 45 +PIN -336 64 LEFT 8 +PINATTR PinName PWM6 +PINATTR SpiceOrder 46 +PIN -144 -864 TOP 8 +PINATTR PinName Pllin +PINATTR SpiceOrder 47 +PIN -48 896 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 48 diff --git a/spice/copy/sym/PowerProducts/LTC7860.asy b/spice/copy/sym/PowerProducts/LTC7860.asy new file mode 100755 index 0000000..fd4370a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7860.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -256 128 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC7860 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7860.sub +SYMATTR Value2 LTC7860 +SYMATTR Description High Efficiency Switching Surge Stopper +PIN -128 -96 LEFT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 1 +PIN -128 192 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 2 +PIN -48 256 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 4 +PIN 128 192 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 6 +PIN 128 96 RIGHT 8 +PINATTR PinName Vfbn +PINATTR SpiceOrder 7 +PIN -128 -192 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 8 +PIN 0 -256 TOP 8 +PINATTR PinName Cap +PINATTR SpiceOrder 9 +PIN 128 -96 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 10 +PIN 128 -192 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN 128 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 12 +PIN 48 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTC7862.asy b/spice/copy/sym/PowerProducts/LTC7862.asy new file mode 100755 index 0000000..8a96e13 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7862.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 368 208 -352 -208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -95 Center 2 +WINDOW 3 1 97 Center 2 +SYMATTR Value LTC7862 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7862.sub +SYMATTR Value2 LTC7862 +SYMATTR Description 140V High Efficiency Switching Surge Stopper +PIN -160 -208 TOP 8 +PINATTR PinName BG +PINATTR SpiceOrder 10 +PIN -352 -48 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 15 +PIN 176 -208 TOP 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 19 +PIN 288 -208 TOP 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 20 +PIN 288 208 BOTTOM 8 +PINATTR PinName Ith +PINATTR SpiceOrder 3 +PIN 368 -144 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 14 +PIN 368 -48 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 2 +PIN -160 208 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 1 +PIN -48 208 BOTTOM 8 +PINATTR PinName WarnB +PINATTR SpiceOrder 6 +PIN 176 208 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 4 +PIN -272 208 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 5 +PIN 368 48 RIGHT 8 +PINATTR PinName Ovlo +PINATTR SpiceOrder 18 +PIN -352 144 LEFT 8 +PINATTR PinName DrvUV +PINATTR SpiceOrder 16 +PIN -352 48 LEFT 8 +PINATTR PinName DrVcc +PINATTR SpiceOrder 12 +PIN -272 -208 TOP 8 +PINATTR PinName TG +PINATTR SpiceOrder 7 +PIN -352 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 368 144 RIGHT 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 11 +PIN -48 -208 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 8 +PIN 64 -208 TOP 8 +PINATTR PinName Boost +PINATTR SpiceOrder 9 +PIN 64 208 BOTTOM 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTC7871.asy b/spice/copy/sym/PowerProducts/LTC7871.asy new file mode 100755 index 0000000..08dd375 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTC7871.asy @@ -0,0 +1,173 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 1584 -160 -1584 +TEXT 0 -448 Center 2 LT +WINDOW 0 0 -719 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTC7871 +SYMATTR Prefix X +SYMATTR SpiceModel LTC7871.sub +SYMATTR Value2 LTC7871 +SYMATTR Description 6-phase Bidirectional Buck or Boost Controller +PIN 160 1488 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 1 +PIN 160 -1152 RIGHT 8 +PINATTR PinName VFBLow +PINATTR SpiceOrder 3 +PIN -160 -1152 LEFT 8 +PINATTR PinName ITHLow +PINATTR SpiceOrder 4 +PIN 0 1584 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 5 +PIN -160 -1232 LEFT 8 +PINATTR PinName ITHHigh +PINATTR SpiceOrder 6 +PIN 160 -1360 RIGHT 8 +PINATTR PinName VFBHigh +PINATTR SpiceOrder 7 +PIN -160 1488 LEFT 8 +PINATTR PinName V5 +PINATTR SpiceOrder 9 +PIN 160 1536 RIGHT 8 +PINATTR PinName IMON +PINATTR SpiceOrder 10 +PIN -160 -192 LEFT 8 +PINATTR PinName SETCUR +PINATTR SpiceOrder 11 +PIN 160 -1424 RIGHT 8 +PINATTR PinName OVHigh +PINATTR SpiceOrder 13 +PIN 160 -1392 RIGHT 8 +PINATTR PinName UVHigh +PINATTR SpiceOrder 14 +PIN 160 -1104 RIGHT 8 +PINATTR PinName OVLow +PINATTR SpiceOrder 15 +PIN -160 -336 LEFT 8 +PINATTR PinName SNSA1+ +PINATTR SpiceOrder 17 +PIN -160 -240 LEFT 8 +PINATTR PinName SNS1- +PINATTR SpiceOrder 18 +PIN -160 -288 LEFT 8 +PINATTR PinName SNSD1+ +PINATTR SpiceOrder 19 +PIN -160 528 LEFT 8 +PINATTR PinName SNSD2+ +PINATTR SpiceOrder 20 +PIN -160 576 LEFT 8 +PINATTR PinName SNS2- +PINATTR SpiceOrder 21 +PIN -160 480 LEFT 8 +PINATTR PinName SNSA2+ +PINATTR SpiceOrder 22 +PIN -160 1296 LEFT 8 +PINATTR PinName SNSA3+ +PINATTR SpiceOrder 23 +PIN -160 1392 LEFT 8 +PINATTR PinName SNS3- +PINATTR SpiceOrder 24 +PIN -160 1344 LEFT 8 +PINATTR PinName SNSD3+ +PINATTR SpiceOrder 25 +PIN -160 -912 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 27 +PIN 160 624 RIGHT 8 +PINATTR PinName PWMEN +PINATTR SpiceOrder 28 +PIN -160 -560 LEFT 8 +PINATTR PinName PWM1 +PINATTR SpiceOrder 29 +PIN -160 1536 LEFT 8 +PINATTR PinName PGOOD +PINATTR SpiceOrder 30 +PIN -160 256 LEFT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 31 +PIN -160 1072 LEFT 8 +PINATTR PinName PWM3 +PINATTR SpiceOrder 32 +PIN 160 1072 RIGHT 8 +PINATTR PinName PWM4 +PINATTR SpiceOrder 33 +PIN 160 256 RIGHT 8 +PINATTR PinName PWM5 +PINATTR SpiceOrder 34 +PIN -160 -1312 LEFT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 35 +PIN 160 -560 RIGHT 8 +PINATTR PinName PWM6 +PINATTR SpiceOrder 36 +PIN -160 -1408 LEFT 8 +PINATTR PinName CSB +PINATTR SpiceOrder 37 +PIN -160 -1456 LEFT 8 +PINATTR PinName SDO +PINATTR SpiceOrder 38 +PIN -160 -1504 LEFT 8 +PINATTR PinName SDI +PINATTR SpiceOrder 39 +PIN -160 -1552 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 40 +PIN 160 -1056 RIGHT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 42 +PIN 160 -192 RIGHT 8 +PINATTR PinName DRVSet +PINATTR SpiceOrder 44 +PIN 160 1440 RIGHT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 46 +PIN 160 -1552 RIGHT 8 +PINATTR PinName VHigh +PINATTR SpiceOrder 48 +PIN -160 1440 LEFT 8 +PINATTR PinName ILIM +PINATTR SpiceOrder 49 +PIN 160 -1200 RIGHT 8 +PINATTR PinName CLKOut +PINATTR SpiceOrder 50 +PIN 160 -912 RIGHT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 51 +PIN 160 -1008 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 52 +PIN 160 -1248 RIGHT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 53 +PIN -160 -1008 LEFT 8 +PINATTR PinName BUCK +PINATTR SpiceOrder 54 +PIN 160 1344 RIGHT 8 +PINATTR PinName SNSD4+ +PINATTR SpiceOrder 56 +PIN 160 1392 RIGHT 8 +PINATTR PinName SNS4- +PINATTR SpiceOrder 57 +PIN 160 1296 RIGHT 8 +PINATTR PinName SNSA4+ +PINATTR SpiceOrder 58 +PIN 160 480 RIGHT 8 +PINATTR PinName SNSA5+ +PINATTR SpiceOrder 59 +PIN 160 576 RIGHT 8 +PINATTR PinName SNS5- +PINATTR SpiceOrder 60 +PIN 160 528 RIGHT 8 +PINATTR PinName SNSD5+ +PINATTR SpiceOrder 61 +PIN 160 -288 RIGHT 8 +PINATTR PinName SNSD6+ +PINATTR SpiceOrder 62 +PIN 160 -240 RIGHT 8 +PINATTR PinName SNS6- +PINATTR SpiceOrder 63 +PIN 160 -336 RIGHT 8 +PINATTR PinName SNSA6+ +PINATTR SpiceOrder 64 diff --git a/spice/copy/sym/PowerProducts/LTM4600.asy b/spice/copy/sym/PowerProducts/LTM4600.asy new file mode 100755 index 0000000..6e74554 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4600.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 128 -176 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 55 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTM4600 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4600.sub +SYMATTR Value2 LTM4600 +SYMATTR Description 10A High Efficiency DC/DC µModule +PIN 64 -112 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 1 +PIN 176 32 RIGHT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 3 +PIN -176 -16 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -176 32 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -176 80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 6 +PIN 176 80 RIGHT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 7 +PIN 176 -16 RIGHT 8 +PINATTR PinName Voset +PINATTR SpiceOrder 8 +PIN -64 128 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN 64 128 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 176 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 11 +PIN -64 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LTM4600HV.asy b/spice/copy/sym/PowerProducts/LTM4600HV.asy new file mode 100755 index 0000000..76f0606 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4600HV.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 128 -176 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 55 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTM4600HV +SYMATTR Prefix X +SYMATTR SpiceModel LTM4600.sub +SYMATTR Value2 LTM4600 +SYMATTR Description 10A High Efficiency DC/DC µModule +PIN 64 -112 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 1 +PIN 176 32 RIGHT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 3 +PIN -176 -16 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -176 32 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -176 80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 6 +PIN 176 80 RIGHT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 7 +PIN 176 -16 RIGHT 8 +PINATTR PinName Voset +PINATTR SpiceOrder 8 +PIN -64 128 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN 64 128 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 176 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 11 +PIN -64 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LTM4601-1.asy b/spice/copy/sym/PowerProducts/LTM4601-1.asy new file mode 100755 index 0000000..d581bea --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4601-1.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 240 -192 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 135 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTM4601-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4601-1.sub +SYMATTR Value2 LTM4601-1 +SYMATTR Description 12A DC/DC µModule with PLL, Output Tracking and Margining +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 -208 RIGHT 8 +PINATTR PinName Vout_LCL +PINATTR SpiceOrder 5 +PIN -80 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -208 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -192 48 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 48 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 -16 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN 192 176 RIGHT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN -192 112 LEFT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 -80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN 192 112 RIGHT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN -192 176 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4601.asy b/spice/copy/sym/PowerProducts/LTM4601.asy new file mode 100755 index 0000000..7640b9b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4601.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 304 -192 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 135 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTM4601 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4601.sub +SYMATTR Value2 LTM4601 +SYMATTR Description 12A DC/DC µModule with PLL, Output Tracking and Margining +PIN -80 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 112 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 192 -80 RIGHT 8 +PINATTR PinName Vout_LCL +PINATTR SpiceOrder 5 +PIN 192 -16 RIGHT 8 +PINATTR PinName DiffVout +PINATTR SpiceOrder 6 +PIN 192 48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 7 +PIN -80 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -208 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -192 48 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 240 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 176 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN -192 176 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN -192 112 LEFT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 -80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN 64 -256 TOP 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4601A-1.asy b/spice/copy/sym/PowerProducts/LTM4601A-1.asy new file mode 100755 index 0000000..04033ab --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4601A-1.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 240 -192 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 135 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTM4601A-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4601-1.sub +SYMATTR Value2 LTM4601-1 +SYMATTR Description 12A DC/DC µModule with PLL, Output Tracking and Margining +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 -208 RIGHT 8 +PINATTR PinName Vout_LCL +PINATTR SpiceOrder 5 +PIN -80 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -208 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -192 48 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 48 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 -16 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN 192 176 RIGHT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN -192 112 LEFT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 -80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN 192 112 RIGHT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN -192 176 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4601A.asy b/spice/copy/sym/PowerProducts/LTM4601A.asy new file mode 100755 index 0000000..6be9526 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4601A.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 304 -192 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 135 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTM4601A +SYMATTR Prefix X +SYMATTR SpiceModel LTM4601.sub +SYMATTR Value2 LTM4601 +SYMATTR Description 12A DC/DC µModule with PLL, Output Tracking and Margining +PIN -80 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 112 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 192 -80 RIGHT 8 +PINATTR PinName Vout_LCL +PINATTR SpiceOrder 5 +PIN 192 -16 RIGHT 8 +PINATTR PinName DiffVout +PINATTR SpiceOrder 6 +PIN 192 48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 7 +PIN -80 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -208 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -192 48 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 240 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 176 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN -192 176 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN -192 112 LEFT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 -80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN 64 -256 TOP 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4601AHV.asy b/spice/copy/sym/PowerProducts/LTM4601AHV.asy new file mode 100755 index 0000000..e8607ae --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4601AHV.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 304 -192 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 135 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTM4601AHV +SYMATTR Prefix X +SYMATTR SpiceModel LTM4601.sub +SYMATTR Value2 LTM4601 +SYMATTR Description 12A, 28Vin DC/DC µModule with PLL, Output Tracking and Margining +PIN -80 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 112 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 192 -80 RIGHT 8 +PINATTR PinName Vout_LCL +PINATTR SpiceOrder 5 +PIN 192 -16 RIGHT 8 +PINATTR PinName DiffVout +PINATTR SpiceOrder 6 +PIN 192 48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 7 +PIN -80 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -208 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -192 48 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 240 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 176 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN -192 176 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN -192 112 LEFT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 -80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN 64 -256 TOP 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4601HV.asy b/spice/copy/sym/PowerProducts/LTM4601HV.asy new file mode 100755 index 0000000..74742ef --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4601HV.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 304 -192 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 135 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTM4601HV +SYMATTR Prefix X +SYMATTR SpiceModel LTM4601.sub +SYMATTR Value2 LTM4601 +SYMATTR Description 12A DC/DC µModule with PLL, Output Tracking and Margining +PIN -80 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 112 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 192 -80 RIGHT 8 +PINATTR PinName Vout_LCL +PINATTR SpiceOrder 5 +PIN 192 -16 RIGHT 8 +PINATTR PinName DiffVout +PINATTR SpiceOrder 6 +PIN 192 48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 7 +PIN -80 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -208 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -192 48 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 240 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 176 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN -192 176 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN -192 112 LEFT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 -80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN 64 -256 TOP 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4602.asy b/spice/copy/sym/PowerProducts/LTM4602.asy new file mode 100755 index 0000000..bf63785 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4602.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 128 -176 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 55 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTM4602 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4602.sub +SYMATTR Value2 LTM4602 +SYMATTR Description 6A High Efficiency DC/DC µModule +PIN 64 -112 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 1 +PIN 176 32 RIGHT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 3 +PIN -176 -16 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -176 32 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -176 80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 6 +PIN 176 80 RIGHT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 7 +PIN 176 -16 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -64 128 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN 64 128 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 176 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 11 +PIN -64 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LTM4602HV.asy b/spice/copy/sym/PowerProducts/LTM4602HV.asy new file mode 100755 index 0000000..8d9fef1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4602HV.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 128 -176 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 55 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTM4602HV +SYMATTR Prefix X +SYMATTR SpiceModel LTM4602.sub +SYMATTR Value2 LTM4602 +SYMATTR Description 6A, 28Vin High Efficiency DC/DC µModule +PIN 64 -112 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 1 +PIN 176 32 RIGHT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 2 +PIN -176 -64 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 3 +PIN -176 -16 LEFT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -176 32 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -176 80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 6 +PIN 176 80 RIGHT 8 +PINATTR PinName PwrGD +PINATTR SpiceOrder 7 +PIN 176 -16 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -64 128 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN 64 128 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 176 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 11 +PIN -64 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LTM4603-1.asy b/spice/copy/sym/PowerProducts/LTM4603-1.asy new file mode 100755 index 0000000..dd2a8ef --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4603-1.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 240 -192 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 135 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTM4603-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4603-1.sub +SYMATTR Value2 LTM4603-1 +SYMATTR Description 6A DC/DC µModule with PLL, Output Tracking and Margining +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 -208 RIGHT 8 +PINATTR PinName Vout_LCL +PINATTR SpiceOrder 5 +PIN -80 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -208 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -192 48 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 48 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 -16 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN 192 176 RIGHT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN -192 112 LEFT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 -80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN 192 112 RIGHT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN -192 176 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4603.asy b/spice/copy/sym/PowerProducts/LTM4603.asy new file mode 100755 index 0000000..56f5eb8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4603.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 304 -192 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 135 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTM4603 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4603.sub +SYMATTR Value2 LTM4603 +SYMATTR Description 6A DC/DC µModule with PLL, Output Tracking and Margining +PIN -80 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 112 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 192 -80 RIGHT 8 +PINATTR PinName Vout_LCL +PINATTR SpiceOrder 5 +PIN 192 -16 RIGHT 8 +PINATTR PinName DiffVout +PINATTR SpiceOrder 6 +PIN 192 48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 7 +PIN -80 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -208 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -192 48 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 240 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 176 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN -192 176 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN -192 112 LEFT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 -80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN 64 -256 TOP 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4603HV.asy b/spice/copy/sym/PowerProducts/LTM4603HV.asy new file mode 100755 index 0000000..5f0033c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4603HV.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 304 -192 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 135 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTM4603HV +SYMATTR Prefix X +SYMATTR SpiceModel LTM4603.sub +SYMATTR Value2 LTM4603 +SYMATTR Description 6A, 28Vin DC/DC µModule with PLL, Output Tracking and Margining +PIN -80 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 304 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -208 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 112 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 192 -80 RIGHT 8 +PINATTR PinName Vout_LCL +PINATTR SpiceOrder 5 +PIN 192 -16 RIGHT 8 +PINATTR PinName DiffVout +PINATTR SpiceOrder 6 +PIN 192 48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 7 +PIN -80 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -208 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -192 48 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 240 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 176 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN -192 176 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN -192 112 LEFT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 -80 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN 64 -256 TOP 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 -16 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4604.asy b/spice/copy/sym/PowerProducts/LTM4604.asy new file mode 100755 index 0000000..7d7d8b7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4604.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 112 -176 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 55 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTM4604 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4604.sub +SYMATTR Value2 LTM4604 +SYMATTR Description Low Voltage, 4A DC/DC µModule with Tracking +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 176 64 RIGHT 8 +PINATTR PinName Track +PINATTR SpiceOrder 2 +PIN -176 64 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 3 +PIN -176 -64 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 4 +PIN 176 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -176 0 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 6 +PIN 176 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTM4604A.asy b/spice/copy/sym/PowerProducts/LTM4604A.asy new file mode 100755 index 0000000..9cf1b67 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4604A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 112 -176 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 55 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTM4604A +SYMATTR Prefix X +SYMATTR SpiceModel LTM4604.sub +SYMATTR Value2 LTM4604 +SYMATTR Description Low Voltage, 4A DC/DC µModule with Tracking +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 176 64 RIGHT 8 +PINATTR PinName Track +PINATTR SpiceOrder 2 +PIN -176 64 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 3 +PIN -176 -64 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 4 +PIN 176 0 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 5 +PIN -176 0 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 6 +PIN 176 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN 0 -112 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTM4605.asy b/spice/copy/sym/PowerProducts/LTM4605.asy new file mode 100755 index 0000000..796d678 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4605.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -288 192 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM4605 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4605.sub +SYMATTR Value2 LTM4605 +SYMATTR Description High Efficiency Buck-Boost DC/DC µModule +PIN 192 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 192 -224 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -80 288 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 3 +PIN -80 -288 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN -192 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 64 -288 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 6 +PIN 192 -96 RIGHT 8 +PINATTR PinName Rsense +PINATTR SpiceOrder 7 +PIN 192 -32 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN 192 32 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 9 +PIN -192 96 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 10 +PIN -192 -32 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 11 +PIN -192 224 LEFT 8 +PINATTR PinName PLLFLTR +PINATTR SpiceOrder 12 +PIN -192 32 LEFT 8 +PINATTR PinName STBYMD +PINATTR SpiceOrder 13 +PIN 192 224 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN -192 -160 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 15 +PIN 192 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 160 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 17 +PIN 192 -160 RIGHT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 18 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 19 +PIN -192 -96 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4606.asy b/spice/copy/sym/PowerProducts/LTM4606.asy new file mode 100755 index 0000000..044a97c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4606.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 256 -192 -240 +TEXT 0 0 Center 2 LT +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value LTM4606 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4606.sub +SYMATTR Value2 LTM4606 +SYMATTR Description Ultralow EMI 28Vin,6A DC/DC µModule +PIN -80 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 80 256 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 192 -192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 192 -64 RIGHT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 4 +PIN -192 -64 LEFT 8 +PINATTR PinName Vd +PINATTR SpiceOrder 5 +PIN -80 256 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 8 +PIN -192 -192 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 10 +PIN -192 128 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 11 +PIN 192 128 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 12 +PIN 192 64 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN 192 0 RIGHT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 14 +PIN 192 192 RIGHT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 15 +PIN -192 0 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 -128 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 17 +PIN -192 192 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 18 +PIN 64 -240 TOP 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 19 +PIN -192 64 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4607.asy b/spice/copy/sym/PowerProducts/LTM4607.asy new file mode 100755 index 0000000..15c7ef0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4607.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -288 192 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM4607 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4607.sub +SYMATTR Value2 LTM4607 +SYMATTR Description 36Vin, 24Vout High Efficiency Buck-Boost DC/DC µModule +PIN 192 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 192 -224 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -80 288 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 3 +PIN -80 -288 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN -192 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 64 -288 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 6 +PIN 192 -96 RIGHT 8 +PINATTR PinName Rsense +PINATTR SpiceOrder 7 +PIN 192 -32 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN 192 32 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 9 +PIN -192 96 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 10 +PIN -192 -32 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 11 +PIN -192 224 LEFT 8 +PINATTR PinName PLLFLTR +PINATTR SpiceOrder 12 +PIN -192 32 LEFT 8 +PINATTR PinName STBYMD +PINATTR SpiceOrder 13 +PIN 192 224 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN -192 -160 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 15 +PIN 192 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 160 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 17 +PIN 192 -160 RIGHT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 18 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 19 +PIN -192 -96 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4608.asy b/spice/copy/sym/PowerProducts/LTM4608.asy new file mode 100755 index 0000000..b990876 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4608.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -304 192 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTM4608 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4608.sub +SYMATTR Value2 LTM4608 +SYMATTR Description Low Vin, 8A DC/DC µModule with Tracking, Margining, and Frequency Synchronization +PIN 192 -240 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -96 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 2 +PIN -192 240 LEFT 8 +PINATTR PinName PLLLPF +PINATTR SpiceOrder 3 +PIN 96 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 192 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN -192 -240 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 10 +PIN -192 80 LEFT 8 +PINATTR PinName CLKin +PINATTR SpiceOrder 11 +PIN -192 0 LEFT 8 +PINATTR PinName PHmode +PINATTR SpiceOrder 12 +PIN 96 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 +PIN 192 240 RIGHT 8 +PINATTR PinName MGN +PINATTR SpiceOrder 20 +PIN 192 160 RIGHT 8 +PINATTR PinName Bsel +PINATTR SpiceOrder 21 +PIN 0 -304 TOP 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 22 +PIN 192 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 29 +PIN -192 -80 LEFT 8 +PINATTR PinName Track +PINATTR SpiceOrder 30 +PIN 192 0 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 32 +PIN 192 80 RIGHT 8 +PINATTR PinName IthM +PINATTR SpiceOrder 33 +PIN -96 -304 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 34 +PIN -192 -160 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 37 +PIN -192 160 LEFT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4608A.asy b/spice/copy/sym/PowerProducts/LTM4608A.asy new file mode 100755 index 0000000..2cced9f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4608A.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -304 192 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTM4608A +SYMATTR Prefix X +SYMATTR SpiceModel LTM4608.sub +SYMATTR Value2 LTM4608 +SYMATTR Description Low Vin, 8A DC/DC µModule with Tracking, Margining, and Frequency Synchronization +PIN 192 -240 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -96 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 2 +PIN -192 240 LEFT 8 +PINATTR PinName PLLLPF +PINATTR SpiceOrder 3 +PIN 96 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 192 -160 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 6 +PIN -192 -240 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 10 +PIN -192 80 LEFT 8 +PINATTR PinName CLKin +PINATTR SpiceOrder 11 +PIN -192 0 LEFT 8 +PINATTR PinName PHmode +PINATTR SpiceOrder 12 +PIN 96 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 +PIN 192 240 RIGHT 8 +PINATTR PinName MGN +PINATTR SpiceOrder 20 +PIN 192 160 RIGHT 8 +PINATTR PinName Bsel +PINATTR SpiceOrder 21 +PIN 0 -304 TOP 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 22 +PIN 192 -80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 29 +PIN -192 -80 LEFT 8 +PINATTR PinName Track +PINATTR SpiceOrder 30 +PIN 192 0 RIGHT 8 +PINATTR PinName Ith +PINATTR SpiceOrder 32 +PIN 192 80 RIGHT 8 +PINATTR PinName IthM +PINATTR SpiceOrder 33 +PIN -96 -304 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 34 +PIN -192 -160 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 37 +PIN -192 160 LEFT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4609.asy b/spice/copy/sym/PowerProducts/LTM4609.asy new file mode 100755 index 0000000..0dc0dee --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4609.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -288 192 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM4609 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4609.sub +SYMATTR Value2 LTM4609 +SYMATTR Description 36Vin, 34Vout High Efficiency Buck-Boost DC/DC µModule +PIN 192 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 192 -224 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -80 288 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 3 +PIN -80 -288 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 4 +PIN -192 -224 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN 64 -288 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 6 +PIN 192 -96 RIGHT 8 +PINATTR PinName Rsense +PINATTR SpiceOrder 7 +PIN 192 -32 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 +PIN 192 32 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 9 +PIN -192 96 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 10 +PIN -192 -32 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 11 +PIN -192 224 LEFT 8 +PINATTR PinName PLLFLTR +PINATTR SpiceOrder 12 +PIN -192 32 LEFT 8 +PINATTR PinName STBYMD +PINATTR SpiceOrder 13 +PIN 192 224 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 14 +PIN -192 -160 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 15 +PIN 192 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -192 160 LEFT 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 17 +PIN 192 -160 RIGHT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 18 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 19 +PIN -192 -96 LEFT 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM4611.asy b/spice/copy/sym/PowerProducts/LTM4611.asy new file mode 100755 index 0000000..3608c70 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4611.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -288 176 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM4611 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4611.sub +SYMATTR Value2 LTM4611 +SYMATTR Description Ultralow Vin, 15A DC/DC µModule Regulator +PIN -176 48 LEFT 8 +PINATTR PinName Mode_PLLin +PINATTR SpiceOrder 1 +PIN -176 -144 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 2 +PIN 176 48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 3 +PIN 176 144 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 176 -240 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 176 -144 RIGHT 8 +PINATTR PinName Vout_lcl +PINATTR SpiceOrder 6 +PIN 176 -48 RIGHT 8 +PINATTR PinName DiffVout +PINATTR SpiceOrder 7 +PIN 48 -288 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 8 +PIN -48 288 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -176 -48 LEFT 8 +PINATTR PinName PLLFLTR/Fset +PINATTR SpiceOrder 10 +PIN 176 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN -176 144 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 12 +PIN -176 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 13 +PIN -176 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 14 +PIN -48 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 48 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTM4612.asy b/spice/copy/sym/PowerProducts/LTM4612.asy new file mode 100755 index 0000000..378235d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4612.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 288 -176 -288 +TEXT 0 0 Center 2 LT +WINDOW 3 0 112 Center 2 +WINDOW 0 0 -112 Center 2 +SYMATTR Value LTM4612 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4612.sub +SYMATTR Value2 LTM4612 +SYMATTR Description Ultralow Noise 36Vin, 15Vout, 5A, DC/DC µModule +PIN -64 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 176 -240 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN -176 240 LEFT 8 +PINATTR PinName VD +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 5 +PIN -176 -80 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 6 +PIN 64 -288 TOP 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 8 +PIN -176 160 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 9 +PIN 176 240 RIGHT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 10 +PIN -176 80 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 11 +PIN 176 -160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN 176 160 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 14 +PIN -64 288 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 15 +PIN 176 -80 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -176 -240 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 17 +PIN -176 -160 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 18 diff --git a/spice/copy/sym/PowerProducts/LTM4613.asy b/spice/copy/sym/PowerProducts/LTM4613.asy new file mode 100755 index 0000000..1eb5110 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4613.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 288 -176 -288 +TEXT 0 0 Center 2 LT +WINDOW 3 0 112 Center 2 +WINDOW 0 0 -112 Center 2 +SYMATTR Value LTM4613 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4613.sub +SYMATTR Value2 LTM4613 +SYMATTR Description EN55022B Compliant 36Vin, 15Vout, 8A, DC/DC µModule Regulator +PIN -64 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN 176 -240 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN -176 240 LEFT 8 +PINATTR PinName VD +PINATTR SpiceOrder 4 +PIN -176 0 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 5 +PIN -176 -80 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 6 +PIN 64 -288 TOP 8 +PINATTR PinName PLLIN +PINATTR SpiceOrder 7 +PIN 176 0 RIGHT 8 +PINATTR PinName FCB +PINATTR SpiceOrder 8 +PIN -176 160 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 9 +PIN 176 240 RIGHT 8 +PINATTR PinName MPGM +PINATTR SpiceOrder 10 +PIN -176 80 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 11 +PIN 176 -160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 12 +PIN 176 80 RIGHT 8 +PINATTR PinName MARG0 +PINATTR SpiceOrder 13 +PIN 176 160 RIGHT 8 +PINATTR PinName MARG1 +PINATTR SpiceOrder 14 +PIN -64 288 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 15 +PIN 176 -80 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 16 +PIN -176 -240 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 17 +PIN -176 -160 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 18 diff --git a/spice/copy/sym/PowerProducts/LTM4614.asy b/spice/copy/sym/PowerProducts/LTM4614.asy new file mode 100755 index 0000000..72e02f1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4614.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 224 -160 -224 +TEXT 0 0 Center 2 LT +WINDOW 3 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value LTM4614 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4614.sub +SYMATTR Value2 LTM4614 +SYMATTR Description Dual 4A per Channel Low Vin DC/DC µModule +PIN -48 224 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 1 +PIN -160 -96 LEFT 8 +PINATTR PinName Track1 +PINATTR SpiceOrder 2 +PIN -160 -32 LEFT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 3 +PIN -160 -160 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 4 +PIN 160 -96 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 5 +PIN 160 -32 RIGHT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 6 +PIN 160 -160 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 7 +PIN -48 -224 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 8 +PIN 48 224 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 11 +PIN 48 -224 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 12 +PIN 160 32 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 13 +PIN 160 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 14 +PIN 160 160 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 15 +PIN -160 32 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 16 +PIN -160 160 LEFT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 17 +PIN -160 96 LEFT 8 +PINATTR PinName Track2 +PINATTR SpiceOrder 18 diff --git a/spice/copy/sym/PowerProducts/LTM4615.asy b/spice/copy/sym/PowerProducts/LTM4615.asy new file mode 100755 index 0000000..df3ebec --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4615.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 320 -160 -320 +TEXT 0 0 Center 2 LT +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value LTM4615 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4615.sub +SYMATTR Value2 LTM4615 +SYMATTR Description Triple Output, Low Voltage DC/DC µModule +PIN -80 320 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 1 +PIN -160 -192 LEFT 8 +PINATTR PinName Track1 +PINATTR SpiceOrder 2 +PIN -160 -128 LEFT 8 +PINATTR PinName Run/SS1 +PINATTR SpiceOrder 3 +PIN -160 -256 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 4 +PIN 160 -192 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 5 +PIN 160 -128 RIGHT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 6 +PIN 160 -256 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 7 +PIN -48 -320 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 8 +PIN 0 320 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 11 +PIN 48 -320 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 12 +PIN 160 -64 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 13 +PIN 160 0 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 14 +PIN 160 64 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 15 +PIN -160 -64 LEFT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 16 +PIN -160 64 LEFT 8 +PINATTR PinName Run/SS2 +PINATTR SpiceOrder 17 +PIN -160 0 LEFT 8 +PINATTR PinName Track2 +PINATTR SpiceOrder 18 +PIN 160 128 RIGHT 8 +PINATTR PinName LDO_IN +PINATTR SpiceOrder 19 +PIN -160 192 LEFT 8 +PINATTR PinName Boost3 +PINATTR SpiceOrder 20 +PIN -160 256 LEFT 8 +PINATTR PinName EN3 +PINATTR SpiceOrder 21 +PIN 80 320 BOTTOM 8 +PINATTR PinName GND3 +PINATTR SpiceOrder 22 +PIN 160 192 RIGHT 8 +PINATTR PinName LDO_OUT +PINATTR SpiceOrder 24 +PIN 160 256 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 25 +PIN -160 128 LEFT 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 26 diff --git a/spice/copy/sym/PowerProducts/LTM4616.asy b/spice/copy/sym/PowerProducts/LTM4616.asy new file mode 100755 index 0000000..4f52dc6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4616.asy @@ -0,0 +1,125 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -320 -480 320 480 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTM4616 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4616.sub +SYMATTR Value2 LTM4616 +SYMATTR Description Dual 8A per Channel Low Vin DC/DC µModule +PIN 320 -416 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 1 +PIN -224 480 BOTTOM 8 +PINATTR PinName SGND1 +PINATTR SpiceOrder 2 +PIN -320 -160 LEFT 8 +PINATTR PinName PLLLPF1 +PINATTR SpiceOrder 3 +PIN -320 -416 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -320 288 LEFT 8 +PINATTR PinName PLLLPF2 +PINATTR SpiceOrder 5 +PIN 320 -352 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 6 +PIN 0 -480 TOP 8 +PINATTR PinName CLKin2 +PINATTR SpiceOrder 7 +PIN 112 -480 TOP 8 +PINATTR PinName CLKout2 +PINATTR SpiceOrder 8 +PIN -320 416 LEFT 8 +PINATTR PinName PHmode2 +PINATTR SpiceOrder 9 +PIN -320 -96 LEFT 8 +PINATTR PinName Mode1 +PINATTR SpiceOrder 10 +PIN -224 -480 TOP 8 +PINATTR PinName CLKin1 +PINATTR SpiceOrder 11 +PIN -320 -32 LEFT 8 +PINATTR PinName PHmode1 +PINATTR SpiceOrder 12 +PIN -112 480 BOTTOM 8 +PINATTR PinName GND1 +PINATTR SpiceOrder 13 +PIN -320 96 LEFT 8 +PINATTR PinName SVin2 +PINATTR SpiceOrder 14 +PIN 0 480 BOTTOM 8 +PINATTR PinName SGND2 +PINATTR SpiceOrder 15 +PIN 112 480 BOTTOM 8 +PINATTR PinName GND2 +PINATTR SpiceOrder 17 +PIN -320 32 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 18 +PIN 320 96 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 320 -32 RIGHT 8 +PINATTR PinName MGN1 +PINATTR SpiceOrder 20 +PIN 320 -96 RIGHT 8 +PINATTR PinName Bsel1 +PINATTR SpiceOrder 21 +PIN 224 -480 TOP 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 22 +PIN 320 160 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 23 +PIN 320 416 RIGHT 8 +PINATTR PinName MGN2 +PINATTR SpiceOrder 24 +PIN 320 352 RIGHT 8 +PINATTR PinName Bsel2 +PINATTR SpiceOrder 25 +PIN -320 224 LEFT 8 +PINATTR PinName Track2 +PINATTR SpiceOrder 26 +PIN -320 160 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 27 +PIN -320 352 LEFT 8 +PINATTR PinName Mode2 +PINATTR SpiceOrder 28 +PIN 320 -288 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 29 +PIN -320 -224 LEFT 8 +PINATTR PinName Track1 +PINATTR SpiceOrder 30 +PIN 320 224 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 31 +PIN 320 -224 RIGHT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 32 +PIN 320 -160 RIGHT 8 +PINATTR PinName IthM1 +PINATTR SpiceOrder 33 +PIN -320 -352 LEFT 8 +PINATTR PinName SVin1 +PINATTR SpiceOrder 34 +PIN 320 288 RIGHT 8 +PINATTR PinName IthM2 +PINATTR SpiceOrder 35 +PIN 224 480 BOTTOM 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 36 +PIN -320 -288 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 37 +PIN -112 -480 TOP 8 +PINATTR PinName CLKout1 +PINATTR SpiceOrder 38 +PIN 320 32 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 39 diff --git a/spice/copy/sym/PowerProducts/LTM4618.asy b/spice/copy/sym/PowerProducts/LTM4618.asy new file mode 100755 index 0000000..3ad553a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4618.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -240 176 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM4618 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4618.sub +SYMATTR Value2 LTM4618 +SYMATTR Description 6A DC/DC µModule Regulator with Tracking and Frequency Synchronization +PIN -176 0 LEFT 8 +PINATTR PinName Mode/PLLin +PINATTR SpiceOrder 1 +PIN 176 -96 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 2 +PIN 176 96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 3 +PIN 176 -192 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 4 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 48 -240 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 8 +PIN -48 240 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -176 -96 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 10 +PIN 176 192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN -176 96 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 12 +PIN -176 192 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 13 +PIN -176 -192 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 14 +PIN -48 -240 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 48 240 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/PowerProducts/LTM4619.asy b/spice/copy/sym/PowerProducts/LTM4619.asy new file mode 100755 index 0000000..dfae42f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4619.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -400 224 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LTM4619 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4619.sub +SYMATTR Value2 LTM4619 +SYMATTR Description Dual, 26Vin, 4A DC/DC µModule Regulator +PIN -224 240 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 1 +PIN -224 -48 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 2 +PIN 224 -48 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 3 +PIN -224 48 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN 224 336 RIGHT 8 +PINATTR PinName Freq/PLLFLTR +PINATTR SpiceOrder 5 +PIN -224 336 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 6 +PIN 224 -240 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 7 +PIN -224 144 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 8 +PIN -80 400 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -224 -240 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 10 +PIN 224 144 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 11 +PIN 224 48 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 12 +PIN 224 240 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 15 +PIN 224 -144 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 17 +PIN 64 400 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 20 +PIN 64 -400 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 21 +PIN -64 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 24 +PIN -224 -144 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 26 +PIN -224 -336 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 28 +PIN 224 -336 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LTM4620.asy b/spice/copy/sym/PowerProducts/LTM4620.asy new file mode 100755 index 0000000..ee866e4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4620.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4620 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4620.sub +SYMATTR Value2 LTM4620 +SYMATTR Description High Efficiency Dual 13A or Single 26A µModule +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4620A.asy b/spice/copy/sym/PowerProducts/LTM4620A.asy new file mode 100755 index 0000000..d076312 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4620A.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4620A +SYMATTR Prefix X +SYMATTR SpiceModel LTM4620A.sub +SYMATTR Value2 LTM4620A +SYMATTR Description Dual 13A or Single 26A DC/DC µModule Regulator +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4622.asy b/spice/copy/sym/PowerProducts/LTM4622.asy new file mode 100755 index 0000000..6259c4b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4622.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -304 192 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM4622 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4622.sub +SYMATTR Value2 LTM4622 +SYMATTR Description Dual Ultrathin 2.5A Step-Down DC/DC µModule Regulator +PIN -192 -144 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 1 +PIN -192 -240 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 3 +PIN 96 -304 TOP 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 4 +PIN 64 304 BOTTOM 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 5 +PIN 192 -240 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 6 +PIN -64 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 7 +PIN 192 -144 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 8 +PIN 192 48 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN 192 240 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 10 +PIN 192 144 RIGHT 8 +PINATTR PinName COMP2 +PINATTR SpiceOrder 11 +PIN 0 -304 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 19 +PIN -96 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 +PIN -192 144 LEFT 8 +PINATTR PinName COMP1 +PINATTR SpiceOrder 26 +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 27 +PIN -192 48 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 28 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 2 +PIN -192 -48 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/PowerProducts/LTM4622A.asy b/spice/copy/sym/PowerProducts/LTM4622A.asy new file mode 100755 index 0000000..8c632b8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4622A.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -304 192 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 -2 97 Center 2 +SYMATTR Value LTM4622A +SYMATTR Prefix X +SYMATTR SpiceModel LTM4622A.sub +SYMATTR Value2 LTM4622A +SYMATTR Description Dual Ultrathin 2A or Single 4A Step-Down DC/DC µModule Regulator +PIN -192 -144 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 1 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 2 +PIN -192 -240 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 3 +PIN 48 -304 TOP 8 +PINATTR PinName Mode +PINATTR SpiceOrder 4 +PIN 64 304 BOTTOM 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 5 +PIN 192 -240 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 6 +PIN -64 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 7 +PIN 192 -144 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 8 +PIN 192 48 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN 192 240 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 10 +PIN 192 144 RIGHT 8 +PINATTR PinName COMP2 +PINATTR SpiceOrder 11 +PIN -192 -48 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 12 +PIN -48 -304 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 13 +PIN -128 -304 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 14 +PIN 128 -304 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 15 +PIN -192 144 LEFT 8 +PINATTR PinName COMP1 +PINATTR SpiceOrder 16 +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 17 +PIN -192 48 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 18 diff --git a/spice/copy/sym/PowerProducts/LTM4623.asy b/spice/copy/sym/PowerProducts/LTM4623.asy new file mode 100755 index 0000000..82d4b5b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4623.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 304 -176 -304 +TEXT 0 0 Center 2 LT +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value LTM4623 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4623.sub +SYMATTR Value2 LTM4623 +SYMATTR Description Ultrathin 20Vin, 3A Step-Down DC/DC µModule Regulator +PIN -176 240 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 1 +PIN 176 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN -176 -144 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 3 +PIN 176 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -176 -48 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 5 +PIN 176 144 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 6 +PIN -176 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN 176 -240 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN 176 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 9 +PIN 64 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -64 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 64 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN -64 -304 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 13 +PIN -176 48 LEFT 8 +PINATTR PinName CLKIN +PINATTR SpiceOrder 17 +PIN 176 240 RIGHT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 18 +PIN -176 144 LEFT 8 +PINATTR PinName PhMode +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LTM4624.asy b/spice/copy/sym/PowerProducts/LTM4624.asy new file mode 100755 index 0000000..617123a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4624.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 224 -176 -224 +TEXT 0 0 Center 2 LT +WINDOW 3 0 112 Center 2 +WINDOW 0 0 -112 Center 2 +SYMATTR Value LTM4624 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4624.sub +SYMATTR Value2 LTM4624 +SYMATTR Description 14Vin, 4A Step-Down DC/DC µModule Regulator +PIN -176 80 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 1 +PIN 0 -224 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 2 +PIN 176 -160 RIGHT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 3 +PIN 176 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -176 160 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 5 +PIN 176 160 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 6 +PIN -176 0 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN 176 -80 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 9 +PIN 64 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -64 224 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN -176 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 12 +PIN -176 -80 LEFT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTM4625.asy b/spice/copy/sym/PowerProducts/LTM4625.asy new file mode 100755 index 0000000..5b9890e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4625.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 304 -176 -304 +TEXT 0 0 Center 2 LT +WINDOW 3 0 96 Center 2 +WINDOW 0 0 -96 Center 2 +SYMATTR Value LTM4625 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4625.sub +SYMATTR Value2 LTM4625 +SYMATTR Description 20V, 5A Step-Down µModule Regulator +PIN -176 240 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 1 +PIN -176 144 LEFT 8 +PINATTR PinName PhMode +PINATTR SpiceOrder 2 +PIN -176 -144 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 3 +PIN 176 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -176 -48 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 5 +PIN 176 144 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 6 +PIN -176 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN 176 -240 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN 176 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 9 +PIN 64 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 64 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 17 +PIN -64 -304 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 19 +PIN 176 -144 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN -64 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 22 +PIN 176 240 RIGHT 8 +PINATTR PinName CLKOUT +PINATTR SpiceOrder 23 +PIN -176 48 LEFT 8 +PINATTR PinName CLKIN +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LTM4626.asy b/spice/copy/sym/PowerProducts/LTM4626.asy new file mode 100755 index 0000000..6e8e97c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4626.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 336 352 -336 -352 +TEXT 0 0 Center 2 LT +WINDOW 3 0 144 Center 2 +WINDOW 0 0 -144 Center 2 +SYMATTR Value LTM4626 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4626.sub +SYMATTR Value2 LTM4626 +SYMATTR Description 20Vin, 12A Step-Down DC/DC µModule Regulator +PIN -336 96 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 1 +PIN 80 -352 TOP 8 +PINATTR PinName PhMode +PINATTR SpiceOrder 2 +PIN 336 192 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 3 +PIN 336 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -336 0 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 5 +PIN -336 288 LEFT 8 +PINATTR PinName COMPa +PINATTR SpiceOrder 6 +PIN -336 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN 336 -96 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -336 192 LEFT 8 +PINATTR PinName COMPb +PINATTR SpiceOrder 9 +PIN 0 352 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 336 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 11 +PIN 336 -288 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 12 +PIN 336 0 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 13 +PIN 336 288 RIGHT 8 +PINATTR PinName Tsense+ +PINATTR SpiceOrder 14 +PIN 192 352 BOTTOM 8 +PINATTR PinName Tsense- +PINATTR SpiceOrder 15 +PIN -336 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 17 +PIN -240 -352 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 240 -352 TOP 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 23 +PIN -80 -352 TOP 8 +PINATTR PinName Mode/CLKin +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LTM4627.asy b/spice/copy/sym/PowerProducts/LTM4627.asy new file mode 100755 index 0000000..ad9dd42 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4627.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -288 208 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM4627 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4627.sub +SYMATTR Value2 LTM4627 +SYMATTR Description 15A DC/DC µModule Regulator +PIN -208 48 LEFT 8 +PINATTR PinName Mode_PLLin +PINATTR SpiceOrder 1 +PIN -208 -144 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 2 +PIN 208 48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 3 +PIN 208 144 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 208 -240 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 208 -144 RIGHT 8 +PINATTR PinName Vout_lcl +PINATTR SpiceOrder 6 +PIN 208 -48 RIGHT 8 +PINATTR PinName Diff_Out +PINATTR SpiceOrder 7 +PIN 96 -288 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 8 +PIN -64 288 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -208 -48 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 10 +PIN 208 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN -208 144 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 12 +PIN -208 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 13 +PIN -208 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 14 +PIN -96 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 +PIN 0 -288 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTM4628.asy b/spice/copy/sym/PowerProducts/LTM4628.asy new file mode 100755 index 0000000..fd54690 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4628.asy @@ -0,0 +1,92 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4628 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4628.sub +SYMATTR Value2 LTM4628 +SYMATTR Description High Efficiency Dual 8A or Single 16A µModule +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -144 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 48 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN -48 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 144 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4630-1.asy b/spice/copy/sym/PowerProducts/LTM4630-1.asy new file mode 100755 index 0000000..1699db9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4630-1.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4630-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4630-1.sub +SYMATTR Value2 LTM4630-1 +SYMATTR Description Dual 18A or Single 36A µModule Regulator with ±1% DC and ±3% Transient Accuracy +PIN -288 288 LEFT 8 +PINATTR PinName Track1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName Track2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode_PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4630.asy b/spice/copy/sym/PowerProducts/LTM4630.asy new file mode 100755 index 0000000..d4268cd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4630.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4630 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4630.sub +SYMATTR Value2 LTM4630 +SYMATTR Description Dual 18A or Single 36A DC/DC µModule Regulator +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4630A.asy b/spice/copy/sym/PowerProducts/LTM4630A.asy new file mode 100755 index 0000000..563333f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4630A.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4630A +SYMATTR Prefix X +SYMATTR SpiceModel LTM4630A.sub +SYMATTR Value2 LTM4630A +SYMATTR Description Dual 18A or Single 36A DC/DC µModule Regulator +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4631.asy b/spice/copy/sym/PowerProducts/LTM4631.asy new file mode 100755 index 0000000..004a3ce --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4631.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4631 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4631.sub +SYMATTR Value2 LTM4631 +SYMATTR Description Ultrathin Dual 10A or Single 20A DC/DC µModule Regulator +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4632.asy b/spice/copy/sym/PowerProducts/LTM4632.asy new file mode 100755 index 0000000..ab4d338 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4632.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -304 192 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM4632 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4632.sub +SYMATTR Value2 LTM4632 +SYMATTR Description Ultrathin, Step-Down µModule Regulator for DDR-QDR4 Memory Power +PIN -192 -144 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 1 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 2 +PIN -192 -240 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 3 +PIN 64 304 BOTTOM 8 +PINATTR PinName Sync/Mode +PINATTR SpiceOrder 4 +PIN 192 -240 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 6 +PIN -64 304 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 7 +PIN 192 -144 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 8 +PIN -192 144 LEFT 8 +PINATTR PinName VDDQin +PINATTR SpiceOrder 10 +PIN 192 240 RIGHT 8 +PINATTR PinName COMP2 +PINATTR SpiceOrder 11 +PIN -192 -48 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 12 +PIN 192 48 RIGHT 8 +PINATTR PinName VTTR +PINATTR SpiceOrder 18 +PIN 64 -304 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 19 +PIN -64 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 +PIN 192 144 RIGHT 8 +PINATTR PinName COMP1 +PINATTR SpiceOrder 26 +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 27 +PIN -192 48 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTM4633.asy b/spice/copy/sym/PowerProducts/LTM4633.asy new file mode 100755 index 0000000..58d3af1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4633.asy @@ -0,0 +1,107 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -672 -400 672 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM4633 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4633.sub +SYMATTR Value2 LTM4633 +SYMATTR Description Triple 10A Step-Down DC/DC µModule Regulator +PIN 672 240 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 1 +PIN 400 400 BOTTOM 8 +PINATTR PinName TK/SS3 +PINATTR SpiceOrder 2 +PIN -672 -48 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 3 +PIN -672 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -400 400 BOTTOM 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 5 +PIN -80 400 BOTTOM 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 6 +PIN 560 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -672 336 LEFT 8 +PINATTR PinName Temp1 +PINATTR SpiceOrder 8 +PIN -672 48 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 9 +PIN -672 144 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 10 +PIN 240 -400 TOP 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 672 48 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 12 +PIN 672 144 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 13 +PIN 80 400 BOTTOM 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 14 +PIN 240 400 BOTTOM 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 15 +PIN -80 -400 TOP 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 16 +PIN 80 -400 TOP 8 +PINATTR PinName Pgood12 +PINATTR SpiceOrder 17 +PIN 672 336 RIGHT 8 +PINATTR PinName Temp2 +PINATTR SpiceOrder 18 +PIN -240 400 BOTTOM 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 20 +PIN -400 -400 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 22 +PIN -240 -400 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 23 +PIN -560 -400 TOP 8 +PINATTR PinName CNTL_PWR +PINATTR SpiceOrder 24 +PIN 672 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 25 +PIN 672 -48 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 26 +PIN 672 -144 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 27 +PIN -672 -144 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN -560 400 BOTTOM 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 34 +PIN 672 -336 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 35 +PIN -672 -336 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 36 +PIN 400 -400 TOP 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 37 +PIN 560 -400 TOP 8 +PINATTR PinName Freq/PLLFLTR +PINATTR SpiceOrder 38 +PIN -672 240 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 40 diff --git a/spice/copy/sym/PowerProducts/LTM4634.asy b/spice/copy/sym/PowerProducts/LTM4634.asy new file mode 100755 index 0000000..eb5b146 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4634.asy @@ -0,0 +1,107 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -672 -400 672 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM4634 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4634.sub +SYMATTR Value2 LTM4634 +SYMATTR Description Triple Output 5A/5A/4A Step-Down DC/DC µModule Regulator +PIN 672 240 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 1 +PIN 400 400 BOTTOM 8 +PINATTR PinName TK/SS3 +PINATTR SpiceOrder 2 +PIN -672 -48 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 3 +PIN -672 -240 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN -400 400 BOTTOM 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 5 +PIN -80 400 BOTTOM 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 6 +PIN 560 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -672 336 LEFT 8 +PINATTR PinName Temp1 +PINATTR SpiceOrder 8 +PIN -672 48 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 9 +PIN -672 144 LEFT 8 +PINATTR PinName Ith1 +PINATTR SpiceOrder 10 +PIN 240 -400 TOP 8 +PINATTR PinName SGND +PINATTR SpiceOrder 11 +PIN 672 48 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 12 +PIN 672 144 RIGHT 8 +PINATTR PinName Ith2 +PINATTR SpiceOrder 13 +PIN 80 400 BOTTOM 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 14 +PIN 240 400 BOTTOM 8 +PINATTR PinName Ith3 +PINATTR SpiceOrder 15 +PIN -80 -400 TOP 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 16 +PIN 80 -400 TOP 8 +PINATTR PinName Pgood12 +PINATTR SpiceOrder 17 +PIN 672 336 RIGHT 8 +PINATTR PinName Temp2 +PINATTR SpiceOrder 18 +PIN -240 400 BOTTOM 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 20 +PIN -400 -400 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 22 +PIN -240 -400 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 23 +PIN -560 -400 TOP 8 +PINATTR PinName CNTL_PWR +PINATTR SpiceOrder 24 +PIN 672 -240 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 25 +PIN 672 -48 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 26 +PIN 672 -144 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 27 +PIN -672 -144 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN -560 400 BOTTOM 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 34 +PIN 672 -336 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 35 +PIN -672 -336 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 36 +PIN 400 -400 TOP 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 37 +PIN 560 -400 TOP 8 +PINATTR PinName Freq/PLLFLTR +PINATTR SpiceOrder 38 +PIN -672 240 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 40 diff --git a/spice/copy/sym/PowerProducts/LTM4636-1.asy b/spice/copy/sym/PowerProducts/LTM4636-1.asy new file mode 100755 index 0000000..781f2ec --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4636-1.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 272 -496 -304 496 +TEXT 0 0 Center 2 LT +WINDOW 0 -3 -240 Center 2 +WINDOW 3 -10 239 Center 2 +SYMATTR Value LTM4636-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4636-1.sub +SYMATTR Value2 LTM4636-1 +SYMATTR Description 40A µModule Regulator with OverVoltage/ \n\n OverTemperature Protection +PIN -304 240 LEFT 8 +PINATTR PinName COMPA +PINATTR SpiceOrder 2 +PIN 272 144 RIGHT 8 +PINATTR PinName VoutS1- +PINATTR SpiceOrder 3 +PIN 272 432 RIGHT 8 +PINATTR PinName VFB +PINATTR SpiceOrder 4 +PIN -304 432 LEFT 8 +PINATTR PinName TK/SS +PINATTR SpiceOrder 5 +PIN 48 -496 TOP 8 +PINATTR PinName HiZReg +PINATTR SpiceOrder 6 +PIN -304 144 LEFT 8 +PINATTR PinName COMPB +PINATTR SpiceOrder 8 +PIN -304 336 LEFT 8 +PINATTR PinName RunC +PINATTR SpiceOrder 9 +PIN -80 496 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 10 +PIN 272 -48 RIGHT 8 +PINATTR PinName VOUT +PINATTR SpiceOrder 11 +PIN 272 336 RIGHT 8 +PINATTR PinName SNSP2 +PINATTR SpiceOrder 12 +PIN 272 240 RIGHT 8 +PINATTR PinName SNSP1 +PINATTR SpiceOrder 13 +PIN -208 496 BOTTOM 8 +PINATTR PinName PGood +PINATTR SpiceOrder 14 +PIN -304 48 LEFT 8 +PINATTR PinName PVCC +PINATTR SpiceOrder 15 +PIN -80 -496 TOP 8 +PINATTR PinName RunP +PINATTR SpiceOrder 16 +PIN 272 -144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 17 +PIN 272 -240 RIGHT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 18 +PIN 272 48 RIGHT 8 +PINATTR PinName VoutS1+ +PINATTR SpiceOrder 19 +PIN 48 496 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 21 +PIN -304 -336 LEFT 8 +PINATTR PinName OVP_Set +PINATTR SpiceOrder 23 +PIN 272 -336 RIGHT 8 +PINATTR PinName CROWBAR +PINATTR SpiceOrder 24 +PIN -304 -432 LEFT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 25 +PIN 272 -432 RIGHT 8 +PINATTR PinName OVP_Trip +PINATTR SpiceOrder 26 +PIN -304 -48 LEFT 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 30 +PIN -304 -240 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 31 +PIN -304 -144 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 32 +PIN 176 496 BOTTOM 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 33 +PIN 176 -496 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 34 +PIN -208 -496 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 35 diff --git a/spice/copy/sym/PowerProducts/LTM4636.asy b/spice/copy/sym/PowerProducts/LTM4636.asy new file mode 100755 index 0000000..f48d8f6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4636.asy @@ -0,0 +1,83 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 272 -400 -304 400 +TEXT 0 1 Center 2 LT +WINDOW 0 -3 -193 Center 2 +WINDOW 3 1 190 Center 2 +SYMATTR Value LTM4636 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4636.sub +SYMATTR Value2 LTM4636 +SYMATTR Description 40A DC/DC µModule Regulator +PIN -208 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -304 144 LEFT 8 +PINATTR PinName COMPA +PINATTR SpiceOrder 2 +PIN 272 48 RIGHT 8 +PINATTR PinName VoutS1- +PINATTR SpiceOrder 3 +PIN 272 336 RIGHT 8 +PINATTR PinName VFB +PINATTR SpiceOrder 4 +PIN -304 336 LEFT 8 +PINATTR PinName TK/SS +PINATTR SpiceOrder 5 +PIN 48 -400 TOP 8 +PINATTR PinName HiZReg +PINATTR SpiceOrder 6 +PIN 176 -400 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 7 +PIN -304 48 LEFT 8 +PINATTR PinName COMPB +PINATTR SpiceOrder 8 +PIN -304 240 LEFT 8 +PINATTR PinName RunC +PINATTR SpiceOrder 9 +PIN -80 400 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 10 +PIN 272 -144 RIGHT 8 +PINATTR PinName VOUT +PINATTR SpiceOrder 11 +PIN 272 240 RIGHT 8 +PINATTR PinName SNSP2 +PINATTR SpiceOrder 12 +PIN 272 144 RIGHT 8 +PINATTR PinName SNSP1 +PINATTR SpiceOrder 13 +PIN -208 400 BOTTOM 8 +PINATTR PinName PGood +PINATTR SpiceOrder 14 +PIN -304 -48 LEFT 8 +PINATTR PinName PVCC +PINATTR SpiceOrder 15 +PIN -80 -400 TOP 8 +PINATTR PinName RunP +PINATTR SpiceOrder 16 +PIN 272 -240 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 17 +PIN 272 -336 RIGHT 8 +PINATTR PinName PWM2 +PINATTR SpiceOrder 18 +PIN 272 -48 RIGHT 8 +PINATTR PinName VoutS1+ +PINATTR SpiceOrder 19 +PIN 176 400 BOTTOM 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 20 +PIN 48 400 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 21 +PIN -304 -240 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 22 +PIN -304 -336 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 23 +PIN -304 -144 LEFT 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LTM4637.asy b/spice/copy/sym/PowerProducts/LTM4637.asy new file mode 100755 index 0000000..c26a743 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4637.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -288 208 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM4637 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4637.sub +SYMATTR Value2 LTM4637 +SYMATTR Description 20A DC/DC µModule Step-Down Regulator +PIN -208 48 LEFT 8 +PINATTR PinName Mode_PLLin +PINATTR SpiceOrder 1 +PIN -208 -144 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 2 +PIN 208 48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 3 +PIN 208 144 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 208 -240 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 208 -144 RIGHT 8 +PINATTR PinName Vout_lcl +PINATTR SpiceOrder 6 +PIN 208 -48 RIGHT 8 +PINATTR PinName Diff_Out +PINATTR SpiceOrder 7 +PIN 96 -288 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 8 +PIN -64 288 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -208 -48 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 10 +PIN 208 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN -208 144 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 12 +PIN -208 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 13 +PIN -208 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 14 +PIN -96 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 64 288 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 +PIN 0 -288 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTM4638.asy b/spice/copy/sym/PowerProducts/LTM4638.asy new file mode 100755 index 0000000..34345b4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4638.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 336 352 -336 -352 +TEXT 0 0 Center 2 LT +WINDOW 3 0 144 Center 2 +WINDOW 0 0 -144 Center 2 +SYMATTR Value LTM4638 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4638.sub +SYMATTR Value2 LTM4638 +SYMATTR Description 20Vin, 15A Step-Down DC/DC µModule Regulator +PIN -336 96 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 1 +PIN 80 -352 TOP 8 +PINATTR PinName PhMode +PINATTR SpiceOrder 2 +PIN 336 192 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 3 +PIN 336 96 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN -336 0 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 5 +PIN -336 288 LEFT 8 +PINATTR PinName COMPa +PINATTR SpiceOrder 6 +PIN -336 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN 336 -96 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -336 192 LEFT 8 +PINATTR PinName COMPb +PINATTR SpiceOrder 9 +PIN 0 352 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 10 +PIN 336 -192 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 11 +PIN 336 -288 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 12 +PIN 336 0 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 13 +PIN 336 288 RIGHT 8 +PINATTR PinName Tsense+ +PINATTR SpiceOrder 14 +PIN 192 352 BOTTOM 8 +PINATTR PinName Tsense- +PINATTR SpiceOrder 15 +PIN -336 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 17 +PIN -240 -352 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 21 +PIN 240 -352 TOP 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 23 +PIN -80 -352 TOP 8 +PINATTR PinName Mode/CLKin +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LTM4639.asy b/spice/copy/sym/PowerProducts/LTM4639.asy new file mode 100755 index 0000000..6219eed --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4639.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -384 208 384 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTM4639 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4639.sub +SYMATTR Value2 LTM4639 +SYMATTR Description Low Vin 20A DC/DC µModule Step-Down Regulator \n\n[Note]: OT_Test pin is not modeled +PIN -208 48 LEFT 8 +PINATTR PinName Mode_PLLin +PINATTR SpiceOrder 1 +PIN -208 -144 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 2 +PIN 208 -48 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 3 +PIN 208 48 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 4 +PIN 208 -336 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 208 -240 RIGHT 8 +PINATTR PinName Vout_lcl +PINATTR SpiceOrder 6 +PIN 208 -144 RIGHT 8 +PINATTR PinName Diff_Out +PINATTR SpiceOrder 7 +PIN 96 -384 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 8 +PIN -64 384 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 9 +PIN -208 -48 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 10 +PIN 208 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 208 240 RIGHT 8 +PINATTR PinName CompA +PINATTR SpiceOrder 12 +PIN -208 144 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 13 +PIN -208 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 14 +PIN -208 -336 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 15 +PIN 64 384 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 16 +PIN 0 -384 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 17 +PIN 208 336 RIGHT 8 +PINATTR PinName CompB +PINATTR SpiceOrder 18 +PIN -96 -384 TOP 8 +PINATTR PinName CPWR +PINATTR SpiceOrder 19 +PIN -208 240 LEFT 8 +PINATTR PinName Temp+ +PINATTR SpiceOrder 20 +PIN -208 336 LEFT 8 +PINATTR PinName Temp- +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LTM4641.asy b/spice/copy/sym/PowerProducts/LTM4641.asy new file mode 100755 index 0000000..5ddbd7d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4641.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 208 496 -208 -496 +TEXT 0 0 Center 2 LT +WINDOW 123 0 192 Center 2 +WINDOW 0 0 -192 Center 2 +SYMATTR Value2 LTM4641 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4641.sub +SYMATTR Value LTM4641 +SYMATTR Description 38V, 8A DC/DC µModule Regulator with Advanced Input and Output Protection +PIN -160 496 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 1 +PIN -208 -48 LEFT 8 +PINATTR PinName HYST +PINATTR SpiceOrder 2 +PIN -208 48 LEFT 8 +PINATTR PinName IOVRETRY +PINATTR SpiceOrder 3 +PIN 160 496 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -208 240 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 5 +PIN -208 336 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 6 +PIN 208 144 RIGHT 8 +PINATTR PinName CROWBAR +PINATTR SpiceOrder 7 +PIN 208 336 RIGHT 8 +PINATTR PinName OVpgm +PINATTR SpiceOrder 8 +PIN 208 240 RIGHT 8 +PINATTR PinName _LATCH +PINATTR SpiceOrder 9 +PIN -208 -336 LEFT 8 +PINATTR PinName 1Vref +PINATTR SpiceOrder 10 +PIN 208 -432 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 11 +PIN 208 -240 RIGHT 8 +PINATTR PinName Vorb+ +PINATTR SpiceOrder 12 +PIN 208 48 RIGHT 8 +PINATTR PinName Vorb- +PINATTR SpiceOrder 13 +PIN -208 144 LEFT 8 +PINATTR PinName PGOOD +PINATTR SpiceOrder 14 +PIN -80 496 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 15 +PIN -208 -432 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 16 +PIN 208 -144 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 17 +PIN 208 -48 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 18 +PIN 208 -336 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 19 +PIN 208 432 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 20 +PIN -208 432 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 21 +PIN -144 -496 TOP 8 +PINATTR PinName VinL +PINATTR SpiceOrder 22 +PIN -208 -240 LEFT 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 23 +PIN 80 496 BOTTOM 8 +PINATTR PinName FCB +PINATTR SpiceOrder 24 +PIN -208 -144 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 25 +PIN 144 -496 TOP 8 +PINATTR PinName VinH +PINATTR SpiceOrder 26 +PIN 0 496 BOTTOM 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 28 +PIN -48 -496 TOP 8 +PINATTR PinName VinG +PINATTR SpiceOrder 29 +PIN 48 -496 TOP 8 +PINATTR PinName VinGP +PINATTR SpiceOrder 30 diff --git a/spice/copy/sym/PowerProducts/LTM4642.asy b/spice/copy/sym/PowerProducts/LTM4642.asy new file mode 100755 index 0000000..256886d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4642.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -320 -464 320 464 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4642 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4642.sub +SYMATTR Value2 LTM4642 +SYMATTR Description 20Vin, Dual 4A or Single 8A DC/DC µModule Regulator +PIN 160 -464 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 1 +PIN -128 464 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN -320 -112 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 3 +PIN -320 -16 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 4 +PIN -256 -464 TOP 8 +PINATTR PinName Vrng1 +PINATTR SpiceOrder 5 +PIN -320 80 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 6 +PIN -320 176 LEFT 8 +PINATTR PinName Vfb1 +PINATTR SpiceOrder 7 +PIN -16 464 BOTTOM 8 +PINATTR PinName VoutS- +PINATTR SpiceOrder 8 +PIN 320 -208 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 9 +PIN 256 -464 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 10 +PIN 320 -112 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 11 +PIN 320 -16 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 12 +PIN 320 176 RIGHT 8 +PINATTR PinName Vfb2 +PINATTR SpiceOrder 13 +PIN -240 464 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN 320 272 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 15 +PIN 320 80 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 16 +PIN -144 -464 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 17 +PIN -32 -464 TOP 8 +PINATTR PinName DrVcc +PINATTR SpiceOrder 18 +PIN 320 -304 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 19 +PIN 320 368 RIGHT 8 +PINATTR PinName Track2 +PINATTR SpiceOrder 20 +PIN -320 272 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 21 +PIN 96 464 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 22 +PIN 224 464 BOTTOM 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 23 +PIN -320 -384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 24 +PIN 320 -384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 25 +PIN -320 -304 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 26 +PIN -320 368 LEFT 8 +PINATTR PinName Track1 +PINATTR SpiceOrder 27 +PIN -320 -208 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 28 +PIN 64 -464 TOP 8 +PINATTR PinName Cpwr +PINATTR SpiceOrder 29 diff --git a/spice/copy/sym/PowerProducts/LTM4643.asy b/spice/copy/sym/PowerProducts/LTM4643.asy new file mode 100755 index 0000000..3b46713 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4643.asy @@ -0,0 +1,143 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -576 -592 560 592 +TEXT -16 0 Center 2 LT +WINDOW 0 -16 -192 Center 2 +WINDOW 3 -16 192 Center 2 +SYMATTR Value LTM4643 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4643.sub +SYMATTR Value2 LTM4643 +SYMATTR Description Ultrathin Quad µModule Regulator with Configurable 3A Output Array +PIN 48 592 BOTTOM 8 +PINATTR PinName IntVcc1 +PINATTR SpiceOrder 1 +PIN -576 -528 LEFT 8 +PINATTR PinName SVin1 +PINATTR SpiceOrder 2 +PIN -400 592 BOTTOM 8 +PINATTR PinName Mode1 +PINATTR SpiceOrder 3 +PIN 560 -432 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN 560 -336 RIGHT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 5 +PIN -400 -592 TOP 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 6 +PIN -576 -336 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 7 +PIN 48 -592 TOP 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 8 +PIN 560 -528 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 9 +PIN 496 592 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -512 -592 TOP 8 +PINATTR PinName CLKIn +PINATTR SpiceOrder 11 +PIN -512 592 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 12 +PIN -576 -432 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 13 +PIN -576 -240 LEFT 8 +PINATTR PinName SVin2 +PINATTR SpiceOrder 14 +PIN -576 -144 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 15 +PIN -576 48 LEFT 8 +PINATTR PinName SVin3 +PINATTR SpiceOrder 16 +PIN -576 144 LEFT 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 17 +PIN 160 592 BOTTOM 8 +PINATTR PinName IntVcc2 +PINATTR SpiceOrder 18 +PIN -576 -48 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 19 +PIN 560 -144 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 20 +PIN 272 592 BOTTOM 8 +PINATTR PinName IntVcc3 +PINATTR SpiceOrder 21 +PIN 560 -48 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 22 +PIN 160 -592 TOP 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 23 +PIN -288 -592 TOP 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 24 +PIN 560 -240 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 25 +PIN -576 240 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 26 +PIN -288 592 BOTTOM 8 +PINATTR PinName Mode2 +PINATTR SpiceOrder 27 +PIN 560 144 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 28 +PIN 560 240 RIGHT 8 +PINATTR PinName Track/SS3 +PINATTR SpiceOrder 29 +PIN 272 -592 TOP 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 30 +PIN -176 -592 TOP 8 +PINATTR PinName Comp3 +PINATTR SpiceOrder 31 +PIN 560 48 RIGHT 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 32 +PIN -176 592 BOTTOM 8 +PINATTR PinName Mode3 +PINATTR SpiceOrder 33 +PIN -576 336 LEFT 8 +PINATTR PinName SVin4 +PINATTR SpiceOrder 34 +PIN -576 432 LEFT 8 +PINATTR PinName Vin4 +PINATTR SpiceOrder 35 +PIN 384 592 BOTTOM 8 +PINATTR PinName IntVcc4 +PINATTR SpiceOrder 36 +PIN -576 528 LEFT 8 +PINATTR PinName Run4 +PINATTR SpiceOrder 37 +PIN 560 432 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 38 +PIN 560 528 RIGHT 8 +PINATTR PinName Track/SS4 +PINATTR SpiceOrder 39 +PIN 384 -592 TOP 8 +PINATTR PinName Pgood4 +PINATTR SpiceOrder 40 +PIN -64 -592 TOP 8 +PINATTR PinName Comp4 +PINATTR SpiceOrder 41 +PIN 560 336 RIGHT 8 +PINATTR PinName Vout4 +PINATTR SpiceOrder 42 +PIN -64 592 BOTTOM 8 +PINATTR PinName Mode4 +PINATTR SpiceOrder 43 +PIN 496 -592 TOP 8 +PINATTR PinName CLKOut +PINATTR SpiceOrder 44 diff --git a/spice/copy/sym/PowerProducts/LTM4644-1.asy b/spice/copy/sym/PowerProducts/LTM4644-1.asy new file mode 100755 index 0000000..8b6375a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4644-1.asy @@ -0,0 +1,143 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -496 -592 496 592 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 191 Center 2 +SYMATTR Value LTM4644-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4644-1.sub +SYMATTR Value2 LTM4644-1 +SYMATTR Description Quad DC/DC µModule Regulator with Configurable 4A Output Array +PIN 48 592 BOTTOM 8 +PINATTR PinName IntVcc1 +PINATTR SpiceOrder 1 +PIN -496 -528 LEFT 8 +PINATTR PinName SVin1 +PINATTR SpiceOrder 2 +PIN -336 592 BOTTOM 8 +PINATTR PinName Mode1 +PINATTR SpiceOrder 3 +PIN 496 -432 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN 496 -336 RIGHT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 5 +PIN -336 -592 TOP 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 6 +PIN -496 -336 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 7 +PIN 48 -592 TOP 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 8 +PIN 496 -528 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 9 +PIN 432 592 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -432 -592 TOP 8 +PINATTR PinName CLKIn +PINATTR SpiceOrder 11 +PIN -432 592 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 12 +PIN -496 -432 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 13 +PIN -496 -240 LEFT 8 +PINATTR PinName SVin2 +PINATTR SpiceOrder 14 +PIN -496 -144 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 15 +PIN -496 48 LEFT 8 +PINATTR PinName SVin3 +PINATTR SpiceOrder 16 +PIN -496 144 LEFT 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 17 +PIN 144 592 BOTTOM 8 +PINATTR PinName IntVcc2 +PINATTR SpiceOrder 18 +PIN -496 -48 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 19 +PIN 496 -144 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 20 +PIN 240 592 BOTTOM 8 +PINATTR PinName IntVcc3 +PINATTR SpiceOrder 21 +PIN 496 -48 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 22 +PIN 144 -592 TOP 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 23 +PIN -240 -592 TOP 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 24 +PIN 496 -240 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 25 +PIN -496 240 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 26 +PIN -240 592 BOTTOM 8 +PINATTR PinName Mode2 +PINATTR SpiceOrder 27 +PIN 496 144 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 28 +PIN 496 240 RIGHT 8 +PINATTR PinName Track/SS3 +PINATTR SpiceOrder 29 +PIN 240 -592 TOP 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 30 +PIN -144 -592 TOP 8 +PINATTR PinName Comp3 +PINATTR SpiceOrder 31 +PIN 496 48 RIGHT 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 32 +PIN -144 592 BOTTOM 8 +PINATTR PinName Mode3 +PINATTR SpiceOrder 33 +PIN -496 336 LEFT 8 +PINATTR PinName SVin4 +PINATTR SpiceOrder 34 +PIN -496 432 LEFT 8 +PINATTR PinName Vin4 +PINATTR SpiceOrder 35 +PIN 336 592 BOTTOM 8 +PINATTR PinName IntVcc4 +PINATTR SpiceOrder 36 +PIN -496 528 LEFT 8 +PINATTR PinName Run4 +PINATTR SpiceOrder 37 +PIN 496 432 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 38 +PIN 496 528 RIGHT 8 +PINATTR PinName Track/SS4 +PINATTR SpiceOrder 39 +PIN 336 -592 TOP 8 +PINATTR PinName Pgood4 +PINATTR SpiceOrder 40 +PIN -48 -592 TOP 8 +PINATTR PinName Comp4 +PINATTR SpiceOrder 41 +PIN 496 336 RIGHT 8 +PINATTR PinName Vout4 +PINATTR SpiceOrder 42 +PIN -48 592 BOTTOM 8 +PINATTR PinName Mode4 +PINATTR SpiceOrder 43 +PIN 432 -592 TOP 8 +PINATTR PinName CLKOut +PINATTR SpiceOrder 44 diff --git a/spice/copy/sym/PowerProducts/LTM4644.asy b/spice/copy/sym/PowerProducts/LTM4644.asy new file mode 100755 index 0000000..c75084d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4644.asy @@ -0,0 +1,143 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -496 -592 496 592 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTM4644 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4644.sub +SYMATTR Value2 LTM4644 +SYMATTR Description Quad DC/DC µModule Regulator with Configurable 4A Output Array +PIN 48 592 BOTTOM 8 +PINATTR PinName IntVcc1 +PINATTR SpiceOrder 1 +PIN -496 -528 LEFT 8 +PINATTR PinName SVin1 +PINATTR SpiceOrder 2 +PIN -336 592 BOTTOM 8 +PINATTR PinName Mode1 +PINATTR SpiceOrder 3 +PIN 496 -432 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN 496 -336 RIGHT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 5 +PIN -336 -592 TOP 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 6 +PIN -496 -336 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 7 +PIN 48 -592 TOP 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 8 +PIN 496 -528 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 9 +PIN 432 592 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -432 -592 TOP 8 +PINATTR PinName CLKIn +PINATTR SpiceOrder 11 +PIN -432 592 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 12 +PIN -496 -432 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 13 +PIN -496 -240 LEFT 8 +PINATTR PinName SVin2 +PINATTR SpiceOrder 14 +PIN -496 -144 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 15 +PIN -496 48 LEFT 8 +PINATTR PinName SVin3 +PINATTR SpiceOrder 16 +PIN -496 144 LEFT 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 17 +PIN 144 592 BOTTOM 8 +PINATTR PinName IntVcc2 +PINATTR SpiceOrder 18 +PIN -496 -48 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 19 +PIN 496 -144 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 20 +PIN 240 592 BOTTOM 8 +PINATTR PinName IntVcc3 +PINATTR SpiceOrder 21 +PIN 496 -48 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 22 +PIN 144 -592 TOP 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 23 +PIN -240 -592 TOP 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 24 +PIN 496 -240 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 25 +PIN -496 240 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 26 +PIN -240 592 BOTTOM 8 +PINATTR PinName Mode2 +PINATTR SpiceOrder 27 +PIN 496 144 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 28 +PIN 496 240 RIGHT 8 +PINATTR PinName Track/SS3 +PINATTR SpiceOrder 29 +PIN 240 -592 TOP 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 30 +PIN -144 -592 TOP 8 +PINATTR PinName Comp3 +PINATTR SpiceOrder 31 +PIN 496 48 RIGHT 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 32 +PIN -144 592 BOTTOM 8 +PINATTR PinName Mode3 +PINATTR SpiceOrder 33 +PIN -496 336 LEFT 8 +PINATTR PinName SVin4 +PINATTR SpiceOrder 34 +PIN -496 432 LEFT 8 +PINATTR PinName Vin4 +PINATTR SpiceOrder 35 +PIN 336 592 BOTTOM 8 +PINATTR PinName IntVcc4 +PINATTR SpiceOrder 36 +PIN -496 528 LEFT 8 +PINATTR PinName Run4 +PINATTR SpiceOrder 37 +PIN 496 432 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 38 +PIN 496 528 RIGHT 8 +PINATTR PinName Track/SS4 +PINATTR SpiceOrder 39 +PIN 336 -592 TOP 8 +PINATTR PinName Pgood4 +PINATTR SpiceOrder 40 +PIN -48 -592 TOP 8 +PINATTR PinName Comp4 +PINATTR SpiceOrder 41 +PIN 496 336 RIGHT 8 +PINATTR PinName Vout4 +PINATTR SpiceOrder 42 +PIN -48 592 BOTTOM 8 +PINATTR PinName Mode4 +PINATTR SpiceOrder 43 +PIN 432 -592 TOP 8 +PINATTR PinName CLKOut +PINATTR SpiceOrder 44 diff --git a/spice/copy/sym/PowerProducts/LTM4645.asy b/spice/copy/sym/PowerProducts/LTM4645.asy new file mode 100755 index 0000000..c90101e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4645.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 272 -352 -304 352 +TEXT 1 1 Center 2 LT +WINDOW 0 -3 -145 Center 2 +WINDOW 3 0 141 Center 2 +SYMATTR Value LTM4645 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4645.sub +SYMATTR Value2 LTM4645 +SYMATTR Description 25A DC/DC Step-Down µModule Regulator +PIN -208 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -80 -352 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 2 +PIN 272 288 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 3 +PIN 272 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -304 288 LEFT 8 +PINATTR PinName TK/SS +PINATTR SpiceOrder 5 +PIN 48 -352 TOP 8 +PINATTR PinName HiZB +PINATTR SpiceOrder 6 +PIN 272 96 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 7 +PIN 272 192 RIGHT 8 +PINATTR PinName VFB +PINATTR SpiceOrder 8 +PIN -304 0 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 9 +PIN -80 352 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 10 +PIN -304 192 LEFT 8 +PINATTR PinName CompA +PINATTR SpiceOrder 11 +PIN -304 96 LEFT 8 +PINATTR PinName CompB +PINATTR SpiceOrder 12 +PIN -208 352 BOTTOM 8 +PINATTR PinName PGood +PINATTR SpiceOrder 14 +PIN 272 -192 RIGHT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 15 +PIN 272 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 16 +PIN 272 -288 RIGHT 8 +PINATTR PinName DrVcc +PINATTR SpiceOrder 17 +PIN 48 352 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 21 +PIN -304 -96 LEFT 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 30 +PIN -304 -288 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 31 +PIN -304 -192 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 32 +PIN 176 352 BOTTOM 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 33 +PIN 176 -352 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 34 diff --git a/spice/copy/sym/PowerProducts/LTM4646.asy b/spice/copy/sym/PowerProducts/LTM4646.asy new file mode 100755 index 0000000..f2e9b4c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4646.asy @@ -0,0 +1,107 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -448 -448 448 448 +TEXT 0 1 Center 2 LT +WINDOW 0 1 -238 Center 2 +WINDOW 3 11 245 Center 2 +SYMATTR Value LTM4646 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4646.sub +SYMATTR Value2 LTM4646 +SYMATTR Description Dual 10A or Single 20A µModule Regulator +PIN 448 384 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 1 +PIN 448 192 RIGHT 8 +PINATTR PinName Comp2A +PINATTR SpiceOrder 2 +PIN 448 96 RIGHT 8 +PINATTR PinName Vfb2 +PINATTR SpiceOrder 3 +PIN 112 448 BOTTOM 8 +PINATTR PinName PhasMD +PINATTR SpiceOrder 4 +PIN -224 448 BOTTOM 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 5 +PIN 336 448 BOTTOM 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 6 +PIN 0 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 7 +PIN -112 448 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 8 +PIN -336 448 BOTTOM 8 +PINATTR PinName Vrng +PINATTR SpiceOrder 9 +PIN -448 192 LEFT 8 +PINATTR PinName Comp1A +PINATTR SpiceOrder 10 +PIN -448 384 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 11 +PIN -448 96 LEFT 8 +PINATTR PinName Vfb1 +PINATTR SpiceOrder 12 +PIN -448 0 LEFT 8 +PINATTR PinName VoutS1- +PINATTR SpiceOrder 13 +PIN -448 -192 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 15 +PIN -112 -448 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 17 +PIN -224 -448 TOP 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 18 +PIN -448 -288 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 21 +PIN -336 -448 TOP 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 23 +PIN 0 -448 TOP 8 +PINATTR PinName Cpwr +PINATTR SpiceOrder 24 +PIN 112 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 26 +PIN 224 448 BOTTOM 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 27 +PIN 448 -288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 30 +PIN 224 -448 TOP 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 33 +PIN 336 -448 TOP 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 34 +PIN 448 -192 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 36 +PIN 448 0 RIGHT 8 +PINATTR PinName VoutS2- +PINATTR SpiceOrder 38 +PIN -448 288 LEFT 8 +PINATTR PinName Comp1B +PINATTR SpiceOrder 40 +PIN 448 288 RIGHT 8 +PINATTR PinName Comp2B +PINATTR SpiceOrder 41 +PIN -448 -384 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 42 +PIN 448 -384 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 43 +PIN -448 -96 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 44 +PIN 448 -96 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 45 diff --git a/spice/copy/sym/PowerProducts/LTM4647.asy b/spice/copy/sym/PowerProducts/LTM4647.asy new file mode 100755 index 0000000..9a36341 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4647.asy @@ -0,0 +1,77 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 272 -352 -304 352 +TEXT 1 1 Center 2 LT +WINDOW 0 -3 -145 Center 2 +WINDOW 3 0 141 Center 2 +SYMATTR Value LTM4647 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4647.sub +SYMATTR Value2 LTM4647 +SYMATTR Description 30A DC/DC Step-Down µModule Regulator +PIN -208 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -80 -352 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 2 +PIN 272 288 RIGHT 8 +PINATTR PinName Vosns- +PINATTR SpiceOrder 3 +PIN 272 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -304 288 LEFT 8 +PINATTR PinName TK/SS +PINATTR SpiceOrder 5 +PIN 48 -352 TOP 8 +PINATTR PinName HiZB +PINATTR SpiceOrder 6 +PIN 272 96 RIGHT 8 +PINATTR PinName Vosns+ +PINATTR SpiceOrder 7 +PIN 272 192 RIGHT 8 +PINATTR PinName VFB +PINATTR SpiceOrder 8 +PIN -304 0 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 9 +PIN -80 352 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 10 +PIN -304 192 LEFT 8 +PINATTR PinName CompA +PINATTR SpiceOrder 11 +PIN -304 96 LEFT 8 +PINATTR PinName CompB +PINATTR SpiceOrder 12 +PIN -208 352 BOTTOM 8 +PINATTR PinName PGood +PINATTR SpiceOrder 14 +PIN 272 -192 RIGHT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 15 +PIN 272 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 16 +PIN 272 -288 RIGHT 8 +PINATTR PinName DrVcc +PINATTR SpiceOrder 17 +PIN 48 352 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 21 +PIN -304 -96 LEFT 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 30 +PIN -304 -288 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 31 +PIN -304 -192 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 32 +PIN 176 352 BOTTOM 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 33 +PIN 176 -352 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 34 diff --git a/spice/copy/sym/PowerProducts/LTM4648.asy b/spice/copy/sym/PowerProducts/LTM4648.asy new file mode 100755 index 0000000..47e2a7b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4648.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -400 192 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LTM4648 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4648.sub +SYMATTR Value2 LTM4648 +SYMATTR Description Low Vin, 10A Step-Down µModule Regulator +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 1 +PIN 192 336 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 2 +PIN 192 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 192 -240 RIGHT 8 +PINATTR PinName Vout_lcl +PINATTR SpiceOrder 9 +PIN 192 -48 RIGHT 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 192 48 RIGHT 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 -144 RIGHT 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 192 -336 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 14 +PIN -192 144 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 16 +PIN 0 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -192 -144 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 20 +PIN -192 48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 25 +PIN -192 -336 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN 192 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 31 +PIN 64 -400 TOP 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 32 +PIN -192 -48 LEFT 8 +PINATTR PinName PHmode +PINATTR SpiceOrder 33 +PIN -64 -400 TOP 8 +PINATTR PinName CLKin +PINATTR SpiceOrder 34 +PIN -192 336 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 35 +PIN -192 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4649.asy b/spice/copy/sym/PowerProducts/LTM4649.asy new file mode 100755 index 0000000..5fed90d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4649.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -192 -400 192 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LTM4649 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4649.sub +SYMATTR Value2 LTM4649 +SYMATTR Description 10A Step-Down DC/DC µModule Regulator +PIN -192 240 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 1 +PIN 192 336 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 2 +PIN 192 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 3 +PIN 192 -240 RIGHT 8 +PINATTR PinName Vout_lcl +PINATTR SpiceOrder 9 +PIN 192 -48 RIGHT 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 192 48 RIGHT 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 -144 RIGHT 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 192 -336 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 14 +PIN -192 144 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 16 +PIN 0 400 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -192 -144 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 20 +PIN -192 48 LEFT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 25 +PIN -192 -336 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN 192 144 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 31 +PIN 64 -400 TOP 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 32 +PIN -192 -48 LEFT 8 +PINATTR PinName PHmode +PINATTR SpiceOrder 33 +PIN -64 -400 TOP 8 +PINATTR PinName CLKin +PINATTR SpiceOrder 34 +PIN -192 336 LEFT 8 +PINATTR PinName FREQ +PINATTR SpiceOrder 35 +PIN -192 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4650-1.asy b/spice/copy/sym/PowerProducts/LTM4650-1.asy new file mode 100755 index 0000000..07483d0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4650-1.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4650-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4650-1.sub +SYMATTR Value2 LTM4650-1 +SYMATTR Description Dual 25A or Single 50A µModule Regulator with 3% Transient Accuracy +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4650.asy b/spice/copy/sym/PowerProducts/LTM4650.asy new file mode 100755 index 0000000..93bc415 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4650.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4650 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4650.sub +SYMATTR Value2 LTM4650 +SYMATTR Description Dual 25A or Single 50A DC/DC µModule Regulator +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4650A-1.asy b/spice/copy/sym/PowerProducts/LTM4650A-1.asy new file mode 100755 index 0000000..55333dd --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4650A-1.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4650A-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4650A-1.sub +SYMATTR Value2 LTM4650A-1 +SYMATTR Description Dual 25A or Single 50A DC/DC µModule Regulator with 1% DC Accuracy +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4650A.asy b/spice/copy/sym/PowerProducts/LTM4650A.asy new file mode 100755 index 0000000..f2669e6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4650A.asy @@ -0,0 +1,95 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -448 288 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM4650A +SYMATTR Prefix X +SYMATTR SpiceModel LTM4650A.sub +SYMATTR Value2 LTM4650A +SYMATTR Description Dual 25A or Single 50A DC/DC µModule Regulator with 1% DC Accuracy +PIN -288 288 LEFT 8 +PINATTR PinName TK/SS1 +PINATTR SpiceOrder 1 +PIN -288 192 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 2 +PIN -288 96 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 3 +PIN -192 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 4 +PIN 288 96 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN 288 192 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 6 +PIN 288 288 RIGHT 8 +PINATTR PinName TK/SS2 +PINATTR SpiceOrder 7 +PIN 288 -96 RIGHT 8 +PINATTR PinName VOUT2 +PINATTR SpiceOrder 8 +PIN -288 0 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 9 +PIN 96 448 BOTTOM 8 +PINATTR PinName Diffp +PINATTR SpiceOrder 10 +PIN 0 448 BOTTOM 8 +PINATTR PinName Diffn +PINATTR SpiceOrder 11 +PIN 192 448 BOTTOM 8 +PINATTR PinName Diffout +PINATTR SpiceOrder 12 +PIN 288 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 13 +PIN -288 -96 LEFT 8 +PINATTR PinName VOUT1 +PINATTR SpiceOrder 14 +PIN 288 0 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 15 +PIN -288 -288 LEFT 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 16 +PIN 288 -288 RIGHT 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 17 +PIN -96 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 288 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 19 +PIN 96 -448 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 24 +PIN 0 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 25 +PIN -96 -448 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 26 +PIN -288 -192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 31 +PIN 288 384 RIGHT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 32 +PIN 192 -448 TOP 8 +PINATTR PinName PhaseMD +PINATTR SpiceOrder 33 +PIN -288 384 LEFT 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName Fset +PINATTR SpiceOrder 35 +PIN -288 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4651.asy b/spice/copy/sym/PowerProducts/LTM4651.asy new file mode 100755 index 0000000..7db4257 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4651.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 352 -240 -352 +TEXT 0 0 Center 2 LT +WINDOW 3 -2 154 Center 2 +WINDOW 0 1 -150 Center 2 +SYMATTR Value LTM4651 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4651.sub +SYMATTR Value2 LTM4651 +SYMATTR Description EN55022B Compliant 58V, 24W Inverting-Output DC/DC µModule Regulator +PIN 224 96 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 1 +PIN 224 -192 RIGHT 8 +PINATTR PinName PGND +PINATTR SpiceOrder 2 +PIN -64 -352 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -240 288 LEFT 8 +PINATTR PinName Compb +PINATTR SpiceOrder 4 +PIN -240 -192 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -128 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -240 96 LEFT 8 +PINATTR PinName CLKin +PINATTR SpiceOrder 7 +PIN -240 -96 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN 224 288 RIGHT 8 +PINATTR PinName PGDFB +PINATTR SpiceOrder 9 +PIN 224 192 RIGHT 8 +PINATTR PinName SVout- +PINATTR SpiceOrder 10 +PIN -240 -288 LEFT 8 +PINATTR PinName VinREG +PINATTR SpiceOrder 11 +PIN -240 0 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 12 +PIN 224 -288 RIGHT 8 +PINATTR PinName GNDsns +PINATTR SpiceOrder 13 +PIN 0 352 BOTTOM 8 +PINATTR PinName Iseta +PINATTR SpiceOrder 14 +PIN -240 192 LEFT 8 +PINATTR PinName Compa +PINATTR SpiceOrder 15 +PIN 160 -352 TOP 8 +PINATTR PinName EXTVcc +PINATTR SpiceOrder 16 +PIN 48 -352 TOP 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 17 +PIN -160 -352 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 18 +PIN 224 -96 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 19 +PIN 128 352 BOTTOM 8 +PINATTR PinName Isetb +PINATTR SpiceOrder 20 +PIN 224 0 RIGHT 8 +PINATTR PinName VD +PINATTR SpiceOrder 21 diff --git a/spice/copy/sym/PowerProducts/LTM4653.asy b/spice/copy/sym/PowerProducts/LTM4653.asy new file mode 100755 index 0000000..c56b0e7 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4653.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 496 -224 -576 +TEXT 0 0 Center 2 LT +WINDOW 3 0 192 Center 2 +WINDOW 0 0 -192 Center 2 +SYMATTR Value LTM4653 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4653.sub +SYMATTR Value2 LTM4653 +SYMATTR Description EN55022B Compliant 58V, 4A Step-Down DC/DC µModule Regulator +PIN 128 496 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 1 +PIN 224 -528 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -224 -336 LEFT 8 +PINATTR PinName Vd +PINATTR SpiceOrder 3 +PIN -224 -528 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -224 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -128 496 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 6 +PIN -224 144 LEFT 8 +PINATTR PinName Clkin +PINATTR SpiceOrder 7 +PIN 224 -240 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN 224 -144 RIGHT 8 +PINATTR PinName PGDFB +PINATTR SpiceOrder 9 +PIN 224 -48 RIGHT 8 +PINATTR PinName IMONa +PINATTR SpiceOrder 10 +PIN -224 -48 LEFT 8 +PINATTR PinName VinReg +PINATTR SpiceOrder 11 +PIN -224 240 LEFT 8 +PINATTR PinName Fset +PINATTR SpiceOrder 12 +PIN 224 -432 RIGHT 8 +PINATTR PinName Vosns +PINATTR SpiceOrder 13 +PIN 224 240 RIGHT 8 +PINATTR PinName ISETa +PINATTR SpiceOrder 14 +PIN -224 336 LEFT 8 +PINATTR PinName COMPa +PINATTR SpiceOrder 15 +PIN -224 48 LEFT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 16 +PIN -224 -144 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 17 +PIN -224 432 LEFT 8 +PINATTR PinName COMPb +PINATTR SpiceOrder 18 +PIN 224 -336 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 19 +PIN 224 144 RIGHT 8 +PINATTR PinName ISETb +PINATTR SpiceOrder 20 +PIN 224 48 RIGHT 8 +PINATTR PinName IMONb +PINATTR SpiceOrder 21 +PIN 224 336 RIGHT 8 +PINATTR PinName TEMP+ +PINATTR SpiceOrder 22 +PIN 224 432 RIGHT 8 +PINATTR PinName TEMP- +PINATTR SpiceOrder 23 +PIN -224 -432 LEFT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 24 +PIN 0 496 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 diff --git a/spice/copy/sym/PowerProducts/LTM4655.asy b/spice/copy/sym/PowerProducts/LTM4655.asy new file mode 100755 index 0000000..4c18f4a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4655.asy @@ -0,0 +1,170 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 960 560 -944 -560 +TEXT 0 0 Center 2 LT +WINDOW 3 13 293 Center 2 +WINDOW 0 12 -288 Center 2 +SYMATTR Value LTM4655 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4655.sub +SYMATTR Value2 LTM4655 +SYMATTR Description 60V EMI Compliant Split-Supply DC/DC Regulator +PIN 960 -96 RIGHT 8 +PINATTR PinName Vout1- +PINATTR SpiceOrder 1 +PIN -944 -288 LEFT 8 +PINATTR PinName SVINF1 +PINATTR SpiceOrder 2 +PIN -944 -384 LEFT 8 +PINATTR PinName VD1 +PINATTR SpiceOrder 3 +PIN -944 -192 LEFT 8 +PINATTR PinName SVIN1 +PINATTR SpiceOrder 4 +PIN -944 -96 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 5 +PIN 960 480 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -272 -560 TOP 8 +PINATTR PinName Clkin1 +PINATTR SpiceOrder 7 +PIN -496 -560 TOP 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 8 +PIN 624 -560 TOP 8 +PINATTR PinName PGDFB1 +PINATTR SpiceOrder 9 +PIN 848 -560 TOP 8 +PINATTR PinName Imon1a +PINATTR SpiceOrder 10 +PIN -832 -560 TOP 8 +PINATTR PinName Vinreg1 +PINATTR SpiceOrder 11 +PIN -384 -560 TOP 8 +PINATTR PinName Freq1 +PINATTR SpiceOrder 12 +PIN 960 -288 RIGHT 8 +PINATTR PinName Vosns1+ +PINATTR SpiceOrder 13 +PIN 400 -560 TOP 8 +PINATTR PinName Iset1a +PINATTR SpiceOrder 14 +PIN 176 -560 TOP 8 +PINATTR PinName Ith1a +PINATTR SpiceOrder 15 +PIN -608 -560 TOP 8 +PINATTR PinName Extvcc1 +PINATTR SpiceOrder 16 +PIN -720 -560 TOP 8 +PINATTR PinName Intvcc1 +PINATTR SpiceOrder 17 +PIN -944 -480 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 18 +PIN 960 -480 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 19 +PIN 512 -560 TOP 8 +PINATTR PinName Iset1b +PINATTR SpiceOrder 20 +PIN 288 -560 TOP 8 +PINATTR PinName Ith1b +PINATTR SpiceOrder 21 +PIN 960 -384 RIGHT 8 +PINATTR PinName Vout1+ +PINATTR SpiceOrder 22 +PIN 960 -192 RIGHT 8 +PINATTR PinName SVout1- +PINATTR SpiceOrder 23 +PIN 736 -560 TOP 8 +PINATTR PinName Imon1b +PINATTR SpiceOrder 24 +PIN -48 -560 TOP 8 +PINATTR PinName +5V +PINATTR SpiceOrder 25 +PIN 64 -560 TOP 8 +PINATTR PinName Clkset +PINATTR SpiceOrder 26 +PIN -944 288 LEFT 8 +PINATTR PinName VD2 +PINATTR SpiceOrder 27 +PIN -272 560 BOTTOM 8 +PINATTR PinName Clkin2 +PINATTR SpiceOrder 28 +PIN -944 0 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 30 +PIN -720 560 BOTTOM 8 +PINATTR PinName Intvcc2 +PINATTR SpiceOrder 31 +PIN 960 384 RIGHT 8 +PINATTR PinName Vout2- +PINATTR SpiceOrder 32 +PIN 960 0 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 33 +PIN 960 192 RIGHT 8 +PINATTR PinName Vosns2+ +PINATTR SpiceOrder 34 +PIN -496 560 BOTTOM 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 35 +PIN -608 560 BOTTOM 8 +PINATTR PinName Extvcc2 +PINATTR SpiceOrder 36 +PIN -384 560 BOTTOM 8 +PINATTR PinName Freq2 +PINATTR SpiceOrder 37 +PIN 400 560 BOTTOM 8 +PINATTR PinName Iset2a +PINATTR SpiceOrder 38 +PIN 160 560 BOTTOM 8 +PINATTR PinName Ith2a +PINATTR SpiceOrder 39 +PIN 736 560 BOTTOM 8 +PINATTR PinName Imon2a +PINATTR SpiceOrder 40 +PIN -832 560 BOTTOM 8 +PINATTR PinName Vinreg2 +PINATTR SpiceOrder 41 +PIN 624 560 BOTTOM 8 +PINATTR PinName PGDFB2 +PINATTR SpiceOrder 42 +PIN -944 192 LEFT 8 +PINATTR PinName SVINF2 +PINATTR SpiceOrder 43 +PIN -944 96 LEFT 8 +PINATTR PinName SVIN2 +PINATTR SpiceOrder 44 +PIN -944 384 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 45 +PIN 512 560 BOTTOM 8 +PINATTR PinName Iset2b +PINATTR SpiceOrder 46 +PIN 288 560 BOTTOM 8 +PINATTR PinName Ith2b +PINATTR SpiceOrder 47 +PIN 960 96 RIGHT 8 +PINATTR PinName Vout2+ +PINATTR SpiceOrder 48 +PIN 960 288 RIGHT 8 +PINATTR PinName SVout2- +PINATTR SpiceOrder 49 +PIN 848 560 BOTTOM 8 +PINATTR PinName Imon2b +PINATTR SpiceOrder 50 +PIN -160 -560 TOP 8 +PINATTR PinName Clkout1 +PINATTR SpiceOrder 51 +PIN -128 560 BOTTOM 8 +PINATTR PinName Clkout2 +PINATTR SpiceOrder 52 +PIN 16 560 BOTTOM 8 +PINATTR PinName Mod +PINATTR SpiceOrder 53 +PIN -944 480 LEFT 8 +PINATTR PinName LDO_IN +PINATTR SpiceOrder 54 diff --git a/spice/copy/sym/PowerProducts/LTM4656.asy b/spice/copy/sym/PowerProducts/LTM4656.asy new file mode 100755 index 0000000..fbe8038 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4656.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -191 -432 192 433 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTM4656 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4656.sub +SYMATTR Value2 LTM4656 +SYMATTR Description Synchronous Boost uModule Regulator with Short Protection +PIN 192 192 RIGHT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN -192 0 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 14 +PIN 192 368 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 13 +PIN -192 368 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -192 -96 LEFT 8 +PINATTR PinName FLT +PINATTR SpiceOrder 4 +PIN -192 288 LEFT 8 +PINATTR PinName Temp- +PINATTR SpiceOrder 17 +PIN 192 -384 RIGHT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -192 -384 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -192 -288 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 2 +PIN 192 0 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN 192 -192 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 7 +PIN 192 -288 RIGHT 8 +PINATTR PinName BVIN +PINATTR SpiceOrder 6 +PIN 192 -96 RIGHT 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 8 +PIN -192 -192 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 3 +PIN -192 96 LEFT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 15 +PIN -192 192 LEFT 8 +PINATTR PinName Temp+ +PINATTR SpiceOrder 16 +PIN 192 288 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 192 96 RIGHT 8 +PINATTR PinName PLLin/Mode +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTM4657.asy b/spice/copy/sym/PowerProducts/LTM4657.asy new file mode 100755 index 0000000..77cb91c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4657.asy @@ -0,0 +1,62 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 320 -176 -336 +TEXT 0 0 Center 2 LT +WINDOW 3 0 72 Center 2 +WINDOW 0 0 -88 Center 2 +SYMATTR Value LTM4657 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4657.sub +SYMATTR Value2 LTM4657 +SYMATTR Description 20Vin, 8A Step-Down DC/DC uModule Regulator +PIN 0 -336 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -176 -288 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 2 +PIN -176 -208 LEFT 8 +PINATTR PinName Track/SS +PINATTR SpiceOrder 3 +PIN -176 -128 LEFT 8 +PINATTR PinName Mode/CLKin +PINATTR SpiceOrder 4 +PIN -176 -48 LEFT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 5 +PIN -176 32 LEFT 8 +PINATTR PinName PhMode +PINATTR SpiceOrder 6 +PIN -176 112 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 7 +PIN 176 -240 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN 176 -160 RIGHT 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 9 +PIN 176 -80 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 10 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 11 +PIN 176 80 RIGHT 8 +PINATTR PinName VoutS+ +PINATTR SpiceOrder 12 +PIN 176 160 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 13 +PIN 176 240 RIGHT 8 +PINATTR PinName VoutS- +PINATTR SpiceOrder 14 +PIN -176 192 LEFT 8 +PINATTR PinName COMPa +PINATTR SpiceOrder 15 +PIN -176 272 LEFT 8 +PINATTR PinName COMPb +PINATTR SpiceOrder 16 +PIN 0 320 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTM4660.asy b/spice/copy/sym/PowerProducts/LTM4660.asy new file mode 100755 index 0000000..0bb1db4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4660.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -448 256 448 +TEXT 0 0 Center 2 LT +WINDOW 0 4 -242 Center 2 +WINDOW 3 5 240 Center 2 +SYMATTR Value LTM4660 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4660.sub +SYMATTR Value2 LTM4660 +SYMATTR Description 72V, 300W Hybrid Step-Down Non-Isolated µModule Bus Converter +PIN -256 -288 LEFT 8 +PINATTR PinName Mode_PLLin +PINATTR SpiceOrder 1 +PIN -256 288 LEFT 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 2 +PIN 128 -448 TOP 8 +PINATTR PinName Run +PINATTR SpiceOrder 3 +PIN -256 96 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 4 +PIN -256 0 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 5 +PIN -256 -384 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN -256 384 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN -256 192 LEFT 8 +PINATTR PinName ExtRef +PINATTR SpiceOrder 8 +PIN -256 -192 LEFT 8 +PINATTR PinName Hys_prgm +PINATTR SpiceOrder 9 +PIN 128 448 BOTTOM 8 +PINATTR PinName CompA +PINATTR SpiceOrder 10 +PIN -256 -96 LEFT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 11 +PIN 256 192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 12 +PIN 256 384 RIGHT 8 +PINATTR PinName Vfb +PINATTR SpiceOrder 13 +PIN -128 448 BOTTOM 8 +PINATTR PinName CompB +PINATTR SpiceOrder 14 +PIN 256 288 RIGHT 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 16 +PIN -128 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 19 +PIN 256 96 RIGHT 8 +PINATTR PinName C- +PINATTR SpiceOrder 20 +PIN 256 -96 RIGHT 8 +PINATTR PinName Mid +PINATTR SpiceOrder 25 +PIN 256 0 RIGHT 8 +PINATTR PinName Mid_sense +PINATTR SpiceOrder 26 +PIN 256 -288 RIGHT 8 +PINATTR PinName Vin_sense +PINATTR SpiceOrder 27 +PIN 256 -384 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 +PIN 256 -192 RIGHT 8 +PINATTR PinName C+ +PINATTR SpiceOrder 29 +PIN 0 448 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 33 diff --git a/spice/copy/sym/PowerProducts/LTM4661.asy b/spice/copy/sym/PowerProducts/LTM4661.asy new file mode 100755 index 0000000..03fe427 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4661.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 97 Center 2 +SYMATTR Value LTM4661 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4661.sub +SYMATTR Value2 LTM4661 +SYMATTR Description 15V, 4A Step-Up µModule Regulator +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -144 48 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 6 +PIN -144 144 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 10 +PIN -144 -48 LEFT 8 +PINATTR PinName _SD +PINATTR SpiceOrder 11 +PIN 0 208 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 12 +PIN 144 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTM4662.asy b/spice/copy/sym/PowerProducts/LTM4662.asy new file mode 100755 index 0000000..44a0b88 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4662.asy @@ -0,0 +1,107 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -448 -448 448 448 +TEXT 0 1 Center 2 LT +WINDOW 0 1 -238 Center 2 +WINDOW 3 11 245 Center 2 +SYMATTR Value LTM4662 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4662.sub +SYMATTR Value2 LTM4662 +SYMATTR Description High Efficiency Dual 12A module +PIN 448 384 RIGHT 8 +PINATTR PinName Track/SS2 +PINATTR SpiceOrder 1 +PIN 448 192 RIGHT 8 +PINATTR PinName Comp2A +PINATTR SpiceOrder 2 +PIN 112 448 BOTTOM 8 +PINATTR PinName PhasMD +PINATTR SpiceOrder 4 +PIN -224 448 BOTTOM 8 +PINATTR PinName Mode/PLLIN +PINATTR SpiceOrder 5 +PIN 336 448 BOTTOM 8 +PINATTR PinName Clkout +PINATTR SpiceOrder 6 +PIN 0 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 7 +PIN -112 448 BOTTOM 8 +PINATTR PinName Freq +PINATTR SpiceOrder 8 +PIN -336 448 BOTTOM 8 +PINATTR PinName Vrng +PINATTR SpiceOrder 9 +PIN -448 192 LEFT 8 +PINATTR PinName Comp1A +PINATTR SpiceOrder 10 +PIN -448 384 LEFT 8 +PINATTR PinName Track/SS1 +PINATTR SpiceOrder 11 +PIN -448 0 LEFT 8 +PINATTR PinName VoutS1- +PINATTR SpiceOrder 13 +PIN -448 96 LEFT 8 +PINATTR PinName Vfb1 +PINATTR SpiceOrder 12 +PIN -448 288 LEFT 8 +PINATTR PinName Comp1B +PINATTR SpiceOrder 40 +PIN -112 -448 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 17 +PIN -224 -448 TOP 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 18 +PIN -448 -288 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 21 +PIN -448 -384 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 42 +PIN -448 -192 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 15 +PIN -448 -96 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 44 +PIN -336 -448 TOP 8 +PINATTR PinName DRVcc +PINATTR SpiceOrder 23 +PIN 0 -448 TOP 8 +PINATTR PinName Cpwr +PINATTR SpiceOrder 24 +PIN 112 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 26 +PIN 224 448 BOTTOM 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 27 +PIN 448 -96 RIGHT 8 +PINATTR PinName VoutS2 +PINATTR SpiceOrder 45 +PIN 448 -192 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 36 +PIN 448 -384 RIGHT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 43 +PIN 448 -288 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 30 +PIN 224 -448 TOP 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 33 +PIN 336 -448 TOP 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 34 +PIN 448 288 RIGHT 8 +PINATTR PinName Comp2B +PINATTR SpiceOrder 41 +PIN 448 96 RIGHT 8 +PINATTR PinName Vfb2 +PINATTR SpiceOrder 3 +PIN 448 0 RIGHT 8 +PINATTR PinName VoutS2- +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/PowerProducts/LTM4663.asy b/spice/copy/sym/PowerProducts/LTM4663.asy new file mode 100755 index 0000000..af223ff Binary files /dev/null and b/spice/copy/sym/PowerProducts/LTM4663.asy differ diff --git a/spice/copy/sym/PowerProducts/LTM4664.asy b/spice/copy/sym/PowerProducts/LTM4664.asy new file mode 100755 index 0000000..357fc37 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4664.asy @@ -0,0 +1,204 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -1008 -688 1024 688 +TEXT 0 0 Center 2 LT +WINDOW 0 5 -334 Center 2 +WINDOW 3 3 338 Center 2 +SYMATTR Value LTM4664 +SYMATTR Prefix X +SYMATTR Description High Efficiency Dual Output Step-Down Converter with Power System Management +SYMATTR ModelFile LTM4664.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1 Vout_1=1 Ilim0_range=1 Ilim1_range=1 OC_limit0=1 OC_limit1=1 Mode_ll=2 Fault_response=0 Retry_delay=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K Sync=0 +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 1024 -48 RIGHT 8 +PINATTR PinName Vosns+_C0 +PINATTR SpiceOrder 1 +PIN 1024 48 RIGHT 8 +PINATTR PinName Vosns-_C0 +PINATTR SpiceOrder 2 +PIN 1024 -432 RIGHT 8 +PINATTR PinName PWM_C0 +PINATTR SpiceOrder 3 +PIN 1024 -336 RIGHT 8 +PINATTR PinName GL_C0 +PINATTR SpiceOrder 4 +PIN 1024 240 RIGHT 8 +PINATTR PinName Comp_C0a +PINATTR SpiceOrder 5 +PIN 1024 144 RIGHT 8 +PINATTR PinName Comp_C0b +PINATTR SpiceOrder 6 +PIN -1008 -432 LEFT 8 +PINATTR PinName PWM_C1 +PINATTR SpiceOrder 7 +PIN -1008 -336 LEFT 8 +PINATTR PinName GL_C1 +PINATTR SpiceOrder 8 +PIN 1024 -624 RIGHT 8 +PINATTR PinName VinS3_C0 +PINATTR SpiceOrder 9 +PIN -1008 -608 LEFT 8 +PINATTR PinName VinS3_C1 +PINATTR SpiceOrder 10 +PIN -1008 624 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 11 +PIN -384 688 BOTTOM 8 +PINATTR PinName FreqS1 +PINATTR SpiceOrder 12 +PIN -832 688 BOTTOM 8 +PINATTR PinName HysPrgmS1 +PINATTR SpiceOrder 13 +PIN -272 -688 TOP 8 +PINATTR PinName IntVccS1 +PINATTR SpiceOrder 14 +PIN -272 688 BOTTOM 8 +PINATTR PinName TimerS1 +PINATTR SpiceOrder 15 +PIN -496 688 BOTTOM 8 +PINATTR PinName _FaultS1 +PINATTR SpiceOrder 16 +PIN 1024 528 RIGHT 8 +PINATTR PinName Run_C0 +PINATTR SpiceOrder 17 +PIN -1008 528 LEFT 8 +PINATTR PinName Run_C1 +PINATTR SpiceOrder 18 +PIN -608 688 BOTTOM 8 +PINATTR PinName PgoodS1 +PINATTR SpiceOrder 19 +PIN 1024 432 RIGHT 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 20 +PIN 1024 336 RIGHT 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 21 +PIN -1008 336 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 22 +PIN -1008 432 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 23 +PIN 1024 624 RIGHT 8 +PINATTR PinName Fswph_cfg +PINATTR SpiceOrder 24 +PIN 848 688 BOTTOM 8 +PINATTR PinName Vdd25 +PINATTR SpiceOrder 25 +PIN -720 688 BOTTOM 8 +PINATTR PinName UVS1 +PINATTR SpiceOrder 26 +PIN -160 -688 TOP 8 +PINATTR PinName ExtVccS1 +PINATTR SpiceOrder 27 +PIN 736 688 BOTTOM 8 +PINATTR PinName Vdd33 +PINATTR SpiceOrder 28 +PIN -1008 144 LEFT 8 +PINATTR PinName Comp_C1b +PINATTR SpiceOrder 29 +PIN -1008 240 LEFT 8 +PINATTR PinName Comp_C1a +PINATTR SpiceOrder 30 +PIN -1008 48 LEFT 8 +PINATTR PinName Vosns-_C1 +PINATTR SpiceOrder 31 +PIN -1008 -48 LEFT 8 +PINATTR PinName Vosns+_C1 +PINATTR SpiceOrder 32 +PIN -1008 -528 LEFT 8 +PINATTR PinName PGood_C1 +PINATTR SpiceOrder 33 +PIN -1008 -240 LEFT 8 +PINATTR PinName SWC1 +PINATTR SpiceOrder 34 +PIN -944 688 BOTTOM 8 +PINATTR PinName RunS1 +PINATTR SpiceOrder 35 +PIN 400 688 BOTTOM 8 +PINATTR PinName FreqS2 +PINATTR SpiceOrder 36 +PIN -1008 -144 LEFT 8 +PINATTR PinName VoutC1 +PINATTR SpiceOrder 37 +PIN -48 -688 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 38 +PIN -48 688 BOTTOM 8 +PINATTR PinName HysPrgmS2 +PINATTR SpiceOrder 39 +PIN 624 688 BOTTOM 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 40 +PIN 960 688 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 41 +PIN 1024 -144 RIGHT 8 +PINATTR PinName VoutC0 +PINATTR SpiceOrder 42 +PIN 176 -688 TOP 8 +PINATTR PinName IntVccS2 +PINATTR SpiceOrder 43 +PIN 512 688 BOTTOM 8 +PINATTR PinName TimerS2 +PINATTR SpiceOrder 44 +PIN 1024 -240 RIGHT 8 +PINATTR PinName SWC0 +PINATTR SpiceOrder 45 +PIN 288 688 BOTTOM 8 +PINATTR PinName _FaultS2 +PINATTR SpiceOrder 46 +PIN 176 688 BOTTOM 8 +PINATTR PinName PgoodS2 +PINATTR SpiceOrder 47 +PIN 1024 -528 RIGHT 8 +PINATTR PinName PGood_C0 +PINATTR SpiceOrder 48 +PIN 64 688 BOTTOM 8 +PINATTR PinName UVS2 +PINATTR SpiceOrder 51 +PIN 64 -688 TOP 8 +PINATTR PinName ExtVccS2 +PINATTR SpiceOrder 52 +PIN -160 688 BOTTOM 8 +PINATTR PinName RunS2 +PINATTR SpiceOrder 53 +PIN -496 -688 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 54 +PIN -384 -688 TOP 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 55 +PIN -608 -688 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 56 +PIN -720 -688 TOP 8 +PINATTR PinName VinS1 +PINATTR SpiceOrder 57 +PIN -944 -688 TOP 8 +PINATTR PinName InSnsS1+ +PINATTR SpiceOrder 59 +PIN -832 -688 TOP 8 +PINATTR PinName InSnsS1- +PINATTR SpiceOrder 49 +PIN 848 -688 TOP 8 +PINATTR PinName SW4 +PINATTR SpiceOrder 60 +PIN 960 -688 TOP 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 61 +PIN 736 -688 TOP 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 62 +PIN 512 -688 TOP 8 +PINATTR PinName VinS2 +PINATTR SpiceOrder 63 +PIN 400 -688 TOP 8 +PINATTR PinName InSnsS2- +PINATTR SpiceOrder 64 +PIN 288 -688 TOP 8 +PINATTR PinName InSnsS2+ +PINATTR SpiceOrder 65 +PIN 624 -688 TOP 8 +PINATTR PinName VinS2F +PINATTR SpiceOrder 66 diff --git a/spice/copy/sym/PowerProducts/LTM4668.asy b/spice/copy/sym/PowerProducts/LTM4668.asy new file mode 100755 index 0000000..c4136d7 Binary files /dev/null and b/spice/copy/sym/PowerProducts/LTM4668.asy differ diff --git a/spice/copy/sym/PowerProducts/LTM4668A.asy b/spice/copy/sym/PowerProducts/LTM4668A.asy new file mode 100755 index 0000000..9b391dd Binary files /dev/null and b/spice/copy/sym/PowerProducts/LTM4668A.asy differ diff --git a/spice/copy/sym/PowerProducts/LTM4671.asy b/spice/copy/sym/PowerProducts/LTM4671.asy new file mode 100755 index 0000000..d6c19be --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4671.asy @@ -0,0 +1,152 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -512 -736 513 720 +TEXT 0 0 Center 2 LT +WINDOW 0 5 -385 Center 2 +WINDOW 3 0 368 Center 2 +SYMATTR Value LTM4671 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4671.sub +SYMATTR Value2 LTM4671 +SYMATTR Description Quad DC/DC µModule regulator with Configurable Dual 12A, Dual 5A Output Array +PIN -224 720 BOTTOM 8 +PINATTR PinName Pgood1 +PINATTR SpiceOrder 1 +PIN -512 272 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 3 +PIN 336 720 BOTTOM 8 +PINATTR PinName Mode12 +PINATTR SpiceOrder 4 +PIN -448 720 BOTTOM 8 +PINATTR PinName Freq12 +PINATTR SpiceOrder 5 +PIN 512 272 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 6 +PIN 224 720 BOTTOM 8 +PINATTR PinName Pgood2 +PINATTR SpiceOrder 8 +PIN 512 560 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN 112 720 BOTTOM 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 10 +PIN 512 656 RIGHT 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 11 +PIN 512 464 RIGHT 8 +PINATTR PinName Vosns2 +PINATTR SpiceOrder 17 +PIN 512 368 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 13 +PIN -336 720 BOTTOM 8 +PINATTR PinName IntVcc12 +PINATTR SpiceOrder 19 +PIN -512 368 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 23 +PIN -512 464 LEFT 8 +PINATTR PinName Vosns1 +PINATTR SpiceOrder 20 +PIN -512 656 LEFT 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 26 +PIN -112 720 BOTTOM 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 27 +PIN -512 560 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 28 +PIN 448 720 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -736 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 21 +PIN -512 -672 LEFT 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 18 +PIN 512 -672 RIGHT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 22 +PIN 512 -288 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 25 +PIN 512 96 RIGHT 8 +PINATTR PinName SS3 +PINATTR SpiceOrder 39 +PIN 512 -192 RIGHT 8 +PINATTR PinName Comp3a +PINATTR SpiceOrder 41 +PIN 512 -480 RIGHT 8 +PINATTR PinName Vosns3+ +PINATTR SpiceOrder 47 +PIN 512 -576 RIGHT 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 48 +PIN -512 -576 LEFT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 12 +PIN -512 -480 LEFT 8 +PINATTR PinName Vosns0+ +PINATTR SpiceOrder 2 +PIN -512 -192 LEFT 8 +PINATTR PinName Comp0a +PINATTR SpiceOrder 33 +PIN -512 96 LEFT 8 +PINATTR PinName SS0 +PINATTR SpiceOrder 31 +PIN -512 -288 LEFT 8 +PINATTR PinName FB0 +PINATTR SpiceOrder 24 +PIN -512 0 LEFT 8 +PINATTR PinName Clkout0 +PINATTR SpiceOrder 36 +PIN -512 176 LEFT 8 +PINATTR PinName Freq0 +PINATTR SpiceOrder 34 +PIN 112 -736 TOP 8 +PINATTR PinName Intvcc3 +PINATTR SpiceOrder 15 +PIN 512 -384 RIGHT 8 +PINATTR PinName Vosns3- +PINATTR SpiceOrder 46 +PIN -512 -384 LEFT 8 +PINATTR PinName Vosns0- +PINATTR SpiceOrder 38 +PIN 512 -96 RIGHT 8 +PINATTR PinName Comp3b +PINATTR SpiceOrder 49 +PIN -512 -96 LEFT 8 +PINATTR PinName Comp0b +PINATTR SpiceOrder 14 +PIN -112 -736 TOP 8 +PINATTR PinName Intvcc0 +PINATTR SpiceOrder 16 +PIN 512 0 RIGHT 8 +PINATTR PinName Clkout3 +PINATTR SpiceOrder 44 +PIN 512 176 RIGHT 8 +PINATTR PinName Freq3 +PINATTR SpiceOrder 42 +PIN -224 -736 TOP 8 +PINATTR PinName Mode0 +PINATTR SpiceOrder 35 +PIN -336 -736 TOP 8 +PINATTR PinName Phmode0 +PINATTR SpiceOrder 37 +PIN -448 -736 TOP 8 +PINATTR PinName Pgood0 +PINATTR SpiceOrder 32 +PIN 224 -736 TOP 8 +PINATTR PinName Mode3 +PINATTR SpiceOrder 43 +PIN 336 -736 TOP 8 +PINATTR PinName Phmode3 +PINATTR SpiceOrder 45 +PIN 448 -736 TOP 8 +PINATTR PinName Pgood3 +PINATTR SpiceOrder 40 diff --git a/spice/copy/sym/PowerProducts/LTM4675.asy b/spice/copy/sym/PowerProducts/LTM4675.asy new file mode 100755 index 0000000..5989470 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4675.asy @@ -0,0 +1,103 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -448 400 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTM4675 +SYMATTR Prefix X +SYMATTR Description Dual 9A or Single 18A µModule Regulator with Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4675.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=2 Fault_response=0 Retry_delay=.1m +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 400 -96 RIGHT 8 +PINATTR PinName Vosns0+ +PINATTR SpiceOrder 1 +PIN 400 96 RIGHT 8 +PINATTR PinName Vosns0- +PINATTR SpiceOrder 2 +PIN 400 288 RIGHT 8 +PINATTR PinName COMP0a +PINATTR SpiceOrder 5 +PIN -320 448 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 8 +PIN 400 -384 RIGHT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 9 +PIN 400 -192 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 11 +PIN 320 -448 TOP 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 14 +PIN -320 -448 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 15 +PIN 400 384 RIGHT 8 +PINATTR PinName COMP0b +PINATTR SpiceOrder 16 +PIN -64 448 BOTTOM 8 +PINATTR PinName Fswphcfg +PINATTR SpiceOrder 17 +PIN 192 448 BOTTOM 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 18 +PIN -400 288 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 19 +PIN 320 448 BOTTOM 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 20 +PIN -400 384 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 21 +PIN 64 -448 TOP 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 22 +PIN -400 192 LEFT 8 +PINATTR PinName COMP1b +PINATTR SpiceOrder 23 +PIN -400 -384 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 24 +PIN 192 -448 TOP 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 25 +PIN -400 96 LEFT 8 +PINATTR PinName COMP1a +PINATTR SpiceOrder 26 +PIN -400 -96 LEFT 8 +PINATTR PinName Vosns1 +PINATTR SpiceOrder 27 +PIN -400 -288 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 29 +PIN -400 -192 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 30 +PIN -64 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 33 +PIN -192 448 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 35 +PIN 400 0 RIGHT 8 +PINATTR PinName Vorb0+ +PINATTR SpiceOrder 36 +PIN 400 192 RIGHT 8 +PINATTR PinName Vorb0- +PINATTR SpiceOrder 37 +PIN -400 0 LEFT 8 +PINATTR PinName Vorb1 +PINATTR SpiceOrder 38 +PIN 400 -288 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 39 +PIN 64 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 41 + diff --git a/spice/copy/sym/PowerProducts/LTM4676.asy b/spice/copy/sym/PowerProducts/LTM4676.asy new file mode 100755 index 0000000..5d54787 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4676.asy @@ -0,0 +1,132 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -688 400 688 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -288 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTM4676 +SYMATTR Prefix X +SYMATTR Description Dual 13A or Single 26A µModule Regulator with PMBus Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4676.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=2 Fault_response=0 Retry_delay=.1m +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 400 144 RIGHT 8 +PINATTR PinName Vosns0+ +PINATTR SpiceOrder 1 +PIN 400 336 RIGHT 8 +PINATTR PinName Vosns0- +PINATTR SpiceOrder 2 +PIN -400 -144 LEFT 8 +PINATTR PinName Isns1a+ +PINATTR SpiceOrder 3 +PIN -400 48 LEFT 8 +PINATTR PinName Isns1a- +PINATTR SpiceOrder 4 +PIN 400 528 RIGHT 8 +PINATTR PinName COMP0a +PINATTR SpiceOrder 5 +PIN 400 -240 RIGHT 8 +PINATTR PinName Isns0b+ +PINATTR SpiceOrder 6 +PIN 400 48 RIGHT 8 +PINATTR PinName Isns0a- +PINATTR SpiceOrder 7 +PIN -320 688 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 8 +PIN 400 -624 RIGHT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 9 +PIN 400 -528 RIGHT 8 +PINATTR PinName SNUB0 +PINATTR SpiceOrder 10 +PIN 400 -336 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 11 +PIN 400 -144 RIGHT 8 +PINATTR PinName Isns0a+ +PINATTR SpiceOrder 12 +PIN 400 -48 RIGHT 8 +PINATTR PinName Isns0b- +PINATTR SpiceOrder 13 +PIN 320 -688 TOP 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 14 +PIN -320 -688 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 15 +PIN 400 624 RIGHT 8 +PINATTR PinName COMP0b +PINATTR SpiceOrder 16 +PIN -64 688 BOTTOM 8 +PINATTR PinName Fswphcfg +PINATTR SpiceOrder 17 +PIN 192 688 BOTTOM 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 18 +PIN -400 528 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 19 +PIN 320 688 BOTTOM 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 20 +PIN -400 624 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 21 +PIN 64 -688 TOP 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 22 +PIN -400 432 LEFT 8 +PINATTR PinName COMP1b +PINATTR SpiceOrder 23 +PIN -400 -624 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 24 +PIN 192 -688 TOP 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 25 +PIN -400 336 LEFT 8 +PINATTR PinName COMP1a +PINATTR SpiceOrder 26 +PIN -400 144 LEFT 8 +PINATTR PinName Vosns1 +PINATTR SpiceOrder 27 +PIN -400 -528 LEFT 8 +PINATTR PinName SNUB1 +PINATTR SpiceOrder 28 +PIN -400 -432 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 29 +PIN -400 -336 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 30 +PIN -400 -240 LEFT 8 +PINATTR PinName Isns1b+ +PINATTR SpiceOrder 31 +PIN -400 -48 LEFT 8 +PINATTR PinName Isns1b- +PINATTR SpiceOrder 32 +PIN -64 -688 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 33 +PIN -192 688 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 34 +PIN -192 -688 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 35 +PIN 400 240 RIGHT 8 +PINATTR PinName Vorb0+ +PINATTR SpiceOrder 36 +PIN 400 432 RIGHT 8 +PINATTR PinName Vorb0- +PINATTR SpiceOrder 37 +PIN -400 240 LEFT 8 +PINATTR PinName Vorb1 +PINATTR SpiceOrder 38 +PIN 400 -432 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 39 +PIN 64 688 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 41 diff --git a/spice/copy/sym/PowerProducts/LTM4676A.asy b/spice/copy/sym/PowerProducts/LTM4676A.asy new file mode 100755 index 0000000..c931260 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4676A.asy @@ -0,0 +1,133 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -688 400 688 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -288 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTM4676A +SYMATTR Prefix X +SYMATTR Description Dual 13A or Single 26A µModule Regulator with Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4676A.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=2 Fault_response=0 Retry_delay=.1m +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 400 144 RIGHT 8 +PINATTR PinName Vosns0+ +PINATTR SpiceOrder 1 +PIN 400 336 RIGHT 8 +PINATTR PinName Vosns0- +PINATTR SpiceOrder 2 +PIN -400 -144 LEFT 8 +PINATTR PinName Isns1a+ +PINATTR SpiceOrder 3 +PIN -400 48 LEFT 8 +PINATTR PinName Isns1a- +PINATTR SpiceOrder 4 +PIN 400 528 RIGHT 8 +PINATTR PinName COMP0a +PINATTR SpiceOrder 5 +PIN 400 -240 RIGHT 8 +PINATTR PinName Isns0b+ +PINATTR SpiceOrder 6 +PIN 400 48 RIGHT 8 +PINATTR PinName Isns0a- +PINATTR SpiceOrder 7 +PIN -320 688 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 8 +PIN 400 -624 RIGHT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 9 +PIN 400 -528 RIGHT 8 +PINATTR PinName SNUB0 +PINATTR SpiceOrder 10 +PIN 400 -336 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 11 +PIN 400 -144 RIGHT 8 +PINATTR PinName Isns0a+ +PINATTR SpiceOrder 12 +PIN 400 -48 RIGHT 8 +PINATTR PinName Isns0b- +PINATTR SpiceOrder 13 +PIN 320 -688 TOP 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 14 +PIN -320 -688 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 15 +PIN 400 624 RIGHT 8 +PINATTR PinName COMP0b +PINATTR SpiceOrder 16 +PIN -64 688 BOTTOM 8 +PINATTR PinName Fswphcfg +PINATTR SpiceOrder 17 +PIN 192 688 BOTTOM 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 18 +PIN -400 528 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 19 +PIN 320 688 BOTTOM 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 20 +PIN -400 624 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 21 +PIN 64 -688 TOP 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 22 +PIN -400 432 LEFT 8 +PINATTR PinName COMP1b +PINATTR SpiceOrder 23 +PIN -400 -624 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 24 +PIN 192 -688 TOP 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 25 +PIN -400 336 LEFT 8 +PINATTR PinName COMP1a +PINATTR SpiceOrder 26 +PIN -400 144 LEFT 8 +PINATTR PinName Vosns1 +PINATTR SpiceOrder 27 +PIN -400 -528 LEFT 8 +PINATTR PinName SNUB1 +PINATTR SpiceOrder 28 +PIN -400 -432 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 29 +PIN -400 -336 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 30 +PIN -400 -240 LEFT 8 +PINATTR PinName Isns1b+ +PINATTR SpiceOrder 31 +PIN -400 -48 LEFT 8 +PINATTR PinName Isns1b- +PINATTR SpiceOrder 32 +PIN -64 -688 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 33 +PIN -192 688 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 34 +PIN -192 -688 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 35 +PIN 400 240 RIGHT 8 +PINATTR PinName Vorb0+ +PINATTR SpiceOrder 36 +PIN 400 432 RIGHT 8 +PINATTR PinName Vorb0- +PINATTR SpiceOrder 37 +PIN -400 240 LEFT 8 +PINATTR PinName Vorb1 +PINATTR SpiceOrder 38 +PIN 400 -432 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 39 +PIN 64 688 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 41 + diff --git a/spice/copy/sym/PowerProducts/LTM4677.asy b/spice/copy/sym/PowerProducts/LTM4677.asy new file mode 100755 index 0000000..da3a006 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4677.asy @@ -0,0 +1,132 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -688 400 688 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -288 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTM4677 +SYMATTR Prefix X +SYMATTR Description Dual 18A or Single 36A µModule Regulator with Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4677.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=2 Fault_response=0 Retry_delay=.1m +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 400 144 RIGHT 8 +PINATTR PinName Vosns0+ +PINATTR SpiceOrder 1 +PIN 400 336 RIGHT 8 +PINATTR PinName Vosns0- +PINATTR SpiceOrder 2 +PIN -400 -144 LEFT 8 +PINATTR PinName Isns1a+ +PINATTR SpiceOrder 3 +PIN -400 48 LEFT 8 +PINATTR PinName Isns1a- +PINATTR SpiceOrder 4 +PIN 400 528 RIGHT 8 +PINATTR PinName COMP0a +PINATTR SpiceOrder 5 +PIN 400 -240 RIGHT 8 +PINATTR PinName Isns0b+ +PINATTR SpiceOrder 6 +PIN 400 48 RIGHT 8 +PINATTR PinName Isns0a- +PINATTR SpiceOrder 7 +PIN -320 688 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 8 +PIN 400 -624 RIGHT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 9 +PIN 400 -528 RIGHT 8 +PINATTR PinName SNUB0 +PINATTR SpiceOrder 10 +PIN 400 -336 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 11 +PIN 400 -144 RIGHT 8 +PINATTR PinName Isns0a+ +PINATTR SpiceOrder 12 +PIN 400 -48 RIGHT 8 +PINATTR PinName Isns0b- +PINATTR SpiceOrder 13 +PIN 320 -688 TOP 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 14 +PIN -320 -688 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 15 +PIN 400 624 RIGHT 8 +PINATTR PinName COMP0b +PINATTR SpiceOrder 16 +PIN -64 688 BOTTOM 8 +PINATTR PinName Fswphcfg +PINATTR SpiceOrder 17 +PIN 192 688 BOTTOM 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 18 +PIN -400 528 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 19 +PIN 320 688 BOTTOM 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 20 +PIN -400 624 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 21 +PIN 64 -688 TOP 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 22 +PIN -400 432 LEFT 8 +PINATTR PinName COMP1b +PINATTR SpiceOrder 23 +PIN -400 -624 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 24 +PIN 192 -688 TOP 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 25 +PIN -400 336 LEFT 8 +PINATTR PinName COMP1a +PINATTR SpiceOrder 26 +PIN -400 144 LEFT 8 +PINATTR PinName Vosns1 +PINATTR SpiceOrder 27 +PIN -400 -528 LEFT 8 +PINATTR PinName SNUB1 +PINATTR SpiceOrder 28 +PIN -400 -432 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 29 +PIN -400 -336 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 30 +PIN -400 -240 LEFT 8 +PINATTR PinName Isns1b+ +PINATTR SpiceOrder 31 +PIN -400 -48 LEFT 8 +PINATTR PinName Isns1b- +PINATTR SpiceOrder 32 +PIN -64 -688 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 33 +PIN -192 688 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 34 +PIN -192 -688 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 35 +PIN 400 240 RIGHT 8 +PINATTR PinName Vorb0+ +PINATTR SpiceOrder 36 +PIN 400 432 RIGHT 8 +PINATTR PinName Vorb0- +PINATTR SpiceOrder 37 +PIN -400 240 LEFT 8 +PINATTR PinName Vorb1 +PINATTR SpiceOrder 38 +PIN 400 -432 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 39 +PIN 64 688 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 41 diff --git a/spice/copy/sym/PowerProducts/LTM4678.asy b/spice/copy/sym/PowerProducts/LTM4678.asy new file mode 100755 index 0000000..086c034 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4678.asy @@ -0,0 +1,105 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -544 256 544 +TEXT 0 0 Center 2 LT +WINDOW 0 2 -243 Center 2 +WINDOW 3 8 245 Center 2 +SYMATTR Value LTM4678 +SYMATTR Prefix X +SYMATTR Description Dual Output Polyphase Step-Down DC/DC Controller with Sub-Milliohm DCR Sensing and Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4678.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=1 Fault_response=0 Retry_delay=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K Sync=0 +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 256 -192 RIGHT 8 +PINATTR PinName Vsense0+ +PINATTR SpiceOrder 1 +PIN 256 -96 RIGHT 8 +PINATTR PinName Vsense0- +PINATTR SpiceOrder 2 +PIN 256 96 RIGHT 8 +PINATTR PinName Comp0a +PINATTR SpiceOrder 5 +PIN 256 0 RIGHT 8 +PINATTR PinName Comp0b +PINATTR SpiceOrder 6 +PIN 256 -480 RIGHT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 9 +PIN -256 -480 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 10 +PIN 96 544 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 11 +PIN 192 544 BOTTOM 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 17 +PIN -192 544 BOTTOM 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 18 +PIN 256 288 RIGHT 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 20 +PIN 256 192 RIGHT 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 21 +PIN -256 192 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 22 +PIN -256 288 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 23 +PIN -256 384 LEFT 8 +PINATTR PinName Fswph_cfg +PINATTR SpiceOrder 24 +PIN -96 544 BOTTOM 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 25 +PIN 0 544 BOTTOM 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 28 +PIN -256 0 LEFT 8 +PINATTR PinName Comp1b +PINATTR SpiceOrder 29 +PIN -256 96 LEFT 8 +PINATTR PinName Comp1a +PINATTR SpiceOrder 30 +PIN -256 -96 LEFT 8 +PINATTR PinName Vsense1- +PINATTR SpiceOrder 31 +PIN -256 -192 LEFT 8 +PINATTR PinName Vsense1+ +PINATTR SpiceOrder 32 +PIN -256 480 LEFT 8 +PINATTR PinName PGood1 +PINATTR SpiceOrder 33 +PIN -256 -384 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN -256 -288 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 37 +PIN -96 -544 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 38 +PIN -192 -544 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 39 +PIN 192 -544 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 40 +PIN 0 -544 TOP 8 +PINATTR PinName PGND +PINATTR SpiceOrder 41 +PIN 256 -288 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 42 +PIN 256 -384 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 45 +PIN 256 480 RIGHT 8 +PINATTR PinName PGood0 +PINATTR SpiceOrder 48 +PIN 96 -544 TOP 8 +PINATTR PinName SGND +PINATTR SpiceOrder 49 diff --git a/spice/copy/sym/PowerProducts/LTM4680.asy b/spice/copy/sym/PowerProducts/LTM4680.asy new file mode 100755 index 0000000..0aefabe --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4680.asy @@ -0,0 +1,105 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -544 256 544 +TEXT 0 0 Center 2 LT +WINDOW 0 2 -243 Center 2 +WINDOW 3 8 245 Center 2 +SYMATTR Value LTM4680 +SYMATTR Prefix X +SYMATTR Description Dual Output Polyphase Step-Down DC/DC Controller with Sub-Milliohm DCR Sensing and Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4680.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=1 Fault_response=0 Retry_delay=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K Sync=0 +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 256 -192 RIGHT 8 +PINATTR PinName Vsense0+ +PINATTR SpiceOrder 1 +PIN 256 -96 RIGHT 8 +PINATTR PinName Vsense0- +PINATTR SpiceOrder 2 +PIN 256 96 RIGHT 8 +PINATTR PinName Comp0a +PINATTR SpiceOrder 5 +PIN 256 0 RIGHT 8 +PINATTR PinName Comp0b +PINATTR SpiceOrder 6 +PIN 256 -480 RIGHT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 9 +PIN -256 -480 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 10 +PIN 96 544 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 11 +PIN 192 544 BOTTOM 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 17 +PIN -192 544 BOTTOM 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 18 +PIN 256 288 RIGHT 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 20 +PIN 256 192 RIGHT 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 21 +PIN -256 192 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 22 +PIN -256 288 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 23 +PIN -256 384 LEFT 8 +PINATTR PinName Fswph_cfg +PINATTR SpiceOrder 24 +PIN -96 544 BOTTOM 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 25 +PIN 0 544 BOTTOM 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 28 +PIN -256 0 LEFT 8 +PINATTR PinName Comp1b +PINATTR SpiceOrder 29 +PIN -256 96 LEFT 8 +PINATTR PinName Comp1a +PINATTR SpiceOrder 30 +PIN -256 -96 LEFT 8 +PINATTR PinName Vsense1- +PINATTR SpiceOrder 31 +PIN -256 -192 LEFT 8 +PINATTR PinName Vsense1+ +PINATTR SpiceOrder 32 +PIN -256 480 LEFT 8 +PINATTR PinName PGood1 +PINATTR SpiceOrder 33 +PIN -256 -384 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN -256 -288 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 37 +PIN -96 -544 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 38 +PIN -192 -544 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 39 +PIN 192 -544 TOP 8 +PINATTR PinName ExtVcc +PINATTR SpiceOrder 40 +PIN 0 -544 TOP 8 +PINATTR PinName PGND +PINATTR SpiceOrder 41 +PIN 256 -288 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 42 +PIN 256 -384 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 45 +PIN 256 480 RIGHT 8 +PINATTR PinName PGood0 +PINATTR SpiceOrder 48 +PIN 96 -544 TOP 8 +PINATTR PinName SGND +PINATTR SpiceOrder 49 diff --git a/spice/copy/sym/PowerProducts/LTM4681.asy b/spice/copy/sym/PowerProducts/LTM4681.asy new file mode 100755 index 0000000..17a2fd9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4681.asy @@ -0,0 +1,189 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -544 1872 1024 +TEXT 834 223 Center 2 LT +WINDOW 0 836 -20 Center 2 +WINDOW 3 842 468 Center 2 +SYMATTR Value LTM4681 +SYMATTR Prefix X +SYMATTR Description Dual Output 50A Polyphase Step-Down Power Supply Module with Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4681.sub +SYMATTR SpiceLine Vin01ON=5.5 Vin01OFF=5 Vo0=1 Vo1=1 ILM0=0 ILM1=0 OC0=1 OC1=1 Mode01=1 Fault01=0 Retry01=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K Sync01=0 Fsw01=500K PH0=0 PH1=180 Ton0=.3m Ton0r=.5m Ton1=.3m Ton1r=.5m Toff0=.2m Toff0f=.3m Toff1=.2m Toff1f=.3m Vo0r=0 Vo1r=0 +SYMATTR SpiceLine2 Vin23ON=5.5 Vin23OFF=5 Vo2=1 Vo3=1 ILM2=0 ILM3=0 OC2=1 OC3=1 Mode23=1 Fault23=0 Retry23=.1m gm2=3m gm3=3m Rth2=5K Rth3=5K Sync23=0 Fsw23=500K PH2=0 PH3=180 Ton2=.3m Ton2r=.5m Ton3=.3m Ton3r=.5m Toff2=.2m Toff2f=.3m Toff3=.2m Toff3f=.3m Vo2r=0 Vo3r=0 +PIN -256 0 LEFT 8 +PINATTR PinName Vosns0+ +PINATTR SpiceOrder 1 +PIN -256 96 LEFT 8 +PINATTR PinName Vosns0- +PINATTR SpiceOrder 2 +PIN -256 -480 LEFT 8 +PINATTR PinName VIN_Vbias +PINATTR SpiceOrder 3 +PIN -256 288 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 4 +PIN 320 1024 BOTTOM 8 +PINATTR PinName Comp0a +PINATTR SpiceOrder 5 +PIN 464 1024 BOTTOM 8 +PINATTR PinName Comp0b +PINATTR SpiceOrder 6 +PIN 1872 -384 RIGHT 8 +PINATTR PinName Vin23 +PINATTR SpiceOrder 7 +PIN -256 -96 LEFT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 8 +PIN 32 1024 BOTTOM 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 9 +PIN 1616 1024 BOTTOM 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 10 +PIN 608 1024 BOTTOM 8 +PINATTR PinName SYNC_01 +PINATTR SpiceOrder 11 +PIN 1872 768 RIGHT 8 +PINATTR PinName IntVcc_23 +PINATTR SpiceOrder 14 +PIN 1872 864 RIGHT 8 +PINATTR PinName VDD33_23 +PINATTR SpiceOrder 15 +PIN 1872 960 RIGHT 8 +PINATTR PinName VDD25_23 +PINATTR SpiceOrder 16 +PIN -256 576 LEFT 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 17 +PIN -256 672 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 18 +PIN 1024 -544 TOP 8 +PINATTR PinName Fswph_23_cfg +PINATTR SpiceOrder 19 +PIN 608 -544 TOP 8 +PINATTR PinName SYNC_23 +PINATTR SpiceOrder 20 +PIN 176 1024 BOTTOM 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 21 +PIN 1472 1024 BOTTOM 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 22 +PIN 1872 -192 RIGHT 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 23 +PIN 1040 1024 BOTTOM 8 +PINATTR PinName Fswph_01_cfg +PINATTR SpiceOrder 24 +PIN -256 960 LEFT 8 +PINATTR PinName VDD25_01 +PINATTR SpiceOrder 25 +PIN 1872 0 RIGHT 8 +PINATTR PinName Vosns2+ +PINATTR SpiceOrder 27 +PIN -256 864 LEFT 8 +PINATTR PinName VDD33_01 +PINATTR SpiceOrder 28 +PIN 1328 1024 BOTTOM 8 +PINATTR PinName Comp1b +PINATTR SpiceOrder 29 +PIN 1184 1024 BOTTOM 8 +PINATTR PinName Comp1a +PINATTR SpiceOrder 30 +PIN -256 480 LEFT 8 +PINATTR PinName Vosns1- +PINATTR SpiceOrder 31 +PIN -256 384 LEFT 8 +PINATTR PinName Vosns1+ +PINATTR SpiceOrder 32 +PIN 1760 1024 BOTTOM 8 +PINATTR PinName PGood1 +PINATTR SpiceOrder 33 +PIN -256 192 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN 1872 96 RIGHT 8 +PINATTR PinName Vosns2- +PINATTR SpiceOrder 35 +PIN 320 -544 TOP 8 +PINATTR PinName Comp2a +PINATTR SpiceOrder 36 +PIN 176 -544 TOP 8 +PINATTR PinName Vout2_cfg +PINATTR SpiceOrder 37 +PIN -256 768 LEFT 8 +PINATTR PinName IntVcc_01 +PINATTR SpiceOrder 38 +PIN -256 -384 LEFT 8 +PINATTR PinName Vin01 +PINATTR SpiceOrder 39 +PIN 880 -544 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 40 +PIN 896 1024 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 41 +PIN 1872 576 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 42 +PIN 1872 672 RIGHT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 43 +PIN 1872 192 RIGHT 8 +PINATTR PinName SW3 +PINATTR SpiceOrder 44 +PIN -256 -192 LEFT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 45 +PIN 1168 -544 TOP 8 +PINATTR PinName Comp3a +PINATTR SpiceOrder 46 +PIN 1456 -544 TOP 8 +PINATTR PinName Vout3_cfg +PINATTR SpiceOrder 47 +PIN -112 1024 BOTTOM 8 +PINATTR PinName PGood0 +PINATTR SpiceOrder 48 +PIN 752 1024 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 49 +PIN 752 -544 TOP 8 +PINATTR PinName Runp +PINATTR SpiceOrder 51 +PIN -256 -288 LEFT 8 +PINATTR PinName SVin_01 +PINATTR SpiceOrder 52 +PIN 464 -544 TOP 8 +PINATTR PinName Comp2b +PINATTR SpiceOrder 53 +PIN 1312 -544 TOP 8 +PINATTR PinName Comp3b +PINATTR SpiceOrder 54 +PIN 1872 384 RIGHT 8 +PINATTR PinName Vosns3+ +PINATTR SpiceOrder 55 +PIN 1872 480 RIGHT 8 +PINATTR PinName Vosns3- +PINATTR SpiceOrder 56 +PIN -112 -544 TOP 8 +PINATTR PinName PGood2 +PINATTR SpiceOrder 57 +PIN 1744 -544 TOP 8 +PINATTR PinName PGood3 +PINATTR SpiceOrder 58 +PIN 1872 -96 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 59 +PIN 1872 288 RIGHT 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 60 +PIN 32 -544 TOP 8 +PINATTR PinName Vtrim2_cfg +PINATTR SpiceOrder 61 +PIN 1600 -544 TOP 8 +PINATTR PinName Vtrim3_cfg +PINATTR SpiceOrder 62 +PIN 1872 -288 RIGHT 8 +PINATTR PinName SVin_23 +PINATTR SpiceOrder 63 diff --git a/spice/copy/sym/PowerProducts/LTM4686-1.asy b/spice/copy/sym/PowerProducts/LTM4686-1.asy new file mode 100755 index 0000000..16e6a78 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4686-1.asy @@ -0,0 +1,102 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -448 400 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTM4686-1 +SYMATTR Prefix X +SYMATTR Description Dual 10A or Single 20A µModule Regulator with Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4686-1.sub +SYMATTR SpiceLine Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=2 Fault_response=0 Retry_delay=.1m +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 400 -96 RIGHT 8 +PINATTR PinName Vosns0+ +PINATTR SpiceOrder 1 +PIN 400 96 RIGHT 8 +PINATTR PinName Vosns0- +PINATTR SpiceOrder 2 +PIN 400 288 RIGHT 8 +PINATTR PinName COMP0a +PINATTR SpiceOrder 5 +PIN -320 448 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 8 +PIN 400 -384 RIGHT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 9 +PIN 400 -192 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 11 +PIN 320 -448 TOP 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 14 +PIN -320 -448 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 15 +PIN 400 384 RIGHT 8 +PINATTR PinName COMP0b +PINATTR SpiceOrder 16 +PIN -64 448 BOTTOM 8 +PINATTR PinName Fswphcfg +PINATTR SpiceOrder 17 +PIN 192 448 BOTTOM 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 18 +PIN -400 288 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 19 +PIN 320 448 BOTTOM 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 20 +PIN -400 384 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 21 +PIN 64 -448 TOP 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 22 +PIN -400 192 LEFT 8 +PINATTR PinName COMP1b +PINATTR SpiceOrder 23 +PIN -400 -384 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 24 +PIN 192 -448 TOP 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 25 +PIN -400 96 LEFT 8 +PINATTR PinName COMP1a +PINATTR SpiceOrder 26 +PIN -400 -96 LEFT 8 +PINATTR PinName Vosns1 +PINATTR SpiceOrder 27 +PIN -400 -288 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 29 +PIN -400 -192 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 30 +PIN -64 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 33 +PIN -192 448 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 35 +PIN 400 0 RIGHT 8 +PINATTR PinName Vorb0+ +PINATTR SpiceOrder 36 +PIN 400 192 RIGHT 8 +PINATTR PinName Vorb0- +PINATTR SpiceOrder 37 +PIN -400 0 LEFT 8 +PINATTR PinName Vorb1 +PINATTR SpiceOrder 38 +PIN 400 -288 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 39 +PIN 64 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 41 diff --git a/spice/copy/sym/PowerProducts/LTM4686.asy b/spice/copy/sym/PowerProducts/LTM4686.asy new file mode 100755 index 0000000..2b38f9a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4686.asy @@ -0,0 +1,102 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -400 -448 400 448 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTM4686 +SYMATTR Prefix X +SYMATTR Description Dual 10A or Single 20A µModule Regulator with Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4686.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=2 Fault_response=0 Retry_delay=.1m +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 400 -96 RIGHT 8 +PINATTR PinName Vosns0+ +PINATTR SpiceOrder 1 +PIN 400 96 RIGHT 8 +PINATTR PinName Vosns0- +PINATTR SpiceOrder 2 +PIN 400 288 RIGHT 8 +PINATTR PinName COMP0a +PINATTR SpiceOrder 5 +PIN -320 448 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 8 +PIN 400 -384 RIGHT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 9 +PIN 400 -192 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 11 +PIN 320 -448 TOP 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 14 +PIN -320 -448 TOP 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 15 +PIN 400 384 RIGHT 8 +PINATTR PinName COMP0b +PINATTR SpiceOrder 16 +PIN -64 448 BOTTOM 8 +PINATTR PinName Fswphcfg +PINATTR SpiceOrder 17 +PIN 192 448 BOTTOM 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 18 +PIN -400 288 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 19 +PIN 320 448 BOTTOM 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 20 +PIN -400 384 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 21 +PIN 64 -448 TOP 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 22 +PIN -400 192 LEFT 8 +PINATTR PinName COMP1b +PINATTR SpiceOrder 23 +PIN -400 -384 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 24 +PIN 192 -448 TOP 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 25 +PIN -400 96 LEFT 8 +PINATTR PinName COMP1a +PINATTR SpiceOrder 26 +PIN -400 -96 LEFT 8 +PINATTR PinName Vosns1 +PINATTR SpiceOrder 27 +PIN -400 -288 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 29 +PIN -400 -192 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 30 +PIN -64 -448 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 33 +PIN -192 448 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 34 +PIN -192 -448 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 35 +PIN 400 0 RIGHT 8 +PINATTR PinName Vorb0+ +PINATTR SpiceOrder 36 +PIN 400 192 RIGHT 8 +PINATTR PinName Vorb0- +PINATTR SpiceOrder 37 +PIN -400 0 LEFT 8 +PINATTR PinName Vorb1 +PINATTR SpiceOrder 38 +PIN 400 -288 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 39 +PIN 64 448 BOTTOM 8 +PINATTR PinName SGND +PINATTR SpiceOrder 41 diff --git a/spice/copy/sym/PowerProducts/LTM4691.asy b/spice/copy/sym/PowerProducts/LTM4691.asy new file mode 100755 index 0000000..97a5132 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4691.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -240 160 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM4691 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4691.sub +SYMATTR Value2 LTM4691 +SYMATTR Description Low Vin, High Efficiency, Dual 2A Step-Down DC/DC uModule Regulator +PIN -160 -192 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 1 +PIN -160 -80 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 2 +PIN 160 -80 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 3 +PIN 160 32 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 4 +PIN 0 304 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -160 32 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 6 +PIN -160 144 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 7 +PIN 160 -192 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 8 +PIN -160 256 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 9 +PIN 160 144 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 10 +PIN 160 256 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM4693.asy b/spice/copy/sym/PowerProducts/LTM4693.asy new file mode 100755 index 0000000..6ca8b91 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4693.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 161 224 -160 -192 +TEXT 0 0 Center 2 LT +WINDOW 3 -3 79 Center 2 +WINDOW 0 2 -64 Center 2 +SYMATTR Value LTM4693 +SYMATTR Prefix X +SYMATTR SpiceModel LTM4693.sub +SYMATTR Value2 LTM4693 +SYMATTR Description 5A Low Noise, High Performance Buck-Boost DC/DC µModule Regulator +PIN -64 -192 TOP 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 1 +PIN 64 -192 TOP 8 +PINATTR PinName SW2 +PINATTR SpiceOrder 2 +PIN 160 -128 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN -160 -32 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 4 +PIN -160 64 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 5 +PIN 160 160 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 6 +PIN 160 -32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 160 64 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 9 +PIN -160 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -160 160 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM4699.asy b/spice/copy/sym/PowerProducts/LTM4699.asy new file mode 100755 index 0000000..e397c44 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4699.asy @@ -0,0 +1,162 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -976 256 992 +TEXT 0 0 Center 2 LT +WINDOW 0 7 -524 Center 2 +WINDOW 3 -4 622 Center 2 +SYMATTR Value LTM4699 +SYMATTR Prefix X +SYMATTR Description Dual Output 50A Polyphase Step-Down Power Supply Module with Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4699.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=1 Fault_response=0 Retry_delay=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K Sync=0 +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 256 -624 RIGHT 8 +PINATTR PinName Vosns+_C0 +PINATTR SpiceOrder 1 +PIN 256 -528 RIGHT 8 +PINATTR PinName Vosns-_C0 +PINATTR SpiceOrder 2 +PIN 256 48 RIGHT 8 +PINATTR PinName VoutC1 +PINATTR SpiceOrder 4 +PIN 256 -336 RIGHT 8 +PINATTR PinName Comp_C0a +PINATTR SpiceOrder 5 +PIN 256 -432 RIGHT 8 +PINATTR PinName Comp_C0b +PINATTR SpiceOrder 6 +PIN 256 -720 RIGHT 8 +PINATTR PinName VoutC0 +PINATTR SpiceOrder 8 +PIN 256 -144 RIGHT 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 9 +PIN 256 624 RIGHT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 10 +PIN 96 992 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 11 +PIN 192 992 BOTTOM 8 +PINATTR PinName Run_C0 +PINATTR SpiceOrder 17 +PIN -192 992 BOTTOM 8 +PINATTR PinName Run_C1 +PINATTR SpiceOrder 18 +PIN 256 -240 RIGHT 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 21 +PIN 256 528 RIGHT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 22 +PIN 256 720 RIGHT 8 +PINATTR PinName Fswph_cfg +PINATTR SpiceOrder 24 +PIN 0 -976 TOP 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 25 +PIN -96 992 BOTTOM 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 28 +PIN 256 336 RIGHT 8 +PINATTR PinName Comp_C1b +PINATTR SpiceOrder 29 +PIN 256 432 RIGHT 8 +PINATTR PinName Comp_C1a +PINATTR SpiceOrder 30 +PIN 256 240 RIGHT 8 +PINATTR PinName Vosns-_C1 +PINATTR SpiceOrder 31 +PIN 256 144 RIGHT 8 +PINATTR PinName Vosns+_C1 +PINATTR SpiceOrder 32 +PIN 256 912 RIGHT 8 +PINATTR PinName PGood_C1 +PINATTR SpiceOrder 33 +PIN 256 -48 RIGHT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN 256 816 RIGHT 8 +PINATTR PinName IntVcc_C0_C1 +PINATTR SpiceOrder 38 +PIN 256 -912 RIGHT 8 +PINATTR PinName Vin2_C0_C1 +PINATTR SpiceOrder 39 +PIN 192 -976 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 40 +PIN 0 992 BOTTOM 8 +PINATTR PinName PGND +PINATTR SpiceOrder 41 +PIN 256 -816 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 45 +PIN -256 912 LEFT 8 +PINATTR PinName PGood_C0 +PINATTR SpiceOrder 48 +PIN 96 -976 TOP 8 +PINATTR PinName SGND +PINATTR SpiceOrder 49 +PIN -96 -976 TOP 8 +PINATTR PinName Runp +PINATTR SpiceOrder 51 +PIN -192 -976 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 52 +PIN -256 -912 LEFT 8 +PINATTR PinName VinS1 +PINATTR SpiceOrder 16 +PIN -256 -816 LEFT 8 +PINATTR PinName Cfly+ +PINATTR SpiceOrder 12 +PIN -256 -720 LEFT 8 +PINATTR PinName Mid +PINATTR SpiceOrder 13 +PIN -256 -624 LEFT 8 +PINATTR PinName Cfly- +PINATTR SpiceOrder 14 +PIN -256 -528 LEFT 8 +PINATTR PinName VoutS1 +PINATTR SpiceOrder 44 +PIN -256 -432 LEFT 8 +PINATTR PinName ExtVccS1 +PINATTR SpiceOrder 26 +PIN -256 -336 LEFT 8 +PINATTR PinName IntVccS1 +PINATTR SpiceOrder 15 +PIN -256 -240 LEFT 8 +PINATTR PinName VfbS1 +PINATTR SpiceOrder 35 +PIN -256 -144 LEFT 8 +PINATTR PinName CompaS1 +PINATTR SpiceOrder 36 +PIN -256 -48 LEFT 8 +PINATTR PinName CompbS1 +PINATTR SpiceOrder 46 +PIN -256 48 LEFT 8 +PINATTR PinName TrackS1 +PINATTR SpiceOrder 37 +PIN -256 144 LEFT 8 +PINATTR PinName Mode_PLLinS1 +PINATTR SpiceOrder 43 +PIN -256 240 LEFT 8 +PINATTR PinName ClkoutS1 +PINATTR SpiceOrder 42 +PIN -256 336 LEFT 8 +PINATTR PinName RunS1 +PINATTR SpiceOrder 27 +PIN -256 432 LEFT 8 +PINATTR PinName PgoodS1 +PINATTR SpiceOrder 23 +PIN -256 528 LEFT 8 +PINATTR PinName _FaultS1 +PINATTR SpiceOrder 20 +PIN -256 624 LEFT 8 +PINATTR PinName FreqS1 +PINATTR SpiceOrder 3 +PIN -256 720 LEFT 8 +PINATTR PinName Hys_prgmS1 +PINATTR SpiceOrder 7 +PIN -256 816 LEFT 8 +PINATTR PinName TimerS1 +PINATTR SpiceOrder 19 diff --git a/spice/copy/sym/PowerProducts/LTM4700.asy b/spice/copy/sym/PowerProducts/LTM4700.asy new file mode 100755 index 0000000..154e39e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM4700.asy @@ -0,0 +1,108 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -256 -544 256 544 +TEXT 0 0 Center 2 LT +WINDOW 0 2 -243 Center 2 +WINDOW 3 8 245 Center 2 +SYMATTR Value LTM4700 +SYMATTR Prefix X +SYMATTR Description Dual Output 50A Polyphase Step-Down Power Supply Module with Digital Power System Management\n\nNote: SDA, SCL, _Alert, Share_clk, WP, GPIOs, ASEL, TSNSs are not modeled +SYMATTR ModelFile LTM4700.sub +SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=1 Fault_response=0 Retry_delay=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K Sync=0 +SYMATTR SpiceLine2 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 +PIN 256 -192 RIGHT 8 +PINATTR PinName Vosns0+ +PINATTR SpiceOrder 1 +PIN 256 -96 RIGHT 8 +PINATTR PinName Vosns0- +PINATTR SpiceOrder 2 +PIN -256 -288 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 4 +PIN 256 96 RIGHT 8 +PINATTR PinName Comp0a +PINATTR SpiceOrder 5 +PIN 256 0 RIGHT 8 +PINATTR PinName Comp0b +PINATTR SpiceOrder 6 +PIN 256 -288 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 8 +PIN 256 288 RIGHT 8 +PINATTR PinName Vtrim0_cfg +PINATTR SpiceOrder 9 +PIN -256 288 LEFT 8 +PINATTR PinName Vtrim1_cfg +PINATTR SpiceOrder 10 +PIN 96 544 BOTTOM 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 11 +PIN 192 544 BOTTOM 8 +PINATTR PinName Run0 +PINATTR SpiceOrder 17 +PIN -192 544 BOTTOM 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 18 +PIN 256 192 RIGHT 8 +PINATTR PinName Vout0_cfg +PINATTR SpiceOrder 21 +PIN -256 192 LEFT 8 +PINATTR PinName Vout1_cfg +PINATTR SpiceOrder 22 +PIN -256 384 LEFT 8 +PINATTR PinName Fswph_cfg +PINATTR SpiceOrder 24 +PIN -96 544 BOTTOM 8 +PINATTR PinName VDD25 +PINATTR SpiceOrder 25 +PIN 0 544 BOTTOM 8 +PINATTR PinName VDD33 +PINATTR SpiceOrder 28 +PIN -256 0 LEFT 8 +PINATTR PinName Comp1b +PINATTR SpiceOrder 29 +PIN -256 96 LEFT 8 +PINATTR PinName Comp1a +PINATTR SpiceOrder 30 +PIN -256 -96 LEFT 8 +PINATTR PinName Vosns1- +PINATTR SpiceOrder 31 +PIN -256 -192 LEFT 8 +PINATTR PinName Vosns1+ +PINATTR SpiceOrder 32 +PIN -256 480 LEFT 8 +PINATTR PinName PGood1 +PINATTR SpiceOrder 33 +PIN -256 -384 LEFT 8 +PINATTR PinName SW1 +PINATTR SpiceOrder 34 +PIN -96 -544 TOP 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 38 +PIN 256 -480 RIGHT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 39 +PIN 192 -544 TOP 8 +PINATTR PinName Vbias +PINATTR SpiceOrder 40 +PIN 0 -544 TOP 8 +PINATTR PinName PGND +PINATTR SpiceOrder 41 +PIN 256 -384 RIGHT 8 +PINATTR PinName SW0 +PINATTR SpiceOrder 45 +PIN 256 480 RIGHT 8 +PINATTR PinName PGood0 +PINATTR SpiceOrder 48 +PIN 96 -544 TOP 8 +PINATTR PinName SGND +PINATTR SpiceOrder 49 +PIN 256 384 RIGHT 8 +PINATTR PinName Runp +PINATTR SpiceOrder 51 +PIN -192 -544 TOP 8 +PINATTR PinName SVin +PINATTR SpiceOrder 52 +PIN -256 -480 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 53 diff --git a/spice/copy/sym/PowerProducts/LTM4701.asy b/spice/copy/sym/PowerProducts/LTM4701.asy new file mode 100755 index 0000000..9e84667 Binary files /dev/null and b/spice/copy/sym/PowerProducts/LTM4701.asy differ diff --git a/spice/copy/sym/PowerProducts/LTM8001.asy b/spice/copy/sym/PowerProducts/LTM8001.asy new file mode 100755 index 0000000..a1dc6a2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8001.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -544 176 544 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -240 Center 2 +WINDOW 3 0 240 Center 2 +SYMATTR Value LTM8001 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8001.sub +SYMATTR Value2 LTM8001 +SYMATTR Description 36Vin. 5A µModule Regulator with 5-Output Configurable LDO Array +PIN -176 -480 LEFT 8 +PINATTR PinName Vin0 +PINATTR SpiceOrder 1 +PIN -176 -384 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 2 +PIN -176 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -176 -288 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 5 +PIN -176 -192 LEFT 8 +PINATTR PinName Ilim +PINATTR SpiceOrder 6 +PIN -176 192 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 7 +PIN -176 480 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -176 384 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 9 +PIN -176 288 LEFT 8 +PINATTR PinName FB0 +PINATTR SpiceOrder 10 +PIN -176 -96 LEFT 8 +PINATTR PinName Bias123 +PINATTR SpiceOrder 11 +PIN -176 0 LEFT 8 +PINATTR PinName Bias45 +PINATTR SpiceOrder 12 +PIN 0 -544 TOP 8 +PINATTR PinName Vi45 +PINATTR SpiceOrder 13 +PIN 176 480 RIGHT 8 +PINATTR PinName Set5 +PINATTR SpiceOrder 14 +PIN 176 384 RIGHT 8 +PINATTR PinName Vout5 +PINATTR SpiceOrder 15 +PIN 176 288 RIGHT 8 +PINATTR PinName Set4 +PINATTR SpiceOrder 16 +PIN 176 192 RIGHT 8 +PINATTR PinName Vout4 +PINATTR SpiceOrder 17 +PIN 176 96 RIGHT 8 +PINATTR PinName Set3 +PINATTR SpiceOrder 18 +PIN 176 0 RIGHT 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 19 +PIN 176 -96 RIGHT 8 +PINATTR PinName Set2 +PINATTR SpiceOrder 20 +PIN 176 -192 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 21 +PIN 176 -288 RIGHT 8 +PINATTR PinName Set1 +PINATTR SpiceOrder 22 +PIN 176 -384 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 23 +PIN 176 -480 RIGHT 8 +PINATTR PinName Vout0 +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/PowerProducts/LTM8002.asy b/spice/copy/sym/PowerProducts/LTM8002.asy new file mode 100755 index 0000000..b6de181 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8002.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 -2 -97 Center 2 +WINDOW 3 -2 96 Center 2 +SYMATTR Value LTM8002 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8002.sub +SYMATTR Value2 LTM8002 +SYMATTR Description 40Vin, 2.5A Silent Switcher µModule Regulator +PIN 144 48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 144 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 0 -208 TOP 8 +PINATTR PinName Run +PINATTR SpiceOrder 14 +PIN -144 144 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 15 +PIN 144 144 RIGHT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 -48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 17 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -144 48 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM8003-3.3.asy b/spice/copy/sym/PowerProducts/LTM8003-3.3.asy new file mode 100755 index 0000000..ae7f43b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8003-3.3.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 161 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTM8003-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8003-3.3.sub +SYMATTR Value2 LTM8003-3.3 +SYMATTR Description 40Vin, 3.5A Step-Down µModule Regulator (Fixed Output Version) +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 2 +PIN 160 16 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 3 +PIN -160 112 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 5 +PIN -160 -64 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 10 +PIN -160 16 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 11 +PIN -160 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 12 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 160 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTM8003.asy b/spice/copy/sym/PowerProducts/LTM8003.asy new file mode 100755 index 0000000..c2c550e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8003.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 161 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTM8003 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8003.sub +SYMATTR Value2 LTM8003 +SYMATTR Description 40Vin, 3.5A Step-Down µModule Regulator (H Grade) +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 2 +PIN 160 16 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 3 +PIN -160 112 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 5 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN -160 -64 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 10 +PIN -160 16 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 11 +PIN -160 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 12 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 160 -64 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTM8005.asy b/spice/copy/sym/PowerProducts/LTM8005.asy new file mode 100755 index 0000000..8f98647 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8005.asy @@ -0,0 +1,86 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -208 -400 208 400 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 176 Center 2 +SYMATTR Value LTM8005 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8005.sub +SYMATTR Value2 LTM8005 +SYMATTR Description 38Vin Boost µModule Regulator for LED Drive with 10A Switch +PIN 208 48 RIGHT 8 +PINATTR PinName LED +PINATTR SpiceOrder 30 +PIN 208 144 RIGHT 8 +PINATTR PinName Aux +PINATTR SpiceOrder 33 +PIN 208 240 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 208 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -160 400 BOTTOM 8 +PINATTR PinName Ismon +PINATTR SpiceOrder 5 +PIN -208 -48 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 6 +PIN 208 -48 RIGHT 8 +PINATTR PinName ISN +PINATTR SpiceOrder 2 +PIN 0 400 BOTTOM 8 +PINATTR PinName Vc +PINATTR SpiceOrder 8 +PIN -208 -144 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 9 +PIN -208 -240 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 10 +PIN 160 400 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 11 +PIN 80 400 BOTTOM 8 +PINATTR PinName RT +PINATTR SpiceOrder 12 +PIN -80 400 BOTTOM 8 +PINATTR PinName RAMP +PINATTR SpiceOrder 13 +PIN -208 48 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 14 +PIN -208 240 LEFT 8 +PINATTR PinName _ShortLED +PINATTR SpiceOrder 15 +PIN -208 336 LEFT 8 +PINATTR PinName _OpenLED +PINATTR SpiceOrder 16 +PIN 208 -240 RIGHT 8 +PINATTR PinName DA +PINATTR SpiceOrder 32 +PIN 208 -336 RIGHT 8 +PINATTR PinName SW +PINATTR SpiceOrder 31 +PIN 208 336 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -48 -400 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 23 +PIN -144 -400 TOP 8 +PINATTR PinName EN/UVLO +PINATTR SpiceOrder 24 +PIN -208 -336 LEFT 8 +PINATTR PinName OVLO +PINATTR SpiceOrder 25 +PIN 144 -400 TOP 8 +PINATTR PinName IVINN +PINATTR SpiceOrder 26 +PIN 48 -400 TOP 8 +PINATTR PinName IVINP +PINATTR SpiceOrder 27 +PIN -208 144 LEFT 8 +PINATTR PinName IVINCOMP +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTM8008.asy b/spice/copy/sym/PowerProducts/LTM8008.asy new file mode 100755 index 0000000..5dbc0ad --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8008.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -352 160 352 +TEXT 0 0 Center 2 LT +WINDOW 0 3 -193 Center 2 +WINDOW 3 -3 192 Center 2 +SYMATTR Value LTM8008 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8008.sub +SYMATTR Value2 LTM8008 +SYMATTR Description 72Vin, 6 Output DC/DC µModule Regulator +PIN -160 96 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 6 +PIN -160 288 LEFT 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 11 +PIN -160 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN -160 -96 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 160 -288 RIGHT 8 +PINATTR PinName SPV +PINATTR SpiceOrder 2 +PIN 0 -352 TOP 8 +PINATTR PinName SW +PINATTR SpiceOrder 7 +PIN 0 352 BOTTOM 8 +PINATTR PinName INTVcc +PINATTR SpiceOrder 8 +PIN -160 -192 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 9 +PIN -160 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 10 +PIN -160 192 LEFT 8 +PINATTR PinName Vc +PINATTR SpiceOrder 1 +PIN 160 -192 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 17 +PIN 160 -96 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 13 +PIN 160 0 RIGHT 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 14 +PIN 160 96 RIGHT 8 +PINATTR PinName Vout4 +PINATTR SpiceOrder 15 +PIN 160 192 RIGHT 8 +PINATTR PinName Vout5 +PINATTR SpiceOrder 16 +PIN 160 288 RIGHT 8 +PINATTR PinName Vout6 +PINATTR SpiceOrder 18 diff --git a/spice/copy/sym/PowerProducts/LTM8020.asy b/spice/copy/sym/PowerProducts/LTM8020.asy new file mode 100755 index 0000000..6d52ae9 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8020.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTM8020 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8020.sub +SYMATTR Value2 LTM8020 +SYMATTR Description 200mA, 36V DC/DC µModule +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 144 64 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 5 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTM8021.asy b/spice/copy/sym/PowerProducts/LTM8021.asy new file mode 100755 index 0000000..ba2db3e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8021.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTM8021 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8021.sub +SYMATTR Value2 LTM8021 +SYMATTR Description 500mA, 40V DC/DC µModule +PIN 0 -128 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 64 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 144 64 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 5 +PIN 144 -64 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/PowerProducts/LTM8022.asy b/spice/copy/sym/PowerProducts/LTM8022.asy new file mode 100755 index 0000000..7e31f35 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8022.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM8022 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8022.sub +SYMATTR Value2 LTM8022 +SYMATTR Description 1A, 36V DC/DC µModule +PIN -144 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 6 +PIN 144 32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 7 +PIN 144 -32 RIGHT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 8 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTM8023.asy b/spice/copy/sym/PowerProducts/LTM8023.asy new file mode 100755 index 0000000..6ddf5aa --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8023.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM8023 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8023.sub +SYMATTR Value2 LTM8023 +SYMATTR Description 2A, 36V DC/DC µModule +PIN -144 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 6 +PIN 144 32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 7 +PIN 144 -32 RIGHT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 8 +PIN 144 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTM8024.asy b/spice/copy/sym/PowerProducts/LTM8024.asy new file mode 100755 index 0000000..939c0b6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8024.asy @@ -0,0 +1,74 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -448 144 432 +TEXT 0 1 Center 2 LT +WINDOW 0 0 -143 Center 2 +WINDOW 3 0 145 Center 2 +SYMATTR Value LTM8024 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8024.sub +SYMATTR Value2 LTM8024 +SYMATTR Description Dual 40V, 3A Step-Down Silent Switcher µModule Regulator +PIN -144 384 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 1 +PIN 0 432 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -144 -192 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 3 +PIN -64 -448 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 4 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 5 +PIN -144 -96 LEFT 8 +PINATTR PinName Aux1 +PINATTR SpiceOrder 6 +PIN 64 -448 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Aux2 +PINATTR SpiceOrder 10 +PIN -144 -384 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 11 +PIN 144 -384 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 12 +PIN -144 -288 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 14 +PIN 144 -288 RIGHT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 15 +PIN -144 288 LEFT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 16 +PIN 144 288 RIGHT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 17 +PIN 144 384 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 26 +PIN -144 96 LEFT 8 +PINATTR PinName Share1 +PINATTR SpiceOrder 27 +PIN -144 0 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 28 +PIN -144 192 LEFT 8 +PINATTR PinName TRSS1 +PINATTR SpiceOrder 29 +PIN 144 192 RIGHT 8 +PINATTR PinName TRSS2 +PINATTR SpiceOrder 30 +PIN 144 0 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 31 +PIN 144 96 RIGHT 8 +PINATTR PinName Share2 +PINATTR SpiceOrder 32 diff --git a/spice/copy/sym/PowerProducts/LTM8025.asy b/spice/copy/sym/PowerProducts/LTM8025.asy new file mode 100755 index 0000000..fd53b33 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8025.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -176 128 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTM8025 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8025.sub +SYMATTR Value2 LTM8025 +SYMATTR Description 36V, 3A Step-Down µModule Converter +PIN 128 -128 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 1 +PIN 128 32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN 128 -48 RIGHT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -128 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 128 112 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 8 +PIN -128 112 LEFT 8 +PINATTR PinName Share +PINATTR SpiceOrder 9 +PIN -128 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8026.asy b/spice/copy/sym/PowerProducts/LTM8026.asy new file mode 100755 index 0000000..4247420 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8026.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -256 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM8026 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8026.sub +SYMATTR Value2 LTM8026 +SYMATTR Description 36Vin. 5A CVCC Step-Down µModule Regulator +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -192 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 2 +PIN -144 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName CTL_T +PINATTR SpiceOrder 4 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN -144 0 LEFT 8 +PINATTR PinName CTL_I +PINATTR SpiceOrder 6 +PIN -144 192 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 144 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 14 +PIN 144 192 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTM8027.asy b/spice/copy/sym/PowerProducts/LTM8027.asy new file mode 100755 index 0000000..86d15ff --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8027.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -192 128 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM8027 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8027.sub +SYMATTR Value2 LTM8027 +SYMATTR Description 60V, 4A DC/DC µModule Regulator +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 -144 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 3 +PIN 128 48 RIGHT 8 +PINATTR PinName Bias2 +PINATTR SpiceOrder 4 +PIN -128 144 LEFT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName Bias1 +PINATTR SpiceOrder 6 +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 7 +PIN -128 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 8 +PIN 128 144 RIGHT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 9 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTM8028.asy b/spice/copy/sym/PowerProducts/LTM8028.asy new file mode 100755 index 0000000..4250fbe --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8028.asy @@ -0,0 +1,56 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -352 144 352 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM8028 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8028.sub +SYMATTR Value2 LTM8028 +SYMATTR Description 36Vin. UltraFast, Low Ouput Noise 5A µModule Regulator +PIN 144 -288 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 144 -96 RIGHT 8 +PINATTR PinName BKV +PINATTR SpiceOrder 2 +PIN 0 352 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -144 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName Vo0 +PINATTR SpiceOrder 5 +PIN -144 96 LEFT 8 +PINATTR PinName Vo1 +PINATTR SpiceOrder 6 +PIN -144 192 LEFT 8 +PINATTR PinName Vo2 +PINATTR SpiceOrder 7 +PIN 144 192 RIGHT 8 +PINATTR PinName MARGA +PINATTR SpiceOrder 8 +PIN 144 -192 RIGHT 8 +PINATTR PinName Sensep +PINATTR SpiceOrder 9 +PIN -144 -96 LEFT 8 +PINATTR PinName VoB +PINATTR SpiceOrder 10 +PIN 144 0 RIGHT 8 +PINATTR PinName Imax +PINATTR SpiceOrder 11 +PIN -144 288 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 12 +PIN 144 288 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 13 +PIN -144 -192 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 14 +PIN 144 96 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 15 diff --git a/spice/copy/sym/PowerProducts/LTM8029.asy b/spice/copy/sym/PowerProducts/LTM8029.asy new file mode 100755 index 0000000..37d3ed1 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8029.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -176 128 176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM8029 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8029.sub +SYMATTR Value2 LTM8029 +SYMATTR Description 36V, 600mA Step-Down µModule Converter with 5µA Quiescent Current +PIN 128 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 128 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 -48 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 3 +PIN -128 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 128 144 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 128 -144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 8 +PIN -128 48 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 9 +PIN -128 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTM8031.asy b/spice/copy/sym/PowerProducts/LTM8031.asy new file mode 100755 index 0000000..7293fb3 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8031.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM8031 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8031.sub +SYMATTR Value2 LTM8031 +SYMATTR Description Ultralow Noise EMC 36V, 1A DC/DC µModule Regulator +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 96 LEFT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName Share +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 6 +PIN -144 -32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 7 +PIN 144 32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 8 +PIN 144 -96 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 9 +PIN 144 -32 RIGHT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 10 +PIN 64 -160 TOP 8 +PINATTR PinName Fin +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8032.asy b/spice/copy/sym/PowerProducts/LTM8032.asy new file mode 100755 index 0000000..503e2fc --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8032.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -160 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM8032 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8032.sub +SYMATTR Value2 LTM8032 +SYMATTR Description Ultralow Noise EMC Compliant 36V, 2A DC/DC µModule +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -64 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 96 LEFT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName Share +PINATTR SpiceOrder 4 +PIN -144 -96 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 6 +PIN -144 -32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 7 +PIN 144 32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 8 +PIN 144 -96 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 9 +PIN 144 -32 RIGHT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 10 +PIN 64 -160 TOP 8 +PINATTR PinName Fin +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8033.asy b/spice/copy/sym/PowerProducts/LTM8033.asy new file mode 100755 index 0000000..a2b5891 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8033.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -176 128 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTM8033 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8033.sub +SYMATTR Value2 LTM8033 +SYMATTR Description Ultralow Noise EMC 36Vin, 3A DC/DC µModule Regulator +PIN 128 -128 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 1 +PIN 128 32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN 128 -48 RIGHT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 3 +PIN 48 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -128 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -48 -176 TOP 8 +PINATTR PinName FIN +PINATTR SpiceOrder 6 +PIN -128 -48 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 128 112 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 8 +PIN -128 112 LEFT 8 +PINATTR PinName Share +PINATTR SpiceOrder 9 +PIN -128 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8040.asy b/spice/copy/sym/PowerProducts/LTM8040.asy new file mode 100755 index 0000000..f1d1ff6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8040.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM8040 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8040.sub +SYMATTR Value2 LTM8040 +SYMATTR Description 36V, 1A µModule LED Driver and Current Source +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN -144 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN -144 -32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 144 32 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 5 +PIN 144 -32 RIGHT 8 +PINATTR PinName LPWR +PINATTR SpiceOrder 6 +PIN 144 -96 RIGHT 8 +PINATTR PinName LEDA +PINATTR SpiceOrder 7 +PIN -144 96 LEFT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 8 +PIN -144 32 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTM8042-1.asy b/spice/copy/sym/PowerProducts/LTM8042-1.asy new file mode 100755 index 0000000..b499aee --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8042-1.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM8042-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8042-1.sub +SYMATTR Value2 LTM8042-1 +SYMATTR Description µModule Boost LED Driver and Current Source +PIN -176 -160 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -176 -32 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 2 +PIN -176 -96 LEFT 8 +PINATTR PinName BSTIN/BKLED- +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 176 160 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN 176 96 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 6 +PIN -176 32 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 7 +PIN -176 160 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 8 +PIN -176 96 LEFT 8 +PINATTR PinName TGEN +PINATTR SpiceOrder 11 +PIN 176 -32 RIGHT 8 +PINATTR PinName LED+ +PINATTR SpiceOrder 12 +PIN 176 -160 RIGHT 8 +PINATTR PinName BSTOUT/BKIN +PINATTR SpiceOrder 13 +PIN 176 -96 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 14 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTM8042.asy b/spice/copy/sym/PowerProducts/LTM8042.asy new file mode 100755 index 0000000..731a09f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8042.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTM8042 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8042.sub +SYMATTR Value2 LTM8042 +SYMATTR Description µModule Boost LED Driver and Current Source +PIN -176 -160 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -176 -32 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 2 +PIN -176 -96 LEFT 8 +PINATTR PinName BSTIN/BKLED- +PINATTR SpiceOrder 3 +PIN 176 32 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN 176 160 RIGHT 8 +PINATTR PinName SYNC +PINATTR SpiceOrder 5 +PIN 176 96 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 6 +PIN -176 32 LEFT 8 +PINATTR PinName PWM +PINATTR SpiceOrder 7 +PIN -176 160 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 8 +PIN -176 96 LEFT 8 +PINATTR PinName TGEN +PINATTR SpiceOrder 11 +PIN 176 -32 RIGHT 8 +PINATTR PinName LED+ +PINATTR SpiceOrder 12 +PIN 176 -160 RIGHT 8 +PINATTR PinName BSTOUT/BKIN +PINATTR SpiceOrder 13 +PIN 176 -96 RIGHT 8 +PINATTR PinName TG +PINATTR SpiceOrder 14 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 diff --git a/spice/copy/sym/PowerProducts/LTM8045.asy b/spice/copy/sym/PowerProducts/LTM8045.asy new file mode 100755 index 0000000..93634a8 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8045.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTM8045 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8045.sub +SYMATTR Value2 LTM8045 +SYMATTR Description Inverting or SEPIC µModule with Up to 700mA Output Current +PIN 144 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 144 0 RIGHT 8 +PINATTR PinName Vout+ +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN 144 -80 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 4 +PIN -144 -80 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 5 +PIN -144 80 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 6 +PIN -144 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 7 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/PowerProducts/LTM8046.asy b/spice/copy/sym/PowerProducts/LTM8046.asy new file mode 100755 index 0000000..9a6311c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8046.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM8046 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8046.sub +SYMATTR Value2 LTM8046 +SYMATTR Description 3.1Vin to 32Vin, 2kVAC Isolated DC/DC µModule Converter +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -64 RIGHT 8 +PINATTR PinName Vout+ +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 3 +PIN -160 144 LEFT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTM8047.asy b/spice/copy/sym/PowerProducts/LTM8047.asy new file mode 100755 index 0000000..2dab86b --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8047.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM8047 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8047.sub +SYMATTR Value2 LTM8047 +SYMATTR Description 3.1Vin to 32Vin Isolated µModule DC/DC Converter +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -64 RIGHT 8 +PINATTR PinName Vout+ +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 3 +PIN -160 144 LEFT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 4 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTM8047A.asy b/spice/copy/sym/PowerProducts/LTM8047A.asy new file mode 100755 index 0000000..3b1b1ea --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8047A.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM8047A +SYMATTR Prefix X +SYMATTR SpiceModel LTM8047.sub +SYMATTR Value2 LTM8047 +SYMATTR Description 3.1Vin to 32Vin Isolated µModule DC/DC Converter +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -64 RIGHT 8 +PINATTR PinName Vout+ +PINATTR SpiceOrder 2 +PIN 160 64 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 3 +PIN -160 144 LEFT 8 +PINATTR PinName Adj +PINATTR SpiceOrder 4 +PIN 0 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN -160 48 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTM8048.asy b/spice/copy/sym/PowerProducts/LTM8048.asy new file mode 100755 index 0000000..1bc1941 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8048.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM8048 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8048.sub +SYMATTR Value2 LTM8048 +SYMATTR Description 3.1Vin to 32Vin Isolated µModule DC/DC Converter with LDO Post Regulator +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -192 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 2 +PIN 160 192 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 3 +PIN -160 192 LEFT 8 +PINATTR PinName Adj1 +PINATTR SpiceOrder 4 +PIN -160 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN -160 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 9 +PIN 160 -96 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 10 +PIN 160 96 RIGHT 8 +PINATTR PinName Adj2 +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8048A.asy b/spice/copy/sym/PowerProducts/LTM8048A.asy new file mode 100755 index 0000000..a172467 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8048A.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM8048A +SYMATTR Prefix X +SYMATTR SpiceModel LTM8048.sub +SYMATTR Value2 LTM8048 +SYMATTR Description 3.1Vin to 32Vin Isolated µModule DC/DC Converter with LDO Post Regulator +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -192 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 2 +PIN 160 192 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 3 +PIN -160 192 LEFT 8 +PINATTR PinName Adj1 +PINATTR SpiceOrder 4 +PIN -160 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN -160 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 9 +PIN 160 -96 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 10 +PIN 160 96 RIGHT 8 +PINATTR PinName Adj2 +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8049.asy b/spice/copy/sym/PowerProducts/LTM8049.asy new file mode 100755 index 0000000..2ab63df --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8049.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -384 176 432 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTM8049 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8049.sub +SYMATTR Value2 LTM8049 +SYMATTR Description Dual SEPIC or Inverting µModule DC/DC Converter +PIN 176 -176 RIGHT 8 +PINATTR PinName FBx1 +PINATTR SpiceOrder 6 +PIN 176 -256 RIGHT 8 +PINATTR PinName Vout1- +PINATTR SpiceOrder 24 +PIN 64 -384 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 11 +PIN 176 -336 RIGHT 8 +PINATTR PinName Vout1+ +PINATTR SpiceOrder 1 +PIN -176 -336 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 22 +PIN -176 -176 LEFT 8 +PINATTR PinName Rt1 +PINATTR SpiceOrder 21 +PIN -176 -256 LEFT 8 +PINATTR PinName SS1 +PINATTR SpiceOrder 20 +PIN 176 -96 RIGHT 8 +PINATTR PinName Share1 +PINATTR SpiceOrder 5 +PIN 0 432 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 25 +PIN -176 -96 LEFT 8 +PINATTR PinName Sync1 +PINATTR SpiceOrder 19 +PIN -176 64 LEFT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 15 +PIN -176 224 LEFT 8 +PINATTR PinName Rt2 +PINATTR SpiceOrder 16 +PIN -176 144 LEFT 8 +PINATTR PinName SS2 +PINATTR SpiceOrder 17 +PIN -176 304 LEFT 8 +PINATTR PinName Sync2 +PINATTR SpiceOrder 18 +PIN 176 224 RIGHT 8 +PINATTR PinName FBx2 +PINATTR SpiceOrder 7 +PIN 176 144 RIGHT 8 +PINATTR PinName Vout2- +PINATTR SpiceOrder 28 +PIN 176 64 RIGHT 8 +PINATTR PinName Vout2+ +PINATTR SpiceOrder 27 +PIN 176 304 RIGHT 8 +PINATTR PinName Share2 +PINATTR SpiceOrder 8 +PIN -64 -384 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN -176 -16 LEFT 8 +PINATTR PinName CLKout1 +PINATTR SpiceOrder 23 +PIN -176 384 LEFT 8 +PINATTR PinName CLKout2 +PINATTR SpiceOrder 14 +PIN 176 -16 RIGHT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 3 +PIN 176 384 RIGHT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTM8050.asy b/spice/copy/sym/PowerProducts/LTM8050.asy new file mode 100755 index 0000000..4c42697 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8050.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -176 128 160 +TEXT 0 -7 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTM8050 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8050.sub +SYMATTR Value2 LTM8050 +SYMATTR Description 58V, 2A Step-Down µModule Regulator +PIN 128 -128 RIGHT 8 +PINATTR PinName BIAS +PINATTR SpiceOrder 1 +PIN 128 32 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN 128 -48 RIGHT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -128 -128 LEFT 8 +PINATTR PinName Run/SS +PINATTR SpiceOrder 5 +PIN -128 -48 LEFT 8 +PINATTR PinName Pgood +PINATTR SpiceOrder 7 +PIN 128 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 8 +PIN -128 112 LEFT 8 +PINATTR PinName Share +PINATTR SpiceOrder 9 +PIN -128 32 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 10 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8051.asy b/spice/copy/sym/PowerProducts/LTM8051.asy new file mode 100755 index 0000000..3a6bcd8 Binary files /dev/null and b/spice/copy/sym/PowerProducts/LTM8051.asy differ diff --git a/spice/copy/sym/PowerProducts/LTM8052.asy b/spice/copy/sym/PowerProducts/LTM8052.asy new file mode 100755 index 0000000..1e5ce01 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8052.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -256 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM8052 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8052.sub +SYMATTR Value2 LTM8052 +SYMATTR Description 36Vin. 5A, 2-Quadrant CVCC Step-Down µModule Regulator +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -192 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 2 +PIN -144 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName CTL_T +PINATTR SpiceOrder 4 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN -144 0 LEFT 8 +PINATTR PinName CTL_I +PINATTR SpiceOrder 6 +PIN -144 192 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 144 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 14 +PIN 144 192 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTM8052A.asy b/spice/copy/sym/PowerProducts/LTM8052A.asy new file mode 100755 index 0000000..731610e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8052A.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -256 144 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM8052A +SYMATTR Prefix X +SYMATTR SpiceModel LTM8052A.sub +SYMATTR Value2 LTM8052A +SYMATTR Description 36Vin. 5A, 2-Quadrant CVCC Step-Down µModule Regulator +PIN 0 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -144 -192 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 2 +PIN -144 -96 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName CTL_T +PINATTR SpiceOrder 4 +PIN 144 -192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN -144 0 LEFT 8 +PINATTR PinName CTL_I +PINATTR SpiceOrder 6 +PIN -144 192 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 144 0 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 10 +PIN 144 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 14 +PIN 144 192 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN 0 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/LTM8053.asy b/spice/copy/sym/PowerProducts/LTM8053.asy new file mode 100755 index 0000000..ca705f2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8053.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -176 160 161 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -40 Center 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTM8053 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8053.sub +SYMATTR Value2 LTM8053 +SYMATTR Description 40Vin, 3.5A/6A Step-Down µModule Regulator +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 2 +PIN 160 48 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 3 +PIN -160 48 LEFT 8 +PINATTR PinName Share +PINATTR SpiceOrder 4 +PIN -160 112 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 5 +PIN 160 112 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 7 +PIN 160 -80 RIGHT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 8 +PIN -160 -80 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 10 +PIN -160 -16 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 11 +PIN -160 -144 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 12 +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 13 +PIN 160 -16 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/PowerProducts/LTM8054.asy b/spice/copy/sym/PowerProducts/LTM8054.asy new file mode 100755 index 0000000..6b6573f --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8054.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 208 448 -208 -448 +TEXT 0 0 Center 2 LT +WINDOW 3 0 224 Center 2 +WINDOW 0 0 -224 Center 2 +SYMATTR Value LTM8054 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8054.sub +SYMATTR Value2 LTM8054 +SYMATTR Description 36Vin, 5.4A Buck-Boost µModule Regulator +PIN -208 96 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 1 +PIN -208 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN -208 288 LEFT 8 +PINATTR PinName LL +PINATTR SpiceOrder 4 +PIN 208 0 RIGHT 8 +PINATTR PinName IOUTmon +PINATTR SpiceOrder 7 +PIN 208 -96 RIGHT 8 +PINATTR PinName IINmon +PINATTR SpiceOrder 8 +PIN -208 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 9 +PIN -208 -192 LEFT 8 +PINATTR PinName Iin +PINATTR SpiceOrder 10 +PIN -208 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -208 -384 LEFT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 12 +PIN 208 -384 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 25 +PIN 208 -288 RIGHT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 26 +PIN 208 384 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 30 +PIN -208 192 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 32 +PIN 208 192 RIGHT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 33 +PIN 208 288 RIGHT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 34 +PIN -208 384 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 35 +PIN 208 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 36 +PIN 208 -192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 37 diff --git a/spice/copy/sym/PowerProducts/LTM8055-1.asy b/spice/copy/sym/PowerProducts/LTM8055-1.asy new file mode 100755 index 0000000..5b1f08c --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8055-1.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 208 448 -208 -448 +TEXT 0 0 Center 2 LT +WINDOW 3 0 224 Center 2 +WINDOW 0 0 -224 Center 2 +SYMATTR Value LTM8055-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8055-1.sub +SYMATTR Value2 LTM8055-1 +SYMATTR Description 36Vin, 8.5A Buck-Boost µModule Regulator +PIN -208 96 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 1 +PIN -208 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN -208 288 LEFT 8 +PINATTR PinName LL +PINATTR SpiceOrder 4 +PIN 208 0 RIGHT 8 +PINATTR PinName IOUTmon +PINATTR SpiceOrder 7 +PIN 208 -96 RIGHT 8 +PINATTR PinName IINmon +PINATTR SpiceOrder 8 +PIN -208 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 9 +PIN -208 -192 LEFT 8 +PINATTR PinName Iin +PINATTR SpiceOrder 10 +PIN -208 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -208 -384 LEFT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 12 +PIN 208 -384 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 25 +PIN 208 -288 RIGHT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 26 +PIN 208 384 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 30 +PIN -208 192 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 32 +PIN 208 192 RIGHT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 33 +PIN 208 288 RIGHT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 34 +PIN -208 384 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 35 +PIN 208 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 36 +PIN 208 -192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 37 diff --git a/spice/copy/sym/PowerProducts/LTM8055.asy b/spice/copy/sym/PowerProducts/LTM8055.asy new file mode 100755 index 0000000..e3c99b6 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8055.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 208 448 -208 -448 +TEXT 0 0 Center 2 LT +WINDOW 3 0 224 Center 2 +WINDOW 0 0 -224 Center 2 +SYMATTR Value LTM8055 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8055.sub +SYMATTR Value2 LTM8055 +SYMATTR Description 36Vin, 8.5A Buck-Boost µModule Regulator +PIN -208 96 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 1 +PIN -208 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN -208 288 LEFT 8 +PINATTR PinName LL +PINATTR SpiceOrder 4 +PIN 208 0 RIGHT 8 +PINATTR PinName IOUTmon +PINATTR SpiceOrder 7 +PIN 208 -96 RIGHT 8 +PINATTR PinName IINmon +PINATTR SpiceOrder 8 +PIN -208 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 9 +PIN -208 -192 LEFT 8 +PINATTR PinName Iin +PINATTR SpiceOrder 10 +PIN -208 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -208 -384 LEFT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 12 +PIN 208 -384 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 25 +PIN 208 -288 RIGHT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 26 +PIN 208 384 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 30 +PIN -208 192 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 32 +PIN 208 192 RIGHT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 33 +PIN 208 288 RIGHT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 34 +PIN -208 384 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 35 +PIN 208 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 36 +PIN 208 -192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 37 diff --git a/spice/copy/sym/PowerProducts/LTM8056.asy b/spice/copy/sym/PowerProducts/LTM8056.asy new file mode 100755 index 0000000..37ce15d --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8056.asy @@ -0,0 +1,65 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 208 448 -208 -448 +TEXT 0 0 Center 2 LT +WINDOW 3 0 224 Center 2 +WINDOW 0 0 -224 Center 2 +SYMATTR Value LTM8056 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8056.sub +SYMATTR Value2 LTM8056 +SYMATTR Description 58Vin, 48Vout Buck-Boost µModule Regulator +PIN -208 96 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 1 +PIN -208 0 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 2 +PIN -208 288 LEFT 8 +PINATTR PinName LL +PINATTR SpiceOrder 4 +PIN 208 0 RIGHT 8 +PINATTR PinName IOUTmon +PINATTR SpiceOrder 7 +PIN 208 -96 RIGHT 8 +PINATTR PinName IINmon +PINATTR SpiceOrder 8 +PIN -208 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 9 +PIN -208 -192 LEFT 8 +PINATTR PinName Iin +PINATTR SpiceOrder 10 +PIN -208 -288 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 11 +PIN -208 -384 LEFT 8 +PINATTR PinName SVin +PINATTR SpiceOrder 12 +PIN 208 -384 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 25 +PIN 208 -288 RIGHT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 26 +PIN 208 384 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 30 +PIN -208 192 LEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 32 +PIN 208 192 RIGHT 8 +PINATTR PinName CLKout +PINATTR SpiceOrder 33 +PIN 208 288 RIGHT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 34 +PIN -208 384 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 35 +PIN 208 96 RIGHT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 36 +PIN 208 -192 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 37 diff --git a/spice/copy/sym/PowerProducts/LTM8057.asy b/spice/copy/sym/PowerProducts/LTM8057.asy new file mode 100755 index 0000000..5b60a3a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8057.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -192 160 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM8057 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8057.sub +SYMATTR Value2 LTM8057 +SYMATTR Description 3.1Vin to 31Vin Isolated µModule DC/DC Converter +PIN 160 144 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -144 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 2 +PIN 160 -48 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 3 +PIN 160 48 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 4 +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -160 48 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -48 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN -160 144 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/PowerProducts/LTM8058.asy b/spice/copy/sym/PowerProducts/LTM8058.asy new file mode 100755 index 0000000..5bab529 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8058.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -224 160 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM8058 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8058.sub +SYMATTR Value2 LTM8058 +SYMATTR Description 3.1Vin to 32Vin Isolated µModule DC/DC Converter with LDO Post Regulator +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 160 -192 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 2 +PIN 160 192 RIGHT 8 +PINATTR PinName Vout- +PINATTR SpiceOrder 3 +PIN -160 192 LEFT 8 +PINATTR PinName Adj1 +PINATTR SpiceOrder 4 +PIN -160 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 6 +PIN -160 -96 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 7 +PIN -160 96 LEFT 8 +PINATTR PinName SS +PINATTR SpiceOrder 8 +PIN 160 0 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 9 +PIN 160 -96 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 10 +PIN 160 96 RIGHT 8 +PINATTR PinName Adj2 +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8060.asy b/spice/copy/sym/PowerProducts/LTM8060.asy new file mode 100755 index 0000000..b81cd12 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8060.asy @@ -0,0 +1,119 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -800 240 800 +TEXT 1 -1 Center 2 LT +WINDOW 0 1 -145 Center 2 +WINDOW 3 0 142 Center 2 +SYMATTR Value LTM8060 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8060.sub +SYMATTR Value2 LTM8060 +SYMATTR Description Quad 40V, 3A Step-Down Silent Switcher uModule Regulator +PIN -144 -800 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 1 +PIN -16 -800 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 2 +PIN 112 -800 TOP 8 +PINATTR PinName Vin34 +PINATTR SpiceOrder 3 +PIN -240 -736 LEFT 8 +PINATTR PinName Run1 +PINATTR SpiceOrder 4 +PIN 240 -736 RIGHT 8 +PINATTR PinName Run2 +PINATTR SpiceOrder 5 +PIN -240 32 LEFT 8 +PINATTR PinName Run3 +PINATTR SpiceOrder 6 +PIN 240 32 RIGHT 8 +PINATTR PinName Run4 +PINATTR SpiceOrder 7 +PIN -240 -640 LEFT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 8 +PIN 240 -640 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 9 +PIN -240 128 LEFT 8 +PINATTR PinName Vout3 +PINATTR SpiceOrder 10 +PIN 240 128 RIGHT 8 +PINATTR PinName Vout4 +PINATTR SpiceOrder 11 +PIN -240 -544 LEFT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 12 +PIN 240 -544 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 13 +PIN -240 224 LEFT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 14 +PIN 240 224 RIGHT 8 +PINATTR PinName FB4 +PINATTR SpiceOrder 15 +PIN -240 -160 LEFT 8 +PINATTR PinName PG1 +PINATTR SpiceOrder 16 +PIN 240 -160 RIGHT 8 +PINATTR PinName PG2 +PINATTR SpiceOrder 17 +PIN -240 608 LEFT 8 +PINATTR PinName PG3 +PINATTR SpiceOrder 18 +PIN 240 608 RIGHT 8 +PINATTR PinName PG4 +PINATTR SpiceOrder 19 +PIN -240 -64 LEFT 8 +PINATTR PinName Rt12 +PINATTR SpiceOrder 20 +PIN -240 704 LEFT 8 +PINATTR PinName Rt34 +PINATTR SpiceOrder 21 +PIN 240 -256 RIGHT 8 +PINATTR PinName Bias12 +PINATTR SpiceOrder 22 +PIN 240 512 RIGHT 8 +PINATTR PinName Bias34 +PINATTR SpiceOrder 23 +PIN -240 -352 LEFT 8 +PINATTR PinName TRSS1 +PINATTR SpiceOrder 24 +PIN 240 -352 RIGHT 8 +PINATTR PinName TRSS2 +PINATTR SpiceOrder 25 +PIN -240 416 LEFT 8 +PINATTR PinName TRSS3 +PINATTR SpiceOrder 26 +PIN 240 416 RIGHT 8 +PINATTR PinName TRSS4 +PINATTR SpiceOrder 27 +PIN -240 -448 LEFT 8 +PINATTR PinName Share1 +PINATTR SpiceOrder 28 +PIN 240 -448 RIGHT 8 +PINATTR PinName Share2 +PINATTR SpiceOrder 29 +PIN -240 320 LEFT 8 +PINATTR PinName Share3 +PINATTR SpiceOrder 30 +PIN 240 320 RIGHT 8 +PINATTR PinName Share4 +PINATTR SpiceOrder 31 +PIN -240 -256 LEFT 8 +PINATTR PinName Sync12 +PINATTR SpiceOrder 32 +PIN -240 512 LEFT 8 +PINATTR PinName Sync34 +PINATTR SpiceOrder 33 +PIN 240 -64 RIGHT 8 +PINATTR PinName CLKout12 +PINATTR SpiceOrder 34 +PIN 240 704 RIGHT 8 +PINATTR PinName CLKout34 +PINATTR SpiceOrder 35 +PIN 0 800 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 36 diff --git a/spice/copy/sym/PowerProducts/LTM8061-4.1.asy b/spice/copy/sym/PowerProducts/LTM8061-4.1.asy new file mode 100755 index 0000000..3d8c80a --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8061-4.1.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTM8061-4.1 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8061-4.1.sub +SYMATTR Value2 LTM8061-4.1 +SYMATTR Description 32V, 2A µModule Li-Ion/Polymer Battery Charger +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName VinC/CLP +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 144 LEFT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 -240 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN -144 -240 LEFT 8 +PINATTR PinName VinA +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 11 +PIN -144 240 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTM8061-4.2.asy b/spice/copy/sym/PowerProducts/LTM8061-4.2.asy new file mode 100755 index 0000000..5c81c13 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8061-4.2.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTM8061-4.2 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8061-4.2.sub +SYMATTR Value2 LTM8061-4.2 +SYMATTR Description 32V, 2A µModule Li-Ion/Polymer Battery Charger +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName VinC/CLP +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 144 LEFT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 -240 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN -144 -240 LEFT 8 +PINATTR PinName VinA +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 11 +PIN -144 240 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTM8061-8.2.asy b/spice/copy/sym/PowerProducts/LTM8061-8.2.asy new file mode 100755 index 0000000..7502fb0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8061-8.2.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTM8061-8.2 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8061-8.2.sub +SYMATTR Value2 LTM8061-8.2 +SYMATTR Description 32V, 2A µModule Li-Ion/Polymer Battery Charger +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName VinC/CLP +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 144 LEFT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 -240 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN -144 -240 LEFT 8 +PINATTR PinName VinA +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 11 +PIN -144 240 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTM8061-8.4.asy b/spice/copy/sym/PowerProducts/LTM8061-8.4.asy new file mode 100755 index 0000000..747a365 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8061-8.4.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTM8061-8.4 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8061-8.4.sub +SYMATTR Value2 LTM8061-8.4 +SYMATTR Description 32V, 2A µModule Li-Ion/Polymer Battery Charger +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName VinC/CLP +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 3 +PIN 144 -48 RIGHT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 144 LEFT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName RNG/SS +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 -240 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN -144 -240 LEFT 8 +PINATTR PinName VinA +PINATTR SpiceOrder 10 +PIN 144 -144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 11 +PIN -144 240 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTM8062.asy b/spice/copy/sym/PowerProducts/LTM8062.asy new file mode 100755 index 0000000..2358b51 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8062.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTM8062 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8062.sub +SYMATTR Value2 LTM8062 +SYMATTR Description 32 Vin, 2A µModule Power Tracking Battery Charger +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin_reg +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 3 +PIN 144 -240 RIGHT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN 144 -144 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 144 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 11 +PIN -144 -240 LEFT 8 +PINATTR PinName VinA +PINATTR SpiceOrder 12 +PIN -144 240 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTM8062A.asy b/spice/copy/sym/PowerProducts/LTM8062A.asy new file mode 100755 index 0000000..ea1c7c2 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8062A.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -287 144 288 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value LTM8062A +SYMATTR Prefix X +SYMATTR SpiceModel LTM8062.sub +SYMATTR Value2 LTM8062 +SYMATTR Description 32 Vin, 2A µModule Power Tracking Battery Charger +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Vin_reg +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 3 +PIN 144 -240 RIGHT 8 +PINATTR PinName _CHRG +PINATTR SpiceOrder 4 +PIN 144 -144 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 5 +PIN -144 144 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 6 +PIN 144 240 RIGHT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 7 +PIN 144 144 RIGHT 8 +PINATTR PinName NTC +PINATTR SpiceOrder 8 +PIN 144 48 RIGHT 8 +PINATTR PinName BAT +PINATTR SpiceOrder 9 +PIN 144 -48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 11 +PIN -144 -240 LEFT 8 +PINATTR PinName VinA +PINATTR SpiceOrder 12 +PIN -144 240 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/PowerProducts/LTM8063.asy b/spice/copy/sym/PowerProducts/LTM8063.asy new file mode 100755 index 0000000..602adf4 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8063.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -176 128 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM8063 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8063.sub +SYMATTR Value2 LTM8063 +SYMATTR Description 40Vin, 2A Silent Switcher µModule Regulator +PIN 128 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN 128 144 RIGHT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -128 48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 5 +PIN 128 -48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -128 144 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN 128 48 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN -128 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -128 -48 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 10 +PIN 0 192 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8064.asy b/spice/copy/sym/PowerProducts/LTM8064.asy new file mode 100755 index 0000000..b740530 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8064.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -304 144 304 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM8064 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8064.sub +SYMATTR Value2 LTM8064 +SYMATTR Description 58Vin, 6A CVCC Step-Down µModule Regulator +PIN 144 -240 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN 0 -304 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -144 -240 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 4 +PIN -144 -144 LEFT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 5 +PIN -144 144 LEFT 8 +PINATTR PinName PGood +PINATTR SpiceOrder 9 +PIN 144 -144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 11 +PIN 144 240 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 +PIN -144 48 LEFT 8 +PINATTR PinName CTRL2 +PINATTR SpiceOrder 13 +PIN -144 -48 LEFT 8 +PINATTR PinName CTRL1 +PINATTR SpiceOrder 14 +PIN 144 -48 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 15 +PIN 144 48 RIGHT 8 +PINATTR PinName Ioutmon +PINATTR SpiceOrder 19 +PIN -144 240 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 20 +PIN 144 144 RIGHT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 22 diff --git a/spice/copy/sym/PowerProducts/LTM8065.asy b/spice/copy/sym/PowerProducts/LTM8065.asy new file mode 100755 index 0000000..33caa86 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8065.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTM8065 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8065.sub +SYMATTR Value2 LTM8065 +SYMATTR Description 40Vin, 2.5A Silent Switcher µModule Regulator +PIN 144 -144 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 144 48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 144 -48 RIGHT 8 +PINATTR PinName Aux +PINATTR SpiceOrder 13 +PIN 0 -208 TOP 8 +PINATTR PinName Run +PINATTR SpiceOrder 14 +PIN -144 144 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 48 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 -48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 17 +PIN 48 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -48 208 BOTTOM 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM8067.asy b/spice/copy/sym/PowerProducts/LTM8067.asy new file mode 100755 index 0000000..f8868bb --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8067.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -144 112 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTM8067 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8067.sub +SYMATTR Value2 LTM8067 +SYMATTR Description 28Vin to 40Vin Isolated µModule DC/DC Converter +PIN -112 0 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 1 +PIN -112 -96 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -112 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 -96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 112 0 RIGHT 8 +PINATTR PinName Voutn +PINATTR SpiceOrder 2 +PIN 112 96 RIGHT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/PowerProducts/LTM8068.asy b/spice/copy/sym/PowerProducts/LTM8068.asy new file mode 100755 index 0000000..8fdb54e --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8068.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -240 112 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTM8068 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8068.sub +SYMATTR Value2 LTM8068 +SYMATTR Description 28Vin to 40Vin Isolated µModule DC/DC Converter with LDO Post Regulator +PIN -112 -96 LEFT 8 +PINATTR PinName RUN +PINATTR SpiceOrder 1 +PIN 112 192 RIGHT 8 +PINATTR PinName Voutn +PINATTR SpiceOrder 2 +PIN -112 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -112 192 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 -192 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 5 +PIN -112 96 LEFT 8 +PINATTR PinName Rref +PINATTR SpiceOrder 7 +PIN 112 -96 RIGHT 8 +PINATTR PinName Vout2 +PINATTR SpiceOrder 6 +PIN 112 0 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 8 +PIN 112 96 RIGHT 8 +PINATTR PinName BYP +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/PowerProducts/LTM8071.asy b/spice/copy/sym/PowerProducts/LTM8071.asy new file mode 100755 index 0000000..f75e476 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8071.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -208 144 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 -1 95 Center 2 +SYMATTR Value LTM8071 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8071.sub +SYMATTR Value2 LTM8071 +SYMATTR Description 60Vin, 5A Silent Switcher µModule Regulator +PIN 144 48 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN 144 -48 RIGHT 8 +PINATTR PinName Aux +PINATTR SpiceOrder 2 +PIN -144 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 144 -144 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN -48 -208 TOP 8 +PINATTR PinName Run +PINATTR SpiceOrder 14 +PIN -144 48 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -144 144 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -144 -48 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 17 +PIN -48 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN 48 -208 TOP 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 144 144 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 +PIN 48 208 BOTTOM 8 +PINATTR PinName Share +PINATTR SpiceOrder 30 diff --git a/spice/copy/sym/PowerProducts/LTM8073.asy b/spice/copy/sym/PowerProducts/LTM8073.asy new file mode 100755 index 0000000..16edacf --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8073.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -224 176 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTM8073 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8073.sub +SYMATTR Value2 LTM8073 +SYMATTR Description 60Vin, 3A Silent Switcher µModule Converter +PIN 176 0 RIGHT 8 +PINATTR PinName Bias +PINATTR SpiceOrder 1 +PIN 0 -224 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 176 160 RIGHT 8 +PINATTR PinName Share +PINATTR SpiceOrder 5 +PIN 176 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 176 -80 RIGHT 8 +PINATTR PinName Aux +PINATTR SpiceOrder 9 +PIN -176 -160 LEFT 8 +PINATTR PinName Run +PINATTR SpiceOrder 14 +PIN -176 80 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 15 +PIN -176 160 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 16 +PIN -176 0 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 17 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 18 +PIN -176 -80 LEFT 8 +PINATTR PinName PG +PINATTR SpiceOrder 19 +PIN 176 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/PowerProducts/LTM8074.asy b/spice/copy/sym/PowerProducts/LTM8074.asy new file mode 100755 index 0000000..40693d0 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM8074.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -240 144 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTM8074 +SYMATTR Prefix X +SYMATTR SpiceModel LTM8074.sub +SYMATTR Value2 LTM8074 +SYMATTR Description 40Vin, 1.2A Silent Switcher uModule Regulator +PIN 144 -192 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -144 192 LEFT 8 +PINATTR PinName Rt +PINATTR SpiceOrder 4 +PIN -144 0 LEFT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 5 +PIN 144 64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN -144 96 LEFT 8 +PINATTR PinName TR/SS +PINATTR SpiceOrder 7 +PIN 144 -64 RIGHT 8 +PINATTR PinName PG +PINATTR SpiceOrder 8 +PIN -144 -192 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 9 +PIN -144 -96 LEFT 8 +PINATTR PinName EN/UV +PINATTR SpiceOrder 10 +PIN 144 192 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/PowerProducts/LTM8078.asy b/spice/copy/sym/PowerProducts/LTM8078.asy new file mode 100755 index 0000000..44c80db Binary files /dev/null and b/spice/copy/sym/PowerProducts/LTM8078.asy differ diff --git a/spice/copy/sym/PowerProducts/LTM8083.asy b/spice/copy/sym/PowerProducts/LTM8083.asy new file mode 100755 index 0000000..b82c1ea Binary files /dev/null and b/spice/copy/sym/PowerProducts/LTM8083.asy differ diff --git a/spice/copy/sym/PowerProducts/LTM9100.asy b/spice/copy/sym/PowerProducts/LTM9100.asy new file mode 100755 index 0000000..53d8482 --- /dev/null +++ b/spice/copy/sym/PowerProducts/LTM9100.asy @@ -0,0 +1,84 @@ +Version 4 +SymbolType CELL +LINE Normal -288 192 -288 -160 +LINE Normal -256 192 -256 -160 +RECTANGLE Normal -400 -160 400 192 +TEXT 0 0 Center 2 LT +TEXT -270 17 VCenter 2 ISOLATION BARRIER +WINDOW 3 0 -41 Center 2 +WINDOW 0 0 41 Center 2 +WINDOW 123 0 96 Center 2 +SYMATTR Value LTM9100 +SYMATTR Value2 OVRTRY=1 UVRTRY=1 OCRTRY=0 +SYMATTR Prefix X +SYMATTR Description Anyside Isolated Switch Controller with I2C Command and Telemetry +SYMATTR ModelFile LTM9100.sub +PIN -400 112 LEFT 8 +PINATTR PinName _PG +PINATTR SpiceOrder 1 +PIN -400 64 LEFT 8 +PINATTR PinName _ALERT +PINATTR SpiceOrder 2 +PIN -400 16 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -400 -32 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 6 +PIN -400 -80 LEFT 8 +PINATTR PinName VL +PINATTR SpiceOrder 7 +PIN -400 -128 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 +PIN -400 160 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 288 -160 TOP 8 +PINATTR PinName _PG2 +PINATTR SpiceOrder 10 +PIN 192 -160 TOP 8 +PINATTR PinName _ALERT2 +PINATTR SpiceOrder 11 +PIN 96 -160 TOP 8 +PINATTR PinName EN2 +PINATTR SpiceOrder 12 +PIN 0 -160 TOP 8 +PINATTR PinName PGIO +PINATTR SpiceOrder 15 +PIN -96 -160 TOP 8 +PINATTR PinName VS +PINATTR SpiceOrder 16 +PIN -192 192 BOTTOM 8 +PINATTR PinName Vee +PINATTR SpiceOrder 17 +PIN 192 192 BOTTOM 8 +PINATTR PinName SS +PINATTR SpiceOrder 19 +PIN 0 192 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 20 +PIN -192 -160 TOP 8 +PINATTR PinName Vcc2 +PINATTR SpiceOrder 21 +PIN 400 160 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 22 +PIN 400 112 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 23 +PIN 400 64 RIGHT 8 +PINATTR PinName Drain +PINATTR SpiceOrder 24 +PIN 400 16 RIGHT 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 25 +PIN 400 -32 RIGHT 8 +PINATTR PinName OV +PINATTR SpiceOrder 26 +PIN 400 -80 RIGHT 8 +PINATTR PinName UVH +PINATTR SpiceOrder 27 +PIN 400 -128 RIGHT 8 +PINATTR PinName UVL +PINATTR SpiceOrder 28 diff --git a/spice/copy/sym/PowerProducts/RH117H.asy b/spice/copy/sym/PowerProducts/RH117H.asy new file mode 100755 index 0000000..d0a2ffd --- /dev/null +++ b/spice/copy/sym/PowerProducts/RH117H.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value RH117H +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 RH117H +SYMATTR Description Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/RH117K.asy b/spice/copy/sym/PowerProducts/RH117K.asy new file mode 100755 index 0000000..aa6185e --- /dev/null +++ b/spice/copy/sym/PowerProducts/RH117K.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -63 Bottom 2 +WINDOW 3 16 112 Left 2 +SYMATTR Value RH117K +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 RH117K +SYMATTR Description Positive Adjustable Regulator +PIN 0 96 BOTTOM 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/PowerProducts/RH3080.asy b/spice/copy/sym/PowerProducts/RH3080.asy new file mode 100755 index 0000000..96c8441 --- /dev/null +++ b/spice/copy/sym/PowerProducts/RH3080.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value RH3080 +SYMATTR Prefix X +SYMATTR SpiceModel LT3080.sub +SYMATTR Value2 LT3080 +SYMATTR Description Adjustable 1.1A Single Resistor Low Dropout Regulator +PIN 0 112 BOTTOM 8 +PINATTR PinName SET +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN -128 0 LEFT 8 +PINATTR PinName Vcntrl +PINATTR SpiceOrder 4 +PIN 0 -112 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/PowerProducts/RH6105.asy b/spice/copy/sym/PowerProducts/RH6105.asy new file mode 100755 index 0000000..af802ac --- /dev/null +++ b/spice/copy/sym/PowerProducts/RH6105.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -128 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value RH6105 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LT6105 +SYMATTR Description Precision, Extended Input Range Current Sense Amplifier +PIN 80 -128 TOP 8 +PINATTR PinName IN- +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 2 +PIN 0 128 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -80 -128 TOP 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/References/AD590.asy b/spice/copy/sym/References/AD590.asy new file mode 100755 index 0000000..2bf925f --- /dev/null +++ b/spice/copy/sym/References/AD590.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -64 -64 64 64 +TEXT 0 0 Center 2 ADI +WINDOW 0 16 -80 Left 2 +WINDOW 3 16 80 Left 2 +SYMATTR Value AD590 +SYMATTR Prefix X +SYMATTR SpiceModel ADR.lib +SYMATTR Value2 AD590 +SYMATTR Description 2-Terminal IC Temperature Transducer +PIN 0 -64 TOP 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN 0 64 BOTTOM 8 +PINATTR PinName V- +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/ADR225.asy b/spice/copy/sym/References/ADR225.asy new file mode 100755 index 0000000..c3a9805 --- /dev/null +++ b/spice/copy/sym/References/ADR225.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -80 112 80 +TEXT 0 0 Center 2 ADI +WINDOW 0 0 -80 Bottom 2 +WINDOW 3 12 93 Left 2 +SYMATTR Value ADR225 +SYMATTR Prefix X +SYMATTR SpiceModel ADR.lib +SYMATTR Value2 ADR225 +SYMATTR Description High Temperature, Low Drift, µPower 2.5V Reference +PIN -112 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 112 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/ADR4525.asy b/spice/copy/sym/References/ADR4525.asy new file mode 100755 index 0000000..6848ee9 --- /dev/null +++ b/spice/copy/sym/References/ADR4525.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -64 128 96 +TEXT 0 0 Center 2 ADI +WINDOW 0 -1 -42 Center 2 +WINDOW 3 -53 35 Left 2 +SYMATTR Value ADR4525 +SYMATTR Prefix X +SYMATTR SpiceModel ADR4525.sub +SYMATTR Value2 ADR4525 +PIN -128 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/ADR5040.asy b/spice/copy/sym/References/ADR5040.asy new file mode 100755 index 0000000..8a2c3f7 --- /dev/null +++ b/spice/copy/sym/References/ADR5040.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value ADR5040 +SYMATTR Prefix X +SYMATTR SpiceModel ADR5040.sub +SYMATTR Value2 ADR5040 +SYMATTR Description Precision, Micropower 2.048V Shunt Mode Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1004-1.2.asy b/spice/copy/sym/References/LT1004-1.2.asy new file mode 100755 index 0000000..1b0cf10 --- /dev/null +++ b/spice/copy/sym/References/LT1004-1.2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1004-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1004-1.2 +SYMATTR Description Micropower Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VOUT +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1004-2.5.asy b/spice/copy/sym/References/LT1004-2.5.asy new file mode 100755 index 0000000..e6a34e4 --- /dev/null +++ b/spice/copy/sym/References/LT1004-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1004-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1004-2.5 +SYMATTR Description Micropower Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VOUT +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1009.asy b/spice/copy/sym/References/LT1009.asy new file mode 100755 index 0000000..fbeac82 --- /dev/null +++ b/spice/copy/sym/References/LT1009.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +LINE Normal 32 0 11 0 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1009 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1009 +SYMATTR Description 2.5V Adjustable Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 +PIN 32 0 NONE 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT1021-10.asy b/spice/copy/sym/References/LT1021-10.asy new file mode 100755 index 0000000..3a2e9a4 --- /dev/null +++ b/spice/copy/sym/References/LT1021-10.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 96 80 -96 -80 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Bottom 2 +WINDOW 3 1 80 Top 2 +SYMATTR Value LT1021-10 +SYMATTR Prefix X +SYMATTR SpiceModel LT1021-10.sub +SYMATTR Value2 LT1021-10 +SYMATTR Description Precision 10V Reference +PIN -96 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 96 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 96 48 RIGHT 8 +PINATTR PinName TRIM +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/References/LT1021-5.asy b/spice/copy/sym/References/LT1021-5.asy new file mode 100755 index 0000000..2c42ad0 --- /dev/null +++ b/spice/copy/sym/References/LT1021-5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 96 80 -96 -80 +TEXT 0 0 Center 2 LT +WINDOW 0 -1 -80 Bottom 2 +WINDOW 3 0 80 Top 2 +SYMATTR Value LT1021-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1021-5.sub +SYMATTR Value2 LT1021-5 +SYMATTR Description Precision 5V Reference +PIN -96 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 96 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 96 48 RIGHT 8 +PINATTR PinName TRIM +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/References/LT1021-7.asy b/spice/copy/sym/References/LT1021-7.asy new file mode 100755 index 0000000..bf6e9d2 --- /dev/null +++ b/spice/copy/sym/References/LT1021-7.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 80 -112 -48 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Bottom 2 +WINDOW 3 16 96 Left 2 +SYMATTR Value LT1021-7 +SYMATTR Prefix X +SYMATTR SpiceModel LT1021-7.sub +SYMATTR Value2 LT1021-7 +SYMATTR Description Precision 7V Reference +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT1236-10.asy b/spice/copy/sym/References/LT1236-10.asy new file mode 100755 index 0000000..156d41a --- /dev/null +++ b/spice/copy/sym/References/LT1236-10.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -96 -96 96 96 +TEXT 0 -25 Center 2 LT +WINDOW 0 29 -107 Left 2 +WINDOW 3 0 24 Center 2 +SYMATTR Value LT1236-10 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LT1236-10 +SYMATTR Description Precision Reference, 10V Output +PIN 0 -96 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 96 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT1236-5.asy b/spice/copy/sym/References/LT1236-5.asy new file mode 100755 index 0000000..c267de6 --- /dev/null +++ b/spice/copy/sym/References/LT1236-5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -96 -96 96 96 +TEXT 0 -25 Center 2 LT +WINDOW 0 29 -107 Left 2 +WINDOW 3 0 24 Center 2 +SYMATTR Value LT1236-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4.lib +SYMATTR Value2 LT1236-5 +SYMATTR Description Precision Reference, 5V Output +PIN 0 -96 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 96 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 96 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT1389-1.25.asy b/spice/copy/sym/References/LT1389-1.25.asy new file mode 100755 index 0000000..292ae9e --- /dev/null +++ b/spice/copy/sym/References/LT1389-1.25.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1389-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel LT1389.lib +SYMATTR Value2 LT1389-1.25 +SYMATTR Description Nanopower Precision Shunt Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1389-2.5.asy b/spice/copy/sym/References/LT1389-2.5.asy new file mode 100755 index 0000000..291123f --- /dev/null +++ b/spice/copy/sym/References/LT1389-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1389-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1389.lib +SYMATTR Value2 LT1389-2.5 +SYMATTR Description Nanopower Precision Shunt Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1389-4.096.asy b/spice/copy/sym/References/LT1389-4.096.asy new file mode 100755 index 0000000..3cf0977 --- /dev/null +++ b/spice/copy/sym/References/LT1389-4.096.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1389-4.096 +SYMATTR Prefix X +SYMATTR SpiceModel LT1389.lib +SYMATTR Value2 LT1389-4.096 +SYMATTR Description Nanopower Precision Shunt Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1389-5.asy b/spice/copy/sym/References/LT1389-5.asy new file mode 100755 index 0000000..f4e47bd --- /dev/null +++ b/spice/copy/sym/References/LT1389-5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1389-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT1389.lib +SYMATTR Value2 LT1389-5 +SYMATTR Description Nanopower Precision Shunt Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1431.asy b/spice/copy/sym/References/LT1431.asy new file mode 100755 index 0000000..dce25bd --- /dev/null +++ b/spice/copy/sym/References/LT1431.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT1431 +SYMATTR Prefix X +SYMATTR SpiceModel LT1431.sub +SYMATTR Value2 LT1431 +SYMATTR Description Programmable Reference +PIN -128 -96 LEFT 8 +PINATTR PinName Coll +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName Comp +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName Rtop +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName GND-S +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName GND-F +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Rmid +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/References/LT1634-1.25.asy b/spice/copy/sym/References/LT1634-1.25.asy new file mode 100755 index 0000000..5005dc2 --- /dev/null +++ b/spice/copy/sym/References/LT1634-1.25.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1634-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1634-1.25 +SYMATTR Description µPrecision 1.25V Shunt Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1634-2.5.asy b/spice/copy/sym/References/LT1634-2.5.asy new file mode 100755 index 0000000..809b092 --- /dev/null +++ b/spice/copy/sym/References/LT1634-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1634-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1634-2.5 +SYMATTR Description µPrecision 2.5V Shunt Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1634-4.096.asy b/spice/copy/sym/References/LT1634-4.096.asy new file mode 100755 index 0000000..48217e7 --- /dev/null +++ b/spice/copy/sym/References/LT1634-4.096.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1634-4.096 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1634-4.096 +SYMATTR Description µPrecision 4.096V Shunt Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT1634-5.asy b/spice/copy/sym/References/LT1634-5.asy new file mode 100755 index 0000000..d74fa6e --- /dev/null +++ b/spice/copy/sym/References/LT1634-5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value LT1634-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1634-5 +SYMATTR Description µPrecision 5V Shunt Voltage Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT6650.asy b/spice/copy/sym/References/LT6650.asy new file mode 100755 index 0000000..ef7914f --- /dev/null +++ b/spice/copy/sym/References/LT6650.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -80 -80 112 80 +TEXT 0 -25 Center 2 LT +WINDOW 0 29 -91 Left 2 +WINDOW 3 0 24 Center 2 +SYMATTR Value LT6650 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT6650 +SYMATTR Description µPower, 400mV Reference with Rail-to-Rail Buffer Amplifier in SOT-23 +PIN 0 -80 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 112 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 112 32 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/References/LT6654-1.25.asy b/spice/copy/sym/References/LT6654-1.25.asy new file mode 100755 index 0000000..69c65a4 --- /dev/null +++ b/spice/copy/sym/References/LT6654-1.25.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6654-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel LT6654.lib +SYMATTR Value2 LT6654-1.25 +SYMATTR Description Precision Wide Supply High Output Drive Low Noise Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6654-2.048.asy b/spice/copy/sym/References/LT6654-2.048.asy new file mode 100755 index 0000000..4fd6e3d --- /dev/null +++ b/spice/copy/sym/References/LT6654-2.048.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6654-2.048 +SYMATTR Prefix X +SYMATTR SpiceModel LT6654.lib +SYMATTR Value2 LT6654-2.048 +SYMATTR Description Precision Wide Supply High Output Drive Low Noise Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6654-2.5.asy b/spice/copy/sym/References/LT6654-2.5.asy new file mode 100755 index 0000000..91c42bd --- /dev/null +++ b/spice/copy/sym/References/LT6654-2.5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6654-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6654.lib +SYMATTR Value2 LT6654-2.5 +SYMATTR Description Precision Wide Supply High Output Drive Low Noise Reference +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/References/LT6654-3.3.asy b/spice/copy/sym/References/LT6654-3.3.asy new file mode 100755 index 0000000..526657b --- /dev/null +++ b/spice/copy/sym/References/LT6654-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6654-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT6654.lib +SYMATTR Value2 LT6654-3.3 +SYMATTR Description Precision Wide Supply High Output Drive Low Noise Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6654-3.asy b/spice/copy/sym/References/LT6654-3.asy new file mode 100755 index 0000000..58af677 --- /dev/null +++ b/spice/copy/sym/References/LT6654-3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6654-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT6654.lib +SYMATTR Value2 LT6654-3 +SYMATTR Description Precision Wide Supply High Output Drive Low Noise Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6654-4.096.asy b/spice/copy/sym/References/LT6654-4.096.asy new file mode 100755 index 0000000..2c20893 --- /dev/null +++ b/spice/copy/sym/References/LT6654-4.096.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6654-4.096 +SYMATTR Prefix X +SYMATTR SpiceModel LT6654.lib +SYMATTR Value2 LT6654-4.096 +SYMATTR Description Precision Wide Supply High Output Drive Low Noise Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6654-5.asy b/spice/copy/sym/References/LT6654-5.asy new file mode 100755 index 0000000..024e3f4 --- /dev/null +++ b/spice/copy/sym/References/LT6654-5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6654-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6654.lib +SYMATTR Value2 LT6654-5 +SYMATTR Description Precision Wide Supply High Output Drive Low Noise Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6656-1.25.asy b/spice/copy/sym/References/LT6656-1.25.asy new file mode 100755 index 0000000..c03cc39 --- /dev/null +++ b/spice/copy/sym/References/LT6656-1.25.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6656-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel LT6656.lib +SYMATTR Value2 LT6656-1.25 +SYMATTR Description 1µA Precision Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6656-2.048.asy b/spice/copy/sym/References/LT6656-2.048.asy new file mode 100755 index 0000000..9822549 --- /dev/null +++ b/spice/copy/sym/References/LT6656-2.048.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6656-2.048 +SYMATTR Prefix X +SYMATTR SpiceModel LT6656.lib +SYMATTR Value2 LT6656-2.048 +SYMATTR Description 1µA Precision Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6656-2.5.asy b/spice/copy/sym/References/LT6656-2.5.asy new file mode 100755 index 0000000..3018ef7 --- /dev/null +++ b/spice/copy/sym/References/LT6656-2.5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6656-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6656.lib +SYMATTR Value2 LT6656-2.5 +SYMATTR Description 1µA Precision Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6656-3.3.asy b/spice/copy/sym/References/LT6656-3.3.asy new file mode 100755 index 0000000..a816464 --- /dev/null +++ b/spice/copy/sym/References/LT6656-3.3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6656-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT6656.lib +SYMATTR Value2 LT6656-3.3 +SYMATTR Description 1µA Precision Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6656-3.asy b/spice/copy/sym/References/LT6656-3.asy new file mode 100755 index 0000000..3a3c369 --- /dev/null +++ b/spice/copy/sym/References/LT6656-3.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6656-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT6656.lib +SYMATTR Value2 LT6656-3 +SYMATTR Description 1µA Precision Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6656-4.096.asy b/spice/copy/sym/References/LT6656-4.096.asy new file mode 100755 index 0000000..e07bdfd --- /dev/null +++ b/spice/copy/sym/References/LT6656-4.096.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6656-4.096 +SYMATTR Prefix X +SYMATTR SpiceModel LT6656.lib +SYMATTR Value2 LT6656-4.096 +SYMATTR Description 1µA Precision Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6656-5.asy b/spice/copy/sym/References/LT6656-5.asy new file mode 100755 index 0000000..8637c1e --- /dev/null +++ b/spice/copy/sym/References/LT6656-5.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -64 112 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LT6656-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6656.lib +SYMATTR Value2 LT6656-5 +SYMATTR Description 1µA Precision Series Voltage Reference +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/References/LT6657-1.25.asy b/spice/copy/sym/References/LT6657-1.25.asy new file mode 100755 index 0000000..b832dae --- /dev/null +++ b/spice/copy/sym/References/LT6657-1.25.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 1 31 Center 2 +SYMATTR Value LT6657-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel LT6657.lib +SYMATTR Value2 LT6657-1.25 +SYMATTR Description 1.5ppm/°C Drift, Low Noise, Buffered Reference +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/References/LT6657-2.5.asy b/spice/copy/sym/References/LT6657-2.5.asy new file mode 100755 index 0000000..5bcaede --- /dev/null +++ b/spice/copy/sym/References/LT6657-2.5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 1 31 Center 2 +SYMATTR Value LT6657-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6657.lib +SYMATTR Value2 LT6657-2.5 +SYMATTR Description 1.5ppm/°C Drift, Low Noise, Buffered Reference +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/References/LT6657-3.asy b/spice/copy/sym/References/LT6657-3.asy new file mode 100755 index 0000000..2d5a778 --- /dev/null +++ b/spice/copy/sym/References/LT6657-3.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 1 31 Center 2 +SYMATTR Value LT6657-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT6657.lib +SYMATTR Value2 LT6657-3 +SYMATTR Description 1.5ppm/°C Drift, Low Noise, Buffered Reference +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/References/LT6657-4.096.asy b/spice/copy/sym/References/LT6657-4.096.asy new file mode 100755 index 0000000..fd809e7 --- /dev/null +++ b/spice/copy/sym/References/LT6657-4.096.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 1 31 Center 2 +SYMATTR Value LT6657-4.096 +SYMATTR Prefix X +SYMATTR SpiceModel LT6657.lib +SYMATTR Value2 LT6657-4.096 +SYMATTR Description 1.5ppm/°C Drift, Low Noise, Buffered Reference +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/References/LT6657-5.asy b/spice/copy/sym/References/LT6657-5.asy new file mode 100755 index 0000000..cc5da3e --- /dev/null +++ b/spice/copy/sym/References/LT6657-5.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -80 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -32 Center 2 +WINDOW 3 1 31 Center 2 +SYMATTR Value LT6657-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6657.lib +SYMATTR Value2 LT6657-5 +SYMATTR Description 1.5ppm/°C Drift, Low Noise, Buffered Reference +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -144 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/References/LT6658-1.2.asy b/spice/copy/sym/References/LT6658-1.2.asy new file mode 100755 index 0000000..877f5f2 --- /dev/null +++ b/spice/copy/sym/References/LT6658-1.2.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 192 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT6658-1.2 +SYMATTR Prefix X +SYMATTR SpiceModel LT6658.lib +SYMATTR Value2 LT6658-1.2 +SYMATTR Description Precision Dual Output, High Current, Low Noise, Voltage Reference +PIN -96 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 96 -192 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName _OD +PINATTR SpiceOrder 4 +PIN 0 192 BOTTOM 8 +PINATTR PinName Bypass +PINATTR SpiceOrder 5 +PIN 192 32 RIGHT 8 +PINATTR PinName Vout1_F +PINATTR SpiceOrder 6 +PIN 192 112 RIGHT 8 +PINATTR PinName Vout1_S +PINATTR SpiceOrder 7 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vout2_F +PINATTR SpiceOrder 8 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2_S +PINATTR SpiceOrder 9 +PIN -96 192 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 10 +PIN 96 192 BOTTOM 8 +PINATTR PinName NR +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/References/LT6658-1.8.asy b/spice/copy/sym/References/LT6658-1.8.asy new file mode 100755 index 0000000..e5d02cf --- /dev/null +++ b/spice/copy/sym/References/LT6658-1.8.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 192 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT6658-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LT6658.lib +SYMATTR Value2 LT6658-1.8 +SYMATTR Description Precision Dual Output, High Current, Low Noise, Voltage Reference +PIN -96 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 96 -192 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName _OD +PINATTR SpiceOrder 4 +PIN 0 192 BOTTOM 8 +PINATTR PinName Bypass +PINATTR SpiceOrder 5 +PIN 192 32 RIGHT 8 +PINATTR PinName Vout1_F +PINATTR SpiceOrder 6 +PIN 192 112 RIGHT 8 +PINATTR PinName Vout1_S +PINATTR SpiceOrder 7 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vout2_F +PINATTR SpiceOrder 8 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2_S +PINATTR SpiceOrder 9 +PIN -96 192 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 10 +PIN 96 192 BOTTOM 8 +PINATTR PinName NR +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/References/LT6658-2.5.asy b/spice/copy/sym/References/LT6658-2.5.asy new file mode 100755 index 0000000..9a70151 --- /dev/null +++ b/spice/copy/sym/References/LT6658-2.5.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 192 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT6658-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6658.lib +SYMATTR Value2 LT6658-2.5 +SYMATTR Description Precision Dual Output, High Current, Low Noise, Voltage Reference +PIN -96 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 96 -192 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName _OD +PINATTR SpiceOrder 4 +PIN 0 192 BOTTOM 8 +PINATTR PinName Bypass +PINATTR SpiceOrder 5 +PIN 192 32 RIGHT 8 +PINATTR PinName Vout1_F +PINATTR SpiceOrder 6 +PIN 192 112 RIGHT 8 +PINATTR PinName Vout1_S +PINATTR SpiceOrder 7 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vout2_F +PINATTR SpiceOrder 8 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2_S +PINATTR SpiceOrder 9 +PIN -96 192 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 10 +PIN 96 192 BOTTOM 8 +PINATTR PinName NR +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/References/LT6658-3.3.asy b/spice/copy/sym/References/LT6658-3.3.asy new file mode 100755 index 0000000..651047c --- /dev/null +++ b/spice/copy/sym/References/LT6658-3.3.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 192 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT6658-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LT6658.lib +SYMATTR Value2 LT6658-3.3 +SYMATTR Description Precision Dual Output, High Current, Low Noise, Voltage Reference +PIN -96 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 96 -192 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName _OD +PINATTR SpiceOrder 4 +PIN 0 192 BOTTOM 8 +PINATTR PinName Bypass +PINATTR SpiceOrder 5 +PIN 192 32 RIGHT 8 +PINATTR PinName Vout1_F +PINATTR SpiceOrder 6 +PIN 192 112 RIGHT 8 +PINATTR PinName Vout1_S +PINATTR SpiceOrder 7 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vout2_F +PINATTR SpiceOrder 8 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2_S +PINATTR SpiceOrder 9 +PIN -96 192 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 10 +PIN 96 192 BOTTOM 8 +PINATTR PinName NR +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/References/LT6658-3.asy b/spice/copy/sym/References/LT6658-3.asy new file mode 100755 index 0000000..2f09ad0 --- /dev/null +++ b/spice/copy/sym/References/LT6658-3.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 192 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT6658-3 +SYMATTR Prefix X +SYMATTR SpiceModel LT6658.lib +SYMATTR Value2 LT6658-3 +SYMATTR Description Precision Dual Output, High Current, Low Noise, Voltage Reference +PIN -96 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 96 -192 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName _OD +PINATTR SpiceOrder 4 +PIN 0 192 BOTTOM 8 +PINATTR PinName Bypass +PINATTR SpiceOrder 5 +PIN 192 32 RIGHT 8 +PINATTR PinName Vout1_F +PINATTR SpiceOrder 6 +PIN 192 112 RIGHT 8 +PINATTR PinName Vout1_S +PINATTR SpiceOrder 7 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vout2_F +PINATTR SpiceOrder 8 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2_S +PINATTR SpiceOrder 9 +PIN -96 192 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 10 +PIN 96 192 BOTTOM 8 +PINATTR PinName NR +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/References/LT6658-5.asy b/spice/copy/sym/References/LT6658-5.asy new file mode 100755 index 0000000..54797ae --- /dev/null +++ b/spice/copy/sym/References/LT6658-5.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 192 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT6658-5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6658.lib +SYMATTR Value2 LT6658-5 +SYMATTR Description Precision Dual Output, High Current, Low Noise, Voltage Reference +PIN -96 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 96 -192 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName _OD +PINATTR SpiceOrder 4 +PIN 0 192 BOTTOM 8 +PINATTR PinName Bypass +PINATTR SpiceOrder 5 +PIN 192 32 RIGHT 8 +PINATTR PinName Vout1_F +PINATTR SpiceOrder 6 +PIN 192 112 RIGHT 8 +PINATTR PinName Vout1_S +PINATTR SpiceOrder 7 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vout2_F +PINATTR SpiceOrder 8 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2_S +PINATTR SpiceOrder 9 +PIN -96 192 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 10 +PIN 96 192 BOTTOM 8 +PINATTR PinName NR +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/References/LT6658.asy b/spice/copy/sym/References/LT6658.asy new file mode 100755 index 0000000..9a70151 --- /dev/null +++ b/spice/copy/sym/References/LT6658.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -176 -192 192 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LT6658-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LT6658.lib +SYMATTR Value2 LT6658-2.5 +SYMATTR Description Precision Dual Output, High Current, Low Noise, Voltage Reference +PIN -96 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 0 -192 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 96 -192 TOP 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 3 +PIN -176 0 LEFT 8 +PINATTR PinName _OD +PINATTR SpiceOrder 4 +PIN 0 192 BOTTOM 8 +PINATTR PinName Bypass +PINATTR SpiceOrder 5 +PIN 192 32 RIGHT 8 +PINATTR PinName Vout1_F +PINATTR SpiceOrder 6 +PIN 192 112 RIGHT 8 +PINATTR PinName Vout1_S +PINATTR SpiceOrder 7 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vout2_F +PINATTR SpiceOrder 8 +PIN 192 -48 RIGHT 8 +PINATTR PinName Vout2_S +PINATTR SpiceOrder 9 +PIN -96 192 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 10 +PIN 96 192 BOTTOM 8 +PINATTR PinName NR +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/References/LTC6655-1.25.asy b/spice/copy/sym/References/LTC6655-1.25.asy new file mode 100755 index 0000000..8c45146 --- /dev/null +++ b/spice/copy/sym/References/LTC6655-1.25.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LTC6655-1.25 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6655-1.25.sub +SYMATTR Value2 LTC6655-1.25 +SYMATTR Description .25ppm Noise, Low Drift Precision Reference +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT_S +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT_F +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/References/LTC6655-2.048.asy b/spice/copy/sym/References/LTC6655-2.048.asy new file mode 100755 index 0000000..4e7c961 --- /dev/null +++ b/spice/copy/sym/References/LTC6655-2.048.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LTC6655-2.048 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6655-2.048.sub +SYMATTR Value2 LTC6655-2.048 +SYMATTR Description .25ppm Noise, Low Drift Precision Reference +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT_S +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT_F +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/References/LTC6655-2.5.asy b/spice/copy/sym/References/LTC6655-2.5.asy new file mode 100755 index 0000000..8c516be --- /dev/null +++ b/spice/copy/sym/References/LTC6655-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LTC6655-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6655-2.5.sub +SYMATTR Value2 LTC6655-2.5 +SYMATTR Description .25ppm Noise, Low Drift Precision Reference +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT_S +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT_F +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/References/LTC6655-3.3.asy b/spice/copy/sym/References/LTC6655-3.3.asy new file mode 100755 index 0000000..d3bc530 --- /dev/null +++ b/spice/copy/sym/References/LTC6655-3.3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LTC6655-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6655-3.3.sub +SYMATTR Value2 LTC6655-3.3 +SYMATTR Description .25ppm Noise, Low Drift Precision Reference +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT_S +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT_F +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/References/LTC6655-3.asy b/spice/copy/sym/References/LTC6655-3.asy new file mode 100755 index 0000000..8a747bb --- /dev/null +++ b/spice/copy/sym/References/LTC6655-3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LTC6655-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6655-3.sub +SYMATTR Value2 LTC6655-3 +SYMATTR Description .25ppm Noise, Low Drift Precision Reference +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT_S +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT_F +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/References/LTC6655-4.096.asy b/spice/copy/sym/References/LTC6655-4.096.asy new file mode 100755 index 0000000..0c94f05 --- /dev/null +++ b/spice/copy/sym/References/LTC6655-4.096.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LTC6655-4.096 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6655-4.096.sub +SYMATTR Value2 LTC6655-4.096 +SYMATTR Description .25ppm Noise, Low Drift Precision Reference +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT_S +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT_F +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/References/LTC6655-5.asy b/spice/copy/sym/References/LTC6655-5.asy new file mode 100755 index 0000000..6cd8444 --- /dev/null +++ b/spice/copy/sym/References/LTC6655-5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LTC6655-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6655-5.sub +SYMATTR Value2 LTC6655-5 +SYMATTR Description .25ppm Noise, Low Drift Precision Reference +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 32 RIGHT 8 +PINATTR PinName OUT_S +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT_F +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/References/LTC6655LN-2.5.asy b/spice/copy/sym/References/LTC6655LN-2.5.asy new file mode 100755 index 0000000..34f7d5a --- /dev/null +++ b/spice/copy/sym/References/LTC6655LN-2.5.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -64 144 64 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 12 77 Left 2 +SYMATTR Value LTC6655LN-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6655LN-2.5.sub +SYMATTR Value2 LTC6655LN-2.5 +SYMATTR Description .25ppm Noise, Low Drift Precision Reference +PIN -144 32 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 64 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 144 32 RIGHT 8 +PINATTR PinName NR +PINATTR SpiceOrder 4 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT_F +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/References/LTZ1000.asy b/spice/copy/sym/References/LTZ1000.asy new file mode 100755 index 0000000..d1bb10a --- /dev/null +++ b/spice/copy/sym/References/LTZ1000.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType BLOCK +LINE Normal -96 -32 -96 -96 +LINE Normal -80 -32 -96 -32 +LINE Normal -80 -24 -80 -32 +LINE Normal -112 -24 -80 -24 +LINE Normal -80 0 -112 0 +LINE Normal -112 16 -80 16 +LINE Normal -96 32 -112 32 +LINE Normal -96 96 -96 32 +LINE Normal 80 0 96 -16 +LINE Normal 80 16 96 32 +LINE Normal 80 22 80 -6 +LINE Normal 32 8 80 8 +LINE Normal 96 -96 96 -16 +LINE Normal 96 96 96 32 +LINE Normal -48 0 -32 -16 +LINE Normal -48 16 -32 32 +LINE Normal -48 22 -48 -6 +LINE Normal -64 8 -48 8 +LINE Normal -37 24 -32 32 +LINE Normal -40 27 -32 32 +LINE Normal -32 -96 -32 -16 +LINE Normal 32 -56 32 -96 +LINE Normal 45 -56 19 -56 +LINE Normal 19 -56 15 -61 +LINE Normal 16 -32 32 -56 +LINE Normal 48 -32 16 -32 +LINE Normal 32 -56 48 -32 +LINE Normal 32 96 32 -32 +LINE Normal -32 48 -32 32 +LINE Normal 96 48 -32 48 +LINE Normal -64 64 -64 8 +LINE Normal -32 64 -64 64 +LINE Normal -32 96 -32 64 +LINE Normal -112 -16 -112 -24 +LINE Normal -80 -8 -80 -16 +LINE Normal -112 0 -112 -8 +LINE Normal -80 8 -80 0 +LINE Normal -112 16 -112 8 +LINE Normal -80 24 -80 16 +LINE Normal -112 -16 -80 -16 +LINE Normal -112 -8 -80 -8 +LINE Normal -112 8 -80 8 +LINE Normal -112 24 -80 24 +LINE Normal -112 32 -112 24 +LINE Normal -40 27 -37 24 +LINE Normal 91 24 96 32 +LINE Normal 88 27 96 32 +LINE Normal 88 27 91 24 +LINE Normal 49 -51 45 -56 +RECTANGLE Normal -128 -96 128 96 +CIRCLE Normal 33 9 31 7 +CIRCLE Normal 34 10 30 6 +CIRCLE Normal 35 11 29 5 +CIRCLE Normal 97 49 95 47 +CIRCLE Normal 98 50 94 46 +CIRCLE Normal 99 51 93 45 +TEXT -90 -80 Left 2 1 +TEXT -26 -80 Left 2 8 +TEXT 39 -80 Left 2 3 +TEXT 102 -80 Left 2 5 +TEXT -90 80 Left 2 2 +TEXT -26 80 Left 2 6 +TEXT 39 80 Left 2 4 +TEXT 102 80 Left 2 7 +TEXT -4 0 Center 2 LT +WINDOW 0 112 -112 Left 2 +WINDOW 3 112 112 Left 2 +SYMATTR Value LTZ1000 +SYMATTR SpiceModel LTZ1000.lib +SYMATTR Value2 LTZ1000 +SYMATTR Prefix X +SYMATTR Description Ultra Precision Reference +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 96 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 32 -96 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 32 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 -96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN -32 96 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 96 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN -32 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/References/LTZ1000A.asy b/spice/copy/sym/References/LTZ1000A.asy new file mode 100755 index 0000000..4fe5e90 --- /dev/null +++ b/spice/copy/sym/References/LTZ1000A.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType BLOCK +LINE Normal -96 -32 -96 -96 +LINE Normal -80 -32 -96 -32 +LINE Normal -80 -24 -80 -32 +LINE Normal -112 -24 -80 -24 +LINE Normal -80 0 -112 0 +LINE Normal -112 16 -80 16 +LINE Normal -96 32 -112 32 +LINE Normal -96 96 -96 32 +LINE Normal 80 0 96 -16 +LINE Normal 80 16 96 32 +LINE Normal 80 22 80 -6 +LINE Normal 32 8 80 8 +LINE Normal 96 -96 96 -16 +LINE Normal 96 96 96 32 +LINE Normal -48 0 -32 -16 +LINE Normal -48 16 -32 32 +LINE Normal -48 22 -48 -6 +LINE Normal -64 8 -48 8 +LINE Normal -37 24 -32 32 +LINE Normal -40 27 -32 32 +LINE Normal -32 -96 -32 -16 +LINE Normal 32 -56 32 -96 +LINE Normal 45 -56 19 -56 +LINE Normal 19 -56 15 -61 +LINE Normal 16 -32 32 -56 +LINE Normal 48 -32 16 -32 +LINE Normal 32 -56 48 -32 +LINE Normal 32 96 32 -32 +LINE Normal -32 48 -32 32 +LINE Normal 96 48 -32 48 +LINE Normal -64 64 -64 8 +LINE Normal -32 64 -64 64 +LINE Normal -32 96 -32 64 +LINE Normal -112 -16 -112 -24 +LINE Normal -80 -8 -80 -16 +LINE Normal -112 0 -112 -8 +LINE Normal -80 8 -80 0 +LINE Normal -112 16 -112 8 +LINE Normal -80 24 -80 16 +LINE Normal -112 -16 -80 -16 +LINE Normal -112 -8 -80 -8 +LINE Normal -112 8 -80 8 +LINE Normal -112 24 -80 24 +LINE Normal -112 32 -112 24 +LINE Normal -40 27 -37 24 +LINE Normal 91 24 96 32 +LINE Normal 88 27 96 32 +LINE Normal 88 27 91 24 +LINE Normal 49 -51 45 -56 +RECTANGLE Normal -128 -96 128 96 +CIRCLE Normal 33 9 31 7 +CIRCLE Normal 34 10 30 6 +CIRCLE Normal 35 11 29 5 +CIRCLE Normal 97 49 95 47 +CIRCLE Normal 98 50 94 46 +CIRCLE Normal 99 51 93 45 +TEXT -90 -80 Left 2 1 +TEXT -26 -80 Left 2 8 +TEXT 39 -80 Left 2 3 +TEXT 102 -80 Left 2 5 +TEXT -90 80 Left 2 2 +TEXT -26 80 Left 2 6 +TEXT 39 80 Left 2 4 +TEXT 102 80 Left 2 7 +TEXT -4 0 Center 2 LT +WINDOW 0 112 -112 Left 2 +WINDOW 3 112 112 Left 2 +SYMATTR Value LTZ1000A +SYMATTR SpiceModel LTZ1000.lib +SYMATTR Value2 LTZ1000A +SYMATTR Prefix X +SYMATTR Description Ultra Precision Reference +PIN -96 -96 NONE 8 +PINATTR PinName 1 +PINATTR SpiceOrder 1 +PIN -96 96 NONE 8 +PINATTR PinName 2 +PINATTR SpiceOrder 2 +PIN 32 -96 NONE 8 +PINATTR PinName 3 +PINATTR SpiceOrder 3 +PIN 32 96 NONE 8 +PINATTR PinName 4 +PINATTR SpiceOrder 4 +PIN 96 -96 NONE 8 +PINATTR PinName 5 +PINATTR SpiceOrder 5 +PIN -32 96 NONE 8 +PINATTR PinName 6 +PINATTR SpiceOrder 6 +PIN 96 96 NONE 8 +PINATTR PinName 7 +PINATTR SpiceOrder 7 +PIN -32 -96 NONE 8 +PINATTR PinName 8 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/References/RH1009.asy b/spice/copy/sym/References/RH1009.asy new file mode 100755 index 0000000..dd48075 --- /dev/null +++ b/spice/copy/sym/References/RH1009.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType BLOCK +LINE Normal 16 -16 -16 -16 +LINE Normal 27 -26 16 -16 +LINE Normal -16 -16 -27 -6 +LINE Normal -21 16 0 -16 +LINE Normal 21 16 -21 16 +LINE Normal 0 -16 21 16 +LINE Normal 0 -32 0 -16 +LINE Normal 0 16 0 32 +LINE Normal 32 0 11 0 +WINDOW 3 16 32 Left 2 +WINDOW 0 30 -32 Left 2 +SYMATTR Value RH1009 +SYMATTR Prefix X +SYMATTR SpiceModel LTC3.lib +SYMATTR Value2 LT1009 +SYMATTR Description 2.5V Adjustable Reference +PIN 0 -32 NONE 8 +PINATTR PinName VCC +PINATTR SpiceOrder 1 +PIN 0 32 NONE 8 +PINATTR PinName VEE +PINATTR SpiceOrder 2 +PIN 32 0 NONE 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/SOAtherm-HeatSink.asy b/spice/copy/sym/SOAtherm-HeatSink.asy new file mode 100755 index 0000000..c9d7d44 --- /dev/null +++ b/spice/copy/sym/SOAtherm-HeatSink.asy @@ -0,0 +1,98 @@ +Version 4 +SymbolType CELL +LINE Normal 48 64 -48 64 2 +LINE Normal 48 -7 32 -7 2 +LINE Normal 48 -16 48 -7 2 +LINE Normal 32 -16 48 -16 2 +LINE Normal 48 -40 32 -40 2 +LINE Normal 48 -48 48 -40 2 +LINE Normal 48 -64 -48 -64 2 +LINE Normal 32 -48 48 -48 2 +LINE Normal 32 -56 32 -48 2 +LINE Normal 48 -56 32 -56 2 +LINE Normal 48 -64 48 -56 2 +LINE Normal -80 64 -48 64 1 +LINE Normal -80 -64 -80 64 1 +LINE Normal -48 -64 -80 -64 1 +LINE Normal -48 64 -48 -64 2 +LINE Normal 48 -24 32 -24 2 +LINE Normal 48 -32 48 -24 2 +LINE Normal 32 -32 48 -32 2 +LINE Normal 32 -24 32 -16 2 +LINE Normal 32 -40 32 -32 2 +LINE Normal 48 55 48 64 2 +LINE Normal 32 55 48 55 2 +LINE Normal 48 31 32 31 2 +LINE Normal 48 23 48 31 2 +LINE Normal 32 23 48 23 2 +LINE Normal 32 15 32 23 2 +LINE Normal 48 15 32 15 2 +LINE Normal 48 7 48 15 2 +LINE Normal 48 47 32 47 2 +LINE Normal 48 39 48 47 2 +LINE Normal 32 39 48 39 2 +LINE Normal 32 47 32 55 2 +LINE Normal 32 31 32 39 2 +LINE Normal 48 7 32 7 2 +LINE Normal 32 -7 32 7 2 +LINE Normal -48 -96 -80 -64 1 +LINE Normal -16 -96 -48 -96 1 +LINE Normal -48 -64 -16 -96 2 +LINE Normal 80 -96 -16 -96 2 +LINE Normal 48 -64 80 -96 2 +LINE Normal 80 -88 48 -56 2 +LINE Normal 80 -80 48 -48 2 +LINE Normal 80 -72 48 -40 2 +LINE Normal 80 -64 48 -32 2 +LINE Normal 80 -56 48 -24 2 +LINE Normal 80 -48 48 -16 2 +LINE Normal 80 -39 48 -7 2 +LINE Normal 80 -25 48 7 2 +LINE Normal 80 -17 48 15 2 +LINE Normal 80 -9 48 23 2 +LINE Normal 80 -1 48 31 2 +LINE Normal 80 7 48 39 2 +LINE Normal 80 15 48 47 2 +LINE Normal 80 23 48 55 2 +LINE Normal 80 32 48 64 2 +LINE Normal 80 -88 80 -96 2 +LINE Normal 80 -72 80 -80 2 +LINE Normal 80 -56 80 -64 2 +LINE Normal 80 -39 80 -48 2 +LINE Normal 80 -17 80 -25 2 +LINE Normal 80 -1 80 -9 2 +LINE Normal 80 15 80 7 2 +LINE Normal 80 32 80 23 2 +LINE Normal 40 -56 32 -48 2 +LINE Normal 40 -40 32 -32 2 +LINE Normal 40 -24 32 -16 2 +LINE Normal 46 -7 32 7 2 +LINE Normal 40 15 32 23 2 +LINE Normal 40 31 32 39 2 +LINE Normal 40 47 32 55 2 +LINE Normal 72 -80 80 -80 2 +LINE Normal 72 -64 80 -64 2 +LINE Normal 72 -48 80 -48 2 +LINE Normal 72 23 80 23 2 +LINE Normal 72 7 80 7 2 +LINE Normal 72 -9 80 -9 2 +LINE Normal 66 -25 80 -25 2 +WINDOW 0 0 -64 Bottom 2 +WINDOW 3 97 29 Left 2 +WINDOW 123 97 52 Left 2 +WINDOW 38 97 -28 Left 2 +SYMATTR Value Rtheta=10 Tambient=85 +SYMATTR Value2 Area_Contact_mm2=100 Volume_mm3=1000 +SYMATTR SpiceModel copper +SYMATTR Prefix X +SYMATTR ModelFile SOAtherm-HeatSink.lib +SYMATTR Description Heat Sink Thermal Model +PIN -80 0 VTOP 1 +PINATTR PinName Tc +PINATTR SpiceOrder 1 +PIN -48 0 VTOP 1 +PINATTR PinName Tinterface +PINATTR SpiceOrder 2 +PIN 48 0 VBOTTOM 16 +PINATTR PinName Tfin +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/SOAtherm-PCB.asy b/spice/copy/sym/SOAtherm-PCB.asy new file mode 100755 index 0000000..4f2ec99 --- /dev/null +++ b/spice/copy/sym/SOAtherm-PCB.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal -79 -40 -112 40 2 +LINE Normal 112 -40 -79 -40 2 +LINE Normal 80 40 112 -40 2 +LINE Normal -112 40 80 40 2 +LINE Normal -112 48 -112 40 2 +LINE Normal 80 48 -112 48 2 +LINE Normal 80 48 80 40 2 +LINE Normal 112 -32 80 48 2 +LINE Normal 112 -40 112 -32 2 +WINDOW 0 16 -40 Bottom 2 +WINDOW 3 -112 64 Left 2 +WINDOW 123 -112 96 Left 2 +SYMATTR Value Area_Contact_mm2=100 Area_PCB_mm2=2500 Copper_Thickness_oz=1 +SYMATTR Value2 Tambient=85 LFM=100 PCB_FR4_Thickness_mm=1.5 +SYMATTR Prefix X +SYMATTR SpiceModel TopsideCopper +SYMATTR ModelFile SOAtherm-PCB.lib +SYMATTR Description PCB Thermal Model +PIN 0 0 TOP 1 +PINATTR PinName Tcenter +PINATTR SpiceOrder 1 diff --git a/spice/copy/sym/SpecialFunctions/2ndOrdAllpass.asy b/spice/copy/sym/SpecialFunctions/2ndOrdAllpass.asy new file mode 100755 index 0000000..54522a1 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/2ndOrdAllpass.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal -80 8 -72 16 +LINE Normal -80 24 -72 16 +LINE Normal -80 -27 143 -27 +LINE Normal -80 -27 -80 64 +LINE Normal -80 64 144 64 +LINE Normal 144 64 160 16 +LINE Normal 143 -27 160 16 +LINE Normal 65 11 -8 11 +WINDOW 0 -65 -43 Left 2 +WINDOW 3 -64 80 Left 2 +SYMATTR Value f0=1k Q=.5 H=1 +SYMATTR Prefix X +SYMATTR Description Second Order Allpass Filter +SYMATTR ModelFile 2ndOrderAllpass.sub +SYMATTR SpiceModel 2ndOrderAllpass +PIN -80 16 LEFT 12 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 160 16 RIGHT 12 +PINATTR PinName OUT +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/SpecialFunctions/2ndOrdBandpass.asy b/spice/copy/sym/SpecialFunctions/2ndOrdBandpass.asy new file mode 100755 index 0000000..bd24179 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/2ndOrdBandpass.asy @@ -0,0 +1,25 @@ +Version 4 +SymbolType CELL +LINE Normal -80 8 -72 16 +LINE Normal -80 24 -72 16 +LINE Normal -80 -27 143 -27 +LINE Normal -80 -27 -80 64 +LINE Normal -80 64 144 64 +LINE Normal 144 64 160 16 +LINE Normal 143 -27 160 16 +LINE Normal 56 -7 17 -7 +LINE Normal 83 40 56 -7 +LINE Normal -8 39 17 -7 +WINDOW 0 -65 -43 Left 2 +WINDOW 3 -64 80 Left 2 +SYMATTR Value f0=1k Q=.5 H=.1 +SYMATTR Prefix X +SYMATTR Description Second Order Band Pass Filter +SYMATTR ModelFile 2ndOrderBandpass.sub +SYMATTR SpiceModel 2ndOrderBandpass +PIN -80 16 LEFT 12 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 160 16 RIGHT 12 +PINATTR PinName OUT +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/SpecialFunctions/2ndOrdComplexzero.asy b/spice/copy/sym/SpecialFunctions/2ndOrdComplexzero.asy new file mode 100755 index 0000000..dd3a7dc --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/2ndOrdComplexzero.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal -80 8 -72 16 +LINE Normal -80 24 -72 16 +LINE Normal -80 -27 143 -27 +LINE Normal -80 -27 -80 64 +LINE Normal -80 64 144 64 +LINE Normal 144 64 160 16 +LINE Normal 143 -27 160 16 +WINDOW 0 -65 -43 Left 2 +WINDOW 3 -64 80 Left 2 +SYMATTR Value f0=1k fn=2k Q=.5 Qn=1 H=1 +SYMATTR Prefix X +SYMATTR Description Second Order Complexzero Filter +SYMATTR ModelFile 2ndOrderComplexzero.sub +SYMATTR SpiceModel 2ndOrderComplexzero +PIN -80 16 LEFT 12 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 160 16 RIGHT 12 +PINATTR PinName OUT +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/SpecialFunctions/2ndOrdHighpass.asy b/spice/copy/sym/SpecialFunctions/2ndOrdHighpass.asy new file mode 100755 index 0000000..69802a2 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/2ndOrdHighpass.asy @@ -0,0 +1,24 @@ +Version 4 +SymbolType CELL +LINE Normal -80 8 -72 16 +LINE Normal -80 24 -72 16 +LINE Normal -80 -27 143 -27 +LINE Normal -80 -27 -80 64 +LINE Normal -80 64 144 64 +LINE Normal 144 64 160 16 +LINE Normal 143 -27 160 16 +LINE Normal 56 -7 17 -7 +LINE Normal -8 39 17 -7 +WINDOW 0 -65 -43 Left 2 +WINDOW 3 -64 80 Left 2 +SYMATTR Value f0=1k Q=.5 H=1 +SYMATTR Prefix X +SYMATTR Description Second Order High Pass Filter +SYMATTR ModelFile 2ndOrderHighpass.sub +SYMATTR SpiceModel 2ndOrderHighpass +PIN -80 16 LEFT 12 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 160 16 RIGHT 12 +PINATTR PinName OUT +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/SpecialFunctions/2ndOrdLowpass.asy b/spice/copy/sym/SpecialFunctions/2ndOrdLowpass.asy new file mode 100755 index 0000000..e74ab2c --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/2ndOrdLowpass.asy @@ -0,0 +1,24 @@ +Version 4 +SymbolType CELL +LINE Normal -80 8 -72 16 +LINE Normal -80 24 -72 16 +LINE Normal -80 -27 143 -27 +LINE Normal -80 -27 -80 64 +LINE Normal -80 64 144 64 +LINE Normal 144 64 160 16 +LINE Normal 143 -27 160 16 +LINE Normal 35 -7 -4 -7 +LINE Normal 60 39 35 -7 +WINDOW 0 -65 -43 Left 2 +WINDOW 3 -64 80 Left 2 +SYMATTR Value f0=1k Q=.5 H=1 +SYMATTR Prefix X +SYMATTR Description Second Order High Pass Filter +SYMATTR ModelFile 2ndOrderLowpass.sub +SYMATTR SpiceModel 2ndOrderLowpass +PIN -80 16 LEFT 12 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 160 16 RIGHT 12 +PINATTR PinName OUT +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/SpecialFunctions/2ndOrdNotch.asy b/spice/copy/sym/SpecialFunctions/2ndOrdNotch.asy new file mode 100755 index 0000000..b469ba5 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/2ndOrdNotch.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +LINE Normal -80 8 -72 16 +LINE Normal -80 24 -72 16 +LINE Normal -80 -27 143 -27 +LINE Normal -80 -27 -80 64 +LINE Normal -80 64 144 64 +LINE Normal 144 64 160 16 +LINE Normal 143 -27 160 16 +LINE Normal -3 -7 -26 -7 +LINE Normal 22 39 -3 -7 +LINE Normal 47 -7 70 -7 +LINE Normal 22 39 47 -7 +WINDOW 0 -65 -43 Left 2 +WINDOW 3 -64 80 Left 2 +SYMATTR Value f0=1k Q=.5 H=1 +SYMATTR Prefix X +SYMATTR Description Second Order Notch Filter +SYMATTR ModelFile 2ndOrderNotch.sub +SYMATTR SpiceModel 2ndOrderNotch +PIN -80 16 LEFT 12 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 160 16 RIGHT 12 +PINATTR PinName OUT +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/SpecialFunctions/AD8452.asy b/spice/copy/sym/SpecialFunctions/AD8452.asy new file mode 100755 index 0000000..c7bcf6c --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/AD8452.asy @@ -0,0 +1,137 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal -352 -384 384 384 +TEXT 0 -7 Center 2 ADI +WINDOW 3 0 128 Center 2 +WINDOW 0 0 -160 Center 2 +SYMATTR Value AD8452 +SYMATTR Value2 AD8452 +SYMATTR Prefix X +SYMATTR SpiceModel AD8452.sub +SYMATTR Description Precision Integrated Analog Front End, Controller and PWM for Battery Test/Formation Systems +PIN -352 -272 LEFT 8 +PINATTR PinName Isrefh +PINATTR SpiceOrder 1 +PIN -352 -224 LEFT 8 +PINATTR PinName Isrefl +PINATTR SpiceOrder 2 +PIN -352 -160 LEFT 8 +PINATTR PinName Isvp +PINATTR SpiceOrder 4 +PIN -352 -64 LEFT 8 +PINATTR PinName Isvn +PINATTR SpiceOrder 5 +PIN -352 48 LEFT 8 +PINATTR PinName Bvp +PINATTR SpiceOrder 6 +PIN -352 144 LEFT 8 +PINATTR PinName Bvn +PINATTR SpiceOrder 8 +PIN -352 208 LEFT 8 +PINATTR PinName Bvrefl +PINATTR SpiceOrder 10 +PIN -352 256 LEFT 8 +PINATTR PinName Bvrefh +PINATTR SpiceOrder 12 +PIN -240 384 VLEFT 8 +PINATTR PinName AVee +PINATTR SpiceOrder 13 +PIN -192 384 VLEFT 8 +PINATTR PinName Vset +PINATTR SpiceOrder 14 +PIN -144 384 VLEFT 8 +PINATTR PinName VVP0 +PINATTR SpiceOrder 15 +PIN -96 384 VLEFT 8 +PINATTR PinName Bvmea +PINATTR SpiceOrder 16 +PIN -48 384 VLEFT 8 +PINATTR PinName Vsetb +PINATTR SpiceOrder 17 +PIN 0 384 VLEFT 8 +PINATTR PinName Vve0 +PINATTR SpiceOrder 18 +PIN 48 384 VLEFT 8 +PINATTR PinName Vve1 +PINATTR SpiceOrder 19 +PIN 96 384 VLEFT 8 +PINATTR PinName Vint_CV +PINATTR SpiceOrder 20 +PIN 192 384 VLEFT 8 +PINATTR PinName Mode +PINATTR SpiceOrder 22 +PIN 240 384 VLEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 23 +PIN 288 384 VLEFT 8 +PINATTR PinName Fault +PINATTR SpiceOrder 24 +PIN 384 256 RIGHT 8 +PINATTR PinName CLflg +PINATTR SpiceOrder 25 +PIN 384 208 RIGHT 8 +PINATTR PinName Sync +PINATTR SpiceOrder 26 +PIN 384 160 RIGHT 8 +PINATTR PinName Scfg +PINATTR SpiceOrder 27 +PIN 384 112 RIGHT 8 +PINATTR PinName Vreg +PINATTR SpiceOrder 28 +PIN 384 -80 RIGHT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 29 +PIN 384 16 RIGHT 8 +PINATTR PinName DL +PINATTR SpiceOrder 30 +PIN 384 -32 RIGHT 8 +PINATTR PinName DH +PINATTR SpiceOrder 31 +PIN 384 64 RIGHT 8 +PINATTR PinName Dgnd +PINATTR SpiceOrder 32 +PIN 384 -128 RIGHT 8 +PINATTR PinName DT +PINATTR SpiceOrder 33 +PIN 384 -176 RIGHT 8 +PINATTR PinName SS +PINATTR SpiceOrder 34 +PIN 384 -224 RIGHT 8 +PINATTR PinName Dmax +PINATTR SpiceOrder 35 +PIN 384 -272 RIGHT 8 +PINATTR PinName Freq +PINATTR SpiceOrder 36 +PIN 288 -384 VRIGHT 8 +PINATTR PinName CLvt +PINATTR SpiceOrder 37 +PIN 240 -384 VRIGHT 8 +PINATTR PinName CLp +PINATTR SpiceOrder 38 +PIN 192 -384 VRIGHT 8 +PINATTR PinName CLn +PINATTR SpiceOrder 39 +PIN -192 -384 VRIGHT 8 +PINATTR PinName AVcc +PINATTR SpiceOrder 40 +PIN 96 -384 VRIGHT 8 +PINATTR PinName Vint_CC +PINATTR SpiceOrder 41 +PIN 48 -384 VRIGHT 8 +PINATTR PinName Ive1 +PINATTR SpiceOrder 42 +PIN 0 -384 VRIGHT 8 +PINATTR PinName Ive0 +PINATTR SpiceOrder 43 +PIN -48 -384 VRIGHT 8 +PINATTR PinName Ismea +PINATTR SpiceOrder 44 +PIN -96 -384 VRIGHT 8 +PINATTR PinName Iset +PINATTR SpiceOrder 45 +PIN -144 -384 VRIGHT 8 +PINATTR PinName Agnd +PINATTR SpiceOrder 47 +PIN -240 -384 VRIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 48 diff --git a/spice/copy/sym/SpecialFunctions/LT1166.asy b/spice/copy/sym/SpecialFunctions/LT1166.asy new file mode 100755 index 0000000..a0315c5 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT1166.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -208 128 208 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -120 Center 2 +WINDOW 3 0 120 Center 2 +SYMATTR Value LT1166 +SYMATTR Prefix X +SYMATTR SpiceModel LTC.lib +SYMATTR Value2 LT1166 +SYMATTR Description Power Output Stage Automatic Bias System +PIN 0 -208 TOP 8 +PINATTR PinName Vtop +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 2 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 3 +PIN 0 208 BOTTOM 8 +PINATTR PinName Vbottom +PINATTR SpiceOrder 4 +PIN 128 160 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 5 +PIN 128 80 RIGHT 8 +PINATTR PinName Ilim- +PINATTR SpiceOrder 6 +PIN 128 -80 RIGHT 8 +PINATTR PinName Ilim+ +PINATTR SpiceOrder 7 +PIN 128 -160 RIGHT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LT1739.asy b/spice/copy/sym/SpecialFunctions/LT1739.asy new file mode 100755 index 0000000..34f9e2f --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT1739.asy @@ -0,0 +1,60 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -29 +LINE Normal 0 48 0 29 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal -16 48 -16 38 +LINE Normal 16 48 16 19 +LINE Normal 9 10 13 10 +LINE Normal 13 15 13 10 +LINE Normal 13 15 9 15 +LINE Normal 9 5 9 10 +LINE Normal 9 5 13 5 +LINE Normal -18 29 -14 29 +LINE Normal -14 34 -14 29 +LINE Normal -14 34 -18 34 +LINE Normal -18 24 -18 29 +LINE Normal -18 24 -14 24 +LINE Normal 16 15 16 5 +LINE Normal 18 5 16 5 +LINE Normal 20 6 18 5 +LINE Normal 20 10 20 6 +LINE Normal 18 11 20 10 +LINE Normal 20 15 18 11 +LINE Normal 16 11 18 11 +LINE Normal -4 21 4 21 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT1739 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1794 +SYMATTR Description Dual 500mA, 200MHz xDSL Line Driver Amplifier(1 of 2) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -16 48 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 6 +PIN 16 48 NONE 0 +PINATTR PinName SR +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/SpecialFunctions/LT1794.asy b/spice/copy/sym/SpecialFunctions/LT1794.asy new file mode 100755 index 0000000..92a8856 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT1794.asy @@ -0,0 +1,60 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -48 48 0 +LINE Normal -32 48 48 0 +LINE Normal -32 -48 -32 48 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -48 0 -29 +LINE Normal 0 48 0 29 +LINE Normal -4 -20 4 -20 +LINE Normal 0 -24 0 -16 +LINE Normal -16 48 -16 38 +LINE Normal 16 48 16 19 +LINE Normal 9 10 13 10 +LINE Normal 13 15 13 10 +LINE Normal 13 15 9 15 +LINE Normal 9 5 9 10 +LINE Normal 9 5 13 5 +LINE Normal -18 29 -14 29 +LINE Normal -14 34 -14 29 +LINE Normal -14 34 -18 34 +LINE Normal -18 24 -18 29 +LINE Normal -18 24 -14 24 +LINE Normal 16 15 16 5 +LINE Normal 18 5 16 5 +LINE Normal 20 6 18 5 +LINE Normal 20 10 20 6 +LINE Normal 18 11 20 10 +LINE Normal 20 15 18 11 +LINE Normal 16 11 18 11 +LINE Normal -4 21 4 21 +WINDOW 0 32 -40 Left 2 +WINDOW 3 32 40 Left 2 +SYMATTR Value LT1794 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1.lib +SYMATTR Value2 LT1794 +SYMATTR Description Dual 500mA, 200MHz xDSL Line Driver Amplifier(1 of 2) +PIN -32 16 NONE 0 +PINATTR PinName In+ +PINATTR SpiceOrder 1 +PIN -32 -16 NONE 0 +PINATTR PinName In- +PINATTR SpiceOrder 2 +PIN 0 -48 NONE 0 +PINATTR PinName V+ +PINATTR SpiceOrder 3 +PIN 0 48 NONE 0 +PINATTR PinName V- +PINATTR SpiceOrder 4 +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 5 +PIN -16 48 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 6 +PIN 16 48 NONE 0 +PINATTR PinName SR +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/SpecialFunctions/LT4294.asy b/spice/copy/sym/SpecialFunctions/LT4294.asy new file mode 100755 index 0000000..5208cc0 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4294.asy @@ -0,0 +1,38 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 160 -192 -160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LT4294 +SYMATTR Prefix X +SYMATTR SpiceModel LT4294.sub +SYMATTR Value2 LT4294 +SYMATTR Description IEEE 802.3bt PD Interface Controller +PIN -192 -96 LEFT 8 +PINATTR PinName AUX +PINATTR SpiceOrder 2 +PIN -192 -32 LEFT 8 +PINATTR PinName Rclass +PINATTR SpiceOrder 3 +PIN -192 32 LEFT 8 +PINATTR PinName Rclass++ +PINATTR SpiceOrder 4 +PIN -192 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 192 128 RIGHT 8 +PINATTR PinName _T2P +PINATTR SpiceOrder 6 +PIN 192 64 RIGHT 8 +PINATTR PinName pwrGD +PINATTR SpiceOrder 7 +PIN 192 0 RIGHT 8 +PINATTR PinName HSsrc +PINATTR SpiceOrder 8 +PIN 192 -64 RIGHT 8 +PINATTR PinName HSgate +PINATTR SpiceOrder 9 +PIN 192 -128 RIGHT 8 +PINATTR PinName Vport +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LT4320-1.asy b/spice/copy/sym/SpecialFunctions/LT4320-1.asy new file mode 100755 index 0000000..c686521 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4320-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 128 -144 -128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT4320-1 +SYMATTR Prefix X +SYMATTR Description Ideal Diode Bridge Controller +SYMATTR SpiceModel LT4320-1.sub +SYMATTR Value2 LT4320-1 +PIN -144 -96 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName Outn +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName Outp +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LT4320.asy b/spice/copy/sym/SpecialFunctions/LT4320.asy new file mode 100755 index 0000000..0c302fe --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4320.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 128 -144 -128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT4320 +SYMATTR Prefix X +SYMATTR Description Ideal Diode Bridge Controller +SYMATTR SpiceModel LT4320.sub +SYMATTR Value2 LT4320 +PIN -144 -96 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 1 +PIN -144 -32 LEFT 8 +PINATTR PinName TG2 +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName BG2 +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName BG1 +PINATTR SpiceOrder 4 +PIN 144 96 RIGHT 8 +PINATTR PinName Outn +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName Outp +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName TG1 +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LT4321.asy b/spice/copy/sym/SpecialFunctions/LT4321.asy new file mode 100755 index 0000000..ebe7a01 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4321.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 192 -192 -192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LT4321 +SYMATTR Prefix X +SYMATTR Description POE Ideal Diode Bridge Controller +SYMATTR SpiceModel LT4321.sub +SYMATTR Value2 LT4321 +PIN 144 -192 TOP 8 +PINATTR PinName TG36 +PINATTR SpiceOrder 1 +PIN -192 -32 LEFT 8 +PINATTR PinName In36 +PINATTR SpiceOrder 2 +PIN -192 32 LEFT 8 +PINATTR PinName In45 +PINATTR SpiceOrder 3 +PIN -48 192 BOTTOM 4 +PINATTR PinName TG45 +PINATTR SpiceOrder 4 +PIN 48 192 BOTTOM 4 +PINATTR PinName TG78 +PINATTR SpiceOrder 5 +PIN -192 96 LEFT 8 +PINATTR PinName In78 +PINATTR SpiceOrder 6 +PIN 144 192 BOTTOM 4 +PINATTR PinName BG78 +PINATTR SpiceOrder 7 +PIN -144 192 BOTTOM 8 +PINATTR PinName BG45 +PINATTR SpiceOrder 8 +PIN 192 96 RIGHT 8 +PINATTR PinName OutN +PINATTR SpiceOrder 9 +PIN 192 -32 RIGHT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 10 +PIN 192 32 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 11 +PIN 192 -96 RIGHT 8 +PINATTR PinName OutP +PINATTR SpiceOrder 12 +PIN 48 -192 TOP 8 +PINATTR PinName BG36 +PINATTR SpiceOrder 13 +PIN -48 -192 TOP 8 +PINATTR PinName BG12 +PINATTR SpiceOrder 14 +PIN -192 -96 LEFT 8 +PINATTR PinName In12 +PINATTR SpiceOrder 15 +PIN -144 -192 TOP 8 +PINATTR PinName TG12 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LT4351.asy b/spice/copy/sym/SpecialFunctions/LT4351.asy new file mode 100755 index 0000000..cb1945a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4351.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 144 -160 -256 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 -22 Center 2 +WINDOW 0 0 -95 Bottom 2 +SYMATTR Value LT4351 +SYMATTR Prefix X +SYMATTR SpiceModel LT4351.sub +SYMATTR Description MOSFET Diode-OR Controller +SYMATTR Value2 LT4351 +PIN 0 -256 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 1 +PIN -160 -176 LEFT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN -96 -256 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 3 +PIN -160 -96 LEFT 8 +PINATTR PinName SW +PINATTR SpiceOrder 4 +PIN 144 32 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 8 +PIN 144 -144 RIGHT 8 +PINATTR PinName Status +PINATTR SpiceOrder 9 +PIN -160 0 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 7 +PIN -160 96 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 6 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 96 -256 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LT4356-1.asy b/spice/copy/sym/SpecialFunctions/LT4356-1.asy new file mode 100755 index 0000000..cd5d29b --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4356-1.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -304 -160 320 112 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 25 Center 2 +SYMATTR Value LT4356-1 +SYMATTR SpiceModel LT4356-1.sub +SYMATTR Description Surge Stopper +SYMATTR Value2 LT4356-1 +SYMATTR Prefix X +PIN 128 112 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 1 +PIN 320 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 256 -160 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 128 -160 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 4 +PIN -48 -160 TOP 8 +PINATTR PinName SNS +PINATTR SpiceOrder 5 +PIN -224 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 +PIN -304 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 320 -16 RIGHT 8 +PINATTR PinName _FLT +PINATTR SpiceOrder 8 +PIN 320 -80 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 9 +PIN -112 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -304 -16 LEFT 8 +PINATTR PinName Aout +PINATTR SpiceOrder 11 +PIN -304 48 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LT4356-2.asy b/spice/copy/sym/SpecialFunctions/LT4356-2.asy new file mode 100755 index 0000000..69e3b61 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4356-2.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -304 -160 320 112 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 25 Center 2 +SYMATTR Value LT4356-2 +SYMATTR SpiceModel LT4356-2.sub +SYMATTR Description Surge Stopper +SYMATTR Value2 LT4356-2 +SYMATTR Prefix X +PIN 128 112 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 1 +PIN 320 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 256 -160 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 128 -160 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 4 +PIN -48 -160 TOP 8 +PINATTR PinName SNS +PINATTR SpiceOrder 5 +PIN -224 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 +PIN -304 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 320 -16 RIGHT 8 +PINATTR PinName _FLT +PINATTR SpiceOrder 8 +PIN 320 -80 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 9 +PIN -112 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -304 -16 LEFT 8 +PINATTR PinName Aout +PINATTR SpiceOrder 11 +PIN -304 48 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LT4356-3.asy b/spice/copy/sym/SpecialFunctions/LT4356-3.asy new file mode 100755 index 0000000..7085790 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4356-3.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -304 -160 320 112 +TEXT 0 -40 Center 2 LT +WINDOW 0 0 -80 Center 2 +WINDOW 3 0 25 Center 2 +SYMATTR Value LT4356-3 +SYMATTR SpiceModel LT4356-3.sub +SYMATTR Description Surge Stopper +SYMATTR Value2 LT4356-3 +SYMATTR Prefix X +PIN 128 112 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 1 +PIN 320 48 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 2 +PIN 256 -160 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 3 +PIN 128 -160 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 4 +PIN -48 -160 TOP 8 +PINATTR PinName SNS +PINATTR SpiceOrder 5 +PIN -224 -160 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 +PIN -304 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN 320 -16 RIGHT 8 +PINATTR PinName _FLT +PINATTR SpiceOrder 8 +PIN 320 -80 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 9 +PIN -112 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN -304 -16 LEFT 8 +PINATTR PinName Aout +PINATTR SpiceOrder 11 +PIN -304 48 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LT4363-1.asy b/spice/copy/sym/SpecialFunctions/LT4363-1.asy new file mode 100755 index 0000000..09fd167 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4363-1.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -128 272 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 62 Center 2 +SYMATTR Value LT4363-1 +SYMATTR SpiceModel LT4363-1.sub +SYMATTR Description Surge Stopper +SYMATTR Value2 LT4363-1 +SYMATTR Prefix X +PIN 272 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 208 -128 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 80 -128 TOP 8 +PINATTR PinName SNS +PINATTR SpiceOrder 3 +PIN -48 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 4 +PIN -176 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN -240 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -240 0 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 7 +PIN -80 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 272 0 RIGHT 8 +PINATTR PinName FLTB +PINATTR SpiceOrder 9 +PIN 272 64 RIGHT 8 +PINATTR PinName ENOUT +PINATTR SpiceOrder 10 +PIN 112 128 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 11 diff --git a/spice/copy/sym/SpecialFunctions/LT4363-2.asy b/spice/copy/sym/SpecialFunctions/LT4363-2.asy new file mode 100755 index 0000000..758c203 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LT4363-2.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -128 272 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 62 Center 2 +SYMATTR Value LT4363-2 +SYMATTR SpiceModel LT4363-2.sub +SYMATTR Description Surge Stopper +SYMATTR Value2 LT4363-2 +SYMATTR Prefix X +PIN 272 -64 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 1 +PIN 208 -128 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 80 -128 TOP 8 +PINATTR PinName SNS +PINATTR SpiceOrder 3 +PIN -48 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 4 +PIN -176 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN -240 -64 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN -240 64 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 7 +PIN -240 0 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 8 +PIN -80 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 272 0 RIGHT 8 +PINATTR PinName FLTB +PINATTR SpiceOrder 10 +PIN 272 64 RIGHT 8 +PINATTR PinName ENOUT +PINATTR SpiceOrder 11 +PIN 112 128 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC1153.asy b/spice/copy/sym/SpecialFunctions/LTC1153.asy new file mode 100755 index 0000000..5a9b307 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1153.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -192 144 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC1153 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1153.sub +SYMATTR Value2 LTC1153 +SYMATTR Description Auto-Reset Electronic Circuit Breaker +PIN -144 -144 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName Ct +PINATTR SpiceOrder 2 +PIN -144 48 LEFT 8 +PINATTR PinName Status +PINATTR SpiceOrder 3 +PIN -144 144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 144 RIGHT 8 +PINATTR PinName SD +PINATTR SpiceOrder 5 +PIN 144 48 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 +PIN 144 -48 RIGHT 8 +PINATTR PinName DS +PINATTR SpiceOrder 7 +PIN 144 -144 RIGHT 8 +PINATTR PinName Vs +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC1232.asy b/spice/copy/sym/SpecialFunctions/LTC1232.asy new file mode 100755 index 0000000..1fe3f67 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1232.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 192 160 -192 -144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1232 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1232.sub +SYMATTR Value2 LTC1232 +SYMATTR Description Microprocessor Supervisory Circuit +PIN -192 -112 LEFT 8 +PINATTR PinName _PB_RST +PINATTR SpiceOrder 1 +PIN -192 -32 LEFT 8 +PINATTR PinName TD +PINATTR SpiceOrder 2 +PIN -192 48 LEFT 8 +PINATTR PinName TOL +PINATTR SpiceOrder 3 +PIN -192 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 192 -112 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 +PIN 192 -32 RIGHT 8 +PINATTR PinName _ST +PINATTR SpiceOrder 7 +PIN 192 128 RIGHT 8 +PINATTR PinName RST +PINATTR SpiceOrder 5 +PIN 192 48 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC1235.asy b/spice/copy/sym/SpecialFunctions/LTC1235.asy new file mode 100755 index 0000000..ff13ddd --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1235.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 300 -224 -320 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1235 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1235.sub +SYMATTR Value2 LTC1235 +SYMATTR Description Microprocessor Supervisory Circuit +PIN -224 -288 LEFT 8 +PINATTR PinName Vbatt +PINATTR SpiceOrder 1 +PIN -224 -208 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -224 -128 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -224 -48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -224 32 LEFT 8 +PINATTR PinName Batt_On +PINATTR SpiceOrder 5 +PIN -224 112 LEFT 8 +PINATTR PinName _Low_Line +PINATTR SpiceOrder 6 +PIN -224 192 LEFT 8 +PINATTR PinName _PB_RST +PINATTR SpiceOrder 7 +PIN -224 272 LEFT 8 +PINATTR PinName Backup +PINATTR SpiceOrder 8 +PIN 224 272 RIGHT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 9 +PIN 224 192 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 10 +PIN 224 112 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 11 +PIN 224 32 RIGHT 8 +PINATTR PinName _CE Out +PINATTR SpiceOrder 12 +PIN 224 -48 RIGHT 8 +PINATTR PinName _CE In +PINATTR SpiceOrder 13 +PIN 224 -128 RIGHT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 14 +PIN 224 -208 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 15 +PIN 224 -288 RIGHT 8 +PINATTR PinName Reset +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC1477.asy b/spice/copy/sym/SpecialFunctions/LTC1477.asy new file mode 100755 index 0000000..bfa3994 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1477.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC1477 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC1477 +SYMATTR Description Single Protected High Side Switch +PIN 144 0 RIGHT 8 +PINATTR PinName VOUT +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 0 -128 TOP 8 +PINATTR PinName Vins +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 32 LEFT 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 6 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/SpecialFunctions/LTC1478.asy b/spice/copy/sym/SpecialFunctions/LTC1478.asy new file mode 100755 index 0000000..300ecbb --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1478.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -128 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC1478 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2.lib +SYMATTR Value2 LTC1477 +SYMATTR Description Dual Protected High Side Switch +PIN 144 0 RIGHT 8 +PINATTR PinName VOUT +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 2 +PIN 0 -128 TOP 8 +PINATTR PinName Vins +PINATTR SpiceOrder 3 +PIN -144 96 LEFT 8 +PINATTR PinName EN +PINATTR SpiceOrder 4 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -144 32 LEFT 8 +PINATTR PinName Vin3 +PINATTR SpiceOrder 6 +PIN -144 -32 LEFT 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/SpecialFunctions/LTC1643AH.asy b/spice/copy/sym/SpecialFunctions/LTC1643AH.asy new file mode 100755 index 0000000..77f5742 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1643AH.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 432 224 -416 -224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1643AH +SYMATTR Prefix X +SYMATTR SpiceModel LTC1643AH.sub +SYMATTR Value2 LTC1643AH +SYMATTR Description PCI-Bus Hot Swap Controller (IC Temp. Not Modeled) +PIN -416 -64 LEFT 8 +PINATTR PinName 12Vin +PINATTR SpiceOrder 1 +PIN -416 0 LEFT 8 +PINATTR PinName VeeIN +PINATTR SpiceOrder 2 +PIN 0 -224 TOP 8 +PINATTR PinName 3Vout +PINATTR SpiceOrder 3 +PIN 432 96 RIGHT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 4 +PIN -416 64 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 5 +PIN -416 128 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 6 +PIN -416 192 LEFT 8 +PINATTR PinName _PWRGD +PINATTR SpiceOrder 7 +PIN -416 -128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -336 -224 TOP 8 +PINATTR PinName 3Vin +PINATTR SpiceOrder 9 +PIN -224 -224 TOP 8 +PINATTR PinName 3Vsense +PINATTR SpiceOrder 10 +PIN -112 -224 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 11 +PIN 224 -224 TOP 8 +PINATTR PinName 5Vsense +PINATTR SpiceOrder 12 +PIN 112 -224 TOP 8 +PINATTR PinName 5Vin +PINATTR SpiceOrder 13 +PIN 352 -224 TOP 8 +PINATTR PinName 5Vout +PINATTR SpiceOrder 14 +PIN 432 -16 RIGHT 8 +PINATTR PinName VeeOUT +PINATTR SpiceOrder 15 +PIN 432 -128 RIGHT 8 +PINATTR PinName 12Vout +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC1643AL-1.asy b/spice/copy/sym/SpecialFunctions/LTC1643AL-1.asy new file mode 100755 index 0000000..7fbeb74 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1643AL-1.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 432 224 -416 -224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1643AL-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1643AL-1.sub +SYMATTR Value2 LTC1643AL-1 +SYMATTR Description PCI-Bus Hot Swap Controller (IC Temp. Not Modeled) +PIN -416 -64 LEFT 8 +PINATTR PinName 12Vin +PINATTR SpiceOrder 1 +PIN -416 0 LEFT 8 +PINATTR PinName VeeIN +PINATTR SpiceOrder 2 +PIN 0 -224 TOP 8 +PINATTR PinName 3Vout +PINATTR SpiceOrder 3 +PIN 432 96 RIGHT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 4 +PIN -416 64 LEFT 8 +PINATTR PinName _ON +PINATTR SpiceOrder 5 +PIN -416 128 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 6 +PIN -416 192 LEFT 8 +PINATTR PinName _PWRGD +PINATTR SpiceOrder 7 +PIN -416 -128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -336 -224 TOP 8 +PINATTR PinName 3Vin +PINATTR SpiceOrder 9 +PIN -224 -224 TOP 8 +PINATTR PinName 3Vsense +PINATTR SpiceOrder 10 +PIN -112 -224 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 11 +PIN 224 -224 TOP 8 +PINATTR PinName 5Vsense +PINATTR SpiceOrder 12 +PIN 112 -224 TOP 8 +PINATTR PinName 5Vin +PINATTR SpiceOrder 13 +PIN 352 -224 TOP 8 +PINATTR PinName 5Vout +PINATTR SpiceOrder 14 +PIN 432 -16 RIGHT 8 +PINATTR PinName VeeOUT +PINATTR SpiceOrder 15 +PIN 432 -128 RIGHT 8 +PINATTR PinName 12Vout +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC1643AL.asy b/spice/copy/sym/SpecialFunctions/LTC1643AL.asy new file mode 100755 index 0000000..7f79924 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1643AL.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 432 224 -416 -224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1643AL +SYMATTR Prefix X +SYMATTR SpiceModel LTC1643AL.sub +SYMATTR Value2 LTC1643AL +SYMATTR Description PCI-Bus Hot Swap Controller (IC Temp. Not Modeled) +PIN -416 -64 LEFT 8 +PINATTR PinName 12Vin +PINATTR SpiceOrder 1 +PIN -416 0 LEFT 8 +PINATTR PinName VeeIN +PINATTR SpiceOrder 2 +PIN 0 -224 TOP 8 +PINATTR PinName 3Vout +PINATTR SpiceOrder 3 +PIN 432 96 RIGHT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 4 +PIN -416 64 LEFT 8 +PINATTR PinName _ON +PINATTR SpiceOrder 5 +PIN -416 128 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 6 +PIN -416 192 LEFT 8 +PINATTR PinName _PWRGD +PINATTR SpiceOrder 7 +PIN -416 -128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -336 -224 TOP 8 +PINATTR PinName 3Vin +PINATTR SpiceOrder 9 +PIN -224 -224 TOP 8 +PINATTR PinName 3Vsense +PINATTR SpiceOrder 10 +PIN -112 -224 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 11 +PIN 224 -224 TOP 8 +PINATTR PinName 5Vsense +PINATTR SpiceOrder 12 +PIN 112 -224 TOP 8 +PINATTR PinName 5Vin +PINATTR SpiceOrder 13 +PIN 352 -224 TOP 8 +PINATTR PinName 5Vout +PINATTR SpiceOrder 14 +PIN 432 -16 RIGHT 8 +PINATTR PinName VeeOUT +PINATTR SpiceOrder 15 +PIN 432 -128 RIGHT 8 +PINATTR PinName 12Vout +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC1644.asy b/spice/copy/sym/SpecialFunctions/LTC1644.asy new file mode 100755 index 0000000..d6312a6 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1644.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 432 224 -416 -224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1644 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1644.sub +SYMATTR Value2 LTC1644 +SYMATTR Description CompactPCI Dual Hot Swap Controller (IC Temp. Not Modeled) +PIN -272 224 BOTTOM 8 +PINATTR PinName 12Vin +PINATTR SpiceOrder 1 +PIN 128 224 BOTTOM 8 +PINATTR PinName VeeIN +PINATTR SpiceOrder 2 +PIN 352 -224 TOP 8 +PINATTR PinName 5Vout +PINATTR SpiceOrder 3 +PIN 432 112 RIGHT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 4 +PIN -416 48 LEFT 8 +PINATTR PinName _ON +PINATTR SpiceOrder 5 +PIN -416 112 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 6 +PIN -416 176 LEFT 8 +PINATTR PinName _PWRGD +PINATTR SpiceOrder 7 +PIN -416 -144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN -416 -16 LEFT 8 +PINATTR PinName _ResetIN +PINATTR SpiceOrder 9 +PIN 432 0 RIGHT 8 +PINATTR PinName _ResetOUT +PINATTR SpiceOrder 10 +PIN 432 -112 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 11 +PIN -416 -80 LEFT 8 +PINATTR PinName Precharge +PINATTR SpiceOrder 12 +PIN 112 -224 TOP 8 +PINATTR PinName 5Vin +PINATTR SpiceOrder 13 +PIN 224 -224 TOP 8 +PINATTR PinName 5Vsense +PINATTR SpiceOrder 14 +PIN -112 -224 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 15 +PIN -224 -224 TOP 8 +PINATTR PinName 3Vsense +PINATTR SpiceOrder 16 +PIN -336 -224 TOP 8 +PINATTR PinName 3Vin +PINATTR SpiceOrder 17 +PIN 0 -224 TOP 8 +PINATTR PinName 3Vout +PINATTR SpiceOrder 18 +PIN 304 224 BOTTOM 8 +PINATTR PinName VeeOUT +PINATTR SpiceOrder 19 +PIN -96 224 BOTTOM 8 +PINATTR PinName 12Vout +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/SpecialFunctions/LTC1645.asy b/spice/copy/sym/SpecialFunctions/LTC1645.asy new file mode 100755 index 0000000..8673264 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1645.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 432 224 -416 -224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1645 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1645.sub +SYMATTR Value2 LTC1645 +SYMATTR Description Dual-Channel Hot Swap Controller/Power Sequencer +PIN -416 0 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 11 +PIN -416 112 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 4 +PIN 432 64 RIGHT 8 +PINATTR PinName Comp+ +PINATTR SpiceOrder 8 +PIN 352 -224 TOP 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 3 +PIN 0 224 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -336 -224 TOP 8 +PINATTR PinName Vcc1 +PINATTR SpiceOrder 14 +PIN -224 -224 TOP 8 +PINATTR PinName Sense1 +PINATTR SpiceOrder 13 +PIN -112 -224 TOP 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 12 +PIN 224 -224 TOP 8 +PINATTR PinName Sense2 +PINATTR SpiceOrder 2 +PIN 112 -224 TOP 8 +PINATTR PinName Vcc2 +PINATTR SpiceOrder 1 +PIN 432 -32 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 5 +PIN 432 160 RIGHT 8 +PINATTR PinName CompOUT +PINATTR SpiceOrder 9 +PIN -416 -96 LEFT 8 +PINATTR PinName _ON +PINATTR SpiceOrder 10 +PIN 432 -128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC1646.asy b/spice/copy/sym/SpecialFunctions/LTC1646.asy new file mode 100755 index 0000000..482ac9c --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1646.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 432 224 -416 -224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC1646 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1646.sub +SYMATTR Value2 LTC1646 +SYMATTR Description CompactPCI Dual Hot Swap Controller (IC Temp. Not Modeled) +PIN 432 0 RIGHT 8 +PINATTR PinName _ResetOUT +PINATTR SpiceOrder 1 +PIN 432 112 RIGHT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 2 +PIN -416 112 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 3 +PIN -416 176 LEFT 8 +PINATTR PinName _PWRGD +PINATTR SpiceOrder 4 +PIN 352 -224 TOP 8 +PINATTR PinName 5Vout +PINATTR SpiceOrder 5 +PIN -416 -144 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 0 -224 TOP 8 +PINATTR PinName 3Vout +PINATTR SpiceOrder 7 +PIN -336 -224 TOP 8 +PINATTR PinName 3Vin +PINATTR SpiceOrder 8 +PIN -224 -224 TOP 8 +PINATTR PinName 3Vsense +PINATTR SpiceOrder 9 +PIN -112 -224 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 10 +PIN 224 -224 TOP 8 +PINATTR PinName 5Vsense +PINATTR SpiceOrder 11 +PIN 112 -224 TOP 8 +PINATTR PinName 5Vin +PINATTR SpiceOrder 12 +PIN -416 -80 LEFT 8 +PINATTR PinName Precharge +PINATTR SpiceOrder 13 +PIN 432 -112 RIGHT 8 +PINATTR PinName Drive +PINATTR SpiceOrder 14 +PIN -416 48 LEFT 8 +PINATTR PinName _ON +PINATTR SpiceOrder 15 +PIN -416 -16 LEFT 8 +PINATTR PinName _ResetIN +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC1696.asy b/spice/copy/sym/SpecialFunctions/LTC1696.asy new file mode 100755 index 0000000..d1551f7 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1696.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -144 160 144 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC1696 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1696.sub +SYMATTR Value2 LTC1696 +SYMATTR Description Overvoltage Protection Controller +PIN 160 -96 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 1 +PIN 160 96 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -160 -96 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -160 0 LEFT 8 +PINATTR PinName Out +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 5 +PIN -160 96 LEFT 8 +PINATTR PinName _Timer/Reset +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC1726-2.5.asy b/spice/copy/sym/SpecialFunctions/LTC1726-2.5.asy new file mode 100755 index 0000000..4b1bd96 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1726-2.5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 80 -144 -208 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 -22 Center 2 +WINDOW 0 0 -95 Bottom 2 +SYMATTR Value LTC1726-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1726-2.5.sub +SYMATTR Description Triple Supply Monitor uP Supervisor with Adjustable Reset and Watchdog Timer +SYMATTR Value2 LTC1726-2.5 +PIN 0 -208 TOP 8 +PINATTR PinName VCC3 +PINATTR SpiceOrder 1 +PIN -96 -208 TOP 8 +PINATTR PinName VCC25 +PINATTR SpiceOrder 2 +PIN 96 -208 TOP 8 +PINATTR PinName VCCA +PINATTR SpiceOrder 3 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 32 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 5 +PIN 144 -96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN -144 32 LEFT 8 +PINATTR PinName WT +PINATTR SpiceOrder 7 +PIN -144 -96 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC1726-5.asy b/spice/copy/sym/SpecialFunctions/LTC1726-5.asy new file mode 100755 index 0000000..62b0361 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1726-5.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 80 -144 -208 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 -22 Center 2 +WINDOW 0 0 -95 Bottom 2 +SYMATTR Value LTC1726-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1726-5.sub +SYMATTR Description Triple Supply Monitor uP Supervisor with Adjustable Reset and Watchdog Timer +SYMATTR Value2 LTC1726-5 +PIN 0 -208 TOP 8 +PINATTR PinName VCC3 +PINATTR SpiceOrder 1 +PIN -96 -208 TOP 8 +PINATTR PinName VCC5 +PINATTR SpiceOrder 2 +PIN 96 -208 TOP 8 +PINATTR PinName VCCA +PINATTR SpiceOrder 3 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 144 32 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 5 +PIN 144 -96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN -144 32 LEFT 8 +PINATTR PinName WT +PINATTR SpiceOrder 7 +PIN -144 -96 LEFT 8 +PINATTR PinName RT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC1727-2.5.asy b/spice/copy/sym/SpecialFunctions/LTC1727-2.5.asy new file mode 100755 index 0000000..9f587ad --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1727-2.5.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 128 -112 -128 +ARC Normal -16 -144 16 -112 -16 -128 16 -128 +TEXT 0 0 Center 2 LT +WINDOW 3 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value LTC1727-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1727-2.5.sub +SYMATTR Description µPower Precision Triple Supply Monitor in 8-Lead MSOP +SYMATTR Value2 LTC1727-2.5 +PIN -112 -96 LEFT 8 +PINATTR PinName Vcc3 +PINATTR SpiceOrder 1 +PIN -112 -32 LEFT 8 +PINATTR PinName Vcc2.5 +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VccA +PINATTR SpiceOrder 3 +PIN -112 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 96 RIGHT 8 +PINATTR PinName CompA +PINATTR SpiceOrder 5 +PIN 112 32 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN 112 -32 RIGHT 8 +PINATTR PinName Comp2.5 +PINATTR SpiceOrder 7 +PIN 112 -96 RIGHT 8 +PINATTR PinName Comp3 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC1727-5.asy b/spice/copy/sym/SpecialFunctions/LTC1727-5.asy new file mode 100755 index 0000000..2adc7c4 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1727-5.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 128 -112 -128 +ARC Normal -16 -144 16 -112 -16 -128 16 -128 +TEXT 0 0 Center 2 LT +WINDOW 3 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value LTC1727-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1727-5.sub +SYMATTR Description µPower Precision Triple Supply Monitor in 8-Lead MSOP +SYMATTR Value2 LTC1727-5 +PIN -112 -96 LEFT 8 +PINATTR PinName Vcc3 +PINATTR SpiceOrder 1 +PIN -112 -32 LEFT 8 +PINATTR PinName Vcc5 +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VccA +PINATTR SpiceOrder 3 +PIN -112 96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 96 RIGHT 8 +PINATTR PinName CompA +PINATTR SpiceOrder 5 +PIN 112 32 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 6 +PIN 112 -32 RIGHT 8 +PINATTR PinName Comp5 +PINATTR SpiceOrder 7 +PIN 112 -96 RIGHT 8 +PINATTR PinName Comp3 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC1728-1.8.asy b/spice/copy/sym/SpecialFunctions/LTC1728-1.8.asy new file mode 100755 index 0000000..0c29259 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1728-1.8.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 64 -112 -128 +ARC Normal -16 -144 16 -112 -16 -128 16 -128 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 0 Center 2 +WINDOW 0 0 -128 Bottom 2 +SYMATTR Value LTC1728-1.8 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1728-1.8.sub +SYMATTR Description µPower Precision Triple Supply Monitor in 5 lead SOT-23 +SYMATTR Value2 LTC1728-1.8 +PIN -112 -96 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 1 +PIN -112 -32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VccA +PINATTR SpiceOrder 3 +PIN 112 32 RIGHT 8 +PINATTR PinName Vcc1.8 +PINATTR SpiceOrder 4 +PIN 112 -96 RIGHT 8 +PINATTR PinName Vcc3 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC1728-2.5.asy b/spice/copy/sym/SpecialFunctions/LTC1728-2.5.asy new file mode 100755 index 0000000..ab1f82e --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1728-2.5.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 64 -112 -128 +ARC Normal -16 -144 16 -112 -16 -128 16 -128 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 0 Center 2 +WINDOW 0 0 -128 Bottom 2 +SYMATTR Value LTC1728-2.5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1728-2.5.sub +SYMATTR Description uPower Precidiom Triple Supply Monitor in 5-lead SOT-23 +SYMATTR Value2 LTC1728-2.5 +PIN -112 -96 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 1 +PIN -112 -32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VccA +PINATTR SpiceOrder 3 +PIN 112 32 RIGHT 8 +PINATTR PinName Vcc2.5 +PINATTR SpiceOrder 4 +PIN 112 -96 RIGHT 8 +PINATTR PinName Vcc3 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC1728-3.3.asy b/spice/copy/sym/SpecialFunctions/LTC1728-3.3.asy new file mode 100755 index 0000000..bfd9f09 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1728-3.3.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 64 -112 -128 +ARC Normal -16 -144 16 -112 -16 -128 16 -128 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 0 Center 2 +WINDOW 0 0 -128 Bottom 2 +SYMATTR Value LTC1728-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1728-3.3.sub +SYMATTR Description µPower Precision Triple Supply Monitor in 5 lead SOT-23 +SYMATTR Value2 LTC1728-3.3 +PIN -112 -96 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 1 +PIN -112 -32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VccA +PINATTR SpiceOrder 3 +PIN 112 32 RIGHT 8 +PINATTR PinName Vcc1.8 +PINATTR SpiceOrder 4 +PIN 112 -96 RIGHT 8 +PINATTR PinName Vcc3 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC1728-5.asy b/spice/copy/sym/SpecialFunctions/LTC1728-5.asy new file mode 100755 index 0000000..92a7db5 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1728-5.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 64 -112 -128 +ARC Normal -16 -144 16 -112 -16 -128 16 -128 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 0 Center 2 +WINDOW 0 1 -128 Bottom 2 +SYMATTR Value LTC1728-5 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1728-5.sub +SYMATTR Description µPower Precision Triple Supply Monitor in 5-lead SOT-23 +SYMATTR Value2 LTC1728-5 +PIN -112 -96 LEFT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 1 +PIN -112 -32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 32 LEFT 8 +PINATTR PinName VccA +PINATTR SpiceOrder 3 +PIN 112 32 RIGHT 8 +PINATTR PinName Vcc5 +PINATTR SpiceOrder 4 +PIN 112 -96 RIGHT 8 +PINATTR PinName Vcc3 +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC1799.asy b/spice/copy/sym/SpecialFunctions/LTC1799.asy new file mode 100755 index 0000000..3c5411c --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1799.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC1799 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1799.sub +SYMATTR Value2 LTC1799 +SYMATTR Description 1KHz to 33MHz Resistor Set SOT-23 Oscillator +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC1966.asy b/spice/copy/sym/SpecialFunctions/LTC1966.asy new file mode 100755 index 0000000..663e89c --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1966.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 112 -112 -112 +TEXT 0 -24 Center 2 LT +WINDOW 3 0 23 Center 2 +WINDOW 0 59 -112 Bottom 2 +SYMATTR Value LTC1966 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1966.lib +SYMATTR Value2 LTC1966 +SYMATTR Description Precision µPower, Delta-Sigma RMS-to-DC Converter +PIN 48 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 -48 LEFT 8 +PINATTR PinName In1 +PINATTR SpiceOrder 2 +PIN -112 48 LEFT 8 +PINATTR PinName In2 +PINATTR SpiceOrder 3 +PIN -48 112 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 112 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 112 48 RIGHT 8 +PINATTR PinName OutRtn +PINATTR SpiceOrder 6 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/SpecialFunctions/LTC1967.asy b/spice/copy/sym/SpecialFunctions/LTC1967.asy new file mode 100755 index 0000000..8c526eb --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1967.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 112 -112 -112 +TEXT 0 -24 Center 2 LT +WINDOW 3 0 23 Center 2 +WINDOW 0 62 -112 Bottom 2 +SYMATTR Value LTC1967 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1966.lib +SYMATTR Value2 LTC1967 +SYMATTR Description Precision Extended Bandwidth RMS-to-DC Converter +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 -48 LEFT 8 +PINATTR PinName In1 +PINATTR SpiceOrder 2 +PIN -112 48 LEFT 8 +PINATTR PinName In2 +PINATTR SpiceOrder 3 +PIN 112 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 112 48 RIGHT 8 +PINATTR PinName OutRtn +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC1968.asy b/spice/copy/sym/SpecialFunctions/LTC1968.asy new file mode 100755 index 0000000..3639bdd --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC1968.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 112 112 -112 -112 +TEXT 0 -24 Center 2 LT +WINDOW 3 0 23 Center 2 +WINDOW 0 56 -111 Bottom 2 +SYMATTR Value LTC1968 +SYMATTR Prefix X +SYMATTR SpiceModel LTC1966.lib +SYMATTR Value2 LTC1968 +SYMATTR Description Precision Wide Bandwidth RMS-to-DC Converter +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -112 -48 LEFT 8 +PINATTR PinName In1 +PINATTR SpiceOrder 2 +PIN -112 48 LEFT 8 +PINATTR PinName In2 +PINATTR SpiceOrder 3 +PIN 112 -48 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 112 48 RIGHT 8 +PINATTR PinName OutRtn +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC2641-12.asy b/spice/copy/sym/SpecialFunctions/LTC2641-12.asy new file mode 100755 index 0000000..d46ef7c --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2641-12.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 128 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2641-12 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2641-12.sub +SYMATTR Value2 LTC2641-12 +SYMATTR Description 12-Bit Vout DAC in 3mm X 3mm DFN +PIN 48 -144 TOP 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName _CS +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName DIN +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _CLR +PINATTR SpiceOrder 5 +PIN 128 -16 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN -64 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2641-14.asy b/spice/copy/sym/SpecialFunctions/LTC2641-14.asy new file mode 100755 index 0000000..f49c226 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2641-14.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 63 Center 2 +SYMATTR Value LTC2641-14 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2641-14.sub +SYMATTR Value2 LTC2641-14 +SYMATTR Description 14-Bit Vout DAC in 3mm X 3mm DFN +PIN 64 -144 TOP 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName _CS +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName DIN +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _CLR +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN -48 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2641-16.asy b/spice/copy/sym/SpecialFunctions/LTC2641-16.asy new file mode 100755 index 0000000..b57b7e3 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2641-16.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2641-16 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2641-16.sub +SYMATTR Value2 LTC2641-16 +SYMATTR Description 16-Bit Vout DAC in 3mm X 3mm DFN +PIN 64 -144 TOP 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName _CS +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName DIN +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _CLR +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN -64 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2641A-16.asy b/spice/copy/sym/SpecialFunctions/LTC2641A-16.asy new file mode 100755 index 0000000..5d284bd --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2641A-16.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 1 -63 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2641A-16 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2641A-16.sub +SYMATTR Value2 LTC2641A-16 +SYMATTR Description 16-Bit Vout DAC in 3mm X 3mm DFN +PIN 64 -144 TOP 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName _CS +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName DIN +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _CLR +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN -64 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2642-12.asy b/spice/copy/sym/SpecialFunctions/LTC2642-12.asy new file mode 100755 index 0000000..c588a36 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2642-12.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2642-12 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2642-12.sub +SYMATTR Value2 LTC2642-12 +SYMATTR Description 12-Bit Vout DACs in 3mm X 3mm DFN +PIN 48 -144 TOP 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName _CS +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName DIN +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _CLR +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName INV +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 8 +PIN -64 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC2642-14.asy b/spice/copy/sym/SpecialFunctions/LTC2642-14.asy new file mode 100755 index 0000000..bb84b8a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2642-14.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC2642-14 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2642-14.sub +SYMATTR Value2 LTC2642-14 +SYMATTR Description 14-Bit Vout DACs in 3mm X 3mm DFN +PIN 48 -144 TOP 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName _CS +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName DIN +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _CLR +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName INV +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 8 +PIN -64 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC2642-16.asy b/spice/copy/sym/SpecialFunctions/LTC2642-16.asy new file mode 100755 index 0000000..781cdb6 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2642-16.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -144 -144 144 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 63 Center 2 +SYMATTR Value LTC2642-16 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2642-16.sub +SYMATTR Value2 LTC2642-16 +SYMATTR Description 16-Bit Vout DACs in 3mm X 3mm DFN +PIN 48 -144 TOP 8 +PINATTR PinName REF +PINATTR SpiceOrder 1 +PIN -144 -96 LEFT 8 +PINATTR PinName _CS +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName SCLK +PINATTR SpiceOrder 3 +PIN -144 32 LEFT 8 +PINATTR PinName DIN +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _CLR +PINATTR SpiceOrder 5 +PIN 144 96 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 8 +PINATTR PinName INV +PINATTR SpiceOrder 7 +PIN 144 -96 RIGHT 8 +PINATTR PinName Rfb +PINATTR SpiceOrder 8 +PIN -64 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 9 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC2862-1.asy b/spice/copy/sym/SpecialFunctions/LTC2862-1.asy new file mode 100755 index 0000000..adf49e3 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2862-1.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType CELL +LINE Normal -32 96 -32 32 +LINE Normal 48 64 -32 96 +LINE Normal -32 32 48 64 +LINE Normal 48 -112 48 -48 +LINE Normal -32 -80 48 -112 +LINE Normal 48 -48 -32 -80 +LINE Normal -128 -80 -32 -80 +LINE Normal 26 80 102 80 +LINE Normal 23 74 26 80 +LINE Normal -32 64 -128 64 +LINE Normal -39 -32 -128 -32 +LINE Normal -39 0 -128 0 +LINE Normal 1 -39 1 -66 +LINE Normal 1 45 1 7 +LINE Normal 102 80 102 -96 +LINE Normal 60 -64 72 -64 +LINE Normal 102 -96 48 -96 +LINE Normal 102 -48 128 -48 +LINE Normal 72 48 30 48 +LINE Normal 72 -64 72 48 +LINE Normal 72 16 128 16 +RECTANGLE Normal 128 160 -128 -160 +RECTANGLE Normal 46 7 -39 -39 +CIRCLE Normal 60 -58 48 -69 +CIRCLE Normal 30 54 18 42 +CIRCLE Normal 73 17 71 15 +CIRCLE Normal 75 19 69 13 +CIRCLE Normal 74 18 70 14 +CIRCLE Normal 103 -47 101 -49 +CIRCLE Normal 105 -45 99 -51 +CIRCLE Normal 104 -46 100 -50 +TEXT 0 64 Center 2 TX +TEXT 16 -80 Center 2 RX +TEXT -124 -94 Left 2 RO +TEXT -124 51 Left 2 DI +TEXT -124 -46 Left 2 _RE +TEXT -124 -14 Left 2 DE +TEXT 124 -61 Right 2 A +TEXT 124 3 Right 2 B +TEXT 2 -15 Center 2 LOGIC +WINDOW 3 80 176 Center 2 +WINDOW 0 64 -176 Center 2 +SYMATTR Value LTC2862-1 +SYMATTR Prefix X +SYMATTR Description +/- 60V Fault Protected 3V to 5.5V RS485/RS422 Transceivers +SYMATTR SpiceModel LTC2862-1.lib +SYMATTR Value2 LTC2862-1 +PIN -128 -80 NONE 8 +PINATTR PinName RO +PINATTR SpiceOrder 1 +PIN -128 -32 NONE 8 +PINATTR PinName _RE +PINATTR SpiceOrder 2 +PIN -128 0 NONE 8 +PINATTR PinName DE +PINATTR SpiceOrder 3 +PIN -128 64 NONE 8 +PINATTR PinName DI +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 4 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 16 NONE 8 +PINATTR PinName B +PINATTR SpiceOrder 10 +PIN 128 -48 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 11 +PIN 0 -160 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2862-2.asy b/spice/copy/sym/SpecialFunctions/LTC2862-2.asy new file mode 100755 index 0000000..1b44139 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2862-2.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType CELL +LINE Normal -32 96 -32 32 +LINE Normal 48 64 -32 96 +LINE Normal -32 32 48 64 +LINE Normal 48 -112 48 -48 +LINE Normal -32 -80 48 -112 +LINE Normal 48 -48 -32 -80 +LINE Normal -128 -80 -32 -80 +LINE Normal 26 80 102 80 +LINE Normal 23 74 26 80 +LINE Normal -32 64 -128 64 +LINE Normal -39 -32 -128 -32 +LINE Normal -39 0 -128 0 +LINE Normal 1 -39 1 -67 +LINE Normal 1 45 1 7 +LINE Normal 102 80 102 -96 +LINE Normal 59 -64 72 -64 +LINE Normal 102 -96 48 -96 +LINE Normal 102 -48 128 -48 +LINE Normal 72 48 30 48 +LINE Normal 72 -64 72 48 +LINE Normal 72 16 128 16 +RECTANGLE Normal 128 160 -128 -160 +RECTANGLE Normal 46 7 -39 -39 +CIRCLE Normal 59 -58 48 -69 +CIRCLE Normal 30 54 18 42 +CIRCLE Normal 103 -47 101 -49 +CIRCLE Normal 104 -46 100 -50 +CIRCLE Normal 105 -45 99 -51 +CIRCLE Normal 73 17 71 15 +CIRCLE Normal 74 18 70 14 +CIRCLE Normal 75 19 69 13 +TEXT 0 64 Center 2 TX +TEXT 16 -80 Center 2 RX +TEXT -124 -94 Left 2 RO +TEXT -124 51 Left 2 DI +TEXT -124 -46 Left 2 _RE +TEXT -124 -14 Left 2 DE +TEXT 124 -61 Right 2 A +TEXT 124 3 Right 2 B +TEXT 2 -15 Center 2 LOGIC +WINDOW 3 80 176 Center 2 +WINDOW 0 64 -176 Center 2 +SYMATTR Value LTC2862-2 +SYMATTR Prefix X +SYMATTR Description +/- 60V Fault Protected 3V to 5.5V RS485/RS422 Transceivers +SYMATTR SpiceModel LTC2862-2.lib +SYMATTR Value2 LTC2862-2 +PIN -128 -80 NONE 8 +PINATTR PinName RO +PINATTR SpiceOrder 1 +PIN -128 -32 NONE 8 +PINATTR PinName _RE +PINATTR SpiceOrder 2 +PIN -128 0 NONE 8 +PINATTR PinName DE +PINATTR SpiceOrder 3 +PIN -128 64 NONE 8 +PINATTR PinName DI +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 4 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 16 NONE 8 +PINATTR PinName B +PINATTR SpiceOrder 10 +PIN 128 -48 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 11 +PIN 0 -160 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2863-1.asy b/spice/copy/sym/SpecialFunctions/LTC2863-1.asy new file mode 100755 index 0000000..205fc29 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2863-1.asy @@ -0,0 +1,58 @@ +Version 4 +SymbolType CELL +LINE Normal -32 96 -32 32 +LINE Normal 48 64 -32 96 +LINE Normal -32 32 48 64 +LINE Normal 48 -112 48 -48 +LINE Normal -32 -80 48 -112 +LINE Normal 48 -48 -32 -80 +LINE Normal 59 -64 128 -64 +LINE Normal -128 -80 -32 -80 +LINE Normal 48 -96 128 -96 +LINE Normal 30 48 128 48 +LINE Normal 26 80 128 80 +LINE Normal 23 74 26 80 +LINE Normal -32 64 -128 64 +RECTANGLE Normal 128 160 -128 -160 +CIRCLE Normal 59 -58 48 -69 +CIRCLE Normal 30 54 18 42 +TEXT 0 64 Center 2 TX +TEXT 16 -80 Center 2 RX +TEXT -124 -93 Left 2 RO +TEXT -124 51 Left 2 DI +TEXT 124 -109 Right 2 A +TEXT 124 -77 Right 2 B +TEXT 124 67 Right 2 Y +TEXT 124 35 Right 2 Z +TEXT 0 -8 Center 2 LT +WINDOW 3 80 176 Center 2 +WINDOW 0 64 -176 Center 2 +SYMATTR Value LTC2863-1 +SYMATTR Prefix X +SYMATTR Description +/- 60V Fault Protected 3V to 5.5V RS485/RS422 Transceivers +SYMATTR SpiceModel LTC2863-1.lib +SYMATTR Value2 LTC2863-1 +PIN -128 -80 NONE 8 +PINATTR PinName RO +PINATTR SpiceOrder 1 +PIN -128 64 NONE 8 +PINATTR PinName DI +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 4 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 80 NONE 8 +PINATTR PinName Y +PINATTR SpiceOrder 8 +PIN 128 48 NONE 8 +PINATTR PinName Z +PINATTR SpiceOrder 9 +PIN 128 -64 NONE 8 +PINATTR PinName B +PINATTR SpiceOrder 10 +PIN 128 -96 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 11 +PIN 0 -160 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2863-2.asy b/spice/copy/sym/SpecialFunctions/LTC2863-2.asy new file mode 100755 index 0000000..0f5e1a2 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2863-2.asy @@ -0,0 +1,58 @@ +Version 4 +SymbolType CELL +LINE Normal -32 96 -32 32 +LINE Normal 48 64 -32 96 +LINE Normal -32 32 48 64 +LINE Normal 48 -112 48 -48 +LINE Normal -32 -80 48 -112 +LINE Normal 48 -48 -32 -80 +LINE Normal 59 -64 128 -64 +LINE Normal -128 -80 -32 -80 +LINE Normal 47 -96 128 -96 +LINE Normal 30 48 128 48 +LINE Normal 26 80 128 80 +LINE Normal 23 74 26 80 +LINE Normal -32 64 -128 64 +RECTANGLE Normal 128 160 -128 -160 +CIRCLE Normal 59 -58 48 -69 +CIRCLE Normal 30 54 18 42 +TEXT 0 64 Center 2 TX +TEXT 16 -80 Center 2 RX +TEXT -124 -94 Left 2 RO +TEXT -124 51 Left 2 DI +TEXT 124 -109 Right 2 A +TEXT 124 -77 Right 2 B +TEXT 124 67 Right 2 Y +TEXT 124 34 Right 2 Z +TEXT 0 -8 Center 2 LT +WINDOW 3 80 176 Center 2 +WINDOW 0 64 -176 Center 2 +SYMATTR Value LTC2863-2 +SYMATTR Prefix X +SYMATTR Description +/- 60V Fault Protected 3V to 5.5V RS485/RS422 Transceivers +SYMATTR SpiceModel LTC2863-2.lib +SYMATTR Value2 LTC2863-2 +PIN -128 -80 NONE 8 +PINATTR PinName RO +PINATTR SpiceOrder 1 +PIN -128 64 NONE 8 +PINATTR PinName DI +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 4 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 80 NONE 8 +PINATTR PinName Y +PINATTR SpiceOrder 8 +PIN 128 48 NONE 8 +PINATTR PinName Z +PINATTR SpiceOrder 9 +PIN 128 -64 NONE 8 +PINATTR PinName B +PINATTR SpiceOrder 10 +PIN 128 -96 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 11 +PIN 0 -160 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2864-1.asy b/spice/copy/sym/SpecialFunctions/LTC2864-1.asy new file mode 100755 index 0000000..5215bc0 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2864-1.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +LINE Normal -31 95 -31 31 +LINE Normal 49 63 -31 95 +LINE Normal -31 31 49 63 +LINE Normal 47 -111 47 -47 +LINE Normal -32 -80 47 -111 +LINE Normal 47 -47 -32 -80 +LINE Normal 58 -64 128 -64 +LINE Normal -128 -80 -32 -80 +LINE Normal 47 -96 128 -96 +LINE Normal 33 48 128 48 +LINE Normal 26 80 128 80 +LINE Normal 23 73 26 80 +LINE Normal -31 64 -128 64 +LINE Normal -39 -32 -128 -32 +LINE Normal -39 0 -128 0 +LINE Normal 1 -39 1 -66 +LINE Normal 1 44 1 7 +RECTANGLE Normal 128 160 -128 -160 +RECTANGLE Normal 46 7 -39 -39 +CIRCLE Normal 58 -58 47 -69 +CIRCLE Normal 33 54 21 42 +TEXT 0 64 Center 2 TX +TEXT 16 -80 Center 2 RX +TEXT -124 -94 Left 2 RO +TEXT -124 51 Left 2 DI +TEXT -123 -46 Left 2 _RE +TEXT -124 -14 Left 2 DE +TEXT 124 -109 Right 2 A +TEXT 124 -78 Right 2 B +TEXT 124 67 Right 2 Y +TEXT 124 34 Right 2 Z +TEXT 2 -15 Center 2 LOGIC +WINDOW 3 80 176 Center 2 +WINDOW 0 64 -176 Center 2 +SYMATTR Value LTC2864-1 +SYMATTR Prefix X +SYMATTR Description +/- 60V Fault Protected 3V to 5.5V RS485/RS422 Transceivers +SYMATTR SpiceModel LTC2864-1.lib +SYMATTR Value2 LTC2864-1 +PIN -128 -80 NONE 8 +PINATTR PinName RO +PINATTR SpiceOrder 1 +PIN -128 -32 NONE 8 +PINATTR PinName _RE +PINATTR SpiceOrder 2 +PIN -128 0 NONE 8 +PINATTR PinName DE +PINATTR SpiceOrder 3 +PIN -128 64 NONE 8 +PINATTR PinName DI +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 4 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 80 NONE 8 +PINATTR PinName Y +PINATTR SpiceOrder 8 +PIN 128 48 NONE 8 +PINATTR PinName Z +PINATTR SpiceOrder 9 +PIN 128 -64 NONE 8 +PINATTR PinName B +PINATTR SpiceOrder 10 +PIN 128 -96 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 11 +PIN 0 -160 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2864-2.asy b/spice/copy/sym/SpecialFunctions/LTC2864-2.asy new file mode 100755 index 0000000..594d348 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2864-2.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +LINE Normal -31 95 -31 31 +LINE Normal 49 63 -31 95 +LINE Normal -31 31 49 63 +LINE Normal 47 -111 47 -47 +LINE Normal -32 -80 47 -111 +LINE Normal 47 -47 -32 -80 +LINE Normal 58 -64 128 -64 +LINE Normal -128 -80 -32 -80 +LINE Normal 47 -96 128 -96 +LINE Normal 33 48 128 48 +LINE Normal 26 80 128 80 +LINE Normal 23 73 26 80 +LINE Normal -31 64 -128 64 +LINE Normal -39 -32 -128 -32 +LINE Normal -39 0 -128 0 +LINE Normal 1 -39 1 -66 +LINE Normal 1 44 1 7 +RECTANGLE Normal 128 160 -128 -160 +RECTANGLE Normal 46 7 -39 -39 +CIRCLE Normal 58 -58 47 -69 +CIRCLE Normal 33 54 21 42 +TEXT 0 64 Center 2 TX +TEXT 16 -80 Center 2 RX +TEXT -124 -94 Left 2 RO +TEXT -124 51 Left 2 DI +TEXT -124 -46 Left 2 _RE +TEXT -124 -14 Left 2 DE +TEXT 124 -109 Right 2 A +TEXT 124 -77 Right 2 B +TEXT 124 67 Right 2 Y +TEXT 124 34 Right 2 Z +TEXT 2 -15 Center 2 LOGIC +WINDOW 3 80 176 Center 2 +WINDOW 0 64 -176 Center 2 +SYMATTR Value LTC2864-2 +SYMATTR Prefix X +SYMATTR Description +/- 60V Fault Protected 3V to 5.5V RS485/RS422 Transceivers +SYMATTR SpiceModel LTC2864-2.lib +SYMATTR Value2 LTC2864-2 +PIN -128 -80 NONE 8 +PINATTR PinName RO +PINATTR SpiceOrder 1 +PIN -128 -32 NONE 8 +PINATTR PinName _RE +PINATTR SpiceOrder 2 +PIN -128 0 NONE 8 +PINATTR PinName DE +PINATTR SpiceOrder 3 +PIN -128 64 NONE 8 +PINATTR PinName DI +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 4 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 128 80 NONE 8 +PINATTR PinName Y +PINATTR SpiceOrder 8 +PIN 128 48 NONE 8 +PINATTR PinName Z +PINATTR SpiceOrder 9 +PIN 128 -64 NONE 8 +PINATTR PinName B +PINATTR SpiceOrder 10 +PIN 128 -96 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 11 +PIN 0 -160 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2865.asy b/spice/copy/sym/SpecialFunctions/LTC2865.asy new file mode 100755 index 0000000..ab22086 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2865.asy @@ -0,0 +1,81 @@ +Version 4 +SymbolType CELL +LINE Normal -31 95 -31 31 +LINE Normal 49 63 -31 95 +LINE Normal -31 31 49 63 +LINE Normal 47 -111 47 -47 +LINE Normal -32 -80 47 -111 +LINE Normal 47 -47 -32 -80 +LINE Normal 60 -64 128 -64 +LINE Normal -128 -80 -32 -80 +LINE Normal 47 -96 128 -96 +LINE Normal 33 48 128 48 +LINE Normal 26 80 128 80 +LINE Normal 23 73 26 80 +LINE Normal -31 64 -128 64 +LINE Normal 2 112 -128 112 +LINE Normal 2 82 2 112 +LINE Normal -39 -32 -128 -32 +LINE Normal -39 0 -128 0 +LINE Normal 1 -39 1 -66 +LINE Normal 1 44 1 7 +RECTANGLE Normal 128 160 -128 -160 +RECTANGLE Normal 46 7 -39 -39 +CIRCLE Normal 60 -58 47 -69 +CIRCLE Normal 33 54 21 42 +TEXT 0 64 Center 2 TX +TEXT 16 -80 Center 2 RX +TEXT -124 -128 Left 2 VL +TEXT -124 -94 Left 2 RO +TEXT -124 51 Left 2 DI +TEXT -124 100 Left 2 _SLO +TEXT -124 -46 Left 2 _RE +TEXT -123 -14 Left 2 DE +TEXT 124 -109 Right 2 A +TEXT 124 -77 Right 2 B +TEXT 124 66 Right 2 Y +TEXT 124 34 Right 2 Z +TEXT 2 -15 Center 2 LOGIC +WINDOW 3 80 176 Center 2 +WINDOW 0 64 -176 Center 2 +SYMATTR Value LTC2865 +SYMATTR Prefix X +SYMATTR Description +/- 60V Fault Protected 3V to 5.5V RS485/RS422 Transceivers +SYMATTR SpiceModel LTC2865.lib +SYMATTR Value2 LTC2865 +PIN -128 -80 NONE 8 +PINATTR PinName RO +PINATTR SpiceOrder 1 +PIN -128 -32 NONE 8 +PINATTR PinName _RE +PINATTR SpiceOrder 2 +PIN -128 0 NONE 8 +PINATTR PinName DE +PINATTR SpiceOrder 3 +PIN -128 64 NONE 8 +PINATTR PinName DI +PINATTR SpiceOrder 4 +PIN -128 -128 NONE 8 +PINATTR PinName VL +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 4 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -128 112 NONE 8 +PINATTR PinName _SLO +PINATTR SpiceOrder 7 +PIN 128 80 NONE 8 +PINATTR PinName Y +PINATTR SpiceOrder 8 +PIN 128 48 NONE 8 +PINATTR PinName Z +PINATTR SpiceOrder 9 +PIN 128 -64 NONE 8 +PINATTR PinName B +PINATTR SpiceOrder 10 +PIN 128 -96 NONE 8 +PINATTR PinName A +PINATTR SpiceOrder 11 +PIN 0 -160 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2875.asy b/spice/copy/sym/SpecialFunctions/LTC2875.asy new file mode 100755 index 0000000..0f4fd00 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2875.asy @@ -0,0 +1,72 @@ +Version 4 +SymbolType CELL +LINE Normal -48 96 -48 32 +LINE Normal 32 64 -48 96 +LINE Normal -48 32 32 64 +LINE Normal 33 -96 33 -32 +LINE Normal -47 -64 33 -96 +LINE Normal 33 -32 -47 -64 +LINE Normal -160 -64 -47 -64 +LINE Normal 8 80 80 80 +LINE Normal 7 48 1 51 +LINE Normal -48 64 -160 64 +LINE Normal -64 0 -160 0 +LINE Normal -16 -16 -16 -51 +LINE Normal -16 45 -16 16 +LINE Normal 80 80 80 -80 +LINE Normal 33 -48 56 -48 +LINE Normal 80 -80 42 -80 +LINE Normal 56 -32 160 -32 +LINE Normal 56 48 7 48 +LINE Normal 56 -48 56 48 +LINE Normal 80 32 160 32 +RECTANGLE Normal 160 144 -160 -144 +RECTANGLE Normal 32 16 -64 -16 +CIRCLE Normal 57 -31 55 -33 +CIRCLE Normal 58 -30 54 -34 +CIRCLE Normal 59 -29 53 -35 +CIRCLE Normal 81 33 79 31 +CIRCLE Normal 82 34 78 30 +CIRCLE Normal 83 35 77 29 +CIRCLE Normal 8 85 -1 76 +CIRCLE Normal 42 -75 33 -84 +TEXT -16 64 Center 2 TX +TEXT 1 -64 Center 2 RX +TEXT -156 -78 Left 2 RXD +TEXT -156 51 Left 2 TXD +TEXT -156 -14 Left 2 RS +TEXT 156 -45 Right 2 CANH +TEXT 156 19 Right 2 CANL +TEXT -13 0 Center 2 LOGIC +TEXT 156 85 Right 2 SPLIT +WINDOW 3 80 160 Center 2 +WINDOW 0 64 -160 Center 2 +SYMATTR Value LTC2875 +SYMATTR Prefix X +SYMATTR Description +/- 60V Fault Protected 3.3V or 5V 25kV ESD High Speed CAN Transceiver +SYMATTR SpiceModel LTC6.lib +SYMATTR Value2 LTC2875 +PIN -160 64 NONE 8 +PINATTR PinName TXD +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 4 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 0 -144 TOP 4 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -160 -64 NONE 8 +PINATTR PinName RXD +PINATTR SpiceOrder 4 +PIN 160 96 NONE 8 +PINATTR PinName SPLIT +PINATTR SpiceOrder 5 +PIN 160 32 NONE 8 +PINATTR PinName CANL +PINATTR SpiceOrder 6 +PIN 160 -32 NONE 8 +PINATTR PinName CANH +PINATTR SpiceOrder 7 +PIN -160 0 NONE 8 +PINATTR PinName RS +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2909-25.asy b/spice/copy/sym/SpecialFunctions/LTC2909-25.asy new file mode 100755 index 0000000..7aa40e4 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2909-25.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 0 Center 2 +SYMATTR Value LTC2909-25 +SYMATTR Prefix X +SYMATTR Description Dual Adjustable UV/OV Monitor, 2.5V UVLO +SYMATTR SpiceModel LTC2909-25.sub +SYMATTR Value2 LTC2909-25 +PIN -128 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2909-33.asy b/spice/copy/sym/SpecialFunctions/LTC2909-33.asy new file mode 100755 index 0000000..8bf24a5 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2909-33.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 0 Center 2 +SYMATTR Value LTC2909-33 +SYMATTR Prefix X +SYMATTR Description Dual Adjustable UV/OV Monitor, 3.3V UVLO +SYMATTR SpiceModel LTC2909-33.sub +SYMATTR Value2 LTC2909-33 +PIN -128 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2909-50.asy b/spice/copy/sym/SpecialFunctions/LTC2909-50.asy new file mode 100755 index 0000000..2a4040f --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2909-50.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -20 -128 -20 -112 +LINE Normal 20 -128 20 -112 +LINE Normal -8 -100 8 -100 +RECTANGLE Normal -128 -128 128 128 +ARC Normal -20 -124 4 -100 -20 -112 -8 -100 +ARC Normal -4 -124 20 -100 8 -100 20 -112 +TEXT 0 -64 Center 2 LT +WINDOW 0 0 -144 Center 2 +WINDOW 3 0 0 Center 2 +SYMATTR Value LTC2909-50 +SYMATTR Prefix X +SYMATTR Description Dual Adjustable UV/OV Monitor, 5.0V UVLO +SYMATTR SpiceModel LTC2909-50.sub +SYMATTR Value2 LTC2909-50 +PIN -128 -96 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -128 -32 LEFT 8 +PINATTR PinName REF +PINATTR SpiceOrder 2 +PIN -128 32 LEFT 8 +PINATTR PinName ADJ2 +PINATTR SpiceOrder 3 +PIN -128 96 LEFT 8 +PINATTR PinName ADJ1 +PINATTR SpiceOrder 4 +PIN 128 96 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 5 +PIN 128 32 RIGHT 8 +PINATTR PinName TMR +PINATTR SpiceOrder 6 +PIN 128 -32 RIGHT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 7 +PIN 128 -96 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2925.asy b/spice/copy/sym/SpecialFunctions/LTC2925.asy new file mode 100755 index 0000000..d85f538 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2925.asy @@ -0,0 +1,82 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -352 -272 352 272 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 96 Center 2 +SYMATTR Value LTC2925 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2925.lib +SYMATTR Value2 LTC2925 +PIN -352 -224 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 1 +PIN 0 -272 TOP 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 2 +PIN -128 -272 TOP 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 3 +PIN -352 -32 LEFT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 4 +PIN 352 -128 RIGHT 8 +PINATTR PinName _SD1 +PINATTR SpiceOrder 5 +PIN 352 0 RIGHT 8 +PINATTR PinName _SD2 +PINATTR SpiceOrder 6 +PIN 352 128 RIGHT 8 +PINATTR PinName _SD3 +PINATTR SpiceOrder 7 +PIN 352 -64 RIGHT 8 +PINATTR PinName FB1 +PINATTR SpiceOrder 8 +PIN 352 64 RIGHT 8 +PINATTR PinName FB2 +PINATTR SpiceOrder 9 +PIN 352 192 RIGHT 8 +PINATTR PinName FB3 +PINATTR SpiceOrder 10 +PIN 128 -272 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 11 +PIN 352 -192 RIGHT 8 +PINATTR PinName PGI +PINATTR SpiceOrder 12 +PIN 256 -272 TOP 8 +PINATTR PinName Ramp +PINATTR SpiceOrder 13 +PIN -352 32 LEFT 8 +PINATTR PinName RampBuf +PINATTR SpiceOrder 14 +PIN -352 -160 LEFT 8 +PINATTR PinName Remote +PINATTR SpiceOrder 15 +PIN -64 272 BOTTOM 8 +PINATTR PinName SCTMR +PINATTR SpiceOrder 16 +PIN 64 272 BOTTOM 8 +PINATTR PinName SDTMR +PINATTR SpiceOrder 17 +PIN -352 -96 LEFT 8 +PINATTR PinName Status +PINATTR SpiceOrder 18 +PIN -352 96 LEFT 8 +PINATTR PinName Track1 +PINATTR SpiceOrder 19 +PIN -352 160 LEFT 8 +PINATTR PinName Track2 +PINATTR SpiceOrder 20 +PIN -352 224 LEFT 8 +PINATTR PinName Track3 +PINATTR SpiceOrder 21 +PIN -256 -272 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 22 +PIN 192 272 BOTTOM 8 +PINATTR PinName PGTMR +PINATTR SpiceOrder 23 +PIN -192 272 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/SpecialFunctions/LTC2941-1.asy b/spice/copy/sym/SpecialFunctions/LTC2941-1.asy new file mode 100755 index 0000000..5888852 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2941-1.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 192 -160 -192 +TEXT 1 1 Center 2 LT +TEXT 0 51 Center 2 LTC2941-1 +WINDOW 3 1 -156 Center 2 +WINDOW 0 1 -62 Center 2 +WINDOW 40 1 152 Center 2 +SYMATTR Value B_Reg=4 CD_Reg=32767 +SYMATTR SpiceLine2 EF_Reg=65535 GH_Reg=0 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2941-1 +SYMATTR Description 1A I2C Battery Gas Gauge with Internal Sense Resistor +SYMATTR Value2 EF_Reg=65535 GH_Reg=0 +SYMATTR ModelFile LTC2941-1.sub +PIN -160 -96 LEFT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -160 96 LEFT 8 +PINATTR PinName StatusReg +PINATTR SpiceOrder 3 +PIN 160 96 RIGHT 8 +PINATTR PinName ACRreg +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName _AL/CC +PINATTR SpiceOrder 5 +PIN 160 -96 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC2941.asy b/spice/copy/sym/SpecialFunctions/LTC2941.asy new file mode 100755 index 0000000..dd48f5a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2941.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 192 -160 -192 +TEXT 1 1 Center 2 LT +TEXT 0 51 Center 2 LTC2941 +WINDOW 3 1 -156 Center 2 +WINDOW 0 1 -62 Center 2 +WINDOW 40 1 152 Center 2 +SYMATTR Value B_Reg=04 CD_Reg=32767 +SYMATTR SpiceLine2 EF_Reg=65535 GH_Reg=0 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2941 +SYMATTR Description Battery Gas Gauge with I2C Interface +SYMATTR Value2 EF_Reg=65535 GH_Reg=0 +SYMATTR ModelFile LTC2941.sub +PIN -160 -96 LEFT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -160 96 LEFT 8 +PINATTR PinName StatusReg +PINATTR SpiceOrder 3 +PIN 160 96 RIGHT 8 +PINATTR PinName ACRreg +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName _AL/CC +PINATTR SpiceOrder 5 +PIN 160 -96 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC2942-1.asy b/spice/copy/sym/SpecialFunctions/LTC2942-1.asy new file mode 100755 index 0000000..bac6d25 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2942-1.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 161 128 -160 -144 +TEXT 1 1 Center 2 LT +TEXT 0 51 Center 2 LTC2942-1 +WINDOW 3 14 152 Center 2 +WINDOW 0 1 -62 Center 2 +WINDOW 40 7 183 Center 2 +SYMATTR Value B_Reg=04 CD_Reg=32767 EF_Reg=65535 +SYMATTR SpiceLine2 GH_Reg=0 K_Reg=255 L_Reg=0 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2942-1 +SYMATTR Description 1A Battery Gas Gauge with Internal Sense Resistor and Temperature/Voltage Measurement (Temperature not modeled) +SYMATTR Value2 EF_Reg=65535 GH_Reg=0 +SYMATTR ModelFile LTC2942-1.sub +PIN -160 -96 LEFT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -160 96 LEFT 8 +PINATTR PinName StatusReg +PINATTR SpiceOrder 3 +PIN 160 96 RIGHT 8 +PINATTR PinName ACRreg +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName _AL/CC +PINATTR SpiceOrder 5 +PIN 160 -96 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName VoltReg +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/SpecialFunctions/LTC2942.asy b/spice/copy/sym/SpecialFunctions/LTC2942.asy new file mode 100755 index 0000000..681d42b --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2942.asy @@ -0,0 +1,36 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 161 128 -160 -144 +TEXT 1 1 Center 2 LT +TEXT 0 51 Center 2 LTC2942 +WINDOW 3 14 152 Center 2 +WINDOW 0 1 -62 Center 2 +WINDOW 40 7 183 Center 2 +SYMATTR Value B_Reg=04 CD_Reg=32767 EF_Reg=65535 +SYMATTR SpiceLine2 GH_Reg=0 K_Reg=255 L_Reg=0 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2942 +SYMATTR Description Battery Gas Gauge with Temperature, Voltage Measurement (Temperature not modeled) +SYMATTR Value2 EF_Reg=65535 GH_Reg=0 +SYMATTR ModelFile LTC2942.sub +PIN -160 -96 LEFT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -160 96 LEFT 8 +PINATTR PinName StatusReg +PINATTR SpiceOrder 3 +PIN 160 96 RIGHT 8 +PINATTR PinName ACRreg +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName _AL/CC +PINATTR SpiceOrder 5 +PIN 160 -96 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName VoltReg +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/SpecialFunctions/LTC2943.asy b/spice/copy/sym/SpecialFunctions/LTC2943.asy new file mode 100755 index 0000000..421b27c --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2943.asy @@ -0,0 +1,39 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 161 128 -160 -144 +TEXT 1 1 Center 2 LT +TEXT 0 51 Center 2 LTC2943 +WINDOW 3 14 152 Center 2 +WINDOW 0 1 -62 Center 2 +WINDOW 40 7 183 Center 2 +SYMATTR Value B_Reg=36 CD_Reg=32767 EF_Reg=65535 GH_Reg=0 +SYMATTR SpiceLine2 KL_Reg=65535 MN_Reg=0 QR_Reg=65535 ST_Reg=0 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2943 +SYMATTR Description Multicell Battery Gas Gauge with Temperature, Voltage, and Current Measurement (Temperature not modeled) +SYMATTR Value2 EF_Reg=65535 GH_Reg=0 +SYMATTR ModelFile LTC2943.sub +PIN -160 -96 LEFT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 1 +PIN -160 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -160 96 LEFT 8 +PINATTR PinName StatusReg +PINATTR SpiceOrder 3 +PIN 160 96 RIGHT 8 +PINATTR PinName ACRReg +PINATTR SpiceOrder 4 +PIN 160 0 RIGHT 8 +PINATTR PinName _AL/CC +PINATTR SpiceOrder 5 +PIN 160 -96 RIGHT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 6 +PIN -64 -144 TOP 8 +PINATTR PinName VoltReg +PINATTR SpiceOrder 7 +PIN 64 -144 TOP 8 +PINATTR PinName CurReg +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2945.asy b/spice/copy/sym/SpecialFunctions/LTC2945.asy new file mode 100755 index 0000000..3268dab --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2945.asy @@ -0,0 +1,76 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -400 224 400 +TEXT 0 -80 Center 2 LT +WINDOW 0 0 -200 Center 2 +WINDOW 3 0 0 Center 2 +WINDOW 123 0 64 Center 2 +WINDOW 39 0 112 Center 2 +WINDOW 40 0 160 Center 2 +SYMATTR Value LTC2945 +SYMATTR Value2 A0=1 A2=1 +SYMATTR SpiceLine A5=0 A6=0 +SYMATTR SpiceLine2 A7=0 +SYMATTR Prefix X +SYMATTR Description Wide Range I2C Power Monitor +SYMATTR ModelFile LTC2945.sub +PIN -224 -320 LEFT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -224 -240 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 2 +PIN -224 -160 LEFT 8 +PINATTR PinName ADin +PINATTR SpiceOrder 3 +PIN -96 -400 TOP 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 4 +PIN 96 -400 TOP 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 5 +PIN 0 400 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 6 +PIN 224 -320 RIGHT 8 +PINATTR PinName >Power +PINATTR SpiceOrder 7 +PIN 224 -272 RIGHT 8 +PINATTR PinName >MaxPower +PINATTR SpiceOrder 8 +PIN 224 -224 RIGHT 8 +PINATTR PinName >MinPower +PINATTR SpiceOrder 9 +PIN 224 -160 RIGHT 8 +PINATTR PinName >Sense +PINATTR SpiceOrder 10 +PIN 224 -112 RIGHT 8 +PINATTR PinName >MaxSense +PINATTR SpiceOrder 11 +PIN 224 -64 RIGHT 8 +PINATTR PinName >MinSense +PINATTR SpiceOrder 12 +PIN 224 0 RIGHT 8 +PINATTR PinName >Vin +PINATTR SpiceOrder 13 +PIN 224 48 RIGHT 8 +PINATTR PinName >MaxVin +PINATTR SpiceOrder 14 +PIN 224 96 RIGHT 8 +PINATTR PinName >MinVin +PINATTR SpiceOrder 15 +PIN 224 160 RIGHT 8 +PINATTR PinName >ADin +PINATTR SpiceOrder 16 +PIN 224 208 RIGHT 8 +PINATTR PinName >MaxAdin +PINATTR SpiceOrder 17 +PIN 224 256 RIGHT 8 +PINATTR PinName >MinAdin +PINATTR SpiceOrder 18 +PIN 224 320 RIGHT 8 +PINATTR PinName >Busy/A3 +PINATTR SpiceOrder 19 +PIN -224 240 LEFT 8 +PINATTR PinName >SD/A1 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/SpecialFunctions/LTC2946.asy b/spice/copy/sym/SpecialFunctions/LTC2946.asy new file mode 100755 index 0000000..aeaaa3a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2946.asy @@ -0,0 +1,85 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -464 224 464 +TEXT 0 -80 Center 2 LT +WINDOW 0 0 -200 Center 2 +WINDOW 3 0 0 Center 2 +WINDOW 123 -48 80 Center 2 +WINDOW 39 -48 128 Center 2 +WINDOW 40 -48 176 Center 2 +SYMATTR Value LTC2946 +SYMATTR Value2 CA2=0 CA1=1 CA0=1 +SYMATTR SpiceLine CA4=1 CA3=1 +SYMATTR SpiceLine2 CA7=0 CA6=0 CA5=0 +SYMATTR Prefix X +SYMATTR Description Wide Range I2C Power,Charge, and Energy Monitor +SYMATTR ModelFile LTC2946.sub +PIN -224 -320 LEFT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -224 -240 LEFT 8 +PINATTR PinName IntVcc +PINATTR SpiceOrder 2 +PIN -224 -160 LEFT 8 +PINATTR PinName ADin +PINATTR SpiceOrder 3 +PIN -96 -464 TOP 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 4 +PIN 96 -464 TOP 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 5 +PIN 0 464 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 6 +PIN 224 -400 RIGHT 8 +PINATTR PinName >Power +PINATTR SpiceOrder 7 +PIN 224 -352 RIGHT 8 +PINATTR PinName >MaxPower +PINATTR SpiceOrder 8 +PIN 224 -304 RIGHT 8 +PINATTR PinName >MinPower +PINATTR SpiceOrder 9 +PIN 224 -240 RIGHT 8 +PINATTR PinName >Sense +PINATTR SpiceOrder 10 +PIN 224 -192 RIGHT 8 +PINATTR PinName >MaxSense +PINATTR SpiceOrder 11 +PIN 224 -144 RIGHT 8 +PINATTR PinName >MinSense +PINATTR SpiceOrder 12 +PIN 224 -80 RIGHT 8 +PINATTR PinName >Vin +PINATTR SpiceOrder 13 +PIN 224 -32 RIGHT 8 +PINATTR PinName >MaxVin +PINATTR SpiceOrder 14 +PIN 224 16 RIGHT 8 +PINATTR PinName >MinVin +PINATTR SpiceOrder 15 +PIN 224 80 RIGHT 8 +PINATTR PinName >ADin +PINATTR SpiceOrder 16 +PIN 224 128 RIGHT 8 +PINATTR PinName >MaxAdin +PINATTR SpiceOrder 17 +PIN 224 176 RIGHT 8 +PINATTR PinName >MinAdin +PINATTR SpiceOrder 18 +PIN 224 240 RIGHT 8 +PINATTR PinName >Time +PINATTR SpiceOrder 19 +PIN 224 288 RIGHT 8 +PINATTR PinName >Charge +PINATTR SpiceOrder 20 +PIN 224 336 RIGHT 8 +PINATTR PinName >Energy +PINATTR SpiceOrder 21 +PIN 224 400 RIGHT 8 +PINATTR PinName >Busy +PINATTR SpiceOrder 22 +PIN -224 240 LEFT 8 +PINATTR PinName >SD +PINATTR SpiceOrder 23 diff --git a/spice/copy/sym/SpecialFunctions/LTC2950-1.asy b/spice/copy/sym/SpecialFunctions/LTC2950-1.asy new file mode 100755 index 0000000..9336416 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2950-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2950-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2950-1.sub +SYMATTR Value2 LTC2950-1 +SYMATTR Description Push Button On/Off Controller +PIN -112 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 2 +PIN -48 128 BOTTOM 8 +PINATTR PinName ONT +PINATTR SpiceOrder 3 +PIN -112 80 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 6 +PIN 48 128 BOTTOM 8 +PINATTR PinName OFFT +PINATTR SpiceOrder 7 +PIN 112 80 RIGHT 8 +PINATTR PinName _KILL +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2950-2.asy b/spice/copy/sym/SpecialFunctions/LTC2950-2.asy new file mode 100755 index 0000000..006bdc0 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2950-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2950-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2950-2.sub +SYMATTR Value2 LTC2950-2 +SYMATTR Description Push Button On/Off Controller +PIN -112 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 2 +PIN -48 128 BOTTOM 8 +PINATTR PinName ONT +PINATTR SpiceOrder 3 +PIN -112 80 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 6 +PIN 48 128 BOTTOM 8 +PINATTR PinName OFFT +PINATTR SpiceOrder 7 +PIN 112 80 RIGHT 8 +PINATTR PinName _KILL +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2952.asy b/spice/copy/sym/SpecialFunctions/LTC2952.asy new file mode 100755 index 0000000..dcf0f54 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2952.asy @@ -0,0 +1,71 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 208 368 -208 -304 +TEXT 0 32 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTC2952 +SYMATTR Prefix X +SYMATTR Description Dual Ideal Diode Push Button Power Path Controller with Supervisor +SYMATTR SpiceModel LTC2952.sub +SYMATTR Value2 LTC2952 +PIN 208 -96 RIGHT 8 +PINATTR PinName VM +PINATTR SpiceOrder 1 +PIN 208 -224 RIGHT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 2 +PIN 208 32 RIGHT 8 +PINATTR PinName WDE +PINATTR SpiceOrder 3 +PIN -208 112 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 4 +PIN 208 -32 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 5 +PIN 208 -160 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 6 +PIN -80 368 BOTTOM 8 +PINATTR PinName ONT +PINATTR SpiceOrder 7 +PIN 80 368 BOTTOM 8 +PINATTR PinName OFFT +PINATTR SpiceOrder 8 +PIN 0 368 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 208 288 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 10 +PIN 208 224 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 11 +PIN 64 -304 TOP 8 +PINATTR PinName G2 +PINATTR SpiceOrder 12 +PIN 128 -304 TOP 8 +PINATTR PinName V2 +PINATTR SpiceOrder 13 +PIN 0 -304 TOP 8 +PINATTR PinName VS +PINATTR SpiceOrder 14 +PIN -128 -304 TOP 8 +PINATTR PinName V1 +PINATTR SpiceOrder 15 +PIN -64 -304 TOP 8 +PINATTR PinName G1 +PINATTR SpiceOrder 16 +PIN 208 160 RIGHT 8 +PINATTR PinName G1Stat +PINATTR SpiceOrder 17 +PIN -208 16 LEFT 8 +PINATTR PinName M2 +PINATTR SpiceOrder 18 +PIN -208 -80 LEFT 8 +PINATTR PinName M1 +PINATTR SpiceOrder 19 +PIN 208 96 RIGHT 8 +PINATTR PinName _KILL +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/SpecialFunctions/LTC2953-1.asy b/spice/copy/sym/SpecialFunctions/LTC2953-1.asy new file mode 100755 index 0000000..6e9eaa9 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2953-1.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 336 -144 -288 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2953-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2953-1.sub +SYMATTR Value2 LTC2953-1 +SYMATTR Description Push Button On/Off Controller with Voltage Monitor +PIN -64 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 144 -112 RIGHT 8 +PINATTR PinName VM +PINATTR SpiceOrder 2 +PIN 64 336 BOTTOM 8 +PINATTR PinName _KILL +PINATTR SpiceOrder 3 +PIN -144 208 LEFT 8 +PINATTR PinName PDT +PINATTR SpiceOrder 4 +PIN -144 64 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 5 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 -224 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 7 +PIN -144 -80 LEFT 8 +PINATTR PinName _PFI +PINATTR SpiceOrder 8 +PIN 144 112 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 10 +PIN 144 -224 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 11 +PIN 144 224 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2953-2.asy b/spice/copy/sym/SpecialFunctions/LTC2953-2.asy new file mode 100755 index 0000000..6ccf4d9 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2953-2.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 336 -144 -288 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2953-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2953-2.sub +SYMATTR Value2 LTC2953-2 +SYMATTR Description Push Button On/Off Controller with Voltage Monitor +PIN -64 336 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN 144 -112 RIGHT 8 +PINATTR PinName VM +PINATTR SpiceOrder 2 +PIN 64 336 BOTTOM 8 +PINATTR PinName _KILL +PINATTR SpiceOrder 3 +PIN -144 208 LEFT 8 +PINATTR PinName PDT +PINATTR SpiceOrder 4 +PIN -144 64 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 5 +PIN 0 -288 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN -144 -224 LEFT 8 +PINATTR PinName UVLO +PINATTR SpiceOrder 7 +PIN -144 -80 LEFT 8 +PINATTR PinName _PFI +PINATTR SpiceOrder 8 +PIN 144 112 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 10 +PIN 144 -224 RIGHT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 11 +PIN 144 224 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2954-1.asy b/spice/copy/sym/SpecialFunctions/LTC2954-1.asy new file mode 100755 index 0000000..9689936 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2954-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2954-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2954-1.sub +SYMATTR Value2 LTC2954-1 +SYMATTR Description Push Button On/Off Controller with µP Interrupt +PIN -112 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 2 +PIN -48 128 BOTTOM 8 +PINATTR PinName ONT +PINATTR SpiceOrder 3 +PIN -112 80 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 6 +PIN 48 128 BOTTOM 8 +PINATTR PinName PDT +PINATTR SpiceOrder 7 +PIN 112 80 RIGHT 8 +PINATTR PinName _KILL +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2954-2.asy b/spice/copy/sym/SpecialFunctions/LTC2954-2.asy new file mode 100755 index 0000000..070e95f --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2954-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2954-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2954-2.sub +SYMATTR Value2 LTC2954-2 +SYMATTR Description Push Button On/Off Controller with µP Interrupt +PIN -112 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 2 +PIN -48 128 BOTTOM 8 +PINATTR PinName ONT +PINATTR SpiceOrder 3 +PIN -112 80 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 6 +PIN 48 128 BOTTOM 8 +PINATTR PinName PDT +PINATTR SpiceOrder 7 +PIN 112 80 RIGHT 8 +PINATTR PinName _KILL +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2955-1.asy b/spice/copy/sym/SpecialFunctions/LTC2955-1.asy new file mode 100755 index 0000000..55ff22d --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2955-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -160 +TEXT 0 -33 Center 2 LT +WINDOW 3 1 27 Center 2 +WINDOW 0 0 -95 Center 2 +SYMATTR Value LTC2955-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2955-1.sub +SYMATTR Description Push Button On/Off Controller with µP Interrupt +SYMATTR Value2 LTC2955-1 +PIN 112 -64 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 1 +PIN 112 64 RIGHT 8 +PINATTR PinName PGD +PINATTR SpiceOrder 2 +PIN 112 -128 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 3 +PIN -112 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -112 64 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 5 +PIN -48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -112 -64 LEFT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 7 +PIN 32 128 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 8 +PIN 112 0 RIGHT 8 +PINATTR PinName _KILL +PINATTR SpiceOrder 9 +PIN -112 0 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC2955-2.asy b/spice/copy/sym/SpecialFunctions/LTC2955-2.asy new file mode 100755 index 0000000..298932e --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2955-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 128 -112 -160 +TEXT 0 -33 Center 2 LT +WINDOW 3 1 27 Center 2 +WINDOW 0 0 -95 Center 2 +SYMATTR Value LTC2955-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2955-2.sub +SYMATTR Description Push Button On/Off Controller with µP Interrupt +SYMATTR Value2 LTC2955-2 +PIN 112 -64 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 1 +PIN 112 64 RIGHT 8 +PINATTR PinName PGD +PINATTR SpiceOrder 2 +PIN 112 -128 RIGHT 8 +PINATTR PinName _EN +PINATTR SpiceOrder 3 +PIN -112 -128 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN -112 64 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 5 +PIN -48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -112 -64 LEFT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 7 +PIN 32 128 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 8 +PIN 112 0 RIGHT 8 +PINATTR PinName _KILL +PINATTR SpiceOrder 9 +PIN -112 0 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC2956-1.asy b/spice/copy/sym/SpecialFunctions/LTC2956-1.asy new file mode 100755 index 0000000..2098f25 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2956-1.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -192 224 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC2956-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2956-1.sub +SYMATTR Value2 LTC2956-1 +SYMATTR Description Wake-Up Timer with Pushbutton Control +PIN -224 -64 LEFT 8 +PINATTR PinName OnMax +PINATTR SpiceOrder 1 +PIN -64 192 BOTTOM 8 +PINATTR PinName Long +PINATTR SpiceOrder 2 +PIN 48 192 BOTTOM 8 +PINATTR PinName Range +PINATTR SpiceOrder 3 +PIN 144 192 BOTTOM 8 +PINATTR PinName Period +PINATTR SpiceOrder 4 +PIN -112 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -144 192 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 6 +PIN -224 80 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 7 +PIN 112 -192 TOP 8 +PINATTR PinName EN +PINATTR SpiceOrder 8 +PIN 224 -128 RIGHT 8 +PINATTR PinName _PBout +PINATTR SpiceOrder 9 +PIN 224 32 RIGHT 8 +PINATTR PinName _OffAlert +PINATTR SpiceOrder 10 +PIN 224 112 RIGHT 8 +PINATTR PinName _Sleep +PINATTR SpiceOrder 11 +PIN 224 -48 RIGHT 8 +PINATTR PinName _OnAlert +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2956-2.asy b/spice/copy/sym/SpecialFunctions/LTC2956-2.asy new file mode 100755 index 0000000..b7667fb --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2956-2.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -192 224 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC2956-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2956-2.sub +SYMATTR Value2 LTC2956-2 +SYMATTR Description Wake-Up Timer with Pushbutton Control +PIN -224 -64 LEFT 8 +PINATTR PinName OnMax +PINATTR SpiceOrder 1 +PIN -64 192 BOTTOM 8 +PINATTR PinName Long +PINATTR SpiceOrder 2 +PIN 48 192 BOTTOM 8 +PINATTR PinName Range +PINATTR SpiceOrder 3 +PIN 144 192 BOTTOM 8 +PINATTR PinName Period +PINATTR SpiceOrder 4 +PIN -112 -192 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 5 +PIN -144 192 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 6 +PIN -224 80 LEFT 8 +PINATTR PinName _PB +PINATTR SpiceOrder 7 +PIN 112 -192 TOP 8 +PINATTR PinName _EN +PINATTR SpiceOrder 8 +PIN 224 -128 RIGHT 8 +PINATTR PinName _PBout +PINATTR SpiceOrder 9 +PIN 224 32 RIGHT 8 +PINATTR PinName _OffAlert +PINATTR SpiceOrder 10 +PIN 224 112 RIGHT 8 +PINATTR PinName _Sleep +PINATTR SpiceOrder 11 +PIN 224 -48 RIGHT 8 +PINATTR PinName _OnAlert +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC2960-1.asy b/spice/copy/sym/SpecialFunctions/LTC2960-1.asy new file mode 100755 index 0000000..ce5490a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2960-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 160 -112 -160 +TEXT 0 58 Center 2 LTC2960-1 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -55 Center 2 +SYMATTR Value LTC2960-1 +SYMATTR Prefix X +SYMATTR Value2 LTC2960-1 +SYMATTR Description 36V Nano-Current Two Input Voltage Monitor +SYMATTR SpiceModel LTC2960-1.sub +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 112 -112 RIGHT 8 +PINATTR PinName RT +PINATTR SpiceOrder 2 +PIN 112 112 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 3 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -112 -112 LEFT 8 +PINATTR PinName _MR +PINATTR SpiceOrder 6 +PIN -112 112 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 7 +PIN -112 0 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2960-2.asy b/spice/copy/sym/SpecialFunctions/LTC2960-2.asy new file mode 100755 index 0000000..ec17ff1 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2960-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 160 -112 -160 +TEXT 0 58 Center 2 LTC2960-2 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -55 Center 2 +SYMATTR Value LTC2960-2 +SYMATTR Prefix X +SYMATTR Value2 LTC2960-2 +SYMATTR Description 36V Nano-Current Two Input Voltage Monitor +SYMATTR SpiceModel LTC2960-2.sub +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 112 -112 RIGHT 8 +PINATTR PinName RT +PINATTR SpiceOrder 2 +PIN 112 112 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 3 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -112 -112 LEFT 8 +PINATTR PinName _MR +PINATTR SpiceOrder 6 +PIN -112 112 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 7 +PIN -112 0 LEFT 8 +PINATTR PinName IN- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2960-3.asy b/spice/copy/sym/SpecialFunctions/LTC2960-3.asy new file mode 100755 index 0000000..e90c658 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2960-3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 160 -112 -160 +TEXT 0 58 Center 2 LTC2960-3 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -55 Center 2 +SYMATTR Value LTC2960-3 +SYMATTR Prefix X +SYMATTR Value2 LTC2960-3 +SYMATTR Description 36V Nano-Current Two Input Voltage Monitor +SYMATTR SpiceModel LTC2960-3.sub +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 112 -112 RIGHT 8 +PINATTR PinName DVCC +PINATTR SpiceOrder 2 +PIN 112 112 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 3 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -112 -112 LEFT 8 +PINATTR PinName _MR +PINATTR SpiceOrder 6 +PIN -112 112 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 7 +PIN -112 0 LEFT 8 +PINATTR PinName IN+ +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2960-4.asy b/spice/copy/sym/SpecialFunctions/LTC2960-4.asy new file mode 100755 index 0000000..278b9aa --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2960-4.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 112 160 -112 -160 +TEXT 0 58 Center 2 LTC2960-4 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -55 Center 2 +SYMATTR Value LTC2960-4 +SYMATTR Prefix X +SYMATTR Value2 LTC2960-4 +SYMATTR Description 36V Nano-Current Two Input Voltage Monitor +SYMATTR SpiceModel LTC2960-4.sub +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN 112 -112 RIGHT 8 +PINATTR PinName DVCC +PINATTR SpiceOrder 2 +PIN 112 112 RIGHT 8 +PINATTR PinName _RST +PINATTR SpiceOrder 3 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 4 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -112 -112 LEFT 8 +PINATTR PinName _MR +PINATTR SpiceOrder 6 +PIN -112 112 LEFT 8 +PINATTR PinName ADJ +PINATTR SpiceOrder 7 +PIN -112 0 LEFT 8 +PINATTR PinName IN- +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2965.asy b/spice/copy/sym/SpecialFunctions/LTC2965.asy new file mode 100755 index 0000000..e004ffc --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2965.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 176 -128 -160 +TEXT 0 0 Center 2 LT +WINDOW 3 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value LTC2965 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2965.sub +SYMATTR Description 100V µPower Single Voltage Monitor +SYMATTR Value2 LTC2965 +PIN 0 -160 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 -80 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName INH +PINATTR SpiceOrder 3 +PIN -128 80 LEFT 8 +PINATTR PinName INL +PINATTR SpiceOrder 4 +PIN -80 176 BOTTOM 8 +PINATTR PinName PS +PINATTR SpiceOrder 5 +PIN 0 176 BOTTOM 8 +PINATTR PinName RS +PINATTR SpiceOrder 6 +PIN 80 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC2966.asy b/spice/copy/sym/SpecialFunctions/LTC2966.asy new file mode 100755 index 0000000..1ea3e24 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2966.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 336 288 -336 -288 +TEXT 0 0 Center 2 LT +WINDOW 3 0 64 Center 2 +WINDOW 0 0 -64 Center 2 +SYMATTR Value LTC2966 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2966.sub +SYMATTR Description 100V µPower Dual Voltage Monitor +SYMATTR Value2 LTC2966 +PIN -176 -288 TOP 8 +PINATTR PinName VinA +PINATTR SpiceOrder 1 +PIN -336 -224 LEFT 8 +PINATTR PinName Ref +PINATTR SpiceOrder 2 +PIN -336 -112 LEFT 8 +PINATTR PinName INHA +PINATTR SpiceOrder 3 +PIN -336 0 LEFT 8 +PINATTR PinName INLA +PINATTR SpiceOrder 4 +PIN -240 288 BOTTOM 8 +PINATTR PinName PSA +PINATTR SpiceOrder 5 +PIN -144 288 BOTTOM 8 +PINATTR PinName RS1A +PINATTR SpiceOrder 6 +PIN -48 288 BOTTOM 8 +PINATTR PinName RS2A +PINATTR SpiceOrder 7 +PIN 336 -64 RIGHT 8 +PINATTR PinName OUTA +PINATTR SpiceOrder 8 +PIN 336 224 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -16 -288 TOP 8 +PINATTR PinName VinB +PINATTR SpiceOrder 10 +PIN -336 112 LEFT 8 +PINATTR PinName INHB +PINATTR SpiceOrder 11 +PIN -336 224 LEFT 8 +PINATTR PinName INLB +PINATTR SpiceOrder 12 +PIN 48 288 BOTTOM 8 +PINATTR PinName PSB +PINATTR SpiceOrder 13 +PIN 144 288 BOTTOM 8 +PINATTR PinName RS1B +PINATTR SpiceOrder 14 +PIN 240 288 BOTTOM 8 +PINATTR PinName RS2B +PINATTR SpiceOrder 15 +PIN 336 64 RIGHT 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC2995.asy b/spice/copy/sym/SpecialFunctions/LTC2995.asy new file mode 100755 index 0000000..898cdec --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2995.asy @@ -0,0 +1,68 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 272 256 -288 -256 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC2995 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2995.sub +SYMATTR Description Temperature Sensor and Dual Voltage Monitor with Alert Outputs +SYMATTR Value2 LTC2995 +PIN -288 -48 LEFT 8 +PINATTR PinName VL1 +PINATTR SpiceOrder 1 +PIN -288 48 LEFT 8 +PINATTR PinName VH2 +PINATTR SpiceOrder 2 +PIN -288 144 LEFT 8 +PINATTR PinName VL2 +PINATTR SpiceOrder 3 +PIN -112 256 BOTTOM 8 +PINATTR PinName VT2 +PINATTR SpiceOrder 4 +PIN 0 256 BOTTOM 8 +PINATTR PinName VT1 +PINATTR SpiceOrder 5 +PIN 112 -256 TOP 8 +PINATTR PinName D+ +PINATTR SpiceOrder 6 +PIN 224 -256 TOP 8 +PINATTR PinName D- +PINATTR SpiceOrder 7 +PIN 272 -192 RIGHT 8 +PINATTR PinName VPTAT +PINATTR SpiceOrder 8 +PIN 0 -256 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 9 +PIN -224 256 BOTTOM 8 +PINATTR PinName Vref +PINATTR SpiceOrder 11 +PIN 272 0 RIGHT 8 +PINATTR PinName _TO1 +PINATTR SpiceOrder 12 +PIN 272 -96 RIGHT 8 +PINATTR PinName _TO2 +PINATTR SpiceOrder 13 +PIN 272 96 RIGHT 8 +PINATTR PinName _OV +PINATTR SpiceOrder 14 +PIN 272 192 RIGHT 8 +PINATTR PinName _UV +PINATTR SpiceOrder 15 +PIN 224 256 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 16 +PIN 112 256 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 17 +PIN -224 -256 TOP 8 +PINATTR PinName DS +PINATTR SpiceOrder 18 +PIN -112 -256 TOP 8 +PINATTR PinName PS +PINATTR SpiceOrder 19 +PIN -288 -144 LEFT 8 +PINATTR PinName VH1 +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/SpecialFunctions/LTC2996.asy b/spice/copy/sym/SpecialFunctions/LTC2996.asy new file mode 100755 index 0000000..5990913 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2996.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 128 -144 -256 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 -8 Center 2 +WINDOW 0 0 -119 Center 2 +SYMATTR Value LTC2996 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2996.sub +SYMATTR Description Temperature Sensor with Alert Outputs +SYMATTR Value2 LTC2996 +PIN 144 -64 RIGHT 8 +PINATTR PinName Vth +PINATTR SpiceOrder 1 +PIN 144 48 RIGHT 8 +PINATTR PinName Vtl +PINATTR SpiceOrder 2 +PIN -144 -64 LEFT 8 +PINATTR PinName D+ +PINATTR SpiceOrder 3 +PIN -144 48 LEFT 8 +PINATTR PinName D- +PINATTR SpiceOrder 4 +PIN -144 -176 LEFT 8 +PINATTR PinName Vptat +PINATTR SpiceOrder 5 +PIN -64 -256 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 +PIN -64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 144 -176 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 8 +PIN 80 128 BOTTOM 8 +PINATTR PinName _UT +PINATTR SpiceOrder 9 +PIN 64 -256 TOP 8 +PINATTR PinName _OT +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC2997.asy b/spice/copy/sym/SpecialFunctions/LTC2997.asy new file mode 100755 index 0000000..500f3a8 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC2997.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 80 -144 -208 +TEXT 0 -64 Center 2 LT +WINDOW 3 0 -24 Center 2 +WINDOW 0 0 -104 Center 2 +SYMATTR Value LTC2997 +SYMATTR Prefix X +SYMATTR SpiceModel LTC2997.sub +SYMATTR Description Remote/Internal Temperature Sensor +SYMATTR Value2 LTC2997 +PIN -144 -128 LEFT 8 +PINATTR PinName D+ +PINATTR SpiceOrder 1 +PIN -144 0 LEFT 8 +PINATTR PinName D- +PINATTR SpiceOrder 2 +PIN 144 -128 RIGHT 8 +PINATTR PinName Vptat +PINATTR SpiceOrder 3 +PIN 0 -208 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 4 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 144 0 RIGHT 8 +PINATTR PinName Vref +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC4150.asy b/spice/copy/sym/SpecialFunctions/LTC4150.asy new file mode 100755 index 0000000..153aa2f --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4150.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 207 -144 -192 +TEXT 1 1 Center 2 LT +WINDOW 3 1 78 Center 2 +WINDOW 0 1 -62 Center 2 +SYMATTR Value LTC4150 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4150.sub +SYMATTR Description Coulomb Counter/Battery Gas Gauge +SYMATTR Value2 LTC4150 +PIN 144 -80 RIGHT 8 +PINATTR PinName _CLR +PINATTR SpiceOrder 9 +PIN 144 0 RIGHT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 +PIN 144 80 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 144 160 RIGHT 8 +PINATTR PinName POL +PINATTR SpiceOrder 6 +PIN -144 -80 LEFT 8 +PINATTR PinName Sense- +PINATTR SpiceOrder 2 +PIN -144 0 LEFT 8 +PINATTR PinName Cf+ +PINATTR SpiceOrder 3 +PIN -144 80 LEFT 8 +PINATTR PinName Cf- +PINATTR SpiceOrder 4 +PIN -144 160 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN -144 -160 LEFT 8 +PINATTR PinName Sense+ +PINATTR SpiceOrder 1 +PIN 144 -160 RIGHT 8 +PINATTR PinName _INT +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4242.asy b/spice/copy/sym/SpecialFunctions/LTC4242.asy new file mode 100755 index 0000000..a5a774b --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4242.asy @@ -0,0 +1,125 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -576 -496 576 496 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -192 Center 2 +WINDOW 3 0 192 Center 2 +SYMATTR Value LTC4242 +SYMATTR Prefix X +SYMATTR Description Dual Slot Hot Swap Controller for PCI Express +SYMATTR Value2 LTC4242 +SYMATTR SpiceModel LTC4242.sub +PIN 576 -80 RIGHT 8 +PINATTR PinName _En1 +PINATTR SpiceOrder 1 +PIN 576 -208 RIGHT 8 +PINATTR PinName Fon1 +PINATTR SpiceOrder 2 +PIN -576 -288 LEFT 8 +PINATTR PinName On1 +PINATTR SpiceOrder 3 +PIN -576 -352 LEFT 8 +PINATTR PinName AuxOn1 +PINATTR SpiceOrder 4 +PIN 512 -496 TOP 8 +PINATTR PinName 3Vout1 +PINATTR SpiceOrder 5 +PIN 384 -496 TOP 8 +PINATTR PinName 3VGate1 +PINATTR SpiceOrder 6 +PIN 256 -496 TOP 8 +PINATTR PinName 3Vsense1 +PINATTR SpiceOrder 7 +PIN 128 -496 TOP 8 +PINATTR PinName 3Vin1 +PINATTR SpiceOrder 8 +PIN -576 -416 LEFT 8 +PINATTR PinName AuxIn1 +PINATTR SpiceOrder 9 +PIN -512 -496 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 10 +PIN -576 416 LEFT 8 +PINATTR PinName AuxIn2 +PINATTR SpiceOrder 11 +PIN 128 496 BOTTOM 8 +PINATTR PinName 3Vin2 +PINATTR SpiceOrder 12 +PIN 256 496 BOTTOM 8 +PINATTR PinName 3Vsense2 +PINATTR SpiceOrder 13 +PIN 384 496 BOTTOM 8 +PINATTR PinName 3VGate2 +PINATTR SpiceOrder 14 +PIN 512 496 BOTTOM 8 +PINATTR PinName 3Vout2 +PINATTR SpiceOrder 15 +PIN -576 352 LEFT 8 +PINATTR PinName AuxOn2 +PINATTR SpiceOrder 16 +PIN -576 288 LEFT 8 +PINATTR PinName On2 +PINATTR SpiceOrder 17 +PIN 576 208 RIGHT 8 +PINATTR PinName Fon2 +PINATTR SpiceOrder 18 +PIN 576 80 RIGHT 8 +PINATTR PinName _En2 +PINATTR SpiceOrder 19 +PIN -576 224 LEFT 8 +PINATTR PinName _Fault2 +PINATTR SpiceOrder 20 +PIN -576 160 LEFT 8 +PINATTR PinName _AuxFault2 +PINATTR SpiceOrder 21 +PIN -576 96 LEFT 8 +PINATTR PinName _Pgood2 +PINATTR SpiceOrder 22 +PIN -384 496 BOTTOM 8 +PINATTR PinName 12Vin2 +PINATTR SpiceOrder 23 +PIN -256 496 BOTTOM 8 +PINATTR PinName 12Vsense2 +PINATTR SpiceOrder 24 +PIN -128 496 BOTTOM 8 +PINATTR PinName 12Vgate2 +PINATTR SpiceOrder 25 +PIN 0 496 BOTTOM 8 +PINATTR PinName 12Vout2 +PINATTR SpiceOrder 26 +PIN 576 336 RIGHT 8 +PINATTR PinName AuxOut2 +PINATTR SpiceOrder 27 +PIN -512 496 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 28 +PIN 576 -336 RIGHT 8 +PINATTR PinName AuxOut1 +PINATTR SpiceOrder 29 +PIN 0 -496 TOP 8 +PINATTR PinName 12Vout1 +PINATTR SpiceOrder 30 +PIN -128 -496 TOP 8 +PINATTR PinName 12Vgate1 +PINATTR SpiceOrder 31 +PIN -256 -496 TOP 8 +PINATTR PinName 12Vsense1 +PINATTR SpiceOrder 32 +PIN -384 -496 TOP 8 +PINATTR PinName 12Vin1 +PINATTR SpiceOrder 33 +PIN -576 -96 LEFT 8 +PINATTR PinName _Pgood1 +PINATTR SpiceOrder 34 +PIN -576 -160 LEFT 8 +PINATTR PinName _AuxFault1 +PINATTR SpiceOrder 35 +PIN -576 -224 LEFT 8 +PINATTR PinName _Fault1 +PINATTR SpiceOrder 36 +PIN -576 -32 LEFT 8 +PINATTR PinName _AUXpgood1 +PINATTR SpiceOrder 37 +PIN -576 32 LEFT 8 +PINATTR PinName _AUXpgood2 +PINATTR SpiceOrder 38 diff --git a/spice/copy/sym/SpecialFunctions/LTC4265.asy b/spice/copy/sym/SpecialFunctions/LTC4265.asy new file mode 100755 index 0000000..582f011 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4265.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 191 -176 -192 +TEXT 0 0 Center 2 LT +WINDOW 3 0 48 Center 2 +WINDOW 0 0 -48 Center 2 +SYMATTR Value LTC4265 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4265.sub +SYMATTR Description IEEE802.3 at High Power PD Interface Controller with 2-Event Classification Recognition +SYMATTR Value2 LTC4265 +PIN -176 -160 LEFT 8 +PINATTR PinName SHDN +PINATTR SpiceOrder 1 +PIN -176 -80 LEFT 8 +PINATTR PinName _T2PSE +PINATTR SpiceOrder 2 +PIN -176 0 LEFT 8 +PINATTR PinName Rclass +PINATTR SpiceOrder 3 +PIN -176 80 LEFT 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 5 +PIN -176 160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 6 +PIN 176 160 RIGHT 8 +PINATTR PinName Vout1 +PINATTR SpiceOrder 7 +PIN 176 80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 176 0 RIGHT 8 +PINATTR PinName PWRGD +PINATTR SpiceOrder 9 +PIN 176 -80 RIGHT 8 +PINATTR PinName _PWRGD +PINATTR SpiceOrder 10 +PIN 176 -160 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC4300A-1.asy b/spice/copy/sym/SpecialFunctions/LTC4300A-1.asy new file mode 100755 index 0000000..d6d2fee --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4300A-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -160 -128 160 128 +TEXT 0 -32 Center 2 LT +WINDOW 0 8 -144 Left 2 +WINDOW 3 0 40 Center 2 +SYMATTR Value LTC4300A-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4300A-1.sub +SYMATTR Value2 LTC4300A-1 +SYMATTR Description Hot Swappable 2-Wire Bus Buffers Note: Stop Bit and Bus Idle detection not modeled +PIN -160 80 LEFT 8 +PINATTR PinName ENABLE +PINATTR SpiceOrder 1 +PIN 160 -80 RIGHT 8 +PINATTR PinName SCLOUT +PINATTR SpiceOrder 2 +PIN -160 -80 LEFT 8 +PINATTR PinName SCLIN +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 160 80 RIGHT 8 +PINATTR PinName READY +PINATTR SpiceOrder 5 +PIN -160 0 LEFT 8 +PINATTR PinName SDAIN +PINATTR SpiceOrder 6 +PIN 160 0 RIGHT 8 +PINATTR PinName SDAOUT +PINATTR SpiceOrder 7 +PIN 0 -128 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC4350.asy b/spice/copy/sym/SpecialFunctions/LTC4350.asy new file mode 100755 index 0000000..1557346 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4350.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 240 208 -240 -176 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC4350 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4350.sub +SYMATTR Value2 LTC4350 +SYMATTR Description Hot Swappable Load Share Controller +PIN -240 -32 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 1 +PIN -240 48 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -240 128 LEFT 8 +PINATTR PinName Timer +PINATTR SpiceOrder 3 +PIN -176 208 BOTTOM 8 +PINATTR PinName Gain +PINATTR SpiceOrder 4 +PIN 160 208 BOTTOM 8 +PINATTR PinName Comp2 +PINATTR SpiceOrder 5 +PIN -64 208 BOTTOM 8 +PINATTR PinName Comp1 +PINATTR SpiceOrder 6 +PIN 240 64 RIGHT 8 +PINATTR PinName SB +PINATTR SpiceOrder 7 +PIN 48 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 240 -128 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 9 +PIN 240 128 RIGHT 8 +PINATTR PinName Rset +PINATTR SpiceOrder 10 +PIN 240 -64 RIGHT 8 +PINATTR PinName Iout +PINATTR SpiceOrder 11 +PIN 112 -176 TOP 8 +PINATTR PinName R- +PINATTR SpiceOrder 12 +PIN 0 -176 TOP 8 +PINATTR PinName R+ +PINATTR SpiceOrder 13 +PIN -128 -176 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 14 +PIN 240 0 RIGHT 8 +PINATTR PinName Status +PINATTR SpiceOrder 15 +PIN -240 -112 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC4352.asy b/spice/copy/sym/SpecialFunctions/LTC4352.asy new file mode 100755 index 0000000..d6211d1 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4352.asy @@ -0,0 +1,47 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -176 288 160 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC4352 +SYMATTR SpiceModel LTC4352.sub +SYMATTR Description Low Voltage Ideal Diode Controller with Monitoring +SYMATTR Value2 LTC4352 +SYMATTR Prefix X +PIN 0 -176 TOP 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -288 -112 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -288 -32 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 3 +PIN -288 48 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 4 +PIN 288 -32 RIGHT 8 +PINATTR PinName _Status +PINATTR SpiceOrder 5 +PIN 288 48 RIGHT 8 +PINATTR PinName _Fault +PINATTR SpiceOrder 6 +PIN -288 128 LEFT 8 +PINATTR PinName Rev +PINATTR SpiceOrder 7 +PIN 224 -176 TOP 8 +PINATTR PinName Out +PINATTR SpiceOrder 8 +PIN 0 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN -224 -176 TOP 8 +PINATTR PinName CPO +PINATTR SpiceOrder 10 +PIN 112 -176 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 11 +PIN -112 -176 TOP 8 +PINATTR PinName Source +PINATTR SpiceOrder 12 diff --git a/spice/copy/sym/SpecialFunctions/LTC4353.asy b/spice/copy/sym/SpecialFunctions/LTC4353.asy new file mode 100755 index 0000000..5c4aaef --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4353.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -160 256 128 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Bottom 2 +WINDOW 3 0 46 Center 2 +SYMATTR Value LTC4353 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4353.sub +SYMATTR Value2 LTC4353 +SYMATTR Description Dual Low Voltage Ideal Diode Controller +PIN -224 64 LEFT 8 +PINATTR PinName _EN2 +PINATTR SpiceOrder 1 +PIN -32 128 BOTTOM 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 2 +PIN 64 128 BOTTOM 8 +PINATTR PinName GATE2 +PINATTR SpiceOrder 3 +PIN -128 128 BOTTOM 8 +PINATTR PinName CPO2 +PINATTR SpiceOrder 4 +PIN 160 128 BOTTOM 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 5 +PIN 256 16 RIGHT 8 +PINATTR PinName _ONST2 +PINATTR SpiceOrder 6 +PIN 256 -48 RIGHT 8 +PINATTR PinName _ONST1 +PINATTR SpiceOrder 7 +PIN 160 -160 TOP 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 8 +PIN -128 -160 TOP 8 +PINATTR PinName CPO1 +PINATTR SpiceOrder 9 +PIN 64 -160 TOP 8 +PINATTR PinName GATE1 +PINATTR SpiceOrder 10 +PIN -32 -160 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 11 +PIN -224 -48 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 12 +PIN -224 16 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 +PIN -224 -96 LEFT 8 +PINATTR PinName _EN1 +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/SpecialFunctions/LTC4355.asy b/spice/copy/sym/SpecialFunctions/LTC4355.asy new file mode 100755 index 0000000..da6f1ae --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4355.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 336 176 -320 -160 +TEXT 0 8 Center 2 LT +WINDOW 3 0 56 Center 2 +WINDOW 0 0 -40 Center 2 +SYMATTR Value LTC4355 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4355 +SYMATTR Description Positive High Voltage Ideal Diode-OR with Input Supply and Fuse Monitors +SYMATTR ModelFile LTC4355.sub +SYMATTR Value2 LTC4355 +PIN -224 -160 TOP 8 +PINATTR PinName In1 +PINATTR SpiceOrder 1 +PIN -112 -160 TOP 8 +PINATTR PinName Gate1 +PINATTR SpiceOrder 2 +PIN 224 -160 TOP 8 +PINATTR PinName Out +PINATTR SpiceOrder 3 +PIN 112 -160 TOP 8 +PINATTR PinName Gate2 +PINATTR SpiceOrder 4 +PIN 0 -160 TOP 8 +PINATTR PinName In2 +PINATTR SpiceOrder 5 +PIN 336 -80 RIGHT 8 +PINATTR PinName _VdsFlt +PINATTR SpiceOrder 6 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -320 112 LEFT 8 +PINATTR PinName Set +PINATTR SpiceOrder 8 +PIN -320 16 LEFT 8 +PINATTR PinName Mon2 +PINATTR SpiceOrder 9 +PIN 336 112 RIGHT 8 +PINATTR PinName _PwrFlt2 +PINATTR SpiceOrder 10 +PIN 336 16 RIGHT 8 +PINATTR PinName _FuseFlt2 +PINATTR SpiceOrder 11 +PIN 336 -32 RIGHT 8 +PINATTR PinName _FuseFlt1 +PINATTR SpiceOrder 12 +PIN 336 64 RIGHT 8 +PINATTR PinName _PwrFlt1 +PINATTR SpiceOrder 13 +PIN -320 -80 LEFT 8 +PINATTR PinName Mon1 +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/SpecialFunctions/LTC4357.asy b/spice/copy/sym/SpecialFunctions/LTC4357.asy new file mode 100755 index 0000000..f5bfc2f --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4357.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 128 112 -128 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 39 Center 2 +WINDOW 0 0 -40 Center 2 +SYMATTR Value LTC4357 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4357.sub +SYMATTR Value2 LTC4357 +SYMATTR Description Positive High Voltage Ideal Diode Controller +PIN 128 -48 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -128 -48 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 0 -112 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 3 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 128 48 RIGHT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC4358.asy b/spice/copy/sym/SpecialFunctions/LTC4358.asy new file mode 100755 index 0000000..e3b007b --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4358.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 128 112 -128 -112 +TEXT 0 0 Center 2 LT +WINDOW 3 0 39 Center 2 +WINDOW 0 0 -40 Center 2 +SYMATTR Value LTC4358 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4358.sub +SYMATTR Value2 LTC4358 +SYMATTR Description 5A Ideal Diode +PIN 128 0 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -128 -64 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 2 +PIN 128 -64 RIGHT 8 +PINATTR PinName Drain +PINATTR SpiceOrder 3 +PIN -128 64 LEFT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 4 +PIN 128 64 RIGHT 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 5 +PIN 0 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC4359.asy b/spice/copy/sym/SpecialFunctions/LTC4359.asy new file mode 100755 index 0000000..f6e7e3d --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4359.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -240 -128 240 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 1 47 Center 2 +SYMATTR Value LTC4359 +SYMATTR SpiceModel LTC4359.sub +SYMATTR Description Ideal Diode Controller with Reverse Input Protection +SYMATTR Value2 LTC4359 +SYMATTR Prefix X +PIN 192 -128 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 64 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 2 +PIN -64 -128 TOP 8 +PINATTR PinName SOURCE +PINATTR SpiceOrder 3 +PIN -192 -128 TOP 8 +PINATTR PinName IN +PINATTR SpiceOrder 4 +PIN -240 0 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 5 +PIN 0 128 BOTTOM 8 +PINATTR PinName VSS +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC4360-1.asy b/spice/copy/sym/SpecialFunctions/LTC4360-1.asy new file mode 100755 index 0000000..e466983 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4360-1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -145 -176 143 160 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC4360-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4360-1.sub +SYMATTR Value2 LTC4360-1 +SYMATTR Description Overvoltage Protection Controller +PIN -144 -128 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 1 +PIN 0 -176 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName _On +PINATTR SpiceOrder 3 +PIN 144 -128 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 4 +PIN 144 32 RIGHT 8 +PINATTR PinName _Pwrgd +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC4360-2.asy b/spice/copy/sym/SpecialFunctions/LTC4360-2.asy new file mode 100755 index 0000000..91b77e6 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4360-2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -145 -176 143 160 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC4360-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4360-2.sub +SYMATTR Value2 LTC4360-2 +SYMATTR Description Overvoltage Protection Controller +PIN -144 -128 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 1 +PIN 0 -176 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 2 +PIN -144 32 LEFT 8 +PINATTR PinName Gp +PINATTR SpiceOrder 3 +PIN 144 -128 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 4 +PIN 144 32 RIGHT 8 +PINATTR PinName _Pwrgd +PINATTR SpiceOrder 5 +PIN 0 160 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC4361-1.asy b/spice/copy/sym/SpecialFunctions/LTC4361-1.asy new file mode 100755 index 0000000..975e541 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4361-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -145 -176 143 160 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC4361-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4361-1.sub +SYMATTR Value2 LTC4361-1 +SYMATTR Description Overvoltage/Overcurrent Protection Controller +PIN -144 32 LEFT 8 +PINATTR PinName GP +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 2 +PIN -144 -128 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _On +PINATTR SpiceOrder 5 +PIN 144 -128 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 6 +PIN 144 32 RIGHT 8 +PINATTR PinName _Pwrgd +PINATTR SpiceOrder 7 +PIN 0 160 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC4361-2.asy b/spice/copy/sym/SpecialFunctions/LTC4361-2.asy new file mode 100755 index 0000000..b59d251 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4361-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -145 -176 143 160 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC4361-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4361-2.sub +SYMATTR Value2 LTC4361-2 +SYMATTR Description Overvoltage/Overcurrent Protection Controller +PIN -144 32 LEFT 8 +PINATTR PinName GP +PINATTR SpiceOrder 1 +PIN -144 -48 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 2 +PIN -144 -128 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 0 -176 TOP 8 +PINATTR PinName Gate +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _On +PINATTR SpiceOrder 5 +PIN 144 -128 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 6 +PIN 144 32 RIGHT 8 +PINATTR PinName _Pwrgd +PINATTR SpiceOrder 7 +PIN 0 160 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC4362-1.asy b/spice/copy/sym/SpecialFunctions/LTC4362-1.asy new file mode 100755 index 0000000..9a61ac1 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4362-1.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -145 -176 143 160 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC4362-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4362-1.sub +SYMATTR Value2 LTC4362-1 +SYMATTR Description 1.2A Overvoltage/Overcurrent Protector +PIN -144 32 LEFT 8 +PINATTR PinName GP +PINATTR SpiceOrder 1 +PIN -144 -128 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 144 -128 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _On +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName _Pwrgd +PINATTR SpiceOrder 6 +PIN 0 160 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/SpecialFunctions/LTC4362-2.asy b/spice/copy/sym/SpecialFunctions/LTC4362-2.asy new file mode 100755 index 0000000..d0be01e --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4362-2.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -145 -176 143 160 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 72 Center 2 +SYMATTR Value LTC4362-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4362-2.sub +SYMATTR Value2 LTC4362-2 +SYMATTR Description 1.2A Overvoltage/Overcurrent Protector +PIN -144 32 LEFT 8 +PINATTR PinName GP +PINATTR SpiceOrder 1 +PIN -144 -128 LEFT 8 +PINATTR PinName In +PINATTR SpiceOrder 2 +PIN -144 -80 LEFT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 3 +PIN 144 -128 RIGHT 8 +PINATTR PinName Out +PINATTR SpiceOrder 4 +PIN -144 96 LEFT 8 +PINATTR PinName _On +PINATTR SpiceOrder 5 +PIN 144 32 RIGHT 8 +PINATTR PinName _Pwrgd +PINATTR SpiceOrder 6 +PIN 0 160 BOTTOM 8 +PINATTR PinName Gnd +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/SpecialFunctions/LTC4364-1.asy b/spice/copy/sym/SpecialFunctions/LTC4364-1.asy new file mode 100755 index 0000000..2456541 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4364-1.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal -496 -160 496 160 +TEXT 0 -1 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 -5 49 Center 2 +SYMATTR Value LTC4364-1 +SYMATTR Description Surge Stopper with Ideal Diode +SYMATTR Prefix X +SYMATTR SpiceModel LTC4364-1.sub +SYMATTR Value2 LTC4364-1 +PIN 400 -160 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 240 -160 TOP 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 80 -160 TOP 8 +PINATTR PinName DGATE +PINATTR SpiceOrder 3 +PIN -80 -160 TOP 8 +PINATTR PinName SOURCE +PINATTR SpiceOrder 4 +PIN -240 -160 TOP 8 +PINATTR PinName HGATE +PINATTR SpiceOrder 5 +PIN -400 -160 TOP 8 +PINATTR PinName VCC +PINATTR SpiceOrder 6 +PIN -496 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -496 0 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 8 +PIN -496 80 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 9 +PIN -176 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 496 0 RIGHT 8 +PINATTR PinName _FLT +PINATTR SpiceOrder 11 +PIN 496 -80 RIGHT 8 +PINATTR PinName ENOUT +PINATTR SpiceOrder 12 +PIN 160 160 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 13 +PIN 496 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/SpecialFunctions/LTC4364-2.asy b/spice/copy/sym/SpecialFunctions/LTC4364-2.asy new file mode 100755 index 0000000..cf05fa3 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4364-2.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal -496 -160 496 160 +TEXT 0 -1 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 -5 49 Center 2 +SYMATTR Value LTC4364-2 +SYMATTR Description Surge Stopper with Ideal Diode +SYMATTR Prefix X +SYMATTR SpiceModel LTC4364-2.sub +SYMATTR Value2 LTC4364-2 +PIN 400 -160 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 240 -160 TOP 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 2 +PIN 80 -160 TOP 8 +PINATTR PinName DGATE +PINATTR SpiceOrder 3 +PIN -80 -160 TOP 8 +PINATTR PinName SOURCE +PINATTR SpiceOrder 4 +PIN -240 -160 TOP 8 +PINATTR PinName HGATE +PINATTR SpiceOrder 5 +PIN -400 -160 TOP 8 +PINATTR PinName VCC +PINATTR SpiceOrder 6 +PIN -496 -80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 7 +PIN -496 0 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 8 +PIN -496 80 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 9 +PIN -176 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 10 +PIN 496 0 RIGHT 8 +PINATTR PinName _FLT +PINATTR SpiceOrder 11 +PIN 496 -80 RIGHT 8 +PINATTR PinName ENOUT +PINATTR SpiceOrder 12 +PIN 160 160 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 13 +PIN 496 80 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 14 diff --git a/spice/copy/sym/SpecialFunctions/LTC4365-1.asy b/spice/copy/sym/SpecialFunctions/LTC4365-1.asy new file mode 100755 index 0000000..1941139 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4365-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 80 -160 -224 +TEXT -3 -88 Center 2 LT +WINDOW 3 -3 -24 Center 2 +WINDOW 0 -3 -152 Center 2 +SYMATTR Value LTC4365-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4365-1.sub +SYMATTR Description UV, OV and Reverse Supply Protection Controller +SYMATTR Value2 LTC4365-1 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -160 32 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -160 -32 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 3 +PIN -160 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 0 -224 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 5 +PIN 144 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 7 +PIN -160 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC4365.asy b/spice/copy/sym/SpecialFunctions/LTC4365.asy new file mode 100755 index 0000000..fc53879 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4365.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 80 -160 -224 +TEXT -3 -88 Center 2 LT +WINDOW 3 -3 -24 Center 2 +WINDOW 0 -3 -152 Center 2 +SYMATTR Value LTC4365 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4365.sub +SYMATTR Description UV, OV and Reverse Supply Protection Controller +SYMATTR Value2 LTC4365 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -160 32 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -160 -32 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 3 +PIN -160 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 0 -224 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 5 +PIN 144 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 7 +PIN -160 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC4366-1.asy b/spice/copy/sym/SpecialFunctions/LTC4366-1.asy new file mode 100755 index 0000000..e2c8da8 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4366-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 65 -143 -145 +TEXT 6 -40 Center 2 LT +WINDOW 3 6 -1 Center 2 +WINDOW 0 6 -80 Center 2 +SYMATTR Value LTC4366-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4366-1.sub +SYMATTR Description Very High Voltage Overvoltage Protector +SYMATTR Value2 LTC4366-1 +PIN 0 -144 TOP 8 +PINATTR PinName VDD +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName _SD +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName TIMER +PINATTR SpiceOrder 3 +PIN -48 64 BOTTOM 8 +PINATTR PinName VSS +PINATTR SpiceOrder 4 +PIN 48 64 BOTTOM 8 +PINATTR PinName BASE +PINATTR SpiceOrder 5 +PIN 144 16 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 144 -80 RIGHT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC4366-2.asy b/spice/copy/sym/SpecialFunctions/LTC4366-2.asy new file mode 100755 index 0000000..395b092 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4366-2.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 144 65 -143 -145 +TEXT 6 -40 Center 2 LT +WINDOW 3 6 -1 Center 2 +WINDOW 0 6 -80 Center 2 +SYMATTR Value LTC4366-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4366-2.sub +SYMATTR Value2 LTC4366-2 +SYMATTR Description Very High Voltage Overvoltage Protector +PIN 0 -144 TOP 8 +PINATTR PinName VDD +PINATTR SpiceOrder 1 +PIN -144 -80 LEFT 8 +PINATTR PinName _SD +PINATTR SpiceOrder 2 +PIN -144 -32 LEFT 8 +PINATTR PinName TIMER +PINATTR SpiceOrder 3 +PIN -48 64 BOTTOM 8 +PINATTR PinName VSS +PINATTR SpiceOrder 4 +PIN 48 64 BOTTOM 8 +PINATTR PinName BASE +PINATTR SpiceOrder 5 +PIN 144 16 RIGHT 8 +PINATTR PinName FB +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 7 +PIN 144 -80 RIGHT 8 +PINATTR PinName GATE +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC4367-1.asy b/spice/copy/sym/SpecialFunctions/LTC4367-1.asy new file mode 100755 index 0000000..f1c2c47 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4367-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 80 -160 -224 +TEXT -3 -88 Center 2 LT +WINDOW 3 -5 0 Center 2 +WINDOW 0 -3 -152 Center 2 +SYMATTR Value LTC4367-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4367-1.sub +SYMATTR Description 100V OV, UV and Reverse Supply Protection Controller +SYMATTR Value2 LTC4367-1 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -160 32 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -160 -32 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 3 +PIN -160 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 0 -224 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 5 +PIN 144 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 7 +PIN -160 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC4367.asy b/spice/copy/sym/SpecialFunctions/LTC4367.asy new file mode 100755 index 0000000..15d201a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4367.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 144 80 -160 -224 +TEXT -3 -88 Center 2 LT +WINDOW 3 -3 -24 Center 2 +WINDOW 0 -3 -152 Center 2 +SYMATTR Value LTC4367 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4367.sub +SYMATTR Description 100V OV, UV and Reverse Supply Protection Controller +SYMATTR Value2 LTC4367 +PIN 0 80 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 1 +PIN -160 32 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 2 +PIN -160 -32 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 3 +PIN -160 -160 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 4 +PIN 0 -224 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 5 +PIN 144 -160 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 6 +PIN 144 -32 RIGHT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 7 +PIN -160 -96 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC4368-1.asy b/spice/copy/sym/SpecialFunctions/LTC4368-1.asy new file mode 100755 index 0000000..913cf44 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4368-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -208 +TEXT 0 0 Center 2 LT +WINDOW 3 0 112 Center 2 +WINDOW 0 0 -112 Center 2 +SYMATTR Value LTC4368-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4368-1.sub +SYMATTR Value2 LTC4368-1 +SYMATTR Description 100V Overvoltage, Overcurrent and Reverse Supply Protection Controller +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 2 +PIN -160 144 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 3 +PIN 160 64 RIGHT 8 +PINATTR PinName RETRY +PINATTR SpiceOrder 4 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 160 -64 RIGHT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 7 +PIN 96 -208 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 0 -208 TOP 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 9 +PIN -96 -208 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4368-2.asy b/spice/copy/sym/SpecialFunctions/LTC4368-2.asy new file mode 100755 index 0000000..0cf68ae --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4368-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 160 208 -160 -208 +TEXT 0 0 Center 2 LT +WINDOW 3 0 112 Center 2 +WINDOW 0 0 -112 Center 2 +SYMATTR Value LTC4368-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4368-2.sub +SYMATTR Value2 LTC4368-2 +SYMATTR Description 100V Overvoltage, Overcurrent and Reverse Supply Protection Controller +PIN -160 -144 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -160 48 LEFT 8 +PINATTR PinName UV +PINATTR SpiceOrder 2 +PIN -160 144 LEFT 8 +PINATTR PinName OV +PINATTR SpiceOrder 3 +PIN 160 64 RIGHT 8 +PINATTR PinName RETRY +PINATTR SpiceOrder 4 +PIN 0 208 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN -160 -48 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 6 +PIN 160 -64 RIGHT 8 +PINATTR PinName _FAULT +PINATTR SpiceOrder 7 +PIN 96 -208 TOP 8 +PINATTR PinName Vout +PINATTR SpiceOrder 8 +PIN 0 -208 TOP 8 +PINATTR PinName SENSE +PINATTR SpiceOrder 9 +PIN -96 -208 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4370.asy b/spice/copy/sym/SpecialFunctions/LTC4370.asy new file mode 100755 index 0000000..3509ebd --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4370.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -224 -160 256 128 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -64 Bottom 2 +WINDOW 3 0 46 Center 2 +SYMATTR Value LTC4370 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4370.sub +SYMATTR Value2 LTC4370 +SYMATTR Description Two-Supply Diode-OR Current Balancing Controlller +PIN -224 80 LEFT 8 +PINATTR PinName _EN2 +PINATTR SpiceOrder 1 +PIN -224 32 LEFT 8 +PINATTR PinName RANGE +PINATTR SpiceOrder 2 +PIN 256 80 RIGHT 8 +PINATTR PinName COMP +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName Vin2 +PINATTR SpiceOrder 4 +PIN 128 128 BOTTOM 8 +PINATTR PinName GATE2 +PINATTR SpiceOrder 5 +PIN -96 128 BOTTOM 8 +PINATTR PinName CPO2 +PINATTR SpiceOrder 6 +PIN 256 32 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 7 +PIN 256 -16 RIGHT 8 +PINATTR PinName FETON2 +PINATTR SpiceOrder 8 +PIN 256 -64 RIGHT 8 +PINATTR PinName FETON1 +PINATTR SpiceOrder 9 +PIN 256 -112 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 10 +PIN -96 -160 TOP 8 +PINATTR PinName CPO1 +PINATTR SpiceOrder 11 +PIN 128 -160 TOP 8 +PINATTR PinName GATE1 +PINATTR SpiceOrder 12 +PIN 0 -160 TOP 8 +PINATTR PinName Vin1 +PINATTR SpiceOrder 13 +PIN -224 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 14 +PIN -224 -16 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 15 +PIN -224 -112 LEFT 8 +PINATTR PinName _EN1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC4371.asy b/spice/copy/sym/SpecialFunctions/LTC4371.asy new file mode 100755 index 0000000..b863fe3 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4371.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -432 -160 432 192 +TEXT 0 0 Center 2 LT +WINDOW 3 0 -41 Center 2 +WINDOW 0 0 41 Center 2 +SYMATTR Value LTC4371 +SYMATTR Prefix X +SYMATTR Description Dual Negative Voltage Ideal Diode-OR Controller +SYMATTR SpiceModel LTC4371 +SYMATTR ModelFile LTC4371.sub +PIN -336 192 BOTTOM 8 +PINATTR PinName DA +PINATTR SpiceOrder 1 +PIN -112 192 BOTTOM 8 +PINATTR PinName GA +PINATTR SpiceOrder 2 +PIN 112 192 BOTTOM 8 +PINATTR PinName SA +PINATTR SpiceOrder 3 +PIN -112 -160 TOP 8 +PINATTR PinName Vz +PINATTR SpiceOrder 4 +PIN 112 -160 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 5 +PIN 336 192 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 432 0 RIGHT 8 +PINATTR PinName FaultB +PINATTR SpiceOrder 7 +PIN 224 192 BOTTOM 8 +PINATTR PinName SB +PINATTR SpiceOrder 8 +PIN 0 192 BOTTOM 8 +PINATTR PinName GB +PINATTR SpiceOrder 9 +PIN -224 192 BOTTOM 8 +PINATTR PinName DB +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4380-1.asy b/spice/copy/sym/SpecialFunctions/LTC4380-1.asy new file mode 100755 index 0000000..10e188f --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4380-1.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -128 272 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 62 Center 2 +SYMATTR Value LTC4380-1 +SYMATTR Description Low-Current Surge Stopper +SYMATTR Prefix X +SYMATTR ModelFile LTC4380-1.sub +PIN 272 64 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 1 +PIN 208 -128 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 80 -128 TOP 8 +PINATTR PinName SNS +PINATTR SpiceOrder 3 +PIN -48 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 4 +PIN -288 -32 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN -224 -128 TOP 8 +PINATTR PinName DRN +PINATTR SpiceOrder 6 +PIN -288 64 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 7 +PIN 112 128 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 8 +PIN -80 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 272 -32 RIGHT 8 +PINATTR PinName FLTB +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4380-2.asy b/spice/copy/sym/SpecialFunctions/LTC4380-2.asy new file mode 100755 index 0000000..127e707 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4380-2.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -128 272 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 62 Center 2 +SYMATTR Value LTC4380-2 +SYMATTR Description Low-Current Surge Stopper +SYMATTR Prefix X +SYMATTR ModelFile LTC4380-2.sub +PIN 272 64 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 1 +PIN 208 -128 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 80 -128 TOP 8 +PINATTR PinName SNS +PINATTR SpiceOrder 3 +PIN -48 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 4 +PIN -288 -32 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN -224 -128 TOP 8 +PINATTR PinName DRN +PINATTR SpiceOrder 6 +PIN -288 64 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 7 +PIN 112 128 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 8 +PIN -80 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 272 -32 RIGHT 8 +PINATTR PinName FLTB +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4380-3.asy b/spice/copy/sym/SpecialFunctions/LTC4380-3.asy new file mode 100755 index 0000000..b2e2a84 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4380-3.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -128 272 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 62 Center 2 +SYMATTR Value LTC4380-3 +SYMATTR Description Low-Current Surge Stopper +SYMATTR Prefix X +SYMATTR ModelFile LTC4380-3.sub +PIN 272 64 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 1 +PIN 208 -128 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 80 -128 TOP 8 +PINATTR PinName SNS +PINATTR SpiceOrder 3 +PIN -48 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 4 +PIN -288 -32 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN -224 -128 TOP 8 +PINATTR PinName DRN +PINATTR SpiceOrder 6 +PIN -288 64 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 7 +PIN 112 128 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 8 +PIN -80 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 272 -32 RIGHT 8 +PINATTR PinName FLTB +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4380-4.asy b/spice/copy/sym/SpecialFunctions/LTC4380-4.asy new file mode 100755 index 0000000..8d95a80 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4380-4.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -288 -128 272 128 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 62 Center 2 +SYMATTR Value LTC4380-4 +SYMATTR Description Low-Current Surge Stopper +SYMATTR Prefix X +SYMATTR ModelFile LTC4380-4.sub +PIN 272 64 RIGHT 8 +PINATTR PinName SEL +PINATTR SpiceOrder 1 +PIN 208 -128 TOP 8 +PINATTR PinName OUT +PINATTR SpiceOrder 2 +PIN 80 -128 TOP 8 +PINATTR PinName SNS +PINATTR SpiceOrder 3 +PIN -48 -128 TOP 8 +PINATTR PinName GATE +PINATTR SpiceOrder 4 +PIN -288 -32 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN -224 -128 TOP 8 +PINATTR PinName DRN +PINATTR SpiceOrder 6 +PIN -288 64 LEFT 8 +PINATTR PinName ON +PINATTR SpiceOrder 7 +PIN 112 128 BOTTOM 8 +PINATTR PinName TMR +PINATTR SpiceOrder 8 +PIN -80 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 9 +PIN 272 -32 RIGHT 8 +PINATTR PinName FLTB +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4411.asy b/spice/copy/sym/SpecialFunctions/LTC4411.asy new file mode 100755 index 0000000..f18104a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4411.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 1 64 Center 2 +SYMATTR Value LTC4411 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4411.sub +SYMATTR Value2 LTC4411 +SYMATTR Description 2.6A Low Loss Ideal diode in ThinSOT +PIN -128 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 80 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName STAT +PINATTR SpiceOrder 4 +PIN 128 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC4413-1.asy b/spice/copy/sym/SpecialFunctions/LTC4413-1.asy new file mode 100755 index 0000000..4abee7e --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4413-1.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 95 Center 2 +SYMATTR Value LTC4413-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4413-1.sub +SYMATTR Value2 LTC4413-1 +SYMATTR Description Dual 2.6A, 2.5V to 5.5V Fast Ideal Diodes in 3mm×3mm DFN +PIN -128 -128 LEFT 8 +PINATTR PinName INA +PINATTR SpiceOrder 1 +PIN -128 -64 LEFT 8 +PINATTR PinName ENBA +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 64 LEFT 8 +PINATTR PinName ENBB +PINATTR SpiceOrder 4 +PIN -128 128 LEFT 8 +PINATTR PinName INB +PINATTR SpiceOrder 5 +PIN 128 128 RIGHT 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 6 +PIN 128 0 RIGHT 8 +PINATTR PinName STAT +PINATTR SpiceOrder 9 +PIN 128 -128 RIGHT 8 +PINATTR PinName OUTA +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4413-2.asy b/spice/copy/sym/SpecialFunctions/LTC4413-2.asy new file mode 100755 index 0000000..e9ebf56 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4413-2.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 95 Center 2 +SYMATTR Value LTC4413-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4413-2.sub +SYMATTR Value2 LTC4413-2 +SYMATTR Description Dual 2.6A, 2.5V to 5.5V Fast Ideal Diodes in 3mm×3mm DFN +PIN -128 -128 LEFT 8 +PINATTR PinName INA +PINATTR SpiceOrder 1 +PIN -128 -64 LEFT 8 +PINATTR PinName ENBA +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 64 LEFT 8 +PINATTR PinName ENBB +PINATTR SpiceOrder 4 +PIN -128 128 LEFT 8 +PINATTR PinName INB +PINATTR SpiceOrder 5 +PIN 128 128 RIGHT 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 6 +PIN 128 0 RIGHT 8 +PINATTR PinName OVP +PINATTR SpiceOrder 7 +PIN 128 -64 RIGHT 8 +PINATTR PinName OVI +PINATTR SpiceOrder 8 +PIN 128 64 RIGHT 8 +PINATTR PinName STAT +PINATTR SpiceOrder 9 +PIN 128 -128 RIGHT 8 +PINATTR PinName OUTA +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4413.asy b/spice/copy/sym/SpecialFunctions/LTC4413.asy new file mode 100755 index 0000000..78e60cd --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4413.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -160 128 160 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -96 Center 2 +WINDOW 3 0 95 Center 2 +SYMATTR Value LTC4413 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4413.sub +SYMATTR Value2 LTC4413 +SYMATTR Description Dual 2.6A, 2.5V to 5.5V Ideal Diodes in 3mm×3mm DFN +PIN -128 -128 LEFT 8 +PINATTR PinName INA +PINATTR SpiceOrder 1 +PIN -128 -64 LEFT 8 +PINATTR PinName ENBA +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 64 LEFT 8 +PINATTR PinName ENBB +PINATTR SpiceOrder 4 +PIN -128 128 LEFT 8 +PINATTR PinName INB +PINATTR SpiceOrder 5 +PIN 128 128 RIGHT 8 +PINATTR PinName OUTB +PINATTR SpiceOrder 6 +PIN 128 0 RIGHT 8 +PINATTR PinName STAT +PINATTR SpiceOrder 9 +PIN 128 -128 RIGHT 8 +PINATTR PinName OUTA +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4414.asy b/spice/copy/sym/SpecialFunctions/LTC4414.asy new file mode 100755 index 0000000..0f57770 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4414.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -112 128 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC4414 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4414.sub +SYMATTR Value2 LTC4414 +SYMATTR Description 36V, Low Loss PowerPath Controller for Large PFETs +PIN -128 -80 LEFT 8 +PINATTR PinName Vin +PINATTR SpiceOrder 1 +PIN -128 0 LEFT 8 +PINATTR PinName CTL +PINATTR SpiceOrder 2 +PIN -128 80 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName STAT +PINATTR SpiceOrder 4 +PIN 128 -80 RIGHT 8 +PINATTR PinName Sense +PINATTR SpiceOrder 5 +PIN 128 0 RIGHT 8 +PINATTR PinName Gate +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC4415.asy b/spice/copy/sym/SpecialFunctions/LTC4415.asy new file mode 100755 index 0000000..51d0e4f --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4415.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -208 128 240 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -176 Center 2 +WINDOW 3 0 144 Center 2 +SYMATTR Value LTC4415 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4415.sub +SYMATTR Value2 LTC4415 +SYMATTR Description Dual 4A Ideal Diodes with Adjustable Current Limit +PIN -128 -144 LEFT 8 +PINATTR PinName IN1 +PINATTR SpiceOrder 1 +PIN -128 -80 LEFT 8 +PINATTR PinName EN1 +PINATTR SpiceOrder 2 +PIN -128 -16 LEFT 8 +PINATTR PinName CLIM1 +PINATTR SpiceOrder 3 +PIN -128 48 LEFT 8 +PINATTR PinName CLIM2 +PINATTR SpiceOrder 4 +PIN -128 112 LEFT 8 +PINATTR PinName _EN2 +PINATTR SpiceOrder 5 +PIN -128 176 LEFT 8 +PINATTR PinName IN2 +PINATTR SpiceOrder 6 +PIN 128 176 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 7 +PIN 128 112 RIGHT 8 +PINATTR PinName _STAT2 +PINATTR SpiceOrder 8 +PIN 128 48 RIGHT 8 +PINATTR PinName _WARN2 +PINATTR SpiceOrder 9 +PIN 128 -16 RIGHT 8 +PINATTR PinName _WARN1 +PINATTR SpiceOrder 10 +PIN 128 -80 RIGHT 8 +PINATTR PinName _STAT1 +PINATTR SpiceOrder 11 +PIN 128 -144 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 12 +PIN 0 240 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 13 diff --git a/spice/copy/sym/SpecialFunctions/LTC4416-1.asy b/spice/copy/sym/SpecialFunctions/LTC4416-1.asy new file mode 100755 index 0000000..1d6da11 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4416-1.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 -192 -128 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC4416-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4416-1.sub +SYMATTR Value2 LTC4416-1 +SYMATTR Description 36V, Low Loss Dual PowerPath Controller for Large PFETs +PIN -128 80 LEFT 8 +PINATTR PinName H1 +PINATTR SpiceOrder 1 +PIN -128 -160 LEFT 8 +PINATTR PinName E1 +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 -80 LEFT 8 +PINATTR PinName _E2 +PINATTR SpiceOrder 4 +PIN -128 160 LEFT 8 +PINATTR PinName _H2 +PINATTR SpiceOrder 5 +PIN 128 80 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 6 +PIN 128 160 RIGHT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName Vs +PINATTR SpiceOrder 8 +PIN 128 -160 RIGHT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 9 +PIN 128 -80 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4416.asy b/spice/copy/sym/SpecialFunctions/LTC4416.asy new file mode 100755 index 0000000..4c972c3 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4416.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 128 -192 -128 192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC4416 +SYMATTR Prefix X +SYMATTR SpiceModel LTC4416.sub +SYMATTR Value2 LTC4416 +SYMATTR Description 36V, Low Loss Dual PowerPath Controller for Large PFETs +PIN -128 80 LEFT 8 +PINATTR PinName H1 +PINATTR SpiceOrder 1 +PIN -128 -160 LEFT 8 +PINATTR PinName E1 +PINATTR SpiceOrder 2 +PIN -128 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -128 -80 LEFT 8 +PINATTR PinName _E2 +PINATTR SpiceOrder 4 +PIN -128 160 LEFT 8 +PINATTR PinName _H2 +PINATTR SpiceOrder 5 +PIN 128 80 RIGHT 8 +PINATTR PinName G2 +PINATTR SpiceOrder 6 +PIN 128 160 RIGHT 8 +PINATTR PinName V2 +PINATTR SpiceOrder 7 +PIN 128 0 RIGHT 8 +PINATTR PinName Vs +PINATTR SpiceOrder 8 +PIN 128 -160 RIGHT 8 +PINATTR PinName V1 +PINATTR SpiceOrder 9 +PIN 128 -80 RIGHT 8 +PINATTR PinName G1 +PINATTR SpiceOrder 10 diff --git a/spice/copy/sym/SpecialFunctions/LTC4417.asy b/spice/copy/sym/SpecialFunctions/LTC4417.asy new file mode 100755 index 0000000..268ef66 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC4417.asy @@ -0,0 +1,84 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -304 -448 288 560 +TEXT 0 113 Center 2 LTC4417 +TEXT 0 0 Center 2 LT +TEXT 0 533 Center 2 GND +WINDOW 0 0 -96 Center 2 +SYMATTR Value LTC4417 +SYMATTR SpiceModel LTC4417.sub +SYMATTR Description High Voltage Triple Input Prioritized PowerPath(tm) Controller +SYMATTR Value2 LTC4417 +SYMATTR Prefix X +PIN 288 176 RIGHT 10 +PINATTR PinName EN +PINATTR SpiceOrder 1 +PIN 288 288 RIGHT 10 +PINATTR PinName _SHDN +PINATTR SpiceOrder 2 +PIN 288 400 RIGHT 10 +PINATTR PinName HYS +PINATTR SpiceOrder 3 +PIN -304 -272 LEFT 10 +PINATTR PinName UV1 +PINATTR SpiceOrder 4 +PIN -304 -160 LEFT 10 +PINATTR PinName OV1 +PINATTR SpiceOrder 5 +PIN -304 64 LEFT 10 +PINATTR PinName UV2 +PINATTR SpiceOrder 6 +PIN -304 176 LEFT 10 +PINATTR PinName OV2 +PINATTR SpiceOrder 7 +PIN -304 400 LEFT 10 +PINATTR PinName UV3 +PINATTR SpiceOrder 8 +PIN -304 512 LEFT 10 +PINATTR PinName OV3 +PINATTR SpiceOrder 9 +PIN 288 -160 RIGHT 10 +PINATTR PinName _VALID1 +PINATTR SpiceOrder 10 +PIN 288 -48 RIGHT 10 +PINATTR PinName _VALID2 +PINATTR SpiceOrder 11 +PIN 288 64 RIGHT 10 +PINATTR PinName _VALID3 +PINATTR SpiceOrder 12 +PIN 0 560 NONE 0 +PINATTR PinName VNEG +PINATTR SpiceOrder 13 +PIN 288 512 RIGHT 10 +PINATTR PinName CAS +PINATTR SpiceOrder 14 +PIN 288 -272 RIGHT 10 +PINATTR PinName Vout +PINATTR SpiceOrder 15 +PIN 240 -448 TOP 10 +PINATTR PinName G3 +PINATTR SpiceOrder 16 +PIN 176 -448 TOP 10 +PINATTR PinName VS3 +PINATTR SpiceOrder 17 +PIN 32 -448 TOP 10 +PINATTR PinName G2 +PINATTR SpiceOrder 18 +PIN -32 -448 TOP 10 +PINATTR PinName VS2 +PINATTR SpiceOrder 19 +PIN -176 -448 TOP 10 +PINATTR PinName G1 +PINATTR SpiceOrder 20 +PIN -240 -448 TOP 10 +PINATTR PinName VS1 +PINATTR SpiceOrder 21 +PIN -304 288 LEFT 10 +PINATTR PinName V3 +PINATTR SpiceOrder 22 +PIN -304 -48 LEFT 10 +PINATTR PinName V2 +PINATTR SpiceOrder 23 +PIN -304 -384 LEFT 10 +PINATTR PinName V1 +PINATTR SpiceOrder 24 diff --git a/spice/copy/sym/SpecialFunctions/LTC5505-1.asy b/spice/copy/sym/SpecialFunctions/LTC5505-1.asy new file mode 100755 index 0000000..2777de2 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC5505-1.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 8 -160 Left 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LTC5505-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5505-1.sub +SYMATTR Value2 LTC5505-1 +SYMATTR Description RF Power Detector with Buffered Output and >40dB Dynamic Range +PIN -128 -80 LEFT 8 +PINATTR PinName RFin +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC5505-2.asy b/spice/copy/sym/SpecialFunctions/LTC5505-2.asy new file mode 100755 index 0000000..bcc63ed --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC5505-2.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 8 -160 Left 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LTC5505-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5505-2.sub +SYMATTR Value2 LTC5505-2 +SYMATTR Description RF Power Detector with Buffered Output and >40dB Dynamic Range +PIN -128 -80 LEFT 8 +PINATTR PinName RFin +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 80 LEFT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 128 0 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN 0 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC5507.asy b/spice/copy/sym/SpecialFunctions/LTC5507.asy new file mode 100755 index 0000000..6e4eb43 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC5507.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -56 Center 2 +WINDOW 3 0 56 Center 2 +SYMATTR Value LTC5507 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5507.sub +SYMATTR Value2 LTC5507 +SYMATTR Description 100kHz to 1GHz RF Power Detector +PIN -128 112 LEFT 8 +PINATTR PinName RFin +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN 128 112 RIGHT 8 +PINATTR PinName _SHDN +PINATTR SpiceOrder 3 +PIN 128 -112 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 4 +PIN -128 -112 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 5 +PIN -128 0 LEFT 8 +PINATTR PinName PCAP +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC5532.asy b/spice/copy/sym/SpecialFunctions/LTC5532.asy new file mode 100755 index 0000000..dfe85cd --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC5532.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -144 128 144 +TEXT 0 -32 Center 2 LT +WINDOW 0 8 -160 Left 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value LTC5532 +SYMATTR Prefix X +SYMATTR SpiceModel LTC5532.sub +SYMATTR Value2 LTC5532 +SYMATTR Description Precision 300MHz to 7GHz RF Detector with Gain and Offset Adjustment +PIN -128 -80 LEFT 8 +PINATTR PinName RFin +PINATTR SpiceOrder 1 +PIN 0 144 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 80 LEFT 8 +PINATTR PinName Vos +PINATTR SpiceOrder 3 +PIN 128 80 RIGHT 8 +PINATTR PinName Vm +PINATTR SpiceOrder 4 +PIN 128 -80 RIGHT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 5 +PIN 0 -144 TOP 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC690.asy b/spice/copy/sym/SpecialFunctions/LTC690.asy new file mode 100755 index 0000000..075cae0 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC690.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 160 -176 -192 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC690 +SYMATTR Prefix X +SYMATTR SpiceModel LTC690.sub +SYMATTR Value2 LTC690 +SYMATTR Description Microprocessor Supervisory Circuit +PIN -176 -160 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -176 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -176 128 LEFT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 4 +PIN 176 128 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 176 32 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 6 +PIN 176 -64 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 7 +PIN 176 -160 RIGHT 8 +PINATTR PinName Vbatt +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC6900.asy b/spice/copy/sym/SpecialFunctions/LTC6900.asy new file mode 100755 index 0000000..64b6de9 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6900.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6900 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6900.sub +SYMATTR Value2 LTC6900 +SYMATTR Description Resistor Set SOT-23 Oscillator +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC6902.asy b/spice/copy/sym/SpecialFunctions/LTC6902.asy new file mode 100755 index 0000000..6347fb7 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6902.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -224 112 224 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -64 Center 2 +WINDOW 3 0 64 Center 2 +SYMATTR Value LTC6902 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6902.sub +SYMATTR Value2 LTC6902 +SYMATTR Description Multiphase Oscillator with Spread Spectrum Frequency Modulation +PIN -112 -192 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN 112 0 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 +PIN 112 -192 RIGHT 8 +PINATTR PinName SET +PINATTR SpiceOrder 10 +PIN -112 -96 LEFT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 2 +PIN -112 192 LEFT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 5 +PIN -112 0 LEFT 8 +PINATTR PinName PH +PINATTR SpiceOrder 3 +PIN -112 96 LEFT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 4 +PIN 112 192 RIGHT 8 +PINATTR PinName OUT3 +PINATTR SpiceOrder 6 +PIN 112 96 RIGHT 8 +PINATTR PinName OUT4 +PINATTR SpiceOrder 7 +PIN 112 -96 RIGHT 8 +PINATTR PinName MOD +PINATTR SpiceOrder 9 diff --git a/spice/copy/sym/SpecialFunctions/LTC6905-100.asy b/spice/copy/sym/SpecialFunctions/LTC6905-100.asy new file mode 100755 index 0000000..2dc05de --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6905-100.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC6905-100 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6905-100.sub +SYMATTR Value2 LTC6905-100 +SYMATTR Description Fixed Frequency SOT-23 Oscillator +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName 0E +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC6905-133.asy b/spice/copy/sym/SpecialFunctions/LTC6905-133.asy new file mode 100755 index 0000000..c8e6b64 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6905-133.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC6905-133 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6905-133.sub +SYMATTR Value2 LTC6905-133 +SYMATTR Description Fixed Frequency SOT-23 Oscillator +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName 0E +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC6905-80.asy b/spice/copy/sym/SpecialFunctions/LTC6905-80.asy new file mode 100755 index 0000000..ced0740 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6905-80.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC6905-80 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6905-80.sub +SYMATTR Value2 LTC6905-80 +SYMATTR Description Fixed Frequency SOT-23 Oscillator +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName 0E +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC6905-96.asy b/spice/copy/sym/SpecialFunctions/LTC6905-96.asy new file mode 100755 index 0000000..64b4014 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6905-96.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC6905-96 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6905-96.sub +SYMATTR Value2 LTC6905-96 +SYMATTR Description Fixed Frequency SOT-23 Oscillator +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName 0E +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC6905.asy b/spice/copy/sym/SpecialFunctions/LTC6905.asy new file mode 100755 index 0000000..994f98a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6905.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC6905 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6905.sub +SYMATTR Value2 LTC6905 +SYMATTR Description 17MHz to 170MHz Resistor Set SOT-23 Oscillator +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/LTC6906.asy b/spice/copy/sym/SpecialFunctions/LTC6906.asy new file mode 100755 index 0000000..1b26f4e --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6906.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC6906 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6906.sub +SYMATTR Value2 LTC6906 +SYMATTR Description µPower, 10kHz to 1MHz Resistor Set Oscillator in SOT-23 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName SET +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName GRD +PINATTR SpiceOrder 5 +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6907.asy b/spice/copy/sym/SpecialFunctions/LTC6907.asy new file mode 100755 index 0000000..067667b --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6907.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 49 Center 2 +SYMATTR Value LTC6907 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6907.sub +SYMATTR Value2 LTC6907 +SYMATTR Description µPower, 40kHz to 4MHz Resistor Set Oscillator in SOT-23 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName SET +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName GRD +PINATTR SpiceOrder 5 +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6908-1.asy b/spice/copy/sym/SpecialFunctions/LTC6908-1.asy new file mode 100755 index 0000000..cba3e31 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6908-1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6908-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6908-1.sub +SYMATTR Value2 LTC6908-1 +SYMATTR Description Resistor Set SOT-23 Oscillator with Spread Spectrum Modulation +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName MOD +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6908-2.asy b/spice/copy/sym/SpecialFunctions/LTC6908-2.asy new file mode 100755 index 0000000..9949d50 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6908-2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6908-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6908-2.sub +SYMATTR Value2 LTC6908-2 +SYMATTR Description Resistor Set SOT-23 Oscillator with Spread Spectrum Modulation +PIN -112 -80 LEFT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName MOD +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6909.asy b/spice/copy/sym/SpecialFunctions/LTC6909.asy new file mode 100755 index 0000000..411eb29 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6909.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -128 -256 128 256 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -128 Center 2 +WINDOW 3 0 128 Center 2 +SYMATTR Value LTC6909 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6909.sub +SYMATTR Value2 LTC6909 +SYMATTR Description 1 to 8 Output, Multiphase Silicon Oscillator with Spread Spectrum Modulation +PIN -128 -224 LEFT 8 +PINATTR PinName V+D +PINATTR SpiceOrder 13 +PIN -128 -160 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -128 160 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 16 +PIN -128 224 LEFT 8 +PINATTR PinName MOD +PINATTR SpiceOrder 14 +PIN 128 -160 RIGHT 8 +PINATTR PinName OUT2 +PINATTR SpiceOrder 6 +PIN 128 -224 RIGHT 8 +PINATTR PinName OUT1 +PINATTR SpiceOrder 5 +PIN 128 -96 RIGHT 8 +PINATTR PinName OUT3 +PINATTR SpiceOrder 7 +PIN 128 -32 RIGHT 8 +PINATTR PinName OUT4 +PINATTR SpiceOrder 8 +PIN 128 32 RIGHT 8 +PINATTR PinName OUT5 +PINATTR SpiceOrder 9 +PIN 128 96 RIGHT 8 +PINATTR PinName OUT6 +PINATTR SpiceOrder 10 +PIN 128 160 RIGHT 8 +PINATTR PinName OUT7 +PINATTR SpiceOrder 11 +PIN 128 224 RIGHT 8 +PINATTR PinName OUT8 +PINATTR SpiceOrder 12 +PIN -128 -32 LEFT 8 +PINATTR PinName PH0 +PINATTR SpiceOrder 3 +PIN -128 32 LEFT 8 +PINATTR PinName PH1 +PINATTR SpiceOrder 4 +PIN -128 96 LEFT 8 +PINATTR PinName PH2 +PINATTR SpiceOrder 15 +PIN -128 -96 LEFT 8 +PINATTR PinName V+A +PINATTR SpiceOrder 1 diff --git a/spice/copy/sym/SpecialFunctions/LTC691.asy b/spice/copy/sym/SpecialFunctions/LTC691.asy new file mode 100755 index 0000000..3981163 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC691.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 300 -224 -320 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -88 Center 2 +WINDOW 3 0 73 Center 2 +SYMATTR Value LTC691 +SYMATTR Prefix X +SYMATTR SpiceModel LTC691.sub +SYMATTR Value2 LTC691 +SYMATTR Description Microprocessor Supervisory Circuit +PIN -224 -288 LEFT 8 +PINATTR PinName Vbatt +PINATTR SpiceOrder 1 +PIN -224 -208 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -224 -128 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -224 -48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -224 32 LEFT 8 +PINATTR PinName Batt_On +PINATTR SpiceOrder 5 +PIN -224 112 LEFT 8 +PINATTR PinName _Low_Line +PINATTR SpiceOrder 6 +PIN -224 192 LEFT 8 +PINATTR PinName Osc In +PINATTR SpiceOrder 7 +PIN -224 272 LEFT 8 +PINATTR PinName Osc Sel +PINATTR SpiceOrder 8 +PIN 224 272 RIGHT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 9 +PIN 224 192 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 10 +PIN 224 112 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 11 +PIN 224 32 RIGHT 8 +PINATTR PinName _CE Out +PINATTR SpiceOrder 12 +PIN 224 -48 RIGHT 8 +PINATTR PinName _CE In +PINATTR SpiceOrder 13 +PIN 224 -128 RIGHT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 14 +PIN 224 -208 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 15 +PIN 224 -288 RIGHT 8 +PINATTR PinName Reset +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC692.asy b/spice/copy/sym/SpecialFunctions/LTC692.asy new file mode 100755 index 0000000..fd30721 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC692.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 160 -176 -192 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC692 +SYMATTR Prefix X +SYMATTR SpiceModel LTC692.sub +SYMATTR Value2 LTC692 +SYMATTR Description Microprocessor Supervisory Circuit +PIN -176 -160 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -176 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -176 128 LEFT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 4 +PIN 176 128 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 176 32 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 6 +PIN 176 -64 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 7 +PIN 176 -160 RIGHT 8 +PINATTR PinName Vbatt +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC693.asy b/spice/copy/sym/SpecialFunctions/LTC693.asy new file mode 100755 index 0000000..113a114 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC693.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 300 -224 -320 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 73 Center 2 +SYMATTR Value LTC693 +SYMATTR Prefix X +SYMATTR SpiceModel LTC693.sub +SYMATTR Value2 LTC693 +SYMATTR Description Microprocessor Supervisory Circuit +PIN -224 -288 LEFT 8 +PINATTR PinName Vbatt +PINATTR SpiceOrder 1 +PIN -224 -208 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -224 -128 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -224 -48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -224 32 LEFT 8 +PINATTR PinName Batt_On +PINATTR SpiceOrder 5 +PIN -224 112 LEFT 8 +PINATTR PinName _Low_Line +PINATTR SpiceOrder 6 +PIN -224 192 LEFT 8 +PINATTR PinName Osc In +PINATTR SpiceOrder 7 +PIN -224 272 LEFT 8 +PINATTR PinName Osc Sel +PINATTR SpiceOrder 8 +PIN 224 272 RIGHT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 9 +PIN 224 192 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 10 +PIN 224 112 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 11 +PIN 224 32 RIGHT 8 +PINATTR PinName _CE Out +PINATTR SpiceOrder 12 +PIN 224 -48 RIGHT 8 +PINATTR PinName _CE In +PINATTR SpiceOrder 13 +PIN 224 -128 RIGHT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 14 +PIN 224 -208 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 15 +PIN 224 -288 RIGHT 8 +PINATTR PinName Reset +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC694-3.3.asy b/spice/copy/sym/SpecialFunctions/LTC694-3.3.asy new file mode 100755 index 0000000..ed3d334 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC694-3.3.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 160 -176 -192 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC694-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC694-3.3.sub +SYMATTR Value2 LTC694-3.3 +SYMATTR Description 3.3V Microprocessor Supervisory Circuit +PIN -176 -160 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -176 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -176 128 LEFT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 4 +PIN 176 128 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 176 32 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 6 +PIN 176 -64 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 7 +PIN 176 -160 RIGHT 8 +PINATTR PinName Vbatt +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC694.asy b/spice/copy/sym/SpecialFunctions/LTC694.asy new file mode 100755 index 0000000..3fde9b5 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC694.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 160 -176 -192 +TEXT 0 -16 Center 2 LT +WINDOW 0 0 -112 Center 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value LTC694 +SYMATTR Prefix X +SYMATTR SpiceModel LTC694.sub +SYMATTR Value2 LTC694 +SYMATTR Description Microprocessor Supervisory Circuit +PIN -176 -160 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -176 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -176 128 LEFT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 4 +PIN 176 128 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 5 +PIN 176 32 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 6 +PIN 176 -64 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 7 +PIN 176 -160 RIGHT 8 +PINATTR PinName Vbatt +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC695-3.3.asy b/spice/copy/sym/SpecialFunctions/LTC695-3.3.asy new file mode 100755 index 0000000..68b26ef --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC695-3.3.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 300 -224 -320 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 73 Center 2 +SYMATTR Value LTC695-3.3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC695-3.3.sub +SYMATTR Value2 LTC695-3.3 +SYMATTR Description 3.3V Microprocessor Supervisory Circuit +PIN -224 -288 LEFT 8 +PINATTR PinName Vbatt +PINATTR SpiceOrder 1 +PIN -224 -208 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -224 -128 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -224 -48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -224 32 LEFT 8 +PINATTR PinName Batt_On +PINATTR SpiceOrder 5 +PIN -224 112 LEFT 8 +PINATTR PinName _Low_Line +PINATTR SpiceOrder 6 +PIN -224 192 LEFT 8 +PINATTR PinName Osc In +PINATTR SpiceOrder 7 +PIN -224 272 LEFT 8 +PINATTR PinName Osc Sel +PINATTR SpiceOrder 8 +PIN 224 272 RIGHT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 9 +PIN 224 192 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 10 +PIN 224 112 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 11 +PIN 224 32 RIGHT 8 +PINATTR PinName _CE Out +PINATTR SpiceOrder 12 +PIN 224 -48 RIGHT 8 +PINATTR PinName _CE In +PINATTR SpiceOrder 13 +PIN 224 -128 RIGHT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 14 +PIN 224 -208 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 15 +PIN 224 -288 RIGHT 8 +PINATTR PinName Reset +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC695.asy b/spice/copy/sym/SpecialFunctions/LTC695.asy new file mode 100755 index 0000000..6022526 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC695.asy @@ -0,0 +1,59 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 224 300 -224 -320 +TEXT 0 -8 Center 2 LT +WINDOW 0 0 -87 Center 2 +WINDOW 3 0 74 Center 2 +SYMATTR Value LTC695 +SYMATTR Prefix X +SYMATTR SpiceModel LTC695.sub +SYMATTR Value2 LTC695 +SYMATTR Description Microprocessor Supervisory Circuit +PIN -224 -288 LEFT 8 +PINATTR PinName Vbatt +PINATTR SpiceOrder 1 +PIN -224 -208 LEFT 8 +PINATTR PinName Vout +PINATTR SpiceOrder 2 +PIN -224 -128 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 3 +PIN -224 -48 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN -224 32 LEFT 8 +PINATTR PinName Batt_On +PINATTR SpiceOrder 5 +PIN -224 112 LEFT 8 +PINATTR PinName _Low_Line +PINATTR SpiceOrder 6 +PIN -224 192 LEFT 8 +PINATTR PinName Osc In +PINATTR SpiceOrder 7 +PIN -224 272 LEFT 8 +PINATTR PinName Osc Sel +PINATTR SpiceOrder 8 +PIN 224 272 RIGHT 8 +PINATTR PinName PFI +PINATTR SpiceOrder 9 +PIN 224 192 RIGHT 8 +PINATTR PinName _PFO +PINATTR SpiceOrder 10 +PIN 224 112 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 11 +PIN 224 32 RIGHT 8 +PINATTR PinName _CE Out +PINATTR SpiceOrder 12 +PIN 224 -48 RIGHT 8 +PINATTR PinName _CE In +PINATTR SpiceOrder 13 +PIN 224 -128 RIGHT 8 +PINATTR PinName _WDO +PINATTR SpiceOrder 14 +PIN 224 -208 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 15 +PIN 224 -288 RIGHT 8 +PINATTR PinName Reset +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/SpecialFunctions/LTC699.asy b/spice/copy/sym/SpecialFunctions/LTC699.asy new file mode 100755 index 0000000..a977bbe --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC699.asy @@ -0,0 +1,35 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal 176 160 -176 -192 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 53 Center 2 +SYMATTR Value LTC699 +SYMATTR Prefix X +SYMATTR SpiceModel LTC699.sub +SYMATTR Value2 LTC699 +SYMATTR Description Microprocessor Supervisory Circuit +PIN -176 -160 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 1 +PIN -176 -64 LEFT 8 +PINATTR PinName Vcc +PINATTR SpiceOrder 2 +PIN -176 32 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -176 128 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 176 128 RIGHT 8 +PINATTR PinName NC +PINATTR SpiceOrder 5 +PIN 176 32 RIGHT 8 +PINATTR PinName WDI +PINATTR SpiceOrder 6 +PIN 176 -64 RIGHT 8 +PINATTR PinName _Reset +PINATTR SpiceOrder 7 +PIN 176 -160 RIGHT 8 +PINATTR PinName GND +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/LTC6990.asy b/spice/copy/sym/SpecialFunctions/LTC6990.asy new file mode 100755 index 0000000..72cdf19 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6990.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6990 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6990.sub +SYMATTR Value2 LTC6990 +SYMATTR Description TimerBlox SOT-23 VCO +PIN -112 -80 LEFT 8 +PINATTR PinName OE +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6991.asy b/spice/copy/sym/SpecialFunctions/LTC6991.asy new file mode 100755 index 0000000..8db36cd --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6991.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6991 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6991.sub +SYMATTR Value2 LTC6991 +SYMATTR Description TimerBlox Low Freq Clock +PIN -112 -80 LEFT 8 +PINATTR PinName RST +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6992-1.asy b/spice/copy/sym/SpecialFunctions/LTC6992-1.asy new file mode 100755 index 0000000..186a72d --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6992-1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6992-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6992-1.sub +SYMATTR Value2 LTC6992-1 +SYMATTR Description TimerBlox 0% to 100% DC PWM +PIN -112 -80 LEFT 8 +PINATTR PinName MOD +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6992-2.asy b/spice/copy/sym/SpecialFunctions/LTC6992-2.asy new file mode 100755 index 0000000..e72c81b --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6992-2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6992-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6992-2.sub +SYMATTR Value2 LTC6992-2 +SYMATTR Description TimerBlox 5% TO 95% PWM +PIN -112 -80 LEFT 8 +PINATTR PinName MOD +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6992-3.asy b/spice/copy/sym/SpecialFunctions/LTC6992-3.asy new file mode 100755 index 0000000..5af97ca --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6992-3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6992-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6992-3.sub +SYMATTR Value2 LTC6992-3 +SYMATTR Description TimerBlox 0% TO 95% PWM +PIN -112 -80 LEFT 8 +PINATTR PinName MOD +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6992-4.asy b/spice/copy/sym/SpecialFunctions/LTC6992-4.asy new file mode 100755 index 0000000..40f735a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6992-4.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6992-4 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6992-4.sub +SYMATTR Value2 LTC6992-4 +SYMATTR Description TimerBlox 5% TO 100% PWM +PIN -112 -80 LEFT 8 +PINATTR PinName MOD +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6993-1.asy b/spice/copy/sym/SpecialFunctions/LTC6993-1.asy new file mode 100755 index 0000000..bf015c8 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6993-1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6993-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6993-1.sub +SYMATTR Value2 LTC6993-1 +SYMATTR Description TimerBlox Non-Retriggerable One Shot +PIN -112 -80 LEFT 8 +PINATTR PinName TRIG +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6993-2.asy b/spice/copy/sym/SpecialFunctions/LTC6993-2.asy new file mode 100755 index 0000000..82e8144 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6993-2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6993-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6993-2.sub +SYMATTR Value2 LTC6993-2 +SYMATTR Description TimerBlox Retriggerable One Shot +PIN -112 -80 LEFT 8 +PINATTR PinName TRIG +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6993-3.asy b/spice/copy/sym/SpecialFunctions/LTC6993-3.asy new file mode 100755 index 0000000..bcedbf8 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6993-3.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6993-3 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6993-3.sub +SYMATTR Value2 LTC6993-3 +SYMATTR Description TimerBlox Non-Retrig Fall Edge One Shot +PIN -112 -80 LEFT 8 +PINATTR PinName TRIG +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6993-4.asy b/spice/copy/sym/SpecialFunctions/LTC6993-4.asy new file mode 100755 index 0000000..7b07e15 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6993-4.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6993-4 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6993-4.sub +SYMATTR Value2 LTC6993-4 +SYMATTR Description TimerBlox Retriggerable One Shot +PIN -112 -80 LEFT 8 +PINATTR PinName TRIG +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6994-1.asy b/spice/copy/sym/SpecialFunctions/LTC6994-1.asy new file mode 100755 index 0000000..0592289 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6994-1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6994-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6994-1.sub +SYMATTR Value2 LTC6994-1 +SYMATTR Description TimerBlox Retriggerable One Edge Delay +PIN -112 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6994-2.asy b/spice/copy/sym/SpecialFunctions/LTC6994-2.asy new file mode 100755 index 0000000..fc7ac46 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6994-2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6994-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6994-2.sub +SYMATTR Value2 LTC6994-2 +SYMATTR Description TimerBlox Retriggerable Either Edge Delay +PIN -112 -80 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6995-1.asy b/spice/copy/sym/SpecialFunctions/LTC6995-1.asy new file mode 100755 index 0000000..dece6a9 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6995-1.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6995-1 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6995-1.sub +SYMATTR Value2 LTC6995-1 +SYMATTR Description Long Time POR_Watchdog Timer +PIN -112 -80 LEFT 8 +PINATTR PinName RST +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/LTC6995-2.asy b/spice/copy/sym/SpecialFunctions/LTC6995-2.asy new file mode 100755 index 0000000..54e2bfc --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/LTC6995-2.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +RECTANGLE Normal -112 -112 112 112 +TEXT 0 0 Center 2 LT +WINDOW 0 0 -48 Center 2 +WINDOW 3 0 48 Center 2 +SYMATTR Value LTC6995-2 +SYMATTR Prefix X +SYMATTR SpiceModel LTC6995-2.sub +SYMATTR Value2 LTC6995-2 +SYMATTR Description Long Time POR_Watchdog Timer +PIN -112 -80 LEFT 8 +PINATTR PinName RST/ +PINATTR SpiceOrder 1 +PIN -112 0 LEFT 8 +PINATTR PinName GND +PINATTR SpiceOrder 2 +PIN -112 80 LEFT 8 +PINATTR PinName SET +PINATTR SpiceOrder 3 +PIN 112 80 RIGHT 8 +PINATTR PinName DIV +PINATTR SpiceOrder 4 +PIN 112 0 RIGHT 8 +PINATTR PinName V+ +PINATTR SpiceOrder 5 +PIN 112 -80 RIGHT 8 +PINATTR PinName OUT +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/SpecialFunctions/capmeter.asy b/spice/copy/sym/SpecialFunctions/capmeter.asy new file mode 100755 index 0000000..e4dcc0a --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/capmeter.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType CELL +LINE Normal -80 -64 288 -64 +LINE Normal -80 -64 -80 128 +LINE Normal -80 128 288 128 +LINE Normal 288 128 288 -64 +WINDOW 0 -64 -80 Left 2 +WINDOW 3 -64 152 Left 2 +SYMATTR Value capometer +SYMATTR Prefix X +SYMATTR SpiceLine current=1m freq=3Meg C=.5µ Q=.25 +SYMATTR Description A vector impedance meter. You must .lib capometer.sub +PIN -80 32 LEFT 8 +PINATTR PinName DUT+ +PINATTR SpiceOrder 1 +PIN -80 96 LEFT 8 +PINATTR PinName DUT- +PINATTR SpiceOrder 2 +PIN -80 -32 LEFT 8 +PINATTR PinName bias +PINATTR SpiceOrder 3 +PIN 288 0 RIGHT 8 +PINATTR PinName Resistance +PINATTR SpiceOrder 4 +PIN 288 64 RIGHT 8 +PINATTR PinName Capacitance +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/modulate.asy b/spice/copy/sym/SpecialFunctions/modulate.asy new file mode 100755 index 0000000..59e18f8 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/modulate.asy @@ -0,0 +1,24 @@ +Version 4 +SymbolType CELL +LINE Normal 0 -32 112 -32 +LINE Normal 0 -32 0 96 +LINE Normal 0 96 112 96 +LINE Normal 112 96 144 32 +LINE Normal 144 32 112 -32 +WINDOW 0 16 -48 Left 2 +WINDOW 3 16 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel MODULATOR +SYMATTR Description Behavioral VCO and Modulator. Output is a sine wave modulated by AM and FM input voltages. +PIN 0 0 LEFT 8 +PINATTR PinName FM +PINATTR SpiceOrder 1 +PIN 0 64 LEFT 8 +PINATTR PinName AM +PINATTR SpiceOrder 2 +PIN 144 32 RIGHT 8 +PINATTR PinName Q +PINATTR SpiceOrder 7 +PIN 0 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/modulate2.asy b/spice/copy/sym/SpecialFunctions/modulate2.asy new file mode 100755 index 0000000..e32b9c6 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/modulate2.asy @@ -0,0 +1,28 @@ +Version 4 +SymbolType CELL +LINE Normal 0 -32 112 -32 +LINE Normal 0 -32 0 96 +LINE Normal 0 96 112 96 +LINE Normal 112 96 144 64 +LINE Normal 144 0 112 -32 +LINE Normal 144 64 144 0 +WINDOW 0 16 -48 Left 2 +WINDOW 3 16 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel MODULATOR +SYMATTR Description Behavioral VCO and Modulator. Output is a sine wave modulated by AM and FM input voltages. This version supplies an output in quadrature. +PIN 0 0 LEFT 8 +PINATTR PinName FM +PINATTR SpiceOrder 1 +PIN 0 64 LEFT 8 +PINATTR PinName AM +PINATTR SpiceOrder 2 +PIN 144 64 RIGHT 8 +PINATTR PinName COS +PINATTR SpiceOrder 6 +PIN 144 0 RIGHT 10 +PINATTR PinName SIN +PINATTR SpiceOrder 7 +PIN 0 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/mota.asy b/spice/copy/sym/SpecialFunctions/mota.asy new file mode 100755 index 0000000..ad4c02b --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/mota.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 12 56 +LINE Normal -32 96 12 72 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 32 88 32 96 +LINE Normal 32 88 28 84 +LINE Normal 28 72 28 84 +CIRCLE Normal 32 76 8 52 +CIRCLE Normal 48 76 24 52 +WINDOW 0 0 32 Left 2 +WINDOW 3 40 104 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel OTA +SYMATTR Description Behavioral Operational Transconductance Amplifier with multiplying input +PIN -32 48 NONE 0 +PINATTR PinName invin +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName noninvin +PINATTR SpiceOrder 2 +PIN 32 96 NONE 0 +PINATTR PinName mult +PINATTR SpiceOrder 3 +PIN 48 64 NONE 0 +PINATTR PinName out +PINATTR SpiceOrder 7 +PIN -32 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/mota2.asy b/spice/copy/sym/SpecialFunctions/mota2.asy new file mode 100755 index 0000000..6099edf --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/mota2.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 12 56 +LINE Normal -32 96 12 72 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 44 -24 52 +LINE Normal 32 88 32 96 +LINE Normal 32 88 28 84 +LINE Normal 28 72 28 84 +CIRCLE Normal 32 76 8 52 +CIRCLE Normal 48 76 24 52 +WINDOW 0 0 32 Left 2 +WINDOW 3 40 104 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel OTA +SYMATTR Description Behavioral Operational Transconductance Amplifier with multiplying input +PIN -32 80 NONE 0 +PINATTR PinName invin +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName noninvin +PINATTR SpiceOrder 2 +PIN 32 96 NONE 0 +PINATTR PinName mult +PINATTR SpiceOrder 3 +PIN 48 64 NONE 0 +PINATTR PinName out +PINATTR SpiceOrder 7 +PIN -32 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/mota3.asy b/spice/copy/sym/SpecialFunctions/mota3.asy new file mode 100755 index 0000000..7c296ca --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/mota3.asy @@ -0,0 +1,40 @@ +Version 4 +SymbolType CELL +LINE Normal -32 16 8 56 +LINE Normal -32 112 8 72 +LINE Normal -32 16 -32 112 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 24 72 0 112 +LINE Normal 24 72 48 112 +LINE Normal 0 112 48 112 +LINE Normal 44 64 48 64 +LINE Normal 8 104 16 104 +LINE Normal 32 104 40 104 +LINE Normal 36 100 36 108 +CIRCLE Normal 28 76 4 52 +CIRCLE Normal 44 76 20 52 +WINDOW 0 0 32 Left 2 +WINDOW 3 56 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel OTA +SYMATTR Description Behavioral Operational Transconductance Amplifier with differential multiplying input +PIN -32 48 NONE 0 +PINATTR PinName invin +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName noninvin +PINATTR SpiceOrder 2 +PIN 48 112 NONE 0 +PINATTR PinName mult+ +PINATTR SpiceOrder 3 +PIN 0 112 NONE 0 +PINATTR PinName mult- +PINATTR SpiceOrder 4 +PIN 48 64 NONE 0 +PINATTR PinName out +PINATTR SpiceOrder 7 +PIN -32 112 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/mota8.asy b/spice/copy/sym/SpecialFunctions/mota8.asy new file mode 100755 index 0000000..126ea0c --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/mota8.asy @@ -0,0 +1,51 @@ +Version 4 +SymbolType CELL +LINE Normal -32 16 8 56 +LINE Normal -32 112 8 72 +LINE Normal -32 16 -32 112 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +LINE Normal 24 72 0 112 +LINE Normal 24 72 48 112 +LINE Normal 0 112 48 112 +LINE Normal 44 64 48 64 +LINE Normal 8 104 16 104 +LINE Normal 32 104 40 104 +LINE Normal 36 100 36 108 +LINE Normal -28 96 -20 96 +LINE Normal -28 32 -20 32 +LINE Normal -24 36 -24 28 +LINE Normal -32 32 -48 16 +LINE Normal -48 112 -32 96 +CIRCLE Normal 28 76 4 52 +CIRCLE Normal 44 76 20 52 +WINDOW 0 0 32 Left 2 +WINDOW 3 56 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel OTA +SYMATTR Description Behavioral Operational Transconductance Amplifier with differential multiplying input +PIN -32 48 NONE 0 +PINATTR PinName invin +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName noninvin +PINATTR SpiceOrder 2 +PIN 48 112 NONE 0 +PINATTR PinName mult+ +PINATTR SpiceOrder 3 +PIN 0 112 NONE 0 +PINATTR PinName mult- +PINATTR SpiceOrder 4 +PIN -48 112 NONE 0 +PINATTR PinName -V +PINATTR SpiceOrder 5 +PIN -48 16 NONE 0 +PINATTR PinName +V +PINATTR SpiceOrder 6 +PIN 48 64 NONE 0 +PINATTR PinName out +PINATTR SpiceOrder 7 +PIN -32 112 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/odev.asy b/spice/copy/sym/SpecialFunctions/odev.asy new file mode 100755 index 0000000..da1badd --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/odev.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 12 -8 +LINE Normal -32 32 12 8 +LINE Normal -32 -32 -32 32 +LINE Normal -28 -16 -20 -16 +LINE Normal -28 16 -20 16 +LINE Normal -24 20 -24 12 +LINE Normal 0 -15 0 -32 +LINE Normal 0 15 0 32 +LINE Normal 4 -18 12 -18 +LINE Normal 8 -14 8 -22 +LINE Normal 4 18 12 18 +CIRCLE Normal 32 12 8 -12 +CIRCLE Normal 48 12 24 -12 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Prefix Ö +SYMATTR Description Transconductance Device\n\nParameters:\n Gm1=<1st order transconductance>\n Gm2=<2nd order transconductance>\n Ibias= +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 -32 NONE 0 +PINATTR PinName +V +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName -V +PINATTR SpiceOrder 3 +PIN -32 -16 NONE 0 +PINATTR PinName -IN +PINATTR SpiceOrder 4 +PIN -32 16 NONE 0 +PINATTR PinName +IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/odev2.asy b/spice/copy/sym/SpecialFunctions/odev2.asy new file mode 100755 index 0000000..d1f1785 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/odev2.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType CELL +LINE Normal -32 -32 12 -8 +LINE Normal -32 32 12 8 +LINE Normal -32 -32 -32 32 +LINE Normal -28 16 -20 16 +LINE Normal -28 -16 -20 -16 +LINE Normal -24 -20 -24 -12 +LINE Normal 0 -15 0 -32 +LINE Normal 0 15 0 32 +LINE Normal 4 -18 12 -18 +LINE Normal 8 -14 8 -22 +LINE Normal 4 18 12 18 +CIRCLE Normal 32 12 8 -12 +CIRCLE Normal 48 12 24 -12 +WINDOW 0 16 -32 Left 2 +WINDOW 3 16 32 Left 2 +SYMATTR Prefix Ö +SYMATTR Description Transconductance Device\n\nParameters:\n Gm1=<1st order transconductance>\n Gm2=<2nd order transconductance>\n Ibias= +PIN 48 0 NONE 0 +PINATTR PinName OUT +PINATTR SpiceOrder 1 +PIN 0 -32 NONE 0 +PINATTR PinName +V +PINATTR SpiceOrder 2 +PIN 0 32 NONE 0 +PINATTR PinName -V +PINATTR SpiceOrder 3 +PIN -32 16 NONE 0 +PINATTR PinName -IN +PINATTR SpiceOrder 4 +PIN -32 -16 NONE 0 +PINATTR PinName +IN +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/SpecialFunctions/ota.asy b/spice/copy/sym/SpecialFunctions/ota.asy new file mode 100755 index 0000000..0322e4d --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/ota.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 12 56 +LINE Normal -32 96 12 72 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 84 -24 76 +CIRCLE Normal 32 76 8 52 +CIRCLE Normal 48 76 24 52 +WINDOW 0 0 32 Left 2 +WINDOW 3 0 104 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel OTA +SYMATTR Description Behavioral Operational Transconductance Amplifier +PIN -32 48 NONE 0 +PINATTR PinName invin +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName noninvin +PINATTR SpiceOrder 2 +PIN 48 64 NONE 0 +PINATTR PinName out +PINATTR SpiceOrder 7 +PIN -32 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/ota2.asy b/spice/copy/sym/SpecialFunctions/ota2.asy new file mode 100755 index 0000000..45cf4c0 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/ota2.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType CELL +LINE Normal -32 32 12 56 +LINE Normal -32 96 12 72 +LINE Normal -32 32 -32 96 +LINE Normal -28 48 -20 48 +LINE Normal -28 80 -20 80 +LINE Normal -24 44 -24 52 +CIRCLE Normal 32 76 8 52 +CIRCLE Normal 48 76 24 52 +WINDOW 0 0 32 Left 2 +WINDOW 3 0 104 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel OTA +SYMATTR Description Behavioral Operational Transconductance Amplifier +PIN -32 80 NONE 0 +PINATTR PinName invin +PINATTR SpiceOrder 1 +PIN -32 48 NONE 0 +PINATTR PinName noninvin +PINATTR SpiceOrder 2 +PIN 48 64 NONE 0 +PINATTR PinName out +PINATTR SpiceOrder 7 +PIN -32 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/sample.asy b/spice/copy/sym/SpecialFunctions/sample.asy new file mode 100755 index 0000000..e55c00c --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/sample.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal -80 -64 80 -64 +LINE Normal -80 -64 -80 96 +LINE Normal -80 96 80 96 +LINE Normal 80 96 96 16 +LINE Normal 96 16 80 -64 +LINE Normal -80 40 -72 32 +LINE Normal -80 24 -72 32 +WINDOW 0 -64 -80 Left 2 +WINDOW 3 -64 120 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel SAMPLEHOLD +SYMATTR Description Behavioral Sample and Hold function block +PIN -80 -32 LEFT 8 +PINATTR PinName in+ +PINATTR SpiceOrder 1 +PIN -80 0 LEFT 8 +PINATTR PinName in- +PINATTR SpiceOrder 2 +PIN -80 32 LEFT 8 +PINATTR PinName CLK +PINATTR SpiceOrder 3 +PIN -80 64 LEFT 8 +PINATTR PinName S/H +PINATTR SpiceOrder 4 +PIN 96 16 RIGHT 8 +PINATTR PinName out +PINATTR SpiceOrder 7 +PIN -80 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/SpecialFunctions/varistor.asy b/spice/copy/sym/SpecialFunctions/varistor.asy new file mode 100755 index 0000000..ca38654 --- /dev/null +++ b/spice/copy/sym/SpecialFunctions/varistor.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal -16 96 -16 88 +LINE Normal -16 32 -16 40 +LINE Normal -4 96 -4 92 +LINE Normal -28 36 -28 32 +LINE Normal -4 92 -28 36 +LINE Normal -32 80 -24 80 +LINE Normal -32 48 -24 48 +LINE Normal -24 88 -8 88 +LINE Normal -8 40 -8 88 +LINE Normal -8 40 -24 40 +LINE Normal -24 88 -24 40 +LINE Normal -20 80 -12 80 +LINE Normal -16 76 -16 84 +WINDOW 0 0 32 Left 2 +WINDOW 3 0 104 Left 2 +SYMATTR Prefix A +SYMATTR SpiceModel VARISTOR +SYMATTR Description Voltage controlled varistor +PIN -32 48 NONE 0 +PINATTR PinName invin +PINATTR SpiceOrder 1 +PIN -32 80 NONE 0 +PINATTR PinName noninvin +PINATTR SpiceOrder 2 +PIN -16 32 NONE 0 +PINATTR PinName out +PINATTR SpiceOrder 7 +PIN -16 96 NONE 0 +PINATTR PinName com +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG1201.asy b/spice/copy/sym/Switches/ADG1201.asy new file mode 100755 index 0000000..02e0e90 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1201.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG1201 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1201.sub +SYMATTR Value2 ADG1201 +SYMATTR Description Low Capacitance, Low Charge Injection, ±15 V/+12 V, iCMOS, SPST in SOT-23 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1208.asy b/spice/copy/sym/Switches/ADG1208.asy new file mode 100755 index 0000000..fd7b441 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1208.asy @@ -0,0 +1,131 @@ +Version 4 +SymbolType CELL +LINE Normal 21 192 64 192 +LINE Normal -128 192 -53 192 +LINE Normal 12 171 -44 190 +LINE Normal 21 128 64 128 +LINE Normal -128 128 -53 128 +LINE Normal 12 107 -44 126 +LINE Normal 21 64 64 64 +LINE Normal -128 64 -53 64 +LINE Normal 12 43 -44 62 +LINE Normal 21 0 64 0 +LINE Normal -128 0 -53 0 +LINE Normal 12 -21 -44 -2 +LINE Normal 21 -64 64 -64 +LINE Normal -128 -64 -53 -64 +LINE Normal 12 -85 -44 -66 +LINE Normal 21 -128 64 -128 +LINE Normal -128 -128 -53 -128 +LINE Normal 12 -149 -44 -130 +LINE Normal 21 -192 64 -192 +LINE Normal -128 -192 -53 -192 +LINE Normal 12 -213 -44 -194 +LINE Normal 21 -256 64 -256 +LINE Normal -128 -256 -53 -256 +LINE Normal 12 -277 -44 -258 +LINE Normal 64 -256 64 192 +LINE Normal 64 -32 128 -32 +RECTANGLE Normal -128 -320 128 432 +CIRCLE Normal 11 197 21 187 +CIRCLE Normal -53 197 -43 187 +CIRCLE Normal 11 133 21 123 +CIRCLE Normal -53 133 -43 123 +CIRCLE Normal 11 69 21 59 +CIRCLE Normal -53 69 -43 59 +CIRCLE Normal 11 5 21 -5 +CIRCLE Normal -53 5 -43 -5 +CIRCLE Normal 11 -59 21 -69 +CIRCLE Normal -53 -59 -43 -69 +CIRCLE Normal 11 -123 21 -133 +CIRCLE Normal -53 -123 -43 -133 +CIRCLE Normal 11 -187 21 -197 +CIRCLE Normal -53 -187 -43 -197 +CIRCLE Normal 11 -251 21 -261 +CIRCLE Normal -53 -251 -43 -261 +CIRCLE Normal 65 129 63 127 +CIRCLE Normal 66 130 62 126 +CIRCLE Normal 67 131 61 125 +CIRCLE Normal 65 -191 63 -193 +CIRCLE Normal 66 -190 62 -194 +CIRCLE Normal 67 -189 61 -195 +CIRCLE Normal 65 -127 63 -129 +CIRCLE Normal 66 -126 62 -130 +CIRCLE Normal 67 -125 61 -131 +CIRCLE Normal 65 -63 63 -65 +CIRCLE Normal 66 -62 62 -66 +CIRCLE Normal 67 -61 61 -67 +CIRCLE Normal 65 -31 63 -33 +CIRCLE Normal 66 -30 62 -34 +CIRCLE Normal 67 -29 61 -35 +CIRCLE Normal 65 1 63 -1 +CIRCLE Normal 66 2 62 -2 +CIRCLE Normal 67 3 61 -3 +CIRCLE Normal 65 65 63 63 +CIRCLE Normal 66 66 62 62 +CIRCLE Normal 67 67 61 61 +TEXT 0 288 Center 2 ADI +TEXT -102 -256 Bottom 2 S1 +TEXT -102 -192 Bottom 2 S2 +TEXT -102 -128 Bottom 2 S3 +TEXT -102 -64 Bottom 2 S4 +TEXT -102 0 Bottom 2 S5 +TEXT -102 64 Bottom 2 S6 +TEXT -102 128 Bottom 2 S7 +TEXT -102 192 Bottom 2 S8 +TEXT 102 -32 Bottom 2 D +WINDOW 0 64 -320 Bottom 2 +WINDOW 3 0 352 Center 2 +SYMATTR Value ADG1208 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1208.sub +SYMATTR Value2 ADG1208 +SYMATTR Description Low Capacitance, 8-Channel, ±15V/+12V iCMOS Multiplexer +PIN -128 256 LEFT 8 +PINATTR PinName A0 +PINATTR SpiceOrder 1 +PIN 128 256 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN -64 432 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 3 +PIN -128 -256 NONE 8 +PINATTR PinName S1 +PINATTR SpiceOrder 4 +PIN -128 -192 NONE 8 +PINATTR PinName S2 +PINATTR SpiceOrder 5 +PIN -128 -128 NONE 8 +PINATTR PinName S3 +PINATTR SpiceOrder 6 +PIN -128 -64 NONE 8 +PINATTR PinName S4 +PINATTR SpiceOrder 7 +PIN 128 -32 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 8 +PIN -128 192 NONE 8 +PINATTR PinName S8 +PINATTR SpiceOrder 9 +PIN -128 128 NONE 8 +PINATTR PinName S7 +PINATTR SpiceOrder 10 +PIN -128 64 NONE 8 +PINATTR PinName S6 +PINATTR SpiceOrder 11 +PIN -128 0 NONE 8 +PINATTR PinName S5 +PINATTR SpiceOrder 12 +PIN 0 -320 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 13 +PIN 64 432 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN -128 384 LEFT 8 +PINATTR PinName A2 +PINATTR SpiceOrder 15 +PIN -128 320 LEFT 8 +PINATTR PinName A1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/Switches/ADG1209.asy b/spice/copy/sym/Switches/ADG1209.asy new file mode 100755 index 0000000..95437d4 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1209.asy @@ -0,0 +1,80 @@ +Version 4 +SymbolType CELL +LINE Normal 21 -64 64 -64 +LINE Normal -128 -64 -53 -64 +LINE Normal 12 -85 -44 -66 +LINE Normal 21 -128 64 -128 +LINE Normal -128 -128 -53 -128 +LINE Normal 12 -149 -44 -130 +LINE Normal 21 -192 64 -192 +LINE Normal -128 -192 -53 -192 +LINE Normal 12 -213 -44 -194 +LINE Normal 21 -256 64 -256 +LINE Normal -128 -256 -53 -256 +LINE Normal 12 -277 -44 -258 +LINE Normal 64 -256 64 -64 +LINE Normal 64 -160 128 -160 +RECTANGLE Normal -128 -320 128 112 +CIRCLE Normal 11 -59 21 -69 +CIRCLE Normal -53 -59 -43 -69 +CIRCLE Normal 11 -123 21 -133 +CIRCLE Normal -53 -123 -43 -133 +CIRCLE Normal 11 -187 21 -197 +CIRCLE Normal -53 -187 -43 -197 +CIRCLE Normal 11 -251 21 -261 +CIRCLE Normal -53 -251 -43 -261 +CIRCLE Normal 65 -191 63 -193 +CIRCLE Normal 66 -190 62 -194 +CIRCLE Normal 67 -189 61 -195 +CIRCLE Normal 65 -127 63 -129 +CIRCLE Normal 66 -126 62 -130 +CIRCLE Normal 67 -125 61 -131 +CIRCLE Normal 65 -159 63 -161 +CIRCLE Normal 66 -158 62 -162 +CIRCLE Normal 67 -157 61 -163 +TEXT 0 -32 Center 2 ADI +TEXT -102 -256 Bottom 2 S1 +TEXT -102 -192 Bottom 2 S2 +TEXT -102 -128 Bottom 2 S3 +TEXT -102 -64 Bottom 2 S4 +TEXT 102 -160 Bottom 2 D +WINDOW 0 64 -320 Bottom 2 +WINDOW 3 0 32 Center 2 +SYMATTR Value ADG1209 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1209.sub +SYMATTR Value2 ADG1209 +SYMATTR Description Low Capacitance, 8-Channel, ±15V/+12V iCMOS Multiplexer +PIN -128 0 LEFT 8 +PINATTR PinName A0 +PINATTR SpiceOrder 1 +PIN 128 0 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 2 +PIN -64 112 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 3 +PIN -128 -256 NONE 8 +PINATTR PinName S1 +PINATTR SpiceOrder 4 +PIN -128 -192 NONE 8 +PINATTR PinName S2 +PINATTR SpiceOrder 5 +PIN -128 -128 NONE 8 +PINATTR PinName S3 +PINATTR SpiceOrder 6 +PIN -128 -64 NONE 8 +PINATTR PinName S4 +PINATTR SpiceOrder 7 +PIN 128 -160 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 8 +PIN 0 -320 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 13 +PIN 64 112 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN -128 64 LEFT 8 +PINATTR PinName A1 +PINATTR SpiceOrder 16 diff --git a/spice/copy/sym/Switches/ADG1211.asy b/spice/copy/sym/Switches/ADG1211.asy new file mode 100755 index 0000000..ae81c89 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1211.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +LINE Normal 16 -51 -16 -51 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG1211 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1211.sub +SYMATTR Value2 ADG1211 +SYMATTR Description Low Capacitance, Low Charge Injection, ±15 V/+12 V iCMOS Quad SPST Switches +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1212.asy b/spice/copy/sym/Switches/ADG1212.asy new file mode 100755 index 0000000..752996f --- /dev/null +++ b/spice/copy/sym/Switches/ADG1212.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG1212 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1212.sub +SYMATTR Value2 ADG1212 +SYMATTR Description Low Capacitance, Low Charge Injection, ±15 V/+12 V iCMOS Quad SPST Switches +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1219.asy b/spice/copy/sym/Switches/ADG1219.asy new file mode 100755 index 0000000..f781dd9 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1219.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal -17 -75 27 -48 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -80 -80 Bottom 2 SA +TEXT -80 -16 Bottom 2 SB +TEXT 80 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG1219 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1219.sub +SYMATTR Value2 ADG1219 +SYMATTR Description Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS, Dual SPDT Switch +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 8 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 7 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 6 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 2 +PIN 96 48 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 1 diff --git a/spice/copy/sym/Switches/ADG1221.asy b/spice/copy/sym/Switches/ADG1221.asy new file mode 100755 index 0000000..ee3583a --- /dev/null +++ b/spice/copy/sym/Switches/ADG1221.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG1221 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1221.sub +SYMATTR Value2 ADG1221 +SYMATTR Description Low Capacitance, Low Charge Injection, ±15 V/+12 V iCMOS Dual SPST Switches\n\nAlso models 2 channels of the ADG1223 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1222.asy b/spice/copy/sym/Switches/ADG1222.asy new file mode 100755 index 0000000..f8afb50 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1222.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal -11 16 0 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +CIRCLE Normal -11 18 -16 13 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG1222 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1222.sub +SYMATTR Value2 ADG1222 +SYMATTR Description Low Capacitance, Low Charge Injection, ±15 V/+12 V iCMOS Dual SPST Switches\n\nAlso models 2 channels of the ADG1223 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1233.asy b/spice/copy/sym/Switches/ADG1233.asy new file mode 100755 index 0000000..2b99f91 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1233.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 32 -48 -16 -80 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +TEXT -79 112 Bottom 2 _EN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG1233 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1233.sub +SYMATTR Value2 ADG1233 +SYMATTR Description Low Capacitance, Triple/Quad SPDT, +/-15 V, +12 V, iCMOS Switches \n \n Only one channel is modelled +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -96 112 NONE 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG1236.asy b/spice/copy/sym/Switches/ADG1236.asy new file mode 100755 index 0000000..627cbe8 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1236.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 28 -48 -16 -21 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -80 -80 Bottom 2 SA +TEXT -80 -16 Bottom 2 SB +TEXT 80 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG1236 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1236.sub +SYMATTR Value2 ADG1236 +SYMATTR Description Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS, Dual SPDT Switch +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 5 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/Switches/ADG1311.asy b/spice/copy/sym/Switches/ADG1311.asy new file mode 100755 index 0000000..ff782fb --- /dev/null +++ b/spice/copy/sym/Switches/ADG1311.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal -11 16 0 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +CIRCLE Normal -11 18 -16 13 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG1311 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1311.sub +SYMATTR Value2 ADG1311 +SYMATTR Description ±15 V/+12 V Quad SPST Switches\n\nAlso models 2 channels of the ADG1313 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1312.asy b/spice/copy/sym/Switches/ADG1312.asy new file mode 100755 index 0000000..eee2675 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1312.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG1312 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1312.sub +SYMATTR Value2 ADG1312 +SYMATTR Description ±15 V/+12 V Quad SPST Switches\n\nAlso models 2 channels of the ADG1313 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1334.asy b/spice/copy/sym/Switches/ADG1334.asy new file mode 100755 index 0000000..afe1423 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1334.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 32 -48 -16 -80 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG1334 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1334.sub +SYMATTR Value2 ADG1334 +SYMATTR Description Quad SPDT, +/-15 V, +12 V Switches \n \n Only one channel is modelled +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 5 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/Switches/ADG1401.asy b/spice/copy/sym/Switches/ADG1401.asy new file mode 100755 index 0000000..5bada94 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1401.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +LINE Normal 12 -58 -16 -48 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 1 83 Center 2 +SYMATTR Value ADG1401 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1401.sub +SYMATTR Value2 ADG1401 +SYMATTR Description 1 Ohm On Resistance, +/-15 V/+12 V/+/-5 V iCMOS SPST Switches +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1402.asy b/spice/copy/sym/Switches/ADG1402.asy new file mode 100755 index 0000000..cc5c1be --- /dev/null +++ b/spice/copy/sym/Switches/ADG1402.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +LINE Normal -11 16 0 16 2 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal -11 18 -16 13 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 1 83 Center 2 +SYMATTR Value ADG1402 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1402.sub +SYMATTR Value2 ADG1402 +SYMATTR Description 1 Ohm On Resistance, ±15V, +12V, ±5 V iCMOS SPST Switches +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1408.asy b/spice/copy/sym/Switches/ADG1408.asy new file mode 100755 index 0000000..1f21f77 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1408.asy @@ -0,0 +1,131 @@ +Version 4 +SymbolType CELL +LINE Normal 21 192 64 192 +LINE Normal -128 192 -53 192 +LINE Normal 12 171 -44 190 +LINE Normal 21 128 64 128 +LINE Normal -128 128 -53 128 +LINE Normal 12 107 -44 126 +LINE Normal 21 64 64 64 +LINE Normal -128 64 -53 64 +LINE Normal 12 43 -44 62 +LINE Normal 21 0 64 0 +LINE Normal -128 0 -53 0 +LINE Normal 12 -21 -44 -2 +LINE Normal 21 -64 64 -64 +LINE Normal -128 -64 -53 -64 +LINE Normal 12 -85 -44 -66 +LINE Normal 21 -128 64 -128 +LINE Normal -128 -128 -53 -128 +LINE Normal 12 -149 -44 -130 +LINE Normal 21 -192 64 -192 +LINE Normal -128 -192 -53 -192 +LINE Normal 12 -213 -44 -194 +LINE Normal 21 -256 64 -256 +LINE Normal -128 -256 -53 -256 +LINE Normal 12 -277 -44 -258 +LINE Normal 64 -256 64 192 +LINE Normal 64 -32 128 -32 +RECTANGLE Normal -128 -320 128 432 +CIRCLE Normal 11 197 21 187 +CIRCLE Normal -53 197 -43 187 +CIRCLE Normal 11 133 21 123 +CIRCLE Normal -53 133 -43 123 +CIRCLE Normal 11 69 21 59 +CIRCLE Normal -53 69 -43 59 +CIRCLE Normal 11 5 21 -5 +CIRCLE Normal -53 5 -43 -5 +CIRCLE Normal 11 -59 21 -69 +CIRCLE Normal -53 -59 -43 -69 +CIRCLE Normal 11 -123 21 -133 +CIRCLE Normal -53 -123 -43 -133 +CIRCLE Normal 11 -187 21 -197 +CIRCLE Normal -53 -187 -43 -197 +CIRCLE Normal 11 -251 21 -261 +CIRCLE Normal -53 -251 -43 -261 +CIRCLE Normal 65 129 63 127 +CIRCLE Normal 66 130 62 126 +CIRCLE Normal 67 131 61 125 +CIRCLE Normal 65 -191 63 -193 +CIRCLE Normal 66 -190 62 -194 +CIRCLE Normal 67 -189 61 -195 +CIRCLE Normal 65 -127 63 -129 +CIRCLE Normal 66 -126 62 -130 +CIRCLE Normal 67 -125 61 -131 +CIRCLE Normal 65 -63 63 -65 +CIRCLE Normal 66 -62 62 -66 +CIRCLE Normal 67 -61 61 -67 +CIRCLE Normal 65 -31 63 -33 +CIRCLE Normal 66 -30 62 -34 +CIRCLE Normal 67 -29 61 -35 +CIRCLE Normal 65 1 63 -1 +CIRCLE Normal 66 2 62 -2 +CIRCLE Normal 67 3 61 -3 +CIRCLE Normal 65 65 63 63 +CIRCLE Normal 66 66 62 62 +CIRCLE Normal 67 67 61 61 +TEXT 0 288 Center 2 ADI +TEXT -102 -256 Bottom 2 S1 +TEXT -102 -192 Bottom 2 S2 +TEXT -102 -128 Bottom 2 S3 +TEXT -102 -64 Bottom 2 S4 +TEXT -102 0 Bottom 2 S5 +TEXT -102 64 Bottom 2 S6 +TEXT -102 128 Bottom 2 S7 +TEXT -102 192 Bottom 2 S8 +TEXT 102 -32 Bottom 2 D +WINDOW 0 64 -320 Bottom 2 +WINDOW 3 0 352 Center 2 +SYMATTR Value ADG1408 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1408.sub +SYMATTR Value2 ADG1408 +SYMATTR Description 4 Ohm Ron, 8-Channel, ±15V/+12V/±5V iCMOS Multiplexer +PIN -128 256 LEFT 8 +PINATTR PinName A0 +PINATTR SpiceOrder 2 +PIN 128 256 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 432 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN -128 -256 NONE 8 +PINATTR PinName S1 +PINATTR SpiceOrder 8 +PIN -128 -192 NONE 8 +PINATTR PinName S2 +PINATTR SpiceOrder 9 +PIN -128 -128 NONE 8 +PINATTR PinName S3 +PINATTR SpiceOrder 10 +PIN -128 -64 NONE 8 +PINATTR PinName S4 +PINATTR SpiceOrder 11 +PIN 128 -32 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 16 +PIN -128 192 NONE 8 +PINATTR PinName S8 +PINATTR SpiceOrder 15 +PIN -128 128 NONE 8 +PINATTR PinName S7 +PINATTR SpiceOrder 14 +PIN -128 64 NONE 8 +PINATTR PinName S6 +PINATTR SpiceOrder 13 +PIN -128 0 NONE 8 +PINATTR PinName S5 +PINATTR SpiceOrder 12 +PIN 0 -320 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN 64 432 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN -128 384 LEFT 8 +PINATTR PinName A2 +PINATTR SpiceOrder 4 +PIN -128 320 LEFT 8 +PINATTR PinName A1 +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/Switches/ADG1411.asy b/spice/copy/sym/Switches/ADG1411.asy new file mode 100755 index 0000000..1f7d2e4 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1411.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +LINE Normal 0 16 -10 16 2 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal -10 19 -16 13 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 -51 84 Left 2 +SYMATTR Value ADG1411 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1411.sub +SYMATTR Value2 ADG1411 +SYMATTR Description 1.5 Ohm Resistance, +/-15V, +12V, +/-5V, iCMOS, Quad SPST Switch\n\n Also models 2 channels of the ADG1413 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1412.asy b/spice/copy/sym/Switches/ADG1412.asy new file mode 100755 index 0000000..7eafa93 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1412.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 -51 84 Left 2 +SYMATTR Value ADG1412 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1412.sub +SYMATTR Value2 ADG1412 +SYMATTR Description 1.5 Ω Typical On Resistance, ±15V, +12V, ±5V, iCMOS, Quad SPST Switch\n\nAlso models 2 channels of the ADG1413 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1414.asy b/spice/copy/sym/Switches/ADG1414.asy new file mode 100755 index 0000000..2c422ec Binary files /dev/null and b/spice/copy/sym/Switches/ADG1414.asy differ diff --git a/spice/copy/sym/Switches/ADG1419.asy b/spice/copy/sym/Switches/ADG1419.asy new file mode 100755 index 0000000..519c5b3 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1419.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal -16 -80 32 -48 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +TEXT 77 48 Bottom 2 EN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG1419 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1419.sub +SYMATTR Value2 ADG1419 +SYMATTR Description 2.1 Ohm On Resistance, +/-15V/+12V/+/-5V, iCMOS SPDT Switch +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN 96 48 NONE 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG1421.asy b/spice/copy/sym/Switches/ADG1421.asy new file mode 100755 index 0000000..59bd5e4 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1421.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 -51 84 Left 2 +SYMATTR Value ADG1421 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1421.sub +SYMATTR Value2 ADG1421 +SYMATTR Description 2.1 On Resistance, ±15V, +12V, ±5V, iCMOS, Dual SPST Switch\n\nAlso models 1 channel of the ADG1423 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1422.asy b/spice/copy/sym/Switches/ADG1422.asy new file mode 100755 index 0000000..d2023d6 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1422.asy @@ -0,0 +1,45 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +LINE Normal -10 16 0 16 2 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal -10 19 -16 13 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 -51 84 Left 2 +SYMATTR Value ADG1422 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1422.sub +SYMATTR Value2 ADG1422 +SYMATTR Description 2.1 On Resistance, ±15V, +12V, ±5V, iCMOS, Dual SPST Switch\n\nAlso models 1 channel of the ADG1423 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG1433.asy b/spice/copy/sym/Switches/ADG1433.asy new file mode 100755 index 0000000..c8f6b69 --- /dev/null +++ b/spice/copy/sym/Switches/ADG1433.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 32 -48 -16 -80 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +TEXT -79 112 Bottom 2 _EN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG1433 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1433.sub +SYMATTR Value2 ADG1433 +SYMATTR Description 4 Ohm On-Resistance, Triple/Quad SPDT, +/-15 V, +12 V, +/-5 V Switches \n \n Only one channel is modelled +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -96 112 NONE 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG1434.asy b/spice/copy/sym/Switches/ADG1434.asy new file mode 100755 index 0000000..284996b Binary files /dev/null and b/spice/copy/sym/Switches/ADG1434.asy differ diff --git a/spice/copy/sym/Switches/ADG1436.asy b/spice/copy/sym/Switches/ADG1436.asy new file mode 100755 index 0000000..a66d26c --- /dev/null +++ b/spice/copy/sym/Switches/ADG1436.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 32 -48 -16 -80 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +TEXT 77 48 Bottom 2 EN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG1436 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1436.sub +SYMATTR Value2 ADG1436 +SYMATTR Description 1.5 Ohm, On Resistance, +/-15V/+12V/+/-5V, iCMOS, Dual SPDT Switch +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN 96 48 NONE 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG1611.asy b/spice/copy/sym/Switches/ADG1611.asy new file mode 100755 index 0000000..1e898a6 Binary files /dev/null and b/spice/copy/sym/Switches/ADG1611.asy differ diff --git a/spice/copy/sym/Switches/ADG1612.asy b/spice/copy/sym/Switches/ADG1612.asy new file mode 100755 index 0000000..e7a6eba Binary files /dev/null and b/spice/copy/sym/Switches/ADG1612.asy differ diff --git a/spice/copy/sym/Switches/ADG1633.asy b/spice/copy/sym/Switches/ADG1633.asy new file mode 100755 index 0000000..7aa6fa6 Binary files /dev/null and b/spice/copy/sym/Switches/ADG1633.asy differ diff --git a/spice/copy/sym/Switches/ADG1634.asy b/spice/copy/sym/Switches/ADG1634.asy new file mode 100755 index 0000000..c43568a Binary files /dev/null and b/spice/copy/sym/Switches/ADG1634.asy differ diff --git a/spice/copy/sym/Switches/ADG1636.asy b/spice/copy/sym/Switches/ADG1636.asy new file mode 100755 index 0000000..b48fa3d --- /dev/null +++ b/spice/copy/sym/Switches/ADG1636.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 32 -48 -16 -80 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +TEXT -79 112 Bottom 2 EN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG1636 +SYMATTR Prefix X +SYMATTR SpiceModel ADG1636.sub +SYMATTR Value2 ADG1636 +SYMATTR Description 1 Ohm Typical On-Resistance, +/-5 V, +12 V, +5 V, and +3.3V Dual Switches \n \n Only one channel is modelled +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -96 112 NONE 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG411.asy b/spice/copy/sym/Switches/ADG411.asy new file mode 100755 index 0000000..ece268b --- /dev/null +++ b/spice/copy/sym/Switches/ADG411.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +LINE Normal 16 -51 -16 -51 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG411 +SYMATTR Prefix X +SYMATTR SpiceModel ADG411.sub +SYMATTR Value2 ADG411 +SYMATTR Description LC2MOS Precision Quad SPST Switches (VL = 5V) +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG412.asy b/spice/copy/sym/Switches/ADG412.asy new file mode 100755 index 0000000..ae0cc40 --- /dev/null +++ b/spice/copy/sym/Switches/ADG412.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG412 +SYMATTR Prefix X +SYMATTR SpiceModel ADG412.sub +SYMATTR Value2 ADG412 +SYMATTR Description LC2MOS Precision Quad SPST Switches (VL = 5V) +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG419.asy b/spice/copy/sym/Switches/ADG419.asy new file mode 100755 index 0000000..71f0a96 --- /dev/null +++ b/spice/copy/sym/Switches/ADG419.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal -16 -80 32 -48 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 S1 +TEXT -79 -16 Bottom 2 S2 +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG419 +SYMATTR Prefix X +SYMATTR SpiceModel ADG419.sub +SYMATTR Value2 ADG419 +SYMATTR Description LC2MOS Precision Mini-DIP Analog Switch (VL = 5V) +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName S1 +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName S2 +PINATTR SpiceOrder 4 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Switches/ADG436.asy b/spice/copy/sym/Switches/ADG436.asy new file mode 100755 index 0000000..7671357 --- /dev/null +++ b/spice/copy/sym/Switches/ADG436.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal -17 -21 27 -46 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -80 -80 Bottom 2 SA +TEXT -80 -16 Bottom 2 SB +TEXT 80 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG436 +SYMATTR Prefix X +SYMATTR SpiceModel ADG436.sub +SYMATTR Value2 ADG436 +SYMATTR Description Dual SPDT Switch (VL = 5V) +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 5 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/Switches/ADG451.asy b/spice/copy/sym/Switches/ADG451.asy new file mode 100755 index 0000000..b9096a4 --- /dev/null +++ b/spice/copy/sym/Switches/ADG451.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +LINE Normal 16 -51 -16 -51 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG451 +SYMATTR Prefix X +SYMATTR SpiceModel ADG451.sub +SYMATTR Value2 ADG451 +SYMATTR Description LC2MOS 5 Ω RON SPST Switch (VL = 5V) +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG452.asy b/spice/copy/sym/Switches/ADG452.asy new file mode 100755 index 0000000..7a56a8b --- /dev/null +++ b/spice/copy/sym/Switches/ADG452.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG452 +SYMATTR Prefix X +SYMATTR SpiceModel ADG452.sub +SYMATTR Value2 ADG452 +SYMATTR Description LC2MOS 5 Ω RON SPST Switch (VL = 5V) +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG5212.asy b/spice/copy/sym/Switches/ADG5212.asy new file mode 100755 index 0000000..cf046a5 --- /dev/null +++ b/spice/copy/sym/Switches/ADG5212.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG5212 +SYMATTR Prefix X +SYMATTR SpiceModel ADG5212.sub +SYMATTR Value2 ADG5212 +SYMATTR Description High Voltage Latch-Up Proof, Quad SPST Switch +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG5233.asy b/spice/copy/sym/Switches/ADG5233.asy new file mode 100755 index 0000000..e4de919 --- /dev/null +++ b/spice/copy/sym/Switches/ADG5233.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 32 -48 -16 -80 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +TEXT -79 112 Bottom 2 _EN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG5233 +SYMATTR Prefix X +SYMATTR SpiceModel ADG5233.sub +SYMATTR Value2 ADG5233 +SYMATTR Description High Voltage, Latch-Up Proof, Triple/Quad SPDT, +/-15 V, +12 V, iCMOS Switches \n \n Only one channel is modelled +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -96 112 NONE 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG5236.asy b/spice/copy/sym/Switches/ADG5236.asy new file mode 100755 index 0000000..ec92184 --- /dev/null +++ b/spice/copy/sym/Switches/ADG5236.asy @@ -0,0 +1,50 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 28 -48 -16 -21 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -76 -80 Bottom 2 SA +TEXT -76 -16 Bottom 2 SB +TEXT 80 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG5236 +SYMATTR Prefix X +SYMATTR SpiceModel ADG5236.sub +SYMATTR Value2 ADG5236 +SYMATTR Description High Voltage Latch-Up Proof, Dual SPDT Switches +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 5 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 diff --git a/spice/copy/sym/Switches/ADG5248F.asy b/spice/copy/sym/Switches/ADG5248F.asy new file mode 100755 index 0000000..0b68ea0 --- /dev/null +++ b/spice/copy/sym/Switches/ADG5248F.asy @@ -0,0 +1,143 @@ +Version 4 +SymbolType CELL +LINE Normal 21 192 64 192 +LINE Normal -144 192 -53 192 +LINE Normal 12 171 -44 190 +LINE Normal 21 128 64 128 +LINE Normal -144 128 -53 128 +LINE Normal 12 107 -44 126 +LINE Normal 21 64 64 64 +LINE Normal -144 64 -53 64 +LINE Normal 12 43 -44 62 +LINE Normal 21 0 64 0 +LINE Normal -144 0 -53 0 +LINE Normal 12 -21 -44 -2 +LINE Normal 21 -64 64 -64 +LINE Normal -144 -64 -53 -64 +LINE Normal 12 -85 -44 -66 +LINE Normal 21 -128 64 -128 +LINE Normal -144 -128 -53 -128 +LINE Normal 12 -149 -44 -130 +LINE Normal 21 -192 64 -192 +LINE Normal -144 -192 -53 -192 +LINE Normal 12 -213 -44 -194 +LINE Normal 21 -256 64 -256 +LINE Normal -144 -256 -53 -256 +LINE Normal 12 -277 -44 -258 +LINE Normal 64 -256 64 192 +LINE Normal 64 -32 144 -32 +RECTANGLE Normal -144 -320 144 448 +CIRCLE Normal 11 197 21 187 +CIRCLE Normal -53 197 -43 187 +CIRCLE Normal 11 133 21 123 +CIRCLE Normal -53 133 -43 123 +CIRCLE Normal 11 69 21 59 +CIRCLE Normal -53 69 -43 59 +CIRCLE Normal 11 5 21 -5 +CIRCLE Normal -53 5 -43 -5 +CIRCLE Normal 11 -59 21 -69 +CIRCLE Normal -53 -59 -43 -69 +CIRCLE Normal 11 -123 21 -133 +CIRCLE Normal -53 -123 -43 -133 +CIRCLE Normal 11 -187 21 -197 +CIRCLE Normal -53 -187 -43 -197 +CIRCLE Normal 11 -251 21 -261 +CIRCLE Normal -53 -251 -43 -261 +CIRCLE Normal 65 129 63 127 +CIRCLE Normal 66 130 62 126 +CIRCLE Normal 67 131 61 125 +CIRCLE Normal 65 -191 63 -193 +CIRCLE Normal 66 -190 62 -194 +CIRCLE Normal 67 -189 61 -195 +CIRCLE Normal 65 -127 63 -129 +CIRCLE Normal 66 -126 62 -130 +CIRCLE Normal 67 -125 61 -131 +CIRCLE Normal 65 -63 63 -65 +CIRCLE Normal 66 -62 62 -66 +CIRCLE Normal 67 -61 61 -67 +CIRCLE Normal 65 -31 63 -33 +CIRCLE Normal 66 -30 62 -34 +CIRCLE Normal 67 -29 61 -35 +CIRCLE Normal 65 1 63 -1 +CIRCLE Normal 66 2 62 -2 +CIRCLE Normal 67 3 61 -3 +CIRCLE Normal 65 65 63 63 +CIRCLE Normal 66 66 62 62 +CIRCLE Normal 67 67 61 61 +TEXT 0 288 Center 2 ADI +TEXT -118 -256 Bottom 2 S1 +TEXT -118 -192 Bottom 2 S2 +TEXT -118 -128 Bottom 2 S3 +TEXT -118 -64 Bottom 2 S4 +TEXT -118 0 Bottom 2 S5 +TEXT -118 64 Bottom 2 S6 +TEXT -118 128 Bottom 2 S7 +TEXT -118 192 Bottom 2 S8 +TEXT 118 -32 Bottom 2 D +WINDOW 0 2 -321 Bottom 2 +WINDOW 3 0 352 Center 2 +SYMATTR Value ADG5248F +SYMATTR Prefix X +SYMATTR SpiceModel ADG.lib +SYMATTR Value2 ADG5248F +SYMATTR Description User-Defined Fault Protection and Detection, 0.8pC Qinj, 8:1 Multiplexer +PIN -144 256 LEFT 8 +PINATTR PinName A0/F0 +PINATTR SpiceOrder 1 +PIN 144 256 RIGHT 8 +PINATTR PinName EN/F2 +PINATTR SpiceOrder 2 +PIN 0 448 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 3 +PIN -144 -256 NONE 8 +PINATTR PinName S1 +PINATTR SpiceOrder 4 +PIN -144 -192 NONE 8 +PINATTR PinName S2 +PINATTR SpiceOrder 5 +PIN -144 -128 NONE 8 +PINATTR PinName S3 +PINATTR SpiceOrder 6 +PIN -144 -64 NONE 8 +PINATTR PinName S4 +PINATTR SpiceOrder 7 +PIN 144 -32 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 8 +PIN -144 192 NONE 8 +PINATTR PinName S8 +PINATTR SpiceOrder 9 +PIN -144 128 NONE 8 +PINATTR PinName S7 +PINATTR SpiceOrder 10 +PIN -144 64 NONE 8 +PINATTR PinName S6 +PINATTR SpiceOrder 11 +PIN -144 0 NONE 8 +PINATTR PinName S5 +PINATTR SpiceOrder 12 +PIN 64 -320 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 13 +PIN 80 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN -144 384 LEFT 8 +PINATTR PinName A2 +PINATTR SpiceOrder 15 +PIN -144 320 LEFT 8 +PINATTR PinName A1/F1 +PINATTR SpiceOrder 16 +PIN -80 448 BOTTOM 8 +PINATTR PinName NEGFV +PINATTR SpiceOrder 17 +PIN -64 -320 TOP 8 +PINATTR PinName POSFV +PINATTR SpiceOrder 18 +PIN 144 320 RIGHT 8 +PINATTR PinName FF +PINATTR SpiceOrder 19 +PIN 144 384 RIGHT 8 +PINATTR PinName SF +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/Switches/ADG5249F.asy b/spice/copy/sym/Switches/ADG5249F.asy new file mode 100755 index 0000000..f52f147 --- /dev/null +++ b/spice/copy/sym/Switches/ADG5249F.asy @@ -0,0 +1,143 @@ +Version 4 +SymbolType CELL +LINE Normal 21 192 64 192 +LINE Normal -144 192 -53 192 +LINE Normal 12 171 -44 190 +LINE Normal 21 128 64 128 +LINE Normal -144 128 -53 128 +LINE Normal 12 107 -44 126 +LINE Normal 21 64 64 64 +LINE Normal -144 64 -53 64 +LINE Normal 12 43 -44 62 +LINE Normal 21 0 64 0 +LINE Normal -144 0 -53 0 +LINE Normal 12 -21 -44 -2 +LINE Normal 21 -64 64 -64 +LINE Normal -144 -64 -53 -64 +LINE Normal 12 -85 -44 -66 +LINE Normal 21 -128 64 -128 +LINE Normal -144 -128 -53 -128 +LINE Normal 12 -149 -44 -130 +LINE Normal 21 -192 64 -192 +LINE Normal -144 -192 -53 -192 +LINE Normal 12 -213 -44 -194 +LINE Normal 21 -256 64 -256 +LINE Normal -144 -256 -53 -256 +LINE Normal 12 -277 -44 -258 +LINE Normal 64 0 64 192 +LINE Normal 64 -160 144 -160 +LINE Normal 64 96 144 96 +LINE Normal 64 -256 64 -64 +RECTANGLE Normal -144 -320 144 448 +CIRCLE Normal 11 197 21 187 +CIRCLE Normal -53 197 -43 187 +CIRCLE Normal 11 133 21 123 +CIRCLE Normal -53 133 -43 123 +CIRCLE Normal 11 69 21 59 +CIRCLE Normal -53 69 -43 59 +CIRCLE Normal 11 5 21 -5 +CIRCLE Normal -53 5 -43 -5 +CIRCLE Normal 11 -59 21 -69 +CIRCLE Normal -53 -59 -43 -69 +CIRCLE Normal 11 -123 21 -133 +CIRCLE Normal -53 -123 -43 -133 +CIRCLE Normal 11 -187 21 -197 +CIRCLE Normal -53 -187 -43 -197 +CIRCLE Normal 11 -251 21 -261 +CIRCLE Normal -53 -251 -43 -261 +CIRCLE Normal 65 129 63 127 +CIRCLE Normal 66 130 62 126 +CIRCLE Normal 67 131 61 125 +CIRCLE Normal 65 -191 63 -193 +CIRCLE Normal 66 -190 62 -194 +CIRCLE Normal 67 -189 61 -195 +CIRCLE Normal 65 -127 63 -129 +CIRCLE Normal 66 -126 62 -130 +CIRCLE Normal 67 -125 61 -131 +CIRCLE Normal 65 -159 63 -161 +CIRCLE Normal 66 -158 62 -162 +CIRCLE Normal 67 -157 61 -163 +CIRCLE Normal 65 65 63 63 +CIRCLE Normal 66 66 62 62 +CIRCLE Normal 67 67 61 61 +CIRCLE Normal 65 97 63 95 +CIRCLE Normal 66 98 62 94 +CIRCLE Normal 67 99 61 93 +TEXT 0 288 Center 2 ADI +TEXT -118 -256 Bottom 2 S1 +TEXT -118 -192 Bottom 2 S2 +TEXT -118 -128 Bottom 2 S3 +TEXT -118 -64 Bottom 2 S4 +TEXT -118 0 Bottom 2 S5 +TEXT -118 64 Bottom 2 S6 +TEXT -118 128 Bottom 2 S7 +TEXT -118 192 Bottom 2 S8 +TEXT 118 -160 Bottom 2 DA +TEXT 118 96 Bottom 2 DB +WINDOW 0 2 -321 Bottom 2 +WINDOW 3 0 352 Center 2 +SYMATTR Value ADG5249F +SYMATTR Prefix X +SYMATTR SpiceModel ADG.lib +SYMATTR Value2 ADG5249F +SYMATTR Description User-Defined Fault Protection and Detection, 0.8pC Qinj, 4:1 Multiplexers +PIN -144 256 LEFT 8 +PINATTR PinName A0/F0 +PINATTR SpiceOrder 1 +PIN 144 256 RIGHT 8 +PINATTR PinName EN/F2 +PINATTR SpiceOrder 2 +PIN 0 448 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 3 +PIN -144 -256 NONE 8 +PINATTR PinName S1 +PINATTR SpiceOrder 4 +PIN -144 -192 NONE 8 +PINATTR PinName S2 +PINATTR SpiceOrder 5 +PIN -144 -128 NONE 8 +PINATTR PinName S3 +PINATTR SpiceOrder 6 +PIN -144 -64 NONE 8 +PINATTR PinName S4 +PINATTR SpiceOrder 7 +PIN 144 -160 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 8 +PIN -144 192 NONE 8 +PINATTR PinName S8 +PINATTR SpiceOrder 9 +PIN -144 128 NONE 8 +PINATTR PinName S7 +PINATTR SpiceOrder 10 +PIN -144 64 NONE 8 +PINATTR PinName S6 +PINATTR SpiceOrder 11 +PIN -144 0 NONE 8 +PINATTR PinName S5 +PINATTR SpiceOrder 12 +PIN 64 -320 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 13 +PIN 80 448 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 14 +PIN 144 96 NONE 8 +PINATTR PinName D1 +PINATTR SpiceOrder 15 +PIN -144 320 LEFT 8 +PINATTR PinName A1/F1 +PINATTR SpiceOrder 16 +PIN -80 448 BOTTOM 8 +PINATTR PinName NEGFV +PINATTR SpiceOrder 17 +PIN -64 -320 TOP 8 +PINATTR PinName POSFV +PINATTR SpiceOrder 18 +PIN 144 320 RIGHT 8 +PINATTR PinName FF +PINATTR SpiceOrder 19 +PIN 144 384 RIGHT 8 +PINATTR PinName SF +PINATTR SpiceOrder 20 diff --git a/spice/copy/sym/Switches/ADG5401.asy b/spice/copy/sym/Switches/ADG5401.asy new file mode 100755 index 0000000..0afecff --- /dev/null +++ b/spice/copy/sym/Switches/ADG5401.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 1 83 Center 2 +SYMATTR Value ADG5401 +SYMATTR Prefix X +SYMATTR SpiceModel ADG5401.sub +SYMATTR Value2 ADG5401 +SYMATTR Description High Voltage, Latch-Up Proof, Single SPST Switch \n\n Only one channel is modeled +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG5412.asy b/spice/copy/sym/Switches/ADG5412.asy new file mode 100755 index 0000000..a85f3c4 --- /dev/null +++ b/spice/copy/sym/Switches/ADG5412.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 -51 84 Left 2 +SYMATTR Value ADG5412 +SYMATTR Prefix X +SYMATTR SpiceModel ADG5412.sub +SYMATTR Value2 ADG5412 +SYMATTR Description High Voltage Latch-up Proof Quad SPST Switches \n\nAlso models 2 channels of the ADG1413 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG5412F.asy b/spice/copy/sym/Switches/ADG5412F.asy new file mode 100755 index 0000000..987ad11 Binary files /dev/null and b/spice/copy/sym/Switches/ADG5412F.asy differ diff --git a/spice/copy/sym/Switches/ADG5419.asy b/spice/copy/sym/Switches/ADG5419.asy new file mode 100755 index 0000000..eb66ac6 --- /dev/null +++ b/spice/copy/sym/Switches/ADG5419.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal -16 -80 32 -48 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +TEXT -79 95 Bottom 2 EN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG5419 +SYMATTR Prefix X +SYMATTR SpiceModel ADG5419.sub +SYMATTR Value2 ADG5419 +SYMATTR Description High Voltage Latch-Up Proof Single SPDT SPDT Switch +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -96 96 NONE 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG5421.asy b/spice/copy/sym/Switches/ADG5421.asy new file mode 100755 index 0000000..c362ed4 --- /dev/null +++ b/spice/copy/sym/Switches/ADG5421.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 -51 84 Left 2 +SYMATTR Value ADG5421 +SYMATTR Prefix X +SYMATTR SpiceModel ADG5421.sub +SYMATTR Value2 ADG5421 +SYMATTR Description High Voltage, Latch-up Proof, Dual SPST Switch\n\nAlso models 1 channel of the ADG5423 +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG5433.asy b/spice/copy/sym/Switches/ADG5433.asy new file mode 100755 index 0000000..cb2235e --- /dev/null +++ b/spice/copy/sym/Switches/ADG5433.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 32 -48 -16 -80 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +TEXT -79 112 Bottom 2 _EN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG5433 +SYMATTR Prefix X +SYMATTR SpiceModel ADG5433.sub +SYMATTR Value2 ADG5433 +SYMATTR Description High Voltage Latch-up Proof, Triple/Quad SPDT Switches \n \n Only one channel is modelled +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN -96 112 NONE 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG5436.asy b/spice/copy/sym/Switches/ADG5436.asy new file mode 100755 index 0000000..02076c3 --- /dev/null +++ b/spice/copy/sym/Switches/ADG5436.asy @@ -0,0 +1,54 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal 32 -48 -16 -80 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -78 -81 Bottom 2 SA +TEXT -79 -16 Bottom 2 SB +TEXT 81 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +TEXT 77 48 Bottom 2 EN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG5436 +SYMATTR Prefix X +SYMATTR SpiceModel ADG5436.sub +SYMATTR Value2 ADG5436 +SYMATTR Description High Voltage Latch-Up Proof, Dual SPDT Switches \n \n One channel modelled +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN 96 48 NONE 8 +PINATTR PinName EN +PINATTR SpiceOrder 5 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 6 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 7 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG611.asy b/spice/copy/sym/Switches/ADG611.asy new file mode 100755 index 0000000..3f79d75 --- /dev/null +++ b/spice/copy/sym/Switches/ADG611.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +LINE Normal 16 -51 -16 -51 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG611 +SYMATTR Prefix X +SYMATTR SpiceModel ADG611.sub +SYMATTR Value2 ADG611 +SYMATTR Description 1 pC Charge Injection, 100 pA Leakage, CMOS, +/-5V +5V/+3V, Quad SPST Switches +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG612.asy b/spice/copy/sym/Switches/ADG612.asy new file mode 100755 index 0000000..2823f86 --- /dev/null +++ b/spice/copy/sym/Switches/ADG612.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADG612 +SYMATTR Prefix X +SYMATTR SpiceModel ADG612.sub +SYMATTR Value2 ADG612 +SYMATTR Description 1 pC Charge Injection, 100 pA Leakage, CMOS, +/-5V +5V/+3V, Quad SPST Switches +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADG636.asy b/spice/copy/sym/Switches/ADG636.asy new file mode 100755 index 0000000..4a85286 --- /dev/null +++ b/spice/copy/sym/Switches/ADG636.asy @@ -0,0 +1,53 @@ +Version 4 +SymbolType CELL +LINE Normal 37 -48 96 -48 +LINE Normal -96 -16 -21 -16 +LINE Normal -64 48 -96 48 +LINE Normal -64 64 -64 32 +LINE Normal -32 48 -64 32 +LINE Normal -64 64 -32 48 +LINE Normal -21 -80 -96 -80 +LINE Normal 0 48 -32 48 2 +LINE Normal 0 0 0 48 2 +LINE Normal -17 -75 27 -48 +RECTANGLE Normal -96 -144 96 160 +CIRCLE Normal 27 -43 37 -53 +CIRCLE Normal -48 0 48 -96 2 +CIRCLE Normal -21 -11 -11 -21 +CIRCLE Normal -21 -75 -11 -85 +TEXT 0 80 Center 2 ADI +TEXT -80 -80 Bottom 2 SA +TEXT -80 -16 Bottom 2 SB +TEXT 80 -48 Bottom 2 D +TEXT -80 48 Bottom 2 IN +WINDOW 0 64 -144 Bottom 2 +WINDOW 3 0 112 Center 2 +SYMATTR Value ADG636 +SYMATTR Prefix X +SYMATTR SpiceModel ADG636.sub +SYMATTR Value2 ADG636 +SYMATTR Description 1 pC Charge Injection, 100 pA Leakage, CMOS, ±5 V/+5 V/+3 V Dual SPDT Switch +PIN 96 48 RIGHT 8 +PINATTR PinName EN +PINATTR SpiceOrder 8 +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 7 +PIN 64 160 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 6 +PIN -64 160 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 5 +PIN -96 -16 NONE 8 +PINATTR PinName SB +PINATTR SpiceOrder 4 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 3 +PIN -96 -80 NONE 8 +PINATTR PinName SA +PINATTR SpiceOrder 2 +PIN -96 48 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 diff --git a/spice/copy/sym/Switches/ADG701.asy b/spice/copy/sym/Switches/ADG701.asy new file mode 100755 index 0000000..7901e8e --- /dev/null +++ b/spice/copy/sym/Switches/ADG701.asy @@ -0,0 +1,42 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +TEXT -22 -95 Left 2 Vdd +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 1 83 Center 2 +SYMATTR Value ADG701 +SYMATTR Prefix X +SYMATTR SpiceModel ADG701.sub +SYMATTR Value2 ADG701 +SYMATTR Description CMOS Low Voltage 2 Ohm SPST Switches +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 0 -112 NONE 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Switches/ADG702.asy b/spice/copy/sym/Switches/ADG702.asy new file mode 100755 index 0000000..3098eae --- /dev/null +++ b/spice/copy/sym/Switches/ADG702.asy @@ -0,0 +1,43 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +LINE Normal -10 16 0 16 2 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal -16 13 -10 19 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +TEXT -22 -95 Left 2 Vdd +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 1 83 Center 2 +SYMATTR Value ADG702 +SYMATTR Prefix X +SYMATTR SpiceModel ADG702.sub +SYMATTR Value2 ADG702 +SYMATTR Description CMOS Low Voltage 2 Ohm SPST Switches +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN 0 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 4 +PIN 0 -112 NONE 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 5 diff --git a/spice/copy/sym/Switches/ADG711.asy b/spice/copy/sym/Switches/ADG711.asy new file mode 100755 index 0000000..93c7163 Binary files /dev/null and b/spice/copy/sym/Switches/ADG711.asy differ diff --git a/spice/copy/sym/Switches/ADG712.asy b/spice/copy/sym/Switches/ADG712.asy new file mode 100755 index 0000000..9cb9e3a Binary files /dev/null and b/spice/copy/sym/Switches/ADG712.asy differ diff --git a/spice/copy/sym/Switches/ADG721.asy b/spice/copy/sym/Switches/ADG721.asy new file mode 100755 index 0000000..195549a Binary files /dev/null and b/spice/copy/sym/Switches/ADG721.asy differ diff --git a/spice/copy/sym/Switches/ADG722.asy b/spice/copy/sym/Switches/ADG722.asy new file mode 100755 index 0000000..92963b9 Binary files /dev/null and b/spice/copy/sym/Switches/ADG722.asy differ diff --git a/spice/copy/sym/Switches/ADG741.asy b/spice/copy/sym/Switches/ADG741.asy new file mode 100755 index 0000000..e8c1604 Binary files /dev/null and b/spice/copy/sym/Switches/ADG741.asy differ diff --git a/spice/copy/sym/Switches/ADG742.asy b/spice/copy/sym/Switches/ADG742.asy new file mode 100755 index 0000000..675721c Binary files /dev/null and b/spice/copy/sym/Switches/ADG742.asy differ diff --git a/spice/copy/sym/Switches/ADG801.asy b/spice/copy/sym/Switches/ADG801.asy new file mode 100755 index 0000000..b3e86a2 Binary files /dev/null and b/spice/copy/sym/Switches/ADG801.asy differ diff --git a/spice/copy/sym/Switches/ADG802.asy b/spice/copy/sym/Switches/ADG802.asy new file mode 100755 index 0000000..8b9803f Binary files /dev/null and b/spice/copy/sym/Switches/ADG802.asy differ diff --git a/spice/copy/sym/Switches/ADG918.asy b/spice/copy/sym/Switches/ADG918.asy new file mode 100755 index 0000000..6ced6c9 --- /dev/null +++ b/spice/copy/sym/Switches/ADG918.asy @@ -0,0 +1,85 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -96 -64 -96 +LINE Normal 96 -96 19 -96 +LINE Normal -64 64 -96 64 +LINE Normal 15 -106 -13 -97 +LINE Normal -64 80 -64 48 +LINE Normal -32 64 -64 48 +LINE Normal -64 80 -32 64 +LINE Normal 0 64 -32 64 2 +LINE Normal -19 16 -64 16 +LINE Normal 96 16 19 16 +LINE Normal 19 13 -13 15 +LINE Normal 51 -55 48 -77 +LINE Normal 48 -96 48 -83 +LINE Normal 48 -55 48 -48 +LINE Normal 54 -17 42 -17 +LINE Normal 48 -11 42 -17 +LINE Normal 48 -11 54 -17 +LINE Normal 58 55 49 35 +LINE Normal 48 16 48 29 +LINE Normal 0 64 0 -96 2 +LINE Normal -64 -96 -64 16 +LINE Normal -64 -32 -96 -32 +LINE Normal 48 -48 54 -45 +LINE Normal 42 -27 48 -24 +LINE Normal 42 -39 54 -45 +LINE Normal 54 -33 42 -39 +LINE Normal 42 -27 54 -33 +LINE Normal 48 -24 48 -17 +LINE Normal 48 57 48 64 +LINE Normal 54 95 42 95 +LINE Normal 48 101 42 95 +LINE Normal 48 101 54 95 +LINE Normal 48 64 54 67 +LINE Normal 42 85 48 88 +LINE Normal 42 73 54 67 +LINE Normal 54 79 42 73 +LINE Normal 42 85 54 79 +LINE Normal 48 88 48 95 +LINE Normal 0 -69 48 -69 2 +LINE Normal 0 42 48 42 2 +RECTANGLE Normal -96 -144 96 176 +CIRCLE Normal -13 -93 -19 -99 +CIRCLE Normal 19 -93 13 -99 +CIRCLE Normal -13 19 -19 13 +CIRCLE Normal 19 19 13 13 +CIRCLE Normal 45 -77 51 -83 +CIRCLE Normal 45 -55 51 -61 +CIRCLE Normal 45 35 51 29 +CIRCLE Normal 45 57 51 51 +CIRCLE Normal -63 -31 -65 -33 +CIRCLE Normal -62 -30 -66 -34 +CIRCLE Normal 49 -95 47 -97 +CIRCLE Normal 50 -94 46 -98 +CIRCLE Normal 49 17 47 15 +CIRCLE Normal 50 18 46 14 +TEXT 0 124 Center 2 ADI +TEXT 69 -96 Bottom 1 RF1 +TEXT 68 16 Bottom 1 RF2 +WINDOW 0 16 -160 Left 2 +WINDOW 3 16 192 Left 2 +SYMATTR Value ADG918 +SYMATTR Prefix X +SYMATTR SpiceModel ADG.lib +SYMATTR Value2 ADG918 +SYMATTR Description Wideband 4GHz, 43dB Isolation at 1GHz, CMOS 1.65V to 2.75V, 2:1 Mux/SPDT +PIN 0 -144 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -96 64 NONE 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 2 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 -32 NONE 8 +PINATTR PinName RFC +PINATTR SpiceOrder 4 +PIN 96 16 NONE 8 +PINATTR PinName RF2 +PINATTR SpiceOrder 5 +PIN 96 -96 NONE 8 +PINATTR PinName RF1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADG919.asy b/spice/copy/sym/Switches/ADG919.asy new file mode 100755 index 0000000..763f5fc --- /dev/null +++ b/spice/copy/sym/Switches/ADG919.asy @@ -0,0 +1,73 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -64 -64 -64 +LINE Normal 96 -64 19 -64 +LINE Normal -64 80 -96 80 +LINE Normal 15 -74 -13 -65 +LINE Normal -64 96 -64 64 +LINE Normal -32 80 -64 64 +LINE Normal -64 96 -32 80 +LINE Normal 0 80 -32 80 2 +LINE Normal -19 32 -64 32 +LINE Normal 96 32 19 32 +LINE Normal 19 29 -13 31 +LINE Normal 51 -23 48 -45 +LINE Normal 48 -64 48 -51 +LINE Normal 48 -23 48 -10 +LINE Normal 55 -10 42 -10 +LINE Normal 48 -4 42 -10 +LINE Normal 48 -4 54 -10 +LINE Normal 58 71 49 51 +LINE Normal 48 32 48 45 +LINE Normal 48 73 48 86 +LINE Normal 55 86 42 86 +LINE Normal 48 92 42 86 +LINE Normal 48 92 54 86 +LINE Normal 0 80 0 -64 2 +LINE Normal -64 -64 -64 32 +LINE Normal -64 -16 -96 -16 +LINE Normal 48 -37 0 -37 2 +LINE Normal 48 59 0 59 2 +RECTANGLE Normal -96 -112 96 176 +CIRCLE Normal -13 -61 -19 -67 +CIRCLE Normal 19 -61 13 -67 +CIRCLE Normal -13 35 -19 29 +CIRCLE Normal 19 35 13 29 +CIRCLE Normal 45 -45 51 -51 +CIRCLE Normal 45 -23 51 -29 +CIRCLE Normal 45 51 51 45 +CIRCLE Normal 45 73 51 67 +CIRCLE Normal -63 -15 -65 -17 +CIRCLE Normal -62 -14 -66 -18 +CIRCLE Normal 49 -63 47 -65 +CIRCLE Normal 50 -62 46 -66 +CIRCLE Normal 49 33 47 31 +CIRCLE Normal 50 34 46 30 +TEXT 0 120 Center 2 ADI +TEXT 69 -64 Bottom 1 RF1 +TEXT 68 32 Bottom 1 RF2 +WINDOW 0 16 -128 Left 2 +WINDOW 3 16 192 Left 2 +SYMATTR Value ADG919 +SYMATTR Prefix X +SYMATTR SpiceModel ADG.lib +SYMATTR Value2 ADG919 +SYMATTR Description Wideband 4GHz, 43dB Isolation at 1GHz, CMOS 1.65V to 2.75V, 2:1 Mux/SPDT +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 1 +PIN -96 80 NONE 8 +PINATTR PinName CTRL +PINATTR SpiceOrder 2 +PIN 0 176 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 3 +PIN -96 -16 NONE 8 +PINATTR PinName RFC +PINATTR SpiceOrder 4 +PIN 96 32 NONE 8 +PINATTR PinName RF2 +PINATTR SpiceOrder 5 +PIN 96 -64 NONE 8 +PINATTR PinName RF1 +PINATTR SpiceOrder 8 diff --git a/spice/copy/sym/Switches/ADGS1212.asy b/spice/copy/sym/Switches/ADGS1212.asy new file mode 100755 index 0000000..53ea0d5 --- /dev/null +++ b/spice/copy/sym/Switches/ADGS1212.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -19 -48 -96 -48 +LINE Normal 96 -48 19 -48 +LINE Normal 0 -16 0 16 2 +LINE Normal 15 -58 -13 -49 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 0 +LINE Normal -48 32 -16 16 +LINE Normal -48 16 -96 16 2 +LINE Normal 0 16 -16 16 2 +RECTANGLE Normal -96 -128 96 128 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +CIRCLE Normal 32 -16 -32 -80 2 +TEXT 0 50 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -73 16 Bottom 2 IN +WINDOW 0 64 -128 Bottom 2 +WINDOW 3 0 80 Center 2 +SYMATTR Value ADGS1212 +SYMATTR Prefix X +SYMATTR SpiceModel ADGS1212.sub +SYMATTR Value2 ADGS1212 +SYMATTR Description Quad SPST Switch, Low Qinj, Low Con, +/-15 V, +12 V, Mux Configurable \n\n SPI functionality is not modelled \n Only one channel is modelled +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -64 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 64 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -128 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADGS1412.asy b/spice/copy/sym/Switches/ADGS1412.asy new file mode 100755 index 0000000..b1e1ffa --- /dev/null +++ b/spice/copy/sym/Switches/ADGS1412.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +LINE Normal 13 -60 -16 -48 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 -51 84 Left 2 +SYMATTR Value ADGS1412 +SYMATTR Prefix X +SYMATTR SpiceModel ADGS1412.sub +SYMATTR Value2 ADGS1412 +SYMATTR Description 1.5 On Resistance, +/-15V, +12V, Quad SPST Switch, Mux Configurable\n\nSPI Function is not modelled +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADGS1414D.asy b/spice/copy/sym/Switches/ADGS1414D.asy new file mode 100755 index 0000000..b3f09e3 --- /dev/null +++ b/spice/copy/sym/Switches/ADGS1414D.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 1 83 Center 2 +SYMATTR Value ADGS1414D +SYMATTR Prefix X +SYMATTR SpiceModel ADGS1414D.sub +SYMATTR Value2 ADGS1414D +SYMATTR Description 1.5 Ω Typical On Resistance, ±15V, +12V, High Density Octal SPST Switch +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADGS1612.asy b/spice/copy/sym/Switches/ADGS1612.asy new file mode 100755 index 0000000..6c31671 --- /dev/null +++ b/spice/copy/sym/Switches/ADGS1612.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +LINE Normal 13 -60 -16 -48 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 -51 84 Left 2 +SYMATTR Value ADGS1612 +SYMATTR Prefix X +SYMATTR SpiceModel ADGS1612.sub +SYMATTR Value2 ADGS1612 +SYMATTR Description 1.0 On Resistance, +/-5V, +12V, 5V, 3.3 V, Quad SPST Switch, Mux Configurable\n\nSPI Function is not modelled +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADGS5412.asy b/spice/copy/sym/Switches/ADGS5412.asy new file mode 100755 index 0000000..2f57a68 --- /dev/null +++ b/spice/copy/sym/Switches/ADGS5412.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +LINE Normal 13 -60 -16 -48 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 1 84 Center 2 +SYMATTR Value ADGS5412 +SYMATTR Prefix X +SYMATTR SpiceModel ADGS5412.sub +SYMATTR Value2 ADGS5412 +SYMATTR Description 9.8 On Resistance, +/-20V, +36V, Quad SPST Switches, Mux Configurable\n\nSPI Function is not modelled. Only one channel is modeled +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/Switches/ADGS5414.asy b/spice/copy/sym/Switches/ADGS5414.asy new file mode 100755 index 0000000..f85eed0 --- /dev/null +++ b/spice/copy/sym/Switches/ADGS5414.asy @@ -0,0 +1,44 @@ +Version 4 +SymbolType CELL +LINE Normal 13 -56 -16 -48 +LINE Normal -48 32 -48 0 +LINE Normal -16 16 -48 32 +LINE Normal -48 0 -16 16 +LINE Normal 0 16 -16 16 2 +LINE Normal 0 -19 0 16 2 +LINE Normal -96 -48 -16 -48 +LINE Normal 96 -48 16 -48 +LINE Normal -96 16 -48 16 +RECTANGLE Normal 96 128 -96 -112 +CIRCLE Normal 29 -19 -29 -74 2 +CIRCLE Normal -13 -45 -19 -51 +CIRCLE Normal 19 -45 13 -51 +TEXT 2 56 Center 2 ADI +TEXT -80 -48 Bottom 2 S +TEXT 80 -48 Bottom 2 D +TEXT -75 16 Bottom 2 IN +WINDOW 0 64 -112 Bottom 2 +WINDOW 3 1 83 Center 2 +SYMATTR Value ADGS5414 +SYMATTR Prefix X +SYMATTR SpiceModel ADGS5414.sub +SYMATTR Value2 ADGS5414 +SYMATTR Description 13.5 On Resistance, ±20V/ +36V, Octal SPST Switch, Mux \n\n SPI functionality is not modeled \n Only one channel is modeled +PIN -96 16 NONE 8 +PINATTR PinName IN +PINATTR SpiceOrder 1 +PIN 96 -48 NONE 8 +PINATTR PinName D +PINATTR SpiceOrder 2 +PIN -96 -48 NONE 8 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN -48 128 BOTTOM 8 +PINATTR PinName Vss +PINATTR SpiceOrder 4 +PIN 48 128 BOTTOM 8 +PINATTR PinName GND +PINATTR SpiceOrder 5 +PIN 0 -112 TOP 8 +PINATTR PinName Vdd +PINATTR SpiceOrder 6 diff --git a/spice/copy/sym/TVSdiode.asy b/spice/copy/sym/TVSdiode.asy new file mode 100755 index 0000000..6b2e66c --- /dev/null +++ b/spice/copy/sym/TVSdiode.asy @@ -0,0 +1,24 @@ +Version 4 +SymbolType CELL +LINE Normal 0 32 -4 36 +LINE Normal 32 32 36 28 +LINE Normal 0 32 32 32 +LINE Normal 0 8 32 8 +LINE Normal 32 8 16 32 +LINE Normal 0 8 16 32 +LINE Normal 0 56 32 56 +LINE Normal 32 56 16 32 +LINE Normal 0 56 16 32 +LINE Normal 16 0 16 8 +LINE Normal 16 56 16 64 +WINDOW 0 24 -2 Left 2 +WINDOW 3 24 65 Left 2 +SYMATTR Value D +SYMATTR Prefix D +SYMATTR Description Zener Diode +PIN 16 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/bi.asy b/spice/copy/sym/bi.asy new file mode 100755 index 0000000..20f20ea --- /dev/null +++ b/spice/copy/sym/bi.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 0 56 4 44 +LINE Normal 0 56 -4 44 +LINE Normal -4 44 4 44 +LINE Normal 0 24 0 44 +LINE Normal 0 80 0 72 +LINE Normal 0 0 0 8 +CIRCLE Normal -32 8 32 72 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 80 Left 2 +SYMATTR Value I=F(...) +SYMATTR Prefix B +SYMATTR Description Arbitrary behavioral current source +PIN 0 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/bi2.asy b/spice/copy/sym/bi2.asy new file mode 100755 index 0000000..f151c5e --- /dev/null +++ b/spice/copy/sym/bi2.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 0 24 4 36 +LINE Normal 0 24 -4 36 +LINE Normal -4 36 4 36 +LINE Normal 0 36 0 56 +LINE Normal 0 80 0 72 +LINE Normal 0 0 0 8 +CIRCLE Normal -32 8 32 72 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 81 Left 2 +SYMATTR Value I=F(...) +SYMATTR Prefix B +SYMATTR Description Arbitrary behavioral current source +PIN 0 80 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 0 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/bv.asy b/spice/copy/sym/bv.asy new file mode 100755 index 0000000..c23d2de --- /dev/null +++ b/spice/copy/sym/bv.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +LINE Normal -8 36 8 36 +LINE Normal -8 76 8 76 +LINE Normal 0 28 0 44 +LINE Normal 0 96 0 88 +LINE Normal 0 16 0 24 +CIRCLE Normal -32 24 32 88 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value V=F(...) +SYMATTR Prefix B +SYMATTR Description Arbitrary behavioral voltage source +PIN 0 16 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/cap.asy b/spice/copy/sym/cap.asy new file mode 100755 index 0000000..55b1905 --- /dev/null +++ b/spice/copy/sym/cap.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +LINE Normal 16 36 16 64 +LINE Normal 16 28 16 0 +LINE Normal 0 28 32 28 +LINE Normal 0 36 32 36 +WINDOW 0 24 8 Left 2 +WINDOW 3 24 56 Left 2 +SYMATTR Value C +SYMATTR Prefix C +SYMATTR Description Capacitor +PIN 16 0 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/csw.asy b/spice/copy/sym/csw.asy new file mode 100755 index 0000000..fa6289e --- /dev/null +++ b/spice/copy/sym/csw.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +LINE Normal 0 80 0 56 +LINE Normal 0 0 0 20 +LINE Normal 0 20 20 44 +CIRCLE Normal -32 8 32 72 +CIRCLE Normal -4 60 4 52 +CIRCLE Normal 16 40 24 48 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 88 Left 2 +SYMATTR Value CSW +SYMATTR Prefix W +SYMATTR Description Current controlled switch +PIN 0 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/current.asy b/spice/copy/sym/current.asy new file mode 100755 index 0000000..527c632 --- /dev/null +++ b/spice/copy/sym/current.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 0 56 4 44 +LINE Normal 0 56 -4 44 +LINE Normal -4 44 4 44 +LINE Normal 0 24 0 44 +LINE Normal 0 80 0 72 +LINE Normal 0 0 0 8 +CIRCLE Normal -32 8 32 72 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 80 Left 2 +SYMATTR Value I +SYMATTR Prefix I +SYMATTR Description Current source, either DC, AC, PULSE, SINE, PWL, EXP, or SFFM +PIN 0 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/diode.asy b/spice/copy/sym/diode.asy new file mode 100755 index 0000000..4be813f --- /dev/null +++ b/spice/copy/sym/diode.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +LINE Normal 0 44 32 44 +LINE Normal 0 20 32 20 +LINE Normal 32 20 16 44 +LINE Normal 0 20 16 44 +LINE Normal 16 0 16 20 +LINE Normal 16 44 16 64 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 64 Left 2 +SYMATTR Value D +SYMATTR Prefix D +SYMATTR Description Diode +PIN 16 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/e.asy b/spice/copy/sym/e.asy new file mode 100755 index 0000000..b9a9549 --- /dev/null +++ b/spice/copy/sym/e.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -32 32 +LINE Normal -32 32 -24 36 +LINE Normal -48 80 -32 80 +LINE Normal -32 80 -24 76 +LINE Normal 0 16 0 24 +LINE Normal 0 96 0 88 +LINE Normal -48 72 -40 72 +LINE Normal -48 40 -40 40 +LINE Normal -44 36 -44 44 +LINE Normal -4 72 4 72 +LINE Normal -4 40 4 40 +LINE Normal 0 36 0 44 +CIRCLE Normal -32 24 32 88 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value E +SYMATTR Prefix E +SYMATTR Description Voltage dependent voltage source +PIN 0 16 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 +PIN -48 32 NONE 0 +PINATTR PinName P +PINATTR SpiceOrder 3 +PIN -48 80 NONE 0 +PINATTR PinName N +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/e2.asy b/spice/copy/sym/e2.asy new file mode 100755 index 0000000..dfa8358 --- /dev/null +++ b/spice/copy/sym/e2.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -32 32 +LINE Normal -32 32 -24 36 +LINE Normal -48 80 -32 80 +LINE Normal -32 80 -24 76 +LINE Normal 0 16 0 24 +LINE Normal 0 96 0 88 +LINE Normal -48 72 -40 72 +LINE Normal -44 76 -44 68 +LINE Normal -48 40 -40 40 +LINE Normal -4 72 4 72 +LINE Normal -4 40 4 40 +LINE Normal 0 36 0 44 +CIRCLE Normal -32 24 32 88 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value E +SYMATTR Prefix E +SYMATTR Description Voltage dependent voltage source +PIN 0 16 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 +PIN -48 80 NONE 0 +PINATTR PinName P +PINATTR SpiceOrder 3 +PIN -48 32 NONE 0 +PINATTR PinName N +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/f.asy b/spice/copy/sym/f.asy new file mode 100755 index 0000000..96ec7e4 --- /dev/null +++ b/spice/copy/sym/f.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 0 56 4 44 +LINE Normal 0 56 -4 44 +LINE Normal -4 44 4 44 +LINE Normal 0 24 0 44 +LINE Normal 0 80 0 72 +LINE Normal 0 0 0 8 +CIRCLE Normal -32 8 32 72 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 80 Left 2 +SYMATTR Value F +SYMATTR Prefix F +SYMATTR Description Linear current dependent current source +PIN 0 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/g.asy b/spice/copy/sym/g.asy new file mode 100755 index 0000000..520d185 --- /dev/null +++ b/spice/copy/sym/g.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -32 32 +LINE Normal -32 32 -24 36 +LINE Normal -48 80 -32 80 +LINE Normal -32 80 -24 76 +LINE Normal 0 16 0 24 +LINE Normal 0 96 0 88 +LINE Normal -48 72 -40 72 +LINE Normal -48 40 -40 40 +LINE Normal -44 36 -44 44 +LINE Normal 4 52 0 40 +LINE Normal -4 52 0 40 +LINE Normal -4 52 4 52 +LINE Normal 0 52 0 72 +CIRCLE Normal -32 24 32 88 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value G +SYMATTR Prefix G +SYMATTR Description Voltage dependent current source +PIN 0 96 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 16 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 +PIN -48 32 NONE 0 +PINATTR PinName NC+ +PINATTR SpiceOrder 3 +PIN -48 80 NONE 0 +PINATTR PinName NC- +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/g2.asy b/spice/copy/sym/g2.asy new file mode 100755 index 0000000..fcfa9c4 --- /dev/null +++ b/spice/copy/sym/g2.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -32 32 +LINE Normal -32 32 -24 36 +LINE Normal -48 80 -32 80 +LINE Normal -32 80 -24 76 +LINE Normal 0 16 0 24 +LINE Normal 0 96 0 88 +LINE Normal -48 72 -40 72 +LINE Normal -48 40 -40 40 +LINE Normal -44 76 -44 68 +LINE Normal 4 52 0 40 +LINE Normal -4 52 0 40 +LINE Normal -4 52 4 52 +LINE Normal 0 52 0 72 +CIRCLE Normal -32 24 32 88 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value G +SYMATTR Prefix G +SYMATTR Description Voltage dependent current source +PIN 0 96 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 16 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 +PIN -48 80 NONE 0 +PINATTR PinName NC+ +PINATTR SpiceOrder 3 +PIN -48 32 NONE 0 +PINATTR PinName NC- +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/h.asy b/spice/copy/sym/h.asy new file mode 100755 index 0000000..9b72f08 --- /dev/null +++ b/spice/copy/sym/h.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +LINE Normal -8 36 8 36 +LINE Normal -8 76 8 76 +LINE Normal 0 28 0 44 +LINE Normal 0 96 0 88 +LINE Normal 0 16 0 24 +CIRCLE Normal -32 24 32 88 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value H +SYMATTR Prefix H +SYMATTR Description Linear current dependent voltage source +PIN 0 16 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/ind.asy b/spice/copy/sym/ind.asy new file mode 100755 index 0000000..6a5567b --- /dev/null +++ b/spice/copy/sym/ind.asy @@ -0,0 +1,16 @@ +Version 4 +SymbolType CELL +ARC Normal 0 40 32 72 4 68 4 44 +ARC Normal 0 64 32 96 16 96 4 68 +ARC Normal 0 16 32 48 4 44 16 16 +WINDOW 0 36 40 Left 2 +WINDOW 3 36 80 Left 2 +SYMATTR Value L +SYMATTR Prefix L +SYMATTR Description Inductor +PIN 16 16 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 96 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/ind2.asy b/spice/copy/sym/ind2.asy new file mode 100755 index 0000000..920fe69 --- /dev/null +++ b/spice/copy/sym/ind2.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType CELL +CIRCLE Normal 4 80 12 88 +ARC Normal 0 40 32 72 4 68 4 44 +ARC Normal 0 64 32 96 16 96 4 68 +ARC Normal 0 16 32 48 4 44 16 16 +WINDOW 0 36 40 Left 2 +WINDOW 3 36 80 Left 2 +SYMATTR Value L +SYMATTR Prefix L +SYMATTR Description Inductor +PIN 16 16 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 96 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/load.asy b/spice/copy/sym/load.asy new file mode 100755 index 0000000..7ea0627 --- /dev/null +++ b/spice/copy/sym/load.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 0 48 40 8 +LINE Normal 40 8 28 12 +LINE Normal 40 8 36 20 +LINE Normal 8 8 8 56 +LINE Normal 8 56 24 56 +LINE Normal 24 56 24 8 +LINE Normal 24 8 8 8 +LINE Normal 16 0 16 8 +LINE Normal 16 56 16 64 +WINDOW 0 48 8 Left 2 +WINDOW 3 48 56 Left 2 +SYMATTR Value I +SYMATTR Prefix I +SYMATTR Description Current Source, either DC, AC, PULSE, SINE, PWL, EXP, or SFFM +PIN 16 0 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/load2.asy b/spice/copy/sym/load2.asy new file mode 100755 index 0000000..c466650 --- /dev/null +++ b/spice/copy/sym/load2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 36 4 32 16 +LINE Normal 36 4 24 8 +LINE Normal -32 72 36 4 +LINE Normal 0 56 4 48 +LINE Normal 0 56 -4 48 +LINE Normal -4 48 4 48 +LINE Normal 0 24 0 48 +LINE Normal 0 80 0 72 +LINE Normal 0 0 0 8 +CIRCLE Normal -32 8 32 72 +WINDOW 0 17 -16 Left 2 +WINDOW 3 25 84 Left 2 +SYMATTR Value I +SYMATTR Prefix I +SYMATTR Description Current Source, either DC, AC, PULSE, SINE, PWL, EXP, or SFFM +PIN 0 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/lpnp.asy b/spice/copy/sym/lpnp.asy new file mode 100755 index 0000000..a98c5a7 --- /dev/null +++ b/spice/copy/sym/lpnp.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal 16 64 44 76 +LINE Normal 44 76 36 84 +LINE Normal 16 64 36 84 +LINE Normal 40 80 64 96 +LINE Normal 16 80 16 16 +LINE Normal 16 32 64 0 +LINE Normal 16 48 0 48 +LINE Normal 52 48 64 48 +LINE Normal 16 48 36 48 +LINE Normal 36 40 36 56 +LINE Normal 52 40 52 56 +LINE Normal 52 40 36 48 +LINE Normal 52 56 36 48 +WINDOW 0 72 32 Left 2 +WINDOW 3 72 68 Left 2 +SYMATTR Value LPNP +SYMATTR Prefix QP +SYMATTR Description Bipolar Lateral PNP transistor. You would normally use this with your own .model statement. +PIN 64 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 +PIN 64 48 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/ltline.asy b/spice/copy/sym/ltline.asy new file mode 100755 index 0000000..a39cc8a --- /dev/null +++ b/spice/copy/sym/ltline.asy @@ -0,0 +1,34 @@ +Version 4 +SymbolType CELL +LINE Normal -48 16 48 16 +LINE Normal -36 12 36 12 +LINE Normal -36 -12 36 -12 +LINE Normal -48 -16 48 -16 +LINE Normal -48 16 -36 12 +LINE Normal -48 -16 -36 -12 +LINE Normal 48 16 36 12 +LINE Normal 48 -16 36 -12 +LINE Normal -40 0 -32 0 +LINE Normal -32 0 -24 8 +LINE Normal -24 8 -8 -8 +LINE Normal -8 -8 8 8 +LINE Normal 8 8 24 -8 +LINE Normal 24 -8 32 0 +LINE Normal 32 0 40 0 +WINDOW 0 0 -16 Bottom 2 +WINDOW 3 0 16 Top 2 +SYMATTR Value LTRA +SYMATTR Prefix O +SYMATTR Description Lossy Transmission Line. Note: You must supply the .model for this device +PIN -48 -16 NONE 0 +PINATTR PinName I1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 0 +PINATTR PinName R1 +PINATTR SpiceOrder 2 +PIN 48 -16 NONE 0 +PINATTR PinName I2 +PINATTR SpiceOrder 3 +PIN 48 16 NONE 0 +PINATTR PinName R2 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/mesfet.asy b/spice/copy/sym/mesfet.asy new file mode 100755 index 0000000..fccf8cd --- /dev/null +++ b/spice/copy/sym/mesfet.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 16 12 16 84 +LINE Normal 48 80 48 96 +LINE Normal 48 16 48 0 +LINE Normal 16 16 48 16 +LINE Normal 0 80 16 80 +LINE Normal 16 80 48 80 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 72 Left 2 +SYMATTR Value NMF +SYMATTR Prefix Z +SYMATTR Description GaAs MESFET transistor Note: You must supply the .model for this device +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/njf.asy b/spice/copy/sym/njf.asy new file mode 100755 index 0000000..425c0d5 --- /dev/null +++ b/spice/copy/sym/njf.asy @@ -0,0 +1,25 @@ +Version 4 +SymbolType CELL +LINE Normal 16 16 16 80 +LINE Normal 48 72 48 96 +LINE Normal 16 72 48 72 +LINE Normal 48 24 48 0 +LINE Normal 16 24 48 24 +LINE Normal 0 64 4 64 +LINE Normal 4 68 16 64 +LINE Normal 4 60 16 64 +LINE Normal 4 60 4 68 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 72 Left 2 +SYMATTR Value NJF +SYMATTR Prefix JN +SYMATTR Description N-Channel JFET +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 64 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/nmos.asy b/spice/copy/sym/nmos.asy new file mode 100755 index 0000000..7f54bb2 --- /dev/null +++ b/spice/copy/sym/nmos.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 72 Left 2 +SYMATTR Value NMOS +SYMATTR Prefix MN +SYMATTR Description N-Channel MOSFET transistor +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/nmos4.asy b/spice/copy/sym/nmos4.asy new file mode 100755 index 0000000..c87983d --- /dev/null +++ b/spice/copy/sym/nmos4.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal 48 80 48 96 +LINE Normal 16 80 48 80 +LINE Normal 40 48 48 48 +LINE Normal 16 48 40 44 +LINE Normal 16 48 40 52 +LINE Normal 40 44 40 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 72 Left 2 +SYMATTR Value NMOS +SYMATTR Prefix MN +SYMATTR Description N-Channel MOSFET transistor with explicit substrate connection(used for monolithic MOSFETS) +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN 48 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/npn.asy b/spice/copy/sym/npn.asy new file mode 100755 index 0000000..63560f8 --- /dev/null +++ b/spice/copy/sym/npn.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 44 76 36 84 +LINE Normal 64 96 44 76 +LINE Normal 64 96 36 84 +LINE Normal 40 80 16 64 +LINE Normal 16 80 16 16 +LINE Normal 16 32 64 0 +LINE Normal 16 48 0 48 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 68 Left 2 +SYMATTR Value NPN +SYMATTR Prefix QN +SYMATTR Description Bipolar NPN transistor +PIN 64 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/npn2.asy b/spice/copy/sym/npn2.asy new file mode 100755 index 0000000..f6920f8 --- /dev/null +++ b/spice/copy/sym/npn2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 44 76 36 84 +LINE Normal 64 96 44 76 +LINE Normal 64 96 36 84 +LINE Normal 40 80 16 64 +LINE Normal 16 32 64 0 +LINE Normal 12 48 0 48 +RECTANGLE Normal 16 72 12 24 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 68 Left 2 +SYMATTR Value NPN +SYMATTR Prefix QN +SYMATTR Description Bipolar NPN transistor +PIN 64 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/npn3.asy b/spice/copy/sym/npn3.asy new file mode 100755 index 0000000..436303b --- /dev/null +++ b/spice/copy/sym/npn3.asy @@ -0,0 +1,26 @@ +Version 4 +SymbolType CELL +LINE Normal 44 76 36 84 +LINE Normal 64 96 44 76 +LINE Normal 64 96 36 84 +LINE Normal 40 80 20 64 +LINE Normal 20 72 20 24 +LINE Normal 12 72 12 24 +LINE Normal 20 72 12 72 +LINE Normal 20 24 12 24 +LINE Normal 20 32 64 0 +LINE Normal 12 48 0 48 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 68 Left 2 +SYMATTR Value NPN +SYMATTR Prefix QN +SYMATTR Description Bipolar NPN transistor +PIN 64 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/npn4.asy b/spice/copy/sym/npn4.asy new file mode 100755 index 0000000..b16d576 --- /dev/null +++ b/spice/copy/sym/npn4.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal 16 48 0 48 +LINE Normal 16 32 64 0 +LINE Normal 16 80 16 16 +LINE Normal 40 80 16 64 +LINE Normal 64 96 36 84 +LINE Normal 64 96 44 76 +LINE Normal 44 76 36 84 +LINE Normal 40 16 48 28 +LINE Normal 64 48 56 40 +LINE Normal 40 32 56 20 +LINE Normal 48 44 64 32 +LINE Normal 48 44 48 28 +LINE Normal 64 32 48 28 +WINDOW 0 72 32 Left 2 +WINDOW 3 72 68 Left 2 +SYMATTR Value NPN +SYMATTR Prefix QN +SYMATTR Description Bipolar NPN transistor with substrate node. You would normally use this with your own .model statement. +PIN 64 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 +PIN 64 48 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/pjf.asy b/spice/copy/sym/pjf.asy new file mode 100755 index 0000000..688625f --- /dev/null +++ b/spice/copy/sym/pjf.asy @@ -0,0 +1,25 @@ +Version 4 +SymbolType CELL +LINE Normal 16 16 16 80 +LINE Normal 48 72 48 96 +LINE Normal 16 72 48 72 +LINE Normal 48 24 48 0 +LINE Normal 16 24 48 24 +LINE Normal 12 64 16 64 +LINE Normal 12 68 0 64 +LINE Normal 12 60 0 64 +LINE Normal 12 60 12 68 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 72 Left 2 +SYMATTR Value PJF +SYMATTR Prefix JP +SYMATTR Description P-Channel JFET transistor +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 64 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/pmos.asy b/spice/copy/sym/pmos.asy new file mode 100755 index 0000000..55bdad5 --- /dev/null +++ b/spice/copy/sym/pmos.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType CELL +LINE Normal 48 48 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 72 Left 2 +SYMATTR Value PMOS +SYMATTR Prefix MP +SYMATTR Description P-Channel MOSFET transistor +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/pmos4.asy b/spice/copy/sym/pmos4.asy new file mode 100755 index 0000000..01c35db --- /dev/null +++ b/spice/copy/sym/pmos4.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal 48 80 48 96 +LINE Normal 16 80 48 80 +LINE Normal 16 48 24 48 +LINE Normal 48 48 24 44 +LINE Normal 48 48 24 52 +LINE Normal 24 44 24 52 +LINE Normal 16 8 16 24 +LINE Normal 16 40 16 56 +LINE Normal 16 72 16 88 +LINE Normal 0 80 8 80 +LINE Normal 8 16 8 80 +LINE Normal 48 16 16 16 +LINE Normal 48 0 48 16 +WINDOW 0 56 32 Left 2 +WINDOW 3 56 72 Left 2 +SYMATTR Value PMOS +SYMATTR Prefix MP +SYMATTR Description P-Channel MOSFET transistor with explicit substrate connection(used for monolithic MOSFETS) +PIN 48 0 NONE 0 +PINATTR PinName D +PINATTR SpiceOrder 1 +PIN 0 80 NONE 0 +PINATTR PinName G +PINATTR SpiceOrder 2 +PIN 48 96 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 3 +PIN 48 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/pnp.asy b/spice/copy/sym/pnp.asy new file mode 100755 index 0000000..2d1777e --- /dev/null +++ b/spice/copy/sym/pnp.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 16 64 44 76 +LINE Normal 44 76 36 84 +LINE Normal 16 64 36 84 +LINE Normal 40 80 64 96 +LINE Normal 16 80 16 16 +LINE Normal 16 32 64 0 +LINE Normal 16 48 0 48 +WINDOW 0 84 32 Left 2 +WINDOW 3 84 68 Left 2 +SYMATTR Value PNP +SYMATTR Prefix QP +SYMATTR Description Bipolar PNP transistor +PIN 64 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/pnp2.asy b/spice/copy/sym/pnp2.asy new file mode 100755 index 0000000..f5cdd28 --- /dev/null +++ b/spice/copy/sym/pnp2.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 16 64 44 76 +LINE Normal 44 76 36 84 +LINE Normal 16 64 36 84 +LINE Normal 40 80 64 96 +LINE Normal 16 32 64 0 +LINE Normal 12 48 0 48 +RECTANGLE Normal 16 72 12 24 +WINDOW 0 84 32 Left 2 +WINDOW 3 84 68 Left 2 +SYMATTR Value PNP +SYMATTR Prefix QP +SYMATTR Description Bipolar PNP transistor +PIN 64 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 diff --git a/spice/copy/sym/pnp4.asy b/spice/copy/sym/pnp4.asy new file mode 100755 index 0000000..2bf88ea --- /dev/null +++ b/spice/copy/sym/pnp4.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal 16 64 44 76 +LINE Normal 44 76 36 84 +LINE Normal 16 64 36 84 +LINE Normal 40 80 64 96 +LINE Normal 16 80 16 16 +LINE Normal 16 32 64 0 +LINE Normal 16 48 0 48 +LINE Normal 40 16 48 28 +LINE Normal 64 48 56 40 +LINE Normal 40 32 56 20 +LINE Normal 48 44 64 32 +LINE Normal 40 32 56 40 +LINE Normal 56 20 56 40 +WINDOW 0 72 32 Left 2 +WINDOW 3 72 68 Left 2 +SYMATTR Value PNP +SYMATTR Prefix QP +SYMATTR Description Bipolar PNP transistor with substrate node. You would normally use this with your own .model statement. +PIN 64 0 NONE 0 +PINATTR PinName C +PINATTR SpiceOrder 1 +PIN 0 48 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN 64 96 NONE 0 +PINATTR PinName E +PINATTR SpiceOrder 3 +PIN 64 48 NONE 0 +PINATTR PinName S +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/polcap.asy b/spice/copy/sym/polcap.asy new file mode 100755 index 0000000..7bb33bb --- /dev/null +++ b/spice/copy/sym/polcap.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +LINE Normal 16 36 16 64 +LINE Normal 16 0 16 28 +LINE Normal 8 12 8 20 +LINE Normal 4 16 12 16 +LINE Normal 0 28 32 28 +ARC Normal -16 36 48 100 32 40 0 40 +WINDOW 0 24 8 Left 2 +WINDOW 3 24 57 Left 2 +SYMATTR Value C +SYMATTR Prefix C +SYMATTR Description Polarized Capacitor +PIN 16 0 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/res.asy b/spice/copy/sym/res.asy new file mode 100755 index 0000000..d351308 --- /dev/null +++ b/spice/copy/sym/res.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 16 88 16 96 +LINE Normal 0 80 16 88 +LINE Normal 32 64 0 80 +LINE Normal 0 48 32 64 +LINE Normal 32 32 0 48 +LINE Normal 16 16 16 24 +LINE Normal 16 24 32 32 +WINDOW 0 36 40 Left 2 +WINDOW 3 36 76 Left 2 +SYMATTR Value R +SYMATTR Prefix R +SYMATTR Description A resistor +PIN 16 16 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 96 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/res2.asy b/spice/copy/sym/res2.asy new file mode 100755 index 0000000..8d069f9 --- /dev/null +++ b/spice/copy/sym/res2.asy @@ -0,0 +1,22 @@ +Version 4 +SymbolType CELL +LINE Normal 16 0 32 4 +LINE Normal 0 12 32 4 +LINE Normal 0 12 32 20 +LINE Normal 0 28 32 20 +LINE Normal 0 28 32 36 +LINE Normal 0 44 32 36 +LINE Normal 0 44 32 52 +LINE Normal 0 60 32 52 +LINE Normal 0 60 16 64 +WINDOW 0 36 16 Left 2 +WINDOW 3 36 56 Left 2 +SYMATTR Value R +SYMATTR Prefix R +SYMATTR Description A resistor +PIN 16 0 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/schottky.asy b/spice/copy/sym/schottky.asy new file mode 100755 index 0000000..97744e0 --- /dev/null +++ b/spice/copy/sym/schottky.asy @@ -0,0 +1,23 @@ +Version 4 +SymbolType CELL +LINE Normal 0 36 4 36 +LINE Normal 0 44 0 36 +LINE Normal 0 44 32 44 +LINE Normal 32 44 32 52 +LINE Normal 32 52 28 52 +LINE Normal 0 20 32 20 +LINE Normal 32 20 16 44 +LINE Normal 0 20 16 44 +LINE Normal 16 0 16 20 +LINE Normal 16 44 16 64 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 64 Left 2 +SYMATTR Value D +SYMATTR Prefix D +SYMATTR Description Schottky diode +PIN 16 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/sw.asy b/spice/copy/sym/sw.asy new file mode 100755 index 0000000..56d6ba0 --- /dev/null +++ b/spice/copy/sym/sw.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType CELL +LINE Normal -48 32 -32 32 +LINE Normal -32 32 -24 36 +LINE Normal -48 80 -32 80 +LINE Normal -32 80 -24 76 +LINE Normal 0 96 0 72 +LINE Normal 0 16 0 36 +LINE Normal 0 36 20 60 +LINE Normal -48 72 -40 72 +LINE Normal -44 76 -44 68 +LINE Normal -48 40 -40 40 +CIRCLE Normal -32 24 32 88 +CIRCLE Normal -4 76 4 68 +CIRCLE Normal 16 56 24 64 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value SW +SYMATTR Prefix S +SYMATTR Description Voltage controlled switch +PIN 0 16 NONE 0 +PINATTR PinName A +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName B +PINATTR SpiceOrder 2 +PIN -48 80 NONE 0 +PINATTR PinName NC+ +PINATTR SpiceOrder 3 +PIN -48 32 NONE 0 +PINATTR PinName NC- +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/tline.asy b/spice/copy/sym/tline.asy new file mode 100755 index 0000000..0754ceb --- /dev/null +++ b/spice/copy/sym/tline.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType CELL +LINE Normal -48 16 48 16 +LINE Normal -32 8 32 8 +LINE Normal -32 -8 32 -8 +LINE Normal -48 -16 48 -16 +LINE Normal -48 16 -32 8 +LINE Normal -48 -16 -32 -8 +LINE Normal 48 16 32 8 +LINE Normal 48 -16 32 -8 +WINDOW 0 0 -16 Bottom 2 +WINDOW 3 0 16 Top 2 +SYMATTR Value Td=50n Z0=50 +SYMATTR Prefix T +SYMATTR Description Ideal Lossless Transmission Line +PIN -48 -16 NONE 0 +PINATTR PinName I1 +PINATTR SpiceOrder 1 +PIN -48 16 NONE 0 +PINATTR PinName R1 +PINATTR SpiceOrder 2 +PIN 48 -16 NONE 0 +PINATTR PinName I2 +PINATTR SpiceOrder 3 +PIN 48 16 NONE 0 +PINATTR PinName R2 +PINATTR SpiceOrder 4 diff --git a/spice/copy/sym/varactor.asy b/spice/copy/sym/varactor.asy new file mode 100755 index 0000000..2cb85f7 --- /dev/null +++ b/spice/copy/sym/varactor.asy @@ -0,0 +1,20 @@ +Version 4 +SymbolType CELL +LINE Normal 0 36 32 36 +LINE Normal 0 44 32 44 +LINE Normal 0 16 32 16 +LINE Normal 32 16 16 36 +LINE Normal 0 16 16 36 +LINE Normal 16 0 16 16 +LINE Normal 16 44 16 64 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 64 Left 2 +SYMATTR Value D +SYMATTR Prefix D +SYMATTR Description Diode +PIN 16 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/voltage.asy b/spice/copy/sym/voltage.asy new file mode 100755 index 0000000..be43217 --- /dev/null +++ b/spice/copy/sym/voltage.asy @@ -0,0 +1,19 @@ +Version 4 +SymbolType CELL +LINE Normal -8 36 8 36 +LINE Normal -8 76 8 76 +LINE Normal 0 28 0 44 +LINE Normal 0 96 0 88 +LINE Normal 0 16 0 24 +CIRCLE Normal -32 24 32 88 +WINDOW 0 24 16 Left 2 +WINDOW 3 24 96 Left 2 +SYMATTR Value V +SYMATTR Prefix V +SYMATTR Description Voltage Source, either DC, AC, PULSE, SINE, PWL, EXP, or SFFM +PIN 0 16 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 0 96 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/copy/sym/zener.asy b/spice/copy/sym/zener.asy new file mode 100755 index 0000000..858b2f1 --- /dev/null +++ b/spice/copy/sym/zener.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType CELL +LINE Normal 0 44 -4 48 +LINE Normal 32 44 36 40 +LINE Normal 0 44 32 44 +LINE Normal 0 20 32 20 +LINE Normal 32 20 16 44 +LINE Normal 0 20 16 44 +LINE Normal 16 0 16 20 +LINE Normal 16 44 16 64 +WINDOW 0 24 0 Left 2 +WINDOW 3 24 64 Left 2 +SYMATTR Value D +SYMATTR Prefix D +SYMATTR Description Zener Diode +PIN 16 0 NONE 0 +PINATTR PinName + +PINATTR SpiceOrder 1 +PIN 16 64 NONE 0 +PINATTR PinName - +PINATTR SpiceOrder 2 diff --git a/spice/test/AD8038.sub b/spice/test/AD8038.sub new file mode 100755 index 0000000..7f4600b --- /dev/null +++ b/spice/test/AD8038.sub @@ -0,0 +1,264 @@ +*AD8038 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.2.1 Jun 2015-ZZ +*Copyright 2015 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents, +* Shut Down pin functionality where applicable, +* Single supply & offset supply functionality. +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | PD +* | | | | | | +.Subckt AD8038 100 101 102 103 104 106 +* +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.2e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 0.8e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 500e-6 +IbiasP 110 2 dc 0.4e-6 +IbiasN 110 9 dc 0.4e-6 +RinCMP 110 2 Rideal 20e6 +RinCMN 9 110 Rideal 20e6 +CinCMP 110 2 1e-12 +CinCMN 9 110 1e-12 +IOS 9 2 0.025e-6 +RinDiff 9 2 Rideal 2e3 +CinDiff 9 2 0.1e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 1.46 +VinN 42 112 dc 1.46 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -1e-10 +Lcmrr 11 12 1e-12 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 4.5 +VPD1 81 0 dc 2 +RPD 111 106 Rideal 1e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 48 Hz*** +g210 210 110 200 110 3.8149e-6 +R210 210 110 Rideal 3.32e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.839 +VoutN 64 66 dc 5.839 +e60 65 110 111 110 1.05 +e61 66 110 112 110 1.05 +* +* +***Pole at 800MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 0.1989e-12 +* +***Pole at 900MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.1768e-12 +* +***Pole at 1200MHz*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +C240 240 110 0.1326e-12 +* +***Zero at 1800MHz*** +g245 245 110 240 110 0.001 +R245 245 246 Rideal 1000 +L245 246 110 0.0884e-6 +* +***Buffer*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +* +***Peak: f=160MHz, Zeta=0.7, Gain=1.2dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 7.105e-9 +C290 291 292 139.26e-12 +R291 292 110 Rideal 67.498 +e295 295 110 292 110 1.1482 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 33 +Lout 303 310 4.6e-9 +Cout 310 110 1e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 15.336 +VIoutN 304 306 dc 19.336 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 1.685 +VoutN1 74 112 dc 1.685 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=2.005,Voff=1.995,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=111.881) +.model DzSlewN D(BV=111.881) +.model DVnoisy D(IS=2.29e-15 KF=2.13e-15) +.model DINnoisy D(IS=1.03e-17 KF=1.07e-14) +.model DIPnoisy D(IS=1.03e-17 KF=1.07e-14) +.model Rideal res(T_ABS=-273) +* +.ends diff --git a/spice/test/ADA4891.sub b/spice/test/ADA4891.sub new file mode 100755 index 0000000..564e8ff --- /dev/null +++ b/spice/test/ADA4891.sub @@ -0,0 +1,265 @@ +*ADA4891 Macro-model +*Function:Amplifier +* +*Revision History: +*Rev.2.1 Oct 2016-JL +*Copyright 2016 by Analog Devices +* +*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license +*for License Statement. Use of this model indicates your acceptance +*of the terms and provisions in the License Staement. +* +*Tested on MultSIm, SiMetrix(NGSpice), PSpice +* +*Not modeled: Distortion, PSRR, Overload Recovery, +* Shutdown Turn On/Turn Off time +* +*Parameters modeled include: +* Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range, +* Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp, +* Capacitive load drive, Quiescent and dynamic supply currents. +* +* +* +*Node Assignments +* Non-Inverting Input +* | Inverting Input +* | | Positive supply +* | | | Negative supply +* | | | | Output +* | | | | | +* | | | | | +.Subckt ADA4891 100 101 102 103 104 +* +***Power Supplies*** +Rz1 102 1020 Rideal 1e-6 +Rz2 103 1030 Rideal 1e-6 +Ibias 1020 1030 dc 0.01e-3 +DzPS 98 1020 diode +Iquies 1020 98 dc 4.39e-3 +S1 98 1030 106 113 Switch +R1 1020 99 Rideal 1e7 +R2 99 1030 Rideal 1e7 +e1 111 110 1020 110 1 +e2 110 112 110 1030 1 +e3 110 0 99 0 1 +* +* +***Inputs*** +S2 1 100 106 113 Switch +S3 9 101 106 113 Switch +VOS 1 2 dc 2.5e-3 +IbiasP 110 2 dc 2e-12 +IbiasN 110 9 dc 2e-12 +RinCMP 110 2 Rideal 5000e6 +RinCMN 9 110 Rideal 5000e6 +CinCMP 110 2 2.2e-12 +CinCMN 9 110 2.2e-12 +IOS 9 2 1e-15 +RinDiff 9 2 Rideal 10000e3 +CinDiff 9 2 0.8e-12 +* +* +***Non-Inverting Input with Clamp*** +g1 3 110 110 2 0.001 +RInP 3 110 Rideal 1e3 +RX1 40 3 Rideal 0.001 +DInP 40 41 diode +DInN 42 40 diode +VinP 111 41 dc 1.26 +VinN 42 112 dc 0.16 +* +* +***Vnoise*** +hVn 6 5 Vmeas1 707.10678 +Vmeas1 20 110 DC 0 +Vvn 21 110 dc 0.65 +Dvn 21 20 DVnoisy +hVn1 6 7 Vmeas2 707.10678 +Vmeas2 22 110 dc 0 +Vvn1 23 110 dc 0.65 +Dvn1 23 22 DVnoisy +* +* +***Inoise*** +FnIN 9 110 Vmeas3 0.7071068 +Vmeas3 51 110 dc 0 +VnIN 50 110 dc 0.65 +DnIN 50 51 DINnoisy +FnIN1 110 9 Vmeas4 0.7071068 +Vmeas4 53 110 dc 0 +VnIN1 52 110 dc 0.65 +DnIN1 52 53 DINnoisy +* +FnIP 2 110 Vmeas5 0.7071068 +Vmeas5 31 110 dc 0 +VnIP 30 110 dc 0.65 +DnIP 30 31 DIPnoisy +FnIP1 110 2 Vmeas6 0.7071068 +Vmeas6 33 110 dc 0 +VnIP1 32 110 dc 0.65 +DnIP1 32 33 DIPnoisy +* +* +***CMRR*** +RcmrrP 3 10 Rideal 1e12 +RcmrrN 10 9 Rideal 1e12 +g10 11 110 10 110 -8.437e-9 +Lcmrr 11 12 8e-3 +Rcmrr 12 110 Rideal 1e3 +e4 5 3 11 110 1 +* +* +***Power Down*** +VPD 111 80 dc 2 +VPD1 81 0 dc 1.5 +RPD 111 106 Rideal 1e6 +ePD 80 113 82 0 1 +RDP1 82 0 Rideal 1e3 +CPD 82 0 1e-10 +S5 81 82 83 113 Switch +CDP1 83 0 1e-12 +RPD2 106 83 1e6 +* +* +***Feedback Pin*** +*RF 105 104 Rideal 0.001 +* +* +***VFB Stage*** +g200 200 110 7 9 1 +R200 200 110 Rideal 250 +DzSlewP 201 200 DzSlewP +DzSlewN 201 110 DzSlewN +* +* +***Dominant Pole at 8.88 Hz*** +g210 210 110 200 110 3.378e-6 +R210 210 110 Rideal 17.92e6 +C210 210 110 1e-012 +* +* +***Output Voltage Clamp-1*** +RX2 60 210 Rideal 0.001 +DzVoutP 61 60 DzVoutP +DzVoutN 60 62 DzVoutN +DVoutP 61 63 diode +DVoutN 64 62 diode +VoutP 65 63 dc 5.121 +VoutN 64 66 dc 5.095 +e60 65 110 111 110 1.27 +e61 66 110 112 110 1.27 +* +* +***Pole at 500MHz*** +g220 220 110 210 110 0.001 +R220 220 110 Rideal 1000 +C220 220 110 0.3183e-12 +* +***Pole at 800MHz*** +g230 230 110 220 110 0.001 +R230 230 110 Rideal 1000 +C230 230 110 0.1989e-12 +* +***Pole at 1200MHz*** +g240 240 110 230 110 0.001 +R240 240 110 Rideal 1000 +C240 240 110 0.1326e-12 +* +***Pole at 1500MHz*** +g245 245 110 240 110 0.001 +R245 245 110 Rideal 1000 +C245 245 110 0.1061e-12 +* +***Pole at 1700MHz*** +g250 250 110 245 110 0.001 +R250 250 110 Rideal 1000 +C250 250 110 0.0936e-12 +* +***Buffer*** +g255 255 110 250 110 0.001 +R255 255 110 Rideal 1000 +* +***Buffer*** +g260 260 110 255 110 0.001 +R260 260 110 Rideal 1000 +* +***Buffer*** +g265 265 110 260 110 0.001 +R265 265 110 Rideal 1000 +* +***Buffer*** +g270 270 110 265 110 0.001 +R270 270 110 Rideal 1000 +* +***Buffer*** +e280 280 110 270 110 1 +R280 280 285 Rideal 10 +* +***Peak: f=210MHz, Zeta=0.7, Gain=0.2dB*** +e290 290 110 285 110 1 +R290 290 292 Rideal 10 +L290 290 291 5.413e-9 +C290 291 292 106.103e-12 +R291 292 110 Rideal 429.314 +e295 295 110 292 110 1.0233 +* +* +***Output Stage*** +g300 300 110 295 110 0.001 +R300 300 110 Rideal 1000 +e301 301 110 300 110 1 +Rout 302 303 Rideal 36 +Lout 303 310 7e-9 +Cout 310 110 1.3e-12 +* +* +***Output Current Limit*** +H1 301 304 Vsense1 100 +Vsense1 301 302 dc 0 +VIoutP 305 304 dc 19.836 +VIoutN 304 306 dc 30.036 +DIoutP 307 305 diode +DIoutN 306 307 diode +Rx3 307 300 Rideal 0.001 +* +* +***Output Clamp-2*** +VoutP1 111 73 dc 0.705 +VoutN1 74 112 dc 0.695 +DVoutP1 75 73 diode +DVoutN1 74 75 diode +RX4 75 310 Rideal 0.001 +* +* +***Supply Currents*** +FIoVcc 314 110 Vmeas8 1 +Vmeas8 310 311 dc 0 +R314 110 314 Rideal 1e9 +DzOVcc 110 314 diode +DOVcc 102 314 diode +RX5 311 312 Rideal 0.001 +FIoVee 315 110 Vmeas9 1 +Vmeas9 312 313 dc 0 +R315 315 110 Rideal 1e9 +DzOVee 315 110 diode +DOVee 315 103 diode +* +* +***Output Switch*** +S4 104 313 106 113 Switch +* +* +*** Common Models *** +.model diode d(bv=100) +.model Switch vswitch(Von=1.505,Voff=1.495,ron=0.001,roff=1e6) +.model DzVoutP D(BV=4.3) +.model DzVoutN D(BV=4.3) +.model DzSlewP D(BV=50.802) +.model DzSlewN D(BV=62.643) +.model DVnoisy D(IS=2.99e-15 KF=1.02e-14) +.model DINnoisy D(IS=3.81e-19 KF=0.00e0) +.model DIPnoisy D(IS=3.81e-19 KF=0.00e0) +.model Rideal res(T_ABS=-273) +* +.ends ADA4891 diff --git a/spice/test/LMH5401.lib b/spice/test/LMH5401.lib new file mode 100755 index 0000000..b5bd228 --- /dev/null +++ b/spice/test/LMH5401.lib @@ -0,0 +1,449 @@ +* LMH5401 +***************************************************************************** +* (C) Copyright 2012 Texas Instruments Incorporated. All rights reserved. +***************************************************************************** +** This model is designed as an aid for customers of Texas Instruments. +** TI and its licensors and suppliers make no warranties, either expressed +** or implied, with respect to this model, including the warranties of +** merchantability or fitness for a particular purpose. The model is +** provided solely on an "as is" basis. The entire risk as to its quality +** and performance is with the customer. +***************************************************************************** +* +** Released by: WEBENCH(R) Design Center, Texas Instruments Inc. +* Part: LMH5401 +* Date: 10/20/2013 +* Model Type: All In One +* Simulator: TINA9 +* Simulator Version: 9.3.50.40 +* EVM Order Number: N/A +* EVM Users Guide: N/A +* Datasheet: SBOS710 - October 2014 +* +* Model Version: 1.2 +* +***************************************************************************** +* +* Updates: +* +* Version 1.0 : Release to Web +* Version 1.1 : Add internal input resistance +* Version 1.2 : Rev CM output connections. Add current noise +* +***************************************************************************** +* Notes: +* The model meets the following specs for 5V operation, G = 4V/V: +* 1. Turn-on and turn-off time delay +* 2. Slew Rate +* 3. CMRR vs frequency +* 4. Input and output common-mode range +* 5. Input voltage noise +* 6. Output voltage swing and output current +* 7. Quiescent current for active and power-down modes +* 8. Output common-mode bandwidth, gain and offset +* 9. HD2, HD3 vs frequency +* 10 HD2, HD3 vs. VICM and VOCM +* Note: +* The model HD2 & HD3 are 4dB-8dB better than the actual device for f < 50MHz +* The model may not conform to published specs for 3.3V operation +***************************************************************************** +* +*$ +.SUBCKT LMH5401 OUTP OUTN FBP FBN INP INN CM PD VCC VEE GND +X_U17 U3_OUTP U3_OUTN LIMITER_INP LIMITER_INN VMID VCC VEE IOUTP IOUTN ++ LIMITER +G_G2 VMID VEE IOUTN VMID 1 +R_R20 OUTPINT OUTP 10 +E_E8 OUT 0 OUTPINT OUTNINT 1 +X_U30 GBW_INP LIM_INP VCC VEE VMID IN_LIM +G_G10 DIST_OUTN DIST_OUTP N1047668 N1047660 0.13 +X_S2 SHDN VMID N17901 N15575 DEV_SCH_S2 +E_E6 N15575 CM_OUT U2_OUTP U2_OUTN 1 +G_G11 DIST_OUTN DIST_OUTP N1056358 N1055868 0.1 +X_U16 U2_OUTP U2_OUTN LIMITER_INP LIMITER_INN VMID VCC VEE IOUTP IOUTN ++ LIMITER +X_U25 CM_OUT VMID N65800 CMCALC SHDN VMID CM_CL_GAIN +X_H1 N17901 OUTPINT IOUTP VMID DEV_SCH_H1 +X_U18 N459295 LIM_INP vnse +R_R29 0 N1047728 2 +G_G8 DIST_OUTN DIST_OUTP N1056062 N1056052 1 +E_E9 N72619 VMID CMINT VMID 1 +X_U22 LIMITER_INN VMID N837077 VMID VCC VEE VMID VCN_OUT VC_OUT ++ SOFT_LIM_OUTPUT +X_U28 N109210 N109423 N1047668 N1047660 N1056358 N1055868 P2P P2N ERR_1 ++ ERR_2 ERR_3 VMID ERR +R_R12 FBP OUTPINT 25 +R_R30 0 N1047706 2 +R_R16 N109210 N109423 1k +C_C15 P2N P2P 15p +C_C16 VMID N436166 400f +R45 VMID N436166 2300 +R_R41 N1047706 N1047728 4 +R_R27 N1056358 N1055958 1 +E_E1 VMID 0 VCC N00961 0.5 +V_V3 N891663 N436166 0.25mVdc +R_R31 0 N1056062 2 +*E_E3 CMCALC VMID OUTP N07972 0.5 +E_E3 CMCALC VMID OUTPINT N07972 0.5 +R_R33 CNTRL_OUT COMP_IN 1k +X_U21 LIMITER_INP VMID N826132 VMID VCC VEE VMID VCN_OUT VC_OUT ++ SOFT_LIM_OUTPUT +C_C10 N1047668 N1047728 125p +C_C18 N459295 N436166 100f +X_U24 CNTRL_OUT INP INN VCC VEE VMID PD GND CONTROL +R_R28 N1055868 N1055882 1 +R_R10 N72619 N65800 500 +C_C17 N459295 VMID 400f +R46 N459295 VMID 2300 +G_G1 VCC VMID IOUTP VMID 1 +R_R32 0 N1056052 2 TC=0,0 +E_E2 N00961 0 0 VEE 1 +C_C11 N1047660 N1047706 125p +X_U29 GBW_INN LIM_INN VCC VEE VMID IN_LIM +R_R15 VEE PD 200k +C_C9 N1055882 N1055958 8n +*X_U23 N891663 N459295 femt +X_U123 VMID N891663 femt +X_U223 N459295 VMID femt +E_E13 N837077 VMID DIST_OUTN N805589 1 +X_U12 GBW_OUTP GBW_OUTN GBW_INP GBW_INN SHDN VMID GBW_SLEW_FDA +X_U26 INN INP ERR_1 VCC VEE VMID CM1_MON +C_C12 N1056358 N1056062 40p +C_C8 N1047868 N1047716 4.5n +E_E12 N798182 VMID VMID CM_OUT 1 +V_VCN_OUT VCN_OUT VMID 0.01Vdc +R_R36 P2N P2P 2 +R_R19 DIST_OUTN DIST_OUTP 2 +E_E14 N805589 VMID VMID CM_OUT 1 +E_E7 CM_OUT N15690 U3_OUTP U3_OUTN 1 +C_C13 N1055868 N1056052 40p +C_C1 VMID CMINT 1f +R_R34 INN N436166 1 +R_R35 INP N459295 1 +V_VCMoff CM CMINT 27mVdc +X_H2 N18027 OUTNINT IOUTN VMID DEV_SCH_H2 +V_VC_OUT VC_OUT VMID 1.5Vdc +G_G7 DIST_OUTN DIST_OUTP N1047728 N1047706 1 +*E_E4 N07972 VMID VMID OUTN 1 +E_E4 N07972 VMID VMID OUTNINT 1 +R_R14 FBN OUTNINT 25 +G_G9 P2P P2N GBW_OUTP GBW_OUTN -1 +G_G4 DIST_OUTN DIST_OUTP N1055958 N1055882 1 +R_R18 VMID DIST_OUTP 1 +E_E11 N826132 VMID DIST_OUTP N798182 1 +C_C4 0 N1047716 9n +I_I2 N459295 VMID DC 65.7uAdc +R_R25 N1047668 N1047716 1 +C_C6 0 N1055958 16n +I_I1 N891663 VMID DC 66.3uAdc +R_R37 VMID P2P 1 +V_V1 N501608 VMID 0.5 +X_U27 OUTP OUTN ERR_2 ERR_3 VCC VEE VMID CM2_MON +G_G3 DIST_OUTN DIST_OUTP N1047716 N1047868 1 +X_S1 SHDN VMID VCC VEE DEV_SCH_S1 +X_U14 SHDN COMP_IN N501608 VMID COMPARATOR +C_C14 VMID COMP_IN 12p +C_C7 N1055882 0 16n +R_R26 N1047660 N1047868 1 +R_R1 VMID CMINT 119k +C_C2 VMID N65800 0.1p +C_C5 N1047868 0 9n +R_R44 N1056052 N1056062 4 +G_G5 DIST_OUTP DIST_OUTN P2P P2N -1 +R_R17 DIST_OUTN VMID 1 +X_S3 SHDN VMID N18027 N15690 DEV_SCH_S3 +R_R21 OUTNINT OUTN 10 +R_R38 P2N VMID 1 +E_E10 LIM_INN VMID N891663 VMID 1.0005 +.ENDS +*$ +* +.subckt DEV_SCH_S2 1 2 3 4 +S_S2 3 4 1 2 _S2 +RS_S2 1 2 1G +.MODEL _S2 VSWITCH Roff=1e6 Ron=1.0 Voff=0.2V Von=0.8V +.ends DEV_SCH_S2 +*$ +* +.subckt DEV_SCH_H1 1 2 3 4 +H_H1 3 4 VH_H1 1 +VH_H1 1 2 0V +.ends DEV_SCH_H1 +*$ +* +.subckt DEV_SCH_H2 1 2 3 4 +H_H2 3 4 VH_H2 -1 +VH_H2 1 2 0V +.ends DEV_SCH_H2 +*$ +* +.subckt DEV_SCH_S1 1 2 3 4 +S_S1 3 4 1 2 _S1 +RS_S1 1 2 1G +.MODEL _S1 VSWITCH Roff=1700 Ron=90 Voff=0.2V Von=0.8V +.ends DEV_SCH_S1 +*$ +* +.subckt DEV_SCH_S3 1 2 3 4 +S_S3 3 4 1 2 _S3 +RS_S3 1 2 1G +.MODEL _S3 VSWITCH Roff=1e6 Ron=1.0 Voff=0.2V Von=0.8V +.ends DEV_SCH_S3 +*$ +.SUBCKT VNSE 1 2 +.PARAM NLF = 9.5 +.PARAM FLW = 100 +.PARAM NVR = 1.3 +.PARAM GLF={PWR(FLW,0.25)*NLF/1164} +.PARAM RNV={1.184*PWR(NVR,2)} +.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16 +I1 0 7 10E-3 +I2 0 8 10E-3 +D1 7 0 DVN +D2 8 0 DVN +E1 3 6 7 8 {GLF} +R1 3 0 1E9 +R2 3 0 1E9 +R3 3 6 1E9 +E2 6 4 5 0 10 +R4 5 0 {RNV} +R5 5 0 {RNV} +R6 3 4 1E9 +R7 4 0 1E9 +E3 1 2 3 4 1 +C1 1 0 1E-15 +C2 2 0 1E-15 +C3 1 2 1E-15 +.ENDS + +*$ +.SUBCKT FEMT 1 2 +.PARAM NLFF = 2500 +.PARAM FLWF = 50e3 +.PARAM NVRF = 2900 +.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164} +.PARAM RNVF={1.184*PWR(NVRF,2)} +.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16 +I1 0 7 10E-3 +I2 0 8 10E-3 +D1 7 0 DVNF +D2 8 0 DVNF +E1 3 6 7 8 {GLFF} +R1 3 0 1E9 +R2 3 0 1E9 +R3 3 6 1E9 +E2 6 4 5 0 10 +R4 5 0 {RNVF} +R5 5 0 {RNVF} +R6 3 4 1E9 +R7 4 0 1E9 +G1 1 2 3 4 1E-6 +C1 1 0 1E-15 +C2 2 0 1E-15 +C3 1 2 1E-15 +.ENDS + +*$ +* +.SUBCKT IN_LIM OUT IN VCC VEE GNDF +.PARAM V1 = 1.2 +.PARAM V2 = 0.2 +EMAX NMAX GNDF VALUE = {V(VCC,GNDF) - V1} +EMIN NMIN GNDF VALUE = {V(VEE,GNDF) - V2} +EOUT OUT GNDF VALUE = {MAX(MIN(V(IN,GNDF),V(NMAX,GNDF)),V(NMIN,GNDF))} +.ENDS +*$ +* +.SUBCKT LIMITER OUTP OUTN INP INN GNDF VCC VEE VCP VCN +.PARAM VHRP0 = 1 +.PARAM VHRN0 = -1 +.PARAM GAIN = 0.5 +.PARAM ROUT = 100 +.PARAM V_ISC = 0.1 +.PARAM V_IOUT1 = 0.06 +.PARAM ROS = 5 +EZ1 NZ1 GNDF VALUE = {V(VCC,GNDF)} +EZ2 NZ2 GNDF VALUE = {V(VCC,GNDF)-VHRP0} +EHRK NHRK GNDF VALUE = {((V(VCC,GNDF)-VHRP0)/(V_ISC-V_IOUT1))-ROS} +EHRP VHRP GNDF VALUE = {MAX(MIN(VHRP0+(V(VCP,GNDF)-V_IOUT1)*V(NHRK,GNDF),V(VCC,GNDF)),VHRP0)} +EHRN VHRN GNDF VALUE = {MAX(MIN(VHRN0+(V(VCN,GNDF)+V_IOUT1)*V(NHRK,GNDF),VHRN0),V(VEE,GNDF))} +EUL NUL GNDF VALUE = {V(VCC,GNDF) - V(VHRP,GNDF)} +ELL NLL GNDF VALUE = {V(VEE,GNDF) - V(VHRN,GNDF)} +RVCP_TERM VCP GNDF 1k +RVCN_TERM VCN GNDF 1k +EOUT OUTP OUTN VALUE = {MIN(MAX(GAIN*V(INP,INN),V(NLL,GNDF)),V(NUL,GNDF))} +ROUT1+ OUTP GNDF {ROUT} +ROUT1- OUTN GNDF {ROUT} +.ENDS +*$ +* +.SUBCKT CM_CL_GAIN OUTP OUTN INP INN SHDN GNDF +.PARAM GAIN = 1e4 +E1 OUTP OUTN VALUE = {GAIN*V(INP,INN)*V(SHDN,GNDF)} +.ENDS +*$ +* +* +.SUBCKT SOFT_LIM_OUTPUT OUTP OUTN INP INN VCC VEE GNDF VCN VC1 +.PARAM NORDER = 5 +.PARAM GAIN = 1 +** VCN is the headroom to mimic the CLAW curve +** VC1 is the first threshold that begins limiting. It marks the point +** where distortion increases dramatically for increasing output swing +*EHR N_HR GNDF VALUE = {V(VCC,VCN)} +EVC1 N_VC1 GNDF VALUE = {V(VC1,GNDF)} +EHR N_OMAX GNDF VALUE = {V(VCC,VCN)} +EDV N_DV GNDF VALUE = {(2/(NORDER-2))*(V(N_OMAX,GNDF)/GAIN - V(VC1,GNDF))} +EIN N_IN GNDF VALUE = {V(INP,INN)} +EV1 N_V1 GNDF VALUE = {V(VC1,GNDF)} +EV2 N_V2 GNDF VALUE = {V(VC1,GNDF) + V(N_DV,GNDF)} +EV3 N_V3 GNDF VALUE = {V(VC1,GNDF) + 2*V(N_DV,GNDF)} +EV4 N_V4 GNDF VALUE = {V(VC1,GNDF) + 3*V(N_DV,GNDF)} +EV5 N_V5 GNDF VALUE = {V(VC1,GNDF) + 4*V(N_DV,GNDF)} +EG1 N_G1 GNDF VALUE = {GAIN} +EG2 N_G2 GNDF VALUE = {0.75*GAIN} +EG3 N_G3 GNDF VALUE = {0.50*GAIN} +EG4 N_G4 GNDF VALUE = {0.25*GAIN} +EG5 N_G5 GNDF VALUE = {0*GAIN} +EB1 N_B1 GNDF VALUE = {0} +EB2 N_B2 GNDF VALUE = {V(N_B1,GNDF) + 1*(GAIN/(NORDER-1)) ++ *(V(N_V5,GNDF) - NORDER*V(N_DV,GNDF) + 1*V(N_DV,GNDF))} +EB3 N_B3 GNDF VALUE = {V(N_B1,GNDF) + 2*(GAIN/(NORDER-1)) ++ *(V(N_V5,GNDF) - NORDER*V(N_DV,GNDF) + 1.5*V(N_DV,GNDF))} +EB4 N_B4 GNDF VALUE = {V(N_B1,GNDF) + 3*(GAIN/(NORDER-1)) ++ *(V(N_V5,GNDF) - NORDER*V(N_DV,GNDF) + 2*V(N_DV,GNDF))} +EB5 N_B5 GNDF VALUE = {V(N_B1,GNDF) + 4*(GAIN/(NORDER-1)) ++ *(V(N_V5,GNDF) - NORDER*V(N_DV,GNDF) + 2.5*V(N_DV,GNDF))} +E1U N_1U GNDF VALUE = {V(N_G1,GNDF)*V(N_IN,GNDF)} +E2U N_2U GNDF VALUE = {V(N_G2,GNDF)*V(N_IN,GNDF) + V(N_B2,GNDF)} +E3U N_3U GNDF VALUE = {V(N_G3,GNDF)*V(N_IN,GNDF) + V(N_B3,GNDF)} +E4U N_4U GNDF VALUE = {V(N_G4,GNDF)*V(N_IN,GNDF) + V(N_B4,GNDF)} +E5U N_5U GNDF VALUE = {V(N_G5,GNDF)*V(N_IN,GNDF) + V(N_B5,GNDF)} +E2L N_2L GNDF VALUE = {V(N_G2,GNDF)*V(N_IN,GNDF) - V(N_B2,GNDF)} +E3L N_3L GNDF VALUE = {V(N_G3,GNDF)*V(N_IN,GNDF) - V(N_B3,GNDF)} +E4L N_4L GNDF VALUE = {V(N_G4,GNDF)*V(N_IN,GNDF) - V(N_B4,GNDF)} +E5L N_5L GNDF VALUE = {V(N_G5,GNDF)*V(N_IN,GNDF) - V(N_B5,GNDF)} +EX1 N_X1 GNDF VALUE = {MIN(MAX(V(N_1U,GNDF),V(N_2L,GNDF)),V(N_2U,GNDF))} +EX2 N_X2 GNDF VALUE = {MIN(MAX(V(N_X1,GNDF),V(N_3L,GNDF)),V(N_3U,GNDF))} +EX3 N_X3 GNDF VALUE = {MIN(MAX(V(N_X2,GNDF),V(N_4L,GNDF)),V(N_4U,GNDF))} +EX4 OUTP OUTN VALUE = {MIN(MAX(V(N_X3,GNDF),V(N_5L,GNDF)),V(N_5U,GNDF))} +ROUTP OUTP GNDF 100 +ROUTN OUTN GNDF 100 +ROUTD OUTP OUTN 200 +.ENDS +*$ +** +.SUBCKT ERR OUT1P OUT1N OUT2P OUT2N OUT3P OUT3N INP INN IN1 IN2 IN3 GNDF +.PARAM a0 = 0 +.PARAM a1 = 1 +.PARAM a2 = {0.00115} +.PARAM a3 = {0.005} +.PARAM LL = -1000 +.PARAM UL = 1000 +Eid DIFF_IN 0 VALUE = {V(INP) - V(INN)} +EIN1 N1 0 VALUE = {V(IN1,GNDF)} +EIN2 N2 0 VALUE = {V(IN2,GNDF)} +EIN3 N3 0 VALUE = {V(IN3,GNDF)} +E1 OUT1P OUT1N VALUE = {MAX(MIN(a1*V(DIFF_IN),UL),LL)} +E2 OUT2P OUT2N VALUE = {MAX(MIN(a2*V(N1)*V(N2)*PWR(V(DIFF_IN),2),UL),LL)} +E3 OUT3P OUT3N VALUE = {MAX(MIN(a3*V(N1)*V(N3)*PWRS(V(DIFF_IN),3),UL),LL)} +RE1+ OUT1P 0 100 +RE1- 0 OUT1N 100 +RE1d OUT1P OUT1N 200 +RE2+ OUT2P 0 100 +RE2- 0 OUT2N 100 +RE2d OUT2P OUT2N 200 +RE3+ OUT3P 0 100 +RE3- 0 OUT3N 100 +RE3d OUT3P OUT3N 200 +.ENDS +*$ +** +.SUBCKT CONTROL OUT INP INN VCC VEE GNDF PD GND +.PARAM VS_MAX = 5.5 +.PARAM VIH = 0.5 +.PARAM VIL = 0.5 +.PARAM VIMID = 1.1 +**** +EVSTEST NVSTEST GNDF VALUE = {IF(V(VCC,VEE) > VS_MAX,0,1)} +EVICM NVICM GNDF VALUE = {0.5*(V(INP,GNDF)+V(INN,GNDF))} +EVICMMAXTEST NVICMMAXTEST GNDF VALUE = {IF(V(NVICM,GNDF) > V(VCC,GNDF)+VIH,0,1)} +EVICMMINTEST NVICMMINTEST GNDF VALUE = {IF(V(NVICM,GNDF) < V(VEE,GNDF)-VIL,0,1)} +* for this version, PD is inverted and ref’d to ground, not VEE * +EPD NPD GNDF VALUE = {1 - MAX(MIN(1000*(V(PD,GND)-VIMID),1),0)} +EOUT OUT GNDF VALUE = {V(NVSTEST,GNDF)*V(NVICMMAXTEST,GNDF) ++*V(NVICMMINTEST,GNDF)*V(NPD,GNDF)} +.ENDS +*$ +** +* +* +.SUBCKT GBW_SLEW_FDA OUTP OUTN INP INN SHDN GNDF +.PARAM Aol = 57 +.PARAM GBW = 14e9 +.PARAM SRP = 20e9 +.PARAM SRN = 20e9 +.PARAM IT = 0.001 +.PARAM PI = 3.141592 +.PARAM IP = {IT*MAX(1,SRP/SRN)} +.PARAM IN = {IT*MIN(-1,-SRN/SRP)} +.PARAM CC = {IT*MAX(1/SRP,1/SRN)} +.PARAM FP = {GBW/PWR(10,AOL/20)} +.PARAM RC = {1/(2*PI*CC*FP)} +.PARAM GC = {PWR(10,AOL/20)/RC} +* Loading the VO pin with an external resistor will change the AOL. +G1p GNDF OUTP VALUE = {MAX(MIN(GC*V(SHDN,GNDF)*V(INP,INN),IP),IN)} +G1n OUTN GNDF VALUE = {MAX(MIN(GC*V(SHDN,GNDF)*V(INP,INN),IP),IN)} +RG1p OUTP GNDF {0.5*RC} +Cg1dp OUTP GNDF {2*CC} +RG1n OUTN GNDF {0.5*RC} +Cg1dn OUTN GNDF {2*CC} +.ENDS +*$ +* +.SUBCKT CM1_MON IN1 IN2 OUT VCC VEE GNDF +.PARAM VOS = -0.5 +.PARAM VMH = 1400 +.PARAM VML = -1400 +.PARAM VDH = 0.55 +.PARAM VDL = -0.55 +EC NC GNDF VALUE = {0.5*(V(IN1,GNDF)+V(IN2,GNDF)) - VOS} +EBL NBL 0 VALUE = {-VML*(V(VEE,GNDF)- VDL)} +EBH NBH 0 VALUE = {-VMH*(V(VCC,GNDF)- VDH)} +EL1 NLL GNDF VALUE = {VML*V(NC,GNDF) + V(NBL)} +EL2 NLH GNDF VALUE = {VMH*V(NC,GNDF) + V(NBH)} +EO1 OUT GNDF VALUE = {MAX(MAX(V(NLL,GNDF),V(NLH,GNDF)),1)} +.ENDS +*$ +* +.SUBCKT CM2_MON IN1 IN2 OUT2 OUT3 VCC VEE GNDF +.PARAM VOS = 0 +.PARAM VM2H = 114.3 +.PARAM VM2L = -30.91 +.PARAM VD2H = 1.45 +.PARAM VD2L = -1.55 +.PARAM VM3H = 100 +.PARAM VM3L = -100 +.PARAM VD3 = 1.8 +EB2H NB2H 0 VALUE = {-VM2H*(V(VCC,GNDF)-VD2H)} +EB2L NB2L 0 VALUE = {-VM2L*(V(VEE,GNDF)-VD2L)} +EB3H NB3H 0 VALUE = {-VM3H*(V(VCC,GNDF)-VD3)} +EB3L NB3L 0 VALUE = {-VM3H*(V(VCC,GNDF)-VD3)} +EC NC GNDF VALUE = {0.5*(V(IN1,GNDF)+V(IN2,GNDF)) - VOS} +EH2 NH2 GNDF VALUE = {VM2H*V(NC,GNDF) + V(NB2H)} +EL2 NL2 GNDF VALUE = {VM2L*V(NC,GNDF) + V(NB2L)} +EH3 NH3 GNDF VALUE = {VM3H*V(NC,GNDF) + V(NB3H)} +EL3 NL3 GNDF VALUE = {VM3L*V(NC,GNDF) + V(NB3L)} +EO2 OUT2 GNDF VALUE = {MAX(MAX(V(NH2,GNDF),V(NL2,GNDF)),1)} +EO3 OUT3 GNDF VALUE = {MAX(MAX(V(NH3,GNDF),V(NL3,GNDF)),1)} +.ENDS +*$ +* +.SUBCKT COMPARATOR OUT IN REF GNDF +.PARAM VOUT_MAX = 1 +.PARAM VOUT_MIN = 0 +.PARAM GAIN = 1e4 +EOUT OUT GNDF VALUE = {MAX(MIN(GAIN*V(IN,REF),VOUT_MAX),VOUT_MIN)} +.ENDS +*$ + diff --git a/spice/test/OptiMOS2_100V.lib b/spice/test/OptiMOS2_100V.lib new file mode 100755 index 0000000..80fa374 --- /dev/null +++ b/spice/test/OptiMOS2_100V.lib @@ -0,0 +1,4546 @@ +***************************************************************** +* INFINEON Power Transistors * +* Level1/3 PSPICE Library for OptiMOS2 n-Channel Transistors * +* * +* This file also contains simplified models that are compatible * +* to standard Spice. * +* * +* Version 10122008 * +* * +***************************************************************** +* * +* The Simulation Model is subject to change without notice. In * +* addition, models can be a useful tool in evaluating device * +* performance, they cannot reflect the accurate device * +* performance under all conditions, nor are they intended to * +* replace bread boarding for final verification. Infineon * +* therefore does not assume any warranty or liability * +* whatsoever arising from their use. Infineon does not assume * +* any warranty or liability for the values and functions of the * +* Simulation Model. * +* The methods and results of the Simulation Model are to the * +* best of our knowledge * +* correct. However, the user is fully responsible to verify and * +* validate these results under the operating conditions and in * +* the environment of its application. Infineon will not bear * +* the responsibility arising out of or in connection with any * +* malfunction of the Simulation Models. * +* Models provided by Infineon are not warranted by Infineon as * +* completely and comprehensively representing all the * +* specifications and operating characteristics of the * +* semiconductor products to which these models relate. The * +* models describe the characteristics of typical devices. In * +* all cases, the current data sheet information for a given * +* device is the conclusive design guideline and the only actual * +* performance specification. * +* * +* This library contains models of the following INFINEON * +* OptiMOS2 transistors: * +* * +* 100V NL * +* IPB04CN10N IPD12CN10N * +* IPB05CN10N IPD16CN10N * +* IPB06CN10N IPD25CN10N * +* IPB08CN10N IPD33CN10N * +* IPB12CN10N IPD49CN10N * +* IPB16CN10N IPD78CN10N * +* IPP04CN10N IPD64CN10N * +* IPP05CN10N BSC079N10NS * +* IPP06CN10N BSC118N10NS * +* IPP08CN10N BSC196N10NS * +* IPP12CN10N BSC100N10NSF * +* IPP16CN10N BSC152N10NSF * +* IPP26CN10N BSC252N10NSF * +* IPP35CN10N BSC750N10ND * +* IPP50CN10N * +* IPP80CN10N * +* * +* 100 V LL * +* IPP05CN10L IPS12CN10L * +* IPP06CN10L BSC082N10LS BSC159N10LSF * +* IPP08CN10L BSC123N10LS BSC265N10LSF * +* IPP12CN10L BSC205N10LS * +* IPP16CN10L BSC105N10LSF * +***************************************************************** +* thermal nodes of level 3 models: * +* * +* .SUBCKT IPB05CN10N drain gate source Tj Tcase * +* Tj : potential=temperature (in °C) at junction (typically * +* not connected) * +* Tcase : node where the boundary contition - external heat * +* sinks etc - have to be connected (ideal heat sink * +* can be modeled by using a voltage source stating the * +* ambient temperature in °C between Tcase and ground. * +* * +***************************************************************** + + +.SUBCKT S3_100_a_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.065 Fn=0.5 kbq=85.8u +.PARAM c=1.55 muc=0.0 Vth0=4.073 auth=5.5m al=0.001 +.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132 + +.PARAM b0=22.55 p0=6.62 p1=-20.6m p2=39.2u + +.PARAM Rd=60m nmu=2.75 Tref=298 T0=273 lnIsj=-25.7 +.PARAM ndi=1.17 Rdi=12m nmu2=0.3 ta=30n td=100n +.PARAM Rf=0.34 nmu3=1.8 rpa=150u + +.PARAM f3=380p f3a=60p +.PARAM ps1=45p ps2=-62.5m ps3=80p ps4=-2 ps5=1.06p ps6=4p +.PARAM qs1=26p qs2=50p qs3=-2 qs4=175p qs5=-0.0357 + +.PARAM Vmin=3.073 Vmax=5.073 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT S3_100_b_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.065 Fn=0.5 kbq=85.8u +.PARAM c=1.312 muc=5m Vth0=4.073 auth=4.856m al=0.5 +.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132 + +.PARAM b0=10.91 p0=4.562 p1=-12.6m p2=32u + +.PARAM Rd=63m nmu=2.64 Tref=298 T0=273 lnIsj=-25.3 +.PARAM ndi=1.2 Rdi=5.7m nmu2=0.3 ta=30n td=100n +.PARAM Rf=0.28 nmu3=1.8 rpa=0u + +.PARAM f3=185p f3a=55p +.PARAM ps1=25p ps2=-62.5m ps3=40p ps4=-2 ps5=0.6p ps6=3p +.PARAM qs1=30p qs2=50p qs3=-2 qs4=200p qs5=-0.0357 + +.PARAM Vmin=3.073 Vmax=5.073 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT S3_100_c_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.085 Fn=0.5 kbq=85.8u +.PARAM c=1.08 muc=0.0 Vth0=2.69 auth=3.3m al=0.5 +.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132 + +.PARAM b0=35 p0=5.022 p1=-14.6m p2=25u + +.PARAM Rd=66m nmu=2.75 Tref=298 T0=273 lnIsj=-25.7 +.PARAM ndi=1.14 Rdi=12m nmu2=0.7 ta=30n td=100n +.PARAM Rf=0.34 nmu3=1.65 rpa=150u + +.PARAM f3=490p f3a=110p +.PARAM ps1=45p ps2=-62.5m ps3=80p ps4=-2 ps5=1.06p ps6=4p +.PARAM qs1=26p qs2=50p qs3=-2 qs4=180p qs5=-0.0333 + +.PARAM Vmin=2.04 Vmax=2.84 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT S3_100_d_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1 ++gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0 + +.PARAM Fm=0.085 Fn=0.5 kbq=85.8u +.PARAM c=1.4 muc=0.0 Vth0=2.69 auth=3.3m al=0.5 +.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132 + +.PARAM b0=16 p0=6.445 p1=-22.5m p2=39u + +.PARAM Rd=66m nmu=2.75 Tref=298 T0=273 lnIsj=-25.7 +.PARAM ndi=1.14 Rdi=12m nmu2=0.7 ta=30n td=100n +.PARAM Rf=0.34 nmu3=1.65 rpa=300u + +.PARAM f3=245p f3a=100p +.PARAM ps1=25p ps2=-77m ps3=43p ps4=-2 ps5=0.4p ps6=4p +.PARAM qs1=30p qs2=50p qs3=-2 qs4=180p qs5=-0.0333 + +.PARAM Vmin=2.04 Vmax=2.84 dCmax=0.33 +.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} +.PARAM q0={b0*((T0/Tref)**nmu3)*a} +.PARAM q1={(Unn-Inn*Rs-Vth0)*q0} +.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0} +.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)} +.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)} +.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)} +.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)} +.PARAM dC1={1+dCmax*limit(dC,0,1)} + +.PARAM Cox1={ps1*a*dC1} +.PARAM Cox2={ps3*a*dC1} +.PARAM Cox3={(ps5*a+ps6)*dC1} +.PARAM Cds0={qs1*a*dC1} +.PARAM Cds1={qs2*a*dC1} +.PARAM Cds2={qs4*a*dC1} +.PARAM Cgs0={(f3a+f3*a)*dC1} +.PARAM dRdi={Rdi/a} + +.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))} +.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)} +.FUNC J(d,g,T,da,s) ++ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))} + +.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss} +.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)} + +E_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)} +C_Cdg1 ox g {Cox1} +E_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)} +C_Cdg2 ox1 g {Cox2} +Vx d ox2 0 +C_Cdg3 ox2 g {Cox3} + +E_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))} +C_Cds edep s {Cds0+Cds1+Cds2} + +C_Cgs g s {Cgs0} + +G_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))} +G_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)} +V_sense dd d1 0 +G_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))} +G_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)} +V_sense2 d2 d3 0 + +L_L001 a c {td/(ta+td)} +R_R001 a b {1/ta} +V_sense3 c 0 0 +E_E001 b 0 VALUE {I(V_sense2)} +E_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} + +R_R002 e c 1 +R_R003 a 0 500Meg + +R1 g s 1G +Rd01 d s 500Meg +Rd02 d2 s 500Meg +Rd03 d1 d 1k + +Rmet s s0 {Rm} + +G_TH 0 Tj VALUE = ++{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+ ++(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))} + +.ENDS + +********* + +.SUBCKT IPB04CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=623u Rg=1.9 Rd=50u Rm=156u +.PARAM Inn=100 Unn=10 Rmax=4.1m gmin=87 +.PARAM RRf=181m Rrbond=10m Rtb=5 g2=572m +.PARAM act=27.1 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.61m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.21m+limit(Zthtype,0,1)*449.24u} +Rth2 t1 t2 {13.31m+limit(Zthtype,0,1)*4.92m} +Rth3 t2 t3 {75.74m+limit(Zthtype,0,1)*25.08m} +Rth4 t3 t4 {65.33m+limit(Zthtype,0,1)*38.48m} +Rth5 t4 Tcase {173.36m+limit(Zthtype,0,1)*102.12m} +Cth1 Tj 0 377.292u +Cth2 t1 0 856.511u +Cth3 t2 0 9.103m +Cth4 t3 0 4.607m +Cth5 t4 0 136.409m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPB05CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=50u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.1m gmin=81 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=23.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.4m+limit(Zthtype,0,1)*515.4u} +Rth2 t1 t2 {15.33m+limit(Zthtype,0,1)*5.68m} +Rth3 t2 t3 {87.39m+limit(Zthtype,0,1)*28.98m} +Rth4 t3 t4 {75.43m+limit(Zthtype,0,1)*29.02m} +Rth5 t4 Tcase {185.07m+limit(Zthtype,0,1)*71.19m} +Cth1 Tj 0 326.755u +Cth2 t1 0 743.512u +Cth3 t2 0 7.891m +Cth4 t3 0 3.99m +Cth5 t4 0 121.993m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPB06CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=50u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.2m gmin=77 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=17.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.83m+limit(Zthtype,0,1)*681.8u} +Rth2 t1 t2 {20m+limit(Zthtype,0,1)*7.41m} +Rth3 t2 t3 {113.28m+limit(Zthtype,0,1)*38.04m} +Rth4 t3 t4 {98.91m+limit(Zthtype,0,1)*67.42m} +Rth5 t4 Tcase {209.58m+limit(Zthtype,0,1)*142.85m} +Cth1 Tj 0 249.208u +Cth2 t1 0 569.82u +Cth3 t2 0 6.105m +Cth4 t3 0 3.043m +Cth5 t4 0 100.531m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPB08CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=50u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.2m gmin=57 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=12.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.54m+limit(Zthtype,0,1)*945.06u} +Rth2 t1 t2 {27.57m+limit(Zthtype,0,1)*10.21m} +Rth3 t2 t3 {154.04m+limit(Zthtype,0,1)*52.84m} +Rth4 t3 t4 {137.24m+limit(Zthtype,0,1)*97.36m} +Rth5 t4 Tcase {244.09m+limit(Zthtype,0,1)*173.16m} +Cth1 Tj 0 179.597u +Cth2 t1 0 413.456u +Cth3 t2 0 4.512m +Cth4 t3 0 2.193m +Cth5 t4 0 81.53m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPB12CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=1n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=50u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.6m gmin=38 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {213.05m+limit(Zthtype,0,1)*127.18m} +Rth5 t4 Tcase {300.49m+limit(Zthtype,0,1)*179.38m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.413m +Cth5 t4 0 63.737m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPB16CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=1n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=50u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16.2m gmin=30 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=6.16 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {5.33m+limit(Zthtype,0,1)*1.97m} +Rth2 t1 t2 {56.59m+limit(Zthtype,0,1)*20.95m} +Rth3 t2 t3 {306.84m+limit(Zthtype,0,1)*111.08m} +Rth4 t3 t4 {287.41m+limit(Zthtype,0,1)*164.5m} +Rth5 t4 Tcase {346.82m+limit(Zthtype,0,1)*198.51m} +Cth1 Tj 0 85.761u +Cth2 t1 0 201.422u +Cth3 t2 0 2.296m +Cth4 t3 0 1.047m +Cth5 t4 0 55.041m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP04CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=623u Rg=1.9 Rd=350u Rm=156u +.PARAM Inn=100 Unn=10 Rmax=4.4m gmin=87 +.PARAM RRf=181m Rrbond=10m Rtb=5 g2=572m +.PARAM act=27.1 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 7.61m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.21m+limit(Zthtype,0,1)*449.24u} +Rth2 t1 t2 {13.31m+limit(Zthtype,0,1)*4.92m} +Rth3 t2 t3 {75.74m+limit(Zthtype,0,1)*25.08m} +Rth4 t3 t4 {65.33m+limit(Zthtype,0,1)*38.48m} +Rth5 t4 Tcase {173.36m+limit(Zthtype,0,1)*102.12m} +Cth1 Tj 0 377.292u +Cth2 t1 0 856.511u +Cth3 t2 0 9.103m +Cth4 t3 0 4.607m +Cth5 t4 0 136.409m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP05CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=350u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.4m gmin=81 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=23.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.4m+limit(Zthtype,0,1)*515.4u} +Rth2 t1 t2 {15.33m+limit(Zthtype,0,1)*5.68m} +Rth3 t2 t3 {87.39m+limit(Zthtype,0,1)*28.98m} +Rth4 t3 t4 {75.43m+limit(Zthtype,0,1)*29.02m} +Rth5 t4 Tcase {185.07m+limit(Zthtype,0,1)*71.19m} +Cth1 Tj 0 326.755u +Cth2 t1 0 743.512u +Cth3 t2 0 7.891m +Cth4 t3 0 3.99m +Cth5 t4 0 121.993m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP06CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=350u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.5m gmin=77 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=17.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.83m+limit(Zthtype,0,1)*681.8u} +Rth2 t1 t2 {20m+limit(Zthtype,0,1)*7.41m} +Rth3 t2 t3 {113.28m+limit(Zthtype,0,1)*38.04m} +Rth4 t3 t4 {98.91m+limit(Zthtype,0,1)*67.42m} +Rth5 t4 Tcase {209.58m+limit(Zthtype,0,1)*142.85m} +Cth1 Tj 0 249.208u +Cth2 t1 0 569.82u +Cth3 t2 0 6.105m +Cth4 t3 0 3.043m +Cth5 t4 0 100.531m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP08CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=350u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.5m gmin=57 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=12.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.54m+limit(Zthtype,0,1)*945.06u} +Rth2 t1 t2 {27.57m+limit(Zthtype,0,1)*10.21m} +Rth3 t2 t3 {154.04m+limit(Zthtype,0,1)*52.84m} +Rth4 t3 t4 {137.24m+limit(Zthtype,0,1)*97.36m} +Rth5 t4 Tcase {244.09m+limit(Zthtype,0,1)*173.16m} +Cth1 Tj 0 179.597u +Cth2 t1 0 413.456u +Cth3 t2 0 4.512m +Cth4 t3 0 2.193m +Cth5 t4 0 81.53m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP12CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=350u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.9m gmin=38 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {213.05m+limit(Zthtype,0,1)*127.18m} +Rth5 t4 Tcase {300.49m+limit(Zthtype,0,1)*179.38m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.413m +Cth5 t4 0 63.737m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP16CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=350u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16.5m gmin=30 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=6.16 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {5.33m+limit(Zthtype,0,1)*1.97m} +Rth2 t1 t2 {56.59m+limit(Zthtype,0,1)*20.95m} +Rth3 t2 t3 {306.84m+limit(Zthtype,0,1)*111.08m} +Rth4 t3 t4 {287.41m+limit(Zthtype,0,1)*164.5m} +Rth5 t4 Tcase {346.82m+limit(Zthtype,0,1)*198.51m} +Cth1 Tj 0 85.761u +Cth2 t1 0 201.422u +Cth3 t2 0 2.296m +Cth4 t3 0 1.047m +Cth5 t4 0 55.041m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP26CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=1.72m Rg=1.1 Rd=350u Rm=640u +.PARAM Inn=35 Unn=10 Rmax=26m gmin=19 +.PARAM RRf=473m Rrbond=124m Rtb=17.4 g2=822m +.PARAM act=3.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 2.93m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {8.42m+limit(Zthtype,0,1)*3.11m} +Rth2 t1 t2 {87.93m+limit(Zthtype,0,1)*32.54m} +Rth3 t2 t3 {463.44m+limit(Zthtype,0,1)*175.99m} +Rth4 t3 t4 {457.12m+limit(Zthtype,0,1)*225.29m} +Rth5 t4 Tcase {432.84m+limit(Zthtype,0,1)*213.32m} +Cth1 Tj 0 54.297u +Cth2 t1 0 129.642u +Cth3 t2 0 1.539m +Cth4 t3 0 662.942u +Cth5 t4 0 45.488m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP35CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=1.53m Rg=1 Rd=350u Rm=450u +.PARAM Inn=27 Unn=10 Rmax=35m gmin=15 +.PARAM RRf=473m Rrbond=124m Rtb=17.4 g2=822m +.PARAM act=2.92 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 2.93m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {11.24m+limit(Zthtype,0,1)*4.16m} +Rth2 t1 t2 {115.99m+limit(Zthtype,0,1)*42.92m} +Rth3 t2 t3 {603.94m+limit(Zthtype,0,1)*235.6m} +Rth4 t3 t4 {614.86m+limit(Zthtype,0,1)*260.87m} +Rth5 t4 Tcase {498.79m+limit(Zthtype,0,1)*211.63m} +Cth1 Tj 0 40.653u +Cth2 t1 0 98.282u +Cth3 t2 0 1.19m +Cth4 t3 0 496.356u +Cth5 t4 0 41.277m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP50CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=2.62m Rg=0.9 Rd=350u Rm=650u +.PARAM Inn=20 Unn=10 Rmax=50m gmin=10.5 +.PARAM RRf=494m Rrbond=518m Rtb=35.4 g2=904m +.PARAM act=1.98 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.43m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {16.58m+limit(Zthtype,0,1)*6.13m} +Rth2 t1 t2 {167.72m+limit(Zthtype,0,1)*62.07m} +Rth3 t2 t3 {841.93m+limit(Zthtype,0,1)*348.69m} +Rth4 t3 t4 {920.39m+limit(Zthtype,0,1)*260.77m} +Rth5 t4 Tcase {604.46m+limit(Zthtype,0,1)*171.26m} +Cth1 Tj 0 27.566u +Cth2 t1 0 67.968u +Cth3 t2 0 868.439u +Cth4 t3 0 336.57u +Cth5 t4 0 37.577m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP80CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=4.3m Rg=0.8 Rd=350u Rm=660u +.PARAM Inn=13 Unn=10 Rmax=80m gmin=6.5 +.PARAM RRf=498m Rrbond=2 Rtb=69.4 g2=949m +.PARAM act=1.238 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 731.6u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {26.51m+limit(Zthtype,0,1)*9.81m} +Rth2 t1 t2 {260.54m+limit(Zthtype,0,1)*96.42m} +Rth3 t2 t3 {1.23+limit(Zthtype,0,1)*565.19m} +Rth4 t3 t4 {1.5+limit(Zthtype,0,1)*296.12m} +Rth5 t4 Tcase {764.49m+limit(Zthtype,0,1)*150.92m} +Cth1 Tj 0 17.236u +Cth2 t1 0 43.753u +Cth3 t2 0 609.936u +Cth4 t3 0 210.441u +Cth5 t4 0 36.415m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPD12CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=791u Rg=1.5 Rd=50u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.4m gmin=38 +.PARAM RRf=301m Rrbond=14m Rtb=5.8 g2=623m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.9m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {172m+limit(Zthtype,0,1)*138.86m} +Rth5 t4 Tcase {281.76m+limit(Zthtype,0,1)*227.48m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.464m +Cth5 t4 0 34.87m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPD16CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=741u Rg=1.2 Rd=50u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16m gmin=30 +.PARAM RRf=301m Rrbond=14m Rtb=5.8 g2=623m +.PARAM act=6.16 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.9m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {5.33m+limit(Zthtype,0,1)*1.97m} +Rth2 t1 t2 {56.59m+limit(Zthtype,0,1)*20.95m} +Rth3 t2 t3 {306.84m+limit(Zthtype,0,1)*111.08m} +Rth4 t3 t4 {232.04m+limit(Zthtype,0,1)*180.69m} +Rth5 t4 Tcase {328.61m+limit(Zthtype,0,1)*255.9m} +Cth1 Tj 0 85.761u +Cth2 t1 0 201.422u +Cth3 t2 0 2.296m +Cth4 t3 0 1.086m +Cth5 t4 0 29.486m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPD25CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=1.41m Rg=1.1 Rd=50u Rm=640u +.PARAM Inn=35 Unn=10 Rmax=25m gmin=19 +.PARAM RRf=450m Rrbond=55m Rtb=11.6 g2=767m +.PARAM act=3.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.95m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {8.42m+limit(Zthtype,0,1)*3.11m} +Rth2 t1 t2 {87.93m+limit(Zthtype,0,1)*32.54m} +Rth3 t2 t3 {463.44m+limit(Zthtype,0,1)*175.99m} +Rth4 t3 t4 {369.67m+limit(Zthtype,0,1)*266.53m} +Rth5 t4 Tcase {402.31m+limit(Zthtype,0,1)*290.06m} +Cth1 Tj 0 54.297u +Cth2 t1 0 129.642u +Cth3 t2 0 1.539m +Cth4 t3 0 687.254u +Cth5 t4 0 25.436m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD33CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=1.22m Rg=1 Rd=50u Rm=450u +.PARAM Inn=27 Unn=10 Rmax=33m gmin=15 +.PARAM RRf=450m Rrbond=55m Rtb=11.6 g2=767m +.PARAM act=2.92 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 1.95m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {11.24m+limit(Zthtype,0,1)*4.16m} +Rth2 t1 t2 {115.99m+limit(Zthtype,0,1)*42.92m} +Rth3 t2 t3 {603.94m+limit(Zthtype,0,1)*235.6m} +Rth4 t3 t4 {498.05m+limit(Zthtype,0,1)*337.62m} +Rth5 t4 Tcase {447.28m+limit(Zthtype,0,1)*303.2m} +Cth1 Tj 0 40.653u +Cth2 t1 0 98.282u +Cth3 t2 0 1.19m +Cth4 t3 0 514.559u +Cth5 t4 0 25.184m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD49CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=2.01m Rg=0.9 Rd=50u Rm=650u +.PARAM Inn=20 Unn=10 Rmax=49m gmin=10.5 +.PARAM RRf=488m Rrbond=230m Rtb=23.6 g2=871m +.PARAM act=1.98 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 955.96u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {16.58m+limit(Zthtype,0,1)*6.13m} +Rth2 t1 t2 {167.72m+limit(Zthtype,0,1)*62.07m} +Rth3 t2 t3 {841.93m+limit(Zthtype,0,1)*348.69m} +Rth4 t3 t4 {748.13m+limit(Zthtype,0,1)*425.86m} +Rth5 t4 Tcase {498.9m+limit(Zthtype,0,1)*283.99m} +Cth1 Tj 0 27.566u +Cth2 t1 0 67.968u +Cth3 t2 0 868.439u +Cth4 t3 0 348.914u +Cth5 t4 0 29.676m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPD78CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=3.14m Rg=0.8 Rd=50u Rm=660u +.PARAM Inn=13 Unn=10 Rmax=78m gmin=6.5 +.PARAM RRf=497m Rrbond=884m Rtb=46.3 g2=930m +.PARAM act=1.238 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 487.73u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {26.51m+limit(Zthtype,0,1)*9.81m} +Rth2 t1 t2 {260.54m+limit(Zthtype,0,1)*96.42m} +Rth3 t2 t3 {1.23+limit(Zthtype,0,1)*565.19m} +Rth4 t3 t4 {1.23+limit(Zthtype,0,1)*664.58m} +Rth5 t4 Tcase {530.38m+limit(Zthtype,0,1)*286.57m} +Cth1 Tj 0 17.236u +Cth2 t1 0 43.753u +Cth3 t2 0 609.936u +Cth4 t3 0 218.159u +Cth5 t4 0 106.171m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPD64CN10N drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=3.14m Rg=0.9 Rd=50u Rm=660u +.PARAM Inn=17 Unn=10 Rmax=64m gmin=4.86 +.PARAM RRf=497m Rrbond=884m Rtb=46.3 g2=930m +.PARAM act=1.98 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 487.73u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {16.58m+limit(Zthtype,0,1)*6.13m} +Rth2 t1 t2 {167.72m+limit(Zthtype,0,1)*62.07m} +Rth3 t2 t3 {841.93m+limit(Zthtype,0,1)*348.69m} +Rth4 t3 t4 {748.13m+limit(Zthtype,0,1)*425.86m} +Rth5 t4 Tcase {498.9m+limit(Zthtype,0,1)*283.99m} +Cth1 Tj 0 27.566u +Cth2 t1 0 67.968u +Cth3 t2 0 868.439u +Cth4 t3 0 348.914u +Cth5 t4 0 29.676m +Cth6 Tcase 0 70m + +.ENDS + +********** + + +.SUBCKT BSC079N10NS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=7.9m gmin=40 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=11.21 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.93m+limit(Zthtype,0,1)*1.08m} +Rth2 t1 t2 {31.62m+limit(Zthtype,0,1)*11.71m} +Rth3 t2 t3 {174.06m+limit(Zthtype,0,1)*60.85m} +Rth4 t3 t4 {127.51m+limit(Zthtype,0,1)*53.35m} +Rth5 t4 Tcase {237.51m+limit(Zthtype,0,1)*99.38m} +Cth1 Tj 0 156.068u +Cth2 t1 0 360.466u +Cth3 t2 0 4.012m +Cth4 t3 0 1.975m +Cth5 t4 0 43.728m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC118N10NS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=11.8m gmin=33 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=7.207 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.55m+limit(Zthtype,0,1)*1.69m} +Rth2 t1 t2 {48.61m+limit(Zthtype,0,1)*17.99m} +Rth3 t2 t3 {259.98m+limit(Zthtype,0,1)*94.86m} +Rth4 t3 t4 {198.33m+limit(Zthtype,0,1)*67.23m} +Rth5 t4 Tcase {303.78m+limit(Zthtype,0,1)*102.98m} +Cth1 Tj 0 100.337u +Cth2 t1 0 234.513u +Cth3 t2 0 2.715m +Cth4 t3 0 1.27m +Cth5 t4 0 31.977m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC196N10NS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=45 Unn=10 Rmax=19.6m gmin=24 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=4.269 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.69m+limit(Zthtype,0,1)*2.84m} +Rth2 t1 t2 {80.62m+limit(Zthtype,0,1)*29.83m} +Rth3 t2 t3 {427.48m+limit(Zthtype,0,1)*160.67m} +Rth4 t3 t4 {336.57m+limit(Zthtype,0,1)*77.37m} +Rth5 t4 Tcase {387.78m+limit(Zthtype,0,1)*89.15m} +Cth1 Tj 0 59.434u +Cth2 t1 0 141.405u +Cth3 t2 0 1.664m +Cth4 t3 0 752.279u +Cth5 t4 0 25.896m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC100N10NSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=10m gmin=20 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=11.21 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.93m+limit(Zthtype,0,1)*1.08m} +Rth2 t1 t2 {31.62m+limit(Zthtype,0,1)*11.71m} +Rth3 t2 t3 {174.06m+limit(Zthtype,0,1)*60.85m} +Rth4 t3 t4 {127.51m+limit(Zthtype,0,1)*53.35m} +Rth5 t4 Tcase {237.51m+limit(Zthtype,0,1)*99.38m} +Cth1 Tj 0 156.068u +Cth2 t1 0 360.466u +Cth3 t2 0 4.012m +Cth4 t3 0 1.975m +Cth5 t4 0 43.728m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC152N10NSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=15.2m gmin=16 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=7.207 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.55m+limit(Zthtype,0,1)*1.69m} +Rth2 t1 t2 {48.61m+limit(Zthtype,0,1)*17.99m} +Rth3 t2 t3 {259.98m+limit(Zthtype,0,1)*94.86m} +Rth4 t3 t4 {198.33m+limit(Zthtype,0,1)*67.23m} +Rth5 t4 Tcase {303.78m+limit(Zthtype,0,1)*102.98m} +Cth1 Tj 0 100.337u +Cth2 t1 0 234.513u +Cth3 t2 0 2.715m +Cth4 t3 0 1.27m +Cth5 t4 0 31.977m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC252N10NSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=39 Unn=10 Rmax=25.2m gmin=17 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=4.269 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.69m+limit(Zthtype,0,1)*2.84m} +Rth2 t1 t2 {80.62m+limit(Zthtype,0,1)*29.83m} +Rth3 t2 t3 {427.48m+limit(Zthtype,0,1)*160.67m} +Rth4 t3 t4 {336.57m+limit(Zthtype,0,1)*77.37m} +Rth5 t4 Tcase {387.78m+limit(Zthtype,0,1)*89.15m} +Cth1 Tj 0 59.434u +Cth2 t1 0 141.405u +Cth3 t2 0 1.664m +Cth4 t3 0 752.279u +Cth5 t4 0 25.896m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC750N10ND drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=5.06m Rg=0.8 Rd=10u Rm=2m +.PARAM Inn=12 Unn=10 Rmax=75m gmin=7.1 +.PARAM RRf=500m Rrbond=2 Rtb=67.5 g2=995m +.PARAM act=1.238 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 92.18u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {26.51m+limit(Zthtype,0,1)*9.81m} +Rth2 t1 t2 {260.54m+limit(Zthtype,0,1)*96.42m} +Rth3 t2 t3 {1.23+limit(Zthtype,0,1)*565.19m} +Rth4 t3 t4 {1.23+limit(Zthtype,0,1)*664.58m} +Rth5 t4 Tcase {530.38m+limit(Zthtype,0,1)*286.57m} +Cth1 Tj 0 17.236u +Cth2 t1 0 43.753u +Cth3 t2 0 609.936u +Cth4 t3 0 218.159u +Cth5 t4 0 106.171m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPP05CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=350u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.4m gmin=81 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=23.47 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.4m+limit(Zthtype,0,1)*515.4u} +Rth2 t1 t2 {15.33m+limit(Zthtype,0,1)*5.68m} +Rth3 t2 t3 {87.39m+limit(Zthtype,0,1)*28.98m} +Rth4 t3 t4 {75.43m+limit(Zthtype,0,1)*29.02m} +Rth5 t4 Tcase {185.07m+limit(Zthtype,0,1)*71.19m} +Cth1 Tj 0 326.755u +Cth2 t1 0 743.512u +Cth3 t2 0 7.891m +Cth4 t3 0 3.99m +Cth5 t4 0 121.993m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP06CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=350u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.5m gmin=77 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=17.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {1.83m+limit(Zthtype,0,1)*681.8u} +Rth2 t1 t2 {20m+limit(Zthtype,0,1)*7.41m} +Rth3 t2 t3 {113.28m+limit(Zthtype,0,1)*38.04m} +Rth4 t3 t4 {98.91m+limit(Zthtype,0,1)*67.42m} +Rth5 t4 Tcase {209.58m+limit(Zthtype,0,1)*142.85m} +Cth1 Tj 0 249.208u +Cth2 t1 0 569.82u +Cth3 t2 0 6.105m +Cth4 t3 0 3.043m +Cth5 t4 0 100.531m +Cth6 Tcase 0 190m + +.ENDS + +********** + +.SUBCKT IPP08CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=350u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.5m gmin=57 +.PARAM RRf=260m Rrbond=14m Rtb=5.8 g2=606m +.PARAM act=12.9 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 8.78m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.54m+limit(Zthtype,0,1)*945.06u} +Rth2 t1 t2 {27.57m+limit(Zthtype,0,1)*10.21m} +Rth3 t2 t3 {154.04m+limit(Zthtype,0,1)*52.84m} +Rth4 t3 t4 {137.24m+limit(Zthtype,0,1)*97.36m} +Rth5 t4 Tcase {244.09m+limit(Zthtype,0,1)*173.16m} +Cth1 Tj 0 179.597u +Cth2 t1 0 413.456u +Cth3 t2 0 4.512m +Cth4 t3 0 2.193m +Cth5 t4 0 81.53m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP12CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=350u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.9m gmin=38 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {213.05m+limit(Zthtype,0,1)*127.18m} +Rth5 t4 Tcase {300.49m+limit(Zthtype,0,1)*179.38m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.413m +Cth5 t4 0 63.737m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPP16CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=350u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16m gmin=30 +.PARAM RRf=393m Rrbond=31m Rtb=8.7 g2=698m +.PARAM act=6.16 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 5.85m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {5.33m+limit(Zthtype,0,1)*1.97m} +Rth2 t1 t2 {56.59m+limit(Zthtype,0,1)*20.95m} +Rth3 t2 t3 {306.84m+limit(Zthtype,0,1)*111.08m} +Rth4 t3 t4 {287.41m+limit(Zthtype,0,1)*164.5m} +Rth5 t4 Tcase {346.82m+limit(Zthtype,0,1)*198.51m} +Cth1 Tj 0 85.761u +Cth2 t1 0 201.422u +Cth3 t2 0 2.296m +Cth4 t3 0 1.047m +Cth5 t4 0 55.041m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT IPS12CN10L drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=2n Ld=2n Lg=3n + +.PARAM Rs=791u Rg=1.5 Rd=250u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.4m gmin=38 +.PARAM RRf=301m Rrbond=14m Rtb=5.8 g2=623m +.PARAM act=8.31 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 3.9m +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {3.95m+limit(Zthtype,0,1)*1.46m} +Rth2 t1 t2 {42.33m+limit(Zthtype,0,1)*15.67m} +Rth3 t2 t3 {234.29m+limit(Zthtype,0,1)*82.2m} +Rth4 t3 t4 {0p+limit(Zthtype,0,1)*0p} +Rth5 t4 Tcase {140.17m+limit(Zthtype,0,1)*679.93m} +Cth1 Tj 0 115.694u +Cth2 t1 0 269.296u +Cth3 t2 0 2.983m +Cth4 t3 0 1.413m +Cth5 t4 0 63.737m +Cth6 Tcase 0 70m + +.ENDS + +********** + +.SUBCKT BSC082N10LS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=8.2m gmin=60 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=11.21 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.93m+limit(Zthtype,0,1)*1.08m} +Rth2 t1 t2 {31.62m+limit(Zthtype,0,1)*11.71m} +Rth3 t2 t3 {174.06m+limit(Zthtype,0,1)*60.85m} +Rth4 t3 t4 {127.51m+limit(Zthtype,0,1)*53.35m} +Rth5 t4 Tcase {237.51m+limit(Zthtype,0,1)*99.38m} +Cth1 Tj 0 156.068u +Cth2 t1 0 360.466u +Cth3 t2 0 4.012m +Cth4 t3 0 1.975m +Cth5 t4 0 43.728m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC123N10LS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=12.3m gmin=49 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=7.207 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.55m+limit(Zthtype,0,1)*1.69m} +Rth2 t1 t2 {48.61m+limit(Zthtype,0,1)*17.99m} +Rth3 t2 t3 {259.98m+limit(Zthtype,0,1)*94.86m} +Rth4 t3 t4 {198.33m+limit(Zthtype,0,1)*67.23m} +Rth5 t4 Tcase {303.78m+limit(Zthtype,0,1)*102.98m} +Cth1 Tj 0 100.337u +Cth2 t1 0 234.513u +Cth3 t2 0 2.715m +Cth4 t3 0 1.27m +Cth5 t4 0 31.977m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC205N10LS drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=45 Unn=10 Rmax=20.5m gmin=36 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=4.269 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.69m+limit(Zthtype,0,1)*2.84m} +Rth2 t1 t2 {80.62m+limit(Zthtype,0,1)*29.83m} +Rth3 t2 t3 {427.48m+limit(Zthtype,0,1)*160.67m} +Rth4 t3 t4 {336.57m+limit(Zthtype,0,1)*77.37m} +Rth5 t4 Tcase {387.78m+limit(Zthtype,0,1)*89.15m} +Cth1 Tj 0 59.434u +Cth2 t1 0 141.405u +Cth3 t2 0 1.664m +Cth4 t3 0 752.279u +Cth5 t4 0 25.896m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC105N10LSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1.3 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=10.5m gmin=40 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=11.21 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {2.93m+limit(Zthtype,0,1)*1.08m} +Rth2 t1 t2 {31.62m+limit(Zthtype,0,1)*11.71m} +Rth3 t2 t3 {174.06m+limit(Zthtype,0,1)*60.85m} +Rth4 t3 t4 {127.51m+limit(Zthtype,0,1)*53.35m} +Rth5 t4 Tcase {237.51m+limit(Zthtype,0,1)*99.38m} +Cth1 Tj 0 156.068u +Cth2 t1 0 360.466u +Cth3 t2 0 4.012m +Cth4 t3 0 1.975m +Cth5 t4 0 43.728m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC159N10LSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=1.0 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=15.9m gmin=32 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=7.207 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {4.55m+limit(Zthtype,0,1)*1.69m} +Rth2 t1 t2 {48.61m+limit(Zthtype,0,1)*17.99m} +Rth3 t2 t3 {259.98m+limit(Zthtype,0,1)*94.86m} +Rth4 t3 t4 {198.33m+limit(Zthtype,0,1)*67.23m} +Rth5 t4 Tcase {303.78m+limit(Zthtype,0,1)*102.98m} +Cth1 Tj 0 100.337u +Cth2 t1 0 234.513u +Cth3 t2 0 2.715m +Cth4 t3 0 1.27m +Cth5 t4 0 31.977m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT BSC265N10LSF drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1.5 Rd=10u Rm=106u +.PARAM Inn=50 Unn=10 Rmax=26.5m gmin=24 +.PARAM RRf=411m Rrbond=1m Rtb=1.7 g2=841m +.PARAM act=4.269 + +.FUNC Pb(I,dT,Rb) {Rb/(2*Rtb)*(I-limit(dT/(max(I,1n)*Rb)+RRf*I*g2,0,I))**2} + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=1 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} +RLs source s1 10 +RLg gate g1 10 +RLd drain d2 10 + +G_TH 0 Tb VALUE = {Pb(abs(I(Ls)),V(Tj,Tcase),Rrbond*(1+(limit((V(Tb)+V(Tj))/2,-200,999)-25)*4m))} +Cthb Tb 0 18.29u +Rthb Tb Tj {Rtb} +Rth1 Tj t1 {7.69m+limit(Zthtype,0,1)*2.84m} +Rth2 t1 t2 {80.62m+limit(Zthtype,0,1)*29.83m} +Rth3 t2 t3 {427.48m+limit(Zthtype,0,1)*160.67m} +Rth4 t3 t4 {336.57m+limit(Zthtype,0,1)*77.37m} +Rth5 t4 Tcase {387.78m+limit(Zthtype,0,1)*89.15m} +Cth1 Tj 0 59.434u +Cth2 t1 0 141.405u +Cth3 t2 0 1.664m +Cth4 t3 0 752.279u +Cth5 t4 0 25.896m +Cth6 Tcase 0 30m + +.ENDS + +********** + +.SUBCKT IPB04CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=623u Rg=1.9 Rd=50u Rm=156u +.PARAM Inn=100 Unn=10 Rmax=4.1m gmin=87 +.PARAM act=27.1 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB05CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=50u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.1m gmin=81 +.PARAM act=23.47 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB06CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=50u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.2m gmin=77 +.PARAM act=17.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB08CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=1n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=50u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.2m gmin=57 +.PARAM act=12.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB12CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=1n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=50u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.6m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB16CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=1n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=50u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16.2m gmin=30 +.PARAM act=6.16 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP04CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=623u Rg=1.9 Rd=350u Rm=156u +.PARAM Inn=100 Unn=10 Rmax=4.4m gmin=87 +.PARAM act=27.1 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP05CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=350u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.4m gmin=81 +.PARAM act=23.47 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP06CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=350u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.5m gmin=77 +.PARAM act=17.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP08CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=350u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.5m gmin=57 +.PARAM act=12.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP12CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=350u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.9m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP16CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=350u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16.5m gmin=30 +.PARAM act=6.16 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP26CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=1.72m Rg=1.1 Rd=350u Rm=640u +.PARAM Inn=35 Unn=10 Rmax=26m gmin=19 +.PARAM act=3.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP35CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=1.53m Rg=1 Rd=350u Rm=450u +.PARAM Inn=27 Unn=10 Rmax=35m gmin=15 +.PARAM act=2.92 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP50CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=2.62m Rg=0.9 Rd=350u Rm=650u +.PARAM Inn=20 Unn=10 Rmax=50m gmin=10.5 +.PARAM act=1.98 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP80CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=5n Ld=2n Lg=4n + +.PARAM Rs=4.3m Rg=0.8 Rd=350u Rm=660u +.PARAM Inn=13 Unn=10 Rmax=80m gmin=6.5 +.PARAM act=1.238 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD12CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=791u Rg=1.5 Rd=50u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.4m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD16CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=1n Lg=3n + +.PARAM Rs=741u Rg=1.2 Rd=50u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16m gmin=30 +.PARAM act=6.16 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD25CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=1.41m Rg=1.1 Rd=50u Rm=640u +.PARAM Inn=35 Unn=10 Rmax=25m gmin=19 +.PARAM act=3.9 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD33CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=1.22m Rg=1 Rd=50u Rm=450u +.PARAM Inn=27 Unn=10 Rmax=33m gmin=15 +.PARAM act=2.92 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD49CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=2.01m Rg=0.9 Rd=50u Rm=650u +.PARAM Inn=20 Unn=10 Rmax=49m gmin=10.5 +.PARAM act=1.98 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD78CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=3.14m Rg=0.8 Rd=50u Rm=660u +.PARAM Inn=13 Unn=10 Rmax=78m gmin=6.5 +.PARAM act=1.238 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC079N10NS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=7.9m gmin=40 +.PARAM act=11.21 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC118N10NS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=11.8m gmin=33 +.PARAM act=7.207 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC196N10NS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=45 Unn=10 Rmax=19.6m gmin=24 +.PARAM act=4.269 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPD64CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n + +.PARAM Rs=3.14m Rg=0.9 Rd=50u Rm=660u +.PARAM Inn=17 Unn=10 Rmax=64m gmin=4.86 +.PARAM act=1.98 + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC100N10NSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=10m gmin=20 +.PARAM act=11.21 + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC152N10NSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=15.2m gmin=16 +.PARAM act=7.207 + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC252N10NSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=39 Unn=10 Rmax=25.2m gmin=17 +.PARAM act=4.269 + +X1 d1 g s Tj S3_100_b_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC750N10ND_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=5.06m Rg=0.8 Rd=10u Rm=2m +.PARAM Inn=12 Unn=10 Rmax=75m gmin=7.1 +.PARAM act=1.238 + +X1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP05CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=805u Rg=1.9 Rd=350u Rm=300u +.PARAM Inn=100 Unn=10 Rmax=5.4m gmin=81 +.PARAM act=23.47 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP06CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=745u Rg=1.6 Rd=350u Rm=240u +.PARAM Inn=100 Unn=10 Rmax=6.5m gmin=77 +.PARAM act=17.9 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP08CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=3n Ld=2n Lg=4n + +.PARAM Rs=705u Rg=1.5 Rd=350u Rm=200u +.PARAM Inn=95 Unn=10 Rmax=8.5m gmin=57 +.PARAM act=12.9 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP12CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=958u Rg=1.5 Rd=350u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.9m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPP16CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=4n Ld=2n Lg=4n + +.PARAM Rs=908u Rg=1.2 Rd=350u Rm=260u +.PARAM Inn=53 Unn=10 Rmax=16m gmin=30 +.PARAM act=6.16 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPS12CN10L_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2n Ld=2n Lg=3n + +.PARAM Rs=791u Rg=1.5 Rd=250u Rm=310u +.PARAM Inn=67 Unn=10 Rmax=12.4m gmin=38 +.PARAM act=8.31 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC082N10LS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=8.2m gmin=60 +.PARAM act=11.21 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC123N10LS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=0.8 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=12.3m gmin=49 +.PARAM act=7.207 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC205N10LS_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1 Rd=10u Rm=106u +.PARAM Inn=45 Unn=10 Rmax=20.5m gmin=36 +.PARAM act=4.269 + +X1 d1 g s Tj S3_100_c_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC105N10LSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=450u Rg=1.3 Rd=10u Rm=280u +.PARAM Inn=50 Unn=10 Rmax=10.5m gmin=40 +.PARAM act=11.21 + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC159N10LSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=349u Rg=1.0 Rd=10u Rm=179u +.PARAM Inn=50 Unn=10 Rmax=15.9m gmin=32 +.PARAM act=7.207 + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT BSC265N10LSF_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1n Ld=0.5n Lg=2n + +.PARAM Rs=276u Rg=1.5 Rd=10u Rm=106u +.PARAM Inn=50 Unn=10 Rmax=26.5m gmin=24 +.PARAM act=4.269 + +X1 d1 g s Tj S3_100_d_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} + +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0 +Rg g1 g {Rg} +Lg gate g1 {Lg*if(dgfs==99,0,1)} +Gs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)} +Rsa s1 s 1Meg +Ls source s1 {Ls*if(dgfs==99,0,1)} +Rda d1 d2 {Rd} +Ld drain d2 {Ld*if(dgfs==99,0,1)} + +E1 Tj w VALUE={TEMP} +R1 w 0 1u + +.ENDS + +********** + +.SUBCKT IPB04CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 623u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 372.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 2.3m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=7.7n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=51.5p N=1.11 RS=0.74u EG=1.12 TT=90n) +Rdiode d1 21 0.53m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.39n +.MODEL DGD D(M=2.4 CJO=3.39n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 10.36n + +.ENDS IPB04CN10N_L0 + +****** + +.SUBCKT IPP04CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 623u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 372.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 2.6m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=7.7n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=51.5p N=1.11 RS=0.74u EG=1.12 TT=90n) +Rdiode d1 21 0.53m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 3.39n +.MODEL DGD D(M=2.4 CJO=3.39n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 10.36n + +.ENDS IPP04CN10N_L0 + +****** + +.SUBCKT IPB05CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 805u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 322.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 2.65m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=6.67n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=44.6p N=1.11 RS=0.85u EG=1.12 TT=90n) +Rdiode d1 21 0.61m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.94n +.MODEL DGD D(M=2.4 CJO=2.94n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.98n + +.ENDS IPB05CN10N_L0 + +****** + +.SUBCKT IPP05CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 805u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 322.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 2.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=6.67n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=44.6p N=1.11 RS=0.85u EG=1.12 TT=90n) +Rdiode d1 21 0.61m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.94n +.MODEL DGD D(M=2.4 CJO=2.94n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.98n + +.ENDS IPP05CN10N_L0 + +****** + +.SUBCKT IPB06CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 745u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 246.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 3.46m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=5.08n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=34p N=1.11 RS=1.12u EG=1.12 TT=90n) +Rdiode d1 21 0.8m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.24n +.MODEL DGD D(M=2.4 CJO=2.24n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.86n + +.ENDS IPB06CN10N_L0 + +****** + +.SUBCKT IPP06CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 745u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 246.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 3.76m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=5.08n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=34p N=1.11 RS=1.12u EG=1.12 TT=90n) +Rdiode d1 21 0.8m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.24n +.MODEL DGD D(M=2.4 CJO=2.24n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.86n + +.ENDS IPP06CN10N_L0 + +****** + +.SUBCKT IPB08CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 3n +Rs s1 s2 705u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 177.4 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 4.78m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.66n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=24.5p N=1.11 RS=1.55u EG=1.12 TT=90n) +Rdiode d1 21 1.12m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.62n +.MODEL DGD D(M=2.4 CJO=1.62n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.96n + +.ENDS IPB08CN10N_L0 + +****** + +.SUBCKT IPP08CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 705u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 177.4 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.08m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.66n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=24.5p N=1.11 RS=1.55u EG=1.12 TT=90n) +Rdiode d1 21 1.12m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.62n +.MODEL DGD D(M=2.4 CJO=1.62n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.96n + +.ENDS IPP08CN10N_L0 + +****** + +.SUBCKT IPB12CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 4n +Rs s1 s2 958u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 114.3 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 7.39m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.11 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.73m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.22n + +.ENDS IPB12CN10N_L0 + +****** + +.SUBCKT IPP12CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 958u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 114.3 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 7.69m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.11 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.73m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.22n + +.ENDS IPP12CN10N_L0 + +****** + +.SUBCKT IPD12CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 791u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 114.3 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 7.39m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.11 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.73m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.22n + +.ENDS IPD12CN10N_L0 + +****** + +.SUBCKT IPB16CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 1n +Ls source s1 4n +Rs s1 s2 908u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 84.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 9.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.11 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 2.34m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.4n + +.ENDS IPB16CN10N_L0 + +****** + +.SUBCKT IPP16CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 908u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 84.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 10.25m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.11 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 2.34m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.4n + +.ENDS IPP16CN10N_L0 + +****** + +.SUBCKT IPD16CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2n +Rs s1 s2 741u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 84.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 9.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.11 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 2.34m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.4n + +.ENDS IPD16CN10N_L0 + +****** + +.SUBCKT IPP26CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 1.72m + +Rg g1 g2 1.1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 53.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 15.99m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.11n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=7.4p N=1.11 RS=5.13u EG=1.12 TT=90n) +Rdiode d1 21 3.69m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=2.4 CJO=0.49n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS IPP26CN10N_L0 + +****** + +.SUBCKT IPD25CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 1.41m + +Rg g1 g2 1.1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 53.6 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 15.69m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.11n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=7.4p N=1.11 RS=5.13u EG=1.12 TT=90n) +Rdiode d1 21 3.69m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.49n +.MODEL DGD D(M=2.4 CJO=0.49n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.54n + +.ENDS IPD25CN10N_L0 + +****** + +.SUBCKT IPP35CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 1.53m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 40.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 21.24m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.83n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=5.5p N=1.11 RS=6.85u EG=1.12 TT=90n) +Rdiode d1 21 4.93m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.37n +.MODEL DGD D(M=2.4 CJO=0.37n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.17n + +.ENDS IPP35CN10N_L0 + +****** + +.SUBCKT IPD33CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 1.22m + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 40.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 20.94m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.83n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=5.5p N=1.11 RS=6.85u EG=1.12 TT=90n) +Rdiode d1 21 4.93m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.37n +.MODEL DGD D(M=2.4 CJO=0.37n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.17n + +.ENDS IPD33CN10N_L0 + +****** + +.SUBCKT IPP50CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 2.62m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 27.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 31.16m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.56n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.11 RS=10.1u EG=1.12 TT=90n) +Rdiode d1 21 7.27m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.25n +.MODEL DGD D(M=2.4 CJO=0.25n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.81n + +.ENDS IPP50CN10N_L0 + +****** + +.SUBCKT IPD49CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 2.01m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 27.2 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 30.86m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.56n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.11 RS=10.1u EG=1.12 TT=90n) +Rdiode d1 21 7.27m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.25n +.MODEL DGD D(M=2.4 CJO=0.25n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.81n + +.ENDS IPD49CN10N_L0 + +****** + +.SUBCKT IPP80CN10N_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 5n +Rs s1 s2 4.3m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 49.62m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.35n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=2.4p N=1.11 RS=16.16u EG=1.12 TT=90n) +Rdiode d1 21 11.63m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.16n +.MODEL DGD D(M=2.4 CJO=0.16n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.53n + +.ENDS IPP80CN10N_L0 + +****** + +.SUBCKT IPD78CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 3.14m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 49.32m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.35n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=2.4p N=1.11 RS=16.16u EG=1.12 TT=90n) +Rdiode d1 21 11.63m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.16n +.MODEL DGD D(M=2.4 CJO=0.16n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.53n + +.ENDS IPD78CN10N_L0 + +****** + +.SUBCKT BSC079N10NS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 154.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.45m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.18n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.11 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 1.28m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.405n +.MODEL DGD D(M=2.4 CJO=1.405n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.32n + +.ENDS BSC079N10NS_L0 + +****** + +.SUBCKT BSC118N10NS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 99.1 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.47m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.05n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.11 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 2m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.905n +.MODEL DGD D(M=2.4 CJO=0.905n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.8n + +.ENDS BSC118N10NS_L0 + +****** + +.SUBCKT BSC196N10NS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 58.7 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 14.3m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.21n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.11 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 3.37m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.538n +.MODEL DGD D(M=2.4 CJO=0.538n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.68n + +.ENDS BSC196N10NS_L0 + +****** + +.SUBCKT IPD64CN10N_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 1n +Ls source s1 2.5n +Rs s1 s2 3.14m + +Rg g1 g2 0.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 16.7 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 30.05m TC=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.4n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=3.8p N=1.11 RS=10.1u EG=1.12 TT=90n) +Rdiode d1 21 4.04m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.127n +.MODEL DGD D(M=2.1 CJO=0.127n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.43n + +.ENDS IPD64CN10N_L0 + +****** + +.SUBCKT BSC100N10NSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 94.7 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.31m TC=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.24n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.11 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 0.71m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.699n +.MODEL DGD D(M=2.1 CJO=0.699n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.18n + +.ENDS BSC100N10NSF_L0 + +****** + +.SUBCKT BSC152N10NSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 60.9 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.25m TC=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.44n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.11 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 1.11m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.451n +.MODEL DGD D(M=2.1 CJO=0.451n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.42n + +.ENDS BSC152N10NSF_L0 + +****** + +.SUBCKT BSC252N10NSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 36.1 VTO=4.3 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 13.92m TC=10.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.85n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.11 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 1.87m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.269n +.MODEL DGD D(M=2.1 CJO=0.269n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.87n + +.ENDS BSC252N10NSF_L0 + +****** + +.SUBCKT BSC750N10ND_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 5.06m + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 17 VTO=4.2 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 49.28m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=0.35n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=2.4p N=1.11 RS=16.16u EG=1.12 TT=90n) +Rdiode d1 21 11.63m TC=2m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.16n +.MODEL DGD D(M=2.4 CJO=0.16n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 0.53n + +.ENDS BSC750N10ND_L0 + +****** + +.SUBCKT IPP05CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 805u + +Rg g1 g2 1.9 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 535.1 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 3.09m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=6.67n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=44.6p N=1.07 RS=0.85u EG=1.12 TT=90n) +Rdiode d1 21 0.7m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.94n +.MODEL DGD D(M=2.4 CJO=2.94n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 11.56n + +.ENDS IPP05CN10L_L0 + +****** + +.SUBCKT IPP06CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 745u + +Rg g1 g2 1.6 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 408.1 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 3.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=5.08n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=34p N=1.07 RS=1.12u EG=1.12 TT=90n) +Rdiode d1 21 0.92m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 2.24n +.MODEL DGD D(M=2.4 CJO=2.24n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 8.83n + +.ENDS IPP06CN10L_L0 + +****** + +.SUBCKT IPP08CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 3n +Rs s1 s2 705u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 294.1 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.34m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.66n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=24.5p N=1.07 RS=1.55u EG=1.12 TT=90n) +Rdiode d1 21 1.28m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.62n +.MODEL DGD D(M=2.4 CJO=1.62n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 6.38n + +.ENDS IPP08CN10L_L0 + +****** + +.SUBCKT IPP12CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 958u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 189.5 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.1m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.07 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.99m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.13n + +.ENDS IPP12CN10L_L0 + +****** + +.SUBCKT IPS12CN10L_L0 drain gate source + +Lg gate g1 3n +Ld drain d1 2n +Ls source s1 2n +Rs s1 s2 791u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 189.5 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.36n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=15.8p N=1.07 RS=2.41u EG=1.12 TT=90n) +Rdiode d1 21 1.99m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.04n +.MODEL DGD D(M=2.4 CJO=1.04n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 4.13n + +.ENDS IPS12CN10L_L0 + +****** + +.SUBCKT IPP16CN10L_L0 drain gate source + +Lg gate g1 4n +Ld drain d1 2n +Ls source s1 4n +Rs s1 s2 908u + +Rg g1 g2 1.2 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 140.4 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 10.8m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.75n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=11.7p N=1.07 RS=3.25u EG=1.12 TT=90n) +Rdiode d1 21 2.68m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.77n +.MODEL DGD D(M=2.4 CJO=0.77n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.08n + +.ENDS IPP16CN10L_L0 + +****** + +.SUBCKT BSC082N10LS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 255.6 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.75m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.18n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.07 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 1.47m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 1.405n +.MODEL DGD D(M=2.4 CJO=1.405n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 5.55n + +.ENDS BSC082N10LS_L0 + +****** + +.SUBCKT BSC123N10LS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 0.8 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 164.3 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.95m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.05n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.07 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 2.29m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.905n +.MODEL DGD D(M=2.4 CJO=0.905n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 3.59n + +.ENDS BSC123N10LS_L0 + +****** + +.SUBCKT BSC205N10LS_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 97.3 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 15.1m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.21n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.07 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 3.87m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.538n +.MODEL DGD D(M=2.4 CJO=0.538n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.15n + +.ENDS BSC205N10LS_L0 + +****** + + +.SUBCKT BSC105N10LSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 450u + +Rg g1 g2 1.3 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 125.6 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 5.54m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=3.25n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=21.3p N=1.07 RS=1.78u EG=1.12 TT=90n) +Rdiode d1 21 1.47m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.699n +.MODEL DGD D(M=2.4 CJO=0.699n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 2.85n + +.ENDS BSC105N10LSF_L0 + +****** + +.SUBCKT BSC159N10LSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 349u + +Rg g1 g2 1.0 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 80.7 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 8.61m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=2.09n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=13.7p N=1.07 RS=2.78u EG=1.12 TT=90n) +Rdiode d1 21 2.29m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.451n +.MODEL DGD D(M=2.4 CJO=0.451n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.87n + +.ENDS BSC159N10LSF_L0 + +****** + +.SUBCKT BSC265N10LSF_L0 drain gate source + +Lg gate g1 2n +Ld drain d1 0.5n +Ls source s1 1n +Rs s1 s2 276u + +Rg g1 g2 1.5 +M1 d2 g2 s2 s2 DMOS L=1u W=1u +.MODEL DMOS NMOS ( KP= 47.8 VTO=2.7 THETA=0 VMAX=1.5e5 ETA=0.005 LEVEL=3) +Rd d1 d2 14.53m TC=9.5m + +Dbd s2 d2 Dbt +.MODEL Dbt D(BV=131 M=0.35 CJO=1.24n VJ=0.8V) +Dbody s2 21 DBODY +.MODEL DBODY D(IS=8.1p N=1.07 RS=4.68u EG=1.12 TT=90n) +Rdiode d1 21 3.87m TC=4m + +.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) +Maux g2 c a a sw +Maux2 b d g2 g2 sw +Eaux c a d2 g2 1 +Eaux2 d g2 d2 g2 -1 +Cox b d2 0.269n +.MODEL DGD D(M=2.4 CJO=0.269n VJ=10) +Rpar b d2 1Meg +Dgd a d2 DGD +Rpar2 d2 a 10Meg +Cgs g2 s2 1.15n + +.ENDS BSC265N10LSF_L0 + +****** diff --git a/spice/test/opa836_a.lib b/spice/test/opa836_a.lib new file mode 100755 index 0000000..e55b7be --- /dev/null +++ b/spice/test/opa836_a.lib @@ -0,0 +1,324 @@ +* OPA836 - Rev. A +* Created by Sean Cashin; 2020-03-24 +* Created with Green-Williams-Lis Current Sense Amp Macro-model Architecture +* Copyright 2020 by Texas Instruments Corporation +****************************************************** +* MACRO-MODEL SIMULATED PARAMETERS: +****************************************************** +* AC PARAMETERS +********************** +* CLOSED-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zout vs. Freq.) +* CLOSED-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Acl vs. Freq.) +* COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR vs. Freq.) +* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR vs. Freq.) +* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en vs. Freq.) +********************** +* DC PARAMETERS +********************** +* INPUT COMMON-MODE VOLTAGE RANGE (Vcm) +* GAIN ERROR (Eg) +* INPUT BIAS CURRENT VS. INPUT COMMON-MODE VOLTAGE (Ib vs. Vcm) +* INPUT OFFSET VOLTAGE VS. TEMPERATURE (Vos vs. Temp) +* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vout vs. Iout) +* SHORT-CIRCUIT OUTPUT CURRENT (Isc) +* QUIESCENT CURRENT (Iq) +********************** +* TRANSIENT PARAMETERS +********************** +* SLEW RATE (SR) +* SETTLING TIME VS. CAPACITIVE LOAD (ts) +* OVERLOAD RECOVERY TIME (tor) +****************************************************** +.subckt OPA836 IN+ IN- OUT VCC VEE Vnot_pd +****************************************************** +.MODEL R_NOISELESS RES (T_ABS=-273.15) +C_C1 LN CLAMP 4.33E-9 +C_C1A16 N1102900 N1102910 16.12E-9 +C_C1A17 N1102916 N709248 159.2E-12 +C_C1A33 N1106172 N1106182 16.12E-9 +C_C1A34 N1106188 N706294 159.2E-12 +C_C33 N406634 0 1E-15 +C_C34 N317950 0 1 +C_C35 N406794 0 1E-15 +C_C39 N1252259 N1252249 350E-9 +C_C41 N1268170 N1268207 80E-15 +C_C44 N1464277 LN 100E-12 +C_C45 LN N1464195 400E-12 +C_C46 LN N1464227 170E-12 +C_C47 N1480336 N1480326 20E-15 +C_C48 N1682969 LN 200P +C_C7 N31014 LN 1P +C_C_CMN LN ESDN 1.2E-12 +C_C_CMN1 ESDN ESDP 1E-12 +C_C_CMP ESDP LN 1.2E-12 +C_C_VIMON LN VIMON 1E-9 +C_C_VOUT_S LN VOUT_S 1E-12 +E_E3 N112292 LN OUT LN 1 +E_E6 LN 0 N317950 0 1 +E_E7 VCCC 0 VCC 0 1 +E_E8 VEEE 0 VEE 0 1 +G_G100 N1480326 LN N1268170 LN -10 +G_G101 LP LN N1464227 LN -1 +G_G102 N1464195 LN CLAMP LN -1 +G_G103 N1464227 LN N1464195 LN -1 +G_G104 N1254878 LN N1480336 LN -240 +G_G106 N1106172 LN VEE_B LN -403E-3 +G_G107 VCC_CLP VEEE VCC_B VEE_B -1 +G_G108 VEE_CLP VCCC VCC_B VEE_B 1 +G_G109 N1619882 0 VIMON LN 15 +G_G110 0 VEE_CLP LN VIMON 6 +G_G111 VCC VEE N1682969 LN 1E-3 +G_G36 VCC_B 0 VCC 0 -1 +G_G37 VEE_B 0 VEE 0 -1 +G_G6 N25816 N11984 N709248 N706294 -1E-3 +G_G77 N1106188 LN N1106182 LN -2 +G_G87 N1102900 LN VCC_B LN -403E-3 +G_G88 N1102916 LN N1102910 LN -2 +G_G96 N1252249 LN N1464277 ZOUT -90.91 +G_G98 N1263527 LN N1252259 LN -22 +I_I1 VNOT_PD 0 DC 20N +I_I_B N06456 LN DC 650E-9 +I_I_OS ESDN LN DC 620E-9 +I_I_Q VCC VEE DC 5E-6 +L_L1 LP N1464277 1E-9 +R_R1 ESDP IN+ R_NOISELESS 10E-3 +R_R10 ESDN N11991 R_NOISELESS 1E-3 +R_R107 VCC_B 0 R_NOISELESS 1 +R_R108 N317950 0 R_NOISELESS 1E12 +R_R109 VEE_B 0 R_NOISELESS 1 +R_R110 VCC_B N406634 R_NOISELESS 1E-3 +R_R111 N406634 N317950 R_NOISELESS 1E6 +R_R112 N317950 N406794 R_NOISELESS 1E6 +R_R113 N406794 VEE_B R_NOISELESS 1E-3 +R_R148 N1102916 LN R_NOISELESS 1 +R_R162 ESDN ESDP R_NOISELESS 200E3 +R_R183 N1102900 LN R_NOISELESS 1 +R_R185 N1106172 LN R_NOISELESS 1 +R_R186 N1106188 LN R_NOISELESS 1 +R_R1A16 N1102916 N709248 R_NOISELESS 10E3 +R_R1A31 N1102900 N1102910 R_NOISELESS 10E3 +R_R1A33 N1106172 N1106182 R_NOISELESS 10E3 +R_R1A34 N1106188 N706294 R_NOISELESS 10E3 +R_R2 ESDN IN- R_NOISELESS 10E-3 +R_R208 N1252259 N1252249 R_NOISELESS 10E3 +R_R209 LN N1252249 R_NOISELESS 1 +R_R21 N11984 N25816 R_NOISELESS 1E3 +R_R210 LN N1252259 R_NOISELESS 500 +R_R211 LN N1254878 R_NOISELESS 1 +R_R212 LN ZOUT R_NOISELESS 3000 +R_R213 ZOUT N1254878 R_NOISELESS 30000 +R_R218 LN N1263527 R_NOISELESS 1 +R_R219 LN N1268207 R_NOISELESS 10E3 +R_R220 N1268170 N1263527 R_NOISELESS 90E3 +R_R226 LN N1464277 R_NOISELESS 14 +R_R230 LN N1464195 R_NOISELESS 1 +R_R231 LN N1464227 R_NOISELESS 1 +R_R243 N1480336 N1480326 R_NOISELESS 10E3 +R_R244 LN N1480326 R_NOISELESS 1 +R_R245 LN N1480336 R_NOISELESS 20 +R_R248 VCC_CLP N1619882 R_NOISELESS 1E-3 +R_R25 LN N28602 R_NOISELESS 1E9 +R_R251 LN LP R_NOISELESS 1 +R_R254 LN AOLNET R_NOISELESS 1E6 +R_R255 LN N1682945 R_NOISELESS 1 +R_R26 N30136 LN R_NOISELESS 1E9 +R_R27 LN N30913 R_NOISELESS 1 +R_R28 N31014 N30913 R_NOISELESS 1E-3 +R_R2A17 N1102910 LN R_NOISELESS 99.73 +R_R2A18 N709248 LN R_NOISELESS 5 +R_R2A34 N1106182 LN R_NOISELESS 99.73 +R_R2A35 N706294 LN R_NOISELESS 5 +R_R3 LN ESDP R_NOISELESS 200E3 +R_R4 ESDN LN R_NOISELESS 200E3 +R_R8 N638941 N11006 R_NOISELESS 1E3 +R_R81 LN VIMON R_NOISELESS 1 +R_R83 LN N112292 R_NOISELESS 1E9 +R_R9 N11006 N11984 R_NOISELESS 1E-3 +R_R_VOUT_S VOUT_S N112292 R_NOISELESS 100 +V_V4 N1682557 LN 1VDC +V_VCM_MAX N30136 VCC_B -1.1 +V_VCM_MIN N28602 VEE_B -0.2 +X_ESD_OUT OUT VCC VEE ESD_OUT_OPA836 +X_E_N ESDP N06456 VNSE_OPA836 +X_F1 VOUT OUT LN VIMON 08_OP_AMP_COMPLETE_F1_OPA836 +X_IQ_N LN VIMON LN VEE IQ_SRC_OPA836 +X_IQ_P VIMON LN VCC LN IQ_SRC_OPA836 +X_I_NP1 ESDN LN FEMT_OPA836 +X_S10 OUT VCC_CLP LN LP 08_OP_AMP_COMPLETE_S10_OPA836 +X_S11 VNOT_PD VEEE N1682945 N1682557 08_OP_AMP_COMPLETE_S11_OPA836 +X_S12 N1682969 N1682945 N1682969 N1682945 08_OP_AMP_COMPLETE_S12_OPA836 +X_S13 N1682969 LN AOLNET LN 08_OP_AMP_COMPLETE_S13_OPA836 +X_S14 N1682969 LN VOUT ZOUT 08_OP_AMP_COMPLETE_S14_OPA836 +X_S3 VIMON LN VCC_CLP VEEE 08_OP_AMP_COMPLETE_S3_OPA836 +X_S4 LN VIMON VEE_CLP VCCC 08_OP_AMP_COMPLETE_S4_OPA836 +X_S7 VEE_CLP OUT CLAMP LN 08_OP_AMP_COMPLETE_S7_OPA836 +X_S8 OUT VCC_CLP CLAMP LN 08_OP_AMP_COMPLETE_S8_OPA836 +X_S9 VEE_CLP OUT LN LP 08_OP_AMP_COMPLETE_S9_OPA836 +X_U1 LN N06456 FEMT_OPA836 +X_U2 N31014 N11991 AOLNET LN AOL_1_OPA836 +X_U3 AOLNET LN CLAMP LN AOL_2_OPA836 +X_VCM_CLAMP N25816 LN N30913 LN N30136 N28602 VCM_CLAMP_OPA836 +X_VOS_DRIFT N749288 N06456 VOS_DRIFT_OPA836 +X_VOS_VS_VCM N638941 N749288 VCC VEE VOS_VS_VCM_OPA836 +.ENDS OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_F1_OPA836 1 2 3 4 +F_F1 3 4 VF_F1 1 +VF_F1 1 2 0V +.ENDS 08_OP_AMP_COMPLETE_F1_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S10_OPA836 1 2 3 4 +S_S10 3 4 1 2 _S10 +RS_S10 1 2 1G +.MODEL _S10 VSWITCH ROFF=2E6 RON=1E-3 VOFF=-0.1 VON=0.06 +.ENDS 08_OP_AMP_COMPLETE_S10_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S11_OPA836 1 2 3 4 +S_S11 3 4 1 2 _S11 +RS_S11 1 2 1G +.MODEL _S11 VSWITCH ROFF=1E9 RON=1E-3 VOFF=0.7 VON=2.1 +.ENDS 08_OP_AMP_COMPLETE_S11_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S12_OPA836 1 2 3 4 +S_S12 3 4 1 2 _S12 +RS_S12 1 2 1G +.MODEL _S12 VSWITCH ROFF=700 RON=250 VOFF=-0.3 VON=0.1 +.ENDS 08_OP_AMP_COMPLETE_S12_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S13_OPA836 1 2 3 4 +S_S13 3 4 1 2 _S13 +RS_S13 1 2 1G +.MODEL _S13 VSWITCH ROFF=0.001 RON=1E6 VOFF=0.3 VON=0.7 +.ENDS 08_OP_AMP_COMPLETE_S13_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S14_OPA836 1 2 3 4 +S_S14 3 4 1 2 _S14 +RS_S14 1 2 1G +.MODEL _S14 VSWITCH ROFF=10MEG RON=21E-3 VOFF=0.3 VON=0.7 +.ENDS 08_OP_AMP_COMPLETE_S14_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S3_OPA836 1 2 3 4 +S_S3 3 4 1 2 _S3 +RS_S3 1 2 1G +.MODEL _S3 VSWITCH ROFF=1 RON=1E-3 VOFF=55E-3 VON=80E-3 +.ENDS 08_OP_AMP_COMPLETE_S3_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S4_OPA836 1 2 3 4 +S_S4 3 4 1 2 _S4 +RS_S4 1 2 1G +.MODEL _S4 VSWITCH ROFF=1 RON=1E-3 VOFF=55E-3 VON=80E-3 +.ENDS 08_OP_AMP_COMPLETE_S4_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S7_OPA836 1 2 3 4 +S_S7 3 4 1 2 _S7 +RS_S7 1 2 1G +.MODEL _S7 VSWITCH ROFF=2E6 RON=1E-3 VOFF=-0.1 VON=0.06 +.ENDS 08_OP_AMP_COMPLETE_S7_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S8_OPA836 1 2 3 4 +S_S8 3 4 1 2 _S8 +RS_S8 1 2 1G +.MODEL _S8 VSWITCH ROFF=2E6 RON=1E-3 VOFF=-0.1 VON=0.06 +.ENDS 08_OP_AMP_COMPLETE_S8_OPA836 +* +.SUBCKT 08_OP_AMP_COMPLETE_S9_OPA836 1 2 3 4 +S_S9 3 4 1 2 _S9 +RS_S9 1 2 1G +.MODEL _S9 VSWITCH ROFF=2E6 RON=1E-3 VOFF=-0.1 VON=0.06 +.ENDS 08_OP_AMP_COMPLETE_S9_OPA836 +* +.SUBCKT AOL_1_OPA836 VC+ VC- IOUT+ IOUT- +.PARAM GAIN = 1E-4 +.PARAM IPOS = .5 +.PARAM INEG = -.5 +G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)} +.ENDS AOL_1_OPA836 +* +.SUBCKT AOL_2_OPA836 VC+ VC- IOUT+ IOUT- +.PARAM GAIN = 0.0286 +.PARAM IPOS = 1.96 +.PARAM INEG = -2.03 +G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)} +.ENDS AOL_2_OPA836 +* +.SUBCKT ESD_OUT_OPA836 OUT VCC VEE +.MODEL ESD_SW VSWITCH(RON=50 ROFF=1E12 VON=500E-3 VOFF=450E-3) +S1 VCC OUT OUT VCC ESD_SW +S2 OUT VEE VEE OUT ESD_SW +.ENDS ESD_OUT_OPA836 +* +.SUBCKT FEMT_OPA836 1 2 +.PARAM FLWF=1 +.PARAM NLFF=100 +.PARAM NVRF=0.75 +.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164} +.PARAM RNVF={1.184*PWR(NVRF,2)} +.MODEL DNVF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16 +I1 0 7 10E-3 +I2 0 8 10E-3 +D1 7 0 DNVF +D2 8 0 DNVF +E1 3 6 7 8 {GLFF} +R1 3 0 1E9 +R2 3 0 1E9 +R3 3 6 1E9 +E2 6 4 5 0 10 +R4 5 0 {RNVF} +R5 5 0 {RNVF} +R6 3 4 1E9 +R7 4 0 1E9 +G1 1 2 3 4 1E-6 +.ENDS FEMT_OPA836 +* +.SUBCKT IQ_SRC_OPA836 VC+ VC- IOUT+ IOUT- +.PARAM GAIN = 1E-3 +G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )} +.ENDS IQ_SRC_OPA836 +* +.SUBCKT VCM_CLAMP_OPA836 VIN+ VIN- IOUT- IOUT+ VP+ VP- +.PARAM GAIN = 1 +G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))} +.ENDS VCM_CLAMP_OPA836 +* +.SUBCKT VNSE_OPA836 1 2 +.PARAM FLW=1 +.PARAM NLF=75 +.PARAM NVR=4.6 +.PARAM GLF={PWR(FLW,0.25)*NLF/1164} +.PARAM RNV={1.184*PWR(NVR,2)} +.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16 +I1 0 7 10E-3 +I2 0 8 10E-3 +D1 7 0 DVN +D2 8 0 DVN +E1 3 6 7 8 {GLF} +R1 3 0 1E9 +R2 3 0 1E9 +R3 3 6 1E9 +E2 6 4 5 0 10 +R4 5 0 {RNV} +R5 5 0 {RNV} +R6 3 4 1E9 +R7 4 0 1E9 +E3 1 2 3 4 1 +.ENDS VNSE_OPA836 +* +.SUBCKT VOS_DRIFT_OPA836 VOS+ VOS- +.PARAM DC = 45.12E-6 +.PARAM POL = 1 +.PARAM DRIFT = 20E-6 +E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)} +.ENDS VOS_DRIFT_OPA836 +* +.SUBCKT VOS_VS_VCM_OPA836 V+ V- REF+ REF- +E1 V+ 1 TABLE {(V(REF+, V-))} = ++(0.35, 450E-6) ++(0.4, 435E-6) ++(0.55, 275E-6) ++(0.65, 150E-6) ++(0.75, 75E-6) ++(0.85, 25E-6) ++(1, 0) +V1 1 V- 0 +.ENDS VOS_VS_VCM_OPA836 +* \ No newline at end of file