diff --git a/bh.kicad_sym b/bh.kicad_sym
index 39bbb51..594c659 100755
--- a/bh.kicad_sym
+++ b/bh.kicad_sym
@@ -19940,6 +19940,18 @@
     (property "Populate" "" (at 0 0 0)
       (effects (font (size 1.27 1.27)))
     )
+    (property "Sim.Library" "common/spice/ti/SN74AHCT1G125.lib" (at 0 0 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Sim.Name" "SN74AHCT1G125" (at 0 0 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Sim.Device" "SUBCKT" (at 0 0 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Sim.Pins" "1=OE 2=A 3=GND 4=Y 5=VCC" (at 0 0 0)
+      (effects (font (size 1.27 1.27)))
+    )
     (property "ki_description" "IC, Logic, Buffer, Tri-state, Single, Low Enable, SOT-353" (at 0 0 0)
       (effects (font (size 1.27 1.27)) hide)
     )
diff --git a/spice/ti/SN74AHCT1G125.lib b/spice/ti/SN74AHCT1G125.lib
new file mode 100644
index 0000000..17cf68f
--- /dev/null
+++ b/spice/ti/SN74AHCT1G125.lib
@@ -0,0 +1,60 @@
+* SN74AHCT1G125
+*****************************************************************************
+* (C) Copyright 2014 Texas Instruments Incorporated. All rights reserved.                                            
+*****************************************************************************
+** This model is designed as an aid for customers of Texas Instruments.
+** TI and its licensors and suppliers make no warranties, either expressed
+** or implied, with respect to this model, including the warranties of 
+** merchantability or fitness for a particular purpose.  The model is
+** provided solely on an "as is" basis.  The entire risk as to its quality
+** and performance is with the customer.
+*****************************************************************************
+*
+** Released by: WEBENCH(R) Design Center, Texas Instruments Inc.
+* Part: SN74AHCT1G125
+* Date: 11/21/2014
+* Model Type: Transient
+* Simulator: Pspice
+* Simulator Version: Pspice 16.2.0.s003
+* EVM Order Number: N/A 
+* EVM Users Guide: N/A
+* Datasheet: SCLS378L, 24 June 2005
+*
+* Model Version: 1.0
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Version 1.0 : New model
+*
+************************************************************************* 
+************************************************************************
+*$
+.SUBCKT SN74AHCT1G125 OE A GND Y VCC
+R_RA         A 0  50e06 TC=0,0 
+C_CA         A 0  4e-12  TC=0,0 
+R_ROE        OE 0  50e06 TC=0,0
+C_COE        OE 0  4e-12  TC=0,0 
+X_U1         OE A GND Y_INT1 VCC SN74AHCT1G125_BUF 
+R_Rpu        VCC OE  50e06 TC=0,0 
+X_S1    OE N07928 Y Y_INT1 SN74AHCT1G125_S1 
+V_V1         N07928 GND 0.8Vdc
+C_CO         Y 0  10p  TC=0,0 
+.ENDS
+*$
+***
+.subckt SN74AHCT1G125_S1 1 2 3 4  
+S_S1         3 4 1 2 _S1
+RS_S1         1 2 1G
+.MODEL         _S1 VSWITCH Roff=20e6 Ron=1.0 Voff=1.2V Von=0.0V
+.ends SN74AHCT1G125_S1
+*$
+***
+.SUBCKT SN74AHCT1G125_BUF OE A GND Y VCC
+ETHRESH THRESH GND VALUE={0.5*V(VCC)}
+RCC VCC GND 5e06
+EO NO GND VALUE = {IF(V(A) > V(THRESH) & V(OE) < V(THRESH),V(VCC,GND), V(GND))}
+RO NO Y 39
+.ENDS
+*$
diff --git a/spice/ti/SN74AHCT1G125_behavioral.lib b/spice/ti/SN74AHCT1G125_behavioral.lib
new file mode 100644
index 0000000..bf969df
--- /dev/null
+++ b/spice/ti/SN74AHCT1G125_behavioral.lib
@@ -0,0 +1,201 @@
+********************************************************************************
+* SN74AHCT1G125.cir
+* 2.0
+* 2019-11-14 00:00:00
+* Texas Instruments Incorporated.
+* Standard Logic, SLHR
+* 12500 TI Blvd
+* Dallas, TX -75243
+*
+* Revision History:
+* Rev 2.0: 01/01/2019
+* - Model generated from datasheet values
+* - Built using generic logic gate behavioral pspice model V2
+* - Built using an automated model which generalizes parts under same family
+* - Performance is expected typical behavior at 25C
+* - Written for and tested with Tina-TI Version 9.3.100.244 SF-TI
+* - Accurate power consumption with dyanmic as well as static Icc
+*
+********************************************************************************
+*[Disclaimer]
+* This model is designed as an aid for customers of Texas Instruments.
+* TI and its licensors and suppliers make no warranties, either expressed
+* or implied, with respect to this  model, including the warranties of
+* merchantability or fitness for a particular purpose. The model is
+* provided solely on an "as is" basis. The entire risk as to its quality
+* and performance is with the customer.
+*
+*[Copyright]
+*(C) Copyright 2019 Texas Instruments Incorporated.All rights reserved.
+*
+*
+********************************************************************************
+*                                 SN74AHCT1G125
+********************************************************************************
+ 
+.SUBCKT SN74AHCT1G125 Y A OEZ VCC AGND
+XU1 Y A VCC OEZ VCC AGND LOGIC_GATE_2PIN_TRI_STATE_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 
+.ENDS 
+ 
+ 
+ 
+ 
+.SUBCKT LOGIC_GATE_2PIN_TRI_STATE_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 OUT A B OEZ VCC GND
+ 
+.PARAM VCC_ABS_MAX = 7 
+.PARAM VCC_MAX = 5.5 
+.PARAM RA = 880000000 
+.PARAM RB = 880000000 
+.PARAM CA = 1e-11 
+.PARAM CB = 1e-11 
+.PARAM ROEZ = 2000 
+.PARAM COEZ = 3e-12 
+RA  A  GND {RA} 
+RB  B  GND {RB} 
+CA  A  GND {CA} 
+CB  B  GND {CB} 
+ROEZ OEZ GND {ROEZ} 
+COEZ OEZ GND {COEZ} 
+XUA NA A VCC GND LOGIC_INPUT_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 
+XUB NB B VCC GND LOGIC_INPUT_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 
+XUOEZ NOEZ OEZ VCC GND LOGIC_INPUT_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 
+XUG NA NB NOUTG VCC GND LOGIC_FUNCTION_2_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 
+XOUTPD NOUTG NOUTTPD VCC GND TPD_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 
+XUOUT NOUTTPD NOUT_INT NOEZ VCC GND LOGIC_TRI_STATE_OUTPUT_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 
+XICC VCC GND NVIOUT LOGIC_ICC_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 
+SICC VCC GND VCC GND SW1 
+H1 NVIOUT GND VIOUT 1  
+VIOUT NOUT_INT OUTsw 0  
+SIOFF OUTsw OUT VCC GND SW2 
+DA2 GND A D1 
+DB2 GND B D1 
+DO2 GND OUT D1 
+DOE1 NOEZ VCC D1 
+DOE2 GND OEZ D1 
+RDA1 NA1 GND 1e6
+SDA1 NA1 A VCC GND SW2
+RDB1 NB1 GND 1e6
+SDB1 NB1 B VCC GND SW2
+RDO1 NO1 GND 1e6
+SDO1 NO1 OUT VCC GND SW2
+.MODEL SW1 VSWITCH VON = {VCC_ABS_MAX} VOFF = {VCC_MAX} RON = 10 ROFF = 60e6 
+.MODEL SW2 VSWITCH VON = {0.55} VOFF = {0.45} RON = 10m ROFF = 100e6 
+.MODEL D1 D 
+.ENDS 
+.SUBCKT LOGIC_INPUT_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 OUT IN VCC VEE
+.PARAM STANDARD_INPUT_SELECT = 1 
+ 
+.PARAM SCHMITT_TRIGGER_INPUT_SELECT = 0 
+ESTD_THR VSTD_THR VEE TABLE {V(VCC,VEE)} = 
++(1,0.5) 
++(1.8,0.9) 
++(2.5,1.25) 
++(3.3,1.65) 
++(5,2.5) 
++(6,3) 
+ETRP_P VTRP_P VEE TABLE {V(VCC,VEE)} = 
++(3,1.8) 
++(4.5,2.8) 
++(5.5,3.5) 
+ETRP_N VTRP_N VEE TABLE {V(VCC,VEE)} = 
++(3,1.2) 
++(4.5,2) 
++(5.5,2.7) 
+EHYST VHYST VEE TABLE {V(VCC,VEE)} = 
++(3,0.3) 
++(4.5,0.4) 
++(5.5,0.5) 
+ETRUE NTRUE VEE VALUE = {V(VCC,VEE)} 
+EFALSE NFALSE VEE VALUE = {0} 
+EBETA BETA VEE VALUE = {V(VHYST,VEE)/(V(NTRUE,VEE) - V(NFALSE,VEE) + V(VHYST,VEE))} 
+EFB NFB VEE VALUE = {(1 - V(BETA,VEE))*V(IN,VEE) + V(BETA,VEE)*V(CURR_OUT,VEE)} 
+EREF NREF VEE VALUE = {0.5*(1 - V(BETA,VEE))*(V(VTRP_P,VEE) + V(VTRP_N,VEE))  
++ + 0.5*V(BETA,VEE)*(V(NTRUE,VEE) + V(NFALSE,VEE))} 
+EDIFF NDIFF VEE VALUE = {V(NFB,NREF)} 
+ESWITCH VSWITCH VEE VALUE = {0.5*(-SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))} 
+ESWITCH1 VSWITCH1 VEE VALUE = {0.5*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))} 
+GCOMP VEE CURR_OUT VALUE = {SCHMITT_TRIGGER_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))} 
+GSTD VEE CURR_OUT VALUE = {STANDARD_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(IN,VSTD_THR)) + ABS(SGN(V(IN,VSTD_THR))))} 
+ROUT CURR_OUT VEE 1 
+EMID MID VEE VALUE = {0.5*(V(VCC,VEE) + V(VEE))} 
+EARG NARG VEE VALUE = {V(CURR_OUT,VEE) - V(MID,VEE)} 
+EOUT OUT VEE VALUE = {0.5*(SGN(V(NARG,VEE)) + ABS(SGN(V(NARG,VEE) ) ) )} 
+.PARAM MAXICC = maxICC 
+.PARAM VT = .7 
+.PARAM VCC_MIN = 4.5 
+ 
+EV_VT1 VTN VEE VALUE = { VT } 
+EV_VT2 VTP VEE VALUE = { V(VCC,VEE) - VT } 
+ 
+ETEST TEST VEE VALUE = {.9*V(VCC,VEE)} 
+ 
+EVTHDIFF VTH_DIFF VEE VALUE = {V(IN,VSTD_THR)} 
+EVTHPDIFF VTHP_DIFF VEE VALUE = {V(IN,VTRP_P)} 
+EVTHNDIFF VTHN_DIFF VEE VALUE = {V(IN,VTRP_N)} 
+EVTNDIFF VTN_DIFF VEE VALUE = { V(IN,VTN) } 
+EVTPDIFF VTP_DIFF VEE VALUE = { V(IN,VTP) } 
+ 
+ 
+GICCVA VCC VEE VALUE = { (-ABS(( (1+SGN(V(VTN_DIFF,VEE)) ) )/2 -1) * 
++ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
+GICCVB VCC VEE VALUE = { (ABS(( (1+SGN(V(VTHP_DIFF,VEE)) ) )/2 -1) * 
++ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
+GICCVC VCC VEE VALUE = { ( ABS(  (1+SGN(V(VTHN_DIFF,VEE)) ) )/2  * 
++ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
+GICCVD VCC VEE VALUE = { (-ABS(  (1+SGN(V(VTP_DIFF,VEE)) ) )/2  * 
++ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
+ 
+.ENDS 
+.SUBCKT LOGIC_FUNCTION_2_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 A B OUT VCC VEE
+.PARAM AND  = 1 
+.PARAM NAND = 0 
+.PARAM OR   = 0 
+.PARAM NOR  = 0 
+.PARAM XOR  = 0 
+.PARAM XNOR = 0 
+GAND  VEE N1 VALUE = {AND*V(A,VEE)*V(B,VEE)} 
+GNAND VEE N1 VALUE = {NAND*(1 - V(A,VEE)*V(B,VEE))} 
+GOR   VEE N1 VALUE = {OR*(MIN(V(A,VEE) + V(B,VEE),1))} 
+GNOR  VEE N1 VALUE = {NOR*(1 - MIN(V(A,VEE) + V(B,VEE),1))} 
+GXOR  VEE N1 VALUE = {XOR*((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE)))} 
+GXNOR VEE N1 VALUE = {XNOR*(1 - ((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE))))} 
+RN1 N1 VEE 1 
+EOUT OUT VEE N1 VEE 1 
+.ENDS 
+.SUBCKT TPD_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 IN OUT VCC VEE
+.PARAM TPDELAY1 = 1N 
+.PARAM RS = 10K 
+.PARAM CS = {-TPDELAY1/(RS*LOG(0.5))} 
+ETPDNORM NTPDNORM VEE TABLE {V(VCC,VEE)} = 
++(3.3,5.75) 
++(5,4) 
+G1 IN N1 VALUE = {V(IN,N1)/(V(NTPDNORM,VEE)*RS)} 
+RZ IN N1 10G 
+C1 N1 VEE {CS} 
+E1 N2 VEE VALUE = {0.5*(1 + SGN(V(N1,VEE) - 0.5))} 
+EOUT OUT VEE N2 VEE 1 
+.ENDS 
+.SUBCKT LOGIC_TRI_STATE_OUTPUT_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 IN OUT OEZ VCC VEE
+EROH NROH VEE TABLE {V(VCC,VEE)} = 
++(2,0) 
++(3,105) 
++(4.5,70) 
+EROL NROL VEE TABLE {V(VCC,VEE)} = 
++(2,2000) 
++(3,90) 
++(4.5,46.25) 
+EOEZ N2 VEE VALUE = {1 - V(OEZ,VEE)} 
+E1 N1 VEE VALUE = {V(VCC,VEE)*V(IN,VEE)*V(N2,VEE)} 
+GOUT N1 OUT VALUE = {V(N1,OUT)*V(N2,VEE)*(V(IN,VEE)/V(NROH,VEE) + (1 - V(IN,VEE))/V(NROL,VEE))} 
+LOUT N1 OUT .1n 
+ROUT OUT VEE 1E8 
+.ENDS 
+.SUBCKT LOGIC_ICC_AHC_1i_AND_Tristate_CMOS_SN74AHCT1G125 VCC VEE VIOUT
+.PARAM ICC = 1.25e-07 
+.PARAM VCC_MAX = 5.5 
+.PARAM VCC_MIN = 4.5 
+GICC VCC VEE VALUE = {ICC*0.5*(1 + SGN(V(VCC,VEE) - VCC_MIN))} 
+EGNDF GNDF 0 VALUE = {0.5*(V(VCC) + V(VEE))} 
+GOUTP VCC GNDF VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))} 
+GOUTN GNDF VEE VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))} 
+.ENDS