Merge remote-tracking branch 'origin/dev'
This commit is contained in:
commit
6208f236f8
85
bh.kicad_sym
85
bh.kicad_sym
|
|
@ -13958,6 +13958,32 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(symbol "LTM4664_SIM" (in_bom yes) (on_board yes)
|
||||
(property "Reference" "U" (id 0) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "LTM4664_SIM" (id 1) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "" (id 2) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (id 3) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
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(property "Spice_Primitive" "X" (id 4) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Spice_Model" "LTM4664" (id 5) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Spice_Netlist_Enabled" "Y" (id 6) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/copy/sub/LTM4664.sub" (id 7) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
)
|
||||
(symbol "MT48LC64M8A2P-75C" (in_bom yes) (on_board yes)
|
||||
(property "Reference" "U" (id 0) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
|
|
@ -14608,7 +14634,16 @@
|
|||
(property "Populate" "" (id 8) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "ki_description" "Transistor, BJT, NPN" (id 9) (at 0 0 0)
|
||||
(property "Spice_Primitive" "Q" (id 9) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Spice_Netlist_Enabled" "Y" (id 10) (at 0 0 0)
|
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(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Spice_Node_Sequence" "C B E" (id 11) (at 0 0 0)
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||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_description" "Transistor, BJT, NPN" (id 12) (at 0 0 0)
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||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
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||||
(symbol "NPN_0_1"
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||||
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@ -15425,6 +15460,23 @@
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|||
)
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||||
)
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||||
)
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||||
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|
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|
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|
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|
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|
||||
(effects (font (size 1.27 1.27)) (justify left))
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||||
)
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||||
(property "Footprint" "" (id 2) (at 0 0 0)
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(effects (font (size 1.27 1.27)) hide)
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||||
(effects (font (size 1.27 1.27)) hide)
|
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|
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(effects (font (size 1.27 1.27)) hide)
|
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)
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||||
)
|
||||
(symbol "R" (pin_numbers hide) (pin_names (offset 0)) (in_bom yes) (on_board yes)
|
||||
(property "Reference" "R" (id 0) (at 2.032 0 90)
|
||||
(effects (font (size 1.27 1.27)))
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||||
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@ -15899,7 +15951,22 @@
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|||
(property "Populate" "" (id 8) (at 0 -1.27 0)
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||||
(effects (font (size 1.27 1.27)))
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||||
)
|
||||
(property "ki_description" "IC, Logic, NAND, Single, SOT-353" (id 9) (at 0 0 0)
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||||
(property "Spice_Primitive" "X" (id 9) (at 0 0 0)
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||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
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||||
(property "Spice_Model" "SN74LVC1G00" (id 10) (at 0 0 0)
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||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
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||||
(property "Spice_Netlist_Enabled" "Y" (id 11) (at 0 0 0)
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||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Spice_Node_Sequence" "Y A B VCC GND" (id 12) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/ti/SN74LVC1G00.cir" (id 13) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
|
||||
(property "ki_description" "IC, Logic, NAND, Single, SOT-353" (id 14) (at 0 0 0)
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||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
|
||||
(symbol "SN74LVC1G00DCKR_0_1"
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||||
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@ -24107,7 +24174,19 @@
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|||
(property "Populate" "" (id 8) (at 0 0 0)
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||||
(effects (font (size 1.27 1.27)))
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||||
)
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||||
(property "ki_description" "IC, Regulator, Linear, 1.2V 200MA, SC70-5" (id 9) (at 0 0 0)
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||||
(property "Spice_Primitive" "X" (id 9) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
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||||
(property "Spice_Model" "TLV70012" (id 10) (at 0 0 0)
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||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
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||||
(property "Spice_Netlist_Enabled" "Y" (id 11) (at 0 0 0)
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||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
|
||||
(property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/ti/TLV70012.lib" (id 12) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
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||||
(property "ki_description" "IC, Regulator, Linear, 1.2V 200MA, SC70-5" (id 13) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
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||||
)
|
||||
)
|
||||
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|
|||
149
diode.kicad_sym
Normal file
149
diode.kicad_sym
Normal file
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|
@ -0,0 +1,149 @@
|
|||
(kicad_symbol_lib (version 20220331) (generator kicad_symbol_editor)
|
||||
(symbol "D_SCHOTTKY" (pin_numbers hide) (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes)
|
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|
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(effects (font (size 1.27 1.27)))
|
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|
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(property "Value" "D_SCHOTTKY" (id 1) (at 0 -2.54 0)
|
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|
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|
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|
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(effects (font (size 1.27 1.27)) hide)
|
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|
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|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
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|
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|
||||
(effects (font (size 1.27 1.27)) hide)
|
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|
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|
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(effects (font (size 1.27 1.27)))
|
||||
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|
||||
(property "Supplier" "" (id 6) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
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)
|
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(property "SupplierPartNumber" "" (id 7) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
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)
|
||||
(property "Populate" "" (id 8) (at 0 0 0)
|
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(effects (font (size 1.27 1.27)))
|
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)
|
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(property "ki_description" "Diode, Schottky" (id 9) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_fp_filters" "TO-???* *SingleDiode *_Diode_* *SingleDiode* *:D_*" (id 10) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
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|
||||
(symbol "D_SCHOTTKY_0_1"
|
||||
(polyline
|
||||
(pts
|
||||
(xy -1.27 1.27)
|
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(xy -1.27 -1.27)
|
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)
|
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(stroke (width 0.2032) (type default))
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|
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|
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|
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(polyline
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(pts
|
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(xy -1.27 1.27)
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(xy -0.889 1.27)
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|
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(stroke (width 0.2032) (type default))
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(fill (type none))
|
||||
)
|
||||
(polyline
|
||||
(pts
|
||||
(xy 1.27 1.27)
|
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(xy 1.27 -1.27)
|
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(xy -1.27 0)
|
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(xy 1.27 1.27)
|
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)
|
||||
(stroke (width 0.2032) (type default))
|
||||
(fill (type none))
|
||||
)
|
||||
)
|
||||
(symbol "D_SCHOTTKY_1_1"
|
||||
(pin passive line (at 3.81 0 180) (length 2.54)
|
||||
(name "A" (effects (font (size 1.27 1.27))))
|
||||
(number "A" (effects (font (size 1.27 1.27))))
|
||||
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|
||||
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|
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|
||||
(number "K" (effects (font (size 1.27 1.27))))
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol "S115FA" (extends "D_SCHOTTKY")
|
||||
(property "Reference" "D" (id 0) (at 0 2.54 0)
|
||||
(effects (font (size 1.27 1.27)))
|
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
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(effects (font (size 1.27 1.27)) hide)
|
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|
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|
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|
||||
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|
||||
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|
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(effects (font (size 1.27 1.27)))
|
||||
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|
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|
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|
||||
)
|
||||
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|
||||
(effects (font (size 1.27 1.27)) hide)
|
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)
|
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|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
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|
||||
(property "ki_fp_filters" "TO-???* *SingleDiode *_Diode_* *SingleDiode* *:D_*" (id 9) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
)
|
||||
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|
||||
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|
||||
(effects (font (size 1.27 1.27)))
|
||||
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|
||||
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|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Footprint" "" (id 2) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
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|
||||
(property "Datasheet" "https://www.onsemi.com/pdf/datasheet/ss36fa-d.pdf" (id 3) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
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|
||||
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|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
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|
||||
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|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Spice_Netlist_Enabled" "Y" (id 6) (at 0 2.54 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Spice_Lib_File" "/home/brendan/Documents/projects/kicad_new/spice/onsemi/S310FA.LIB" (id 7) (at 0 2.54 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_description" "Diode, Schottky, 3A, 100V, SOD-123FL" (id 8) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "ki_fp_filters" "TO-???* *SingleDiode *_Diode_* *SingleDiode* *:D_*" (id 9) (at 0 0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
)
|
||||
)
|
||||
111
spice/adi/ad840.cir
Normal file
111
spice/adi/ad840.cir
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
* AD840 SPICE Macro-model
|
||||
* Description: Amplifier
|
||||
* Generic Desc: WIDEBAND,FAST SETTLING OP AMP
|
||||
* Developed by: AAG / PMI
|
||||
* Revision History: 08/10/2012 - Updated to new header style
|
||||
* 1.0 (01/1991)
|
||||
* Copyright 1991, 2012 by Analog Devices, Inc.
|
||||
*
|
||||
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
|
||||
* indicates your acceptance with the terms and provisions in the License Statement.
|
||||
*
|
||||
* BEGIN Notes:
|
||||
*
|
||||
* Not Modeled:
|
||||
*
|
||||
* Parameters modeled include:
|
||||
*
|
||||
* END Notes
|
||||
*
|
||||
* Node assignments
|
||||
* non-inverting input
|
||||
* | inverting input
|
||||
* | | positive supply
|
||||
* | | | negative supply
|
||||
* | | | | output
|
||||
* | | | | |
|
||||
.SUBCKT AD840 1 2 100 101 36
|
||||
*
|
||||
* INPUT STAGE & POLE AT 120 MHz
|
||||
*
|
||||
IOS 1 2 DC 0.05E-6
|
||||
CIN 1 2 2E-12
|
||||
R1 1 3 15E3
|
||||
R2 2 3 15E3
|
||||
EOS 9 1 POLY(1) 16 11 200E-6 1
|
||||
R3 100 5 223.38
|
||||
R4 100 6 223.38
|
||||
C2 5 6 2.9687E-12
|
||||
R5 7 4 171.66
|
||||
R6 8 4 171.66
|
||||
Q1 5 2 7 QX
|
||||
Q2 6 9 8 QX
|
||||
I1 4 101 DC 1E-3
|
||||
*
|
||||
* VIRTUAL NODE
|
||||
*
|
||||
RVN1 100 10 25E3
|
||||
RVN2 10 101 25E3
|
||||
*
|
||||
* GAIN STAGE & DOMINANT POLE AT 2.1923 KHz
|
||||
*
|
||||
EREF 11 0 10 0 1
|
||||
G1 11 12 5 6 4.4768E-3
|
||||
R7 12 11 29.039E6
|
||||
C3 12 11 2.5E-12
|
||||
V1 100 13 DC 2.4375
|
||||
D1 12 13 DX
|
||||
V2 14 101 DC 2.4375
|
||||
D2 14 12 DX
|
||||
*
|
||||
* COMMON-MODE GAIN NETWORK WITH ZERO AT 20 KHz
|
||||
*
|
||||
ECM 15 11 3 11 3.1623
|
||||
RCM1 15 16 1E6
|
||||
CCM 15 16 7.9577E-12
|
||||
RCM2 16 11 1
|
||||
*
|
||||
* NEGATIVE ZERO STAGE AT 290 MHz
|
||||
*
|
||||
EZ1 17 11 12 11 1E6
|
||||
RZ1 17 18 1
|
||||
CZ1 17 18 -548.81E-12
|
||||
RZ2 18 11 1E-6
|
||||
*
|
||||
* POLE STAGE AT 500 MHz
|
||||
*
|
||||
GP1 11 19 18 11 1E-6
|
||||
RP1 19 11 1E6
|
||||
CP1 19 11 318.31E-18
|
||||
*
|
||||
* OUTPUT STAGE
|
||||
*
|
||||
IDC 100 101 DC 8.9E-3
|
||||
VX 19 30
|
||||
V3 32 35 DC 2.725
|
||||
D3 30 32 DX
|
||||
V4 35 33 DC 2.575
|
||||
D4 33 30 DX
|
||||
D5 100 31 DX
|
||||
GO1 31 101 30 35 16.667E-3
|
||||
D6 101 31 DY
|
||||
D7 100 34 DX
|
||||
GO2 34 101 35 30 16.667E-3
|
||||
D8 101 34 DY
|
||||
RO1 100 35 60
|
||||
GO3 35 100 100 30 16.667E-3
|
||||
RO2 35 101 60
|
||||
GO4 101 35 30 101 16.667E-3
|
||||
LO 35 36 0.04E-6
|
||||
*
|
||||
* MODELS USED
|
||||
*
|
||||
.MODEL QX NPN(BF=142.86)
|
||||
.MODEL DX D(IS=1E-15)
|
||||
.MODEL DY D(IS=1E-15 BV=50)
|
||||
.ENDS
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
15
spice/onsemi/S115FA.LIB
Normal file
15
spice/onsemi/S115FA.LIB
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
*$
|
||||
*********** Discrete Rectifier Electrical Parameters ***********
|
||||
** Product: S115FA
|
||||
** Surface Mount Schottky Barrier Rectifiers
|
||||
**--------------------------------------------------------------
|
||||
.MODEL S115FA d
|
||||
+ IS=1.50696e-8 N=1.5 RS=0.256155
|
||||
+ ISR=5.320e-8 NR=1.5 TRS1=1.2125e-5
|
||||
+ TRS2=1.084e-7 CJO=9.55e-11 M=0.44017
|
||||
+ VJ=0.5105 BV=165 IBV=2.5e-4
|
||||
+ EG=0.785 TT=8.56e-9
|
||||
****************************************************************
|
||||
** Creation: Jun.-07-2017 Rev: 0.0
|
||||
** ON Semiconductor
|
||||
|
||||
16
spice/onsemi/S310FA.LIB
Normal file
16
spice/onsemi/S310FA.LIB
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
*$
|
||||
*********** Discrete Rectifier Electrical Parameters ***********
|
||||
** Product: S310FA
|
||||
** Package: SOD-123FL
|
||||
** Schottky Barrier Rectifiers
|
||||
****************************************************************
|
||||
.MODEL S310FA D
|
||||
+ IS=1.096e-08 N=1.0 RS=1.230e-1
|
||||
+ ISR=1.7e-8 NR=1.5 TRS1=1.05e-6
|
||||
+ TRS2=1.5e-8 CJO=2.2854e-10 M=0.47
|
||||
+ VJ=0.44 BV=110 IBV=2.5e-4
|
||||
+ TT=7.28e-9 XTI=-12.3 EG=1.16
|
||||
****************************************************************
|
||||
** Creation: Aug.-22-2019 Rev: 1.0
|
||||
** ON Semiconductor
|
||||
|
||||
26
spice/onsemi/SBC817-40L.LIB
Normal file
26
spice/onsemi/SBC817-40L.LIB
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
**************************************
|
||||
* Model Generated by MODPEX *
|
||||
*Copyright(c) Symmetry Design Systems*
|
||||
* All Rights Reserved *
|
||||
* UNPUBLISHED LICENSED SOFTWARE *
|
||||
* Contains Proprietary Information *
|
||||
* Which is The Property of *
|
||||
* SYMMETRY OR ITS LICENSORS *
|
||||
*Commercial Use or Resale Restricted *
|
||||
* by Symmetry License Agreement *
|
||||
**************************************
|
||||
* Model generated on Jul 29, 14
|
||||
* MODEL FORMAT: PSpice
|
||||
.MODEL Qbc81740lt1g npn
|
||||
+IS=1.61861e-13 BF=510.104 NF=0.990132 VAF=62.302
|
||||
+IKF=0.763922 ISE=7.67929e-10 NE=4 BR=38.021
|
||||
+NR=1.0751 VAR=2.67102 IKR=0.0671266 ISC=6.73996e-14
|
||||
+NC=1.07195 RB=2.53475 IRB=0.1 RBM=2.52145
|
||||
+RE=0.040147 RC=0.200735 XTB=1.04773 XTI=2.15473
|
||||
+EG=1.206 CJE=3.98362e-11 VJE=0.4 MJE=0.361957
|
||||
+TF=5.19286e-10 XTF=84.5359 VTF=0.289175 ITF=3.82303
|
||||
+CJC=1.16343e-11 VJC=0.4 MJC=0.269118 XCJC=0.891865
|
||||
+FC=0.8 CJS=0 VJS=0.75 MJS=0.5
|
||||
+TR=1e-07 PTF=0 KF=0 AF=1
|
||||
|
||||
|
||||
200
spice/ti/SN74LVC1G00.cir
Normal file
200
spice/ti/SN74LVC1G00.cir
Normal file
|
|
@ -0,0 +1,200 @@
|
|||
********************************************************************************
|
||||
* SN74LVC1G00.cir
|
||||
* 1.0
|
||||
* 2018-11-16 00:00:00
|
||||
* Texas Instruments Incorporated.
|
||||
* Standard Logic, SLHR
|
||||
* 12500 TI Blvd
|
||||
* Dallas, TX -75243
|
||||
*
|
||||
*
|
||||
* Revision History:
|
||||
* Rev 2.0: 01/01/2019
|
||||
* - Model generated from datasheet values
|
||||
* - Built using generic logic gate behavioral pspice model V2
|
||||
* - Built using an automated model which generalizes parts under same family
|
||||
* - Performance is expected typical behavior at 25C
|
||||
* - Written for and tested with Tina-TI Version 9.3.100.244 SF-TI
|
||||
* - Accurate power consumption with dyanmic as well as static Icc
|
||||
*
|
||||
********************************************************************************
|
||||
*[Disclaimer]
|
||||
* This model is designed as an aid for customers of Texas Instruments.
|
||||
* TI and its licensors and suppliers make no warranties, either expressed
|
||||
* or implied, with respect to this model, including the warranties of
|
||||
* merchantability or fitness for a particular purpose. The model is
|
||||
* provided solely on an "as is" basis. The entire risk as to its quality
|
||||
* and performance is with the customer.
|
||||
*
|
||||
*[Copyright]
|
||||
*(C) Copyright 2019 Texas Instruments Incorporated.All rights reserved.
|
||||
*
|
||||
**
|
||||
********************************************************************************
|
||||
* SN74LVC1G00
|
||||
|
||||
|
||||
.SUBCKT SN74LVC1G00 Y A B VCC AGND
|
||||
XU1 Y A B VCC AGND LOGIC_GATE_2PIN_OD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
|
||||
.ENDS
|
||||
|
||||
|
||||
|
||||
.SUBCKT LOGIC_GATE_2PIN_OD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 OUT A B VCC GND
|
||||
|
||||
.PARAM VCC_ABS_MAX = 6.5
|
||||
.PARAM VCC_MAX = 5.5
|
||||
.PARAM RA = 44000000
|
||||
.PARAM RB = 44000000
|
||||
.PARAM CA = 4e-12
|
||||
.PARAM CB = 4e-12
|
||||
.PARAM ROEZ = 112.49999999999999
|
||||
.PARAM COEZ = 3e-12
|
||||
RA A GND {RA}
|
||||
RB B GND {RB}
|
||||
CA A GND {CA}
|
||||
CB B GND {CB}
|
||||
XUA NA A VCC GND LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
|
||||
XUB NB B VCC GND LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
|
||||
XUG NA NB NOUTG VCC GND LOGIC_FUNCTION_2_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
|
||||
XOUTPD NOUTG NOUTTPD VCC GND TPD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
|
||||
XUOUT NOUTTPD NOUT_INT VCC GND LOGIC_PP_OUTPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
|
||||
XICC VCC GND NVIOUT LOGIC_ICC_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
|
||||
SICC VCC GND VCC GND SW1
|
||||
H1 NVIOUT GND VIOUT 1
|
||||
VIOUT NOUT_INT OUTsw 0
|
||||
SIOFF OUTsw OUT VCC GND SW2
|
||||
DA2 GND A D1
|
||||
DB2 GND B D1
|
||||
DO2 GND OUT D1
|
||||
RDA1 NA1 GND 1e6
|
||||
SDA1 NA1 A VCC GND SW2
|
||||
RDB1 NB1 GND 1e6
|
||||
SDB1 NB1 B VCC GND SW2
|
||||
RDO1 NO1 GND 1e6
|
||||
SDO1 NO1 OUT VCC GND SW2
|
||||
.MODEL SW1 VSWITCH VON = {VCC_ABS_MAX} VOFF = {VCC_MAX} RON = 10 ROFF = 60e6
|
||||
.MODEL SW2 VSWITCH VON = {0.55} VOFF = {0.45} RON = 10m ROFF = 100e6
|
||||
.MODEL D1 D
|
||||
.ENDS
|
||||
.SUBCKT LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 OUT IN VCC VEE
|
||||
.PARAM STANDARD_INPUT_SELECT = 1
|
||||
|
||||
.PARAM SCHMITT_TRIGGER_INPUT_SELECT = 0
|
||||
ESTD_THR VSTD_THR VEE TABLE {V(VCC,VEE)} =
|
||||
+(1,0.5)
|
||||
+(1.8,0.9)
|
||||
+(2.5,1.25)
|
||||
+(3.3,1.65)
|
||||
+(5,2.5)
|
||||
+(6,3)
|
||||
ETRP_P VTRP_P VEE TABLE {V(VCC,VEE)} =
|
||||
+(2.5,1.4)
|
||||
+(3.3,1.9)
|
||||
+(5,3.25)
|
||||
ETRP_N VTRP_N VEE TABLE {V(VCC,VEE)} =
|
||||
+(2.5,1.15)
|
||||
+(3.3,1.5)
|
||||
+(5,2.25)
|
||||
EHYST VHYST VEE TABLE {V(VCC,VEE)} =
|
||||
+(2.5,0.6)
|
||||
+(3.3,0.75)
|
||||
+(5,1.25)
|
||||
ETRUE NTRUE VEE VALUE = {V(VCC,VEE)}
|
||||
EFALSE NFALSE VEE VALUE = {0}
|
||||
|
||||
EBETA BETA VEE VALUE = {V(VHYST,VEE)/(V(NTRUE,VEE) - V(NFALSE,VEE) + V(VHYST,VEE))}
|
||||
EFB NFB VEE VALUE = {(1 - V(BETA,VEE))*V(IN,VEE) + V(BETA,VEE)*V(CURR_OUT,VEE)}
|
||||
EREF NREF VEE VALUE = {0.5*(1 - V(BETA,VEE))*(V(VTRP_P,VEE) + V(VTRP_N,VEE))
|
||||
+ + 0.5*V(BETA,VEE)*(V(NTRUE,VEE) + V(NFALSE,VEE))}
|
||||
EDIFF NDIFF VEE VALUE = {V(NFB,NREF)}
|
||||
ESWITCH VSWITCH VEE VALUE = {0.5*(-SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
|
||||
ESWITCH1 VSWITCH1 VEE VALUE = {0.5*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
|
||||
GCOMP VEE CURR_OUT VALUE = {SCHMITT_TRIGGER_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
|
||||
|
||||
GSTD VEE CURR_OUT VALUE = {STANDARD_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(IN,VSTD_THR)) + ABS(SGN(V(IN,VSTD_THR))))}
|
||||
ROUT CURR_OUT VEE 1
|
||||
EMID MID VEE VALUE = {0.5*(V(VCC,VEE) + V(VEE))}
|
||||
EARG NARG VEE VALUE = {V(CURR_OUT,VEE) - V(MID,VEE)}
|
||||
EOUT OUT VEE VALUE = {0.5*(SGN(V(NARG,VEE)) + ABS(SGN(V(NARG,VEE) ) ) )}
|
||||
|
||||
.PARAM MAXICC = .0009
|
||||
.PARAM VT = .7
|
||||
.PARAM VCC_MIN = 3
|
||||
|
||||
EV_VT1 VTN VEE VALUE = { VT }
|
||||
EV_VT2 VTP VEE VALUE = { V(VCC,VEE) - VT }
|
||||
|
||||
ETEST TEST VEE VALUE = {.9*V(VCC,VEE)}
|
||||
|
||||
EVTHDIFF VTH_DIFF VEE VALUE = {V(IN,VSTD_THR)}
|
||||
EVTHPDIFF VTHP_DIFF VEE VALUE = {V(IN,VTRP_P)}
|
||||
EVTHNDIFF VTHN_DIFF VEE VALUE = {V(IN,VTRP_N)}
|
||||
EVTNDIFF VTN_DIFF VEE VALUE = { V(IN,VTN) }
|
||||
EVTPDIFF VTP_DIFF VEE VALUE = { V(IN,VTP) }
|
||||
|
||||
|
||||
GICCVA VCC VEE VALUE = { (-ABS(( (1+SGN(V(VTN_DIFF,VEE)) ) )/2 -1) *
|
||||
+ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
|
||||
GICCVB VCC VEE VALUE = { (ABS(( (1+SGN(V(VTHP_DIFF,VEE)) ) )/2 -1) *
|
||||
+ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
|
||||
GICCVC VCC VEE VALUE = { ( ABS( (1+SGN(V(VTHN_DIFF,VEE)) ) )/2 *
|
||||
+ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
|
||||
GICCVD VCC VEE VALUE = { (-ABS( (1+SGN(V(VTP_DIFF,VEE)) ) )/2 *
|
||||
+ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
|
||||
|
||||
.ENDS
|
||||
.SUBCKT LOGIC_FUNCTION_2_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 A B OUT VCC VEE
|
||||
.PARAM AND = 0
|
||||
.PARAM NAND = 1
|
||||
.PARAM OR = 0
|
||||
.PARAM NOR = 0
|
||||
.PARAM XOR = 0
|
||||
.PARAM XNOR = 0
|
||||
GAND VEE N1 VALUE = {AND*V(A,VEE)*V(B,VEE)}
|
||||
GNAND VEE N1 VALUE = {NAND*(1 - V(A,VEE)*V(B,VEE))}
|
||||
GOR VEE N1 VALUE = {OR*(MIN(V(A,VEE) + V(B,VEE),1))}
|
||||
GNOR VEE N1 VALUE = {NOR*(1 - MIN(V(A,VEE) + V(B,VEE),1))}
|
||||
GXOR VEE N1 VALUE = {XOR*((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE)))}
|
||||
GXNOR VEE N1 VALUE = {XNOR*(1 - ((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE))))}
|
||||
RN1 N1 VEE 1
|
||||
EOUT OUT VEE N1 VEE 1
|
||||
.ENDS
|
||||
.SUBCKT TPD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 IN OUT VCC VEE
|
||||
.PARAM TPDELAY1 = 1N
|
||||
.PARAM RS = 10K
|
||||
.PARAM CS = {-TPDELAY1/(RS*LOG(0.5))}
|
||||
ETPDNORM NTPDNORM VEE TABLE {V(VCC,VEE)} =
|
||||
+(1.8,4.7)
|
||||
+(2.5,2.65)
|
||||
+(3.3,2.3)
|
||||
+(5,2.1)
|
||||
G1 IN N1 VALUE = {V(IN,N1)/(V(NTPDNORM,VEE)*RS)}
|
||||
RZ IN N1 10G
|
||||
C1 N1 VEE {CS}
|
||||
E1 N2 VEE VALUE = {0.5*(1 + SGN(V(N1,VEE) - 0.5))}
|
||||
EOUT OUT VEE N2 VEE 1
|
||||
.ENDS
|
||||
.SUBCKT LOGIC_PP_OUTPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 IN OUT VCC VEE
|
||||
EROH NROH VEE TABLE {V(VCC,VEE)} =
|
||||
+(1.65,112.5)
|
||||
+(2.3,50)
|
||||
+(3,25)
|
||||
+(4.5,21.875)
|
||||
EROL NROL VEE TABLE {V(VCC,VEE)} =
|
||||
+(1.65,112.5)
|
||||
+(2.3,37.5)
|
||||
+(3,22.9166666666667)
|
||||
+(4.5,17.5)
|
||||
E1 N1 VEE VALUE = {V(VCC,VEE)*V(IN,VEE)}
|
||||
GOUT N1 OUT VALUE = {V(N1,OUT)*(V(IN,VEE)/V(NROH,VEE) + (1 - V(IN,VEE))/V(NROL,VEE))}
|
||||
.ENDS
|
||||
.SUBCKT LOGIC_ICC_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 VCC VEE VIOUT
|
||||
.PARAM ICC = 2.5e-07
|
||||
.PARAM VCC_MAX = 5.5
|
||||
.PARAM VCC_MIN = 1.65
|
||||
GICC VCC VEE VALUE = {ICC*0.5*(1 + SGN(V(VCC,VEE) - VCC_MIN))}
|
||||
EGNDF GNDF 0 VALUE = {0.5*(V(VCC) + V(VEE))}
|
||||
GOUTP VCC GNDF VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))}
|
||||
GOUTN GNDF VEE VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))}
|
||||
.ENDS
|
||||
70
spice/ti/TLV70012.lib
Normal file
70
spice/ti/TLV70012.lib
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70012 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2011 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
|
||||
* Part: TLV70012
|
||||
* Date: 04/05/2011
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number:
|
||||
* EVM Users Guide:
|
||||
* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70012
|
||||
*$
|
||||
.SUBCKT TLV70012 IN GND EN OUT
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dce2e9103f51d0de79
|
||||
259e22a51c65bc4dee29b1af577e67324e552c8ab90b219a64615adc73efa63218909a58bd8b76904fcdb80814ad954a373688de6049867ad38aff4e12555a5d
|
||||
af1dff2e8151d1b3ad961377e023ab654e552c8ab90b219a64615adc73efa632ade02a6c3e64e287c90ba24b54740a7a2a931f55ee8d47b0d3b55e518a88efc0
|
||||
259e22a51c65bc4da1b65c0354cbc4412531ce9df5eb0603c921153da52548beb6f9c085d8eda78df34d311b7ac26f46c1f60d7ea22f9ce9e07acc9f85f01ad6
|
||||
259e22a51c65bc4d51a924006509d8924e552c8ab90b219a64615adc73efa632d9ae151f53d140dbc88e473ce12bfd9706ea93996f83a7bddf7a8af3bf3808c1
|
||||
259e22a51c65bc4d183fce15e18b18aa239bdbe658d21d004e837baae6a4ac8864615adc73efa6327ef5870a5e3da03d727a1739f56464652ba2c1c1728c017b
|
||||
af1dff2e8151d1b3ed846c24bda46d9644f91394b9d9e84610977954546a053d822ef85746450e5043e100eee5b305a94c49b18e65b20125cd81523dba430406
|
||||
3fc4c23aa5b659665a17e7431216915f504ad14f2fb29f6c71cf3cb4f0f12316644126c9831a96bd58f95f397589bbe7e854495f016ffd76d22b26a7b6cfc473
|
||||
5d078000650a8fa5f720513110d464d784228f9fa61e3ec38675a01b2db95be71bddfb574903d61a725ed083df9a515d637d1b072f0e2ebe507e5c82eb9edef9
|
||||
af1dff2e8151d1b3ed846c24bda46d96f5687491f31f292410977954546a053dca2f8c83eb5775a39c064bf94d8ce6078492e52ca990713779eccb7eaf03f4e4
|
||||
97273dca314e0f137158f7066bb1acc8e884561dc52031d166f9df056a16ed558b31c7db94f482141bddfb574903d61a725ed083df9a515d654bea6dfaccad75
|
||||
427c310c1c1f6b42fcdff44f046d00717e012483319edfad3d1a96345bca769f156308c046a85546e73070a45f1d549c8ae9764513fec3e270ea434bac481a10
|
||||
af1dff2e8151d1b3ed846c24bda46d9605f06f9213ce83ba10977954546a053dca2f8c83eb5775a3ecbee74170ca80188492e52ca990713779eccb7eaf03f4e4
|
||||
a96c53d84a6e3a2c777909964b84d5bf2b81e10e996e19ac294ff995b8f67f658ae9764513fec3e28e779e2db5abbf64f4f2ab4e4c8c394ffa8db939ff1224c4
|
||||
cd080d6014ef79b45b21fcbb5127d82b1bddfb574903d61a725ed083df9a515d637d1b072f0e2ebed3bdfb0233d3746a97fd1405997c9bbe211952a674e6752c
|
||||
ce1e320d9877b21bc90ba24b54740a7aa7d24ab7ae54f3c7cb82e1066e82af78e73070a45f1d549c8ae9764513fec3e28e779e2db5abbf646871dc705148aaae
|
||||
259e22a51c65bc4d183fce15e18b18aacd9f9b0fe66d8ad14e837baae6a4ac8864615adc73efa6325ff6f42c959550fbd48c1d14d1b0c61c2ba2c1c1728c017b
|
||||
259e22a51c65bc4d695c770f0bec7fcc4e552c8ab90b219a605c5accbc975768c76c6f59598c925ec90ba24b54740a7ab286dd1121d2a6d23c33417d989f4d2c
|
||||
79b347c5b85360ef9dd0e5cec1514afc4e552c8ab90b219a64615adc73efa632d9ae151f53d140db68bc7b4cd898b01306ea93996f83a7bddf7a8af3bf3808c1
|
||||
79b347c5b85360ef9161d902182c168c4e552c8ab90b219a64615adc73efa63203713b4f43695ba78c0e8091394b9856ac0bbcb25a375ea3a3326a35d52f6cdd
|
||||
259e22a51c65bc4d1db1e7e640c0f26a4e552c8ab90b219a64615adc73efa63218909a58bd8b76908c0e8091394b985661a0613e3a41a223d38aff4e12555a5d
|
||||
d153893f36515c509a2f4988e6fd1384e3d4223c66a65ea17c3d70f9a365ec31fc8a520169f0e78fad7181505892a4c88e95fdd389b2972f9e301436d16375b1
|
||||
c90ba24b54740a7accefcc2bf8692e3b8ae9764513fec3e28e779e2db5abbf64f4f2ab4e4c8c394f02f29020cc6bed9a5594c975cd36d3d3456e122046cc1edb
|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70012
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70012_F1 1 2 3 4
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dce2e9103f51d0de79
|
||||
4f9bfd860debeaf29a2f4988e6fd138446b92e86e8aaa0ba6346aa19326e7599631ebabd5b20ecbf57e2c5aa80851370dcb2222a3ac73375375bc7f7c20b6cb9
|
||||
476007b7708ce3cdb942d935367989681852d2bae2562872b9ef19aa8805d3198e3bef92b0a3919088b82ad28ee6d41b53c9f4b6d37454d87b866626a673e230
|
||||
$CDNENCFINISH
|
||||
.ends SCHEMATIC1_TLV70012_F1
|
||||
*$
|
||||
|
||||
BIN
spice/ti/slvm171.zip
Normal file
BIN
spice/ti/slvm171.zip
Normal file
Binary file not shown.
Loading…
Reference in New Issue
Block a user