Merge remote-tracking branch 'origin/dev'

This commit is contained in:
Brendan Haines 2022-09-20 18:16:08 -06:00
commit 6208f236f8
9 changed files with 669 additions and 3 deletions

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@ -13958,6 +13958,32 @@
)
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@ -14608,7 +14634,16 @@
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@ -15425,6 +15460,23 @@
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@ -15899,7 +15951,22 @@
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@ -24107,7 +24174,19 @@
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149
diode.kicad_sym Normal file
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@ -0,0 +1,149 @@
(kicad_symbol_lib (version 20220331) (generator kicad_symbol_editor)
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)

111
spice/adi/ad840.cir Normal file
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@ -0,0 +1,111 @@
* AD840 SPICE Macro-model
* Description: Amplifier
* Generic Desc: WIDEBAND,FAST SETTLING OP AMP
* Developed by: AAG / PMI
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (01/1991)
* Copyright 1991, 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance with the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | |
.SUBCKT AD840 1 2 100 101 36
*
* INPUT STAGE & POLE AT 120 MHz
*
IOS 1 2 DC 0.05E-6
CIN 1 2 2E-12
R1 1 3 15E3
R2 2 3 15E3
EOS 9 1 POLY(1) 16 11 200E-6 1
R3 100 5 223.38
R4 100 6 223.38
C2 5 6 2.9687E-12
R5 7 4 171.66
R6 8 4 171.66
Q1 5 2 7 QX
Q2 6 9 8 QX
I1 4 101 DC 1E-3
*
* VIRTUAL NODE
*
RVN1 100 10 25E3
RVN2 10 101 25E3
*
* GAIN STAGE & DOMINANT POLE AT 2.1923 KHz
*
EREF 11 0 10 0 1
G1 11 12 5 6 4.4768E-3
R7 12 11 29.039E6
C3 12 11 2.5E-12
V1 100 13 DC 2.4375
D1 12 13 DX
V2 14 101 DC 2.4375
D2 14 12 DX
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 20 KHz
*
ECM 15 11 3 11 3.1623
RCM1 15 16 1E6
CCM 15 16 7.9577E-12
RCM2 16 11 1
*
* NEGATIVE ZERO STAGE AT 290 MHz
*
EZ1 17 11 12 11 1E6
RZ1 17 18 1
CZ1 17 18 -548.81E-12
RZ2 18 11 1E-6
*
* POLE STAGE AT 500 MHz
*
GP1 11 19 18 11 1E-6
RP1 19 11 1E6
CP1 19 11 318.31E-18
*
* OUTPUT STAGE
*
IDC 100 101 DC 8.9E-3
VX 19 30
V3 32 35 DC 2.725
D3 30 32 DX
V4 35 33 DC 2.575
D4 33 30 DX
D5 100 31 DX
GO1 31 101 30 35 16.667E-3
D6 101 31 DY
D7 100 34 DX
GO2 34 101 35 30 16.667E-3
D8 101 34 DY
RO1 100 35 60
GO3 35 100 100 30 16.667E-3
RO2 35 101 60
GO4 101 35 30 101 16.667E-3
LO 35 36 0.04E-6
*
* MODELS USED
*
.MODEL QX NPN(BF=142.86)
.MODEL DX D(IS=1E-15)
.MODEL DY D(IS=1E-15 BV=50)
.ENDS

15
spice/onsemi/S115FA.LIB Normal file
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@ -0,0 +1,15 @@
*$
*********** Discrete Rectifier Electrical Parameters ***********
** Product: S115FA
** Surface Mount Schottky Barrier Rectifiers
**--------------------------------------------------------------
.MODEL S115FA d
+ IS=1.50696e-8 N=1.5 RS=0.256155
+ ISR=5.320e-8 NR=1.5 TRS1=1.2125e-5
+ TRS2=1.084e-7 CJO=9.55e-11 M=0.44017
+ VJ=0.5105 BV=165 IBV=2.5e-4
+ EG=0.785 TT=8.56e-9
****************************************************************
** Creation: Jun.-07-2017 Rev: 0.0
** ON Semiconductor

16
spice/onsemi/S310FA.LIB Normal file
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@ -0,0 +1,16 @@
*$
*********** Discrete Rectifier Electrical Parameters ***********
** Product: S310FA
** Package: SOD-123FL
** Schottky Barrier Rectifiers
****************************************************************
.MODEL S310FA D
+ IS=1.096e-08 N=1.0 RS=1.230e-1
+ ISR=1.7e-8 NR=1.5 TRS1=1.05e-6
+ TRS2=1.5e-8 CJO=2.2854e-10 M=0.47
+ VJ=0.44 BV=110 IBV=2.5e-4
+ TT=7.28e-9 XTI=-12.3 EG=1.16
****************************************************************
** Creation: Aug.-22-2019 Rev: 1.0
** ON Semiconductor

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@ -0,0 +1,26 @@
**************************************
* Model Generated by MODPEX *
*Copyright(c) Symmetry Design Systems*
* All Rights Reserved *
* UNPUBLISHED LICENSED SOFTWARE *
* Contains Proprietary Information *
* Which is The Property of *
* SYMMETRY OR ITS LICENSORS *
*Commercial Use or Resale Restricted *
* by Symmetry License Agreement *
**************************************
* Model generated on Jul 29, 14
* MODEL FORMAT: PSpice
.MODEL Qbc81740lt1g npn
+IS=1.61861e-13 BF=510.104 NF=0.990132 VAF=62.302
+IKF=0.763922 ISE=7.67929e-10 NE=4 BR=38.021
+NR=1.0751 VAR=2.67102 IKR=0.0671266 ISC=6.73996e-14
+NC=1.07195 RB=2.53475 IRB=0.1 RBM=2.52145
+RE=0.040147 RC=0.200735 XTB=1.04773 XTI=2.15473
+EG=1.206 CJE=3.98362e-11 VJE=0.4 MJE=0.361957
+TF=5.19286e-10 XTF=84.5359 VTF=0.289175 ITF=3.82303
+CJC=1.16343e-11 VJC=0.4 MJC=0.269118 XCJC=0.891865
+FC=0.8 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1

200
spice/ti/SN74LVC1G00.cir Normal file
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@ -0,0 +1,200 @@
********************************************************************************
* SN74LVC1G00.cir
* 1.0
* 2018-11-16 00:00:00
* Texas Instruments Incorporated.
* Standard Logic, SLHR
* 12500 TI Blvd
* Dallas, TX -75243
*
*
* Revision History:
* Rev 2.0: 01/01/2019
* - Model generated from datasheet values
* - Built using generic logic gate behavioral pspice model V2
* - Built using an automated model which generalizes parts under same family
* - Performance is expected typical behavior at 25C
* - Written for and tested with Tina-TI Version 9.3.100.244 SF-TI
* - Accurate power consumption with dyanmic as well as static Icc
*
********************************************************************************
*[Disclaimer]
* This model is designed as an aid for customers of Texas Instruments.
* TI and its licensors and suppliers make no warranties, either expressed
* or implied, with respect to this model, including the warranties of
* merchantability or fitness for a particular purpose. The model is
* provided solely on an "as is" basis. The entire risk as to its quality
* and performance is with the customer.
*
*[Copyright]
*(C) Copyright 2019 Texas Instruments Incorporated.All rights reserved.
*
**
********************************************************************************
* SN74LVC1G00
.SUBCKT SN74LVC1G00 Y A B VCC AGND
XU1 Y A B VCC AGND LOGIC_GATE_2PIN_OD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
.ENDS
.SUBCKT LOGIC_GATE_2PIN_OD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 OUT A B VCC GND
.PARAM VCC_ABS_MAX = 6.5
.PARAM VCC_MAX = 5.5
.PARAM RA = 44000000
.PARAM RB = 44000000
.PARAM CA = 4e-12
.PARAM CB = 4e-12
.PARAM ROEZ = 112.49999999999999
.PARAM COEZ = 3e-12
RA A GND {RA}
RB B GND {RB}
CA A GND {CA}
CB B GND {CB}
XUA NA A VCC GND LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
XUB NB B VCC GND LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
XUG NA NB NOUTG VCC GND LOGIC_FUNCTION_2_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
XOUTPD NOUTG NOUTTPD VCC GND TPD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
XUOUT NOUTTPD NOUT_INT VCC GND LOGIC_PP_OUTPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
XICC VCC GND NVIOUT LOGIC_ICC_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
SICC VCC GND VCC GND SW1
H1 NVIOUT GND VIOUT 1
VIOUT NOUT_INT OUTsw 0
SIOFF OUTsw OUT VCC GND SW2
DA2 GND A D1
DB2 GND B D1
DO2 GND OUT D1
RDA1 NA1 GND 1e6
SDA1 NA1 A VCC GND SW2
RDB1 NB1 GND 1e6
SDB1 NB1 B VCC GND SW2
RDO1 NO1 GND 1e6
SDO1 NO1 OUT VCC GND SW2
.MODEL SW1 VSWITCH VON = {VCC_ABS_MAX} VOFF = {VCC_MAX} RON = 10 ROFF = 60e6
.MODEL SW2 VSWITCH VON = {0.55} VOFF = {0.45} RON = 10m ROFF = 100e6
.MODEL D1 D
.ENDS
.SUBCKT LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 OUT IN VCC VEE
.PARAM STANDARD_INPUT_SELECT = 1
.PARAM SCHMITT_TRIGGER_INPUT_SELECT = 0
ESTD_THR VSTD_THR VEE TABLE {V(VCC,VEE)} =
+(1,0.5)
+(1.8,0.9)
+(2.5,1.25)
+(3.3,1.65)
+(5,2.5)
+(6,3)
ETRP_P VTRP_P VEE TABLE {V(VCC,VEE)} =
+(2.5,1.4)
+(3.3,1.9)
+(5,3.25)
ETRP_N VTRP_N VEE TABLE {V(VCC,VEE)} =
+(2.5,1.15)
+(3.3,1.5)
+(5,2.25)
EHYST VHYST VEE TABLE {V(VCC,VEE)} =
+(2.5,0.6)
+(3.3,0.75)
+(5,1.25)
ETRUE NTRUE VEE VALUE = {V(VCC,VEE)}
EFALSE NFALSE VEE VALUE = {0}
EBETA BETA VEE VALUE = {V(VHYST,VEE)/(V(NTRUE,VEE) - V(NFALSE,VEE) + V(VHYST,VEE))}
EFB NFB VEE VALUE = {(1 - V(BETA,VEE))*V(IN,VEE) + V(BETA,VEE)*V(CURR_OUT,VEE)}
EREF NREF VEE VALUE = {0.5*(1 - V(BETA,VEE))*(V(VTRP_P,VEE) + V(VTRP_N,VEE))
+ + 0.5*V(BETA,VEE)*(V(NTRUE,VEE) + V(NFALSE,VEE))}
EDIFF NDIFF VEE VALUE = {V(NFB,NREF)}
ESWITCH VSWITCH VEE VALUE = {0.5*(-SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
ESWITCH1 VSWITCH1 VEE VALUE = {0.5*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
GCOMP VEE CURR_OUT VALUE = {SCHMITT_TRIGGER_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
GSTD VEE CURR_OUT VALUE = {STANDARD_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(IN,VSTD_THR)) + ABS(SGN(V(IN,VSTD_THR))))}
ROUT CURR_OUT VEE 1
EMID MID VEE VALUE = {0.5*(V(VCC,VEE) + V(VEE))}
EARG NARG VEE VALUE = {V(CURR_OUT,VEE) - V(MID,VEE)}
EOUT OUT VEE VALUE = {0.5*(SGN(V(NARG,VEE)) + ABS(SGN(V(NARG,VEE) ) ) )}
.PARAM MAXICC = .0009
.PARAM VT = .7
.PARAM VCC_MIN = 3
EV_VT1 VTN VEE VALUE = { VT }
EV_VT2 VTP VEE VALUE = { V(VCC,VEE) - VT }
ETEST TEST VEE VALUE = {.9*V(VCC,VEE)}
EVTHDIFF VTH_DIFF VEE VALUE = {V(IN,VSTD_THR)}
EVTHPDIFF VTHP_DIFF VEE VALUE = {V(IN,VTRP_P)}
EVTHNDIFF VTHN_DIFF VEE VALUE = {V(IN,VTRP_N)}
EVTNDIFF VTN_DIFF VEE VALUE = { V(IN,VTN) }
EVTPDIFF VTP_DIFF VEE VALUE = { V(IN,VTP) }
GICCVA VCC VEE VALUE = { (-ABS(( (1+SGN(V(VTN_DIFF,VEE)) ) )/2 -1) *
+ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
GICCVB VCC VEE VALUE = { (ABS(( (1+SGN(V(VTHP_DIFF,VEE)) ) )/2 -1) *
+ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
GICCVC VCC VEE VALUE = { ( ABS( (1+SGN(V(VTHN_DIFF,VEE)) ) )/2 *
+ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
GICCVD VCC VEE VALUE = { (-ABS( (1+SGN(V(VTP_DIFF,VEE)) ) )/2 *
+ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
.ENDS
.SUBCKT LOGIC_FUNCTION_2_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 A B OUT VCC VEE
.PARAM AND = 0
.PARAM NAND = 1
.PARAM OR = 0
.PARAM NOR = 0
.PARAM XOR = 0
.PARAM XNOR = 0
GAND VEE N1 VALUE = {AND*V(A,VEE)*V(B,VEE)}
GNAND VEE N1 VALUE = {NAND*(1 - V(A,VEE)*V(B,VEE))}
GOR VEE N1 VALUE = {OR*(MIN(V(A,VEE) + V(B,VEE),1))}
GNOR VEE N1 VALUE = {NOR*(1 - MIN(V(A,VEE) + V(B,VEE),1))}
GXOR VEE N1 VALUE = {XOR*((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE)))}
GXNOR VEE N1 VALUE = {XNOR*(1 - ((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE))))}
RN1 N1 VEE 1
EOUT OUT VEE N1 VEE 1
.ENDS
.SUBCKT TPD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 IN OUT VCC VEE
.PARAM TPDELAY1 = 1N
.PARAM RS = 10K
.PARAM CS = {-TPDELAY1/(RS*LOG(0.5))}
ETPDNORM NTPDNORM VEE TABLE {V(VCC,VEE)} =
+(1.8,4.7)
+(2.5,2.65)
+(3.3,2.3)
+(5,2.1)
G1 IN N1 VALUE = {V(IN,N1)/(V(NTPDNORM,VEE)*RS)}
RZ IN N1 10G
C1 N1 VEE {CS}
E1 N2 VEE VALUE = {0.5*(1 + SGN(V(N1,VEE) - 0.5))}
EOUT OUT VEE N2 VEE 1
.ENDS
.SUBCKT LOGIC_PP_OUTPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 IN OUT VCC VEE
EROH NROH VEE TABLE {V(VCC,VEE)} =
+(1.65,112.5)
+(2.3,50)
+(3,25)
+(4.5,21.875)
EROL NROL VEE TABLE {V(VCC,VEE)} =
+(1.65,112.5)
+(2.3,37.5)
+(3,22.9166666666667)
+(4.5,17.5)
E1 N1 VEE VALUE = {V(VCC,VEE)*V(IN,VEE)}
GOUT N1 OUT VALUE = {V(N1,OUT)*(V(IN,VEE)/V(NROH,VEE) + (1 - V(IN,VEE))/V(NROL,VEE))}
.ENDS
.SUBCKT LOGIC_ICC_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 VCC VEE VIOUT
.PARAM ICC = 2.5e-07
.PARAM VCC_MAX = 5.5
.PARAM VCC_MIN = 1.65
GICC VCC VEE VALUE = {ICC*0.5*(1 + SGN(V(VCC,VEE) - VCC_MIN))}
EGNDF GNDF 0 VALUE = {0.5*(V(VCC) + V(VEE))}
GOUTP VCC GNDF VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))}
GOUTN GNDF VEE VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))}
.ENDS

70
spice/ti/TLV70012.lib Normal file
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@ -0,0 +1,70 @@
**$ENCRYPTED_LIB
**$INTERFACE
* TLV70012 Model
***************************************************************************
** This product is designed as an aid for customers of Texas Instruments.**
** No warranties, either expressed or implied, with respect to this third**
** party software (if any) or with respect to its fitness for any **
** particular purpose is claimed by Texas Instruments or the author. The **
** software (if any) is provided soley on an "as is" basis. The entire **
** risk as to its quality and performance is with the customer **
********************************************************************************
*
* (C) Copyright 2011 Texas Instruments Incorporated . All rights reserved.
*
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
* Part: TLV70012
* Date: 04/05/2011
* Model Type: TRANSIENT
* Simulator: PSPICE
* EVM Order Number:
* EVM Users Guide:
* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
*
*****************************************************************************
*
* Updates:
*
* Final 1.00
* Release to Web.
*
*********************************************************************************
* source TLV70012
*$
.SUBCKT TLV70012 IN GND EN OUT
$CDNENCSTART
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$CDNENCFINISH
.ENDS TLV70012
*$
.subckt SCHEMATIC1_TLV70012_F1 1 2 3 4
$CDNENCSTART
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$CDNENCFINISH
.ends SCHEMATIC1_TLV70012_F1
*$

BIN
spice/ti/slvm171.zip Normal file

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