diff --git a/scripting/plugins/OutputGeneration/FabOutputs.py b/scripting/plugins/OutputGeneration/FabOutputs.py index 4dd9aeb..8f9c88d 100755 --- a/scripting/plugins/OutputGeneration/FabOutputs.py +++ b/scripting/plugins/OutputGeneration/FabOutputs.py @@ -1,8 +1,9 @@ -import pcbnew import os +import zipfile from datetime import datetime from pathlib import Path -import zipfile + +import pcbnew __all__ = ["FabOutputs"] @@ -45,33 +46,36 @@ class FabOutputs(pcbnew.ActionPlugin): ("Front Silkscreen", "gto", pcbnew.F_SilkS), ("Front Mask", "gts", pcbnew.F_Mask), ("Front Copper", "gtl", pcbnew.F_Cu), - *[(f'Inner Layer {layer} Copper', f'g{layer}', layer) for layer in range(1, layer_count-1)], - ('Back Copper', 'gbl', pcbnew.B_Cu), - ('Back Mask', 'gbs', pcbnew.B_Mask), - ('Back SilkScreen', 'gbo', pcbnew.B_SilkS), - ('Back Paste', 'gbp', pcbnew.B_Paste), - ('Edges Cuts', 'gm1', pcbnew.Edge_Cuts), - ('Drill', 'drl', None), + *[ + (f"Inner Layer {layer} Copper", f"g{layer}", layer) + for layer in range(1, layer_count - 1) + ], + ("Back Copper", "gbl", pcbnew.B_Cu), + ("Back Mask", "gbs", pcbnew.B_Mask), + ("Back SilkScreen", "gbo", pcbnew.B_SilkS), + ("Back Paste", "gbp", pcbnew.B_Paste), + ("Edges Cuts", "gm1", pcbnew.Edge_Cuts), + ("Drill", "drl", None), ] stackup = [ # [pcbnew layer, file extension, thickness, comment] - [pcbnew.F_Paste, 'gtp', None, "SN63/PB37"], - [pcbnew.F_SilkS, 'gto', None, "White"], - [pcbnew.F_Mask, 'gts', 1, "Explicit mask material"], + [pcbnew.F_Paste, "gtp", None, "SN63/PB37"], + [pcbnew.F_SilkS, "gto", None, "White"], + [pcbnew.F_Mask, "gts", 1, "Explicit mask material"], [None, None, None, "ENIG"], - [pcbnew.F_Cu, 'gtl', 2.1, "copper roughness"], + [pcbnew.F_Cu, "gtl", 2.1, "copper roughness"], [None, None, 10, "Dielectric stuff"], - [1, 'g1', 0.7, "Copper roughness"], + [1, "g1", 0.7, "Copper roughness"], [None, None, 24, "Dielectric stuff"], [None, None, 12, "Dielectric stuff"], - [2, 'g2', 0.7, "Copper roughness"], + [2, "g2", 0.7, "Copper roughness"], [None, None, 10, "Dielectric stuff"], - [pcbnew.B_Cu, 'gbl', 2.1, "copper roughness"], + [pcbnew.B_Cu, "gbl", 2.1, "copper roughness"], [None, None, None, "ENIG"], - [pcbnew.B_Mask, 'gbs', 1, "Explicit mask material"], - [pcbnew.B_SilkS, 'gbo', None, "White"], - [pcbnew.B_Paste, 'gbp', None, "SN63/PB37"], + [pcbnew.B_Mask, "gbs", 1, "Explicit mask material"], + [pcbnew.B_SilkS, "gbo", None, "White"], + [pcbnew.B_Paste, "gbp", None, "SN63/PB37"], ] board_features = { @@ -81,7 +85,7 @@ class FabOutputs(pcbnew.ActionPlugin): "copper finish": "ENIG", "hard gold": False, "bevelled edge": False, - "soldermask defined": None, # TODO: how do I want to determine this? + "soldermask defined": None, # TODO: how do I want to determine this? } dir_fab.mkdir(parents=True, exist_ok=True) @@ -99,7 +103,7 @@ class FabOutputs(pcbnew.ActionPlugin): plot_controller = pcbnew.PLOT_CONTROLLER(pcb) plot_options = plot_controller.GetPlotOptions() - + # Set General Options: # plot_options.Format() plot_options.SetOutputDirectory(dir_fab) @@ -114,8 +118,8 @@ class FabOutputs(pcbnew.ActionPlugin): plot_options.SetNegative(False) plot_options.SetScale(1) # plot_options.SetAutoScale(True) - #plot_options.SetPlotMode(PLOT_MODE) - #plot_options.SetLineWidth(pcbnew.FromMM(PLOT_LINE_WIDTH)) + # plot_options.SetPlotMode(PLOT_MODE) + # plot_options.SetLineWidth(pcbnew.FromMM(PLOT_LINE_WIDTH)) plot_options.SetUseGerberAttributes(True) plot_options.SetUseGerberProtelExtensions(False) plot_options.SetCreateGerberJobFile(False) @@ -126,28 +130,30 @@ class FabOutputs(pcbnew.ActionPlugin): plot_plan = [ # ( layer ID, file extension, description) - ( pcbnew.F_Paste, 'gtp', 'Front Paste' ), - ( pcbnew.F_SilkS, 'gto', 'Front SilkScreen' ), - ( pcbnew.F_Mask, 'gts', 'Front Mask' ), - ( pcbnew.F_Cu, 'gtl', 'Front Copper' ), - *[(layer, f'g{layer}', f'Inner Layer {layer} Copper') for layer in range(1, layer_count-1)], - ( pcbnew.B_Cu, 'gbl', 'Back Copper' ), - ( pcbnew.B_Mask, 'gbs', 'Back Mask' ), - ( pcbnew.B_SilkS, 'gbo', 'Back SilkScreen' ), - ( pcbnew.B_Paste, 'gbp', 'Back Paste' ), - ( pcbnew.Edge_Cuts, 'gm1', 'Edges Cuts' ), + (pcbnew.F_Paste, "gtp", "Front Paste"), + (pcbnew.F_SilkS, "gto", "Front SilkScreen"), + (pcbnew.F_Mask, "gts", "Front Mask"), + (pcbnew.F_Cu, "gtl", "Front Copper"), + *[ + (layer, f"g{layer}", f"Inner Layer {layer} Copper") + for layer in range(1, layer_count - 1) + ], + (pcbnew.B_Cu, "gbl", "Back Copper"), + (pcbnew.B_Mask, "gbs", "Back Mask"), + (pcbnew.B_SilkS, "gbo", "Back SilkScreen"), + (pcbnew.B_Paste, "gbp", "Back Paste"), + (pcbnew.Edge_Cuts, "gm1", "Edges Cuts"), ] - for layer_info in plot_plan: plot_controller.SetLayer(layer_info[0]) - plot_controller.OpenPlotfile('', pcbnew.PLOT_FORMAT_GERBER, layer_info[2]) + plot_controller.OpenPlotfile("", pcbnew.PLOT_FORMAT_GERBER, layer_info[2]) plot_controller.PlotLayer() fname = f"{project_name}{suffix}.{layer_info[1]}" os.rename(dir_fab / f"{project_name}.gbr", dir_fab / fname) files_fab.append(fname) - + plot_controller.ClosePlot() # ================ @@ -160,7 +166,7 @@ class FabOutputs(pcbnew.ActionPlugin): MANTISSA_DIGITS = 3 MIRROR_Y_AXIS = False HEADER = True - OFFSET = pcbnew.wxPoint(0,0) + OFFSET = pcbnew.wxPoint(0, 0) MERGE_PTH_NPTH = True DRILL_FILE = True MAP_FILE = False @@ -169,7 +175,9 @@ class FabOutputs(pcbnew.ActionPlugin): drill_writer = pcbnew.EXCELLON_WRITER(pcb) drill_writer.SetFormat(METRIC, ZERO_FORMAT, INTEGER_DIGITS, MANTISSA_DIGITS) drill_writer.SetOptions(MIRROR_Y_AXIS, HEADER, OFFSET, MERGE_PTH_NPTH) - drill_writer.CreateDrillandMapFilesSet(str(dir_fab), DRILL_FILE, MAP_FILE, REPORTER) + drill_writer.CreateDrillandMapFilesSet( + str(dir_fab), DRILL_FILE, MAP_FILE, REPORTER + ) fname = f"{project_name}{suffix}.drl" os.rename(dir_fab / f"{project_name}.drl", dir_fab / fname) @@ -200,7 +208,7 @@ class FabOutputs(pcbnew.ActionPlugin): # f.write(f"Layer Order\n") # # for layer in plot_plan: # files_fab.append(fname) - + # ================ # Assembly Notes # ================ @@ -214,20 +222,24 @@ class FabOutputs(pcbnew.ActionPlugin): # Zip # ================ - with zipfile.ZipFile(dir_fab / f"{project_name}{suffix}_fabrication.zip", "w") as z: + with zipfile.ZipFile( + dir_fab / f"{project_name}{suffix}_fabrication.zip", "w" + ) as z: for fname in files_fab: z.write(dir_fab / fname, arcname=fname) - with zipfile.ZipFile(dir_asy / f"{project_name}{suffix}_assembly.zip", "w") as z: + with zipfile.ZipFile( + dir_asy / f"{project_name}{suffix}_assembly.zip", "w" + ) as z: for fname in files_fab: z.write(dir_fab / fname, arcname=Path("fabrication") / fname) for fname in files_asy: z.write(dir_asy / fname, arcname=fname) - + # dir_archive = dir_pcb / "Archive" # with zipfile.ZipFile(dir_archive / f"{project_name}{suffix}_archive.zip", "w") as z: # for fname in files_fab: # z.write(dir_fab / fname, arcname=Path("fabrication") / fname) # for fname in files_asy: # z.write(dir_asy / fname, arcname=Path("assembly") / fname) - # # TODO: archive project here \ No newline at end of file + # # TODO: archive project here diff --git a/scripting/plugins/OutputGeneration/__init__.py b/scripting/plugins/OutputGeneration/__init__.py index 1c2bf0a..ed283bf 100755 --- a/scripting/plugins/OutputGeneration/__init__.py +++ b/scripting/plugins/OutputGeneration/__init__.py @@ -1,2 +1,3 @@ from .FabOutputs import FabOutputs -FabOutputs().register() # Instantiate and register to Pcbnew \ No newline at end of file + +FabOutputs().register() # Instantiate and register to Pcbnew