brendanhaines/kicad
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

add spice models for TLV700**

Browse Source
This commit is contained in:
Brendan Haines
2024-06-15 13:25:35 -06:00
parent 20a89d30d5
commit 434115c68a
91 changed files with 4600 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

137
spice/ti/TLV70022_PSPICE_TRANS/TLV70022-PSpiceFiles/SCHEMATIC1/trans.sim Normal file
View File

@@ -0,0 +1,137 @@
@OrCAD Simulation Server Version: 1.0
@Settings: 0 1
@General:
ProfileName= "trans"
ProfileFile= "trans.sim"
Connectivity= "SCHEMATIC1.net"
NetlistFile= "trans.cir"
DataFile= "trans.dat"
OutFile= "trans.out"
Notes=
@#$BEGINNOTES
@#$ENDNOTES
@End General
@Analysis: 0 1
+0 0 0 0
+0 "1m"
+1 ""
+2 "0"
+3 ""
+4 ""
+5 ""
+6 ""
@End Analysis
@Analysis: 1 0
+2 0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
@End Analysis
@Analysis: 2 0
+0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
+6 ""
+7 ""
@End Analysis
@Analysis: 3 0
+0 0 0
+0 ""
+1 ""
+2 ""
@End Analysis
@Analysis: 4 0
+0 0 1 0 0 0 0 0 0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
+6 ""
+7 ""
LoadFile 0 ""
SaveFile 0 ""
@End Analysis
@Analysis: 5 0
+0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
+6 ""
+7 ""
@End Analysis
@Analysis: 6 0
+1
+0 ""
@End Analysis
@Analysis: 7 0
+0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
@End Analysis
@Analysis: 8 0
+0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
@End Analysis
@Analysis: 9 0
+0 ""
@End Analysis
@Analysis: 10 0
+0 0
+0 ""
+1 ""
+2 ""
+3 ""
+4 ""
+5 ""
+6 ""
+7 ""
@End Analysis
@Analysis: 11 1
+ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0
@End Analysis
@Analysis: 12 0
+8946208 0
@End Analysis
@Analysis: 13 1
+0 1 0 1
@End Analysis
@Analysis: 14 1
+1 1 1 "*"
@End Analysis
@Analysis: 15 0
@End Analysis
@Analysis: 16 0
+0 "0"
+1 "0"
+2 "chkpt_default, , ,"
@End Analysis
@Analysis: 17 0
+0 "-1"
+1 ""
+2 "-1"
+3 "-1"
+4 "1"
@End Analysis

BIN
spice/ti/TLV70022_PSPICE_TRANS/TLV70022-PSpiceFiles/SCHEMATIC1/trans/trans.mrk Normal file
View File

Binary file not shown.

76
spice/ti/TLV70022_PSPICE_TRANS/TLV70022-PSpiceFiles/SCHEMATIC1/trans/trans.prb Normal file
View File

@@ -0,0 +1,76 @@
[DISPLAYS]
BEGIN DISPLAY LAST SESSION
ANALYSIS TRANSIENT_ANALYSIS
SYMBOL ALWAYS
TRACECOLORSCHEME NORMAL
BEGIN ANAPLOT 1
XBASE
BEGIN XAXIS
XAXISUSERNAME 0 (null)
RANGEFLAG AUTO
TYPE LINEAR
UNIT s
BEGIN GRIDS
AUTOMATIC
MAJORNUMBERS
MAJORSTYLE LINES
MAJORPATTERN SOLID
MINORSTYLE LINES
MINORPATTERN DOT
END GRIDS
END XAXIS
BEGIN YAXIS 1
YAXISSIDE LEFT
ACTIVE
RANGEFLAG AUTO
TYPE LINEAR
UNIT V
BEGIN GRIDS
AUTOMATIC
MAJORNUMBERS
MAJORSTYLE LINES
MAJORPATTERN SOLID
MINORSTYLE LINES
MINORPATTERN DOT
END GRIDS
BEGIN TRACE V(Vout)
MARKERID 1
END TRACE V(Vout)
END YAXIS 1
END ANAPLOT 1
BEGIN ANAPLOT 2
ACTIVE
BEGIN XAXIS
XAXISUSERNAME 0 (null)
RANGEFLAG AUTO
TYPE LINEAR
UNIT s
BEGIN GRIDS
AUTOMATIC
MAJORNUMBERS
MAJORSTYLE LINES
MAJORPATTERN SOLID
MINORSTYLE LINES
MINORPATTERN DOT
END GRIDS
END XAXIS
BEGIN YAXIS 1
YAXISSIDE LEFT
ACTIVE
RANGEFLAG AUTO
TYPE LINEAR
UNIT V
BEGIN GRIDS
AUTOMATIC
MAJORNUMBERS
MAJORSTYLE LINES
MAJORPATTERN SOLID
MINORSTYLE LINES
MINORPATTERN DOT
END GRIDS
BEGIN TRACE V(Vin)
MARKERID 2
END TRACE V(Vin)
END YAXIS 1
END ANAPLOT 2
END DISPLAY LAST SESSION