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add spice models for TLV700**

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This commit is contained in:
Brendan Haines
2024-06-15 13:25:35 -06:00
parent 20a89d30d5
commit 434115c68a
91 changed files with 4600 additions and 0 deletions
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137
spice/ti/TLV70019_PSPICE_TRANS/TLV70019-PSpiceFiles/SCHEMATIC1/trans.sim Normal file
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@OrCAD Simulation Server Version: 1.0
@Settings: 0 1
@General:
ProfileName= "trans"
ProfileFile= "trans.sim"
Connectivity= "SCHEMATIC1.net"
NetlistFile= "trans.cir"
DataFile= "trans.dat"
OutFile= "trans.out"
Notes=
@#$BEGINNOTES
@#$ENDNOTES
@End General
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SaveFile 0 ""
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BIN
spice/ti/TLV70019_PSPICE_TRANS/TLV70019-PSpiceFiles/SCHEMATIC1/trans/trans.mrk Normal file
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76
spice/ti/TLV70019_PSPICE_TRANS/TLV70019-PSpiceFiles/SCHEMATIC1/trans/trans.prb Normal file
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[DISPLAYS]
BEGIN DISPLAY LAST SESSION
ANALYSIS TRANSIENT_ANALYSIS
SYMBOL ALWAYS
TRACECOLORSCHEME NORMAL
BEGIN ANAPLOT 1
ACTIVE
XBASE
BEGIN XAXIS
XAXISUSERNAME 0 (null)
RANGEFLAG AUTO
TYPE LINEAR
UNIT s
BEGIN GRIDS
AUTOMATIC
MAJORNUMBERS
MAJORSTYLE LINES
MAJORPATTERN SOLID
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RANGEFLAG AUTO
TYPE LINEAR
UNIT V
BEGIN GRIDS
AUTOMATIC
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MAJORSTYLE LINES
MAJORPATTERN SOLID
MINORSTYLE LINES
MINORPATTERN DOT
END GRIDS
BEGIN TRACE V(Vout)
MARKERID 1
END TRACE V(Vout)
END YAXIS 1
END ANAPLOT 1
BEGIN ANAPLOT 2
BEGIN XAXIS
XAXISUSERNAME 0 (null)
RANGEFLAG AUTO
TYPE LINEAR
UNIT s
BEGIN GRIDS
AUTOMATIC
MAJORNUMBERS
MAJORSTYLE LINES
MAJORPATTERN SOLID
MINORSTYLE LINES
MINORPATTERN DOT
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BEGIN YAXIS 1
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RANGEFLAG AUTO
TYPE LINEAR
UNIT V
BEGIN GRIDS
AUTOMATIC
MAJORNUMBERS
MAJORSTYLE LINES
MAJORPATTERN SOLID
MINORSTYLE LINES
MINORPATTERN DOT
END GRIDS
BEGIN TRACE V(Vin)
MARKERID 4
END TRACE V(Vin)
END YAXIS 1
END ANAPLOT 2
END DISPLAY LAST SESSION