add spice models for TLV700**

2024-06-15 13:25:35 -06:00
parent 20a89d30d5
commit 434115c68a
91 changed files with 4600 additions and 0 deletions
--- a/spice/ti/TLV70018_PSPICE_TRANS/TLV70018-PSpiceFiles/SCHEMATIC1/trans.sim
+++ b/spice/ti/TLV70018_PSPICE_TRANS/TLV70018-PSpiceFiles/SCHEMATIC1/trans.sim
@@ -0,0 +1,137 @@
+@OrCAD Simulation Server Version: 1.0
+
+@Settings: 0 1
+@General:
+ProfileName= "trans" 
+ProfileFile= "trans.sim" 
+Connectivity= "SCHEMATIC1.net" 
+NetlistFile= "trans.cir" 
+DataFile= "trans.dat" 
+OutFile= "trans.out" 
+Notes=
+@#$BEGINNOTES
+@#$ENDNOTES
+@End General
+@Analysis: 0 1
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--- a/spice/ti/TLV70018_PSPICE_TRANS/TLV70018-PSpiceFiles/SCHEMATIC1/trans/trans.mrk
+++ b/spice/ti/TLV70018_PSPICE_TRANS/TLV70018-PSpiceFiles/SCHEMATIC1/trans/trans.mrk
--- a/spice/ti/TLV70018_PSPICE_TRANS/TLV70018-PSpiceFiles/SCHEMATIC1/trans/trans.prb
+++ b/spice/ti/TLV70018_PSPICE_TRANS/TLV70018-PSpiceFiles/SCHEMATIC1/trans/trans.prb
@@ -0,0 +1,76 @@
+[DISPLAYS]
+BEGIN DISPLAY LAST SESSION
+ANALYSIS TRANSIENT_ANALYSIS
+SYMBOL ALWAYS
+TRACECOLORSCHEME NORMAL
+BEGIN ANAPLOT 1
+XBASE
+BEGIN XAXIS
+XAXISUSERNAME 0 (null)
+RANGEFLAG AUTO
+TYPE LINEAR
+UNIT s
+BEGIN GRIDS
+AUTOMATIC
+MAJORNUMBERS
+MAJORSTYLE LINES
+MAJORPATTERN SOLID
+MINORSTYLE LINES
+MINORPATTERN DOT
+END GRIDS
+END XAXIS
+BEGIN YAXIS 1
+YAXISSIDE LEFT
+ACTIVE
+RANGEFLAG AUTO
+TYPE LINEAR
+UNIT V
+BEGIN GRIDS
+AUTOMATIC
+MAJORNUMBERS
+MAJORSTYLE LINES
+MAJORPATTERN SOLID
+MINORSTYLE LINES
+MINORPATTERN DOT
+END GRIDS
+BEGIN TRACE V(Vout)
+MARKERID 1
+END TRACE V(Vout)
+END YAXIS 1
+END ANAPLOT 1
+BEGIN ANAPLOT 2
+ACTIVE
+BEGIN XAXIS
+XAXISUSERNAME 0 (null)
+RANGEFLAG AUTO
+TYPE LINEAR
+UNIT s
+BEGIN GRIDS
+AUTOMATIC
+MAJORNUMBERS
+MAJORSTYLE LINES
+MAJORPATTERN SOLID
+MINORSTYLE LINES
+MINORPATTERN DOT
+END GRIDS
+END XAXIS
+BEGIN YAXIS 1
+YAXISSIDE LEFT
+ACTIVE
+RANGEFLAG AUTO
+TYPE LINEAR
+UNIT V
+BEGIN GRIDS
+AUTOMATIC
+MAJORNUMBERS
+MAJORSTYLE LINES
+MAJORPATTERN SOLID
+MINORSTYLE LINES
+MINORPATTERN DOT
+END GRIDS
+BEGIN TRACE V(Vin)
+MARKERID 2
+END TRACE V(Vin)
+END YAXIS 1
+END ANAPLOT 2
+END DISPLAY LAST SESSION
--- a/spice/ti/TLV70018_PSPICE_TRANS/TLV70018.DSN
+++ b/spice/ti/TLV70018_PSPICE_TRANS/TLV70018.DSN
--- a/spice/ti/TLV70018_PSPICE_TRANS/TLV70018.OLB
+++ b/spice/ti/TLV70018_PSPICE_TRANS/TLV70018.OLB
--- a/spice/ti/TLV70018_PSPICE_TRANS/TLV70018.lib
+++ b/spice/ti/TLV70018_PSPICE_TRANS/TLV70018.lib
@@ -0,0 +1,70 @@
+**$ENCRYPTED_LIB
+**$INTERFACE
+* TLV70018 Model
+***************************************************************************
+** This product is designed as an aid for customers of Texas Instruments.**
+** No warranties, either expressed or implied, with respect to this third**
+** party software (if any) or with respect to its fitness for any        **
+** particular purpose is claimed by Texas Instruments or the author. The **
+** software (if any) is provided soley on an "as is" basis. The entire   **
+** risk as to its quality and performance is with the customer           **
+********************************************************************************
+* 
+* (C) Copyright 2011 Texas Instruments Incorporated  . All rights reserved.
+*
+* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
+* Part: TLV70018
+* Date: 04/05/2011
+* Model Type: TRANSIENT
+* Simulator: PSPICE
+* EVM Order Number: TLV70018EVM-503
+* EVM Users Guide: SLUU391 - DECEMBER 2009
+* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Final 1.00
+* Release to Web.
+*
+*********************************************************************************
+* source TLV70018
+*$
+.SUBCKT TLV70018 IN GND EN OUT
+$CDNENCSTART
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+$CDNENCFINISH
+.ENDS TLV70018
+*$
+.subckt SCHEMATIC1_TLV70018_F1 1 2 3 4  
+$CDNENCSTART
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+$CDNENCFINISH
+.ends SCHEMATIC1_TLV70018_F1
+*$
+
--- a/spice/ti/TLV70018_PSPICE_TRANS/TLV70018.opj
+++ b/spice/ti/TLV70018_PSPICE_TRANS/TLV70018.opj
@@ -0,0 +1,60 @@
+(ExpressProject "TLV70018"
+  (ProjectVersion "19981106")
+  (ProjectType "Analog or A/D Mixed Mode")
+  (Folder "Design Resources"
+    (Folder "Library")
+    (NoModify)
+    (File ".\tlv70018.dsn"
+      (Type "Schematic Design"))
+    (BuildFileAddedOrDeleted "x")
+    (CompileFileAddedOrDeleted "x")
+    (PSPICE_Regenerate_Netlist_Flag "FALSE"))
+  (Folder "Outputs"
+    (File ".\tlv70018-pspicefiles\schematic1\schematic1.net"
+      (Type "Report")))
+  (Folder "PSpice Resources"
+    (Folder "Simulation Profiles"
+      (ActiveProfile ".\tlv70018-pspicefiles\schematic1\trans.sim")
+      (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91}
+         ".\tlv70018-pspicefiles\schematic1\trans.sim"
+        (DisplayName "SCHEMATIC1-trans")
+        (Type "PSpice Profile")))
+    (Folder "Model Libraries"
+      (Sort User)
+      (File ".\tlv70018.lib"
+        (Type "PSpiceLibrary")
+        (DisplayName ".\tlv70018.lib")))
+    (Folder "Stimulus Files"
+      (Sort User))
+    (Folder "Include Files"
+      (Sort User)))
+  (DefaultLibraryBrowseDirectory "library\PSpice")
+  (PartMRUSelector
+    (TLV70018
+      (FullPartName "TLV70018.Normal")
+      (LibraryName
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70018\RELEASE_TI\PSPICE\TLV70018_PSPICE_TRANS\TLV70018.OLB")
+      (DeviceIndex "0")))
+  (GlobalState
+    (FileView
+      (Path "Design Resources")
+      (Path "Outputs"))
+    (HierarchyView)
+    (Doc
+      (Type "COrCapturePMDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 0 200 0 367"))
+      (Tab 0))
+    (Doc
+      (Type "COrSchematicDoc")
+      (Frame
+        (Placement "44 0 1 -1 -1 -1 -1 25 1251 25 556")
+        (Scroll "-104 0")
+        (Zoom "100")
+        (Occurrence "/"))
+      (Path
+         "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\PART_NUMBERS\TLV70018\RELEASE_TI\PSPICE\TLV70018_PSPICE_TRANS\TLV70018.DSN")
+      (Schematic "SCHEMATIC1")
+      (Page "PAGE1")))
+  (LastUsedLibraryBrowseDirectory
+     "C:\ELAB_MODEL_WS\ELAB_MODEL_DS\Part_Numbers\TLV70018\Release_TI\PSPICE\TLV70018_PSPICE_TRANS"))