updates
This commit is contained in:
200
spice/ti/SN74LVC1G00.cir
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200
spice/ti/SN74LVC1G00.cir
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********************************************************************************
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* SN74LVC1G00.cir
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* 1.0
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* 2018-11-16 00:00:00
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* Texas Instruments Incorporated.
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* Standard Logic, SLHR
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* 12500 TI Blvd
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* Dallas, TX -75243
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*
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*
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* Revision History:
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* Rev 2.0: 01/01/2019
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* - Model generated from datasheet values
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* - Built using generic logic gate behavioral pspice model V2
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* - Built using an automated model which generalizes parts under same family
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* - Performance is expected typical behavior at 25C
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* - Written for and tested with Tina-TI Version 9.3.100.244 SF-TI
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* - Accurate power consumption with dyanmic as well as static Icc
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*
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********************************************************************************
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*[Disclaimer]
|
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* This model is designed as an aid for customers of Texas Instruments.
|
||||
* TI and its licensors and suppliers make no warranties, either expressed
|
||||
* or implied, with respect to this model, including the warranties of
|
||||
* merchantability or fitness for a particular purpose. The model is
|
||||
* provided solely on an "as is" basis. The entire risk as to its quality
|
||||
* and performance is with the customer.
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*
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||||
*[Copyright]
|
||||
*(C) Copyright 2019 Texas Instruments Incorporated.All rights reserved.
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||||
*
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**
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********************************************************************************
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* SN74LVC1G00
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.SUBCKT SN74LVC1G00 Y A B VCC AGND
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XU1 Y A B VCC AGND LOGIC_GATE_2PIN_OD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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.ENDS
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.SUBCKT LOGIC_GATE_2PIN_OD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 OUT A B VCC GND
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.PARAM VCC_ABS_MAX = 6.5
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.PARAM VCC_MAX = 5.5
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.PARAM RA = 44000000
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.PARAM RB = 44000000
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||||
.PARAM CA = 4e-12
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.PARAM CB = 4e-12
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.PARAM ROEZ = 112.49999999999999
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.PARAM COEZ = 3e-12
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RA A GND {RA}
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RB B GND {RB}
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CA A GND {CA}
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CB B GND {CB}
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XUA NA A VCC GND LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XUB NB B VCC GND LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XUG NA NB NOUTG VCC GND LOGIC_FUNCTION_2_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XOUTPD NOUTG NOUTTPD VCC GND TPD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XUOUT NOUTTPD NOUT_INT VCC GND LOGIC_PP_OUTPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XICC VCC GND NVIOUT LOGIC_ICC_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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SICC VCC GND VCC GND SW1
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H1 NVIOUT GND VIOUT 1
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VIOUT NOUT_INT OUTsw 0
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SIOFF OUTsw OUT VCC GND SW2
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DA2 GND A D1
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DB2 GND B D1
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DO2 GND OUT D1
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RDA1 NA1 GND 1e6
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SDA1 NA1 A VCC GND SW2
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RDB1 NB1 GND 1e6
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SDB1 NB1 B VCC GND SW2
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RDO1 NO1 GND 1e6
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SDO1 NO1 OUT VCC GND SW2
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.MODEL SW1 VSWITCH VON = {VCC_ABS_MAX} VOFF = {VCC_MAX} RON = 10 ROFF = 60e6
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.MODEL SW2 VSWITCH VON = {0.55} VOFF = {0.45} RON = 10m ROFF = 100e6
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.MODEL D1 D
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.ENDS
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.SUBCKT LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 OUT IN VCC VEE
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.PARAM STANDARD_INPUT_SELECT = 1
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.PARAM SCHMITT_TRIGGER_INPUT_SELECT = 0
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ESTD_THR VSTD_THR VEE TABLE {V(VCC,VEE)} =
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+(1,0.5)
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+(1.8,0.9)
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+(2.5,1.25)
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+(3.3,1.65)
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+(5,2.5)
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+(6,3)
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ETRP_P VTRP_P VEE TABLE {V(VCC,VEE)} =
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+(2.5,1.4)
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+(3.3,1.9)
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+(5,3.25)
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ETRP_N VTRP_N VEE TABLE {V(VCC,VEE)} =
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+(2.5,1.15)
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+(3.3,1.5)
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+(5,2.25)
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EHYST VHYST VEE TABLE {V(VCC,VEE)} =
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+(2.5,0.6)
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+(3.3,0.75)
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+(5,1.25)
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ETRUE NTRUE VEE VALUE = {V(VCC,VEE)}
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EFALSE NFALSE VEE VALUE = {0}
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EBETA BETA VEE VALUE = {V(VHYST,VEE)/(V(NTRUE,VEE) - V(NFALSE,VEE) + V(VHYST,VEE))}
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EFB NFB VEE VALUE = {(1 - V(BETA,VEE))*V(IN,VEE) + V(BETA,VEE)*V(CURR_OUT,VEE)}
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EREF NREF VEE VALUE = {0.5*(1 - V(BETA,VEE))*(V(VTRP_P,VEE) + V(VTRP_N,VEE))
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+ + 0.5*V(BETA,VEE)*(V(NTRUE,VEE) + V(NFALSE,VEE))}
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EDIFF NDIFF VEE VALUE = {V(NFB,NREF)}
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ESWITCH VSWITCH VEE VALUE = {0.5*(-SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
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ESWITCH1 VSWITCH1 VEE VALUE = {0.5*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
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GCOMP VEE CURR_OUT VALUE = {SCHMITT_TRIGGER_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
|
||||
|
||||
GSTD VEE CURR_OUT VALUE = {STANDARD_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(IN,VSTD_THR)) + ABS(SGN(V(IN,VSTD_THR))))}
|
||||
ROUT CURR_OUT VEE 1
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EMID MID VEE VALUE = {0.5*(V(VCC,VEE) + V(VEE))}
|
||||
EARG NARG VEE VALUE = {V(CURR_OUT,VEE) - V(MID,VEE)}
|
||||
EOUT OUT VEE VALUE = {0.5*(SGN(V(NARG,VEE)) + ABS(SGN(V(NARG,VEE) ) ) )}
|
||||
|
||||
.PARAM MAXICC = .0009
|
||||
.PARAM VT = .7
|
||||
.PARAM VCC_MIN = 3
|
||||
|
||||
EV_VT1 VTN VEE VALUE = { VT }
|
||||
EV_VT2 VTP VEE VALUE = { V(VCC,VEE) - VT }
|
||||
|
||||
ETEST TEST VEE VALUE = {.9*V(VCC,VEE)}
|
||||
|
||||
EVTHDIFF VTH_DIFF VEE VALUE = {V(IN,VSTD_THR)}
|
||||
EVTHPDIFF VTHP_DIFF VEE VALUE = {V(IN,VTRP_P)}
|
||||
EVTHNDIFF VTHN_DIFF VEE VALUE = {V(IN,VTRP_N)}
|
||||
EVTNDIFF VTN_DIFF VEE VALUE = { V(IN,VTN) }
|
||||
EVTPDIFF VTP_DIFF VEE VALUE = { V(IN,VTP) }
|
||||
|
||||
|
||||
GICCVA VCC VEE VALUE = { (-ABS(( (1+SGN(V(VTN_DIFF,VEE)) ) )/2 -1) *
|
||||
+ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
|
||||
GICCVB VCC VEE VALUE = { (ABS(( (1+SGN(V(VTHP_DIFF,VEE)) ) )/2 -1) *
|
||||
+ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
|
||||
GICCVC VCC VEE VALUE = { ( ABS( (1+SGN(V(VTHN_DIFF,VEE)) ) )/2 *
|
||||
+ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
|
||||
GICCVD VCC VEE VALUE = { (-ABS( (1+SGN(V(VTP_DIFF,VEE)) ) )/2 *
|
||||
+ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
|
||||
|
||||
.ENDS
|
||||
.SUBCKT LOGIC_FUNCTION_2_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 A B OUT VCC VEE
|
||||
.PARAM AND = 0
|
||||
.PARAM NAND = 1
|
||||
.PARAM OR = 0
|
||||
.PARAM NOR = 0
|
||||
.PARAM XOR = 0
|
||||
.PARAM XNOR = 0
|
||||
GAND VEE N1 VALUE = {AND*V(A,VEE)*V(B,VEE)}
|
||||
GNAND VEE N1 VALUE = {NAND*(1 - V(A,VEE)*V(B,VEE))}
|
||||
GOR VEE N1 VALUE = {OR*(MIN(V(A,VEE) + V(B,VEE),1))}
|
||||
GNOR VEE N1 VALUE = {NOR*(1 - MIN(V(A,VEE) + V(B,VEE),1))}
|
||||
GXOR VEE N1 VALUE = {XOR*((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE)))}
|
||||
GXNOR VEE N1 VALUE = {XNOR*(1 - ((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE))))}
|
||||
RN1 N1 VEE 1
|
||||
EOUT OUT VEE N1 VEE 1
|
||||
.ENDS
|
||||
.SUBCKT TPD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 IN OUT VCC VEE
|
||||
.PARAM TPDELAY1 = 1N
|
||||
.PARAM RS = 10K
|
||||
.PARAM CS = {-TPDELAY1/(RS*LOG(0.5))}
|
||||
ETPDNORM NTPDNORM VEE TABLE {V(VCC,VEE)} =
|
||||
+(1.8,4.7)
|
||||
+(2.5,2.65)
|
||||
+(3.3,2.3)
|
||||
+(5,2.1)
|
||||
G1 IN N1 VALUE = {V(IN,N1)/(V(NTPDNORM,VEE)*RS)}
|
||||
RZ IN N1 10G
|
||||
C1 N1 VEE {CS}
|
||||
E1 N2 VEE VALUE = {0.5*(1 + SGN(V(N1,VEE) - 0.5))}
|
||||
EOUT OUT VEE N2 VEE 1
|
||||
.ENDS
|
||||
.SUBCKT LOGIC_PP_OUTPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 IN OUT VCC VEE
|
||||
EROH NROH VEE TABLE {V(VCC,VEE)} =
|
||||
+(1.65,112.5)
|
||||
+(2.3,50)
|
||||
+(3,25)
|
||||
+(4.5,21.875)
|
||||
EROL NROL VEE TABLE {V(VCC,VEE)} =
|
||||
+(1.65,112.5)
|
||||
+(2.3,37.5)
|
||||
+(3,22.9166666666667)
|
||||
+(4.5,17.5)
|
||||
E1 N1 VEE VALUE = {V(VCC,VEE)*V(IN,VEE)}
|
||||
GOUT N1 OUT VALUE = {V(N1,OUT)*(V(IN,VEE)/V(NROH,VEE) + (1 - V(IN,VEE))/V(NROL,VEE))}
|
||||
.ENDS
|
||||
.SUBCKT LOGIC_ICC_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 VCC VEE VIOUT
|
||||
.PARAM ICC = 2.5e-07
|
||||
.PARAM VCC_MAX = 5.5
|
||||
.PARAM VCC_MIN = 1.65
|
||||
GICC VCC VEE VALUE = {ICC*0.5*(1 + SGN(V(VCC,VEE) - VCC_MIN))}
|
||||
EGNDF GNDF 0 VALUE = {0.5*(V(VCC) + V(VEE))}
|
||||
GOUTP VCC GNDF VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))}
|
||||
GOUTN GNDF VEE VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))}
|
||||
.ENDS
|
||||
70
spice/ti/TLV70012.lib
Normal file
70
spice/ti/TLV70012.lib
Normal file
@@ -0,0 +1,70 @@
|
||||
**$ENCRYPTED_LIB
|
||||
**$INTERFACE
|
||||
* TLV70012 Model
|
||||
***************************************************************************
|
||||
** This product is designed as an aid for customers of Texas Instruments.**
|
||||
** No warranties, either expressed or implied, with respect to this third**
|
||||
** party software (if any) or with respect to its fitness for any **
|
||||
** particular purpose is claimed by Texas Instruments or the author. The **
|
||||
** software (if any) is provided soley on an "as is" basis. The entire **
|
||||
** risk as to its quality and performance is with the customer **
|
||||
********************************************************************************
|
||||
*
|
||||
* (C) Copyright 2011 Texas Instruments Incorporated . All rights reserved.
|
||||
*
|
||||
* Released by: Analog e-Lab Design Center, Texas Instruments Inc.
|
||||
* Part: TLV70012
|
||||
* Date: 04/05/2011
|
||||
* Model Type: TRANSIENT
|
||||
* Simulator: PSPICE
|
||||
* EVM Order Number:
|
||||
* EVM Users Guide:
|
||||
* Datasheet: SLVSA00B - SEPTEMBER 2009 - REVISED DECEMBER 2010
|
||||
*
|
||||
*****************************************************************************
|
||||
*
|
||||
* Updates:
|
||||
*
|
||||
* Final 1.00
|
||||
* Release to Web.
|
||||
*
|
||||
*********************************************************************************
|
||||
* source TLV70012
|
||||
*$
|
||||
.SUBCKT TLV70012 IN GND EN OUT
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dce2e9103f51d0de79
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
af1dff2e8151d1b3ed846c24bda46d96f5687491f31f292410977954546a053dca2f8c83eb5775a39c064bf94d8ce6078492e52ca990713779eccb7eaf03f4e4
|
||||
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|
||||
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|
||||
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|
||||
a96c53d84a6e3a2c777909964b84d5bf2b81e10e996e19ac294ff995b8f67f658ae9764513fec3e28e779e2db5abbf64f4f2ab4e4c8c394ffa8db939ff1224c4
|
||||
cd080d6014ef79b45b21fcbb5127d82b1bddfb574903d61a725ed083df9a515d637d1b072f0e2ebed3bdfb0233d3746a97fd1405997c9bbe211952a674e6752c
|
||||
ce1e320d9877b21bc90ba24b54740a7aa7d24ab7ae54f3c7cb82e1066e82af78e73070a45f1d549c8ae9764513fec3e28e779e2db5abbf646871dc705148aaae
|
||||
259e22a51c65bc4d183fce15e18b18aacd9f9b0fe66d8ad14e837baae6a4ac8864615adc73efa6325ff6f42c959550fbd48c1d14d1b0c61c2ba2c1c1728c017b
|
||||
259e22a51c65bc4d695c770f0bec7fcc4e552c8ab90b219a605c5accbc975768c76c6f59598c925ec90ba24b54740a7ab286dd1121d2a6d23c33417d989f4d2c
|
||||
79b347c5b85360ef9dd0e5cec1514afc4e552c8ab90b219a64615adc73efa632d9ae151f53d140db68bc7b4cd898b01306ea93996f83a7bddf7a8af3bf3808c1
|
||||
79b347c5b85360ef9161d902182c168c4e552c8ab90b219a64615adc73efa63203713b4f43695ba78c0e8091394b9856ac0bbcb25a375ea3a3326a35d52f6cdd
|
||||
259e22a51c65bc4d1db1e7e640c0f26a4e552c8ab90b219a64615adc73efa63218909a58bd8b76908c0e8091394b985661a0613e3a41a223d38aff4e12555a5d
|
||||
d153893f36515c509a2f4988e6fd1384e3d4223c66a65ea17c3d70f9a365ec31fc8a520169f0e78fad7181505892a4c88e95fdd389b2972f9e301436d16375b1
|
||||
c90ba24b54740a7accefcc2bf8692e3b8ae9764513fec3e28e779e2db5abbf64f4f2ab4e4c8c394f02f29020cc6bed9a5594c975cd36d3d3456e122046cc1edb
|
||||
$CDNENCFINISH
|
||||
.ENDS TLV70012
|
||||
*$
|
||||
.subckt SCHEMATIC1_TLV70012_F1 1 2 3 4
|
||||
$CDNENCSTART
|
||||
eee8c5c7a2bc4b01f045f303678664e7916da0bae22e8cb0bba041dd67c69ce448ea70148a9ac1670c8926c1ac5057c8ccfcd77bf87ca9dce2e9103f51d0de79
|
||||
4f9bfd860debeaf29a2f4988e6fd138446b92e86e8aaa0ba6346aa19326e7599631ebabd5b20ecbf57e2c5aa80851370dcb2222a3ac73375375bc7f7c20b6cb9
|
||||
476007b7708ce3cdb942d935367989681852d2bae2562872b9ef19aa8805d3198e3bef92b0a3919088b82ad28ee6d41b53c9f4b6d37454d87b866626a673e230
|
||||
$CDNENCFINISH
|
||||
.ends SCHEMATIC1_TLV70012_F1
|
||||
*$
|
||||
|
||||
BIN
spice/ti/slvm171.zip
Normal file
BIN
spice/ti/slvm171.zip
Normal file
Binary file not shown.
Reference in New Issue
Block a user