201 lines
7.1 KiB
Plaintext
201 lines
7.1 KiB
Plaintext
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********************************************************************************
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* SN74LVC1G00.cir
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* 1.0
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* 2018-11-16 00:00:00
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* Texas Instruments Incorporated.
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* Standard Logic, SLHR
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* 12500 TI Blvd
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* Dallas, TX -75243
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*
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*
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* Revision History:
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* Rev 2.0: 01/01/2019
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* - Model generated from datasheet values
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* - Built using generic logic gate behavioral pspice model V2
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* - Built using an automated model which generalizes parts under same family
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* - Performance is expected typical behavior at 25C
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* - Written for and tested with Tina-TI Version 9.3.100.244 SF-TI
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* - Accurate power consumption with dyanmic as well as static Icc
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*
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********************************************************************************
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*[Disclaimer]
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* This model is designed as an aid for customers of Texas Instruments.
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* TI and its licensors and suppliers make no warranties, either expressed
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* or implied, with respect to this model, including the warranties of
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* merchantability or fitness for a particular purpose. The model is
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* provided solely on an "as is" basis. The entire risk as to its quality
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* and performance is with the customer.
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*
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*[Copyright]
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*(C) Copyright 2019 Texas Instruments Incorporated.All rights reserved.
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*
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**
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********************************************************************************
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* SN74LVC1G00
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.SUBCKT SN74LVC1G00 Y A B VCC AGND
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XU1 Y A B VCC AGND LOGIC_GATE_2PIN_OD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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.ENDS
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.SUBCKT LOGIC_GATE_2PIN_OD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 OUT A B VCC GND
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.PARAM VCC_ABS_MAX = 6.5
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.PARAM VCC_MAX = 5.5
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.PARAM RA = 44000000
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.PARAM RB = 44000000
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.PARAM CA = 4e-12
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.PARAM CB = 4e-12
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.PARAM ROEZ = 112.49999999999999
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.PARAM COEZ = 3e-12
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RA A GND {RA}
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RB B GND {RB}
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CA A GND {CA}
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CB B GND {CB}
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XUA NA A VCC GND LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XUB NB B VCC GND LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XUG NA NB NOUTG VCC GND LOGIC_FUNCTION_2_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XOUTPD NOUTG NOUTTPD VCC GND TPD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XUOUT NOUTTPD NOUT_INT VCC GND LOGIC_PP_OUTPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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XICC VCC GND NVIOUT LOGIC_ICC_LVC_2i_NAND_PP_CMOS_SN74LVC1G00
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SICC VCC GND VCC GND SW1
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H1 NVIOUT GND VIOUT 1
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VIOUT NOUT_INT OUTsw 0
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SIOFF OUTsw OUT VCC GND SW2
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DA2 GND A D1
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DB2 GND B D1
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DO2 GND OUT D1
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RDA1 NA1 GND 1e6
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SDA1 NA1 A VCC GND SW2
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RDB1 NB1 GND 1e6
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SDB1 NB1 B VCC GND SW2
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RDO1 NO1 GND 1e6
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SDO1 NO1 OUT VCC GND SW2
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.MODEL SW1 VSWITCH VON = {VCC_ABS_MAX} VOFF = {VCC_MAX} RON = 10 ROFF = 60e6
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.MODEL SW2 VSWITCH VON = {0.55} VOFF = {0.45} RON = 10m ROFF = 100e6
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.MODEL D1 D
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.ENDS
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.SUBCKT LOGIC_INPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 OUT IN VCC VEE
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.PARAM STANDARD_INPUT_SELECT = 1
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.PARAM SCHMITT_TRIGGER_INPUT_SELECT = 0
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ESTD_THR VSTD_THR VEE TABLE {V(VCC,VEE)} =
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+(1,0.5)
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+(1.8,0.9)
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+(2.5,1.25)
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+(3.3,1.65)
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+(5,2.5)
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+(6,3)
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ETRP_P VTRP_P VEE TABLE {V(VCC,VEE)} =
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+(2.5,1.4)
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+(3.3,1.9)
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+(5,3.25)
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ETRP_N VTRP_N VEE TABLE {V(VCC,VEE)} =
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+(2.5,1.15)
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+(3.3,1.5)
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+(5,2.25)
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EHYST VHYST VEE TABLE {V(VCC,VEE)} =
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+(2.5,0.6)
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+(3.3,0.75)
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+(5,1.25)
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ETRUE NTRUE VEE VALUE = {V(VCC,VEE)}
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EFALSE NFALSE VEE VALUE = {0}
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EBETA BETA VEE VALUE = {V(VHYST,VEE)/(V(NTRUE,VEE) - V(NFALSE,VEE) + V(VHYST,VEE))}
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EFB NFB VEE VALUE = {(1 - V(BETA,VEE))*V(IN,VEE) + V(BETA,VEE)*V(CURR_OUT,VEE)}
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EREF NREF VEE VALUE = {0.5*(1 - V(BETA,VEE))*(V(VTRP_P,VEE) + V(VTRP_N,VEE))
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+ + 0.5*V(BETA,VEE)*(V(NTRUE,VEE) + V(NFALSE,VEE))}
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EDIFF NDIFF VEE VALUE = {V(NFB,NREF)}
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ESWITCH VSWITCH VEE VALUE = {0.5*(-SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
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ESWITCH1 VSWITCH1 VEE VALUE = {0.5*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
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GCOMP VEE CURR_OUT VALUE = {SCHMITT_TRIGGER_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))}
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GSTD VEE CURR_OUT VALUE = {STANDARD_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(IN,VSTD_THR)) + ABS(SGN(V(IN,VSTD_THR))))}
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ROUT CURR_OUT VEE 1
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EMID MID VEE VALUE = {0.5*(V(VCC,VEE) + V(VEE))}
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EARG NARG VEE VALUE = {V(CURR_OUT,VEE) - V(MID,VEE)}
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EOUT OUT VEE VALUE = {0.5*(SGN(V(NARG,VEE)) + ABS(SGN(V(NARG,VEE) ) ) )}
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.PARAM MAXICC = .0009
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.PARAM VT = .7
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.PARAM VCC_MIN = 3
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EV_VT1 VTN VEE VALUE = { VT }
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EV_VT2 VTP VEE VALUE = { V(VCC,VEE) - VT }
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ETEST TEST VEE VALUE = {.9*V(VCC,VEE)}
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EVTHDIFF VTH_DIFF VEE VALUE = {V(IN,VSTD_THR)}
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EVTHPDIFF VTHP_DIFF VEE VALUE = {V(IN,VTRP_P)}
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EVTHNDIFF VTHN_DIFF VEE VALUE = {V(IN,VTRP_N)}
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EVTNDIFF VTN_DIFF VEE VALUE = { V(IN,VTN) }
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EVTPDIFF VTP_DIFF VEE VALUE = { V(IN,VTP) }
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GICCVA VCC VEE VALUE = { (-ABS(( (1+SGN(V(VTN_DIFF,VEE)) ) )/2 -1) *
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+ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
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GICCVB VCC VEE VALUE = { (ABS(( (1+SGN(V(VTHP_DIFF,VEE)) ) )/2 -1) *
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+ 2*MAXICC*((V(IN,VEE)-VT)/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH,VEE)}
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GICCVC VCC VEE VALUE = { ( ABS( (1+SGN(V(VTHN_DIFF,VEE)) ) )/2 *
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+ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
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GICCVD VCC VEE VALUE = { (-ABS( (1+SGN(V(VTP_DIFF,VEE)) ) )/2 *
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+ 2*MAXICC*((V(IN,VEE)-(V(VCC,VEE)-VT))/V(VCC,VEE))^2)*(1 + SGN(V(VCC,VEE) - VCC_MIN))*V(VSWITCH1,VEE)}
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.ENDS
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.SUBCKT LOGIC_FUNCTION_2_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 A B OUT VCC VEE
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.PARAM AND = 0
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.PARAM NAND = 1
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.PARAM OR = 0
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.PARAM NOR = 0
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.PARAM XOR = 0
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.PARAM XNOR = 0
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GAND VEE N1 VALUE = {AND*V(A,VEE)*V(B,VEE)}
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GNAND VEE N1 VALUE = {NAND*(1 - V(A,VEE)*V(B,VEE))}
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GOR VEE N1 VALUE = {OR*(MIN(V(A,VEE) + V(B,VEE),1))}
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GNOR VEE N1 VALUE = {NOR*(1 - MIN(V(A,VEE) + V(B,VEE),1))}
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GXOR VEE N1 VALUE = {XOR*((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE)))}
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GXNOR VEE N1 VALUE = {XNOR*(1 - ((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE))))}
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RN1 N1 VEE 1
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EOUT OUT VEE N1 VEE 1
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.ENDS
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.SUBCKT TPD_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 IN OUT VCC VEE
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.PARAM TPDELAY1 = 1N
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.PARAM RS = 10K
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.PARAM CS = {-TPDELAY1/(RS*LOG(0.5))}
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ETPDNORM NTPDNORM VEE TABLE {V(VCC,VEE)} =
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+(1.8,4.7)
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+(2.5,2.65)
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+(3.3,2.3)
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+(5,2.1)
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G1 IN N1 VALUE = {V(IN,N1)/(V(NTPDNORM,VEE)*RS)}
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RZ IN N1 10G
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C1 N1 VEE {CS}
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E1 N2 VEE VALUE = {0.5*(1 + SGN(V(N1,VEE) - 0.5))}
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EOUT OUT VEE N2 VEE 1
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.ENDS
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.SUBCKT LOGIC_PP_OUTPUT_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 IN OUT VCC VEE
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EROH NROH VEE TABLE {V(VCC,VEE)} =
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+(1.65,112.5)
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+(2.3,50)
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+(3,25)
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+(4.5,21.875)
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EROL NROL VEE TABLE {V(VCC,VEE)} =
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+(1.65,112.5)
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+(2.3,37.5)
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+(3,22.9166666666667)
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+(4.5,17.5)
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E1 N1 VEE VALUE = {V(VCC,VEE)*V(IN,VEE)}
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GOUT N1 OUT VALUE = {V(N1,OUT)*(V(IN,VEE)/V(NROH,VEE) + (1 - V(IN,VEE))/V(NROL,VEE))}
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.ENDS
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.SUBCKT LOGIC_ICC_LVC_2i_NAND_PP_CMOS_SN74LVC1G00 VCC VEE VIOUT
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.PARAM ICC = 2.5e-07
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.PARAM VCC_MAX = 5.5
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.PARAM VCC_MIN = 1.65
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GICC VCC VEE VALUE = {ICC*0.5*(1 + SGN(V(VCC,VEE) - VCC_MIN))}
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EGNDF GNDF 0 VALUE = {0.5*(V(VCC) + V(VEE))}
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GOUTP VCC GNDF VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))}
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GOUTN GNDF VEE VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))}
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.ENDS
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