112 lines
2.3 KiB
Plaintext
112 lines
2.3 KiB
Plaintext
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* AD840 SPICE Macro-model
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* Description: Amplifier
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* Generic Desc: WIDEBAND,FAST SETTLING OP AMP
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* Developed by: AAG / PMI
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* Revision History: 08/10/2012 - Updated to new header style
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* 1.0 (01/1991)
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* Copyright 1991, 2012 by Analog Devices, Inc.
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*
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* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
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* indicates your acceptance with the terms and provisions in the License Statement.
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*
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* BEGIN Notes:
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*
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* Not Modeled:
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*
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* Parameters modeled include:
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*
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* END Notes
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*
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* Node assignments
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* non-inverting input
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* | inverting input
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* | | positive supply
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* | | | negative supply
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* | | | | output
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* | | | | |
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.SUBCKT AD840 1 2 100 101 36
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*
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* INPUT STAGE & POLE AT 120 MHz
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*
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IOS 1 2 DC 0.05E-6
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CIN 1 2 2E-12
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R1 1 3 15E3
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R2 2 3 15E3
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EOS 9 1 POLY(1) 16 11 200E-6 1
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R3 100 5 223.38
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R4 100 6 223.38
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C2 5 6 2.9687E-12
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R5 7 4 171.66
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R6 8 4 171.66
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Q1 5 2 7 QX
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Q2 6 9 8 QX
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I1 4 101 DC 1E-3
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*
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* VIRTUAL NODE
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*
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RVN1 100 10 25E3
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RVN2 10 101 25E3
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*
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* GAIN STAGE & DOMINANT POLE AT 2.1923 KHz
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*
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EREF 11 0 10 0 1
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G1 11 12 5 6 4.4768E-3
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R7 12 11 29.039E6
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C3 12 11 2.5E-12
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V1 100 13 DC 2.4375
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D1 12 13 DX
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V2 14 101 DC 2.4375
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D2 14 12 DX
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*
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* COMMON-MODE GAIN NETWORK WITH ZERO AT 20 KHz
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*
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ECM 15 11 3 11 3.1623
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RCM1 15 16 1E6
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CCM 15 16 7.9577E-12
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RCM2 16 11 1
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*
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* NEGATIVE ZERO STAGE AT 290 MHz
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*
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EZ1 17 11 12 11 1E6
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RZ1 17 18 1
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CZ1 17 18 -548.81E-12
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RZ2 18 11 1E-6
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*
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* POLE STAGE AT 500 MHz
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*
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GP1 11 19 18 11 1E-6
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RP1 19 11 1E6
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CP1 19 11 318.31E-18
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*
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* OUTPUT STAGE
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*
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IDC 100 101 DC 8.9E-3
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VX 19 30
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V3 32 35 DC 2.725
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D3 30 32 DX
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V4 35 33 DC 2.575
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D4 33 30 DX
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D5 100 31 DX
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GO1 31 101 30 35 16.667E-3
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D6 101 31 DY
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D7 100 34 DX
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GO2 34 101 35 30 16.667E-3
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D8 101 34 DY
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RO1 100 35 60
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GO3 35 100 100 30 16.667E-3
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RO2 35 101 60
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GO4 101 35 30 101 16.667E-3
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LO 35 36 0.04E-6
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*
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* MODELS USED
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*
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.MODEL QX NPN(BF=142.86)
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.MODEL DX D(IS=1E-15)
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.MODEL DY D(IS=1E-15 BV=50)
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.ENDS
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