// Author:  Brendan Haines
// Date:    2021-07-02

`timescale 1ns/1ps

module tb_top();

reg clk, reset;
wire [7:0] led;

top dut(
    .clk(clk),
    .n_reset(~reset),
    .led(led)
);

always #5 clk = ~clk;

initial begin
    $dumpfile("tb_top.vcd");
    $dumpvars(0, tb_top);

    clk = 0;
    reset = 1;

    #10
    reset = 0;

    #2560
    // #2560
    $display("----------");
    $display("Finished simulation.");
    $display("Simulation time:\t%d ns", $realtime);
    $finish;
end

endmodule