# RISC-V CPU

Short Term To Do:
- [ ] add stalls for memory access
- [ ] use AXI for memory access (depends on AXIL memory module for test)
- [ ] add tests for non-pipelined case
- [ ] get C working (may depend on memory stalls)

Desired features:
- [ ] 1- or 5-stage pipeline selectable via parameter
- [ ] AXI-lite Master for both instruction and data memory
- [ ] 32, 64, (or 128?) bit word size
- [ ] floating point
- [ ] multiplication
- [ ] division
- [ ] instruction and data caches
- [ ] JTAG debug probe

## Resources
* [AXI4 Protocol Specification](https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification?lang=en)
* [JTAG Bus Description](https://web.archive.org/web/20230314233136/http://www.interfacebus.com/Design_Connector_JTAG_Bus.html)
* [1149.1-2013 - IEEE Standard for Test Access Port and Boundary-Scan Architecture](https://ieeexplore.ieee.org/document/6515989)