XILINX = /opt/Xilinx/14.7/ISE_DS/ISE/
PROJECT = riscv_core
TARGET_PART = xc6slx25-3-ftg256

VSOURCE = hdl/core.v hdl/top.v
# VHDSOURCE = hdl/*.vhd

VTEST = hdl/tb/core_tb.v
# VHDTEST = hdl/tb/*.vhd
TB = core_tb

# XILINX_PLATFORM = lin64

TOPLEVEL = top
CONSTRAINTS = pins.ucf
# COMMON_OPTS =
# XST_OPTS = 
# NGDBUILD_OPTS = 
MAP_OPTS = -mt 2 -ol high
PAR_OPTS = -mt 4 -ol high
# BITGEN_OPTS = -g Compress
# TRACE_OPTS = 
# FUSE_OPTS = 

PROGRAMMER = xc3sprog
XC3SPROG_CABLE = ftdi