`timescale 1 ns / 1 ps 

module core_tb();

initial $timeformat(-9, 2, " ns", 20);

localparam  MEM_INST_LENGTH = 256;
localparam  MEM_DATA_LENGTH = 256;

localparam  INST_NOP = 32'h00000013;  // nop

reg clk, reset;
reg [31:0] mem_inst [0:MEM_INST_LENGTH-1];
wire [31:0] mem_inst_addr;
wire [31:0] mem_inst_idx = mem_inst_addr >> 2;
wire [31:0] mem_inst_data = mem_inst_idx < MEM_INST_LENGTH ? mem_inst[mem_inst_idx] : INST_NOP;

wire dummy_out;

initial begin: mem_inst_init
    integer i;
    for (i=0; i<MEM_INST_LENGTH; i=i+1) begin
        mem_inst[i] = INST_NOP;
    end
    $readmemh("../test/test.hex", mem_inst);
end

reg [31:0] mem_data [0:MEM_DATA_LENGTH-1];
wire [31:0] mem_data_waddr;
wire [31:0] mem_data_wdata;
wire [3:0] mem_data_wmask;
wire mem_data_we;
wire [31:0] mem_data_raddr;
reg [31:0] mem_data_rdata;
wire [3:0] mem_data_rmask;

initial begin
    #0
    clk = 0;
    reset = 1;
    
    #20
    reset = 0;
    
    #5000
    reset = 1;
    $stop;
end

always #10 clk  = !clk;

core dut(
    .clk(clk),
    .reset(reset),

    .mem_inst_addr(mem_inst_addr),
    .mem_inst_data(mem_inst_data),

    // .mem_data_addr(mem_data_addr),
    // .mem_data_wdata(mem_data_wdata),
    // .mem_data_rdata(mem_data_rdata),
    // .mem_data_en(mem_data_en),
    // .mem_data_we(mem_data_we),
    // .mem_data_valid(mem_data_valid),
    // .mem_data_done(mem_data_done)

    .dummy_out(dummy_out)
);

wire axi_mem_data_awvalid;
wire [11:0] axi_mem_data_awaddr;
wire [2:0] axi_mem_data_awprot;
wire axi_mem_data_awready;
wire axi_mem_data_wvalid;
wire [31:0] axi_mem_data_wdata;
wire [3:0] axi_mem_data_wstrb;
wire axi_mem_data_wready;
wire axi_mem_data_bvalid;
wire axi_mem_data_bready;
wire [1:0] axi_mem_data_bresp;
wire axi_mem_data_arvalid;
wire [11:0] axi_mem_data_araddr;
wire [2:0] axi_mem_data_arprot;
wire axi_mem_data_arready;
wire axi_mem_data_rvalid;
wire [31:0] axi_mem_data_rdata;
wire [1:0] axi_mem_data_resp;
wire axi_mem_data_rready;

axi_lite_memory axi_mem_data(
    .ACLK(clk),
    .ARESETn(!reset),
    .AWVALID(axi_mem_data_awvalid),
    .AWADDR(axi_mem_data_awaddr),
    .AWPROT(axi_mem_data_awprot),
    .AWREADY(axi_mem_data_awready),
    .WVALID(axi_mem_data_wvalid),
    .WDATA(axi_mem_data_wdata),
    .WSTRB(axi_mem_data_wstrb),
    .WREADY(axi_mem_data_wready),
    .BVALID(axi_mem_data_bvalid),
    .BREADY(axi_mem_data_bready),
    .BRESP(axi_mem_data_bresp),
    .ARVALID(axi_mem_data_arvalid),
    .ARADDR(axi_mem_data_araddr),
    .ARPROT(axi_mem_data_arprot),
    .ARREADY(axi_mem_data_arready),
    .RVALID(axi_mem_data_rvalid),
    .RDATA(axi_mem_data_rdata),
    .RRESP(axi_mem_data_resp),
    .RREADY(axi_mem_data_rready),

    .WB_WADDR(mem_data_waddr),
    .WB_WPROT(),
    .WB_WDATA(mem_data_wdata),
    .WB_WSTRB(mem_data_wmask),
    .WB_WVALID(mem_data_we),
    .WB_WREADY(1'b1),

    .WB_RADDR(mem_data_raddr),
    .WB_RDATA(mem_data_rdata),
    .WB_RVALID(1'b1),
    .WB_RREADY()
);

wire [31:0] mem_data_widx = mem_data_waddr >> 2;
always @(posedge clk) begin
    if (mem_data_we) begin
        if (mem_data_widx < MEM_DATA_LENGTH) begin
            mem_inst[mem_data_widx] <= (mem_inst[mem_data_widx] & ~{{8{mem_data_wmask[3]}}, {8{mem_data_wmask[2]}}, {8{mem_data_wmask[1]}}, {8{mem_data_wmask[0]}}}) | (mem_data_wdata & {{8{mem_data_wmask[3]}}, {8{mem_data_wmask[2]}}, {8{mem_data_wmask[1]}}, {8{mem_data_wmask[0]}}});
        end
        // ignore illegal writes
    end
end

wire [31:0] mem_data_ridx = mem_data_raddr >> 2;
always @(*) begin
    if (mem_data_ridx < MEM_DATA_LENGTH) begin
        mem_data_rdata = mem_inst[mem_data_ridx] & {{8{mem_data_rmask[3]}}, {8{mem_data_rmask[2]}}, {8{mem_data_rmask[1]}}, {8{mem_data_rmask[0]}}};
    end else begin
        mem_data_rdata = 32'h00000000;
    end
end



endmodule