diff --git a/src/bh_cpu.v b/src/bh_cpu.v
index da8c6a9..cf8907a 100644
--- a/src/bh_cpu.v
+++ b/src/bh_cpu.v
@@ -280,9 +280,9 @@ always @(*) begin
                 10'b100xxxxxxx: s_id_aluop = ALUOP_XOR;     // XORI
                 10'b110xxxxxxx: s_id_aluop = ALUOP_OR;      // ORI
                 10'b111xxxxxxx: s_id_aluop = ALUOP_AND;     // ANDI
-                10'b001000000x: s_id_aluop = ALUOP_SL;      // SLLI     // NOTE: technically s_id_funct7[0] must be 0 however GCC allows shifts of up to 63b despite assembling for 32b. I can tolerate this deviation from ISA spec at essentially no cost
-                10'b101000000x: s_id_aluop = ALUOP_SRL;     // SRLI     // NOTE: technically s_id_funct7[0] must be 0 however GCC allows shifts of up to 63b despite assembling for 32b. I can tolerate this deviation from ISA spec at essentially no cost
-                10'b101010000x: s_id_aluop = ALUOP_SRA;     // SRAI     // NOTE: technically s_id_funct7[0] must be 0 however GCC allows shifts of up to 63b despite assembling for 32b. I can tolerate this deviation from ISA spec at essentially no cost
+                10'b0010000000: s_id_aluop = ALUOP_SL;      // SLLI
+                10'b1010000000: s_id_aluop = ALUOP_SRL;     // SRLI
+                10'b1010100000: s_id_aluop = ALUOP_SRA;     // SRAI
                 default: s_id_invalid = 1;
             endcase
         end