From 63ed8ace809f15f939c319b3a1c7d6e3a8d25a4f Mon Sep 17 00:00:00 2001 From: Brendan Haines Date: Sun, 27 Sep 2020 16:04:16 -0600 Subject: [PATCH] initial commit. Non-working due to newly added MEM backpressure signal --- .gitignore | 1 + Makefile | 187 +++++++++++++++++++++ hdl/core.v | 392 ++++++++++++++++++++++++++++++++++++++++++++ hdl/tb/core_tb.v | 134 +++++++++++++++ hdl/top.v | 98 +++++++++++ pins.ucf | 61 +++++++ project.cfg | 26 +++ sim/core_tb.wcfg | 416 +++++++++++++++++++++++++++++++++++++++++++++++ 8 files changed, 1315 insertions(+) create mode 100644 .gitignore create mode 100644 Makefile create mode 100644 hdl/core.v create mode 100644 hdl/tb/core_tb.v create mode 100644 hdl/top.v create mode 100644 pins.ucf create mode 100644 project.cfg create mode 100644 sim/core_tb.wcfg diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..378eac2 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +build diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..fcbd11b --- /dev/null +++ b/Makefile @@ -0,0 +1,187 @@ +########################################################################### +## Xilinx ISE Makefile +## +## To the extent possible under law, the author(s) have dedicated all copyright +## and related and neighboring rights to this software to the public domain +## worldwide. This software is distributed without any warranty. +########################################################################### + +include project.cfg + + +########################################################################### +# Default values +########################################################################### + +ifndef XILINX + $(error XILINX must be defined) +endif + +ifndef PROJECT + $(error PROJECT must be defined) +endif + +ifndef TARGET_PART + $(error TARGET_PART must be defined) +endif + +TOPLEVEL ?= $(PROJECT) +CONSTRAINTS ?= $(PROJECT).ucf +BITFILE ?= build/$(PROJECT).bit + +COMMON_OPTS ?= -intstyle xflow +XST_OPTS ?= +NGDBUILD_OPTS ?= +MAP_OPTS ?= +PAR_OPTS ?= +BITGEN_OPTS ?= +TRACE_OPTS ?= +FUSE_OPTS ?= -incremental + +PROGRAMMER ?= none + +IMPACT_OPTS ?= -batch impact.cmd + +DJTG_EXE ?= djtgcfg +DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET +DJTG_INDEX ?= 0 + +XC3SPROG_EXE ?= xc3sprog +XC3SPROG_CABLE ?= none +XC3SPROG_OPTS ?= + + +########################################################################### +# Internal variables, platform-specific definitions, and macros +########################################################################### + +ifeq ($(OS),Windows_NT) + XILINX := $(shell cygpath -m $(XILINX)) + CYG_XILINX := $(shell cygpath $(XILINX)) + EXE := .exe + XILINX_PLATFORM ?= nt64 + PATH := $(PATH):$(CYG_XILINX)/bin/$(XILINX_PLATFORM) +else + EXE := + XILINX_PLATFORM ?= lin64 + PATH := $(PATH):$(XILINX)/bin/$(XILINX_PLATFORM) +endif + +TEST_NAMES = $(foreach file,$(VTEST) $(VHDTEST),$(basename $(file))) +TEST_EXES = $(foreach test,$(TEST_NAMES),build/isim_$(test)$(EXE)) + +RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \ + cd build && $(XILINX)/bin/$(XILINX_PLATFORM)/$(1) + +# isim executables don't work without this +export XILINX + + +########################################################################### +# Default build +########################################################################### + +default: $(BITFILE) + +clean: + rm -rf build + +build/$(PROJECT).prj: project.cfg + @echo "Updating $@" + @mkdir -p build + @rm -f $@ + @$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;) + @$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;) + +build/$(PROJECT)_sim.prj: build/$(PROJECT).prj + @cp build/$(PROJECT).prj $@ + @$(foreach file,$(VTEST),echo "verilog work \"../$(file)\"" >> $@;) + @$(foreach file,$(VHDTEST),echo "vhdl work \"../$(file)\"" >> $@;) + @echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@ + +build/$(PROJECT).scr: project.cfg + @echo "Updating $@" + @mkdir -p build + @rm -f $@ + @echo "run" \ + "-ifn $(PROJECT).prj" \ + "-ofn $(PROJECT).ngc" \ + "-ifmt mixed" \ + "$(XST_OPTS)" \ + "-top $(TOPLEVEL)" \ + "-ofmt NGC" \ + "-p $(TARGET_PART)" \ + > build/$(PROJECT).scr + +$(BITFILE): project.cfg $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr + @mkdir -p build + $(call RUN,xst) $(COMMON_OPTS) \ + -ifn $(PROJECT).scr + $(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \ + -p $(TARGET_PART) -uc ../$(CONSTRAINTS) \ + $(PROJECT).ngc $(PROJECT).ngd + $(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \ + -p $(TARGET_PART) \ + -w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf + $(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \ + -w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf + $(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \ + -w $(PROJECT).ncd $(PROJECT).bit + @echo -ne "\e[1;32m======== OK ========\e[m\n" + + +########################################################################### +# Testing (work in progress) +########################################################################### + +trace: project.cfg $(BITFILE) + $(call RUN,trce) $(COMMON_OPTS) $(TRACE_OPTS) \ + $(PROJECT).ncd $(PROJECT).pcf + +test: $(TEST_EXES) + +build/isim_%$(EXE): build/$(PROJECT)_sim.prj $(VSOURCE) $(VHDSOURCE) $(VTEST) $(VHDTEST) + $(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \ + -prj $(PROJECT)_sim.prj \ + -o isim_$*$(EXE) \ + work.$* work.glbl + +isim: build/isim_$(TB)$(EXE) + @grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd + @echo "run all" >> build/isim_$(TB).cmd + cd build ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd + +isimgui: build/isim_$(TB)$(EXE) + @grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd + @echo "run all" >> build/isim_$(TB).cmd + cd build ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd + + +########################################################################### +# Programming +########################################################################### + +ifeq ($(PROGRAMMER), impact) +prog: $(BITFILE) + $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS) +endif + +ifeq ($(PROGRAMMER), digilent) +prog: $(BITFILE) + $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE) +endif + +ifeq ($(PROGRAMMER), xc3sprog) +prog: $(BITFILE) + $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE) +endif + +ifeq ($(PROGRAMMER), none) +prog: + $(error PROGRAMMER must be set to use 'make prog') +endif + + +########################################################################### + +# vim: set filetype=make: # \ No newline at end of file diff --git a/hdl/core.v b/hdl/core.v new file mode 100644 index 0000000..1a66ea4 --- /dev/null +++ b/hdl/core.v @@ -0,0 +1,392 @@ +module core( + input clk, + input reset, + output dummy_out, + + output reg [31:0] mem_inst_addr, + input [31:0] mem_inst_data, + + output reg [31:0] mem_data_addr, + output reg [31:0] mem_data_wdata, + input [31:0] mem_data_rdata, + output reg mem_data_en, + output reg mem_data_we, + input mem_data_valid, + input mem_data_done +); + +// Register File +reg [31:0] regfile [0:31]; +initial regfile[0] = 32'h00000000; + +// Registers +reg [31:0] r_if_pc = 0, r_id_pc, r_ex_pc, r_mem_pc, r_wb_pc; +reg r_id_stall, r_ex_stall, r_mem_stall, r_wb_stall; +reg [31:0] r_id_inst, r_ex_inst, r_mem_inst, r_wb_inst; +reg [4:0] r_ex_rd, r_mem_rd, r_wb_rd; +reg r_ex_alu_seed; +reg [2:0] r_ex_aluop; +reg [31:0] r_ex_s1, r_ex_s2, r_mem_s1, r_mem_s2; +reg [31:0] r_mem_alu_out, r_wb_alu_out; +reg r_mem_alu_zero; +reg r_ex_jump; + +// IF +reg s_if_halt; +reg [31:0] s_if_next_pc; +reg [31:0] s_if_inst; +reg s_if_stall; + +always @(*) begin + s_if_halt = 0; + + if (r_ex_jump) begin + s_if_next_pc = s_ex_alu_out; + s_if_stall = 1'b1; + end else begin + s_if_next_pc = r_if_pc + 4; + s_if_stall = 1'b0; + end + + mem_inst_addr = r_if_pc; + s_if_inst = mem_inst_data; +end + +// ID +reg s_id_halt; +reg [6:0] s_id_opcode; +reg [2:0] s_id_funct3; +reg [6:0] s_id_funct7; +reg [4:0] s_id_rd, s_id_rs1, s_id_rs2; +reg [31:0] s_id_immed_itype, s_id_immed_stype, s_id_immed_utype, s_id_immed_btype, s_id_immed_jtype; +reg [31:0] s_id_s1, s_id_s2; +reg [2:0] s_id_aluop; +reg s_id_alu_seed; +reg s_id_invalid; +reg s_id_jump, s_id_branch; + +// RV32I / RV64I / RV32M +localparam OP_LUI = 7'b0110111, + OP_AUIPC = 7'b0010111, + OP_JAL = 7'b1101111, + OP_JALR = 7'b1100111, + OP_BRANCH = 7'b1100011, + OP_LOAD = 7'b0000011, + OP_STORE = 7'b0100011, + OP_IMM = 7'b0010011, + OP_ALU = 7'b0110011, + OP_FENCE = 7'b0001111, + OP_SYSTEM = 7'b1110011; +// RV64M +// localparam OP_???????? = 7'b0111011; +// RV32A / RV64A +// localparam OP_ATOMIC = 7'b0101111; +// TODO: add opcodes for other extensions + +// ALU OPCODES +localparam ALUOP_ADD = 0, + ALUOP_XOR = 1, + ALUOP_OR = 2, + ALUOP_AND = 3, + ALUOP_SL = 4, + ALUOP_SR = 5, + ALUOP_SLT = 6, + ALUOP_SLTU = 7; + + +always @(*) begin + s_id_halt = 0; + s_id_invalid = 0; + + s_id_opcode = r_id_inst[6:0]; + s_id_rd = r_id_inst[11:7]; + s_id_rs1 = r_id_inst[19:15]; + s_id_rs2 = r_id_inst[24:20]; + s_id_funct3 = r_id_inst[14:12]; + s_id_funct7 = r_id_inst[31:25]; + + s_id_immed_itype = {{20{r_id_inst[31]}}, r_id_inst[31:20]}; + s_id_immed_stype = {{20{r_id_inst[31]}}, r_id_inst[31:25], r_id_inst[11:7]}; + s_id_immed_utype = {r_id_inst[31:12], 12'b0}; + s_id_immed_btype = {{19{r_id_inst[31]}}, r_id_inst[31], r_id_inst[7], r_id_inst[30:25], r_id_inst[11:8], 1'b0}; + s_id_immed_jtype = {{11{r_id_inst[31]}}, r_id_inst[31], r_id_inst[19:12], r_id_inst[20], r_id_inst[30:21], 1'b0}; + + case (s_id_opcode) + OP_LUI: begin + s_id_s1 = 32'h00000000; + s_id_s2 = s_id_immed_utype; + s_id_aluop = ALUOP_ADD; + s_id_alu_seed = 0; + s_id_jump = 0; + s_id_branch = 0; + end + OP_AUIPC: begin + s_id_s1 = r_id_pc; + s_id_s2 = s_id_immed_utype; + s_id_aluop = ALUOP_ADD; + s_id_alu_seed = 0; + s_id_jump = 0; + s_id_branch = 0; + end + OP_JAL: begin + s_id_s1 = r_id_pc; + s_id_s2 = s_id_immed_jtype; + s_id_aluop = ALUOP_ADD; + s_id_alu_seed = 0; + s_id_jump = 1; + s_id_branch = 0; + end + OP_JALR: begin + s_id_s1 = regfile[s_id_rs1]; + s_id_s2 = s_id_immed_itype; + s_id_aluop = ALUOP_ADD; + s_id_alu_seed = 0; + s_id_jump = 1; + s_id_branch = 0; + end + // OP_BRANCH: begin + + // end + // OP_LOAD: begin + + // end + // OP_STORE: begin + + // end + OP_IMM: begin + s_id_s1 = regfile[s_id_rs1]; + s_id_s2 = s_id_immed_itype; + s_id_jump = 0; + s_id_branch = 0; + casex ({s_id_funct3, s_id_funct7}) + 10'b000xxxxxxx: begin s_id_aluop = ALUOP_ADD; s_id_alu_seed = 1'b0; end // ADDI + 10'b010xxxxxxx: begin s_id_aluop = ALUOP_SLT; s_id_alu_seed = 1'bx; end // SLTI + 10'b011xxxxxxx: begin s_id_aluop = ALUOP_SLTU; s_id_alu_seed = 1'bx; end // SLTUI + 10'b100xxxxxxx: begin s_id_aluop = ALUOP_XOR; s_id_alu_seed = 1'bx; end // XORI + 10'b110xxxxxxx: begin s_id_aluop = ALUOP_OR; s_id_alu_seed = 1'bx; end // ORI + 10'b111xxxxxxx: begin s_id_aluop = ALUOP_AND; s_id_alu_seed = 1'bx; end // ANDI + 10'b0010000000: begin s_id_aluop = ALUOP_SL; s_id_alu_seed = 1'bx; end // SLLI + 10'b1010000000: begin s_id_aluop = ALUOP_SR; s_id_alu_seed = 1'b0; end // SRLI + 10'b1010100000: begin s_id_aluop = ALUOP_SR; s_id_alu_seed = 1'b1; end // SRAI + default: begin + s_id_s1 = 32'hxxxxxxxx; + s_id_s2 = 32'hxxxxxxxx; + s_id_invalid = 1; + end + endcase + end + OP_ALU: begin + s_id_s1 = regfile[s_id_rs1]; + s_id_s2 = regfile[s_id_rs2]; + s_id_jump = 0; + s_id_branch = 0; + case ({s_id_funct3, s_id_funct7}) + 10'b0000000000: begin s_id_aluop = ALUOP_ADD; s_id_alu_seed = 1'b0; end // ADD + 10'b0000100000: begin s_id_aluop = ALUOP_ADD; s_id_alu_seed = 1'b1; end // SUB + 10'b0010000000: begin s_id_aluop = ALUOP_SL; s_id_alu_seed = 1'bx; end // SLL + 10'b0100000000: begin s_id_aluop = ALUOP_SLT; s_id_alu_seed = 1'bx; end // SLT + 10'b0110000000: begin s_id_aluop = ALUOP_SLTU; s_id_alu_seed = 1'bx; end // SLTU + 10'b1000000000: begin s_id_aluop = ALUOP_XOR; s_id_alu_seed = 1'bx; end // XOR + 10'b1100000000: begin s_id_aluop = ALUOP_OR; s_id_alu_seed = 1'bx; end // OR + 10'b1110000000: begin s_id_aluop = ALUOP_AND; s_id_alu_seed = 1'bx; end // AND + 10'b1010000000: begin s_id_aluop = ALUOP_SR; s_id_alu_seed = 1'b0; end // SRL + 10'b1010100000: begin s_id_aluop = ALUOP_SR; s_id_alu_seed = 1'b1; end // SRA + default: begin + s_id_s1 = 32'hxxxxxxxx; + s_id_s2 = 32'hxxxxxxxx; + s_id_invalid = 1; + end + endcase + end + // OP_FENCE: begin + + // end + // OP_SYSTEM: begin + + // end + default: begin + s_id_jump = 0; + s_id_branch = 0; + s_id_s1 = 32'hxxxxxxxx; + s_id_s2 = 32'hxxxxxxxx; + s_id_invalid = 1; + end + endcase + + if (s_id_invalid) begin + $display("Invalid instruction at PC=0x%h", r_id_pc); + s_id_halt = 1'b1; + s_id_aluop = 3'hx; + s_id_alu_seed = 1'bx; + end +end + +// EX +reg s_ex_halt; +reg [31:0] s_ex_data1, s_ex_data2; +reg [31:0] s_ex_alu_out; +reg s_ex_alu_zero; +reg [31:0] s_ex_ra; + +always @(*) begin + s_ex_halt = 0; + + s_ex_data1 = r_ex_s1; + s_ex_data2 = r_ex_s2; + + case (r_ex_aluop) + ALUOP_ADD: begin // seed=1: subtract + s_ex_alu_out = s_ex_data1 + (s_ex_data2 ^ {32{r_ex_alu_seed}}) + r_ex_alu_seed; + end + ALUOP_XOR: begin + s_ex_alu_out = (|s_ex_data1) ^ (|s_ex_data2); + end + ALUOP_OR: begin + s_ex_alu_out = (|s_ex_data1) | (|s_ex_data2); + end + ALUOP_AND: begin + s_ex_alu_out = (|s_ex_data1) & (|s_ex_data2); + end + ALUOP_SL: begin + s_ex_alu_out = s_ex_data1 << s_ex_data2; + end + ALUOP_SR: begin // seed=1: arithmetic + s_ex_alu_out = s_ex_data1 >> s_ex_data2; + if (r_ex_alu_seed) begin + s_ex_alu_out = s_ex_data1 >>> s_ex_data2; + end + end + ALUOP_SLT: begin + s_ex_alu_out = $signed(s_ex_data1) < $signed(s_ex_data2); + end + ALUOP_SLTU: begin + s_ex_alu_out = s_ex_data1 < s_ex_data2; + end + default: begin + s_ex_halt = 1; + s_ex_alu_out = 32'hxxxxxxxx; + end + endcase + s_ex_alu_zero = (s_ex_alu_out == 0); + + s_ex_ra = r_ex_pc + 4; +end + +// MEM +reg s_mem_halt; +reg s_mem_bp; + +always @(*) begin + s_mem_halt = 0; + s_mem_bp = 0; + + if (r_mem_store) begin + mem_data_en = 1; + mem_data_we = 1; + s_mem_bp = !mem_data_done; + end else if (r_mem_load) begin + mem_data_en = 1; + mem_data_we = 0; + s_mem_bp = !mem_data_valid; + end else begin + mem_data_en = 0; + mem_data_we = 0; + s_mem_bp = 0; + end +end + +// WB +reg s_wb_halt; +reg [31:0] s_wb_data; +reg s_wb_write; + +always @(*) begin + s_wb_halt = 0; + + // load instructions do not use output of alu in wb + s_wb_data = r_wb_alu_out; + + // FIXME: always writes!!! + s_wb_write = !r_wb_stall; +end + +// SYS +reg s_sys_halt; + +always @(*) begin + s_sys_halt = s_if_halt || s_id_halt || s_ex_halt || s_mem_halt || s_wb_halt; +end + +// Register update +always @(posedge clk) begin + if (reset) begin + r_if_pc <= 32'h00000000; + // rather than resetting all flip-flops just stall the pipeline so values are ignored. + r_id_stall <= 1; + r_ex_stall <= 1; + r_mem_stall <= 1; + r_wb_stall <= 1; + + end else begin + // NOTE: halt disabled because startup causes hault + // if (s_sys_halt && 0) begin + // // stay halted forever + // end else begin + // IF + if (!s_mem_bp) begin + r_if_pc <= s_if_next_pc; + end + + // ID + if (!s_mem_bp) begin + r_id_stall <= s_if_stall; + r_id_pc <= r_if_pc; + r_id_inst <= s_if_inst; + end + + // EX + if (!s_mem_bp) begin + // TODO: also stall EX if taking branch + r_ex_stall <= r_id_stall; + r_ex_pc <= r_id_pc; + r_ex_inst <= r_id_inst; + r_ex_rd <= s_id_rd; + r_ex_s1 <= s_id_s1; + r_ex_s2 <= s_id_s2; + r_ex_aluop <= s_id_aluop; + r_ex_alu_seed <= s_id_alu_seed; + r_ex_jump <= s_id_jump; + end + + + // MEM + if (!s_mem_bp) begin + r_mem_stall <= r_ex_stall; + r_mem_pc <= r_ex_pc; + r_mem_inst <= r_ex_inst; + r_mem_rd <= r_ex_rd; + r_mem_s1 <= r_ex_s1; + r_mem_s2 <= r_ex_s2; + r_mem_alu_out <= s_ex_alu_out; + r_mem_alu_zero <= s_ex_alu_zero; + end + + // WB + if (!s_mem_bp) begin + r_wb_stall <= r_mem_stall; + r_wb_pc <= r_mem_pc; + r_wb_rd <= r_mem_rd; + r_wb_alu_out <= r_mem_alu_out; + end + + // Register File + if (r_wb_rd != 0 && s_wb_write) begin + regfile[r_wb_rd] <= s_wb_data; + end + // end + end +end + +assign dummy_out = s_wb_data[0]; + +endmodule \ No newline at end of file diff --git a/hdl/tb/core_tb.v b/hdl/tb/core_tb.v new file mode 100644 index 0000000..9960b74 --- /dev/null +++ b/hdl/tb/core_tb.v @@ -0,0 +1,134 @@ +`timescale 1 ns / 1 ps + +module core_tb(); + +localparam MEM_INST_LENGTH = 256; +localparam MEM_DATA_LENGTH = 256; + +reg clk, reset; +wire [31:0] mem_inst_addr; +wire [31:0] mem_inst_idx = mem_inst_addr >> 2; +reg [31:0] mem_inst_data; +reg [31:0] mem_inst [0:MEM_INST_LENGTH-1]; +reg [31:0] mem_data [0:MEM_DATA_LENGTH-1]; +wire [31:0] mem_data_addr; +wire [31:0] mem_data_wdata; +reg [31:0] mem_data_rdata; +wire mem_data_en; +wire mem_data_we; +reg mem_data_valid; +reg mem_data_done; +integer i; + +localparam OP_LUI = 7'b0110111, + OP_AUIPC = 7'b0010111, + OP_JAL = 7'b1101111, + OP_JALR = 7'b1100111, + OP_BRANCH = 7'b1100011, + OP_LOAD = 7'b0000011, + OP_STORE = 7'b0100011, + OP_IMM = 7'b0010011, + OP_ALU = 7'b0110011, + OP_FENCE = 7'b0001111, + OP_SYSTEM = 7'b1110011; + +localparam INST_NOP = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd0, OP_ALU}; // nop + +initial begin + for (i=0; i> 2; +reg [31:0] mem_inst_data; +reg [31:0] mem_inst [0:MEM_INST_LENGTH-1]; +integer i; + +localparam OP_LUI = 7'b0110111, + OP_AUIPC = 7'b0010111, + OP_JAL = 7'b1101111, + OP_JALR = 7'b1100111, + OP_BRANCH = 7'b1100011, + OP_LOAD = 7'b0000011, + OP_STORE = 7'b0100011, + OP_IMM = 7'b0010011, + OP_ALU = 7'b0110011, + OP_FENCE = 7'b0001111, + OP_SYSTEM = 7'b1110011; + +localparam MEM_INST_LENGTH = 256; +localparam MEM_DATA_LENGTH = 256; +localparam INST_NOP = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd0, OP_ALU}; // nop + + +initial begin + for (i=0; i + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + regfile[0:31,31:0] + regfile[0:31,31:0] + HEXRADIX + + [0,31:0] + regfile[0,31:0] + HEXRADIX + + + [1,31:0] + regfile[1,31:0] + HEXRADIX + + + [2,31:0] + regfile[2,31:0] + HEXRADIX + + + [3,31:0] + regfile[3,31:0] + HEXRADIX + + + [4,31:0] + regfile[4,31:0] + HEXRADIX + + + [5,31:0] + regfile[5,31:0] + HEXRADIX + + + [6,31:0] + regfile[6,31:0] + HEXRADIX + + + [7,31:0] + regfile[7,31:0] + HEXRADIX + + + [8,31:0] + regfile[8,31:0] + HEXRADIX + + + [9,31:0] + regfile[9,31:0] + HEXRADIX + + + [10,31:0] + regfile[10,31:0] + HEXRADIX + + + [11,31:0] + regfile[11,31:0] + HEXRADIX + + + [12,31:0] + regfile[12,31:0] + HEXRADIX + + + [13,31:0] + regfile[13,31:0] + HEXRADIX + + + [14,31:0] + regfile[14,31:0] + HEXRADIX + + + [15,31:0] + regfile[15,31:0] + HEXRADIX + + + [16,31:0] + regfile[16,31:0] + HEXRADIX + + + [17,31:0] + regfile[17,31:0] + HEXRADIX + + + [18,31:0] + regfile[18,31:0] + HEXRADIX + + + [19,31:0] + regfile[19,31:0] + HEXRADIX + + + [20,31:0] + regfile[20,31:0] + HEXRADIX + + + [21,31:0] + regfile[21,31:0] + HEXRADIX + + + [22,31:0] + regfile[22,31:0] + HEXRADIX + + + [23,31:0] + regfile[23,31:0] + HEXRADIX + + + [24,31:0] + regfile[24,31:0] + HEXRADIX + + + [25,31:0] + regfile[25,31:0] + HEXRADIX + + + [26,31:0] + regfile[26,31:0] + HEXRADIX + + + [27,31:0] + regfile[27,31:0] + HEXRADIX + + + [28,31:0] + regfile[28,31:0] + HEXRADIX + + + [29,31:0] + regfile[29,31:0] + HEXRADIX + + + [30,31:0] + regfile[30,31:0] + HEXRADIX + + + [31,31:0] + regfile[31,31:0] + HEXRADIX + + + + IF + label + + r_if_pc[31:0] + r_if_pc[31:0] + HEXRADIX + + + s_if_next_pc[31:0] + s_if_next_pc[31:0] + HEXRADIX + + + s_if_inst[31:0] + s_if_inst[31:0] + HEXRADIX + + + s_if_halt + s_if_halt + + + + ID + label + + r_id_stall + r_id_stall + + + r_id_pc[31:0] + r_id_pc[31:0] + HEXRADIX + + + r_id_inst[31:0] + r_id_inst[31:0] + HEXRADIX + + + s_id_opcode[6:0] + s_id_opcode[6:0] + + + s_id_funct3[2:0] + s_id_funct3[2:0] + + + s_id_funct7[6:0] + s_id_funct7[6:0] + + + s_id_rd[4:0] + s_id_rd[4:0] + UNSIGNEDDECRADIX + + + s_id_rs1[4:0] + s_id_rs1[4:0] + UNSIGNEDDECRADIX + + + s_id_rs2[4:0] + s_id_rs2[4:0] + UNSIGNEDDECRADIX + + + s_id_aluop[2:0] + s_id_aluop[2:0] + + + s_id_alu_seed + s_id_alu_seed + + + s_id_jump + s_id_jump + + + s_id_invalid + s_id_invalid + + + s_id_halt + s_id_halt + + + + EX + label + + r_ex_stall + r_ex_stall + + + r_ex_pc[31:0] + r_ex_pc[31:0] + HEXRADIX + + + r_ex_inst[31:0] + r_ex_inst[31:0] + HEXRADIX + + + r_ex_rd[4:0] + r_ex_rd[4:0] + UNSIGNEDDECRADIX + + + r_ex_s1[31:0] + r_ex_s1[31:0] + HEXRADIX + + + r_ex_s2[31:0] + r_ex_s2[31:0] + HEXRADIX + + + r_ex_aluop[2:0] + r_ex_aluop[2:0] + + + r_ex_alu_seed + r_ex_alu_seed + + + s_ex_data1[31:0] + s_ex_data1[31:0] + HEXRADIX + + + s_ex_data2[31:0] + s_ex_data2[31:0] + HEXRADIX + + + s_ex_alu_out[31:0] + s_ex_alu_out[31:0] + HEXRADIX + + + s_ex_alu_zero + s_ex_alu_zero + + + r_ex_jump + r_ex_jump + + + s_ex_halt + s_ex_halt + + + + MEM + label + + r_mem_stall + r_mem_stall + + + r_mem_pc[31:0] + r_mem_pc[31:0] + HEXRADIX + + + r_mem_inst[31:0] + r_mem_inst[31:0] + HEXRADIX + + + r_mem_rd[4:0] + r_mem_rd[4:0] + UNSIGNEDDECRADIX + + + r_mem_alu_out[31:0] + r_mem_alu_out[31:0] + HEXRADIX + + + r_mem_alu_zero + r_mem_alu_zero + + + s_mem_halt + s_mem_halt + + + + WB + label + + r_wb_stall + r_wb_stall + + + r_wb_pc[31:0] + r_wb_pc[31:0] + HEXRADIX + + + r_wb_inst[31:0] + r_wb_inst[31:0] + HEXRADIX + + + r_wb_alu_out[31:0] + r_wb_alu_out[31:0] + HEXRADIX + + + r_wb_rd[4:0] + r_wb_rd[4:0] + UNSIGNEDDECRADIX + + + s_wb_data[31:0] + s_wb_data[31:0] + HEXRADIX + + + s_wb_halt + s_wb_halt + + +