From 24171412bda45f3c7ad1a5ebb3c30ffeb10aa801 Mon Sep 17 00:00:00 2001
From: Brendan Haines <brendan.haines@gmail.com>
Date: Sun, 27 Sep 2020 18:38:35 -0600
Subject: [PATCH] successfully using assembler to generate .hex rather than
 writing straight machine code

---
 hdl/tb/core_tb.v |   99 ++--
 sim/core_tb.wcfg | 1297 +++++++++++++++++++++++++++++++++++++++++++++-
 test/Makefile    |    5 +-
 test/test.S      |   28 +
 4 files changed, 1380 insertions(+), 49 deletions(-)

diff --git a/hdl/tb/core_tb.v b/hdl/tb/core_tb.v
index da2bfed..a31f1f1 100644
--- a/hdl/tb/core_tb.v
+++ b/hdl/tb/core_tb.v
@@ -39,55 +39,60 @@ initial begin
         mem_inst[i] = INST_NOP;
     end
 
-    // Initialize all registers
-    mem_inst[0]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd1,  OP_ALU};  // add x1, x0, x0
-    mem_inst[1]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd2,  OP_ALU};  // add x2, x0, x0
-    mem_inst[2]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd3,  OP_ALU};  // add x3, x0, x0
-    mem_inst[3]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd4,  OP_ALU};  // add x4, x0, x0
-    mem_inst[4]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd5,  OP_ALU};  // add x5, x0, x0
-    mem_inst[5]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd6,  OP_ALU};  // add x6, x0, x0
-    mem_inst[6]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd7,  OP_ALU};  // add x7, x0, x0
-    mem_inst[7]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd8,  OP_ALU};  // add x8, x0, x0
-    mem_inst[8]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd9,  OP_ALU};  // add x9, x0, x0
-    mem_inst[9]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd10, OP_ALU};  // add x10, x0, x0
-    mem_inst[10]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd11, OP_ALU};  // add x11, x0, x0
-    mem_inst[11]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd12, OP_ALU};  // add x12, x0, x0
-    mem_inst[12]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd13, OP_ALU};  // add x13, x0, x0
-    mem_inst[13]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd14, OP_ALU};  // add x14, x0, x0
-    mem_inst[14]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd15, OP_ALU};  // add x15, x0, x0
-    mem_inst[15]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd16, OP_ALU};  // add x16, x0, x0
-    mem_inst[16]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd17, OP_ALU};  // add x17, x0, x0
-    mem_inst[17]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd18, OP_ALU};  // add x18, x0, x0
-    mem_inst[18]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd19, OP_ALU};  // add x19, x0, x0
-    mem_inst[19]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd20, OP_ALU};  // add x20, x0, x0
-    mem_inst[20]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd21, OP_ALU};  // add x21, x0, x0
-    mem_inst[21]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd22, OP_ALU};  // add x22, x0, x0
-    mem_inst[22]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd23, OP_ALU};  // add x23, x0, x0
-    mem_inst[23]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd24, OP_ALU};  // add x24, x0, x0
-    mem_inst[24]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd25, OP_ALU};  // add x25, x0, x0
-    mem_inst[25]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd26, OP_ALU};  // add x26, x0, x0
-    mem_inst[26]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd27, OP_ALU};  // add x27, x0, x0
-    mem_inst[27]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd28, OP_ALU};  // add x28, x0, x0
-    mem_inst[28]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd29, OP_ALU};  // add x29, x0, x0
-    mem_inst[29]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd30, OP_ALU};  // add x30, x0, x0
-    mem_inst[30]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd31, OP_ALU};  // add x31, x0, x0
+    $readmemh("../test/test.hex", mem_inst);
 
-    mem_inst[36]    = {12'd1,            5'd0, 3'b000, 5'd2, OP_IMM};   // addi x2, x0, 1
-    mem_inst[42]    = {7'b0000000, 5'd2, 5'd1, 3'b000, 5'd3, OP_ALU};   // add x3, x1, x2
-    mem_inst[48]    = {7'b0000000, 5'd2, 5'd3, 3'b000, 5'd3, OP_ALU};   // add x3, x3, x2
-    mem_inst[54]    = {7'b0000000, 5'd3, 5'd3, 3'b000, 5'd3, OP_ALU};   // add x3, x3, x3
-    mem_inst[60]    = {12'h123,          5'd0, 3'b000, 5'd4, OP_IMM};   // addi x4, x0, 0x123
-    mem_inst[66]    = {12'h000,          5'd4, 3'b000, 5'd5, OP_IMM};   // addi x5, x4, 0
-    mem_inst[72]    = {12'hfff,          5'd5, 3'b000, 5'd5, OP_IMM};   // addi x5, x5, -1
-    mem_inst[78]    = {20'hedcba,                      5'd7, OP_LUI};   // lui x7, 0xedcba
-    mem_inst[84]    = {12'h987,          5'd7, 3'b000, 5'd7, OP_IMM};   // addi x7, x7, 0x987
-    mem_inst[90]    = {20'h00032,                      5'd8, OP_AUIPC}; // auipc x8, 0x32           // 90*4 + 0x32000 = 0x32168
-    // mem_inst[96]    = {12'd288,          5'd0, 3'b000, 5'd9, OP_JALR};  // jalr x9, x0, 72*4        // unconditional jump to index 72 = 288/4
-    mem_inst[102]   = {1'b0, 10'd12, 1'b0, 8'b0, 5'd9,       OP_JAL};   // jal x10, +12             // unconditional jump to index +12 = 24*2/4
-    mem_inst[108]   = {12'd4,            5'd0, 3'b000, 5'd2, OP_IMM};   // addi x11, x0, 4          // this should be skipped
-    mem_inst[114]   = {12'd5,            5'd0, 3'b000, 5'd2, OP_IMM};   // addi x12, x0, 5
-    mem_inst[120]   = {12'd5,            5'd0, 3'b000, 5'd2, OP_IMM};   // addi x12, x12, 6
+//     // Initialize all registers
+//     mem_inst[0]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd1,  OP_ALU};  // add x1, x0, x0
+//     mem_inst[1]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd2,  OP_ALU};  // add x2, x0, x0
+//     mem_inst[2]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd3,  OP_ALU};  // add x3, x0, x0
+//     mem_inst[3]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd4,  OP_ALU};  // add x4, x0, x0
+//     mem_inst[4]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd5,  OP_ALU};  // add x5, x0, x0
+//     mem_inst[5]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd6,  OP_ALU};  // add x6, x0, x0
+//     mem_inst[6]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd7,  OP_ALU};  // add x7, x0, x0
+//     mem_inst[7]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd8,  OP_ALU};  // add x8, x0, x0
+//     mem_inst[8]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd9,  OP_ALU};  // add x9, x0, x0
+//     mem_inst[9]     = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd10, OP_ALU};  // add x10, x0, x0
+//     mem_inst[10]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd11, OP_ALU};  // add x11, x0, x0
+//     mem_inst[11]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd12, OP_ALU};  // add x12, x0, x0
+//     mem_inst[12]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd13, OP_ALU};  // add x13, x0, x0
+//     mem_inst[13]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd14, OP_ALU};  // add x14, x0, x0
+//     mem_inst[14]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd15, OP_ALU};  // add x15, x0, x0
+//     mem_inst[15]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd16, OP_ALU};  // add x16, x0, x0
+//     mem_inst[16]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd17, OP_ALU};  // add x17, x0, x0
+//     mem_inst[17]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd18, OP_ALU};  // add x18, x0, x0
+//     mem_inst[18]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd19, OP_ALU};  // add x19, x0, x0
+//     mem_inst[19]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd20, OP_ALU};  // add x20, x0, x0
+//     mem_inst[20]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd21, OP_ALU};  // add x21, x0, x0
+//     mem_inst[21]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd22, OP_ALU};  // add x22, x0, x0
+//     mem_inst[22]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd23, OP_ALU};  // add x23, x0, x0
+//     mem_inst[23]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd24, OP_ALU};  // add x24, x0, x0
+//     mem_inst[24]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd25, OP_ALU};  // add x25, x0, x0
+//     mem_inst[25]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd26, OP_ALU};  // add x26, x0, x0
+//     mem_inst[26]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd27, OP_ALU};  // add x27, x0, x0
+//     mem_inst[27]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd28, OP_ALU};  // add x28, x0, x0
+//     mem_inst[28]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd29, OP_ALU};  // add x29, x0, x0
+//     mem_inst[29]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd30, OP_ALU};  // add x30, x0, x0
+//     mem_inst[30]    = {7'b0000000, 5'd0, 5'd0, 3'b000, 5'd31, OP_ALU};  // add x31, x0, x0
 
+//     mem_inst[36]    = {12'd1,            5'd0, 3'b000, 5'd2, OP_IMM};   // addi x2, x0, 1
+//     mem_inst[42]    = {7'b0000000, 5'd2, 5'd1, 3'b000, 5'd3, OP_ALU};   // add x3, x1, x2
+//     mem_inst[48]    = {7'b0000000, 5'd2, 5'd3, 3'b000, 5'd3, OP_ALU};   // add x3, x3, x2
+//     mem_inst[54]    = {7'b0000000, 5'd3, 5'd3, 3'b000, 5'd3, OP_ALU};   // add x3, x3, x3
+//     mem_inst[60]    = {12'h123,          5'd0, 3'b000, 5'd4, OP_IMM};   // addi x4, x0, 0x123
+//     mem_inst[66]    = {12'h000,          5'd4, 3'b000, 5'd5, OP_IMM};   // addi x5, x4, 0
+//     mem_inst[72]    = {12'hfff,          5'd5, 3'b000, 5'd5, OP_IMM};   // addi x5, x5, -1
+//     mem_inst[78]    = {20'hedcba,                      5'd7, OP_LUI};   // lui x7, 0xedcba
+//     mem_inst[84]    = {12'h987,          5'd7, 3'b000, 5'd7, OP_IMM};   // addi x7, x7, 0x987
+//     mem_inst[90]    = {20'h00032,                      5'd8, OP_AUIPC}; // auipc x8, 0x32           // 90*4 + 0x32000 = 0x32168
+//     // mem_inst[96]    = {12'd288,          5'd0, 3'b000, 5'd9, OP_JALR};  // jalr x9, x0, 72*4        // unconditional jump to index 72 = 288/4
+//     mem_inst[102]   = {1'b0, 10'd12, 1'b0, 8'b0, 5'd9,       OP_JAL};   // jal x10, +12             // unconditional jump to index +12 = 24*2/4
+//     mem_inst[108]   = {12'd4,            5'd0, 3'b000, 5'd2, OP_IMM};   // addi x11, x0, 4          // this should be skipped
+//     mem_inst[114]   = {12'd5,            5'd0, 3'b000, 5'd2, OP_IMM};   // addi x12, x0, 5
+//     mem_inst[120]   = {12'd5,            5'd0, 3'b000, 5'd2, OP_IMM};   // addi x12, x12, 6
+
+end
+
+initial begin
 end
 
 always @(*) begin
diff --git a/sim/core_tb.wcfg b/sim/core_tb.wcfg
index 8c7a5b5..fb35126 100644
--- a/sim/core_tb.wcfg
+++ b/sim/core_tb.wcfg
@@ -10,7 +10,7 @@
          </top_modules>
       </db_ref>
    </db_ref_list>
-   <WVObjectSize size="8" />
+   <WVObjectSize size="9" />
    <wvobject fp_name="/core_tb/clk" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">clk</obj_property>
       <obj_property name="ObjectShortName">clk</obj_property>
@@ -19,6 +19,1291 @@
       <obj_property name="ElementShortName">reset</obj_property>
       <obj_property name="ObjectShortName">reset</obj_property>
    </wvobject>
+   <wvobject fp_name="/core_tb/mem_inst" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">mem_inst[0:255,31:0]</obj_property>
+      <obj_property name="ObjectShortName">mem_inst[0:255,31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/core_tb/mem_inst[0]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[0,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[0,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[1]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[1,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[1,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[2]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[2,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[2,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[3]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[3,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[3,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[4]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[4,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[4,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[5]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[5,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[5,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[6]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[6,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[6,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[7]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[7,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[7,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[8]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[8,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[8,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[9]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[9,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[9,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[10]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[10,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[10,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[11]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[11,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[11,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[12]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[12,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[12,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[13]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[13,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[13,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[14]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[14,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[14,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[15]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[15,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[15,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[16]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[16,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[16,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[17]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[17,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[17,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[18]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[18,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[18,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[19]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[19,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[19,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[20]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[20,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[20,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[21]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[21,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[21,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[22]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[22,31:0]</obj_property>
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+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[226]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[226,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[226,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[227]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[227,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[227,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[228]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[228,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[228,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[229]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[229,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[229,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[230]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[230,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[230,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[231]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[231,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[231,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[232]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[232,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[232,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[233]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[233,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[233,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[234]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[234,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[234,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[235]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[235,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[235,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[236]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[236,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[236,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[237]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[237,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[237,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[238]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[238,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[238,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[239]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[239,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[239,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[240]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[240,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[240,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[241]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[241,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[241,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[242]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[242,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[242,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[243]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[243,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[243,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[244]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[244,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[244,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[245]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[245,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[245,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[246]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[246,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[246,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[247]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[247,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[247,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[248]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[248,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[248,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[249]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[249,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[249,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[250]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[250,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[250,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[251]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[251,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[251,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[252]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[252,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[252,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[253]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[253,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[253,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[254]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[254,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[254,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/mem_inst[255]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[255,31:0]</obj_property>
+         <obj_property name="ObjectShortName">mem_inst[255,31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
    <wvobject fp_name="/core_tb/dut/regfile" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">regfile[0:31,31:0]</obj_property>
       <obj_property name="ObjectShortName">regfile[0:31,31:0]</obj_property>
@@ -251,6 +1536,16 @@
          <obj_property name="ObjectShortName">s_id_rs2[4:0]</obj_property>
          <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
       </wvobject>
+      <wvobject fp_name="/core_tb/dut/s_id_s1" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">s_id_s1[31:0]</obj_property>
+         <obj_property name="ObjectShortName">s_id_s1[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/core_tb/dut/s_id_s2" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">s_id_s2[31:0]</obj_property>
+         <obj_property name="ObjectShortName">s_id_s2[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
       <wvobject fp_name="/core_tb/dut/s_id_aluop" type="array" db_ref_id="1">
          <obj_property name="ElementShortName">s_id_aluop[2:0]</obj_property>
          <obj_property name="ObjectShortName">s_id_aluop[2:0]</obj_property>
diff --git a/test/Makefile b/test/Makefile
index 1681182..82d3320 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -13,8 +13,11 @@ LDFLAGS = -T test.ld
 %.o: %.S
 	$(AS) $(ASFLAGS) $^ -o $@
 
+%.o: %.c
+	$(CC) $(CFLAGS) $^ -o $@
+
 %.elf: %.o
 	$(LD) $(LDFLAGS) $^ -o $@
 
 test.hex: test.elf
-	riscv64-linux-gnu-objdump -s $^ | sed -n '/0000/,$$p' | cut -f3-6 -d ' ' | sed -e 's/ /\n/g' > $@
+	riscv64-linux-gnu-objdump -s $^ | sed -n '/0000/,$$p' | cut -f3-6 -d ' ' | sed -e 's/ /\n/g' | sed 's/^\(..\)\(..\)\(..\)\(..\)/\4\3\2\1/' > $@
diff --git a/test/test.S b/test/test.S
index d4f69c7..a540baf 100644
--- a/test/test.S
+++ b/test/test.S
@@ -33,4 +33,32 @@ add     x29, x0, x0
 add     x30, x0, x0
 add     x31, x0, x0
 
+# nop required because cpu currently does not detect when something is needed from a later stage of the pipeline.
+# 5 clocks allows one instruction to finish before the next starts
+nop
+nop
+nop
+nop
+nop
+addi    x1, x0, 0x12
+nop
+nop
+nop
+nop
+nop
+addi    x2, x0, 0x11
+nop
+nop
+nop
+nop
+nop
+add     x3, x2, x1
+loop:
+nop
+nop
+nop
+nop
+nop
+j       loop
+
 .data